- Add preprocessor guard to watchdog api that errors if the reset reason api is not also implemented
- Add RESET_REASON and WATCHDOG to K64F targets.json
- Add watchdog reference implementation
- Adjust memory for SoftDevice
- Enable PRIO=5 for interrupt priority check
- Change NRF_SD_BLE_API_VERSION to 6
- Add handle and buffer for advertising and scanning
- Remove guard for phy update
- Change scatter files and mbed_lib.json for PR #8607
Also addressed:
- removed dependency on legacy config (excluded apply_old_config.h)
- removed legacy pwm and saadc headers
- Arm Compiler 5 linking issue (a band-aid for now... needs to
be properly addressed for peripheral sharing)
- added missing header in SoftDevice file
- top level files ported from TARGET_NORDIC/TARGET_NRF5x/
Also addressed:
- fixed linking issue for gcc
- added support for nRF52-DK builds, but reverted to using nRF52840 sdk_config.h (must be updated)
- introduced "RTC" to targets.json (might need to be removed eventually)
Musca-A1 is a Cortex-M33 based target with security extension enabled.
- ARM_MUSCA_A1 is the non-secure target running mbed-os.
- ARM_MUSCA_A1_S is the secure target running TF-M.
- TF-M sources were imported and patched in previous commits.
- TF-M secure bootloader (McuBoot) for MUSCA_A1 is submitted by a pre-built binary.
- A post-build hook concatenates The secure and non-secure binaries,
signs it and then concatenates the bootloader with the signed binary.
due to partial implementation. Having FUTURE_SEQUANA_M0 and
FUTURE_SEQUANA PSA targets is misleading.
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
In M2351 SPDMC (SMCC) test, it boots from secure code to non-secure bootloader, and finally
to non-secure test code itself. The boot sequence will takes longer than usual. In test
initiation, host will send sync signal 1s after reset device. But due to the longer boot
sequence, test code in device can miss the signal. We enlarge the reset idle time to fix
the issue.
Change the heuristic for selection of CMSE in the tools python, so that
a non-TrustZone ARMv8 build can happen.
Ideally we would have more direct flagging in the targets, but this
refines the heuristic so the necessary behaviour can be easily
achieved.
* DOMAIN_NS=1 is based purely on the `-NS` suffix on the core name.
* Enabling CMSE in the compiler and outputting a secure import library
is now enabled when the core doesn't have an `-NS` suffix by either
the target label `TFM` being present or the flag `trustzone` being set.
This covers the existing ARMv8-M behaviour - TF-M builds have the TFM
label, as per its documentation; M2351 secure builds have no explicit
flagging, so we ensure that the M2351_NS target has the trustzone flag
set, and the out-of-tree secure target inherits that.
Some Nuvoton targets support DEVICE_FLASH but their corresponding COMPONENT_FLASHIAP
supports are not enabled. Enable them:
NUMAKER_PFM_M453
NUMAKER_PFM_M2351
According to their cmsis.h, FPU is present, so change targets.json to
use it.
* ARM_MPS2_M4: already was Cortex-M4F
* ARM_MPS2_M7: Cortex-M7 -> M7FD
* FVP_MPS2_M4: Cortex-M4 -> M4F
* FVP_MPS2_M7: Cortex-M7 -> M7FD
If they do not in fact have FPU, then cmsis.h should be modified to set
`__FPU_PRESENT` to 0. This will currently cause compilation problems
with ARMC6, but I'll be submitting a fix for that.
GeneratedSource folders are BSP specific. No parts of the kit BSP can be reused
as generic chip support package. Remove TARGET_CY8C62XX directory,
and use flat BSP inheritance model:
MCU_PSOC6 -> MCU_PSOC6_M4 -> CY8CKIT_062_WIFI_BT
MCU_PSOC6 -> MCU_PSOC6_M0 -> CY8CKIT_062_WIFI_BT_M0
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN382(ARM_MPS2_M0). Add "IAR" to supported_toolchain list.
Change-Id: I2b2ad7645166c4f973a8baa9c394521514183767
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN383(ARM_MPS2_M0P). Add "IAR" to supported_toolchain list.
Change-Id: Ib2278d34e265e53ad070aecd318ed4e6a355e3c0
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN382(ARM_MPS2_M0). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I7046b698834c82e94015e51eef9a0f5e1315ddaa
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN383(ARM_MPS2_M0P). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I48020b4f0f1b6e0aef3c53f5a3586bc9e9fca9c9
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN385(ARM_MPS2_M3). Add "IAR" to supported_toolchain list.
Change-Id: I038b05b8b21bd146a1568de897ed030ccd52ab79
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN386(ARM_MPS2_M4). Add "IAR" to supported_toolchain list.
Change-Id: I4f43617c870197b9d39a4d4c9c12456adcc6f96f
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN500(ARM_MPS2_M7). Add "IAR" to supported_toolchain list.
Change-Id: I0b8f018fc937727382b27ea0669940ae6675c834
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN385(ARM_MPS2_M3). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I3110d4ab37a3294488a80a8dc1c929bfd87ce989
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN386(ARM_MPS2_M4). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ib8cea952e1ce0a5ef11ab623cca6f3786eab56f5
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN500(ARM_MPS2_M7). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ife109e9e1f2ec8e075e566f9d5c2ec7e3c5067f2
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
These file changes provide small fixes for various targets
on MPS2 platform in order to work properly and pass all
Greentea test cases. The __initial_sp has been explicitly set
in the targets' startup files, and also INITIAL_SP has been
given a different value. The values have been extracted from
the specific targets' Application Note documentation.
Affected targets are: ARM_MPS2_M0, ARM_MPS2_M0P, ARM_MPS2_M3,
ARM_MPS2_M4 and ARM_MPS2_M7.
Change-Id: I3d5d0e1ae386cdcc3ba5eb63be929267a257b139
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
The hal code for this target uses "const volatile" types inside of
structs, which are non-trivially copyable in clang (used by ARMC6). This
causes the build to fail.
Here's the commit that changed this in clang:
a3d727ba77
It seems this was reverteed some time ago in clang, but ARMC6 may not
be up to date.
Please note the heap address of the both the banks must not be contigious else
GCC considers it to be single memory bank and does allocation across the banks,
which might result into hard-fault
New `target.console-uart` option added to indicate whether a target has
a console UART on STDIO_UART_TX/RX/RTS/CTS pins. (The existing option
`target.console-uart-flow-control` indicates whether RTS and or CTS is
available in addition to TX and RX).
The option defaults to true, and is currently true on all platforms. It
only applies if DEVICE_SERIAL is true, so no need to go through and mark
it false for non-SERIAL platforms.
An application can turn off target.console-uart to save ROM/power/etc if
they don't want to use the serial console. If this is turned off, the
console won't be activated for stdin/stdout, but the application is
still free to open `UARTSerial(STDIO_UART_TX, STDIO_UART_RX)`
themselves.
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
Until the CMSIS pack device name is officially deployed.
then we'll the name as can be found in Keil CMSIS pack
<!-- ************************* Device 'STM32WB55RG' ***************************** -->
<device Dname="STM32WB55RGVx">
<memory id="IROM1" start="0x08000000" size="0x001000000" startup="1" default="1" />
<memory id="IRAM1" start="0x20000000" size="0x000040000" init="0" default="1" />
<algorithm name="CMSIS/Flash/STM32WB_M4.FLM" start="0x08000000" size="0x001000000" default="1" />
<feature type="QFP" n="68"/>
</device>
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
Nuvoton targets below don't provide SPI-bus SD on-board, identified by 'SD' in
target component list. Instead, these targets provide SD-bus SD on-board, identified
by unofficial 'NUSD', driver of which is provided outside mbed-os tree. So 'SD' must
be removed to reflect the truth.
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
- NUMAKER_PFM_M2351
Old M2351 CMSIS pack reports single secure ROM/RAM spec. It is updated in new
version which reports secure/non-secure ROM/RAM spec. Override this memory spec
in targets.json regardless of CMSIS.
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
Due to a bug the LPTIM peripheral can cause interrupts to fire at the
wrong time on the NUCLEO_L073RZ. This patch switches the backend
of the low power ticker to the RTC until this bug is addressed.
Ronny Liu
aglass0fmilk
Martin Kojtal
Rajkumar Kanagaraj
Steve Cartmell
Ganesh Ramachandran
ccli8
Qinghao Shi
Lukas Mandak
Steven Cooreman
Bartek Szatkowski
Vincent Veron
RFulchiero
Desmond Chen
Michael Schwarcz
Chris Trowbridge
Devaraj Ranganna
Anna Bridge
Guillermo Alonso
Kevin Bracey
Lin Gao
Ryan Morse
petroborys
Mahesh Mahadevan
Laurent Meunier
fred.li
Hennadiy Kytsun
Shawn Shan
Brian Daniels
Cruz Monrreal
Deepika
Leszek Rusinowicz
Ashok Rao
bcostm
David Saada
jk
Oren Cohen
jeromecoutant
Malavika Sajikumar
Yossi Levy
Evgeni Bolotin
Shuopeng Deng
Oleg Kapshii
Senthil Ramakrishnan
Russ Butler
Moran Peker
Moran Peker
Lei Zhang
Seppo Takalo
Amir Cohen
Donatien Garnier
panyz0725@thundersoft.com