Needed for PSoC to deep-sleep for more than 2 seconds
Max sleep with 16 bit lp_ticker (before this change) : 2sec
Max sleep with 32 bit lp_ticker (after this change) : 36hours
The cache must be refreshed when we erase or program flash memory.
It fix 2 issues :
Fix#9934Fix#6380
This solution was initially proposed in #6380.
Signed-off-by: Vincent Veron <vincent.veron@st.com>
The OS timer of RZ/A1 uses P0 clock, so until now it has been set the value of P0 clock in SystemCoreClock.
Changed the system clock value to set to SystemCoreClock.
Changed to refer to P0 clock macro instead of SystemCoreClock in OS timer processing.
Nuvoton targets below don't provide SPI-bus SD on-board, identified by 'SD' in
target component list. Instead, these targets provide SD-bus SD on-board, identified
by unofficial 'NUSD', driver of which is provided outside mbed-os tree. So 'SD' must
be removed to reflect the truth.
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
- NUMAKER_PFM_M2351
The flash driver for the LPC55S69 is different from
prior LPC family. Move the Flash HAL driver to SoC
specific folder
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This data, placed at physically not existing addresses (0x9xxxxxxx) was used
only by PSoC Programmer and KitProg2 and is no longer needed, but was causing
issues with standard hex file processing tools like srecord (srec_cat).
If the board-specific initialization code configures the serial port to
use an 8-bit divider, the serial_init_clock function would configure the
16-bit divider with the same index instead of the intended 8-bit
divider.
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
Page size in all PSOC6 boards is 512 bytes. This is very problematic in
all storage applications. This change reduces the page size (in flash_api's
flash_program_page API) to 32 by reading the original page, modifying it
with programmed data and programming it back. The number 32 for page size
conforms to the number of times (16) this action can be done.
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Due to a bug the LPTIM peripheral can cause interrupts to fire at the
wrong time on the NUCLEO_L073RZ. This patch switches the backend
of the low power ticker to the RTC until this bug is addressed.
Nuvoton M2351 was including generic core_armv8mbl.h from CMSIS - we
need it to be more specific to identify the specific core for
wait_ns. Change to core_cm23.h.
I implemented USB Device feature for Renesas mbed boards.
The code referenced the following code as a starting point and is implemented it by inheritting USBPhy same as other boards.
(mbed-os\features\unsupported\USBDevice\targets\TARGET_RENESAS)
When activating an endpoint assign new data rather than ORing
data to it. This ensures that values set from the previous use
do not effect the current configuration.
Update the patch "Create HAL_PCD_EP_Abort" to fix bugs.
This patch adds the low level functions USB_EPStopXfer, USB_EPSetNak,
USB_EPClearNak and the high level function HAL_PCD_EP_Abort so that
transfers can be stopped.
The functions USB_EPSetNak and USB_EPClearNak allow nak to be enabled
or disabled for an endpoint, preventing or allowing further transfers.
The function USB_EPStopXfer stops pending reads and writes started by
USB_EPStartXfer along with clearing and masking any interrupts enabled
by USB_EPStartXfer.
The function HAL_PCD_EP_Abort aborts any transfers on the given
endpoint. When this function completes the transfer interrupt
is guarenteed not to fire for this endpoint. Furthermore, the size
of data transferred during an aborted read can be found by calling
the function HAL_PCD_EP_GetRxCount.
Other notes on this Change:
1.
Prior to this patch the interrupt USB_OTG_DOEPINT_EPDISD was not
handled. When an OUT endpoint was disabled this interrupt occurred
causing the CPU to get stuck repeatedly handling this interrupt. This
is because this interrupt was unmasked but nothing cleared this
interrupt. This patch also adds code to handle and clear this
interrupt to prevent a lockup.
2.
Stopping a transfer on an OUT endpoint requires global nak OUT to
be in effect. Even with this being done, having entries in the rx fifo
prevented an OUT endpoint from being disabled. This behavior is not
mentioned in the Reference Manual.
Take the code from
mbed-os\features\unsupported\USBDevice\targets\TARGET_STM
as a starting point and use it to fill in the USBPhy template for STM32
devices.
Move the USBPhy header files into usb/device/USBPhy. Also move hal
and target USB files since mbed 2 does not compile when these files
are present without the USBPhy headers.
Directory restructure summary:
platform/USBPhy*
to usb/device/USBPhy/USBPhy*
hal/*
to usb/device/hal/*
targets/TARGET_Freescale/usb/*
to usb/device/targets/TARGET_Freescale/*
targets/TARGET_NXP/TARGET_LPC176X/usb/*
to usb/device/targets/TARGET_NXP/*
Make the following changes to improve stability:
-When disconnecting set address to disabled to prevent nacks
-Clear EP_SLOW one and only once for every interrupt where it is set_address
-Disable and clear control endpoint interrupts when disconnecting
Even thought the USB phy is disabled during disconnect, endpoints
still nack packets sent. This patch disables all endpoints so after
disconnect no USB traffic will be sent. This allows brief disconnects
of ~200us (or more) to be reliably detected by the host PC.
junichi.katsu@uhuru.jp
Brian Daniels
Vivek Pallantla
Lei Zhang
jeromecoutant
Mahesh Mahadevan
Vincent Veron
ecoromka
d-kato
ccli8
Oren Cohen
Michael Schwarcz
Ryan Morse
Malavika Sajikumar
Juho Eskeli
Ashok Rao
Jan Jongboom
Oleg Kapshii
Ganesh Ramachandran
Wajahat Abbas
Michael Coulter
mudassar-ublox
Alexander Zilberkant
David Saada
Yossi Levy
Oren Cohen
Evgeni
Cruz Monrreal II
Arto Kinnunen
Alexander Zilberkant
Leszek Rusinowicz
Sarah Marsh
Kyle Kearney
Neil Tuttle
Neil Tuttle
Shuopeng Deng
Sergii Vozniak
Netanel Gonen
Martin Kojtal
Senthil Ramakrishnan
Kevin Bracey
Deepika
Seppo Takalo
Russ Butler
Moran Peker
itayzafrir
j3hill
Moran Peker
Jarno Lamsa
Amir Cohen
Donatien Garnier
panyz0725@thundersoft.com
bcostm
TomoYamanaka
Russ Butler
Michel Jaouen
Maciej Bocianski