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TARGET_PSOC6: Fix incorrect serial clock divider 

If the board-specific initialization code configures the serial port to
use an 8-bit divider, the serial_init_clock function would configure the
16-bit divider with the same index instead of the intended 8-bit
divider.
pull/10067/head
Neil Tuttle 2019-03-01 14:47:57 -08:00 committed by Cruz Monrreal II
parent 6ea172179f
commit d29baa0125
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c
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@ -305,6 +305,7 @@ static cy_en_sysclk_status_t serial_init_clock(serial_obj_t *obj, uint32_t baudr
}
}
} else {
/* Divider already allocated and connected to the SCB block */
status = CY_SYSCLK_SUCCESS;
}
@ -312,17 +313,17 @@ static cy_en_sysclk_status_t serial_init_clock(serial_obj_t *obj, uint32_t baudr
Cy_SysClk_PeriphDisableDivider(obj->div_type, obj->div_num);
/* Set baud rate */
if (obj->div_type == CY_SYSCLK_DIV_16_5_BIT) {
if ((obj->div_type == CY_SYSCLK_DIV_16_5_BIT) || (obj->div_type == CY_SYSCLK_DIV_24_5_BIT)) {
/* Get fractional divider */
uint32_t divider = divider_value(baudrate * UART_OVERSAMPLE, 5U);
status = Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT,
status = Cy_SysClk_PeriphSetFracDivider(obj->div_type,
obj->div_num,
FRACT_DIV_INT(divider),
FRACT_DIV_FARCT(divider));
} else {
/* Get integer divider */
status = Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT,
status = Cy_SysClk_PeriphSetDivider(obj->div_type,
obj->div_num,
divider_value(baudrate * UART_OVERSAMPLE, 0));
}