From d29baa0125f0424c1520f65aa24b59de919537c2 Mon Sep 17 00:00:00 2001 From: Neil Tuttle Date: Fri, 1 Mar 2019 14:47:57 -0800 Subject: [PATCH] TARGET_PSOC6: Fix incorrect serial clock divider If the board-specific initialization code configures the serial port to use an 8-bit divider, the serial_init_clock function would configure the 16-bit divider with the same index instead of the intended 8-bit divider. --- targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c index 59d3e5749f..6b009f7132 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c @@ -305,6 +305,7 @@ static cy_en_sysclk_status_t serial_init_clock(serial_obj_t *obj, uint32_t baudr } } } else { + /* Divider already allocated and connected to the SCB block */ status = CY_SYSCLK_SUCCESS; } @@ -312,17 +313,17 @@ static cy_en_sysclk_status_t serial_init_clock(serial_obj_t *obj, uint32_t baudr Cy_SysClk_PeriphDisableDivider(obj->div_type, obj->div_num); /* Set baud rate */ - if (obj->div_type == CY_SYSCLK_DIV_16_5_BIT) { + if ((obj->div_type == CY_SYSCLK_DIV_16_5_BIT) || (obj->div_type == CY_SYSCLK_DIV_24_5_BIT)) { /* Get fractional divider */ uint32_t divider = divider_value(baudrate * UART_OVERSAMPLE, 5U); - status = Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT, + status = Cy_SysClk_PeriphSetFracDivider(obj->div_type, obj->div_num, FRACT_DIV_INT(divider), FRACT_DIV_FARCT(divider)); } else { /* Get integer divider */ - status = Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, + status = Cy_SysClk_PeriphSetDivider(obj->div_type, obj->div_num, divider_value(baudrate * UART_OVERSAMPLE, 0)); }