I moved the exit handler from exit.c to retarget.cpp where the rest of
the standard C library retargetting routines are found. The exported
makefiles already explicitly link in retarget.o but not exit.o
When building with the GNU toolchain, it is safest to link in the
object file directly for retargetting routines so that GNU linker has
to use these versions of the routines.
Testing:
I have only tested this change with GCC_ARM. It should really be
tested with more toolchains before getting merged.
Activated the I2CSlave functions. Slave block read/write operations are fully supported. The slave byte read and writes need general modification to I2CSlave.cpp. See pending Issue.
Activated the PWM functions. They are supported now using the SCT after updating us_ticker() to use the MRT instead of the SCT.
Added PWM support for the LPC812 using the SCT. Code was ported from LPC824 libs.
First needed to modify us_ticker() to free up the SCT and use the MRT instead.
PWM can support a maximum of 4 channels using any portpin. All channels will use the same period.
Removed comments again regarding need for dedicated i2c_slave_byte_read() and i2c_slave_byte_read(). This issue is captured in "I2c - slave should have own write/read functions (#896)"
Disabled DEVICE_I2CSLAVE option for LPC812 until the dedicated i2c_slave_byte_read() and i2c_slave_byte_write() functions have been added for all platforms.
Fixed SystemCoreClock calculation for LPC810 (same as for LPC812). Added MainClock variable for serial_api.
Added comments for PLL calculation. Note that SystemCoreClock for LPC810 is still 24MHz rather than rated 30MHz.
The dedicated I2C Slave byte read and byte write functions need to be called
from 'common' mbed I2CSlave API for devices that have separate Master and
Slave engines such as the lpc812 and lpc1549.
Added i2c_slave_byte_read() and i2c_slave_byte_write() for devices such as the lpc812, lpc824 and lpc1549 that have separate I2C engines for Master and Slave functions.
Added support for I2C Slave block read, block write and byte read and write. The slave address can be set and the general call address is automatically enabled. Note that the lpc812, lpc824 and lpc1549 have the same I2C engine. This new engine is very different from the lpc1768 and other NXP mbeds. The newer engine has separate controls for Master and Slave functions and they can be enable at the same time. Note that currently the lib does not support multi-master (arbitration lost is not handled).
Modifies are as below.
- Add flow control
- Change the range of baud rate that can be set in the baud function.
8138 bps more -> 128 bps more
- Fixed a bug that designation of parity had been reversed in format().
Fixed the incorrect clocksource for the baud generator. Should be MainClock instead of SystemCoreClock. This also allows the correct use of the PLL for MainClock and SystemCoreClock without breaking the serial baudrate.
LPC812 was running at 12MHz on IRC. Added and fixed PLL activation to change the clockspeed into the expected 30MHz. Clock source is still the IRC. Selecting the 12 MHz XTAL clocksource should also work with the PLL.
Added MainClock to fix wrong setting of SystemCoreClock and allow the serial_api to use the correct clock.
Quick fix of block read and write. The i2c_start is still wrong: it
should setup the address before initiating a Start condition. Status
read is also wrong in i2c_do_read.
I was getting Hard Faults in even the simplest of samples before I made
these fixes.
* WaitUs() did nothing on optimized builds. I added the volatile
qualifier to the cyc variable to make sure that the delay loop
doesn't get optimized out.
* I removed the #ifdef which skipped the fpuInit() call when building
with GCC.
If user set P0_0 as DigitalOut and set it to low, LPC1114 will be in
reset condion. To avoid this situation, p4, xp4 and dp23 was removed
from PinNames.h.
Please note that this commit goes with another recent commit to the nRF51822 repository which updated values under projectconfig.h. Please remember to update nRF51822 as well.
This has a bearing on issue #832.
Bugs are as below.
- Add terminal setting of IRQ4 and IRQ6 that leaked.
- When set the interrupt function by rise()/fall(), the interrupt disable state will be released by disable_irq().
- Interrupt will be continued to occur when execute disable_irq() after rise(NULL)/fall(NULL) set.
- Fix the setting timing of PMC register.
guidelines.
* Uncommented assertions in operators and added check for operator[] index < 0.
* Moved one operator from private to public, this was a typo thing.
- some minor error correction
- add pin definition for 3 tests (MBED_A5,6,7)
- add new target disco_f401vc to travis_build
travis_build and all test are OK except missing STM32F4 target
MTS_MDOT_F405RG
The mcu STM32L053C8 seems to have a problem in the RCC - LSE hardware
block. The Disco_L053 don't have a 32kHz crystal connected to LSE port
pins in contrast to NUCLEO_L053.
During initialization the HAL tests if it can start the LSE oscillator.
The Flag LSERDY in RCC_CSR is set to 1 by RCC clock control when the
oscillator runs stable. Without a crystal the flag shouldn't be set and
the HAL trys to start the internal LSI oscillator.
But the flag is always set to 1 also without a crystal. That's why the
RTC doesn't start.
In case of off-line compiler, there is no problem about the frequency setting processing.
But in case of online compiler, the frequency setting processing will be error.
So, modify frequency setting processing of SPI to pass in online compiler.
Issue originally reported on mbed site here:
https://developer.mbed.org/questions/5695/FRDM-KL05z-hardfault-when-compiled-with-/
The RAM base address was incorrectly set to the beginning of RAM
instead of at a 0xC0 byte offset to reserve room for the interrupt
vectors. Without this fix, the global variables and the interrupt
vectors were occupying the same space in RAM once the user enabled the
timer interrupt.
The user who originally reported the issue on the mbed site has tested
this fix and verified that it corrected the hard fault issue that they
were encountering.
- Change default setting of CMSIS-RTOS RTX for Cortex-A9 to align with Cortex-M.
- Change the interrupt priority of Ether driver to align with other drivers.
Changes as below.
-I2C
Change communication wait time and Frequency accuracy improvement of I2C.
- Frequency accuracy improvement
- Changed the wait time between one communication completed and the next communication start.
The wait time will be Low clock width by this changing.
-PWM
Modify processing of pulsewidth() of PWM
- Modify processing of pulsewidth() to match the specifications of the RZ_A1H.
-SPI
Fixed a bug that SPI driver is not able to communicate when transfer bit length is 16bit or 32bit.
- Frequency accuracy improvement
- Modify transfer processing when transfer bit length is 16bit or 32bit.
-Serial
Change the reference register macro of Serial
- Change the reference register macro to align with other driver codes.
Changing original STM Cube Driver to call _start instead of main to
initialise the rtos when using it. Without using rtos the behavior is
the same as before.
Original STM32Cube F4 driver sets SYSCLK for STM32F429 to 16MHz. This
adds a 168MHz and 180MHz configuration to system_stm32f4xx.c generated
by STM32CubeMX code generator. The rtos clock configuration is changed
too. In singletest.py run everything is OK.
- Changing original STM Cube Driver to call _start instead of main to
initialise the rtos when using it. Without using rtos the behavior is
the same as before.
- Adding DISCO_F429 to rtos
- Adding targets to RTOS_xx tests.
- All tests are OK. Tested with Nucleo and Disco boards. Not tested with
MDOT_F4 but that uses the same hal like nucleo_f411.
Fix a bug as below.
- Period can not be changed.
Restructions: 1. The upper limits is 491us
2. Change all period of the same channel when changing period.
Fix some bugs of Serial as below.
- TX/RX terminal of XBee(P7_4, P7_5) setting is reverse.
- P5_6 and P5_7 terminals can not be used.
- Tx interrupt will not occur at the right timing.
- There are no settings of WIFI Module terminals(P11_10,P11_11).
- There are no settings of Xbee Module terminals(P6_6,P6_7).
Timer value wraparound operation had not been considered in common wait process.
By defining the EXPIRE_US non-zero value, wraparound operation is enabled.
The EXPIRE_US will be define the value of each vender-specific.
If EXPIRE_US is 0, the common wait process is same as before.
nRF51822 from Nordic Semiconductor
Bluetooth Low-Energy v4.1 compliant - interface to smartphones, tablets
System-on-Chip (SoC) solution - easily transformable into a deployable solution
Drop-in solution for production - no need to design your own antenna
FCC and CE Certified
3x LEDs, 3x Buttons
Powered by interface board or external 3.3V
Y5 Design LLC Interface Board
LPC11u35 from NXP
Low Power, ARM(r) Cortex-M0 suitable for a wide range of applications
On-Chip Bootloader - In-System programming (ISP) and in-application programming (IAP)
ROM-based USB drivers - Flash updates via USB supported
SPI, GPIO, i2C, UART, ADC
3x LEDs, Reset Button
3.3V powered via USB or external
USB interface - shipped with USB-A, male connector, pads for Micro female
Fix IAR serial fgets fgetc
Taken from PR #770:
setbuf(_file, NULL), and std::setvbuf(_file,NULL,_IONBF,NULL) should both give an unbuffered stream (the data is directly written to the input buffer). IAR sets a buffer anyway of size 512 bytes for these calls. Calling setvbuff(_file,buf,_IONBF,NULL) with a buffer that is not a NULL pointer sets the buffer to size one. Which means that as soon as a char is read it is written to the real buffer. If people are interested in looking at this further they can look at the files under ARM/src/dlib: fgets.c, fflush.c, xfrpep.c and xfwprep.c
Three changes, first it fixes:
https://github.com/mbedmicro/mbed/issues/761 (which was reported
slightly wrong because K20 has again different clocking from KLXX for
uarts).
Second it adds mcgpllfll to clk_freqs, which again is different for K20
compared to KLXX .
Finally it adds the fractional baudrate divider for more accurate serial
baudrates.
Change I2C driver transfer sequence to go according to H/W manual.
Changed contents are as below.
- Access procedure of ACTBT bit of MR3 register
- Issuance procedure of stop condition
When read the timer value, it have a potential to read abnormal value.
Because we used 16bit + 16bit cascade timer and read timer count separately.
Changed usticker timer from 16bit + 16bit cascade timer to 32bit timer to fix the bug.
Updates startup files to actual versions of STM32 Cube drivers without
any changes of STs drivers:
- DISCO_F303VC
- DISCO_F334
- NUCLEO_F030
- NUCLEO_F072
- NUCLEO_F302
- NUCLEO_F334
- CoIDE options: wrap main and linker option DiscradUnusedSection=1 was
missing in some targets
- CoIDE options: corrected flash loader config for Nucleo_F030 and
Nucleo_F072
- CoIDE options: corrected memory layout (not used per default but now
it is the same as in linker script)
- gcc linker script: changed the memory size from hex number e.g. 0x2000
to decimal 8K
The bugs of IRQ Edge Interrupt as below.
- Not call a function that was registered in rise, always call a function that was registered in the fall.
- If there are multiple interrupt sources, there is a possibility that end the wrong interrupt processing.
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