mirror of https://github.com/ARMmbed/mbed-os.git
Initial support for LPC11U37H_401
nitin.bhaskar.27.09@gmail.com
parent
542dba531c
commit
f38d985cc8
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@ -0,0 +1,20 @@
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LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
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ER_IROM1 0x00000000 0x20000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0x1F40
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RW_IRAM1 0x100000C0 0x1F40 {
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.ANY (+RW +ZI)
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}
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RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
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.ANY (IOHANDLER_RAM)
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}
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RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
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.ANY (USBRAM)
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}
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}
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@ -0,0 +1,325 @@
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;/*****************************************************************************
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; * @file: startup_LPC11xx.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File
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; * for the NXP LPC11xx Device Series
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; * @version: V1.0
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; * @date: 25. Nov. 2008
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2008 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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; for LPC11Uxx (With USB)
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DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
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DCD FLEX_INT1_IRQHandler
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DCD FLEX_INT2_IRQHandler
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DCD FLEX_INT3_IRQHandler
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DCD FLEX_INT4_IRQHandler
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DCD FLEX_INT5_IRQHandler
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DCD FLEX_INT6_IRQHandler
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DCD FLEX_INT7_IRQHandler
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DCD GINT0_IRQHandler
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DCD GINT1_IRQHandler ; PIO0 (0:7)
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD SSP1_IRQHandler ; SSP1
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DCD I2C_IRQHandler ; I2C
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DCD TIMER16_0_IRQHandler ; 16-bit Timer0
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DCD TIMER16_1_IRQHandler ; 16-bit Timer1
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DCD TIMER32_0_IRQHandler ; 32-bit Timer0
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DCD TIMER32_1_IRQHandler ; 32-bit Timer1
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DCD SSP0_IRQHandler ; SSP0
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DCD UART_IRQHandler ; UART
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DCD USB_IRQHandler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_IRQHandler ; A/D Converter
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DCD WDT_IRQHandler ; Watchdog timer
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD USBWakeup_IRQHandler ; USB wake up
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DCD Reserved_IRQHandler ; Reserved
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;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
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; for particular peripheral.
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;NMI_Handler PROC
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; EXPORT NMI_Handler [WEAK]
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; B .
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; ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Reserved_IRQHandler PROC
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EXPORT Reserved_IRQHandler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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; for LPC11Uxx (With USB)
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EXPORT NMI_Handler [WEAK]
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EXPORT FLEX_INT0_IRQHandler [WEAK]
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EXPORT FLEX_INT1_IRQHandler [WEAK]
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EXPORT FLEX_INT2_IRQHandler [WEAK]
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EXPORT FLEX_INT3_IRQHandler [WEAK]
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EXPORT FLEX_INT4_IRQHandler [WEAK]
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EXPORT FLEX_INT5_IRQHandler [WEAK]
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EXPORT FLEX_INT6_IRQHandler [WEAK]
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EXPORT FLEX_INT7_IRQHandler [WEAK]
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EXPORT GINT0_IRQHandler [WEAK]
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EXPORT GINT1_IRQHandler [WEAK]
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EXPORT SSP1_IRQHandler [WEAK]
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EXPORT I2C_IRQHandler [WEAK]
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EXPORT TIMER16_0_IRQHandler [WEAK]
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EXPORT TIMER16_1_IRQHandler [WEAK]
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EXPORT TIMER32_0_IRQHandler [WEAK]
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EXPORT TIMER32_1_IRQHandler [WEAK]
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EXPORT SSP0_IRQHandler [WEAK]
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EXPORT UART_IRQHandler [WEAK]
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EXPORT USB_IRQHandler [WEAK]
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EXPORT USB_FIQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT USBWakeup_IRQHandler [WEAK]
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NMI_Handler
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FLEX_INT0_IRQHandler
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FLEX_INT1_IRQHandler
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FLEX_INT2_IRQHandler
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FLEX_INT3_IRQHandler
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FLEX_INT4_IRQHandler
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FLEX_INT5_IRQHandler
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FLEX_INT6_IRQHandler
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FLEX_INT7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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SSP1_IRQHandler
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I2C_IRQHandler
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TIMER16_0_IRQHandler
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TIMER16_1_IRQHandler
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TIMER32_0_IRQHandler
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TIMER32_1_IRQHandler
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SSP0_IRQHandler
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UART_IRQHandler
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USB_IRQHandler
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USB_FIQHandler
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ADC_IRQHandler
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WDT_IRQHandler
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BOD_IRQHandler
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FMC_IRQHandler
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USBWakeup_IRQHandler
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B .
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ENDP
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ALIGN
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END
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@ -0,0 +1,20 @@
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LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
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ER_IROM1 0x00000000 0x10000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 8KB - 0xC0 = 0x1F40
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RW_IRAM1 0x100000C0 0x1F40 {
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.ANY (+RW +ZI)
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}
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RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
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.ANY (IOHANDLER_RAM)
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}
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RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
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.ANY (USBRAM)
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}
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}
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@ -0,0 +1,308 @@
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;/*****************************************************************************
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; * @file: startup_LPC11xx.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File
|
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; * for the NXP LPC11xx Device Series
|
||||
; * @version: V1.0
|
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; * @date: 25. Nov. 2008
|
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
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; * Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
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__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
|
||||
|
||||
PRESERVE8
|
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THUMB
|
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|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
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EXPORT __Vectors
|
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|
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
|
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
|
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DCD MemManage_Handler ; MPU Fault Handler
|
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DCD BusFault_Handler ; Bus Fault Handler
|
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
|
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DCD 0 ; Reserved
|
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
|
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DCD SysTick_Handler ; SysTick Handler
|
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|
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; External Interrupts
|
||||
; for LPC11Uxx (With USB)
|
||||
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
|
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DCD FLEX_INT1_IRQHandler
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DCD FLEX_INT2_IRQHandler
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DCD FLEX_INT3_IRQHandler
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DCD FLEX_INT4_IRQHandler
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DCD FLEX_INT5_IRQHandler
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DCD FLEX_INT6_IRQHandler
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DCD FLEX_INT7_IRQHandler
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DCD GINT0_IRQHandler
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DCD GINT1_IRQHandler ; PIO0 (0:7)
|
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD Reserved_IRQHandler
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DCD SSP1_IRQHandler ; SSP1
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DCD I2C_IRQHandler ; I2C
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DCD TIMER16_0_IRQHandler ; 16-bit Timer0
|
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DCD TIMER16_1_IRQHandler ; 16-bit Timer1
|
||||
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
|
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DCD TIMER32_1_IRQHandler ; 32-bit Timer1
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DCD SSP0_IRQHandler ; SSP0
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DCD UART_IRQHandler ; UART
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DCD USB_IRQHandler ; USB IRQ
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DCD USB_FIQHandler ; USB FIQ
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DCD ADC_IRQHandler ; A/D Converter
|
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DCD WDT_IRQHandler ; Watchdog timer
|
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DCD BOD_IRQHandler ; Brown Out Detect
|
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DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
|
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DCD Reserved_IRQHandler ; Reserved
|
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DCD Reserved_IRQHandler ; Reserved
|
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DCD USBWakeup_IRQHandler ; USB wake up
|
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DCD Reserved_IRQHandler ; Reserved
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|
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;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
|
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
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DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
|
||||
; for particular peripheral.
|
||||
;NMI_Handler PROC
|
||||
; EXPORT NMI_Handler [WEAK]
|
||||
; B .
|
||||
; ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; for LPC11Uxx (With USB)
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
EXPORT FLEX_INT0_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT1_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT2_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT3_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT4_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT5_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT6_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_1_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT UART_IRQHandler [WEAK]
|
||||
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT USBWakeup_IRQHandler [WEAK]
|
||||
|
||||
NMI_Handler
|
||||
FLEX_INT0_IRQHandler
|
||||
FLEX_INT1_IRQHandler
|
||||
FLEX_INT2_IRQHandler
|
||||
FLEX_INT3_IRQHandler
|
||||
FLEX_INT4_IRQHandler
|
||||
FLEX_INT5_IRQHandler
|
||||
FLEX_INT6_IRQHandler
|
||||
FLEX_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C_IRQHandler
|
||||
TIMER16_0_IRQHandler
|
||||
TIMER16_1_IRQHandler
|
||||
TIMER32_0_IRQHandler
|
||||
TIMER32_1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
UART_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQHandler
|
||||
ADC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
BOD_IRQHandler
|
||||
FMC_IRQHandler
|
||||
USBWakeup_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
|
||||
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
|
||||
RAMIO (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800
|
||||
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text.Reset_Handler)
|
||||
|
||||
/* Only vectors and code running at reset are safe to be in first 512
|
||||
bytes since RAM can be mapped into this area for RAM based interrupt
|
||||
vectors. */
|
||||
. = 0x00000200;
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/* mbed - LPC11U35 linker script
|
||||
* Based linker script generated by Code Red Technologies Red Suite 4.1
|
||||
*/
|
||||
GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
|
||||
RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
|
||||
RamIo1 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2k */
|
||||
RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
|
||||
}
|
||||
/* Define a symbol for the top of each memory region */
|
||||
__top_MFlash32 = 0x0 + 0x10000;
|
||||
__top_RamLoc8 = 0x10000000 + 0x1F40;
|
||||
__top_RamIo1 = 0x20000000 + 0x800;
|
||||
__top_RamUsb2 = 0x20004000 + 0x800;
|
||||
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* MAIN TEXT SECTION */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text.ResetISR)
|
||||
. = 0x200;
|
||||
|
||||
/* Global Section Table */
|
||||
. = ALIGN(4) ;
|
||||
__section_table_start = .;
|
||||
__data_section_table = .;
|
||||
LONG(LOADADDR(.data));
|
||||
LONG( ADDR(.data)) ;
|
||||
LONG( SIZEOF(.data));
|
||||
LONG(LOADADDR(.data_RAM2));
|
||||
LONG( ADDR(.data_RAM2)) ;
|
||||
LONG( SIZEOF(.data_RAM2));
|
||||
__data_section_table_end = .;
|
||||
__bss_section_table = .;
|
||||
LONG( ADDR(.bss));
|
||||
LONG( SIZEOF(.bss));
|
||||
LONG( ADDR(.bss_RAM2));
|
||||
LONG( SIZEOF(.bss_RAM2));
|
||||
__bss_section_table_end = .;
|
||||
__section_table_end = . ;
|
||||
/* End of Global Section Table */
|
||||
|
||||
|
||||
*(.after_vectors*)
|
||||
|
||||
*(.text*)
|
||||
*(.rodata .rodata.*)
|
||||
. = ALIGN(4);
|
||||
|
||||
/* C++ constructors etc */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
KEEP(*(.fini));
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
/* End C++ */
|
||||
} > MFlash32
|
||||
|
||||
/*
|
||||
* for exception handling/unwind - some Newlib functions (in common
|
||||
* with C++ and STDC++) use this.
|
||||
*/
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > MFlash32
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > MFlash32
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
|
||||
|
||||
.data_RAM2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.data.$RAM2*)
|
||||
*(.data.$RamUsb2*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamUsb2 AT>MFlash32
|
||||
|
||||
/* MAIN DATA SECTION */
|
||||
|
||||
.uninit_RESERVED : ALIGN(4)
|
||||
{
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
} > RamLoc8
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = .;
|
||||
} > RamLoc8 AT>MFlash32
|
||||
|
||||
|
||||
.bss_RAM2 : ALIGN(4)
|
||||
{
|
||||
*(.bss.$RAM2*)
|
||||
*(.bss.$RamUsb2*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamUsb2
|
||||
|
||||
/* MAIN BSS SECTION */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
PROVIDE(end = .);
|
||||
__end__ = .;
|
||||
} > RamLoc8
|
||||
|
||||
PROVIDE(_pvHeapStart = .);
|
||||
PROVIDE(_vStackTop = __top_RamLoc8 - 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)LPC_USART_BASE
|
||||
} UARTName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)LPC_I2C_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
ADC0_0 = 0,
|
||||
ADC0_1,
|
||||
ADC0_2,
|
||||
ADC0_3,
|
||||
ADC0_4,
|
||||
ADC0_5,
|
||||
ADC0_6,
|
||||
ADC0_7
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)LPC_SSP0_BASE,
|
||||
SPI_1 = (int)LPC_SSP1_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
PWM_1 = 0,
|
||||
PWM_2,
|
||||
PWM_3,
|
||||
PWM_4,
|
||||
PWM_5,
|
||||
PWM_6,
|
||||
PWM_7,
|
||||
PWM_8,
|
||||
PWM_9,
|
||||
PWM_10,
|
||||
PWM_11
|
||||
} PWMName;
|
||||
|
||||
#define STDIO_UART_TX UART_TX
|
||||
#define STDIO_UART_RX UART_RX
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{P0_11, ADC0_0, 0x02},
|
||||
{P0_12, ADC0_1, 0x02},
|
||||
{P0_13, ADC0_2, 0x02},
|
||||
{P0_14, ADC0_3, 0x02},
|
||||
{P0_15, ADC0_4, 0x02},
|
||||
{P0_16, ADC0_5, 0x01},
|
||||
{P0_22, ADC0_6, 0x01},
|
||||
{P0_23, ADC0_7, 0x01},
|
||||
{NC , NC , 0 }
|
||||
};
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{P0_5, I2C_0, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{P0_4, I2C_0, 1},
|
||||
{NC , NC, 0}
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{P0_19, UART_0, 1},
|
||||
{P1_13, UART_0, 3},
|
||||
{P1_27, UART_0, 2},
|
||||
{ NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{P0_18, UART_0, 1},
|
||||
{P1_14, UART_0, 3},
|
||||
{P1_26, UART_0, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{P0_6 , SPI_0, 0x02},
|
||||
{P0_10, SPI_0, 0x02},
|
||||
{P1_29, SPI_0, 0x01},
|
||||
{P1_15, SPI_1, 0x03},
|
||||
{P1_20, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{P0_9 , SPI_0, 0x01},
|
||||
{P0_21, SPI_1, 0x02},
|
||||
{P1_22, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{P0_8 , SPI_0, 0x01},
|
||||
{P0_22, SPI_1, 0x03},
|
||||
{P1_21, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{P0_2 , SPI_0, 0x01},
|
||||
{P1_19, SPI_1, 0x02},
|
||||
{P1_23, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
/* To have a PWM where we can change both the period and the duty cycle,
|
||||
* we need an entire timer. With the following conventions:
|
||||
* * MR3 is used for the PWM period
|
||||
* * MR0, MR1, MR2 are used for the duty cycle
|
||||
*/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
/* CT16B0 */
|
||||
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
|
||||
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
|
||||
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
|
||||
|
||||
/* CT16B1 */
|
||||
{P0_21, PWM_4, 1}, /* MR0 */
|
||||
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
|
||||
|
||||
/* CT32B0 */
|
||||
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
|
||||
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
|
||||
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
|
||||
|
||||
/* CT32B1 */
|
||||
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
|
||||
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
|
||||
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
|
||||
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 5
|
||||
|
||||
typedef enum {
|
||||
// LPC11U Pin Names
|
||||
P0_0 = 0,
|
||||
P0_1 = 1,
|
||||
P0_2 = 2,
|
||||
P0_3 = 3,
|
||||
P0_4 = 4,
|
||||
P0_5 = 5,
|
||||
P0_6 = 6,
|
||||
P0_7 = 7,
|
||||
P0_8 = 8,
|
||||
P0_9 = 9,
|
||||
P0_10 = 10,
|
||||
P0_11 = 11,
|
||||
P0_12 = 12,
|
||||
P0_13 = 13,
|
||||
P0_14 = 14,
|
||||
P0_15 = 15,
|
||||
P0_16 = 16,
|
||||
P0_17 = 17,
|
||||
P0_18 = 18,
|
||||
P0_19 = 19,
|
||||
P0_20 = 20,
|
||||
P0_21 = 21,
|
||||
P0_22 = 22,
|
||||
P0_23 = 23,
|
||||
P0_24 = 24,
|
||||
P0_25 = 25,
|
||||
P0_26 = 26,
|
||||
P0_27 = 27,
|
||||
|
||||
P1_0 = 32,
|
||||
P1_1 = 33,
|
||||
P1_2 = 34,
|
||||
P1_3 = 35,
|
||||
P1_4 = 36,
|
||||
P1_5 = 37,
|
||||
P1_6 = 38,
|
||||
P1_7 = 39,
|
||||
P1_8 = 40,
|
||||
P1_9 = 41,
|
||||
P1_10 = 42,
|
||||
P1_11 = 43,
|
||||
P1_12 = 44,
|
||||
P1_13 = 45,
|
||||
P1_14 = 46,
|
||||
P1_15 = 47,
|
||||
P1_16 = 48,
|
||||
P1_17 = 49,
|
||||
P1_18 = 50,
|
||||
P1_19 = 51,
|
||||
P1_20 = 52,
|
||||
P1_21 = 53,
|
||||
P1_22 = 54,
|
||||
P1_23 = 55,
|
||||
P1_24 = 56,
|
||||
P1_25 = 57,
|
||||
P1_26 = 58,
|
||||
P1_27 = 59,
|
||||
P1_28 = 60,
|
||||
P1_29 = 61,
|
||||
|
||||
P1_31 = 63,
|
||||
|
||||
// LED Names
|
||||
LED1 = P1_24,
|
||||
LED2 = P1_25,
|
||||
LED3 = P1_26,
|
||||
LED4 = P0_0,
|
||||
LED5 = P1_3,
|
||||
LED6 = P1_2,
|
||||
LED7 = P1_1,
|
||||
LED8 = P1_0,
|
||||
|
||||
// BTN Names
|
||||
BTN1 = P0_16,
|
||||
BTN2 = P0_1,
|
||||
|
||||
// UART
|
||||
UART_TX = P0_19,
|
||||
UART_RX = P0_18,
|
||||
|
||||
// Arduino Shield Receptacles Names
|
||||
D0 = P0_18,
|
||||
D1 = P0_19,
|
||||
D2 = P1_17,
|
||||
D3 = P1_24,
|
||||
D4 = P1_5,
|
||||
D5 = P0_1,
|
||||
D6 = P1_27,
|
||||
D7 = P0_7,
|
||||
D8 = P0_2,
|
||||
D9 = P1_25,
|
||||
D10= P1_23,
|
||||
D11= P0_21,
|
||||
D12= P0_22,
|
||||
D13= P1_15,
|
||||
D14= P0_5,
|
||||
D15= P0_4,
|
||||
|
||||
A0 = P0_11,
|
||||
A1 = P0_12,
|
||||
A2 = P0_13,
|
||||
A3 = P0_16,
|
||||
A4 = P0_5, // same port as SDA
|
||||
A5 = P0_4, // same port as SCL
|
||||
|
||||
SDA= P0_5, // same port as A4
|
||||
SCL= P0_4, // same port as A5
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF,
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
CHANNEL0 = FLEX_INT0_IRQn,
|
||||
CHANNEL1 = FLEX_INT1_IRQn,
|
||||
CHANNEL2 = FLEX_INT2_IRQn,
|
||||
CHANNEL3 = FLEX_INT3_IRQn,
|
||||
CHANNEL4 = FLEX_INT4_IRQn,
|
||||
CHANNEL5 = FLEX_INT5_IRQn,
|
||||
CHANNEL6 = FLEX_INT6_IRQn,
|
||||
CHANNEL7 = FLEX_INT7_IRQn
|
||||
} Channel;
|
||||
|
||||
typedef enum {
|
||||
PullUp = 2,
|
||||
PullDown = 1,
|
||||
PullNone = 0,
|
||||
Repeater = 3,
|
||||
OpenDrain = 4,
|
||||
PullDefault = PullDown
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 1
|
||||
#define DEVICE_PORTOUT 1
|
||||
#define DEVICE_PORTINOUT 1
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 1
|
||||
#define DEVICE_ANALOGOUT 0
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 1
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 0
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 1
|
||||
|
||||
#define DEVICE_SEMIHOST 0
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
#define DEVICE_ID_LENGTH 32
|
||||
#define DEVICE_MAC_OFFSET 20
|
||||
|
||||
#define DEVICE_SLEEP 1
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 0
|
||||
|
||||
#define DEVICE_ERROR_PATTERN 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -35,6 +35,7 @@ class CodeRed(Exporter):
|
|||
'LPC11U68',
|
||||
'LPCCAPPUCCINO',
|
||||
'LPC824',
|
||||
'LPC11U37H_401',
|
||||
]
|
||||
|
||||
def generate(self):
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,84 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>{{name}}</name>
|
||||
<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red</comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>make</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${workspace_loc:/{{name}}/Debug}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
# This file was automagically generated by mbed.org. For more information,
|
||||
# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
|
||||
|
||||
GCC_BIN =
|
||||
PROJECT = {{name}}
|
||||
OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
|
||||
SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
|
||||
INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
|
||||
LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
|
||||
LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
|
||||
LINKER_SCRIPT = {{linker_script}}
|
||||
|
||||
###############################################################################
|
||||
AS = $(GCC_BIN)arm-none-eabi-as
|
||||
CC = $(GCC_BIN)arm-none-eabi-gcc
|
||||
CPP = $(GCC_BIN)arm-none-eabi-g++
|
||||
LD = $(GCC_BIN)arm-none-eabi-gcc
|
||||
OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
|
||||
OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
|
||||
SIZE = $(GCC_BIN)arm-none-eabi-size
|
||||
|
||||
CPU = -mcpu=cortex-m0 -mthumb
|
||||
CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections
|
||||
CC_FLAGS += -MMD -MP
|
||||
CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
|
||||
|
||||
LD_FLAGS = -mcpu=cortex-m0 -mthumb -Wl,--gc-sections --specs=nano.specs
|
||||
LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
|
||||
LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
|
||||
|
||||
ifeq ($(DEBUG), 1)
|
||||
CC_FLAGS += -DDEBUG -O0
|
||||
else
|
||||
CC_FLAGS += -DNDEBUG -Os
|
||||
endif
|
||||
|
||||
all: $(PROJECT).bin $(PROJECT).hex size
|
||||
|
||||
clean:
|
||||
rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
|
||||
|
||||
.s.o:
|
||||
$(AS) $(CPU) -o $@ $<
|
||||
|
||||
.c.o:
|
||||
$(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $<
|
||||
|
||||
.cpp.o:
|
||||
$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $<
|
||||
|
||||
|
||||
$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
|
||||
$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
|
||||
@echo ""
|
||||
@echo "*****"
|
||||
@echo "***** You must modify vector checksum value in *.bin and *.hex files."
|
||||
@echo "*****"
|
||||
@echo ""
|
||||
|
||||
$(PROJECT).bin: $(PROJECT).elf
|
||||
@$(OBJCOPY) -O binary $< $@
|
||||
|
||||
$(PROJECT).hex: $(PROJECT).elf
|
||||
@$(OBJCOPY) -O ihex $< $@
|
||||
|
||||
$(PROJECT).lst: $(PROJECT).elf
|
||||
@$(OBJDUMP) -Sdh $< > $@
|
||||
|
||||
lst: $(PROJECT).lst
|
||||
|
||||
size:
|
||||
$(SIZE) $(PROJECT).elf
|
||||
|
||||
DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
|
||||
-include $(DEPS)
|
||||
|
||||
|
|
@ -38,6 +38,7 @@ class GccArm(Exporter):
|
|||
'LPC1114',
|
||||
'LPC11U35_401',
|
||||
'LPC11U35_501',
|
||||
'LPC11U37H_401',
|
||||
'STM32F407',
|
||||
'DISCO_F100RB',
|
||||
'DISCO_F051R8',
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@ class Uvision4(Exporter):
|
|||
'NRF51_DK',
|
||||
'NRF51_DONGLE',
|
||||
'BLE_SMURFS',
|
||||
'LPC11U37H_401',
|
||||
]
|
||||
|
||||
USING_MICROLIB = [
|
||||
|
|
@ -88,6 +89,7 @@ class Uvision4(Exporter):
|
|||
'LPC1549',
|
||||
'LPC11U35_501',
|
||||
'KL05Z',
|
||||
'LPC11U37H_401',
|
||||
]
|
||||
|
||||
FILE_TYPES = {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,181 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>mbed NXP LPC11U37H_401</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>1</RunSim>
|
||||
<RunTarget>0</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>0</CpuCode>
|
||||
<DllOpt>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDllName>DARMP1.DLL</SimDlgDllName>
|
||||
<SimDlgDllArguments>-pLPC11U14</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDllName>TARMP1.DLL</TargetDlgDllName>
|
||||
<TargetDlgDllArguments>-pLPC11U14</TargetDlgDllArguments>
|
||||
</DllOpt>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>14</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"MBED CMSIS-DAP" -UA000000001 -O206 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>src</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>8</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>1</TopLine>
|
||||
<CurrentLine>2</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>main.cpp</PathWithFileName>
|
||||
<FilenameWithoutPath>main.cpp</FilenameWithoutPath>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,419 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>mbed NXP LPC11U37H_401</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>LPC11U37/401</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<Cpu>IRAM(0x10000000-0x10001FFF) IRAM2(0x20004000-0x200047FF) IROM(0-0x1FFFF) CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile>"STARTUP\NXP\LPC11Uxx\startup_LPC11Uxx.s" ("NXP LPC11Uxx Startup Code")</StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000)</FlashDriverDll>
|
||||
<DeviceId>5738</DeviceId>
|
||||
<RegisterFile>LPC11Uxx.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>SFD\NXP\LPC11Uxx\LPC11Uxx.SFR</SFDFile>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>NXP\LPC11Uxx\</RegisterFilePath>
|
||||
<DBRegisterFilePath>NXP\LPC11Uxx\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>{{name}}</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>1</RunUserProg2>
|
||||
<UserProg1Name>$K\ARM\BIN\ELFDWT.EXE "!L"</UserProg1Name>
|
||||
<UserProg2Name>fromelf --bin -o {{name}}_LPC11U37H.bin build\{{name}}.axf</UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DARMP1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pLPC11U14</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TARMP1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pLPC11U37</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>14</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4105</DriverSelection>
|
||||
</Flash1>
|
||||
<Flash2>BIN\CMSIS_AGDI.dll</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M0"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x2000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x2000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20004000</StartAddress>
|
||||
<Size>0x800</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<VariousControls>
|
||||
<MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
|
||||
<Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x10000000</DataAddressRange>
|
||||
<ScatterFile>{{scatter_file}}</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>
|
||||
{% for file in object_files %}
|
||||
{{file}}
|
||||
{% endfor %}
|
||||
</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
{% for group,files in source_files %}
|
||||
<Group>
|
||||
<GroupName>{{group}}</GroupName>
|
||||
<Files>
|
||||
{% for file in files %}
|
||||
<File>
|
||||
<FileName>{{file.name}}</FileName>
|
||||
<FileType>{{file.type}}</FileType>
|
||||
<FilePath>{{file.path}}</FilePath>
|
||||
{%if file.type == "1" %}
|
||||
<FileOption>
|
||||
<FileArmAds>
|
||||
<Cads>
|
||||
<VariousControls>
|
||||
<MiscControls>--c99</MiscControls>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
{% endif %}
|
||||
</File>
|
||||
{% endfor %}
|
||||
</Files>
|
||||
</Group>
|
||||
{% endfor %}
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
|
|
@ -334,6 +334,15 @@ class LPC1800(LPCTarget):
|
|||
self.extra_labels = ['NXP', 'LPC43XX']
|
||||
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
|
||||
|
||||
class LPC11U37H_401(LPCTarget):
|
||||
def __init__(self):
|
||||
LPCTarget.__init__(self)
|
||||
self.core = "Cortex-M0"
|
||||
self.extra_labels = ['NXP', 'LPC11UXX']
|
||||
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CR"]
|
||||
self.default_toolchain = "uARM"
|
||||
self.supported_form_factors = ["ARDUINO"]
|
||||
|
||||
|
||||
### Freescale ###
|
||||
|
||||
|
|
@ -893,6 +902,7 @@ TARGETS = [
|
|||
LPC4330_M4(),
|
||||
LPC4330_M0(),
|
||||
LPC4337(),
|
||||
LPC11U37H_401(),
|
||||
|
||||
### Freescale ###
|
||||
KL05Z(),
|
||||
|
|
|
|||
Loading…
Reference in New Issue