mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_F091RC] adding exporter (gcc_arm, coide), enable rtos
- Adding exporter for CoIDE and GCC_ARM - Adding target to RTOS libpull/820/head
ohagendorf
parent
5ebdb92e78
commit
f5c3b18d75
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@ -0,0 +1,153 @@
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/* Linker script to configure memory regions. */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
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RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 32k - 0x0C0
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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* _estack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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KEEP(*(.isr_vector))
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} > FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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__etext = .;
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_sidata = .;
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.data : AT (__etext)
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{
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__data_start__ = .;
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_sdata = .;
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*(vtable)
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*(.data*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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_edata = .;
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} > RAM
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.bss :
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{
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. = ALIGN(4);
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__bss_start__ = .;
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_sbss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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_ebss = .;
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} > RAM
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.heap (COPY):
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{
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__end__ = .;
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end = __end__;
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*(.heap*)
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__HeapLimit = .;
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} > RAM
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (COPY):
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{
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*(.stack*)
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} > RAM
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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_estack = __StackTop;
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}
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@ -0,0 +1,311 @@
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/**
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******************************************************************************
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* @file startup_stm32f091xc.s
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @brief STM32F091xC devices vector table for Atollic TrueSTUDIO toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M0 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m0
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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//bl __libc_init_array
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/* Call the application's entry point.*/
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//bl main
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/**
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* Calling the crt0 'cold-start' entry point. There __libc_init_array is called
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* and when existing hardware_init_hook() and software_init_hook() before
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* starting main(). software_init_hook() is available and has to be called due
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* to initializsation when using rtos.
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*/
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bl _start
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M0. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word 0
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */
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.word RTC_IRQHandler /* RTC through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_CRS_IRQHandler /* RCC and CRS */
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.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
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.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
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.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
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.word TSC_IRQHandler /* TSC */
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.word DMA1_Ch1_IRQHandler /* DMA1 Channel 1 */
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.word DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler /* DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 */
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.word DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler /* DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 */
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.word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
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.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM6_DAC_IRQHandler /* TIM6 and DAC */
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.word TIM7_IRQHandler /* TIM7 */
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.word TIM14_IRQHandler /* TIM14 */
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.word TIM15_IRQHandler /* TIM15 */
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.word TIM16_IRQHandler /* TIM16 */
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.word TIM17_IRQHandler /* TIM17 */
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.word I2C1_IRQHandler /* I2C1 */
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.word I2C2_IRQHandler /* I2C2 */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word USART3_8_IRQHandler /* USART3, USART4, USART5, USART6, USART7, USART8 */
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.word CEC_CAN_IRQHandler /* CEC and CAN */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak PVD_VDDIO2_IRQHandler
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.thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
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.weak RTC_IRQHandler
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.thumb_set RTC_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_CRS_IRQHandler
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.thumb_set RCC_CRS_IRQHandler,Default_Handler
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.weak EXTI0_1_IRQHandler
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.thumb_set EXTI0_1_IRQHandler,Default_Handler
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.weak EXTI2_3_IRQHandler
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.thumb_set EXTI2_3_IRQHandler,Default_Handler
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.weak EXTI4_15_IRQHandler
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.thumb_set EXTI4_15_IRQHandler,Default_Handler
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.weak TSC_IRQHandler
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.thumb_set TSC_IRQHandler,Default_Handler
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.weak DMA1_Ch1_IRQHandler
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.thumb_set DMA1_Ch1_IRQHandler,Default_Handler
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.weak DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
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.thumb_set DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler,Default_Handler
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.weak DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
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.thumb_set DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler,Default_Handler
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.weak ADC1_COMP_IRQHandler
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.thumb_set ADC1_COMP_IRQHandler,Default_Handler
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.weak TIM1_BRK_UP_TRG_COM_IRQHandler
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.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler,Default_Handler
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.weak TIM3_IRQHandler
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.thumb_set TIM3_IRQHandler,Default_Handler
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.weak TIM6_DAC_IRQHandler
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.thumb_set TIM6_DAC_IRQHandler,Default_Handler
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.weak TIM7_IRQHandler
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.thumb_set TIM7_IRQHandler,Default_Handler
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.weak TIM14_IRQHandler
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.thumb_set TIM14_IRQHandler,Default_Handler
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.weak TIM15_IRQHandler
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.thumb_set TIM15_IRQHandler,Default_Handler
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.weak TIM16_IRQHandler
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.thumb_set TIM16_IRQHandler,Default_Handler
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.weak TIM17_IRQHandler
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.thumb_set TIM17_IRQHandler,Default_Handler
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.weak I2C1_IRQHandler
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.thumb_set I2C1_IRQHandler,Default_Handler
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.weak I2C2_IRQHandler
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.thumb_set I2C2_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak SPI2_IRQHandler
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.thumb_set SPI2_IRQHandler,Default_Handler
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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.weak USART2_IRQHandler
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.thumb_set USART2_IRQHandler,Default_Handler
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.weak USART3_8_IRQHandler
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.thumb_set USART3_8_IRQHandler,Default_Handler
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.weak CEC_CAN_IRQHandler
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.thumb_set CEC_CAN_IRQHandler,Default_Handler
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -292,6 +292,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
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#elif defined(TARGET_STM32F072RB)
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#define INITIAL_SP (0x20004000UL)
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#elif defined(TARGET_STM32F091RC)
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#define INITIAL_SP (0x20008000UL)
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#else
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#error "no target defined"
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@ -50,12 +50,13 @@
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// <i> Default: 6
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#ifndef OS_TASKCNT
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# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
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|| defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) \
|
||||
|| defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI)
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \
|
||||
|| defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI)
|
||||
# define OS_TASKCNT 14
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
|
||||
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \
|
||||
|| defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB)
|
||||
|| defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \
|
||||
|| defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC)
|
||||
# define OS_TASKCNT 6
|
||||
# else
|
||||
# error "no target defined"
|
||||
|
|
@ -65,12 +66,12 @@
|
|||
// <o>Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4>
|
||||
#ifndef OS_SCHEDULERSTKSIZE
|
||||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) \
|
||||
|| defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI)
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \
|
||||
|| defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI)
|
||||
# define OS_SCHEDULERSTKSIZE 256
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
|
||||
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \
|
||||
|| defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) defined(TARGET_STM32F072RB)
|
||||
|| defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC)
|
||||
# define OS_SCHEDULERSTKSIZE 128
|
||||
# elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8)
|
||||
# define OS_SCHEDULERSTKSIZE 112
|
||||
|
|
@ -121,7 +122,8 @@
|
|||
# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8)
|
||||
# define OS_CLOCK 72000000
|
||||
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) || defined(TARGET_STM32F072RB)
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) \
|
||||
|| defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC)
|
||||
# define OS_CLOCK 48000000
|
||||
|
||||
# elif defined(TARGET_LPC812)
|
||||
|
|
|
|||
|
|
@ -28,11 +28,11 @@ class CoIDE(Exporter):
|
|||
'LPC1768',
|
||||
'ARCH_PRO',
|
||||
'UBLOX_C027',
|
||||
'DISCO_F407VG',
|
||||
'NUCLEO_L053R8',
|
||||
'NUCLEO_L152RE',
|
||||
'NUCLEO_F030R8',
|
||||
'NUCLEO_F072RB',
|
||||
'NUCLEO_F091RC',
|
||||
'NUCLEO_F103RB',
|
||||
'NUCLEO_F302R8',
|
||||
'NUCLEO_F334R8',
|
||||
|
|
@ -41,10 +41,11 @@ class CoIDE(Exporter):
|
|||
'DISCO_L053C8',
|
||||
'DISCO_F051R8',
|
||||
'DISCO_F100RB',
|
||||
'DISCO_F429ZI',
|
||||
'DISCO_F334C8',
|
||||
'DISCO_F303VC',
|
||||
'DISCO_F334C8',
|
||||
'DISCO_F401VC',
|
||||
'DISCO_F407VG',
|
||||
'DISCO_F429ZI',
|
||||
'MTS_MDOT_F405RG',
|
||||
'MTS_MDOT_F411RE',
|
||||
]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,90 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<Project version="2G - 1.7.5" name="{{name}}">
|
||||
<Target name="{{name}}" isCurrent="1">
|
||||
<Device manufacturerId="9" manufacturerName="ST" chipId="847" chipName="STM32F091RC" boardId="" boardName=""/>
|
||||
<BuildOption>
|
||||
<Compile>
|
||||
<Option name="OptimizationLevel" value="4"/>
|
||||
<Option name="UseFPU" value="0"/>
|
||||
<Option name="UserEditCompiler" value="-fno-common; -fmessage-length=0; -Wall; -fno-strict-aliasing; -fno-rtti; -fno-exceptions; -ffunction-sections; -fdata-sections; -std=gnu++98"/>
|
||||
<Option name="FPU" value="1"/>
|
||||
<Option name="SupportCPlusplus" value="1"/>
|
||||
<Includepaths>
|
||||
{% for path in include_paths %} <Includepath path="{{path}}"/> {% endfor %}
|
||||
</Includepaths>
|
||||
<DefinedSymbols>
|
||||
{% for s in symbols %} <Define name="{{s}}"/> {% endfor %}
|
||||
</DefinedSymbols>
|
||||
</Compile>
|
||||
<Link useDefault="0">
|
||||
<Option name="DiscardUnusedSection" value="1"/>
|
||||
<Option name="UserEditLinkder" value=""/>
|
||||
<Option name="UseMemoryLayout" value="0"/>
|
||||
<Option name="LTO" value="0"/>
|
||||
<Option name="IsNewStartupCode" value="1"/>
|
||||
<Option name="Library" value="Not use C Library"/>
|
||||
<Option name="nostartfiles" value="0"/>
|
||||
<Option name="UserEditLinker" value="-Wl,--wrap,main; --specs=nano.specs; -u _printf_float; -u _scanf_float; {% for file in object_files %}
|
||||
${project.path}/{{file}}; {% endfor %} {% for p in library_paths %}-L${project.path}/{{p}}; {% endfor %}"/>
|
||||
<LinkedLibraries>
|
||||
{% for lib in libraries %}
|
||||
<Libset dir="" libs="{{lib}}"/>
|
||||
{% endfor %}
|
||||
<Libset dir="" libs="stdc++"/>
|
||||
<Libset dir="" libs="supc++"/>
|
||||
<Libset dir="" libs="m"/>
|
||||
<Libset dir="" libs="gcc"/>
|
||||
<Libset dir="" libs="c"/>
|
||||
<Libset dir="" libs="nosys"/>
|
||||
</LinkedLibraries>
|
||||
<MemoryAreas debugInFlashNotRAM="1">
|
||||
<Memory name="IROM1" type="ReadOnly" size="0x00040000" startValue="0x08000000"/>
|
||||
<Memory name="IRAM1" type="ReadWrite" size="0x00007F40" startValue="0x200000C0"/>
|
||||
<Memory name="IROM2" type="ReadOnly" size="" startValue=""/>
|
||||
<Memory name="IRAM2" type="ReadWrite" size="" startValue=""/>
|
||||
</MemoryAreas>
|
||||
<LocateLinkFile path="{{scatter_file}}" type="0"/>
|
||||
</Link>
|
||||
<Output>
|
||||
<Option name="OutputFileType" value="0"/>
|
||||
<Option name="Path" value="./"/>
|
||||
<Option name="Name" value="{{name}}"/>
|
||||
<Option name="HEX" value="1"/>
|
||||
<Option name="BIN" value="1"/>
|
||||
</Output>
|
||||
<User>
|
||||
<UserRun name="Run#1" type="Before" checked="0" value=""/>
|
||||
<UserRun name="Run#1" type="After" checked="0" value=""/>
|
||||
</User>
|
||||
</BuildOption>
|
||||
<DebugOption>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.adapter" value="ST-Link"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.debugMode" value="SWD"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.clockDiv" value="1M"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.corerunToMain" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.jlinkgdbserver" value=""/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.userDefineGDBScript" value=""/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.targetEndianess" value="0"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.jlinkResetMode" value="Type 0: Normal"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.resetMode" value="SYSRESETREQ"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.ifSemihost" value="0"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.ifCacheRom" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.ipAddress" value="127.0.0.1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.portNumber" value="2009"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.autoDownload" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.verify" value="1"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.downloadFuction" value="Erase Effected"/>
|
||||
<Option name="org.coocox.codebugger.gdbjtag.core.defaultAlgorithm" value="./stm32f09x_256.elf"/>
|
||||
</DebugOption>
|
||||
<ExcludeFile/>
|
||||
</Target>
|
||||
<Components path="./"/>
|
||||
<Files>
|
||||
{% for file in source_files %}
|
||||
<File name="sources/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
|
||||
{% endfor %}
|
||||
{% for file in header_files %}
|
||||
<File name="headers/{{file.path}}" path="{{file.path}}" type="{{file.type}}"/>
|
||||
{% endfor %}
|
||||
</Files>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
# This file was automagically generated by mbed.org. For more information,
|
||||
# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
|
||||
|
||||
GCC_BIN =
|
||||
PROJECT = {{name}}
|
||||
OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
|
||||
SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
|
||||
INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
|
||||
LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
|
||||
LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
|
||||
LINKER_SCRIPT = {{linker_script}}
|
||||
|
||||
###############################################################################
|
||||
AS = $(GCC_BIN)arm-none-eabi-as
|
||||
CC = $(GCC_BIN)arm-none-eabi-gcc
|
||||
CPP = $(GCC_BIN)arm-none-eabi-g++
|
||||
LD = $(GCC_BIN)arm-none-eabi-gcc
|
||||
OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
|
||||
OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
|
||||
SIZE = $(GCC_BIN)arm-none-eabi-size
|
||||
|
||||
CPU = -mcpu=cortex-m0 -mthumb
|
||||
CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections
|
||||
CC_FLAGS += -MMD -MP
|
||||
CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
|
||||
|
||||
LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main
|
||||
LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
|
||||
LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
|
||||
|
||||
ifeq ($(DEBUG), 1)
|
||||
CC_FLAGS += -DDEBUG -O0
|
||||
else
|
||||
CC_FLAGS += -DNDEBUG -Os
|
||||
endif
|
||||
|
||||
all: $(PROJECT).bin $(PROJECT).hex size
|
||||
|
||||
clean:
|
||||
rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
|
||||
|
||||
.s.o:
|
||||
$(AS) $(CPU) -o $@ $<
|
||||
|
||||
.c.o:
|
||||
$(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $<
|
||||
|
||||
.cpp.o:
|
||||
$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $<
|
||||
|
||||
|
||||
$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
|
||||
$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
|
||||
|
||||
$(PROJECT).bin: $(PROJECT).elf
|
||||
@$(OBJCOPY) -O binary $< $@
|
||||
|
||||
$(PROJECT).hex: $(PROJECT).elf
|
||||
@$(OBJCOPY) -O ihex $< $@
|
||||
|
||||
$(PROJECT).lst: $(PROJECT).elf
|
||||
@$(OBJDUMP) -Sdh $< > $@
|
||||
|
||||
lst: $(PROJECT).lst
|
||||
|
||||
size:
|
||||
$(SIZE) $(PROJECT).elf
|
||||
|
||||
DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
|
||||
-include $(DEPS)
|
||||
|
||||
|
|
@ -59,6 +59,7 @@ class GccArm(Exporter):
|
|||
'NUCLEO_F030R8',
|
||||
'NUCLEO_F070RB',
|
||||
'NUCLEO_F072RB',
|
||||
'NUCLEO_F091RC',
|
||||
'NUCLEO_F103RB',
|
||||
'NUCLEO_F302R8',
|
||||
'NUCLEO_F334R8',
|
||||
|
|
|
|||
|
|
@ -456,7 +456,7 @@ class NUCLEO_F091RC(Target):
|
|||
Target.__init__(self)
|
||||
self.core = "Cortex-M0"
|
||||
self.extra_labels = ['STM', 'STM32F0', 'STM32F091RC']
|
||||
self.supported_toolchains = ["ARM", "uARM", "IAR"]
|
||||
self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"]
|
||||
self.default_toolchain = "uARM"
|
||||
self.supported_form_factors = ["ARDUINO", "MORPHO"]
|
||||
self.detect_code = ["0731"]
|
||||
|
|
|
|||
|
|
@ -583,7 +583,7 @@ TESTS = [
|
|||
"duration": 15,
|
||||
"automated": True,
|
||||
"host_test": "wait_us_auto",
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_2", "description": "Mutex resource lock",
|
||||
|
|
@ -591,7 +591,7 @@ TESTS = [
|
|||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB],
|
||||
"duration": 20,
|
||||
"automated": True,
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_3", "description": "Semaphore resource lock",
|
||||
|
|
@ -599,28 +599,28 @@ TESTS = [
|
|||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB],
|
||||
"duration": 20,
|
||||
"automated": True,
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_4", "description": "Signals messaging",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "signals"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_5", "description": "Queue messaging",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "queue"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_6", "description": "Mail messaging",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "mail"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_7", "description": "Timer",
|
||||
|
|
@ -629,14 +629,14 @@ TESTS = [
|
|||
"duration": 15,
|
||||
"automated": True,
|
||||
"host_test": "wait_us_auto",
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_8", "description": "ISR (Queue)",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "isr"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB"],
|
||||
"mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_F072RB", "NUCLEO_F091RC"],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_9", "description": "SD File write-read",
|
||||
|
|
|
|||
Loading…
Reference in New Issue