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Add some terminal setting of Serial and modify attach sequence. 

Fix some bugs of Serial as below.
- TX/RX terminal of XBee(P7_4, P7_5) setting is reverse.
- P5_6 and P5_7 terminals can not be used.
- Tx interrupt will not occur at the right timing.
- There are no settings of WIFI Module terminals(P11_10,P11_11).
- There are no settings of Xbee Module terminals(P6_6,P6_7).
pull/784/head
Masao Hamanaka 2014-12-12 14:25:08 +09:00
parent c08208fe4f
commit 7417e1061d
1 changed files with 150 additions and 221 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

371
libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
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@ -31,32 +31,55 @@ typedef struct st_scif SCIF_TypeDef;
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 6
#define UART_NUM 8
#define IRQ_NUM 2
static void uart0_tx_irq(void);
static void uart1_tx_irq(void);
static void uart2_tx_irq(void);
static void uart3_tx_irq(void);
static void uart4_tx_irq(void);
static void uart5_tx_irq(void);
static void uart6_tx_irq(void);
static void uart7_tx_irq(void);
static void uart0_rx_irq(void);
static void uart1_rx_irq(void);
static void uart2_rx_irq(void);
static void uart3_rx_irq(void);
static void uart4_rx_irq(void);
static void uart5_rx_irq(void);
static void uart6_rx_irq(void);
static void uart7_rx_irq(void);
static const PinMap PinMap_UART_TX[] = {
{P6_3 , P_SCIF2, 7},
{P2_14, P_SCIF0, 6},
{P5_0 , P_SCIF4, 5},
{P5_3 , P_SCIF3, 5},
{P5_6 , P_SCIF6, 5},
{P2_5 , P_SCIF1, 6},
{P8_14, P_SCIF4, 7},
{P8_13, P_SCIF5, 5},
{P7_5 , P_SCIF7, 4},
{NC , NC , 0}
{P6_3 , P_SCIF2, 7},
{P2_14 , P_SCIF0, 6},
{P5_0 , P_SCIF4, 5},
{P5_3 , P_SCIF3, 5},
{P5_6 , P_SCIF6, 5},
{P2_5 , P_SCIF1, 6},
{P8_14 , P_SCIF4, 7},
{P8_13 , P_SCIF5, 5},
{P7_4 , P_SCIF7, 4},
{P11_10, P_SCIF5, 3},
{P6_6 , P_SCIF5, 5},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{P6_2 , P_SCIF2, 7},
{P2_15, P_SCIF0, 6},
{P5_1 , P_SCIF4, 5},
{P5_4 , P_SCIF3, 5},
{P5_7 , P_SCIF6, 5},
{P2_6 , P_SCIF1, 6},
{P8_15, P_SCIF4, 7},
{P8_11, P_SCIF5, 5},
{P7_4 , P_SCIF7, 4},
{NC , NC , 0}
{P6_2 , P_SCIF2, 7},
{P2_15 , P_SCIF0, 6},
{P5_1 , P_SCIF4, 5},
{P5_4 , P_SCIF3, 5},
{P5_7 , P_SCIF6, 5},
{P2_6 , P_SCIF1, 6},
{P8_15 , P_SCIF4, 7},
{P8_11 , P_SCIF5, 5},
{P7_5 , P_SCIF7, 4},
{P11_11, P_SCIF5, 3},
{P6_7 , P_SCIF5, 5},
{NC , NC , 0}
};
/* [TODO] impliment hardware Flow Control, interrupt
@ -85,6 +108,51 @@ struct serial_global_data_s {
static struct serial_global_data_s uart_data[UART_NUM];
static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
{SCIFRXI0_IRQn, SCIFTXI0_IRQn},
{SCIFRXI1_IRQn, SCIFTXI1_IRQn},
{SCIFRXI2_IRQn, SCIFTXI2_IRQn},
{SCIFRXI3_IRQn, SCIFTXI3_IRQn},
{SCIFRXI4_IRQn, SCIFTXI4_IRQn},
{SCIFRXI5_IRQn, SCIFTXI5_IRQn},
{SCIFRXI6_IRQn, SCIFTXI6_IRQn},
{SCIFRXI7_IRQn, SCIFTXI7_IRQn}
};
static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
{uart0_rx_irq, uart0_tx_irq},
{uart1_rx_irq, uart1_tx_irq},
{uart2_rx_irq, uart2_tx_irq},
{uart3_rx_irq, uart3_tx_irq},
{uart4_rx_irq, uart4_tx_irq},
{uart5_rx_irq, uart5_tx_irq},
{uart6_rx_irq, uart6_tx_irq},
{uart7_rx_irq, uart7_tx_irq}
};
static __IO uint16_t *SCSCR_MATCH[] = {
&SCSCR_0,
&SCSCR_1,
&SCSCR_2,
&SCSCR_3,
&SCSCR_4,
&SCSCR_5,
&SCSCR_6,
&SCSCR_7,
};
static __IO uint16_t *SCFSR_MATCH[] = {
&SCFSR_0,
&SCFSR_1,
&SCFSR_2,
&SCFSR_3,
&SCFSR_4,
&SCFSR_5,
&SCFSR_6,
&SCFSR_7,
};
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
@ -119,7 +187,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
obj->uart->SCFCR = 0x0006;
/* ---- Serial status register (SCFSR) setting ---- */
obj->uart->SCFSR &= 0xFF6Cu; /* ER,BRK,DR bit clear */
dummy = obj->uart->SCFSR;
obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
/* ---- Line status register (SCLSR) setting ---- */
/* ORER bit clear */
@ -221,104 +290,47 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
******************************************************************************/
static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
uint16_t dummy_read;
/* Clear TDFE */
switch (index) {
case 0:
dummy_read = SCFSR_0;
SCFSR_0 = (dummy_read & ~0x0060);
break;
case 1:
dummy_read = SCFSR_1;
SCFSR_1 = (dummy_read & ~0x0060);
break;
case 2:
dummy_read = SCFSR_2;
SCFSR_2 = (dummy_read & ~0x0060);
break;
case 3:
dummy_read = SCFSR_3;
SCFSR_3 = (dummy_read & ~0x0060);
break;
case 4:
dummy_read = SCFSR_4;
SCFSR_4 = (dummy_read & ~0x0060);
break;
case 5:
dummy_read = SCFSR_5;
SCFSR_5 = (dummy_read & ~0x0060);
break;
case 6:
dummy_read = SCFSR_6;
SCFSR_6 = (dummy_read & ~0x0060);
break;
case 7:
dummy_read = SCFSR_7;
SCFSR_7 = (dummy_read & ~0x0060);
break;
}
__IO uint16_t *dmy_rd_scscr;
__IO uint16_t *dmy_rd_scfsr;
dmy_rd_scscr = SCSCR_MATCH[index];
*dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
dmy_rd_scfsr = SCFSR_MATCH[index];
*dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE
irq_handler(uart_data[index].serial_irq_id, TxIrq);
GIC_EndInterrupt(irq_num);
}
static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
uint16_t dummy_read;
/* Clear RDF */
switch (index) {
case 0:
dummy_read = SCFSR_0;
SCFSR_0 = (dummy_read & ~0x0003);
break;
case 1:
dummy_read = SCFSR_1;
SCFSR_1 = (dummy_read & ~0x0003);
break;
case 2:
dummy_read = SCFSR_2;
SCFSR_2 = (dummy_read & ~0x0003);
break;
case 3:
dummy_read = SCFSR_3;
SCFSR_3 = (dummy_read & ~0x0003);
break;
case 4:
dummy_read = SCFSR_4;
SCFSR_4 = (dummy_read & ~0x0003);
break;
case 5:
dummy_read = SCFSR_5;
SCFSR_5 = (dummy_read & ~0x0003);
break;
case 6:
dummy_read = SCFSR_6;
SCFSR_6 = (dummy_read & ~0x0003);
break;
case 7:
dummy_read = SCFSR_7;
SCFSR_7 = (dummy_read & ~0x0003);
break;
}
__IO uint16_t *dmy_rd_scscr;
__IO uint16_t *dmy_rd_scfsr;
dmy_rd_scscr = SCSCR_MATCH[index];
*dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
dmy_rd_scfsr = SCFSR_MATCH[index];
*dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
irq_handler(uart_data[index].serial_irq_id, RxIrq);
GIC_EndInterrupt(irq_num);
}
/* TX handler */
void uart0_tx_irq() {uart_tx_irq(SCIFTXI0_IRQn, 0);}
void uart1_tx_irq() {uart_tx_irq(SCIFTXI1_IRQn, 1);}
void uart2_tx_irq() {uart_tx_irq(SCIFTXI2_IRQn, 2);}
void uart3_tx_irq() {uart_tx_irq(SCIFTXI3_IRQn, 3);}
void uart4_tx_irq() {uart_tx_irq(SCIFTXI4_IRQn, 4);}
void uart5_tx_irq() {uart_tx_irq(SCIFTXI5_IRQn, 5);}
void uart6_tx_irq() {uart_tx_irq(SCIFTXI6_IRQn, 6);}
void uart7_tx_irq() {uart_tx_irq(SCIFTXI7_IRQn, 7);}
static void uart0_tx_irq(void) {uart_tx_irq(SCIFTXI0_IRQn, 0);}
static void uart1_tx_irq(void) {uart_tx_irq(SCIFTXI1_IRQn, 1);}
static void uart2_tx_irq(void) {uart_tx_irq(SCIFTXI2_IRQn, 2);}
static void uart3_tx_irq(void) {uart_tx_irq(SCIFTXI3_IRQn, 3);}
static void uart4_tx_irq(void) {uart_tx_irq(SCIFTXI4_IRQn, 4);}
static void uart5_tx_irq(void) {uart_tx_irq(SCIFTXI5_IRQn, 5);}
static void uart6_tx_irq(void) {uart_tx_irq(SCIFTXI6_IRQn, 6);}
static void uart7_tx_irq(void) {uart_tx_irq(SCIFTXI7_IRQn, 7);}
/* RX handler */
void uart0_rx_irq() {uart_rx_irq(SCIFRXI0_IRQn, 0);}
void uart1_rx_irq() {uart_rx_irq(SCIFRXI1_IRQn, 1);}
void uart2_rx_irq() {uart_rx_irq(SCIFRXI2_IRQn, 2);}
void uart3_rx_irq() {uart_rx_irq(SCIFRXI3_IRQn, 3);}
void uart4_rx_irq() {uart_rx_irq(SCIFRXI4_IRQn, 4);}
void uart5_rx_irq() {uart_rx_irq(SCIFRXI5_IRQn, 5);}
void uart6_rx_irq() {uart_rx_irq(SCIFRXI6_IRQn, 6);}
void uart7_rx_irq() {uart_rx_irq(SCIFRXI7_IRQn, 7);}
static void uart0_rx_irq(void) {uart_rx_irq(SCIFRXI0_IRQn, 0);}
static void uart1_rx_irq(void) {uart_rx_irq(SCIFRXI1_IRQn, 1);}
static void uart2_rx_irq(void) {uart_rx_irq(SCIFRXI2_IRQn, 2);}
static void uart3_rx_irq(void) {uart_rx_irq(SCIFRXI3_IRQn, 3);}
static void uart4_rx_irq(void) {uart_rx_irq(SCIFRXI4_IRQn, 4);}
static void uart5_rx_irq(void) {uart_rx_irq(SCIFRXI5_IRQn, 5);}
static void uart6_rx_irq(void) {uart_rx_irq(SCIFRXI6_IRQn, 6);}
static void uart7_rx_irq(void) {uart_rx_irq(SCIFRXI7_IRQn, 7);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
@ -326,71 +338,20 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
switch (obj->index){
case 0:
InterruptHandlerRegister(SCIFTXI0_IRQn, (void (*)(uint32_t))uart0_tx_irq);
InterruptHandlerRegister(SCIFRXI0_IRQn, (void (*)(uint32_t))uart0_rx_irq);
GIC_SetPriority(SCIFTXI0_IRQn, 5);
GIC_SetPriority(SCIFRXI0_IRQn, 5);
GIC_EnableIRQ(SCIFTXI0_IRQn);
GIC_EnableIRQ(SCIFRXI0_IRQn);
break;
case 1:
InterruptHandlerRegister(SCIFTXI1_IRQn, (void (*)(uint32_t))uart1_tx_irq);
InterruptHandlerRegister(SCIFRXI1_IRQn, (void (*)(uint32_t))uart1_rx_irq);
GIC_SetPriority(SCIFTXI1_IRQn, 5);
GIC_SetPriority(SCIFRXI1_IRQn, 5);
GIC_EnableIRQ(SCIFTXI1_IRQn);
GIC_EnableIRQ(SCIFRXI1_IRQn);
break;
case 2:
InterruptHandlerRegister(SCIFTXI2_IRQn, (void (*)(uint32_t))uart2_tx_irq);
InterruptHandlerRegister(SCIFRXI2_IRQn, (void (*)(uint32_t))uart2_rx_irq);
GIC_SetPriority(SCIFTXI2_IRQn, 5);
GIC_SetPriority(SCIFRXI2_IRQn, 5);
GIC_EnableIRQ(SCIFTXI2_IRQn);
GIC_EnableIRQ(SCIFRXI2_IRQn);
break;
case 3:
InterruptHandlerRegister(SCIFTXI3_IRQn, (void (*)(uint32_t))uart3_tx_irq);
InterruptHandlerRegister(SCIFRXI3_IRQn, (void (*)(uint32_t))uart3_rx_irq);
GIC_SetPriority(SCIFTXI3_IRQn, 5);
GIC_SetPriority(SCIFRXI3_IRQn, 5);
GIC_EnableIRQ(SCIFTXI3_IRQn);
GIC_EnableIRQ(SCIFRXI3_IRQn);
break;
case 4:
InterruptHandlerRegister(SCIFTXI4_IRQn, (void (*)(uint32_t))uart4_tx_irq);
InterruptHandlerRegister(SCIFRXI4_IRQn, (void (*)(uint32_t))uart4_rx_irq);
GIC_SetPriority(SCIFTXI4_IRQn, 5);
GIC_SetPriority(SCIFRXI4_IRQn, 5);
GIC_EnableIRQ(SCIFTXI4_IRQn);
GIC_EnableIRQ(SCIFRXI4_IRQn);
break;
case 5:
InterruptHandlerRegister(SCIFTXI5_IRQn, (void (*)(uint32_t))uart5_tx_irq);
InterruptHandlerRegister(SCIFRXI5_IRQn, (void (*)(uint32_t))uart5_rx_irq);
GIC_SetPriority(SCIFTXI5_IRQn, 5);
GIC_SetPriority(SCIFRXI5_IRQn, 5);
GIC_EnableIRQ(SCIFTXI5_IRQn);
GIC_EnableIRQ(SCIFRXI5_IRQn);
break;
case 6:
InterruptHandlerRegister(SCIFTXI6_IRQn, (void (*)(uint32_t))uart6_tx_irq);
InterruptHandlerRegister(SCIFRXI6_IRQn, (void (*)(uint32_t))uart6_rx_irq);
GIC_SetPriority(SCIFTXI6_IRQn, 5);
GIC_SetPriority(SCIFRXI6_IRQn, 5);
GIC_EnableIRQ(SCIFTXI6_IRQn);
GIC_EnableIRQ(SCIFRXI6_IRQn);
break;
case 7:
InterruptHandlerRegister(SCIFTXI7_IRQn, (void (*)(uint32_t))uart7_tx_irq);
InterruptHandlerRegister(SCIFRXI7_IRQn, (void (*)(uint32_t))uart7_rx_irq);
GIC_SetPriority(SCIFTXI7_IRQn, 5);
GIC_SetPriority(SCIFRXI7_IRQn, 5);
GIC_EnableIRQ(SCIFTXI7_IRQn);
GIC_EnableIRQ(SCIFRXI7_IRQn);
break;
IRQn_Type IRQn;
IRQHandler handler;
IRQn = irq_set_tbl[obj->index][irq];
handler = hander_set_tbl[obj->index][irq];
if ((obj->index >= 0) && (obj->index <= 7)) {
if (enable) {
InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
GIC_SetPriority(IRQn, 5);
GIC_EnableIRQ(IRQn);
} else {
GIC_DisableIRQ(IRQn);
}
}
}
@ -409,7 +370,13 @@ static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
if (obj->uart->SCFSR & 0x93) { obj->uart->SCFSR = ~0x93;}
uint16_t dummy_read;
if (obj->uart->SCFSR & 0x93) {
dummy_read = obj->uart->SCFSR;
obj->uart->SCFSR = (dummy_read & ~0x93);
}
obj->uart->SCSCR |= 0x0040; // Set RIE
while (!serial_readable(obj));
int data = obj->uart->SCFRDR & 0xff;
/* Clear DR,RDF */
@ -418,9 +385,13 @@ int serial_getc(serial_t *obj) {
}
void serial_putc(serial_t *obj, int c) {
uint16_t dummy_read;
obj->uart->SCSCR |= 0x0080; // Set TIE
while (!serial_writable(obj));
obj->uart->SCFTDR = c;
obj->uart->SCFSR &= 0xff9f; // Clear TEND/TDFE
dummy_read = obj->uart->SCFSR;
obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
uart_data[obj->index].count++;
}
@ -451,47 +422,5 @@ void serial_break_clear(serial_t *obj) {
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
serial_flow_irq_set(obj, 0);
// Only UART1 has hardware flow control on LPC176x
/*LPC_UART1_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)LPC_UART1 ? LPC_UART1 : NULL;
int index = obj->index;
// First, disable flow control completely
if (uart1)
uart1->MCR = uart1->MCR & ~UART_MCR_FLOWCTRL_MASK;
uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
serial_flow_irq_set(obj, 0);
if (FlowControlNone == type)
return;
// Check type(s) of flow control to use
UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
if (((FlowControlCTS == type) || (FlowControlRTSCTS == type)) && (NC != txflow)) {
// Can this be enabled in hardware?
if ((UART_1 == uart_cts) && (NULL != uart1)) {
// Enable auto-CTS mode
uart1->MCR |= UART_MCR_CTSEN_MASK;
pinmap_pinout(txflow, PinMap_UART_CTS);
} else {
// Can't enable in hardware, use software emulation
gpio_init_in(&uart_data[index].sw_cts, txflow);
}
}
if (((FlowControlRTS == type) || (FlowControlRTSCTS == type)) && (NC != rxflow)) {
// Enable FIFOs, trigger level of 1 char on RX FIFO
obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
| 1 << 1 // Rx Fifo Reset
| 1 << 2 // Tx Fifo Reset
| 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
// Can this be enabled in hardware?
if ((UART_1 == uart_rts) && (NULL != uart1)) {
// Enable auto-RTS mode
uart1->MCR |= UART_MCR_RTSEN_MASK;
pinmap_pinout(rxflow, PinMap_UART_RTS);
} else { // can't enable in hardware, use software emulation
gpio_init_out_ex(&uart_data[index].sw_rts, rxflow, 0);
// Enable RX interrupt
serial_flow_irq_set(obj, 1);
}
}*/
}