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fix HAL_NULL, add more GPIO_CLK macros

pull/803/head
mazgch 2014-12-18 16:11:40 +01:00
parent 67fbbf0b63
commit 992afded5c
5 changed files with 30 additions and 26 deletions
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32
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c
View File

@ -166,7 +166,7 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
{
/* Check the CRYP handle allocation */
if(hcryp == NULL)
if(hcryp == HAL_NULL)
{
return HAL_ERROR;
}
@ -210,7 +210,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
{
/* Check the CRYP handle allocation */
if(hcryp == NULL)
if(hcryp == HAL_NULL)
{
return HAL_ERROR;
}
@ -3254,59 +3254,59 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
{
case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_TDESECB_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_TDESECB_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_DESECB_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_DESECB_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_DESCBC_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_DESCBC_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_AESECB_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_AESECB_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_AESCBC_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_AESCBC_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_AESCTR_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYP_AESCTR_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
default:

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c
View File

@ -2646,19 +2646,19 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
{
case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);
HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL);
break;
default:

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c
View File

@ -155,7 +155,7 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
/* Check the hash handle allocation */
if(hhash == NULL)
if(hhash == HAL_NULL)
{
return HAL_ERROR;
}
@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
{
/* Check the HASH handle allocation */
if(hhash == NULL)
if(hhash == HAL_NULL)
{
return HAL_ERROR;
}
@ -898,11 +898,11 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
switch(HASH->CR & HASH_CR_ALGO)
{
case HASH_AlgoSelection_MD5:
HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
HAL_HASH_MD5_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
break;
case HASH_AlgoSelection_SHA1:
HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
HAL_HASH_SHA1_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
break;
default:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c
View File

@ -1014,11 +1014,11 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
{
case HASH_AlgoSelection_SHA224:
HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);
HAL_HASHEx_SHA224_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
break;
case HASH_AlgoSelection_SHA256:
HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);
HAL_HASHEx_SHA256_Start_IT(hhash, HAL_NULL, 0, HAL_NULL);
break;
default:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h
View File

@ -530,6 +530,8 @@ typedef struct
#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
#define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
@ -542,6 +544,8 @@ typedef struct
#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))