mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_F0] Align registers and system files with latest CMSIS files
Same as in new NUCLEO_F070RB targetpull/806/head
bcostm
parent
d9eb8b71d5
commit
03f49ea8ef
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f030x8.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @version V2.2.0
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* @date 05-December-2014
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* @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -371,24 +371,15 @@ typedef struct
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typedef struct
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{
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__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
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uint16_t RESERVED0; /*!< Reserved, 0x02 */
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__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
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uint16_t RESERVED1; /*!< Reserved, 0x06 */
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__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
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uint16_t RESERVED2; /*!< Reserved, 0x0A */
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__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
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uint16_t RESERVED3; /*!< Reserved, 0x0E */
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__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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uint16_t RESERVED4; /*!< Reserved, 0x12 */
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__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
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uint16_t RESERVED5; /*!< Reserved, 0x16 */
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__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
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uint16_t RESERVED6; /*!< Reserved, 0x1A */
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__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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uint16_t RESERVED7; /*!< Reserved, 0x1E */
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__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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uint16_t RESERVED8; /*!< Reserved, 0x22 */
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__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
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__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
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__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
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__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
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__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
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__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
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__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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}SPI_TypeDef;
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/**
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@ -2951,13 +2942,15 @@ typedef struct
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((INSTANCE) == DMA1_Channel5))
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/****************************** GPIO Instances ********************************/
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#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB) || \
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((INSTANCE) == GPIOC) || \
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((INSTANCE) == GPIOD) || \
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((INSTANCE) == GPIOF))
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#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB) || \
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((INSTANCE) == GPIOC) || \
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((INSTANCE) == GPIOD) || \
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((INSTANCE) == GPIOF))
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#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB))
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/****************************** GPIO Lock Instances ****************************/
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#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB))
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f0xx.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @version V2.2.0
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* @date 05-December-2014
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* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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@ -70,10 +70,10 @@
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#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
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!defined (STM32F031x6) && !defined (STM32F038xx) && \
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!defined (STM32F042x6) && !defined (STM32F048xx) && \
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!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
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!defined (STM32F051x8) && !defined (STM32F058xx) && \
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!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
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!defined (STM32F091xC) && !defined (STM32F098xx)
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!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
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!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
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/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
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#define STM32F030x8 /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
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/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
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@ -82,9 +82,12 @@
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/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
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/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
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/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
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/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
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/* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
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/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
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/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
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/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
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/* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
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/* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
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/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
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#endif
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@ -102,10 +105,10 @@
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V2.1.0
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* @brief CMSIS Device version number V2.2.0
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*/
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#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
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#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
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@ -137,6 +140,10 @@
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#include "stm32f051x8.h"
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#elif defined(STM32F058xx)
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#include "stm32f058xx.h"
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#elif defined(STM32F070x6)
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#include "stm32f070x6.h"
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#elif defined(STM32F070xB)
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#include "stm32f070xb.h"
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#elif defined(STM32F071xB)
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#include "stm32f071xb.h"
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#elif defined(STM32F072xB)
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@ -146,7 +153,9 @@
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#elif defined(STM32F091xC)
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#include "stm32f091xc.h"
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#elif defined(STM32F098xx)
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#include "stm32f098xx.h"
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#include "stm32f098xx.h"
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#elif defined(STM32F030xC)
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#include "stm32f030xc.h"
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#else
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#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
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#endif
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file system_stm32f0xx.c
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @version V2.2.0
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* @date 05-December-2014
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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*
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* 1. This file provides two functions and one global variable to be called from
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@ -135,6 +135,7 @@
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updated automatically.
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*/
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uint32_t SystemCoreClock = 48000000;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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@ -191,15 +192,31 @@ void SystemInit(void)
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/* Reset PREDIV[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
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#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
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/* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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#if defined (STM32F072xB) || defined (STM32F078xB)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
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#elif defined (STM32F071xB)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
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#elif defined (STM32F091xC) || defined (STM32F098xx)
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/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
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#else
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/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
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#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
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/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
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#elif defined (STM32F051x8) || defined (STM32F058xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
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#elif defined (STM32F042x6) || defined (STM32F048xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
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#elif defined (STM32F070x6) || defined (STM32F070xB)
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/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
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/* Set default USB clock to PLLCLK, since there is no HSI48 */
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RCC->CFGR3 |= (uint32_t)0x00000080;
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#else
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#warning "No target selected"
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#endif
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/* Reset HSI14 bit */
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@ -288,13 +305,17 @@ void SystemCoreClockUpdate (void)
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#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
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else
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{
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#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
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#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
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defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
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defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
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/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
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SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
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#else
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/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
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#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
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STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
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STM32F091xC || STM32F098xx || STM32F030xC */
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}
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break;
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default: /* HSI used as system clock */
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file system_stm32f0xx.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @version V2.2.0
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* @date 05-December-2014
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* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
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******************************************************************************
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* @attention
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f072xb.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @version V2.2.0
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* @date 05-December-2014
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* @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -506,24 +506,15 @@ typedef struct
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typedef struct
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{
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__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
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uint16_t RESERVED0; /*!< Reserved, 0x02 */
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__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
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uint16_t RESERVED1; /*!< Reserved, 0x06 */
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__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
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uint16_t RESERVED2; /*!< Reserved, 0x0A */
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__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
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uint16_t RESERVED3; /*!< Reserved, 0x0E */
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__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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uint16_t RESERVED4; /*!< Reserved, 0x12 */
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__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
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uint16_t RESERVED5; /*!< Reserved, 0x16 */
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__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
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uint16_t RESERVED6; /*!< Reserved, 0x1A */
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__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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uint16_t RESERVED7; /*!< Reserved, 0x1E */
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__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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uint16_t RESERVED8; /*!< Reserved, 0x22 */
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__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
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__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
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__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
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__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
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__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
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__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
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__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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}SPI_TypeDef;
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/**
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@ -5237,14 +5228,19 @@ typedef struct
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((INSTANCE) == DMA1_Channel7))
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/****************************** GPIO Instances ********************************/
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#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB) || \
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((INSTANCE) == GPIOC) || \
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((INSTANCE) == GPIOD) || \
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((INSTANCE) == GPIOE) || \
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((INSTANCE) == GPIOF))
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#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB) || \
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((INSTANCE) == GPIOC) || \
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((INSTANCE) == GPIOD) || \
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((INSTANCE) == GPIOE) || \
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((INSTANCE) == GPIOF))
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#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB) || \
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((INSTANCE) == GPIOC) || \
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((INSTANCE) == GPIOD) || \
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((INSTANCE) == GPIOE))
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/****************************** GPIO Lock Instances ****************************/
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#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
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((INSTANCE) == GPIOB))
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f0xx.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 03-Oct-2014
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* @version V2.2.0
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* @date 05-December-2014
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* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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@ -70,10 +70,10 @@
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#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
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!defined (STM32F031x6) && !defined (STM32F038xx) && \
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!defined (STM32F042x6) && !defined (STM32F048xx) && \
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!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
|
||||
!defined (STM32F051x8) && !defined (STM32F058xx) && \
|
||||
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
|
||||
!defined (STM32F091xC) && !defined (STM32F098xx)
|
||||
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
|
||||
!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
|
||||
/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||
/* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
|
||||
/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||
|
|
@ -82,9 +82,12 @@
|
|||
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
|
||||
/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
|
||||
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
|
||||
/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||
/* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||
/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||
#define STM32F072xB /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||
/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
|
||||
/* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
|
||||
/* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
|
||||
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
|
||||
#endif
|
||||
|
|
@ -102,10 +105,10 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.1.0
|
||||
* @brief CMSIS Device version number V2.2.0
|
||||
*/
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|
|
@ -137,6 +140,10 @@
|
|||
#include "stm32f051x8.h"
|
||||
#elif defined(STM32F058xx)
|
||||
#include "stm32f058xx.h"
|
||||
#elif defined(STM32F070x6)
|
||||
#include "stm32f070x6.h"
|
||||
#elif defined(STM32F070xB)
|
||||
#include "stm32f070xb.h"
|
||||
#elif defined(STM32F071xB)
|
||||
#include "stm32f071xb.h"
|
||||
#elif defined(STM32F072xB)
|
||||
|
|
@ -146,7 +153,9 @@
|
|||
#elif defined(STM32F091xC)
|
||||
#include "stm32f091xc.h"
|
||||
#elif defined(STM32F098xx)
|
||||
#include "stm32f098xx.h"
|
||||
#include "stm32f098xx.h"
|
||||
#elif defined(STM32F030xC)
|
||||
#include "stm32f030xc.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f0xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 03-Oct-2014
|
||||
* @version V2.2.0
|
||||
* @date 05-December-2014
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
|
|
@ -136,6 +136,7 @@
|
|||
updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 48000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
|
|
@ -194,15 +195,31 @@ void SystemInit(void)
|
|||
/* Reset PREDIV[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
|
||||
/* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
#if defined (STM32F072xB) || defined (STM32F078xB)
|
||||
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
|
||||
#elif defined (STM32F071xB)
|
||||
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
|
||||
#elif defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
|
||||
#else
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
|
||||
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
|
||||
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
|
||||
#elif defined (STM32F051x8) || defined (STM32F058xx)
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
|
||||
#elif defined (STM32F042x6) || defined (STM32F048xx)
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
|
||||
#elif defined (STM32F070x6) || defined (STM32F070xB)
|
||||
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
|
||||
/* Set default USB clock to PLLCLK, since there is no HSI48 */
|
||||
RCC->CFGR3 |= (uint32_t)0x00000080;
|
||||
#else
|
||||
#warning "No target selected"
|
||||
#endif
|
||||
|
||||
/* Reset HSI14 bit */
|
||||
|
|
@ -297,13 +314,17 @@ void SystemCoreClockUpdate (void)
|
|||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||
else
|
||||
{
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
|
||||
defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
|
||||
defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
|
||||
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
|
||||
#else
|
||||
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
|
||||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
|
||||
STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 03-Oct-2014
|
||||
* @version V2.2.0
|
||||
* @date 05-December-2014
|
||||
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f091xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 03-Oct-2014
|
||||
* @version V2.2.0
|
||||
* @date 05-December-2014
|
||||
* @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -325,8 +325,8 @@ typedef struct
|
|||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4*/
|
||||
__IO uint32_t RMPCR; /*!< Remap control register, Address offset: 0xA8 */
|
||||
uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */
|
||||
__IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */
|
||||
}DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -510,24 +510,15 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
uint16_t RESERVED0; /*!< Reserved, 0x02 */
|
||||
__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
uint16_t RESERVED1; /*!< Reserved, 0x06 */
|
||||
__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
uint16_t RESERVED2; /*!< Reserved, 0x0A */
|
||||
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
uint16_t RESERVED3; /*!< Reserved, 0x0E */
|
||||
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
uint16_t RESERVED4; /*!< Reserved, 0x12 */
|
||||
__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
uint16_t RESERVED5; /*!< Reserved, 0x16 */
|
||||
__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
uint16_t RESERVED6; /*!< Reserved, 0x1A */
|
||||
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
uint16_t RESERVED7; /*!< Reserved, 0x1E */
|
||||
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
uint16_t RESERVED8; /*!< Reserved, 0x22 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
}SPI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -2600,160 +2591,160 @@ typedef struct
|
|||
/****************** Bit definition for DMA_CMAR register ********************/
|
||||
#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
||||
|
||||
/****************** Bit definition for DMA_RMPCR1 register ********************/
|
||||
#define DMA_RMPCR1_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA1 */
|
||||
#define DMA_RMPCR1_CH1_ADC ((uint32_t)0x00000001) /*!< Remap ADC on DMA1 Channel 1*/
|
||||
#define DMA_RMPCR1_CH1_TIM17_CH1 ((uint32_t)0x00000007) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_TIM17_UP ((uint32_t)0x00000007) /*!< Remap TIM17 up on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART1_RX ((uint32_t)0x00000008) /*!< Remap USART1 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART2_RX ((uint32_t)0x00000009) /*!< Remap USART2 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART3_RX ((uint32_t)0x0000000A) /*!< Remap USART3 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART4_RX ((uint32_t)0x0000000B) /*!< Remap USART4 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART5_RX ((uint32_t)0x0000000C) /*!< Remap USART5 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART6_RX ((uint32_t)0x0000000D) /*!< Remap USART6 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART7_RX ((uint32_t)0x0000000E) /*!< Remap USART7 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH1_USART8_RX ((uint32_t)0x0000000F) /*!< Remap USART8 Rx on DMA1 channel 1 */
|
||||
#define DMA_RMPCR1_CH2_ADC ((uint32_t)0x00000010) /*!< Remap ADC on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_I2C1_TX ((uint32_t)0x00000020) /*!< Remap I2C1 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_SPI1_RX ((uint32_t)0x00000030) /*!< Remap SPI1 Rx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_TIM1_CH1 ((uint32_t)0x00000040) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_TIM17_CH1 ((uint32_t)0x00000070) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_TIM17_UP ((uint32_t)0x00000070) /*!< Remap TIM17 up on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART1_TX ((uint32_t)0x00000080) /*!< Remap USART1 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART2_TX ((uint32_t)0x00000090) /*!< Remap USART2 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART3_TX ((uint32_t)0x000000A0) /*!< Remap USART3 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART4_TX ((uint32_t)0x000000B0) /*!< Remap USART4 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART5_TX ((uint32_t)0x000000C0) /*!< Remap USART5 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART6_TX ((uint32_t)0x000000D0) /*!< Remap USART6 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART7_TX ((uint32_t)0x000000E0) /*!< Remap USART7 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH2_USART8_TX ((uint32_t)0x000000F0) /*!< Remap USART8 Tx on DMA1 channel 2 */
|
||||
#define DMA_RMPCR1_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC Channel 1on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_I2C1_RX ((uint32_t)0x00000200) /*!< Remap I2C1 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_SPI1_TX ((uint32_t)0x00000300) /*!< Remap SPI1 Tx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_TIM1_CH2 ((uint32_t)0x00000400) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_TIM2_CH2 ((uint32_t)0x00000500) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_TIM16_CH1 ((uint32_t)0x00000700) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_TIM16_UP ((uint32_t)0x00000700) /*!< Remap TIM16 up on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA1 channel 3 */
|
||||
#define DMA_RMPCR1_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_I2C2_TX ((uint32_t)0x00002000) /*!< Remap I2C2 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_SPI2_RX ((uint32_t)0x00003000) /*!< Remap SPI2 Rx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_TIM2_CH4 ((uint32_t)0x00005000) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_TIM3_CH1 ((uint32_t)0x00006000) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_TIM3_TRIG ((uint32_t)0x00006000) /*!< Remap TIM3 Trig on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_TIM16_CH1 ((uint32_t)0x00007000) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_TIM16_UP ((uint32_t)0x00007000) /*!< Remap TIM16 up on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA1 channel 4 */
|
||||
#define DMA_RMPCR1_CH5_I2C2_RX ((uint32_t)0x00020000) /*!< Remap I2C2 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_SPI2_TX ((uint32_t)0x00030000) /*!< Remap SPI1 Tx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_TIM1_CH3 ((uint32_t)0x00040000) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART1_RX ((uint32_t)0x00080000) /*!< Remap USART1 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART2_RX ((uint32_t)0x00090000) /*!< Remap USART2 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART3_RX ((uint32_t)0x000A0000) /*!< Remap USART3 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART4_RX ((uint32_t)0x000B0000) /*!< Remap USART4 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART5_RX ((uint32_t)0x000C0000) /*!< Remap USART5 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART6_RX ((uint32_t)0x000D0000) /*!< Remap USART6 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART7_RX ((uint32_t)0x000E0000) /*!< Remap USART7 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH5_USART8_RX ((uint32_t)0x000F0000) /*!< Remap USART8 Rx on DMA1 channel 5 */
|
||||
#define DMA_RMPCR1_CH6_I2C1_TX ((uint32_t)0x00200000) /*!< Remap I2C1 Tx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_SPI2_RX ((uint32_t)0x00300000) /*!< Remap SPI2 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_TIM1_CH1 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_TIM1_CH2 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_TIM1_CH3 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_TIM3_CH1 ((uint32_t)0x00600000) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_TIM3_TRIG ((uint32_t)0x00600000) /*!< Remap TIM3 Trig on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_TIM16_CH1 ((uint32_t)0x00700000) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_TIM16_UP ((uint32_t)0x00700000) /*!< Remap TIM16 up on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART1_RX ((uint32_t)0x00800000) /*!< Remap USART1 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART2_RX ((uint32_t)0x00900000) /*!< Remap USART2 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART3_RX ((uint32_t)0x00A00000) /*!< Remap USART3 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART4_RX ((uint32_t)0x00B00000) /*!< Remap USART4 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART5_RX ((uint32_t)0x00C00000) /*!< Remap USART5 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART6_RX ((uint32_t)0x00D00000) /*!< Remap USART6 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART7_RX ((uint32_t)0x00E00000) /*!< Remap USART7 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH6_USART8_RX ((uint32_t)0x00F00000) /*!< Remap USART8 Rx on DMA1 channel 6 */
|
||||
#define DMA_RMPCR1_CH7_I2C1_RX ((uint32_t)0x02000000) /*!< Remap I2C1 Rx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_SPI2_TX ((uint32_t)0x03000000) /*!< Remap SPI2 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_TIM2_CH2 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_TIM2_CH4 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_TIM17_CH1 ((uint32_t)0x07000000) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_TIM17_UP ((uint32_t)0x07000000) /*!< Remap TIM17 up on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART1_TX ((uint32_t)0x08000000) /*!< Remap USART1 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART2_TX ((uint32_t)0x09000000) /*!< Remap USART2 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART3_TX ((uint32_t)0x0A000000) /*!< Remap USART3 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART4_TX ((uint32_t)0x0B000000) /*!< Remap USART4 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART5_TX ((uint32_t)0x0C000000) /*!< Remap USART5 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART6_TX ((uint32_t)0x0D000000) /*!< Remap USART6 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART7_TX ((uint32_t)0x0E000000) /*!< Remap USART7 Tx on DMA1 channel 7 */
|
||||
#define DMA_RMPCR1_CH7_USART8_TX ((uint32_t)0x0F000000) /*!< Remap USART8 Tx on DMA1 channel 7 */
|
||||
/****************** Bit definition for DMA1_CSELR register ********************/
|
||||
#define DMA1_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA1 */
|
||||
#define DMA1_CSELR_CH1_ADC ((uint32_t)0x00000001) /*!< Remap ADC on DMA1 Channel 1*/
|
||||
#define DMA1_CSELR_CH1_TIM17_CH1 ((uint32_t)0x00000007) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_TIM17_UP ((uint32_t)0x00000007) /*!< Remap TIM17 up on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART1_RX ((uint32_t)0x00000008) /*!< Remap USART1 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART2_RX ((uint32_t)0x00000009) /*!< Remap USART2 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART3_RX ((uint32_t)0x0000000A) /*!< Remap USART3 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART4_RX ((uint32_t)0x0000000B) /*!< Remap USART4 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART5_RX ((uint32_t)0x0000000C) /*!< Remap USART5 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART6_RX ((uint32_t)0x0000000D) /*!< Remap USART6 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART7_RX ((uint32_t)0x0000000E) /*!< Remap USART7 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH1_USART8_RX ((uint32_t)0x0000000F) /*!< Remap USART8 Rx on DMA1 channel 1 */
|
||||
#define DMA1_CSELR_CH2_ADC ((uint32_t)0x00000010) /*!< Remap ADC on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_I2C1_TX ((uint32_t)0x00000020) /*!< Remap I2C1 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_SPI1_RX ((uint32_t)0x00000030) /*!< Remap SPI1 Rx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_TIM1_CH1 ((uint32_t)0x00000040) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_TIM17_CH1 ((uint32_t)0x00000070) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_TIM17_UP ((uint32_t)0x00000070) /*!< Remap TIM17 up on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART1_TX ((uint32_t)0x00000080) /*!< Remap USART1 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART2_TX ((uint32_t)0x00000090) /*!< Remap USART2 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART3_TX ((uint32_t)0x000000A0) /*!< Remap USART3 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART4_TX ((uint32_t)0x000000B0) /*!< Remap USART4 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART5_TX ((uint32_t)0x000000C0) /*!< Remap USART5 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART6_TX ((uint32_t)0x000000D0) /*!< Remap USART6 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART7_TX ((uint32_t)0x000000E0) /*!< Remap USART7 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH2_USART8_TX ((uint32_t)0x000000F0) /*!< Remap USART8 Tx on DMA1 channel 2 */
|
||||
#define DMA1_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC Channel 1on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_I2C1_RX ((uint32_t)0x00000200) /*!< Remap I2C1 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_SPI1_TX ((uint32_t)0x00000300) /*!< Remap SPI1 Tx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_TIM1_CH2 ((uint32_t)0x00000400) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_TIM2_CH2 ((uint32_t)0x00000500) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_TIM16_CH1 ((uint32_t)0x00000700) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_TIM16_UP ((uint32_t)0x00000700) /*!< Remap TIM16 up on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA1 channel 3 */
|
||||
#define DMA1_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_I2C2_TX ((uint32_t)0x00002000) /*!< Remap I2C2 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_SPI2_RX ((uint32_t)0x00003000) /*!< Remap SPI2 Rx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_TIM2_CH4 ((uint32_t)0x00005000) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_TIM3_CH1 ((uint32_t)0x00006000) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_TIM3_TRIG ((uint32_t)0x00006000) /*!< Remap TIM3 Trig on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_TIM16_CH1 ((uint32_t)0x00007000) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_TIM16_UP ((uint32_t)0x00007000) /*!< Remap TIM16 up on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA1 channel 4 */
|
||||
#define DMA1_CSELR_CH5_I2C2_RX ((uint32_t)0x00020000) /*!< Remap I2C2 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_SPI2_TX ((uint32_t)0x00030000) /*!< Remap SPI1 Tx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_TIM1_CH3 ((uint32_t)0x00040000) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART1_RX ((uint32_t)0x00080000) /*!< Remap USART1 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART2_RX ((uint32_t)0x00090000) /*!< Remap USART2 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART3_RX ((uint32_t)0x000A0000) /*!< Remap USART3 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART4_RX ((uint32_t)0x000B0000) /*!< Remap USART4 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART5_RX ((uint32_t)0x000C0000) /*!< Remap USART5 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART6_RX ((uint32_t)0x000D0000) /*!< Remap USART6 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART7_RX ((uint32_t)0x000E0000) /*!< Remap USART7 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH5_USART8_RX ((uint32_t)0x000F0000) /*!< Remap USART8 Rx on DMA1 channel 5 */
|
||||
#define DMA1_CSELR_CH6_I2C1_TX ((uint32_t)0x00200000) /*!< Remap I2C1 Tx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_SPI2_RX ((uint32_t)0x00300000) /*!< Remap SPI2 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_TIM1_CH1 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_TIM1_CH2 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_TIM1_CH3 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_TIM3_CH1 ((uint32_t)0x00600000) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_TIM3_TRIG ((uint32_t)0x00600000) /*!< Remap TIM3 Trig on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_TIM16_CH1 ((uint32_t)0x00700000) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_TIM16_UP ((uint32_t)0x00700000) /*!< Remap TIM16 up on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART1_RX ((uint32_t)0x00800000) /*!< Remap USART1 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART2_RX ((uint32_t)0x00900000) /*!< Remap USART2 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART3_RX ((uint32_t)0x00A00000) /*!< Remap USART3 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART4_RX ((uint32_t)0x00B00000) /*!< Remap USART4 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART5_RX ((uint32_t)0x00C00000) /*!< Remap USART5 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART6_RX ((uint32_t)0x00D00000) /*!< Remap USART6 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART7_RX ((uint32_t)0x00E00000) /*!< Remap USART7 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH6_USART8_RX ((uint32_t)0x00F00000) /*!< Remap USART8 Rx on DMA1 channel 6 */
|
||||
#define DMA1_CSELR_CH7_I2C1_RX ((uint32_t)0x02000000) /*!< Remap I2C1 Rx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_SPI2_TX ((uint32_t)0x03000000) /*!< Remap SPI2 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_TIM2_CH2 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_TIM2_CH4 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_TIM17_CH1 ((uint32_t)0x07000000) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_TIM17_UP ((uint32_t)0x07000000) /*!< Remap TIM17 up on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART1_TX ((uint32_t)0x08000000) /*!< Remap USART1 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART2_TX ((uint32_t)0x09000000) /*!< Remap USART2 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART3_TX ((uint32_t)0x0A000000) /*!< Remap USART3 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART4_TX ((uint32_t)0x0B000000) /*!< Remap USART4 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART5_TX ((uint32_t)0x0C000000) /*!< Remap USART5 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART6_TX ((uint32_t)0x0D000000) /*!< Remap USART6 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART7_TX ((uint32_t)0x0E000000) /*!< Remap USART7 Tx on DMA1 channel 7 */
|
||||
#define DMA1_CSELR_CH7_USART8_TX ((uint32_t)0x0F000000) /*!< Remap USART8 Tx on DMA1 channel 7 */
|
||||
|
||||
/****************** Bit definition for DMA_RMPCR2 register ********************/
|
||||
#define DMA_RMPCR2_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA2 */
|
||||
#define DMA_RMPCR2_CH1_I2C2_TX ((uint32_t)0x00000002) /*!< Remap I2C2 TX on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART1_TX ((uint32_t)0x00000008) /*!< Remap USART1 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART2_TX ((uint32_t)0x00000009) /*!< Remap USART2 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART3_TX ((uint32_t)0x0000000A) /*!< Remap USART3 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART4_TX ((uint32_t)0x0000000B) /*!< Remap USART4 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART5_TX ((uint32_t)0x0000000C) /*!< Remap USART5 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART6_TX ((uint32_t)0x0000000D) /*!< Remap USART6 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART7_TX ((uint32_t)0x0000000E) /*!< Remap USART7 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH1_USART8_TX ((uint32_t)0x0000000F) /*!< Remap USART8 Tx on DMA2 channel 1 */
|
||||
#define DMA_RMPCR2_CH2_I2C2_RX ((uint32_t)0x00000020) /*!< Remap I2C2 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART1_RX ((uint32_t)0x00000080) /*!< Remap USART1 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART2_RX ((uint32_t)0x00000090) /*!< Remap USART2 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART3_RX ((uint32_t)0x000000A0) /*!< Remap USART3 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART4_RX ((uint32_t)0x000000B0) /*!< Remap USART4 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART5_RX ((uint32_t)0x000000C0) /*!< Remap USART5 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART6_RX ((uint32_t)0x000000D0) /*!< Remap USART6 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART7_RX ((uint32_t)0x000000E0) /*!< Remap USART7 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH2_USART8_RX ((uint32_t)0x000000F0) /*!< Remap USART8 Rx on DMA2 channel 2 */
|
||||
#define DMA_RMPCR2_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC channel 1 on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_SPI1_RX ((uint32_t)0x00000300) /*!< Remap SPI1 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA2 channel 3 */
|
||||
#define DMA_RMPCR2_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC channel 2 on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_SPI1_TX ((uint32_t)0x00003000) /*!< Remap SPI1 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA2 channel 4 */
|
||||
#define DMA_RMPCR2_CH5_ADC ((uint32_t)0x00010000) /*!< Remap ADC on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART1_TX ((uint32_t)0x00080000) /*!< Remap USART1 Tx on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART2_TX ((uint32_t)0x00090000) /*!< Remap USART2 Tx on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART3_TX ((uint32_t)0x000A0000) /*!< Remap USART3 Tx on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART4_TX ((uint32_t)0x000B0000) /*!< Remap USART4 Tx on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART5_TX ((uint32_t)0x000C0000) /*!< Remap USART5 Tx on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART6_TX ((uint32_t)0x000D0000) /*!< Remap USART6 Tx on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART7_TX ((uint32_t)0x000E0000) /*!< Remap USART7 Tx on DMA2 channel 5 */
|
||||
#define DMA_RMPCR2_CH5_USART8_TX ((uint32_t)0x000F0000) /*!< Remap USART8 Tx on DMA2 channel 5 */
|
||||
/****************** Bit definition for DMA2_CSELR register ********************/
|
||||
#define DMA2_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA2 */
|
||||
#define DMA2_CSELR_CH1_I2C2_TX ((uint32_t)0x00000002) /*!< Remap I2C2 TX on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART1_TX ((uint32_t)0x00000008) /*!< Remap USART1 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART2_TX ((uint32_t)0x00000009) /*!< Remap USART2 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART3_TX ((uint32_t)0x0000000A) /*!< Remap USART3 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART4_TX ((uint32_t)0x0000000B) /*!< Remap USART4 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART5_TX ((uint32_t)0x0000000C) /*!< Remap USART5 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART6_TX ((uint32_t)0x0000000D) /*!< Remap USART6 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART7_TX ((uint32_t)0x0000000E) /*!< Remap USART7 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH1_USART8_TX ((uint32_t)0x0000000F) /*!< Remap USART8 Tx on DMA2 channel 1 */
|
||||
#define DMA2_CSELR_CH2_I2C2_RX ((uint32_t)0x00000020) /*!< Remap I2C2 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART1_RX ((uint32_t)0x00000080) /*!< Remap USART1 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART2_RX ((uint32_t)0x00000090) /*!< Remap USART2 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART3_RX ((uint32_t)0x000000A0) /*!< Remap USART3 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART4_RX ((uint32_t)0x000000B0) /*!< Remap USART4 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART5_RX ((uint32_t)0x000000C0) /*!< Remap USART5 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART6_RX ((uint32_t)0x000000D0) /*!< Remap USART6 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART7_RX ((uint32_t)0x000000E0) /*!< Remap USART7 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH2_USART8_RX ((uint32_t)0x000000F0) /*!< Remap USART8 Rx on DMA2 channel 2 */
|
||||
#define DMA2_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC channel 1 on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_SPI1_RX ((uint32_t)0x00000300) /*!< Remap SPI1 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA2 channel 3 */
|
||||
#define DMA2_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC channel 2 on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_SPI1_TX ((uint32_t)0x00003000) /*!< Remap SPI1 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA2 channel 4 */
|
||||
#define DMA2_CSELR_CH5_ADC ((uint32_t)0x00010000) /*!< Remap ADC on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART1_TX ((uint32_t)0x00080000) /*!< Remap USART1 Tx on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART2_TX ((uint32_t)0x00090000) /*!< Remap USART2 Tx on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART3_TX ((uint32_t)0x000A0000) /*!< Remap USART3 Tx on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART4_TX ((uint32_t)0x000B0000) /*!< Remap USART4 Tx on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART5_TX ((uint32_t)0x000C0000) /*!< Remap USART5 Tx on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART6_TX ((uint32_t)0x000D0000) /*!< Remap USART6 Tx on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART7_TX ((uint32_t)0x000E0000) /*!< Remap USART7 Tx on DMA2 channel 5 */
|
||||
#define DMA2_CSELR_CH5_USART8_TX ((uint32_t)0x000F0000) /*!< Remap USART8 Tx on DMA2 channel 5 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -2780,11 +2771,15 @@ typedef struct
|
|||
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
|
||||
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
|
||||
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
|
||||
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
|
||||
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
|
||||
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
|
||||
#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
|
||||
#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
|
||||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_EMR register ********************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
|
|
@ -2806,11 +2801,15 @@ typedef struct
|
|||
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
|
||||
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
|
||||
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
|
||||
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
|
||||
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
|
||||
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
|
||||
#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
|
||||
#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
|
||||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_RTSR register ******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
|
|
@ -2832,6 +2831,9 @@ typedef struct
|
|||
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
||||
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
||||
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
||||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
|
||||
/******************* Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
|
|
@ -2853,6 +2855,9 @@ typedef struct
|
|||
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
||||
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
||||
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
||||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
|
||||
/******************* Bit definition for EXTI_SWIER register *******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
|
|
@ -2874,6 +2879,9 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
||||
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
||||
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
||||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
|
||||
/****************** Bit definition for EXTI_PR register *********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
|
||||
|
|
@ -2895,6 +2903,9 @@ typedef struct
|
|||
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
|
||||
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
|
||||
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
|
||||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -5320,14 +5331,20 @@ typedef struct
|
|||
((INSTANCE) == DMA2_Channel5))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
/****************************** GPIO Lock Instances ****************************/
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB))
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 03-Oct-2014
|
||||
* @version V2.2.0
|
||||
* @date 05-December-2014
|
||||
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -70,10 +70,10 @@
|
|||
|
||||
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
|
||||
!defined (STM32F031x6) && !defined (STM32F038xx) && \
|
||||
!defined (STM32F042x6) && !defined (STM32F048xx) && \
|
||||
!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
|
||||
!defined (STM32F051x8) && !defined (STM32F058xx) && \
|
||||
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
|
||||
!defined (STM32F091xC) && !defined (STM32F098xx)
|
||||
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
|
||||
!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
|
||||
/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||
/* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
|
||||
/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||
|
|
@ -82,9 +82,12 @@
|
|||
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
|
||||
/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
|
||||
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
|
||||
/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
|
||||
/* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||
/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||
/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
|
||||
/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
|
||||
/* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
|
||||
#define STM32F091xC /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
|
||||
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
|
||||
#endif
|
||||
|
|
@ -102,10 +105,10 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.1.0
|
||||
* @brief CMSIS Device version number V2.2.0
|
||||
*/
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|
|
@ -137,6 +140,10 @@
|
|||
#include "stm32f051x8.h"
|
||||
#elif defined(STM32F058xx)
|
||||
#include "stm32f058xx.h"
|
||||
#elif defined(STM32F070x6)
|
||||
#include "stm32f070x6.h"
|
||||
#elif defined(STM32F070xB)
|
||||
#include "stm32f070xb.h"
|
||||
#elif defined(STM32F071xB)
|
||||
#include "stm32f071xb.h"
|
||||
#elif defined(STM32F072xB)
|
||||
|
|
@ -146,7 +153,9 @@
|
|||
#elif defined(STM32F091xC)
|
||||
#include "stm32f091xc.h"
|
||||
#elif defined(STM32F098xx)
|
||||
#include "stm32f098xx.h"
|
||||
#include "stm32f098xx.h"
|
||||
#elif defined(STM32F030xC)
|
||||
#include "stm32f030xc.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f0xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 03-Oct-2014
|
||||
* @version V2.2.0
|
||||
* @date 05-December-2014
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
|
|
@ -136,6 +136,7 @@
|
|||
updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 48000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
|
|
@ -194,15 +195,31 @@ void SystemInit(void)
|
|||
/* Reset PREDIV[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
|
||||
/* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
#if defined (STM32F072xB) || defined (STM32F078xB)
|
||||
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
|
||||
#elif defined (STM32F071xB)
|
||||
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
|
||||
#elif defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
|
||||
#else
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
|
||||
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
|
||||
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
|
||||
#elif defined (STM32F051x8) || defined (STM32F058xx)
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
|
||||
#elif defined (STM32F042x6) || defined (STM32F048xx)
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
|
||||
#elif defined (STM32F070x6) || defined (STM32F070xB)
|
||||
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
|
||||
/* Set default USB clock to PLLCLK, since there is no HSI48 */
|
||||
RCC->CFGR3 |= (uint32_t)0x00000080;
|
||||
#else
|
||||
#warning "No target selected"
|
||||
#endif
|
||||
|
||||
/* Reset HSI14 bit */
|
||||
|
|
@ -297,13 +314,17 @@ void SystemCoreClockUpdate (void)
|
|||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||
else
|
||||
{
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
|
||||
defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
|
||||
defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
|
||||
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
|
||||
#else
|
||||
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
|
||||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
|
||||
STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 03-Oct-2014
|
||||
* @version V2.2.0
|
||||
* @date 05-December-2014
|
||||
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
Loading…
Reference in New Issue