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1975 Commits (cae7427717c5b51a9b73b636fcbcbf96645ce959)

Author SHA1 Message Date
jeromecoutant 89f554fb53 STM32F3 warning compilation 
[-Wparentheses-equality]
 2019-06-07 18:08:51 +02:00
jeromecoutant f3c7cc9d47 STM32F2 warning compilation 
[-Wparentheses-equality]
 2019-06-07 18:08:51 +02:00
jeromecoutant 8c2ee68be1 STM32F1 warning compilation 
[-Wparentheses-equality]
 2019-06-07 18:08:50 +02:00
jeromecoutant 7154ac65f2 STM32F0 warning compilation 
[-Wparentheses-equality]
 2019-06-07 18:08:50 +02:00
jeromecoutant 5d80f9e98f STM32: remove compilation warning 2019-06-07 18:08:39 +02:00
jeromecoutant a90e68e788 STM32H7 UART: enable LPUART 2019-06-07 18:05:06 +02:00
Filip Jagodzinski 14b83e7fdf STM32WB: Fix serial IRQ handling 
Check that the RX or TX interrupt is enabled before calling
a registered handler with RxIrq or TxIrq arg.
 2019-06-07 15:36:21 +02:00
Filip Jagodzinski 53222fa448 STM32L4: Fix serial IRQ handling 
Check that the RX or TX interrupt is enabled before calling
a registered handler with RxIrq or TxIrq arg.
 2019-06-07 15:33:49 +02:00
Filip Jagodzinski fa0cc68657 STM32H7: Fix serial IRQ handling 
Check that the RX or TX interrupt is enabled before calling
a registered handler with RxIrq or TxIrq arg.
 2019-06-07 15:30:03 +02:00
Filip Jagodzinski d6a48218ee STM32F3: Fix serial IRQ handling 
Check that the RX or TX interrupt is enabled before calling
a registered handler with RxIrq or TxIrq arg.
 2019-06-07 15:26:20 +02:00
Filip Jagodzinski b88b94eb75 STM32L0: Fix serial IRQ handling 
Check that the RX or TX interrupt is enabled before calling
a registered handler with RxIrq or TxIrq arg.
 2019-06-07 15:17:22 +02:00
Filip Jagodzinski c387bd889f STM32F0: Fix serial IRQ handling 
Check that the RX or TX interrupt is enabled before calling
a registered handler with RxIrq or TxIrq arg.
 2019-06-07 15:17:17 +02:00
Filip Jagodzinski 84384162bb STM32F7: Fix serial IRQ handling 
Check that the RX or TX interrupt is enabled before calling
a registered handler with RxIrq or TxIrq arg.
 2019-06-07 15:17:07 +02:00
Vincent Veron 82979f6415 TARGET_STM: SPI: update pull up config depending on clk polarity 
Fix #10589

Signed-off-by: Vincent Veron <vincent.veron@st.com>
 2019-06-06 17:06:04 +02:00
jeromecoutant 25e4316963 STM32H7 directory cleanup and refactoring 2019-06-06 10:48:11 +02:00
jeromecoutant 119ff51fee STM32H7: use default files from ST drivers delivery 2019-06-06 10:48:09 +02:00
jeromecoutant 5b53b3aae0 STM32: define USE_FULL_LL_DRIVER at top level 2019-06-06 10:48:08 +02:00
toyowata f1628f0b8d Correct SPDX identifiers 2019-06-05 19:04:55 +09:00
toyowata 9acf2c325c Fix device_name and add SPDX identifiers 2019-06-05 16:48:08 +09:00
toyowata f0a06b24ba Remove ARCH_MAX files from STM32F407xG 2019-06-05 14:51:06 +09:00
toyowata db2cac45f1 Move Seeed ARCH_MAX to TARGET_STM32F407xE MCU 2019-06-05 14:35:25 +09:00
Teijo Kinnunen 728c01f9e3 STM32L0: Add DEVICE_SPI_COUNT to DISCO_L072CZ_LRWAN1 + MTB_MURATA_ABZ 
Enables simultaneous use of both SPIs without interference.
 2019-06-04 09:38:20 +03:00
Vincent Veron 16475829f1 TARGET_STM: SPI: add pulse on master transmissions 
Add a pulse when using hardware chip select for SPI transmissions.
CS is at low level when a transmission is on-going.

Be careful, this is not compatible with all modes. It will work only
if PHA is 0, ie spi mode is 0 or 2. See stm32xx reference manual,
chapter "NSS pulse mode" for more details.

Fix #10671

Signed-off-by: Vincent Veron <vincent.veron@st.com>
 2019-06-03 10:00:06 +02:00
Martin Kojtal 93e4a8251c
Merge pull request #10697 from jeromecoutant/PR_H7FLASH 
STM32H7: flash issue while erasing sector in Bank 1
 2019-06-03 08:35:29 +01:00
jeromecoutant 58994d88cd STM32H7: flash issue while erasing sector in Bank 1 2019-05-29 09:31:30 +02:00
jeromecoutant d919498745 STM32: common cmsis.h and device.h 2019-05-27 16:27:41 +02:00
jeromecoutant 570e9b0bf4 STM32 WATCHDOG : increase timeout value 2019-05-24 11:35:42 +02:00
jeromecoutant 4300e5d6c4 STM32 WATCHDOG : use ST HAL in order to make code commun for all STM32 2019-05-24 11:35:41 +02:00
jeromecoutant feec85cc37 STM32 WATCHDOG : update STM32L0 HAL_IWDG_Init to a newest version 2019-05-24 11:35:41 +02:00
jeromecoutant e29d64fc19 STM32 WATCHDOG : compilation issue with typed define 2019-05-24 11:35:40 +02:00
jeromecoutant 1b8513a5a8 STM32 Watchdog : move API file to STM family level 2019-05-24 11:35:39 +02:00
Filip Jagodzinski 3d31801f4f STM: HAL: Reset_reason: Correct return values 2019-05-24 11:35:35 +02:00
Filip Jagodzinski d26dba40b2 STM32F4: watchdog HAL: Fix issues found with tests 
Fix WATCHDOG_STATUS_INVALID_ARGUMENT for timeout values from 1 ms to
407 ms (fix inability to set prescaler bits to zero).
Fix timeout <-> IWDG registers conversions.
Fix read & write access to IWDG_PR and IWDG_RLR registers.
Fix LSI RC frequency setting.
Limit MAX_TIMEOUT_MS to UINT32_MAX.
 2019-05-24 11:35:29 +02:00
Steven Cartmell 2fb9fc2a8e Rename watchdog.c -> watchdog_api.c to prevent name collision with Platform API 2019-05-24 11:35:25 +02:00
Steven Cartmell e7761a1d39 Move watchdog parameter validation into the driver layer 2019-05-24 11:35:22 +02:00
Steven Cartmell 31924b2481 Add missing license headers 2019-05-24 11:35:21 +02:00
Steven Cartmell 7c392a16d4 Remove window and sleep mode options for watchdog API 2019-05-24 11:35:13 +02:00
Steven Cartmell 8fa38bb25b Add Watchdog driver API 2019-05-24 11:20:26 +02:00
Steven Cartmell 366893ae71 Add independent watchdog reference implementation for STM32 2019-05-24 11:20:25 +02:00
Steven Cartmell 6b3d790fc1 Add function to fetch platform specific reset reason register values 2019-05-24 11:20:24 +02:00
Steven Cartmell 1ec22fee05 Add reset reason reference implementation STM32 2019-05-24 11:20:23 +02:00
Martin Kojtal 4567626ade
Merge pull request #10636 from u-blox/activation_status 
+UPSND sent to poll activation status
 2019-05-23 21:39:48 +01:00
Martin Kojtal 80d7cb2e17
Merge pull request #10631 from VVESTM/update_cube_h7 
Update cube h7 to 1.4.0
 2019-05-23 21:36:38 +01:00
Martin Kojtal 02b91bdfca
Merge pull request #10582 from malavikasajikumar/master 
Adding LED4 definition in PinNames.h of SDP-K1 board.
 2019-05-23 21:35:42 +01:00
Vincent Veron d8e1e43e35 H7 ST CUBE : remove unecessary #if 1 instead of USE_FULL_LL_DRIVER 
Keep #define USE_FULL_LL_DRIVER and define this switch in target.json

Signed-off-by: Vincent Veron <vincent.veron@st.com>
 2019-05-23 14:01:01 +02:00
Vincent Veron 80b41f0276 H7 ST CUBE V1.4.0 2019-05-23 14:01:00 +02:00
Bilal Qamar defc244db2 +UPSND sent to poll activation status 2019-05-22 16:52:03 +05:00
Martin Kojtal d5b84a5d57 SDP_K1: Fix year change in the system clock 2019-05-21 07:44:49 -07:00
Martin Kojtal d4122b0b3a
Merge pull request #10454 from u-blox/ublox_odin_driver_os_5_v3.7.0_rc1 
Enterprise_mode_+_wifi_configuraiton_api: update ODIN drivers to v3.7.0 RC1
 2019-05-20 10:54:45 +01:00
Malavika Sajikumar cf8f3725f9 Removing stale definition. 2019-05-14 12:33:57 -07:00
Malavika Sajikumar 82a6f157b3 Adding omitted definition for LED4. This is used as a STATUS LED. 2019-05-14 12:32:44 -07:00
Martin Kojtal a2cde2e24e
Merge pull request #10570 from jeromecoutant/PR_ASTYLE 
STM32 astyle updates
 2019-05-14 09:22:18 +01:00
Martin Kojtal 3ea1c56124
Merge pull request #10147 from kjbracey-arm/atomic_bitwise 
Assembler atomics
 2019-05-13 14:18:05 +01:00
Martin Kojtal 548a40ee62
Merge pull request #10541 from guialonsoalb/master 
Adding QSPI support to target RHOMBIO_L476DMW1K
 2019-05-13 13:59:40 +01:00
Martin Kojtal 2956a35b17
Merge pull request #10538 from masoudr/master 
Enabled crash reporting for DISCO_F407VG target
 2019-05-13 13:29:17 +01:00
Martin Kojtal 773729fcf6
Merge pull request #10479 from LMESTM/more_flash_for_stm32wb_app 
STM32WB: Update Flash size
 2019-05-12 20:08:49 +01:00
Anna Bridge 97e1c9cbaf
Merge pull request #10287 from linlingao/pr10177 
Enable MTS_DRAGONFLY_F411RE to register with Pelion
 2019-05-10 16:21:46 +01:00
jeromecoutant 0352bbbd5b STM32 astyle updates 2019-05-10 15:32:05 +02:00
Laurent Meunier e3a72eac9e Typo fix for MBED_APP_SIZE 2019-05-09 10:28:20 +02:00
aqin 43759c0c4b Enterprise mode + wifi configuraiton api 2019-05-08 17:52:04 +05:00
M. Rahimi 06ed3c44c2 Enabled crash reporting for DISCO_F407VG on all other toolchains 2019-05-07 21:43:37 +04:30
M. Rahimi d30bdbe08b Enabled crash reporting for DISCO_F407VG target 2019-05-07 19:25:46 +04:30
Guillermo Alonso 70bc390410 added QSPI support to target RHOMBIO_L476DMW1K 2019-05-07 15:44:09 +02:00
Laurent Meunier fcc375f5c9 Update FLASH_SIZE backup value 
By default, FLASH_SIZE should be read from HW.
In case this is not the case, we define it here, as the size of FLASH
that is available to the application running on M4.
 2019-05-06 11:31:37 +02:00
Laurent Meunier 89eef1b490 STM32WB: Update Flash size 
the flash is shared and split between cortex-M4 that
runs (mbed-os) application and the cortex-M0+ that
runs the BLE firmware.

The 512K allocated to the application was a
conservative that can now be updated.

With recent up-to-date BLE firmware flashed @ 0x080CB000,
there should be 812K available to application.

But there are boards out there that don't have an up-to-date
firmware, so we're keeping an intermediate, safer,
application size of 768K.
 2019-05-06 11:31:37 +02:00
mudassar-ublox 5f55eedfae cellular target name change for ublox cellular instance 2019-05-03 11:21:38 +05:00
Martin Kojtal 87711a9111
Merge pull request #10471 from malavikasajikumar/master 
SDP-K1: Updates to target code
 2019-05-02 19:03:22 +01:00
Lin Gao 2c22f549e9 Add option to keep post_binary_hook and make it default. It can be disabled by setting it to null 2019-05-02 11:25:20 -05:00
Lin Gao 438a52f15a Fix handoff issue from the bootloader to the application on MTS_DRAGONFLY_F411RE 2019-05-02 11:25:19 -05:00
Martin Kojtal d41962a8c8
SDP_K1: Fix year change in the system clock 2019-05-02 11:35:40 +01:00
Martin Kojtal 1de0712272
Merge pull request #9944 from deepikabhavnani/stm32_splitheap 
GCC - Add support to split heap across 2-RAM banks
 2019-04-30 11:02:51 +01:00
Malavika Sajikumar e0faeb2b65 Fixing alignment. 2019-04-29 09:52:01 -07:00
Martin Kojtal 2cd7aa1148
Merge pull request #10303 from juhoeskeli/mem_changes 
STM32L4xx: IAR memory maps updated
 2019-04-29 13:46:46 +01:00
Anna Bridge 536da479dc
Merge pull request #10018 from deepikabhavnani/stm32_heap_armc6 
STM: Update linker script for using SRAM1 and SRAM2 in ARM
 2019-04-26 13:30:42 +01:00
Kevin Bracey 87396e0bf6 Assembler atomics 
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.

API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
  aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++

This gives our existing C implementation essentially all the functionality
needed by C++11.

An actual Atomic<T> template based upon these C functions could follow.
 2019-04-26 13:12:35 +03:00
Malavika Sajikumar f11f63ddcf AWAKE signal turned on at system init for SDP-K1 board. 
- Setting AWAKE signal high in the SystemInit() to ensure VIO supply to daughter boards through SDP and Arduino connectors.
 2019-04-25 23:49:19 -07:00
Malavika Sajikumar 869e48dad0 Improvements made to PinNames.h of SDP-K1 board. 
PinNames.h:
- Removing definition of Status LED.
- Redefining SPI and I2C pin names using Arduino pins names.
 2019-04-25 23:49:19 -07:00
Juho Eskeli 443974b864 STM32L4xx: IAR linker file updated to better use available memory 2019-04-23 12:53:53 +03:00
Martin Kojtal b6a2c7b63f
Merge pull request #10019 from deepikabhavnani/uarm_fix 
uARM - Move heap region after IRAM1
 2019-04-18 12:49:56 +01:00
Deepika 4b7e163b57 Add missing boot stack size memory from heap calculation 2019-04-12 15:28:52 -05:00
jeromecoutant 9c63d91c11 STM32: protect compilation when DEVICE_USTICKER is disabled 2019-04-11 17:57:39 +02:00
Deepika feba293673 Update linker script for using SRAM1 and SRAM2 in ARM 
To have the flexibilty in application; to use any of the section
    (data/bss/heap) without updating linker script in every use case,
    following decisions are made:
    1. Fixed size and small sections moved to SRAM2 (32K)
        Vectors
        Crash data
        Remaining section - RW / ZI
    2. Large memory space should be used for variable sections
       RW/ZI
       Heap - (Minimum - 0x12000)
       Stack - At bottom
 2019-04-09 13:41:09 -05:00
Deepika 1576fb0aaa Add support for split heap in ST devices 2019-04-09 12:08:49 -05:00
Deepika 1a52587c2d Update the linker file to support single and multiple heap banks 2019-04-09 12:08:49 -05:00
Deepika 3593444e93 Add support of heap memory split between 2-RAM banks. 
Please note the heap address of the both the banks must not be contigious else
GCC considers it to be single memory bank and does allocation across the banks,
which might result into hard-fault
 2019-04-09 12:08:49 -05:00
Deepika 719d0fb94e Update linker script for split heap support 
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:

1. Fixed size and small sections moved to SRAM2 (32K)
    Vectors
    Crash data
    Stack
    Remaining section - Heap memory
2. Large memory space should be used for variable sections
   Data
   BSS
   Heap - Remaining section

Heap is moved to the end of both sections as GCC allocates till 4K boundary,
if end of heap is not aligned to 4K, that chunk of memory will go unutilized
 2019-04-09 12:08:49 -05:00
Marcus Chang 7c0714132c Expand sbrk to allocate memory from two regions 2019-04-09 12:08:49 -05:00
Deepika 36c7b2de86 uARM - Move heap region after IRAM1 
ARM_LIB_HEAP start is aligned to IRAM1 end, hence should be placed next to
RW_IRAM1 i.e. no other region in between.
 2019-04-09 12:01:01 -05:00
Vincent Veron 9856e86897 TARGET_STM32F7: Reset QSPI in default mode on abort for all versions. 
This patch is missing in F7 HAL.
Fix #10049

Signed-off-by: Vincent Veron <vincent.veron@st.com>
 2019-04-08 11:47:15 +02:00
Martin Kojtal c2ebb79723
Merge pull request #9814 from LMESTM/dev_NUCLEO_WB55RG 
Adding NUCLEO_WB55RG support
 2019-04-04 15:30:07 +02:00
Martin Kojtal 6081727cbf
Merge pull request #10115 from enebular/raven 
Uhuru RAVEN: Adding platform HAL
 2019-04-04 11:05:23 +02:00
Martin Kojtal 2a694cf1d9
Merge pull request #10143 from jeromecoutant/PR_ADC_RESETINTERNAL 
STM32 ADC INTERNAL CHANNEL reset after read
 2019-04-02 13:02:14 +02:00
Cruz Monrreal cdc2579b7b
Merge pull request #10248 from VVESTM/issue_9934 
TARGET_STM32F7: Refresh cache when erasing or programming flash
 2019-04-01 17:04:26 -05:00
Cruz Monrreal 4dd55d2db6
Merge pull request #10281 from ashok-rao/S2_LP 
Adding support for S2_LP (WiSUN) as a new MTB target
 2019-04-01 17:03:37 -05:00
Ashok Rao 1f572f987e SPDX license identifier changed to Apache-2.0 2019-04-01 15:17:06 +01:00
Ashok Rao 5cb1c64d59 Adding SPDX identifier 2019-04-01 11:21:45 +01:00
Ashok Rao 83ad921196 Resolving merge conflicts from my remote 2019-04-01 07:49:37 +01:00
Ashok Rao d4c83fc056 Adding STM32_F429 + S2_LP (WiSUN) as a new MTB target 2019-04-01 07:31:01 +01:00
Laurent Meunier b0f4815261 STM32WB: ADC INTERNAL CHANNEL reset after read 
Internal channels use is enabling ADC "internal path" which needs
to be disabled after measurement.

Same applied here for WB family as was done for others in #10143.
 2019-03-29 16:21:46 +01:00
Laurent Meunier c6277988c6 STM32WB: Only configure default peripherals in SetSysClock 
Typically the RTC clock is configured by RTC driver itself.

RNG on the other hand is shared with M0+ core and it is expected that
M4 turns it on at boot time.
 2019-03-29 16:21:46 +01:00