My previous commit, c6d2c81, broke Keil builds and maybe even IAR.
I need to learn how to read C code :) I thought I was masking off the
O_BINARY bit only for GCC builds but it turns out that my update was
in the fall-through case for all toolchains. This commit now places
the O_BINARY masking operation into a GCC specific #ifdef clause.
Testing:
I tested the same fopen("/local/out.txt","rb") code as before but this
time I built it with the online compiler and GCC_ARM. I tested the
resulting binaries on mbed-LPC11U24 and mbed-LPC1768 boards.
Thanks to @neilt6 for catching & reporting this!
Fixes issue #1562 reported by @justbuchanan.
When building code with GCC-ARM / newlib, attempting to use the
b (binary) mode in a fopen() call would fail. newlib would parse
this option and pass it down to the LocalFileSystem open call which
didn't like the unexpected O_BINARY flag in openmode.
The openmode_to_posix() function in retarget.cpp would never set the
O_BINARY flag for the other toolchains but for GCC it would just pass
down whatever newlib placed there. This commit masks out the O_BINARY
bit so that it never gets passed down to the file system drivers, just
as occurs for the other supported toolchains.
Test case:
FILE *fp = fopen("/local/out.txt", "rb");
I tested that code on mbed LPC1768 and LPC11U24 boards while using
GCC_ARM as the toolchain. It failed on both platforms previous to
this change and succeeded there after.
When two or more analogue inputs are initialized on more than one ADC HW block the initialisation fails with:
Cannot initialize ADC
The reason is the reusage of just one ADC_HandleTypeDef for all initializations (in mbed\targets\hal\TARGET_STM\TARGET_STM32F3\analogin_api.c). After the first (successful) ADC initialisation AdcHandle.State is set to HAL_ADC_STATE_READY).
But for another ADC block initialisation the AdcHandle.State has to be reset so that the HAL initialize it (in mbed\targets\cmsis\TARGET_STM\TARGET_STM32F3\stm32f3xx_hal_adc_ex.c line 424). When this state is not reset the HAL returns with an initialization error. And this error induces the above mbed error message.
The error message can be reproduced just with AnalogIn in1(xx); AnalogIn in2(yy); where xx and yy belongs to two different ADC blocks.
Datasheet (Table 82) says MSEL bits should be 5, and the PSEL bits should
be 1, for the correct FCCO frequency of 288MHz. The current configuration
has FCCO = 144MHz, which is technically out of spec.
Tested on a custom LPC1549 board with crystal oscillator running at 12MHz.
Modified the LPC1549 AnalogIn implementation to use the ADCs in
synchronous mode, which is consistent with the LPC11U68 implementation.
This improves performance, and allows the IRC oscillator to be powered
down if necessary.
Use only the index, not the UARTName any more.
In case of app with 2 serial (using DMA) + 1 serial (stdio), we have found a bug. The dma handler is overwritten by the last initialized serial object.
Therefore read and write functions did not work anymore.
We have reworked this file to save 1 handler per UART IP, and align it with MBED OS file.
Tests have been passed. Same status as before (OK except MBED_37, manual test for SERIAL_ASYNC also OK).
We modified the following to support the export function to the IAR.
- In tools files, add RZ_A1H to the target of IAR.
- In tools files, add the tmpl files.
Can contains 2 fifos. Both generates its own interrupt.
IRQ_RX occurs when a message has arrived in FIFO-0 , FIFO-0 is full or
overrun.
IRQ_RX1 occurs when a message has arrived in FIFO-1 , FIFO-1 is full or
overrun.
Flush errors and current data register at reading start
Allow separate serial obj for TX and RX (= do not initialize [TX/RX]_DMA
when not needed.
Char_match: make it work with long buffers and return the correct
position of the char_match.
* Allow pins to be configured as NC without failing or asserting
* Fix putc() to not return before the entire character has been physically shifted out.
* Use MBED_ASSERT
* Fix baudrate calculation to avoid wrong configuration on startup for stdio
* Setting the PWM period now correctly updates all other channels to keep their duty cycle
* No longer keep values in RAM that can be read directly from a register
* Setting the PWM duty cycle to 100% no longer makes the signal glitch on every period
* Code condensation
* Added PD9 back in (for some reason it was at some point removed from the pinmap, not sure why because it is a usable pin when you remove the on-board sensor or use the Pearl chip standalone)
* Fixed PWM locations to match the pin-CC channel combinations.
Allows clocking the device from RC oscillators (HFRCO, LFRCO).
Note that we can not use the em_cmu.h enums directly as the
preprocessor can not do comparisons on them.
Related changes in serial_api, so that LEUART clock is within
acceptable limits on Pearl.
Contains quite a bit of indentation changes to make the preprocessor
logic more readable so recommend viewing the diff in ignore whitespace
mode.
Keep a counter of sleeps blocked for every device, and do not try
to unblock sleep modes we did not block. This fixes problems where
serial events would cause EM1/EM2 to be unblocked too early,
causing the MCU to go to EM3 and not being able to wake up.
When initializing for use with the board controller, the LEUART must
be clocked from HF clock as the baud rate is otherwise too high.
Do this by first initializing to "standard" 9600, then call serial_baud
which will handle setting up the clocks and dividers.
Switch caused a phantom 0xFF frame to appear on the line when we switched
from LEUART to USART due to a baud rate was increase. This was short
enough that it was only visible at high (~115kbps) speeds.
As a fix, skip disabling the GPIO pins (as their configuration does not
change), and defer disabling the LEUART routing until at the very last
moment. Additionally, do not call serial_format, but immediately
initialize the UART to correct params.
- Do not attempt to disable the transmitter. Did not find a robust
way to do so - see comment in file for more info.
- Do not unblock sleep when abort is called externally, this leads
to jams as EM1 block gets disabled and the next sleep call places
the hardware to directly to EM3.
- Retain more status when switching over from LEUART to USART in
Pearl: keep registered IRQ handlers and other IRQ status.
Changed SPI implementation: #1 To avoid clearing data from buffers, during splitted DMA transfer
RX/TX buffer clear is done only when transfer is started.
USART transmit is completed instead of DMA/LDMA transfer completed.
When doing a large transfer over the LDMA it is required to wait TX to be completed
before transferring the next part of the data. Added a loop, to wait until TXC flag is set in function USART_STATUS_TXC.
+ minor code cleanup and EM1 sleep is allowed again.
Second, the TX interrupt was not cleared after processing, causing
it to stay in an infinite loop.
Conditional when dispatching LEUART irq would always select the RX
side due to a bitwise AND being typoed as a logical AND.
Second, the TX interrupt was not cleared after processing, causing
it to stay in an infinite loop.
Previously, all pins in an mbed Port were set to the same value.
Use GPIO_PortOutSetVal to directly write the desired value to
the pins.
During port initialization the pin mode for input pins was set incorrectly.
Now, input pins are directly set to Input (gpioModeInput) and output pins to
PushPull (gpioModePushPull).
dbestm
Martin Kojtal
Adam Green
neilt6
adustm
Toyomasa Watarai
Peter Conheeney
ohagendorf
mtkrtk
dc37
Kevin Gillespie
bcostm
modtronix-com
tomoyuki yamanaka
Parthasarathy.S
Moin Shaik
Mac Lobdell
sg-
dinau
anpilog
Steven Cooreman
Paul Staron
leibin
Mikko Polojarvi
Aksel Skauge Mellbye
jhokajar