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Merge pull request #1576 from PeterConheeney/master 

latest changes to add arduino support, plus fixes for IOTSS BEID
pull/1584/head
Martin Kojtal 2016-03-02 15:29:53 +01:00
parent c0da36d9a4 ca41874978
commit de3b14ec92
122 changed files with 11259 additions and 3644 deletions
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170
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h → libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h
View File

@ -1,39 +1,39 @@
/**************************************************************************//**
* @file CMSDK_BEID.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_BEID Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file CMSDK_BEID.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_BEID Device
*
*******************************************************************************/
#ifndef CMSDK_BEID_H
@ -59,40 +59,61 @@ typedef enum IRQn
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */
UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */
/* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */
UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
Spare_IRQn = 1, /* Undefined */
UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
I2C0_IRQn = 3, /* I2C 0 Interrupt */
I2C1_IRQn = 4, /* I2C 1 Interrupt */
RTC_IRQn = 5, /* RTC Interrupt */
PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
SPI_IRQn = 11, /* SPI Interrupt */
SPI0_IRQn = 11, /* SPI 0 Interrupt */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */
SPI1_IRQn = 13, /* SPI 1 Interrupt */
RESERVED0_IRQn = 14, /* Reserved */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
PORT0_1_IRQn = 17, /* There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
PORT01_0_IRQn = 16, /* GPIO Port 0 pin 0 Handler */
PORT01_1_IRQn = 17, /* GPIO Port 0 pin 1 Handler */
PORT01_2_IRQn = 18, /* GPIO Port 0 pin 2 Handler */
PORT01_3_IRQn = 19, /* GPIO Port 0 pin 3 Handler */
PORT01_4_IRQn = 20, /* GPIO Port 0 pin 4 Handler */
PORT01_5_IRQn = 21, /* GPIO Port 0 pin 5 Handler */
PORT01_6_IRQn = 22, /* GPIO Port 0 pin 6 Handler */
PORT01_7_IRQn = 23, /* GPIO Port 0 pin 7 Handler */
PORT01_8_IRQn = 24, /* GPIO Port 0 pin 8 Handler */
PORT01_9_IRQn = 25, /* GPIO Port 0 pin 9 Handler */
PORT01_10_IRQn = 26, /* GPIO Port 0 pin 10 Handler */
PORT01_11_IRQn = 27, /* GPIO Port 0 pin 11 Handler */
PORT01_12_IRQn = 28, /* GPIO Port 0 pin 12 Handler */
PORT01_13_IRQn = 29, /* GPIO Port 0 pin 13 Handler */
PORT01_14_IRQn = 30, /* GPIO Port 0 pin 14 Handler */
PORT01_15_IRQn = 31, /* GPIO Port 0 pin 15 Handler */
SYSERROR_IRQn = 32, /* System Error Interrupt */
EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
RESERVED1_IRQn = 34, /* Reserved */
RESERVED2_IRQn = 35, /* Reserved */
RESERVED3_IRQn = 36, /* Reserved */
RESERVED4_IRQn = 37, /* Reserved */
RESERVED5_IRQn = 38, /* Reserved */
RESERVED6_IRQn = 39, /* Reserved */
RESERVED7_IRQn = 40, /* Reserved */
RESERVED8_IRQn = 41, /* Reserved */
PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
TRNG_IRQn = 44, /* Random number generator Interrupt */
UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */
UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */
ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */
I2S_IRQn = 48, /* I2S Interrupt */
MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */
MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */
MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */
MPS2_SPI3_IRQn = 52, /* SPI Interrupt (spi 0 shield 0 replacement) */
MPS2_SPI4_IRQn = 53 /* SPI Interrupt (shield 1) */
} IRQn_Type;
@ -101,7 +122,7 @@ typedef enum IRQn
/* ================================================================================ */
/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
#define __CM3_REV 0x0201 /* Core revision r2p1 */
#define __BEID_REV 0x0201 /* Core revision r2p1 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
@ -725,18 +746,19 @@ typedef struct
#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (0x4002C000UL)
#define CMSDK_UART3_BASE (0x4002D000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
#define CMSDK_GPIO4_BASE (0x40030000UL)
#define CMSDK_GPIO5_BASE (0x40031000UL)
#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
@ -745,7 +767,7 @@ typedef struct
/* ================================================================================ */
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
@ -754,11 +776,13 @@ typedef struct
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
//#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
#define CMSDK_GPIO4 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO4_BASE )
#define CMSDK_GPIO5 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO5_BASE )
#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )

150
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h → libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h
View File

@ -1,18 +1,37 @@
/*
* Copyright:
* ----------------------------------------------------------------
* This confidential and proprietary software may be used only as
* authorised by a licensing agreement from ARM Limited
* (C) COPYRIGHT 2014 ARM Limited
* ALL RIGHTS RESERVED
* The entire notice above must be reproduced on all authorised
* copies and copies may only be made to the extent permitted
* by a licensing agreement from ARM Limited.
* ----------------------------------------------------------------
* File: smm_mps2.h
* Release: Version 1.0
* ----------------------------------------------------------------
*/
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
#define __SMM_MPS2_H
@ -27,7 +46,7 @@
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
@ -41,14 +60,13 @@ typedef struct
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
// Increments when 32-bit prescale counter reach zero
uint32_t RESERVED3[1];
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
__IO uint32_t PRESCALE; // Offset: 0x1C (R/W) Prescaler
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
__IO uint32_t PSCNTR; // Offset: 0x020 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[10];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
@ -88,7 +106,7 @@ typedef struct
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
@ -298,10 +316,10 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
@ -336,7 +354,7 @@ typedef struct
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
@ -345,7 +363,7 @@ typedef struct
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
@ -353,12 +371,12 @@ typedef struct
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
@ -373,33 +391,33 @@ typedef struct
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
@ -554,14 +572,10 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Audio Interface I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
#else
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
@ -577,40 +591,20 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
//******************************************************************************/
/******************************************************************************/
/* General Function Definitions */
/******************************************************************************/
/******************************************************************************/
/* General MACRO Definitions */
/******************************************************************************/
//#define DEBUG
//#ifdef DEBUG
// #define debug(...) printf(__VA_ARGS__)
//#else
// #define debug(...)
//#endif // ifdef DEBUG
// Bit control macros
//#define HW_REG(base,offset) *((volatile unsigned int *)((base) + (offset)))
#define CREATE_MASK(msb, lsb) (((1U << ((msb) - (lsb) + 1)) - 1) << (lsb))
#define MASK_BITS(arg, msb, lsb) ((arg) & CREATE_MASK(msb, lsb))
#define EXTRACT_BITS(arg, msb, lsb) (MASK_BITS(arg, msb, lsb) >> (lsb))
#define INSERT_BITS(arg, msb, lsb, value) \
((arg) = ((arg) & ~CREATE_MASK(msb, lsb)) | (((value) << (lsb)) & CREATE_MASK(msb, lsb)))
#define MASK_FIELD(arg, field) MASK_BITS(arg, field##_MSB, field##_LSB)
#define EXTRACT_FIELD(arg, field) EXTRACT_BITS(arg, field##_MSB, field##_LSB)
#define INSERT_FIELD(arg, field, value) INSERT_BITS(arg, field##_MSB, field##_LSB, value)
#define SET_BIT(arg, bit) ((arg) |= (1 << (bit)))
#define CLEAR_BIT(arg, bit) ((arg) &= ~(1 << (bit)))
#define TEST_BIT(arg, bit) ((arg) & (1 << (bit)))
#ifndef NoOfElements
#define NoOfElements(array) (sizeof(array) / sizeof(array[0]))
#endif
#endif /* __SMM_MPS2_H */

47
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/MPS2.sct Normal file
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@ -0,0 +1,47 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2016 ARM Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
RW_IRAM1 (0x20000000+0x140) (0x400000-0x140) { ; RW data
.ANY (+RW +ZI)
}
}

358
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s Normal file
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@ -0,0 +1,358 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
; @file startup_CMSDK_BEID.s
; @brief CMSIS Core Device Startup File for
; CMSDK_BEID Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt
DCD Spare_IRQHandler ; 1:Undefined
DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt
DCD I2C0_IRQHandler ; 3:I2C 0 Interrupt
DCD I2C1_IRQHandler ; 4:I2C 1 Interrupt
DCD RTC_IRQHandler ; 5:RTC Interrupt
DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt
DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt
DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt
DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt
DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt
DCD SPI0_IRQHandler ; 11:SPI 0 Interrupt
DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt
DCD SPI1_IRQHandler ; 13:SPI 1 Interrupt
DCD RESERVED0_IRQHandler ; 14:Reserved
DCD TSC_IRQHandler ; 15:Touch Screen Interrupt
DCD PORT01_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler
DCD PORT01_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler
DCD PORT01_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler
DCD PORT01_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler
DCD PORT01_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler
DCD PORT01_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler
DCD PORT01_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler
DCD PORT01_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler
DCD PORT01_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler
DCD PORT01_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler
DCD PORT01_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler
DCD PORT01_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler
DCD PORT01_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler
DCD PORT01_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler
DCD PORT01_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler
DCD PORT01_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler
DCD SYSERROR_IRQHandler ; 32:System Error Interrupt
DCD EFLASH_IRQHandler ; 33:Embedded Flash Interrupt
DCD RESERVED1_IRQHandler ; 34:Reserved
DCD RESERVED2_IRQHandler ; 35:Reserved
DCD RESERVED3_IRQHandler ; 36:Reserved
DCD RESERVED4_IRQHandler ; 37:Reserved
DCD RESERVED5_IRQHandler ; 38:Reserved
DCD RESERVED6_IRQHandler ; 39:Reserved
DCD RESERVED7_IRQHandler ; 40:Reserved
DCD RESERVED8_IRQHandler ; 41:Reserved
DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt
DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt
DCD TRNG_IRQHandler ; 44:Random number generator Interrupt
DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt
DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt
DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a.
DCD I2S_IRQHandler ; 48:I2S Interrupt
DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header)
DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd)
DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement)
DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement)
DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1)
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt
EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined
EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt
EXPORT I2C0_IRQHandler [WEAK] ; 3:I2C 0 Interrupt
EXPORT I2C1_IRQHandler [WEAK] ; 4:I2C 1 Interrupt
EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt
EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt
EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt
EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt
EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt
EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt
EXPORT SPI0_IRQHandler [WEAK] ; 11:SPI 0 Interrupt
EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt
EXPORT SPI1_IRQHandler [WEAK] ; 13:SPI 1 Interrupt
EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved
EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt
EXPORT PORT01_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler
EXPORT PORT01_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler
EXPORT PORT01_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler
EXPORT PORT01_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler
EXPORT PORT01_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler
EXPORT PORT01_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler
EXPORT PORT01_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler
EXPORT PORT01_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler
EXPORT PORT01_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler
EXPORT PORT01_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler
EXPORT PORT01_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler
EXPORT PORT01_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler
EXPORT PORT01_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler
EXPORT PORT01_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler
EXPORT PORT01_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler
EXPORT PORT01_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler
EXPORT SYSERROR_IRQHandler [WEAK] ; 32:System Error Interrupt
EXPORT EFLASH_IRQHandler [WEAK] ; 33:Embedded Flash Interrupt
EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved
EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved
EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved
EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved
EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved
EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved
EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved
EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved
EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt
EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt
EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt
EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt
EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt
EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a.
EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt
EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header)
EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd)
EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement)
EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement)
EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1)
UART0_IRQHandler
Spare_IRQHandler
UART1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
RTC_IRQHandler
PORT0_IRQHandler
PORT1_ALL_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
DUALTIMER_IRQHandler
SPI0_IRQHandler
UARTOVF_IRQHandler
SPI1_IRQHandler
RESERVED0_IRQHandler
TSC_IRQHandler
PORT01_0_IRQHandler
PORT01_1_IRQHandler
PORT01_2_IRQHandler
PORT01_3_IRQHandler
PORT01_4_IRQHandler
PORT01_5_IRQHandler
PORT01_6_IRQHandler
PORT01_7_IRQHandler
PORT01_8_IRQHandler
PORT01_9_IRQHandler
PORT01_10_IRQHandler
PORT01_11_IRQHandler
PORT01_12_IRQHandler
PORT01_13_IRQHandler
PORT01_14_IRQHandler
PORT01_15_IRQHandler
SYSERROR_IRQHandler
EFLASH_IRQHandler
RESERVED1_IRQHandler
RESERVED2_IRQHandler
RESERVED3_IRQHandler
RESERVED4_IRQHandler
RESERVED5_IRQHandler
RESERVED6_IRQHandler
RESERVED7_IRQHandler
RESERVED8_IRQHandler
PORT2_ALL_IRQHandler
PORT3_ALL_IRQHandler
TRNG_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
ETHERNET_IRQHandler
I2S_IRQHandler
MPS2_SPI0_IRQHandler
MPS2_SPI1_IRQHandler
MPS2_SPI2_IRQHandler
MPS2_SPI3_IRQHandler
MPS2_SPI4_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

42
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* A generic CMSIS include header, pulling in MPS2 specifics
*******************************************************************************/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "CMSDK_BEID.h"
#include "SMM_MPS2.h"
#include "cmsis_nvic.h"
#endif

58
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}

54
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 64)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

45
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* Name: Device.h
* Purpose: Include the correct device header file
*******************************************************************************/
#ifndef __DEVICE_H
#define __DEVICE_H
#if defined CMSDK_BEID
#include "CMSDK_BEID.h" /* device specific header file */
#else
#warning "no appropriate header file found!"
#endif
#endif /* __DEVICE_H */

95
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file system_CMSDK_BEID.c
* @brief CMSIS Device System Source File for
* CMSDK_BEID Device
*
*******************************************************************************/
#include "CMSDK_BEID.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (48000000UL) /* Oscillator frequency */
#define __SYSTEM_CLOCK (__XTAL / 2)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
// Enable AHB and APB clock
CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO
CMSDK_SYSCON->APBCLKCFG0SET = 0xF9B7; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER
}

76
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************
* @file system_CMSDK_BEID.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_BEID Device
*
******************************************************************************/
#ifndef SYSTEM_CMSDK_BEID_H
#define SYSTEM_CMSDK_BEID_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_BEID_H */

15
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,15 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 +0 { ; load address = execution address
*.o (RESET, +FIRST)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 +0 { ; RW data
.ANY (+RW +ZI)
}
}

291
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s
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@ -1,291 +0,0 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM3.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM3 Device
; * @version V3.02
; * @date 15. November 2013
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2013 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UARTRX0_Handler [WEAK]
EXPORT UARTTX0_Handler [WEAK]
EXPORT UARTRX1_Handler [WEAK]
EXPORT UARTTX1_Handler [WEAK]
EXPORT UARTRX2_Handler [WEAK]
EXPORT UARTTX2_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
EXPORT PORT1_COMB_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
EXPORT SPI_Handler [WEAK]
EXPORT UARTOVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
EXPORT PORT0_3_Handler [WEAK]
EXPORT PORT0_4_Handler [WEAK]
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
UARTRX1_Handler
UARTTX1_Handler
UARTRX2_Handler
UARTTX2_Handler
PORT0_COMB_Handler
PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
SPI_Handler
UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

14
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h
View File

@ -1,14 +0,0 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC1768 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "CMSDK_BEID.h"
#include "SMM_MPS2.h"
#include "cmsis_nvic.h"
#endif

30
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c
View File

@ -1,30 +0,0 @@
/* mbed Microcontroller Library - cmsis_nvic for LCP1768
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}

26
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h
View File

@ -1,26 +0,0 @@
/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

34
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h
View File

@ -1,34 +0,0 @@
/*-----------------------------------------------------------------------------
* Name: Device.h
* Purpose: Include the correct device header file
*-----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* This software is supplied "AS IS" without warranties of any kind.
*
* Copyright (c) 2013 KEIL - An ARM Company. All rights reserved.
*----------------------------------------------------------------------------*/
#ifndef __DEVICE_H
#define __DEVICE_H
#if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */
#elif defined CMSDK_BEID
#include "CMSDK_BEID.h" /* device specific header file */
#else
#warning "no appropriate header file found!"
#endif
#endif /* __DEVICE_H */

95
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c
View File

@ -1,95 +0,0 @@
/**************************************************************************//**
* @file system_CMSDK_BEID.c
* @brief CMSIS Device System Source File for
* CMSDK_M3 Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "CMSDK_BEID.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (50000000UL) /* Oscillator frequency */
#define __SYSTEM_CLOCK (__XTAL / 2)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
// Enable AHB and APB clock
CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO
CMSDK_SYSCON->APBCLKCFG0SET = 0x37; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER
}

75
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h
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@ -1,75 +0,0 @@
/**************************************************************************//**
* @file system_CMSDK_BEID.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_BEID Device
* @version V3.02
* @date 15. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_CMSDK_BEID_H
#define SYSTEM_CMSDK_BEID_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_BEID_H */

135
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h
View File

@ -1,41 +1,37 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file CMSDK_CM0.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_CM0 Device
* @version V3.02
* @date 15. November 2013
*
* @note configured for CM7 without FPU
*
*******************************************************************************/
@ -52,51 +48,48 @@
typedef enum IRQn
{
/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
SPI_IRQn = 11, /* SPI Interrupt */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
PORT0_1_IRQn = 17, /* There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type;
@ -686,7 +679,9 @@ typedef struct
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
@ -704,6 +699,8 @@ typedef struct
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )

119
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h
View File

@ -1,36 +1,36 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.0
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
@ -46,7 +46,7 @@
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
@ -65,11 +65,14 @@ typedef struct
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:7] : Reserved
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
@ -93,12 +96,18 @@ typedef struct
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
@ -308,10 +317,10 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
@ -346,7 +355,7 @@ typedef struct
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
@ -355,7 +364,7 @@ typedef struct
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
@ -363,12 +372,12 @@ typedef struct
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
@ -383,33 +392,33 @@ typedef struct
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,33 +1,33 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2015 ARM Limited
;* Copyright (c) 2006-2016 ARM Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
; *************************************************************
; *** Scatter-Loading Description File ***
@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}

157
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s
View File

@ -1,43 +1,42 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM0 Device
; * @version V3.02
; * @date 04. February 2015
; *
; * @note
; * Copyright (C) 2015 ARM Limited. All rights reserved.
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2015 ARM LIMITED
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
; @file startup_CMSDK_CM0.s
; @brief CMSIS Core Device Startup File for
; CMSDK_CM0 Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
@ -108,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -185,6 +184,14 @@ Default_Handler PROC
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT2_COMB_Handler [WEAK]
EXPORT PORT3_COMB_Handler [WEAK]
EXPORT UARTRX3_Handler [WEAK]
EXPORT UARTTX3_Handler [WEAK]
EXPORT UARTRX4_Handler [WEAK]
EXPORT UARTTX4_Handler [WEAK]
EXPORT ADCSPI_Handler [WEAK]
EXPORT SHIELDSPI_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
@ -193,14 +200,6 @@ Default_Handler PROC
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
@ -218,22 +217,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* A generic CMSIS include header, pulling in MPS2 specifics
*******************************************************************************/

52
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
@ -41,13 +41,13 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
// Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
// Set the vector
vectors[IRQn + 16] = vector;
// Set the vector
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
// We can always read vectors at 0x0, as the addresses are remapped
uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
// Return the vector
return vectors[IRQn + 16];

48
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
@ -37,7 +37,7 @@
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* Name: Device.h
* Purpose: Include the correct device header file

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c
View File

@ -1,41 +1,37 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file system_CMSDK_CM0.c
* @brief CMSIS Device System Source File for
* CMSDK_M0 Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
*******************************************************************************/

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h
View File

@ -1,42 +1,38 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************
* @file system_CMSDK_CM0.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_CM0 Device
* @version V3.02
* @date 15. March 2013
*
* @note
*
******************************************************************************/

137
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h
View File

@ -1,41 +1,37 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file CMSDK_CM0plus.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_CM0plus Device
* @version V3.02
* @date 15. November 2013
*
* @note configured for CM7 without FPU
*
*******************************************************************************/
@ -52,51 +48,48 @@
typedef enum IRQn
{
/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_CM0plus Specific Interrupt Numbers -------------- */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
SPI_IRQn = 11, /* SPI Interrupt */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
PORT0_1_IRQn = 17, /* There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type;
@ -687,7 +680,9 @@ typedef struct
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
@ -705,6 +700,8 @@ typedef struct
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )

119
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h
View File

@ -1,36 +1,36 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.0
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
@ -46,7 +46,7 @@
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
@ -65,11 +65,14 @@ typedef struct
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:7] : Reserved
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
@ -93,12 +96,18 @@ typedef struct
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
@ -308,10 +317,10 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
@ -346,7 +355,7 @@ typedef struct
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
@ -355,7 +364,7 @@ typedef struct
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
@ -363,12 +372,12 @@ typedef struct
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
@ -383,33 +392,33 @@ typedef struct
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,33 +1,33 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2015 ARM Limited
;* Copyright (c) 2006-2016 ARM Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
; *************************************************************
; *** Scatter-Loading Description File ***
@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}

163
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s
View File

@ -1,43 +1,42 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM0 Device
; * @version V3.02
; * @date 15. November 2013
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2013 ARM LIMITED
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
; @file startup_CMSDK_CM0P.s
; @brief CMSIS Core Device Startup File for
; CMSDK_CM0P Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
@ -108,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -164,9 +163,9 @@ PendSV_Handler PROC
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UARTRX0_Handler [WEAK]
@ -185,6 +184,14 @@ Default_Handler PROC
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT2_COMB_Handler [WEAK]
EXPORT PORT3_COMB_Handler [WEAK]
EXPORT UARTRX3_Handler [WEAK]
EXPORT UARTTX3_Handler [WEAK]
EXPORT UARTRX4_Handler [WEAK]
EXPORT UARTTX4_Handler [WEAK]
EXPORT ADCSPI_Handler [WEAK]
EXPORT SHIELDSPI_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
@ -193,14 +200,6 @@ Default_Handler PROC
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
@ -218,22 +217,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* A generic CMSIS include header, pulling in MPS2 specifics
*******************************************************************************/

52
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
@ -41,13 +41,13 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
// Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
// Set the vector
vectors[IRQn + 16] = vector;
// Set the vector
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
// We can always read vectors at 0x0, as the addresses are remapped
uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
// Return the vector
return vectors[IRQn + 16];

48
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
@ -37,7 +37,7 @@
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* Name: Device.h
* Purpose: Include the correct device header file

51
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c
View File

@ -1,46 +1,41 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file system_CMSDK_CM0plus.c
* @brief CMSIS Device System Source File for
* CMSDK_M0 Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
*******************************************************************************/
#include "CMSDK_CM0plus.h"
/*----------------------------------------------------------------------------

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h
View File

@ -1,42 +1,38 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************
* @file system_CMSDK_CM0plus.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_CM0plus Device
* @version V3.02
* @date 15. March 2013
*
* @note
*
******************************************************************************/

121
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h
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@ -1,41 +1,37 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file CMSDK_CM3.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_CM3 Device
* @version V3.02
* @date 15. November 2013
*
* @note configured for CM7 without FPU
*
*******************************************************************************/
@ -63,40 +59,39 @@ typedef enum IRQn
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
SPI_IRQn = 11, /* SPI Interrupt */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
PORT0_1_IRQn = 17, /* There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
/****** CMSDK Specific Interrupt Numbers *********************************************************/
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type;
@ -686,7 +681,9 @@ typedef struct
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
@ -704,6 +701,8 @@ typedef struct
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )

119
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h
View File

@ -1,36 +1,36 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.0
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
@ -46,7 +46,7 @@
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
@ -65,11 +65,14 @@ typedef struct
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:7] : Reserved
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
@ -93,12 +96,18 @@ typedef struct
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
@ -308,10 +317,10 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
@ -346,7 +355,7 @@ typedef struct
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
@ -355,7 +364,7 @@ typedef struct
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
@ -363,12 +372,12 @@ typedef struct
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
@ -383,33 +392,33 @@ typedef struct
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,33 +1,33 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2015 ARM Limited
;* Copyright (c) 2006-2016 ARM Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
; *************************************************************
; *** Scatter-Loading Description File ***
@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}

157
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s
View File

@ -1,43 +1,42 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM3.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM3 Device
; * @version V3.02
; * @date 15. November 2013
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2013 ARM LIMITED
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
; @file startup_CMSDK_CM3.s
; @brief CMSIS Core Device Startup File for
; CMSDK_CM3 Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
@ -108,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -205,6 +204,14 @@ Default_Handler PROC
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT2_COMB_Handler [WEAK]
EXPORT PORT3_COMB_Handler [WEAK]
EXPORT UARTRX3_Handler [WEAK]
EXPORT UARTTX3_Handler [WEAK]
EXPORT UARTRX4_Handler [WEAK]
EXPORT UARTTX4_Handler [WEAK]
EXPORT ADCSPI_Handler [WEAK]
EXPORT SHIELDSPI_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
@ -213,14 +220,6 @@ Default_Handler PROC
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
@ -238,22 +237,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* A generic CMSIS include header, pulling in MPS2 specifics
*******************************************************************************/

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/

48
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
@ -37,7 +37,7 @@
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* Name: Device.h
* Purpose: Include the correct device header file

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c
View File

@ -1,41 +1,37 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file system_CMSDK_CM3.c
* @brief CMSIS Device System Source File for
* CMSDK_M3 Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
*******************************************************************************/

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h
View File

@ -1,42 +1,38 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************
* @file system_CMSDK_CM3.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_CM3 Device
* @version V3.02
* @date 15. March 2013
*
* @note
*
******************************************************************************/

281
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h
View File

@ -1,41 +1,37 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file CMSDK_CM4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
* Device CMSDK_CM4
* @version V3.01
* @date 06. March 2012
*
* @note configured for CM7 without FPU
*
*******************************************************************************/
@ -45,80 +41,57 @@
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup CMSDK_CM4_Definitions CMSDK_CM4 Definitions
This file defines all structures and symbols for CMSDK_CM4:
- registers and bitfields
- peripheral base address
- peripheral ID
- Peripheral definitions
@{
*/
#endif
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup CMSDK_CM4_CMSIS Device CMSIS Definitions
Configuration of the Cortex-M4 Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *******************************************************/
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
// UARTRX3_IRQn = 6, /*!< UART 2 RX Interrupt //only used in extended version */
// UARTTX3_IRQn = 7, /*!< UART 2 TX Interrupt //only used in extended version */
PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
/****** CMSDK Specific Interrupt Numbers *********************************************************/
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type;
@ -285,23 +258,23 @@ typedef struct
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
// <o.7> TimerEn: Timer Enable
// <o.6> TimerMode: Timer Mode
// <0=> Freerunning-mode
// <1=> Periodic mode
// <o.5> IntEnable: Interrupt Enable
// <o.2..3> TimerPre: Timer Prescale
// <0=> / 1
// <1=> / 16
// <2=> / 256
// <3=> Undefined!
// <o.1> TimerSize: Timer Size
// <0=> 16-bit counter
// <1=> 32-bit counter
// <o.0> OneShot: One-shoot mode
// <0=> Wrapping mode
// <1=> One-shot mode
// </h>
/* <o.7> TimerEn: Timer Enable */
/* <o.6> TimerMode: Timer Mode */
/* <0=> Freerunning-mode */
/* <1=> Periodic mode */
/* <o.5> IntEnable: Interrupt Enable */
/* <o.2..3> TimerPre: Timer Prescale */
/* <0=> / 1 */
/* <1=> / 16 */
/* <2=> / 256 */
/* <3=> Undefined! */
/* <o.1> TimerSize: Timer Size */
/* <0=> 16-bit counter */
/* <1=> 32-bit counter */
/* <o.0> OneShot: One-shoot mode */
/* <0=> Wrapping mode */
/* <1=> One-shot mode */
/* </h> */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
@ -310,23 +283,23 @@ typedef struct
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
// <o.7> TimerEn: Timer Enable
// <o.6> TimerMode: Timer Mode
// <0=> Freerunning-mode
// <1=> Periodic mode
// <o.5> IntEnable: Interrupt Enable
// <o.2..3> TimerPre: Timer Prescale
// <0=> / 1
// <1=> / 16
// <2=> / 256
// <3=> Undefined!
// <o.1> TimerSize: Timer Size
// <0=> 16-bit counter
// <1=> 32-bit counter
// <o.0> OneShot: One-shoot mode
// <0=> Wrapping mode
// <1=> One-shot mode
// </h>
/* <o.7> TimerEn: Timer Enable */
/* <o.6> TimerMode: Timer Mode */
/* <0=> Freerunning-mode */
/* <1=> Periodic mode */
/* <o.5> IntEnable: Interrupt Enable */
/* <o.2..3> TimerPre: Timer Prescale */
/* <0=> / 1 */
/* <1=> / 16 */
/* <2=> / 256 */
/* <3=> Undefined! */
/* <o.1> TimerSize: Timer Size */
/* <0=> 16-bit counter */
/* <1=> 32-bit counter */
/* <o.0> OneShot: One-shoot mode */
/* <0=> Wrapping mode */
/* <1=> One-shot mode */
/* </h> */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
@ -413,23 +386,23 @@ typedef struct
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
// <o.7> TimerEn: Timer Enable
// <o.6> TimerMode: Timer Mode
// <0=> Freerunning-mode
// <1=> Periodic mode
// <o.5> IntEnable: Interrupt Enable
// <o.2..3> TimerPre: Timer Prescale
// <0=> / 1
// <1=> / 16
// <2=> / 256
// <3=> Undefined!
// <o.1> TimerSize: Timer Size
// <0=> 16-bit counter
// <1=> 32-bit counter
// <o.0> OneShot: One-shoot mode
// <0=> Wrapping mode
// <1=> One-shot mode
// </h>
/* <o.7> TimerEn: Timer Enable */
/* <o.6> TimerMode: Timer Mode */
/* <0=> Freerunning-mode */
/* <1=> Periodic mode */
/* <o.5> IntEnable: Interrupt Enable */
/* <o.2..3> TimerPre: Timer Prescale */
/* <0=> / 1 */
/* <1=> / 16 */
/* <2=> / 256 */
/* <3=> Undefined! */
/* <o.1> TimerSize: Timer Size */
/* <0=> 16-bit counter */
/* <1=> 32-bit counter */
/* <o.0> OneShot: One-shoot mode */
/* <0=> Wrapping mode */
/* <1=> One-shot mode */
/* </h> */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
@ -1146,9 +1119,9 @@ typedef struct
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
// <o.1> RESEN: Reset enable
// <o.0> INTEN: Interrupt enable
// </h>
/* <o.1> RESEN: Reset enable */
/* <o.0> INTEN: Interrupt enable */
/* </h> */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
@ -1278,8 +1251,9 @@ __IO uint32_t MODECTRL;
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
//#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) //only used in extended version
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
@ -1301,9 +1275,10 @@ __IO uint32_t MODECTRL;
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
//#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) //only used in extended version
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )

119
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h
View File

@ -1,36 +1,36 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.0
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
@ -46,7 +46,7 @@
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
@ -65,11 +65,14 @@ typedef struct
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:7] : Reserved
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
@ -93,12 +96,18 @@ typedef struct
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
@ -308,10 +317,10 @@ typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
@ -346,7 +355,7 @@ typedef struct
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
@ -355,7 +364,7 @@ typedef struct
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
@ -363,12 +372,12 @@ typedef struct
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
@ -383,33 +392,33 @@ typedef struct
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */

50
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,33 +1,33 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2015 ARM Limited
;* Copyright (c) 2006-2016 ARM Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
; *************************************************************
; *** Scatter-Loading Description File ***
@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}

129
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s
View File

@ -1,41 +1,38 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2015 ARM Limited
; Copyright (c) 2006-2016 ARM Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
; @file startup_CMSDK_CM4.s
; @brief CMSIS Core Device Startup File for
; CMSDK_CM4 Device
; @version V3.03
; @date 04. February 2015
;
; @note
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
@ -110,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -207,6 +204,14 @@ Default_Handler PROC
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT2_COMB_Handler [WEAK]
EXPORT PORT3_COMB_Handler [WEAK]
EXPORT UARTRX3_Handler [WEAK]
EXPORT UARTTX3_Handler [WEAK]
EXPORT UARTRX4_Handler [WEAK]
EXPORT UARTTX4_Handler [WEAK]
EXPORT ADCSPI_Handler [WEAK]
EXPORT SHIELDSPI_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
@ -215,14 +220,6 @@ Default_Handler PROC
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
@ -240,22 +237,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* A generic CMSIS include header, pulling in MPS2 specifics
*******************************************************************************/

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/

48
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
@ -37,7 +37,7 @@
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus

46
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h
View File

@ -1,33 +1,33 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* Name: Device.h
* Purpose: Include the correct device header file

51
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c
View File

@ -1,46 +1,41 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file system_CMSDK_CM4.c
* @brief CMSIS Device System Source File for
* CMSDK_M4 Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
*******************************************************************************/
#include "CMSDK_CM4.h"
/*----------------------------------------------------------------------------

51
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h
View File

@ -1,42 +1,38 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************
* @file system_CMSDK_CM4.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_CM4 Device
* @version V3.02
* @date 15. March 2013
*
* @note
*
******************************************************************************/
@ -76,5 +72,4 @@ extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_CM4_H */

67
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h
View File

@ -1,6 +1,6 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -32,10 +32,6 @@
* @file CMSDK_CM7.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_CM7 Device
* @version V1.00
* @date 27. August 2014
*
* @note configured for CM7 without FPU
*
*******************************************************************************/
@ -52,16 +48,16 @@ extern "C" {
typedef enum IRQn
{
/* ------------------- CM7 Processor Exceptions Numbers --------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
// HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
@ -80,23 +76,22 @@ typedef enum IRQn
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
PORT0_1_IRQn = 17, /* There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type;
@ -105,12 +100,12 @@ typedef enum IRQn
/* ================================================================================ */
/* -------- Configuration of the CM7 Processor and Core Peripherals --------- */
#define __CM4_REV 0x0000 /* Core revision r0p0 */
#define __CM7_REV 0x0101 /* Core revision r1p1 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /* no FPU present */
#define __FPU_DP 1 /* unused */
#define __FPU_DP 1 /* unused */
#define __ICACHE_PRESENT 1
#define __DCACHE_PRESENT 1
@ -694,7 +689,9 @@ typedef struct
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
@ -712,6 +709,8 @@ typedef struct
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )

37
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h
View File

@ -1,6 +1,6 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -30,7 +30,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.0
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
@ -65,11 +65,14 @@ typedef struct
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:7] : Reserved
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
@ -93,6 +96,12 @@ typedef struct
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
@ -402,14 +411,14 @@ typedef struct
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
@ -556,13 +565,18 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
@ -571,11 +585,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */

6
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,6 +1,6 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2015 ARM Limited
;* Copyright (c) 2006-2016 ARM Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}

85
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s
View File

@ -1,6 +1,6 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2015 ARM Limited
; Copyright (c) 2006-2016 ARM Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
@ -32,10 +32,7 @@
; @file startup_CMSDK_CM7.s
; @brief CMSIS Core Device Startup File for
; CMSDK_CM7 Device
; @version V1.00
; @date 04. February 2015
;
; @note
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
@ -110,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -207,6 +204,14 @@ Default_Handler PROC
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT2_COMB_Handler [WEAK]
EXPORT PORT3_COMB_Handler [WEAK]
EXPORT UARTRX3_Handler [WEAK]
EXPORT UARTTX3_Handler [WEAK]
EXPORT UARTRX4_Handler [WEAK]
EXPORT UARTTX4_Handler [WEAK]
EXPORT ADCSPI_Handler [WEAK]
EXPORT SHIELDSPI_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
@ -215,14 +220,6 @@ Default_Handler PROC
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
@ -240,22 +237,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

195
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld
View File

@ -1,195 +0,0 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

314
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s
View File

@ -1,314 +0,0 @@
/* File: startup_ARMCM7.S
* Purpose: startup file for Cortex-M7 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.00
* Date: 22 August 2014
*
*/
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long WDT_IRQHandler /* 0: Watchdog Timer */
.long RTC_IRQHandler /* 1: Real Time Clock */
.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
.long MCIA_IRQHandler /* 4: MCIa */
.long MCIB_IRQHandler /* 5: MCIb */
.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
.long UART4_IRQHandler /* 9: UART4 - not connected */
.long AACI_IRQHandler /* 10: AACI / AC97 */
.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
.long ENET_IRQHandler /* 12: Ethernet */
.long USBDC_IRQHandler /* 13: USB Device */
.long USBHC_IRQHandler /* 14: USB Host Controller */
.long CHLCD_IRQHandler /* 15: Character LCD */
.long FLEXRAY_IRQHandler /* 16: Flexray */
.long CAN_IRQHandler /* 17: CAN */
.long LIN_IRQHandler /* 18: LIN */
.long I2C_IRQHandler /* 19: I2C ADC/DAC */
.long 0 /* 20: Reserved */
.long 0 /* 21: Reserved */
.long 0 /* 22: Reserved */
.long 0 /* 23: Reserved */
.long 0 /* 24: Reserved */
.long 0 /* 25: Reserved */
.long 0 /* 26: Reserved */
.long 0 /* 27: Reserved */
.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
.long 0 /* 29: Reserved - CPU FPGA */
.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler WDT_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler TIM0_IRQHandler
def_irq_handler TIM2_IRQHandler
def_irq_handler MCIA_IRQHandler
def_irq_handler MCIB_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler UART4_IRQHandler
def_irq_handler AACI_IRQHandler
def_irq_handler CLCD_IRQHandler
def_irq_handler ENET_IRQHandler
def_irq_handler USBDC_IRQHandler
def_irq_handler USBHC_IRQHandler
def_irq_handler CHLCD_IRQHandler
def_irq_handler FLEXRAY_IRQHandler
def_irq_handler CAN_IRQHandler
def_irq_handler LIN_IRQHandler
def_irq_handler I2C_IRQHandler
def_irq_handler CPU_CLCD_IRQHandler
def_irq_handler SPI_IRQHandler
.end

2
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h
View File

@ -37,7 +37,7 @@
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus

9
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c
View File

@ -1,6 +1,6 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -32,10 +32,6 @@
* @file system_CMSDK_CM7.c
* @brief CMSIS Device System Source File for
* CMSDK_CM7 Device
* @version V1.00
* @date 27. August 2014
*
* @note
*
*******************************************************************************/
@ -64,6 +60,9 @@
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*

6
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h
View File

@ -1,6 +1,6 @@
/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2015 ARM Limited
* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -33,10 +33,6 @@
* @file system_CMSDK_CM7.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_CM7 Device
* @version V1.00
* @date 27. August 2014
*
* @note
*
******************************************************************************/

91
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h Normal file
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@ -0,0 +1,91 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)CMSDK_UART1_BASE,
UART_1 = (int)CMSDK_UART3_BASE,
UART_2 = (int)CMSDK_UART0_BASE,
UART_3 = (int)CMSDK_UART2_BASE
} UARTName;
typedef enum {
I2C_0 = (int)MPS2_TSC_I2C_BASE,
I2C_1 = (int)MPS2_AAIC_I2C_BASE,
I2C_2 = (int)MPS2_SHIELD0_I2C_BASE,
I2C_3 = (int)MPS2_SHIELD1_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7,
ADC0_8,
ADC0_9,
ADC0_10,
ADC0_11
} ADCName;
typedef enum {
SPI_0 = (int)MPS2_SSP0_BASE,
SPI_1 = (int)MPS2_SSP1_BASE,
SPI_2 = (int)MPS2_SSP2_BASE,
SPI_3 = (int)MPS2_SSP3_BASE,
SPI_4 = (int)MPS2_SSP4_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
#define MBED_UART0 USBTX, USBRX
#define MBED_UART1 XB_TX, XB_RX
#define MBED_UART2 SH0_TX, SH0_RX
#define MBED_UART3 SH1_TX, SH1_RX
#define MBED_UARTUSB USBTX, USBRX
#ifdef __cplusplus
}
#endif
#endif

241
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h Normal file
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@ -0,0 +1,241 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// MPS2 EXP Pin Names
EXP0 = 0 ,
EXP1 = 4 ,
EXP2 = 2 ,
EXP3 = 3 ,
EXP4 = 1 ,
EXP5 = 15,
EXP6 = 5 ,
EXP7 = 6 ,
EXP8 = 7 ,
EXP9 = 8 ,
EXP10 =9 ,
EXP11 =13,
EXP12 =10,
EXP13 =11,
EXP14 =12,
EXP15 =14,
EXP16 =18,
EXP17 =19,
EXP18 =20,
EXP19 =21,
EXP20 =52,
EXP21 =53,
EXP22 =54,
EXP23 =55,
EXP24 =56,
EXP25 =57,
EXP26 =16,
EXP27 =25,
EXP28 =24,
EXP29 =31,
EXP30 =17,
EXP31 =23,
EXP32 =27,
EXP33 =30,
EXP34 =26,
EXP35 =28,
EXP36 =29,
EXP37 =58,
EXP38 =48,
EXP39 =49,
EXP40 =50,
EXP41 =22,
EXP42 =59,
EXP43 =60,
EXP44 =51,
EXP45 =61,
EXP46 =62,
EXP47 =63,
EXP48 =64,
EXP49 =65,
EXP50 =66,
EXP51 =67,
// Other mbed Pin Names
//LEDs on mps2
//user leds
USERLED1 = 100,
USERLED2 = 101,
//user switches
USERSW1 = 110,
USERSW2 = 111,
//mcc leds
LED1 = 200,
LED2 = 201,
LED3 = 202,
LED4 = 203,
LED5 = 204,
LED6 = 205,
LED7 = 206,
LED8 = 207,
//MCC Switches
SW1 = 210,
SW2 = 211,
SW3 = 212,
SW4 = 213,
SW5 = 214,
SW6 = 215,
SW7 = 216,
SW8 = 217,
//MPS2 SPI header pins j21
MOSI_SPI = 300,
MISO_SPI = 301,
SCLK_SPI = 302,
SSEL_SPI = 303,
//MPS2 CLCD SPI
CLCD_MOSI = 304,
CLCD_MISO = 305,
CLCD_SCLK = 306,
CLCD_SSEL = 307,
CLCD_RESET = 308,
CLCD_RS = 309,
CLCD_RD = 310,
CLCD_BL_CTRL = 311,
//MPS2 shield 0 SPI
SHIELD_0_SPI_SCK = 320,
SHIELD_0_SPI_MOSI = 321,
SHIELD_0_SPI_MISO = 322,
SHIELD_0_SPI_nCS = 323,
//MPS2 shield 1 SPI
SHIELD_1_SPI_SCK = 331,
SHIELD_1_SPI_MOSI = 332,
SHIELD_1_SPI_MISO = 333,
SHIELD_1_SPI_nCS = 334,
//MPS2 shield ADC SPI
ADC_MOSI = 650,
ADC_MISO = 651,
ADC_SCLK = 652,
ADC_SSEL = 653,
//MPS2 Uart
USBTX = 400,
USBRX = 401,
XB_TX = 402,
XB_RX = 403,
SH0_TX = 404,
SH0_RX = 405,
SH1_TX = 406,
SH1_RX = 407,
//MPS2 I2C touchscreen and audio
TSC_SDA = 500,
TSC_SCL = 501,
AUD_SDA = 502,
AUD_SCL = 503,
//MPS2 I2C for shield
SHIELD_0_SDA = 504,
SHIELD_0_SCL = 505,
SHIELD_1_SDA = 506,
SHIELD_1_SCL = 507,
//MPS2 shield Analog pins
A0_0 = 600,
A0_1 = 601,
A0_2 = 602,
A0_3 = 603,
A0_4 = 604,
A0_5 = 605,
A1_0 = 606,
A1_1 = 607,
A1_2 = 608,
A1_3 = 609,
A1_4 = 610,
A1_5 = 611,
//MPS2 Shield Digital pins
D0_0 = EXP0,
D0_1 = EXP4,
D0_2 = EXP2,
D0_3 = EXP3,
D0_4 = EXP1,
D0_5 = EXP6,
D0_6 = EXP7,
D0_7 = EXP8,
D0_8 = EXP9,
D0_9 = EXP10,
D0_10 = EXP12,
D0_11 = EXP13,
D0_12 = EXP14,
D0_13 = EXP11,
D0_14 = EXP15,
D0_15 = EXP5,
D1_0 = EXP26,
D1_1 = EXP30,
D1_2 = EXP28,
D1_3 = EXP29,
D1_4 = EXP27,
D1_5 = EXP32,
D1_6 = EXP33,
D1_7 = EXP34,
D1_8 = EXP35,
D1_9 = EXP36,
D1_10 = EXP38,
D1_11 = EXP39,
D1_12 = EXP40,
D1_13 = EXP44,
D1_14 = EXP41,
D1_15 = EXP31,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

31
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h Normal file
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@ -0,0 +1,31 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1
} PortName;
#ifdef __cplusplus
}
#endif
#endif

450
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c Normal file
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@ -0,0 +1,450 @@
/* MPS2 Peripheral Library
*
* Copyright (c) 2006-2015 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Code implementation file for the LAN Ethernet interface.
*/
#include <stdio.h>
#include "wait_api.h"
#include "ETH_MPS2.h"
// SMSC9220 low-level operations
unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
{
unsigned int val, maccmd;
int timedout;
int error;
error = 0;
val = SMSC9220->MAC_CSR_CMD;
if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
maccmd = 0;
maccmd |= regoffset;
maccmd |= ((unsigned int)1 << 30); // Indicates read
maccmd |= ((unsigned int)1 << 31); // Start bit
SMSC9220->MAC_CSR_CMD = maccmd; // Start operation
timedout = 50;
do {
val = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1); //Sleepms(1);
timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) {
error = 1;
}
else
*data = SMSC9220->MAC_CSR_DATA;
} else {
*data = 0;
}
return error;
}
unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
{
unsigned int read, maccmd;
int timedout;
int error;
error = 0;
read = SMSC9220->MAC_CSR_CMD;
if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
SMSC9220->MAC_CSR_DATA = data; // Store data.
maccmd = 0;
maccmd |= regoffset;
maccmd &= ~((unsigned int)1 << 30); // Clear indicates write
maccmd |= ((unsigned int)1 << 31); // Indicate start of operation
SMSC9220->MAC_CSR_CMD = maccmd;
timedout = 50;
do {
read = SMSC9220->BYTE_TEST; // A no-op read.
wait_ms(1); //Sleepms(1);
timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
if(!timedout) {
error = 1;
}
} else {
printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n");
}
return error;
}
unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
{
unsigned int val, phycmd; int error;
int timedout;
error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy
phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11]
phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
phycmd &= ~(1 << 1); // Clear [1] indicates read.
phycmd |= (1 << 0); // Set [0] indicates operation start
smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd);
val = 0;
timedout = 50;
do {
wait_ms(1); //Sleepms(1);
timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val);
} while(timedout && (val & ((unsigned int)1 << 0)));
if(!timedout) {
error = 1;
}
else
smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
} else {
*data = 0;
}
return error;
}
unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
{
unsigned int val, phycmd; int error;
int timedout;
error = 0;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
if(!(val & 1)) { // Not busy
smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data
phycmd = 0;
phycmd |= (1 << 11); // 1 to [15:11]
phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
phycmd |= (1 << 1); // Set [1] indicates write.
phycmd |= (1 << 0); // Set [0] indicates operation start
smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); // Start operation
phycmd = 0;
timedout = 50;
do {
wait_ms(1); //Sleepms(1);
timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
} while(timedout && (phycmd & (1 << 0)));
if(!timedout) {
error = 1;
}
} else {
printf("Warning: SMSC9220 MAC MII is busy. No data written.\n");
}
return error;
}
// Returns smsc9220 id.
unsigned int smsc9220_read_id(void)
{
return SMSC9220->ID_REV;
}
// Initiates a soft reset, returns failure or success.
unsigned int smsc9220_soft_reset(void)
{
int timedout;
timedout = 10;
// Soft reset
SMSC9220->HW_CFG |= 1;
do {
wait_ms(1); //Sleepms(1);
timedout--;
} while(timedout && (SMSC9220->HW_CFG & 1));
if(!timedout)
return 1;
return 0;
}
void smsc9220_set_txfifo(unsigned int val)
{
// 2kb minimum, 14kb maximum
if(val < 2 || val > 14)
return;
SMSC9220->HW_CFG = val << 16;
}
unsigned int smsc9220_wait_eeprom(void)
{
int timedout;
timedout = 50;
do {
wait_ms(1); //Sleepms(1);
timedout--;
} while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
if(!timedout)
return 1;
return 0;
}
/* initialise irqs */
void smsc9220_init_irqs(void)
{
SMSC9220->INT_EN = 0x0;
SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts
SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable.
}
unsigned int smsc9220_check_phy(void)
{
unsigned short phyid1, phyid2;
smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1);
smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2);
return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
(phyid1 == 0x0 && phyid2 == 0x0));
}
unsigned int smsc9220_reset_phy(void)
{
unsigned short read;
int error;
error = 0;
if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
error = 1;
return error;
}
read |= (1 << 15);
if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
error = 1;
return error;
}
return 0;
}
/* Advertise all speeds and pause capabilities */
void smsc9220_advertise_cap(void)
{
unsigned short aneg_adv;
aneg_adv = 0;
smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
aneg_adv |= 0xDE0;
smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv);
smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
return;
}
void smsc9220_establish_link(void)
{
unsigned short bcr;
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
bcr |= (1 << 12) | (1 << 9);
smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr);
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
{
unsigned int hw_cfg;
hw_cfg = 0;
hw_cfg = SMSC9220->HW_CFG;
hw_cfg &= 0xF0000;
hw_cfg |= (1 << 20);
SMSC9220->HW_CFG = hw_cfg;
}
return;
}
void smsc9220_enable_xmit(void)
{
SMSC9220->TX_CFG = 0x2; // Enable trasmission
return;
}
void smsc9220_enable_mac_xmit(void)
{
unsigned int mac_cr;
mac_cr = 0;
smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
mac_cr |= (1 << 3); // xmit enable
mac_cr |= (1 << 28); // Heartbeat disable
smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
return;
}
void smsc9220_enable_mac_recv(void)
{
unsigned int mac_cr;
mac_cr = 0;
smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
mac_cr |= (1 << 2); // Recv enable
smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
return;
}
unsigned int smsc9220_check_ready(void)
{
return !(SMSC9220->PMT_CTRL & 1);
}
/* Generate a soft irq */
void smsc9220_set_soft_int(void)
{
SMSC9220->INT_EN |= 0x80000000;
}
/* clear soft irq */
void smsc9220_clear_soft_int(void)
{
SMSC9220->INT_STS |= 0x80000000;
}
unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
{
unsigned int rxfifo_inf; // Tells us the status of rx payload and status fifos.
unsigned int rxfifo_stat;
unsigned int pktsize;
unsigned int dwords_to_read;
rxfifo_inf = SMSC9220->RX_FIFO_INF;
if(rxfifo_inf & 0xFFFF) { // If there's data
rxfifo_stat = SMSC9220->RX_STAT_PORT;
if(rxfifo_stat != 0) { // Fetch status of this packet
pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
if(rxfifo_stat & (1 << 15)) {
printf("Error occured during receiving of packets on the bus.\n");
return 1;
} else {
/* Below formula (recommended by SMSC9220 code)
* gives 1 more than required. This is perhaps because
* a last word is needed for not word aligned packets.
*/
dwords_to_read = (pktsize + 3) >> 2;
// PIO copy of data received:
while(dwords_to_read > 0) {
recvbuf[*index] = SMSC9220->RX_DATA_PORT;
(*index)++;
dwords_to_read--;
}
}
} else {
return 1;
}
} else {
return 1;
}
rxfifo_stat = SMSC9220->RX_STAT_PORT;
rxfifo_inf = SMSC9220->RX_FIFO_INF;
return 0;
}
// Does the actual transfer of data to FIFO, note it does no
// fifo availability checking. This should be done by caller.
// Assumes the whole frame is transferred at once as a single segment
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
{
unsigned int txcmd_a, txcmd_b;
unsigned int dwords_to_write;
volatile unsigned int dwritten;
unsigned int *pktptr;
volatile unsigned int xmit_stat, xmit_stat2, xmit_inf;
int i;
pktptr = (unsigned int *) pkt;
txcmd_a = 0;
txcmd_b = 0;
txcmd_a |= (1 << 12) | (1 << 13); // First and last segments
txcmd_a |= length & 0x7FF; // [10:0] contains length
txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length
txcmd_b |= length & 0x7FF; // [10:0] also contains length
SMSC9220->TX_DATA_PORT = txcmd_a;
SMSC9220->TX_DATA_PORT = txcmd_b;
dwritten = dwords_to_write = (length + 3) >> 2;
// PIO Copy to FIFO. Could replace this with DMA.
while(dwords_to_write > 0) {
SMSC9220->TX_DATA_PORT = *pktptr;
pktptr++;
dwords_to_write--;
}
xmit_stat = SMSC9220->TX_STAT_PORT;
xmit_stat2 = SMSC9220->TX_STAT_PORT;
xmit_inf = SMSC9220->TX_FIFO_INF;
if(xmit_stat2 != 0 ) {
for(i = 0; i < 6; i++) {
xmit_stat2 = SMSC9220->TX_STAT_PORT;
}
}
}

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libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h Normal file
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/* MPS2 Peripheral Library
*
* Copyright (c) 2006-2015 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ETH_MPS2_H_
#define _ETH_MPS2_H_
#include "SMM_MPS2.h"
// Function declarations
unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data);
unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data);
unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data);
unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data);
unsigned int smsc9220_read_id(void);
unsigned int smsc9220_soft_reset(void);
void smsc9220_set_txfifo(unsigned int val);
unsigned int smsc9220_wait_eeprom(void);
void smsc9220_init_irqs(void);
unsigned int smsc9220_check_phy(void);
unsigned int smsc9220_reset_phy(void);
void smsc9220_advertise_cap(void);
void smsc9220_establish_link(void);
void smsc9220_enable_xmit(void);
void smsc9220_enable_mac_xmit(void);
void smsc9220_enable_mac_recv(void);
unsigned int smsc9220_check_ready(void);
void smsc9220_set_soft_int(void);
void smsc9220_clear_soft_int(void);
unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index);
void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length);
#endif

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libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* ----------------------------------------------------------------
* File: fpga.c
* Release: Version 1.0
* ----------------------------------------------------------------
*/
/*
* Code implementation file for the fpga functions.
*/
#include "SMM_MPS2.h" // MPS2 common header
// Function to delay n*ticks (25MHz = 40nS per tick)
// Used for I2C drivers
void i2c_delay(unsigned int tick)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (tick);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}
/* Sleep function to delay n*mS
* Uses FPGA counter.
*/
void Sleepms(unsigned int msec)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * msec * 1000);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}
/* Sleep function to delay n*uS
*/
void Sleepus(unsigned int usec)
{
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * usec);
if(end >= start)
{
while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
}
else
{
while (MPS2_FPGAIO->COUNTER >= start);
while (MPS2_FPGAIO->COUNTER < end);
}
}

34
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Code implementation file for the fpga functions.
*/
#include "SMM_MPS2.h" // MPS2 common header
// Function to delay n*ticks (25MHz = 40nS per tick)
// Used for I2C drivers
void i2c_delay(unsigned int tick);
/* Sleep function to delay n*mS
* Uses FPGA counter.
*/
void Sleepms(unsigned int msec);
/* Sleep function to delay n*uS
*/
void Sleepus(unsigned int usec);

166
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "mps2_ethernet_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#include "toolchain.h"
#include "mbed_error.h"
#include "ETH_MPS2.h"
#include "wait_api.h"
#define TX_PKT_SIZE 256
#define RX_PKT_SIZE 300
// Types
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
int smsc9220_check_id(void)
{
int error;
unsigned int id;
error = 0;
id = smsc9220_read_id();
// If bottom and top halves of the word are the same
if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
error = 1;
return error;
}
switch(((id >> 16) & 0xFFFF)) {
case 0x9220:
break;
default:
error = 1;
break;
}
return error;
}
int smsc9220_check_macaddress(void)
{
int error;
const unsigned int mac_valid_high = 0xC00A;
const unsigned int mac_valid_low = 0x00F70200;
unsigned int mac_low;
unsigned int mac_high;
error = 0;
// Read current mac address.
smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
// Writing temporary address:
smsc9220_mac_regwrite(SMSC9220_MAC_ADDRH, mac_valid_high);
smsc9220_mac_regwrite(SMSC9220_MAC_ADDRL, mac_valid_low);
// Verify write was correct:
smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
if(mac_high != mac_valid_high || mac_low != mac_valid_low) {
error = TRUE;
return error;
}
return error;
}
void smsc9220_print_mac_registers()
{
unsigned int read;
int i;
i = 0;
read = 0;
for(i = 1; i <= 0xC; i++) {
smsc9220_mac_regread(i, &read);
}
return;
}
void smsc9220_print_phy_registers()
{
unsigned short read;
unsigned int i;
i = 0;
read = 0;
for(i = 0; i <= 6; i++) {
smsc9220_phy_regread(i, &read);
}
smsc9220_phy_regread(i = 17, &read);
smsc9220_phy_regread(i = 18, &read);
smsc9220_phy_regread(i = 27, &read);
smsc9220_phy_regread(i = 29, &read);
smsc9220_phy_regread(i = 30, &read);
smsc9220_phy_regread(i = 31, &read);
return;
}
/*----------------------------------------------------------------------------
Ethernet Device initialize
*----------------------------------------------------------------------------*/
int ethernet_transmission(unsigned char * pkt, unsigned int length)
{
smsc9220_xmit_packet(pkt, length);
return 0;
}
int ethernet_reception(unsigned int *recvbuf, unsigned int *index)
{
return smsc9220_recv_packet((unsigned int *)recvbuf, index);
}
int ethernet_mac_address(char *mac)
{
return smsc9220_check_macaddress();
}
unsigned int ethernet_check_ready(void)
{
return smsc9220_check_ready();
}
unsigned int ethernet_intf()
{
unsigned int txfifo_inf;
txfifo_inf = SMSC9220->TX_FIFO_INF;
return txfifo_inf;
}

57
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MPS2_ETHERNET_API_H
#define MPS2_ETHERNET_API_H
#include "device.h"
#if DEVICE_ETHERNET
#ifdef __cplusplus
extern "C" {
#endif
// Connection constants
// send ethernet write buffer, returning the packet size sent
int ethernet_transmission(unsigned char * pkt, unsigned int length);
// recieve from ethernet buffer, returning packet size, or 0 if no packet
int ethernet_reception(unsigned int *recvbuf, unsigned int *index);
// get the ethernet address
int ethernet_mac_address(char *mac);
unsigned int ethernet_check_ready(void);
unsigned int ethernet_intf(void);
int smsc9220_check_id(void);
int smsc9220_check_macaddress(void);
void smsc9220_print_mac_registers(void);
void smsc9220_print_phy_registers(void);
#ifdef __cplusplus
}
#endif
#endif
#endif

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libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define ADC_12BIT_RANGE 0xFFF
static const PinMap PinMap_ADC[] = {
{A0_0, ADC0_0, 0},
{A0_1, ADC0_1, 0},
{A0_2, ADC0_2, 0},
{A0_3, ADC0_3, 0},
{A0_4, ADC0_4, 0},
{A0_5, ADC0_5, 0},
{A1_0, ADC0_6, 0},
{A1_1, ADC0_7, 0},
{A1_2, ADC0_8, 0},
{A1_3, ADC0_9, 0},
{A1_4, ADC0_10, 0},
{A1_5, ADC0_11, 0},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SCLK[] = {
{ADC_SCLK , SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{ADC_MOSI, SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{ADC_MISO, SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{ADC_SSEL, SPI_3, 0},
{NC , NC , 0}
};
#define ADC_RANGE ADC_12BIT_RANGE
int analog_spi_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
obj->pin = pin;
obj->pin_number = pin-600;
obj->address = (0x0000 | (pin-600));
SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI);
SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO);
SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK);
SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL);
SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso);
SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel);
obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl);
if(analog_spi_inited == 0){
obj->adc_spi->CR1 = 0;
obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16;
obj->adc_spi->CPSR = SSP_CPSR_DFLT;
obj->adc_spi->IMSC = 0x8;
obj->adc_spi->DMACR = 0;
obj->adc_spi->CR1 = SSP_CR1_SSE_Msk;
obj->adc_spi->ICR = 0x3;
analog_spi_inited = 1;
}
pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI);
pinmap_pinout(ADC_MISO, PinMap_SPI_MISO);
pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK);
pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL);
pinmap_pinout(pin, PinMap_ADC);
}
static inline uint32_t adc_read(analogin_t *obj) {
return 0;
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read(obj);
return 0;
}
uint16_t analogin_read_u16(analogin_t *obj) {
return 0;
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_SERIAL_FC 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 0
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CLCD 1
#define DEVICE_TSC 1
#define DEVICE_AACI 1
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 1
#define DEVICE_PWMOUT 0
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_SLEEP 0
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_RED 0
#include "objects.h"
#endif

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libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "ethernet_api.h"
#include "mps2_ethernet_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#include "toolchain.h"
#include "mbed_error.h"
#include "ETH_MPS2.h"
#include "wait_api.h"
#define TX_PKT_SIZE 256
#define RX_PKT_SIZE 300
// Types
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
/*----------------------------------------------------------------------------
Ethernet Device initialize
*----------------------------------------------------------------------------*/
int ethernet_init()
{
int error;
error = 0;
if(smsc9220_check_id()) {
error = TRUE;
}
if(smsc9220_soft_reset()) {
error = TRUE;
}
smsc9220_set_txfifo(5);
// Sets automatic flow control thresholds, and backpressure
// threshold to defaults specified.
SMSC9220->AFC_CFG = 0x006E3740;
if(smsc9220_wait_eeprom()) {
error = TRUE;
}
// Configure GPIOs as LED outputs.
SMSC9220->GPIO_CFG = 0x70070000;
smsc9220_init_irqs();
/* Configure MAC addresses here if needed. */
if(smsc9220_check_phy()) {
error = TRUE;
}
if(smsc9220_reset_phy()) {
error = TRUE;
return error;
}
wait_ms(100);
// Checking whether phy reset completed successfully.
{
unsigned short phyreset;
phyreset = 0;
smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset);
if(phyreset & (1 << 15)) {
error = TRUE;
return error;
}
}
/* Advertise capabilities */
smsc9220_advertise_cap();
/* Begin to establish link */
smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing.
// Although it's not so in the manual.
/* Interrupt threshold */
SMSC9220->FIFO_INT = 0xFF000000;
smsc9220_enable_mac_xmit();
smsc9220_enable_xmit();
SMSC9220->RX_CFG = 0;
smsc9220_enable_mac_recv();
// Rx status FIFO level irq threshold
SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles
// This sleep is compulsory otherwise txmit/receive will fail.
wait_ms(2000);
return error;
}
/*----------------------------------------------------------------------------
Ethernet Device Uninitialize
*----------------------------------------------------------------------------*/
void ethernet_free() {
}
int ethernet_write(const char *data, int size)
{
return 0;
}
int ethernet_send()
{
return 0;
}
int ethernet_receive()
{
return 0;
}
// Read from an recevied ethernet packet.
// After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet.
// Read will write up to size bytes into data.
// It is possible to use read multible times.
// Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen)
{
return 0;
}
void ethernet_address(char *mac) {
mbed_mac_address(mac);
}
int ethernet_link(void)
{
return 0;
}
void ethernet_set_link(int speed, int duplex)
{
smsc9220_establish_link();
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
// function to enable the GPIO pin
uint32_t gpio_set(PinName pin) {
return (1);
}
//function to initialise the gpio pin
// this links the board control bits for each pin
// with the object created for the pin
void gpio_init(gpio_t *obj, PinName pin) {
if(pin == NC){ return;}
else {
int pin_value = 0;
obj->pin = pin;
if(pin <=15){
pin_value = pin;
}else if (pin >= 16 && pin <= 31){
pin_value = pin-16;
}else if (pin >= 32 && pin <= 47){
pin_value = pin-32;
}else if (pin >= 48 && pin <= 51){
pin_value = pin-48;
}else if (pin == 100 || pin == 101){
pin_value = pin-100;
}else if (pin == 110 || pin == 111){
pin_value = pin-110;
}else if (pin >= 200 && pin <= 207){
pin_value = pin-200;
}else if (pin >= 210 && pin <= 217){
pin_value = pin-210;
}else if (pin == 303){
pin_value = pin-302;
}else if (pin == 307){
pin_value = pin-307;
}else if (pin == 308){
pin_value = pin-305;
}else if (pin == 309){
pin_value = pin-305;
}else if (pin == 310){
pin_value = pin-305;
}else if (pin == 311){
pin_value = pin-305;
}else if (pin == 323){
pin_value = pin-315;
}else if (pin == 334){
pin_value = pin-325;
}else if (pin == 653){
pin_value = pin-646;
}
obj->mask = 0x1 << pin_value;
obj->pin_number = pin;
if(pin <=15) {
obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
obj->reg_in = &CMSDK_GPIO0->DATA ;
obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
} else if (pin >= 16 && pin <= 31){
obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
obj->reg_in = &CMSDK_GPIO1->DATA ;
obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
} else if (pin >= 32 && pin <= 47){
obj->reg_data = &CMSDK_GPIO2->DATAOUT;
obj->reg_in = &CMSDK_GPIO2->DATA;
obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
} else if (pin >= 48 && pin <= 51){
obj->reg_data = &CMSDK_GPIO3->DATAOUT;
obj->reg_in = &CMSDK_GPIO3->DATA;
obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
} else if (pin == 100 || pin == 101){
obj->reg_data = &MPS2_FPGAIO->LED; //user leds
obj->reg_in = &MPS2_FPGAIO->LED;
} else if (pin == 110 || pin == 111){
obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
}else if (pin >= 200 && pin <= 207){
obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
}else if (pin >= 210 && pin <= 217){
obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
}else if (pin == 303 || pin == 307){
obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
}else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
}else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653
obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits
}
if (pin == 323){
CMSDK_GPIO0->ALTFUNCSET |= 0x0400;
}else if (pin == 334){
CMSDK_GPIO4->ALTFUNCSET |= 0x0001;
}else if (pin == 653){
CMSDK_GPIO1->ALTFUNCSET |= 0x0004;
}
}
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
if(obj->pin >= 0 && obj->pin <= 51)
{
switch (direction) {
case PIN_INPUT : *obj->reg_dirclr = obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
} else {return;}
}
int gpio_is_connected(const gpio_t *obj){
if(obj->pin != (PinName)NC){
return 1;
} else {
return 0;
}
}

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libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
#define CHANNEL_NUM 32
#define CMSDK_GPIO_0 CMSDK_GPIO0
#define CMSDK_GPIO_1 CMSDK_GPIO1
#define PININT_IRQ 0
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) {
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if (ch_bit <16){
if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_0->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
if (ch_bit>=16) {
if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_1->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
void gpio0_irq0(void) {handle_interrupt_in(0);}
void gpio0_irq1(void) {handle_interrupt_in(1);}
void gpio0_irq2(void) {handle_interrupt_in(2);}
void gpio0_irq3(void) {handle_interrupt_in(3);}
void gpio0_irq4(void) {handle_interrupt_in(4);}
void gpio0_irq5(void) {handle_interrupt_in(5);}
void gpio0_irq6(void) {handle_interrupt_in(6);}
void gpio0_irq7(void) {handle_interrupt_in(7);}
void gpio0_irq8(void) {handle_interrupt_in(8);}
void gpio0_irq9(void) {handle_interrupt_in(9);}
void gpio0_irq10(void) {handle_interrupt_in(10);}
void gpio0_irq11(void) {handle_interrupt_in(11);}
void gpio0_irq12(void) {handle_interrupt_in(12);}
void gpio0_irq13(void) {handle_interrupt_in(13);}
void gpio0_irq14(void) {handle_interrupt_in(14);}
void gpio0_irq15(void) {handle_interrupt_in(15);}
void gpio1_irq0(void) {handle_interrupt_in(16);}
void gpio1_irq1(void) {handle_interrupt_in(17);}
void gpio1_irq2(void) {handle_interrupt_in(18);}
void gpio1_irq3(void) {handle_interrupt_in(19);}
void gpio1_irq4(void) {handle_interrupt_in(20);}
void gpio1_irq5(void) {handle_interrupt_in(21);}
void gpio1_irq6(void) {handle_interrupt_in(22);}
void gpio1_irq7(void) {handle_interrupt_in(23);}
void gpio1_irq8(void) {handle_interrupt_in(24);}
void gpio1_irq9(void) {handle_interrupt_in(25);}
void gpio1_irq10(void) {handle_interrupt_in(26);}
void gpio1_irq11(void) {handle_interrupt_in(27);}
void gpio1_irq12(void) {handle_interrupt_in(28);}
void gpio1_irq13(void) {handle_interrupt_in(29);}
void gpio1_irq14(void) {handle_interrupt_in(30);}
void gpio1_irq15(void) {handle_interrupt_in(31);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) {return -1;}
else {
irq_handler = handler;
int found_free_channel = 0;
int i = 0;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) return -1;
/* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h
*/
if (pin <16)
{
CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
}
if (pin >= 16)
{
CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
}
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0: channels_irq = &gpio0_irq0; break;
case 1: channels_irq = &gpio0_irq1; break;
case 2: channels_irq = &gpio0_irq2; break;
case 3: channels_irq = &gpio0_irq3; break;
case 4: channels_irq = &gpio0_irq4; break;
case 5: channels_irq = &gpio0_irq5; break;
case 6: channels_irq = &gpio0_irq6; break;
case 7: channels_irq = &gpio0_irq7; break;
case 8: channels_irq = &gpio0_irq8; break;
case 9: channels_irq = &gpio0_irq9; break;
case 10: channels_irq = &gpio0_irq10; break;
case 11: channels_irq = &gpio0_irq11; break;
case 12: channels_irq = &gpio0_irq12; break;
case 13: channels_irq = &gpio0_irq13; break;
case 14: channels_irq = &gpio0_irq14; break;
case 15: channels_irq = &gpio0_irq15; break;
case 16: channels_irq = &gpio1_irq0; break;
case 17: channels_irq = &gpio1_irq1; break;
case 18: channels_irq = &gpio1_irq2; break;
case 19: channels_irq = &gpio1_irq3; break;
case 20: channels_irq = &gpio1_irq4; break;
case 21: channels_irq = &gpio1_irq5; break;
case 22: channels_irq = &gpio1_irq6; break;
case 23: channels_irq = &gpio1_irq7; break;
case 24: channels_irq = &gpio1_irq8; break;
case 25: channels_irq = &gpio1_irq9; break;
case 26: channels_irq = &gpio1_irq10; break;
case 27: channels_irq = &gpio1_irq11; break;
case 28: channels_irq = &gpio1_irq12; break;
case 29: channels_irq = &gpio1_irq13; break;
case 30: channels_irq = &gpio1_irq14; break;
case 31: channels_irq = &gpio1_irq15; break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
}
void gpio_irq_free(gpio_irq_t *obj) {
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt
if (obj->ch <16)
{
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
{
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
}
if (obj->ch >= 16)
{
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
{
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
// Edge trigger
if (obj->ch <16)
{
CMSDK_GPIO_0->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_0->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
}
}
if (obj->ch >= 16)
{
CMSDK_GPIO_1->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
}
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}

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libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
uint32_t pin_number;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr;
__IO uint32_t *reg_data;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
if (value){
*obj->reg_data |= (obj->mask);
} else {
*obj->reg_data &= ~(obj->mask);
}
}
static inline int gpio_read(gpio_t *obj) {
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "SMM_MPS2.h"
#include "wait_api.h"
#include "fpga.h"
// Types
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
// TSC I2C controller
#define TSC_I2C_ADDR 0x82
// AACI I2C controller I2C address
#define AAIC_I2C_ADDR 0x96
// LM75B I2C address
#define LM75_I2C_ADDR 0x90
// MMA7660 I2C address
#define MMA7660_I2C_ADDR 0x98
// Timing Delays
#define TSC_TSU 15 // Setup delay 600nS min
#define AAIC_TSU 25 // Setup delay 1000nS min
#define SHIELD_TSU 25 // Setup delay 1000nS min
static const PinMap PinMap_I2C_SDA[] = {
{TSC_SDA, I2C_0, 0},
{AUD_SDA, I2C_1, 0},
{SHIELD_0_SDA, I2C_2, 0},
{SHIELD_1_SDA, I2C_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{TSC_SCL, I2C_0, 0},
{AUD_SCL, I2C_1, 0},
{SHIELD_0_SCL, I2C_2, 0},
{SHIELD_1_SCL, I2C_3, 0},
{NC , NC, 0}
};
static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
{
int loop;
switch ((int)obj->i2c) {
case I2C_0:
obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU);
for (loop = 0; loop < 8; loop++)
{
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA;
else
obj->i2c->CONTROLC = SDA;
i2c_delay(TSC_TSU);
obj->i2c->CONTROLS = SCL;
i2c_delay(TSC_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU);
}
obj->i2c->CONTROLS = SDA;
i2c_delay(TSC_TSU);
break;
case I2C_1:
for (loop = 0; loop < 8; loop++) {
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(AAIC_TSU);
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA;
else
obj->i2c->CONTROLC = SDA;
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL;
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
}
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SDA;
i2c_delay(AAIC_TSU);
break;
case I2C_2:
case I2C_3:
obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU);
for (loop = 0; loop < 8; loop++)
{
if (c & (1 << (7 - loop)))
obj->i2c->CONTROLS = SDA;
else
obj->i2c->CONTROLC = SDA;
i2c_delay(SHIELD_TSU);
obj->i2c->CONTROLS = SCL;
i2c_delay(SHIELD_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU);
}
obj->i2c->CONTROLS = SDA;
i2c_delay(SHIELD_TSU);
break;
}
}
static inline unsigned char i2c_receive_byte(i2c_t *obj)
{
int data_receive_byte, loop;
switch ((int)obj->i2c) {
case I2C_0:
obj->i2c->CONTROLS = SDA;
i2c_delay(TSC_TSU);
data_receive_byte = 0;
for (loop = 0; loop < 8; loop++)
{
obj->i2c->CONTROLS = SCL;
i2c_delay(TSC_TSU);
if ((obj->i2c->CONTROL & SDA))
data_receive_byte += (1 << (7 - loop));
obj->i2c->CONTROLC = SCL;
i2c_delay(TSC_TSU);
}
obj->i2c->CONTROLC = SDA;
i2c_delay(TSC_TSU);
break;
case I2C_1:
obj->i2c->CONTROLS = SDA;
data_receive_byte = 0;
for (loop = 0; loop < 8; loop++) {
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLS = SCL | SDA;
i2c_delay(AAIC_TSU);
if ((obj->i2c->CONTROL & SDA))
data_receive_byte += (1 << (7 - loop));
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SCL;
}
i2c_delay(AAIC_TSU);
obj->i2c->CONTROLC = SDA;
i2c_delay(AAIC_TSU);
break;
case I2C_2:
case I2C_3:
obj->i2c->CONTROLS = SDA;
i2c_delay(SHIELD_TSU);
data_receive_byte = 0;
for (loop = 0; loop < 8; loop++)
{
obj->i2c->CONTROLS = SCL;
i2c_delay(SHIELD_TSU);
if ((obj->i2c->CONTROL & SDA))
data_receive_byte += (1 << (7 - loop));
obj->i2c->CONTROLC = SCL;
i2c_delay(SHIELD_TSU);
}
obj->i2c->CONTROLC = SDA;
i2c_delay(SHIELD_TSU);
break;
}
return data_receive_byte;
}
static inline int i2c_receive_ack(i2c_t *obj)
{
int nack;
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
nack = obj->i2c->CONTROL & SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
if(nack==0)
return 1;
return 0;
}
static inline void i2c_send_nack(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
}
static inline void i2c_send_ack(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
// determine the SPI to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c = (MPS2_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
if ((int)obj->i2c == NC) {
error("I2C pin mapping failed");
}
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
switch ((int)obj->i2c) {
case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0xC000; break;
case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x00C0; break;
}
}
int i2c_start(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA | SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
return 0;
}
int i2c_start_tsc(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLC = SCL;
i2c_delay(delay_value);
return 0;
}
int i2c_stop(i2c_t *obj)
{
int delay_value;
switch ((int)obj->i2c) {
case I2C_0: delay_value = TSC_TSU; break;
case I2C_1: delay_value = AAIC_TSU; break;
case I2C_2: delay_value = SHIELD_TSU; break;
case I2C_3: delay_value = SHIELD_TSU; break;
}
// Actual stop bit
i2c_delay(delay_value);
obj->i2c->CONTROLC = SDA;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SCL;
i2c_delay(delay_value);
obj->i2c->CONTROLS = SDA;
i2c_delay(delay_value);
return 0;
}
void i2c_frequency(i2c_t *obj, int hz) {
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
unsigned int loop, rxdata;
int sadr, ack, bytes_read;
rxdata=0;
switch ((int)obj->i2c) {
case I2C_0:
sadr = TSC_I2C_ADDR;
break;
case I2C_1:
sadr = AAIC_I2C_ADDR;
break;
case I2C_2:
case I2C_3:
sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR;
break;
}
bytes_read = 0;
// Start bit
i2c_start(obj);
switch ((int)obj->i2c) {
case I2C_0:
// Set serial and register address
i2c_send_byte(obj,sadr);
ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj);
// Stop bit
i2c_stop(obj);
// Start bit
i2c_start_tsc(obj);
// Read from I2C address
i2c_send_byte(obj,sadr | 1);
ack += i2c_receive_ack(obj);
rxdata = (i2c_receive_byte(obj) & 0xFF);
data[((length-1)-bytes_read)] = (char)rxdata;
bytes_read++;
// Read multiple bytes
if ((length > 1) && (length < 5))
{
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK
i2c_send_ack(obj);
// Next byte
//rxdata = ((rxdata << 8) & 0xFFFFFF00);
//rxdata |= (i2c_receive_byte(obj) & 0xFF);
rxdata = i2c_receive_byte(obj);
data[(length-1)-bytes_read] = (char)rxdata;
bytes_read++;
}
}
break;
case I2C_1:
// Set serial and register address
i2c_send_byte(obj,sadr);
ack += i2c_receive_ack(obj);
i2c_send_byte(obj, address);
ack += i2c_receive_ack(obj);
// Stop bit
i2c_stop(obj);
// Start bit
i2c_start_tsc(obj);
// Fall through to read data
case I2C_2:
case I2C_3:
// Read from preset register address pointer
i2c_send_byte(obj,sadr | 1);
ack += i2c_receive_ack(obj);
rxdata = i2c_receive_byte(obj);
data[bytes_read] = (char)rxdata;
bytes_read++;
// Read multiple bytes
if ((length > 1) && (length < 5))
{
for (loop = 1; loop <= (length - 1); loop++)
{
// Send ACK
i2c_send_ack(obj);
// Next byte
rxdata = i2c_receive_byte(obj);
data[loop] = (char)rxdata;
bytes_read++;
}
}
break;
}
i2c_send_nack(obj);
i2c_stop(obj); // Actual stop bit
return bytes_read;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int ack=0;
int sadr;
char * ptr;
char addr;
ptr = (char*)data;
switch ((int)obj->i2c)
{
case I2C_0:
sadr = TSC_I2C_ADDR;
addr = address;
break;
case I2C_1:
sadr = AAIC_I2C_ADDR;
addr = address;
break;
case I2C_2:
case I2C_3:
sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR;
addr = *ptr++;
break;
}
// printf("adr = %x, reg = %x\n",sadr, address);
i2c_start(obj);
// Set serial and register address
i2c_send_byte(obj,sadr);
ack += i2c_receive_ack(obj);
i2c_send_byte(obj, addr);
ack += i2c_receive_ack(obj);
for(int i = 1; i<length; i++)
{
i2c_send_byte(obj, *ptr++);
ack += i2c_receive_ack(obj);
}
i2c_stop(obj);
if(ack==3) { return 1; }
else{ return 0; }
}
void i2c_reset(i2c_t *obj) {
i2c_stop(obj);
}
int i2c_byte_read(i2c_t *obj, int last) {
return 0;
}
int i2c_byte_write(i2c_t *obj, int data) {
return 0;
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t ch;
};
struct port_s {
__IO uint32_t *reg_dir;
__IO uint32_t *reg_dirclr;
__IO uint32_t *reg_out;
__IO uint32_t *reg_in;
PortName port;
uint32_t mask;
};
struct serial_s {
CMSDK_UART_TypeDef *uart;
int index;
};
struct i2c_s {
MPS2_I2C_TypeDef *i2c;
};
struct tsc_s {
MPS2_I2C_TypeDef *tsc;
};
struct audio_s {
MPS2_I2S_TypeDef *audio_I2S;
MPS2_I2C_TypeDef *audio_I2C;
};
struct spi_s {
MPS2_SSP_TypeDef *spi;
};
struct clcd_s {
MPS2_SSP_TypeDef *clcd;
};
struct analogin_s {
ADCName adc;
MPS2_SSP_TypeDef *adc_spi;
PinName pin;
uint32_t pin_number;
__IO uint32_t address;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
void pin_function(PinName pin, int function) {
MBED_ASSERT(pin != (PinName)NC);
}
void pin_mode(PinName pin, PinMode mode) {
MBED_ASSERT(pin != (PinName)NC);
}

68
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/port_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
PinName port_pin(PortName port, int pin_n) {
return (PinName)((port << PORT_SHIFT) | pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
obj->port = port;
obj->mask = mask;
CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10));
obj->reg_in = &port_reg->DATAOUT;
obj->reg_dir = &port_reg->OUTENABLESET;
obj->reg_dirclr = &port_reg->OUTENABLECLR;
uint32_t i;
// The function is set per pin: reuse gpio logic
for (i=0; i<16; i++) {
if (obj->mask & (1<<i)) {
gpio_set(port_pin(obj->port, i));
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode) {
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i=0; i<32; i++) {
if (obj->mask & (1<<i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir) {
switch (dir) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
}
void port_write(port_t *obj, int value) {
*obj->reg_in = value;
}
int port_read(port_t *obj) {
return (*obj->reg_in);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include <math.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_api.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
static const PinMap PinMap_UART_TX[] = {
{USBTX , UART_0, 0},
{XB_TX , UART_1, 0},
{SH0_TX , UART_2, 0},
{SH1_TX , UART_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{USBRX , UART_0, 0},
{XB_RX , UART_1, 0},
{SH0_RX , UART_2, 0},
{SH1_RX , UART_3, 0},
{NC , NC , 0}
};
#define UART_NUM 4
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t count, rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
if ((int)uart == NC) {
error("Serial pinout mapping failed");
}
obj->uart = (CMSDK_UART_TypeDef *)uart;
//set baud rate and enable Uart in normarl mode (RX and TX enabled)
switch (uart)
{
case UART_0: //UART HEADER
{
CMSDK_UART1->CTRL = 0x0; // Disable UART when changing configuration
if((int)tx != NC)
{
CMSDK_UART1->CTRL |= 0x01; // TX enable
} else {
CMSDK_UART1->CTRL &= 0xFFFE; // TX disable
}
if((int)rx != NC)
{
CMSDK_UART1->CTRL |= 0x02; // RX enable
} else {
CMSDK_UART1->CTRL &= 0xFFFD; // RX disable
}
}
break;
case UART_1: //XBEE SOCKET UART
{
CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC)
{
CMSDK_UART3->CTRL = 0x1; // TX enable
CMSDK_GPIO4->ALTFUNCSET |= 0x0100;
}
if((int)rx != NC)
{
CMSDK_UART3->CTRL |= 0x2; // RX enable
CMSDK_GPIO4->ALTFUNCSET |= 0x0080;
}
}
break;
case UART_2: //Sheild0 UART
{
CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration
if((int)uart_tx != NC)
{
CMSDK_UART0->CTRL |= 0x01; // TX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0002;
}
if((int)uart_rx != NC)
{
CMSDK_UART0->CTRL |= 0x02; // RX enable
CMSDK_GPIO0->ALTFUNCSET |= 0x0001;
}
}
break;
case UART_3: //Sheild1 UART
{
CMSDK_UART2->CTRL = 0x00; // Disable UART when changing configuration
if((int)tx != NC)
{
CMSDK_UART2->CTRL = 0x1; // TX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0002;
}
if((int)rx != NC)
{
CMSDK_UART2->CTRL |= 0x2; // RX enable
CMSDK_GPIO1->ALTFUNCSET |= 0x0001;
}
}
break;
}
// set default baud rate and format
serial_baud (obj, 9600);
// pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) {
case UART_0: obj->index = 0; break;
case UART_1: obj->index = 1; break;
case UART_2: obj->index = 2; break;
case UART_3: obj->index = 3; break;
}
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
serial_set_flow_control(obj, FlowControlNone, NC, NC);
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
uart_data[obj->index].serial_irq_id = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
// The MPS2 has a simple divider to control the baud rate. The formula is:
//
// Baudrate = PCLK / BAUDDIV
//
// PCLK = 24 Mhz
// so for a desired baud rate of 9600
// 24000000 / 9600 = 2500
//
//check to see if minimum baud value entered
int baudrate_div = 0;
baudrate_div = SystemCoreClock / baudrate;
if(baudrate >= 16){
switch ((int)obj->uart) {
case UART_0: CMSDK_UART1->BAUDDIV = baudrate_div; break;
case UART_1: CMSDK_UART3->BAUDDIV = baudrate_div; break;
case UART_2: CMSDK_UART0->BAUDDIV = baudrate_div; break;
case UART_3: CMSDK_UART2->BAUDDIV = baudrate_div; break;
default: error("serial_baud"); break;
}
} else {
error("serial_baud");
}
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) {
SerialIrq irq_type;
switch (intstatus)
{
case 1:
{
irq_type = TxIrq;
}
break;
case 2:
{
irq_type = RxIrq;
}
break;
default: return;
} /* End of Switch */
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin))
{
gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api)
{
/* Disable Rx interrupt */
puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
}
}
if (uart_data[index].serial_irq_id != 0)
{
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
{
irq_handler(uart_data[index].serial_irq_id, irq_type);
}
}
if( irq_type == TxIrq )
{
/* Clear the TX interrupt Flag */
puart->INTCLEAR |= 0x01;
}
else
{
/* Clear the Rx interupt Flag */
puart->INTCLEAR |= 0x02;
}
}
void uart0_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART1);}
void uart1_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART3);}
void uart2_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART0);}
void uart3_irq() {uart_irq(CMSDK_UART2->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART2);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
uart_data[obj->index].serial_irq_id = id;
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart)
{
case UART_0:
irq_n = UART0_IRQn;
vector = (uint32_t)&uart0_irq;
break;
case UART_1:
irq_n = UART1_IRQn;
vector = (uint32_t)&uart1_irq;
break;
case UART_2:
{
irq_n = UART2_IRQn;
vector = (uint32_t)&uart2_irq;
}
break;
case UART_3:
{
irq_n = UART3_IRQn;
vector = (uint32_t)&uart3_irq;
}
break;
}
if (enable)
{
if (irq == TxIrq)
{
/* set TX interrupt enable in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
}
else
{
/* set Rx interrupt on in CTRL REG */
obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
}
else if ((irq == TxIrq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0))
{ /* Disable IRQ */
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->CTRL &= ~(1 << (irq + 2));
all_disabled = (obj->uart->CTRL & (1 << (other_irq + 2))) == 0;
if (all_disabled)
{
NVIC_DisableIRQ(irq_n);
}
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
if (RxIrq == irq)
uart_data[obj->index].rx_irq_set_api = enable;
serial_irq_set_internal(obj, irq, enable);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (serial_readable(obj) == 0);
int data = obj->uart->DATA;
return data;
}
void serial_putc(serial_t *obj, int c) {
while (serial_writable(obj));
obj->uart->DATA = c;
}
int serial_readable(serial_t *obj) {
return obj->uart->STATE & 0x2;
}
int serial_writable(serial_t *obj) {
return obj->uart->STATE & 0x1;
}
void serial_clear(serial_t *obj) {
obj->uart->DATA = 0x00;
}
void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj) {
}
void serial_break_clear(serial_t *obj) {
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <math.h>
#include "spi_api.h"
#include "spi_def.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "wait_api.h"
static const PinMap PinMap_SPI_SCLK[] = {
{SCLK_SPI , SPI_0, 0},
{CLCD_SCLK , SPI_1, 0},
{ADC_SCLK , SPI_2, 0},
{SHIELD_0_SPI_SCK , SPI_3, 0},
{SHIELD_1_SPI_SCK , SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{MOSI_SPI, SPI_0, 0},
{CLCD_MOSI, SPI_1, 0},
{ADC_MOSI, SPI_2, 0},
{SHIELD_0_SPI_MOSI, SPI_3, 0},
{SHIELD_1_SPI_MOSI, SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{MISO_SPI, SPI_0, 0},
{CLCD_MISO, SPI_1, 0},
{ADC_MISO, SPI_2, 0},
{SHIELD_0_SPI_MISO, SPI_3, 0},
{SHIELD_1_SPI_MISO, SPI_4, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{SSEL_SPI, SPI_0, 0},
{CLCD_SSEL, SPI_1, 0},
{ADC_SSEL, SPI_2, 0},
{SHIELD_0_SPI_nCS, SPI_3, 0},
{SHIELD_1_SPI_nCS, SPI_4, 0},
{NC , NC , 0}
};
static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
int altfunction[4];
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
// enable power and clocking
switch ((int)obj->spi) {
case (int)SPI_0:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_1:
/* Configure SSP used for LCD */
obj->spi->CR1 = 0; /* Synchronous serial port disable */
obj->spi->DMACR = 0; /* Disable FIFO DMA */
obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
(1ul << 1) ); /* Clear SSPRTINTR interrupt */
obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
(0ul << 4) | /* Motorola frame format */
(0ul << 6) | /* CPOL = 0 */
(0ul << 7) | /* CPHA = 0 */
(1ul << 8) ); /* Set serial clock rate */
obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
(0ul << 2) ); /* Device configured as master */
break;
case (int)SPI_2:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_3:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_4:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
}
if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
// enable alt function
switch ((int)obj->spi) {
case (int)SPI_2:
CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<5 | altfunction[0]<<4 | altfunction[1]<<3 | altfunction[3]<<2);
break;
case (int)SPI_3:
CMSDK_GPIO0->ALTFUNCSET |= (altfunction[2]<<13 | altfunction[1]<<12 | altfunction[0]<<11 | altfunction[3]<<10);
break;
case (int)SPI_4:
CMSDK_GPIO4->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[1]<<2 | altfunction[0]<<1 | altfunction[3]);
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
ssp_disable(obj);
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error");
}
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
// set it up
int DSS = bits - 1; // DSS (data select size)
int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
int SPH = (phase) ? 1 : 0; // SPH - clock out phase
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF);
tmp |= DSS << 0
| FRF << 4
| SPO << 6
| SPH << 7;
obj->spi->CR0 = tmp;
tmp = obj->spi->CR1;
tmp &= ~(0xD);
tmp |= 0 << 0 // LBM - loop back mode - off
| ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
| 0 << 3; // SOD - slave output disable - na
obj->spi->CR1 = tmp;
ssp_enable(obj);
}
void spi_frequency(spi_t *obj, int hz) {
ssp_disable(obj);
uint32_t PCLK = SystemCoreClock;
int prescaler;
for (prescaler = 2; prescaler <= 254; prescaler += 2) {
int prescale_hz = PCLK / prescaler;
// calculate the divider
int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
// check we can support the divider
if (divider < 256) {
// prescaler
obj->spi->CPSR = prescaler;
// divider
obj->spi->CR0 &= ~(0xFFFF << 8);
obj->spi->CR0 |= (divider - 1) << 8;
ssp_enable(obj);
return;
}
}
error("Couldn't setup requested SPI frequency");
}
static inline int ssp_disable(spi_t *obj) {
return obj->spi->CR1 &= ~(1 << 1);
}
static inline int ssp_enable(spi_t *obj) {
return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
}
static inline int ssp_readable(spi_t *obj) {
return obj->spi->SR & (1 << 2);
}
static inline int ssp_writeable(spi_t *obj) {
return obj->spi->SR & SSP_SR_BSY_Msk;
}
static inline void ssp_write(spi_t *obj, int value) {
obj->spi->DR = value;
while (ssp_writeable(obj));
}
static inline int ssp_read(spi_t *obj) {
int read_DR = obj->spi->DR;
return read_DR;
}
static inline int ssp_busy(spi_t *obj) {
return (obj->spi->SR & (1 << 4)) ? (1) : (0);
}
int spi_master_write(spi_t *obj, int value) {
ssp_write(obj, value);
while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
return (ssp_read(obj));
}
int spi_slave_receive(spi_t *obj) {
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj) {
return obj->spi->DR;
}
void spi_slave_write(spi_t *obj, int value) {
while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value;
}
int spi_busy(spi_t *obj) {
return ssp_busy(obj);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* ----------------------------------------------------------------
* File: apspi.h
* Release: Version 2.0
* ----------------------------------------------------------------
*
* SSP interface Support
* =====================
*/
#define SSPCS_BASE (0x4002804C) // SSP chip select register
#define SSP_BASE (0x40020000) // SSP Prime Cell
#define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
#define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
#define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
#define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
#define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
#define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
#define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
#define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
#define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
#define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
#define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
// SSPCR0 Control register 0
#define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
#define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
#define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
#define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
#define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
#define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
// SSPCR1 Control register 1
#define SSPCR1_SOD 0x0008 // Slave Output mode Disable
#define SSPCR1_MS 0x0004 // Master or Slave mode
#define SSPCR1_SSE 0x0002 // Serial port enable
#define SSPCR1_LBM 0x0001 // Loop Back Mode
// SSPSR Status register
#define SSPSR_BSY 0x0010 // Busy
#define SSPSR_RFF 0x0008 // Receive FIFO full
#define SSPSR_RNE 0x0004 // Receive FIFO not empty
#define SSPSR_TNF 0x0002 // Transmit FIFO not full
#define SSPSR_TFE 0x0001 // Transmit FIFO empty
// SSPCPSR Clock prescale register
#define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
// SSPIMSC Interrupt mask set and clear register
#define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
#define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
#define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
#define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
// SSPRIS Raw interrupt status register
#define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
#define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
#define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
#define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
// SSPMIS Masked interrupt status register
#define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
#define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
#define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
#define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
// SSPICR Interrupt clear register
#define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
#define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
// SSPDMACR DMA control register
#define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
#define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
// SPICS register (0=Chip Select low)
#define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
// SPI defaults
#define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
// EEPROM instruction set
#define EEWRSR 0x0001 // Write status
#define EEWRITE 0x0002 // Write data
#define EEREAD 0x0003 // Read data
#define EEWDI 0x0004 // Write disable
#define EEWREN 0x0006 // Write enable
#define EERDSR 0x0005 // Read status
// EEPROM status register flags
#define EERDSR_WIP 0x0001 // Write in process
#define EERDSR_WEL 0x0002 // Write enable latch
#define EERDSR_BP0 0x0004 // Block protect 0
#define EERDSR_BP1 0x0008 // Block protect 1
#define EERDSR_WPEN 0x0080 // Write protect enable
/* ----------------------------------------------------------------
*
* Color LCD Support
* =================
*/
// Color LCD Controller Internal Register addresses
#define LSSPCS_BASE (0x4002804C) // LSSP chip select register
#define LSSP_BASE (0x40021000) // LSSP Prime Cell
#define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
#define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
#define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
#define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
#define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
#define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
#define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
#define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
#define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
#define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
#define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
// LSSPCR0 Control register 0
#define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
#define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
#define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
#define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
#define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
#define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
// LSSPCR1 Control register 1
#define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
#define LSSPCR1_MS 0x0004 // Master or Slave mode
#define LSSPCR1_SSE 0x0002 // Serial port enable
#define LSSPCR1_LBM 0x0001 // Loop Back Mode
// LSSPSR Status register
#define LSSPSR_BSY 0x0010 // Busy
#define LSSPSR_RFF 0x0008 // Receive FIFO full
#define LSSPSR_RNE 0x0004 // Receive FIFO not empty
#define LSSPSR_TNF 0x0002 // Transmit FIFO not full
#define LSSPSR_TFE 0x0001 // Transmit FIFO empty
// LSSPCPSR Clock prescale register
#define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
// SPICS register
#define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
#define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
#define LCD_RESET 0x0008 // RESET (CLCD_RESET)
#define LCD_RS 0x0010 // RS (CLCD_RS)
#define LCD_RD 0x0020 // RD (CLCD_RD)
#define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
// SPI defaults
#define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
#define LSPI_START (0x70) // Start byte for SPI transfer
#define LSPI_RD (0x01) // WR bit 1 within start
#define LSPI_WR (0x00) // WR bit 0 within start
#define LSPI_DATA (0x02) // RS bit 1 within start byte
#define LSPI_INDEX (0x00) // RS bit 0 within start byte
// Screen size
#define LCD_WIDTH 320 // Screen Width (in pixels)
#define LCD_HEIGHT 240 // Screen Height (in pixels)

84
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c Normal file
View File

@ -0,0 +1,84 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#define US_TICKER_TIMER1 CMSDK_DUALTIMER1
#define US_TICKER_TIMER2 CMSDK_DUALTIMER2
#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn
int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
US_TICKER_TIMER2->TimerControl = 0x00; // disable timer
US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF;
US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF;
US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter
US_TICKER_TIMER1->TimerControl |= 0x80; // enable counter
US_TICKER_TIMER2->TimerControl |= 0x80; // enable counter
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
uint32_t us_ticker_read() {
uint32_t return_value = 0;
if (!us_ticker_inited)
us_ticker_init();
return_value = ((~US_TICKER_TIMER2->TimerValue)/24);
return return_value;
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
int delta = 0;
if (!us_ticker_inited)
us_ticker_init();
delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past:
us_ticker_irq_handler();
return;
}
// enable interrupt
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
US_TICKER_TIMER1->TimerLoad = (delta)*24; //initialise the timer value
US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
}
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER1->TimerControl &= 0xDF;
US_TICKER_TIMER2->TimerControl &= 0xDF;
}
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER1->TimerIntClr = 0x1;
US_TICKER_TIMER2->TimerIntClr = 0x1;
}

30
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h
View File

@ -24,13 +24,17 @@ extern "C" {
typedef enum {
UART_0 = (int)CMSDK_UART0_BASE,
UART_1 = (int)CMSDK_UART1_BASE
UART_1 = (int)CMSDK_UART1_BASE,
UART_2 = (int)CMSDK_UART3_BASE,
UART_3 = (int)CMSDK_UART4_BASE
} UARTName;
typedef enum {
I2C_0 = (int)MPS2_TS_I2C,
I2C_1 = (int)MPS2_AAIC_I2C
I2C_0 = (int)MPS2_TSC_I2C_BASE,
I2C_1 = (int)MPS2_AAIC_I2C_BASE,
I2C_2 = (int)MPS2_SHIELD0_I2C_BASE,
I2C_3 = (int)MPS2_SHIELD1_I2C_BASE
} I2CName;
typedef enum {
@ -41,12 +45,19 @@ typedef enum {
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
ADC0_7,
ADC0_8,
ADC0_9,
ADC0_10,
ADC0_11
} ADCName;
typedef enum {
SPI_0 = (int)MPS2_SSP1,
SPI_1 = (int)MPS2_SSP0
SPI_0 = (int)MPS2_SSP1_BASE,
SPI_1 = (int)MPS2_SSP0_BASE,
SPI_2 = (int)MPS2_SSP2_BASE,
SPI_3 = (int)MPS2_SSP3_BASE,
SPI_4 = (int)MPS2_SSP4_BASE
} SPIName;
typedef enum {
@ -68,8 +79,9 @@ typedef enum {
#define STDIO_UART UART_0
#define MBED_UART0 USBTX, USBRX
#define MBED_UART1 UART_TX1, UART_RX1
#define MBED_UART2 UART_TX2, UART_RX2
#define MBED_UART1 XB_TX, XB_RX
#define MBED_UART2 SH0_TX, SH0_RX
#define MBED_UART3 SH1_TX, SH1_RX
#define MBED_UARTUSB USBTX, USBRX
#ifdef __cplusplus

309
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h
View File

@ -23,131 +23,206 @@ extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// MPS2 EXP Pin Names
EXP0 = 0,
EXP1 = 1,
EXP2 = 2,
EXP3 = 3,
EXP4 = 4,
EXP5 = 5,
EXP6 = 6,
EXP7 = 7,
EXP8 = 8,
EXP9 = 9,
EXP10 = 10,
EXP11 = 11,
EXP12 = 12,
EXP13 = 13,
EXP14 = 14,
EXP15 = 15,
EXP16 = 16,
EXP17 = 17,
EXP18 = 18,
EXP19 = 19,
EXP20 = 20,
EXP21 = 21,
EXP22 = 22,
EXP23 = 23,
EXP24 = 24,
EXP25 = 25,
EXP26 = 26,
EXP27 = 27,
EXP28 = 28,
EXP29 = 29,
EXP30 = 30,
EXP31 = 31,
EXP32 = 32,
EXP33 = 33,
EXP34 = 34,
EXP35 = 35,
EXP36 = 36,
EXP37 = 37,
EXP38 = 38,
EXP39 = 39,
EXP40 = 40,
EXP41 = 41,
EXP42 = 42,
EXP43 = 43,
EXP44 = 44,
EXP45 = 45,
EXP46 = 46,
EXP47 = 47,
EXP48 = 48,
EXP49 = 49,
EXP50 = 50,
EXP51 = 51,
EXP0 = 0,
EXP1 = 1,
EXP2 = 2,
EXP3 = 3,
EXP4 = 4,
EXP5 = 5,
EXP6 = 6,
EXP7 = 7,
EXP8 = 8,
EXP9 = 9,
EXP10 = 10,
EXP11 = 11,
EXP12 = 12,
EXP13 = 13,
EXP14 = 14,
EXP15 = 15,
EXP16 = 16,
EXP17 = 17,
EXP18 = 18,
EXP19 = 19,
EXP20 = 20,
EXP21 = 21,
EXP22 = 22,
EXP23 = 23,
EXP24 = 24,
EXP25 = 25,
EXP26 = 26,
EXP27 = 27,
EXP28 = 28,
EXP29 = 29,
EXP30 = 30,
EXP31 = 31,
EXP32 = 32,
EXP33 = 33,
EXP34 = 34,
EXP35 = 35,
EXP36 = 36,
EXP37 = 37,
EXP38 = 38,
EXP39 = 39,
EXP40 = 40,
EXP41 = 41,
EXP42 = 42,
EXP43 = 43,
EXP44 = 44,
EXP45 = 45,
EXP46 = 46,
EXP47 = 47,
EXP48 = 48,
EXP49 = 49,
EXP50 = 50,
EXP51 = 51,
// Other mbed Pin Names
//LEDs on mps2
//user leds
USERLED1 = 100,
USERLED2 = 101,
//user switches
USERSW1 = 110,
USERSW2 = 111,
//mcc leds
LED1 = 200,
LED2 = 201,
LED3 = 202,
LED4 = 203,
LED5 = 204,
LED6 = 205,
LED7 = 206,
LED8 = 207,
//MCC Switches
SW1 = 210,
SW2 = 211,
SW3 = 212,
SW4 = 213,
SW5 = 214,
SW6 = 215,
SW7 = 216,
SW8 = 217,
//MPS2 SPI header pins j21
MOSI_SPI = 300,
MISO_SPI = 301,
SCLK_SPI = 302,
SSEL_SPI = 303,
//MPS2 CLCD SPI
CLCD_MOSI = 304,
CLCD_MISO = 305,
CLCD_SCLK = 306,
CLCD_SSEL = 307,
CLCD_RESET = 308,
CLCD_RS = 309,
CLCD_RD = 310,
CLCD_BL_CTRL = 311,
//MPS2 Uart
USBTX = 400,
USBRX = 401,
UART_TX1 = 402,
UART_RX1 = 403,
UART_TX2 = 404,
UART_RX2 = 405,
//MPS2 I2C touchscreen and audio
TSC_SDA = 500,
TSC_SCL = 501,
AUD_SDA = 502,
AUD_SCL = 503,
// Not connected
NC = (int)0xFFFFFFFF,
//LEDs on mps2
//user leds
USERLED1 = 100,
USERLED2 = 101,
//user switches
USERSW1 = 110,
USERSW2 = 111,
//mcc leds
LED1 = 200,
LED2 = 201,
LED3 = 202,
LED4 = 203,
LED5 = 204,
LED6 = 205,
LED7 = 206,
LED8 = 207,
//MCC Switches
SW1 = 210,
SW2 = 211,
SW3 = 212,
SW4 = 213,
SW5 = 214,
SW6 = 215,
SW7 = 216,
SW8 = 217,
//MPS2 SPI header pins j21
MOSI_SPI = 300,
MISO_SPI = 301,
SCLK_SPI = 302,
SSEL_SPI = 303,
//MPS2 CLCD SPI
CLCD_MOSI = 304,
CLCD_MISO = 305,
CLCD_SCLK = 306,
CLCD_SSEL = 307,
CLCD_RESET = 308,
CLCD_RS = 309,
CLCD_RD = 310,
CLCD_BL_CTRL = 311,
//MPS2 shield 0 SPI
SHIELD_0_SPI_SCK = 320,
SHIELD_0_SPI_MOSI = 321,
SHIELD_0_SPI_MISO = 322,
SHIELD_0_SPI_nCS = 323,
//MPS2 shield 1 SPI
SHIELD_1_SPI_SCK = 331,
SHIELD_1_SPI_MOSI = 332,
SHIELD_1_SPI_MISO = 333,
SHIELD_1_SPI_nCS = 334,
//MPS2 shield ADC SPI
ADC_MOSI = 650,
ADC_MISO = 651,
ADC_SCLK = 652,
ADC_SSEL = 653,
//MPS2 Uart
USBTX = 400,
USBRX = 401,
XB_TX = 402,
XB_RX = 403,
UART_TX2 = 404,
UART_RX2 = 405,
SH0_TX = 406,
SH0_RX = 407,
SH1_TX = 408,
SH1_RX = 409,
//MPS2 I2C touchscreen and audio
TSC_SDA = 500,
TSC_SCL = 501,
AUD_SDA = 502,
AUD_SCL = 503,
//MPS2 I2C for shield
SHIELD_0_SDA = 504,
SHIELD_0_SCL = 505,
SHIELD_1_SDA = 506,
SHIELD_1_SCL = 507,
//MPS2 shield Analog pins
A0_0 = 600,
A0_1 = 601,
A0_2 = 602,
A0_3 = 603,
A0_4 = 604,
A0_5 = 605,
A1_0 = 606,
A1_1 = 607,
A1_2 = 608,
A1_3 = 609,
A1_4 = 610,
A1_5 = 611,
//MPS2 Shield Digital pins
D0_0 = EXP0,
D0_1 = EXP4,
D0_2 = EXP2,
D0_3 = EXP3,
D0_4 = EXP1,
D0_5 = EXP6,
D0_6 = EXP7,
D0_7 = EXP8,
D0_8 = EXP9,
D0_9 = EXP10,
D0_10 = EXP12,
D0_11 = EXP13,
D0_12 = EXP14,
D0_13 = EXP11,
D0_14 = EXP15,
D0_15 = EXP5,
D1_0 = EXP26,
D1_1 = EXP30,
D1_2 = EXP28,
D1_3 = EXP29,
D1_4 = EXP27,
D1_5 = EXP32,
D1_6 = EXP33,
D1_7 = EXP34,
D1_8 = EXP35,
D1_9 = EXP36,
D1_10 = EXP38,
D1_11 = EXP39,
D1_12 = EXP40,
D1_13 = EXP44,
D1_14 = EXP41,
D1_15 = EXP31,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;

21
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c
View File

@ -35,9 +35,8 @@
*/
#include <stdio.h>
#include "wait_api.h"
#include "ETH_MPS2.h"
#include "fpga.h"
// SMSC9220 low-level operations
unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
@ -58,7 +57,7 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
timedout = 50;
do {
val = SMSC9220->BYTE_TEST; // A no-op read.
Sleepms(1);
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
@ -92,7 +91,7 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
timedout = 50;
do {
read = SMSC9220->BYTE_TEST; // A no-op read.
Sleepms(1);
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
@ -126,7 +125,7 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
val = 0;
timedout = 50;
do {
Sleepms(1);
wait_ms(1);
timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val);
} while(timedout && (val & ((unsigned int)1 << 0)));
@ -166,7 +165,7 @@ unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
do {
Sleepms(1);
wait_ms(1);
timedout--;
smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
} while(timedout && (phycmd & (1 << 0)));
@ -197,7 +196,7 @@ unsigned int smsc9220_soft_reset(void)
SMSC9220->HW_CFG |= 1;
do {
Sleepms(1);
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->HW_CFG & 1));
@ -224,7 +223,7 @@ unsigned int smsc9220_wait_eeprom(void)
timedout = 50;
do {
Sleepms(1);
wait_ms(1);
timedout--;
} while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
@ -238,9 +237,9 @@ unsigned int smsc9220_wait_eeprom(void)
/* initialise irqs */
void smsc9220_init_irqs(void)
{
SMSC9220->INT_EN = 0x0;
SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts
SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable.
SMSC9220->INT_EN = 0x0;
SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts
SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable.
}
unsigned int smsc9220_check_phy(void)

12
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c
View File

@ -28,8 +28,8 @@
// Used for I2C drivers
void i2c_delay(unsigned int tick)
{
unsigned int end;
unsigned int start;
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (tick);
@ -50,8 +50,8 @@ void i2c_delay(unsigned int tick)
*/
void Sleepms(unsigned int msec)
{
unsigned int end;
unsigned int start;
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * msec * 1000);
@ -71,8 +71,8 @@ void Sleepms(unsigned int msec)
*/
void Sleepus(unsigned int usec)
{
unsigned int end;
unsigned int start;
unsigned int end;
unsigned int start;
start = MPS2_FPGAIO->COUNTER;
end = start + (25 * usec);

53
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c
View File

@ -89,6 +89,45 @@ int smsc9220_check_macaddress(void)
return error;
}
void smsc9220_print_mac_registers()
{
unsigned int read;
int i;
i = 0;
read = 0;
for(i = 1; i <= 0xC; i++) {
smsc9220_mac_regread(i, &read);
}
return;
}
void smsc9220_print_phy_registers()
{
unsigned short read;
unsigned int i;
i = 0;
read = 0;
for(i = 0; i <= 6; i++) {
smsc9220_phy_regread(i, &read);
}
smsc9220_phy_regread(i = 17, &read);
smsc9220_phy_regread(i = 18, &read);
smsc9220_phy_regread(i = 27, &read);
smsc9220_phy_regread(i = 29, &read);
smsc9220_phy_regread(i = 30, &read);
smsc9220_phy_regread(i = 31, &read);
return;
}
/*----------------------------------------------------------------------------
Ethernet Device initialize
@ -96,13 +135,13 @@ int smsc9220_check_macaddress(void)
int ethernet_transmission(unsigned char * pkt, unsigned int length)
{
smsc9220_xmit_packet(pkt, length);
return 0;
smsc9220_xmit_packet(pkt, length);
return 0;
}
int ethernet_reception(unsigned int *recvbuf, unsigned int *index)
{
return smsc9220_recv_packet((unsigned int *)recvbuf, index);
return smsc9220_recv_packet((unsigned int *)recvbuf, index);
}
int ethernet_mac_address(char *mac)
@ -112,16 +151,16 @@ int ethernet_mac_address(char *mac)
unsigned int ethernet_check_ready(void)
{
return smsc9220_check_ready();
return smsc9220_check_ready();
}
unsigned int ethernet_intf()
{
unsigned int txfifo_inf;
txfifo_inf = SMSC9220->TX_FIFO_INF;
return txfifo_inf;
txfifo_inf = SMSC9220->TX_FIFO_INF;
return txfifo_inf;
}

110
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c Normal file
View File

@ -0,0 +1,110 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define ADC_12BIT_RANGE 0xFFF
static const PinMap PinMap_ADC[] = {
{A0_0, ADC0_0, 0},
{A0_1, ADC0_1, 0},
{A0_2, ADC0_2, 0},
{A0_3, ADC0_3, 0},
{A0_4, ADC0_4, 0},
{A0_5, ADC0_5, 0},
{A1_0, ADC0_6, 0},
{A1_1, ADC0_7, 0},
{A1_2, ADC0_8, 0},
{A1_3, ADC0_9, 0},
{A1_4, ADC0_10, 0},
{A1_5, ADC0_11, 0},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SCLK[] = {
{ADC_SCLK , SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{ADC_MOSI, SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{ADC_MISO, SPI_3, 0},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{ADC_SSEL, SPI_3, 0},
{NC , NC , 0}
};
#define ADC_RANGE ADC_12BIT_RANGE
int analog_spi_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
obj->pin = pin;
obj->pin_number = pin-600;
obj->address = (0x0000 | (pin-600));
SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI);
SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO);
SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK);
SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL);
SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso);
SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel);
obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl);
if(analog_spi_inited == 0){
obj->adc_spi->CR1 = 0;
obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16;
obj->adc_spi->CPSR = SSP_CPSR_DFLT;
obj->adc_spi->IMSC = 0x8;
obj->adc_spi->DMACR = 0;
obj->adc_spi->CR1 = SSP_CR1_SSE_Msk;
obj->adc_spi->ICR = 0x3;
analog_spi_inited = 1;
}
pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI);
pinmap_pinout(ADC_MISO, PinMap_SPI_MISO);
pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK);
pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL);
pinmap_pinout(pin, PinMap_ADC);
}
static inline uint32_t adc_read(analogin_t *obj) {
return 0;
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read(obj);
return 0;
}
uint16_t analogin_read_u16(analogin_t *obj) {
return 0;
}

4
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h
View File

@ -22,14 +22,14 @@
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 0
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_SERIAL_FC 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_I2CSLAVE 0
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1

10
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c
View File

@ -38,7 +38,7 @@
*----------------------------------------------------------------------------*/
int ethernet_init()
{
int error;
int error;
error = 0;
if(smsc9220_check_id()) {
@ -123,7 +123,7 @@ void ethernet_free() {
int ethernet_write(const char *data, int size)
{
return 0;
return 0;
}
int ethernet_send()
@ -145,7 +145,7 @@ int ethernet_receive()
int ethernet_read(char *data, int dlen)
{
return 0;
return 0;
}
void ethernet_address(char *mac) {
@ -154,11 +154,11 @@ void ethernet_address(char *mac) {
int ethernet_link(void)
{
return 0;
return 0;
}
void ethernet_set_link(int speed, int duplex)
{
smsc9220_establish_link();
smsc9220_establish_link();
}

180
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c
View File

@ -18,95 +18,111 @@
// function to enable the GPIO pin
uint32_t gpio_set(PinName pin) {
return (1);
return (1);
}
//function to initialise the gpio pin
// this links the board control bits for each pin
// with the object created for the pin
void gpio_init(gpio_t *obj, PinName pin) {
if(pin == NC){ return;}
else {
int pin_value = 0;
obj->pin = pin;
if(pin <=15){
pin_value = pin;
}else if (pin >= 16 && pin <= 31){
pin_value = pin-16;
}else if (pin >= 32 && pin <= 47){
pin_value = pin-32;
}else if (pin >= 48 && pin <= 51){
pin_value = pin-48;
}else if (pin == 100 || pin == 101){
pin_value = pin-100;
}else if (pin == 110 || pin == 111){
pin_value = pin-110;
}else if (pin >= 200 && pin <= 207){
pin_value = pin-200;
}else if (pin >= 210 && pin <= 217){
pin_value = pin-210;
}else if (pin == 303){
pin_value = pin-302;
}else if (pin == 307){
pin_value = pin-307;
}else if (pin == 308){
pin_value = pin-305;
}else if (pin == 309){
pin_value = pin-305;
}else if (pin == 310){
pin_value = pin-305;
}else if (pin == 311){
pin_value = pin-305;
}
obj->mask = 0x1 << pin_value;
obj->pin_number = pin;
if(pin <=15) {
obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
obj->reg_in = &CMSDK_GPIO0->DATA ;
obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
} else if (pin >= 16 && pin <= 31){
obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
obj->reg_in = &CMSDK_GPIO1->DATA ;
obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
} else if (pin >= 32 && pin <= 47){
obj->reg_data = &CMSDK_GPIO2->DATAOUT;
obj->reg_in = &CMSDK_GPIO2->DATA;
obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
} else if (pin >= 48 && pin <= 51){
obj->reg_data = &CMSDK_GPIO3->DATAOUT;
obj->reg_in = &CMSDK_GPIO3->DATA;
obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
} else if (pin == 100 || pin == 101){
obj->reg_data = &MPS2_FPGAIO->LED; //user leds
obj->reg_in = &MPS2_FPGAIO->LED;
} else if (pin == 110 || pin == 111){
obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
}else if (pin >= 200 && pin <= 207){
obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
}else if (pin >= 210 && pin <= 217){
obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
}else if (pin == 303 || pin == 307){
obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
}else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
}
}
if(pin == NC){ return;}
else {
int pin_value = 0;
obj->pin = pin;
if(pin <=15){
pin_value = pin;
}else if (pin >= 16 && pin <= 31){
pin_value = pin-16;
}else if (pin >= 32 && pin <= 47){
pin_value = pin-32;
}else if (pin >= 48 && pin <= 51){
pin_value = pin-48;
}else if (pin == 100 || pin == 101){
pin_value = pin-100;
}else if (pin == 110 || pin == 111){
pin_value = pin-110;
}else if (pin >= 200 && pin <= 207){
pin_value = pin-200;
}else if (pin >= 210 && pin <= 217){
pin_value = pin-210;
}else if (pin == 303){
pin_value = pin-302;
}else if (pin == 307){
pin_value = pin-307;
}else if (pin == 308){
pin_value = pin-305;
}else if (pin == 309){
pin_value = pin-305;
}else if (pin == 310){
pin_value = pin-305;
}else if (pin == 311){
pin_value = pin-305;
}else if (pin == 323){
pin_value = pin-315;
}else if (pin == 334){
pin_value = pin-325;
}else if (pin == 653){
pin_value = pin-646;
}
obj->mask = 0x1 << pin_value;
obj->pin_number = pin;
if(pin <=15) {
obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
obj->reg_in = &CMSDK_GPIO0->DATA ;
obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
} else if (pin >= 16 && pin <= 31){
obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
obj->reg_in = &CMSDK_GPIO1->DATA ;
obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
} else if (pin >= 32 && pin <= 47){
obj->reg_data = &CMSDK_GPIO2->DATAOUT;
obj->reg_in = &CMSDK_GPIO2->DATA;
obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
} else if (pin >= 48 && pin <= 51){
obj->reg_data = &CMSDK_GPIO3->DATAOUT;
obj->reg_in = &CMSDK_GPIO3->DATA;
obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ;
obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
} else if (pin == 100 || pin == 101){
obj->reg_data = &MPS2_FPGAIO->LED; //user leds
obj->reg_in = &MPS2_FPGAIO->LED;
} else if (pin == 110 || pin == 111){
obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
}else if (pin >= 200 && pin <= 207){
obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
}else if (pin >= 210 && pin <= 217){
obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
}else if (pin == 303 || pin == 307){
obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
}else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
}else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653
obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits
}
if (pin == 323){
CMSDK_GPIO0->ALTFUNCSET |= 0x1000;
}else if (pin == 334){
CMSDK_GPIO2->ALTFUNCSET |= 0x0040;
}else if (pin == 653){
CMSDK_GPIO1->ALTFUNCSET |= 0x0001;
}
}
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
if(obj->pin >= 0 && obj->pin <= 51)
{
if(obj->pin >= 0 && obj->pin <= 51)
{
switch (direction) {
case PIN_INPUT : *obj->reg_dirclr = obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
@ -115,10 +131,10 @@ void gpio_dir(gpio_t *obj, PinDirection direction) {
}
int gpio_is_connected(const gpio_t *obj){
if(obj->pin != (PinName)NC){
return 1;
} else {
return 0;
}
if(obj->pin != (PinName)NC){
return 1;
} else {
return 0;
}
}

318
libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c
View File

@ -27,36 +27,36 @@ static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static inline void handle_interrupt_in(uint32_t channel) {
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if (ch_bit <16){
if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
uint32_t ch_bit = (1 << channel);
// Return immediately if:
// * The interrupt was already served
// * There is no user handler
// * It is a level interrupt, not an edge interrupt
if (ch_bit <16){
if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_0->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
if (ch_bit>=16) {
if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_0->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
if (ch_bit>=16) {
if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_1->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_RISE);
CMSDK_GPIO_1->INTPOLSET = ch_bit;
}
if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
irq_handler(channel_ids[channel], IRQ_FALL);
}
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
void gpio0_irq0(void) {handle_interrupt_in(0);}
@ -94,148 +94,148 @@ void gpio1_irq15(void) {handle_interrupt_in(31);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) {return -1;}
else {
irq_handler = handler;
int found_free_channel = 0;
int i = 0;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) return -1;
/* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h
*/
if (pin <16)
{
CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
}
if (pin >= 16)
{
CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
}
if (pin == NC) {return -1;}
else {
irq_handler = handler;
int found_free_channel = 0;
int i = 0;
for (i=0; i<CHANNEL_NUM; i++) {
if (channel_ids[i] == 0) {
channel_ids[i] = id;
obj->ch = i;
found_free_channel = 1;
break;
}
}
if (!found_free_channel) return -1;
/* To select a pin for any of the eight pin interrupts, write the pin number
* as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
* @see: mbed_capi/PinNames.h
*/
if (pin <16)
{
CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
}
if (pin >= 16)
{
CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
}
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0: channels_irq = &gpio0_irq0; break;
case 1: channels_irq = &gpio0_irq1; break;
case 2: channels_irq = &gpio0_irq2; break;
case 3: channels_irq = &gpio0_irq3; break;
case 4: channels_irq = &gpio0_irq4; break;
case 5: channels_irq = &gpio0_irq5; break;
case 6: channels_irq = &gpio0_irq6; break;
case 7: channels_irq = &gpio0_irq7; break;
case 8: channels_irq = &gpio0_irq8; break;
case 9: channels_irq = &gpio0_irq9; break;
case 10: channels_irq = &gpio0_irq10; break;
case 11: channels_irq = &gpio0_irq11; break;
case 12: channels_irq = &gpio0_irq12; break;
case 13: channels_irq = &gpio0_irq13; break;
case 14: channels_irq = &gpio0_irq14; break;
case 15: channels_irq = &gpio0_irq15; break;
case 16: channels_irq = &gpio1_irq0; break;
case 17: channels_irq = &gpio1_irq1; break;
case 18: channels_irq = &gpio1_irq2; break;
case 19: channels_irq = &gpio1_irq3; break;
case 20: channels_irq = &gpio1_irq4; break;
case 21: channels_irq = &gpio1_irq5; break;
case 22: channels_irq = &gpio1_irq6; break;
case 23: channels_irq = &gpio1_irq7; break;
case 24: channels_irq = &gpio1_irq8; break;
case 25: channels_irq = &gpio1_irq9; break;
case 26: channels_irq = &gpio1_irq10; break;
case 27: channels_irq = &gpio1_irq11; break;
case 28: channels_irq = &gpio1_irq12; break;
case 29: channels_irq = &gpio1_irq13; break;
case 30: channels_irq = &gpio1_irq14; break;
case 31: channels_irq = &gpio1_irq15; break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
void (*channels_irq)(void) = NULL;
switch (obj->ch) {
case 0: channels_irq = &gpio0_irq0; break;
case 1: channels_irq = &gpio0_irq1; break;
case 2: channels_irq = &gpio0_irq2; break;
case 3: channels_irq = &gpio0_irq3; break;
case 4: channels_irq = &gpio0_irq4; break;
case 5: channels_irq = &gpio0_irq5; break;
case 6: channels_irq = &gpio0_irq6; break;
case 7: channels_irq = &gpio0_irq7; break;
case 8: channels_irq = &gpio0_irq8; break;
case 9: channels_irq = &gpio0_irq9; break;
case 10: channels_irq = &gpio0_irq10; break;
case 11: channels_irq = &gpio0_irq11; break;
case 12: channels_irq = &gpio0_irq12; break;
case 13: channels_irq = &gpio0_irq13; break;
case 14: channels_irq = &gpio0_irq14; break;
case 15: channels_irq = &gpio0_irq15; break;
case 16: channels_irq = &gpio1_irq0; break;
case 17: channels_irq = &gpio1_irq1; break;
case 18: channels_irq = &gpio1_irq2; break;
case 19: channels_irq = &gpio1_irq3; break;
case 20: channels_irq = &gpio1_irq4; break;
case 21: channels_irq = &gpio1_irq5; break;
case 22: channels_irq = &gpio1_irq6; break;
case 23: channels_irq = &gpio1_irq7; break;
case 24: channels_irq = &gpio1_irq8; break;
case 25: channels_irq = &gpio1_irq9; break;
case 26: channels_irq = &gpio1_irq10; break;
case 27: channels_irq = &gpio1_irq11; break;
case 28: channels_irq = &gpio1_irq12; break;
case 29: channels_irq = &gpio1_irq13; break;
case 30: channels_irq = &gpio1_irq14; break;
case 31: channels_irq = &gpio1_irq15; break;
}
NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
return 0;
}
}
void gpio_irq_free(gpio_irq_t *obj) {
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt
if (obj->ch <16)
{
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
{
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
}
if (obj->ch >= 16)
{
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
{
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
// Edge trigger
if (obj->ch <16)
{
CMSDK_GPIO_0->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_0->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
}
}
if (obj->ch >= 16)
{
CMSDK_GPIO_1->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
}
}
unsigned int ch_bit = (1 << obj->ch);
// Clear interrupt
if (obj->ch <16)
{
if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
{
CMSDK_GPIO_0->INTCLEAR = ch_bit;
}
}
if (obj->ch >= 16)
{
if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
{
CMSDK_GPIO_1->INTCLEAR = ch_bit;
}
}
// Edge trigger
if (obj->ch <16)
{
CMSDK_GPIO_0->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_0->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_0->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_0->INTENCLR |= ch_bit;
}
}
}
if (obj->ch >= 16)
{
CMSDK_GPIO_1->INTTYPESET &= ch_bit;
if (event == IRQ_RISE) {
CMSDK_GPIO_1->INTPOLSET |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
} else {
CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
if (enable) {
CMSDK_GPIO_1->INTENSET |= ch_bit;
} else {
CMSDK_GPIO_1->INTENCLR |= ch_bit;
}
}
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}
void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
}

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