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Merge pull request #1501 from stevew817/pearl_support_rebased 

[Silicon Labs] Add support for the new EFM32 Pearl Gecko
pull/1503/head
Martin Kojtal 2016-01-15 07:33:40 +00:00
parent c47cd8d483 3d8637cdfb
commit 919364e6e7
432 changed files with 54866 additions and 10055 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/efm32gg.sct
View File

@ -8,7 +8,7 @@ LR_IROM1 0x00000000 0x00100000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x200000E0 0x0001FF20 { ; RW data
RW_IRAM1 0x200000DC 0x0001FF24 { ; RW data
.ANY (+RW +ZI)
}
}

5
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/startup_efm32gg.S
View File

@ -2,7 +2,7 @@
; * @file startup_efm32gg.s
; * @brief CMSIS Core Device Startup File for
; * Silicon Labs EFM32GG Device Series
; * @version 3.20.6
; * @version 4.2.1
; * @date 03. February 2012
; *
; * @note
@ -262,10 +262,7 @@ MSC_IRQHandler
AES_IRQHandler
EBI_IRQHandler
EMU_IRQHandler
B .
ENDP
ALIGN

2
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/efm32gg.sct
View File

@ -8,7 +8,7 @@ LR_IROM1 0x00000000 0x00100000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x200000E0 0x0001FF20 { ; RW data
RW_IRAM1 0x200000DC 0x0001FF24 { ; RW data
.ANY (+RW +ZI)
}
}

5
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.S
View File

@ -2,7 +2,7 @@
; * @file startup_efm32gg.s
; * @brief CMSIS Core Device Startup File for
; * Silicon Labs EFM32GG Device Series
; * @version 3.20.6
; * @version 4.2.1
; * @date 03. February 2012
; *
; * @note
@ -262,10 +262,7 @@ MSC_IRQHandler
AES_IRQHandler
EBI_IRQHandler
EMU_IRQHandler
B .
ENDP
ALIGN

79
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/efm32gg.ld
View File

@ -4,7 +4,11 @@
/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */
/* Example Code. */
/* */
/* Silicon Laboratories, Inc. 2014 */
/* Silicon Laboratories, Inc. 2015 */
/* */
/* Version 4.2.0 */
/* */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576
@ -13,16 +17,20 @@ MEMORY
/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
* We make room for the table at the very beginning of RAM, i.e. at
* 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32GG */
__vector_size = 0xE0;
__vector_size = 0xDC;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
@ -40,6 +48,8 @@ __vector_size = 0xE0;
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
@ -47,7 +57,11 @@ SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
@ -72,7 +86,7 @@ SECTIONS
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
@ -84,15 +98,49 @@ SECTIONS
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*("dma")
PROVIDE( __start_vector_table__ = .);
. += __vector_size;
PROVIDE( __end_vector_table__ = .);
. += __vector_size;
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
. = ALIGN (4);
@ -118,6 +166,7 @@ SECTIONS
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
@ -126,27 +175,30 @@ SECTIONS
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap :
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
_end = __end__;
*(.heap*)
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
.stack_dummy (COPY):
{
*(.stack)
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
@ -157,4 +209,7 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Check if FLASH usage exceeds FLASH size */
ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
}

485
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/startup_efm32gg.S
View File

@ -1,233 +1,338 @@
/* @file startup_efm32gg.S
* @brief startup file for Silicon Labs EFM32GG devices.
* For use with GCC for ARM Embedded Processors
* @version 3.20.6
* Date: 08 Feb 2012
* @version 4.2.1
* Date: 12 June 2014
*
* Copyright (c) 2012, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv7-m
/* Copyright (c) 2011 - 2014 ARM LIMITED
.section .stack
.align 3
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.size __StackTop, . - __StackTop
.section .heap
.align 3
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0xC00
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 8
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long Default_Handler /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long Default_Handler /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA_IRQHandler /* 0 - DMA */
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
.long TIMER0_IRQHandler /* 2 - TIMER0 */
.long USART0_RX_IRQHandler /* 3 - USART0_RX */
.long USART0_TX_IRQHandler /* 4 - USART0_TX */
.long USB_IRQHandler /* 5 - USB */
.long ACMP0_IRQHandler /* 6 - ACMP0 */
.long ADC0_IRQHandler /* 7 - ADC0 */
.long DAC0_IRQHandler /* 8 - DAC0 */
.long I2C0_IRQHandler /* 9 - I2C0 */
.long I2C1_IRQHandler /* 10 - I2C1 */
.long GPIO_ODD_IRQHandler /* 11 - GPIO_ODD */
.long TIMER1_IRQHandler /* 12 - TIMER1 */
.long TIMER2_IRQHandler /* 13 - TIMER2 */
.long TIMER3_IRQHandler /* 14 - TIMER3 */
.long USART1_RX_IRQHandler /* 15 - USART1_RX */
.long USART1_TX_IRQHandler /* 16 - USART1_TX */
.long LESENSE_IRQHandler /* 17 - LESENSE */
.long USART2_RX_IRQHandler /* 18 - USART2_RX */
.long USART2_TX_IRQHandler /* 19 - USART2_TX */
.long UART0_RX_IRQHandler /* 20 - UART0_RX */
.long UART0_TX_IRQHandler /* 21 - UART0_TX */
.long UART1_RX_IRQHandler /* 22 - UART1_RX */
.long UART1_TX_IRQHandler /* 23 - UART1_TX */
.long LEUART0_IRQHandler /* 24 - LEUART0 */
.long LEUART1_IRQHandler /* 25 - LEUART1 */
.long LETIMER0_IRQHandler /* 26 - LETIMER0 */
.long PCNT0_IRQHandler /* 27 - PCNT0 */
.long PCNT1_IRQHandler /* 28 - PCNT1 */
.long PCNT2_IRQHandler /* 29 - PCNT2 */
.long RTC_IRQHandler /* 30 - RTC */
.long BURTC_IRQHandler /* 31 - BURTC */
.long CMU_IRQHandler /* 32 - CMU */
.long VCMP_IRQHandler /* 33 - VCMP */
.long LCD_IRQHandler /* 34 - LCD */
.long MSC_IRQHandler /* 35 - MSC */
.long AES_IRQHandler /* 36 - AES */
.long EBI_IRQHandler /* 37 - EBI */
.long EMU_IRQHandler /* 38 - EMU */
.long DMA_IRQHandler /* 0 - DMA */
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
.long TIMER0_IRQHandler /* 2 - TIMER0 */
.long USART0_RX_IRQHandler /* 3 - USART0_RX */
.long USART0_TX_IRQHandler /* 4 - USART0_TX */
.long USB_IRQHandler /* 5 - USB */
.long ACMP0_IRQHandler /* 6 - ACMP0 */
.long ADC0_IRQHandler /* 7 - ADC0 */
.long DAC0_IRQHandler /* 8 - DAC0 */
.long I2C0_IRQHandler /* 9 - I2C0 */
.long I2C1_IRQHandler /* 10 - I2C1 */
.long GPIO_ODD_IRQHandler /* 11 - GPIO_ODD */
.long TIMER1_IRQHandler /* 12 - TIMER1 */
.long TIMER2_IRQHandler /* 13 - TIMER2 */
.long TIMER3_IRQHandler /* 14 - TIMER3 */
.long USART1_RX_IRQHandler /* 15 - USART1_RX */
.long USART1_TX_IRQHandler /* 16 - USART1_TX */
.long LESENSE_IRQHandler /* 17 - LESENSE */
.long USART2_RX_IRQHandler /* 18 - USART2_RX */
.long USART2_TX_IRQHandler /* 19 - USART2_TX */
.long UART0_RX_IRQHandler /* 20 - UART0_RX */
.long UART0_TX_IRQHandler /* 21 - UART0_TX */
.long UART1_RX_IRQHandler /* 22 - UART1_RX */
.long UART1_TX_IRQHandler /* 23 - UART1_TX */
.long LEUART0_IRQHandler /* 24 - LEUART0 */
.long LEUART1_IRQHandler /* 25 - LEUART1 */
.long LETIMER0_IRQHandler /* 26 - LETIMER0 */
.long PCNT0_IRQHandler /* 27 - PCNT0 */
.long PCNT1_IRQHandler /* 28 - PCNT1 */
.long PCNT2_IRQHandler /* 29 - PCNT2 */
.long RTC_IRQHandler /* 30 - RTC */
.long BURTC_IRQHandler /* 31 - BURTC */
.long CMU_IRQHandler /* 32 - CMU */
.long VCMP_IRQHandler /* 33 - VCMP */
.long LCD_IRQHandler /* 34 - LCD */
.long MSC_IRQHandler /* 35 - MSC */
.long AES_IRQHandler /* 36 - AES */
.long EBI_IRQHandler /* 37 - EBI */
.long EMU_IRQHandler /* 38 - EMU */
.size __isr_vector, . - __isr_vector
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
#ifndef __NO_SYSTEM_INIT
ldr r0, =SystemInit
blx r0
ldr r0, =SystemInit
blx r0
#endif
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
.flash_to_ram_loop:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .flash_to_ram_loop
.flash_to_ram_loop_end:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __START
#define __START _start
#endif
bl __START
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name:
b .
.size \handler_name, . - \handler_name
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler Default_Handler
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA_IRQHandler
def_irq_handler GPIO_EVEN_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler USART0_RX_IRQHandler
def_irq_handler USART0_TX_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler ACMP0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler GPIO_ODD_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler USART1_RX_IRQHandler
def_irq_handler USART1_TX_IRQHandler
def_irq_handler LESENSE_IRQHandler
def_irq_handler USART2_RX_IRQHandler
def_irq_handler USART2_TX_IRQHandler
def_irq_handler UART0_RX_IRQHandler
def_irq_handler UART0_TX_IRQHandler
def_irq_handler UART1_RX_IRQHandler
def_irq_handler UART1_TX_IRQHandler
def_irq_handler LEUART0_IRQHandler
def_irq_handler LEUART1_IRQHandler
def_irq_handler LETIMER0_IRQHandler
def_irq_handler PCNT0_IRQHandler
def_irq_handler PCNT1_IRQHandler
def_irq_handler PCNT2_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler BURTC_IRQHandler
def_irq_handler CMU_IRQHandler
def_irq_handler VCMP_IRQHandler
def_irq_handler LCD_IRQHandler
def_irq_handler MSC_IRQHandler
def_irq_handler AES_IRQHandler
def_irq_handler EBI_IRQHandler
def_irq_handler EMU_IRQHandler
def_irq_handler DMA_IRQHandler
def_irq_handler GPIO_EVEN_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler USART0_RX_IRQHandler
def_irq_handler USART0_TX_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler ACMP0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler GPIO_ODD_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler USART1_RX_IRQHandler
def_irq_handler USART1_TX_IRQHandler
def_irq_handler LESENSE_IRQHandler
def_irq_handler USART2_RX_IRQHandler
def_irq_handler USART2_TX_IRQHandler
def_irq_handler UART0_RX_IRQHandler
def_irq_handler UART0_TX_IRQHandler
def_irq_handler UART1_RX_IRQHandler
def_irq_handler UART1_TX_IRQHandler
def_irq_handler LEUART0_IRQHandler
def_irq_handler LEUART1_IRQHandler
def_irq_handler LETIMER0_IRQHandler
def_irq_handler PCNT0_IRQHandler
def_irq_handler PCNT1_IRQHandler
def_irq_handler PCNT2_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler BURTC_IRQHandler
def_irq_handler CMU_IRQHandler
def_irq_handler VCMP_IRQHandler
def_irq_handler LCD_IRQHandler
def_irq_handler MSC_IRQHandler
def_irq_handler AES_IRQHandler
def_irq_handler EBI_IRQHandler
def_irq_handler EMU_IRQHandler
.end

18
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg990f1024.h
View File

@ -2,10 +2,10 @@
* @file efm32gg990f1024.h
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32GG990F1024
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -31,8 +31,8 @@
*
*****************************************************************************/
#ifndef __EFM32GG990F1024_H
#define __EFM32GG990F1024_H
#ifndef EFM32GG990F1024_H
#define EFM32GG990F1024_H
#ifdef __cplusplus
extern "C" {
@ -52,7 +52,7 @@ extern "C" {
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
@ -121,8 +121,10 @@ typedef enum IRQn
******************************************************************************/
/** Part family */
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
/* If part number is not defined as compiler option, define it */
#if !defined(EFM32GG990F1024)
@ -474,4 +476,4 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
#endif /* __EFM32GG990F1024_H */
#endif /* EFM32GG990F1024_H */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_acmp.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_acmp.h
* @brief EFM32GG_ACMP register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_ACMP
* @{
@ -327,5 +331,5 @@ typedef struct
#define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */
/** @} End of group EFM32GG_ACMP */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_adc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_adc.h
* @brief EFM32GG_ADC register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_ADC
* @{
@ -666,5 +670,5 @@ typedef struct
#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
/** @} End of group EFM32GG_ADC */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_aes.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_aes.h
* @brief EFM32GG_AES register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_AES
* @{
@ -235,5 +239,5 @@ typedef struct
#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
/** @} End of group EFM32GG_AES */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_pins.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_af_pins.h
* @brief EFM32GG_AF_PINS register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_AF_Pins
* @{
@ -200,5 +204,5 @@
#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : -1)
/** @} End of group EFM32GG_AF_Pins */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_ports.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_af_ports.h
* @brief EFM32GG_AF_PORTS register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_AF_Ports
* @{
@ -200,5 +204,5 @@
#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : -1)
/** @} End of group EFM32GG_AF_Ports */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_burtc.h
* @brief EFM32GG_BURTC register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_BURTC
* @{
@ -55,7 +59,6 @@ typedef struct
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[48]; /**< Reserved registers */
BURTC_RET_TypeDef RET[128]; /**< RetentionReg */
} BURTC_TypeDef; /** @} */
@ -373,5 +376,5 @@ typedef struct
#define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */
/** @} End of group EFM32GG_BURTC */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc_ret.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_burtc_ret.h
* @brief EFM32GG_BURTC_RET register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief BURTC_RET EFM32GG BURTC RET
*****************************************************************************/
@ -37,3 +41,6 @@ typedef struct
__IO uint32_t REG; /**< Retention Register */
} BURTC_RET_TypeDef;
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_calibrate.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_calibrate.h
* @brief EFM32GG_CALIBRATE register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_CALIBRATE
* @{
@ -41,3 +45,6 @@ typedef struct
__I uint32_t VALUE; /**< Default value for calibration register */
} CALIBRATE_TypeDef; /** @} */
/** @} End of group Parts */

19
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_cmu.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_cmu.h
* @brief EFM32GG_CMU register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_CMU
* @{
@ -60,6 +64,7 @@ typedef struct
__IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
uint32_t RESERVED1[1]; /**< Reserved for future use **/
__IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
uint32_t RESERVED3[1]; /**< Reserved for future use **/
@ -78,7 +83,7 @@ typedef struct
/* Bit fields for CMU CTRL */
#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */
#define _CMU_CTRL_MASK 0x53FFFEEFUL /**< Mask for CMU_CTRL */
#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */
#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
@ -187,7 +192,7 @@ typedef struct
#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
@ -454,7 +459,7 @@ typedef struct
/* Bit fields for CMU CMD */
#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
#define _CMU_CMD_MASK 0x0000007FUL /**< Mask for CMU_CMD */
#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */
#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
@ -478,7 +483,7 @@ typedef struct
#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */
#define _CMU_CMD_USBCCLKSEL_MASK 0x60UL /**< Bit mask for CMU_USBCCLKSEL */
#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */
#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */
#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */
@ -1243,5 +1248,5 @@ typedef struct
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
/** @} End of group EFM32GG_CMU */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dac.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_dac.h
* @brief EFM32GG_DAC register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_DAC
* @{
@ -788,5 +792,5 @@ typedef struct
#define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA2MUX */
/** @} End of group EFM32GG_DAC */
/** @} End of group Parts */

23
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_devinfo.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_devinfo.h
* @brief EFM32GG_DEVINFO register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_DEVINFO
* @{
@ -140,15 +144,28 @@ typedef struct
#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
/* Legacy family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
/* New style family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
/** @} End of group EFM32GG_DEVINFO */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_dma.h
* @brief EFM32GG_DMA register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_DMA
* @{
@ -75,7 +79,6 @@ typedef struct
__IO uint32_t RECT0; /**< Channel 0 Rectangle Register */
uint32_t RESERVED6[39]; /**< Reserved registers */
DMA_CH_TypeDef CH[12]; /**< Channel registers */
} DMA_TypeDef; /** @} */
@ -1625,5 +1628,5 @@ typedef struct
#define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for DMA_CH_CTRL */
/** @} End of group EFM32GG_DMA */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_ch.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_dma_ch.h
* @brief EFM32GG_DMA_CH register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief DMA_CH EFM32GG DMA CH
*****************************************************************************/
@ -37,3 +41,6 @@ typedef struct
__IO uint32_t CTRL; /**< Channel Control Register */
} DMA_CH_TypeDef;
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_descriptor.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_dma_descriptor.h
* @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_DMA_DESCRIPTOR
* @{
@ -43,3 +47,6 @@ typedef struct
__IO uint32_t USER; /**< DMA padding register, available for user */
} DMA_DESCRIPTOR_TypeDef; /** @} */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmactrl.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_dmactrl.h
* @brief EFM32GG_DMACTRL register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_DMACTRL_BitFields
@ -132,5 +136,5 @@
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
/** @} End of group EFM32GG_DMA */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmareq.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_dmareq.h
* @brief EFM32GG_DMAREQ register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_DMAREQ_BitFields
@ -95,5 +99,5 @@
#define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
/** @} End of group EFM32GG_DMAREQ */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_ebi.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_ebi.h
* @brief EFM32GG_EBI register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_EBI
* @{
@ -1456,5 +1460,5 @@ typedef struct
#define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */
/** @} End of group EFM32GG_EBI */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_emu.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_emu.h
* @brief EFM32GG_EMU register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_EMU
* @{
@ -353,5 +357,5 @@ typedef struct
#define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
/** @} End of group EFM32GG_EMU */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_etm.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_etm.h
* @brief EFM32GG_ETM register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_ETM
* @{
@ -778,5 +782,5 @@ typedef struct
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
/** @} End of group EFM32GG_ETM */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_gpio.h
* @brief EFM32GG_GPIO register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_GPIO
* @{
@ -1200,5 +1204,5 @@ typedef struct
#define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUCAUSE */
/** @} End of group EFM32GG_GPIO */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio_p.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_gpio_p.h
* @brief EFM32GG_GPIO_P register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief GPIO_P EFM32GG GPIO P
*****************************************************************************/
@ -45,3 +49,6 @@ typedef struct
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
} GPIO_P_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_i2c.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_i2c.h
* @brief EFM32GG_I2C register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_I2C
* @{
@ -697,5 +701,5 @@ typedef struct
#define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */
/** @} End of group EFM32GG_I2C */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lcd.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_lcd.h
* @brief EFM32GG_LCD register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_LCD
* @{
@ -591,5 +595,5 @@ typedef struct
#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
/** @} End of group EFM32GG_LCD */
/** @} End of group Parts */

13
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_lesense.h
* @brief EFM32GG_LESENSE register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_LESENSE
* @{
@ -61,9 +65,10 @@ typedef struct
__IO uint32_t POWERDOWN; /**< LESENSE RAM power-down register */
uint32_t RESERVED0[105]; /**< Reserved registers */
LESENSE_ST_TypeDef ST[16]; /**< Decoding states */
LESENSE_BUF_TypeDef BUF[16]; /**< Scanresult */
LESENSE_CH_TypeDef CH[16]; /**< Scanconfig */
} LESENSE_TypeDef; /** @} */
@ -1921,5 +1926,5 @@ typedef struct
#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
/** @} End of group EFM32GG_LESENSE */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_buf.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_lesense_buf.h
* @brief EFM32GG_LESENSE_BUF register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief LESENSE_BUF EFM32GG LESENSE BUF
*****************************************************************************/
@ -37,3 +41,6 @@ typedef struct
__IO uint32_t DATA; /**< Scan results */
} LESENSE_BUF_TypeDef;
/** @} End of group Parts */

12
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_ch.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_lesense_ch.h
* @brief EFM32GG_LESENSE_CH register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief LESENSE_CH EFM32GG LESENSE CH
*****************************************************************************/
@ -37,7 +41,9 @@ typedef struct
__IO uint32_t TIMING; /**< Scan configuration */
__IO uint32_t INTERACT; /**< Scan configuration */
__IO uint32_t EVAL; /**< Scan configuration */
uint32_t RESERVED0[1]; /**< Reserved future */
} LESENSE_CH_TypeDef;
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_st.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_lesense_st.h
* @brief EFM32GG_LESENSE_ST register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief LESENSE_ST EFM32GG LESENSE ST
*****************************************************************************/
@ -38,3 +42,6 @@ typedef struct
__IO uint32_t TCONFB; /**< State transition configuration B */
} LESENSE_ST_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_letimer.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_letimer.h
* @brief EFM32GG_LETIMER register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_LETIMER
* @{
@ -404,5 +408,5 @@ typedef struct
#define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTE */
/** @} End of group EFM32GG_LETIMER */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_leuart.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_leuart.h
* @brief EFM32GG_LEUART register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_LEUART
* @{
@ -695,5 +699,5 @@ typedef struct
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_INPUT */
/** @} End of group EFM32GG_LEUART */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_msc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_msc.h
* @brief EFM32GG_MSC register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_MSC
* @{
@ -459,5 +463,5 @@ typedef struct
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
/** @} End of group EFM32GG_MSC */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_pcnt.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_pcnt.h
* @brief EFM32GG_PCNT register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_PCNT
* @{
@ -413,5 +417,5 @@ typedef struct
#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
/** @} End of group EFM32GG_PCNT */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_prs.h
* @brief EFM32GG_PRS register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_PRS
* @{
@ -41,7 +45,6 @@ typedef struct
__IO uint32_t ROUTE; /**< I/O Routing Register */
uint32_t RESERVED0[1]; /**< Reserved registers */
PRS_CH_TypeDef CH[12]; /**< Channel registers */
} PRS_TypeDef; /** @} */
@ -448,5 +451,5 @@ typedef struct
#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
/** @} End of group EFM32GG_PRS */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_ch.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_prs_ch.h
* @brief EFM32GG_PRS_CH register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief PRS_CH EFM32GG PRS CH
*****************************************************************************/
@ -37,3 +41,6 @@ typedef struct
__IO uint32_t CTRL; /**< Channel Control Register */
} PRS_CH_TypeDef;
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_signals.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_prs_signals.h
* @brief EFM32GG_PRS_SIGNALS register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,12 +29,15 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @addtogroup EFM32GG_PRS_Signals
* @{
* @brief PRS Signal names
*****************************************************************************/
#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
@ -119,5 +122,5 @@
#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
/** @} End of group EFM32GG_PRS */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rmu.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_rmu.h
* @brief EFM32GG_RMU register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_RMU
* @{
@ -154,5 +158,5 @@ typedef struct
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
/** @} End of group EFM32GG_RMU */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_romtable.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_romtable.h
* @brief EFM32GG_ROMTABLE register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_ROMTABLE
* @{
@ -64,5 +68,5 @@ typedef struct
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
/** @} End of group EFM32GG_ROMTABLE */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rtc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_rtc.h
* @brief EFM32GG_RTC register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_RTC
* @{
@ -210,5 +214,5 @@ typedef struct
#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
/** @} End of group EFM32GG_RTC */
/** @} End of group Parts */

17
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_timer.h
* @brief EFM32GG_TIMER register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_TIMER
* @{
@ -49,7 +53,6 @@ typedef struct
__IO uint32_t ROUTE; /**< I/O Routing Register */
uint32_t RESERVED0[1]; /**< Reserved registers */
TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
uint32_t RESERVED1[4]; /**< Reserved for future use **/
@ -181,7 +184,7 @@ typedef struct
#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Ouptut initial State */
#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
@ -516,15 +519,15 @@ typedef struct
#define TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */
#define _TIMER_ROUTE_LOCATION_MASK 0x70000UL /**< Bit mask for TIMER_LOCATION */
#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */
@ -961,5 +964,5 @@ typedef struct
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
/** @} End of group EFM32GG_TIMER */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer_cc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_timer_cc.h
* @brief EFM32GG_TIMER_CC register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief TIMER_CC EFM32GG TIMER CC
*****************************************************************************/
@ -40,3 +44,6 @@ typedef struct
__IO uint32_t CCVB; /**< CC Channel Buffer Register */
} TIMER_CC_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_uart.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_uart.h
* @brief EFM32GG_UART register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_UART_BitFields
@ -1113,5 +1117,5 @@
#define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */
/** @} End of group EFM32GG_UART */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usart.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_usart.h
* @brief EFM32GG_USART register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_USART
* @{
@ -1145,5 +1149,5 @@ typedef struct
#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
/** @} End of group EFM32GG_USART */
/** @} End of group Parts */

212
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_usb.h
* @brief EFM32GG_USB register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_USB
* @{
@ -81,7 +85,6 @@ typedef struct
__IO uint32_t HPRT; /**< Host Port Control and Status Register */
uint32_t RESERVED6[47]; /**< Reserved registers */
USB_HC_TypeDef HC[14]; /**< Host Channel Registers */
uint32_t RESERVED7[80]; /**< Reserved for future use **/
@ -110,7 +113,6 @@ typedef struct
__I uint32_t DIEP0TXFSTS; /**< Device IN Endpoint 0 Transmit FIFO Status Register */
uint32_t RESERVED14[1]; /**< Reserved registers */
USB_DIEP_TypeDef DIEP[6]; /**< Device IN Endpoint x+1 Registers */
uint32_t RESERVED15[72]; /**< Reserved for future use **/
@ -122,70 +124,54 @@ typedef struct
__IO uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */
uint32_t RESERVED18[2]; /**< Reserved registers */
USB_DOEP_TypeDef DOEP[6]; /**< Device OUT Endpoint x+1 Registers */
uint32_t RESERVED19[136]; /**< Reserved for future use **/
__IO uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */
uint32_t RESERVED20[127]; /**< Reserved registers */
__IO uint32_t FIFO0D[512]; /**< Device EP 0/Host Channel 0 FIFO */
uint32_t RESERVED21[512]; /**< Reserved registers */
__IO uint32_t FIFO1D[512]; /**< Device EP 1/Host Channel 1 FIFO */
uint32_t RESERVED22[512]; /**< Reserved registers */
__IO uint32_t FIFO2D[512]; /**< Device EP 2/Host Channel 2 FIFO */
uint32_t RESERVED23[512]; /**< Reserved registers */
__IO uint32_t FIFO3D[512]; /**< Device EP 3/Host Channel 3 FIFO */
uint32_t RESERVED24[512]; /**< Reserved registers */
__IO uint32_t FIFO4D[512]; /**< Device EP 4/Host Channel 4 FIFO */
uint32_t RESERVED25[512]; /**< Reserved registers */
__IO uint32_t FIFO5D[512]; /**< Device EP 5/Host Channel 5 FIFO */
uint32_t RESERVED26[512]; /**< Reserved registers */
__IO uint32_t FIFO6D[512]; /**< Device EP 6/Host Channel 6 FIFO */
uint32_t RESERVED27[512]; /**< Reserved registers */
__IO uint32_t FIFO7D[512]; /**< Host Channel 7 FIFO */
uint32_t RESERVED28[512]; /**< Reserved registers */
__IO uint32_t FIFO8D[512]; /**< Host Channel 8 FIFO */
uint32_t RESERVED29[512]; /**< Reserved registers */
__IO uint32_t FIFO9D[512]; /**< Host Channel 9 FIFO */
uint32_t RESERVED30[512]; /**< Reserved registers */
__IO uint32_t FIFO10D[512]; /**< Host Channel 10 FIFO */
uint32_t RESERVED31[512]; /**< Reserved registers */
__IO uint32_t FIFO11D[512]; /**< Host Channel 11 FIFO */
uint32_t RESERVED32[512]; /**< Reserved registers */
__IO uint32_t FIFO12D[512]; /**< Host Channel 12 FIFO */
uint32_t RESERVED33[512]; /**< Reserved registers */
__IO uint32_t FIFO13D[512]; /**< Host Channel 13 FIFO */
uint32_t RESERVED34[17920]; /**< Reserved registers */
__IO uint32_t FIFORAM[512]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */
} USB_TypeDef; /** @} */
@ -321,12 +307,12 @@ typedef struct
/* Bit fields for USB GOTGCTL */
#define _USB_GOTGCTL_RESETVALUE 0x00010000UL /**< Default value for USB_GOTGCTL */
#define _USB_GOTGCTL_MASK 0x001F0FFFUL /**< Mask for USB_GOTGCTL */
#define USB_GOTGCTL_SESREQSCS (0x1UL << 0) /**< Session Request Success (device only) */
#define USB_GOTGCTL_SESREQSCS (0x1UL << 0) /**< Session Request Success device only */
#define _USB_GOTGCTL_SESREQSCS_SHIFT 0 /**< Shift value for USB_SESREQSCS */
#define _USB_GOTGCTL_SESREQSCS_MASK 0x1UL /**< Bit mask for USB_SESREQSCS */
#define _USB_GOTGCTL_SESREQSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_SESREQSCS_DEFAULT (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_SESREQ (0x1UL << 1) /**< Session Request (device only) */
#define USB_GOTGCTL_SESREQ (0x1UL << 1) /**< Session Request device only */
#define _USB_GOTGCTL_SESREQ_SHIFT 1 /**< Shift value for USB_SESREQ */
#define _USB_GOTGCTL_SESREQ_MASK 0x2UL /**< Bit mask for USB_SESREQ */
#define _USB_GOTGCTL_SESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
@ -361,27 +347,27 @@ typedef struct
#define _USB_GOTGCTL_AVALIDOVVAL_MASK 0x80UL /**< Bit mask for USB_AVALIDOVVAL */
#define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_AVALIDOVVAL_DEFAULT (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_HSTNEGSCS (0x1UL << 8) /**< Host Negotiation Success (device only) */
#define USB_GOTGCTL_HSTNEGSCS (0x1UL << 8) /**< Host Negotiation Success device only */
#define _USB_GOTGCTL_HSTNEGSCS_SHIFT 8 /**< Shift value for USB_HSTNEGSCS */
#define _USB_GOTGCTL_HSTNEGSCS_MASK 0x100UL /**< Bit mask for USB_HSTNEGSCS */
#define _USB_GOTGCTL_HSTNEGSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_HSTNEGSCS_DEFAULT (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_HNPREQ (0x1UL << 9) /**< HNP Request (device only) */
#define USB_GOTGCTL_HNPREQ (0x1UL << 9) /**< HNP Request device only */
#define _USB_GOTGCTL_HNPREQ_SHIFT 9 /**< Shift value for USB_HNPREQ */
#define _USB_GOTGCTL_HNPREQ_MASK 0x200UL /**< Bit mask for USB_HNPREQ */
#define _USB_GOTGCTL_HNPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_HNPREQ_DEFAULT (_USB_GOTGCTL_HNPREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_HSTSETHNPEN (0x1UL << 10) /**< Host Set HNP Enable (host only) */
#define USB_GOTGCTL_HSTSETHNPEN (0x1UL << 10) /**< Host Set HNP Enable host only */
#define _USB_GOTGCTL_HSTSETHNPEN_SHIFT 10 /**< Shift value for USB_HSTSETHNPEN */
#define _USB_GOTGCTL_HSTSETHNPEN_MASK 0x400UL /**< Bit mask for USB_HSTSETHNPEN */
#define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_HSTSETHNPEN_DEFAULT (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_DEVHNPEN (0x1UL << 11) /**< Device HNP Enabled (device only) */
#define USB_GOTGCTL_DEVHNPEN (0x1UL << 11) /**< Device HNP Enabled device only */
#define _USB_GOTGCTL_DEVHNPEN_SHIFT 11 /**< Shift value for USB_DEVHNPEN */
#define _USB_GOTGCTL_DEVHNPEN_MASK 0x800UL /**< Bit mask for USB_DEVHNPEN */
#define _USB_GOTGCTL_DEVHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_DEVHNPEN_DEFAULT (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_CONIDSTS (0x1UL << 16) /**< Connector ID Status (host and device) */
#define USB_GOTGCTL_CONIDSTS (0x1UL << 16) /**< Connector ID Status host and device */
#define _USB_GOTGCTL_CONIDSTS_SHIFT 16 /**< Shift value for USB_CONIDSTS */
#define _USB_GOTGCTL_CONIDSTS_MASK 0x10000UL /**< Bit mask for USB_CONIDSTS */
#define _USB_GOTGCTL_CONIDSTS_A 0x00000000UL /**< Mode A for USB_GOTGCTL */
@ -390,7 +376,7 @@ typedef struct
#define USB_GOTGCTL_CONIDSTS_A (_USB_GOTGCTL_CONIDSTS_A << 16) /**< Shifted mode A for USB_GOTGCTL */
#define USB_GOTGCTL_CONIDSTS_DEFAULT (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_CONIDSTS_B (_USB_GOTGCTL_CONIDSTS_B << 16) /**< Shifted mode B for USB_GOTGCTL */
#define USB_GOTGCTL_DBNCTIME (0x1UL << 17) /**< Long/Short Debounce Time (host only) */
#define USB_GOTGCTL_DBNCTIME (0x1UL << 17) /**< Long/Short Debounce Time host only */
#define _USB_GOTGCTL_DBNCTIME_SHIFT 17 /**< Shift value for USB_DBNCTIME */
#define _USB_GOTGCTL_DBNCTIME_MASK 0x20000UL /**< Bit mask for USB_DBNCTIME */
#define _USB_GOTGCTL_DBNCTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
@ -399,12 +385,12 @@ typedef struct
#define USB_GOTGCTL_DBNCTIME_DEFAULT (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_DBNCTIME_LONG (_USB_GOTGCTL_DBNCTIME_LONG << 17) /**< Shifted mode LONG for USB_GOTGCTL */
#define USB_GOTGCTL_DBNCTIME_SHORT (_USB_GOTGCTL_DBNCTIME_SHORT << 17) /**< Shifted mode SHORT for USB_GOTGCTL */
#define USB_GOTGCTL_ASESVLD (0x1UL << 18) /**< A-Session Valid (host only) */
#define USB_GOTGCTL_ASESVLD (0x1UL << 18) /**< A-Session Valid host only */
#define _USB_GOTGCTL_ASESVLD_SHIFT 18 /**< Shift value for USB_ASESVLD */
#define _USB_GOTGCTL_ASESVLD_MASK 0x40000UL /**< Bit mask for USB_ASESVLD */
#define _USB_GOTGCTL_ASESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_ASESVLD_DEFAULT (_USB_GOTGCTL_ASESVLD_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGCTL */
#define USB_GOTGCTL_BSESVLD (0x1UL << 19) /**< B-Session Valid (device only) */
#define USB_GOTGCTL_BSESVLD (0x1UL << 19) /**< B-Session Valid device only */
#define _USB_GOTGCTL_BSESVLD_SHIFT 19 /**< Shift value for USB_BSESVLD */
#define _USB_GOTGCTL_BSESVLD_MASK 0x80000UL /**< Bit mask for USB_BSESVLD */
#define _USB_GOTGCTL_BSESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
@ -422,32 +408,32 @@ typedef struct
/* Bit fields for USB GOTGINT */
#define _USB_GOTGINT_RESETVALUE 0x00000000UL /**< Default value for USB_GOTGINT */
#define _USB_GOTGINT_MASK 0x000E0304UL /**< Mask for USB_GOTGINT */
#define USB_GOTGINT_SESENDDET (0x1UL << 2) /**< Session End Detected (host and device) */
#define USB_GOTGINT_SESENDDET (0x1UL << 2) /**< Session End Detected host and device */
#define _USB_GOTGINT_SESENDDET_SHIFT 2 /**< Shift value for USB_SESENDDET */
#define _USB_GOTGINT_SESENDDET_MASK 0x4UL /**< Bit mask for USB_SESENDDET */
#define _USB_GOTGINT_SESENDDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_SESENDDET_DEFAULT (_USB_GOTGINT_SESENDDET_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_SESREQSUCSTSCHNG (0x1UL << 8) /**< Session Request Success Status Change (host and device) */
#define USB_GOTGINT_SESREQSUCSTSCHNG (0x1UL << 8) /**< Session Request Success Status Change host and device */
#define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT 8 /**< Shift value for USB_SESREQSUCSTSCHNG */
#define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100UL /**< Bit mask for USB_SESREQSUCSTSCHNG */
#define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_HSTNEGSUCSTSCHNG (0x1UL << 9) /**< Host Negotiation Success Status Change (host and device) */
#define USB_GOTGINT_HSTNEGSUCSTSCHNG (0x1UL << 9) /**< Host Negotiation Success Status Change host and device */
#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT 9 /**< Shift value for USB_HSTNEGSUCSTSCHNG */
#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200UL /**< Bit mask for USB_HSTNEGSUCSTSCHNG */
#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_HSTNEGDET (0x1UL << 17) /**< Host Negotiation Detected (host and device) */
#define USB_GOTGINT_HSTNEGDET (0x1UL << 17) /**< Host Negotiation Detected host and device */
#define _USB_GOTGINT_HSTNEGDET_SHIFT 17 /**< Shift value for USB_HSTNEGDET */
#define _USB_GOTGINT_HSTNEGDET_MASK 0x20000UL /**< Bit mask for USB_HSTNEGDET */
#define _USB_GOTGINT_HSTNEGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_HSTNEGDET_DEFAULT (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_ADEVTOUTCHG (0x1UL << 18) /**< A-Device Timeout Change (host and device) */
#define USB_GOTGINT_ADEVTOUTCHG (0x1UL << 18) /**< A-Device Timeout Change host and device */
#define _USB_GOTGINT_ADEVTOUTCHG_SHIFT 18 /**< Shift value for USB_ADEVTOUTCHG */
#define _USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000UL /**< Bit mask for USB_ADEVTOUTCHG */
#define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_ADEVTOUTCHG_DEFAULT (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGINT */
#define USB_GOTGINT_DBNCEDONE (0x1UL << 19) /**< Debounce Done (host only) */
#define USB_GOTGINT_DBNCEDONE (0x1UL << 19) /**< Debounce Done host only */
#define _USB_GOTGINT_DBNCEDONE_SHIFT 19 /**< Shift value for USB_DBNCEDONE */
#define _USB_GOTGINT_DBNCEDONE_MASK 0x80000UL /**< Bit mask for USB_DBNCEDONE */
#define _USB_GOTGINT_DBNCEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
@ -456,7 +442,7 @@ typedef struct
/* Bit fields for USB GAHBCFG */
#define _USB_GAHBCFG_RESETVALUE 0x00000000UL /**< Default value for USB_GAHBCFG */
#define _USB_GAHBCFG_MASK 0x006001BFUL /**< Mask for USB_GAHBCFG */
#define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /**< Global Interrupt Mask (host and device) */
#define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /**< Global Interrupt Mask host and device */
#define _USB_GAHBCFG_GLBLINTRMSK_SHIFT 0 /**< Shift value for USB_GLBLINTRMSK */
#define _USB_GAHBCFG_GLBLINTRMSK_MASK 0x1UL /**< Bit mask for USB_GLBLINTRMSK */
#define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
@ -475,12 +461,12 @@ typedef struct
#define USB_GAHBCFG_HBSTLEN_INCR4 (_USB_GAHBCFG_HBSTLEN_INCR4 << 1) /**< Shifted mode INCR4 for USB_GAHBCFG */
#define USB_GAHBCFG_HBSTLEN_INCR8 (_USB_GAHBCFG_HBSTLEN_INCR8 << 1) /**< Shifted mode INCR8 for USB_GAHBCFG */
#define USB_GAHBCFG_HBSTLEN_INCR16 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1) /**< Shifted mode INCR16 for USB_GAHBCFG */
#define USB_GAHBCFG_DMAEN (0x1UL << 5) /**< DMA Enable (host and device) */
#define USB_GAHBCFG_DMAEN (0x1UL << 5) /**< DMA Enable host and device */
#define _USB_GAHBCFG_DMAEN_SHIFT 5 /**< Shift value for USB_DMAEN */
#define _USB_GAHBCFG_DMAEN_MASK 0x20UL /**< Bit mask for USB_DMAEN */
#define _USB_GAHBCFG_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
#define USB_GAHBCFG_DMAEN_DEFAULT (_USB_GAHBCFG_DMAEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GAHBCFG */
#define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /**< Non-Periodic TxFIFO Empty Level (host and device) */
#define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /**< Non-Periodic TxFIFO Empty Level host and device */
#define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT 7 /**< Shift value for USB_NPTXFEMPLVL */
#define _USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80UL /**< Bit mask for USB_NPTXFEMPLVL */
#define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
@ -489,7 +475,7 @@ typedef struct
#define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GAHBCFG */
#define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
#define USB_GAHBCFG_NPTXFEMPLVL_EMPTY (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7) /**< Shifted mode EMPTY for USB_GAHBCFG */
#define USB_GAHBCFG_PTXFEMPLVL (0x1UL << 8) /**< Periodic TxFIFO Empty Level (host only) */
#define USB_GAHBCFG_PTXFEMPLVL (0x1UL << 8) /**< Periodic TxFIFO Empty Level host only */
#define _USB_GAHBCFG_PTXFEMPLVL_SHIFT 8 /**< Shift value for USB_PTXFEMPLVL */
#define _USB_GAHBCFG_PTXFEMPLVL_MASK 0x100UL /**< Bit mask for USB_PTXFEMPLVL */
#define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
@ -516,17 +502,17 @@ typedef struct
#define _USB_GUSBCFG_TOUTCAL_MASK 0x7UL /**< Bit mask for USB_TOUTCAL */
#define _USB_GUSBCFG_TOUTCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_TOUTCAL_DEFAULT (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_FSINTF (0x1UL << 5) /**< Full-Speed Serial Interface Select (host and device) */
#define USB_GUSBCFG_FSINTF (0x1UL << 5) /**< Full-Speed Serial Interface Select host and device */
#define _USB_GUSBCFG_FSINTF_SHIFT 5 /**< Shift value for USB_FSINTF */
#define _USB_GUSBCFG_FSINTF_MASK 0x20UL /**< Bit mask for USB_FSINTF */
#define _USB_GUSBCFG_FSINTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_FSINTF_DEFAULT (_USB_GUSBCFG_FSINTF_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_SRPCAP (0x1UL << 8) /**< SRP-Capable (host and device) */
#define USB_GUSBCFG_SRPCAP (0x1UL << 8) /**< SRP-Capable host and device */
#define _USB_GUSBCFG_SRPCAP_SHIFT 8 /**< Shift value for USB_SRPCAP */
#define _USB_GUSBCFG_SRPCAP_MASK 0x100UL /**< Bit mask for USB_SRPCAP */
#define _USB_GUSBCFG_SRPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_SRPCAP_DEFAULT (_USB_GUSBCFG_SRPCAP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_HNPCAP (0x1UL << 9) /**< HNP-Capable (host and device) */
#define USB_GUSBCFG_HNPCAP (0x1UL << 9) /**< HNP-Capable host and device */
#define _USB_GUSBCFG_HNPCAP_SHIFT 9 /**< Shift value for USB_HNPCAP */
#define _USB_GUSBCFG_HNPCAP_MASK 0x200UL /**< Bit mask for USB_HNPCAP */
#define _USB_GUSBCFG_HNPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
@ -535,7 +521,7 @@ typedef struct
#define _USB_GUSBCFG_USBTRDTIM_MASK 0x3C00UL /**< Bit mask for USB_USBTRDTIM */
#define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /**< TermSel DLine Pulsing Selection (device only) */
#define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /**< TermSel DLine Pulsing Selection device only */
#define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /**< Shift value for USB_TERMSELDLPULSE */
#define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /**< Bit mask for USB_TERMSELDLPULSE */
#define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
@ -544,22 +530,22 @@ typedef struct
#define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_TERMSELDLPULSE_TXVALID (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */
#define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */
#define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /**< Tx End Delay (device only) */
#define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /**< Tx End Delay device only */
#define _USB_GUSBCFG_TXENDDELAY_SHIFT 28 /**< Shift value for USB_TXENDDELAY */
#define _USB_GUSBCFG_TXENDDELAY_MASK 0x10000000UL /**< Bit mask for USB_TXENDDELAY */
#define _USB_GUSBCFG_TXENDDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_TXENDDELAY_DEFAULT (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_FORCEHSTMODE (0x1UL << 29) /**< Force Host Mode (host and device) */
#define USB_GUSBCFG_FORCEHSTMODE (0x1UL << 29) /**< Force Host Mode host and device */
#define _USB_GUSBCFG_FORCEHSTMODE_SHIFT 29 /**< Shift value for USB_FORCEHSTMODE */
#define _USB_GUSBCFG_FORCEHSTMODE_MASK 0x20000000UL /**< Bit mask for USB_FORCEHSTMODE */
#define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_FORCEHSTMODE_DEFAULT (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_FORCEDEVMODE (0x1UL << 30) /**< Force Device Mode (host and device) */
#define USB_GUSBCFG_FORCEDEVMODE (0x1UL << 30) /**< Force Device Mode host and device */
#define _USB_GUSBCFG_FORCEDEVMODE_SHIFT 30 /**< Shift value for USB_FORCEDEVMODE */
#define _USB_GUSBCFG_FORCEDEVMODE_MASK 0x40000000UL /**< Bit mask for USB_FORCEDEVMODE */
#define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_FORCEDEVMODE_DEFAULT (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /**< Corrupt Tx packet (host and device) */
#define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /**< Corrupt Tx packet host and device */
#define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT 31 /**< Shift value for USB_CORRUPTTXPKT */
#define _USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000UL /**< Bit mask for USB_CORRUPTTXPKT */
#define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
@ -568,22 +554,22 @@ typedef struct
/* Bit fields for USB GRSTCTL */
#define _USB_GRSTCTL_RESETVALUE 0x80000000UL /**< Default value for USB_GRSTCTL */
#define _USB_GRSTCTL_MASK 0xC00007F5UL /**< Mask for USB_GRSTCTL */
#define USB_GRSTCTL_CSFTRST (0x1UL << 0) /**< Core Soft Reset (host and device) */
#define USB_GRSTCTL_CSFTRST (0x1UL << 0) /**< Core Soft Reset host and device */
#define _USB_GRSTCTL_CSFTRST_SHIFT 0 /**< Shift value for USB_CSFTRST */
#define _USB_GRSTCTL_CSFTRST_MASK 0x1UL /**< Bit mask for USB_CSFTRST */
#define _USB_GRSTCTL_CSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_CSFTRST_DEFAULT (_USB_GRSTCTL_CSFTRST_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_FRMCNTRRST (0x1UL << 2) /**< Host Frame Counter Reset (host only) */
#define USB_GRSTCTL_FRMCNTRRST (0x1UL << 2) /**< Host Frame Counter Reset host only */
#define _USB_GRSTCTL_FRMCNTRRST_SHIFT 2 /**< Shift value for USB_FRMCNTRRST */
#define _USB_GRSTCTL_FRMCNTRRST_MASK 0x4UL /**< Bit mask for USB_FRMCNTRRST */
#define _USB_GRSTCTL_FRMCNTRRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_FRMCNTRRST_DEFAULT (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /**< RxFIFO Flush (host and device) */
#define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /**< RxFIFO Flush host and device */
#define _USB_GRSTCTL_RXFFLSH_SHIFT 4 /**< Shift value for USB_RXFFLSH */
#define _USB_GRSTCTL_RXFFLSH_MASK 0x10UL /**< Bit mask for USB_RXFFLSH */
#define _USB_GRSTCTL_RXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_RXFFLSH_DEFAULT (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /**< TxFIFO Flush (host and device) */
#define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /**< TxFIFO Flush host and device */
#define _USB_GRSTCTL_TXFFLSH_SHIFT 5 /**< Shift value for USB_TXFFLSH */
#define _USB_GRSTCTL_TXFFLSH_MASK 0x20UL /**< Bit mask for USB_TXFFLSH */
#define _USB_GRSTCTL_TXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
@ -608,12 +594,12 @@ typedef struct
#define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /**< Shifted mode F5 for USB_GRSTCTL */
#define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /**< Shifted mode F6 for USB_GRSTCTL */
#define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /**< Shifted mode FALL for USB_GRSTCTL */
#define USB_GRSTCTL_DMAREQ (0x1UL << 30) /**< DMA Request Signal (host and device) */
#define USB_GRSTCTL_DMAREQ (0x1UL << 30) /**< DMA Request Signal host and device */
#define _USB_GRSTCTL_DMAREQ_SHIFT 30 /**< Shift value for USB_DMAREQ */
#define _USB_GRSTCTL_DMAREQ_MASK 0x40000000UL /**< Bit mask for USB_DMAREQ */
#define _USB_GRSTCTL_DMAREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_DMAREQ_DEFAULT (_USB_GRSTCTL_DMAREQ_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GRSTCTL */
#define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /**< AHB Master Idle (host and device) */
#define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /**< AHB Master Idle host and device */
#define _USB_GRSTCTL_AHBIDLE_SHIFT 31 /**< Shift value for USB_AHBIDLE */
#define _USB_GRSTCTL_AHBIDLE_MASK 0x80000000UL /**< Bit mask for USB_AHBIDLE */
#define _USB_GRSTCTL_AHBIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GRSTCTL */
@ -621,8 +607,8 @@ typedef struct
/* Bit fields for USB GINTSTS */
#define _USB_GINTSTS_RESETVALUE 0x14000020UL /**< Default value for USB_GINTSTS */
#define _USB_GINTSTS_MASK 0xF7FC7CFFUL /**< Mask for USB_GINTSTS */
#define USB_GINTSTS_CURMOD (0x1UL << 0) /**< Current Mode of Operation (host and device) */
#define _USB_GINTSTS_MASK 0xF7FCFCFFUL /**< Mask for USB_GINTSTS */
#define USB_GINTSTS_CURMOD (0x1UL << 0) /**< Current Mode of Operation host and device */
#define _USB_GINTSTS_CURMOD_SHIFT 0 /**< Shift value for USB_CURMOD */
#define _USB_GINTSTS_CURMOD_MASK 0x1UL /**< Bit mask for USB_CURMOD */
#define _USB_GINTSTS_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
@ -631,127 +617,132 @@ typedef struct
#define USB_GINTSTS_CURMOD_DEFAULT (_USB_GINTSTS_CURMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_CURMOD_DEVICE (_USB_GINTSTS_CURMOD_DEVICE << 0) /**< Shifted mode DEVICE for USB_GINTSTS */
#define USB_GINTSTS_CURMOD_HOST (_USB_GINTSTS_CURMOD_HOST << 0) /**< Shifted mode HOST for USB_GINTSTS */
#define USB_GINTSTS_MODEMIS (0x1UL << 1) /**< Mode Mismatch Interrupt (host and device) */
#define USB_GINTSTS_MODEMIS (0x1UL << 1) /**< Mode Mismatch Interrupt host and device */
#define _USB_GINTSTS_MODEMIS_SHIFT 1 /**< Shift value for USB_MODEMIS */
#define _USB_GINTSTS_MODEMIS_MASK 0x2UL /**< Bit mask for USB_MODEMIS */
#define _USB_GINTSTS_MODEMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_MODEMIS_DEFAULT (_USB_GINTSTS_MODEMIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_OTGINT (0x1UL << 2) /**< OTG Interrupt (host and device) */
#define USB_GINTSTS_OTGINT (0x1UL << 2) /**< OTG Interrupt host and device */
#define _USB_GINTSTS_OTGINT_SHIFT 2 /**< Shift value for USB_OTGINT */
#define _USB_GINTSTS_OTGINT_MASK 0x4UL /**< Bit mask for USB_OTGINT */
#define _USB_GINTSTS_OTGINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_OTGINT_DEFAULT (_USB_GINTSTS_OTGINT_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_SOF (0x1UL << 3) /**< Start of Frame (host and device) */
#define USB_GINTSTS_SOF (0x1UL << 3) /**< Start of Frame host and device */
#define _USB_GINTSTS_SOF_SHIFT 3 /**< Shift value for USB_SOF */
#define _USB_GINTSTS_SOF_MASK 0x8UL /**< Bit mask for USB_SOF */
#define _USB_GINTSTS_SOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_SOF_DEFAULT (_USB_GINTSTS_SOF_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_RXFLVL (0x1UL << 4) /**< RxFIFO Non-Empty (host and device) */
#define USB_GINTSTS_RXFLVL (0x1UL << 4) /**< RxFIFO Non-Empty host and device */
#define _USB_GINTSTS_RXFLVL_SHIFT 4 /**< Shift value for USB_RXFLVL */
#define _USB_GINTSTS_RXFLVL_MASK 0x10UL /**< Bit mask for USB_RXFLVL */
#define _USB_GINTSTS_RXFLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_RXFLVL_DEFAULT (_USB_GINTSTS_RXFLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_NPTXFEMP (0x1UL << 5) /**< Non-Periodic TxFIFO Empty (host only) */
#define USB_GINTSTS_NPTXFEMP (0x1UL << 5) /**< Non-Periodic TxFIFO Empty host only */
#define _USB_GINTSTS_NPTXFEMP_SHIFT 5 /**< Shift value for USB_NPTXFEMP */
#define _USB_GINTSTS_NPTXFEMP_MASK 0x20UL /**< Bit mask for USB_NPTXFEMP */
#define _USB_GINTSTS_NPTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_NPTXFEMP_DEFAULT (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /**< Global IN Non-periodic NAK Effective (device only) */
#define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /**< Global IN Non-periodic NAK Effective device only */
#define _USB_GINTSTS_GINNAKEFF_SHIFT 6 /**< Shift value for USB_GINNAKEFF */
#define _USB_GINTSTS_GINNAKEFF_MASK 0x40UL /**< Bit mask for USB_GINNAKEFF */
#define _USB_GINTSTS_GINNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_GINNAKEFF_DEFAULT (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /**< Global OUT NAK Effective (device only) */
#define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /**< Global OUT NAK Effective device only */
#define _USB_GINTSTS_GOUTNAKEFF_SHIFT 7 /**< Shift value for USB_GOUTNAKEFF */
#define _USB_GINTSTS_GOUTNAKEFF_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFF */
#define _USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_GOUTNAKEFF_DEFAULT (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /**< Early Suspend (device only) */
#define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /**< Early Suspend device only */
#define _USB_GINTSTS_ERLYSUSP_SHIFT 10 /**< Shift value for USB_ERLYSUSP */
#define _USB_GINTSTS_ERLYSUSP_MASK 0x400UL /**< Bit mask for USB_ERLYSUSP */
#define _USB_GINTSTS_ERLYSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_ERLYSUSP_DEFAULT (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_USBSUSP (0x1UL << 11) /**< USB Suspend (device only) */
#define USB_GINTSTS_USBSUSP (0x1UL << 11) /**< USB Suspend device only */
#define _USB_GINTSTS_USBSUSP_SHIFT 11 /**< Shift value for USB_USBSUSP */
#define _USB_GINTSTS_USBSUSP_MASK 0x800UL /**< Bit mask for USB_USBSUSP */
#define _USB_GINTSTS_USBSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_USBSUSP_DEFAULT (_USB_GINTSTS_USBSUSP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_USBRST (0x1UL << 12) /**< USB Reset (device only) */
#define USB_GINTSTS_USBRST (0x1UL << 12) /**< USB Reset device only */
#define _USB_GINTSTS_USBRST_SHIFT 12 /**< Shift value for USB_USBRST */
#define _USB_GINTSTS_USBRST_MASK 0x1000UL /**< Bit mask for USB_USBRST */
#define _USB_GINTSTS_USBRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_USBRST_DEFAULT (_USB_GINTSTS_USBRST_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_ENUMDONE (0x1UL << 13) /**< Enumeration Done (device only) */
#define USB_GINTSTS_ENUMDONE (0x1UL << 13) /**< Enumeration Done device only */
#define _USB_GINTSTS_ENUMDONE_SHIFT 13 /**< Shift value for USB_ENUMDONE */
#define _USB_GINTSTS_ENUMDONE_MASK 0x2000UL /**< Bit mask for USB_ENUMDONE */
#define _USB_GINTSTS_ENUMDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_ENUMDONE_DEFAULT (_USB_GINTSTS_ENUMDONE_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt (device only) */
#define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt device only */
#define _USB_GINTSTS_ISOOUTDROP_SHIFT 14 /**< Shift value for USB_ISOOUTDROP */
#define _USB_GINTSTS_ISOOUTDROP_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROP */
#define _USB_GINTSTS_ISOOUTDROP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_ISOOUTDROP_DEFAULT (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_IEPINT (0x1UL << 18) /**< IN Endpoints Interrupt (device only) */
#define USB_GINTSTS_EOPF (0x1UL << 15) /**< End of Periodic Frame Interrupt */
#define _USB_GINTSTS_EOPF_SHIFT 15 /**< Shift value for USB_EOPF */
#define _USB_GINTSTS_EOPF_MASK 0x8000UL /**< Bit mask for USB_EOPF */
#define _USB_GINTSTS_EOPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_EOPF_DEFAULT (_USB_GINTSTS_EOPF_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_IEPINT (0x1UL << 18) /**< IN Endpoints Interrupt device only */
#define _USB_GINTSTS_IEPINT_SHIFT 18 /**< Shift value for USB_IEPINT */
#define _USB_GINTSTS_IEPINT_MASK 0x40000UL /**< Bit mask for USB_IEPINT */
#define _USB_GINTSTS_IEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_IEPINT_DEFAULT (_USB_GINTSTS_IEPINT_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_OEPINT (0x1UL << 19) /**< OUT Endpoints Interrupt (device only) */
#define USB_GINTSTS_OEPINT (0x1UL << 19) /**< OUT Endpoints Interrupt device only */
#define _USB_GINTSTS_OEPINT_SHIFT 19 /**< Shift value for USB_OEPINT */
#define _USB_GINTSTS_OEPINT_MASK 0x80000UL /**< Bit mask for USB_OEPINT */
#define _USB_GINTSTS_OEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_OEPINT_DEFAULT (_USB_GINTSTS_OEPINT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /**< Incomplete Isochronous IN Transfer (device only) */
#define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /**< Incomplete Isochronous IN Transfer device only */
#define _USB_GINTSTS_INCOMPISOIN_SHIFT 20 /**< Shift value for USB_INCOMPISOIN */
#define _USB_GINTSTS_INCOMPISOIN_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOIN */
#define _USB_GINTSTS_INCOMPISOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_INCOMPISOIN_DEFAULT (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_INCOMPLP (0x1UL << 21) /**< Incomplete Periodic Transfer (device only) */
#define USB_GINTSTS_INCOMPLP (0x1UL << 21) /**< Incomplete Periodic Transfer host and device */
#define _USB_GINTSTS_INCOMPLP_SHIFT 21 /**< Shift value for USB_INCOMPLP */
#define _USB_GINTSTS_INCOMPLP_MASK 0x200000UL /**< Bit mask for USB_INCOMPLP */
#define _USB_GINTSTS_INCOMPLP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_INCOMPLP_DEFAULT (_USB_GINTSTS_INCOMPLP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_FETSUSP (0x1UL << 22) /**< Data Fetch Suspended (device only) */
#define USB_GINTSTS_FETSUSP (0x1UL << 22) /**< Data Fetch Suspended device only */
#define _USB_GINTSTS_FETSUSP_SHIFT 22 /**< Shift value for USB_FETSUSP */
#define _USB_GINTSTS_FETSUSP_MASK 0x400000UL /**< Bit mask for USB_FETSUSP */
#define _USB_GINTSTS_FETSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_FETSUSP_DEFAULT (_USB_GINTSTS_FETSUSP_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_RESETDET (0x1UL << 23) /**< Reset detected Interrupt (device only) */
#define USB_GINTSTS_RESETDET (0x1UL << 23) /**< Reset detected Interrupt device only */
#define _USB_GINTSTS_RESETDET_SHIFT 23 /**< Shift value for USB_RESETDET */
#define _USB_GINTSTS_RESETDET_MASK 0x800000UL /**< Bit mask for USB_RESETDET */
#define _USB_GINTSTS_RESETDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_RESETDET_DEFAULT (_USB_GINTSTS_RESETDET_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_PRTINT (0x1UL << 24) /**< Host Port Interrupt (host only) */
#define USB_GINTSTS_PRTINT (0x1UL << 24) /**< Host Port Interrupt host only */
#define _USB_GINTSTS_PRTINT_SHIFT 24 /**< Shift value for USB_PRTINT */
#define _USB_GINTSTS_PRTINT_MASK 0x1000000UL /**< Bit mask for USB_PRTINT */
#define _USB_GINTSTS_PRTINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_PRTINT_DEFAULT (_USB_GINTSTS_PRTINT_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_HCHINT (0x1UL << 25) /**< Host Channels Interrupt (host only) */
#define USB_GINTSTS_HCHINT (0x1UL << 25) /**< Host Channels Interrupt host only */
#define _USB_GINTSTS_HCHINT_SHIFT 25 /**< Shift value for USB_HCHINT */
#define _USB_GINTSTS_HCHINT_MASK 0x2000000UL /**< Bit mask for USB_HCHINT */
#define _USB_GINTSTS_HCHINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_HCHINT_DEFAULT (_USB_GINTSTS_HCHINT_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_PTXFEMP (0x1UL << 26) /**< Periodic TxFIFO Empty (host only) */
#define USB_GINTSTS_PTXFEMP (0x1UL << 26) /**< Periodic TxFIFO Empty host only */
#define _USB_GINTSTS_PTXFEMP_SHIFT 26 /**< Shift value for USB_PTXFEMP */
#define _USB_GINTSTS_PTXFEMP_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMP */
#define _USB_GINTSTS_PTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_PTXFEMP_DEFAULT (_USB_GINTSTS_PTXFEMP_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_CONIDSTSCHNG (0x1UL << 28) /**< Connector ID Status Change (host and device) */
#define USB_GINTSTS_CONIDSTSCHNG (0x1UL << 28) /**< Connector ID Status Change host and device */
#define _USB_GINTSTS_CONIDSTSCHNG_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNG */
#define _USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNG */
#define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_CONIDSTSCHNG_DEFAULT (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_DISCONNINT (0x1UL << 29) /**< Disconnect Detected Interrupt (host only) */
#define USB_GINTSTS_DISCONNINT (0x1UL << 29) /**< Disconnect Detected Interrupt host only */
#define _USB_GINTSTS_DISCONNINT_SHIFT 29 /**< Shift value for USB_DISCONNINT */
#define _USB_GINTSTS_DISCONNINT_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINT */
#define _USB_GINTSTS_DISCONNINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_DISCONNINT_DEFAULT (_USB_GINTSTS_DISCONNINT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_SESSREQINT (0x1UL << 30) /**< Session Request/New Session Detected Interrupt (host and device) */
#define USB_GINTSTS_SESSREQINT (0x1UL << 30) /**< Session Request/New Session Detected Interrupt host and device */
#define _USB_GINTSTS_SESSREQINT_SHIFT 30 /**< Shift value for USB_SESSREQINT */
#define _USB_GINTSTS_SESSREQINT_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINT */
#define _USB_GINTSTS_SESSREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_SESSREQINT_DEFAULT (_USB_GINTSTS_SESSREQINT_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTSTS */
#define USB_GINTSTS_WKUPINT (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt (host and device) */
#define USB_GINTSTS_WKUPINT (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt host and device */
#define _USB_GINTSTS_WKUPINT_SHIFT 31 /**< Shift value for USB_WKUPINT */
#define _USB_GINTSTS_WKUPINT_MASK 0x80000000UL /**< Bit mask for USB_WKUPINT */
#define _USB_GINTSTS_WKUPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
@ -759,128 +750,133 @@ typedef struct
/* Bit fields for USB GINTMSK */
#define _USB_GINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_GINTMSK */
#define _USB_GINTMSK_MASK 0xF7FC7CFEUL /**< Mask for USB_GINTMSK */
#define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /**< Mode Mismatch Interrupt Mask (host and device) */
#define _USB_GINTMSK_MASK 0xF7FCFCFEUL /**< Mask for USB_GINTMSK */
#define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /**< Mode Mismatch Interrupt Mask host and device */
#define _USB_GINTMSK_MODEMISMSK_SHIFT 1 /**< Shift value for USB_MODEMISMSK */
#define _USB_GINTMSK_MODEMISMSK_MASK 0x2UL /**< Bit mask for USB_MODEMISMSK */
#define _USB_GINTMSK_MODEMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_MODEMISMSK_DEFAULT (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_OTGINTMSK (0x1UL << 2) /**< OTG Interrupt Mask (host and device) */
#define USB_GINTMSK_OTGINTMSK (0x1UL << 2) /**< OTG Interrupt Mask host and device */
#define _USB_GINTMSK_OTGINTMSK_SHIFT 2 /**< Shift value for USB_OTGINTMSK */
#define _USB_GINTMSK_OTGINTMSK_MASK 0x4UL /**< Bit mask for USB_OTGINTMSK */
#define _USB_GINTMSK_OTGINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_OTGINTMSK_DEFAULT (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_SOFMSK (0x1UL << 3) /**< Start of Frame Mask (host and device) */
#define USB_GINTMSK_SOFMSK (0x1UL << 3) /**< Start of Frame Mask host and device */
#define _USB_GINTMSK_SOFMSK_SHIFT 3 /**< Shift value for USB_SOFMSK */
#define _USB_GINTMSK_SOFMSK_MASK 0x8UL /**< Bit mask for USB_SOFMSK */
#define _USB_GINTMSK_SOFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_SOFMSK_DEFAULT (_USB_GINTMSK_SOFMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /**< Receive FIFO Non-Empty Mask (host and device) */
#define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /**< Receive FIFO Non-Empty Mask host and device */
#define _USB_GINTMSK_RXFLVLMSK_SHIFT 4 /**< Shift value for USB_RXFLVLMSK */
#define _USB_GINTMSK_RXFLVLMSK_MASK 0x10UL /**< Bit mask for USB_RXFLVLMSK */
#define _USB_GINTMSK_RXFLVLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_RXFLVLMSK_DEFAULT (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_NPTXFEMPMSK (0x1UL << 5) /**< Non-Periodic TxFIFO Empty Mask (host only) */
#define USB_GINTMSK_NPTXFEMPMSK (0x1UL << 5) /**< Non-Periodic TxFIFO Empty Mask host only */
#define _USB_GINTMSK_NPTXFEMPMSK_SHIFT 5 /**< Shift value for USB_NPTXFEMPMSK */
#define _USB_GINTMSK_NPTXFEMPMSK_MASK 0x20UL /**< Bit mask for USB_NPTXFEMPMSK */
#define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_NPTXFEMPMSK_DEFAULT (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /**< Global Non-periodic IN NAK Effective Mask (device only) */
#define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /**< Global Non-periodic IN NAK Effective Mask device only */
#define _USB_GINTMSK_GINNAKEFFMSK_SHIFT 6 /**< Shift value for USB_GINNAKEFFMSK */
#define _USB_GINTMSK_GINNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_GINNAKEFFMSK */
#define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_GINNAKEFFMSK_DEFAULT (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /**< Global OUT NAK Effective Mask (device only) */
#define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /**< Global OUT NAK Effective Mask device only */
#define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT 7 /**< Shift value for USB_GOUTNAKEFFMSK */
#define _USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFFMSK */
#define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /**< Early Suspend Mask (device only) */
#define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /**< Early Suspend Mask device only */
#define _USB_GINTMSK_ERLYSUSPMSK_SHIFT 10 /**< Shift value for USB_ERLYSUSPMSK */
#define _USB_GINTMSK_ERLYSUSPMSK_MASK 0x400UL /**< Bit mask for USB_ERLYSUSPMSK */
#define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_ERLYSUSPMSK_DEFAULT (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /**< USB Suspend Mask (device only) */
#define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /**< USB Suspend Mask device only */
#define _USB_GINTMSK_USBSUSPMSK_SHIFT 11 /**< Shift value for USB_USBSUSPMSK */
#define _USB_GINTMSK_USBSUSPMSK_MASK 0x800UL /**< Bit mask for USB_USBSUSPMSK */
#define _USB_GINTMSK_USBSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_USBSUSPMSK_DEFAULT (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /**< USB Reset Mask (device only) */
#define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /**< USB Reset Mask device only */
#define _USB_GINTMSK_USBRSTMSK_SHIFT 12 /**< Shift value for USB_USBRSTMSK */
#define _USB_GINTMSK_USBRSTMSK_MASK 0x1000UL /**< Bit mask for USB_USBRSTMSK */
#define _USB_GINTMSK_USBRSTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_USBRSTMSK_DEFAULT (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /**< Enumeration Done Mask (device only) */
#define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /**< Enumeration Done Mask device only */
#define _USB_GINTMSK_ENUMDONEMSK_SHIFT 13 /**< Shift value for USB_ENUMDONEMSK */
#define _USB_GINTMSK_ENUMDONEMSK_MASK 0x2000UL /**< Bit mask for USB_ENUMDONEMSK */
#define _USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_ENUMDONEMSK_DEFAULT (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt Mask (device only) */
#define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt Mask device only */
#define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT 14 /**< Shift value for USB_ISOOUTDROPMSK */
#define _USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROPMSK */
#define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /**< IN Endpoints Interrupt Mask (device only) */
#define USB_GINTMSK_EOPFMSK (0x1UL << 15) /**< End of Periodic Frame Interrupt Mask device only */
#define _USB_GINTMSK_EOPFMSK_SHIFT 15 /**< Shift value for USB_EOPFMSK */
#define _USB_GINTMSK_EOPFMSK_MASK 0x8000UL /**< Bit mask for USB_EOPFMSK */
#define _USB_GINTMSK_EOPFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_EOPFMSK_DEFAULT (_USB_GINTMSK_EOPFMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /**< IN Endpoints Interrupt Mask device only */
#define _USB_GINTMSK_IEPINTMSK_SHIFT 18 /**< Shift value for USB_IEPINTMSK */
#define _USB_GINTMSK_IEPINTMSK_MASK 0x40000UL /**< Bit mask for USB_IEPINTMSK */
#define _USB_GINTMSK_IEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_IEPINTMSK_DEFAULT (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /**< OUT Endpoints Interrupt Mask (device only) */
#define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /**< OUT Endpoints Interrupt Mask device only */
#define _USB_GINTMSK_OEPINTMSK_SHIFT 19 /**< Shift value for USB_OEPINTMSK */
#define _USB_GINTMSK_OEPINTMSK_MASK 0x80000UL /**< Bit mask for USB_OEPINTMSK */
#define _USB_GINTMSK_OEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_OEPINTMSK_DEFAULT (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /**< Incomplete Isochronous IN Transfer Mask (device only) */
#define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /**< Incomplete Isochronous IN Transfer Mask device only */
#define _USB_GINTMSK_INCOMPISOINMSK_SHIFT 20 /**< Shift value for USB_INCOMPISOINMSK */
#define _USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOINMSK */
#define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_INCOMPISOINMSK_DEFAULT (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /**< Incomplete Periodic Transfer Mask (host only) */
#define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /**< Incomplete Periodic Transfer Mask host and device */
#define _USB_GINTMSK_INCOMPLPMSK_SHIFT 21 /**< Shift value for USB_INCOMPLPMSK */
#define _USB_GINTMSK_INCOMPLPMSK_MASK 0x200000UL /**< Bit mask for USB_INCOMPLPMSK */
#define _USB_GINTMSK_INCOMPLPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_INCOMPLPMSK_DEFAULT (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /**< Data Fetch Suspended Mask (device only) */
#define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /**< Data Fetch Suspended Mask device only */
#define _USB_GINTMSK_FETSUSPMSK_SHIFT 22 /**< Shift value for USB_FETSUSPMSK */
#define _USB_GINTMSK_FETSUSPMSK_MASK 0x400000UL /**< Bit mask for USB_FETSUSPMSK */
#define _USB_GINTMSK_FETSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_FETSUSPMSK_DEFAULT (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /**< Reset detected Interrupt Mask (device only) */
#define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /**< Reset detected Interrupt Mask device only */
#define _USB_GINTMSK_RESETDETMSK_SHIFT 23 /**< Shift value for USB_RESETDETMSK */
#define _USB_GINTMSK_RESETDETMSK_MASK 0x800000UL /**< Bit mask for USB_RESETDETMSK */
#define _USB_GINTMSK_RESETDETMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_RESETDETMSK_DEFAULT (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_PRTINTMSK (0x1UL << 24) /**< Host Port Interrupt Mask (host only) */
#define USB_GINTMSK_PRTINTMSK (0x1UL << 24) /**< Host Port Interrupt Mask host only */
#define _USB_GINTMSK_PRTINTMSK_SHIFT 24 /**< Shift value for USB_PRTINTMSK */
#define _USB_GINTMSK_PRTINTMSK_MASK 0x1000000UL /**< Bit mask for USB_PRTINTMSK */
#define _USB_GINTMSK_PRTINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_PRTINTMSK_DEFAULT (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_HCHINTMSK (0x1UL << 25) /**< Host Channels Interrupt Mask (host only) */
#define USB_GINTMSK_HCHINTMSK (0x1UL << 25) /**< Host Channels Interrupt Mask host only */
#define _USB_GINTMSK_HCHINTMSK_SHIFT 25 /**< Shift value for USB_HCHINTMSK */
#define _USB_GINTMSK_HCHINTMSK_MASK 0x2000000UL /**< Bit mask for USB_HCHINTMSK */
#define _USB_GINTMSK_HCHINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_HCHINTMSK_DEFAULT (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_PTXFEMPMSK (0x1UL << 26) /**< Periodic TxFIFO Empty Mask (host only) */
#define USB_GINTMSK_PTXFEMPMSK (0x1UL << 26) /**< Periodic TxFIFO Empty Mask host only */
#define _USB_GINTMSK_PTXFEMPMSK_SHIFT 26 /**< Shift value for USB_PTXFEMPMSK */
#define _USB_GINTMSK_PTXFEMPMSK_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMPMSK */
#define _USB_GINTMSK_PTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_PTXFEMPMSK_DEFAULT (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_CONIDSTSCHNGMSK (0x1UL << 28) /**< Connector ID Status Change Mask (host and device) */
#define USB_GINTMSK_CONIDSTSCHNGMSK (0x1UL << 28) /**< Connector ID Status Change Mask host and device */
#define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNGMSK */
#define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNGMSK */
#define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_DISCONNINTMSK (0x1UL << 29) /**< Disconnect Detected Interrupt Mask (host and device) */
#define USB_GINTMSK_DISCONNINTMSK (0x1UL << 29) /**< Disconnect Detected Interrupt Mask host and device */
#define _USB_GINTMSK_DISCONNINTMSK_SHIFT 29 /**< Shift value for USB_DISCONNINTMSK */
#define _USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINTMSK */
#define _USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_DISCONNINTMSK_DEFAULT (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_SESSREQINTMSK (0x1UL << 30) /**< Session Request/New Session Detected Interrupt Mask (host and device) */
#define USB_GINTMSK_SESSREQINTMSK (0x1UL << 30) /**< Session Request/New Session Detected Interrupt Mask host and device */
#define _USB_GINTMSK_SESSREQINTMSK_SHIFT 30 /**< Shift value for USB_SESSREQINTMSK */
#define _USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINTMSK */
#define _USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_SESSREQINTMSK_DEFAULT (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTMSK */
#define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt Mask (host and device) */
#define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt Mask host and device */
#define _USB_GINTMSK_WKUPINTMSK_SHIFT 31 /**< Shift value for USB_WKUPINTMSK */
#define _USB_GINTMSK_WKUPINTMSK_MASK 0x80000000UL /**< Bit mask for USB_WKUPINTMSK */
#define _USB_GINTMSK_WKUPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
@ -2657,5 +2653,5 @@ typedef struct
#define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
/** @} End of group EFM32GG_USB */
/** @} End of group Parts */

12
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_diep.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_usb_diep.h
* @brief EFM32GG_USB_DIEP register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief USB_DIEP EFM32GG USB DIEP
*****************************************************************************/
@ -41,7 +45,9 @@ typedef struct
__IO uint32_t TSIZ; /**< Device IN Endpoint x+1 Transfer Size Register */
__IO uint32_t DMAADDR; /**< Device IN Endpoint x+1 DMA Address Register */
__I uint32_t TXFSTS; /**< Device IN Endpoint x+1 Transmit FIFO Status Register */
uint32_t RESERVED2[1]; /**< Reserved future */
} USB_DIEP_TypeDef;
/** @} End of group Parts */

12
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_doep.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_usb_doep.h
* @brief EFM32GG_USB_DOEP register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief USB_DOEP EFM32GG USB DOEP
*****************************************************************************/
@ -40,7 +44,9 @@ typedef struct
uint32_t RESERVED1[1]; /**< Reserved for future use **/
__IO uint32_t TSIZ; /**< Device OUT Endpoint x+1 Transfer Size Register */
__IO uint32_t DMAADDR; /**< Device OUT Endpoint x+1 DMA Address Register */
uint32_t RESERVED2[2]; /**< Reserved future */
} USB_DOEP_TypeDef;
/** @} End of group Parts */

12
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_hc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_usb_hc.h
* @brief EFM32GG_USB_HC register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief USB_HC EFM32GG USB HC
*****************************************************************************/
@ -40,7 +44,9 @@ typedef struct
__IO uint32_t INTMSK; /**< Host Channel x Interrupt Mask Register */
__IO uint32_t TSIZ; /**< Host Channel x Transfer Size Register */
__IO uint32_t DMAADDR; /**< Host Channel x DMA Address Register */
uint32_t RESERVED1[2]; /**< Reserved future */
} USB_HC_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_vcmp.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_vcmp.h
* @brief EFM32GG_VCMP register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_VCMP
* @{
@ -192,5 +196,5 @@ typedef struct
#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
/** @} End of group EFM32GG_VCMP */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_wdog.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32gg_wdog.h
* @brief EFM32GG_WDOG register and bit field definitions
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32GG_WDOG
* @{
@ -128,5 +132,5 @@ typedef struct
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
/** @} End of group EFM32GG_WDOG */
/** @} End of group Parts */

27
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/em_device.h
View File

@ -9,11 +9,13 @@
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "em_device.h" to your source files
*
*
* @endverbatim
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,19 +31,18 @@
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifndef __EM_DEVICE_H
#define __EM_DEVICE_H
#ifndef EM_DEVICE_H
#define EM_DEVICE_H
#if defined(EFM32GG230F1024)
#include "efm32gg230f1024.h"
@ -133,6 +134,12 @@
#elif defined(EFM32GG895F512)
#include "efm32gg895f512.h"
#elif defined(EFM32GG900F1024)
#include "efm32gg900f1024.h"
#elif defined(EFM32GG900F512)
#include "efm32gg900f512.h"
#elif defined(EFM32GG940F1024)
#include "efm32gg940f1024.h"
@ -163,9 +170,7 @@
#elif defined(EFM32GG995F512)
#include "efm32gg995f512.h"
#else
#error "em_device.h: PART NUMBER undefined"
#endif
#endif
#endif /* EM_DEVICE_H */

55
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.c
View File

@ -1,10 +1,10 @@
/***************************************************************************//**
* @file system_efm32gg.c
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -20,12 +20,12 @@
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
@ -54,27 +54,27 @@
/* SW footprint. */
#ifndef EFM32_HFXO_FREQ
#ifdef _EFM32_GIANT_FAMILY
#define EFM32_HFXO_FREQ (48000000UL)
#else
#define EFM32_HFXO_FREQ (32000000UL)
#endif
#endif
#define EFM32_HFRCO_MAX_FREQ (28000000UL)
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
@ -123,13 +123,11 @@ uint32_t SystemCoreClock;
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
#if defined (_EFM32_GIANT_FAMILY)
/* Leopard/Giant Gecko has an additional divider */
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
#endif
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
@ -139,6 +137,23 @@ uint32_t SystemCoreClockGet(void)
}
/***************************************************************************//**
* @brief
* Get the maximum core clock frequency.
*
* @note
* This is an EFR32 proprietary function, not part of the CMSIS definition.
*
* @return
* The maximum core clock frequency in Hz.
******************************************************************************/
uint32_t SystemMaxCoreClockGet(void)
{
return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
}
/***************************************************************************//**
* @brief
* Get the current HFCLK frequency.
@ -152,7 +167,7 @@ uint32_t SystemCoreClockGet(void)
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
@ -165,11 +180,11 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
@ -179,7 +194,7 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{

14
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.h
View File

@ -1,10 +1,10 @@
/***************************************************************************//**
* @file system_efm32gg.h
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.
* @version 3.20.6
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -30,8 +30,8 @@
*
*****************************************************************************/
#ifndef __SYSTEM_EFM32GG_H
#define __SYSTEM_EFM32GG_H
#ifndef SYSTEM_EFM32GG_H
#define SYSTEM_EFM32GG_H
#ifdef __cplusplus
extern "C" {
@ -50,7 +50,6 @@ extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
******************************************************************************/
/* Interrupt routines - prototypes */
#if defined(_EFM32_GIANT_FAMILY)
void Reset_Handler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
@ -61,6 +60,7 @@ void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA_IRQHandler(void);
void GPIO_EVEN_IRQHandler(void);
void TIMER0_IRQHandler(void);
@ -100,9 +100,9 @@ void MSC_IRQHandler(void);
void AES_IRQHandler(void);
void EBI_IRQHandler(void);
void EMU_IRQHandler(void);
#endif
uint32_t SystemCoreClockGet(void);
uint32_t SystemMaxCoreClockGet(void);
/**************************************************************************//**
* @brief
@ -135,4 +135,4 @@ void SystemLFXOClockSet(uint32_t freq);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_EFM32GG_H */
#endif /* SYSTEM_EFM32GG_H */

2
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/efm32hg.sct
View File

@ -8,7 +8,7 @@ LR_IROM1 0x00000000 0x00010000 { ; load region size_region
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000098 0x00001F68 { ; RW data
RW_IRAM1 0x20000094 0x00001F6C { ; RW data
.ANY (+RW +ZI)
}
}

2
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.S
View File

@ -2,7 +2,7 @@
; * @file startup_efm32hg.s
; * @brief CMSIS Core Device Startup File for
; * Silicon Labs EFM32HG Device Series
; * @version 3.20.12
; * @version 4.2.1
; * @date 03. February 2012
; *
; * @note

73
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg.ld
View File

@ -6,8 +6,9 @@
/* */
/* Silicon Laboratories, Inc. 2015 */
/* */
/* Version 3.20.12 */
/* Version 4.2.0 */
/* */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 65536
@ -16,17 +17,21 @@ MEMORY
/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
* We make room for the table at the very beginning of RAM, i.e. at
* 0x20000000. We need (16+21) * sizeof(uint32_t) = 144 bytes for EFM32HG */
* 0x20000000. We need (16+21) * sizeof(uint32_t) = 148 bytes for EFM32HG */
__vector_size = 0x94;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
@ -44,6 +49,8 @@ __vector_size = 0x94;
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
@ -51,7 +58,11 @@ SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
@ -76,7 +87,7 @@ SECTIONS
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
@ -88,15 +99,49 @@ SECTIONS
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*("dma")
PROVIDE( __start_vector_table__ = .);
. += __vector_size;
PROVIDE( __end_vector_table__ = .);
. += __vector_size;
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
. = ALIGN (4);
@ -122,6 +167,7 @@ SECTIONS
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
@ -130,27 +176,30 @@ SECTIONS
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap :
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
_end = __end__;
*(.heap*)
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
.stack_dummy (COPY):
{
*(.stack)
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by

415
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/startup_efm32hg.S
View File

@ -1,194 +1,309 @@
/* @file startup_efm32hg.S
* @brief startup file for Silicon Labs EFM32HG devices.
* For use with GCC for ARM Embedded Processors
* @version 3.20.12
* Date: 08 Feb 2012
* @version 4.2.1
* Date: 12 June 2014
*
* Copyright (c) 2012, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv6-m
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.section .stack
.align 3
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.size __StackTop, . - __StackTop
.section .heap
.align 3
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x0
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 8
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA_IRQHandler /* 0 - DMA */
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
.long TIMER0_IRQHandler /* 2 - TIMER0 */
.long ACMP0_IRQHandler /* 3 - ACMP0 */
.long ADC0_IRQHandler /* 4 - ADC0 */
.long I2C0_IRQHandler /* 5 - I2C0 */
.long GPIO_ODD_IRQHandler /* 6 - GPIO_ODD */
.long TIMER1_IRQHandler /* 7 - TIMER1 */
.long USART1_RX_IRQHandler /* 8 - USART1_RX */
.long USART1_TX_IRQHandler /* 9 - USART1_TX */
.long LEUART0_IRQHandler /* 10 - LEUART0 */
.long PCNT0_IRQHandler /* 11 - PCNT0 */
.long RTC_IRQHandler /* 12 - RTC */
.long CMU_IRQHandler /* 13 - CMU */
.long VCMP_IRQHandler /* 14 - VCMP */
.long MSC_IRQHandler /* 15 - MSC */
.long AES_IRQHandler /* 16 - AES */
.long USART0_RX_IRQHandler /* 17 - USART0_RX */
.long USART0_TX_IRQHandler /* 18 - USART0_TX */
.long USB_IRQHandler /* 19 - USB */
.long TIMER2_IRQHandler /* 20 - TIMER2 */
.long DMA_IRQHandler /* 0 - DMA */
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
.long TIMER0_IRQHandler /* 2 - TIMER0 */
.long ACMP0_IRQHandler /* 3 - ACMP0 */
.long ADC0_IRQHandler /* 4 - ADC0 */
.long I2C0_IRQHandler /* 5 - I2C0 */
.long GPIO_ODD_IRQHandler /* 6 - GPIO_ODD */
.long TIMER1_IRQHandler /* 7 - TIMER1 */
.long USART1_RX_IRQHandler /* 8 - USART1_RX */
.long USART1_TX_IRQHandler /* 9 - USART1_TX */
.long LEUART0_IRQHandler /* 10 - LEUART0 */
.long PCNT0_IRQHandler /* 11 - PCNT0 */
.long RTC_IRQHandler /* 12 - RTC */
.long CMU_IRQHandler /* 13 - CMU */
.long VCMP_IRQHandler /* 14 - VCMP */
.long MSC_IRQHandler /* 15 - MSC */
.long AES_IRQHandler /* 16 - AES */
.long USART0_RX_IRQHandler /* 17 - USART0_RX */
.long USART0_TX_IRQHandler /* 18 - USART0_TX */
.long USB_IRQHandler /* 19 - USB */
.long TIMER2_IRQHandler /* 20 - TIMER2 */
.size __isr_vector, . - __isr_vector
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
#ifndef __NO_SYSTEM_INIT
ldr r0, =SystemInit
blx r0
ldr r0, =SystemInit
blx r0
#endif
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
.flash_to_ram_loop:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .flash_to_ram_loop
.flash_to_ram_loop_end:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __START
#define __START _start
#endif
bl __START
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name:
b .
.size \handler_name, . - \handler_name
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler Default_Handler
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA_IRQHandler
def_irq_handler GPIO_EVEN_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler ACMP0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler GPIO_ODD_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler USART1_RX_IRQHandler
def_irq_handler USART1_TX_IRQHandler
def_irq_handler LEUART0_IRQHandler
def_irq_handler PCNT0_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler CMU_IRQHandler
def_irq_handler VCMP_IRQHandler
def_irq_handler MSC_IRQHandler
def_irq_handler AES_IRQHandler
def_irq_handler USART0_RX_IRQHandler
def_irq_handler USART0_TX_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler DMA_IRQHandler
def_irq_handler GPIO_EVEN_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler ACMP0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler GPIO_ODD_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler USART1_RX_IRQHandler
def_irq_handler USART1_TX_IRQHandler
def_irq_handler LEUART0_IRQHandler
def_irq_handler PCNT0_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler CMU_IRQHandler
def_irq_handler VCMP_IRQHandler
def_irq_handler MSC_IRQHandler
def_irq_handler AES_IRQHandler
def_irq_handler USART0_RX_IRQHandler
def_irq_handler USART0_TX_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler TIMER2_IRQHandler
.end

13
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h
View File

@ -2,10 +2,10 @@
* @file efm32hg322f64.h
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32HG322F64
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -31,8 +31,8 @@
*
*****************************************************************************/
#ifndef __SILICON_LABS_EFM32HG322F64_H__
#define __SILICON_LABS_EFM32HG322F64_H__
#ifndef EFM32HG322F64_H
#define EFM32HG322F64_H
#ifdef __cplusplus
extern "C" {
@ -224,6 +224,9 @@ typedef enum IRQn
/** @} End of group EFM32HG322F64_Part */
#ifndef ARM_MATH_CM0PLUS
#define ARM_MATH_CM0PLUS
#endif
#include "arm_math.h" /* To get __CLZ definitions etc. */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system_efm32hg.h" /* System Header */
@ -396,4 +399,4 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
#endif /* __SILICON_LABS_EFM32HG322F64_H__ */
#endif /* EFM32HG322F64_H */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_acmp.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_acmp.h
* @brief EFM32HG_ACMP register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_ACMP
* @{
@ -325,5 +329,5 @@ typedef struct
#define ACMP_ROUTE_LOCATION_LOC3 (_ACMP_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for ACMP_ROUTE */
/** @} End of group EFM32HG_ACMP */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_adc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_adc.h
* @brief EFM32HG_ADC register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_ADC
* @{
@ -651,5 +655,5 @@ typedef struct
#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
/** @} End of group EFM32HG_ADC */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_aes.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_aes.h
* @brief EFM32HG_AES register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_AES
* @{
@ -189,5 +193,5 @@ typedef struct
#define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
/** @} End of group EFM32HG_AES */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_pins.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_af_pins.h
* @brief EFM32HG_AF_PINS register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_AF_Pins
* @{
@ -79,5 +83,5 @@
#define AF_DBG_SWCLK_PIN(i) ((i) == 0 ? 0 : -1)
/** @} End of group EFM32HG_AF_Pins */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_ports.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_af_ports.h
* @brief EFM32HG_AF_PORTS register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_AF_Ports
* @{
@ -79,5 +83,5 @@
#define AF_DBG_SWCLK_PORT(i) ((i) == 0 ? 5 : -1)
/** @} End of group EFM32HG_AF_Ports */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_calibrate.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_calibrate.h
* @brief EFM32HG_CALIBRATE register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_CALIBRATE
* @{
@ -41,3 +45,6 @@ typedef struct
__I uint32_t VALUE; /**< Default value for calibration register */
} CALIBRATE_TypeDef; /** @} */
/** @} End of group Parts */

12
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_cmu.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_cmu.h
* @brief EFM32HG_CMU register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_CMU
* @{
@ -84,7 +88,7 @@ typedef struct
*****************************************************************************/
/* Bit fields for CMU CTRL */
#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */
#define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
#define _CMU_CTRL_MASK 0x07FFFEEFUL /**< Mask for CMU_CTRL */
#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
@ -1198,5 +1202,5 @@ typedef struct
#define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */
/** @} End of group EFM32HG_CMU */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_devinfo.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_devinfo.h
* @brief EFM32HG_DEVINFO register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_DEVINFO
* @{
@ -152,9 +156,10 @@ typedef struct
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
/** @} End of group EFM32HG_DEVINFO */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_dma.h
* @brief EFM32HG_DMA register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_DMA
* @{
@ -884,5 +888,5 @@ typedef struct
#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
/** @} End of group EFM32HG_DMA */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_ch.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_dma_ch.h
* @brief EFM32HG_DMA_CH register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief DMA_CH EFM32HG DMA CH
*****************************************************************************/
@ -37,3 +41,6 @@ typedef struct
__IO uint32_t CTRL; /**< Channel Control Register */
} DMA_CH_TypeDef;
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_descriptor.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_dma_descriptor.h
* @brief EFM32HG_DMA_DESCRIPTOR register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_DMA_DESCRIPTOR
* @{
@ -43,3 +47,6 @@ typedef struct
__IO uint32_t USER; /**< DMA padding register, available for user */
} DMA_DESCRIPTOR_TypeDef; /** @} */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmactrl.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_dmactrl.h
* @brief EFM32HG_DMACTRL register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_DMACTRL_BitFields
@ -132,5 +136,5 @@
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
/** @} End of group EFM32HG_DMA */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmareq.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_dmareq.h
* @brief EFM32HG_DMAREQ register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_DMAREQ_BitFields
@ -68,5 +72,5 @@
#define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
/** @} End of group EFM32HG_DMAREQ */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_emu.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_emu.h
* @brief EFM32HG_EMU register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_EMU
* @{
@ -98,5 +102,5 @@ typedef struct
#define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
/** @} End of group EFM32HG_EMU */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_gpio.h
* @brief EFM32HG_GPIO register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_GPIO
* @{
@ -1146,5 +1150,5 @@ typedef struct
#define GPIO_EM4WUCAUSE_EM4WUCAUSE_C4 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_C4 << 0) /**< Shifted mode C4 for GPIO_EM4WUCAUSE */
/** @} End of group EFM32HG_GPIO */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio_p.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_gpio_p.h
* @brief EFM32HG_GPIO_P register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief GPIO_P EFM32HG GPIO P
*****************************************************************************/
@ -45,3 +49,6 @@ typedef struct
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
} GPIO_P_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_i2c.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_i2c.h
* @brief EFM32HG_I2C register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_I2C
* @{
@ -697,5 +701,5 @@ typedef struct
#define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */
/** @} End of group EFM32HG_I2C */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_idac.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_idac.h
* @brief EFM32HG_IDAC register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_IDAC
* @{
@ -144,5 +148,5 @@ typedef struct
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
/** @} End of group EFM32HG_IDAC */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_leuart.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_leuart.h
* @brief EFM32HG_LEUART register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_LEUART
* @{
@ -685,5 +689,5 @@ typedef struct
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_INPUT */
/** @} End of group EFM32HG_LEUART */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_msc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_msc.h
* @brief EFM32HG_MSC register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_MSC
* @{
@ -408,5 +412,5 @@ typedef struct
#define MSC_IRQLATENCY_IRQLATENCY_DEFAULT (_MSC_IRQLATENCY_IRQLATENCY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IRQLATENCY */
/** @} End of group EFM32HG_MSC */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_mtb.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_mtb.h
* @brief EFM32HG_MTB register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_MTB
* @{
@ -115,5 +119,5 @@ typedef struct
#define MTB_BASE_BASE_DEFAULT (_MTB_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_BASE */
/** @} End of group EFM32HG_MTB */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_pcnt.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_pcnt.h
* @brief EFM32HG_PCNT register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_PCNT
* @{
@ -478,5 +482,5 @@ typedef struct
#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
/** @} End of group EFM32HG_PCNT */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_prs.h
* @brief EFM32HG_PRS register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_PRS
* @{
@ -350,5 +354,5 @@ typedef struct
#define PRS_TRACECTRL_TSTOP_PRSCH5 (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
/** @} End of group EFM32HG_PRS */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_ch.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_prs_ch.h
* @brief EFM32HG_PRS_CH register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief PRS_CH EFM32HG PRS CH
*****************************************************************************/
@ -37,3 +41,6 @@ typedef struct
__IO uint32_t CTRL; /**< Channel Control Register */
} PRS_CH_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_signals.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_prs_signals.h
* @brief EFM32HG_PRS_SIGNALS register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @addtogroup EFM32HG_PRS_Signals
* @{
@ -83,5 +87,5 @@
#define PRS_PCNT0_TCC ((54 << 16) + 0) /**< PRS Triggered compare match */
/** @} End of group EFM32HG_PRS */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rmu.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_rmu.h
* @brief EFM32HG_RMU register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_RMU
* @{
@ -124,5 +128,5 @@ typedef struct
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
/** @} End of group EFM32HG_RMU */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_romtable.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_romtable.h
* @brief EFM32HG_ROMTABLE register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_ROMTABLE
* @{
@ -64,5 +68,5 @@ typedef struct
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
/** @} End of group EFM32HG_ROMTABLE */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rtc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_rtc.h
* @brief EFM32HG_RTC register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_RTC
* @{
@ -210,5 +214,5 @@ typedef struct
#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
/** @} End of group EFM32HG_RTC */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_timer.h
* @brief EFM32HG_TIMER register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_TIMER
* @{
@ -947,5 +951,5 @@ typedef struct
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
/** @} End of group EFM32HG_TIMER */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer_cc.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_timer_cc.h
* @brief EFM32HG_TIMER_CC register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief TIMER_CC EFM32HG TIMER CC
*****************************************************************************/
@ -40,3 +44,6 @@ typedef struct
__IO uint32_t CCVB; /**< CC Channel Buffer Register */
} TIMER_CC_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usart.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_usart.h
* @brief EFM32HG_USART register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_USART
* @{
@ -1141,5 +1145,5 @@ typedef struct
#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
/** @} End of group EFM32HG_USART */
/** @} End of group Parts */

12
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_usb.h
* @brief EFM32HG_USB register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_USB
* @{
@ -802,7 +806,7 @@ typedef struct
#define USB_DCFG_RESVALID_DEFAULT (_USB_DCFG_RESVALID_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DCFG */
/* Bit fields for USB DCTL */
#define _USB_DCTL_RESETVALUE 0x00000000UL /**< Default value for USB_DCTL */
#define _USB_DCTL_RESETVALUE 0x00000002UL /**< Default value for USB_DCTL */
#define _USB_DCTL_MASK 0x00018FFFUL /**< Mask for USB_DCTL */
#define USB_DCTL_RMTWKUPSIG (0x1UL << 0) /**< Remote Wakeup Signaling */
#define _USB_DCTL_RMTWKUPSIG_SHIFT 0 /**< Shift value for USB_RMTWKUPSIG */
@ -1789,5 +1793,5 @@ typedef struct
#define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
/** @} End of group EFM32HG_USB */
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_diep.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_usb_diep.h
* @brief EFM32HG_USB_DIEP register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief USB_DIEP EFM32HG USB DIEP
*****************************************************************************/
@ -44,3 +48,6 @@ typedef struct
uint32_t RESERVED2[1]; /**< Reserved future */
} USB_DIEP_TypeDef;
/** @} End of group Parts */

11
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_doep.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_usb_doep.h
* @brief EFM32HG_USB_DOEP register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief USB_DOEP EFM32HG USB DOEP
*****************************************************************************/
@ -43,3 +47,6 @@ typedef struct
uint32_t RESERVED2[2]; /**< Reserved future */
} USB_DOEP_TypeDef;
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_vcmp.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_vcmp.h
* @brief EFM32HG_VCMP register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_VCMP
* @{
@ -192,5 +196,5 @@ typedef struct
#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
/** @} End of group EFM32HG_VCMP */
/** @} End of group Parts */

10
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_wdog.h
View File

@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_wdog.h
* @brief EFM32HG_WDOG register and bit field definitions
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -29,6 +29,10 @@
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32HG_WDOG
* @{
@ -128,5 +132,5 @@ typedef struct
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
/** @} End of group EFM32HG_WDOG */
/** @} End of group Parts */

15
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/em_device.h
View File

@ -9,11 +9,13 @@
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "em_device.h" to your source files
*
*
* @endverbatim
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -39,9 +41,8 @@
*
*****************************************************************************/
#ifndef __SILICON_LABS_EM_DEVICE_H__
#define __SILICON_LABS_EM_DEVICE_H__
#ifndef EM_DEVICE_H
#define EM_DEVICE_H
#if defined(EFM32HG108F32)
#include "efm32hg108f32.h"
@ -103,9 +104,7 @@
#elif defined(EFM32HG350F64)
#include "efm32hg350f64.h"
#else
#error "em_device.h: PART NUMBER undefined"
#endif
#endif /* __SILICON_LABS_EM_DEVICE_H__ */
#endif /* EM_DEVICE_H */

22
libraries/mbed/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/system_efm32hg.c
View File

@ -1,10 +1,10 @@
/***************************************************************************//**
* @file system_efm32hg.c
* @brief CMSIS Cortex-M0+ System Layer for EFM32HG devices.
* @version 3.20.12
* @version 4.2.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
* <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@ -54,9 +54,11 @@
/* SW footprint. */
#ifndef EFM32_HFXO_FREQ
#define EFM32_HFXO_FREQ (24000000UL)
#define EFM32_HFRCO_MAX_FREQ (21000000UL)
#define EFM32_HFXO_FREQ (24000000UL)
#endif
#define EFM32_HFRCO_MAX_FREQ (21000000UL)
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@ -68,6 +70,7 @@ static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@ -156,9 +159,12 @@ uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL |
CMU_STATUS_USHFRCODIV2SEL))
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL
| CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL
#if defined(CMU_STATUS_USHFRCODIV2SEL)
| CMU_STATUS_USHFRCODIV2SEL
#endif
))
{
case CMU_STATUS_LFXOSEL:
#if (EFM32_LFXO_FREQ > 0)
@ -184,9 +190,11 @@ uint32_t SystemHFClockGet(void)
#endif
break;
#if defined(CMU_STATUS_USHFRCODIV2SEL)
case CMU_STATUS_USHFRCODIV2SEL:
ret = 24000000;
break;
#endif
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)

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