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Merge pull request #1588 from adustm/master 

[STM32F7] Update STM32F7Cube_FW version
pull/1596/head
Martin Kojtal 2016-03-07 09:45:59 +00:00
parent 57543e50d2 c97e05f496
commit ee20d03969
152 changed files with 4874 additions and 2252 deletions
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53
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
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10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 28-April-2015
;* Version : V1.0.2
;* Date : 21-September-2015
;* Description : STM32F746xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -350,12 +350,12 @@ Default_Handler PROC
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct
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@ -1,6 +1,6 @@
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2015, STMicroelectronics
; Copyright (c) 2016, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without

10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 28-April-2015
;* Version : V1.0.2
;* Date : 21-September-2015
;* Description : STM32F746xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -323,12 +323,12 @@ Default_Handler PROC
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct
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@ -1,6 +1,6 @@
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2015, STMicroelectronics
; Copyright (c) 2016, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
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@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32f746xx.s
* @author MCD Application Team
* Version V1.0.0
* Date 28-April-2015
* @Version V1.0.2
* @Date 21-September-2015
* @brief STM32F746xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S
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@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 28-April-2015
;* Version : V1.0.2
;* Date : 21-September-2015
;* Description : STM32F746xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h
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@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c
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@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -27,7 +27,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h
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@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c
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@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h
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@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

122
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f746xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,7 +64,7 @@
* @brief STM32F7xx Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum IRQn
typedef enum
{
/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
@ -125,7 +125,7 @@ typedef enum IRQn
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
@ -182,14 +182,14 @@ typedef enum IRQn
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
#define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */
#define __CM7_REV 0x0001 /*!< Cortex-M7 revision r0p1 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
#include "system_stm32f7xx.h"
@ -353,6 +353,7 @@ typedef struct
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
@ -697,11 +698,10 @@ typedef struct
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Power Control
*/
@ -967,7 +967,6 @@ typedef struct
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
@ -1002,6 +1001,7 @@ typedef struct
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
@ -1140,7 +1140,8 @@ typedef struct
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
@ -1148,13 +1149,13 @@ typedef struct
#define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */
#define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
#define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */
#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */
#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */
#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
/* Legacy define */
@ -1226,7 +1227,7 @@ typedef struct
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
/*!< AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
@ -3125,6 +3126,7 @@ typedef struct
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
@ -3216,6 +3218,7 @@ typedef struct
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
/* Debug MCU */
@ -3291,7 +3294,7 @@ typedef struct
#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
@ -3841,8 +3844,6 @@ typedef struct
#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@ -4877,6 +4878,7 @@ typedef struct
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
@ -4891,7 +4893,7 @@ typedef struct
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@ -4905,6 +4907,9 @@ typedef struct
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
/* Legacy define */
#define I2C_CR1_DFN I2C_CR1_DNF /*!< Digital noise filter */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@ -5163,7 +5168,6 @@ typedef struct
#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
/******************************************************************************/
/* */
/* Power Control */
@ -5453,6 +5457,7 @@ typedef struct
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
@ -6496,7 +6501,7 @@ typedef struct
#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
#define SAI_xCR2_CPL ((uint32_t)0x00002000) /*!< Complement Bit */
#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
@ -6907,13 +6912,15 @@ typedef struct
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
@ -7540,6 +7547,7 @@ typedef struct
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
@ -7705,6 +7713,7 @@ typedef struct
#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */
#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */
@ -7775,35 +7784,57 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 ((uint32_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T_1 ((uint32_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T_2 ((uint32_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T_3 ((uint32_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T_4 ((uint32_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T_5 ((uint32_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T_6 ((uint32_t)0x40) /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
/* Legacy defines */
#define WWDG_CR_T0 WWDG_CR_T_0 /*!<Bit 0 */
#define WWDG_CR_T1 WWDG_CR_T_1 /*!<Bit 1 */
#define WWDG_CR_T2 WWDG_CR_T_2 /*!<Bit 2 */
#define WWDG_CR_T3 WWDG_CR_T_3 /*!<Bit 3 */
#define WWDG_CR_T4 WWDG_CR_T_4 /*!<Bit 4 */
#define WWDG_CR_T5 WWDG_CR_T_5 /*!<Bit 5 */
#define WWDG_CR_T6 WWDG_CR_T_6 /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 ((uint32_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W_1 ((uint32_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W_2 ((uint32_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W_3 ((uint32_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W_4 ((uint32_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W_5 ((uint32_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W_6 ((uint32_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
/* Legacy defines */
#define WWDG_CFR_W0 WWDG_CFR_W_0 /*!<Bit 0 */
#define WWDG_CFR_W1 WWDG_CFR_W_1 /*!<Bit 1 */
#define WWDG_CFR_W2 WWDG_CFR_W_2 /*!<Bit 2 */
#define WWDG_CFR_W3 WWDG_CFR_W_3 /*!<Bit 3 */
#define WWDG_CFR_W4 WWDG_CFR_W_4 /*!<Bit 4 */
#define WWDG_CFR_W5 WWDG_CFR_W_5 /*!<Bit 5 */
#define WWDG_CFR_W6 WWDG_CFR_W_6 /*!<Bit 6 */
#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 ((uint32_t)0x0080) /*!<Bit 0 */
#define WWDG_CFR_WDGTB_1 ((uint32_t)0x0100) /*!<Bit 1 */
/* Legacy defines */
#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 /*!<Bit 0 */
#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 /*!<Bit 1 */
#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
@ -8476,6 +8507,7 @@ typedef struct
#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
#define USB_OTG_DOEPMSK_OTEPSPRM ((uint32_t)0x00000020) /*!< Status Phase Received mask */
#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
@ -8943,6 +8975,7 @@ typedef struct
#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_OTEPSPR ((uint32_t)0x00000020) /*!< Status Phase Received For Control Write */
#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
@ -8989,6 +9022,7 @@ typedef struct
/******************************* DCMI Instances *******************************/
#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
/******************************* DMA2D Instances *******************************/
#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
@ -9059,6 +9093,7 @@ typedef struct
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@ -9075,7 +9110,6 @@ typedef struct
/******************************** SDMMC Instances *******************************/
#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
/****************************** SPDIFRX Instances *********************************/
#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h
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@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f7xx_hal_conf_template.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f7xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

168
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -39,7 +39,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -109,14 +109,13 @@ HAL_StatusTypeDef HAL_Init(void);
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
on EVAL board as data memory */
on STMicroelectronics EVAL/Discovery boards as data memory */
/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
need to be added in the project preprocessor to avoid SDRAM multiple configuration
(the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
/* #define DATA_IN_ExtSRAM */
/* #define DATA_IN_ExtSDRAM */
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
@ -218,7 +217,7 @@ void SystemInit(void)
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
@ -336,7 +335,151 @@ void SystemCoreClockUpdate(void)
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0;
#if defined (DATA_IN_ExtSDRAM)
#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index;
/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x55550545;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x55554145;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCCC000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xFF800FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x55400555;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CC00CC;
GPIOG->AFR[1] = 0xC00000CC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x80220AAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0x80320FFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x40110555;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x55550450;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00145555;
/*-- FMC Configuration ------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[4] = 0x00001091;
FMC_Bank1->BTCR[5] = 0x00110212;
FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
/* Configure and enable SDRAM bank1 */
FMC_Bank5_6->SDCR[0] = 0x000019E5;
FMC_Bank5_6->SDTR[0] = 0x01116361;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x000000F3;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#elif defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index;
@ -473,9 +616,8 @@ void SystemInit_ExtMemCtl(void)
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */
#if defined(DATA_IN_ExtSRAM)
#elif defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 28-April-2015
;* Version : V1.0.2
;* Date : 21-September-2015
;* Description : STM32F746xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 28-April-2015
;* Version : V1.0.2
;* Date : 21-September-2015
;* Description : STM32F746xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32f746xx.s
* @author MCD Application Team
* Version V1.0.0
* Date 28-April-2015
* @Version V1.0.2
* @Date 21-September-2015
* @brief STM32F746xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/startup_stm32f746xx.S
View File

@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 28-April-2015
;* Version : V1.0.2
;* Date : 21-September-2015
;* Description : STM32F746xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP

122
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f746xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,7 +64,7 @@
* @brief STM32F7xx Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum IRQn
typedef enum
{
/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
@ -125,7 +125,7 @@ typedef enum IRQn
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
@ -182,14 +182,14 @@ typedef enum IRQn
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
#define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */
#define __CM7_REV 0x0001 /*!< Cortex-M7 revision r0p1 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
#include "system_stm32f7xx.h"
@ -353,6 +353,7 @@ typedef struct
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
@ -697,11 +698,10 @@ typedef struct
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Power Control
*/
@ -967,7 +967,6 @@ typedef struct
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
@ -1002,6 +1001,7 @@ typedef struct
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
@ -1140,7 +1140,8 @@ typedef struct
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
@ -1148,13 +1149,13 @@ typedef struct
#define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */
#define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
#define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */
#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */
#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */
#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */
#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
/* Legacy define */
@ -1226,7 +1227,7 @@ typedef struct
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
/*!< AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
@ -3125,6 +3126,7 @@ typedef struct
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
@ -3216,6 +3218,7 @@ typedef struct
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
/* Debug MCU */
@ -3291,7 +3294,7 @@ typedef struct
#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
@ -3841,8 +3844,6 @@ typedef struct
#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@ -4877,6 +4878,7 @@ typedef struct
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
@ -4891,7 +4893,7 @@ typedef struct
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@ -4905,6 +4907,9 @@ typedef struct
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
/* Legacy define */
#define I2C_CR1_DFN I2C_CR1_DNF /*!< Digital noise filter */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@ -5163,7 +5168,6 @@ typedef struct
#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
/******************************************************************************/
/* */
/* Power Control */
@ -5453,6 +5457,7 @@ typedef struct
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
@ -6496,7 +6501,7 @@ typedef struct
#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
#define SAI_xCR2_CPL ((uint32_t)0x00002000) /*!< Complement Bit */
#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
@ -6907,13 +6912,15 @@ typedef struct
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
@ -7540,6 +7547,7 @@ typedef struct
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
@ -7705,6 +7713,7 @@ typedef struct
#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */
#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */
@ -7775,35 +7784,57 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 ((uint32_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T_1 ((uint32_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T_2 ((uint32_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T_3 ((uint32_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T_4 ((uint32_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T_5 ((uint32_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T_6 ((uint32_t)0x40) /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
/* Legacy defines */
#define WWDG_CR_T0 WWDG_CR_T_0 /*!<Bit 0 */
#define WWDG_CR_T1 WWDG_CR_T_1 /*!<Bit 1 */
#define WWDG_CR_T2 WWDG_CR_T_2 /*!<Bit 2 */
#define WWDG_CR_T3 WWDG_CR_T_3 /*!<Bit 3 */
#define WWDG_CR_T4 WWDG_CR_T_4 /*!<Bit 4 */
#define WWDG_CR_T5 WWDG_CR_T_5 /*!<Bit 5 */
#define WWDG_CR_T6 WWDG_CR_T_6 /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 ((uint32_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W_1 ((uint32_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W_2 ((uint32_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W_3 ((uint32_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W_4 ((uint32_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W_5 ((uint32_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W_6 ((uint32_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
/* Legacy defines */
#define WWDG_CFR_W0 WWDG_CFR_W_0 /*!<Bit 0 */
#define WWDG_CFR_W1 WWDG_CFR_W_1 /*!<Bit 1 */
#define WWDG_CFR_W2 WWDG_CFR_W_2 /*!<Bit 2 */
#define WWDG_CFR_W3 WWDG_CFR_W_3 /*!<Bit 3 */
#define WWDG_CFR_W4 WWDG_CFR_W_4 /*!<Bit 4 */
#define WWDG_CFR_W5 WWDG_CFR_W_5 /*!<Bit 5 */
#define WWDG_CFR_W6 WWDG_CFR_W_6 /*!<Bit 6 */
#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 ((uint32_t)0x0080) /*!<Bit 0 */
#define WWDG_CFR_WDGTB_1 ((uint32_t)0x0100) /*!<Bit 1 */
/* Legacy defines */
#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 /*!<Bit 0 */
#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 /*!<Bit 1 */
#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
@ -8476,6 +8507,7 @@ typedef struct
#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
#define USB_OTG_DOEPMSK_OTEPSPRM ((uint32_t)0x00000020) /*!< Status Phase Received mask */
#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
@ -8943,6 +8975,7 @@ typedef struct
#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_OTEPSPR ((uint32_t)0x00000020) /*!< Status Phase Received For Control Write */
#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
@ -8989,6 +9022,7 @@ typedef struct
/******************************* DCMI Instances *******************************/
#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
/******************************* DMA2D Instances *******************************/
#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
@ -9059,6 +9093,7 @@ typedef struct
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@ -9075,7 +9110,6 @@ typedef struct
/******************************** SDMMC Instances *******************************/
#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
/****************************** SPDIFRX Instances *********************************/
#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h
View File

@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f7xx_hal_conf_template.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f7xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

392
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -39,7 +39,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -108,6 +108,14 @@ HAL_StatusTypeDef HAL_Init(void);
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
on STMicroelectronics EVAL/Discovery boards as data memory */
/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
need to be added in the project preprocessor to avoid SDRAM multiple configuration
(the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
/* #define DATA_IN_ExtSRAM */
/* #define DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
@ -153,6 +161,10 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif
@ -199,9 +211,13 @@ void SystemInit(void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
@ -307,6 +323,374 @@ void SystemCoreClockUpdate(void)
SystemCoreClock >>= tmp;
}
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f7xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0;
#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index;
/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x55550545;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x55554145;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCCC000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xFF800FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x55400555;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CC00CC;
GPIOG->AFR[1] = 0xC00000CC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x80220AAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0x80320FFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x40110555;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x55550450;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00145555;
/*-- FMC Configuration ------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[4] = 0x00001091;
FMC_Bank1->BTCR[5] = 0x00110212;
FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
/* Configure and enable SDRAM bank1 */
FMC_Bank5_6->SDCR[0] = 0x000019E5;
FMC_Bank5_6->SDTR[0] = 0x01116361;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x000000F3;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#elif defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register uint32_t index;
/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x50150005;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x55554005;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCCC000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x55400555;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CC00CC;
GPIOG->AFR[1] = 0xC000000C;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x80020A0A;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0x80020A0A;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x40010505;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x55550450;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00145555;
/*-- FMC Configuration ------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable SDRAM bank1 */
FMC_Bank5_6->SDCR[0] = 0x000019E5;
FMC_Bank5_6->SDTR[0] = 0x01116361;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x000000F3;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#elif defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x55550545;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x55554145;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x55000555;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00200AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x00300FFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00100555;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[4] = 0x00001091;
FMC_Bank1->BTCR[5] = 0x00110212;
FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
#endif /* DATA_IN_ExtSRAM */
(void)(tmp);
}
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.2
* @date 21-September-2015
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

561
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -102,7 +102,15 @@
#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
/**
* @}
*/
@ -121,11 +129,28 @@
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
/**
* @}
*/
/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
/**
* @}
*/
@ -255,7 +280,14 @@
#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
#define OB_WDG_SW OB_IWDG_SW
#define OB_WDG_HW OB_IWDG_HW
#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@ -264,14 +296,15 @@
* @{
*/
#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
/**
* @}
*/
@ -330,6 +363,26 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F3) || defined(STM32F1)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F3 */
/**
* @}
*/
@ -346,6 +399,15 @@
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
/**
* @}
*/
@ -804,7 +866,8 @@
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
@ -1178,23 +1241,166 @@
/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32F3)
#define COMP_START __HAL_COMP_ENABLE
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
__HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
__HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP7_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
__HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
# endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
/**
@ -1346,7 +1552,7 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@ -1355,8 +1561,8 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@ -2015,47 +2221,211 @@
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
/* alias define maintained for legacy */
#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
#define Sdmmc1ClockSelection SdioClockSelection
#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
@ -2065,13 +2435,14 @@
#endif
#if defined(STM32F7) || defined(STM32L4)
#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
#define SdioClockSelection Sdmmc1ClockSelection
#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
@ -2086,28 +2457,81 @@
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
#define IS_RCC_HCLK_DIV IS_RCC_PCLK
#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
#define IS_RCC_HCLK_DIV IS_RCC_PCLK
#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define RCC_MCO_NODIV RCC_MCODIV_1
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#if defined(STM32L0)
#define RCC_IT_LSECSS RCC_IT_CSSLSE
#define RCC_IT_CSS RCC_IT_CSSHSE
#endif
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
#define RCC_MCO_NODIV RCC_MCODIV_1
#define RCC_MCO_DIV1 RCC_MCODIV_1
#define RCC_MCO_DIV2 RCC_MCODIV_2
#define RCC_MCO_DIV4 RCC_MCODIV_4
#define RCC_MCO_DIV8 RCC_MCODIV_8
#define RCC_MCO_DIV16 RCC_MCODIV_16
#define RCC_MCO_DIV32 RCC_MCODIV_32
#define RCC_MCO_DIV64 RCC_MCODIV_64
#define RCC_MCO_DIV128 RCC_MCODIV_128
#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
#define HSION_BitNumber RCC_HSION_BIT_NUMBER
#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
#define LSION_BitNumber RCC_LSION_BIT_NUMBER
#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
@ -2128,9 +2552,18 @@
#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
#define CR_HSEON_BB RCC_CR_HSEON_BB
#define CSR_RMVF_BB RCC_CSR_RMVF_BB
#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
/**
* @}
*/

16
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -68,11 +68,11 @@
* @{
*/
/**
* @brief STM32F7xx HAL Driver version number V1.0.1
* @brief STM32F7xx HAL Driver version number V1.0.4
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@ -213,7 +213,7 @@ __weak void HAL_MspInit(void)
}
/**
* @brief DeInitializes the MSP.
* @brief DeInitializes the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
@ -309,7 +309,7 @@ __weak uint32_t HAL_GetTick(void)
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note ThiS function is declared as __weak to be overwritten in case of other
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @retval None
@ -327,7 +327,7 @@ __weak void HAL_Delay(__IO uint32_t Delay)
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the the SysTick interrupt will be disabled and so Tick increment
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
@ -343,7 +343,7 @@ __weak void HAL_SuspendTick(void)
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the the SysTick interrupt will be enabled and so Tick increment
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************

783
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
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File diff suppressed because it is too large Load Diff

266
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
@ -58,105 +58,97 @@
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
}HAL_ADC_StateTypeDef;
/**
* @brief ADC Init structure definition
*/
* @brief Structure definition of ADC and regular group initialization
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
all the ADCs.
This parameter can be a value of @ref ADC_ClockPrescaler */
uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
uint32_t Resolution; /*!< Configures the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
This parameter can be a value of @ref ADC_data_align */
uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
at the end of single channel conversion or at the end of all conversions.
This parameter can be a value of @ref ADC_EOCSelection */
uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
Scan direction is upward: from rank1 to rank 'n'. */
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
This parameter can be a value of @ref ADC_EOCSelection.
Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
after the selected trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
regular channel group.
uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
for regular channels.
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
using the sequencer for regular channel group.
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
If set to ADC_SOFTWARE_START, external triggers are disabled.
This parameter can be a value of @ref ADC_External_trigger_Source_Regular
Note: This parameter can be modified only if there is no conversion is ongoing. */
If set to external trigger source, triggering is on event rising edge by default.
This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_External_trigger_edge_Regular
Note: This parameter can be modified only if there is no conversion is ongoing. */
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
This parameter can be set to ENABLE or DISABLE. */
}ADC_InitTypeDef;
/**
* @brief ADC handle Structure definition
*/
typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC required parameters */
__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
/**
* @brief ADC Configuration regular Channel structure definition
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC can be either disabled or enabled without conversion on going on regular group.
*/
typedef struct
{
uint32_t Channel; /*!< The ADC channel to configure.
This parameter can be a value of @ref ADC_channels */
uint32_t Rank; /*!< The rank in the regular group sequencer.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
This parameter can be a value of @ref ADC_sampling_times */
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels */
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
This parameter can be a value of @ref ADC_sampling_times
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
}ADC_ChannelConfTypeDef;
/**
* @brief ADC Configuration multi-mode structure definition
* @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
@ -174,30 +166,83 @@ typedef struct
This parameter can be set to ENABLE or DISABLE */
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
}ADC_AnalogWDGConfTypeDef;
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
* @brief ADC handle Structure definition
*/
typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC required parameters */
__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state */
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
/**
* @}
*/
*/
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
@ -258,6 +303,8 @@ typedef struct
*/
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
@ -275,11 +322,12 @@ typedef struct
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
/**
* @}
*/
/** @defgroup ADC_data_align ADC Data Align
/** @defgroup ADC_data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
@ -533,8 +581,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
@ -565,6 +613,52 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
/* Macro reserved for internal HAL driver usage, not intended to be used in
code of final user */
/**
* @brief Verification of ADC state: enabled or disabled
* @param __HANDLE__: ADC handle
* @retval SET (ADC enabled) or RESET (ADC disabled)
*/
#define ADC_IS_ENABLE(__HANDLE__) \
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
) ? SET : RESET)
/**
* @brief Test if conversion trigger of regular group is software start
* or external trigger.
* @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger)
*/
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
/**
* @brief Test if conversion trigger of injected group is software start
* or external trigger.
* @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger)
*/
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
/**
* @brief Simultaneously clears and sets specific bits of the handle State
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
* the first parameter is the ADC handle State, the second parameter is the
* bit field to clear, the third and last parameter is the bit field to set.
* @retval None
*/
#define ADC_STATE_CLR_SET MODIFY_REG
/**
* @brief Clear ADC error code (set it to error code: "no error")
* @param __HANDLE__: ADC handle
* @retval None
*/
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \

601
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@ -131,25 +131,25 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup ADCEx_Private_Functions
* @{
*/
/* Private function prototypes -----------------------------------------------*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
* @{
*/
*/
/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
@ -182,17 +182,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
/* Check if a regular conversion is ongoing */
if(hadc->State == HAL_ADC_STATE_BUSY_REG)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ;
}
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
@ -201,7 +191,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
@ -210,30 +200,57 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
}
}
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
/* - Set state bitfield related to injected operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
HAL_ADC_STATE_INJ_BUSY);
/* Check if a regular conversion is ongoing */
/* Note: On this device, there is no ADC error code fields related to */
/* conversions on group injected only. In case of conversion on */
/* going on group regular, no error code is reset. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
@ -249,25 +266,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0;
uint32_t tmp1 = 0, tmp2 =0;
uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
/* Check if a regular conversion is ongoing */
if(hadc->State == HAL_ADC_STATE_BUSY_REG)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ;
}
/* Set ADC error code to none */
hadc->ErrorCode = HAL_ADC_ERROR_NONE;
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
@ -276,7 +280,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
@ -285,60 +289,122 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
}
}
/* Enable the ADC end of conversion interrupt for injected group */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Enable the ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
/* - Set state bitfield related to injected operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
HAL_ADC_STATE_INJ_BUSY);
/* Check if a regular conversion is ongoing */
/* Note: On this device, there is no ADC error code fields related to */
/* conversions on group injected only. In case of conversion on */
/* going on group regular, no error code is reset. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Enable end of conversion interrupt for injected channels */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables ADC and stop conversion of injected channels.
*
* @note Caution: This function will stop also regular channels.
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status.
* @brief Stop conversion of injected channels. Disable ADC peripheral if
* no regular conversion is on going.
* @note If ADC must be disabled and if conversion is on going on
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
* @note If injected group mode auto-injection is enabled,
* function HAL_ADC_Stop must be used.
* @note In case of auto-injection mode, HAL_ADC_Stop must be used.
* @param hadc: ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
{
/* Disable the Peripheral */
__HAL_ADC_DISABLE(hadc);
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Change ADC state */
hadc->State = HAL_ADC_STATE_READY;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion and disable ADC peripheral */
/* Conditioned to: */
/* - No conversion on the other group (regular group) is intended to */
/* continue (injected and regular groups stop conversion and ADC disable */
/* are common) */
/* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
{
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
return tmp_hal_status;
}
/**
@ -371,16 +437,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
}
}
/* Check if a regular conversion is ready */
if(hadc->State == HAL_ADC_STATE_EOC_REG)
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
/* Determine whether any further conversion upcoming on group injected */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F7, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_INJ;
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Return ADC state */
@ -388,30 +470,65 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
}
/**
* @brief Disables the interrupt and stop ADC conversion of injected channels.
*
* @note Caution: This function will stop also regular channels.
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status.
* @brief Stop conversion of injected channels, disable interruption of
* end-of-conversion. Disable ADC peripheral if no regular conversion
* is on going.
* @note If ADC must be disabled and if conversion is on going on
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
* @note If injected group mode auto-injection is enabled,
* function HAL_ADC_Stop must be used.
* @param hadc: ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
{
/* Disable the ADC end of conversion interrupt for regular group */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Disable the ADC end of conversion interrupt for injected group */
__HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Stop potential conversion and disable ADC peripheral */
/* Conditioned to: */
/* - No conversion on the other group (regular group) is intended to */
/* continue (injected and regular groups stop conversion and ADC disable */
/* are common) */
/* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
{
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable ADC end of conversion interrupt for injected channels */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
/* Enable the Peripheral */
__HAL_ADC_DISABLE(hadc);
/* Change ADC state */
hadc->State = HAL_ADC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
return tmp_hal_status;
}
/**
@ -433,8 +550,9 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
/* Check the parameters */
assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
/* Clear the ADCx's flag for injected end of conversion */
__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
/* Clear injected group conversion flag to have similar behaviour as */
/* regular group: reading data register also clears end of conversion flag. */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Return the selected ADC converted value */
switch(InjectedRank)
@ -488,35 +606,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Process locked */
__HAL_LOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
if (hadc->Init.DMAContinuousRequests != DISABLE)
{
/* Enable the selected ADC DMA request after last transfer */
ADC->CCR |= ADC_CCR_DDS;
}
else
{
/* Disable the selected ADC EOC rising on each regular channel conversion */
ADC->CCR &= ~ADC_CCR_DDS;
}
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@ -533,16 +622,81 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
}
}
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
if (hadc->Init.DMAContinuousRequests != DISABLE)
{
/* Enable the selected ADC DMA request after last transfer */
ADC->CCR |= ADC_CCR_DDS;
}
else
{
/* Disable the selected ADC EOC rising on each regular channel conversion */
ADC->CCR &= ~ADC_CCR_DDS;
}
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
@ -555,29 +709,42 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the Peripheral */
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* Disable the selected ADC DMA request after last transfer */
ADC->CCR &= ~ADC_CCR_DDS;
/* Disable the ADC DMA Stream */
HAL_DMA_Abort(hadc->DMA_Handle);
/* Change ADC state */
hadc->State = HAL_ADC_STATE_READY;
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable the selected ADC DMA mode for multimode */
ADC->CCR &= ~ADC_CCR_DDS;
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
return tmp_hal_status;
}
/**
@ -601,6 +768,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
*/
@ -616,7 +785,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
{
#ifdef USE_FULL_ASSERT
uint32_t tmp = 0;
#endif /* USE_FULL_ASSERT */
@ -626,7 +795,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
@ -636,6 +804,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}
/* Process locked */
__HAL_LOCK(hadc);
@ -669,13 +842,27 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Set the SQx bits for the selected rank */
hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
}
if (sConfigInjected->AutoInjectedConv != DISABLE)
{
@ -793,21 +980,49 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Check if an injected conversion is ready */
if(hadc->State == HAL_ADC_STATE_EOC_INJ)
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F7, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_REG;
/* Call DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
HAL_ADC_ConvCpltCallback(hadc);
}
/**
@ -832,7 +1047,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hadc->State= HAL_ADC_STATE_ERROR;
hadc->State= HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
HAL_ADC_ErrorCallback(hadc);

107
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
@ -60,33 +60,78 @@
*/
/**
* @brief ADC Configuration injected Channel structure definition
*/
* @brief ADC Configuration injected Channel structure definition
* @note Parameters of this structure are shared within 2 scopes:
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
* - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
*/
typedef struct
{
uint32_t InjectedChannel; /*!< Configure the ADC injected channel.
This parameter can be a value of @ref ADC_channels */
uint32_t InjectedRank; /*!< The rank in the injected group sequencer
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
This parameter can be a value of @ref ADC_sampling_times */
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
injected channel group.
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group
conversion after regular one */
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */
uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */
}ADC_InjectionConfTypeDef;
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_channel_selection
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
This parameter can be a value of @ref ADC_sampling_times
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE.
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
To maintain JAUTO always enabled, DMA must be configured in circular mode.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
If set to external trigger source, triggering is on event rising edge.
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
}ADC_InjectionConfTypeDef;
/**
* @}
*/
/**
* @brief ADC Configuration multi-mode structure definition
* @brief ADC Configuration multi-mode structure definition
*/
typedef struct
{
@ -167,6 +212,7 @@ typedef struct
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1)
/**
* @}
*/
@ -185,7 +231,7 @@ typedef struct
/** @defgroup ADCEx_channels ADC Specific Channels
* @{
*/
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000)
/**
* @}
*/
@ -217,11 +263,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
@ -286,7 +332,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO))
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))

22
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@ -490,6 +490,8 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspInit could be implemented in the user file
*/
@ -503,6 +505,8 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspDeInit could be implemented in the user file
*/
@ -1120,8 +1124,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
/* Set CAN error code to EWG error */
hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
/* Clear Error Warning Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);
}
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
@ -1132,8 +1134,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
/* Set CAN error code to EPV error */
hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
/* Clear Error Passive Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);
}
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
@ -1144,8 +1144,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
/* Set CAN error code to BOF error */
hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
/* Clear Bus-Off Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);
}
tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
@ -1192,6 +1190,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
/* Call the Error call Back in case of Errors */
if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
{
/* Clear ERRI Flag */
hcan->Instance->MSR = CAN_MSR_ERRI;
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
/* Call Error callback function */
@ -1207,6 +1207,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxCpltCallback could be implemented in the user file
*/
@ -1220,6 +1222,8 @@ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxCpltCallback could be implemented in the user file
*/
@ -1233,6 +1237,8 @@ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/

29
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -412,9 +412,12 @@ typedef struct
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
#define CAN_FLAG_INAK ((uint32_t)0x00000100) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI ((uint32_t)0x00000102) /*!< Error flag */
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
@ -559,17 +562,13 @@ typedef struct
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__: CAN Handle
@ -600,7 +599,7 @@ typedef struct
* @retval None
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
@ -609,9 +608,9 @@ typedef struct
* @retval None
*/
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
/**
* @brief Enable or disable the DBG Freeze for CAN.

14
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
@ -246,6 +246,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
*/
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspInit can be implemented in the user file
*/
@ -258,6 +260,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
*/
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspDeInit can be implemented in the user file
*/
@ -877,6 +881,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
*/
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_TxCpltCallback can be implemented in the user file
*/
@ -889,6 +895,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
*/
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_TxCpltCallback can be implemented in the user file
*/
@ -901,6 +909,8 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
*/
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_ErrorCallback can be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
@ -266,29 +266,6 @@ typedef struct
/* Exported Macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/** @brief Configures the SysTick clock source.
* @param __CLKSRC__: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
do { \
if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
{ \
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
} \
else \
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
} while(0)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions

79
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -92,8 +92,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
*/
/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions.
*
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@ -110,8 +110,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
*/
/**
* @brief Initializes the CRC according to the specified
* parameters in the CRC_InitTypeDef and creates the associated handle.
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc: CRC handle
* @retval HAL status
*/
@ -140,7 +140,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
/* initialize IP with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
@ -149,7 +149,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
else
{
/* initialize CRC IP with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -158,7 +158,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
}
/**
* @brief DeInitializes the CRC peripheral.
* @brief DeInitialize the CRC peripheral.
* @param hcrc: CRC handle
* @retval HAL status
*/
@ -229,24 +229,30 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
}
/**
* @brief Initializes the CRC MSP.
* @brief Initialize the CRC MSP.
* @param hcrc: CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitializes the CRC MSP.
* @brief DeInitialize the CRC MSP.
* @param hcrc: CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
@ -257,8 +263,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
*/
/** @defgroup HAL_CRC_Group2 Peripheral Control functions
* @brief Peripheral Control functions
*
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
@ -282,7 +288,13 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length
* @param BufferLength: input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
@ -328,14 +340,19 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
return temp;
}
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length
* @param BufferLength: input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
@ -387,8 +404,6 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
return temp;
}
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
@ -409,20 +424,20 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
}
/* last bytes specific handling */
if ((BufferLength%4) != 0)
if((BufferLength%4) != 0)
{
if (BufferLength%4 == 1)
if(BufferLength%4 == 1)
{
*(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
}
if (BufferLength%4 == 2)
if(BufferLength%4 == 2)
{
*(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
}
if (BufferLength%4 == 3)
if(BufferLength%4 == 3)
{
*(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));
*(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
*(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
}
}
@ -430,8 +445,6 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
return hcrc->Instance->DR;
}
/**
* @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
@ -451,9 +464,9 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
{
hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
}
if ((BufferLength%2) != 0)
if((BufferLength%2) != 0)
{
*(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
*(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
}
/* Return the CRC computed value */
@ -465,8 +478,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
*/
/** @defgroup HAL_CRC_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
* @brief Peripheral State functions.
*
@verbatim
==============================================================================
##### Peripheral State functions #####
@ -480,7 +493,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
*/
/**
* @brief Returns the CRC state.
* @brief Return the CRC state.
* @param hcrc: CRC handle
* @retval HAL state
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention

37
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@ -103,7 +103,7 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#if defined(STM32F756xx)
#if defined (STM32F756xx)
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
@ -691,6 +691,9 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
*/
__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspInit could be implemented in the user file
*/
@ -704,6 +707,9 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
*/
__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspDeInit could be implemented in the user file
*/
@ -2285,13 +2291,13 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
* @param Timeout: Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
{
/* Process Locked */
__HAL_LOCK(hcryp);
@ -2306,7 +2312,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
__HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@ -2365,13 +2371,13 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
* @param Timeout: Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
{
/* Process Locked */
__HAL_LOCK(hcryp);
@ -2386,7 +2392,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
__HAL_CRYP_ENABLE(hcryp);
/* Write Plain Data and Get Cypher Data */
if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@ -3638,6 +3644,9 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_
*/
__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_InCpltCallback could be implemented in the user file
*/
@ -3651,6 +3660,9 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
*/
__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_OutCpltCallback could be implemented in the user file
*/
@ -3664,6 +3676,9 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
*/
__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_ErrorCallback could be implemented in the user file
*/

10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined(STM32F756xx)
#if defined (STM32F756xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@ -388,9 +388,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
*/
/* DES encryption/decryption using polling ***********************************/
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
/* DES encryption/decryption using interrupt *********************************/
HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@ -102,7 +102,7 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#if defined(STM32F756xx)
#if defined (STM32F756xx)
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined(STM32F756xx)
#if defined (STM32F756xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"

22
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@ -302,6 +302,9 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
*/
@ -315,6 +318,9 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
*/
@ -682,6 +688,9 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallback could be implemented in the user file
*/
@ -695,6 +704,9 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
*/
@ -708,6 +720,9 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
@ -721,6 +736,9 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

16
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@ -269,6 +269,9 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file
*/
@ -282,6 +285,9 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
*/
@ -295,6 +301,9 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
*/
@ -308,6 +317,9 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

19
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@ -247,6 +247,9 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
*/
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspInit could be implemented in the user file
*/
@ -260,6 +263,9 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
*/
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspDeInit could be implemented in the user file
*/
@ -539,6 +545,9 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
*/
__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_ErrorCallback could be implemented in the user file
*/
@ -565,6 +574,9 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
*/
__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_VsyncEventCallback could be implemented in the user file
*/
@ -578,6 +590,9 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
*/
__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_FrameEventCallback could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief DCMI Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DCMI extension peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of DCMI Extension HAL module.
******************************************************************************
* @attention

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_def.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@ -103,7 +103,7 @@ typedef enum
#if (USE_RTOS == 1)
/* Reserved for future use */
#error “USE_RTOS should be 0 in the current HAL release”
#error "USE_RTOS should be 0 in the current HAL release"
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \

153
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@ -73,8 +73,6 @@
(+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
(+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
(+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
@ -128,6 +126,13 @@
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register */
__IO uint32_t Reserved0;
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
} DMA_Base_Registers;
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA_Private_Constants
@ -143,6 +148,8 @@
* @{
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
/**
* @brief Sets the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@ -291,6 +298,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
DMA_CalcBaseAndBitshift(hdma);
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -308,6 +319,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
{
@ -341,12 +354,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021;
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3F << hdma->StreamIndex;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -440,20 +452,9 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
/* Enable the Half transfer complete interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
/* Enable the transfer Error interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
/* Enable the FIFO Error interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
/* Enable the direct mode Error interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
/* Enable all interrupts */
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
hdma->Instance->FCR |= DMA_IT_FE;
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
@ -523,26 +524,31 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
uint32_t temp, tmp, tmp1, tmp2;
uint32_t tickstart = 0;
/* calculate DMA base and stream number */
DMA_Base_Registers *regs;
regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Transfer Complete flag */
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
}
else
{
/* Half Transfer Complete flag */
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
}
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
while((regs->ISR & temp) == RESET)
{
tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
{
if(tmp != RESET)
@ -551,7 +557,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
/* Clear the transfer error flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
}
if(tmp1 != RESET)
{
@ -559,7 +565,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
/* Clear the FIFO error flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
}
if(tmp2 != RESET)
{
@ -567,7 +573,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
/* Clear the Direct Mode error flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
}
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_ERROR;
@ -598,14 +604,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Clear the half transfer and transfer complete flags */
regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
@ -621,11 +625,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
}
else
{
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
/* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
are complete) */
hdma->State = HAL_DMA_STATE_READY_MEM0;
@ -634,13 +633,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
__HAL_UNLOCK(hdma);
}
else
{
{
/* Clear the half transfer complete flag */
regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
@ -656,9 +655,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
}
else
{
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
}
@ -674,8 +670,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* calculate DMA base and stream number */
DMA_Base_Registers *regs;
regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
/* Transfer Error Interrupt management ***************************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
{
@ -683,7 +684,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
/* Clear the transfer error flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
@ -702,7 +703,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* FIFO Error Interrupt management ******************************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
{
@ -710,7 +711,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
/* Clear the FIFO error flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
@ -729,7 +730,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Direct Mode Error Interrupt management ***********************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
{
@ -737,7 +738,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
/* Clear the direct mode error flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
@ -756,7 +757,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Half Transfer Complete Interrupt management ******************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
{
@ -764,7 +765,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@ -788,7 +789,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
@ -802,14 +803,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/* Transfer Complete Interrupt management ***********************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
{
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
{
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
/* Current memory buffer used is Memory 1 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
@ -839,7 +840,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
@ -860,6 +861,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
/**
* @}
*/
@ -905,6 +907,33 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
* @}
*/
/**
* @brief Returns the DMA Stream base address depending on stream number
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval Stream base address
*/
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
/* lookup table for necessary bitshift of flags within status registers */
static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
hdma->StreamIndex = flagBitshiftOffset[stream_number];
if (stream_number > 3)
{
/* return pointer to HISR and HIFCR */
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
}
else
{
/* return pointer to LISR and LIFCR */
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
}
return hdma->StreamBaseAddress;
}
/**
* @}
*/

9
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@ -165,6 +165,11 @@ typedef struct __DMA_HandleTypeDef
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
uint32_t StreamIndex; /*!< DMA Stream Index */
}DMA_HandleTypeDef;
/**

10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@ -292,6 +292,9 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
*/
__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DMA2D_MspInit could be implemented in the user file
*/
@ -305,6 +308,9 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
*/
__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DMA2D_MspDeInit could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention

46
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@ -114,8 +114,9 @@
/** @defgroup ETH_Private_Constants ETH Private Constants
* @{
*/
#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
#define ETH_TIMEOUT_SWRESET ((uint32_t)500)
#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000)
#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000)
/**
* @}
@ -208,9 +209,25 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/* After reset all the registers holds their respective reset values */
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for software reset */
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
{
heth->State= HAL_ETH_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
not available, please check your external PHY or the IO configuration */
return HAL_TIMEOUT;
}
}
/*-------------------------------- MAC Initialization ----------------------*/
@ -243,7 +260,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/* CSR Clock Range between 100-150 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
}
else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */
else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
{
/* CSR Clock Range between 150-216 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
@ -283,7 +300,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
{
/* In case of write timeout */
err = ETH_ERROR;
@ -326,7 +343,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
{
/* In case of write timeout */
err = ETH_ERROR;
@ -589,6 +606,9 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
*/
__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_MspInit could be implemented in the user file
*/
@ -602,6 +622,9 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
*/
__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_MspDeInit could be implemented in the user file
*/
@ -981,6 +1004,9 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
@ -994,6 +1020,9 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
*/
__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
@ -1007,6 +1036,9 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@ -66,10 +66,6 @@
((MODE) == ETH_MODE_HALFDUPLEX))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
((MODE) == ETH_RXINTERRUPT_MODE))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
((MODE) == ETH_RXINTERRUPT_MODE))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
((MODE) == ETH_RXINTERRUPT_MODE))
#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \

18
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -415,8 +415,8 @@ void HAL_FLASH_IRQHandler(void)
temp = pFlash.Address;
break;
}
default :
break;
default :
break;
}
/*Save the Error code*/
FLASH_SetErrorCode();
@ -455,9 +455,11 @@ void HAL_FLASH_IRQHandler(void)
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
@ -471,8 +473,10 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}

13
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
@ -80,7 +80,7 @@ typedef struct
__IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */
__IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */
__IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */
__IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */
@ -88,7 +88,7 @@ typedef struct
HAL_LockTypeDef Lock; /* FLASH locking object */
__IO uint32_t ErrorCode; /* FLASH error code */
__IO uint32_t ErrorCode; /* FLASH error code */
}FLASH_ProcessTypeDef;
@ -346,6 +346,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
* @{
*/
/**
* @brief OPTCR register byte 1 (Bits[15:8]) base address
*/
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
/**
* @}
*/

51
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@ -120,7 +120,7 @@ extern FLASH_ProcessTypeDef pFlash;
static void FLASH_MassErase(uint8_t VoltageRange);
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level);
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
@ -281,7 +281,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
}
/**
* @brief Program option bytes
* @brief Program option bytes
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
{
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
/*Get WRP*/
pOBInit->WRPSector = FLASH_OB_GetWRP();
@ -377,10 +377,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
/*Get BOR Level*/
pOBInit->BORLevel = FLASH_OB_GetBOR();
/*Get Boot Address when Boot pin = 0 */
/*Get Boot Address when Boot pin = 0 */
pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
/*Get Boot Address when Boot pin = 1 */
pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
}
@ -406,16 +406,13 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
*/
static void FLASH_MassErase(uint8_t VoltageRange)
{
uint32_t tmp_psize = 0;
/* Check the parameters */
assert_param(IS_VOLTAGERANGE(VoltageRange));
/* if the previous operation is completed, proceed to erase all sectors */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= FLASH_CR_MER;
FLASH->CR |= FLASH_CR_STRT;
FLASH->CR |= FLASH_CR_STRT | (VoltageRange <<8);
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
@ -479,9 +476,8 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
* @brief Enable the write protection of the desired bank1 or bank 2 sectors
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM4
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
* it is not possible to program or erase the flash sector i if CortexM7
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WRPSector: specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
@ -543,9 +539,6 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
return status;
}
/**
* @brief Set the read protection level.
* @param Level: specifies the read protection level.
@ -558,7 +551,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
*
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
{
HAL_StatusTypeDef status = HAL_OK;
@ -570,7 +563,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
if(status == HAL_OK)
{
MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_RDP, Level);
*(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
}
return status;
@ -604,7 +597,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
* @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby )
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
{
uint32_t useroptionmask = 0x00;
uint32_t useroptionvalue = 0x00;
@ -687,17 +680,17 @@ static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
if(BootOption == OPTIONBYTE_BOOTADDR_0)
{
MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
}
else
{
MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
}
}
else
{
MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
}
}
return status;
@ -736,11 +729,11 @@ static uint8_t FLASH_OB_GetRDP(void)
{
uint8_t readstatus = OB_RDP_LEVEL_0;
if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_0)
if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
{
readstatus = OB_RDP_LEVEL_0;
}
else if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_2)
else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
{
readstatus = OB_RDP_LEVEL_2;
}

21
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
@ -89,7 +89,7 @@ typedef struct
uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
uint32_t RDPLevel; /*!< Set the read protection level.
@ -212,7 +212,7 @@ typedef struct
* @{
*/
#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STOP mode */
#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000) /*!< IWDG counter active in STOP mode */
/**
* @}
*/
@ -248,7 +248,6 @@ typedef struct
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000) /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004) /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013) /*!< Boot from SRAM2 (0x2004C000) */
/**
* @}
*/
@ -313,8 +312,6 @@ typedef struct
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000) /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */
/**
* @}
*/
@ -423,17 +420,17 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))
/**
* @}
*/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -514,6 +514,9 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@ -157,10 +157,10 @@ typedef enum
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */
#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< Fast speed */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< High speed */
/**
* @}
*/

14
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
@ -96,7 +96,6 @@
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
/**
* @brief AF 4 selection
*/
@ -132,7 +131,6 @@
#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
@ -154,9 +152,9 @@
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#if defined(STM32F756xx) || defined(STM32F746xx)
#if defined(STM32F746xx) || defined(STM32F756xx)
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F756xx || STM32F746xx */
#endif /* STM32F746xx || STM32F756xx */
/**
* @brief AF 10 selection
*/
@ -182,12 +180,12 @@
*/
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#if defined(STM32F756xx) || defined(STM32F746xx)
#if defined(STM32F746xx) || defined(STM32F756xx)
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F756xx || STM32F746xx */
#endif /* STM32F746xx || STM32F756xx */
/**
* @brief AF 15 selection
*/

21
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@ -428,6 +428,9 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_HASH_MspInit could be implemented in the user file
*/
@ -441,6 +444,9 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_HASH_MspDeInit could be implemented in the user file
*/
@ -454,6 +460,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
*/
__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_HASH_InCpltCallback could be implemented in the user file
*/
@ -467,6 +476,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
*/
__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_HASH_ErrorCallback could be implemented in the user file
*/
@ -481,6 +493,9 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
*/
__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_HASH_DgstCpltCallback could be implemented in the user file
*/
@ -1836,7 +1851,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
* the configuration information for HASH module
* @retval HAL state
*/
HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
{
return hhash->State;
}

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
@ -90,7 +90,7 @@ typedef enum
HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */
HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */
}HAL_HASH_STATETypeDef;
}HAL_HASH_StateTypeDef;
/**
* @}
@ -130,13 +130,13 @@ typedef struct
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
HAL_LockTypeDef Lock; /*!< HASH locking object */
__IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
} HASH_HandleTypeDef;
/**
@ -352,7 +352,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/** @addtogroup HASH_Exported_Functions_Group8
* @{
*/
HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention

142
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -26,8 +26,9 @@
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
(##) Enable the HCD/USB Low Level interface clock using the following macros
(+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
(+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
@ -77,7 +78,8 @@
* @{
*/
/** @addtogroup HCD
/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
@ -88,7 +90,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup HCD_Private_Functions
/** @defgroup HCD_Private_Functions HCD Private Functions
* @{
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
@ -100,12 +102,12 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HCD_Exported_Functions
/** @defgroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
/** @addtogroup HCD_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@ -118,7 +120,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
/**
* @brief Initialize the host driver
* @brief Initialize the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@ -156,7 +158,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
}
/**
* @brief Initialize a host channel
* @brief Initialize a host channel.
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
@ -212,7 +214,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
}
/**
* @brief Halt a host channel
* @brief Halt a host channel.
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
@ -230,7 +232,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
}
/**
* @brief DeInitialize the host driver
* @brief DeInitialize the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@ -255,24 +257,30 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
}
/**
* @brief Initializes the HCD MSP.
* @brief Initialize the HCD MSP.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes HCD MSP.
* @brief DeInitialize the HCD MSP.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_MspDeInit could be implemented in the user file
*/
@ -282,14 +290,14 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
* @}
*/
/** @addtogroup HCD_Exported_Functions_Group2
/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @brief HCD IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the USB Host Data
[..] This subsection provides a set of functions allowing to manage the USB Host Data
Transfer
@endverbatim
@ -297,7 +305,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
*/
/**
* @brief Submit a new URB for processing
* @brief Submit a new URB for processing.
* @param hhcd: HCD handle
* @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
@ -440,7 +448,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
/**
* @brief This function handles HCD interrupt request.
* @brief Handle HCD interrupt request.
* @param hhcd: HCD handle
* @retval None
*/
@ -549,30 +557,39 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
*/
__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_SOF_Callback could be implemented in the user file
*/
}
/**
* @brief Connexion Event callback.
* @brief Connection Event callback.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_Connect_Callback could be implemented in the user file
*/
}
/**
* @brief Disconnexion Event callback.
* @brief Disconnection Event callback.
* @param hhcd: HCD handle
* @retval None
*/
__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
@ -595,6 +612,9 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/
@ -604,8 +624,8 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
* @}
*/
/** @addtogroup HCD_Exported_Functions_Group3
* @brief Peripheral management functions
/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
@ -620,7 +640,7 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
*/
/**
* @brief Start the host driver
* @brief Start the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@ -634,7 +654,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
}
/**
* @brief Stop the host driver
* @brief Stop the host driver.
* @param hhcd: HCD handle
* @retval HAL status
*/
@ -648,7 +668,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
}
/**
* @brief Reset the host port
* @brief Reset the host port.
* @param hhcd: HCD handle
* @retval HAL status
*/
@ -661,7 +681,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
* @}
*/
/** @addtogroup HCD_Exported_Functions_Group4
/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@ -677,7 +697,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
*/
/**
* @brief Return the HCD state
* @brief Return the HCD handle state.
* @param hhcd: HCD handle
* @retval HAL state
*/
@ -687,7 +707,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
}
/**
* @brief Return URB state for a channel
* @brief Return URB state for a channel.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@ -698,7 +718,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL/
* URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@ -707,7 +727,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
/**
* @brief Return the last host transfer size
* @brief Return the last host transfer size.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@ -719,12 +739,12 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
* @brief Return the Host Channel state
* @brief Return the Host Channel state.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
* This parameter can be one of the these values:
* This parameter can be one of these values:
* HC_IDLE/
* HC_XFRC/
* HC_HALTED/
@ -733,7 +753,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
* HC_STALL/
* HC_XACTERR/
* HC_BBLERR/
* HC_DATATGLERR/
* HC_DATATGLERR
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@ -741,7 +761,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
* @brief Return the current Host frame number
* @brief Return the current Host frame number.
* @param hhcd: HCD handle
* @retval Current Host frame number
*/
@ -751,7 +771,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
}
/**
* @brief Return the Host enumeration speed
* @brief Return the Host enumeration speed.
* @param hhcd: HCD handle
* @retval Enumeration speed
*/
@ -759,6 +779,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
{
return (USB_GetHostSpeed(hhcd->Instance));
}
/**
* @}
*/
@ -771,7 +792,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
* @{
*/
/**
* @brief This function handles Host Channel IN interrupt requests.
* @brief Handle Host Channel IN interrupt requests.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@ -780,7 +801,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t tmpreg = 0;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
@ -874,8 +896,10 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/* re-activate the channel */
USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
@ -896,22 +920,22 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
}
hhcd->hc[chnum].state = HC_NAK;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
hhcd->hc[chnum].state = HC_NAK;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
}
/**
* @brief This function handles Host Channel OUT interrupt requests.
* @brief Handle Host Channel OUT interrupt requests.
* @param hhcd: HCD handle
* @param chnum: Channel number.
* This parameter can be a value from 1 to 15
@ -920,6 +944,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t tmpreg = 0;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
@ -1043,8 +1068,10 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/* re-activate the channel */
USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
@ -1053,7 +1080,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
/**
* @brief This function handles Rx Queue Level interrupt requests.
* @brief Handle Rx Queue Level interrupt requests.
* @param hhcd: HCD handle
* @retval none
*/
@ -1064,6 +1091,7 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
uint32_t pktsts;
uint32_t pktcnt;
uint32_t temp = 0;
uint32_t tmpreg = 0;
temp = hhcd->Instance->GRXSTSP ;
channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
@ -1086,8 +1114,10 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
{
/* re-activate the channel when more packets are expected */
USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
tmpreg = USBx_HC(channelnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(channelnum)->HCCHAR = tmpreg;
hhcd->hc[channelnum].toggle_in ^= 1;
}
}
@ -1103,7 +1133,7 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
}
/**
* @brief This function handles Host Port interrupt requests.
* @brief Handle Host Port interrupt requests.
* @param hhcd: HCD handle
* @retval None
*/
@ -1187,6 +1217,10 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
* @}
*/
/**
* @}
*/
#endif /* HAL_HCD_MODULE_ENABLED */
/**
* @}

16
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
@ -105,6 +105,7 @@ typedef struct
/** @defgroup HCD_Exported_Constants HCD Exported Constants
* @{
*/
/** @defgroup HCD_Speed HCD Speed
* @{
*/
@ -150,7 +151,7 @@ typedef struct
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HCD_Exported_Functions HCD Exported Functions
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
@ -174,7 +175,8 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
* @}
*/
/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
/* I/O operation functions ***************************************************/
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
@ -198,7 +200,8 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
* @}
*/
/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
/* Peripheral Control functions **********************************************/
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
@ -208,7 +211,8 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
* @}
*/
/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
/* Peripheral State functions ************************************************/
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);

718
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
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File diff suppressed because it is too large Load Diff

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention

10
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
@ -90,7 +90,7 @@
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Noise Filters
@endverbatim
* @{
@ -172,7 +172,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DFN);
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8;
@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
}
/**
* @}

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
@ -70,6 +70,7 @@
* @}
*/
/**
* @}
*/
@ -80,7 +81,6 @@
/* Peripheral Control methods ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@ -379,6 +379,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implemented in the user file
*/
@ -392,6 +395,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implemented in the user file
*/
@ -526,7 +532,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
/* Wait until Busy flag is reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
{
/* Set the error code and execute error callback*/
hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
@ -1202,6 +1208,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
*/
@ -1215,6 +1224,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
@ -1228,6 +1240,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
@ -1241,6 +1256,9 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
@ -1254,6 +1272,9 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
*/

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@ -334,7 +334,7 @@ typedef struct
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
__IO uint32_t tmpreg = 0x00; \
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
@ -346,7 +346,7 @@ typedef struct
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
__IO uint32_t tmpreg = 0x00; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
} while(0)

25
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
@ -297,6 +297,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_IRDA_MspInit could be implemented in the user file
*/
@ -310,6 +313,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_IRDA_MspDeInit could be implemented in the user file
*/
@ -967,6 +973,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
*/
__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
*/
@ -980,6 +989,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
*/
__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxCpltCallback can be implemented in the user file
*/
@ -993,6 +1005,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
*/
__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
*/
@ -1006,6 +1021,9 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxCpltCallback can be implemented in the user file
*/
@ -1019,6 +1037,9 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_ErrorCallback can be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention

9
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief IWDG HAL module driver.
*
* This file provides firmware functions to manage the following
@ -207,7 +207,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
/* by writing 0x5555 in KR */
/* by writing 0x00005555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
@ -249,6 +249,9 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hiwdg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IWDG_MspInit could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention

31
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
@ -352,6 +352,9 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_MspInit could be implemented in the user file
*/
@ -364,6 +367,9 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_MspDeInit could be implemented in the user file
*/
@ -1526,6 +1532,9 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
*/
@ -1538,6 +1547,9 @@ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
*/
@ -1550,6 +1562,9 @@ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_TriggerCallback could be implemented in the user file
*/
@ -1562,6 +1577,9 @@ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
*/
@ -1574,6 +1592,9 @@ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
*/
@ -1586,6 +1607,9 @@ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
*/
@ -1598,6 +1622,9 @@ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
*/
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention

20
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
@ -102,7 +102,7 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#if defined(STM32F756xx) || defined(STM32F746xx)
#if defined (STM32F746xx) || defined (STM32F756xx)
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
@ -263,6 +263,9 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
*/
__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LTDC_MspInit could be implemented in the user file
*/
@ -276,6 +279,9 @@ __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
*/
__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LTDC_MspDeInit could be implemented in the user file
*/
@ -385,6 +391,9 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
@ -398,6 +407,9 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
*/
__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LTDC_LineEvenCallback could be implemented in the user file
*/
@ -1184,7 +1196,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/**
* @}
*/
#endif /* STM32F756xx || STM32F746xx */
#endif /* STM32F746xx || STM32F756xx */
/**
* @}

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
@ -467,7 +467,6 @@ typedef struct
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
* @{
@ -616,7 +615,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
#endif /* STM32F756xx || STM32F746xx */
#endif /* STM32F746xx || STM32F756xx */
/**
* @}
*/

13
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nand.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@ -196,6 +196,9 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
*/
__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspInit could be implemented in the user file
*/
@ -209,6 +212,9 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
*/
__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspDeInit could be implemented in the user file
*/
@ -273,6 +279,9 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
*/
__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_ITCallback could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nand.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention

14
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nor.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@ -231,6 +231,9 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
*/
__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspInit could be implemented in the user file
*/
@ -244,6 +247,9 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
*/
__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspDeInit could be implemented in the user file
*/
@ -258,6 +264,10 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
*/
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
UNUSED(Timeout);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspWait could be implemented in the user file
*/

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nor.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention

123
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -24,12 +24,12 @@
(#) Fill parameters of Init structure in HCD handle
(#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
(#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
(+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
(+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@ -38,7 +38,7 @@
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
(#)Enable HCD transmission and reception:
(#)Enable PCD transmission and reception:
(##) HAL_PCD_Start();
@endverbatim
@ -203,7 +203,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
}
/**
* @brief DeInitializes the PCD peripheral
* @brief DeInitializes the PCD peripheral.
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -235,6 +235,9 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implemented in the user file
*/
@ -247,6 +250,9 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspDeInit could be implemented in the user file
*/
@ -256,7 +262,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
* @}
*/
/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
@ -301,7 +307,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
}
/**
* @brief This function handles PCD interrupt request.
* @brief Handle PCD interrupt request.
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -372,6 +378,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
/* Clear Status Phase Received interrupt */
if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
}
epnum++;
ep_intr >>= 1;
@ -462,7 +473,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Suspend Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
@ -508,7 +518,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
else
{
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
}
@ -612,136 +622,168 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/**
* @brief Data out stage callbacks
* @brief Data OUT stage callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Data IN stage callbacks
* @brief Data IN stage callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
* @brief Setup stage callback
* @brief Setup stage callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
/**
* @brief USB Start Of Frame callbacks
* @brief USB Start Of Frame callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
/**
* @brief USB Reset callbacks
* @brief USB Reset callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
/**
* @brief Suspend event callbacks
* @brief Suspend event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
/**
* @brief Resume event callbacks
* @brief Resume event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO OUT callbacks
* @brief Incomplete ISO OUT callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO IN callbacks
* @brief Incomplete ISO IN callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
/**
* @brief Connection event callbacks
* @brief Connection event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
/**
* @brief Disconnection event callbacks
* @brief Disconnection event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
@ -767,7 +809,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
/**
* @brief Connect the USB device
* @brief Connect the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -780,7 +822,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
}
/**
* @brief Disconnect the USB device
* @brief Disconnect the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -793,7 +835,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
}
/**
* @brief Set the USB Device address
* @brief Set the USB Device address.
* @param hpcd: PCD handle
* @param address: new device address
* @retval HAL status
@ -806,7 +848,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
return HAL_OK;
}
/**
* @brief Open and configure an endpoint
* @brief Open and configure an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param ep_mps: endpoint max packet size
@ -850,7 +892,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/**
* @brief Deactivate an endpoint
* @brief Deactivate an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@ -879,7 +921,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
* @brief Receive an amount of data
* @brief Receive an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the reception buffer
@ -920,7 +962,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
}
/**
* @brief Get Received Data Size
* @brief Get Received Data Size.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval Data Size
@ -930,7 +972,7 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
}
/**
* @brief Send an amount of data
* @brief Send an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the transmission buffer
@ -972,7 +1014,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
/**
* @brief Set a STALL condition over an endpoint
* @brief Set a STALL condition over an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@ -1007,7 +1049,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
* @brief Clear a STALL condition over in an endpoint
* @brief Clear a STALL condition over in an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@ -1037,7 +1079,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
* @brief Flush an endpoint
* @brief Flush an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@ -1061,7 +1103,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
* @brief HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling
* @brief Activate remote wakeup signalling.
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -1071,14 +1113,14 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
/* Activate Remote wake-up signaling */
/* Activate Remote wakeup signaling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
}
return HAL_OK;
}
/**
* @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling
* @brief De-activate remote wakeup signalling.
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -1086,7 +1128,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
/* De-activate Remote wake-up signaling */
/* De-activate Remote wakeup signaling */
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
}
@ -1110,7 +1152,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
/**
* @brief Return the PCD state
* @brief Return the PCD handle state.
* @param hpcd: PCD handle
* @retval HAL state
*/
@ -1132,8 +1174,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
*/
/**
* @brief DCD_WriteEmptyTxFifo
* check FIFO for the next packet to be loaded
* @brief Check FIFO for the next packet to be loaded.
* @param hpcd: PCD handle
* @param epnum : endpoint number
* @retval HAL status

13
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@ -219,6 +219,9 @@ typedef struct
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
@ -239,7 +242,7 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
@ -295,6 +298,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
/** @defgroup PCD_Instance_definition PCD Instance definition
* @{
*/

24
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -59,7 +59,7 @@
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
* @{
*/
@ -103,7 +103,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
if(fifo == 0)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
else
{
@ -114,8 +114,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
return HAL_OK;
@ -135,7 +134,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
}
/**
* @brief HAL_PCDEx_ActivateLPM : active LPM Feature
* @brief Activate LPM Feature
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -152,7 +151,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
}
/**
* @brief HAL_PCDEx_DeActivateLPM : de-active LPM feature
* @brief DeActivate LPM feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
@ -168,13 +167,20 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
}
/**
* @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer
* @brief Send LPM message to user layer callback.
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.0.1
* @date 25-June-2015
* @version V1.0.4
* @date 09-December-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@ -63,7 +63,7 @@ typedef enum
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions

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