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3503 Commits (03fa626edab0ce835416a076ee67b202a298f7b6)

Author SHA1 Message Date
Cruz Monrreal 21dbbc5e8b
Merge pull request #7510 from mattbrown015/fix_stm32_gpio_irq_deepsleep 
STM32: Improve GPIO IRQ edge detection when waking from deepsleep
 2018-07-23 10:12:49 -05:00
Cruz Monrreal 057138c2a0
Merge pull request #7536 from ganesh-ramachandran/master 
Add Support for Toshiba TMPM3H6
 2018-07-20 12:38:25 -05:00
Cruz Monrreal bb7b97cadc
Merge pull request #7491 from evva-sfw/feature/EFM32_make_PeripheralPins_overridable 
EFM32: fix weak PeripheralPins configuration
 2018-07-20 08:01:39 -05:00
cyliangtw 240619745d Fixed NUC472 SD & EMAC IP reset define 2018-07-20 18:23:41 +08:00
Cruz Monrreal 541fc1f28b
Merge pull request #7539 from jeromecoutant/PR_LL_API 
STM32F2/F4/F7 : LL API is now available for IRQ
 2018-07-19 20:43:28 -05:00
Cruz Monrreal 218811024f
Merge pull request #7479 from SiliconLabs/feature/crc 
Silicon Labs: Add support for hardware CRC
 2018-07-19 13:06:42 -05:00
Qinghao Shi f207944341 enable HAL FLASH API on Fast Models MPS2 targets 2018-07-19 14:41:21 +01:00
bcostm bf8587ed50 STM32L496: fix RAM size in ARM scatter file 2018-07-19 14:02:05 +02:00
Ganesh Ramachandran 8673286100 Resolved conflict in targets/targets.json 2018-07-19 16:32:51 +05:30
Ganesh Ramachandran bfcfe9cc4b Added Support for Toshiba TMPM3H6 2018-07-19 16:31:11 +05:30
zzw b6a67c103b realtek rtl8195am remove DEVICE_EMAC 
1, remove DEVICE_EMAC for wifi feature
 2018-07-19 18:07:18 +08:00
Cruz Monrreal dd6482b955
Merge pull request #7504 from TacoGrandeTX/feature_itm_fix 
Feature itm fix
 2018-07-18 09:01:13 -05:00
Cruz Monrreal db9a0e8b72
Merge pull request #7533 from marcuschangarm/fix-nrf52832-iar 
Fix linker script for NRF52832/IAR
 2018-07-18 08:56:44 -05:00
Cruz Monrreal e9e1ff997d
Merge pull request #7302 from OpenNuvoton/nuvoton_m2351_v1.1 
Support Nuvoton's NUMAKER_PFM_M2351 target
 2018-07-18 08:49:55 -05:00
jeromecoutant 59fd0c0cce STM32F2/F4/F7 : LL API is now available 2018-07-18 15:17:46 +02:00
Marcus Chang 9a073c0ae4 Fix linker script for NRF52832/IAR 
IAR linker script was using memory settings from the NRF52840 and
not the NRF52832.
 2018-07-17 12:43:23 -07:00
PHST 804edd578e Place "MBED_WEAK" for IAR-Toolchain before the type. 2018-07-17 08:12:41 +02:00
Keyur Hariya ed94e6aa35 Add bootloader configuration parameters for MAX32625PICO and rework targets.json 2018-07-16 18:26:51 -05:00
PHST de266d827e Added missing include. 2018-07-16 19:28:54 +02:00
PHST 1658349965 Replace __attribute__((weak)) with MBED_WEAK 2018-07-16 15:38:25 +02:00
PHST a8dcf52971 Make PeripheralPins.c configuration tables weakly defined to be overridable for target EFM32GG11. 2018-07-16 12:35:44 +02:00
PHST 95d78df962 EFM32 Make PeripheralPins.c configuration tables weakly defined to be overridable. 
See issue "https://github.com/ARMmbed/mbed-os/issues/7424#issuecomment-404233377"
 2018-07-16 11:48:53 +02:00
Steven Cooreman 86491627bf Add implementation for CRC API 2018-07-16 11:08:45 +02:00
justinkim 8b5485664d fix timer Interrupt callback function bug 2018-07-16 14:44:15 +09:00
justinkim 65601525d6 add Systick configuration function in Init function 2018-07-16 14:43:45 +09:00
justinkim 3b412128af fix GPIO bug & typo 
initialization bug
 2018-07-16 14:42:48 +09:00
justinkim 6e86402d8a add GPIO Pad Type Define & fix typo 2018-07-16 14:41:19 +09:00
Deepika 455f1fd440 [M2351] Support only ARMC6 toolchain 
Support for GCC_ARM/IAR toolchains are TODO.
 2018-07-16 10:15:36 +08:00
Cruz Monrreal 38744b9e68
Merge pull request #7498 from bcostm/fix_hsi_lse_lpuart 
STM32: enable HSI/LSE clocks for LPUART
 2018-07-14 13:33:35 -05:00
Cruz Monrreal 671b3c875e
Merge pull request #7507 from jeromecoutant/PR_LPTIM 
STM32 LPTICKER with LPTIM minor update
 2018-07-14 06:29:36 -05:00
Cruz Monrreal 602b0cea09
Merge pull request #7079 from SiliconLabs/feature/EFM32GG11-OS5.9 
Add support for EFM32GG11
 2018-07-13 17:33:34 -05:00
Cruz Monrreal cc8651e45c
Merge pull request #7505 from naveenkaje/pushbranch 
Fix linker script for NRF52840/ARM
 2018-07-13 13:30:25 -05:00
Cruz Monrreal 531ee3c5d4
Merge pull request #7461 from 0xc0170/fix_raytac_removal 
Raytac: target removal
 2018-07-13 11:46:58 -05:00
Deepika 2bbe043793 [M2351] Adding missing ENDP for ARM 2018-07-13 10:56:45 -05:00
mattbrown015 7ef70223fb Improve GPIO IRQ edge detection when waking from deepsleep 2018-07-13 16:02:31 +01:00
Cruz Monrreal 1145d6bb3c
Merge pull request #7489 from mirelachirica/wise_1570_hsi_source_clock 
Cellular: HSI set to be source clock for WISE_1570
 2018-07-13 09:12:22 -05:00
jeromecoutant 8a0b83233a STM32 LPTICKER with LPTIM minor update 
Code cleaning (L0 Cube update, comment precision)
 2018-07-13 10:03:31 +02:00
Naveen Kaje ed251020b6 NRF52832 linker script: formatting fix 2018-07-12 15:19:13 -05:00
Naveen Kaje 192eb28814 Fix linker script for NRF52840/ARM 2018-07-12 15:19:13 -05:00
RFulchiero 0198481f8f Improved formatting for preprocessor conditionals. 2018-07-12 13:30:36 -05:00
Marcus Chang 10b90edea3 Fix ITM on NRF52 series 
The ITM must be initialized before the SoftDevice, but due to the
lazy initialization in C++ on (at least) GCC the ITM init call
might happen too late.

This commit moves the initialization code into the NRF52 system
startup file.
 2018-07-12 13:29:24 -05:00
Cruz Monrreal f4c936f455
Merge pull request #7486 from marcuschangarm/fix-nrf52-iar 
Fix linker script for NRF52840/IAR
 2018-07-12 10:09:12 -05:00
Cruz Monrreal 6300d8b5e4
Merge pull request #7487 from marcuschangarm/fix-nrf52-serial 
Allow STDIO pins to be NC in NRF52 series
 2018-07-12 10:05:08 -05:00
bcostm 665de33cc6 stm32 lpuart: enable lse and hsi if not done 2018-07-12 15:58:02 +02:00
ccli8 e61c5146c6 [M2351] Fix binary-compatible across compilers in secure functions 
1. Rename m2351_stddriver_sup.h/c to stddriver_secure.h/.c for naming consistency
2. Add hal_secure.h to include hal-exported secure functions
3. Change return/argument type in secure functions:
   (1) Change int to int32_t
   (2) Change PinName to int32_t
   (3) Change time_t to int64_t
4. Update secure lib/bin accordingly
 2018-07-12 18:01:41 +08:00
ccli8 6bf8e191af [M2351] Support configurable for partitioning flash/SRAM 2018-07-12 18:01:39 +08:00
ccli8 778aa1e766 [M2351] Place default secure binary/library 2018-07-12 18:01:38 +08:00
ccli8 31bf7bf342 [M2351] Fix include file name error on case-sensitive system 2018-07-12 18:01:36 +08:00
ccli8 d350f45b4b [M2351] Synchronize lp_ticker code to us_ticker 
This is to make us_ticker/lp_ticker code consistent.
 2018-07-12 18:01:35 +08:00
ccli8 688029a511 [M2351] Remove special handling for dummy interrupt in lp_ticker 
It is because dummy interrupt is very rare or pending time caused by it
is very short.
 2018-07-12 18:01:34 +08:00
ccli8 124b4ad557 [M2351] Remove NUMAKER_PFM_M2351_S/_NS targets 2018-07-12 18:01:33 +08:00
ccli8 c382e9642e [M2351] Upgrade chip version to B from A 
There is a reset halt issue with PLL in A version.
To switch back to A version for some reason, define NU_CHIP_MAJOR to 1.
 2018-07-12 17:52:10 +08:00
ccli8 c725f188ec [M2351] Change pinout to meet NuMaker-PFM-M2351 V1.1 2018-07-12 17:52:09 +08:00
ccli8 93ee13adbe [M2351] Change secure flash/SRAM to 256KB/32KB as default 
This is to compilant with CMSIS pack.
 2018-07-12 17:52:08 +08:00
ccli8 c3c661da8d [M2351] Change secure/non-secure stack/heap size 
1. Change RTOS-less main stack/RTOS ISR stack size to 2KiB
2. Change secure/non-secure heap size to 16KiB/32KiB for IAR
 2018-07-12 17:52:07 +08:00
ccli8 04f723755b [M2351] Meet new RTC HAL spec (Mbed OS 5.9) 
1. Power down RTC access from CPU domain in rtc_free. After rtc_free, RTC gets
   inaccessible from CPU domain but keeps counting.
2. Fix RTC cannot cross reset cycle.
 2018-07-12 17:52:06 +08:00
ccli8 6729b65236 [M2351] Meet new lp_ticker HAL spec (Mbed OS 5.9) 
1. Add LPTICKER in device_has option of targets.json file.
2. Disable interrupt in lp_ticker_init
3. Add lp_ticker_free
4. Enable interrupt in lp_ticker_set_interrupt/lp_ticker_fire_interrupt
5. Disable interupt in ISR
 2018-07-12 17:52:05 +08:00
ccli8 9cbc8b21ee [M2351] Meet new us_ticker HAL spec (Mbed OS 5.9) 
1. Add USTICKER in device_has option of targets.json file.
2. Disable interrupt in us_ticker_init
3. Add us_ticker_free
4. Enable interrupt in us_ticker_set_interrupt/us_ticker_fire_interrupt
5. Disable interrupt in ISR
 2018-07-12 17:52:03 +08:00
ccli8 de83cb2892 [M2351] Add secure gateway functions SYS_LockReg_S/SYS_UnlockReg_S 2018-07-12 17:52:02 +08:00
ccli8 990665512d [M2351] Add SD pinmap 2018-07-12 17:52:01 +08:00
ccli8 1b9fa07b6f [M2351] Default MBED_TZ_DEFAULT_ACCESS to 1 to control secure SYS/CLK regions from non-secure threads 
To initialize/uninitialize H/W module, we need to control secure SYS/CLK regions through secure functions.
For a new thread to call these secure functions, we need to allocate secure context for it.
 2018-07-12 17:52:00 +08:00
ccli8 89d32227a0 [M2351] Replace __attribute__((cmse_nonsecure_entry)) with compiler agnostic __NONSECURE_ENTRY 2018-07-12 17:51:59 +08:00
ccli8 767e74b1db [M2351] Support TrustZone and bootloader for IAR 2018-07-12 17:51:58 +08:00
ccli8 8f1623f717 [M2351] Add consistency check for CRYPTO/CRPT's secure attribute and TRNG/Mbed TLS H/W 2018-07-12 17:51:55 +08:00
ccli8 2854b57091 [M2351] Remove dead code with '#if 0' in SPI 2018-07-12 17:51:54 +08:00
ccli8 d3c64785c7 [M2351] Add GPIO debounce configuration in targets.json 2018-07-12 17:51:53 +08:00
ccli8 13e1209c83 [M2351] Support PWM out 2018-07-12 17:51:52 +08:00
ccli8 d05ef693ac [M2351] Support analog-in 2018-07-12 17:51:51 +08:00
ccli8 1da430f1e9 [M2351] Support TRNG 
To change TRNG security state, we need to:
1. Change CRPT/CRYPTO bit in NVIC/SCU in partition_M2351.h
2. Add/remove TRNG in device_has list in targets.json to match partition_M2351.h
 2018-07-12 17:51:50 +08:00
ccli8 dd7fd76758 [M2351] Centralize size configuration for secure flash, secure SRAM, NSC, and bootloader 2018-07-12 17:51:48 +08:00
ccli8 ca63abae73 [M2351] Change NSC location 
NSC location has the following requirements:
1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range.
 2018-07-12 17:51:48 +08:00
ccli8 42aa7fe0c5 [M2351] Upgrade partition format 
Following BSP, this upgrade makes partitioning flash/SRAM clear.
flash_api.c relies on flash partition, so it is updated accordingly.
 2018-07-12 17:51:47 +08:00
ccli8 805049d80f [M2351] Fix page size in flash IAP 
In Mbed OS, page size is program unit, which is different than FMC definition.
After fixing page size, we can pass NVSTORE test (mbed-os-features-nvstore-tests-nvstore-functionality).
 2018-07-12 17:51:45 +08:00
ccli8 711cb64e95 [M2351] Support flash IAP 2018-07-12 17:51:44 +08:00
ccli8 fa0124ed8d [M2351] Add missing delay in lp_ticker 2018-07-12 17:51:43 +08:00
ccli8 06cb070442 [M2351] Trim HIRC48 to 48M against LXT 2018-07-12 17:51:42 +08:00
ccli8 649389a962 [M2351] Support I2C 2018-07-12 17:51:41 +08:00
ccli8 3ca24b62ff [M2351] Support SPI 2018-07-12 17:51:40 +08:00
ccli8 dcfe1d4283 [M2351] Refine UART code 
1. Replace SYS_ResetModule/CLK_SetModuleClock/CLK_EnableModuleClock/CLK_DisableModuleClock with TrustZone-aware versions.
2. Configure all UART to secure
3. Support asynchronous transfer
4. Remove sleep management code, which has been replaced with Sleep Manager.
 2018-07-12 17:51:38 +08:00
ccli8 ebf53b9f64 [M2351] Support PDMA 2018-07-12 17:51:38 +08:00
cyliangtw 999dd332e6 [M2351] Rework us_ticker and lp_ticker 
The rework includes the following:
1. Remove ticker overflow handling because upper layer (mbed_ticker_api.c) has done with it.
   This makes us_ticker/lp_ticker implementation more succinct and avoids potential error.
2. Refine timer register access with low-power clock source
 2018-07-12 17:51:37 +08:00
ccli8 236bf657b6 [M2351] Remove peripheral sleep management from hal_sleep/hal_deepsleep 
The upper layer has introduced Sleep Manager to handle the task.
 2018-07-12 17:51:36 +08:00
ccli8 6bfc90dc73 [M2351] Rework RTC 
The rework includes the following:
1. Support year range beyond H/W RTC 2000~2099.
2. Refine RTC register access with low-power clock source
 2018-07-12 17:51:34 +08:00
ccli8 f16b971482 [M2351] Fix GPIO to be TrustZone-aware 
1. Revise NU_PORT_BASE to be TrustZone-aware
2. Add TrustZone-aware NU_GET_GPIO_PIN_DATA/NU_SET_GPIO_PIN_DATA to replace GPIO_PIN_DATA
3. Revise pin_function to be TrustZone-aware
 2018-07-12 17:51:33 +08:00
ccli8 2aa2b7eb00 [M2351] Fix SystemCoreClockUpdate isn't called in non-secure domain 2018-07-12 17:51:32 +08:00
ccli8 0cb7633356 [M2351] Fix HCLK clock source 
There is a reset halt issue with PLL in A version.
Work around it by using HIRC48 instead of PLL as HCLK clock source.
 2018-07-12 17:51:31 +08:00
ccli8 135f1279ca [M2351] Add secure BSP driver function 
SYS_ResetModule_S
CLK_SetModuleClock_S
CLK_EnableModuleClock_S
CLK_DisableModuleClock_S
 2018-07-12 17:51:30 +08:00
ccli8 d84a90e29d [M2351] Unify secure/non-secure peripheral base based on partition file 2018-07-12 17:51:29 +08:00
ccli8 77e45d414b [M2351] Configure most modules to non-secure 
All modules are configured to non-secure except:
1. TIMER0/1 hard-wired to secure and TIMER2/3 reserved for non-secure.
2. PDMA0 hard-wired to secure and PDMA1 reserved for non-secure.
3. RTC configured to secure and shared to non-secure through NSC.
4. CRYPTO configured to secure and shared to non-secure through NSC.
 2018-07-12 17:51:28 +08:00
ccli8 2da6bf6301 [M2351] Fix STDIO UART 2018-07-12 17:51:27 +08:00
ccli8 a3846932a6 [M2351] Fix target configuration 
1. NUMAKER_PFM_M2351 defaults to non-secure
2. Add NUMAKER_PFM_M2351_S/NUMAKER_PFM_M2351_NS which are for secure/non-secure build respectively.
3. Change output format to Intel HEX
4. Fix device name to M2351KIAAEES from M2351K1AAEES
5. Add detect_code
 2018-07-12 17:51:25 +08:00
cyliangtw 0c3f0f7cb7 [M2351] To fulfill _rtc_localtime one more argument 2018-07-12 17:51:24 +08:00
deepikabhavnani 21de229047 [M2351] Disabled fault handler support 2018-07-12 17:51:23 +08:00
cyliangtw 2b44eeaef5 [M2351] Add gpio_is_connected 2018-07-12 17:51:22 +08:00
cyliangtw ef7f04808d [M2351] Set secure SRAM size as 24KB in SAU & SCU 2018-07-12 17:51:21 +08:00
cyliangtw d99fbcb166 [M2351] Set 48KB SRAM and UART0 as non-secure 2018-07-12 17:51:20 +08:00
cyliangtw 12a7830c9a [M2351] Resolve reset halt issue in MP chip A version 2018-07-12 17:51:19 +08:00
cyliangtw 6163628b1e [M2351] Sync IRQ arrangement to fulfill MP version 2018-07-12 17:51:18 +08:00
cyliangtw 331945fa08 [M2351] Remove redundant GetPC 2018-07-12 17:51:17 +08:00
cyliangtw 90fcc04596 [M2351] Migrate for MP chip version, build sucessfully 2018-07-12 17:51:16 +08:00
Deepika 94d95d34a4 [M2351] Support TrustZone in port_read/port_write 2018-07-12 17:51:14 +08:00
Deepika aec7c5441c [M2351] Add non-secure reset handler address 2018-07-12 17:51:13 +08:00
deepikabhavnani eebc6e38cb [M2351] Corrected Vector table address in scatter file 2018-07-12 17:51:12 +08:00
cyliangtw 46f948aa6f [M2351] Link register base with partition file & correct heap size in linker file 2018-07-12 17:51:11 +08:00
cyliangtw 5985dcd268 [M2351] Support secure loader invoke non-secure Mbed OS 2018-07-12 17:51:10 +08:00
deepikabhavnani 2f01120d93 [M2351] Corrected preprocess define usage in toolchain specific linker files 2018-07-12 17:51:09 +08:00
cyliangtw 18ca9b5e6c [M2351] Fix GCC linker file 'cannot move location counter backwards' issue 2018-07-12 17:51:08 +08:00
cyliangtw ba9e5fdc29 [M2351] IAR linker file support both of secure & non-secure domain 2018-07-12 17:51:07 +08:00
cyliangtw f06644a920 [M2351] Linker files support both of secure & non-secure domain 2018-07-12 17:51:06 +08:00
cyliangtw a2aac528f4 [M2351] Update GCC linker for NSC Veneer 2018-07-12 17:51:05 +08:00
Deepika f7ea847dfe [M2351] ARMC6 compiler related changes 2018-07-12 17:51:04 +08:00
Deepika 1117e84d9e [M2351] Removed device name, till device patch is added to IAR/Keil 2018-07-12 17:51:03 +08:00
Deepika d46220c7e0 [M2351] Set SAU Region present flag for M2351 device and include security header file. 
As per SAU documents, SAU is always present if the security extension is
available. The functionality differs if the SAU contains SAU regions.
If SAU regions are available it is configured with the macro __SAUREGION_PRESENT
 2018-07-12 17:51:02 +08:00
Deepika 11792f60fa [M2351] Added xx_ticker_fire_interrupt function for M2351 device 2018-07-12 17:51:01 +08:00
Deepika ffcc438b5a [M2351] Use Cortex M23 specific header files and interrupts 
1. Update use of correct header files
2. Added missing entry of M2351 device in IAR defines.
3. Removed support of ARM toolchain in targets.json
 2018-07-12 17:51:00 +08:00
cyliangtw e67ed3f86e [M2351] Revise nu_bitutil.h for M23 2018-07-12 17:50:59 +08:00
cyliangtw 6b85478730 [M2351] Modify Nuvoton common files to avoid conflicting with master 2018-07-12 17:50:58 +08:00
cyliangtw 98c8427a90 [M2351] Add partition header file for CMSE feature 2018-07-12 17:50:57 +08:00
cyliangtw 368f8eef93 [M2351] Remove mbed_sdk_init_forced 
1. mbed_sdk_init is called before C++ global obj constructor in OS 5
2. Refine startup file with GCC_ARM toolchain related to this modification.
 2018-07-12 17:50:56 +08:00
cyliangtw 06910bdea5 [M2351] remove progen, not used any more 2018-07-12 17:50:55 +08:00
cyliangtw c5494eb751 [M2351] Support __vector_table instead of __vector_handlers in IAR 2018-07-12 17:50:54 +08:00
cyliangtw 1f27546480 [M2351] Support GCC & IAR toolchain 2018-07-12 17:50:53 +08:00
cyliangtw dcdd9fb56e [M2351] Sync SDH_CardDetection type to avoid GCC compiler error 2018-07-12 17:50:52 +08:00
cyliangtw 205f8dbab2 [M2351] Add one new target M2351, regard as M0+ with some V8M CPU control at first 2018-07-12 17:50:51 +08:00
Mirela Chirica 72aabc9db4 Cellular: HSI set to be source clock for WISE_1570 2018-07-12 10:12:15 +03:00
Cruz Monrreal e1df16e843
Merge pull request #7365 from jeromecoutant/PR_RTC_SHADOW 
STM32 RTC : bypass shadow registers
 2018-07-11 21:29:02 -05:00
Cruz Monrreal 19c6f3b316
Merge pull request #7290 from bcostm/refactor_us_ticker 
STM32: Refactor us_ticker files
 2018-07-11 21:28:32 -05:00
Marcus Chang fd088d2c4e Allow STDIO pins to be NC in NRF52 series 
Prevent ASSERT from triggering when one of the STDIO pins is not
connected.
 2018-07-11 17:19:18 -07:00
Marcus Chang 6f0bb757f4 Fix linker script for NRF52840/IAR 
Add missing noinit section.
 2018-07-11 15:48:51 -07:00
Cruz Monrreal c669655d86
Merge pull request #7042 from shuoo/feature-cm3ds-flash 
Flash API: Enable Flash api on CM3DS
 2018-07-11 09:28:17 -05:00
Cruz Monrreal 38c5e9c669
Merge pull request #7453 from marcuschangarm/fix-nrf52-swi 
Fix SWI conflict in SoftDevice for NRF52 series
 2018-07-11 08:12:30 -05:00
bcostm 0b133be504 stm32 ticker: change th eplace where timer init in done, fix overflow issue with 16-bit timer 
- Move back the 16/32bit timer initialization in HAL_InitTick() and not in us_ticker_init()
- Use ticker_read_us() and us_ticker_read() in HAL_GetTick() to fix potential overflow issue with the 16bit timer

==> These corrections allow timer, rtc, sleep, tick tests to PASS
 2018-07-11 14:45:48 +02:00
bcostm fc50e28ae6 stm32 ticker: corrections in order to pass tests 2018-07-11 14:44:23 +02:00
bcostm 7097e07b62 stm32 ticker: typo corrections 2018-07-11 14:43:36 +02:00
bcostm d8e839a789 stm32 ticker: change license 2018-07-11 14:43:16 +02:00
bcostm 32031cbab3 stm32 ticker: rename hal_tick.h in us_ticker_data.h 2018-07-11 14:42:44 +02:00
Cruz Monrreal dc946b3c34
Merge pull request #7446 from kivaisan/disable_lse_MTB_USI_WM_BN_BM_22 
Disable LSE for MTB_USI_WM_BN_BM_22
 2018-07-11 07:39:44 -05:00
bcostm fbd7a97e19 stm32 ticker: rename macro and update ST HAL Tick functions 
- rename TIM_MST_16BIT in TIM_MST_BIT_WIDTH in order to use it directly in ticker info structure
- change HAL_InitTick() and HAL_GetTick()
 2018-07-11 14:39:42 +02:00
bcostm b1bbd765b7 stm32 ticker: rename files and move functions 
- rename hal_tick_common.c in hal_tick_overrides.c
- move 16 and 32bits timer functions in us_ticker.c
 2018-07-11 14:36:58 +02:00
Steven Cooreman 001844231b Add EFM32GG11_STK3701 support 2018-07-11 10:45:38 +02:00
jeromecoutant 1052993236 STM32 RTC : bypass shadow registers 
- RTC_SSR for the subseconds
- RTC_TR for the time
- RTC_DR for the date

These registers were accessed through shadow registers which are synchronized with PCLK1 (APB1 clock).
They are now accessed directly in order to avoid waiting for the synchronization duration.
 2018-07-11 10:08:02 +02:00
Martin Kojtal 396c88ac3c Raytac: target removal 
No files to build - should not be in targets
Reverts part of the https://github.com/ARMmbed/mbed-os/pull/6178
 2018-07-10 12:23:34 +01:00
Kimmo Vaisanen a5ac795304 Disable LSE for MTB_USI_WM_BN_BM_22 
Current MTB_USI_WM_BN_BM_22 modules do not have OSC32_IN connected, so
external xtal is not in use.
 2018-07-10 08:49:38 +03:00
Marcus Chang 4bb84fdb71 Change NRF52 series UART to only use one SWI channel 
This fixes conflicts with the SoftDevice.
 2018-07-09 12:54:09 -07:00
Marcus Chang cfb99d689a Fix inconsistent SWI configuration in NRF52 series 
All SWI channels except SWI0 is being used by the SoftDevice and
not only SWI1.
 2018-07-09 12:54:09 -07:00
Marcus Chang 01135e30ce Remove white space in config files for NRF52 series 2018-07-09 12:54:08 -07:00
Cruz Monrreal bcec185754
Merge pull request #7352 from bcostm/fix_rtc_ticker 
STM32: Fix RTC test issue on targets using a 16-bit timer for us_ticker
 2018-07-09 10:20:13 -05:00
Karl Zhang bbb97c803b Flash API: Enable Flash api on CM3DS 
Implement flash_api.c for CM3DS on MPS2+.
Because MPS2+ board has no physical flash chip, the implementation emulates
flash over SRAM.
 2018-07-09 21:07:48 +08:00
Cruz Monrreal 69d8c0bac3
Merge pull request #7429 from codeauroraforum/MXRT_Fix_AnalogIn 
MXRT1050: Ensure the pins are in input mode for analogin
 2018-07-06 11:24:40 -05:00
Cruz Monrreal 59defa29e9
Merge pull request #7406 from OpenNuvoton/nuvoton_fix_wakeup_delay 
NANO130: Change PLL clock source to HIRC instead of HXT
 2018-07-06 11:20:40 -05:00