mirror of https://github.com/ARMmbed/mbed-os.git
[M2351] Upgrade partition format
Following BSP, this upgrade makes partitioning flash/SRAM clear. flash_api.c relies on flash partition, so it is updated accordingly.pull/7302/head
ccli8
parent
805049d80f
commit
42aa7fe0c5
|
|
@ -1,8 +1,6 @@
|
|||
/**************************************************************************//**
|
||||
* @file partition_M2351.c
|
||||
* @version V3.00
|
||||
* $Revision: 2 $
|
||||
* $Date: 16/12/28 1:08p $
|
||||
* @brief SAU configuration for secure/nonsecure region settings.
|
||||
*
|
||||
* @note
|
||||
|
|
@ -17,6 +15,271 @@
|
|||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
SRAMNSSET
|
||||
*/
|
||||
/*
|
||||
// Bit 0..16
|
||||
// <o.0..16> Secure SRAM Size <0=> 0 KB
|
||||
// <0x2000=> 8KB
|
||||
// <0x4000=> 16KB
|
||||
// <0x6000=> 24KB
|
||||
// <0x8000=> 32KB
|
||||
// <0xa000=> 40KB
|
||||
// <0xc000=> 48KB
|
||||
// <0xe000=> 56KB
|
||||
// <0x10000=> 64KB
|
||||
// <0x12000=> 72KB
|
||||
// <0x14000=> 80KB
|
||||
// <0x16000=> 88KB
|
||||
// <0x18000=> 96KB
|
||||
*/
|
||||
#define SCU_SECURE_SRAM_SIZE 0x6000
|
||||
#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
NSBA
|
||||
*/
|
||||
#define FMC_INIT_NSBA 1
|
||||
/*
|
||||
// <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
|
||||
*/
|
||||
|
||||
#define FMC_SECURE_ROM_SIZE 0x40000
|
||||
|
||||
#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
|
||||
|
||||
__STATIC_INLINE void FMC_NSBA_Setup(void)
|
||||
{
|
||||
/* Skip NSBA Setupt according config */
|
||||
if(FMC_INIT_NSBA == 0)
|
||||
return;
|
||||
|
||||
/* Check if NSBA value with current active NSBA */
|
||||
if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
|
||||
{
|
||||
/* Unlock Protected Register */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* Enable ISP and config update */
|
||||
FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
|
||||
|
||||
/* Config Base of NSBA */
|
||||
FMC->ISPADDR = 0x200800;
|
||||
|
||||
/* Read Non-secure base address config */
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Setting NSBA when it is empty */
|
||||
if(FMC->ISPDAT == 0xfffffffful)
|
||||
{
|
||||
FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
|
||||
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Force Chip Reset to valid new setting */
|
||||
SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
/* Fatal Error:
|
||||
FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
|
||||
User must double confirm which one is wrong.
|
||||
|
||||
If user need to change NSBA config of FMC, user must do Mess-erase by
|
||||
ISP or ICP.
|
||||
*/
|
||||
while(1);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*
|
||||
// <h> Peripheral Secure Attribution Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
PNSSET0
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.9> USBH <0=> Secure <1=> Non-Secure
|
||||
// <o.13> SD0 <0=> Secure <1=> Non-Secure
|
||||
// <o.16> EBI <0=> Secure <1=> Non-Secure
|
||||
// <o.24> PDMA1 <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET0_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET1
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.17> CRC <0=> Secure <1=> Non-Secure
|
||||
// <o.18> CRPT <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET1_VAL 0xFFFBFFFF
|
||||
/*
|
||||
PNSSET2
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.1> RTC <0=> Secure <1=> Non-Secure
|
||||
// <o.3> EADC <0=> Secure <1=> Non-Secure
|
||||
// <o.5> ACMP01 <0=> Secure <1=> Non-Secure
|
||||
//
|
||||
// <o.7> DAC <0=> Secure <1=> Non-Secure
|
||||
// <o.8> I2S0 <0=> Secure <1=> Non-Secure
|
||||
// <o.13> OTG <0=> Secure <1=> Non-Secure
|
||||
// <o.17> TMR23 <0=> Secure <1=> Non-Secure
|
||||
// <h> EPWM
|
||||
// <o.24> EPWM0 <0=> Secure <1=> Non-Secure
|
||||
// <o.25> EPWM1 <0=> Secure <1=> Non-Secure
|
||||
// <o.26> BPWM0 <0=> Secure <1=> Non-Secure
|
||||
// <o.27> BPWM1 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
*/
|
||||
#define SCU_INIT_PNSSET2_VAL 0xFFFFFFFD
|
||||
/*
|
||||
PNSSET3
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <h> SPI
|
||||
// <o.0> QSPI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.1> SPI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.2> SPI1 <0=> Secure <1=> Non-Secure
|
||||
// <o.3> SPI2 <0=> Secure <1=> Non-Secure
|
||||
// <o.4> SPI3 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
// <h> UART
|
||||
// <o.16> UART0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> UART1 <0=> Secure <1=> Non-Secure
|
||||
// <o.18> UART2 <0=> Secure <1=> Non-Secure
|
||||
// <o.19> UART3 <0=> Secure <1=> Non-Secure
|
||||
// <o.20> UART4 <0=> Secure <1=> Non-Secure
|
||||
// <o.21> UART5 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
*/
|
||||
#define SCU_INIT_PNSSET3_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET4
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <h> I2C
|
||||
// <o.0> I2C0 <0=> Secure <1=> Non-Secure
|
||||
// <o.1> I2C1 <0=> Secure <1=> Non-Secure
|
||||
// <o.2> I2C2 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
// <h> Smart Card
|
||||
// <o.16> SC0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> SC1 <0=> Secure <1=> Non-Secure
|
||||
// <o.18> SC2 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
*/
|
||||
#define SCU_INIT_PNSSET4_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET5
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.0> CAN0 <0=> Secure <1=> Non-Secure
|
||||
// <h> QEI
|
||||
// <o.16> QEI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> QEI1 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
// <h> ECAP
|
||||
// <o.20> ECAP0 <0=> Secure <1=> Non-Secure
|
||||
// <o.21> ECAP1 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
// <o.25> TRNG <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET5_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET6
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.0> USBD <0=> Secure <1=> Non-Secure
|
||||
// <h> USCI
|
||||
// <o.16> USCI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> USCI1 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
*/
|
||||
#define SCU_INIT_PNSSET6_VAL 0xFFFFFFFF
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
// <h> GPIO Secure Attribution Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
IONSSET
|
||||
*/
|
||||
/*
|
||||
// Bit 0..31
|
||||
// <o.0> PA <0=> Secure <1=> Non-Secure
|
||||
// <o.1> PB <0=> Secure <1=> Non-Secure
|
||||
// <o.2> PC <0=> Secure <1=> Non-Secure
|
||||
// <o.3> PD <0=> Secure <1=> Non-Secure
|
||||
// <o.4> PE <0=> Secure <1=> Non-Secure
|
||||
// <o.5> PF <0=> Secure <1=> Non-Secure
|
||||
// <o.6> PG <0=> Secure <1=> Non-Secure
|
||||
// <o.7> PH <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_IONSSET_VAL 0xFFFFFFFF
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Setup SCU Configuration Unit
|
||||
\details
|
||||
|
||||
*/
|
||||
__STATIC_INLINE void SCU_Setup(void)
|
||||
{
|
||||
int32_t i;
|
||||
|
||||
SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
|
||||
SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
|
||||
SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
|
||||
SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
|
||||
SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
|
||||
SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
|
||||
SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
|
||||
|
||||
SCU->IONSSET = SCU_INIT_IONSSET_VAL;
|
||||
|
||||
/* Set Non-secure SRAM */
|
||||
for(i = 11; i >= SCU_SECURE_SRAM_SIZE / 8192; i--)
|
||||
{
|
||||
SCU->SRAMNSSET |= (1U << i);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
// <e>Secure Attribute Unit (SAU) Control
|
||||
*/
|
||||
|
|
@ -41,6 +304,7 @@
|
|||
// </e>
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <h>Enable and Set Secure/Non-Secure region
|
||||
*/
|
||||
|
|
@ -50,7 +314,7 @@
|
|||
// <e>SAU Region 0
|
||||
// <i> Setup SAU Region 0
|
||||
*/
|
||||
#define SAU_INIT_REGION0 1
|
||||
#define SAU_INIT_REGION0 0
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
|
|
@ -73,7 +337,7 @@
|
|||
// <e>SAU Region 1
|
||||
// <i> Setup SAU Region 1
|
||||
*/
|
||||
#define SAU_INIT_REGION1 1
|
||||
#define SAU_INIT_REGION1 0
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
|
|
@ -123,122 +387,122 @@
|
|||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x30006000
|
||||
#define SAU_INIT_START3 0x3f000
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x30017FFF
|
||||
#define SAU_INIT_END3 0x3ffff
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
#define SAU_INIT_NSC3 1
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>SAU Region 4
|
||||
// <i> Setup SAU Region 4
|
||||
<e>SAU Region 4
|
||||
<i> Setup SAU Region 4
|
||||
*/
|
||||
#define SAU_INIT_REGION4 1
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x50000000 /* start address of SAU region 4 */
|
||||
#define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x5FFFFFFF /* end address of SAU region 4 */
|
||||
#define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>SAU Region 5
|
||||
// <i> Setup SAU Region 5
|
||||
<e>SAU Region 5
|
||||
<i> Setup SAU Region 5
|
||||
*/
|
||||
#define SAU_INIT_REGION5 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x00807C00
|
||||
#define SAU_INIT_START5 0x00807E00
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x00807FFF
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 1
|
||||
/*
|
||||
// </e>
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>SAU Region 6
|
||||
// <i> Setup SAU Region 6
|
||||
<e>SAU Region 6
|
||||
<i> Setup SAU Region 6
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
#define SAU_INIT_REGION6 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000
|
||||
#define SAU_INIT_START6 NON_SECURE_SRAM_BASE
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000
|
||||
#define SAU_INIT_END6 0x30017FFF
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>SAU Region 7
|
||||
// <i> Setup SAU Region 7
|
||||
<e>SAU Region 7
|
||||
<i> Setup SAU Region 7
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
#define SAU_INIT_REGION7 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000
|
||||
#define SAU_INIT_START7 0x50000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000
|
||||
#define SAU_INIT_END7 0x5FFFFFFF
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -292,38 +556,44 @@
|
|||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
/*
|
||||
// <o.0> BODOUT <0=> Secure <1=> Non-Secure
|
||||
// <o.1> IRC <0=> Secure <1=> Non-Secure
|
||||
// <o.2> PWRWU_ <0=> Secure <1=> Non-Secure
|
||||
// <o.3> SRAM_PERR <0=> Secure <1=> Non-Secure
|
||||
// <o.4> CLKFAIL <0=> Secure <1=> Non-Secure
|
||||
// BODOUT Always secure
|
||||
// IRC Always secure
|
||||
// PWRWU_ Always secure
|
||||
// SRAM_PERR Always secure
|
||||
// CLKFAIL Always secure
|
||||
|
||||
// <o.6> RTC <0=> Secure <1=> Non-Secure
|
||||
// <o.7> TAMPER <0=> Secure <1=> Non-Secure
|
||||
// <o.8> WDT <0=> Secure <1=> Non-Secure
|
||||
// <o.9> WWDT <0=> Secure <1=> Non-Secure
|
||||
// WDT Always secure
|
||||
// WWDT Always secure
|
||||
// <h> EINT
|
||||
// <o.10> EINT0 <0=> Secure <1=> Non-Secure
|
||||
// <o.11> EINT1 <0=> Secure <1=> Non-Secure
|
||||
// <o.12> EINT2 <0=> Secure <1=> Non-Secure
|
||||
// <o.13> EINT3 <0=> Secure <1=> Non-Secure
|
||||
// <o.14> EINT4 <0=> Secure <1=> Non-Secure
|
||||
// <o.15> EINT5 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
// <h> GPIO
|
||||
// <o.16> GPA <0=> Secure <1=> Non-Secure
|
||||
// <o.17> GPB <0=> Secure <1=> Non-Secure
|
||||
// <o.18> GPC <0=> Secure <1=> Non-Secure
|
||||
// <o.19> GPD <0=> Secure <1=> Non-Secure
|
||||
// <o.20> GPE <0=> Secure <1=> Non-Secure
|
||||
// <o.21> GPF <0=> Secure <1=> Non-Secure
|
||||
// <o.22> SPI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.23> SPI1 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
// <o.22> QSPI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.23> SPI0 <0=> Secure <1=> Non-Secure
|
||||
// <h> EPWM
|
||||
// <o.24> BRAKE0 <0=> Secure <1=> Non-Secure
|
||||
// <o.25> PWM0_P0 <0=> Secure <1=> Non-Secure
|
||||
// <o.26> PWM0_P1 <0=> Secure <1=> Non-Secure
|
||||
// <o.27> PWM0_P2 <0=> Secure <1=> Non-Secure
|
||||
// <o.25> EPWM0_P0 <0=> Secure <1=> Non-Secure
|
||||
// <o.26> EPWM0_P1 <0=> Secure <1=> Non-Secure
|
||||
// <o.27> EPWM0_P2 <0=> Secure <1=> Non-Secure
|
||||
// <o.28> BRAKE1 <0=> Secure <1=> Non-Secure
|
||||
// <o.29> PWM1_P0 <0=> Secure <1=> Non-Secure
|
||||
// <o.30> PWM1_P1 <0=> Secure <1=> Non-Secure
|
||||
// <o.31> PWM1_P2 <0=> Secure <1=> Non-Secure
|
||||
// <o.29> EPWM1_P0 <0=> Secure <1=> Non-Secure
|
||||
// <o.30> EPWM1_P1 <0=> Secure <1=> Non-Secure
|
||||
// <o.31> EPWM1_P2 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
//
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0xFFFFFFBF
|
||||
|
|
@ -333,10 +603,12 @@
|
|||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
/*
|
||||
// <o.0> TMR0 <0=> Secure <1=> Non-Secure
|
||||
// <o.1> TMR1 <0=> Secure <1=> Non-Secure
|
||||
// <h> TIMER
|
||||
// TMR0 Always secure
|
||||
// TMR1 Always secure
|
||||
// <o.2> TMR2 <0=> Secure <1=> Non-Secure
|
||||
// <o.3> TMR3 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
// <o.4> UART0 <0=> Secure <1=> Non-Secure
|
||||
// <o.5> UART1 <0=> Secure <1=> Non-Secure
|
||||
// <o.6> I2C0 <0=> Secure <1=> Non-Secure
|
||||
|
|
@ -352,18 +624,20 @@
|
|||
// <o.16> UART2 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> UART3 <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <o.19> SPI2 <0=> Secure <1=> Non-Secure
|
||||
// <o.20> SPI3 <0=> Secure <1=> Non-Secure
|
||||
// <o.19> SPI1 <0=> Secure <1=> Non-Secure
|
||||
// <o.20> SPI2 <0=> Secure <1=> Non-Secure
|
||||
// <o.21> USBD <0=> Secure <1=> Non-Secure
|
||||
// <o.22> USBH <0=> Secure <1=> Non-Secure
|
||||
// <o.23> USBOTG <0=> Secure <1=> Non-Secure
|
||||
// <o.24> CAN0 <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <h> Smart Card
|
||||
// <o.26> SC0 <0=> Secure <1=> Non-Secure
|
||||
// <o.27> SC1 <0=> Secure <1=> Non-Secure
|
||||
// <o.28> SC2 <0=> Secure <1=> Non-Secure
|
||||
// </h>
|
||||
|
||||
// <o.30> SPI4 <0=> Secure <1=> Non-Secure
|
||||
// <o.30> SPI3 <0=> Secure <1=> Non-Secure
|
||||
|
||||
//
|
||||
*/
|
||||
|
|
@ -380,10 +654,10 @@
|
|||
|
||||
// <o.4> I2S0 <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <o.6> OPA0 <0=> Secure <1=> Non-Secure
|
||||
//
|
||||
// <o.7> CRYPTO <0=> Secure <1=> Non-Secure
|
||||
// <o.8> GPG <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <o.9> EINT6 <0=> Secure <1=> Non-Secure
|
||||
// <o.10> UART4 <0=> Secure <1=> Non-Secure
|
||||
// <o.11> UART5 <0=> Secure <1=> Non-Secure
|
||||
// <o.12> USCI0 <0=> Secure <1=> Non-Secure
|
||||
|
|
@ -391,17 +665,17 @@
|
|||
// <o.14> BPWM0 <0=> Secure <1=> Non-Secure
|
||||
// <o.15> BPWM1 <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <o.17> ICAP <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <o.18> I2C2 <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <o.20> QEI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.21> QEI1 <0=> Secure <1=> Non-Secure
|
||||
// <o.22> ECAP0 <0=> Secure <1=> Non-Secure
|
||||
// <o.23> ECAP1 <0=> Secure <1=> Non-Secure
|
||||
// <o.24> GPH <0=> Secure <1=> Non-Secure
|
||||
// <o.25> EINT7 <0=> Secure <1=> Non-Secure
|
||||
|
||||
|
||||
// <o.26> SDH1 <0=> Secure <1=> Non-Secure
|
||||
|
||||
// <o.28> USBH <0=> Secure <1=> Non-Secure
|
||||
|
||||
|
||||
|
|
@ -416,11 +690,9 @@
|
|||
*/
|
||||
#define NVIC_INIT_ITNS3 1
|
||||
/*
|
||||
// <o.0> SPI5 <0=> Secure <1=> Non-Secure
|
||||
// <o.1> DSRC <0=> Secure <1=> Non-Secure
|
||||
// <o.2> PDMA1 <0=> Secure <1=> Non-Secure
|
||||
// <o.3> SCU <0=> Secure <1=> Non-Secure
|
||||
// <o.4> LCD <0=> Secure <1=> Non-Secure
|
||||
// SCU Always secure
|
||||
//
|
||||
// <o.5> TRNG <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0xFFFFFFFF
|
||||
|
|
@ -431,8 +703,8 @@
|
|||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/*
|
||||
max 128 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
|
|
@ -452,7 +724,7 @@
|
|||
__STATIC_INLINE void TZ_SAU_Setup(void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
#if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
|
|
@ -488,13 +760,13 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
|
|||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT ) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
|
||||
|
|
@ -539,267 +811,8 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
|
|||
/* repeat this for all possible ITNS elements */
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
// <h> Peripheral Secure Attribution Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
PNSSET0
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.9> USBH <0=> Secure <1=> Non-Secure
|
||||
// <o.13> SD0 <0=> Secure <1=> Non-Secure
|
||||
// <o.14> SD1 <0=> Secure <1=> Non-Secure
|
||||
// <o.16> EBI <0=> Secure <1=> Non-Secure
|
||||
// <o.24> PDMA1 <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET0_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET1
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.17> CRC <0=> Secure <1=> Non-Secure
|
||||
// <o.18> CRPT <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET1_VAL 0xFFFBFFFF
|
||||
/*
|
||||
PNSSET2
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.1> RTC <0=> Secure <1=> Non-Secure
|
||||
// <o.3> EADC <0=> Secure <1=> Non-Secure
|
||||
// <o.5> ACMP01 <0=> Secure <1=> Non-Secure
|
||||
// <o.6> OPA <0=> Secure <1=> Non-Secure
|
||||
// <o.7> DAC <0=> Secure <1=> Non-Secure
|
||||
// <o.8> I2S0 <0=> Secure <1=> Non-Secure
|
||||
// <o.13> OTG <0=> Secure <1=> Non-Secure
|
||||
// <o.17> TMR23 <0=> Secure <1=> Non-Secure
|
||||
// <o.24> PWM0 <0=> Secure <1=> Non-Secure
|
||||
// <o.25> PWM1 <0=> Secure <1=> Non-Secure
|
||||
// <o.26> BPWM0 <0=> Secure <1=> Non-Secure
|
||||
// <o.27> BPWM1 <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET2_VAL 0xFFFFFFFD
|
||||
/*
|
||||
PNSSET3
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.0> SPI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.1> SPI1 <0=> Secure <1=> Non-Secure
|
||||
// <o.2> SPI2 <0=> Secure <1=> Non-Secure
|
||||
// <o.3> SPI3 <0=> Secure <1=> Non-Secure
|
||||
// <o.4> SPI4 <0=> Secure <1=> Non-Secure
|
||||
// <o.5> SPI5 <0=> Secure <1=> Non-Secure
|
||||
// <o.16> UART0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> UART1 <0=> Secure <1=> Non-Secure
|
||||
// <o.18> UART2 <0=> Secure <1=> Non-Secure
|
||||
// <o.19> UART3 <0=> Secure <1=> Non-Secure
|
||||
// <o.20> UART4 <0=> Secure <1=> Non-Secure
|
||||
// <o.21> UART5 <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET3_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET4
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.0> I2C0 <0=> Secure <1=> Non-Secure
|
||||
// <o.1> I2C1 <0=> Secure <1=> Non-Secure
|
||||
// <o.2> I2C2 <0=> Secure <1=> Non-Secure
|
||||
// <o.16> SC0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> SC1 <0=> Secure <1=> Non-Secure
|
||||
// <o.18> SC2 <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET4_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET5
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.0> CAN0 <0=> Secure <1=> Non-Secure
|
||||
// <o.16> QEI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> QEI1 <0=> Secure <1=> Non-Secure
|
||||
// <o.20> ECAP0 <0=> Secure <1=> Non-Secure
|
||||
// <o.21> ECAP1 <0=> Secure <1=> Non-Secure
|
||||
// <o.23> DSRC <0=> Secure <1=> Non-Secure
|
||||
// <o.24> LCD <0=> Secure <1=> Non-Secure
|
||||
// <o.25> TRNG <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET5_VAL 0xFFFFFFFF
|
||||
/*
|
||||
PNSSET6
|
||||
*/
|
||||
/*
|
||||
// Module 0..31
|
||||
// <o.0> USBD <0=> Secure <1=> Non-Secure
|
||||
// <o.16> USCI0 <0=> Secure <1=> Non-Secure
|
||||
// <o.17> USCI1 <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_PNSSET6_VAL 0xFFFFFFFF
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
// <h> GPIO Secure Attribution Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
IONSSET
|
||||
*/
|
||||
/*
|
||||
// Bit 0..31
|
||||
// <o.0> PA <0=> Secure <1=> Non-Secure
|
||||
// <o.1> PB <0=> Secure <1=> Non-Secure
|
||||
// <o.2> PC <0=> Secure <1=> Non-Secure
|
||||
// <o.3> PD <0=> Secure <1=> Non-Secure
|
||||
// <o.4> PE <0=> Secure <1=> Non-Secure
|
||||
// <o.5> PF <0=> Secure <1=> Non-Secure
|
||||
// <o.6> PG <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_IONSSET_VAL 0xFFFFFFFF
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <h> SRAM Secure Attribution Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
SRAMNSSET
|
||||
*/
|
||||
/*
|
||||
// Bit 0..31
|
||||
// <o.0> 0x00000000 ~ 0x00001FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.1> 0x00002000 ~ 0x00003FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.2> 0x00004000 ~ 0x00005FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.3> 0x00006000 ~ 0x00007FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.4> 0x00008000 ~ 0x00009FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.5> 0x0000A000 ~ 0x0000BFFF <0=> Secure <1=> Non-Secure
|
||||
// <o.6> 0x0000C000 ~ 0x0000DFFF <0=> Secure <1=> Non-Secure
|
||||
// <o.7> 0x0000E000 ~ 0x0000FFFF <0=> Secure <1=> Non-Secure
|
||||
// <o.8> 0x00010000 ~ 0x00011FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.9> 0x00012000 ~ 0x00013FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.10> 0x00014000 ~ 0x00015FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.11> 0x00016000 ~ 0x00017FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.12> 0x00018000 ~ 0x00019FFF <0=> Secure <1=> Non-Secure
|
||||
// <o.13> 0x0001A000 ~ 0x0001BFFF <0=> Secure <1=> Non-Secure
|
||||
// <o.14> 0x0001C000 ~ 0x0001DFFF <0=> Secure <1=> Non-Secure
|
||||
// <o.15> 0x0001E000 ~ 0x0001FFFF <0=> Secure <1=> Non-Secure
|
||||
*/
|
||||
#define SCU_INIT_SRAMNSSET_VAL 0x00000FF8
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Setup SCU Configuration Unit
|
||||
\details
|
||||
|
||||
*/
|
||||
__STATIC_INLINE void SCU_Setup(void)
|
||||
{
|
||||
SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
|
||||
SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
|
||||
SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
|
||||
SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
|
||||
SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
|
||||
SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
|
||||
SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
|
||||
|
||||
SCU->IONSSET = SCU_INIT_IONSSET_VAL;
|
||||
SCU->SRAMNSSET = SCU_INIT_SRAMNSSET_VAL;
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
// <h> APROM Non-secure Base Address Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
NSBA
|
||||
*/
|
||||
/*
|
||||
// <e> Enable Non-secure Base Address
|
||||
// <i> To check active Non-secure base address.
|
||||
*/
|
||||
#define FMC_INIT_NSBA 1
|
||||
/*
|
||||
// <o>NSBA <0x4000-0x7FFFF>
|
||||
*/
|
||||
#define FMC_INIT_NSBA_VAL 0x00040000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
__STATIC_INLINE void FMC_NSBA_Setup(void)
|
||||
{
|
||||
/* Skip NSBA Setupt according config */
|
||||
if(FMC_INIT_NSBA == 0)
|
||||
return;
|
||||
|
||||
/* Check if NSBA value with current active NSBA */
|
||||
if(SCU->FNSADDR != FMC_INIT_NSBA_VAL)
|
||||
{
|
||||
/* Unlock Protected Register */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* Enable ISP and config update */
|
||||
FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
|
||||
|
||||
/* Config Base of NSBA */
|
||||
FMC->ISPADDR = 0x200800;
|
||||
|
||||
/* Read Non-secure base address config */
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Setting NSBA when it is empty */
|
||||
if(FMC->ISPDAT == 0xfffffffful)
|
||||
{
|
||||
FMC->ISPDAT = FMC_INIT_NSBA_VAL;
|
||||
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Force Chip Reset to valid new setting */
|
||||
SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
/* Fatal Error:
|
||||
FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
|
||||
User must double confirm which one is wrong.
|
||||
|
||||
If user need to change NSBA config of FMC, user must do Mess-erase by
|
||||
ISP or ICP.
|
||||
*/
|
||||
while(1);
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
#endif /* PARTITION_M2351 */
|
||||
|
||||
|
|
|
|||
|
|
@ -94,10 +94,10 @@ static const flash_target_config_t flash_target_config = {
|
|||
// Here page_size is program unit, which is different
|
||||
// than FMC definition.
|
||||
.flash_start = 0x0,
|
||||
#if SAU_INIT_REGION1
|
||||
.flash_size = (SAU_INIT_START1 & ~NS_OFFSET) - 0x0,
|
||||
#if defined(FMC_SECURE_ROM_SIZE)
|
||||
.flash_size = FMC_SECURE_ROM_SIZE,
|
||||
#else
|
||||
.flash_size = 0x80000 // 512 KB
|
||||
.flash_size = 0x80000, // 512 KB
|
||||
#endif
|
||||
.sectors = sectors_info,
|
||||
.sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
|
||||
|
|
@ -105,7 +105,7 @@ static const flash_target_config_t flash_target_config = {
|
|||
|
||||
/* Non-secure flash */
|
||||
static const sector_info_t sectors_info_ns[] = {
|
||||
{SAU_INIT_START1, 0x800}, // (start, sector size)
|
||||
{(NS_OFFSET + FMC_SECURE_ROM_SIZE), 0x800}, // (start, sector size)
|
||||
};
|
||||
|
||||
/* Non-secure flash */
|
||||
|
|
@ -113,9 +113,9 @@ static const flash_target_config_t flash_target_config_ns = {
|
|||
.page_size = 4, // 4 bytes
|
||||
// Here page_size is program unit, which is different
|
||||
// than FMC definition.
|
||||
.flash_start = SAU_INIT_START1,
|
||||
#if SAU_INIT_REGION1
|
||||
.flash_size = SAU_INIT_END1 - SAU_INIT_START1 + 1,
|
||||
.flash_start = NS_OFFSET + FMC_SECURE_ROM_SIZE,
|
||||
#if defined(FMC_SECURE_ROM_SIZE)
|
||||
.flash_size = 0x80000 - FMC_SECURE_ROM_SIZE,
|
||||
#else
|
||||
.flash_size = 0,
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue