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[M2351] Change secure/non-secure stack/heap size 

1. Change RTOS-less main stack/RTOS ISR stack size to 2KiB
2. Change secure/non-secure heap size to 16KiB/32KiB for IAR
pull/7302/head
ccli8 2018-05-03 17:22:36 +08:00
parent 04f723755b
commit c3c661da8d
4 changed files with 49 additions and 15 deletions
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27
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct
View File

@ -21,6 +21,15 @@
*/
#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE)
/* Initial/ISR stack size */
#if (! defined(NU_INITIAL_STACK_SIZE))
#if defined(__DOMAIN_NS) && __DOMAIN_NS
#define NU_INITIAL_STACK_SIZE 0x800
#else
#define NU_INITIAL_STACK_SIZE 0x800
#endif
#endif
#if defined(__DOMAIN_NS) && __DOMAIN_NS
#if (! defined(MBED_APP_START))
@ -41,12 +50,15 @@ LR_IROM1 MBED_APP_START
.ANY (+RO)
}
ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY 0x800
ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY NU_INITIAL_STACK_SIZE
{
}
/* Reserve for vectors */
ER_IRAMVEC 0x30000800 + NU_TZ_SECURE_SRAM_SIZE EMPTY (4*(16 + 102))
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
@ -84,12 +96,15 @@ LR_IROM1 MBED_APP_START
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY 0x800
ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE
{
}
/* Reserve for vectors */
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102))
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}

27
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct
View File

@ -21,6 +21,15 @@
*/
#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE)
/* Initial/ISR stack size */
#if (! defined(NU_INITIAL_STACK_SIZE))
#if defined(__DOMAIN_NS) && __DOMAIN_NS
#define NU_INITIAL_STACK_SIZE 0x800
#else
#define NU_INITIAL_STACK_SIZE 0x800
#endif
#endif
#if defined(__DOMAIN_NS) && __DOMAIN_NS
#if (! defined(MBED_APP_START))
@ -41,12 +50,15 @@ LR_IROM1 MBED_APP_START
.ANY (+RO)
}
ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY 0x800
ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY NU_INITIAL_STACK_SIZE
{
}
/* Reserve for vectors */
ER_IRAMVEC 0x30000800 + NU_TZ_SECURE_SRAM_SIZE EMPTY (4*(16 + 102))
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}
@ -84,12 +96,15 @@ LR_IROM1 MBED_APP_START
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY 0x800
ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE
{
}
/* Reserve for vectors */
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102))
/* Reserve for vectors
*
* Vector table base address is required to be 128-byte aligned at a minimum.
* A PE might impose further restrictions on it. */
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
{
}

4
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld
View File

@ -2,7 +2,11 @@
* Nuvoton M2351 GCC linker script file
*/
#if defined(__DOMAIN_NS) && __DOMAIN_NS
StackSize = 0x800;
#else
StackSize = 0x800;
#endif
#include "partition_M2351_sub.h"

6
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf
View File

@ -25,7 +25,7 @@ if (isdefinedsymbol(__DOMAIN_NS)) {
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_heap__ = 0x8000;
} else {
@ -61,8 +61,8 @@ if (isdefinedsymbol(__DOMAIN_NS)) {
export symbol __NU_TZ_NSC_REGION_SIZE__ = NU_TZ_NSC_REGION_SIZE;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x4000;
}
/**** End of ICF editor section. ###ICF###*/