The memset function from c library will be linked in flash
space, it's risk for FLASHIAP. So I wrote flexspi_memset
to replace the memset for IMX FLASHIAP, and put the function
into targets/.../TARGET_IMX/flash_api.c file. All IMX Soc
platforms can declare it as extern and use in their Soc
flexspi driver files.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
The flash access may fail when implementing flash
initialization. So there is risk for interrupt handler
which linked in flash space.
Add the critical section to avoid the risk.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
NXP MIMXRT1050 EVK can support Hyper Flash or QSPI Flash with
small hardware reworks. Modify the XIP file to support boot
from the two kinds of Flash device. The Hyper Flash should be
the default device and defined in tartgets.json with the macro
"HYPERFLASH_BOOT". To select the QSPI Flash, just remove the
macro with the below line in any overriding json file.
"target.macros_remove" : ["HYPERFLASH_BOOT"]
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
Static pinmap extension required to use pin_function() and pin_mode() functions instead of pinmap_pinout(). Unfortunatelly pin_function() does not allow passing NC pin.
Call pin_function() and pin_mode() only if MISO/MOSI pin is not NC.
Remove an obsolete HAL implementation from LPC408X to fix the GCC_ARM
build with the "-flto" flag.
With the lto enabled, unreferenced buffers defined in ethernet_api.c
were not excluded at link time overflowing the 16kB peripheral SRAM1
(ld error: "section '.AHBSRAM1' will not fit in region 'ETH_RAM'").
The Ethernet HAL API is deprecated in favor of EMAC.
1. Do not disable and enable osillators during deep sleep
entry and exit
2. Increase the deep sleep to pass tests
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add a "used" attribute to hyperflash_config/image_vector_table to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
All targets must implement soft_- and hard_power_on/off() functions which are practically same what onboard_modem_api offered.
These were seen as a duplicate features and therefore we removed this.
All targets involved have been updated to reflect the changes
The SDK header provides separate arrays for high and low
GPIO interrupts in place of the previous combined array
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. No need to copy RAM functions, this is done in the startup file
2. Update memory config for the FLASH section
3. Configure the PMIC_STDBY pin
4. Update UART clock setting
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
As the `psa` library is not included in the baremetal profile, perform
a TFM system reset only if the `psa` library is included in
the build otherwise perform a normal CMSIS system reset.
ARM Compiler 6.13 testing revealed linker errors pointing out
conflicting use of `__user_setup_stackheap` and
`__user_initial_stackheap` in some targets. Remove the unwanted
`__user_initial_stackheap` from the targets - the setup is
centralised in the common platform code.
Looking into this, a number of other issues were highlighted
* Almost all targets had `__initial_sp` hardcoded in assembler,
rather than getting it from the scatter file. This was behind
issue #11313. Fix this generally.
* A few targets' `__initial_sp` values did not match the scatter
file layout, in some cases meaning they were overlapping heap
space. They now all use the area reserved in the scatter file.
If any problems are seen, then there is an error in the
scatter file.
* A number of targets were reserving unneeded space for heap and
stack in their startup assembler, on top of the space reserved in
the scatter file, so wasting a few K. A couple were using that
space for the stack, rather than the space in the scatter file.
To clarify expected behaviour:
* Each scatter file contains empty regions `ARM_LIB_HEAP` and
`ARM_LIB_STACK` to reserve space. `ARM_LIB_STACK` is sized
by the macro `MBED_BOOT_STACK_SIZE`, which is set by the tools.
`ARM_LIB_HEAP` is generally the space left over after static
RAM and stack.
* The address of the end of `ARM_LIB_STACK` is written into the
vector table and on reset the CPU sets MSP to that address.
* The common platform code in Mbed OS provides `__user_setup_stackheap`
for the ARM library. The ARM library calls this during startup, and
it calls `__mbed_user_setup_stackheap`.
* The default weak definition of `__mbed_user_setup_stackheap` does not
modify SP, so we remain on the boot stack, and the heap is set to
the region described by `ARM_LIB_HEAP`. If `ARM_LIB_HEAP` doesn't
exist, then the heap is the space from the end of the used data in
`RW_IRAM1` to the start of `ARM_LIB_STACK`.
* Targets can override `__mbed_user_setup_stackheap` if they want.
Currently only Renesas (ARMv7-A class) devices do.
* If microlib is in use, then it doesn't call `__user_setup_stackheap`.
Instead it just finds and uses `ARM_LIB_STACK` and `ARM_LIB_HEAP`
itself.
We should not block in case the UART is busy transmitting. The
API has been updated to check the status of all UART's and return
1 in case any of them is busy transmitting.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The code checks if any of the UART's is still transmitting.
If so then prevent from entering deepsleep
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Use the updated API's provided by the SMC driver
2. Wait till debug UART has finished transmitting data
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update to handle 12-bit resolution
2. Properly handle the pin configuration
3. Update the pin setup to handle the ADC B channel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The IRQ disable was always disabling both rising
and falling edges of the interrupt thereby causing
failures in cases when one of the two should stay enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update the clock divider setting
2. ADC resolution is 12-bits, update the API return value
to return 16-bit result
3. Update IOMUX setup
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
An extra start signal was observed on the bus which was
discovered by the FPGA test shield.
This is because the hardware sends out a transaction as soon
as a write to the START bit. Hence the write to the START
bit is delayed by using a flag.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
As the build tool in mbed-os 5.13 cannot appropriately deal with a segmented
bootloader when combining it with an application, this commit adjusts the
size reserved for interrupts (via the linker file) to avoid a bootloader
segmentation due to an unpopulated ROM area.
The microcontroller has a total of 60 vector interrupts + 16 exception
handlers. The allocated ROM flash for interrupts should be (60 + 16) x word
size in bytes = 76 x 4 = 304 = 0x130.
This commit changes the interrupt reserved space from 0x140 to 0x130.
The file 'fsl_powerquad_data.h' declares several dctXXX_cosFactor
arrays with sizes twice larger compared to the actual definitions in
'fsl_powerquad_data.c'.
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
Spotted in compiler warnings - code was trying to access a non-existent
second security control block, rather than access the settings for the
second APB bridge in the first and only security control block.
Fixes test failure seen with tests-mbed_hal-stack_size_unification
under IAR and ARM toolchain
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
The flash driver for the LPC55S69 is different from
prior LPC family. Move the Flash HAL driver to SoC
specific folder
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Gavin Liu
Martin Kojtal
mudassar-ublox
Rajkumar Kanagaraj
Przemyslaw Stekiel
Filip Jagodzinski
Mahesh Mahadevan
Hugues Kamba
Maciej Bocianski
Pawel Zarembski
Tymoteusz Bloch
Antti Kauppila
toyowata
Qinghao Shi
Kevin Bracey
int_szyk
Jaeden Amero
Chris Snow
David Rauschenbach
Seppo Takalo
Arto Kinnunen
Mathias Brossard
Wajahat Abbas
Deepika
Michael Schwarcz
David Saada
Oren Cohen
Alexander Zilberkant