mirror of https://github.com/ARMmbed/mbed-os.git
MIMXRT1050: Update the mbed_overrides file
1. No need to copy RAM functions, this is done in the startup file 2. Update memory config for the FLASH section 3. Configure the PMIC_STDBY pin 4. Update UART clock setting Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>pull/12095/head
Mahesh Mahadevan
parent
6c3adb026c
commit
b906d259d8
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK
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@ -17,6 +17,8 @@
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#include "fsl_clock_config.h"
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#include "fsl_clock.h"
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#include "fsl_xbara.h"
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#include "fsl_iomuxc.h"
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#include "fsl_gpio.h"
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#include "lpm.h"
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#define LPSPI_CLOCK_SOURCE_DIVIDER (7U)
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@ -40,10 +42,10 @@ void BOARD_ConfigMPU(void)
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
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* API in core_cm7.h.
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* API in mpu_armv7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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* Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Use MACROS defined in mpu_armv7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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@ -60,26 +62,22 @@ void BOARD_ConfigMPU(void)
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h.
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*/
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/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 2 setting */
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/* Region 2 setting */
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Setting Memory with Normal type, not shareable, outer/inner write back. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
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#else
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/* Setting Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
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#endif
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/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
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@ -98,9 +96,9 @@ void BOARD_ConfigMPU(void)
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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/* The define sets the cacheable memory to shareable,
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* this suggestion is referred from chapter 2.2.1 Memory regions,
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* types and attributes in Cortex-M7 Devices, Generic User Guide */
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/* The define sets the cacheable memory to shareable,
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* this suggestion is referred from chapter 2.2.1 Memory regions,
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* types and attributes in Cortex-M7 Devices, Generic User Guide */
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#if defined(SDRAM_IS_SHAREABLE)
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/* Region 7 setting: Memory with Normal type, shareable, outer/inner write back, write/read allocate */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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@ -125,38 +123,44 @@ void BOARD_ConfigMPU(void)
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SCB_EnableICache();
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}
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#if defined(TOOLCHAIN_GCC_ARM)
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extern uint32_t __ram_function_flash_start[];
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#define __RAM_FUNCTION_FLASH_START __ram_function_flash_start
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extern uint32_t __ram_function_ram_start[];
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#define __RAM_FUNCTION_RAM_START __ram_function_ram_start
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extern uint32_t __ram_function_size[];
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#define __RAM_FUNCTION_SIZE __ram_function_size
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void Board_CopyToRam()
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{
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unsigned char *source;
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unsigned char *destiny;
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unsigned int size;
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void BOARD_Init_PMIC_STBY_REQ(void) {
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs); /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */
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source = (unsigned char *)(__RAM_FUNCTION_FLASH_START);
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destiny = (unsigned char *)(__RAM_FUNCTION_RAM_START);
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size = (unsigned long)(__RAM_FUNCTION_SIZE);
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/* GPIO configuration of PERI_PWREN on PMIC_STBY_REQ (pin L7) */
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gpio_pin_config_t PERI_PWREN_config = {
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.direction = kGPIO_DigitalOutput,
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.outputLogic = 0U,
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.interruptMode = kGPIO_NoIntmode
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};
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/* Initialize GPIO functionality on PMIC_STBY_REQ (pin L7) */
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GPIO_PinInit(GPIO5, 2U, &PERI_PWREN_config);
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while (size--)
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{
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*destiny++ = *source++;
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}
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IOMUXC_SetPinMux(
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IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ is configured as GPIO5_IO02 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinConfig(
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IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ PAD functional properties : */
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0x10B0U); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: R0/6
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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}
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#endif
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// called before main
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void mbed_sdk_init()
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{
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BOARD_ConfigMPU();
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BOARD_BootClockRUN();
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#if defined(TOOLCHAIN_GCC_ARM)
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Board_CopyToRam();
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#endif
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/* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is
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* connected to LCD power switch circuit. So it needs to be configured as a low-level output GPIO to reduce the
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* current. */
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BOARD_Init_PMIC_STBY_REQ();
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LPM_Init();
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}
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@ -187,16 +191,15 @@ uint32_t us_ticker_get_clock()
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void serial_setup_clock(void)
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{
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/* We assume default PLL and divider settings */
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/* Configure UART divider to default */
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CLOCK_SetMux(kCLOCK_UartMux, 1); /* Set UART source to OSC 24M */
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CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
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}
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uint32_t serial_get_clock(void)
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{
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uint32_t clock_freq;
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/* We assume default PLL and divider settings, and the only variable
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* from application is use PLL3 source or OSC source
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*/
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ {
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clock_freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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} else {
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