ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #12095 from NXPmicro/Update_MXRT_SDK6 

Update MXRT1050 to SDK 6.0
pull/12189/head
Martin Kojtal 2020-01-03 15:22:13 +00:00 committed by GitHub
parent 83101170a3 a947c523ea
commit 7fd637b66b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
165 changed files with 39595 additions and 11764 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
features/netsocket/emac-drivers/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c
View File

@ -215,7 +215,7 @@ void kinetis_init_eth_hardware(void)
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 10, 1);
GPIO_WritePinOutput(GPIO1, 9, 0);
wait_ms(1);
wait_us(1 * 1000);
GPIO_WritePinOutput(GPIO1, 9, 1);
}

27
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c
View File

@ -38,7 +38,8 @@ static gpio_irq_handler irq_handler;
static GPIO_Type * const gpio_addrs[] = GPIO_BASE_PTRS;
/* Array of PORT IRQ number. */
static const IRQn_Type gpio_irqs[] = GPIO_COMBINED_IRQS;
static const IRQn_Type gpio_low_irqs[] = GPIO_COMBINED_LOW_IRQS;
static const IRQn_Type gpio_high_irqs[] = GPIO_COMBINED_HIGH_IRQS;
static void handle_interrupt_in(PortName port, int ch_base)
{
@ -117,8 +118,6 @@ void gpio5_irq(void)
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
uint32_t int_index;
if (pin == NC) {
return -1;
}
@ -156,14 +155,14 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
break;
}
int_index = 2 * obj->port;
if (obj->pin > 15) {
int_index -= 1;
NVIC_SetVector(gpio_high_irqs[obj->port], vector);
NVIC_EnableIRQ(gpio_high_irqs[obj->port]);
} else {
NVIC_SetVector(gpio_low_irqs[obj->port], vector);
NVIC_EnableIRQ(gpio_low_irqs[obj->port]);
}
NVIC_SetVector(gpio_irqs[int_index], vector);
NVIC_EnableIRQ(gpio_irqs[int_index]);
obj->ch = ch_base + obj->pin;
channel_ids[obj->ch] = id;
@ -243,12 +242,20 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
void gpio_irq_enable(gpio_irq_t *obj)
{
NVIC_EnableIRQ(gpio_irqs[obj->port]);
if (obj->pin > 15) {
NVIC_EnableIRQ(gpio_high_irqs[obj->port]);
} else {
NVIC_EnableIRQ(gpio_low_irqs[obj->port]);
}
}
void gpio_irq_disable(gpio_irq_t *obj)
{
NVIC_DisableIRQ(gpio_irqs[obj->port]);
if (obj->pin > 15) {
NVIC_DisableIRQ(gpio_high_irqs[obj->port]);
} else {
NVIC_DisableIRQ(gpio_low_irqs[obj->port]);
}
}
#endif

4
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/lp_ticker.c
View File

@ -52,6 +52,7 @@ void lp_ticker_init(void)
gptConfig.clockSource = kGPT_ClockSource_LowFreq;
gptConfig.enableFreeRun = true;
gptConfig.enableMode = false;
gptConfig.enableRunInDoze = true;
GPT_Init(GPT2, &gptConfig);
GPT_EnableInterrupts(GPT2, kGPT_OutputCompare1InterruptEnable);
@ -114,7 +115,8 @@ void lp_ticker_clear_interrupt(void)
void lp_ticker_free(void)
{
GPT_DisableInterrupts(GPT2, kGPT_OutputCompare1InterruptEnable);
NVIC_DisableIRQ(GPT2_IRQn);
}
#endif /* DEVICE_LPTICKER */

22
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/serial_api.c
View File

@ -29,7 +29,8 @@
#include "PeripheralPins.h"
#include "fsl_clock_config.h"
static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {0};
/* LPUART starts from index 1 */
static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0};
static uart_irq_handler irq_handler;
/* Array of UART peripheral base address. */
static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS;
@ -320,28 +321,28 @@ static int serial_is_enabled(uint32_t uart_index)
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
case 1:
clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG12_MASK) >> CCM_CCGR5_CG12_SHIFT;
break;
case 1:
case 2:
clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG14_MASK) >> CCM_CCGR0_CG14_SHIFT;
break;
case 2:
case 3:
clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG6_MASK) >> CCM_CCGR0_CG6_SHIFT;
break;
case 3:
case 4:
clock_enabled = (CCM->CCGR1 & CCM_CCGR1_CG12_MASK) >> CCM_CCGR1_CG12_SHIFT;
break;
case 4:
case 5:
clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG1_MASK) >> CCM_CCGR3_CG1_SHIFT;
break;
case 5:
case 6:
clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG3_MASK) >> CCM_CCGR3_CG3_SHIFT;
break;
case 6:
case 7:
clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG13_MASK) >> CCM_CCGR5_CG13_SHIFT;
break;
case 7:
case 8:
clock_enabled = (CCM->CCGR6 & CCM_CCGR6_CG7_MASK) >> CCM_CCGR6_CG7_SHIFT;
break;
default:
@ -357,7 +358,8 @@ bool serial_check_tx_ongoing()
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* The first LPUART instance number is 1 */
for (i = 1; i <= FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */

4
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/sleep.c
View File

@ -23,13 +23,9 @@ extern bool serial_check_tx_ongoing();
void hal_sleep(void)
{
vPortPRE_SLEEP_PROCESSING(kCLOCK_ModeWait);
__DSB();
__WFI();
__ISB();
vPortPOST_SLEEP_PROCESSING(kCLOCK_ModeWait);
}
void hal_deepsleep(void)

10
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c
View File

@ -50,18 +50,18 @@ void us_ticker_init(void)
{
/* Common for ticker/timer. */
uint32_t busClock;
/* Structure to initialize PIT. */
pit_config_t pitConfig;
us_ticker_setup_clock();
PIT_GetDefaultConfig(&pitConfig);
PIT_Init(PIT, &pitConfig);
busClock = us_ticker_get_clock();
/* Let the timer to count if re-init. */
if (!us_ticker_inited) {
/* Structure to initialize PIT. */
pit_config_t pitConfig;
PIT_GetDefaultConfig(&pitConfig);
PIT_Init(PIT, &pitConfig);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF);

2
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h
View File

@ -205,7 +205,7 @@ typedef enum {
I2C_SCL = A5,
I2C_SDA = A4,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;

292
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c
View File

@ -1,35 +1,10 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
@ -47,7 +22,7 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v4.1
product: Clocks v5.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
@ -56,6 +31,7 @@ board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "fsl_clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
@ -87,22 +63,34 @@ outputs:
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 37.5 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
@ -112,6 +100,8 @@ outputs:
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
@ -128,6 +118,8 @@ settings:
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
@ -136,6 +128,7 @@ settings:
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
- {id: CCM_ANALOG.PLL5.div, value: '40'}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
@ -147,14 +140,17 @@ sources:
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
@ -163,61 +159,70 @@ void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* Init System PLL. */
#ifndef SKIP_SYSCLK_INIT
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
#endif
/* Init Usb1 PLL. */
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
#endif
/* Enbale Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Enbale Video PLL output. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* Enable ENET PLL output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
CLOCK_DisableClock(kCLOCK_Xbar3);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
* unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
@ -225,72 +230,119 @@ void BOARD_BootClockRUN(void)
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
/* Set CSI_PODF. */
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
/* Set Csi clock source. */
CLOCK_SetMux(kCLOCK_CsiMux, 0);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 2);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Disable Flexio2 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio2);
/* Set FLEXIO2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
/* Set FLEXIO2_CLK_PODF. */
@ -299,9 +351,121 @@ void BOARD_BootClockRUN(void)
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
* unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
* well.*/
#ifndef SKIP_SYSCLK_INIT
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
/* Disable pfd offset. */
CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
* well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* DeInit Video PLL. */
CLOCK_DeinitVideoPll();
/* Bypass Video PLL. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
/* Set divider for Video PLL. */
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
/* Enable Video PLL output. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET =
(CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll();
/* Bypass Usb2 PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
/* Enable Usb2 PLL output. */
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
CCM_ANALOG->MISC1 =
(CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Tx clock source. */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

91
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h
View File

@ -1,35 +1,10 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
@ -38,9 +13,9 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
@ -65,17 +40,64 @@ void BOARD_InitBootClocks(void);
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_arm_pll_config_t g_armPllConfig_BOARD_BootClockRUN;
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t g_usb1PllConfig_BOARD_BootClockRUN;
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN;
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
@ -95,4 +117,3 @@ void BOARD_BootClockRUN(void);
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

43
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_phy.h"
@ -38,7 +12,7 @@
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
#define PHY_TIMEOUT_COUNT 100000
/*******************************************************************************
* Prototypes
@ -82,7 +56,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
counter--;
}
if (!counter)
@ -94,11 +68,10 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
if (result == kStatus_Success)
{
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
uint32_t data = 0;
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if ( result != kStatus_Success)
if (result != kStatus_Success)
{
return result;
}
@ -131,16 +104,16 @@ status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
if (result == kStatus_Success)
{
/* Check auto negotiation complete. */
while (counter --)
while (counter--)
{
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
if ( result == kStatus_Success)
if (result == kStatus_Success)
{
PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
{
/* Wait a moment for Phy status stable. */
for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay++)
{
__ASM("nop");
}

36
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
@ -70,16 +44,16 @@
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
@ -138,7 +112,7 @@ extern "C" {
*
* This function initialize the SMI interface and initialize PHY.
* The SMI is the MII management interface between PHY and MAC, which should be
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.

1011
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c
View File

File diff suppressed because it is too large Load Diff

188
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h
View File

@ -1,127 +1,100 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _LPM_H_
#define _LPM_H_
#include "fsl_clock.h"
#include <stdint.h>
/*******************************************************************************
* Definitions
******************************************************************************/
extern void vPortGPTIsr(void);
extern uint32_t g_savedPrimask;
#define vPortGptIsr GPT1_IRQHandler
#define CLOCK_SET_MUX(mux, value) \
\
do \
{ \
CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | \
(((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); \
while (CCM->CDHIPR != 0) \
{ \
} \
\
} \
while (0)
#define CLOCK_SET_DIV(divider, value) \
\
do \
{ \
CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | \
(((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); \
while (CCM->CDHIPR != 0) \
{ \
} \
\
} \
while (0)
#define CLOCK_CCM_HANDSHAKE_WAIT() \
\
do \
\
do \
{ \
while (CCM->CDHIPR != 0) \
{ \
} \
\
} \
while (0)
\
} while (0)
#define LPM_DELAY(value) \
\
do \
{ \
for (uint32_t i = 0; i < 5 * value; i++) \
{ \
__NOP(); \
} \
\
} \
while (0)
#define ROM_CODE_ENTRY_ADDR (0x200000U)
/*! @name Time sensitive region */
/* @{ */
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) __ramfunc func
#elif(defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#elif defined(__MCUXPRESSO)
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section(".ramfunc.$SRAM_ITC"))) func
#elif(defined(__GNUC__))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#define LPM_EnterCritical() \
\
do \
{ \
g_savedPrimask = DisableGlobalIRQ(); \
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \
\
} while (0)
#define LPM_ExitCritical() \
\
do \
{ \
EnableGlobalIRQ(g_savedPrimask); \
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; \
\
} while (0)
#else
#error Toolchain not supported.
#endif /* defined(__ICCARM__) */
#else
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#elif(defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#elif(defined(__MCUXPRESSO))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#elif(defined(__GNUC__))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#else
#error Toolchain not supported.
#define LPM_EnterCritical()
#define LPM_ExitCritical()
#endif
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
/* Power mode definition of low power management.
* Waken up duration Off > Dsm > Idle > Wait > Run.
*/
typedef enum _lpm_power_mode
{
LPM_PowerModeOverRun = 0, /* Over RUN mode, CPU won't stop running */
LPM_PowerModeFullRun, /* Full RUN mode, CPU won't stop running */
LPM_PowerModeLowSpeedRun,
LPM_PowerModeLowPowerRun,
LPM_PowerModeRunEnd = LPM_PowerModeLowPowerRun,
/* In system wait mode, cpu clock is gated.
* All peripheral can remain active, clock gating decided by CCGR setting.
* DRAM enters auto-refresh mode when there is no access.
*/
LPM_PowerModeSysIdle, /* System WAIT mode, also system low speed idle */
/* In low power idle mode, all PLL/PFD is off, cpu power is off.
* Analog modules running in low power mode.
* All high-speed peripherals are power gated
* Low speed peripherals can remain running at low frequency
* DRAM in self-refresh.
*/
LPM_PowerModeLPIdle, /* Low Power Idle mode */
/* In deep sleep mode, all PLL/PFD is off, XTAL is off, cpu power is off.
* All clocks are shut off except 32K RTC clock
* All high-speed peripherals are power gated
* Low speed peripherals are clock gated
* DRAM in self-refresh.
* If RTOS is used, systick will be disabled in DSM
*/
LPM_PowerModeSuspend, /* Deep Sleep mode, suspend. */
LPM_PowerModeSNVS, /* Power off mode, or shutdown mode */
LPM_PowerModeEnd = LPM_PowerModeSNVS
} lpm_power_mode_t;
/*******************************************************************************
* API
@ -131,8 +104,8 @@ do \
extern "C" {
#endif /* __cplusplus*/
AT_QUICKACCESS_SECTION_CODE(void LPM_SwitchFlexspiClock(clock_mode_t powermode));
AT_QUICKACCESS_SECTION_CODE(void LPM_RestoreFlexspiClock(void));
AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value));
AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_DIV(clock_div_t divider, uint32_t value));
/* Initialize the Low Power Management */
bool LPM_Init(void);
@ -146,6 +119,25 @@ void LPM_EnableWakeupSource(uint32_t irq);
/* Disable wakeup source in low power mode */
void LPM_DisableWakeupSource(uint32_t irq);
void ClockSelectXtalOsc(void);
void ClockSelectRcOsc(void);
void LPM_EnableWakeupSource(uint32_t irq);
void LPM_DisableWakeupSource(uint32_t irq);
void LPM_PreEnterWaitMode(void);
void LPM_PostExitWaitMode(void);
void LPM_PreEnterStopMode(void);
void LPM_PostExitStopMode(void);
void LPM_OverDriveRun(void);
void LPM_FullSpeedRun(void);
void LPM_LowSpeedRun(void);
void LPM_LowPowerRun(void);
void LPM_EnterSystemIdle(void);
void LPM_ExitSystemIdle(void);
void LPM_EnterLowPowerIdle(void);
void LPM_ExitLowPowerIdle(void);
void LPM_EnterSuspend(void);
void LPM_EnterSNVS(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/

87
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c
View File

@ -17,6 +17,8 @@
#include "fsl_clock_config.h"
#include "fsl_clock.h"
#include "fsl_xbara.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "lpm.h"
#define LPSPI_CLOCK_SOURCE_DIVIDER (7U)
@ -40,10 +42,10 @@ void BOARD_ConfigMPU(void)
/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
* API in core_cm7.h.
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Use MACROS defined in mpu_armv7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
@ -60,26 +62,22 @@ void BOARD_ConfigMPU(void)
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h.
*/
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 2 setting */
/* Region 2 setting */
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
#else
/* Setting Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
#endif
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
@ -98,9 +96,9 @@ void BOARD_ConfigMPU(void)
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* The define sets the cacheable memory to shareable,
* this suggestion is referred from chapter 2.2.1 Memory regions,
* types and attributes in Cortex-M7 Devices, Generic User Guide */
/* The define sets the cacheable memory to shareable,
* this suggestion is referred from chapter 2.2.1 Memory regions,
* types and attributes in Cortex-M7 Devices, Generic User Guide */
#if defined(SDRAM_IS_SHAREABLE)
/* Region 7 setting: Memory with Normal type, shareable, outer/inner write back, write/read allocate */
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
@ -125,38 +123,44 @@ void BOARD_ConfigMPU(void)
SCB_EnableICache();
}
#if defined(TOOLCHAIN_GCC_ARM)
extern uint32_t __ram_function_flash_start[];
#define __RAM_FUNCTION_FLASH_START __ram_function_flash_start
extern uint32_t __ram_function_ram_start[];
#define __RAM_FUNCTION_RAM_START __ram_function_ram_start
extern uint32_t __ram_function_size[];
#define __RAM_FUNCTION_SIZE __ram_function_size
void Board_CopyToRam()
{
unsigned char *source;
unsigned char *destiny;
unsigned int size;
void BOARD_Init_PMIC_STBY_REQ(void) {
CLOCK_EnableClock(kCLOCK_IomuxcSnvs); /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */
source = (unsigned char *)(__RAM_FUNCTION_FLASH_START);
destiny = (unsigned char *)(__RAM_FUNCTION_RAM_START);
size = (unsigned long)(__RAM_FUNCTION_SIZE);
/* GPIO configuration of PERI_PWREN on PMIC_STBY_REQ (pin L7) */
gpio_pin_config_t PERI_PWREN_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on PMIC_STBY_REQ (pin L7) */
GPIO_PinInit(GPIO5, 2U, &PERI_PWREN_config);
while (size--)
{
*destiny++ = *source++;
}
IOMUXC_SetPinMux(
IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ is configured as GPIO5_IO02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ PAD functional properties : */
0x10B0U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
}
#endif
// called before main
void mbed_sdk_init()
{
BOARD_ConfigMPU();
BOARD_BootClockRUN();
#if defined(TOOLCHAIN_GCC_ARM)
Board_CopyToRam();
#endif
/* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is
* connected to LCD power switch circuit. So it needs to be configured as a low-level output GPIO to reduce the
* current. */
BOARD_Init_PMIC_STBY_REQ();
LPM_Init();
}
@ -187,16 +191,15 @@ uint32_t us_ticker_get_clock()
void serial_setup_clock(void)
{
/* We assume default PLL and divider settings */
/* Configure UART divider to default */
CLOCK_SetMux(kCLOCK_UartMux, 1); /* Set UART source to OSC 24M */
CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
}
uint32_t serial_get_clock(void)
{
uint32_t clock_freq;
/* We assume default PLL and divider settings, and the only variable
* from application is use PLL3 source or OSC source
*/
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ {
clock_freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
} else {

609
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c Normal file
View File

@ -0,0 +1,609 @@
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "specific.h"
#include "fsl_common.h"
#include "fsl_clock.h"
#include "lpm.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Code
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_PowerMode = {
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_PowerMode = {
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_PowerMode = {
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode));
#define NUMBER_OF_CCM_GATE_REGS 7
static uint32_t clock_gate_values[NUMBER_OF_CCM_GATE_REGS];
void SwitchSystemClocks(lpm_power_mode_t power_mode)
{
#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
{
}
FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
/* Disable clock gate of flexspi. */
CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK);
#endif
switch (power_mode)
{
case LPM_PowerModeOverRun:
CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0
/* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */
//CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1);
CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
//CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL
CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK
break;
case LPM_PowerModeFullRun:
CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0
/* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */
CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1);
CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL
CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK
break;
case LPM_PowerModeLowSpeedRun:
case LPM_PowerModeSysIdle:
CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode
CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2
/* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */
CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
CLOCK_SET_DIV(kCLOCK_AhbDiv, 3);
CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // Switch PRE_PERIPH_CLK to SYS PLL
CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // Switch PERIPH_CLK to PRE_PERIPH_CLK
break;
case LPM_PowerModeLowPowerRun:
case LPM_PowerModeLPIdle:
CLOCK_SET_DIV(kCLOCK_PeriphClk2Div, 0);
CLOCK_SET_MUX(kCLOCK_PeriphClk2Mux, 1); // PERIPH_CLK2 mux to OSC
CLOCK_SET_MUX(kCLOCK_PeriphMux, 1); // PERIPH_CLK mux to PERIPH_CLK2
CLOCK_SET_DIV(kCLOCK_SemcDiv, 0);
CLOCK_SET_MUX(kCLOCK_SemcMux, 0); // SEMC mux to PERIPH_CLK
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre
/* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */
//CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
CLOCK_SET_DIV(kCLOCK_IpgDiv, 1);
CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
//CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
break;
default:
break;
}
#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Enable clock gate of flexspi. */
CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);
if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode))
{
FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19);
}
else
{
FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15);
}
FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
{
}
while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
{
}
#endif
}
void ClockSetToOverDriveRun(void)
{
// CORE CLK mux to 24M before reconfigure PLLs
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLowPowerRun);
LPM_ExitCritical();
//ClockSelectXtalOsc();
/* Init ARM PLL */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
CLOCK_InitArmPll(&armPllConfig_PowerMode);
/* Init SYS PLL*/
CLOCK_InitSysPll(&sysPllConfig_PowerMode);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
/* Init USB1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
/* Init USB2 PLL*/
CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK;
CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK;
while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
/* Init AUDIO PLL */
CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
/* Init VIDEO PLL */
CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
/* Init ENET PLL */
CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK;
CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeOverRun);
LPM_ExitCritical();
}
void ClockSetToFullSpeedRun(void)
{
// CORE CLK mux to 24M before reconfigure PLLs
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLowPowerRun);
LPM_ExitCritical();
ClockSelectXtalOsc();
/* Init ARM PLL */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
CLOCK_InitArmPll(&armPllConfig_PowerMode);
/* Init SYS PLL. */
CLOCK_InitSysPll(&sysPllConfig_PowerMode);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
/* Init USB1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
/* Init USB2 PLL*/
CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK;
CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK;
while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
/* Init AUDIO PLL */
CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
/* Init VIDEO PLL */
CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
/* Init ENET PLL */
CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK;
CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
{
}
CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeFullRun);
LPM_ExitCritical();
}
void ClockSetToLowSpeedRun(void)
{
// CORE CLK mux to 24M before reconfigure PLLs
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLowPowerRun);
LPM_ExitCritical();
ClockSelectXtalOsc();
/* Deinit ARM PLL */
CLOCK_DeinitArmPll();
/* Init SYS PLL */
CLOCK_InitSysPll(&sysPllConfig_PowerMode);
/* Deinit SYS PLL PFD 0 1 3 */
CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
/* Deinit USB1 PLL */
CLOCK_DeinitUsb1Pll();
/* Deinit USB1 PLL PFD 0 1 2 3 */
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
/* Deinit USB2 PLL */
CLOCK_DeinitUsb2Pll();
/* Deinit AUDIO PLL */
CLOCK_DeinitAudioPll();
/* Deinit VIDEO PLL */
CLOCK_DeinitVideoPll();
/* Deinit ENET PLL */
CLOCK_DeinitEnetPll();
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLowSpeedRun);
LPM_ExitCritical();
}
void ClockSetToLowPowerRun(void)
{
// CORE CLK mux to 24M before reconfigure PLLs
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLowPowerRun);
LPM_ExitCritical();
ClockSelectRcOsc();
/* Deinit ARM PLL */
CLOCK_DeinitArmPll();
/* Deinit SYS PLL */
CLOCK_DeinitSysPll();
/* Deinit SYS PLL PFD 0 1 2 3 */
CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
CLOCK_DeinitSysPfd(kCLOCK_Pfd2);
CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
/* Power Down USB1 PLL */
CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK;
CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK;
CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK;
/* Deinit USB1 PLL PFD 0 1 2 3 */
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
/* Deinit USB2 PLL */
CLOCK_DeinitUsb2Pll();
/* Deinit AUDIO PLL */
CLOCK_DeinitAudioPll();
/* Deinit VIDEO PLL */
CLOCK_DeinitVideoPll();
/* Deinit ENET PLL */
CLOCK_DeinitEnetPll();
}
void ClockSetToSystemIdle(void)
{
// CORE CLK mux to 24M before reconfigure PLLs
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLowPowerRun);
LPM_ExitCritical();
ClockSelectXtalOsc();
/* Deinit ARM PLL */
CLOCK_DeinitArmPll();
/* Init SYS PLL */
CLOCK_InitSysPll(&sysPllConfig_PowerMode);
/* Deinit SYS PLL PFD 0 1 3 */
CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
/* Deinit USB1 PLL */
CLOCK_DeinitUsb1Pll();
/* Deinit USB1 PLL PFD 0 1 2 3 */
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
/* Deinit USB2 PLL */
CLOCK_DeinitUsb2Pll();
/* Deinit AUDIO PLL */
CLOCK_DeinitAudioPll();
/* Deinit VIDEO PLL */
CLOCK_DeinitVideoPll();
/* Deinit ENET PLL */
CLOCK_DeinitEnetPll();
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeSysIdle);
LPM_ExitCritical();
}
void ClockSetToLowPowerIdle(void)
{
// CORE CLK mux to 24M before reconfigure PLLs
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLowPowerRun);
LPM_ExitCritical();
//ClockSelectRcOsc();
/* Deinit ARM PLL */
CLOCK_DeinitArmPll();
/* Deinit SYS PLL */
CLOCK_DeinitSysPll();
/* Deinit SYS PLL PFD 0 1 2 3 */
CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
CLOCK_DeinitSysPfd(kCLOCK_Pfd2);
CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
/* Deinit USB1 PLL */
CLOCK_DeinitUsb1Pll();
/* Deinit USB1 PLL PFD 0 1 2 3 */
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
/* Deinit USB2 PLL */
CLOCK_DeinitUsb2Pll();
/* Deinit AUDIO PLL */
CLOCK_DeinitAudioPll();
/* Deinit VIDEO PLL */
CLOCK_DeinitVideoPll();
/* Deinit ENET PLL */
CLOCK_DeinitEnetPll();
LPM_EnterCritical();
SwitchSystemClocks(LPM_PowerModeLPIdle);
LPM_ExitCritical();
}
void SetLowPowerClockGate(void)
{
/* Save of the clock gate registers */
clock_gate_values[0] = CCM->CCGR0;
clock_gate_values[1] = CCM->CCGR1;
clock_gate_values[2] = CCM->CCGR2;
clock_gate_values[3] = CCM->CCGR3;
clock_gate_values[4] = CCM->CCGR4;
clock_gate_values[5] = CCM->CCGR5;
clock_gate_values[6] = CCM->CCGR6;
/* Set low power gate values */
CCM->CCGR0 = CCM_CCGR0_CG0(1) | CCM_CCGR0_CG1(1) | CCM_CCGR0_CG3(3) | CCM_CCGR0_CG11(1) | CCM_CCGR0_CG12(1);
CCM->CCGR1 = CCM_CCGR1_CG9(3) | CCM_CCGR1_CG10(1) | CCM_CCGR1_CG13(1) | CCM_CCGR1_CG14(1) | CCM_CCGR1_CG15(1);
CCM->CCGR2 = CCM_CCGR2_CG2(1) | CCM_CCGR2_CG8(1) | CCM_CCGR2_CG9(1) | CCM_CCGR2_CG10(1);
CCM->CCGR3 = CCM_CCGR3_CG2(1) | CCM_CCGR3_CG4(1) | CCM_CCGR3_CG9(1) | CCM_CCGR3_CG14(3) | CCM_CCGR3_CG15(1);
CCM->CCGR4 =
CCM_CCGR4_CG1(1) | CCM_CCGR4_CG2(1) | CCM_CCGR4_CG4(1) | CCM_CCGR4_CG5(1) | CCM_CCGR4_CG6(1) | CCM_CCGR4_CG7(1);
CCM->CCGR5 = CCM_CCGR5_CG0(1) | CCM_CCGR5_CG1(1) | CCM_CCGR5_CG4(1) | CCM_CCGR5_CG6(1) | CCM_CCGR5_CG12(1) |
CCM_CCGR5_CG14(1) | CCM_CCGR5_CG15(1);
/* We can enable DCDC when need to config it and close it after configuration */
CCM->CCGR6 = CCM_CCGR6_CG3(1) | CCM_CCGR6_CG4(1) | CCM_CCGR6_CG5(1) | CCM_CCGR6_CG9(1) | CCM_CCGR6_CG10(1) |
CCM_CCGR6_CG11(1);
}
void SetRestoreClockGate(void)
{
CCM->CCGR0 = clock_gate_values[0];
CCM->CCGR1 = clock_gate_values[1];
CCM->CCGR2 = clock_gate_values[2];
CCM->CCGR3 = clock_gate_values[3];
CCM->CCGR4 = clock_gate_values[4];
CCM->CCGR5 = clock_gate_values[5];
CCM->CCGR6 = clock_gate_values[6];
}
void PowerDownUSBPHY(void)
{
USBPHY1->CTRL = 0xFFFFFFFF;
USBPHY2->CTRL = 0xFFFFFFFF;
}
void ConfigUartRxPinToGpio(void)
{
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2) | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK);
}
void ReConfigUartRxPin(void)
{
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_SW_PAD_CTL_PAD_SPEED(2));
}
#define GPR4_STOP_REQ_BITS \
(IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK | \
IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK | \
IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
#define GPR4_STOP_ACK_BITS \
(IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK | \
IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK | \
IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
#define GPR7_STOP_REQ_BITS \
(IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK | \
IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK | \
IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK | \
IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK | \
IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK | \
IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK | \
IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK | \
IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
#define GPR7_STOP_ACK_BITS \
(IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK | \
IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK | \
IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK | \
IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK | \
IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK | \
IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK | \
IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK | \
IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
#define GPR8_DOZE_BITS \
(IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK | \
IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK | \
IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK | \
IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK | \
IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK | \
IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK | \
IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK | \
IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
#define GPR8_STOP_MODE_BITS \
(IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK | \
IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK | \
IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK | \
IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK | \
IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK | \
IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK | \
IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK | \
IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
#define GPR12_DOZE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
#define GPR12_STOP_MODE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
void PeripheralEnterDozeMode(void)
{
IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS;
IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS;
}
void PeripheralExitDozeMode(void)
{
IOMUXC_GPR->GPR8 = 0x00000000;
IOMUXC_GPR->GPR12 = 0x00000000;
}
void PeripheralEnterStopMode(void)
{
IOMUXC_GPR->GPR4 = IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK;
while ((IOMUXC_GPR->GPR4 & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) != IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
{
}
IOMUXC_GPR->GPR4 = GPR4_STOP_REQ_BITS;
IOMUXC_GPR->GPR7 = GPR7_STOP_REQ_BITS;
IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS | GPR8_STOP_MODE_BITS;
IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS | GPR12_STOP_MODE_BITS;
while ((IOMUXC_GPR->GPR4 & GPR4_STOP_ACK_BITS) != GPR4_STOP_ACK_BITS)
{
}
while ((IOMUXC_GPR->GPR7 & GPR7_STOP_ACK_BITS) != GPR7_STOP_ACK_BITS)
{
}
}

49
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.h Normal file
View File

@ -0,0 +1,49 @@
/*
* Copyright 2018-2019 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _SPECIFIC_H_
#define _SPECIFIC_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define FLEXSPI_INST FLEXSPI
#define HAS_WAKEUP_PIN (1)
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
void ClockSetToOverDriveRun(void);
void ClockSetToFullSpeedRun(void);
void ClockSetToLowSpeedRun(void);
void ClockSetToLowPowerRun(void);
void ClockSetToSystemIdle(void);
void ClockSetToLowPowerIdle(void);
void SetLowPowerClockGate(void);
void SetRestoreClockGate(void);
void PowerDownUSBPHY(void);
void ConfigUartRxPinToGpio(void);
void ReConfigUartRxPin(void);
void PeripheralEnterDozeMode(void);
void PeripheralExitDozeMode(void);
void PeripheralEnterStopMode(void);
void APP_PrintRunFrequency(int32_t run_freq_only);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _SPECIFIC_H_ */

33
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c
View File

@ -1,38 +1,17 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkbimxrt1050_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/

41
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h
View File

@ -1,42 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this
* list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice,
* this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
@ -46,6 +13,12 @@
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0

1406
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c
View File

File diff suppressed because it is too large Load Diff

49
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h
View File

@ -1,47 +1,32 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__
#define __EVKBIMXRT1050_DCD_SDRAM_INIT__
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef __EVKBIMXRT1050_SDRAM_INI_DCD__
#define __EVKBIMXRT1050_SDRAM_INI_DCD__
#include <stdint.h>
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_VERSION (0x40)
#define DCD_ARRAY_SIZE 1
#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */
#endif /* __EVKBIMXRT1050_SDRAM_INI_DCD__ */

15148
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h
View File

File diff suppressed because it is too large Load Diff

111
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h
View File

@ -1,44 +1,16 @@
/*
** ###################################################################
** Version: rev. 0.1, 2017-01-10
** Build: b180509
** Version: rev. 1.1, 2018-11-16
** Build: b190319
**
** Abstract:
** Chip specific module features.
**
** The Clear BSD License
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2019 NXP
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted (subject to the limitations in the
** disclaimer below) provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright
** notice, this list of conditions and the following disclaimer.
**
** * Redistributions in binary form must reproduce the above copyright
** notice, this list of conditions and the following disclaimer in the
** documentation and/or other materials provided with the distribution.
**
** * Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from
** this software without specific prior written permission.
**
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -46,6 +18,12 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update feature files to align with IMXRT1050RM Rev.1.
**
** ###################################################################
*/
@ -166,6 +144,8 @@
#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
/* @brief Remove ALT Clock selection feature. */
#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
/* @brief Conversion control count (related to number of registers HCn and Rn). */
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8)
/* ADC_ETC module features */
@ -185,20 +165,34 @@
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
/* @brief Has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
/* @brief Instance has extended bit timing register (register CBT). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
/* @brief Has extra MB interrupt or common one. */
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
@ -229,6 +223,12 @@
#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
/* @brief Channel IRQ entry shared offset. */
#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
/* @brief If 8 bytes transfer supported. */
#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
/* @brief If 16 bytes transfer supported. */
#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
/* DMAMUX module features */
@ -256,6 +256,13 @@
/* @brief Has Additional 1588 Timer Channel Interrupt. */
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
/* EWM module features */
/* @brief Has clock select (register CLKCTRL). */
#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
/* @brief Has clock prescaler (register CLKPRESCALER). */
#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
/* FLEXIO module features */
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
@ -278,11 +285,13 @@
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
/* @brief Reset value of the FLEXIO_PARAM register */
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
/* @brief Flexio DMA request base channel */
#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
/* FLEXRAM module features */
/* @brief Bank size */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
/* @brief Total Bank numbers */
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
@ -418,7 +427,7 @@
/* @brief Lowest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
/* @brief Highest interrupt request number. */
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151)
/* OCOTP module features */
@ -488,7 +497,10 @@
/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
#define FSL_FEATURE_SAI_FIFO_COUNT (32)
/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
#define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
(((x) == SAI1) ? (4) : \
(((x) == SAI2) ? (1) : \
(((x) == SAI3) ? (1) : (-1))))
/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
@ -507,8 +519,23 @@
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
/* @brief Has register of MCR. */
#define FSL_FEATURE_SAI_HAS_MCR (0)
/* @brief Has bit field MICS of the MCR register. */
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
/* @brief Has register of MDR */
#define FSL_FEATURE_SAI_HAS_MDR (0)
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
/* SEMC module features */
/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1)
/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */
#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1)
/* SNVS module features */
@ -602,14 +629,8 @@
/* XBARA module features */
/* @brief DMA_CH_MUX_REQ_30. */
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1)
/* @brief DMA_CH_MUX_REQ_31. */
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1)
/* @brief DMA_CH_MUX_REQ_94. */
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1)
/* @brief DMA_CH_MUX_REQ_95. */
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
/* @brief Number of interrupt requests. */
#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4)
#endif /* _MIMXRT1052_FEATURES_H_ */

38
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct
View File

@ -8,45 +8,17 @@
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 0.1, 2017-01-10
** Build: b180606
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** The Clear BSD License
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted (subject to the limitations in the
** disclaimer below) provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright
** notice, this list of conditions and the following disclaimer.
**
** * Redistributions in binary form must reproduce the above copyright
** notice, this list of conditions and the following disclaimer in the
** documentation and/or other materials provided with the distribution.
**
** * Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from
** this software without specific prior written permission.
**
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -146,8 +118,8 @@ LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start {
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ram_text m_text2_start UNINIT m_text2_size { ; load address = execution address
* (RamFunction)
RW_m_ram_text m_text2_start m_text2_size {
* (CodeQuickAccess)
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)

94
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S
View File

@ -2,44 +2,16 @@
; * @file: startup_MIMXRT1052.s
; * @purpose: CMSIS Cortex-M7 Core Device Startup File
; * MIMXRT1052
; * @version: 0.1
; * @date: 2017-1-10
; * @build: b180509
; * @version: 1.2
; * @date: 2018-11-27
; * @build: b190124
; * -------------------------------------------------------------------------
; *
; * The Clear BSD License
; * Copyright 1997-2016 Freescale Semiconductor, Inc.
; * Copyright 2016-2018 NXP
; * Copyright 2016-2019 NXP
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted (subject to the limitations in the
; * disclaimer below) provided that the following conditions are met:
; *
; * * Redistributions of source code must retain the above copyright
; * notice, this list of conditions and the following disclaimer.
; *
; * * Redistributions in binary form must reproduce the above copyright
; * notice, this list of conditions and the following disclaimer in the
; * documentation and/or other materials provided with the distribution.
; *
; * * Neither the name of the copyright holder nor the names of its
; * contributors may be used to endorse or promote products derived from
; * this software without specific prior written permission.
; *
; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
; * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
; * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
; * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
; * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
; * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
; * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
; * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; * SPDX-License-Identifier: BSD-3-Clause
; *
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
@ -137,10 +109,10 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD SAI3_RX_IRQHandler ;SAI3 interrupt
DCD SAI3_TX_IRQHandler ;SAI3 interrupt
DCD SPDIF_IRQHandler ;SPDIF interrupt
DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt
DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt
DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt
DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt
DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt
DCD Reserved78_IRQHandler ;Reserved interrupt
DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt
DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt
DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
@ -228,14 +200,14 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt
DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt
DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt
DCD Reserved168_IRQHandler ;Reserved interrupt
DCD Reserved169_IRQHandler ;Reserved interrupt
DCD Reserved170_IRQHandler ;Reserved interrupt
DCD Reserved171_IRQHandler ;Reserved interrupt
DCD Reserved172_IRQHandler ;Reserved interrupt
DCD Reserved173_IRQHandler ;Reserved interrupt
DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt
DCD NMI_WAKEUP_IRQHandler ;NMI wake up
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
@ -781,10 +753,10 @@ Default_Handler\
EXPORT SAI3_RX_DriverIRQHandler [WEAK]
EXPORT SAI3_TX_DriverIRQHandler [WEAK]
EXPORT SPDIF_DriverIRQHandler [WEAK]
EXPORT ANATOP_EVENT0_IRQHandler [WEAK]
EXPORT ANATOP_EVENT1_IRQHandler [WEAK]
EXPORT ANATOP_TAMP_LOW_HIGH_IRQHandler [WEAK]
EXPORT ANATOP_TEMP_PANIC_IRQHandler [WEAK]
EXPORT PMU_EVENT_IRQHandler [WEAK]
EXPORT Reserved78_IRQHandler [WEAK]
EXPORT TEMP_LOW_HIGH_IRQHandler [WEAK]
EXPORT TEMP_PANIC_IRQHandler [WEAK]
EXPORT USB_PHY1_IRQHandler [WEAK]
EXPORT USB_PHY2_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
@ -872,14 +844,6 @@ Default_Handler\
EXPORT PWM4_2_IRQHandler [WEAK]
EXPORT PWM4_3_IRQHandler [WEAK]
EXPORT PWM4_FAULT_IRQHandler [WEAK]
EXPORT Reserved168_IRQHandler [WEAK]
EXPORT Reserved169_IRQHandler [WEAK]
EXPORT Reserved170_IRQHandler [WEAK]
EXPORT Reserved171_IRQHandler [WEAK]
EXPORT Reserved172_IRQHandler [WEAK]
EXPORT Reserved173_IRQHandler [WEAK]
EXPORT SJC_ARM_DEBUG_IRQHandler [WEAK]
EXPORT NMI_WAKEUP_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
@ -942,10 +906,10 @@ SAI2_DriverIRQHandler
SAI3_RX_DriverIRQHandler
SAI3_TX_DriverIRQHandler
SPDIF_DriverIRQHandler
ANATOP_EVENT0_IRQHandler
ANATOP_EVENT1_IRQHandler
ANATOP_TAMP_LOW_HIGH_IRQHandler
ANATOP_TEMP_PANIC_IRQHandler
PMU_EVENT_IRQHandler
Reserved78_IRQHandler
TEMP_LOW_HIGH_IRQHandler
TEMP_PANIC_IRQHandler
USB_PHY1_IRQHandler
USB_PHY2_IRQHandler
ADC1_IRQHandler
@ -1033,14 +997,6 @@ PWM4_1_IRQHandler
PWM4_2_IRQHandler
PWM4_3_IRQHandler
PWM4_FAULT_IRQHandler
Reserved168_IRQHandler
Reserved169_IRQHandler
Reserved170_IRQHandler
Reserved171_IRQHandler
Reserved172_IRQHandler
Reserved173_IRQHandler
SJC_ARM_DEBUG_IRQHandler
NMI_WAKEUP_IRQHandler
DefaultISR
LDR R0, =DefaultISR
BX R0

41
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld
View File

@ -7,45 +7,17 @@
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 0.1, 2017-01-10
** Build: b180509
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the GNU C Compiler
**
** The Clear BSD License
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted (subject to the limitations in the
** disclaimer below) provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright
** notice, this list of conditions and the following disclaimer.
**
** * Redistributions in binary form must reproduce the above copyright
** notice, this list of conditions and the following disclaimer in the
** documentation and/or other materials provided with the distribution.
**
** * Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from
** this software without specific prior written permission.
**
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -227,16 +199,15 @@ SECTIONS
. = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
.ram_function : AT(__ram_function_flash_start)
{
. = ALIGN(32);
__ram_function_ram_start = .;
*(RamFunction)
__ram_function_start__ = .;
*(CodeQuickAccess)
. = ALIGN(128);
__ram_function_ram_end = .;
__ram_function_end__ = .;
} > m_text2
__ram_function_size = SIZEOF(.ram_function);

152
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S
View File

@ -2,44 +2,16 @@
/* @file: startup_MIMXRT1052.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1052 */
/* @version: 0.1 */
/* @date: 2017-1-10 */
/* @build: b180509 */
/* @version: 1.2 */
/* @date: 2018-11-27 */
/* @build: b190124 */
/* ------------------------------------------------------------------------- */
/* */
/* The Clear BSD License */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* Copyright 2016-2019 NXP */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted (subject to the limitations in the */
/* disclaimer below) provided that the following conditions are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of the copyright holder nor the names of its */
/* contributors may be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE */
/* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT */
/* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED */
/* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */
/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */
/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */
/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */
/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN */
/* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
@ -129,10 +101,10 @@ __isr_vector:
.long SAI3_RX_IRQHandler /* SAI3 interrupt*/
.long SAI3_TX_IRQHandler /* SAI3 interrupt*/
.long SPDIF_IRQHandler /* SPDIF interrupt*/
.long ANATOP_EVENT0_IRQHandler /* ANATOP interrupt*/
.long ANATOP_EVENT1_IRQHandler /* ANATOP interrupt*/
.long ANATOP_TAMP_LOW_HIGH_IRQHandler /* ANATOP interrupt*/
.long ANATOP_TEMP_PANIC_IRQHandler /* ANATOP interrupt*/
.long PMU_EVENT_IRQHandler /* Brown-out event interrupt*/
.long Reserved78_IRQHandler /* Reserved interrupt*/
.long TEMP_LOW_HIGH_IRQHandler /* TempSensor low/high interrupt*/
.long TEMP_PANIC_IRQHandler /* TempSensor panic interrupt*/
.long USB_PHY1_IRQHandler /* USBPHY (UTMI0), Interrupt*/
.long USB_PHY2_IRQHandler /* USBPHY (UTMI0), Interrupt*/
.long ADC1_IRQHandler /* ADC1 interrupt*/
@ -220,14 +192,14 @@ __isr_vector:
.long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/
.long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/
.long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/
.long Reserved168_IRQHandler /* Reserved interrupt*/
.long Reserved169_IRQHandler /* Reserved interrupt*/
.long Reserved170_IRQHandler /* Reserved interrupt*/
.long Reserved171_IRQHandler /* Reserved interrupt*/
.long Reserved172_IRQHandler /* Reserved interrupt*/
.long Reserved173_IRQHandler /* Reserved interrupt*/
.long SJC_ARM_DEBUG_IRQHandler /* SJC ARM debug interrupt*/
.long NMI_WAKEUP_IRQHandler /* NMI wake up*/
.long DefaultISR /* 168*/
.long DefaultISR /* 169*/
.long DefaultISR /* 170*/
.long DefaultISR /* 171*/
.long DefaultISR /* 172*/
.long DefaultISR /* 173*/
.long DefaultISR /* 174*/
.long DefaultISR /* 175*/
.long DefaultISR /* 176*/
.long DefaultISR /* 177*/
.long DefaultISR /* 178*/
@ -339,23 +311,17 @@ Reset_Handler:
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* __ram_function_start__/__ram_function_end__ : ramfunction region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
#ifdef __PERFORMANCE_IMPLEMENTATION
/* Here are two copies of loop implementations. First one favors performance
* and the second one favors code size. Default uses the second one.
* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
subs r3, r2
ble .LC1
.LC0:
@ -364,18 +330,45 @@ Reset_Handler:
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#if 1
.LC2:
#else /* code size implemenation */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#else
blt .LC0
#endif
#ifdef __STARTUP_INITIALIZE_RAMFUNCTION
ldr r2, =__ram_function_start__
ldr r3, =__ram_function_end__
#ifdef __PERFORMANCE_IMPLEMENTATION
/* Here are two copies of loop implementations. First one favors performance
* and the second one favors code size. Default uses the second one.
* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
subs r3, r2
ble .LC_ramfunc_copy_end
.LC_ramfunc_copy_start:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC_ramfunc_copy_start
.LC_ramfunc_copy_end:
#else /* code size implemenation */
.LC_ramfunc_copy_start:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC_ramfunc_copy_start
#endif
#endif /* __STARTUP_INITIALIZE_RAMFUNCTION */
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#ifdef __PERFORMANCE_IMPLEMENTATION
/* Here are two copies of loop implementations. First one favors performance
* and the second one favors code size. Default uses the second one.
* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
subs r3, r2
ble .LC3
.LC2:
@ -384,6 +377,13 @@ Reset_Handler:
str r0, [r2, r3]
bgt .LC2
.LC3:
#else /* code size implemenation */
.LC2:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#endif
/* zero inited ncache section initialization */
ldr r3, =__noncachedata_end__
@ -484,15 +484,6 @@ SysTick_Handler:
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak NMI_WAKEUP_IRQHandler
.type NMI_WAKEUP_IRQHandler, %function
NMI_WAKEUP_IRQHandler:
ldr r0,=NMI_WAKEUP_IRQHandler
bx r0
.size NMI_WAKEUP_IRQHandler, . - NMI_WAKEUP_IRQHandler
.align 1
.thumb_func
.weak DMA0_DMA16_IRQHandler
@ -991,10 +982,10 @@ ENET_1588_Timer_IRQHandler:
def_irq_handler SAI3_RX_DriverIRQHandler
def_irq_handler SAI3_TX_DriverIRQHandler
def_irq_handler SPDIF_DriverIRQHandler
def_irq_handler ANATOP_EVENT0_IRQHandler
def_irq_handler ANATOP_EVENT1_IRQHandler
def_irq_handler ANATOP_TAMP_LOW_HIGH_IRQHandler
def_irq_handler ANATOP_TEMP_PANIC_IRQHandler
def_irq_handler PMU_EVENT_IRQHandler
def_irq_handler Reserved78_IRQHandler
def_irq_handler TEMP_LOW_HIGH_IRQHandler
def_irq_handler TEMP_PANIC_IRQHandler
def_irq_handler USB_PHY1_IRQHandler
def_irq_handler USB_PHY2_IRQHandler
def_irq_handler ADC1_IRQHandler
@ -1082,12 +1073,5 @@ ENET_1588_Timer_IRQHandler:
def_irq_handler PWM4_2_IRQHandler
def_irq_handler PWM4_3_IRQHandler
def_irq_handler PWM4_FAULT_IRQHandler
def_irq_handler Reserved168_IRQHandler
def_irq_handler Reserved169_IRQHandler
def_irq_handler Reserved170_IRQHandler
def_irq_handler Reserved171_IRQHandler
def_irq_handler Reserved172_IRQHandler
def_irq_handler Reserved173_IRQHandler
def_irq_handler SJC_ARM_DEBUG_IRQHandler
.end

46
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf
View File

@ -7,45 +7,17 @@
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 0.1, 2017-01-10
** Build: b180509
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** The Clear BSD License
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted (subject to the limitations in the
** disclaimer below) provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright
** notice, this list of conditions and the following disclaimer.
**
** * Redistributions in binary form must reproduce the above copyright
** notice, this list of conditions and the following disclaimer in the
** documentation and/or other materials provided with the distribution.
**
** * Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from
** this software without specific prior written permission.
**
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -95,6 +67,7 @@ define symbol m_boot_hdr_ivt_start = 0x60001000;
define symbol m_boot_hdr_boot_data_start = 0x60001020;
define symbol m_boot_hdr_dcd_data_start = 0x60001030;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
@ -129,8 +102,9 @@ define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { first readwrite, section m_usb_dma_init_data };
define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
define block QACCESS_FUNC {section .textrw};
initialize by copy { readwrite, section .textrw };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
@ -143,10 +117,10 @@ place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
place in TEXT_region { readonly };
place in DATA3_region { block RW };
place in DATA3_region { block ZI };
place in DATA3_region { last block HEAP };
place in DATA3_region { block RW };
place in DATA3_region { block ZI };
place in DATA3_region { last block HEAP };
place in CSTACK_region { block CSTACK };
place in NCACHE_region { block NCACHE_VAR };
place in TEXT2_region { section .textrw};
place in TEXT2_region { block QACCESS_FUNC };
place in m_interrupts_ram_region { section m_interrupts_ram };

94
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S
View File

@ -2,44 +2,16 @@
; @file: startup_MIMXRT1052.s
; @purpose: CMSIS Cortex-M7 Core Device Startup File
; MIMXRT1052
; @version: 0.1
; @date: 2017-1-10
; @build: b180509
; @version: 1.2
; @date: 2018-11-27
; @build: b190124
; -------------------------------------------------------------------------
;
; The Clear BSD License
; Copyright 1997-2016 Freescale Semiconductor, Inc.
; Copyright 2016-2018 NXP
; Copyright 2016-2019 NXP
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted (subject to the limitations in the
; disclaimer below) provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; * Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
; GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
; HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
; BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
; IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; SPDX-License-Identifier: BSD-3-Clause
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
@ -155,10 +127,10 @@ __vector_table_0x1c
DCD SAI3_RX_IRQHandler ;SAI3 interrupt
DCD SAI3_TX_IRQHandler ;SAI3 interrupt
DCD SPDIF_IRQHandler ;SPDIF interrupt
DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt
DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt
DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt
DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt
DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt
DCD Reserved78_IRQHandler ;Reserved interrupt
DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt
DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt
DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
@ -246,14 +218,14 @@ __vector_table_0x1c
DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt
DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt
DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt
DCD Reserved168_IRQHandler ;Reserved interrupt
DCD Reserved169_IRQHandler ;Reserved interrupt
DCD Reserved170_IRQHandler ;Reserved interrupt
DCD Reserved171_IRQHandler ;Reserved interrupt
DCD Reserved172_IRQHandler ;Reserved interrupt
DCD Reserved173_IRQHandler ;Reserved interrupt
DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt
DCD NMI_WAKEUP_IRQHandler ;NMI wake up
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
@ -707,10 +679,10 @@ SPDIF_IRQHandler
LDR R0, =SPDIF_DriverIRQHandler
BX R0
PUBWEAK ANATOP_EVENT0_IRQHandler
PUBWEAK ANATOP_EVENT1_IRQHandler
PUBWEAK ANATOP_TAMP_LOW_HIGH_IRQHandler
PUBWEAK ANATOP_TEMP_PANIC_IRQHandler
PUBWEAK PMU_EVENT_IRQHandler
PUBWEAK Reserved78_IRQHandler
PUBWEAK TEMP_LOW_HIGH_IRQHandler
PUBWEAK TEMP_PANIC_IRQHandler
PUBWEAK USB_PHY1_IRQHandler
PUBWEAK USB_PHY2_IRQHandler
PUBWEAK ADC1_IRQHandler
@ -840,14 +812,6 @@ ENET_1588_Timer_IRQHandler
PUBWEAK PWM4_2_IRQHandler
PUBWEAK PWM4_3_IRQHandler
PUBWEAK PWM4_FAULT_IRQHandler
PUBWEAK Reserved168_IRQHandler
PUBWEAK Reserved169_IRQHandler
PUBWEAK Reserved170_IRQHandler
PUBWEAK Reserved171_IRQHandler
PUBWEAK Reserved172_IRQHandler
PUBWEAK Reserved173_IRQHandler
PUBWEAK SJC_ARM_DEBUG_IRQHandler
PUBWEAK NMI_WAKEUP_IRQHandler
PUBWEAK DefaultISR
SECTION .text:CODE:REORDER:NOROOT(1)
DMA0_DMA16_DriverIRQHandler
@ -911,10 +875,10 @@ SAI2_DriverIRQHandler
SAI3_RX_DriverIRQHandler
SAI3_TX_DriverIRQHandler
SPDIF_DriverIRQHandler
ANATOP_EVENT0_IRQHandler
ANATOP_EVENT1_IRQHandler
ANATOP_TAMP_LOW_HIGH_IRQHandler
ANATOP_TEMP_PANIC_IRQHandler
PMU_EVENT_IRQHandler
Reserved78_IRQHandler
TEMP_LOW_HIGH_IRQHandler
TEMP_PANIC_IRQHandler
USB_PHY1_IRQHandler
USB_PHY2_IRQHandler
ADC1_IRQHandler
@ -1002,14 +966,6 @@ PWM4_1_IRQHandler
PWM4_2_IRQHandler
PWM4_3_IRQHandler
PWM4_FAULT_IRQHandler
Reserved168_IRQHandler
Reserved169_IRQHandler
Reserved170_IRQHandler
Reserved171_IRQHandler
Reserved172_IRQHandler
Reserved173_IRQHandler
SJC_ARM_DEBUG_IRQHandler
NMI_WAKEUP_IRQHandler
DefaultISR
B DefaultISR

30
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h
View File

@ -1,37 +1,9 @@
/*
* The Clear BSD License
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*
*/

55
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c
View File

@ -5,54 +5,26 @@
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** Compilers: Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 0.1, 2017-01-10
** Build: b180509
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
** Version: rev. 1.2, 2018-11-27
** Build: b190329
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** The Clear BSD License
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2019 NXP
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted (subject to the limitations in the
** disclaimer below) provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright
** notice, this list of conditions and the following disclaimer.
**
** * Redistributions in binary form must reproduce the above copyright
** notice, this list of conditions and the following disclaimer in the
** documentation and/or other materials provided with the distribution.
**
** * Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from
** this software without specific prior written permission.
**
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -60,14 +32,22 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update header files to align with IMXRT1050RM Rev.1.
** - rev. 1.2 (2018-11-27)
** Update header files to align with IMXRT1050RM Rev.2.1.
**
** ###################################################################
*/
/*!
* @file MIMXRT1052
* @version 0.1
* @date 2017-01-10
* @version 1.2
* @date 2018-11-27
* @brief Device specific configuration file for MIMXRT1052 (implementation file)
*
* Provides a system configuration function and a global variable that contains
@ -177,6 +157,7 @@ void SystemCoreClockUpdate (void) {
case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
break;
case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
default:

52
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h
View File

@ -5,54 +5,26 @@
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** Compilers: Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 0.1, 2017-01-10
** Build: b180509
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
** Version: rev. 1.2, 2018-11-27
** Build: b181205
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** The Clear BSD License
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted (subject to the limitations in the
** disclaimer below) provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright
** notice, this list of conditions and the following disclaimer.
**
** * Redistributions in binary form must reproduce the above copyright
** notice, this list of conditions and the following disclaimer in the
** documentation and/or other materials provided with the distribution.
**
** * Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from
** this software without specific prior written permission.
**
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
@ -60,14 +32,22 @@
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
** - rev. 1.0 (2018-09-21)
** Update interrupt vector table and dma request source.
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
** - rev. 1.1 (2018-11-16)
** Update header files to align with IMXRT1050RM Rev.1.
** - rev. 1.2 (2018-11-27)
** Update header files to align with IMXRT1050RM Rev.2.1.
**
** ###################################################################
*/
/*!
* @file MIMXRT1052
* @version 0.1
* @date 2017-01-10
* @version 1.2
* @date 2018-11-27
* @brief Device specific configuration file for MIMXRT1052 (header file)
*
* Provides a system configuration function and a global variable that contains

168
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_adc.h"
@ -39,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -56,8 +29,10 @@ static uint32_t ADC_GetInstance(ADC_Type *base);
/*! @brief Pointers to ADC bases for each instance. */
static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to ADC clocks for each instance. */
static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
@ -80,14 +55,22 @@ static uint32_t ADC_GetInstance(ADC_Type *base)
return instance;
}
/*!
* brief Initialize the ADC module.
*
* param base ADC peripheral base address.
* param config Pointer to "adc_config_t" structure.
*/
void ADC_Init(ADC_Type *base, const adc_config_t *config)
{
assert(NULL != config);
uint32_t tmp32;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* ADCx_CFG */
tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
@ -123,33 +106,90 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config)
base->GC = tmp32;
}
/*!
* brief De-initializes the ADC module.
*
* param base ADC peripheral base address.
*/
void ADC_Deinit(ADC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets an available pre-defined settings for the converter's configuration.
*
* This function initializes the converter configuration structure with available settings. The default values are:
* code
* config->enableAsynchronousClockOutput = true;
* config->enableOverWrite = false;
* config->enableContinuousConversion = false;
* config->enableHighSpeed = false;
* config->enableLowPower = false;
* config->enableLongSample = false;
* config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
* config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
* config->clockSource = kADC_ClockSourceAD;
* config->clockDriver = kADC_ClockDriver1;
* config->resolution = kADC_Resolution12Bit;
* endcode
* param base ADC peripheral base address.
* param config Pointer to the configuration structure.
*/
void ADC_GetDefaultConfig(adc_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableAsynchronousClockOutput = true;
config->enableOverWrite = false;
config->enableContinuousConversion = false;
config->enableHighSpeed = false;
config->enableLowPower = false;
config->enableLongSample = false;
config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
config->clockSource = kADC_ClockSourceAD;
config->clockDriver = kADC_ClockDriver1;
config->resolution = kADC_Resolution12Bit;
config->enableOverWrite = false;
config->enableContinuousConversion = false;
config->enableHighSpeed = false;
config->enableLowPower = false;
config->enableLongSample = false;
config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
config->clockSource = kADC_ClockSourceAD;
config->clockDriver = kADC_ClockDriver1;
config->resolution = kADC_Resolution12Bit;
}
/*!
* brief Configures the conversion channel.
*
* This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
* configures the channel while the external trigger source helps to trigger the conversion.
*
* Note that the "Channel Group" has a detailed description.
* To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
* group of status and control registers, one for each conversion. The channel group parameter indicates which group of
* registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
* registers. The
* channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
* the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
* hardware
* trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
* use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
* about the
* number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
* for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
* Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
* vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
* conversion aborts the current conversion.
*
* param base ADC peripheral base address.
* param channelGroup Channel group index.
* param config Pointer to the "adc_channel_config_t" structure for the conversion channel.
*/
void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
{
assert(NULL != config);
assert(channelGroup < ADC_HC_COUNT);
assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
uint32_t tmp32;
@ -168,6 +208,19 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
* 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
* 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
*/
/*!
* brief Automates the hardware calibration.
*
* This auto calibration helps to adjust the plus/minus side gain automatically.
* Execute the calibration before using the converter. Note that the software trigger should be used
* during calibration.
*
* param base ADC peripheral base address.
*
* return Execution status.
* retval kStatus_Success Calibration is done successfully.
* retval kStatus_Fail Calibration has failed.
*/
status_t ADC_DoAutoCalibration(ADC_Type *base)
{
status_t status = kStatus_Success;
@ -222,6 +275,12 @@ status_t ADC_DoAutoCalibration(ADC_Type *base)
return status;
}
/*!
* brief Set user defined offset.
*
* param base ADC peripheral base address.
* param config Pointer to "adc_offest_config_t" structure.
*/
void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
{
assert(NULL != config);
@ -236,6 +295,19 @@ void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
base->OFS = tmp32;
}
/*!
* brief Configures the hardware compare mode.
*
* The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
* result
* in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
* reference
* manual for more information.
*
* param base ADC peripheral base address.
* param Pointer to "adc_hardware_compare_config_t" structure.
*
*/
void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
{
uint32_t tmp32;
@ -269,10 +341,20 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con
base->GC = tmp32;
/* Load the compare values. */
tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
base->CV = tmp32;
}
/*!
* brief Configures the hardware average mode.
*
* The hardware average mode provides a way to process the conversion result automatically by using hardware. The
* multiple
* conversion results are accumulated and averaged internally making them easier to read.
*
* param base ADC peripheral base address.
* param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
*/
void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
{
uint32_t tmp32;
@ -290,6 +372,12 @@ void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mo
}
}
/*!
* brief Clears the converter's status falgs.
*
* param base ADC peripheral base address.
* param mask Mask value for the cleared flags. See "adc_status_flags_t".
*/
void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
{
uint32_t tmp32 = 0;

60
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ADC_H_
@ -43,20 +17,20 @@
*/
/*******************************************************************************
* Definitions
******************************************************************************/
* Definitions
******************************************************************************/
/*! @brief ADC driver version */
#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
/*!
* @brief Converter's status flags.
*/
typedef enum _adc_status_flags
{
kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */
kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */
kADC_AsynchronousWakeupInterruptFlag =
ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */
ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occurred, support w1c. */
} adc_status_flags_t;
/*!
@ -95,7 +69,7 @@ typedef enum _adc_sample_period_mode
*/
typedef enum _adc_clock_source
{
kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */
kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */
kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */
#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE)
kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */
@ -119,7 +93,7 @@ typedef enum _adc_clock_drvier
*/
typedef enum _adc_resolution
{
kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */
kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */
kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */
kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */
} adc_resolution_t;
@ -146,10 +120,10 @@ typedef enum _adc_hardware_compare_mode
*/
typedef enum _adc_hardware_average_mode
{
kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */
} adc_hardware_average_mode_t;
@ -214,8 +188,8 @@ typedef struct _adc_channel_config
bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
} adc_channel_config_t;
/*******************************************************************************
* API
******************************************************************************/
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
@ -301,7 +275,7 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
*/
static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
{
assert(channelGroup < ADC_R_COUNT);
assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
return base->R[channelGroup];
}
@ -325,7 +299,7 @@ static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t ch
*/
static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
{
assert(channelGroup < ADC_HC_COUNT);
assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
/* If flag is set,return 1,otherwise, return 0. */
return (((base->HS) & (1U << channelGroup)) >> channelGroup);

110
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_adc_etc.h"
@ -55,16 +29,17 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
******************************************************************************/
/*! @brief Pointers to ADC_ETC bases for each instance. */
static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to ADC_ETC clocks for each instance. */
static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
{
uint32_t instance = 0U;
uint32_t instance = 0U;
uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0]));
/* Find the instance index from base address mappings. */
@ -80,6 +55,12 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
}
#endif /* ADC_ETC_CLOCKS */
/*!
* brief Initialize the ADC_ETC module.
*
* param base ADC_ETC peripheral base address.
* param config Pointer to "adc_etc_config_t" structure.
*/
void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
{
assert(NULL != config);
@ -119,6 +100,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
base->CTRL = tmp32;
}
/*!
* brief De-Initialize the ADC_ETC module.
*
* param base ADC_ETC peripheral base address.
*/
void ADC_ETC_Deinit(ADC_ETC_Type *base)
{
/* Do software reset to clear all logical. */
@ -132,9 +118,27 @@ void ADC_ETC_Deinit(ADC_ETC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets an available pre-defined settings for the ADC_ETC's configuration.
* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
* code
* config->enableTSCBypass = true;
* config->enableTSC0Trigger = false;
* config->enableTSC1Trigger = false;
* config->TSC0triggerPriority = 0U;
* config->TSC1triggerPriority = 0U;
* config->clockPreDivider = 0U;
* config->XBARtriggerMask = 0U;
* endCode
*
* param config Pointer to "adc_etc_config_t" structure.
*/
void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
{
config->enableTSCBypass = true;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableTSCBypass = true;
config->enableTSC0Trigger = false;
config->enableTSC1Trigger = false;
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
@ -142,10 +146,17 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
config->TSC0triggerPriority = 0U;
config->TSC1triggerPriority = 0U;
config->clockPreDivider = 0U;
config->XBARtriggerMask = 0U;
config->clockPreDivider = 0U;
config->XBARtriggerMask = 0U;
}
/*!
* brief Set the external XBAR trigger configuration.
*
* param base ADC_ETC peripheral base address.
* param triggerGroup Trigger group index.
* param config Pointer to "adc_etc_trigger_config_t" structure.
*/
void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
{
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
@ -172,6 +183,16 @@ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const a
base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
}
/*!
* brief Set the external XBAR trigger chain configuration.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
* configurated.
*
* param base ADC_ETC peripheral base address.
* param triggerGroup Trigger group index. Available number is 0~7.
* param chainGroup Trigger chain group index. Available number is 0~7.
* param config Pointer to "adc_etc_trigger_chain_config_t" structure.
*/
void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
uint32_t triggerGroup,
uint32_t chainGroup,
@ -262,6 +283,14 @@ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
}
}
/*!
* brief Gets the interrupt status flags of external XBAR and TSC triggers.
*
* param base ADC_ETC peripheral base address.
* param sourceIndex trigger source index.
*
* return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
{
uint32_t tmp32 = 0U;
@ -289,6 +318,13 @@ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_tr
return tmp32;
}
/*!
* brief Clears the ADC_ETC's interrupt status falgs.
*
* param base ADC_ETC peripheral base address.
* param sourceIndex trigger source index.
* param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
{
if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
@ -309,6 +345,16 @@ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trig
}
}
/*!
* brief Get ADC conversion result from external XBAR sources.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
* return Trigger0 source's chain1 conversion result.
*
* param base ADC_ETC peripheral base address.
* param triggerGroup Trigger group index. Available number is 0~7.
* param chainGroup Trigger chain group index. Available number is 0~7.
* return ADC conversion result value.
*/
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
{
assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);

263
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ADC_ETC_H_
@ -43,16 +17,16 @@
*/
/*******************************************************************************
* Definitions
******************************************************************************/
* Definitions
******************************************************************************/
/*! @brief ADC_ETC driver version */
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
/*! @brief The mask of status flags cleared by writing 1. */
#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
/*!
* @brief ADC_ETC customized status flags mask.
*/
* @brief ADC_ETC customized status flags mask.
*/
enum _adc_etc_status_flag_mask
{
kADC_ETC_Done0StatusFlagMask = 1U,
@ -62,8 +36,8 @@ enum _adc_etc_status_flag_mask
};
/*!
* @brief External triggers sources.
*/
* @brief External triggers sources.
*/
typedef enum _adc_etc_external_trigger_source
{
/* External XBAR sources. Support HW or SW mode. */
@ -81,11 +55,11 @@ typedef enum _adc_etc_external_trigger_source
} adc_etc_external_trigger_source_t;
/*!
* @brief Interrupt enable/disable mask.
*/
* @brief Interrupt enable/disable mask.
*/
typedef enum _adc_etc_interrupt_enable
{
kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */
kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */
kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
@ -93,12 +67,13 @@ typedef enum _adc_etc_interrupt_enable
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
/*!
* @brief DMA mode selection.
*/
* @brief DMA mode selection.
*/
typedef enum _adc_etc_dma_mode_selection
{
kADC_ETC_TrigDMAWithLatchedSignal = 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
kADC_ETC_TrigDMAWithLatchedSignal =
0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
} adc_etc_dma_mode_selection_t;
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
@ -107,26 +82,26 @@ typedef enum _adc_etc_dma_mode_selection
*/
typedef struct _adc_etc_config
{
bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
Otherwise TSC would trigger ADC through ADC_ETC. */
bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
Otherwise TSC would trigger ADC through ADC_ETC. */
bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
Clock would be divided by (clockPreDivider+1). */
uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
trigger7:0x80
For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
enabled. */
adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
Clock would be divided by (clockPreDivider+1). */
uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
trigger7:0x80
For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
enabled. */
} adc_etc_config_t;
/*!
* @brief ADC_ETC trigger chain configuration.
*/
* @brief ADC_ETC trigger chain configuration.
*/
typedef struct _adc_etc_trigger_chain_config
{
bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
@ -137,8 +112,8 @@ typedef struct _adc_etc_trigger_chain_config
} adc_etc_trigger_chain_config_t;
/*!
* @brief ADC_ETC trigger configuration.
*/
* @brief ADC_ETC trigger configuration.
*/
typedef struct _adc_etc_trigger_config
{
bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
@ -151,8 +126,8 @@ typedef struct _adc_etc_trigger_config
} adc_etc_trigger_config_t;
/*******************************************************************************
* API
******************************************************************************/
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
@ -163,88 +138,88 @@ extern "C" {
*/
/*!
* @brief Initialize the ADC_ETC module.
*
* @param base ADC_ETC peripheral base address.
* @param config Pointer to "adc_etc_config_t" structure.
*/
* @brief Initialize the ADC_ETC module.
*
* @param base ADC_ETC peripheral base address.
* @param config Pointer to "adc_etc_config_t" structure.
*/
void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
/*!
* @brief De-Initialize the ADC_ETC module.
*
* @param base ADC_ETC peripheral base address.
*/
* @brief De-Initialize the ADC_ETC module.
*
* @param base ADC_ETC peripheral base address.
*/
void ADC_ETC_Deinit(ADC_ETC_Type *base);
/*!
* @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
* @code
* config->enableTSCBypass = true;
* config->enableTSC0Trigger = false;
* config->enableTSC1Trigger = false;
* config->TSC0triggerPriority = 0U;
* config->TSC1triggerPriority = 0U;
* config->clockPreDivider = 0U;
* config->XBARtriggerMask = 0U;
* @endCode
*
* @param config Pointer to "adc_etc_config_t" structure.
*/
* @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
* @code
* config->enableTSCBypass = true;
* config->enableTSC0Trigger = false;
* config->enableTSC1Trigger = false;
* config->TSC0triggerPriority = 0U;
* config->TSC1triggerPriority = 0U;
* config->clockPreDivider = 0U;
* config->XBARtriggerMask = 0U;
* @endCode
*
* @param config Pointer to "adc_etc_config_t" structure.
*/
void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
/*!
* @brief Set the external XBAR trigger configuration.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index.
* @param config Pointer to "adc_etc_trigger_config_t" structure.
*/
* @brief Set the external XBAR trigger configuration.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index.
* @param config Pointer to "adc_etc_trigger_config_t" structure.
*/
void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
/*!
* @brief Set the external XBAR trigger chain configuration.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
* configurated.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
* @param chainGroup Trigger chain group index. Available number is 0~7.
* @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
*/
* @brief Set the external XBAR trigger chain configuration.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
* configurated.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
* @param chainGroup Trigger chain group index. Available number is 0~7.
* @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
*/
void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
uint32_t triggerGroup,
uint32_t chainGroup,
const adc_etc_trigger_chain_config_t *config);
/*!
* @brief Gets the interrupt status flags of external XBAR and TSC triggers.
*
* @param base ADC_ETC peripheral base address.
* @param sourceIndex trigger source index.
*
* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
* @brief Gets the interrupt status flags of external XBAR and TSC triggers.
*
* @param base ADC_ETC peripheral base address.
* @param sourceIndex trigger source index.
*
* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
/*!
* @brief Clears the ADC_ETC's interrupt status falgs.
*
* @param base ADC_ETC peripheral base address.
* @param sourceIndex trigger source index.
* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
* @brief Clears the ADC_ETC's interrupt status falgs.
*
* @param base ADC_ETC peripheral base address.
* @param sourceIndex trigger source index.
* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
*/
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
adc_etc_external_trigger_source_t sourceIndex,
uint32_t mask);
/*!
* @brief Enable the DMA corresponding to each trigger source.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
*/
* @brief Enable the DMA corresponding to each trigger source.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
*/
static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
{
/* Avoid clearing status flags at the same time. */
@ -253,11 +228,11 @@ static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
}
/*!
* @brief Disable the DMA corresponding to each trigger sources.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
*/
* @brief Disable the DMA corresponding to each trigger sources.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
*/
static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
{
/* Avoid clearing status flags at the same time. */
@ -290,11 +265,11 @@ static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask
}
/*!
* @brief When enable ,all logical will be reset.
*
* @param base ADC_ETC peripheral base address.
* @param enable Enable/Disable the software reset.
*/
* @brief When enable ,all logical will be reset.
*
* @param base ADC_ETC peripheral base address.
* @param enable Enable/Disable the software reset.
*/
static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
{
if (enable)
@ -308,14 +283,14 @@ static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
}
/*!
* @brief Do software trigger corresponding to each XBAR trigger sources.
* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
* can only work in hardware trigger mode.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
*/
* @brief Do software trigger corresponding to each XBAR trigger sources.
* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
* can only work in hardware trigger mode.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
*/
static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
{
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
@ -324,15 +299,15 @@ static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t trigge
}
/*!
* @brief Get ADC conversion result from external XBAR sources.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
* return Trigger0 source's chain1 conversion result.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
* @param chainGroup Trigger chain group index. Available number is 0~7.
* @return ADC conversion result value.
*/
* @brief Get ADC conversion result from external XBAR sources.
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
* return Trigger0 source's chain1 conversion result.
*
* @param base ADC_ETC peripheral base address.
* @param triggerGroup Trigger group index. Available number is 0~7.
* @param chainGroup Trigger chain group index. Available number is 0~7.
* @return ADC conversion result value.
*/
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
#if defined(__cplusplus)

53
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_aipstz.h"
@ -43,24 +17,35 @@
#define FSL_COMPONENT_ID "platform.drivers.aipstz"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* brief Configure the privilege level for master.
*
* param base AIPSTZ peripheral base pointer
* param master Masters for AIPSTZ.
* param privilegeConfig Configuration is ORed from aipstz_master_privilege_level_t.
*/
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
{
uint32_t mask = ((uint32_t)master >> 8) - 1;
uint32_t mask = ((uint32_t)master >> 8) - 1;
uint32_t shift = (uint32_t)master & 0xFF;
base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
}
/*!
* brief Configure the access for peripheral.
*
* param base AIPSTZ peripheral base pointer
* param master Peripheral for AIPSTZ.
* param accessControl Configuration is ORed from aipstz_peripheral_access_control_t.
*/
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
{
volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
uint32_t shift = (uint32_t)peripheral & 0xFF;
uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
uint32_t shift = (uint32_t)peripheral & 0xFF;
*reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
}

79
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_AIPSTZ_H_
#define _FSL_AIPSTZ_H_
@ -51,15 +25,17 @@
/*@}*/
/*! @brief List of AIPSTZ privilege configuration.*/
typedef enum _aipstz_master_privilege_level {
kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
typedef enum _aipstz_master_privilege_level
{
kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */
kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
} aipstz_master_privilege_level_t;
/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/
typedef enum _aipstz_master {
typedef enum _aipstz_master
{
kAIPSTZ_Master0 = (0x400U | 28U),
kAIPSTZ_Master1 = (0x400U | 24U),
kAIPSTZ_Master2 = (0x400U | 20U),
@ -68,47 +44,50 @@ typedef enum _aipstz_master {
} aipstz_master_t;
/*! @brief List of AIPSTZ peripheral access control configuration.*/
typedef enum _aipstz_peripheral_access_control {
typedef enum _aipstz_peripheral_access_control
{
kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
kAIPSTZ_PeripheralWriteProtected = (1U << 1),
kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
kAIPSTZ_PeripheralWriteProtected = (1U << 1),
kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
} aipstz_peripheral_access_control_t;
/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/
typedef enum _aipstz_peripheral {
/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and
* shift for lower 8 bits.*/
typedef enum _aipstz_peripheral
{
kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28),
kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24),
kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20),
kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16),
kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12),
kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28),
kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24),
kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20),
kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16),
kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12),
kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28),
kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24),
kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20),
kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16),
kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12),
kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28),
kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24),
kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20),
kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16),
kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12),
kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28),
kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24)
} aipstz_peripheral_t;

104
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_aoi.h"
@ -38,7 +12,6 @@
#define FSL_COMPONENT_ID "platform.drivers.aoi"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
@ -49,9 +22,9 @@ static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
/*! @brief Pointers to aoi clocks for each instance. */
static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for AOI module.
*
@ -82,6 +55,13 @@ static uint32_t AOI_GetInstance(AOI_Type *base)
return instance;
}
/*!
* brief Initializes an AOI instance for operation.
*
* This function un-gates the AOI clock.
*
* param base AOI peripheral address.
*/
void AOI_Init(AOI_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -90,6 +70,13 @@ void AOI_Init(AOI_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Deinitializes an AOI instance for operation.
*
* This function shutdowns AOI module.
*
* param base AOI peripheral address.
*/
void AOI_Deinit(AOI_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -98,6 +85,22 @@ void AOI_Deinit(AOI_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets the Boolean evaluation associated.
*
* This function returns the Boolean evaluation associated.
*
* Example:
code
aoi_event_config_t demoEventLogicStruct;
AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
endcode
*
* param base AOI peripheral address.
* param event Index of the event which will be set of type aoi_event_t.
* param config Selected input configuration .
*/
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
{
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
@ -132,6 +135,45 @@ void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config
config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT);
}
/*!
* brief Configures an AOI event.
*
* This function configures an AOI event according
* to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D)
* of all product terms (0, 1, 2, and 3) of a desired event.
*
* Example:
code
aoi_event_config_t demoEventLogicStruct;
demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;
demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;
demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;
demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;
AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
endcode
*
* param base AOI peripheral address.
* param event Event which will be configured of type aoi_event_t.
* param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
* filling out the members of this structure and passing the pointer to this function.
*/
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
{
assert(eventConfig != NULL);

37
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_AOI_H_
#define _FSL_AOI_H_
@ -41,7 +15,6 @@
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
@ -58,13 +31,13 @@
* @brief AOI input configurations.
*
* The selection item represents the Boolean evaluations.
*/
*/
typedef enum _aoi_input_config
{
kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */
kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */
kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */
kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */
kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */
kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */
kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */
} aoi_input_config_t;
/*!

271
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_bee.h"
@ -43,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.bee"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
@ -54,7 +27,7 @@
static void aligned_memcpy(void *dst, const void *src, size_t size)
{
register uint32_t *to32 = (uint32_t *)(uintptr_t)dst;
register uint32_t *to32 = (uint32_t *)(uintptr_t)dst;
register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src;
while (size >= sizeof(uint32_t))
@ -66,6 +39,13 @@ static void aligned_memcpy(void *dst, const void *src, size_t size)
}
}
/*!
* brief Resets BEE module to factory default values.
*
* This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared.
*
* param base BEE peripheral address.
*/
void BEE_Init(BEE_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -75,6 +55,14 @@ void BEE_Init(BEE_Type *base)
base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK;
}
/*!
* brief Resets BEE module, clears keys for both regions and disables clock to the BEE.
*
* This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both
* regions are cleared.
*
* param base BEE peripheral address.
*/
void BEE_Deinit(BEE_Type *base)
{
base->CTRL &=
@ -85,20 +73,55 @@ void BEE_Deinit(BEE_Type *base)
#endif
}
/*!
* brief Loads default values to the BEE region configuration structure.
*
* Loads default values to the BEE region configuration structure. The default values are as follows:
* code
* config->region0Mode = kBEE_AesCtrMode;
* config->region1Mode = kBEE_AesCtrMode;
* config->region0AddrOffset = 0U;
* config->region1AddrOffset = 0U;
* config->region0SecLevel = kBEE_SecurityLevel3;
* config->region1SecLevel = kBEE_SecurityLevel3;
* config->region1Bot = 0U;
* config->region1Top = 0U;
* config->accessPermission = kBEE_AccessProtDisabled;
* config->endianSwapEn = kBEE_EndianSwapEnabled;
* endcode
*
* param config Configuration structure for BEE peripheral.
*/
void BEE_GetDefaultConfig(bee_region_config_t *config)
{
assert(config);
config->mode = kBEE_AesEcbMode;
config->regionBot = 0U;
config->regionTop = 0U;
config->addrOffset = 0xF0000000U;
config->regionEn = kBEE_RegionDisabled;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->region0Mode = kBEE_AesCtrMode;
config->region1Mode = kBEE_AesCtrMode;
config->region0AddrOffset = 0U;
config->region1AddrOffset = 0U;
config->region0SecLevel = kBEE_SecurityLevel3;
config->region1SecLevel = kBEE_SecurityLevel3;
config->region1Bot = 0U;
config->region1Top = 0U;
config->accessPermission = kBEE_AccessProtDisabled;
config->endianSwapEn = kBEE_EndianSwapEnabled;
}
status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config)
/*!
* brief Sets BEE configuration.
*
* This function sets BEE peripheral and BEE region settings accorging to given configuration structure.
*
* param base BEE peripheral address.
* param config Configuration structure for BEE.
*/
void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config)
{
IOMUXC_GPR_Type *iomuxc = IOMUXC_GPR;
uint32_t beeCtrlVal;
bool reenable = false;
/* Wait until BEE is in idle state */
@ -107,62 +130,51 @@ status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_regi
}
/* Disable BEE before region configuration in case it is enabled. */
if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1)
if (base->CTRL & BEE_CTRL_BEE_ENABLE_MASK)
{
BEE_Disable(base);
reenable = true;
}
if (region == kBEE_Region0)
{
/* Region 0 config */
iomuxc->GPR18 = config->regionBot;
iomuxc->GPR19 = config->regionTop;
/* Preserve CTRL bit values that are not set by this function */
beeCtrlVal = base->CTRL & 0xFFFF0037;
base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R0(config->mode);
base->ADDR_OFFSET0 = BEE_ADDR_OFFSET0_ADDR_OFFSET0(config->addrOffset);
}
/* Set variable according to configuration */
beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) |
BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) |
BEE_CTRL_SECURITY_LEVEL_R1(config->region1SecLevel) | BEE_CTRL_CTRL_AES_MODE_R1(config->region1Mode);
else if (region == kBEE_Region1)
{
/* Region 1 config */
iomuxc->GPR20 = config->regionBot;
iomuxc->GPR21 = config->regionTop;
base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R1(config->mode);
base->ADDR_OFFSET1 = BEE_ADDR_OFFSET1_ADDR_OFFSET0(config->addrOffset);
base->REGION1_BOT = BEE_REGION1_BOT_REGION1_BOT(config->regionBot);
base->REGION1_TOP = BEE_REGION1_TOP_REGION1_TOP(config->regionTop);
}
else
{
return kStatus_InvalidArgument;
}
/* Enable/disable region if desired */
if (config->regionEn == kBEE_RegionEnabled)
{
iomuxc->GPR11 |= IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region);
}
else
{
iomuxc->GPR11 &= ~IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region);
}
/* Load values to registers */
base->CTRL = beeCtrlVal;
base->ADDR_OFFSET0 = config->region0AddrOffset;
base->ADDR_OFFSET1 = config->region1AddrOffset;
base->REGION1_BOT = config->region1Bot;
base->REGION1_TOP = config->region1Top;
/* Reenable BEE if it was enabled before. */
if (reenable)
{
BEE_Enable(base);
}
return kStatus_Success;
}
status_t BEE_SetRegionKey(
BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize)
/*!
* brief Loads the AES key for selected region into BEE key registers.
*
* This function loads given AES key to BEE register for the given region.
* The key must be 32-bit aligned and stored in little-endian format.
*
* Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
* Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
*
* param base BEE peripheral address.
* param region Selection of the BEE region to be configured.
* param key AES key (in little-endian format).
* param keySize Size of AES key.
*/
status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize)
{
bool reenable = false;
bool redisable = false;
/* Key must be 32-bit aligned */
if (((uintptr_t)key & 0x3u) || (keySize != 16))
@ -175,39 +187,27 @@ status_t BEE_SetRegionKey(
{
}
/* Disable BEE before region configuration in case it is enabled. */
if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1)
/* Clear KEY_VALID bit before new key is loaded */
base->CTRL &= ~BEE_CTRL_KEY_VALID_MASK;
/* Write key registers, key is stored in little-endian format in memory */
aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize);
/* Enable BEE before key configuration. */
if (!(base->CTRL & BEE_CTRL_BEE_ENABLE_MASK))
{
BEE_Disable(base);
reenable = true;
BEE_Enable(base);
redisable = true;
}
if (region == kBEE_Region0)
{
base->CTRL &= ~BEE_CTRL_KEY_REGION_SEL_MASK;
if (nonce)
{
if (nonceSize != 16)
{
return kStatus_InvalidArgument;
}
memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize);
}
}
else if (region == kBEE_Region1)
{
base->CTRL |= BEE_CTRL_KEY_REGION_SEL_MASK;
if (nonce)
{
if (nonceSize != 16)
{
return kStatus_InvalidArgument;
}
memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize);
}
}
else
@ -215,28 +215,87 @@ status_t BEE_SetRegionKey(
return kStatus_InvalidArgument;
}
/* Try to load key. If BEE key selection fuse is programmed to use OTMP key on this device, this operation should
* fail. */
aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize);
if (memcmp((uint32_t *)&base->AES_KEY0_W0, key, keySize) != 0)
/* Set KEY_VALID bit to trigger key loading */
base->CTRL |= BEE_CTRL_KEY_VALID_MASK;
/* Wait until key is ready */
while (!(base->CTRL & BEE_CTRL_KEY_VALID_MASK))
{
return kStatus_Fail;
}
/* Reenable BEE if it was enabled before. */
if (reenable)
/* Redisable BEE if it was disabled before this function call. */
if (redisable)
{
BEE_Enable(base);
BEE_Disable(base);
}
return kStatus_Success;
}
/*!
* brief Loads the nonce for selected region into BEE nonce registers.
*
* This function loads given nonce(only AES CTR mode) to BEE register for the given region.
* The nonce must be 32-bit aligned and stored in little-endian format.
*
* param base BEE peripheral address.
* param region Selection of the BEE region to be configured.
* param nonce AES nonce (in little-endian format).
* param nonceSize Size of AES nonce.
*/
status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize)
{
/* Nonce must be 32-bit aligned */
if (((uintptr_t)nonce & 0x3u) || (nonceSize != 16))
{
return kStatus_InvalidArgument;
}
/* Wait until BEE is in idle state */
while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag))
{
}
/* Write nonce registers, nonce is stored in little-endian format in memory */
if (region == kBEE_Region0)
{
aligned_memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize);
}
else if (region == kBEE_Region1)
{
aligned_memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize);
}
else
{
return kStatus_InvalidArgument;
}
return kStatus_Success;
}
/*!
* brief Gets the BEE status flags.
*
* This function returns status of BEE peripheral.
*
* param base BEE peripheral address.
*
* return The status flags. This is the logical OR of members of the
* enumeration ::bee_status_flags_t
*/
uint32_t BEE_GetStatusFlags(BEE_Type *base)
{
return base->STATUS;
}
/*!
* brief Clears the BEE status flags.
*
* param base BEE peripheral base address.
* param mask The status flags to clear. This is a logical OR of members of the
* enumeration ::bee_status_flags_t
*/
void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask)
{
/* w1c */

157
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_BEE_H_
@ -37,21 +11,26 @@
#include "fsl_common.h"
/*!
* @addtogroup bee
* @{
*/
/*******************************************************************************
* Definitions
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief BEE driver version. Version 2.0.0.
/*! @brief BEE driver version. Version 2.0.1.
*
* Current version: 2.0.0
* Current version: 2.0.1
*
* Change log:
* - Version 2.0.0
* - Version 2.0.1
* - Initial version
*/
#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
typedef enum _bee_aes_mode
@ -66,31 +45,50 @@ typedef enum _bee_region
kBEE_Region1 = 1U /*!< BEE region 1 */
} bee_region_t;
typedef enum _bee_region_enable
typedef enum _bee_ac_prot_enable
{
kBEE_RegionDisabled = 0U, /*!< BEE region disabled */
kBEE_RegionEnabled = 1U /*!< BEE region enabled */
} bee_region_enable_t;
kBEE_AccessProtDisabled = 0U, /*!< BEE access permission control disabled */
kBEE_AccessProtEnabled = 1U /*!< BEE access permission control enabled */
} bee_ac_prot_enable;
typedef enum _bee_endian_swap_enable
{
kBEE_EndianSwapDisabled = 1U, /*!< BEE endian swap disabled */
kBEE_EndianSwapEnabled = 0U /*!< BEE endian swap enabled */
} bee_endian_swap_enable;
typedef enum _bee_security_level
{
kBEE_SecurityLevel0 = 0U, /*!< BEE security level 0 */
kBEE_SecurityLevel1 = 1U, /*!< BEE security level 1 */
kBEE_SecurityLevel2 = 2U, /*!< BEE security level 2 */
kBEE_SecurityLevel3 = 3U /*!< BEE security level 3 */
} bee_security_level;
typedef enum _bee_status_flags
{
kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */
kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */
kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */
kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */
kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */
kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */
kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */
kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */
kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */
kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */
kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */
kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */
kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */
kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */
} bee_status_flags_t;
/*! @brief BEE region configuration structure. */
typedef struct _bee_region_config
{
bee_aes_mode_t mode; /*!< AES mode used for encryption/decryption */
uint32_t regionBot; /*!< Region bottom address */
uint32_t regionTop; /*!< Region top address */
uint32_t addrOffset; /*!< Region address offset */
bee_region_enable_t regionEn; /*!< Region enable/disable */
bee_aes_mode_t region0Mode; /*!< AES mode used for encryption/decryption for region 0 */
bee_aes_mode_t region1Mode; /*!< AES mode used for encryption/decryption for region 1 */
uint32_t region0AddrOffset; /*!< Region 0 address offset */
uint32_t region1AddrOffset; /*!< Region 1 address offset */
bee_security_level region0SecLevel; /*!< Region 0 security level */
bee_security_level region1SecLevel; /*!< Region 1 security level */
uint32_t region1Bot; /*!< Region 1 bottom address */
uint32_t region1Top; /*!< Region 1 top address */
bee_ac_prot_enable accessPermission; /*!< Access permission control enable/disable */
bee_endian_swap_enable endianSwapEn; /*!< Endian swap enable/disable */
} bee_region_config_t;
/*******************************************************************************
@ -128,7 +126,7 @@ void BEE_Deinit(BEE_Type *base);
*/
static inline void BEE_Enable(BEE_Type *base)
{
base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK;
}
/*!
@ -140,7 +138,7 @@ static inline void BEE_Enable(BEE_Type *base)
*/
static inline void BEE_Disable(BEE_Type *base)
{
base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK;
}
/*!
@ -148,45 +146,60 @@ static inline void BEE_Disable(BEE_Type *base)
*
* Loads default values to the BEE region configuration structure. The default values are as follows:
* @code
* config->mode = kBEE_AesCbcMode;
* config->regionBot = 0U;
* config->regionTop = 0U;
* config->addrOffset = 0xF0000000U;
* config->regionEn = kBEE_RegionDisabled;
* config->region0Mode = kBEE_AesCtrMode;
* config->region1Mode = kBEE_AesCtrMode;
* config->region0AddrOffset = 0U;
* config->region1AddrOffset = 0U;
* config->region0SecLevel = kBEE_SecurityLevel3;
* config->region1SecLevel = kBEE_SecurityLevel3;
* config->region1Bot = 0U;
* config->region1Top = 0U;
* config->accessPermission = kBEE_AccessProtDisabled;
* config->endianSwapEn = kBEE_EndianSwapEnabled;
* @endcode
*
* @param config Configuration structure for BEE region.
* @param config Configuration structure for BEE peripheral.
*/
void BEE_GetDefaultConfig(bee_region_config_t *config);
/*!
* @brief Sets BEE region configuration.
* @brief Sets BEE configuration.
*
* This function sets BEE region settings accorging to given configuration structure.
* This function sets BEE peripheral and BEE region settings accorging to given configuration structure.
*
* @param base BEE peripheral address.
* @param region Selection of the BEE region to be configured.
* @param config Configuration structure for BEE region.
* @param config Configuration structure for BEE.
*/
status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config);
void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config);
/*!
* @brief Loads the AES key and nonce for selected region into BEE key registers.
* @brief Loads the AES key for selected region into BEE key registers.
*
* This function loads given AES key and nonce(only AES CTR mode) to BEE register for the given region.
* This function loads given AES key to BEE register for the given region.
* The key must be 32-bit aligned and stored in little-endian format.
*
* Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
* Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
*
* @param base BEE peripheral address.
* @param region Selection of the BEE region to be configured.
* @param key AES key.
* @param key AES key (in little-endian format).
* @param keySize Size of AES key.
* @param nonce AES nonce.
*/
status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize);
/*!
* @brief Loads the nonce for selected region into BEE nonce registers.
*
* This function loads given nonce(only AES CTR mode) to BEE register for the given region.
* The nonce must be 32-bit aligned and stored in little-endian format.
*
* @param base BEE peripheral address.
* @param region Selection of the BEE region to be configured.
* @param nonce AES nonce (in little-endian format).
* @param nonceSize Size of AES nonce.
*/
status_t BEE_SetRegionKey(
BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize);
status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize);
/*!
* @brief Gets the BEE status flags.
@ -209,18 +222,6 @@ uint32_t BEE_GetStatusFlags(BEE_Type *base);
*/
void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask);
/*!
* @brief Computes offset to be set for specifed memory location.
*
* This function calculates offset that must be set for BEE region to access physical memory location.
*
* @param addressMemory Address of physical memory location.
*/
static inline uint32_t BEE_GetOffset(uint32_t addressMemory)
{
return (addressMemory >> 16);
}
#if defined(__cplusplus)
}
#endif

265
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cache.h"
@ -50,10 +24,10 @@
#define L2CACHE_SMALLWAYS_NUM 8U
#define L2CACHE_1KBCOVERTOB 1024U
#define L2CACHE_SAMLLWAYS_SIZE 16U
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
/*******************************************************************************
* Prototypes
******************************************************************************/
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Set for all ways and waiting for the operation finished.
* This is provided for all the background operations.
@ -124,7 +98,7 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
******************************************************************************/
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
{
uint16_t mask = L2CACHE_8WAYS_MASK;
uint16_t mask = L2CACHE_8WAYS_MASK;
uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
/* Check the ways used at first. */
@ -192,10 +166,15 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
*size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
}
/*!
* brief Initializes the level 2 cache controller module.
*
* param config Pointer to configuration structure. See "l2cache_config_t".
*/
void L2CACHE_Init(l2cache_config_t *config)
{
assert (config);
assert(config);
uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
uint8_t count;
uint32_t auxReg = 0;
@ -206,7 +185,7 @@ void L2CACHE_Init(l2cache_config_t *config)
if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
{
L2CACHE_Disable();
}
}
/* Unlock all entries. */
if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
@ -214,20 +193,18 @@ void L2CACHE_Init(l2cache_config_t *config)
waysNum = 0xFFFFU;
}
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++)
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
{
L2CACHE_LockdownByWayEnable(count, waysNum, false);
L2CACHE_LockdownByWayEnable(count, waysNum, false);
}
/* Set the ways and way-size etc. */
auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) |
L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) |
L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
L2CACHEC->REG1_AUX_CONTROL = auxReg;
/* Set the tag/data ram latency. */
@ -235,39 +212,66 @@ void L2CACHE_Init(l2cache_config_t *config)
{
uint32_t data = 0;
/* Tag latency. */
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)|
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
L2CACHEC->REG1_TAG_RAM_CONTROL = data;
/* Data latency. */
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)|
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
L2CACHEC->REG1_DATA_RAM_CONTROL = data;
}
}
/*!
* brief Gets an available default settings for the cache controller.
*
* This function initializes the cache controller configuration structure with default settings.
* The default values are:
* code
* config->waysNum = kL2CACHE_8ways;
* config->waySize = kL2CACHE_32KbSize;
* config->repacePolicy = kL2CACHE_Roundrobin;
* config->lateConfig = NULL;
* config->istrPrefetchEnable = false;
* config->dataPrefetchEnable = false;
* config->nsLockdownEnable = false;
* config->writeAlloc = kL2CACHE_UseAwcache;
* endcode
* param config Pointer to the configuration structure.
*/
void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
/* Get the default value */
config->wayNum = (l2cache_way_num_t)number;
config->waySize = (l2cache_way_size)size;
config->repacePolicy = kL2CACHE_Roundrobin;
config->lateConfig = NULL;
config->wayNum = (l2cache_way_num_t)number;
config->waySize = (l2cache_way_size)size;
config->repacePolicy = kL2CACHE_Roundrobin;
config->lateConfig = NULL;
config->istrPrefetchEnable = false;
config->dataPrefetchEnable = false;
config->nsLockdownEnable = false;
config->writeAlloc = kL2CACHE_UseAwcache;
config->nsLockdownEnable = false;
config->writeAlloc = kL2CACHE_UseAwcache;
}
/*!
* brief Enables the level 2 cache controller.
* This function enables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Enable(void)
{
/* Invalidate first. */
@ -276,6 +280,12 @@ void L2CACHE_Enable(void)
L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
}
/*!
* brief Disables the level 2 cache controller.
* This function disables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Disable(void)
{
/* First CleanInvalidate all enties in the cache. */
@ -286,6 +296,11 @@ void L2CACHE_Disable(void)
__DSB();
}
/*!
* brief Invalidates the Level 2 cache.
* This function invalidates all entries in cache.
*
*/
void L2CACHE_Invalidate(void)
{
/* Invalidate all entries in cache. */
@ -294,6 +309,11 @@ void L2CACHE_Invalidate(void)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans the level 2 cache controller.
* This function cleans all entries in the level 2 cache controller.
*
*/
void L2CACHE_Clean(void)
{
/* Clean all entries of the cache. */
@ -302,6 +322,11 @@ void L2CACHE_Clean(void)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans and invalidates the level 2 cache controller.
* This function cleans and invalidates all entries in the level 2 cache controller.
*
*/
void L2CACHE_CleanInvalidate(void)
{
/* Clean all entries of the cache. */
@ -310,6 +335,17 @@ void L2CACHE_CleanInvalidate(void)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Invalidates the Level 2 cache lines in the range of two physical addresses.
* This function invalidates all cache lines between two physical addresses.
*
* param address The start address of the memory to be invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte;
@ -326,11 +362,22 @@ void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans the Level 2 cache lines in the range of two physical addresses.
* This function cleans all cache lines between two physical addresses.
*
* param address The start address of the memory to be cleaned.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
uint32_t num_ways = 0;
uint32_t size_way = 0;
uint32_t endAddr = address + size_byte;
uint32_t endAddr = address + size_byte;
/* Get the number and size of the cache way. */
L2CACHE_GetWayNumSize(&num_ways, &size_way);
@ -353,11 +400,22 @@ void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
* This function cleans and invalidates all cache lines between two physical addresses.
*
* param address The start address of the memory to be cleaned and invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
uint32_t num_ways = 0;
uint32_t size_way = 0;
uint32_t endAddr = address + size_byte;
uint32_t endAddr = address + size_byte;
/* Get the number and size of the cache way. */
L2CACHE_GetWayNumSize(&num_ways, &size_way);
@ -380,6 +438,23 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Enables or disables to lock down the data and instruction by way.
* This function locks down the cached instruction/data by way and prevent the adresses from
* being allocated and prevent dara from being evicted out of the level 2 cache.
* But the normal cache maintenance operations that invalidate, clean or clean
* and validate cache contents affect the locked-down cache lines as normal.
*
* param masterId The master id, range from 0 ~ 7.
* param mask The ways to be enabled or disabled to lockdown.
* each bit in value is related to each way of the cache. for example:
* value: bit 0 ------ way 0.
* value: bit 1 ------ way 1.
* --------------------------
* value: bit 15 ------ way 15.
* Note: please make sure the value setting is align with your supported ways.
* param enable True enable the lockdown, false to disable the lockdown.
*/
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
{
uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
@ -407,13 +482,23 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
}
}
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*!
* brief Invalidate cortex-m7 L1 instruction cache by range.
*
* param address The start address of the memory to be invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 I-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
{
#if (__DCACHE_PRESENT == 1U)
uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
int32_t size = size_byte + address - addr;
uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
int32_t size = size_byte + address - addr;
uint32_t linesize = 32U;
__DSB();
@ -425,9 +510,21 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
}
__DSB();
__ISB();
#endif
#endif
}
/*!
* brief Invalidates all instruction caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@ -436,9 +533,21 @@ void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
L1CACHE_InvalidateICacheByRange(address, size_byte);
L1CACHE_InvalidateICacheByRange(address, size_byte);
}
/*!
* brief Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@ -449,6 +558,18 @@ void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
L1CACHE_InvalidateDCacheByRange(address, size_byte);
}
/*!
* brief Cleans all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be cleaned.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanDCacheByRange(address, size_byte);
@ -459,6 +580,18 @@ void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
}
/*!
* brief Cleans and Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be cleaned and invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);

123
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_H_
#define _FSL_CACHE_H_
@ -53,7 +27,7 @@
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
#endif
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*******************************************************************************
@ -64,80 +38,80 @@
/*! @brief Number of level 2 cache controller ways. */
typedef enum _l2cache_way_num
{
kL2CACHE_8ways = 0, /*!< 8 ways. */
kL2CACHE_8ways = 0, /*!< 8 ways. */
#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
kL2CACHE_16ways /*!< 16 ways. */
#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
kL2CACHE_16ways /*!< 16 ways. */
#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
} l2cache_way_num_t;
/*! @brief Level 2 cache controller way size. */
typedef enum _l2cache_way_size
{
kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
} l2cache_way_size;
/*! @brief Level 2 cache controller replacement policy. */
typedef enum _l2cache_replacement
{
kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
} l2cache_replacement_t;
/*! @brief Level 2 cache controller force write allocate options. */
typedef enum _l2cache_writealloc
{
kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
} l2cache_writealloc_t;
/*! @brief Level 2 cache controller tag/data ram latency. */
typedef enum _l2cache_latency
{
kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
} l2cache_latency_t;
/*! @brief Level 2 cache controller tag/data ram latency configure structure. */
typedef struct _l2cache_latency_config
{
l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
l2cache_latency_t dataWriteLate; /*!< Data write latency. */
l2cache_latency_t dataReadLate; /*!< Data Read latency. */
l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
l2cache_latency_t dataWriteLate; /*!< Data write latency. */
l2cache_latency_t dataReadLate; /*!< Data Read latency. */
l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
} L2cache_latency_config_t;
/*! @brief Level 2 cache controller configure structure. */
typedef struct _l2cache_config
{
/* ------------------------ l2 cachec basic settings ---------------------------- */
l2cache_way_num_t wayNum; /*!< The number of ways. */
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */
l2cache_way_num_t wayNum; /*!< The number of ways. */
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */
/* ------------------------ tag/data ram latency settings ----------------------- */
L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
/* ------------------------ Prefetch enable settings ---------------------------- */
bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
bool dataPrefetchEnable; /*!< Data prefetch enable. */
bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
bool dataPrefetchEnable; /*!< Data prefetch enable. */
/* ------------------------ Non-secure access settings -------------------------- */
bool nsLockdownEnable; /*!< None-secure lockdown enable. */
bool nsLockdownEnable; /*!< None-secure lockdown enable. */
/* ------------------------ other settings -------------------------------------- */
l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */
l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */
} l2cache_config_t;
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*******************************************************************************
* API
******************************************************************************/
@ -183,7 +157,7 @@ static inline void L1CACHE_InvalidateICache(void)
*
* @param address The start address of the memory to be invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 I-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
@ -240,15 +214,15 @@ static inline void L1CACHE_CleanInvalidateDCache(void)
*
* @param address The start address of the memory to be invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 D-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
uint32_t size = size_byte + address - startAddr;
uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
uint32_t size = size_byte + address - startAddr;
SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size);
}
@ -265,8 +239,8 @@ static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t si
*/
static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
uint32_t size = size_byte + address - startAddr;
uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
uint32_t size = size_byte + address - startAddr;
SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size);
}
@ -283,8 +257,8 @@ static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_by
*/
static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
uint32_t size = size_byte + address - startAddr;
uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
uint32_t size = size_byte + address - startAddr;
SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size);
}
@ -306,7 +280,7 @@ void L2CACHE_Init(l2cache_config_t *config);
/*!
* @brief Gets an available default settings for the cache controller.
*
* This function initializes the cache controller configuration structure with default settings.
* This function initializes the cache controller configuration structure with default settings.
* The default values are:
* @code
* config->waysNum = kL2CACHE_8ways;
@ -316,7 +290,7 @@ void L2CACHE_Init(l2cache_config_t *config);
* config->istrPrefetchEnable = false;
* config->dataPrefetchEnable = false;
* config->nsLockdownEnable = false;
* config->writeAlloc = kL2CACHE_UseAwcache;
* config->writeAlloc = kL2CACHE_UseAwcache;
* @endcode
* @param config Pointer to the configuration structure.
*/
@ -484,7 +458,6 @@ void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
/*@}*/
#if defined(__cplusplus)
}
#endif

56
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2017 - 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -520,7 +520,7 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
/* Initialize the fractional mode */
CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
/* Initialize the spread spectrum mode */
@ -626,7 +626,7 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) |
CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src);
CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator);
/*
@ -713,7 +713,7 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src);
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator);
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator);
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator);
/*
@ -1209,3 +1209,51 @@ void CLOCK_DisableUsbhs1PhyPllClock(void)
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
}
/*!
* brief Use DWT to delay at least for some time.
* Please note that, this API will calculate the microsecond period with the maximum devices
* supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
* delay count was needed, please implement a new timer count to achieve this function.
*
* param delay_us Delay time in unit of microsecond.
*/
__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us)
{
assert(0U != delay_us);
uint64_t count = 0U;
uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000;
/* Make sure the DWT trace fucntion is enabled. */
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
{
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
}
/* CYCCNT not supported on this device. */
assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
/* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */
if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
{
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
}
/* Calculate the count ticks. */
count = DWT->CYCCNT;
count += (uint64_t)period * delay_us;
if (count > 0xFFFFFFFFUL)
{
count -= 0xFFFFFFFFUL;
/* wait for cyccnt overflow. */
while (count < DWT->CYCCNT)
{
}
}
/* Wait for cyccnt reach count value. */
while (count > DWT->CYCCNT)
{
}
}

484
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2017 - 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -39,15 +39,19 @@
/*! @name Driver version */
/*@{*/
/*! @brief CLOCK driver version 2.1.5. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*! @brief CLOCK driver version 2.2.0. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/* Definition for delay API in clock driver, users can redefine it to the real application. */
#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
#endif
/* analog pll definition */
#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
/*@}*/
/*!
@ -75,11 +79,10 @@
#define PLL_AUDIO_OFFSET 0x70
#define PLL_VIDEO_OFFSET 0xA0
#define PLL_ENET_OFFSET 0xE0
#define PLL_USB2_OFFSET 0x20
#define PLL_USB2_OFFSET 0x20
#define CCM_TUPLE(reg, shift, mask, busyShift) \
(int)((reg & 0xFFU) | ((shift) << 8U) | \
((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define CCM_TUPLE(reg, shift, mask, busyShift) \
(int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
@ -100,7 +103,7 @@
* @brief clock1PN frequency.
*/
#define CLKPN_FREQ 0U
/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
*
* The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
@ -300,16 +303,15 @@ extern volatile uint32_t g_rtcXtalFreq;
}
/*! @brief Clock ip name array for PWM. */
#define PWM_CLOCKS \
{ \
{ \
kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \
} \
, {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
{kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
{ \
kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
} \
#define PWM_CLOCKS \
{ \
{kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
{kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
{kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
{kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
{ \
kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
} \
}
/*! @brief Clock ip name array for PXP. */
@ -393,18 +395,18 @@ extern volatile uint32_t g_rtcXtalFreq;
/*! @brief Clock name used to get clock frequency. */
typedef enum _clock_name
{
kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
kCLOCK_PerClk = 0x4U, /*!< PER clock */
kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
kCLOCK_PerClk = 0x4U, /*!< PER clock */
kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
@ -412,7 +414,7 @@ typedef enum _clock_name
kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */
kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */
kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */
kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
@ -436,151 +438,151 @@ typedef enum _clock_ip_name
kCLOCK_IpInvalid = -1,
/* CCM CCGR0 */
kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
/* CCM CCGR1 */
kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */
kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */
kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */
kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */
kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
/* CCM CCGR2 */
kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */
kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */
kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */
kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */
kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */
kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */
kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */
kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */
kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */
kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */
kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */
kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */
kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */
kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */
/* CCM CCGR3 */
kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */
kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */
kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */
kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */
kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */
kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */
kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */
kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */
kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
/* CCM CCGR4 */
kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */
kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */
kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */
kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */
kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */
kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */
kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */
kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */
kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */
kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */
/* CCM CCGR5 */
kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */
kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */
kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
/* CCM CCGR6 */
kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */
kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */
} clock_ip_name_t;
/*! @brief OSC 24M sorce select */
typedef enum _clock_osc
{
kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
} clock_osc_t;
/*! @brief Clock gate value */
typedef enum _clock_gate_value
{
kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
} clock_gate_value_t;
/*! @brief System clock mode */
typedef enum _clock_mode_t
{
kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
} clock_mode_t;
@ -600,7 +602,7 @@ typedef enum _clock_mux
CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
CCM_CBCDR_PERIPH_CLK_SEL_MASK,
CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
@ -608,41 +610,53 @@ typedef enum _clock_mux
CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< semc mux name */
kCLOCK_SemcMux = CCM_TUPLE(
CBCDR_OFFSET, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */
kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
CCM_CBCDR_SEMC_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< semc mux name */
kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
kCLOCK_TraceMux = CCM_TUPLE(
CBCMR_OFFSET, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */
kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
CCM_CBCMR_TRACE_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< trace mux name */
kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
kCLOCK_LpspiMux = CCM_TUPLE(
CBCMR_OFFSET, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
CCM_CBCMR_LPSPI_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
kCLOCK_Sai3Mux = CCM_TUPLE(
CSCMR1_OFFSET, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
kCLOCK_Sai2Mux = CCM_TUPLE(
CSCMR1_OFFSET, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
kCLOCK_Sai1Mux = CCM_TUPLE(
CSCMR1_OFFSET, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
CCM_CSCMR1_SAI3_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
CCM_CSCMR1_SAI2_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
CCM_CSCMR1_SAI1_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< perclk mux name */
@ -651,28 +665,38 @@ typedef enum _clock_mux
CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */
kCLOCK_CanMux = CCM_TUPLE(
CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */
kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
CCM_CSCMR2_CAN_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< can mux name */
kCLOCK_UartMux = CCM_TUPLE(
CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */
kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
CCM_CSCDR1_UART_CLK_SEL_SHIFT,
CCM_CSCDR1_UART_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< uart mux name */
kCLOCK_SpdifMux = CCM_TUPLE(
CDCDR_OFFSET, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */
kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< spdif mux name */
kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
kCLOCK_Lpi2cMux = CCM_TUPLE(
CSCDR2_OFFSET, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */
kCLOCK_CsiMux = CCM_TUPLE(
CSCDR3_OFFSET, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */
kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
CCM_CSCDR3_CSI_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< csi mux name */
} clock_mux_t;
/*!
@ -685,77 +709,101 @@ typedef enum _clock_mux
*/
typedef enum _clock_div
{
kCLOCK_ArmDiv = CCM_TUPLE(
CACRR_OFFSET, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
CCM_CACRR_ARM_PODF_SHIFT,
CCM_CACRR_ARM_PODF_MASK,
CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_SEMC_PODF_SHIFT,
CCM_CBCDR_SEMC_PODF_MASK,
CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
kCLOCK_AhbDiv = CCM_TUPLE(
CBCDR_OFFSET, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
kCLOCK_IpgDiv =
CCM_TUPLE(CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_AHB_PODF_SHIFT,
CCM_CBCDR_AHB_PODF_MASK,
CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
kCLOCK_IpgDiv = CCM_TUPLE(
CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
kCLOCK_LpspiDiv = CCM_TUPLE(
CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
kCLOCK_LcdifDiv = CCM_TUPLE(
CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
kCLOCK_FlexspiDiv = CCM_TUPLE(
CSCMR1_OFFSET, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */
kCLOCK_PerclkDiv = CCM_TUPLE(
CSCMR1_OFFSET, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */
kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
CCM_CSCMR1_FLEXSPI_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< flexspi div name */
kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_PERCLK_PODF_SHIFT,
CCM_CSCMR1_PERCLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< perclk div name */
kCLOCK_CanDiv = CCM_TUPLE(
CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */
kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
CCM_CSCMR2_CAN_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< can div name */
kCLOCK_TraceDiv = CCM_TUPLE(
CSCDR1_OFFSET, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */
kCLOCK_Usdhc2Div = CCM_TUPLE(
CSCDR1_OFFSET, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
kCLOCK_Usdhc1Div = CCM_TUPLE(
CSCDR1_OFFSET, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
kCLOCK_UartDiv = CCM_TUPLE(
CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */
kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
CCM_CSCDR1_TRACE_PODF_SHIFT,
CCM_CSCDR1_TRACE_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< trace div name */
kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
CCM_CSCDR1_USDHC2_PODF_SHIFT,
CCM_CSCDR1_USDHC2_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
CCM_CSCDR1_USDHC1_PODF_SHIFT,
CCM_CSCDR1_USDHC1_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
CCM_CSCDR1_UART_CLK_PODF_SHIFT,
CCM_CSCDR1_UART_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< uart div name */
kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */
kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
CCM_CS1CDR_SAI3_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
kCLOCK_Sai3Div = CCM_TUPLE(
CS1CDR_OFFSET, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */
kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
CCM_CS1CDR_SAI3_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< sai3 div name */
kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
CCM_CS1CDR_SAI1_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
kCLOCK_Sai1Div = CCM_TUPLE(
CS1CDR_OFFSET, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */
kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
CCM_CS1CDR_SAI1_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< sai1 div name */
kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
CCM_CS2CDR_SAI2_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
kCLOCK_Sai2Div = CCM_TUPLE(
CS2CDR_OFFSET, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */
kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
CCM_CS2CDR_SAI2_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< sai2 div name */
kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< spdif div name */
@ -763,26 +811,28 @@ typedef enum _clock_div
CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio1 div name */
kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
kCLOCK_LcdifPreDiv = CCM_TUPLE(
CSCDR2_OFFSET, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
CCM_CSCDR2_LCDIF_PRED_SHIFT,
CCM_CSCDR2_LCDIF_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
kCLOCK_CsiDiv =
CCM_TUPLE(CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
kCLOCK_CsiDiv = CCM_TUPLE(
CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
} clock_div_t;
/*! @brief USB clock source definition. */
typedef enum _clock_usb_src
{
kCLOCK_Usb480M = 0, /*!< Use 480M. */
kCLOCK_Usb480M = 0, /*!< Use 480M. */
kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
care the clock source. */
} clock_usb_src_t;
@ -797,7 +847,7 @@ typedef enum _clock_usb_phy_src
enum _clock_pll_clk_src
{
kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
};
/*! @brief PLL configuration for ARM */
@ -871,9 +921,9 @@ typedef struct _clock_enet_pll_config
/*! @brief PLL name */
typedef enum _clock_pll
{
kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
@ -912,7 +962,7 @@ static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
{
uint32_t busyShift;
busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
(((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
@ -949,7 +999,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
{
uint32_t busyShift;
busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
(((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
@ -989,7 +1039,7 @@ static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t va
assert(index <= 6);
reg = ((volatile uint32_t *)&CCM->CCGR0) + index;
reg = ((volatile uint32_t *)&CCM->CCGR0) + index;
*reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift);
}
@ -1489,6 +1539,16 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
*/
void CLOCK_DisableUsbhs1PhyPllClock(void);
/*!
* @brief Use DWT to delay at least for some time.
* Please note that, this API will calculate the microsecond period with the maximum
* supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
* delay count was needed, please implement a new timer count to achieve this function.
*
* @param delay_us Delay time in unit of microsecond.
*/
void SDK_DelayAtLeastUs(uint32_t delay_us);
/* @} */
#if defined(__cplusplus)

194
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cmp.h"
@ -39,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.cmp"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -81,6 +54,19 @@ static uint32_t CMP_GetInstance(CMP_Type *base)
return instance;
}
/*!
* brief Initializes the CMP.
*
* This function initializes the CMP module. The operations included are as follows.
* - Enabling the clock for CMP module.
* - Configuring the comparator.
* - Enabling the CMP module.
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
* any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
*
* param base CMP peripheral base address.
* param config Pointer to the configuration structure.
*/
void CMP_Init(CMP_Type *base, const cmp_config_t *config)
{
assert(NULL != config);
@ -95,43 +81,56 @@ void CMP_Init(CMP_Type *base, const cmp_config_t *config)
/* Configure. */
CMP_Enable(base, false); /* Disable the CMP module during configuring. */
/* CMPx_CR1. */
tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK);
if (config->enableHighSpeed)
tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK));
if (true == config->enableHighSpeed)
{
tmp8 |= CMP_CR1_PMODE_MASK;
}
if (config->enableInvertOutput)
if (true == config->enableInvertOutput)
{
tmp8 |= CMP_CR1_INV_MASK;
}
if (config->useUnfilteredOutput)
if (true == config->useUnfilteredOutput)
{
tmp8 |= CMP_CR1_COS_MASK;
}
if (config->enablePinOut)
if (true == config->enablePinOut)
{
tmp8 |= CMP_CR1_OPE_MASK;
}
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
if (config->enableTriggerMode)
if (true == config->enableTriggerMode)
{
tmp8 |= CMP_CR1_TRIGM_MASK;
}
else
{
tmp8 &= ~CMP_CR1_TRIGM_MASK;
tmp8 &= ~(uint8_t)CMP_CR1_TRIGM_MASK;
}
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
base->CR1 = tmp8;
/* CMPx_CR0. */
tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK;
tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK;
tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
base->CR0 = tmp8;
CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
}
/*!
* brief De-initializes the CMP module.
*
* This function de-initializes the CMP module. The operations included are as follows.
* - Disabling the CMP module.
* - Disabling the clock for CMP module.
*
* This function disables the clock for the CMP.
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
* clock for the CMP, ensure that all the CMP instances are not used.
*
* param base CMP peripheral base address.
*/
void CMP_Deinit(CMP_Type *base)
{
/* Disable the CMP module. */
@ -143,34 +142,74 @@ void CMP_Deinit(CMP_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Initializes the CMP user configuration structure.
*
* This function initializes the user configuration structure to these default values.
* code
* config->enableCmp = true;
* config->hysteresisMode = kCMP_HysteresisLevel0;
* config->enableHighSpeed = false;
* config->enableInvertOutput = false;
* config->useUnfilteredOutput = false;
* config->enablePinOut = false;
* config->enableTriggerMode = false;
* endcode
* param config Pointer to the configuration structure.
*/
void CMP_GetDefaultConfig(cmp_config_t *config)
{
assert(NULL != config);
config->enableCmp = true; /* Enable the CMP module after initialization. */
config->hysteresisMode = kCMP_HysteresisLevel0;
config->enableHighSpeed = false;
config->enableInvertOutput = false;
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->enableCmp = true; /* Enable the CMP module after initialization. */
config->hysteresisMode = kCMP_HysteresisLevel0;
config->enableHighSpeed = false;
config->enableInvertOutput = false;
config->useUnfilteredOutput = false;
config->enablePinOut = false;
config->enablePinOut = false;
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
config->enableTriggerMode = false;
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
}
/*!
* brief Sets the input channels for the comparator.
*
* This function sets the input channels for the comparator.
* Note that two input channels cannot be set the same way in the application. When the user selects the same input
* from the analog mux to the positive and negative port, the comparator is disabled automatically.
*
* param base CMP peripheral base address.
* param positiveChannel Positive side input channel number. Available range is 0-7.
* param negativeChannel Negative side input channel number. Available range is 0-7.
*/
void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
{
uint8_t tmp8 = base->MUXCR;
tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
tmp8 &= ~(uint8_t)(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
base->MUXCR = tmp8;
}
#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
/*!
* brief Enables/disables the DMA request for rising/falling events.
*
* This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
* the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
* the CMP
* if the DMA is disabled.
*
* param base CMP peripheral base address.
* param enable Enables or disables the feature.
*/
void CMP_EnableDMA(CMP_Type *base, bool enable)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
if (enable)
{
@ -178,12 +217,18 @@ void CMP_EnableDMA(CMP_Type *base, bool enable)
}
else
{
tmp8 &= ~CMP_SCR_DMAEN_MASK;
tmp8 &= ~(uint8_t)CMP_SCR_DMAEN_MASK;
}
base->SCR = tmp8;
}
#endif /* FSL_FEATURE_CMP_HAS_DMA */
/*!
* brief Configures the filter.
*
* param base CMP peripheral base address.
* param config Pointer to the configuration structure.
*/
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
{
assert(NULL != config);
@ -202,13 +247,19 @@ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
}
#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
/* Set the filter count. */
tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
tmp8 = (uint8_t)(base->CR0 & ~CMP_CR0_FILTER_CNT_MASK);
tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
base->CR0 = tmp8;
/* Set the filter period. It is used as the divider to bus clock. */
base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
}
/*!
* brief Configures the internal DAC.
*
* param base CMP peripheral base address.
* param config Pointer to the configuration structure. "NULL" disables the feature.
*/
void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
{
uint8_t tmp8 = 0U;
@ -230,64 +281,89 @@ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
base->DACCR = tmp8;
}
/*!
* brief Enables the interrupts.
*
* param base CMP peripheral base address.
* param mask Mask value for interrupts. See "_cmp_interrupt_enable".
*/
void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
if (0U != (kCMP_OutputRisingInterruptEnable & mask))
if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
{
tmp8 |= CMP_SCR_IER_MASK;
}
if (0U != (kCMP_OutputFallingInterruptEnable & mask))
if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
{
tmp8 |= CMP_SCR_IEF_MASK;
}
base->SCR = tmp8;
}
/*!
* brief Disables the interrupts.
*
* param base CMP peripheral base address.
* param mask Mask value for interrupts. See "_cmp_interrupt_enable".
*/
void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
if (0U != (kCMP_OutputRisingInterruptEnable & mask))
if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
{
tmp8 &= ~CMP_SCR_IER_MASK;
tmp8 &= ~(uint8_t)CMP_SCR_IER_MASK;
}
if (0U != (kCMP_OutputFallingInterruptEnable & mask))
if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
{
tmp8 &= ~CMP_SCR_IEF_MASK;
tmp8 &= ~(uint8_t)CMP_SCR_IEF_MASK;
}
base->SCR = tmp8;
}
/*!
* brief Gets the status flags.
*
* param base CMP peripheral base address.
*
* return Mask value for the asserted flags. See "_cmp_status_flags".
*/
uint32_t CMP_GetStatusFlags(CMP_Type *base)
{
uint32_t ret32 = 0U;
if (0U != (CMP_SCR_CFR_MASK & base->SCR))
{
ret32 |= kCMP_OutputRisingEventFlag;
ret32 |= (uint32_t)kCMP_OutputRisingEventFlag;
}
if (0U != (CMP_SCR_CFF_MASK & base->SCR))
{
ret32 |= kCMP_OutputFallingEventFlag;
ret32 |= (uint32_t)kCMP_OutputFallingEventFlag;
}
if (0U != (CMP_SCR_COUT_MASK & base->SCR))
{
ret32 |= kCMP_OutputAssertEventFlag;
ret32 |= (uint32_t)kCMP_OutputAssertEventFlag;
}
return ret32;
}
/*!
* brief Clears the status flags.
*
* param base CMP peripheral base address.
* param mask Mask value for the flags. See "_cmp_status_flags".
*/
void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
{
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
if (0U != (kCMP_OutputRisingEventFlag & mask))
if (0U != ((uint32_t)kCMP_OutputRisingEventFlag & mask))
{
tmp8 |= CMP_SCR_CFR_MASK;
}
if (0U != (kCMP_OutputFallingEventFlag & mask))
if (0U != ((uint32_t)kCMP_OutputFallingEventFlag & mask))
{
tmp8 |= CMP_SCR_CFF_MASK;
}

82
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CMP_H_
@ -42,23 +16,22 @@
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CMP driver version 2.0.0. */
#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*! @brief CMP driver version 2.0.1. */
#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*!
* @brief Interrupt enable/disable mask.
*/
* @brief Interrupt enable/disable mask.
*/
enum _cmp_interrupt_enable
{
kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */
kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */
kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */
};
@ -67,9 +40,9 @@ enum _cmp_interrupt_enable
*/
enum _cmp_status_flags
{
kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */
kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */
kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */
kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */
kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
};
/*!
@ -126,7 +99,7 @@ typedef struct _cmp_filter_config
typedef struct _cmp_dac_config
{
cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
} cmp_dac_config_t;
#if defined(__cplusplus)
@ -186,25 +159,25 @@ static inline void CMP_Enable(CMP_Type *base, bool enable)
}
else
{
base->CR1 &= ~CMP_CR1_EN_MASK;
base->CR1 &= ~(uint8_t)CMP_CR1_EN_MASK;
}
}
/*!
* @brief Initializes the CMP user configuration structure.
*
* This function initializes the user configuration structure to these default values.
* @code
* config->enableCmp = true;
* config->hysteresisMode = kCMP_HysteresisLevel0;
* config->enableHighSpeed = false;
* config->enableInvertOutput = false;
* config->useUnfilteredOutput = false;
* config->enablePinOut = false;
* config->enableTriggerMode = false;
* @endcode
* @param config Pointer to the configuration structure.
*/
* @brief Initializes the CMP user configuration structure.
*
* This function initializes the user configuration structure to these default values.
* @code
* config->enableCmp = true;
* config->hysteresisMode = kCMP_HysteresisLevel0;
* config->enableHighSpeed = false;
* config->enableInvertOutput = false;
* config->useUnfilteredOutput = false;
* config->enablePinOut = false;
* config->enableTriggerMode = false;
* @endcode
* @param config Pointer to the configuration structure.
*/
void CMP_GetDefaultConfig(cmp_config_t *config);
/*!
@ -232,7 +205,8 @@ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negat
* @brief Enables/disables the DMA request for rising/falling events.
*
* This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
* the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
* the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
* the CMP
* if the DMA is disabled.
*
* @param base CMP peripheral base address.

107
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c
View File

@ -1,45 +1,19 @@
/*
* The Clear BSD License
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#define SDK_MEM_MAGIC_NUMBER 12345U
#define SDK_MEM_MAGIC_NUMBER 12345U
typedef struct _mem_align_control_block
{
uint16_t identifier; /*!< Identifier for the memory control block. */
uint16_t offset; /*!< offset from aligned adress to real address */
uint16_t identifier; /*!< Identifier for the memory control block. */
uint16_t offset; /*!< offset from aligned address to real address */
} mem_align_cb_t;
/* Component ID definition, used by tools. */
@ -47,13 +21,12 @@ typedef struct _mem_align_control_block
#define FSL_COMPONENT_ID "platform.drivers.common"
#endif
#ifndef __GIC_PRIO_BITS
#if defined(ENABLE_RAM_VECTOR_TABLE)
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
@ -70,7 +43,7 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) */
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
@ -104,30 +77,22 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#endif /* __GIC_PRIO_BITS. */
#ifndef QN908XC_SERIES
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
{
SYSCON->STARTERP1 = 1u << intNumber;
}
#else
{
uint32_t index = 0;
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
SYSCON->STARTERSET[index] = 1u << intNumber;
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
@ -136,28 +101,19 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
uint32_t intNumber = (uint32_t)interrupt;
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
{
SYSCON->STARTERP1 &= ~(1u << intNumber);
}
#else
{
uint32_t index = 0;
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERCLR[index] = 1u << intNumber;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#endif /* QN908XC_SERIES */
void *SDK_Malloc(size_t size, size_t alignbytes)
{
mem_align_cb_t *p_cb = NULL;
@ -171,16 +127,16 @@ void *SDK_Malloc(size_t size, size_t alignbytes)
p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U);
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
return (void *)p_align_addr;
}
void SDK_Free(void *ptr)
{
mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U);
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
{
@ -189,4 +145,3 @@ void SDK_Free(void *ptr)
free((void *)((uint32_t)ptr - p_cb->offset));
}

174
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_COMMON_H_
@ -64,21 +38,21 @@
/*! @name Driver version */
/*@{*/
/*! @brief common driver version 2.0.0. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*! @brief common driver version 2.0.1. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
/*! @brief Status group numbers. */
enum _status_groups
@ -142,15 +116,43 @@ enum _status_groups
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
};
/*! @brief Generic status return codes. */
@ -168,20 +170,6 @@ enum _generic_status
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
/*
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
* defined in previous of this file.
*/
#include "fsl_clock.h"
/*
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
*/
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
#include "fsl_reset.h"
#endif
/*
* Macro guard for whether to use default weak IRQ implementation in drivers
*/
@ -192,11 +180,11 @@ typedef int32_t status_t;
/*! @name Min/max macros */
/* @{ */
#if !defined(MIN)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#if !defined(MAX)
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* @} */
@ -295,7 +283,7 @@ _Pragma("diag_suppress=Pm120")
*/
/* @{ */
#if (defined(__ICCARM__))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
@ -307,7 +295,7 @@ _Pragma("diag_suppress=Pm120")
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
#endif
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
@ -324,7 +312,7 @@ _Pragma("diag_suppress=Pm120")
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*/
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
@ -347,6 +335,61 @@ _Pragma("diag_suppress=Pm120")
/* @} */
/*! @name Time sensitive region */
/* @{ */
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) __ramfunc func
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
#elif(defined(__GNUC__))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
#else
#error Toolchain not supported.
#endif /* defined(__ICCARM__) */
#else
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#elif(defined(__GNUC__))
#define AT_QUICKACCESS_SECTION_CODE(func) func
#define AT_QUICKACCESS_SECTION_DATA(func) func
#else
#error Toolchain not supported.
#endif
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
/* @} */
/*! @name Ram Function */
#if (defined(__ICCARM__))
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#elif(defined(__GNUC__))
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
#else
#error Toolchain not supported.
#endif /* defined(__ICCARM__) */
/* @} */
/*
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
* defined in previous of this file.
*/
#include "fsl_clock.h"
/*
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
*/
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
#include "fsl_reset.h"
#endif
/*******************************************************************************
* API
@ -443,6 +486,9 @@ _Pragma("diag_suppress=Pm120")
*/
static inline uint32_t DisableGlobalIRQ(void)
{
#if defined (__XCC__)
return 0;
#else
#if defined(CPSR_I_Msk)
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
@ -455,6 +501,7 @@ _Pragma("diag_suppress=Pm120")
__disable_irq();
return regPrimask;
#endif
#endif
}
@ -470,10 +517,13 @@ _Pragma("diag_suppress=Pm120")
*/
static inline void EnableGlobalIRQ(uint32_t primask)
{
#if defined (__XCC__)
#else
#if defined(CPSR_I_Msk)
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
#else
__set_PRIMASK(primask);
#endif
#endif
}
@ -498,7 +548,7 @@ _Pragma("diag_suppress=Pm120")
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
*
* @param interrupt The IRQ number.
*/
@ -513,7 +563,7 @@ _Pragma("diag_suppress=Pm120")
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
*
* @param interrupt The IRQ number.
*/

713
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c
View File

@ -1,38 +1,15 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* Copyright 2017-2018 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_csi.h"
#if CSI_DRIVER_FRAG_MODE
#include "fsl_cache.h"
#endif
/*******************************************************************************
* Definitions
@ -43,13 +20,16 @@
#define FSL_COMPONENT_ID "platform.drivers.csi"
#endif
/* Two frame buffer loaded to CSI register at most. */
#define CSI_MAX_ACTIVE_FRAME_NUM 2
/* CSI driver only support RGB565 and YUV422 in fragment mode, 2 bytes per pixel. */
#define CSI_FRAG_INPUT_BYTES_PER_PIXEL 2
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the instance from the base address
*
@ -59,6 +39,7 @@
*/
static uint32_t CSI_GetInstance(CSI_Type *base);
#if !CSI_DRIVER_FRAG_MODE
/*!
* @brief Get the delta value of two index in queue.
*
@ -105,6 +86,12 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle)
/* Typedef for interrupt handler. */
typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle);
#else
/* Typedef for interrupt handler to work in fragment mode. */
typedef void (*csi_isr_t)(CSI_Type *base, csi_frag_handle_t *handle);
#endif /* CSI_DRIVER_FRAG_MODE */
/*******************************************************************************
* Variables
******************************************************************************/
@ -117,7 +104,11 @@ static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Array for the CSI driver handle. */
#if !CSI_DRIVER_FRAG_MODE
static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
#else
static csi_frag_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
#endif
/* Array of CSI IRQ number. */
static const IRQn_Type s_csiIRQ[] = CSI_IRQS;
@ -146,6 +137,7 @@ static uint32_t CSI_GetInstance(CSI_Type *base)
return instance;
}
#if !CSI_DRIVER_FRAG_MODE
static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx)
{
if (endIdx >= startIdx)
@ -154,7 +146,7 @@ static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx)
}
else
{
return startIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - endIdx;
return endIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - startIdx;
}
}
@ -195,7 +187,19 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle)
/* There are two CSI buffers, so could use XOR to get the next index. */
handle->nextBufferIdx ^= 1U;
}
#endif /* CSI_DRIVER_FRAG_MODE */
/*!
* brief Initialize the CSI.
*
* This function enables the CSI peripheral clock, and resets the CSI registers.
*
* param base CSI peripheral base address.
* param config Pointer to the configuration structure.
*
* retval kStatus_Success Initialize successfully.
* retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
{
assert(config);
@ -288,6 +292,13 @@ status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
return kStatus_Success;
}
/*!
* brief De-initialize the CSI.
*
* This function disables the CSI peripheral clock.
*
* param base CSI peripheral base address.
*/
void CSI_Deinit(CSI_Type *base)
{
/* Disable transfer first. */
@ -298,6 +309,13 @@ void CSI_Deinit(CSI_Type *base)
#endif
}
/*!
* brief Reset the CSI.
*
* This function resets the CSI peripheral registers to default status.
*
* param base CSI peripheral base address.
*/
void CSI_Reset(CSI_Type *base)
{
uint32_t csisr;
@ -321,7 +339,7 @@ void CSI_Reset(CSI_Type *base)
CSI_ReflashFifoDma(base, kCSI_AllFifo);
/* Clear the status. */
csisr = base->CSISR;
csisr = base->CSISR;
base->CSISR = csisr;
/* Set the control registers to default value. */
@ -337,10 +355,12 @@ void CSI_Reset(CSI_Type *base)
base->CSIIMAG_PARA = 0U;
}
void CSI_GetDefaultConfig(csi_config_t *config)
{
assert(config);
/*!
* brief Get the default configuration for to initialize the CSI.
*
* The default configuration value is:
*
* code
config->width = 320U;
config->height = 240U;
config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
@ -349,8 +369,34 @@ void CSI_GetDefaultConfig(csi_config_t *config)
config->workMode = kCSI_GatedClockMode;
config->dataBus = kCSI_DataBus8Bit;
config->useExtVsync = true;
endcode
*
* param config Pointer to the CSI configuration.
*/
void CSI_GetDefaultConfig(csi_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->width = 320U;
config->height = 240U;
config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
config->bytesPerPixel = 2U;
config->linePitch_Bytes = 320U * 2U;
config->workMode = kCSI_GatedClockMode;
config->dataBus = kCSI_DataBus8Bit;
config->useExtVsync = true;
}
/*!
* brief Set the RX frame buffer address.
*
* param base CSI peripheral base address.
* param index Buffer index.
* param addr Frame buffer address to set.
*/
void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
{
if (index)
@ -363,13 +409,21 @@ void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
}
}
/*!
* brief Clear the CSI FIFO.
*
* This function clears the CSI FIFO.
*
* param base CSI peripheral base address.
* param fifo The FIFO to clear.
*/
void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
{
uint32_t cr1;
uint32_t mask = 0U;
/* The FIFO could only be cleared when CSICR1[FCC] = 0, so first clear the FCC. */
cr1 = base->CSICR1;
cr1 = base->CSICR1;
base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK);
if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo)
@ -393,6 +447,19 @@ void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
base->CSICR1 = cr1;
}
/*!
* brief Reflash the CSI FIFO DMA.
*
* This function reflashes the CSI FIFO DMA.
*
* For RXFIFO, there are two frame buffers. When the CSI module started, it saves
* the frames to frame buffer 0 then frame buffer 1, the two buffers will be
* written by turns. After reflash DMA using this function, the CSI is reset to
* save frame to buffer 0.
*
* param base CSI peripheral base address.
* param fifo The FIFO DMA to reflash.
*/
void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
{
uint32_t cr3 = 0U;
@ -415,6 +482,13 @@ void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
}
}
/*!
* brief Enable or disable the CSI FIFO DMA request.
*
* param base CSI peripheral base address.
* param fifo The FIFO DMA reques to enable or disable.
* param enable True to enable, false to disable.
*/
void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
{
uint32_t cr3 = 0U;
@ -439,6 +513,12 @@ void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
}
}
/*!
* brief Enables CSI interrupt requests.
*
* param base CSI peripheral base address.
* param mask The interrupts to enable, pass in as OR'ed value of ref _csi_interrupt_enable.
*/
void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
{
base->CSICR1 |= (mask & CSI_CSICR1_INT_EN_MASK);
@ -446,6 +526,12 @@ void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
base->CSICR18 |= ((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
}
/*!
* brief Disable CSI interrupt requests.
*
* param base CSI peripheral base address.
* param mask The interrupts to disable, pass in as OR'ed value of ref _csi_interrupt_enable.
*/
void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
{
base->CSICR1 &= ~(mask & CSI_CSICR1_INT_EN_MASK);
@ -453,6 +539,20 @@ void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
base->CSICR18 &= ~((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
}
#if !CSI_DRIVER_FRAG_MODE
/*!
* brief Initializes the CSI handle.
*
* This function initializes CSI handle, it should be called before any other
* CSI transactional functions.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
* param callback Callback function for CSI transfer.
* param userData Callback function parameter.
*
* retval kStatus_Success Handle created successfully.
*/
status_t CSI_TransferCreateHandle(CSI_Type *base,
csi_handle_t *handle,
csi_transfer_callback_t callback,
@ -481,6 +581,20 @@ status_t CSI_TransferCreateHandle(CSI_Type *base,
return kStatus_Success;
}
/*!
* brief Start the transfer using transactional functions.
*
* When the empty frame buffers have been submit to CSI driver using function
* ref CSI_TransferSubmitEmptyBuffer, user could call this function to start
* the transfer. The incoming frame will be saved to the empty frame buffer,
* and user could be optionally notified through callback function.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
*
* retval kStatus_Success Started successfully.
* retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue.
*/
status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
{
assert(handle);
@ -494,11 +608,16 @@ status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
return kStatus_CSI_NoEmptyBuffer;
}
handle->nextBufferIdx = 0U;
handle->nextBufferIdx = 0U;
handle->activeBufferNum = 0U;
/* Write to memory from second completed frame. */
base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(2);
/*
* Write to memory from first completed frame.
* DMA base addr switch at the edge of the first data of each frame, thus
* if one frame is broken, it could be reset at the next frame.
*/
base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0) |
CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK | CSI_CSICR18_BASEADDR_SWITCH_EN_MASK;
/* Load the frame buffer to CSI register, there are at least two empty buffers. */
CSI_TransferLoadBufferToDevice(base, handle);
@ -517,6 +636,18 @@ status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
return kStatus_Success;
}
/*!
* brief Stop the transfer using transactional functions.
*
* The driver does not clean the full frame buffers in queue. In other words, after
* calling this function, user still could get the full frame buffers in queue
* using function ref CSI_TransferGetFullBuffer.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
*
* retval kStatus_Success Stoped successfully.
*/
status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
{
assert(handle);
@ -534,6 +665,20 @@ status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
return kStatus_Success;
}
/*!
* brief Submit empty frame buffer to queue.
*
* This function could be called before ref CSI_TransferStart or after ref
* CSI_TransferStart. If there is no room in queue to store the empty frame
* buffer, this function returns error.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
* param frameBuffer Empty frame buffer to submit.
*
* retval kStatus_Success Started successfully.
* retval kStatus_CSI_QueueFull Could not submit because there is no room in queue.
*/
status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer)
{
uint32_t csicr1;
@ -550,7 +695,16 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin
/* Save the empty frame buffer address to queue. */
handle->frameBufferQueue[handle->queueUserWriteIdx] = frameBuffer;
handle->queueUserWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserWriteIdx);
handle->queueUserWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserWriteIdx);
/*
* If transfer is ongoing and an active slot is available, Load the buffer
* now to prevent buffer starvation during next TransferHandleIRQ event.
*/
if (handle->transferOnGoing && handle->activeBufferNum < CSI_MAX_ACTIVE_FRAME_NUM)
{
CSI_TransferLoadBufferToDevice(base, handle);
}
base->CSICR1 = csicr1;
@ -563,7 +717,7 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin
if ((!handle->transferOnGoing) && (CSI_TransferGetEmptyBufferCount(base, handle) >= 2U))
{
handle->transferOnGoing = true;
handle->nextBufferIdx = 0U;
handle->nextBufferIdx = 0U;
/* Load the frame buffers to CSI module. */
CSI_TransferLoadBufferToDevice(base, handle);
@ -576,6 +730,21 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin
return kStatus_Success;
}
/*!
* brief Get one full frame buffer from queue.
*
* After the transfer started using function ref CSI_TransferStart, the incoming
* frames will be saved to the empty frame buffers in queue. This function gets
* the full-filled frame buffer from the queue. If there is no full frame buffer
* in queue, this function returns error.
*
* param base CSI peripheral base address.
* param handle Pointer to the handle structure.
* param frameBuffer Full frame buffer.
*
* retval kStatus_Success Started successfully.
* retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue.
*/
status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer)
{
uint32_t csicr1;
@ -600,6 +769,15 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_
return kStatus_Success;
}
/*!
* brief CSI IRQ handle function.
*
* This function handles the CSI IRQ request to work with CSI driver transactional
* APIs.
*
* param base CSI peripheral base address.
* param handle CSI handle pointer.
*/
void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
{
uint32_t queueDrvWriteIdx;
@ -627,8 +805,8 @@ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
if (2U == handle->activeBufferNum)
{
queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(queueDrvWriteIdx);
base->CSIDMASA_FB2 = handle->frameBufferQueue[queueDrvWriteIdx];
queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(queueDrvWriteIdx);
base->CSIDMASA_FB2 = handle->frameBufferQueue[queueDrvWriteIdx];
handle->nextBufferIdx = 0U;
}
else
@ -669,6 +847,455 @@ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
}
}
#else /* CSI_DRIVER_FRAG_MODE */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
__asm void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
push {r4-r7, lr}
10
LDMIA R1!, {r3-r6}
bfi r7, r3, #0, #8 /* Y0 */
bfi ip, r5, #0, #8 /* Y4 */
lsr r3, r3, #16
lsr r5, r5, #16
bfi r7, r3, #8, #8 /* Y1 */
bfi ip, r5, #8, #8 /* Y5 */
bfi r7, r4, #16, #8 /* Y2 */
bfi ip, r6, #16, #8 /* Y6 */
lsr r4, r4, #16
lsr r6, r6, #16
bfi r7, r4, #24, #8 /* Y3 */
bfi ip, r6, #24, #8 /* Y7 */
STMIA r0!, {r7, ip}
subs r2, #8
bne %b10
pop {r4-r7, pc}
/* clang-format on */
}
__asm void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
push {r4-r7, lr}
10
LDMIA R1!, {r3-r6}
lsr r3, r3, #8
lsr r5, r5, #8
bfi r7, r3, #0, #8 /* Y0 */
bfi ip, r5, #0, #8 /* Y4 */
lsr r3, r3, #16
lsr r5, r5, #16
bfi r7, r3, #8, #8 /* Y1 */
bfi ip, r5, #8, #8 /* Y5 */
lsr r4, r4, #8
lsr r6, r6, #8
bfi r7, r4, #16, #8 /* Y2 */
bfi ip, r6, #16, #8 /* Y6 */
lsr r4, r4, #16
lsr r6, r6, #16
bfi r7, r4, #24, #8 /* Y3 */
bfi ip, r6, #24, #8 /* Y7 */
STMIA r0!, {r7, ip}
subs r2, #8
bne %b10
pop {r4-r7, pc}
/* clang-format on */
}
#elif (defined(__GNUC__) || defined(__ICCARM__))
#if defined(__ICCARM__)
#pragma diag_suppress = Pe940
#endif
__attribute__((naked)) void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
__asm volatile(
" push {r1-r7, r12, lr} \n"
"loop0: \n"
" ldmia r1!, {r3-r6} \n"
" bfi r7, r3, #0, #8 \n" /* Y0 */
" bfi r12, r5, #0, #8 \n" /* Y4 */
" lsr r3, r3, #16 \n"
" lsr r5, r5, #16 \n"
" bfi r7, r3, #8, #8 \n" /* Y1 */
" bfi r12, r5, #8, #8 \n" /* Y5 */
" bfi r7, r4, #16, #8 \n" /* Y2 */
" bfi r12, r6, #16, #8 \n" /* Y6 */
" lsr r4, r4, #16 \n"
" lsr r6, r6, #16 \n"
" bfi r7, r4, #24, #8 \n" /* Y3 */
" bfi r12, r6, #24, #8 \n" /* Y7 */
" stmia r0!, {r7, r12} \n"
" subs r2, #8 \n"
" bne loop0 \n"
" pop {r1-r7, r12, pc} \n");
/* clang-format on */
}
__attribute__((naked)) void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
{
/* clang-format off */
__asm volatile(
" push {r1-r7, r12, lr} \n"
"loop1: \n"
" ldmia r1!, {r3-r6} \n"
" lsr r3, r3, #8 \n"
" lsr r5, r5, #8 \n"
" bfi r7, r3, #0, #8 \n" /* Y0 */
" bfi r12, r5, #0, #8 \n" /* Y4 */
" lsr r3, r3, #16 \n"
" lsr r5, r5, #16 \n"
" bfi r7, r3, #8, #8 \n" /* Y1 */
" bfi r12, r5, #8, #8 \n" /* Y5 */
" lsr r4, r4, #8 \n"
" lsr r6, r6, #8 \n"
" bfi r7, r4, #16, #8 \n" /* Y2 */
" bfi r12, r6, #16, #8 \n" /* Y6 */
" lsr r4, r4, #16 \n"
" lsr r6, r6, #16 \n"
" bfi r7, r4, #24, #8 \n" /* Y3 */
" bfi r12, r6, #24, #8 \n" /* Y7 */
" stmia r0!, {r7, r12} \n"
" subs r2, #8 \n"
" bne loop1 \n"
" pop {r1-r7, r12, pc} \n");
/* clang-format on */
}
#if defined(__ICCARM__)
#pragma diag_default = Pe940
#endif
#else
#error Toolchain not supported.
#endif
static void CSI_MemCopy(void *pDest, const void *pSrc, size_t cnt)
{
memcpy(pDest, pSrc, cnt);
}
/*!
* brief Initialize the CSI to work in fragment mode.
*
* This function enables the CSI peripheral clock, and resets the CSI registers.
*
* param base CSI peripheral base address.
*/
void CSI_FragModeInit(CSI_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = CSI_GetInstance(base);
CLOCK_EnableClock(s_csiClocks[instance]);
#endif
CSI_Reset(base);
}
/*!
* brief De-initialize the CSI.
*
* This function disables the CSI peripheral clock.
*
* param base CSI peripheral base address.
*/
void CSI_FragModeDeinit(CSI_Type *base)
{
CSI_Deinit(base);
}
/*!
* brief Create handle for CSI work in fragment mode.
*
* param base CSI peripheral base address.
* param handle Pointer to the transactional handle.
* param config Pointer to the configuration structure.
* param callback Callback function for CSI transfer.
* param userData Callback function parameter.
*
* retval kStatus_Success Initialize successfully.
* retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeCreateHandle(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_config_t *config,
csi_frag_transfer_callback_t callback,
void *userData)
{
assert(config);
uint32_t reg;
uint32_t instance;
uint32_t imgWidth_Bytes;
imgWidth_Bytes = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
/* The image buffer line width should be multiple of 8-bytes. */
if ((imgWidth_Bytes & 0x07) != 0)
{
return kStatus_InvalidArgument;
}
/* Camera frame height must be dividable by DMA buffer line. */
if (config->height % config->dmaBufferLine != 0)
{
return kStatus_InvalidArgument;
}
memset(handle, 0, sizeof(*handle));
handle->callback = callback;
handle->userData = userData;
handle->height = config->height;
handle->width = config->width;
handle->maxLinePerFrag = config->dmaBufferLine;
handle->dmaBytePerLine = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
handle->isDmaBufferCachable = config->isDmaBufferCachable;
/* Get instance from peripheral base address. */
instance = CSI_GetInstance(base);
/* Save the handle in global variables to support the double weak mechanism. */
s_csiHandle[instance] = handle;
s_csiIsr = CSI_FragModeTransferHandleIRQ;
EnableIRQ(s_csiIRQ[instance]);
/* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */
reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK;
if (config->useExtVsync)
{
reg |= CSI_CSICR1_EXT_VSYNC_MASK;
}
base->CSICR1 = reg;
/* No stride. */
base->CSIFBUF_PARA = 0;
/* Enable auto ECC. */
base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK;
/*
* For better performance.
* The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte,
* choose the best burst size based on bytes per line.
*/
if (!(imgWidth_Bytes % (8 * 16)))
{
base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U);
base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
}
else if (!(imgWidth_Bytes % (8 * 8)))
{
base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U);
base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
}
else
{
base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U);
base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
}
base->CSIDMASA_FB1 = config->dmaBufferAddr0;
base->CSIDMASA_FB2 = config->dmaBufferAddr1;
if (handle->isDmaBufferCachable)
{
DCACHE_CleanInvalidateByRange(config->dmaBufferAddr0,
config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
DCACHE_CleanInvalidateByRange(config->dmaBufferAddr1,
config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
}
return kStatus_Success;
}
/*!
* brief Start to capture a image.
*
* param base CSI peripheral base address.
* param handle Pointer to the transactional handle.
* param config Pointer to the capture configuration.
*
* retval kStatus_Success Initialize successfully.
* retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_capture_config_t *config)
{
assert(config);
uint16_t windowWidth;
/*
* If no special window setting, capture full frame.
* If capture window, then capture 1 one each fragment.
*/
if (config->window != NULL)
{
handle->windowULX = config->window->windowULX;
handle->windowULY = config->window->windowULY;
handle->windowLRX = config->window->windowLRX;
handle->windowLRY = config->window->windowLRY;
handle->linePerFrag = 1;
}
else
{
handle->windowULX = 0;
handle->windowULY = 0;
handle->windowLRX = handle->width - 1;
handle->windowLRY = handle->height - 1;
handle->linePerFrag = handle->maxLinePerFrag;
}
windowWidth = handle->windowLRX - handle->windowULX + 1;
if (config->outputGrayScale)
{
/* When output format is gray, the window width must be multiple value of 8. */
if (windowWidth % 8 != 0)
{
return kStatus_InvalidArgument;
}
handle->datBytePerLine = windowWidth;
if (handle->inputFormat == kCSI_FragInputYUYV)
{
handle->copyFunc = CSI_ExtractYFromYUYV;
}
else
{
handle->copyFunc = CSI_ExtractYFromUYVY;
}
}
else
{
handle->datBytePerLine = windowWidth * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
handle->copyFunc = CSI_MemCopy;
}
handle->dmaCurLine = 0;
handle->outputBuffer = (uint32_t)config->buffer;
handle->datCurWriteAddr = (uint32_t)config->buffer;
/* Image parameter. */
base->CSIIMAG_PARA =
((uint32_t)(handle->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) |
((uint32_t)(handle->linePerFrag) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT);
/*
* Write to memory from first completed frame.
* DMA base addr switch at dma transfer done.
*/
base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0);
CSI_EnableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
kCSI_RxBuffer0DmaDoneInterruptEnable);
return kStatus_Success;
}
/*!
* brief Abort image capture.
*
* Abort image capture initialized by ref CSI_FragModeTransferCaptureImage.
*
* param base CSI peripheral base address.
* param handle Pointer to the transactional handle.
*/
void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle)
{
CSI_Stop(base);
CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
kCSI_RxBuffer0DmaDoneInterruptEnable);
}
/*!
* brief CSI IRQ handle function.
*
* This function handles the CSI IRQ request to work with CSI driver fragment mode
* APIs.
*
* param base CSI peripheral base address.
* param handle CSI handle pointer.
*/
void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle)
{
uint32_t csisr = base->CSISR;
uint32_t dmaBufAddr;
uint16_t line;
/* Clear the error flags. */
base->CSISR = csisr;
/* Start of frame, clear the FIFO and start receiving. */
if (csisr & kCSI_StartOfFrameFlag)
{
/* Reflash the DMA and enable RX DMA request. */
base->CSICR3 |= (CSI_CSICR3_DMA_REFLASH_RFF_MASK | CSI_CSICR3_DMA_REQ_EN_RFF_MASK);
CSI_Start(base);
handle->dmaCurLine = 0;
handle->datCurWriteAddr = handle->outputBuffer;
}
else if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) != 0)
{
if ((csisr & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) == CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
{
dmaBufAddr = base->CSIDMASA_FB1;
}
else
{
dmaBufAddr = base->CSIDMASA_FB2;
}
if (handle->isDmaBufferCachable)
{
DCACHE_InvalidateByRange(dmaBufAddr, handle->dmaBytePerLine * handle->linePerFrag);
}
/* Copy from DMA buffer to user data buffer. */
dmaBufAddr += (handle->windowULX * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
for (line = 0; line < handle->linePerFrag; line++)
{
if (handle->dmaCurLine + line > handle->windowLRY)
{
/* out of window range */
break;
}
else if (handle->dmaCurLine + line >= handle->windowULY)
{
handle->copyFunc((void *)(handle->datCurWriteAddr), (void const *)dmaBufAddr, handle->datBytePerLine);
handle->datCurWriteAddr += handle->datBytePerLine;
dmaBufAddr += handle->dmaBytePerLine;
}
else
{
}
}
handle->dmaCurLine += handle->linePerFrag;
if (handle->dmaCurLine >= handle->height)
{
CSI_Stop(base);
CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
kCSI_RxBuffer0DmaDoneInterruptEnable);
/* Image captured. Stop the CSI. */
if (handle->callback)
{
handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData);
}
}
}
else
{
}
}
#endif /* CSI_DRIVER_FRAG_MODE */
#if defined(CSI)
void CSI_DriverIRQHandler(void)
{

296
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* Copyright 2017-2019 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CSI_H_
@ -48,7 +22,7 @@
/*! @name Driver version */
/*@{*/
#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
/*! @brief Size of the frame buffer queue used in CSI transactional function. */
@ -56,6 +30,11 @@
#define CSI_DRIVER_QUEUE_SIZE 4U
#endif
/*! @brief Enable fragment capture function or not. */
#ifndef CSI_DRIVER_FRAG_MODE
#define CSI_DRIVER_FRAG_MODE 0U
#endif
/*
* There is one empty room in queue, used to distinguish whether the queue
* is full or empty. When header equals tail, the queue is empty; when header
@ -84,7 +63,9 @@
#error CSI_CSICR3_INT_EN_MASK could not cover all interrupt bits in CSICR3.
#endif
#if ((~CSI_CSICR18_INT_EN_MASK) & ((CSI_CSICR18_FIELD0_DONE_IE_MASK | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) << 6U))
#if ((~CSI_CSICR18_INT_EN_MASK) & ((CSI_CSICR18_FIELD0_DONE_IE_MASK | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK | \
CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) \
<< 6U))
#error CSI_CSICR18_INT_EN_MASK could not cover all interrupt bits in CSICR18.
#endif
@ -92,7 +73,7 @@
enum _csi_status
{
kStatus_CSI_NoEmptyBuffer = MAKE_STATUS(kStatusGroup_CSI, 0), /*!< No empty frame buffer in queue to load to CSI. */
kStatus_CSI_NoFullBuffer = MAKE_STATUS(kStatusGroup_CSI, 1), /*!< No full frame buffer in queue to read out. */
kStatus_CSI_NoFullBuffer = MAKE_STATUS(kStatusGroup_CSI, 1), /*!< No full frame buffer in queue to read out. */
kStatus_CSI_QueueFull = MAKE_STATUS(kStatusGroup_CSI, 2), /*!< Queue is full, no room to save new empty buffer. */
kStatus_CSI_FrameDone = MAKE_STATUS(kStatusGroup_CSI, 3), /*!< New frame received and saved to queue. */
};
@ -104,9 +85,9 @@ enum _csi_status
*/
typedef enum _csi_work_mode
{
kCSI_GatedClockMode = CSI_CSICR1_GCLK_MODE(1U), /*!< HSYNC, VSYNC, and PIXCLK signals are used. */
kCSI_NonGatedClockMode = 0U, /*!< VSYNC, and PIXCLK signals are used. */
kCSI_CCIR656ProgressiveMode = CSI_CSICR1_CCIR_EN(1U), /*!< CCIR656 progressive mode. */
kCSI_GatedClockMode = CSI_CSICR1_GCLK_MODE(1U), /*!< HSYNC, VSYNC, and PIXCLK signals are used. */
kCSI_NonGatedClockMode = 0U, /*!< VSYNC, and PIXCLK signals are used. */
kCSI_CCIR656ProgressiveMode = CSI_CSICR1_CCIR_EN(1U), /*!< CCIR656 progressive mode. */
} csi_work_mode_t;
/*!
@ -122,12 +103,12 @@ typedef enum _csi_data_bus
/*! @brief CSI signal polarity. */
enum _csi_polarity_flags
{
kCSI_HsyncActiveLow = 0U, /*!< HSYNC is active low. */
kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK, /*!< HSYNC is active high. */
kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */
kCSI_DataLatchOnFallingEdge = 0U, /*!< Pixel data latched at falling edge of pixel clock. */
kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */
kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */
kCSI_HsyncActiveLow = 0U, /*!< HSYNC is active low. */
kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK, /*!< HSYNC is active high. */
kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */
kCSI_DataLatchOnFallingEdge = 0U, /*!< Pixel data latched at falling edge of pixel clock. */
kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */
kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */
};
/*! @brief Configuration to initialize the CSI module. */
@ -151,33 +132,34 @@ typedef struct _csi_config
/*! @brief The CSI FIFO, used for FIFO operation. */
typedef enum _csi_fifo
{
kCSI_RxFifo = (1U << 0U), /*!< RXFIFO. */
kCSI_StatFifo = (1U << 1U), /*!< STAT FIFO. */
kCSI_AllFifo = 0x01 | 0x02, /*!< Both RXFIFO and STAT FIFO. */
kCSI_RxFifo = (1U << 0U), /*!< RXFIFO. */
kCSI_StatFifo = (1U << 1U), /*!< STAT FIFO. */
kCSI_AllFifo = 0x01 | 0x02, /*!< Both RXFIFO and STAT FIFO. */
} csi_fifo_t;
/*! @brief CSI feature interrupt source. */
enum _csi_interrupt_enable
{
kCSI_EndOfFrameInterruptEnable = CSI_CSICR1_EOF_INT_EN_MASK, /*!< End of frame interrupt enable. */
kCSI_ChangeOfFieldInterruptEnable = CSI_CSICR1_COF_INT_EN_MASK, /*!< Change of field interrupt enable. */
kCSI_EndOfFrameInterruptEnable = CSI_CSICR1_EOF_INT_EN_MASK, /*!< End of frame interrupt enable. */
kCSI_ChangeOfFieldInterruptEnable = CSI_CSICR1_COF_INT_EN_MASK, /*!< Change of field interrupt enable. */
kCSI_StatFifoOverrunInterruptEnable = CSI_CSICR1_SF_OR_INTEN_MASK, /*!< STAT FIFO overrun interrupt enable. */
kCSI_RxFifoOverrunInterruptEnable = CSI_CSICR1_RF_OR_INTEN_MASK, /*!< RXFIFO overrun interrupt enable. */
kCSI_RxFifoOverrunInterruptEnable = CSI_CSICR1_RF_OR_INTEN_MASK, /*!< RXFIFO overrun interrupt enable. */
kCSI_StatFifoDmaDoneInterruptEnable =
CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK, /*!< STAT FIFO DMA done interrupt enable. */
kCSI_StatFifoFullInterruptEnable = CSI_CSICR1_STATFF_INTEN_MASK, /*!< STAT FIFO full interrupt enable. */
kCSI_RxBuffer1DmaDoneInterruptEnable =
CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 1 DMA transfer done. */
kCSI_RxBuffer0DmaDoneInterruptEnable =
CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 0 DMA transfer done. */
kCSI_RxFifoFullInterruptEnable = CSI_CSICR1_RXFF_INTEN_MASK, /*!< RXFIFO full interrupt enable. */
kCSI_StartOfFrameInterruptEnable = CSI_CSICR1_SOF_INTEN_MASK, /*!< Start of frame (SOF) interrupt enable. */
CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 0 DMA transfer done. */
kCSI_RxFifoFullInterruptEnable = CSI_CSICR1_RXFF_INTEN_MASK, /*!< RXFIFO full interrupt enable. */
kCSI_StartOfFrameInterruptEnable = CSI_CSICR1_SOF_INTEN_MASK, /*!< Start of frame (SOF) interrupt enable. */
kCSI_EccErrorInterruptEnable = CSI_CSICR3_ECC_INT_EN_MASK, /*!< ECC error detection interrupt enable. */
kCSI_EccErrorInterruptEnable = CSI_CSICR3_ECC_INT_EN_MASK, /*!< ECC error detection interrupt enable. */
kCSI_AhbResErrorInterruptEnable = CSI_CSICR3_HRESP_ERR_EN_MASK, /*!< AHB response Error interrupt enable. */
kCSI_BaseAddrChangeErrorInterruptEnable = CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK << 6U, /*!< The DMA output buffer base address
changes before DMA completed. */
kCSI_BaseAddrChangeErrorInterruptEnable = CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK
<< 6U, /*!< The DMA output buffer base address
changes before DMA completed. */
kCSI_Field0DoneInterruptEnable = CSI_CSICR18_FIELD0_DONE_IE_MASK << 6U, /*!< Field 0 done interrupt enable. */
kCSI_Field1DoneInterruptEnable = CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK << 6U, /*!< Field 1 done interrupt enable. */
};
@ -202,23 +184,23 @@ enum _csi_interrupt_enable
*/
enum _csi_flags
{
kCSI_RxFifoDataReadyFlag = CSI_CSISR_DRDY_MASK, /*!< RXFIFO data ready. */
kCSI_EccErrorFlag = CSI_CSISR_ECC_INT_MASK, /*!< ECC error detected. */
kCSI_AhbResErrorFlag = CSI_CSISR_HRESP_ERR_INT_MASK, /*!< Hresponse (AHB bus response) Error. */
kCSI_ChangeOfFieldFlag = CSI_CSISR_COF_INT_MASK, /*!< Change of field. */
kCSI_Field0PresentFlag = CSI_CSISR_F1_INT_MASK, /*!< Field 0 present in CCIR mode. */
kCSI_Field1PresentFlag = CSI_CSISR_F2_INT_MASK, /*!< Field 1 present in CCIR mode. */
kCSI_StartOfFrameFlag = CSI_CSISR_SOF_INT_MASK, /*!< Start of frame (SOF) detected. */
kCSI_EndOfFrameFlag = CSI_CSISR_EOF_INT_MASK, /*!< End of frame (EOF) detected. */
kCSI_RxFifoFullFlag = CSI_CSISR_RxFF_INT_MASK, /*!< RXFIFO full (Number of data reaches trigger level). */
kCSI_RxBuffer1DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB2_MASK, /*!< RX frame buffer 1 DMA transfer done. */
kCSI_RxBuffer0DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB1_MASK, /*!< RX frame buffer 0 DMA transfer done. */
kCSI_StatFifoFullFlag = CSI_CSISR_STATFF_INT_MASK, /*!< STAT FIFO full (Reach trigger level). */
kCSI_StatFifoDmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_SFF_MASK, /*!< STAT FIFO DMA transfer done. */
kCSI_StatFifoOverrunFlag = CSI_CSISR_SF_OR_INT_MASK, /*!< STAT FIFO overrun. */
kCSI_RxFifoOverrunFlag = CSI_CSISR_RF_OR_INT_MASK, /*!< RXFIFO overrun. */
kCSI_Field0DoneFlag = CSI_CSISR_DMA_FIELD0_DONE_MASK, /*!< Field 0 transfer done. */
kCSI_Field1DoneFlag = CSI_CSISR_DMA_FIELD1_DONE_MASK, /*!< Field 1 transfer done. */
kCSI_RxFifoDataReadyFlag = CSI_CSISR_DRDY_MASK, /*!< RXFIFO data ready. */
kCSI_EccErrorFlag = CSI_CSISR_ECC_INT_MASK, /*!< ECC error detected. */
kCSI_AhbResErrorFlag = CSI_CSISR_HRESP_ERR_INT_MASK, /*!< Hresponse (AHB bus response) Error. */
kCSI_ChangeOfFieldFlag = CSI_CSISR_COF_INT_MASK, /*!< Change of field. */
kCSI_Field0PresentFlag = CSI_CSISR_F1_INT_MASK, /*!< Field 0 present in CCIR mode. */
kCSI_Field1PresentFlag = CSI_CSISR_F2_INT_MASK, /*!< Field 1 present in CCIR mode. */
kCSI_StartOfFrameFlag = CSI_CSISR_SOF_INT_MASK, /*!< Start of frame (SOF) detected. */
kCSI_EndOfFrameFlag = CSI_CSISR_EOF_INT_MASK, /*!< End of frame (EOF) detected. */
kCSI_RxFifoFullFlag = CSI_CSISR_RxFF_INT_MASK, /*!< RXFIFO full (Number of data reaches trigger level). */
kCSI_RxBuffer1DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB2_MASK, /*!< RX frame buffer 1 DMA transfer done. */
kCSI_RxBuffer0DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB1_MASK, /*!< RX frame buffer 0 DMA transfer done. */
kCSI_StatFifoFullFlag = CSI_CSISR_STATFF_INT_MASK, /*!< STAT FIFO full (Reach trigger level). */
kCSI_StatFifoDmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_SFF_MASK, /*!< STAT FIFO DMA transfer done. */
kCSI_StatFifoOverrunFlag = CSI_CSISR_SF_OR_INT_MASK, /*!< STAT FIFO overrun. */
kCSI_RxFifoOverrunFlag = CSI_CSISR_RF_OR_INT_MASK, /*!< RXFIFO overrun. */
kCSI_Field0DoneFlag = CSI_CSISR_DMA_FIELD0_DONE_MASK, /*!< Field 0 transfer done. */
kCSI_Field1DoneFlag = CSI_CSISR_DMA_FIELD1_DONE_MASK, /*!< Field 1 transfer done. */
kCSI_BaseAddrChangeErrorFlag = CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK, /*!< The DMA output buffer base address
changes before DMA completed. */
};
@ -258,6 +240,99 @@ struct _csi_handle
void *userData; /*!< CSI callback function parameter.*/
};
#if CSI_DRIVER_FRAG_MODE
/*! @brief Input pixel format when CSI works in fragment mode. */
typedef enum _csi_frag_input_pixel_format
{
kCSI_FragInputRGB565 = 0, /*!< Input pixel format is RGB565. */
kCSI_FragInputYUYV, /*!< Input pixel format is YUV422 (Y-U-Y-V). */
kCSI_FragInputUYVY, /*!< Input pixel format is YUV422 (U-Y-V-Y). */
} csi_frag_input_pixel_format_t;
/*! @brief Configuration for CSI module to work in fragment mode. */
typedef struct _csi_frag_config
{
uint16_t width; /*!< Pixels of the input frame. */
uint16_t height; /*!< Lines of the input frame. */
uint32_t polarityFlags; /*!< Timing signal polarity flags, OR'ed value of @ref _csi_polarity_flags. */
csi_work_mode_t workMode; /*!< CSI work mode. */
csi_data_bus_t dataBus; /*!< Data bus width. */
bool useExtVsync; /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false
to use internal VSYNC signal decoded from SOF. */
csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
uint32_t dmaBufferAddr0; /*!< Buffer 0 used for CSI DMA, must be double word aligned. */
uint32_t dmaBufferAddr1; /*!< Buffer 1 used for CSI DMA, must be double word aligned. */
uint16_t dmaBufferLine; /*!< Lines of each DMA buffer. The size of DMA buffer 0 and
buffer 1 must be the same. Camera frame height must be
dividable by this value. */
bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */
} csi_frag_config_t;
/* Forward declaration of the handle typedef. */
typedef struct _csi_frag_handle csi_frag_handle_t;
/*!
* @brief CSI fragment transfer callback function.
*
* When a new frame is received and saved to the frame buffer queue, the callback
* is called and the pass the status @ref kStatus_CSI_FrameDone to upper layer.
*/
typedef void (*csi_frag_transfer_callback_t)(CSI_Type *base,
csi_frag_handle_t *handle,
status_t status,
void *userData);
/*!
* @brief Function to copy data from CSI DMA buffer to user buffer.
*/
typedef void (*csi_frag_copy_func_t)(void *pDest, const void *pSrc, size_t cnt);
/*! @brief Handle for CSI module to work in fragment mode. */
struct _csi_frag_handle
{
uint16_t width; /*!< Pixels of the input frame. */
uint16_t height; /*!< Lines of the input frame. */
uint16_t maxLinePerFrag; /*!< Max line saved per fragment. */
uint16_t linePerFrag; /*!< Actual line saved per fragment. */
uint16_t dmaBytePerLine; /*!< How many bytes DMA transfered each line. */
uint16_t datBytePerLine; /*!< How many bytes copied to user buffer each line. */
uint16_t dmaCurLine; /*!< Current line index in whole frame. */
uint16_t windowULX; /*!< X of windows upper left corner. */
uint16_t windowULY; /*!< Y of windows upper left corner. */
uint16_t windowLRX; /*!< X of windows lower right corner. */
uint16_t windowLRY; /*!< Y of windows lower right corner. */
uint32_t outputBuffer; /*!< Address of buffer to save the captured image. */
uint32_t datCurWriteAddr; /*!< Current write address to the user buffer. */
csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
csi_frag_transfer_callback_t callback; /*!< Callback function. */
void *userData; /*!< CSI callback function parameter.*/
csi_frag_copy_func_t copyFunc; /*!< Function to copy data from CSI DMA buffer to user buffer. */
bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */
};
/*! @brief Handle for CSI module to work in fragment mode. */
typedef struct _csi_frag_window
{
uint16_t windowULX; /*!< X of windows upper left corner. */
uint16_t windowULY; /*!< Y of windows upper left corner. */
uint16_t windowLRX; /*!< X of windows lower right corner. */
uint16_t windowLRY; /*!< Y of windows lower right corner. */
} csi_frag_window_t;
/*! @brief Handle for CSI module to work in fragment mode. */
typedef struct _csi_frag_capture_config
{
bool outputGrayScale; /*!< Output gray scale image or not, could only enable when input format is YUV. */
uint32_t buffer; /*!< Buffer to save the captured image. */
csi_frag_window_t *window; /*!< Capture window. Capture full frame if set this to NULL. When output format is gray,
the window width must be multiple value of 8. */
} csi_frag_capture_config_t;
#endif /* CSI_DRIVER_FRAG_MODE */
/*******************************************************************************
* API
******************************************************************************/
@ -455,6 +530,7 @@ static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask)
}
/* @} */
#if !CSI_DRIVER_FRAG_MODE
/*!
* @name Transactional
* @{
@ -553,6 +629,88 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_
void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle);
/* @} */
#else
/*!
* @name Fragment mode
* @{
*/
/*!
* @brief Initialize the CSI to work in fragment mode.
*
* This function enables the CSI peripheral clock, and resets the CSI registers.
*
* @param base CSI peripheral base address.
*/
void CSI_FragModeInit(CSI_Type *base);
/*!
* @brief De-initialize the CSI.
*
* This function disables the CSI peripheral clock.
*
* @param base CSI peripheral base address.
*/
void CSI_FragModeDeinit(CSI_Type *base);
/*!
* @brief Create handle for CSI work in fragment mode.
*
* @param base CSI peripheral base address.
* @param handle Pointer to the transactional handle.
* @param config Pointer to the configuration structure.
* @param callback Callback function for CSI transfer.
* @param userData Callback function parameter.
*
* @retval kStatus_Success Initialize successfully.
* @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeCreateHandle(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_config_t *config,
csi_frag_transfer_callback_t callback,
void *userData);
/*!
* @brief Start to capture a image.
*
* @param base CSI peripheral base address.
* @param handle Pointer to the transactional handle.
* @param config Pointer to the capture configuration.
*
* @retval kStatus_Success Initialize successfully.
* @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
*/
status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
csi_frag_handle_t *handle,
const csi_frag_capture_config_t *config);
/*!
* @brief Abort image capture.
*
* Abort image capture initialized by @ref CSI_FragModeTransferCaptureImage.
*
* @param base CSI peripheral base address.
* @param handle Pointer to the transactional handle.
*/
void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle);
/*!
* @brief CSI IRQ handle function.
*
* This function handles the CSI IRQ request to work with CSI driver fragment mode
* APIs.
*
* @param base CSI peripheral base address.
* @param handle CSI handle pointer.
*/
void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle);
/* @} */
#endif /* CSI_DRIVER_FRAG_MODE */
#if defined(__cplusplus)
}
#endif

226
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP
* Copyright 2017, NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_dcdc.h"
@ -39,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -82,6 +55,11 @@ static uint32_t DCDC_GetInstance(DCDC_Type *base)
return instance;
}
/*!
* brief Enable the access to DCDC registers.
*
* param base DCDC peripheral base address.
*/
void DCDC_Init(DCDC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -90,6 +68,11 @@ void DCDC_Init(DCDC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Disable the access to DCDC registers.
*
* param base DCDC peripheral base address.
*/
void DCDC_Deinit(DCDC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -98,14 +81,19 @@ void DCDC_Deinit(DCDC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Configure the DCDC clock source.
*
* param base DCDC peripheral base address.
* param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
*/
void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
{
uint32_t tmp32;
/* Configure the DCDC_REG0 register. */
tmp32 = base->REG0 &
~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK |
DCDC_REG0_PWD_OSC_INT_MASK);
tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |
DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK);
switch (clockSource)
{
case kDCDC_ClockInternalOsc:
@ -125,20 +113,47 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
base->REG0 = tmp32;
}
/*!
* brief Get the default setting for detection configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* code
* config->enableXtalokDetection = false;
* config->powerDownOverVoltageDetection = true;
* config->powerDownLowVlotageDetection = false;
* config->powerDownOverCurrentDetection = true;
* config->powerDownPeakCurrentDetection = true;
* config->powerDownZeroCrossDetection = true;
* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
{
assert(NULL != config);
config->enableXtalokDetection = false;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableXtalokDetection = false;
config->powerDownOverVoltageDetection = true;
config->powerDownLowVlotageDetection = false;
config->powerDownLowVlotageDetection = false;
config->powerDownOverCurrentDetection = true;
config->powerDownPeakCurrentDetection = true;
config->powerDownZeroCrossDetection = true;
config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
config->powerDownZeroCrossDetection = true;
config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
}
/*!
* breif Configure the DCDC detection.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
{
assert(NULL != config);
@ -179,25 +194,47 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con
base->REG0 = tmp32;
}
/*!
* brief Get the default setting for low power configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* code
* config->enableOverloadDetection = true;
* config->enableAdjustHystereticValue = false;
* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
*/
void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
{
assert(NULL != config);
config->enableOverloadDetection = true;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableOverloadDetection = true;
config->enableAdjustHystereticValue = false;
config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
}
/*!
* brief Configure the DCDC low power.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
*/
void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
{
assert(NULL != config);
uint32_t tmp32;
/* Configure the DCDC_REG0 register. */
tmp32 = base->REG0 &
~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK |
DCDC_REG0_LP_OVERLOAD_THRSH_MASK);
tmp32 = base->REG0 & ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK |
DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK);
tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) |
DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold);
if (config->enableOverloadDetection)
@ -211,6 +248,12 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf
base->REG0 = tmp32;
}
/*!
* brief Get DCDC status flags.
*
* param base peripheral base address.
* return Mask of asserted status flags. See to "_dcdc_status_flags_t".
*/
uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
{
uint32_t tmp32 = 0U;
@ -223,6 +266,12 @@ uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
return tmp32;
}
/*!
* brief Reset current alert signal. Alert signal is generate by peak current detection.
*
* param base DCDC peripheral base address.
* param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
*/
void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
{
if (enable)
@ -235,20 +284,47 @@ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
}
}
/*!
* brief Get the default setting for loop control configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* code
* config->enableCommonHysteresis = false;
* config->enableCommonThresholdDetection = false;
* config->enableInvertHysteresisSign = false;
* config->enableRCThresholdDetection = false;
* config->enableRCScaleCircuit = 0U;
* config->complementFeedForwardStep = 0U;
* config->controlParameterMagnitude = 2U;
* config->integralProportionalRatio = 2U;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
*/
void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
{
assert(NULL != config);
config->enableCommonHysteresis = false;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableCommonHysteresis = false;
config->enableCommonThresholdDetection = false;
config->enableInvertHysteresisSign = false;
config->enableRCThresholdDetection = false;
config->enableRCScaleCircuit = 0U;
config->complementFeedForwardStep = 0U;
config->controlParameterMagnitude = 2U;
config->integralProportionalRatio = 2U;
config->enableInvertHysteresisSign = false;
config->enableRCThresholdDetection = false;
config->enableRCScaleCircuit = 0U;
config->complementFeedForwardStep = 0U;
config->controlParameterMagnitude = 2U;
config->integralProportionalRatio = 2U;
}
/*!
* brief Configure the DCDC loop control.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
*/
void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
{
assert(NULL != config);
@ -268,10 +344,9 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
base->REG1 = tmp32;
/* configure the DCDC_REG2 register. */
tmp32 = base->REG2 &
~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | DCDC_REG2_LOOPCTRL_DC_R_MASK |
DCDC_REG2_LOOPCTRL_DC_C_MASK);
tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK |
DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK);
tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) |
DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) |
@ -287,6 +362,12 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
base->REG2 = tmp32;
}
/*!
* brief Configure for the min power.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
*/
void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
{
assert(NULL != config);
@ -301,6 +382,18 @@ void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *conf
base->REG3 = tmp32;
}
/*!
* brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
*
* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
* stabled.
* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
* back to run mode if it detects the current loading is larger than about 50 mA(typical value).
*
* param base DCDC peripheral base address.
* param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
* param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
*/
void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
{
uint32_t tmp32;
@ -321,6 +414,12 @@ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStan
}
}
/*!
* brief Configure the DCDC internal regulator.
*
* param base DCDC peripheral base address.
* param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
*/
void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
{
assert(NULL != config);
@ -337,6 +436,16 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula
base->REG1 = tmp32;
}
/*!
* brief Boot DCDC into DCM(discontinous conduction mode).
*
* pwd_zcd=0x0;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
* DCM_set_ctrl=1'b1;
*
* param base DCDC peripheral base address.
*/
void DCDC_BootIntoDCM(DCDC_Type *base)
{
base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
@ -344,6 +453,15 @@ void DCDC_BootIntoDCM(DCDC_Type *base)
DCDC_REG2_DCM_SET_CTRL_MASK;
}
/*!
* brief Boot DCDC into CCM(continous conduction mode).
*
* pwd_zcd=0x1;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3;
*
* param base DCDC peripheral base address.
*/
void DCDC_BootIntoCCM(DCDC_Type *base)
{
base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;

356
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP
* Copyright 2017, NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_DCDC_H__
@ -48,27 +22,27 @@
/*! @brief DCDC driver version. */
#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
/*!
* @brief DCDC status flags.
*/
* @brief DCDC status flags.
*/
enum _dcdc_status_flags_t
{
kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */
};
/*!
* @brief The current bias of low power comparator.
*/
* @brief The current bias of low power comparator.
*/
typedef enum _dcdc_comparator_current_bias
{
kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */
kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */
kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */
kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */
kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */
} dcdc_comparator_current_bias_t;
/*!
* @brief The threshold of over current detection.
*/
* @brief The threshold of over current detection.
*/
typedef enum _dcdc_over_current_threshold
{
kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */
@ -78,8 +52,8 @@ typedef enum _dcdc_over_current_threshold
} dcdc_over_current_threshold_t;
/*!
* @brief The threshold if peak current detection.
*/
* @brief The threshold if peak current detection.
*/
typedef enum _dcdc_peak_current_threshold
{
kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */
@ -91,23 +65,23 @@ typedef enum _dcdc_peak_current_threshold
} dcdc_peak_current_threshold_t;
/*!
* @brief The period of counting the charging times in power save mode.
*/
* @brief The period of counting the charging times in power save mode.
*/
typedef enum _dcdc_count_charging_time_period
{
kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */
kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */
kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */
} dcdc_count_charging_time_period_t;
/*!
* @brief The threshold of the counting number of charging times
*/
* @brief The threshold of the counting number of charging times
*/
typedef enum _dcdc_count_charging_time_threshold
{
kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */
kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */
kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */
kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */
kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */
} dcdc_count_charging_time_threshold_t;
/*!
@ -115,14 +89,14 @@ typedef enum _dcdc_count_charging_time_threshold
*/
typedef enum _dcdc_clock_source
{
kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */
kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */
kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */
kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */
} dcdc_clock_source_t;
/*!
* @brief Configuration for DCDC detection.
*/
* @brief Configuration for DCDC detection.
*/
typedef struct _dcdc_detection_config
{
bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */
@ -137,8 +111,8 @@ typedef struct _dcdc_detection_config
} dcdc_detection_config_t;
/*!
* @brief Configuration for the loop control.
*/
* @brief Configuration for the loop control.
*/
typedef struct _dcdc_loop_control_config
{
bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators.
@ -160,8 +134,8 @@ typedef struct _dcdc_loop_control_config
optimize efficiency and loop response. */
} dcdc_loop_control_config_t;
/*!
* @brief Configuration for DCDC low power.
*/
* @brief Configuration for DCDC low power.
*/
typedef struct _dcdc_low_power_config
{
bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the
@ -176,8 +150,8 @@ typedef struct _dcdc_low_power_config
} dcdc_low_power_config_t;
/*!
* @brief Configuration for DCDC internal regulator.
*/
* @brief Configuration for DCDC internal regulator.
*/
typedef struct _dcdc_internal_regulator_config
{
bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is
@ -206,17 +180,17 @@ extern "C" {
*/
/*!
* @brief Enable the access to DCDC registers.
*
* @param base DCDC peripheral base address.
*/
* @brief Enable the access to DCDC registers.
*
* @param base DCDC peripheral base address.
*/
void DCDC_Init(DCDC_Type *base);
/*!
* @brief Disable the access to DCDC registers.
*
* @param base DCDC peripheral base address.
*/
* @brief Disable the access to DCDC registers.
*
* @param base DCDC peripheral base address.
*/
void DCDC_Deinit(DCDC_Type *base);
/* @} */
@ -227,11 +201,11 @@ void DCDC_Deinit(DCDC_Type *base);
*/
/*!
* @brief Get DCDC status flags.
*
* @param base peripheral base address.
* @return Mask of asserted status flags. See to "_dcdc_status_flags_t".
*/
* @brief Get DCDC status flags.
*
* @param base peripheral base address.
* @return Mask of asserted status flags. See to "_dcdc_status_flags_t".
*/
uint32_t DCDC_GetstatusFlags(DCDC_Type *base);
/* @} */
@ -262,79 +236,79 @@ static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable
}
/*!
* @brief Configure the DCDC clock source.
*
* @param base DCDC peripheral base address.
* @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
*/
* @brief Configure the DCDC clock source.
*
* @param base DCDC peripheral base address.
* @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
*/
void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
/*!
* @brief Get the default setting for detection configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* @code
* config->enableXtalokDetection = false;
* config->powerDownOverVoltageDetection = true;
* config->powerDownLowVlotageDetection = false;
* config->powerDownOverCurrentDetection = true;
* config->powerDownPeakCurrentDetection = true;
* config->powerDownZeroCrossDetection = true;
* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
* @endcode
*
* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
* @brief Get the default setting for detection configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* @code
* config->enableXtalokDetection = false;
* config->powerDownOverVoltageDetection = true;
* config->powerDownLowVlotageDetection = false;
* config->powerDownOverCurrentDetection = true;
* config->powerDownPeakCurrentDetection = true;
* config->powerDownZeroCrossDetection = true;
* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
* @endcode
*
* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config);
/*!
* @breif Configure the DCDC detection.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
* @breif Configure the DCDC detection.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
*/
void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config);
/*!
* @brief Get the default setting for low power configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* @code
* config->enableOverloadDetection = true;
* config->enableAdjustHystereticValue = false;
* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
* @endcode
*
* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
*/
* @brief Get the default setting for low power configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* @code
* config->enableOverloadDetection = true;
* config->enableAdjustHystereticValue = false;
* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
* @endcode
*
* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
*/
void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config);
/*!
* @brief Configure the DCDC low power.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
*/
* @brief Configure the DCDC low power.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
*/
void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config);
/*!
* @brief Reset current alert signal. Alert signal is generate by peak current detection.
*
* @param base DCDC peripheral base address.
* @param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
*/
* @brief Reset current alert signal. Alert signal is generate by peak current detection.
*
* @param base DCDC peripheral base address.
* @param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
*/
void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable);
/*!
* @brief Set the bangap trim value to trim bandgap voltage.
*
* @param base DCDC peripheral base address.
* @param TrimValue The bangap trim value. Available range is 0U-31U.
*/
* @brief Set the bangap trim value to trim bandgap voltage.
*
* @param base DCDC peripheral base address.
* @param TrimValue The bangap trim value. Available range is 0U-31U.
*/
static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
{
base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
@ -342,31 +316,31 @@ static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t tri
}
/*!
* @brief Get the default setting for loop control configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* @code
* config->enableCommonHysteresis = false;
* config->enableCommonThresholdDetection = false;
* config->enableInvertHysteresisSign = false;
* config->enableRCThresholdDetection = false;
* config->enableRCScaleCircuit = 0U;
* config->complementFeedForwardStep = 0U;
* config->controlParameterMagnitude = 2U;
* config->integralProportionalRatio = 2U;
* @endcode
*
* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
*/
* @brief Get the default setting for loop control configuration.
*
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* @code
* config->enableCommonHysteresis = false;
* config->enableCommonThresholdDetection = false;
* config->enableInvertHysteresisSign = false;
* config->enableRCThresholdDetection = false;
* config->enableRCScaleCircuit = 0U;
* config->complementFeedForwardStep = 0U;
* config->controlParameterMagnitude = 2U;
* config->integralProportionalRatio = 2U;
* @endcode
*
* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
*/
void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config);
/*!
* @brief Configure the DCDC loop control.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
*/
* @brief Configure the DCDC loop control.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
*/
void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config);
/*!
@ -378,11 +352,11 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config);
/*!
* @brief Set the current bias of low power comparator.
*
* @param base DCDC peripheral base address.
* @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t".
*/
* @brief Set the current bias of low power comparator.
*
* @param base DCDC peripheral base address.
* @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t".
*/
static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule)
{
base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
@ -395,33 +369,33 @@ static inline void DCDC_LockTargetVoltage(DCDC_Type *base)
}
/*!
* @brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
*
* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
* stabled.
* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
* back to run mode if it detects the current loading is larger than about 50 mA(typical value).
*
* @param base DCDC peripheral base address.
* @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
* @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
*/
* @brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
*
* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
* stabled.
* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
* back to run mode if it detects the current loading is larger than about 50 mA(typical value).
*
* @param base DCDC peripheral base address.
* @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
* @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
*/
void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby);
/*!
* @brief Configure the DCDC internal regulator.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
*/
* @brief Configure the DCDC internal regulator.
*
* @param base DCDC peripheral base address.
* @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
*/
void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config);
/*!
* @brief Ajust delay to reduce ground noise.
*
* @param base DCDC peripheral base address.
* @param enable Enable the feature or not.
*/
* @brief Ajust delay to reduce ground noise.
*
* @param base DCDC peripheral base address.
* @param enable Enable the feature or not.
*/
static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
{
if (enable)
@ -435,12 +409,12 @@ static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
}
/*!
* @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero
* cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM.
*
* @param base DCDC peripheral base address.
* @param enable Enable the feature or not.
*/
* @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero
* cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM.
*
* @param base DCDC peripheral base address.
* @param enable Enable the feature or not.
*/
static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
{
if (enable)
@ -461,26 +435,26 @@ static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
*/
/*!
* @brief Boot DCDC into DCM(discontinous conduction mode).
*
* pwd_zcd=0x0;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
* DCM_set_ctrl=1'b1;
*
* @param base DCDC peripheral base address.
*/
* @brief Boot DCDC into DCM(discontinous conduction mode).
*
* pwd_zcd=0x0;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
* DCM_set_ctrl=1'b1;
*
* @param base DCDC peripheral base address.
*/
void DCDC_BootIntoDCM(DCDC_Type *base);
/*!
* @brief Boot DCDC into CCM(continous conduction mode).
*
* pwd_zcd=0x1;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3;
*
* @param base DCDC peripheral base address.
*/
* @brief Boot DCDC into CCM(continous conduction mode).
*
* pwd_zcd=0x1;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3;
*
* @param base DCDC peripheral base address.
*/
void DCDC_BootIntoCCM(DCDC_Type *base);
#if defined(__cplusplus)

356
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_dcp.h"
@ -43,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.dcp"
#endif
/*! Compile time sizeof() check */
#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
@ -79,20 +52,20 @@ typedef struct _dcp_hash_ctx_internal
/*!< SHA-1/SHA-2 digest length in bytes */
enum _dcp_hash_digest_len
{
kDCP_OutLenSha1 = 20u,
kDCP_OutLenSha1 = 20u,
kDCP_OutLenSha256 = 32u,
kDCP_OutLenCrc32 = 4u,
kDCP_OutLenCrc32 = 4u,
};
enum _dcp_work_packet_bit_definitions
{
kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */
kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */
kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */
kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */
kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */
kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */
kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */
kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */
kDCP_CONTROL1_HASH_SELECT_SHA256 = 2u << 16,
kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16,
kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16,
kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16,
kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16,
};
/*! 64-byte block represented as byte array of 16 32-bit words */
@ -133,7 +106,7 @@ static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel)
{
uint32_t statReg = 0;
uint32_t semaReg = 0;
status_t status = kStatus_Fail;
status_t status = kStatus_Fail;
switch (channel)
{
@ -172,7 +145,11 @@ static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel)
static void dcp_clear_status(DCP_Type *base)
{
volatile uint32_t *dcpStatClrPtr = &base->STAT + 2u;
*dcpStatClrPtr = 0xFFu;
*dcpStatClrPtr = 0xFFu;
while(base->STAT & 0xffu)
{
}
}
static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask)
@ -181,22 +158,22 @@ static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask)
if (mask & kDCP_Channel0)
{
chStatClrPtr = &base->CH0STAT + 2u;
chStatClrPtr = &base->CH0STAT + 2u;
*chStatClrPtr = 0xFFu;
}
if (mask & kDCP_Channel1)
{
chStatClrPtr = &base->CH1STAT + 2u;
chStatClrPtr = &base->CH1STAT + 2u;
*chStatClrPtr = 0xFFu;
}
if (mask & kDCP_Channel2)
{
chStatClrPtr = &base->CH2STAT + 2u;
chStatClrPtr = &base->CH2STAT + 2u;
*chStatClrPtr = 0xFFu;
}
if (mask & kDCP_Channel3)
{
chStatClrPtr = &base->CH3STAT + 2u;
chStatClrPtr = &base->CH3STAT + 2u;
*chStatClrPtr = 0xFFu;
}
}
@ -205,7 +182,7 @@ static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle,
{
base->KEY = DCP_KEY_INDEX(handle->keySlot) | DCP_KEY_SUBWORD(0);
/* move the key by 32-bit words */
int i = 0;
int i = 0;
size_t keySize = 16u;
while (keySize)
{
@ -216,6 +193,11 @@ static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle,
return kStatus_Success;
}
/* Disable optimizations for GCC to prevent instruction reordering */
#if defined(__GNUC__)
#pragma GCC push_options
#pragma GCC optimize ("O0")
#endif
static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket)
{
status_t status;
@ -263,7 +245,11 @@ static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work
/* set out packet to DCP CMDPTR */
*cmdptr = (uint32_t)dcpPacket;
/* set the channel semaphore */
/* Make sure that all data memory accesses are completed before starting of the job */
__DSB();
__ISB();
/* set the channel semaphore to start the job */
*chsema = 1u;
}
@ -285,7 +271,28 @@ static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work
return status;
}
#if defined(__GNUC__)
#pragma GCC pop_options
#endif
/*!
* brief Set AES key to dcp_handle_t struct and optionally to DCP.
*
* Sets the AES key for encryption/decryption with the dcp_handle_t structure.
* The dcp_handle_t input argument specifies keySlot.
* If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use
* status.
* For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct.
* If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2,
* kDCP_KeySlot3),
* this function will also load the supplied key to the specified keySlot in DCP.
*
* param base DCP peripheral base address.
* param handle Handle used for the request.
* param key 0-mod-4 aligned pointer to AES key.
* param keySize AES key size in bytes. Shall equal 16.
* return status from set key operation
*/
status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize)
{
status_t status = kStatus_Fail;
@ -336,6 +343,19 @@ status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key
return status;
}
/*!
* brief Encrypts AES on one or multiple 128-bit block(s).
*
* Encrypts AES.
* The source plaintext and destination ciphertext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param plaintext Input plain text to encrypt
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return Status from encrypt operation
*/
status_t DCP_AES_EncryptEcb(
DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size)
{
@ -355,6 +375,20 @@ status_t DCP_AES_EncryptEcb(
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Encrypts AES using the ECB block mode.
*
* Puts AES ECB encrypt work packet to DCP channel.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param[out] dcpPacket Memory for the DCP work packet.
* param plaintext Input plain text to encrypt.
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -368,10 +402,11 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
return kStatus_InvalidArgument;
}
dcpPacket->control0 = 0x122u; /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
dcpPacket->control0 =
0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
dcpPacket->bufferSize = (uint32_t)size;
dcpPacket->bufferSize = (uint32_t)size;
if (handle->keySlot == kDCP_OtpKey)
{
@ -397,6 +432,19 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Decrypts AES on one or multiple 128-bit block(s).
*
* Decrypts AES.
* The source ciphertext and destination plaintext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param ciphertext Input plain text to encrypt
* param[out] plaintext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return Status from decrypt operation
*/
status_t DCP_AES_DecryptEcb(
DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size)
{
@ -416,6 +464,20 @@ status_t DCP_AES_DecryptEcb(
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Decrypts AES using ECB block mode.
*
* Puts AES ECB decrypt dcpPacket to DCP input job ring.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param[out] dcpPacket Memory for the DCP work packet.
* param ciphertext Input cipher text to decrypt
* param[out] plaintext Output plain text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -429,10 +491,10 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
return kStatus_InvalidArgument;
}
dcpPacket->control0 = 0x22u; /* ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
dcpPacket->control0 = 0x22u | (handle->swapConfig & 0xFC0000u); /* ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
dcpPacket->bufferSize = (uint32_t)size;
dcpPacket->bufferSize = (uint32_t)size;
if (handle->keySlot == kDCP_OtpKey)
{
@ -458,6 +520,20 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Encrypts AES using CBC block mode.
*
* Encrypts AES using CBC block mode.
* The source plaintext and destination ciphertext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param plaintext Input plain text to encrypt
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return Status from encrypt operation
*/
status_t DCP_AES_EncryptCbc(DCP_Type *base,
dcp_handle_t *handle,
const uint8_t *plaintext,
@ -481,6 +557,21 @@ status_t DCP_AES_EncryptCbc(DCP_Type *base,
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Encrypts AES using CBC block mode.
*
* Puts AES CBC encrypt dcpPacket to DCP input job ring.
*
* param base DCP peripheral base address
* param handle Handle used for this request. Specifies jobRing.
* param[out] dcpPacket Memory for the DCP work packet.
* param plaintext Input plain text to encrypt
* param[out] ciphertext Output cipher text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -495,11 +586,12 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
return kStatus_InvalidArgument;
}
dcpPacket->control0 = 0x322u; /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
dcpPacket->control0 =
0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
dcpPacket->bufferSize = (uint32_t)size;
dcpPacket->bufferSize = (uint32_t)size;
if (handle->keySlot == kDCP_OtpKey)
{
@ -530,6 +622,20 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Decrypts AES using CBC block mode.
*
* Decrypts AES using CBC block mode.
* The source ciphertext and destination plaintext can overlap in system memory.
*
* param base DCP peripheral base address
* param handle Handle used for this request.
* param ciphertext Input cipher text to decrypt
* param[out] plaintext Output plain text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return Status from decrypt operation
*/
status_t DCP_AES_DecryptCbc(DCP_Type *base,
dcp_handle_t *handle,
const uint8_t *ciphertext,
@ -553,6 +659,21 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base,
return DCP_WaitForChannelComplete(base, handle);
}
/*!
* brief Decrypts AES using CBC block mode.
*
* Puts AES CBC decrypt dcpPacket to DCP input job ring.
*
* param base DCP peripheral base address
* param handle Handle used for this request. Specifies jobRing.
* param[out] dcpPacket Memory for the DCP work packet.
* param ciphertext Input cipher text to decrypt
* param[out] plaintext Output plain text
* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* param iv Input initial vector to combine with the first input block.
* return kStatus_Success The work packet has been scheduled at DCP channel.
* return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,
@ -567,11 +688,11 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
return kStatus_InvalidArgument;
}
dcpPacket->control0 = 0x222u; /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
dcpPacket->control1 = 0x10u; /* CBC */
dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
dcpPacket->bufferSize = (uint32_t)size;
dcpPacket->bufferSize = (uint32_t)size;
if (handle->keySlot == kDCP_OtpKey)
{
@ -602,12 +723,29 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
return dcp_schedule_work(base, handle, dcpPacket);
}
/*!
* brief Gets the default configuration structure.
*
* This function initializes the DCP configuration structure to a default value. The default
* values are as follows.
* dcpConfig->gatherResidualWrites = true;
* dcpConfig->enableContextCaching = true;
* dcpConfig->enableContextSwitching = true;
* dcpConfig->enableChannnel = kDCP_chEnableAll;
* dcpConfig->enableChannelInterrupt = kDCP_chIntDisable;
*
* param[out] config Pointer to configuration structure.
*/
void DCP_GetDefaultConfig(dcp_config_t *config)
{
/* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses
* dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support
* Hash context switch (different messages interleaved) on the same channel.
*/
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
dcp_config_t userConfig = {
true, false, true, kDCP_chEnableAll, kDCP_chIntDisable,
};
@ -615,6 +753,14 @@ void DCP_GetDefaultConfig(dcp_config_t *config)
*config = userConfig;
}
/*!
* brief Enables clock to and enables DCP
*
* Enable DCP clock and configure DCP.
*
* param base DCP base address
* param config Pointer to configuration structure.
*/
void DCP_Init(DCP_Type *base, const dcp_config_t *config)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -639,6 +785,13 @@ void DCP_Init(DCP_Type *base, const dcp_config_t *config)
base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer;
}
/*!
* brief Disable DCP clock
*
* Reset DCP and Disable DCP clock.
*
* param base DCP base address
*/
void DCP_Deinit(DCP_Type *base)
{
base->CTRL = 0xF0800000u; /* reset value */
@ -649,6 +802,16 @@ void DCP_Deinit(DCP_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Poll and wait on DCP channel.
*
* Polls the specified DCP channel until current it completes activity.
*
* param base DCP peripheral base address.
* param handle Specifies DCP channel.
* return kStatus_Success When data processing completes without error.
* return kStatus_Fail When error occurs.
*/
status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle)
{
/* wait if our channel is still active */
@ -663,6 +826,7 @@ status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle)
return kStatus_Fail;
}
dcp_clear_status(base);
return kStatus_Success;
}
@ -745,7 +909,7 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct
if ((kDCP_Sha256 == ctxInternal->algo) || (kDCP_Sha1 == ctxInternal->algo) || (kDCP_Crc32 == ctxInternal->algo))
{
ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT;
status = kStatus_Success;
status = kStatus_Success;
}
return status;
@ -754,7 +918,8 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct
static status_t dcp_hash_update_non_blocking(
DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
{
dcpPacket->control0 = ctxInternal->ctrl0 | kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) |
kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
if (ctxInternal->algo == kDCP_Sha256)
{
dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256;
@ -771,10 +936,10 @@ static status_t dcp_hash_update_non_blocking(
{
return kStatus_Fail;
}
dcpPacket->sourceBufferAddress = (uint32_t)msg;
dcpPacket->sourceBufferAddress = (uint32_t)msg;
dcpPacket->destinationBufferAddress = 0;
dcpPacket->bufferSize = size;
dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash;
dcpPacket->bufferSize = size;
dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash;
return dcp_schedule_work(base, ctxInternal->handle, dcpPacket);
}
@ -932,6 +1097,17 @@ static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal)
}
}
/*!
* brief Initialize HASH context
*
* This function initializes the HASH.
*
* param base DCP peripheral base address
* param handle Specifies the DCP channel used for hashing.
* param[out] ctx Output hash context
* param algo Underlaying algorithm to use for hash computation.
* return Status of initialization
*/
status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
{
status_t status;
@ -948,19 +1124,34 @@ status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx
}
/* set algorithm in context struct for later use */
ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
ctxInternal->algo = algo;
ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
ctxInternal->algo = algo;
ctxInternal->blksz = 0u;
for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++)
{
ctxInternal->blk.w[0] = 0u;
}
ctxInternal->state = kDCP_StateHashInit;
ctxInternal->state = kDCP_StateHashInit;
ctxInternal->fullMessageSize = 0;
ctxInternal->handle = handle;
ctxInternal->handle = handle;
return status;
}
/*!
* brief Add data to current HASH
*
* Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
* hashed. The functions blocks. If it returns kStatus_Success, the running hash
* has been updated (DCP has processed the input data), so the memory at ref input pointer
* can be released back to system. The DCP context buffer is updated with the running hash
* and with all necessary information to support possible context switch.
*
* param base DCP peripheral base address
* param[in,out] ctx HASH context
* param input Input data
* param inputSize Size of input data in bytes
* return Status of the hash update operation
*/
status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
{
bool isUpdateState;
@ -974,7 +1165,7 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp
}
ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
status = dcp_hash_check_context(ctxInternal, input);
status = dcp_hash_check_context(ctxInternal, input);
if (kStatus_Success != status)
{
return status;
@ -1014,6 +1205,17 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp
return status;
}
/*!
* brief Finalize hashing
*
* Outputs the final hash (computed by DCP_HASH_Update()) and erases the context.
*
* param[in,out] ctx Input hash context
* param[out] output Output hash data
* param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
* output[] buffer. On function return, it stores the number of updated output bytes.
* return Status of the hash finish operation
*/
status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize)
{
size_t algOutSize = 0;
@ -1021,7 +1223,7 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s
dcp_hash_ctx_internal_t *ctxInternal;
ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
status = dcp_hash_check_context(ctxInternal, output);
status = dcp_hash_check_context(ctxInternal, output);
if (kStatus_Success != status)
{
return status;
@ -1100,6 +1302,20 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s
return status;
}
/*!
* brief Create HASH on given data
*
* Perform the full SHA or CRC32 in one function call. The function is blocking.
*
* param base DCP peripheral base address
* param handle Handle used for the request.
* param algo Underlaying algorithm to use for hash computation.
* param input Input data
* param inputSize Size of input data in bytes
* param[out] output Output hash data
* param[out] outputSize Output parameter storing the size of the output hash in bytes
* return Status of the one call hash operation.
*/
status_t DCP_HASH(DCP_Type *base,
dcp_handle_t *handle,
dcp_hash_algo_t algo,

105
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DCP_H_
@ -53,15 +27,21 @@ enum _dcp_status
*/
/*! @name Driver version */
/*@{*/
/*! @brief DCP driver version. Version 2.0.0.
/*! @brief DCP driver version. Version 2.1.1.
*
* Current version: 2.0.0
* Current version: 2.1.1
*
* Change log:
* - Version 2.1.1
* - Add DCP status clearing when channel operation is complete
*
* - 2.1.0
* - Add byte/word swap feature for key, input and output data
*
* - Version 2.0.0
* - Initial version
*/
#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*! @brief DCP channel enable.
@ -69,11 +49,11 @@ enum _dcp_status
*/
typedef enum _dcp_ch_enable
{
kDCP_chDisable = 0U, /*!< DCP channel disable */
kDCP_ch0Enable = 1U, /*!< DCP channel 0 enable */
kDCP_ch1Enable = 2U, /*!< DCP channel 1 enable */
kDCP_ch2Enable = 4U, /*!< DCP channel 2 enable */
kDCP_ch3Enable = 8U, /*!< DCP channel 3 enable */
kDCP_chDisable = 0U, /*!< DCP channel disable */
kDCP_ch0Enable = 1U, /*!< DCP channel 0 enable */
kDCP_ch1Enable = 2U, /*!< DCP channel 1 enable */
kDCP_ch2Enable = 4U, /*!< DCP channel 2 enable */
kDCP_ch3Enable = 8U, /*!< DCP channel 3 enable */
kDCP_chEnableAll = 15U, /*!< DCP channel enable all */
} _dcp_ch_enable_t;
@ -105,15 +85,29 @@ typedef enum _dcp_channel
*/
typedef enum _dcp_key_slot
{
kDCP_KeySlot0 = 0U, /*!< DCP key slot 0. */
kDCP_KeySlot1 = 1U, /*!< DCP key slot 1. */
kDCP_KeySlot2 = 2U, /*!< DCP key slot 2.*/
kDCP_KeySlot3 = 3U, /*!< DCP key slot 3. */
kDCP_OtpKey = 4U, /*!< DCP OTP key. */
kDCP_KeySlot0 = 0U, /*!< DCP key slot 0. */
kDCP_KeySlot1 = 1U, /*!< DCP key slot 1. */
kDCP_KeySlot2 = 2U, /*!< DCP key slot 2.*/
kDCP_KeySlot3 = 3U, /*!< DCP key slot 3. */
kDCP_OtpKey = 4U, /*!< DCP OTP key. */
kDCP_OtpUniqueKey = 5U, /*!< DCP unique OTP key. */
kDCP_PayloadKey = 6U, /*!< DCP payload key. */
kDCP_PayloadKey = 6U, /*!< DCP payload key. */
} dcp_key_slot_t;
/*! @brief DCP key, input & output swap options
*
*/
typedef enum _dcp_swap
{
kDCP_NoSwap = 0x0U,
kDCP_KeyByteSwap = 0x40000U,
kDCP_KeyWordSwap = 0x80000U,
kDCP_InputByteSwap = 0x100000U,
kDCP_InputWordSwap = 0x200000U,
kDCP_OutputByteSwap = 0x400000U,
kDCP_OutputWordSwap = 0x800000U,
} dcp_swap_t;
/*! @brief DCP's work packet. */
typedef struct _dcp_work_packet
{
@ -132,6 +126,7 @@ typedef struct _dcp_handle
{
dcp_channel_t channel; /*!< Specify DCP channel. */
dcp_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify DCP key slot. */
uint32_t swapConfig; /*!< For configuration of key, input, output byte/word swap options */
uint32_t keyWord[4];
uint32_t iv[4];
} dcp_handle_t;
@ -382,19 +377,19 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base,
* @{
*/
/*!
* @brief Encrypts AES using the ECB block mode.
*
* Puts AES ECB encrypt work packet to DCP channel.
*
* @param base DCP peripheral base address
* @param handle Handle used for this request.
* @param[out] dcpPacket Memory for the DCP work packet.
* @param plaintext Input plain text to encrypt.
* @param[out] ciphertext Output cipher text
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* @return kStatus_Success The work packet has been scheduled at DCP channel.
* @return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
* @brief Encrypts AES using the ECB block mode.
*
* Puts AES ECB encrypt work packet to DCP channel.
*
* @param base DCP peripheral base address
* @param handle Handle used for this request.
* @param[out] dcpPacket Memory for the DCP work packet.
* @param plaintext Input plain text to encrypt.
* @param[out] ciphertext Output cipher text
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* @return kStatus_Success The work packet has been scheduled at DCP channel.
* @return kStatus_DCP_Again The DCP channel is busy processing previous request.
*/
status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
dcp_handle_t *handle,
dcp_work_packet_t *dcpPacket,

44
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_dmamux.h"
@ -43,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.dmamux"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -88,6 +61,14 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
return instance;
}
/*!
* brief Initializes the DMAMUX peripheral.
*
* This function ungates the DMAMUX clock.
*
* param base DMAMUX peripheral base address.
*
*/
void DMAMUX_Init(DMAMUX_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -95,6 +76,13 @@ void DMAMUX_Init(DMAMUX_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Deinitializes the DMAMUX peripheral.
*
* This function gates the DMAMUX clock.
*
* param base DMAMUX peripheral base address.
*/
void DMAMUX_Deinit(DMAMUX_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)

49
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DMAMUX_H_
@ -42,15 +16,14 @@
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief DMAMUX driver version 2.0.2. */
#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*! @brief DMAMUX driver version 2.0.3. */
#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
/*******************************************************************************
@ -101,7 +74,7 @@ void DMAMUX_Deinit(DMAMUX_Type *base);
*/
static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
}
@ -117,9 +90,9 @@ static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
*/
static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK;
}
/*!
@ -131,9 +104,9 @@ static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
*/
static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
}
#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
@ -147,7 +120,7 @@ static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_
*/
static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
}
@ -162,9 +135,9 @@ static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channe
*/
static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK;
}
#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */

1240
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c
View File

File diff suppressed because it is too large Load Diff

126
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EDMA_H_
@ -49,22 +23,19 @@
/*! @name Driver version */
/*@{*/
/*! @brief eDMA driver version */
#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */
#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*!< Version 2.1.7. */
/*@}*/
/*! @brief Compute the offset unit from DCHPRI3 */
#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
/*! @brief Get the pointer of DCHPRIn */
#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3U - ((channel)&0x03U)))
/*! @brief eDMA transfer configuration */
typedef enum _edma_transfer_size
{
kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */
kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */
kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
} edma_transfer_size_t;
@ -109,7 +80,7 @@ typedef enum _edma_modulo
/*! @brief Bandwidth control */
typedef enum _edma_bandwidth
{
kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */
kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */
kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */
} edma_bandwidth_t;
@ -125,29 +96,29 @@ typedef enum _edma_channel_link_type
/*!@brief eDMA channel status flags. */
enum _edma_channel_status_flags
{
kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/
kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */
kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/
kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */
kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */
};
/*! @brief eDMA channel error status flags. */
enum _edma_error_status_flags
{
kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */
kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */
kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */
kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */
kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */
kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */
kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */
kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */
kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */
kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */
kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */
kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/
kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */
kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */
kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */
#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */
kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/
kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */
kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */
kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */
#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1)
kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
#endif
kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
};
/*! @brief eDMA interrupt source */
@ -155,7 +126,7 @@ typedef enum _edma_interrupt_enable
{
kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */
kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */
kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */
kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */
} edma_interrupt_enable_t;
/*! @brief eDMA transfer type */
@ -170,7 +141,7 @@ typedef enum _edma_transfer_type
enum _edma_transfer_status
{
kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */
kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the
kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the
transfer request. */
};
@ -239,7 +210,7 @@ typedef struct _edma_tcd
__IO uint32_t DADDR; /*!< DADDR register, used for destination address */
__IO uint16_t DOFF; /*!< DOFF register, used for destination offset */
__IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
__IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */
__IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
__IO uint16_t CSR; /*!< CSR register, for TCD control status */
__IO uint16_t BITER; /*!< BITER register, begin minor loop count. */
} edma_tcd_t;
@ -255,10 +226,10 @@ struct _edma_handle;
* all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.
*
* @param handle EDMA handle pointer, users shall not touch the values inside.
* @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to
* @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to
* change in EDMA callback function.
* @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter
* gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the
* gather mode, this parameter shows is the current transfer block in EDMA register is done. As the
* load of core is different, it will be different if the new tcd loaded into EDMA registers while
* this callback called. If true, it always means new tcd still not loaded into registers, while
* false means new tcd already loaded into registers.
@ -411,17 +382,7 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino
* @param channel eDMA channel number
* @param config A pointer to the channel preemption configuration structure.
*/
static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
uint32_t channel,
const edma_channel_Preemption_config_t *config)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
assert(config != NULL);
DMA_DCHPRIn(base, channel) =
(DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) |
DMA_DCHPRI0_CHPRI(config->channelPriority));
}
void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config);
/*!
* @brief Sets the channel link for the eDMA transfer.
@ -481,9 +442,9 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e
*/
static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel);
base->EARS = (base->EARS & (uint32_t)(~(1U << channel))) | ((true == enable ? 1U : 0U) << channel);
}
#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */
@ -498,9 +459,10 @@ static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, boo
*/
static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
base->TCD[channel].CSR =
(uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U)));
}
/*!
@ -611,9 +573,9 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
{
assert(tcd != NULL);
assert(((uint32_t)tcd & 0x1FU) == 0);
assert(((uint32_t)tcd & 0x1FU) == 0U);
tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth));
}
/*!
@ -640,9 +602,9 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d
static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
{
assert(tcd != NULL);
assert(((uint32_t)tcd & 0x1FU) == 0);
assert(((uint32_t)tcd & 0x1FU) == 0U);
tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U)));
}
/*!
@ -679,7 +641,7 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
*/
static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->SERQ = DMA_SERQ_SERQ(channel);
}
@ -694,7 +656,7 @@ static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
*/
static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->CERQ = DMA_CERQ_CERQ(channel);
}
@ -709,7 +671,7 @@ static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
*/
static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
base->SSRT = DMA_SSRT_SSRT(channel);
}
@ -748,7 +710,7 @@ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel);
*
* @param base eDMA peripheral base address.
* @return The mask of error status flags. Users need to use the
* _edma_error_status_flags type to decode the return variables.
* _edma_error_status_flags type to decode the return variables.
*/
static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
{
@ -799,7 +761,7 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
* This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
* while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
* (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
* Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
* Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
*
* @param handle eDMA handle pointer.
* @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
@ -900,7 +862,9 @@ void EDMA_AbortTransfer(edma_handle_t *handle);
*/
static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)
{
return (handle->tcdSize - handle->tcdUsed);
int8_t tmpTcdSize = handle->tcdSize;
int8_t tmpTcdUsed = handle->tcdUsed;
return ((uint32_t)tmpTcdSize - (uint32_t)tmpTcdUsed);
}
/*!

142
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_elcdif.h"
@ -39,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.elcdif"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -117,6 +90,15 @@ static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
return instance;
}
/*!
* brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
*
* This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
* to the configuration structure.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
{
assert(config);
@ -160,14 +142,16 @@ void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config
base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK |
((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT);
base->CUR_BUF = config->bufferAddr;
base->CUR_BUF = config->bufferAddr;
base->NEXT_BUF = config->bufferAddr;
}
void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
{
assert(config);
/*!
* brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
*
* This function sets the configuration structure to default values.
* The default configuration is set to the following values.
* code
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
@ -176,13 +160,61 @@ void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow |
config->polarityFlags = kELCDIF_VsyncActiveLow |
kELCDIF_HsyncActiveLow |
kELCDIF_DataEnableActiveLow |
kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
code
*
* param config Pointer to the eLCDIF configuration structure.
*/
void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow |
kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
}
/*!
* brief Set the pixel format in RGB (DOTCLK) mode.
*
* param base eLCDIF peripheral base address.
* param pixelFormat The pixel format.
*/
void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat)
{
assert(pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
base->CTRL = (base->CTRL & ~(LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK |
LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK | LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)) |
s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl;
base->CTRL1 = s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl1;
}
/*!
* brief Deinitializes the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Deinit(LCDIF_Type *base)
{
ELCDIF_Reset(base);
@ -197,6 +229,11 @@ void ELCDIF_Deinit(LCDIF_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Stop display in RGB (DOTCLK) mode and wait until finished.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_RgbModeStop(LCDIF_Type *base)
{
base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
@ -207,6 +244,11 @@ void ELCDIF_RgbModeStop(LCDIF_Type *base)
}
}
/*!
* brief Reset the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Reset(LCDIF_Type *base)
{
volatile uint32_t i = 0x100;
@ -237,15 +279,27 @@ void ELCDIF_Reset(LCDIF_Type *base)
}
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
/*!
* brief Set the configuration for alpha surface buffer.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
{
assert(config);
base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
base->AS_BUF = config->bufferAddr;
base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
base->AS_BUF = config->bufferAddr;
base->AS_NEXT_BUF = config->bufferAddr;
}
/*!
* brief Set the alpha surface blending configuration.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
{
assert(config);
@ -267,6 +321,20 @@ void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_c
#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
/*!
* brief Load the LUT value.
*
* This function loads the LUT value to the specific LUT memory, user can
* specify the start entry index.
*
* param base eLCDIF peripheral base address.
* param lut Which LUT to load.
* param startIndex The start index of the LUT entry to update.
* param lutData The LUT data to load.
* param count Count of p lutData.
* retval kStatus_Success Initialization success.
* retval kStatus_InvalidArgument Wrong argument.
*/
status_t ELCDIF_UpdateLut(
LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
{

106
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2017, NXP Semiconductors, Inc.
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ELCDIF_H_
@ -49,7 +23,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief eLCDIF driver version */
#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
/*@}*/
/* All IRQ flags in CTRL1 register. */
@ -88,14 +62,14 @@
*/
enum _elcdif_polarity_flags
{
kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */
kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */
kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */
kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */
kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */
kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */
kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data
on rising clock edge. */
kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */
kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */
kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */
kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */
kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */
kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */
kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data
on rising clock edge. */
kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling
clock edge, capture data
on rising clock edge. */
@ -106,8 +80,8 @@ enum _elcdif_polarity_flags
*/
enum _elcdif_interrupt_enable
{
kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */
kELCDIF_CurFrameDoneInterruptEnable =
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
@ -124,8 +98,8 @@ enum _elcdif_interrupt_enable
*/
enum _elcdif_interrupt_flags
{
kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */
kELCDIF_CurFrameDone =
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
@ -140,9 +114,9 @@ enum _elcdif_interrupt_flags
*/
enum _elcdif_status_flags
{
kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */
kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */
kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */
kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */
kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */
kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */
kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */
#if defined(LCDIF_STAT_BUSY_MASK)
kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */
@ -161,18 +135,18 @@ enum _elcdif_status_flags
*/
typedef enum _elcdif_pixel_format
{
kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */
kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */
kELCDIF_PixelFormatRGB565 = 1, /*!< RGB565, two pixel use 32 bits. */
kELCDIF_PixelFormatRGB666 = 2, /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused,
upper 2 bits of other bytes unused. */
kELCDIF_PixelFormatXRGB8888 = 3, /*!< XRGB8888 unpacked, one pixel uses 32 bits, high byte unused. */
kELCDIF_PixelFormatRGB888 = 4, /*!< RGB888 packed, one pixel uses 24 bits. */
kELCDIF_PixelFormatRGB888 = 4, /*!< RGB888 packed, one pixel uses 24 bits. */
} elcdif_pixel_format_t;
/*! @brief The LCD data bus type. */
typedef enum _elcdif_lcd_data_bus
{
kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */
kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */
kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */
kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */
kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */
@ -219,12 +193,12 @@ typedef struct _elcdif_rgb_mode_config
typedef enum _elcdif_as_pixel_format
{
kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
} elcdif_as_pixel_format_t;
/*!
@ -261,18 +235,18 @@ typedef enum _elcdif_alpha_mode
*/
typedef enum _elcdif_rop_mode
{
kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */
kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */
kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */
kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */
kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */
kELCDIF_RopNot = 0x7, /*!< nPS. */
kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */
kELCDIF_RopNot = 0x7, /*!< nPS. */
kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */
kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */
kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */
kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */
} elcdif_rop_mode_t;
/*!
@ -367,6 +341,14 @@ void ELCDIF_Deinit(LCDIF_Type *base);
* @{
*/
/*!
* @brief Set the pixel format in RGB (DOTCLK) mode.
*
* @param base eLCDIF peripheral base address.
* @param pixelFormat The pixel format.
*/
void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat);
/*!
* @brief Start to display in RGB (DOTCLK) mode.
*
@ -513,7 +495,7 @@ static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base)
#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
| LCDIF_STAT_DVI_CURRENT_FIELD_MASK
#endif
);
);
}
/*!
@ -644,7 +626,7 @@ static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32
*/
static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
{
base->AS_CLRKEYLOW = colorKeyLow;
base->AS_CLRKEYLOW = colorKeyLow;
base->AS_CLRKEYHIGH = colorKeyHigh;
}

185
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_enc.h"
@ -88,6 +62,17 @@ static uint32_t ENC_GetInstance(ENC_Type *base)
return instance;
}
/*!
* brief Initialization for the ENC module.
*
* This function is to make the initialization for the ENC module. It should be called firstly before any operation to
* the ENC with the operations like:
* - Enable the clock for ENC module.
* - Configure the ENC's working attributes.
*
* param base ENC peripheral base address.
* param config Pointer to configuration structure. See to "enc_config_t".
*/
void ENC_Init(ENC_Type *base, const enc_config_t *config)
{
assert(NULL != config);
@ -177,6 +162,15 @@ void ENC_Init(ENC_Type *base, const enc_config_t *config)
base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */
}
/*!
* brief De-initialization for the ENC module.
*
* This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with
* the operations like:
* - Disable the clock for ENC module.
*
* param base ENC peripheral base address.
*/
void ENC_Deinit(ENC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -185,28 +179,63 @@ void ENC_Deinit(ENC_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Get an available pre-defined settings for ENC's configuration.
*
* This function initializes the ENC configuration structure with an available settings, the default value are:
* code
* config->enableReverseDirection = false;
* config->decoderWorkMode = kENC_DecoderWorkAsNormalMode;
* config->HOMETriggerMode = kENC_HOMETriggerDisabled;
* config->INDEXTriggerMode = kENC_INDEXTriggerDisabled;
* config->enableTRIGGERClearPositionCounter = false;
* config->enableTRIGGERClearHoldPositionCounter = false;
* config->enableWatchdog = false;
* config->watchdogTimeoutValue = 0U;
* config->filterCount = 0U;
* config->filterSamplePeriod = 0U;
* config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
* config->positionCompareValue = 0xFFFFFFFFU;
* config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse;
* config->enableModuloCountMode = false;
* config->positionModulusValue = 0U;
* config->positionInitialValue = 0U;
* endcode
* param config Pointer to a variable of configuration structure. See to "enc_config_t".
*/
void ENC_GetDefaultConfig(enc_config_t *config)
{
assert(NULL != config);
config->enableReverseDirection = false;
config->decoderWorkMode = kENC_DecoderWorkAsNormalMode;
config->HOMETriggerMode = kENC_HOMETriggerDisabled;
config->INDEXTriggerMode = kENC_INDEXTriggerDisabled;
config->enableTRIGGERClearPositionCounter = false;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableReverseDirection = false;
config->decoderWorkMode = kENC_DecoderWorkAsNormalMode;
config->HOMETriggerMode = kENC_HOMETriggerDisabled;
config->INDEXTriggerMode = kENC_INDEXTriggerDisabled;
config->enableTRIGGERClearPositionCounter = false;
config->enableTRIGGERClearHoldPositionCounter = false;
config->enableWatchdog = false;
config->watchdogTimeoutValue = 0U;
config->filterCount = 0U;
config->filterSamplePeriod = 0U;
config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
config->positionCompareValue = 0xFFFFFFFFU;
config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse;
config->enableModuloCountMode = false;
config->positionModulusValue = 0U;
config->positionInitialValue = 0U;
config->enableWatchdog = false;
config->watchdogTimeoutValue = 0U;
config->filterCount = 0U;
config->filterSamplePeriod = 0U;
config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
config->positionCompareValue = 0xFFFFFFFFU;
config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse;
config->enableModuloCountMode = false;
config->positionModulusValue = 0U;
config->positionInitialValue = 0U;
}
/*!
* brief Load the initial position value to position counter.
*
* This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and
* LPOS), so that to provide the consistent operation the position counter registers.
*
* param base ENC peripheral base address.
*/
void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)
{
uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS);
@ -215,6 +244,16 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)
base->CTRL = tmp16;
}
/*!
* brief Enable and configure the self test function.
*
* This function is to enable and configuration the self test function. It controls and sets the frequency of a
* quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module.
* It is a factory test feature; however, it may be useful to customers' software development and testing.
*
* param base ENC peripheral base address.
* param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable.
*/
void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)
{
uint16_t tmp16 = 0U;
@ -233,6 +272,12 @@ void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)
base->TST = tmp16;
}
/*!
* brief Enable watchdog for ENC module.
*
* param base ENC peripheral base address
* param enable Enables or disables the watchdog
*/
void ENC_EnableWatchdog(ENC_Type *base, bool enable)
{
uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK));
@ -244,6 +289,13 @@ void ENC_EnableWatchdog(ENC_Type *base, bool enable)
base->CTRL = tmp16;
}
/*!
* brief Get the status flags.
*
* param base ENC peripheral base address.
*
* return Mask value of status flags. For available mask, see to "_enc_status_flags".
*/
uint32_t ENC_GetStatusFlags(ENC_Type *base)
{
uint32_t ret32 = 0U;
@ -287,6 +339,12 @@ uint32_t ENC_GetStatusFlags(ENC_Type *base)
return ret32;
}
/*!
* brief Clear the status flags.
*
* param base ENC peripheral base address.
* param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags".
*/
void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)
{
uint32_t tmp16 = 0U;
@ -333,6 +391,12 @@ void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)
}
}
/*!
* brief Enable the interrupts.
*
* param base ENC peripheral base address.
* param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable".
*/
void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)
{
uint32_t tmp16 = 0U;
@ -378,6 +442,12 @@ void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)
}
}
/*!
* brief Disable the interrupts.
*
* param base ENC peripheral base address.
* param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable".
*/
void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)
{
uint16_t tmp16 = 0U;
@ -423,6 +493,13 @@ void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)
}
}
/*!
* brief Get the enabled interrupts' flags.
*
* param base ENC peripheral base address.
*
* return Mask value of enabled interrupts.
*/
uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)
{
uint32_t ret32 = 0U;
@ -460,12 +537,25 @@ uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)
return ret32;
}
/*!
* brief Set initial position value for ENC module.
*
* param base ENC peripheral base address
* param value Positive initial value
*/
void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value)
{
base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */
base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */
}
/*!
* brief Get the current position counter's value.
*
* param base ENC peripheral base address.
*
* return Current position counter's value.
*/
uint32_t ENC_GetPositionValue(ENC_Type *base)
{
uint32_t ret32;
@ -477,6 +567,17 @@ uint32_t ENC_GetPositionValue(ENC_Type *base)
return ret32;
}
/*!
* brief Get the hold position counter's value.
*
* When any of the counter registers is read, the contents of each counter register is written to the corresponding hold
* register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to
* be attained.
*
* param base ENC peripheral base address.
*
* return Hold position counter's value.
*/
uint32_t ENC_GetHoldPositionValue(ENC_Type *base)
{
uint32_t ret32;

68
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ENC_H_
@ -51,13 +25,13 @@
*/
enum _enc_interrupt_enable
{
kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */
kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */
kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */
kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */
kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */
kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */
kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */
kENC_SimultBothPhaseChangeInterruptEnable =
(1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */
kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */
kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */
kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */
};
@ -68,14 +42,14 @@ enum _enc_interrupt_enable
*/
enum _enc_status_flags
{
kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */
kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */
kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */
kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */
kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */
kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */
kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */
kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */
kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */
kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */
kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */
kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */
kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */
kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */
kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */
};
/*!
@ -85,14 +59,14 @@ enum _enc_status_flags
*/
enum _enc_signal_status_flags
{
kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */
kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */
kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */
kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */
kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */
kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */
kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */
kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */
kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */
kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */
kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */
kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */
kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */
kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */
kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */
kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */
};
/*!
@ -177,7 +151,7 @@ typedef struct _enc_config
enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */
bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */
bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not.
*/
*/
/* Watchdog. */
bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */

770
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c
View File

File diff suppressed because it is too large Load Diff

103
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ENET_H_
#define _FSL_ENET_H_
@ -50,7 +24,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief Defines the driver version. */
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*!< Version 2.2.4. */
/*@}*/
/*! @name ENET DESCRIPTOR QUEUE */
@ -445,7 +419,7 @@ typedef struct _enet_tx_bd_struct
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
} enet_tx_bd_struct_t;
/*! @brief Defines the ENET data error statistic structure. */
/*! @brief Defines the ENET data error statistics structure. */
typedef struct _enet_data_error_stats
{
uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */
@ -619,9 +593,8 @@ typedef struct _enet_config
uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO
before a frame transmit start. */
#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
enet_intcoalesce_config_t
*intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set
to NULL. */
enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2),
please set to NULL. */
#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
uint8_t ringNum; /*!< Number of used rings. default with 1 -- single ring. */
} enet_config_t;
@ -1169,21 +1142,21 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/*!
* @brief Gets the size of the read frame for single ring.
*
* This function gets a received frame size from the ENET buffer descriptors.
* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
*
* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
* @param length The length of the valid frame received.
* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
* and NULL length to update the receive buffers.
* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
* should be called with the right data buffer and the captured data length input.
*/
* @brief Gets the size of the read frame for single ring.
*
* This function gets a received frame size from the ENET buffer descriptors.
* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
*
* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
* @param length The length of the valid frame received.
* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
* and NULL length to update the receive buffers.
* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
* should be called with the right data buffer and the captured data length input.
*/
status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length);
/*!
@ -1303,23 +1276,23 @@ status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle,
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/*!
* @brief Gets the size of the read frame for extended mutli-ring.
*
* This function gets a received frame size from the ENET buffer descriptors.
* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
* After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the
* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is
* the same to the single ring, refer to ENET_GetRxFrameSize.
*
* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
* @param length The length of the valid frame received.
* @param ringId The ring index or ring number;
* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame.
* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data
* and NULL length to update the receive buffers.
* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
* should be called with the right data buffer and the captured data length input.
*/
* @brief Gets the size of the read frame for extended mutli-ring.
*
* This function gets a received frame size from the ENET buffer descriptors.
* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
* After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the
* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is
* the same to the single ring, refer to ENET_GetRxFrameSize.
*
* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
* @param length The length of the valid frame received.
* @param ringId The ring index or ring number;
* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame.
* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data
* and NULL length to update the receive buffers.
* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
* should be called with the right data buffer and the captured data length input.
*/
status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId);
/*!

100
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_ewm.h"
@ -39,11 +13,29 @@
#define FSL_COMPONENT_ID "platform.drivers.ewm"
#endif
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief Initializes the EWM peripheral.
*
* This function is used to initialize the EWM. After calling, the EWM
* runs immediately according to the configuration.
* Note that, except for the interrupt enable control bit, other control bits and registers are write once after a
* CPU reset. Modifying them more than once generates a bus transfer error.
*
* This is an example.
* code
* ewm_config_t config;
* EWM_GetDefaultConfig(&config);
* config.compareHighValue = 0xAAU;
* EWM_Init(ewm_base,&config);
* endcode
*
* param base EWM peripheral base address
* param config The configuration of the EWM
*/
void EWM_Init(EWM_Type *base, const ewm_config_t *config)
{
assert(config);
@ -51,7 +43,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
uint32_t value = 0U;
#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(kCLOCK_Ewm0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@ -71,42 +63,78 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
base->CTRL = value;
}
/*!
* brief Deinitializes the EWM peripheral.
*
* This function is used to shut down the EWM.
*
* param base EWM peripheral base address
*/
void EWM_Deinit(EWM_Type *base)
{
EWM_DisableInterrupts(base, kEWM_InterruptEnable);
#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
(defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(kCLOCK_Ewm0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */
}
/*!
* brief Initializes the EWM configuration structure.
*
* This function initializes the EWM configuration structure to default values. The default
* values are as follows.
* code
* ewmConfig->enableEwm = true;
* ewmConfig->enableEwmInput = false;
* ewmConfig->setInputAssertLogic = false;
* ewmConfig->enableInterrupt = false;
* ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
* ewmConfig->prescaler = 0;
* ewmConfig->compareLowValue = 0;
* ewmConfig->compareHighValue = 0xFEU;
* endcode
*
* param config Pointer to the EWM configuration structure.
* see ewm_config_t
*/
void EWM_GetDefaultConfig(ewm_config_t *config)
{
assert(config);
config->enableEwm = true;
config->enableEwmInput = false;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableEwm = true;
config->enableEwmInput = false;
config->setInputAssertLogic = false;
config->enableInterrupt = false;
config->enableInterrupt = false;
#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
config->clockSource = kEWM_LpoClockSource0;
#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/
#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
config->prescaler = 0U;
#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */
config->compareLowValue = 0U;
config->compareLowValue = 0U;
config->compareHighValue = 0xFEU;
}
/*!
* brief Services the EWM.
*
* This function resets the EWM counter to zero.
*
* param base EWM peripheral base address
*/
void EWM_Refresh(EWM_Type *base)
{
uint32_t primaskValue = 0U;
/* Disable the global interrupt to protect refresh sequence */
primaskValue = DisableGlobalIRQ();
base->SERV = (uint8_t)0xB4U;
base->SERV = (uint8_t)0x2CU;
base->SERV = (uint8_t)0xB4U;
base->SERV = (uint8_t)0x2CU;
EnableGlobalIRQ(primaskValue);
}

43
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EWM_H_
#define _FSL_EWM_H_
@ -41,7 +15,6 @@
* @{
*/
/*******************************************************************************
* Definitions
*******************************************************************************/
@ -64,10 +37,10 @@ typedef enum _ewm_lpo_clock_source
#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */
/*!
* @brief Data structure for EWM configuration.
*
* This structure is used to configure the EWM.
*/
* @brief Data structure for EWM configuration.
*
* This structure is used to configure the EWM.
*/
typedef struct _ewm_config
{
bool enableEwm; /*!< Enable EWM module */
@ -135,7 +108,7 @@ extern "C" {
*
* @param base EWM peripheral base address
* @param config The configuration of the EWM
*/
*/
void EWM_Init(EWM_Type *base, const ewm_config_t *config);
/*!
@ -144,7 +117,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config);
* This function is used to shut down the EWM.
*
* @param base EWM peripheral base address
*/
*/
void EWM_Deinit(EWM_Type *base);
/*!
@ -231,7 +204,7 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
* This function resets the EWM counter to zero.
*
* @param base EWM peripheral base address
*/
*/
void EWM_Refresh(EWM_Type *base);
/*@}*/

2042
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c
View File

File diff suppressed because it is too large Load Diff

271
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXCAN_H_
#define _FSL_FLEXCAN_H_
@ -47,10 +21,15 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexCAN driver version 2.2.0. */
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*! @brief FlexCAN driver version 2.4.0. */
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
/*@}*/
#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */
#define FLEXCAN_WAIT_TIMEOUT (1000U)
#endif
/*! @brief FlexCAN Frame ID helper macro. */
#define FLEXCAN_ID_STD(id) \
(((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */
@ -125,10 +104,9 @@
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \
*/
#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \
id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
@ -137,10 +115,9 @@
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \
id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \
*/
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */
#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \
id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
@ -153,43 +130,49 @@
/*! @brief FlexCAN transfer status. */
enum _flexcan_status
{
kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */
kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */
kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */
kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */
kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS(
kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */
kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */
kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */
kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */
kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */
kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */
kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */
kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */
kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */
kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */
kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */
kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */
kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */
kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */
kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */
kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */
kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN is waken up from STOP mode. */
kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< UnHadled Interrupt asserted. */
};
/*! @brief FlexCAN frame format. */
typedef enum _flexcan_frame_format
{
kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */
kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */
kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */
} flexcan_frame_format_t;
/*! @brief FlexCAN frame type. */
typedef enum _flexcan_frame_type
{
kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */
kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */
kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
} flexcan_frame_type_t;
#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
/*! @brief FlexCAN clock source. */
typedef enum _flexcan_clock_source
{
kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */
kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */
kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
} flexcan_clock_source_t;
#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
/*! @brief FlexCAN wake up source. */
typedef enum _flexcan_wake_up_source
{
kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */
kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */
} flexcan_wake_up_source_t;
/*! @brief FlexCAN Rx Fifo Filter type. */
typedef enum _flexcan_rx_fifo_filter_type
@ -208,7 +191,7 @@ typedef enum _flexcan_rx_fifo_filter_type
*/
typedef enum _flexcan_mb_size
{
kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */
kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */
kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */
kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */
kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */
@ -224,7 +207,7 @@ typedef enum _flexcan_mb_size
*/
typedef enum _flexcan_rx_fifo_priority
{
kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/
kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/
kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/
} flexcan_rx_fifo_priority_t;
@ -236,11 +219,11 @@ typedef enum _flexcan_rx_fifo_priority
*/
enum _flexcan_interrupt_enable
{
kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */
kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */
kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */
kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */
kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */
kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */
kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */
kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */
};
/*!
@ -254,28 +237,28 @@ enum _flexcan_interrupt_enable
enum _flexcan_flags
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< Error Overrun Status. */
kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< Error Overrun Status. */
kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Error Overrun Status. */
#endif
kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */
kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */
kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */
kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */
kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */
kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */
kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */
kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */
kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */
kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */
kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */
kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */
kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */
kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */
kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */
kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */
kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */
kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */
kFLEXCAN_ErrorFlag = /*!< All FlexCAN Error Status. */
kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */
kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */
kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */
kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */
kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */
kFLEXCAN_ErrorFlag = (int)( /*!< All FlexCAN Error Status. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | CAN_ESR1_BIT0ERR_FAST_MASK |
CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK |
CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
#endif
CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK |
CAN_ESR1_STFERR_MASK,
CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK |
CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK),
};
/*!
@ -288,19 +271,19 @@ enum _flexcan_flags
enum _flexcan_error_flags
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */
kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */
kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */
kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */
kFLEXCAN_FDBit1Error = CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */
kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */
kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */
kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */
kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */
kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */
kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */
kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */
#endif
kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */
kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */
kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */
kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */
kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */
kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */
kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */
kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */
kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */
kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */
kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */
kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */
};
/*!
@ -314,7 +297,7 @@ enum _flexcan_error_flags
enum _flexcan_rx_fifo_flags
{
kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */
kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */
kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */
kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */
};
@ -388,6 +371,8 @@ typedef struct _flexcan_fd_frame
{
uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */
};
/* Note: the maximum databyte* below is actually 64, user can add them if needed,
or just use dataWord[*] instead. */
struct
{
uint8_t dataByte3; /*!< CAN Frame payload byte3. */
@ -427,13 +412,13 @@ typedef struct _flexcan_config
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */
#endif
#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */
bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */
bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */
bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */
flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */
uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */
bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */
bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */
bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */
bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
bool enableDoze; /*!< Enable or Disable Doze Mode. */
#endif
@ -533,6 +518,18 @@ extern "C" {
* @return FlexCAN instance.
*/
uint32_t FLEXCAN_GetInstance(CAN_Type *base);
/*!
* @brief Calculates the improved timing values by specific baudrates for classical CAN
*
* @param baudRate The classical CAN speed in bps defined by user
* @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching
* @param pconfig Pointer to the FlexCAN timing configuration structure.
*
* @return TRUE if timing configuration found, FALSE if failed to find configuration
*/
bool FLEXCAN_CalculateImprovedTimingValues(uint32_t baudRate,
uint32_t sourceClock_Hz,
flexcan_timing_config_t *pconfig);
/*!
* @brief Initializes a FlexCAN instance.
@ -559,6 +556,51 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base);
*/
void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz);
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
/*!
* @brief Calculates the improved timing values by specific baudrates for CANFD
*
* @param baudRate The CANFD bus control speed in bps defined by user
* @param baudRateFD The CANFD bus data speed in bps defined by user
* @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching
* @param pconfig Pointer to the FlexCAN timing configuration structure.
*
* @return TRUE if timing configuration found, FALSE if failed to find configuration
*/
bool FLEXCAN_FDCalculateImprovedTimingValues(uint32_t baudRate,
uint32_t baudRateFD,
uint32_t sourceClock_Hz,
flexcan_timing_config_t *pconfig);
/*!
* @brief Initializes a FlexCAN instance.
*
* This function initializes the FlexCAN module with user-defined settings.
* This example shows how to set up the flexcan_config_t parameters and how
* to call the FLEXCAN_FDInit function by passing in these parameters.
* @code
* flexcan_config_t flexcanConfig;
* flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc;
* flexcanConfig.baudRate = 1000000U;
* flexcanConfig.baudRateFD = 2000000U;
* flexcanConfig.maxMbNum = 16;
* flexcanConfig.enableLoopBack = false;
* flexcanConfig.enableSelfWakeup = false;
* flexcanConfig.enableIndividMask = false;
* flexcanConfig.enableDoze = false;
* flexcanConfig.timingConfig = timingConfig;
* FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false);
* @endcode
*
* @param base FlexCAN peripheral base address.
* @param config Pointer to the user-defined configuration structure.
* @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
* @param dataSize FlexCAN FD frame payload size.
* @param brs If bitrate switch is enabled in FD mode.
*/
void FLEXCAN_FDInit(
CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs);
#endif
/*!
* @brief De-initializes a FlexCAN instance.
*
@ -574,8 +616,9 @@ void FLEXCAN_Deinit(CAN_Type *base);
*
* This function initializes the FlexCAN configuration structure to default values. The default
* values are as follows.
* flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc;
* flexcanConfig->clkSrc = kFLEXCAN_ClkSrcOsc;
* flexcanConfig->baudRate = 1000000U;
* flexcanConfig->baudRateFD = 2000000U;
* flexcanConfig->maxMbNum = 16;
* flexcanConfig->enableLoopBack = false;
* flexcanConfig->enableSelfWakeup = false;
@ -587,19 +630,6 @@ void FLEXCAN_Deinit(CAN_Type *base);
*/
void FLEXCAN_GetDefaultConfig(flexcan_config_t *config);
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
/*!
* @brief Sets the FlexCAN FD protocol characteristic.
*
* This function gives user settings to CAN FD characteristic.
*
* @param base FlexCAN peripheral base address.
* @param dataSize Quantity of data bytes allocated for the message payload.
* @param brs Enable/Disable the effect of bit rate switch during data phase of Tx messages.
*/
void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs);
#endif
/* @} */
/*!
@ -802,12 +832,12 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
*/
static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
{
if (txErrBuf)
if (NULL != txErrBuf)
{
*txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT);
}
if (rxErrBuf)
if (NULL != rxErrBuf)
{
*rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT);
}
@ -876,7 +906,7 @@ static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
{
/* Solve Wake Up Interrupt. */
if (mask & kFLEXCAN_WakeUpInterruptEnable)
if ((uint32_t)kFLEXCAN_WakeUpInterruptEnable == (mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable))
{
base->MCR |= CAN_MCR_WAKMSK_MASK;
}
@ -897,7 +927,7 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
{
/* Solve Wake Up Interrupt. */
if (mask & kFLEXCAN_WakeUpInterruptEnable)
if ((uint32_t)kFLEXCAN_WakeUpInterruptEnable == (mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable))
{
base->MCR &= ~CAN_MCR_WAKMSK_MASK;
}
@ -1004,7 +1034,7 @@ static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
base->MCR &= ~CAN_MCR_MDIS_MASK;
/* Wait FlexCAN exit from low-power mode. */
while (base->MCR & CAN_MCR_LPMACK_MASK)
while (0U != (base->MCR & CAN_MCR_LPMACK_MASK))
{
}
}
@ -1013,7 +1043,7 @@ static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
base->MCR |= CAN_MCR_MDIS_MASK;
/* Wait FlexCAN enter low-power mode. */
while (!(base->MCR & CAN_MCR_LPMACK_MASK))
while (0U == (base->MCR & CAN_MCR_LPMACK_MASK))
{
}
}
@ -1171,6 +1201,17 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *
* @param mbIdx The FlexCAN FD Message Buffer index.
*/
void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
/*!
* @brief Aborts the interrupt driven message receive process.
*
* This function aborts the interrupt driven message receive process.
*
* @param base FlexCAN peripheral base address.
* @param handle FlexCAN handle pointer.
* @param mbIdx The FlexCAN FD Message Buffer index.
*/
void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
#endif
/*!

177
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio.h"
@ -43,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio"
#endif
/*< @brief user configurable flexio handle count. */
#define FLEXIO_HANDLE_COUNT 2
@ -71,6 +44,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
* Codes
******************************************************************************/
/*!
* brief Get instance number for FLEXIO module.
*
* param base FLEXIO peripheral base address.
*/
uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
{
uint32_t instance;
@ -89,6 +67,24 @@ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
return instance;
}
/*!
* brief Configures the FlexIO with a FlexIO configuration. The configuration structure
* can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().
*
* Example
code
flexio_config_t config = {
.enableFlexio = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false
};
FLEXIO_Configure(base, &config);
endcode
*
* param base FlexIO peripheral base address
* param userConfig pointer to flexio_config_t structure
*/
void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
{
uint32_t ctrlReg = 0;
@ -111,6 +107,13 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
base->CTRL = ctrlReg;
}
/*!
* brief Gates the FlexIO clock. Call this API to stop the FlexIO clock.
*
* note After calling this API, call the FLEXO_Init to use the FlexIO module.
*
* param base FlexIO peripheral base address
*/
void FLEXIO_Deinit(FLEXIO_Type *base)
{
FLEXIO_Enable(base, false);
@ -119,16 +122,36 @@ void FLEXIO_Deinit(FLEXIO_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Gets the default configuration to configure the FlexIO module. The configuration
* can used directly to call the FLEXIO_Configure().
*
* Example:
code
flexio_config_t config;
FLEXIO_GetDefaultConfig(&config);
endcode
*
* param userConfig pointer to flexio_config_t structure
*/
void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)
{
assert(userConfig);
userConfig->enableFlexio = true;
userConfig->enableInDoze = false;
userConfig->enableInDebug = true;
/* Initializes the configure structure to zero. */
memset(userConfig, 0, sizeof(*userConfig));
userConfig->enableFlexio = true;
userConfig->enableInDoze = false;
userConfig->enableInDebug = true;
userConfig->enableFastAccess = false;
}
/*!
* brief Resets the FlexIO module.
*
* param base FlexIO peripheral base address
*/
void FLEXIO_Reset(FLEXIO_Type *base)
{
/*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/
@ -136,6 +159,14 @@ void FLEXIO_Reset(FLEXIO_Type *base)
base->CTRL = 0;
}
/*!
* brief Gets the shifter buffer address for the DMA transfer usage.
*
* param base FlexIO peripheral base address
* param type Shifter type of flexio_shifter_buffer_type_t
* param index Shifter index
* return Corresponding shifter buffer index
*/
uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)
{
assert(index < FLEXIO_SHIFTBUF_COUNT);
@ -184,6 +215,31 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer
return address;
}
/*!
* brief Configures the shifter with the shifter configuration. The configuration structure
* covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper
* mode, select which timer controls the shifter to shift, whether to generate start bit/stop
* bit, and the polarity of start bit and stop bit.
*
* Example
code
flexio_shifter_config_t config = {
.timerSelect = 0,
.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinPolarity = kFLEXIO_PinActiveLow,
.shifterMode = kFLEXIO_ShifterModeTransmit,
.inputSource = kFLEXIO_ShifterInputFromPin,
.shifterStop = kFLEXIO_ShifterStopBitHigh,
.shifterStart = kFLEXIO_ShifterStartBitLow
};
FLEXIO_SetShifterConfig(base, &config);
endcode
*
* param base FlexIO peripheral base address
* param index Shifter index
* param shifterConfig Pointer to flexio_shifter_config_t structure
*/
void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
{
base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
@ -199,6 +255,36 @@ void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shif
FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode);
}
/*!
* brief Configures the timer with the timer configuration. The configuration structure
* covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper
* mode, select trigger source for timer and the timer pin output and the timing for timer.
*
* Example
code
flexio_timer_config_t config = {
.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
.triggerSource = kFLEXIO_TimerTriggerSourceInternal,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinSelect = 0,
.pinPolarity = kFLEXIO_PinActiveHigh,
.timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
.timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
.timerStart = kFLEXIO_TimerStartBitEnabled
};
FLEXIO_SetTimerConfig(base, &config);
endcode
*
* param base FlexIO peripheral base address
* param index Timer index
* param timerConfig Pointer to the flexio_timer_config_t structure
*/
void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)
{
base->TIMCFG[index] =
@ -216,6 +302,15 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_
FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode);
}
/*!
* brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.
*
* param base Pointer to the FlexIO simulated peripheral type.
* param handle Pointer to the handler for FlexIO simulated peripheral.
* param isr FlexIO simulated peripheral interrupt handler.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
{
assert(base);
@ -230,9 +325,9 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
if (s_flexioHandle[index] == NULL)
{
/* Register FLEXIO simulated driver base, handle and isr. */
s_flexioType[index] = base;
s_flexioType[index] = base;
s_flexioHandle[index] = handle;
s_flexioIsr[index] = isr;
s_flexioIsr[index] = isr;
break;
}
}
@ -247,6 +342,13 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
}
}
/*!
* brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.
*
* param base Pointer to the FlexIO simulated peripheral type.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_UnregisterHandleIRQ(void *base)
{
assert(base);
@ -259,9 +361,9 @@ status_t FLEXIO_UnregisterHandleIRQ(void *base)
if (s_flexioType[index] == base)
{
/* Unregister FLEXIO simulated driver handle and isr. */
s_flexioType[index] = NULL;
s_flexioType[index] = NULL;
s_flexioHandle[index] = NULL;
s_flexioIsr[index] = NULL;
s_flexioIsr[index] = NULL;
break;
}
}
@ -318,3 +420,8 @@ void FLEXIO2_DriverIRQHandler(void)
{
FLEXIO_CommonIRQHandler();
}
void FLEXIO3_DriverIRQHandler(void)
{
FLEXIO_CommonIRQHandler();
}

152
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_H_
#define _FSL_FLEXIO_H_
@ -60,7 +34,7 @@
typedef enum _flexio_timer_trigger_polarity
{
kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */
kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */
kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */
} flexio_timer_trigger_polarity_t;
/*! @brief Define type of timer trigger source.*/
@ -73,26 +47,26 @@ typedef enum _flexio_timer_trigger_source
/*! @brief Define type of timer/shifter pin configuration.*/
typedef enum _flexio_pin_config
{
kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */
kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */
kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */
kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */
kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */
kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */
kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */
} flexio_pin_config_t;
/*! @brief Definition of pin polarity.*/
typedef enum _flexio_pin_polarity
{
kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */
kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */
kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */
} flexio_pin_polarity_t;
/*! @brief Define type of timer work mode.*/
typedef enum _flexio_timer_mode
{
kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */
kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */
kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */
kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */
kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */
kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */
kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */
} flexio_timer_mode_t;
/*! @brief Define type of timer initial output or timer reset condition.*/
@ -102,7 +76,7 @@ typedef enum _flexio_timer_output
reset. */
kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer
reset. */
kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */
kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */
kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */
} flexio_timer_output_t;
@ -122,23 +96,23 @@ typedef enum _flexio_timer_decrement_source
/*! @brief Define type of timer reset condition.*/
typedef enum _flexio_timer_reset_condition
{
kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */
kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */
kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */
kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */
kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to
Timer Output. */
kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */
kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */
kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */
kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */
kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */
} flexio_timer_reset_condition_t;
/*! @brief Define type of timer disable condition.*/
typedef enum _flexio_timer_disable_condition
{
kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */
kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */
kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */
kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */
kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */
kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */
kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */
kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */
kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */
kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided
Trigger is high. */
kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */
@ -147,22 +121,22 @@ typedef enum _flexio_timer_disable_condition
/*! @brief Define type of timer enable condition.*/
typedef enum _flexio_timer_enable_condition
{
kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */
kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */
kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */
kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */
kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */
kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */
kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */
kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */
kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */
kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */
kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */
kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */
kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */
kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */
kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */
} flexio_timer_enable_condition_t;
/*! @brief Define type of timer stop bit generate condition.*/
typedef enum _flexio_timer_stop_bit_condition
{
kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */
kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */
kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */
kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */
kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */
kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */
kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer
disable. */
} flexio_timer_stop_bit_condition_t;
@ -171,23 +145,23 @@ typedef enum _flexio_timer_stop_bit_condition
typedef enum _flexio_timer_start_bit_condition
{
kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */
kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */
kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */
} flexio_timer_start_bit_condition_t;
/*! @brief Define type of timer polarity for shifter control. */
typedef enum _flexio_shifter_timer_polarity
{
kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */
kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */
kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */
kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */
} flexio_shifter_timer_polarity_t;
/*! @brief Define type of shifter working mode.*/
typedef enum _flexio_shifter_mode
{
kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */
kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */
kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */
kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */
kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */
kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */
kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */
kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */
kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */
#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE
kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing
@ -202,7 +176,7 @@ typedef enum _flexio_shifter_mode
/*! @brief Define type of shifter input source.*/
typedef enum _flexio_shifter_input_source
{
kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */
kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */
kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */
} flexio_shifter_input_source_t;
@ -210,8 +184,8 @@ typedef enum _flexio_shifter_input_source
typedef enum _flexio_shifter_stop_bit
{
kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */
kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */
kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */
kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */
kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */
} flexio_shifter_stop_bit_t;
/*! @brief Define type of START bit configuration.*/
@ -221,16 +195,16 @@ typedef enum _flexio_shifter_start_bit
data on enable. */
kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads
data on first shift. */
kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */
kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */
kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */
} flexio_shifter_start_bit_t;
/*! @brief Define FlexIO shifter buffer type*/
typedef enum _flexio_shifter_buffer_type
{
kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */
kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */
kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */
kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */
kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */
kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */
kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */
#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP
kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */
@ -368,7 +342,7 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig);
* @note After calling this API, call the FLEXO_Init to use the FlexIO module.
*
* @param base FlexIO peripheral base address
*/
*/
void FLEXIO_Deinit(FLEXIO_Type *base);
/*!
@ -389,7 +363,7 @@ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
* @brief Resets the FlexIO module.
*
* @param base FlexIO peripheral base address
*/
*/
void FLEXIO_Reset(FLEXIO_Type *base);
/*!
@ -397,7 +371,7 @@ void FLEXIO_Reset(FLEXIO_Type *base);
*
* @param base FlexIO peripheral base address
* @param enable true to enable, false to disable.
*/
*/
static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)
{
if (enable)
@ -416,7 +390,7 @@ static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)
*
* @param base FlexIO peripheral base address
* @return FlexIO pin input data
*/
*/
static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)
{
return base->PIN;
@ -429,7 +403,7 @@ static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)
*
* @param base FlexIO peripheral base address
* @return current State pointer
*/
*/
static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)
{
return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK);
@ -508,7 +482,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_
* @param mask The shifter status mask which can be calculated by (1 << shifter index)
* @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate
* the mask by using ((1 << shifter index0) | (1 << shifter index1))
*/
*/
static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
{
base->SHIFTSIEN |= mask;
@ -521,7 +495,7 @@ static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint3
* @param mask The shifter status mask which can be calculated by (1 << shifter index)
* @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate
* the mask by using ((1 << shifter index0) | (1 << shifter index1))
*/
*/
static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
{
base->SHIFTSIEN &= ~mask;
@ -534,7 +508,7 @@ static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint
* @param mask The shifter error mask which can be calculated by (1 << shifter index)
* @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate
* the mask by using ((1 << shifter index0) | (1 << shifter index1))
*/
*/
static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
{
base->SHIFTEIEN |= mask;
@ -547,7 +521,7 @@ static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32
* @param mask The shifter error mask which can be calculated by (1 << shifter index)
* @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate
* the mask by using ((1 << shifter index0) | (1 << shifter index1))
*/
*/
static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
{
base->SHIFTEIEN &= ~mask;
@ -560,7 +534,7 @@ static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint3
* @param mask The timer status mask which can be calculated by (1 << timer index)
* @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate
* the mask by using ((1 << timer index0) | (1 << timer index1))
*/
*/
static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
{
base->TIMIEN |= mask;
@ -573,7 +547,7 @@ static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_
* @param mask The timer status mask which can be calculated by (1 << timer index)
* @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate
* the mask by using ((1 << timer index0) | (1 << timer index1))
*/
*/
static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
{
base->TIMIEN &= ~mask;
@ -591,7 +565,7 @@ static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32
*
* @param base FlexIO peripheral base address
* @return Shifter status flags
*/
*/
static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)
{
return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK);
@ -604,7 +578,7 @@ static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)
* @param mask The shifter status mask which can be calculated by (1 << shifter index)
* @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate
* the mask by using ((1 << shifter index0) | (1 << shifter index1))
*/
*/
static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)
{
base->SHIFTSTAT = mask;
@ -615,7 +589,7 @@ static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t ma
*
* @param base FlexIO peripheral base address
* @return Shifter error flags
*/
*/
static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)
{
return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK);
@ -628,7 +602,7 @@ static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)
* @param mask The shifter error mask which can be calculated by (1 << shifter index)
* @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate
* the mask by using ((1 << shifter index0) | (1 << shifter index1))
*/
*/
static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)
{
base->SHIFTERR = mask;
@ -639,7 +613,7 @@ static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mas
*
* @param base FlexIO peripheral base address
* @return Timer status flags
*/
*/
static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)
{
return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK);
@ -652,7 +626,7 @@ static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)
* @param mask The timer status mask which can be calculated by (1 << timer index)
* @note For clearing multiple timer status flags, for example, two timer status flags, can calculate
* the mask by using ((1 << timer index0) | (1 << timer index1))
*/
*/
static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)
{
base->TIMSTAT = mask;
@ -674,7 +648,7 @@ static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask
* @param base FlexIO peripheral base address
* @param mask The shifter status mask which can be calculated by (1 << shifter index)
* @param enable True to enable, false to disable.
*/
*/
static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)
{
if (enable)
@ -694,7 +668,7 @@ static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mas
* @param type Shifter type of flexio_shifter_buffer_type_t
* @param index Shifter index
* @return Corresponding shifter buffer index
*/
*/
uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index);
/*!
@ -705,7 +679,7 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer
* @param isr FlexIO simulated peripheral interrupt handler.
* @retval kStatus_Success Successfully create the handle.
* @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
*/
status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
/*!
@ -714,7 +688,7 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
* @param base Pointer to the FlexIO simulated peripheral type.
* @retval kStatus_Success Successfully create the handle.
* @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
*/
status_t FLEXIO_UnregisterHandleIRQ(void *base);
/* @} */

213
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.c Normal file
View File

@ -0,0 +1,213 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_camera.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio_camera"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Codes
******************************************************************************/
static uint32_t FLEXIO_CAMERA_GetInstance(FLEXIO_CAMERA_Type *base)
{
return FLEXIO_GetInstance(base->flexioBase);
}
/*!
* brief Gets the default configuration to configure the FlexIO Camera. The configuration
* can be used directly for calling the FLEXIO_CAMERA_Init().
* Example:
code
flexio_camera_config_t config;
FLEXIO_CAMERA_GetDefaultConfig(&userConfig);
endcode
* param config Pointer to the flexio_camera_config_t structure
*/
void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enablecamera = false;
config->enableInDoze = false;
config->enableInDebug = false;
config->enableFastAccess = false;
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO Camera.
*
* param base Pointer to FLEXIO_CAMERA_Type structure
* param config Pointer to flexio_camera_config_t structure
*/
void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config)
{
assert(base && config);
volatile uint32_t i = 0;
volatile uint32_t controlVal = 0;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate flexio clock. */
CLOCK_EnableClock(s_flexioClocks[FLEXIO_CAMERA_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
flexio_shifter_config_t shifterConfig;
flexio_timer_config_t timerConfig;
/* Clear the shifterConfig & timerConfig struct. */
memset(&shifterConfig, 0, sizeof(shifterConfig));
memset(&timerConfig, 0, sizeof(timerConfig));
/* Configure flexio camera */
controlVal = base->flexioBase->CTRL;
controlVal &=
~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
controlVal |= (FLEXIO_CTRL_DBGE(config->enableInDebug) | FLEXIO_CTRL_FASTACC(config->enableFastAccess) |
FLEXIO_CTRL_FLEXEN(config->enablecamera));
if (!config->enableInDoze)
{
controlVal |= FLEXIO_CTRL_DOZEN_MASK;
}
base->flexioBase->CTRL = controlVal;
/* FLEXIO_CAMERA shifter config */
shifterConfig.timerSelect = base->timerIdx;
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->datPinStartIdx;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.parallelWidth = FLEXIO_CAMERA_PARALLEL_DATA_WIDTH - 1U;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromNextShifterOutput;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
/* Configure the shifters as FIFO buffer. */
for (i = base->shifterStartIdx; i < (base->shifterStartIdx + base->shifterCount - 1U); i++)
{
FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig);
}
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig);
/* FLEXIO_CAMERA timer config, the PCLK's clk is source of timer to drive the shifter, the HREF is the selecting
* signal for available data. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->hrefPinIdx);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->pclkPinIdx;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
timerConfig.timerReset = kFLEXIO_TimerResetOnTimerTriggerRisingEdge;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerCompare = 8U * base->shifterCount - 1U;
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIdx, &timerConfig);
/* Clear flags. */
FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx));
FLEXIO_ClearTimerStatusFlags(base->flexioBase, 1U << (base->timerIdx));
}
/*!
* brief Resets the FLEXIO_CAMERA shifer and timer config.
*
* note After calling this API, call FLEXO_CAMERA_Init to use the FlexIO Camera module.
*
* param base Pointer to FLEXIO_CAMERA_Type structure
*/
void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base)
{
base->flexioBase->SHIFTCFG[base->shifterStartIdx] = 0;
base->flexioBase->SHIFTCTL[base->shifterStartIdx] = 0;
base->flexioBase->TIMCFG[base->timerIdx] = 0;
base->flexioBase->TIMCMP[base->timerIdx] = 0;
base->flexioBase->TIMCTL[base->timerIdx] = 0;
/* Clear the shifter flag. */
base->flexioBase->SHIFTSTAT = (1U << base->shifterStartIdx);
/* Clear the timer flag. */
base->flexioBase->TIMSTAT = (1U << base->timerIdx);
}
/*!
* brief Gets the FlexIO Camera status flags.
*
* param base Pointer to FLEXIO_CAMERA_Type structure
* return FlexIO shifter status flags
* arg FLEXIO_SHIFTSTAT_SSF_MASK
* arg 0
*/
uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base)
{
uint32_t status = 0;
status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) >> (base->shifterStartIdx)) &
((1U << (base->shifterCount)) - 1U));
return status;
}
/*!
* brief Clears the receive buffer full flag manually.
*
* param base Pointer to the device.
* param mask status flag
* The parameter can be any combination of the following values:
* arg kFLEXIO_CAMERA_RxDataRegFullFlag
* arg kFLEXIO_CAMERA_RxErrorFlag
*/
void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_CAMERA_RxDataRegFullFlag)
{
FLEXIO_ClearShifterStatusFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U)
<< (base->shifterStartIdx));
}
if (mask & kFLEXIO_CAMERA_RxErrorFlag)
{ /* Clear error flags if they are asserted to make sure the buffer would be available. */
FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx));
}
}
/*!
* brief Switches on the interrupt for receive buffer full event.
*
* param base Pointer to the device.
*/
void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base)
{
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx));
}
/*!
* brief Switches off the interrupt for receive buffer full event.
*
* param base Pointer to the device.
*
*/
void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base)
{
FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx));
}

230
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.h Normal file
View File

@ -0,0 +1,230 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_CAMERA_H_
#define _FSL_FLEXIO_CAMERA_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
/*!
* @addtogroup flexio_camera
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO Camera driver version 2.1.2. */
#define FSL_FLEXIO_CAMERA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*@}*/
/*! @brief Define the Camera CPI interface is constantly 8-bit width. */
#define FLEXIO_CAMERA_PARALLEL_DATA_WIDTH (8U)
/*! @brief Error codes for the Camera driver. */
enum _flexio_camera_status
{
kStatus_FLEXIO_CAMERA_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 0), /*!< Receiver is busy. */
kStatus_FLEXIO_CAMERA_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 1), /*!< Camera receiver is idle. */
};
/*! @brief Define FlexIO Camera status mask. */
enum _flexio_camera_status_flags
{
kFLEXIO_CAMERA_RxDataRegFullFlag = 0x1U, /*!< Receive buffer full flag. */
kFLEXIO_CAMERA_RxErrorFlag = 0x2U, /*!< Receive buffer error flag. */
};
/*!
* @brief Define structure of configuring the FlexIO Camera device.
*/
typedef struct _flexio_camera_type
{
FLEXIO_Type *flexioBase; /*!< FlexIO module base address. */
uint32_t datPinStartIdx; /*!< First data pin (D0) index for flexio_camera.
Then the successive following FLEXIO_CAMERA_DATA_WIDTH-1 pins
are used as D1-D7.*/
uint32_t pclkPinIdx; /*!< Pixel clock pin (PCLK) index for flexio_camera. */
uint32_t hrefPinIdx; /*!< Horizontal sync pin (HREF) index for flexio_camera. */
uint32_t shifterStartIdx; /*!< First shifter index used for flexio_camera data FIFO. */
uint32_t shifterCount; /*!< The count of shifters that are used as flexio_camera data FIFO. */
uint32_t timerIdx; /*!< Timer index used for flexio_camera in FlexIO. */
} FLEXIO_CAMERA_Type;
/*! @brief Define FlexIO Camera user configuration structure. */
typedef struct _flexio_camera_config
{
bool enablecamera; /*!< Enable/disable FlexIO Camera TX & RX. */
bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/
bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/
bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
fast access requires the FlexIO clock to be at least
twice the frequency of the bus clock. */
} flexio_camera_config_t;
/*! @brief Define FlexIO Camera transfer structure. */
typedef struct _flexio_camera_transfer
{
uint32_t dataAddress; /*!< Transfer buffer*/
uint32_t dataNum; /*!< Transfer num*/
} flexio_camera_transfer_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /*_cplusplus*/
/*!
* @name Initialization and configuration
* @{
*/
/*!
* @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO Camera.
*
* @param base Pointer to FLEXIO_CAMERA_Type structure
* @param config Pointer to flexio_camera_config_t structure
*/
void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config);
/*!
* @brief Resets the FLEXIO_CAMERA shifer and timer config.
*
* @note After calling this API, call FLEXO_CAMERA_Init to use the FlexIO Camera module.
*
* @param base Pointer to FLEXIO_CAMERA_Type structure
*/
void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base);
/*!
* @brief Gets the default configuration to configure the FlexIO Camera. The configuration
* can be used directly for calling the FLEXIO_CAMERA_Init().
* Example:
@code
flexio_camera_config_t config;
FLEXIO_CAMERA_GetDefaultConfig(&userConfig);
@endcode
* @param config Pointer to the flexio_camera_config_t structure
*/
void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config);
/*!
* @brief Enables/disables the FlexIO Camera module operation.
*
* @param base Pointer to the FLEXIO_CAMERA_Type
* @param enable True to enable, false does not have any effect.
*/
static inline void FLEXIO_CAMERA_Enable(FLEXIO_CAMERA_Type *base, bool enable)
{
if (enable)
{
base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
}
}
/*! @} */
/*!
* @name Status
* @{
*/
/*!
* @brief Gets the FlexIO Camera status flags.
*
* @param base Pointer to FLEXIO_CAMERA_Type structure
* @return FlexIO shifter status flags
* @arg FLEXIO_SHIFTSTAT_SSF_MASK
* @arg 0
*/
uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base);
/*!
* @brief Clears the receive buffer full flag manually.
*
* @param base Pointer to the device.
* @param mask status flag
* The parameter can be any combination of the following values:
* @arg kFLEXIO_CAMERA_RxDataRegFullFlag
* @arg kFLEXIO_CAMERA_RxErrorFlag
*/
void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask);
/* @} */
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Switches on the interrupt for receive buffer full event.
*
* @param base Pointer to the device.
*/
void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base);
/*!
* @brief Switches off the interrupt for receive buffer full event.
*
* @param base Pointer to the device.
*
*/
void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base);
/*! @} */
/*!
* @name DMA support
* @{
*/
/*!
* @brief Enables/disables the FlexIO Camera receive DMA.
*
* @param base Pointer to FLEXIO_CAMERA_Type structure
* @param enable True to enable, false to disable.
*
* The FlexIO Camera mode can't work without the DMA or eDMA support,
* Usually, it needs at least two DMA or eDMA channels, one for transferring data from
* Camera, such as 0V7670 to FlexIO buffer, another is for transferring data from FlexIO
* buffer to LCD.
*
*/
static inline void FLEXIO_CAMERA_EnableRxDMA(FLEXIO_CAMERA_Type *base, bool enable)
{
FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterStartIdx, enable);
}
/*!
* @brief Gets the data from the receive buffer.
*
* @param base Pointer to the device.
* @return data Pointer to the buffer that keeps the data with count of base->shifterCount .
*/
static inline uint32_t FLEXIO_CAMERA_GetRxBufferAddress(FLEXIO_CAMERA_Type *base)
{
return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterStartIdx);
}
/*! @} */
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
#endif /*_FSL_FLEXIO_CAMERA_H_*/

248
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.c Normal file
View File

@ -0,0 +1,248 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_camera_edma.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio_camera_edma"
#endif
/*<! Structure definition for camera_edma_private_handle_t. The structure is private. */
typedef struct _flexio_camera_edma_private_handle
{
FLEXIO_CAMERA_Type *base;
flexio_camera_edma_handle_t *handle;
} flexio_camera_edma_private_handle_t;
/* CAMERA EDMA transfer handle. */
enum _flexio_camera_edma_tansfer_states
{
kFLEXIO_CAMERA_RxIdle, /* RX idle. */
kFLEXIO_CAMERA_RxBusy /* RX busy. */
};
/*******************************************************************************
* Variables
******************************************************************************/
/*< @brief user configurable flexio camera handle count. */
#define FLEXIO_CAMERA_HANDLE_COUNT 1
/*<! Private handle only used for internally. */
static flexio_camera_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_CAMERA_HANDLE_COUNT];
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief FLEXIO CAMERA EDMA receive finished callback function.
*
* This function is called when FLEXIO CAMERA EDMA receive finished. It disables the CAMERA
* RX EDMA request and sends @ref kStatus_FLEXIO_CAMERA_RxIdle to CAMERA callback.
*
* @param handle The EDMA handle.
* @param param Callback function parameter.
*/
static void FLEXIO_CAMERA_TransferReceiveEDMACallback(edma_handle_t *handle,
void *param,
bool transferDone,
uint32_t tcds);
/*******************************************************************************
* Code
******************************************************************************/
static void FLEXIO_CAMERA_TransferReceiveEDMACallback(edma_handle_t *handle,
void *param,
bool transferDone,
uint32_t tcds)
{
flexio_camera_edma_private_handle_t *cameraPrivateHandle = (flexio_camera_edma_private_handle_t *)param;
/* Avoid the warning for unused variables. */
handle = handle;
tcds = tcds;
if (transferDone)
{
FLEXIO_CAMERA_TransferAbortReceiveEDMA(cameraPrivateHandle->base, cameraPrivateHandle->handle);
if (cameraPrivateHandle->handle->callback)
{
cameraPrivateHandle->handle->callback(cameraPrivateHandle->base, cameraPrivateHandle->handle,
kStatus_FLEXIO_CAMERA_RxIdle, cameraPrivateHandle->handle->userData);
}
}
}
/*!
* brief Initializes the Camera handle, which is used in transactional functions.
*
* param base Pointer to the FLEXIO_CAMERA_Type.
* param handle Pointer to flexio_camera_edma_handle_t structure.
* param callback The callback function.
* param userData The parameter of the callback function.
* param rxEdmaHandle User requested DMA handle for RX DMA transfer.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO Camera eDMA type/handle table out of range.
*/
status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
flexio_camera_edma_transfer_callback_t callback,
void *userData,
edma_handle_t *rxEdmaHandle)
{
assert(handle);
uint8_t index = 0;
/* Find the an empty handle pointer to store the handle. */
for (index = 0; index < FLEXIO_CAMERA_HANDLE_COUNT; index++)
{
if (s_edmaPrivateHandle[index].base == NULL)
{
s_edmaPrivateHandle[index].base = base;
s_edmaPrivateHandle[index].handle = handle;
break;
}
}
if (index == FLEXIO_CAMERA_HANDLE_COUNT)
{
return kStatus_OutOfRange;
}
s_edmaPrivateHandle[index].base = base;
s_edmaPrivateHandle[index].handle = handle;
memset(handle, 0, sizeof(*handle));
handle->rxState = kFLEXIO_CAMERA_RxIdle;
handle->rxEdmaHandle = rxEdmaHandle;
handle->callback = callback;
handle->userData = userData;
/* Configure RX. */
if (rxEdmaHandle)
{
EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_CAMERA_TransferReceiveEDMACallback, &s_edmaPrivateHandle);
}
return kStatus_Success;
}
/*!
* brief Receives data using eDMA.
*
* This function receives data using eDMA. This is a non-blocking function, which returns
* right away. When all data is received, the receive callback function is called.
*
* param base Pointer to the FLEXIO_CAMERA_Type.
* param handle Pointer to the flexio_camera_edma_handle_t structure.
* param xfer Camera eDMA transfer structure, see #flexio_camera_transfer_t.
* retval kStatus_Success if succeeded, others failed.
* retval kStatus_CAMERA_RxBusy Previous transfer on going.
*/
status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
flexio_camera_transfer_t *xfer)
{
assert(handle->rxEdmaHandle);
edma_transfer_config_t xferConfig;
status_t status;
/* If previous RX not finished. */
if (kFLEXIO_CAMERA_RxBusy == handle->rxState)
{
status = kStatus_FLEXIO_CAMERA_RxBusy;
}
else
{
handle->rxState = kFLEXIO_CAMERA_RxBusy;
/* Prepare transfer. */
EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_CAMERA_GetRxBufferAddress(base), 32, (void *)xfer->dataAddress,
32, 32, xfer->dataNum, kEDMA_PeripheralToMemory);
/* Store the initially configured eDMA minor byte transfer count into the FLEXIO CAMERA handle */
handle->nbytes = 32;
/* Submit transfer. */
EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
EDMA_StartTransfer(handle->rxEdmaHandle);
/* Enable CAMERA RX EDMA. */
FLEXIO_CAMERA_EnableRxDMA(base, true);
status = kStatus_Success;
}
return status;
}
/*!
* brief Aborts the receive data which used the eDMA.
*
* This function aborts the receive data which used the eDMA.
*
* param base Pointer to the FLEXIO_CAMERA_Type.
* param handle Pointer to the flexio_camera_edma_handle_t structure.
*/
void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle)
{
assert(handle->rxEdmaHandle);
/* Disable CAMERA RX EDMA. */
FLEXIO_CAMERA_EnableRxDMA(base, false);
/* Stop transfer. */
EDMA_StopTransfer(handle->rxEdmaHandle);
handle->rxState = kFLEXIO_CAMERA_RxIdle;
}
/*!
* brief Gets the remaining bytes to be received.
*
* This function gets the number of bytes still not received.
*
* param base Pointer to the FLEXIO_CAMERA_Type.
* param handle Pointer to the flexio_camera_edma_handle_t structure.
* param count Number of bytes sent so far by the non-blocking transaction.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_InvalidArgument The count parameter is invalid.
*/
status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
size_t *count)
{
assert(handle->rxEdmaHandle);
if (!count)
{
return kStatus_InvalidArgument;
}
if (kFLEXIO_CAMERA_RxBusy == handle->rxState)
{
*count = (handle->rxSize -
(uint32_t)handle->nbytes *
EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel));
}
else
{
*count = handle->rxSize;
}
return kStatus_Success;
}

130
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.h Normal file
View File

@ -0,0 +1,130 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_CAMERA_EDMA_H_
#define _FSL_FLEXIO_CAMERA_EDMA_H_
#include "fsl_flexio_camera.h"
#include "fsl_edma.h"
/*!
* @addtogroup flexio_edma_camera
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO Camera EDMA driver version 2.1.2. */
#define FSL_FLEXIO_CAMERA_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*@}*/
/*! @brief Forward declaration of the handle typedef. */
typedef struct _flexio_camera_edma_handle flexio_camera_edma_handle_t;
/*! @brief Camera transfer callback function. */
typedef void (*flexio_camera_edma_transfer_callback_t)(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
status_t status,
void *userData);
/*!
* @brief Camera eDMA handle
*/
struct _flexio_camera_edma_handle
{
flexio_camera_edma_transfer_callback_t callback; /*!< Callback function. */
void *userData; /*!< Camera callback function parameter.*/
size_t rxSize; /*!< Total bytes to be received. */
edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
volatile uint8_t rxState; /*!< RX transfer state */
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name eDMA transactional
* @{
*/
/*!
* @brief Initializes the Camera handle, which is used in transactional functions.
*
* @param base Pointer to the FLEXIO_CAMERA_Type.
* @param handle Pointer to flexio_camera_edma_handle_t structure.
* @param callback The callback function.
* @param userData The parameter of the callback function.
* @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
* @retval kStatus_Success Successfully create the handle.
* @retval kStatus_OutOfRange The FlexIO Camera eDMA type/handle table out of range.
*/
status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
flexio_camera_edma_transfer_callback_t callback,
void *userData,
edma_handle_t *rxEdmaHandle);
/*!
* @brief Receives data using eDMA.
*
* This function receives data using eDMA. This is a non-blocking function, which returns
* right away. When all data is received, the receive callback function is called.
*
* @param base Pointer to the FLEXIO_CAMERA_Type.
* @param handle Pointer to the flexio_camera_edma_handle_t structure.
* @param xfer Camera eDMA transfer structure, see #flexio_camera_transfer_t.
* @retval kStatus_Success if succeeded, others failed.
* @retval kStatus_CAMERA_RxBusy Previous transfer on going.
*/
status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
flexio_camera_transfer_t *xfer);
/*!
* @brief Aborts the receive data which used the eDMA.
*
* This function aborts the receive data which used the eDMA.
*
* @param base Pointer to the FLEXIO_CAMERA_Type.
* @param handle Pointer to the flexio_camera_edma_handle_t structure.
*/
void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle);
/*!
* @brief Gets the remaining bytes to be received.
*
* This function gets the number of bytes still not received.
*
* @param base Pointer to the FLEXIO_CAMERA_Type.
* @param handle Pointer to the flexio_camera_edma_handle_t structure.
* @param count Number of bytes sent so far by the non-blocking transaction.
* @retval kStatus_Success Succeed get the transfer count.
* @retval kStatus_InvalidArgument The count parameter is invalid.
*/
status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
size_t *count);
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_CAMERA_EDMA_H_ */

417
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_i2c_master.h"
@ -43,16 +17,15 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master"
#endif
/*! @brief FLEXIO I2C transfer state */
enum _flexio_i2c_master_transfer_states
{
kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */
kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */
kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */
kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/
kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */
kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */
kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */
kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/
kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/
kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/
kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/
};
/*******************************************************************************
@ -112,14 +85,14 @@ static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
uint32_t byteCount;
/* Init the handle member. */
handle->transfer.slaveAddress = xfer->slaveAddress;
handle->transfer.direction = xfer->direction;
handle->transfer.subaddress = xfer->subaddress;
handle->transfer.slaveAddress = xfer->slaveAddress;
handle->transfer.direction = xfer->direction;
handle->transfer.subaddress = xfer->subaddress;
handle->transfer.subaddressSize = xfer->subaddressSize;
handle->transfer.data = xfer->data;
handle->transfer.dataSize = xfer->dataSize;
handle->transfer.flags = xfer->flags;
handle->transferSize = xfer->dataSize;
handle->transfer.data = xfer->data;
handle->transfer.dataSize = xfer->dataSize;
handle->transfer.flags = xfer->flags;
handle->transferSize = xfer->dataSize;
/* Initial state, i2c check address state. */
handle->state = kFLEXIO_I2C_CheckAddress;
@ -181,7 +154,7 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
(!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) &&
(handle->transfer.dataSize == 1U))))
{
FLEXIO_I2C_MasterReadByte(base);
(void)FLEXIO_I2C_MasterReadByte(base);
FLEXIO_I2C_MasterAbortStop(base);
@ -207,7 +180,7 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData))
{
FLEXIO_I2C_MasterReadByte(base);
(void)FLEXIO_I2C_MasterReadByte(base);
}
switch (handle->state)
@ -237,17 +210,27 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
{
if (handle->transfer.direction == kFLEXIO_I2C_Write)
{
/* Next state, send data. */
handle->state = kFLEXIO_I2C_SendData;
/* Send first byte of data. */
if (handle->transfer.dataSize > 0)
{
FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
/* Next state, send data. */
handle->state = kFLEXIO_I2C_SendData;
FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
handle->transfer.data++;
handle->transfer.dataSize--;
}
else
{
FLEXIO_I2C_MasterStop(base);
while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
{
}
(void)FLEXIO_I2C_MasterReadByte(base);
handle->state = kFLEXIO_I2C_Idle;
}
}
else
{
@ -280,7 +263,7 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
{
}
FLEXIO_I2C_MasterReadByte(base);
(void)FLEXIO_I2C_MasterReadByte(base);
handle->state = kFLEXIO_I2C_Idle;
}
@ -370,6 +353,34 @@ static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
}
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C
* hardware configuration.
*
* Example
code
FLEXIO_I2C_Type base = {
.flexioBase = FLEXIO,
.SDAPinIndex = 0,
.SCLPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_i2c_master_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 100000
};
FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);
endcode
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param masterConfig Pointer to flexio_i2c_master_config_t structure.
* param srcClock_Hz FlexIO source clock in Hz.
* retval kStatus_Success Initialization successful
* retval kStatus_InvalidArgument The source clock exceed upper range limitation
*/
status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
{
assert(base && masterConfig);
@ -377,8 +388,8 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
flexio_shifter_config_t shifterConfig;
flexio_timer_config_t timerConfig;
uint32_t controlVal = 0;
uint16_t timerDiv = 0;
status_t result = kStatus_Success;
uint16_t timerDiv = 0;
status_t result = kStatus_Success;
memset(&shifterConfig, 0, sizeof(shifterConfig));
memset(&timerConfig, 0, sizeof(timerConfig));
@ -390,46 +401,46 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
/* Do hardware configuration. */
/* 1. Configure the shifter 0 for tx. */
shifterConfig.timerSelect = base->timerIndex[1];
shifterConfig.timerSelect = base->timerIndex[1];
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
shifterConfig.pinSelect = base->SDAPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveLow;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
shifterConfig.pinSelect = base->SDAPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveLow;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
/* 2. Configure the shifter 1 for rx. */
shifterConfig.timerSelect = base->timerIndex[1];
shifterConfig.timerSelect = base->timerIndex[1];
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->SDAPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->SDAPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
/*3. Configure the timer 0 for generating bit clock. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
timerConfig.pinSelect = base->SCLPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
timerConfig.pinSelect = base->SCLPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
/* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */
timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1;
@ -445,20 +456,20 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
/* 4. Configure the timer 1 for controlling shifters. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->SCLPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->SCLPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
/* Set TIMCMP[15:0] = (number of bits x 2) - 1. */
timerConfig.timerCompare = 8 * 2 - 1;
@ -480,18 +491,24 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
return result;
}
/*!
* brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master
* shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called.
*
* param base pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
{
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
/* Clear the shifter flag. */
base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]);
base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]);
@ -500,19 +517,40 @@ void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
}
/*!
* brief Gets the default configuration to configure the FlexIO module. The configuration
* can be used directly for calling the FLEXIO_I2C_MasterInit().
*
* Example:
code
flexio_i2c_master_config_t config;
FLEXIO_I2C_MasterGetDefaultConfig(&config);
endcode
* param masterConfig Pointer to flexio_i2c_master_config_t structure.
*/
void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
{
assert(masterConfig);
masterConfig->enableMaster = true;
masterConfig->enableInDoze = false;
masterConfig->enableInDebug = true;
/* Initializes the configure structure to zero. */
memset(masterConfig, 0, sizeof(*masterConfig));
masterConfig->enableMaster = true;
masterConfig->enableInDoze = false;
masterConfig->enableInDebug = true;
masterConfig->enableFastAccess = false;
/* Default baud rate at 100kbps. */
masterConfig->baudRate_Bps = 100000U;
}
/*!
* brief Gets the FlexIO I2C master status flags.
*
* param base Pointer to FLEXIO_I2C_Type structure
* return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status.
*/
uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
{
uint32_t status = 0;
@ -529,6 +567,16 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
return status;
}
/*!
* brief Clears the FlexIO I2C master status flags.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param mask Status flag.
* The parameter can be any combination of the following values:
* arg kFLEXIO_I2C_RxFullFlag
* arg kFLEXIO_I2C_ReceiveNakFlag
*/
void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2C_TxEmptyFlag)
@ -547,6 +595,14 @@ void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
}
}
/*!
* brief Enables the FlexIO i2c master interrupt requests.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param mask Interrupt source.
* Currently only one interrupt request source:
* arg kFLEXIO_I2C_TransferCompleteInterruptEnable
*/
void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
@ -559,6 +615,12 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
}
}
/*!
* brief Disables the FlexIO I2C master interrupt requests.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param mask Interrupt source.
*/
void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
@ -571,10 +633,17 @@ void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
}
}
/*!
* brief Sets the FlexIO I2C master transfer baudrate.
*
* param base Pointer to FLEXIO_I2C_Type structure
* param baudRate_Bps the baud rate value in HZ
* param srcClock_Hz source clock in HZ
*/
void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
{
uint16_t timerDiv = 0;
uint16_t timerCmp = 0;
uint16_t timerDiv = 0;
uint16_t timerCmp = 0;
FLEXIO_Type *flexioBase = base->flexioBase;
/* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
@ -588,6 +657,17 @@ void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps,
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
}
/*!
* brief Sets the number of bytes to be transferred from a start signal to a stop signal.
*
* note Call this API before a transfer begins because the timer generates a number of clocks according
* to the number of bytes that need to be transferred.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param count Number of bytes need to be transferred from a start signal to a re-start/stop signal
* retval kStatus_Success Successfully configured the count.
* retval kStatus_InvalidArgument Input argument is invalid.
*/
status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
{
if (count > 14U)
@ -595,15 +675,15 @@ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
return kStatus_InvalidArgument;
}
uint16_t timerCmp = 0;
uint32_t timerConfig = 0;
uint16_t timerCmp = 0;
uint32_t timerConfig = 0;
FLEXIO_Type *flexioBase = base->flexioBase;
timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
timerCmp &= 0x00FFU;
timerCmp |= (count * 18 + 1U) << 8U;
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
timerConfig = flexioBase->TIMCFG[base->timerIndex[0]];
timerConfig = flexioBase->TIMCFG[base->timerIndex[0]];
timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig;
@ -611,6 +691,21 @@ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
return kStatus_Success;
}
/*!
* brief Sends START + 7-bit address to the bus.
*
* note This API should be called when the transfer configuration is ready to send a START signal
* and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address
* is put into the data register but the address transfer is not finished on the bus. Ensure that
* the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.
* param base Pointer to FLEXIO_I2C_Type structure.
* param address 7-bit address.
* param direction transfer direction.
* This parameter is one of the values in flexio_i2c_direction_t:
* arg kFLEXIO_I2C_Write: Transmit
* arg kFLEXIO_I2C_Read: Receive
*/
void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
{
uint32_t data;
@ -620,12 +715,22 @@ void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_d
FLEXIO_I2C_MasterWriteByte(base, data);
}
/*!
* brief Sends the repeated start signal on the bus.
*
* param base Pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
{
/* Prepare for RESTART condition, no stop.*/
FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
}
/*!
* brief Sends the stop signal on the bus.
*
* param base Pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
{
/* Prepare normal stop. */
@ -633,6 +738,11 @@ void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
FLEXIO_I2C_MasterWriteByte(base, 0x0U);
}
/*!
* brief Sends the stop signal when transfer is still on-going.
*
* param base Pointer to FLEXIO_I2C_Type structure.
*/
void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
{
uint32_t tmpConfig;
@ -644,6 +754,12 @@ void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
}
/*!
* brief Configures the sent ACK/NAK for the following byte.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param enable True to configure send ACK, false configure to send NAK.
*/
void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
{
uint32_t tmpConfig = 0;
@ -661,6 +777,17 @@ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
}
/*!
* brief Sends a buffer of data in bytes.
*
* note This function blocks via polling until all bytes have been sent.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param txBuff The data bytes to send.
* param txSize The number of data bytes to send.
* retval kStatus_Success Successfully write data.
* retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data.
*/
status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
{
assert(txBuff);
@ -686,6 +813,15 @@ status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *tx
return kStatus_Success;
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks via polling until all bytes have been received.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param rxBuff The buffer to store the received bytes.
* param rxSize The number of data bytes to be received.
*/
void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
{
assert(rxBuff);
@ -702,6 +838,16 @@ void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8
}
}
/*!
* brief Performs a master polling transfer on the I2C bus.
*
* note The API does not return until the transfer succeeds or fails due
* to receiving NAK.
*
* param base pointer to FLEXIO_I2C_Type structure.
* param xfer pointer to flexio_i2c_master_transfer_t structure.
* return status of status_t.
*/
status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
{
assert(xfer);
@ -723,14 +869,29 @@ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_mas
(kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag)))
{
}
FLEXIO_ClearTimerStatusFlags(base->flexioBase, ((1 << base->timerIndex[0]) | (1 << base->timerIndex[1])));
result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags);
} while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success));
/* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent. */
while(0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1 << base->timerIndex[0])))
{
}
return result;
}
/*!
* brief Initializes the I2C handle which is used in transactional functions.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
* param callback Pointer to user callback function.
* param userData User param passed to the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range.
*/
status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
flexio_i2c_master_handle_t *handle,
flexio_i2c_master_transfer_callback_t callback,
@ -745,7 +906,7 @@ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
/* Register callback and userData. */
handle->completionCallback = callback;
handle->userData = userData;
handle->userData = userData;
/* Enable interrupt in NVIC. */
EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]);
@ -754,6 +915,20 @@ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
}
/*!
* brief Performs a master interrupt non-blocking transfer on the I2C bus.
*
* note The API returns immediately after the transfer initiates.
* Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether
* the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer
* is finished.
*
* param base Pointer to FLEXIO_I2C_Type structure
* param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
* param xfer pointer to flexio_i2c_master_transfer_t structure
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer.
*/
status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
flexio_i2c_master_handle_t *handle,
flexio_i2c_master_transfer_t *xfer)
@ -777,6 +952,15 @@ status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
}
}
/*!
* brief Aborts an interrupt non-blocking transfer early.
*
* note This API can be called at any time when an interrupt non-blocking transfer initiates
* to abort the transfer early.
*
* param base Pointer to FLEXIO_I2C_Type structure
* param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
*/
void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
{
assert(handle);
@ -788,6 +972,15 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han
handle->state = kFLEXIO_I2C_Idle;
}
/*!
* brief Gets the master transfer status during a interrupt non-blocking transfer.
*
* param base Pointer to FLEXIO_I2C_Type structure.
* param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
* param count Number of bytes transferred so far by the non-blocking transaction.
* retval kStatus_InvalidArgument count is Invalid.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
{
if (!count)
@ -800,9 +993,15 @@ status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_mas
return kStatus_Success;
}
/*!
* brief Master interrupt handler.
*
* param i2cType Pointer to FLEXIO_I2C_Type structure
* param i2cHandle Pointer to flexio_i2c_master_transfer_t structure
*/
void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
{
FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;
FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;
flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle;
uint32_t statusFlags;
status_t result;

52
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_I2C_MASTER_H_
#define _FSL_FLEXIO_I2C_MASTER_H_
@ -48,8 +22,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2C master driver version 2.1.5. */
#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*! @brief FlexIO I2C master driver version 2.1.7. */
#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
/*@}*/
/*! @brief FlexIO I2C transfer status*/
@ -57,21 +31,21 @@ enum _flexio_i2c_status
{
kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */
kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */
kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */
kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */
};
/*! @brief Define FlexIO I2C master interrupt mask. */
enum _flexio_i2c_master_interrupt
{
kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */
kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */
kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */
};
/*! @brief Define FlexIO I2C master status mask. */
enum _flexio_i2c_master_status_flags
{
kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */
kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */
kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */
kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */
kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */
};
@ -79,7 +53,7 @@ enum _flexio_i2c_master_status_flags
typedef enum _flexio_i2c_direction
{
kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */
kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */
kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */
} flexio_i2c_direction_t;
/*! @brief Define FlexIO I2C master access structure typedef. */
@ -204,7 +178,7 @@ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
*
* @param base Pointer to FLEXIO_I2C_Type structure.
* @param enable Pass true to enable module, false does not have any effect.
*/
*/
static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
{
if (enable)
@ -225,7 +199,7 @@ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
*
* @param base Pointer to FLEXIO_I2C_Type structure
* @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status.
*/
*/
uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
@ -237,7 +211,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
* The parameter can be any combination of the following values:
* @arg kFLEXIO_I2C_RxFullFlag
* @arg kFLEXIO_I2C_ReceiveNakFlag
*/
*/
void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask);
@ -338,7 +312,7 @@ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable);
* @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal
* @retval kStatus_Success Successfully configured the count.
* @retval kStatus_InvalidArgument Input argument is invalid.
*/
*/
status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count);
/*!

468
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_i2s.h"
@ -39,10 +13,9 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
* Definitations
******************************************************************************/
enum _sai_transfer_state
{
kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */
@ -87,11 +60,11 @@ static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
{
uint32_t i = 0;
uint8_t j = 0;
uint32_t i = 0;
uint8_t j = 0;
uint8_t bytesPerWord = bitWidth / 8U;
uint32_t data = 0;
uint32_t temp = 0;
uint32_t data = 0;
uint32_t temp = 0;
for (i = 0; i < size / bytesPerWord; i++)
{
@ -101,21 +74,21 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
data |= (temp << (8U * j));
txData++;
}
base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
data = 0;
base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = data << (32U - bitWidth);
data = 0;
}
}
static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
{
uint32_t i = 0;
uint8_t j = 0;
uint32_t i = 0;
uint8_t j = 0;
uint8_t bytesPerWord = bitWidth / 8U;
uint32_t data = 0;
uint32_t data = 0;
for (i = 0; i < size / bytesPerWord; i++)
{
data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth));
data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]);
for (j = 0; j < bytesPerWord; j++)
{
*rxData = (data >> (8U * j)) & 0xFF;
@ -124,27 +97,44 @@ static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
}
}
/*!
* brief Initializes the FlexIO I2S.
*
* This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure.
* The configuration structure can be filled by the user, or be set with default values by
* FLEXIO_I2S_GetDefaultConfig().
*
* note This API should be called at the beginning of the application to use
* the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault
* because the clock is not enabled.
*
* param base FlexIO I2S base pointer
* param config FlexIO I2S configure structure.
*/
void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
{
assert(base && config);
flexio_shifter_config_t shifterConfig = {0};
flexio_timer_config_t timerConfig = {0};
flexio_timer_config_t timerConfig = {0};
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate flexio clock. */
CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* reset Flexio */
FLEXIO_Reset(base->flexioBase);
/* Set shifter for I2S Tx data */
shifterConfig.timerSelect = base->bclkTimerIndex;
shifterConfig.pinSelect = base->txPinIndex;
shifterConfig.timerSelect = base->bclkTimerIndex;
shifterConfig.pinSelect = base->txPinIndex;
shifterConfig.timerPolarity = config->txTimerPolarity;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinPolarity = config->txPinPolarity;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinPolarity = config->txPinPolarity;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
if (config->masterSlave == kFLEXIO_I2S_Master)
{
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
@ -157,89 +147,89 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig);
/* Set shifter for I2S Rx Data */
shifterConfig.timerSelect = base->bclkTimerIndex;
shifterConfig.pinSelect = base->rxPinIndex;
shifterConfig.timerSelect = base->bclkTimerIndex;
shifterConfig.pinSelect = base->rxPinIndex;
shifterConfig.timerPolarity = config->rxTimerPolarity;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinPolarity = config->rxPinPolarity;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinPolarity = config->rxPinPolarity;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig);
/* Set Timer to I2S frame sync */
if (config->masterSlave == kFLEXIO_I2S_Master)
{
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinSelect = base->fsPinIndex;
timerConfig.pinPolarity = config->fsPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinSelect = base->fsPinIndex;
timerConfig.pinPolarity = config->fsPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
}
else
{
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->fsPinIndex;
timerConfig.pinPolarity = config->fsPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->fsPinIndex;
timerConfig.pinPolarity = config->fsPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
}
FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig);
/* Set Timer to I2S bit clock */
if (config->masterSlave == kFLEXIO_I2S_Master)
{
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinSelect = base->bclkPinIndex;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinPolarity = config->bclkPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinSelect = base->bclkPinIndex;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinPolarity = config->bclkPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
}
else
{
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinSelect = base->bclkPinIndex;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinPolarity = config->bclkPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinSelect = base->bclkPinIndex;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinPolarity = config->bclkPinPolarity;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
}
FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig);
@ -254,32 +244,60 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
}
}
/*!
* brief Sets the FlexIO I2S configuration structure to default values.
*
* The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init().
* Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify
* some fields of the structure before calling FLEXIO_I2S_Init().
*
* param config pointer to master configuration structure
*/
void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
{
config->masterSlave = kFLEXIO_I2S_Master;
config->enableI2S = true;
config->txPinPolarity = kFLEXIO_PinActiveHigh;
config->rxPinPolarity = kFLEXIO_PinActiveHigh;
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->masterSlave = kFLEXIO_I2S_Master;
config->enableI2S = true;
config->txPinPolarity = kFLEXIO_PinActiveHigh;
config->rxPinPolarity = kFLEXIO_PinActiveHigh;
config->bclkPinPolarity = kFLEXIO_PinActiveHigh;
config->fsPinPolarity = kFLEXIO_PinActiveLow;
config->fsPinPolarity = kFLEXIO_PinActiveLow;
config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
}
/*!
* brief De-initializes the FlexIO I2S.
*
* Calling this API resets the FlexIO I2S shifter and timer config. After calling this API,
* call the FLEXO_I2S_Init to use the FlexIO I2S module.
*
* param base FlexIO I2S base pointer
*/
void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
{
base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0;
base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0;
base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0;
base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0;
base->flexioBase->TIMCFG[base->fsTimerIndex] = 0;
base->flexioBase->TIMCMP[base->fsTimerIndex] = 0;
base->flexioBase->TIMCTL[base->fsTimerIndex] = 0;
base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0;
base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0;
base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0;
base->flexioBase->TIMCFG[base->fsTimerIndex] = 0;
base->flexioBase->TIMCMP[base->fsTimerIndex] = 0;
base->flexioBase->TIMCTL[base->fsTimerIndex] = 0;
base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0;
base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0;
base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0;
}
/*!
* brief Enables the FlexIO I2S interrupt.
*
* This function enables the FlexIO UART interrupt.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param mask interrupt source
*/
void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
@ -292,6 +310,12 @@ void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
}
}
/*!
* brief Gets the FlexIO I2S status flags.
*
* param base Pointer to FLEXIO_I2S_Type structure
* return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
*/
uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
{
uint32_t status = 0;
@ -302,6 +326,14 @@ uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
return status;
}
/*!
* brief Disables the FlexIO I2S interrupt.
*
* This function enables the FlexIO UART interrupt.
*
* param base pointer to FLEXIO_I2S_Type structure
* param mask interrupt source
*/
void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
@ -314,9 +346,19 @@ void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
}
}
/*!
* brief Configures the FlexIO I2S audio format in master mode.
*
* Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param format Pointer to FlexIO I2S audio data format structure.
* param srcClock_Hz I2S master clock source frequency in Hz.
*/
void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
{
uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U);
uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U);
uint32_t bclkDiv = 0;
/* Shall keep bclk and fs div an integer */
@ -325,25 +367,44 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form
timDiv += 1U;
}
/* Set Frame sync timer cmp */
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U);
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * timDiv - 1U);
/* Set bit clock timer cmp */
bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U));
bclkDiv = ((timDiv / 2U - 1U) | ((format->bitWidth * 2U - 1U) << 8U));
base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv);
}
/*!
* brief Configures the FlexIO I2S audio format in slave mode.
*
* Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param format Pointer to FlexIO I2S audio data format structure.
*/
void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
{
/* Set Frame sync timer cmp */
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U);
base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 4U - 3U);
/* Set bit clock timer cmp */
base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U);
base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 2U - 1U);
}
/*!
* brief Sends data using a blocking method.
*
* note This function blocks via polling until data is ready to be sent.
*
* param base FlexIO I2S base pointer.
* param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
* param txData Pointer to the data to be written.
* param size Bytes to be written.
*/
void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
{
uint32_t i = 0;
uint32_t i = 0;
uint8_t bytesPerWord = bitWidth / 8U;
for (i = 0; i < size / bytesPerWord; i++)
@ -363,9 +424,19 @@ void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *
}
}
/*!
* brief Receives a piece of data using a blocking method.
*
* note This function blocks via polling until data is ready to be sent.
*
* param base FlexIO I2S base pointer
* param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
* param rxData Pointer to the data to be read.
* param size Bytes to be read.
*/
void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
{
uint32_t i = 0;
uint32_t i = 0;
uint8_t bytesPerWord = bitWidth / 8U;
for (i = 0; i < size / bytesPerWord; i++)
@ -380,6 +451,18 @@ void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *r
}
}
/*!
* brief Initializes the FlexIO I2S handle.
*
* This function initializes the FlexIO I2S handle which can be used for other
* FlexIO I2S transactional APIs. Call this API once to get the
* initialized handle.
*
* param base Pointer to FLEXIO_I2S_Type structure
* param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
* param callback FlexIO I2S callback function, which is called while finished a block.
* param userData User parameter for the FlexIO I2S callback.
*/
void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_callback_t callback,
@ -406,6 +489,18 @@ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
}
/*!
* brief Initializes the FlexIO I2S receive handle.
*
* This function initializes the FlexIO I2S handle which can be used for other
* FlexIO I2S transactional APIs. Call this API once to get the
* initialized handle.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
* param callback FlexIO I2S callback function, which is called while finished a block.
* param userData User parameter for the FlexIO I2S callback.
*/
void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_callback_t callback,
@ -432,6 +527,17 @@ void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
}
/*!
* brief Configures the FlexIO I2S audio format.
*
* Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle FlexIO I2S handle pointer.
* param format Pointer to audio data format structure.
* param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
*/
void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_format_t *format,
@ -454,6 +560,20 @@ void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
}
}
/*!
* brief Performs an interrupt non-blocking send transfer on FlexIO I2S.
*
* note The API returns immediately after transfer initiates.
* Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether
* the transfer is finished. If the return status is 0, the transfer is finished.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* param xfer Pointer to flexio_i2s_transfer_t structure
* retval kStatus_Success Successfully start the data transmission.
* retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet.
* retval kStatus_InvalidArgument The input parameter is invalid.
*/
status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -471,10 +591,10 @@ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
}
/* Add into queue */
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].dataSize = xfer->dataSize;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
/* Set the state to busy */
handle->state = kFLEXIO_I2S_Busy;
@ -487,6 +607,20 @@ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Performs an interrupt non-blocking receive transfer on FlexIO I2S.
*
* note The API returns immediately after transfer initiates.
* Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether
* the transfer is finished. If the return status is 0, the transfer is finished.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* param xfer Pointer to flexio_i2s_transfer_t structure
* retval kStatus_Success Successfully start the data receive.
* retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished.
* retval kStatus_InvalidArgument The input parameter is invalid.
*/
status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -505,10 +639,10 @@ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
}
/* Add into queue */
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].dataSize = xfer->dataSize;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
/* Set state to busy */
handle->state = kFLEXIO_I2S_Busy;
@ -522,6 +656,15 @@ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Aborts the current send.
*
* note This API can be called at any time when interrupt non-blocking transfer initiates
* to abort the transfer in a early time.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
*/
void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
{
assert(handle);
@ -533,9 +676,18 @@ void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *ha
/* Clear the queue */
memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
handle->queueDriver = 0;
handle->queueUser = 0;
handle->queueUser = 0;
}
/*!
* brief Aborts the current receive.
*
* note This API can be called at any time when interrupt non-blocking transfer initiates
* to abort the transfer in a early time.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
*/
void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
{
assert(handle);
@ -547,9 +699,18 @@ void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t
/* Clear the queue */
memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
handle->queueDriver = 0;
handle->queueUser = 0;
handle->queueUser = 0;
}
/*!
* brief Gets the remaining bytes to be sent.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* param count Bytes sent.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
{
assert(handle);
@ -568,6 +729,15 @@ status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handl
return status;
}
/*!
* brief Gets the remaining bytes to be received.
*
* param base Pointer to FLEXIO_I2S_Type structure.
* param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
* return count Bytes received.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
{
assert(handle);
@ -586,14 +756,20 @@ status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_ha
return status;
}
/*!
* brief Tx interrupt handler.
*
* param i2sBase Pointer to FLEXIO_I2S_Type structure.
* param i2sHandle Pointer to flexio_i2s_handle_t structure
*/
void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
{
assert(i2sHandle);
flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
uint8_t *buffer = handle->queue[handle->queueDriver].data;
uint8_t dataSize = handle->bitWidth / 8U;
FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
uint8_t *buffer = handle->queue[handle->queueDriver].data;
uint8_t dataSize = handle->bitWidth / 8U;
/* Handle error */
if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex))
@ -611,7 +787,7 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
handle->queue[handle->queueDriver].data += dataSize;
}
/* If finished a blcok, call the callback function */
/* If finished a block, call the callback function */
if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
{
memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
@ -629,14 +805,20 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
}
}
/*!
* brief Rx interrupt handler.
*
* param i2sBase Pointer to FLEXIO_I2S_Type structure.
* param i2sHandle Pointer to flexio_i2s_handle_t structure.
*/
void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
{
assert(i2sHandle);
flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
uint8_t *buffer = handle->queue[handle->queueDriver].data;
uint8_t dataSize = handle->bitWidth / 8U;
FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
uint8_t *buffer = handle->queue[handle->queueDriver].data;
uint8_t dataSize = handle->bitWidth / 8U;
/* Handle transfer */
if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) &&
@ -649,7 +831,7 @@ void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
handle->queue[handle->queueDriver].data += dataSize;
}
/* If finished a blcok, call the callback function */
/* If finished a block, call the callback function */
if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
{
memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));

78
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_I2S_H_
#define _FSL_FLEXIO_I2S_H_
@ -48,17 +22,17 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2S driver version 2.1.4. */
#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*! @brief FlexIO I2S driver version 2.1.6. */
#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
/*@}*/
/*! @brief FlexIO I2S transfer status */
enum _flexio_i2s_status
{
kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */
kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */
kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */
kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */
kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */
kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */
kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */
kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */
kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */
};
@ -80,21 +54,21 @@ typedef struct _flexio_i2s_type
typedef enum _flexio_i2s_master_slave
{
kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */
kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */
kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */
} flexio_i2s_master_slave_t;
/*! @brief Define FlexIO FlexIO I2S interrupt mask. */
enum _flexio_i2s_interrupt_enable
{
kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
};
/*! @brief Define FlexIO FlexIO I2S status mask. */
enum _flexio_i2s_status_flags
{
kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */
kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */
};
/*! @brief FlexIO I2S configure structure */
@ -123,22 +97,22 @@ typedef struct _flexio_i2s_format
/*! @brief Audio sample rate */
typedef enum _flexio_i2s_sample_rate
{
kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */
kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */
kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */
kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */
kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */
kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */
kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */
kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */
kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */
kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */
kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */
kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */
kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */
kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */
kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */
kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */
kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */
} flexio_i2s_sample_rate_t;
/*! @brief Audio word width */
typedef enum _flexio_i2s_word_width
{
kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */
kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */
kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */
kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */
kFLEXIO_I2S_WordWidth32bits = 32U /*!< Audio data width 32 bits */
@ -198,7 +172,7 @@ extern "C" {
*
* @param base FlexIO I2S base pointer
* @param config FlexIO I2S configure structure.
*/
*/
void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config);
/*!
@ -219,7 +193,7 @@ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config);
* call the FLEXO_I2S_Init to use the FlexIO I2S module.
*
* @param base FlexIO I2S base pointer
*/
*/
void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base);
/*!
@ -227,7 +201,7 @@ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base);
*
* @param base Pointer to FLEXIO_I2S_Type
* @param enable True to enable, false dose not have any effect.
*/
*/
static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)
{
if (enable)
@ -248,7 +222,7 @@ static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)
*
* @param base Pointer to FLEXIO_I2S_Type structure
* @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
*/
*/
uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base);
/*! @} */
@ -349,7 +323,7 @@ static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base
* @param base Pointer to FLEXIO_I2S_Type structure
* @param format Pointer to FlexIO I2S audio data format structure.
* @param srcClock_Hz I2S master clock source frequency in Hz.
*/
*/
void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz);
/*!
@ -360,7 +334,7 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form
*
* @param base Pointer to FLEXIO_I2S_Type structure
* @param format Pointer to FlexIO I2S audio data format structure.
*/
*/
void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format);
/*!
@ -444,7 +418,7 @@ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
* @param handle FlexIO I2S handle pointer.
* @param format Pointer to audio data format structure.
* @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
*/
*/
void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
flexio_i2s_handle_t *handle,
flexio_i2s_format_t *format,

169
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_i2s_edma.h"
@ -39,7 +13,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
@ -86,14 +59,14 @@ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, boo
static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds);
/*******************************************************************************
* Code
******************************************************************************/
* Code
******************************************************************************/
static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
{
flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
/* If finished a blcok, call the callback function */
/* If finished a block, call the callback function */
memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
if (flexio_i2sHandle->callback)
@ -111,9 +84,9 @@ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, boo
static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
{
flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
/* If finished a blcok, call the callback function */
/* If finished a block, call the callback function */
memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
if (flexio_i2sHandle->callback)
@ -128,6 +101,19 @@ static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, boo
}
}
/*!
* brief Initializes the FlexIO I2S eDMA handle.
*
* This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master
* transactional APIs.
* Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S eDMA handle pointer.
* param callback FlexIO I2S eDMA callback function called while finished a block.
* param userData User parameter for callback.
* param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
*/
void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_edma_callback_t callback,
@ -141,13 +127,13 @@ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
/* Set flexio_i2s base to handle */
handle->dmaHandle = dmaHandle;
handle->callback = callback;
handle->userData = userData;
handle->callback = callback;
handle->userData = userData;
/* Set FLEXIO I2S state to idle */
handle->state = kFLEXIO_I2S_Idle;
s_edmaPrivateHandle[0].base = base;
s_edmaPrivateHandle[0].base = base;
s_edmaPrivateHandle[0].handle = handle;
/* Need to use scatter gather */
@ -157,6 +143,19 @@ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]);
}
/*!
* brief Initializes the FlexIO I2S Rx eDMA handle.
*
* This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional
* APIs.
* Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S eDMA handle pointer.
* param callback FlexIO I2S eDMA callback function called while finished a block.
* param userData User parameter for callback.
* param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
*/
void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_edma_callback_t callback,
@ -170,13 +169,13 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
/* Set flexio_i2s base to handle */
handle->dmaHandle = dmaHandle;
handle->callback = callback;
handle->userData = userData;
handle->callback = callback;
handle->userData = userData;
/* Set FLEXIO I2S state to idle */
handle->state = kFLEXIO_I2S_Idle;
s_edmaPrivateHandle[1].base = base;
s_edmaPrivateHandle[1].base = base;
s_edmaPrivateHandle[1].handle = handle;
/* Need to use scatter gather */
@ -186,6 +185,19 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]);
}
/*!
* brief Configures the FlexIO I2S Tx audio format.
*
* Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
* format to be transferred. This function also sets the eDMA parameter according to format.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S eDMA handle pointer
* param format Pointer to FlexIO I2S audio data format structure.
* param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.
* retval kStatus_Success Audio format set successfully.
* retval kStatus_InvalidArgument The input arguments is invalid.
*/
void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_format_t *format,
@ -204,10 +216,23 @@ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
FLEXIO_I2S_SlaveSetFormat(base, format);
}
/* Get the tranfer size from format, this should be used in EDMA configuration */
/* Get the transfer size from format, this should be used in EDMA configuration */
handle->bytesPerFrame = format->bitWidth / 8U;
}
/*!
* brief Performs a non-blocking FlexIO I2S transfer using DMA.
*
* note This interface returned immediately after transfer initiates. Users should call
* FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param xfer Pointer to DMA transfer structure.
* retval kStatus_Success Start a FlexIO I2S eDMA send successfully.
* retval kStatus_InvalidArgument The input arguments is invalid.
* retval kStatus_TxBusy FlexIO I2S is busy sending data.
*/
status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -215,7 +240,7 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
assert(handle && xfer);
edma_transfer_config_t config = {0};
uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
/* Check if input parameter invalid */
if ((xfer->data == NULL) || (xfer->dataSize == 0U))
@ -232,10 +257,10 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
handle->state = kFLEXIO_I2S_Busy;
/* Update the queue state */
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].dataSize = xfer->dataSize;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
/* Prepare edma configure */
EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame,
@ -258,6 +283,20 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO I2S receive using eDMA.
*
* note This interface returned immediately after transfer initiates. Users should call
* FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is
* finished.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param xfer Pointer to DMA transfer structure.
* retval kStatus_Success Start a FlexIO I2S eDMA receive successfully.
* retval kStatus_InvalidArgument The input arguments is invalid.
* retval kStatus_RxBusy FlexIO I2S is busy receiving data.
*/
status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_transfer_t *xfer)
@ -265,7 +304,7 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
assert(handle && xfer);
edma_transfer_config_t config = {0};
uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base);
/* Check if input parameter invalid */
if ((xfer->data == NULL) || (xfer->dataSize == 0U))
@ -282,10 +321,10 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
handle->state = kFLEXIO_I2S_Busy;
/* Update queue state */
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].dataSize = xfer->dataSize;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
/* Prepare edma configure */
EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
@ -308,6 +347,12 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO I2S transfer using eDMA.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
*/
void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
{
assert(handle);
@ -322,6 +367,12 @@ void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_han
handle->state = kFLEXIO_I2S_Idle;
}
/*!
* brief Aborts a FlexIO I2S receive using eDMA.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
*/
void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
{
assert(handle);
@ -336,6 +387,15 @@ void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_
handle->state = kFLEXIO_I2S_Idle;
}
/*!
* brief Gets the remaining bytes to be sent.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param count Bytes sent.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
{
assert(handle);
@ -356,6 +416,15 @@ status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_e
return status;
}
/*!
* brief Get the remaining bytes to be received.
*
* param base FlexIO I2S peripheral base address.
* param handle FlexIO I2S DMA handle pointer.
* param count Bytes received.
* retval kStatus_Success Succeed get the transfer count.
* retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
{
assert(handle);

36
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_I2S_EDMA_H_
#define _FSL_FLEXIO_I2S_EDMA_H_
@ -48,8 +22,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO I2S EDMA driver version 2.1.4. */
#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*! @brief FlexIO I2S EDMA driver version 2.1.5. */
#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*@}*/
typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t;
@ -138,7 +112,7 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
* @param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.
* @retval kStatus_Success Audio format set successfully.
* @retval kStatus_InvalidArgument The input arguments is invalid.
*/
*/
void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_format_t *format,

1286
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.c Normal file
View File

File diff suppressed because it is too large Load Diff

687
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.h Normal file
View File

@ -0,0 +1,687 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_MCULCD_H_
#define _FSL_FLEXIO_MCULCD_H_
#include "fsl_common.h"
#include "fsl_flexio.h"
/*!
* @addtogroup flexio_mculcd
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO MCULCD driver version 2.0.2. */
#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
#ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME
/*!
* @brief The delay time to wait for FLEXIO transmit complete.
*
* Currently there is no method to detect whether the data has been
* sent out from the shifter, so the driver use a software delay for this. When
* the data is written to shifter buffer, the driver call the delay
* function to wait for the data shift out.
* If this value is too small, then the last few bytes might be lost when writing
* data using interrupt method or DMA method.
*/
#define FLEXIO_MCULCD_WAIT_COMPLETE_TIME 512
#endif
#ifndef FLEXIO_MCULCD_DATA_BUS_WIDTH
/*!
* @brief The data bus width, must be 8 or 16.
*/
#define FLEXIO_MCULCD_DATA_BUS_WIDTH 16
#endif
#if (16 != FLEXIO_MCULCD_DATA_BUS_WIDTH) && (8 != FLEXIO_MCULCD_DATA_BUS_WIDTH)
#error Only support data bus 8-bit or 16-bit
#endif
/*! @brief FlexIO LCD transfer status */
enum _flexio_mculcd_status
{
kStatus_FLEXIO_MCULCD_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 0), /*!< FlexIO LCD is idle. */
kStatus_FLEXIO_MCULCD_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 1), /*!< FlexIO LCD is busy */
kStatus_FLEXIO_MCULCD_Error = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 2), /*!< FlexIO LCD error occurred */
};
/*! @brief Define FlexIO MCULCD pixel format. */
typedef enum _flexio_mculcd_pixel_format
{
kFLEXIO_MCULCD_RGB565 = 0, /*!< RGB565, 16-bit. */
kFLEXIO_MCULCD_BGR565, /*!< BGR565, 16-bit. */
kFLEXIO_MCULCD_RGB888, /*!< RGB888, 24-bit. */
kFLEXIO_MCULCD_BGR888, /*!< BGR888, 24-bit. */
} flexio_mculcd_pixel_format_t;
/*! @brief Define FlexIO MCULCD bus type. */
typedef enum _flexio_mculcd_bus
{
kFLEXIO_MCULCD_8080, /*!< Using Intel 8080 bus. */
kFLEXIO_MCULCD_6800, /*!< Using Motorola 6800 bus. */
} flexio_mculcd_bus_t;
/*! @brief Define FlexIO MCULCD interrupt mask. */
enum _flexio_mculcd_interrupt_enable
{
kFLEXIO_MCULCD_TxEmptyInterruptEnable = (1U << 0U), /*!< Transmit buffer empty interrupt enable. */
kFLEXIO_MCULCD_RxFullInterruptEnable = (1U << 1U), /*!< Receive buffer full interrupt enable. */
};
/*! @brief Define FlexIO MCULCD status mask. */
enum _flexio_mculcd_status_flags
{
kFLEXIO_MCULCD_TxEmptyFlag = (1U << 0U), /*!< Transmit buffer empty flag. */
kFLEXIO_MCULCD_RxFullFlag = (1U << 1U), /*!< Receive buffer full flag. */
};
/*! @brief Define FlexIO MCULCD DMA mask. */
enum _flexio_mculcd_dma_enable
{
kFLEXIO_MCULCD_TxDmaEnable = 0x1U, /*!< Tx DMA request source */
kFLEXIO_MCULCD_RxDmaEnable = 0x2U, /*!< Rx DMA request source */
};
/*! @brief Function to set or clear the CS and RS pin. */
typedef void (*flexio_mculcd_pin_func_t)(bool set);
/*! @brief Define FlexIO MCULCD access structure typedef. */
typedef struct _flexio_mculcd_type
{
FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
flexio_mculcd_bus_t busType; /*!< The bus type, 8080 or 6800. */
uint8_t dataPinStartIndex; /*!< Start index of the data pin, the FlexIO pin dataPinStartIndex
to (dataPinStartIndex + FLEXIO_MCULCD_DATA_BUS_WIDTH -1)
will be used for data transfer. Only support data bus width 8 and 16. */
uint8_t ENWRPinIndex; /*!< Pin select for WR(8080 mode), EN(6800 mode). */
uint8_t RDPinIndex; /*!< Pin select for RD(8080 mode), not used in 6800 mode. */
uint8_t txShifterStartIndex; /*!< Start index of shifters used for data write, it must be 0 or 4. */
uint8_t txShifterEndIndex; /*!< End index of shifters used for data write. */
uint8_t rxShifterStartIndex; /*!< Start index of shifters used for data read. */
uint8_t rxShifterEndIndex; /*!< End index of shifters used for data read, it must be 3 or 7. */
uint8_t timerIndex; /*!< Timer index used in FlexIO MCULCD. */
flexio_mculcd_pin_func_t setCSPin; /*!< Function to set or clear the CS pin. */
flexio_mculcd_pin_func_t setRSPin; /*!< Function to set or clear the RS pin. */
flexio_mculcd_pin_func_t setRDWRPin; /*!< Function to set or clear the RD/WR pin, only used in 6800 mode. */
} FLEXIO_MCULCD_Type;
/*! @brief Define FlexIO MCULCD configuration structure. */
typedef struct _flexio_mculcd_config
{
bool enable; /*!< Enable/disable FlexIO MCULCD after configuration. */
bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */
bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */
bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
fast access requires the FlexIO clock to be at least
twice the frequency of the bus clock. */
uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
} flexio_mculcd_config_t;
/*! @brief Transfer mode.*/
typedef enum _flexio_mculcd_transfer_mode
{
kFLEXIO_MCULCD_ReadArray, /*!< Read data into an array. */
kFLEXIO_MCULCD_WriteArray, /*!< Write data from an array. */
kFLEXIO_MCULCD_WriteSameValue, /*!< Write the same value many times. */
} flexio_mculcd_transfer_mode_t;
/*! @brief Define FlexIO MCULCD transfer structure. */
typedef struct _flexio_mculcd_transfer
{
uint32_t command; /*!< Command to send. */
flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times,
this is the value to send. When writing or reading array,
this is the address of the data array. */
size_t dataSize; /*!< How many bytes to transfer. */
} flexio_mculcd_transfer_t;
/*! @brief typedef for flexio_mculcd_handle_t in advance. */
typedef struct _flexio_mculcd_handle flexio_mculcd_handle_t;
/*! @brief FlexIO MCULCD callback for finished transfer.
*
* When transfer finished, the callback function is called and returns the
* @p status as kStatus_FLEXIO_MCULCD_Idle.
*/
typedef void (*flexio_mculcd_transfer_callback_t)(FLEXIO_MCULCD_Type *base,
flexio_mculcd_handle_t *handle,
status_t status,
void *userData);
/*! @brief Define FlexIO MCULCD handle structure. */
struct _flexio_mculcd_handle
{
uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times,
this is the value to send. When writing or reading array,
this is the address of the data array. */
size_t dataCount; /*!< Total count to be transferred. */
volatile size_t remainingCount; /*!< Remaining count to transfer. */
volatile uint32_t state; /*!< FlexIO MCULCD internal state. */
flexio_mculcd_transfer_callback_t completionCallback; /*!< FlexIO MCULCD transfer completed callback. */
void *userData; /*!< Callback parameter. */
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /*_cplusplus*/
/*!
* @name FlexIO MCULCD Configuration
* @{
*/
/*!
* @brief Ungates the FlexIO clock, resets the FlexIO module, configures the
* FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD
* configuration.
* The configuration structure can be filled by the user, or be set with default
* values
* by the @ref FLEXIO_MCULCD_GetDefaultConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param config Pointer to the flexio_mculcd_config_t structure.
* @param srcClock_Hz FlexIO source clock in Hz.
* @retval kStatus_Success Initialization success.
* @retval kStatus_InvalidArgument Initialization failed because of invalid
* argument.
*/
status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz);
/*!
* @brief Resets the FLEXIO_MCULCD timer and shifter configuration.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*/
void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base);
/*!
* @brief Gets the default configuration to configure the FlexIO MCULCD.
*
* The default configuration value is:
* @code
* config->enable = true;
* config->enableInDoze = false;
* config->enableInDebug = true;
* config->enableFastAccess = true;
* config->baudRate_Bps = 96000000U;
* @endcode
* @param Config Pointer to the flexio_mculcd_config_t structure.
*/
void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config);
/*@}*/
/*!
* @name Status
* @{
*/
/*!
* @brief Gets FlexIO MCULCD status flags.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @return status flag; OR'ed value or the @ref _flexio_mculcd_status_flags.
*
* @note Don't use this function with DMA APIs.
*/
uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base);
/*!
* @brief Clears FlexIO MCULCD status flags.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param mask Status to clear, it is the OR'ed value of @ref
* _flexio_mculcd_status_flags.
*
* @note Don't use this function with DMA APIs.
*/
void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask);
/*@}*/
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enables the FlexIO MCULCD interrupt.
*
* This function enables the FlexIO MCULCD interrupt.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param mask Interrupts to enable, it is the OR'ed value of @ref
* _flexio_mculcd_interrupt_enable.
*/
void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
/*!
* @brief Disables the FlexIO MCULCD interrupt.
*
* This function disables the FlexIO MCULCD interrupt.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param mask Interrupts to disable, it is the OR'ed value of @ref
* _flexio_mculcd_interrupt_enable.
*/
void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
/*@}*/
/*!
* @name DMA Control
* @{
*/
/*!
* @brief Enables/disables the FlexIO MCULCD transmit DMA.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param mask MCULCD DMA source.
* @param enable True means enable DMA, false means disable DMA.
*/
static inline void FLEXIO_MCULCD_EnableTxDMA(FLEXIO_MCULCD_Type *base, bool enable)
{
FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1U << base->txShifterStartIndex), enable);
}
/*!
* @brief Enables/disables the FlexIO MCULCD receive DMA.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param mask MCULCD DMA source.
* @param enable True means enable DMA, false means disable DMA.
*/
static inline void FLEXIO_MCULCD_EnableRxDMA(FLEXIO_MCULCD_Type *base, bool enable)
{
FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1U << base->rxShifterEndIndex), enable);
}
/*!
* @brief Gets the FlexIO MCULCD transmit data register address.
*
* This function returns the MCULCD data register address, which is mainly used
* by DMA/eDMA.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @return FlexIO MCULCD transmit data register address.
*/
static inline uint32_t FLEXIO_MCULCD_GetTxDataRegisterAddress(FLEXIO_MCULCD_Type *base)
{
return (uint32_t) & (base->flexioBase->SHIFTBUF[base->txShifterStartIndex]);
}
/*!
* @brief Gets the FlexIO MCULCD receive data register address.
*
* This function returns the MCULCD data register address, which is mainly used
* by DMA/eDMA.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @return FlexIO MCULCD receive data register address.
*/
static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type *base)
{
return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]);
}
/*@}*/
/*!
* @name Bus Operations
* @{
*/
/*!
* @brief Set desired baud rate.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param baudRate_Bps Desired baud rate.
* @param srcClock_Hz FLEXIO clock frequency in Hz.
* @retval kStatus_Success Set successfully.
* @retval kStatus_InvalidArgument Could not set the baud rate.
*/
status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
/*!
* @brief Configures the FLEXIO MCULCD to multiple beats write mode.
*
* At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
* multiple beats write mode using this function. After write operation, the configuration
* is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
*
* Clear the write configuration set by @ref FLEXIO_MCULCD_SetSingleBeatWriteConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Configures the FLEXIO MCULCD to multiple beats read mode.
*
* At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
* to multiple beats read mode using this function. After read operation, the configuration
* is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatReadConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
*
* Clear the read configuration set by @ref FLEXIO_MCULCD_SetSingleBeatReadConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Configures the FLEXIO MCULCD to multiple beats write mode.
*
* At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
* multiple beats write mode using this function. After write operation, the configuration
* is cleared by @ref FLEXIO_MCULCD_ClearMultBeatsWriteConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
*
* Clear the write configuration set by @ref FLEXIO_MCULCD_SetMultBeatsWriteConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Configures the FLEXIO MCULCD to multiple beats read mode.
*
* At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
* to multiple beats read mode using this function. After read operation, the configuration
* is cleared by @ref FLEXIO_MCULCD_ClearMultBeatsReadConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
*
* Clear the read configuration set by @ref FLEXIO_MCULCD_SetMultBeatsReadConfig.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
*
* @note This is an internal used function, upper layer should not use.
*/
void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base);
/*!
* @brief Enables/disables the FlexIO MCULCD module operation.
*
* @param base Pointer to the FLEXIO_MCULCD_Type.
* @param enable True to enable, false does not have any effect.
*/
static inline void FLEXIO_MCULCD_Enable(FLEXIO_MCULCD_Type *base, bool enable)
{
if (enable)
{
FLEXIO_Enable(base->flexioBase, enable);
}
}
/*!
* @brief Read data from the FLEXIO MCULCD RX shifter buffer.
*
* Read data from the RX shift buffer directly, it does no check whether the
* buffer is empty or not.
*
* If the data bus width is 8-bit:
* @code
* uint8_t value;
* value = (uint8_t)FLEXIO_MCULCD_ReadData(base);
* @endcode
*
* If the data bus width is 16-bit:
* @code
* uint16_t value;
* value = (uint16_t)FLEXIO_MCULCD_ReadData(base);
* @endcode
*
* @note This function returns the RX shifter buffer value (32-bit) directly.
* The return value should be converted according to data bus width.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @return The data read out.
*
* @note Don't use this function with DMA APIs.
*/
uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base);
/*!
* @brief Write data into the FLEXIO MCULCD TX shifter buffer.
*
* Write data into the TX shift buffer directly, it does no check whether the
* buffer is full or not.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param data The data to write.
*
* @note Don't use this function with DMA APIs.
*/
static inline void FLEXIO_MCULCD_WriteData(FLEXIO_MCULCD_Type *base, uint32_t data)
{
base->flexioBase->SHIFTBUF[base->txShifterStartIndex] = data;
}
/*!
* @brief Assert the nCS to start transfer.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
*/
static inline void FLEXIO_MCULCD_StartTransfer(FLEXIO_MCULCD_Type *base)
{
base->setCSPin(false);
}
/*!
* @brief De-assert the nCS to stop transfer.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
*/
static inline void FLEXIO_MCULCD_StopTransfer(FLEXIO_MCULCD_Type *base)
{
base->setCSPin(true);
}
/*!
* @brief Wait for transmit data send out finished.
*
* Currently there is no effective method to wait for the data send out
* from the shiter, so here use a while loop to wait.
*
* @note This is an internal used function.
*/
void FLEXIO_MCULCD_WaitTransmitComplete(void);
/*!
* @brief Send command in blocking way.
*
* This function sends the command and returns when the command has been sent
* out.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param command The command to send.
*/
void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command);
/*!
* @brief Send data array in blocking way.
*
* This function sends the data array and returns when the data sent out.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param data The data array to send.
* @param size How many bytes to write.
*/
void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size);
/*!
* @brief Read data into array in blocking way.
*
* This function reads the data into array and returns when the data read
* finished.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param data The array to save the data.
* @param size How many bytes to read.
*/
void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size);
/*!
* @brief Send the same value many times in blocking way.
*
* This function sends the same value many times. It could be used to clear the
* LCD screen. If the data bus width is 8, this function will send LSB 8 bits of
* @p sameValue for @p size times. If the data bus is 16, this function will send
* LSB 16 bits of @p sameValue for @p size / 2 times.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param sameValue The same value to send.
* @param size How many bytes to send.
*/
void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size);
/*!
* @brief Performs a polling transfer.
*
* @note The API does not return until the transfer finished.
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param xfer pointer to flexio_mculcd_transfer_t structure.
*/
void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer);
/*@}*/
/*!
* @name Transactional
* @{
*/
/*!
* @brief Initializes the FlexIO MCULCD handle, which is used in transactional
* functions.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param handle Pointer to the flexio_mculcd_handle_t structure to store the
* transfer state.
* @param callback The callback function.
* @param userData The parameter of the callback function.
* @retval kStatus_Success Successfully create the handle.
* @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base,
flexio_mculcd_handle_t *handle,
flexio_mculcd_transfer_callback_t callback,
void *userData);
/*!
* @brief Transfer data using IRQ.
*
* This function sends data using IRQ. This is a non-blocking function, which
* returns right away. When all data is sent out/received, the callback
* function is called.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param handle Pointer to the flexio_mculcd_handle_t structure to store the
* transfer state.
* @param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t.
* @retval kStatus_Success Successfully start a transfer.
* @retval kStatus_InvalidArgument Input argument is invalid.
* @retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer.
*/
status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base,
flexio_mculcd_handle_t *handle,
flexio_mculcd_transfer_t *xfer);
/*!
* @brief Aborts the data transfer, which used IRQ.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param handle Pointer to the flexio_mculcd_handle_t structure to store the
* transfer state.
*/
void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle);
/*!
* @brief Gets the data transfer status which used IRQ.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param handle Pointer to the flexio_mculcd_handle_t structure to store the
* transfer state.
* @param count How many bytes transferred so far by the non-blocking transaction.
* @retval kStatus_Success Get the transferred count Successfully.
* @retval kStatus_NoTransferInProgress No transfer in process.
*/
status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count);
/*!
* @brief FlexIO MCULCD IRQ handler function.
*
* @param base Pointer to the FLEXIO_MCULCD_Type structure.
* @param handle Pointer to the flexio_mculcd_handle_t structure to store the
* transfer state.
*/
void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle);
/*@}*/
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
/*@}*/
#endif /*_FSL_FLEXIO_MCULCD_H_*/

564
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.c Normal file
View File

@ -0,0 +1,564 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_mculcd_edma.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_edma"
#endif
#define EDMA_MAX_MAJOR_COUNT (DMA_CITER_ELINKNO_CITER_MASK >> DMA_CITER_ELINKNO_CITER_SHIFT)
enum _MCULCD_transfer_state
{
kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */
kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */
kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */
kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress.
*/
};
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief EDMA callback function for FLEXIO MCULCD TX.
*
* For details, see @ref edma_callback.
*/
static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds);
/*!
* @brief EDMA callback function for FLEXIO MCULCD RX.
*
* For details, see @ref edma_callback.
*/
static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds);
/*!
* @brief Set EDMA config for FLEXIO MCULCD transfer.
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param handle pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
*/
static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle);
/*!
* @brief Convert the FlexIO shifter number to eDMA modulo.
*
* @param shifterNum The FlexIO shifter number.
* @param modulo The modulo number.
* @retval Get the modulo successfully.
* @retval Could not get the modulo for the shifter number.
*/
static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo);
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds)
{
tcds = tcds;
flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param;
FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base;
if (transferDone)
{
if (flexioLcdMcuHandle->remainingCount >= flexioLcdMcuHandle->minorLoopBytes)
{
FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle);
EDMA_StartTransfer(flexioLcdMcuHandle->txDmaHandle);
}
else
{
FLEXIO_MCULCD_EnableTxDMA(flexioLcdMcuBase, false);
/* Now the data are in shifter, wait for the data send out from the shifter. */
FLEXIO_MCULCD_WaitTransmitComplete();
/* Disable the TX shifter and the timer. */
FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase);
/* Send the remaining data. */
if (flexioLcdMcuHandle->remainingCount)
{
if (kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state)
{
FLEXIO_MCULCD_WriteSameValueBlocking(flexioLcdMcuBase, flexioLcdMcuHandle->dataAddrOrSameValue,
flexioLcdMcuHandle->remainingCount);
}
else
{
FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase,
(void *)flexioLcdMcuHandle->dataAddrOrSameValue,
flexioLcdMcuHandle->remainingCount);
}
}
/* De-assert nCS. */
FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
/* Change the state. */
flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle;
flexioLcdMcuHandle->dataCount = 0;
flexioLcdMcuHandle->remainingCount = 0;
/* Callback to inform upper layer. */
if (flexioLcdMcuHandle->completionCallback)
{
flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle,
flexioLcdMcuHandle->userData);
}
}
}
}
static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds)
{
tcds = tcds;
uint32_t i;
uint32_t rxBufAddr;
flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param;
FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base;
FLEXIO_Type *flexioBase = flexioLcdMcuBase->flexioBase;
if (transferDone)
{
if (flexioLcdMcuHandle->remainingCount >= (2 * flexioLcdMcuHandle->minorLoopBytes))
{
FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle);
EDMA_StartTransfer(flexioLcdMcuHandle->rxDmaHandle);
}
else
{
FLEXIO_MCULCD_EnableRxDMA(flexioLcdMcuBase, false);
/* Wait the data saved to the shifter buffer. */
while (!((1U << flexioLcdMcuBase->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase)))
{
}
/* Disable the RX shifter and the timer. */
FLEXIO_MCULCD_ClearMultiBeatsReadConfig(flexioLcdMcuBase);
rxBufAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(flexioLcdMcuBase);
/* Read out the data. */
#if (defined(__CORTEX_M) && (__CORTEX_M == 0))
/* Cortex M0 and M0+ only support aligned access. */
for (i = 0; i < flexioLcdMcuHandle->rxShifterNum * 4; i++)
{
((uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint8_t *)rxBufAddr)[i];
}
#else
for (i = 0; i < flexioLcdMcuHandle->rxShifterNum; i++)
{
((uint32_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint32_t *)rxBufAddr)[i];
}
#endif
flexioLcdMcuHandle->remainingCount -= flexioLcdMcuHandle->minorLoopBytes;
if (flexioLcdMcuHandle->remainingCount)
{
FLEXIO_MCULCD_ReadDataArrayBlocking(
flexioLcdMcuBase,
(void *)(flexioLcdMcuHandle->dataAddrOrSameValue + flexioLcdMcuHandle->minorLoopBytes),
flexioLcdMcuHandle->remainingCount);
}
/* De-assert nCS. */
FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
/* Change the state. */
flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle;
flexioLcdMcuHandle->dataCount = 0;
flexioLcdMcuHandle->remainingCount = 0;
/* Callback to inform upper layer. */
if (flexioLcdMcuHandle->completionCallback)
{
flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle,
flexioLcdMcuHandle->userData);
}
}
}
}
static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle)
{
edma_transfer_config_t xferConfig = {0};
edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes;
int16_t offset;
uint32_t majorLoopCounts;
uint32_t transferCount;
#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
transferSize = kEDMA_TransferSize1Bytes;
offset = 1;
#else
transferSize = kEDMA_TransferSize2Bytes;
offset = 2;
#endif
majorLoopCounts = handle->remainingCount / handle->minorLoopBytes;
/* For reading, the last minor loop data is not tranfered by DMA. */
if (kFLEXIO_MCULCD_StateReadArray == handle->state)
{
majorLoopCounts--;
}
if (majorLoopCounts > EDMA_MAX_MAJOR_COUNT)
{
majorLoopCounts = EDMA_MAX_MAJOR_COUNT;
}
transferCount = majorLoopCounts * handle->minorLoopBytes;
if (kFLEXIO_MCULCD_StateReadArray == handle->state)
{
xferConfig.srcAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(base);
xferConfig.destAddr = handle->dataAddrOrSameValue;
xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes;
xferConfig.destTransferSize = transferSize;
xferConfig.srcOffset = 4;
xferConfig.destOffset = offset;
xferConfig.minorLoopBytes = handle->minorLoopBytes;
xferConfig.majorLoopCounts = majorLoopCounts;
handle->remainingCount -= transferCount;
handle->dataAddrOrSameValue += transferCount;
EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, handle->rxEdmaModulo,
kEDMA_ModuloDisable);
}
else
{
if (kFLEXIO_MCULCD_StateWriteArray == handle->state)
{
xferConfig.srcAddr = handle->dataAddrOrSameValue;
xferConfig.srcOffset = offset;
handle->dataAddrOrSameValue += transferCount;
}
else
{
xferConfig.srcAddr = (uint32_t)(&(handle->dataAddrOrSameValue));
xferConfig.srcOffset = 0;
}
xferConfig.destAddr = FLEXIO_MCULCD_GetTxDataRegisterAddress(base);
xferConfig.srcTransferSize = transferSize;
xferConfig.destTransferSize = kEDMA_TransferSize4Bytes;
xferConfig.destOffset = 4;
xferConfig.minorLoopBytes = handle->minorLoopBytes;
xferConfig.majorLoopCounts = majorLoopCounts;
handle->remainingCount -= transferCount;
EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, kEDMA_ModuloDisable,
handle->txEdmaModulo);
}
}
static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo)
{
bool ret = true;
switch (shifterNum)
{
case 1U:
*modulo = kEDMA_Modulo4bytes;
break;
case 2U:
*modulo = kEDMA_Modulo8bytes;
break;
case 4U:
*modulo = kEDMA_Modulo16bytes;
break;
case 8U:
*modulo = kEDMA_Modulo32bytes;
break;
default:
ret = false;
break;
}
return ret;
}
/*!
* brief Initializes the FLEXO MCULCD master eDMA handle.
*
* This function initializes the FLEXO MCULCD master eDMA handle which can be
* used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
* instance, call this API once to get the initialized handle.
*
* param base Pointer to FLEXIO_MCULCD_Type structure.
* param handle Pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* param callback MCULCD transfer complete callback, NULL means no callback.
* param userData callback function parameter.
* param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX,
* the DMA request source of this handle should be the first of TX shifters.
* param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX,
* the DMA request source of this handle should be the last of RX shifters.
* retval kStatus_Success Successfully create the handle.
*/
status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
flexio_mculcd_edma_transfer_callback_t callback,
void *userData,
edma_handle_t *txDmaHandle,
edma_handle_t *rxDmaHandle)
{
assert(handle);
/* Zero the handle. */
memset(handle, 0, sizeof(*handle));
/* Initialize the state. */
handle->state = kFLEXIO_MCULCD_StateIdle;
/* Register callback and userData. */
handle->completionCallback = callback;
handle->userData = userData;
handle->base = base;
handle->txShifterNum = base->txShifterEndIndex - base->txShifterStartIndex + 1U;
handle->rxShifterNum = base->rxShifterEndIndex - base->rxShifterStartIndex + 1U;
if (rxDmaHandle)
{
if (!FLEXIO_MCULCD_GetEDMAModulo(handle->rxShifterNum, &handle->rxEdmaModulo))
{
return kStatus_InvalidArgument;
}
handle->rxDmaHandle = rxDmaHandle;
EDMA_SetCallback(rxDmaHandle, FLEXIO_MCULCD_RxEDMACallback, handle);
}
if (txDmaHandle)
{
if (!FLEXIO_MCULCD_GetEDMAModulo(handle->txShifterNum, &handle->txEdmaModulo))
{
return kStatus_InvalidArgument;
}
handle->txDmaHandle = txDmaHandle;
EDMA_SetCallback(txDmaHandle, FLEXIO_MCULCD_TxEDMACallback, handle);
}
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO MCULCD transfer using eDMA.
*
* This function returns immediately after transfer initiates. To check whether
* the transfer is completed, user could:
* 1. Use the transfer completed callback;
* 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* param xfer Pointer to FlexIO MCULCD transfer structure.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
flexio_mculcd_transfer_t *xfer)
{
assert(handle);
assert(xfer);
/*
* The data transfer mechanism:
*
* Read:
* Assume the data length is Lr = (n1 * minorLoopBytes + n2), where
* n2 < minorLoopBytes.
* If (n1 <= 1), then all data are sent using blocking method.
* If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read
* using DMA, the left (minorLoopBytes + n2) are read using blocking method.
*
* Write:
* Assume the data length is Lw = (n1 * minorLoopBytes + n2), where
* n2 < minorLoopBytes.
* If (n1 = 0), then all data are sent using blocking method.
* If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent
* using DMA, the left n2 are sent using blocking method.
*/
/* Check if the device is busy. */
if (kFLEXIO_MCULCD_StateIdle != handle->state)
{
return kStatus_FLEXIO_MCULCD_Busy;
}
/* Set the state in handle. */
if (kFLEXIO_MCULCD_ReadArray == xfer->mode)
{
handle->state = kFLEXIO_MCULCD_StateReadArray;
handle->minorLoopBytes = handle->rxShifterNum * 4U;
}
else
{
handle->minorLoopBytes = handle->txShifterNum * 4U;
if (kFLEXIO_MCULCD_WriteArray == xfer->mode)
{
handle->state = kFLEXIO_MCULCD_StateWriteArray;
}
else
{
handle->state = kFLEXIO_MCULCD_StateWriteSameValue;
}
}
/*
* For TX, if data is less than one minor loop, then use polling method.
* For RX, if data is less than two minor loop, then use polling method.
*/
if ((xfer->dataSize < handle->minorLoopBytes) ||
((kFLEXIO_MCULCD_ReadArray == xfer->mode) && (xfer->dataSize < 2 * (handle->minorLoopBytes))))
{
FLEXIO_MCULCD_TransferBlocking(base, xfer);
handle->state = kFLEXIO_MCULCD_StateIdle;
/* Callback to inform upper layer. */
if (handle->completionCallback)
{
handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
}
}
else
{
handle->dataCount = xfer->dataSize;
handle->remainingCount = xfer->dataSize;
handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue;
/* Setup DMA to transfer data. */
/* Assert the nCS. */
FLEXIO_MCULCD_StartTransfer(base);
/* Send the command. */
FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
/* Setup the DMA configuration. */
FLEXIO_MCULCD_EDMAConfig(base, handle);
/* Start the transfer. */
if (kFLEXIO_MCULCD_ReadArray == xfer->mode)
{
/* For 6800, assert the RDWR pin. */
if (kFLEXIO_MCULCD_6800 == base->busType)
{
base->setRDWRPin(true);
}
FLEXIO_MCULCD_SetMultiBeatsReadConfig(base);
FLEXIO_MCULCD_EnableRxDMA(base, true);
EDMA_StartTransfer(handle->rxDmaHandle);
}
else
{
/* For 6800, de-assert the RDWR pin. */
if (kFLEXIO_MCULCD_6800 == base->busType)
{
base->setRDWRPin(false);
}
FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base);
FLEXIO_MCULCD_EnableTxDMA(base, true);
EDMA_StartTransfer(handle->txDmaHandle);
}
}
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO MCULCD transfer using eDMA.
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle FlexIO MCULCD eDMA handle pointer.
*/
void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle)
{
assert(handle);
/* Disable dma. */
if (handle->txDmaHandle)
{
EDMA_AbortTransfer(handle->txDmaHandle);
}
if (handle->rxDmaHandle)
{
EDMA_AbortTransfer(handle->rxDmaHandle);
}
/* Disable DMA enable bit. */
FLEXIO_MCULCD_EnableTxDMA(handle->base, false);
FLEXIO_MCULCD_EnableRxDMA(handle->base, false);
/* Set the handle state. */
handle->state = kFLEXIO_MCULCD_StateIdle;
handle->dataCount = 0;
}
/*!
* brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer.
*
* param base pointer to FLEXIO_MCULCD_Type structure.
* param handle FlexIO MCULCD eDMA handle pointer.
* param count Number of count transferred so far by the eDMA transaction.
* retval kStatus_Success Get the transferred count Successfully.
* retval kStatus_NoTransferInProgress No transfer in process.
*/
status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
size_t *count)
{
assert(handle);
assert(count);
uint32_t state = handle->state;
if (kFLEXIO_MCULCD_StateIdle == state)
{
return kStatus_NoTransferInProgress;
}
else
{
*count = handle->dataCount - handle->remainingCount;
if (kFLEXIO_MCULCD_StateReadArray == state)
{
*count -= handle->minorLoopBytes *
EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
}
else
{
*count -= handle->minorLoopBytes *
EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel);
}
}
return kStatus_Success;
}

153
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.h Normal file
View File

@ -0,0 +1,153 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_
#define _FSL_FLEXIO_MCULCD_EDMA_H_
#include "fsl_edma.h"
#include "fsl_flexio_mculcd.h"
/*!
* @addtogroup flexio_edma_mculcd
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*@{*/
/*! @brief FlexIO MCULCD EDMA driver version 2.0.2. */
#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */
typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t;
/*! @brief FlexIO MCULCD master callback for transfer complete.
*
* When transfer finished, the callback function is called and returns the
* @p status as kStatus_FLEXIO_MCULCD_Idle.
*/
typedef void (*flexio_mculcd_edma_transfer_callback_t)(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
status_t status,
void *userData);
/*! @brief FlexIO MCULCD eDMA transfer handle, users should not touch the
* content of the handle.*/
struct _flexio_mculcd_edma_handle
{
FLEXIO_MCULCD_Type *base; /*!< Pointer to the FLEXIO_MCULCD_Type. */
uint8_t txShifterNum; /*!< Number of shifters used for TX. */
uint8_t rxShifterNum; /*!< Number of shifters used for RX. */
uint32_t minorLoopBytes; /*!< eDMA transfer minor loop bytes. */
edma_modulo_t txEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */
edma_modulo_t rxEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */
uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times,
this is the value to send. When writing or
reading array, this is the address of the
data array. */
size_t dataCount; /*!< Total count to be transferred. */
volatile size_t remainingCount; /*!< Remaining count still not transfered. */
volatile uint32_t state; /*!< FlexIO MCULCD driver internal state. */
edma_handle_t *txDmaHandle; /*!< DMA handle for MCULCD TX */
edma_handle_t *rxDmaHandle; /*!< DMA handle for MCULCD RX */
flexio_mculcd_edma_transfer_callback_t completionCallback; /*!< Callback for MCULCD DMA transfer */
void *userData; /*!< User Data for MCULCD DMA callback */
};
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name eDMA Transactional
* @{
*/
/*!
* @brief Initializes the FLEXO MCULCD master eDMA handle.
*
* This function initializes the FLEXO MCULCD master eDMA handle which can be
* used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
* instance, call this API once to get the initialized handle.
*
* @param base Pointer to FLEXIO_MCULCD_Type structure.
* @param handle Pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* @param callback MCULCD transfer complete callback, NULL means no callback.
* @param userData callback function parameter.
* @param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX,
* the DMA request source of this handle should be the first of TX shifters.
* @param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX,
* the DMA request source of this handle should be the last of RX shifters.
* @retval kStatus_Success Successfully create the handle.
*/
status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
flexio_mculcd_edma_transfer_callback_t callback,
void *userData,
edma_handle_t *txDmaHandle,
edma_handle_t *rxDmaHandle);
/*!
* @brief Performs a non-blocking FlexIO MCULCD transfer using eDMA.
*
* This function returns immediately after transfer initiates. To check whether
* the transfer is completed, user could:
* 1. Use the transfer completed callback;
* 2. Polling function @ref FLEXIO_MCULCD_GetTransferCountEDMA
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param handle pointer to flexio_mculcd_edma_handle_t structure to store the
* transfer state.
* @param xfer Pointer to FlexIO MCULCD transfer structure.
* @retval kStatus_Success Successfully start a transfer.
* @retval kStatus_InvalidArgument Input argument is invalid.
* @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
* transfer.
*/
status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
flexio_mculcd_transfer_t *xfer);
/*!
* @brief Aborts a FlexIO MCULCD transfer using eDMA.
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param handle FlexIO MCULCD eDMA handle pointer.
*/
void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle);
/*!
* @brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer.
*
* @param base pointer to FLEXIO_MCULCD_Type structure.
* @param handle FlexIO MCULCD eDMA handle pointer.
* @param count Number of count transferred so far by the eDMA transaction.
* @retval kStatus_Success Get the transferred count Successfully.
* @retval kStatus_NoTransferInProgress No transfer in process.
*/
status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
flexio_mculcd_edma_handle_t *handle,
size_t *count);
/*! @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */

528
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_spi.h"
@ -43,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_spi"
#endif
/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
enum _flexio_spi_transfer_states
{
@ -163,6 +136,42 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_
handle->rxRemainingBytes -= handle->bytePerFrame;
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
* and configures the FlexIO SPI with FlexIO SPI master configuration. The
* configuration structure can be filled by the user, or be set with default values
* by the FLEXIO_SPI_MasterGetDefaultConfig().
*
* note FlexIO SPI master only support CPOL = 0, which means clock inactive low.
*
* Example
code
FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_spi_master_config_t config = {
.enableMaster = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 500000,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
endcode
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param masterConfig Pointer to the flexio_spi_master_config_t structure.
* param srcClock_Hz FlexIO source clock in Hz.
*/
void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
{
assert(base);
@ -170,7 +179,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
flexio_shifter_config_t shifterConfig;
flexio_timer_config_t timerConfig;
uint32_t ctrlReg = 0;
uint32_t ctrlReg = 0;
uint16_t timerDiv = 0;
uint16_t timerCmp = 0;
@ -198,34 +207,34 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
/* Do hardware configuration. */
/* 1. Configure the shifter 0 for tx. */
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinSelect = base->SDOPinIndex;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinSelect = base->SDOPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
{
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
}
else
{
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
}
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
/* 2. Configure the shifter 1 for rx. */
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->SDIPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->SDIPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
{
@ -239,20 +248,20 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
/*3. Configure the timer 0 for SCK. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinSelect = base->SCKPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinSelect = base->SCKPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerDiv = srcClock_Hz / masterConfig->baudRate_Bps;
timerDiv = timerDiv / 2 - 1;
@ -265,47 +274,65 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
/* 4. Configure the timer 1 for CSn. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinSelect = base->CSnPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
timerConfig.pinSelect = base->CSnPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerCompare = 0xFFFFU;
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
}
/*!
* brief Resets the FlexIO SPI timer and shifter config.
*
* param base Pointer to the FLEXIO_SPI_Type.
*/
void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
{
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
}
/*!
* brief Gets the default configuration to configure the FlexIO SPI master. The configuration
* can be used directly by calling the FLEXIO_SPI_MasterConfigure().
* Example:
code
flexio_spi_master_config_t masterConfig;
FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
endcode
* param masterConfig Pointer to the flexio_spi_master_config_t structure.
*/
void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
{
assert(masterConfig);
masterConfig->enableMaster = true;
masterConfig->enableInDoze = false;
masterConfig->enableInDebug = true;
/* Initializes the configure structure to zero. */
memset(masterConfig, 0, sizeof(*masterConfig));
masterConfig->enableMaster = true;
masterConfig->enableInDoze = false;
masterConfig->enableInDebug = true;
masterConfig->enableFastAccess = false;
/* Default baud rate 500kbps. */
masterConfig->baudRate_Bps = 500000U;
@ -315,6 +342,39 @@ void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
* configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
* configuration structure can be filled by the user, or be set with default values
* by the FLEXIO_SPI_SlaveGetDefaultConfig().
*
* note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
* FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
* Example
code
FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0}
};
flexio_spi_slave_config_t config = {
.enableSlave = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_SlaveInit(&spiDev, &config);
endcode
* param base Pointer to the FLEXIO_SPI_Type structure.
* param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
*/
void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
{
assert(base && slaveConfig);
@ -347,8 +407,8 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
/* Do hardware configuration. */
/* 1. Configure the shifter 0 for tx. */
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinSelect = base->SDOPinIndex;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinSelect = base->SDOPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
@ -356,24 +416,24 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
{
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
}
else
{
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
}
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
/* 2. Configure the shifter 1 for rx. */
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->SDIPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->SDIPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
{
@ -387,29 +447,29 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
/*3. Configure the timer 0 for shift clock. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->SCKPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->SCKPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
{
/* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous
PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
}
else
{
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
}
timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U;
@ -417,18 +477,36 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
}
/*!
* brief Gates the FlexIO clock.
*
* param base Pointer to the FLEXIO_SPI_Type.
*/
void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
{
FLEXIO_SPI_MasterDeinit(base);
}
/*!
* brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
* can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
* Example:
code
flexio_spi_slave_config_t slaveConfig;
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
endcode
* param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
*/
void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
{
assert(slaveConfig);
slaveConfig->enableSlave = true;
slaveConfig->enableInDoze = false;
slaveConfig->enableInDebug = true;
/* Initializes the configure structure to zero. */
memset(slaveConfig, 0, sizeof(*slaveConfig));
slaveConfig->enableSlave = true;
slaveConfig->enableInDoze = false;
slaveConfig->enableInDebug = true;
slaveConfig->enableFastAccess = false;
/* Default CPHA = 0. */
slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
@ -436,6 +514,16 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
}
/*!
* brief Enables the FlexIO SPI interrupt.
*
* This function enables the FlexIO SPI interrupt.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask interrupt source. The parameter can be any combination of the following values:
* arg kFLEXIO_SPI_RxFullInterruptEnable
* arg kFLEXIO_SPI_TxEmptyInterruptEnable
*/
void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
@ -448,6 +536,16 @@ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
}
}
/*!
* brief Disables the FlexIO SPI interrupt.
*
* This function disables the FlexIO SPI interrupt.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask interrupt source The parameter can be any combination of the following values:
* arg kFLEXIO_SPI_RxFullInterruptEnable
* arg kFLEXIO_SPI_TxEmptyInterruptEnable
*/
void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
@ -460,6 +558,14 @@ void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
}
}
/*!
* brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
* which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask SPI DMA source.
* param enable True means enable DMA, false means disable DMA.
*/
void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
{
if (mask & kFLEXIO_SPI_TxDmaEnable)
@ -473,10 +579,19 @@ void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
}
}
/*!
* brief Gets FlexIO SPI status flags.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* return status flag; Use the status flag to AND the following flag mask and get the status.
* arg kFLEXIO_SPI_TxEmptyFlag
* arg kFLEXIO_SPI_RxEmptyFlag
*/
uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
{
uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
uint32_t status = 0;
uint32_t status = 0;
status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U);
@ -484,6 +599,16 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
return status;
}
/*!
* brief Clears FlexIO SPI status flags.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param mask status flag
* The parameter can be any combination of the following values:
* arg kFLEXIO_SPI_TxEmptyFlag
* arg kFLEXIO_SPI_RxEmptyFlag
*/
void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_SPI_TxBufferEmptyFlag)
@ -496,10 +621,17 @@ void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
}
}
/*!
* brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param baudRate_Bps Baud Rate needed in Hz.
* param srcClockHz SPI source clock frequency in Hz.
*/
void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
{
uint16_t timerDiv = 0;
uint16_t timerCmp = 0;
uint16_t timerDiv = 0;
uint16_t timerCmp = 0;
FLEXIO_Type *flexioBase = base->flexioBase;
/* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
@ -513,6 +645,16 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps,
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
}
/*!
* brief Sends a buffer of data bytes.
*
* note This function blocks using the polling method until all bytes have been sent.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param direction Shift direction of MSB first or LSB first.
* param buffer The data bytes to send.
* param size The number of data bytes to send.
*/
void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
flexio_spi_shift_direction_t direction,
const uint8_t *buffer,
@ -531,6 +673,17 @@ void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
}
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks using the polling method until all bytes have been received.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param direction Shift direction of MSB first or LSB first.
* param buffer The buffer to store the received bytes.
* param size The number of data bytes to be received.
* param direction Shift direction of MSB first or LSB first.
*/
void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
flexio_spi_shift_direction_t direction,
uint8_t *buffer,
@ -549,46 +702,54 @@ void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
}
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks via polling until all bytes have been received.
*
* param base pointer to FLEXIO_SPI_Type structure
* param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
*/
void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
{
flexio_spi_shift_direction_t direction;
uint8_t bytesPerFrame;
uint32_t dataMode = 0;
uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
timerCmp &= 0x00FFU;
/* Configure the values in handle. */
switch (xfer->flags)
{
case kFLEXIO_SPI_8bitMsb:
dataMode = (8 * 2 - 1U) << 8U;
dataMode = (8 * 2 - 1U) << 8U;
bytesPerFrame = 1;
direction = kFLEXIO_SPI_MsbFirst;
direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_8bitLsb:
dataMode = (8 * 2 - 1U) << 8U;
dataMode = (8 * 2 - 1U) << 8U;
bytesPerFrame = 1;
direction = kFLEXIO_SPI_LsbFirst;
direction = kFLEXIO_SPI_LsbFirst;
break;
case kFLEXIO_SPI_16bitMsb:
dataMode = (16 * 2 - 1U) << 8U;
dataMode = (16 * 2 - 1U) << 8U;
bytesPerFrame = 2;
direction = kFLEXIO_SPI_MsbFirst;
direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_16bitLsb:
dataMode = (16 * 2 - 1U) << 8U;
dataMode = (16 * 2 - 1U) << 8U;
bytesPerFrame = 2;
direction = kFLEXIO_SPI_LsbFirst;
direction = kFLEXIO_SPI_LsbFirst;
break;
default:
dataMode = (8 * 2 - 1U) << 8U;
dataMode = (8 * 2 - 1U) << 8U;
bytesPerFrame = 1;
direction = kFLEXIO_SPI_MsbFirst;
direction = kFLEXIO_SPI_MsbFirst;
assert(true);
break;
}
@ -664,6 +825,16 @@ void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfe
}
}
/*!
* brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
* param callback The callback function.
* param userData The parameter of the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
flexio_spi_master_handle_t *handle,
flexio_spi_master_transfer_callback_t callback,
@ -687,6 +858,19 @@ status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
}
/*!
* brief Master transfer data using IRQ.
*
* This function sends data using IRQ. This is a non-blocking function, which returns
* right away. When all data is sent out/received, the callback function is called.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
* param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
*/
status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
flexio_spi_master_handle_t *handle,
flexio_spi_transfer_t *xfer)
@ -696,7 +880,7 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
uint32_t dataMode = 0;
uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
timerCmp &= 0x00FFU;
@ -716,29 +900,29 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
switch (xfer->flags)
{
case kFLEXIO_SPI_8bitMsb:
dataMode = (8 * 2 - 1U) << 8U;
dataMode = (8 * 2 - 1U) << 8U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_MsbFirst;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_8bitLsb:
dataMode = (8 * 2 - 1U) << 8U;
dataMode = (8 * 2 - 1U) << 8U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_LsbFirst;
handle->direction = kFLEXIO_SPI_LsbFirst;
break;
case kFLEXIO_SPI_16bitMsb:
dataMode = (16 * 2 - 1U) << 8U;
dataMode = (16 * 2 - 1U) << 8U;
handle->bytePerFrame = 2U;
handle->direction = kFLEXIO_SPI_MsbFirst;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_16bitLsb:
dataMode = (16 * 2 - 1U) << 8U;
dataMode = (16 * 2 - 1U) << 8U;
handle->bytePerFrame = 2U;
handle->direction = kFLEXIO_SPI_LsbFirst;
handle->direction = kFLEXIO_SPI_LsbFirst;
break;
default:
dataMode = (8 * 2 - 1U) << 8U;
dataMode = (8 * 2 - 1U) << 8U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_MsbFirst;
handle->direction = kFLEXIO_SPI_MsbFirst;
assert(true);
break;
}
@ -748,9 +932,9 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
/* Configure transfer size. */
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
handle->state = kFLEXIO_SPI_Busy;
handle->txData = xfer->txData;
handle->rxData = xfer->rxData;
handle->state = kFLEXIO_SPI_Busy;
handle->txData = xfer->txData;
handle->rxData = xfer->rxData;
handle->rxRemainingBytes = xfer->dataSize;
/* Save total transfer size. */
@ -795,6 +979,15 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief Gets the data transfer status which used IRQ.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
* param count Number of bytes transferred so far by the non-blocking transaction.
* retval kStatus_InvalidArgument count is Invalid.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
{
assert(handle);
@ -817,6 +1010,12 @@ status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_mas
return kStatus_Success;
}
/*!
* brief Aborts the master data transfer, which used IRQ.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
*/
void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
{
assert(handle);
@ -832,6 +1031,12 @@ void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_han
handle->txRemainingBytes = 0;
}
/*!
* brief FlexIO SPI master IRQ handler function.
*
* param spiType Pointer to the FLEXIO_SPI_Type structure.
* param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
*/
void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
{
assert(spiHandle);
@ -845,7 +1050,7 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
return;
}
base = (FLEXIO_SPI_Type *)spiType;
base = (FLEXIO_SPI_Type *)spiType;
status = FLEXIO_SPI_GetStatusFlags(base);
/* Handle rx. */
@ -871,6 +1076,16 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
}
}
/*!
* brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
* param callback The callback function.
* param userData The parameter of the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
flexio_spi_slave_handle_t *handle,
flexio_spi_slave_transfer_callback_t callback,
@ -894,6 +1109,19 @@ status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
}
/*!
* brief Slave transfer data using IRQ.
*
* This function sends data using IRQ. This is a non-blocking function, which returns
* right away. When all data is sent out/received, the callback function is called.
* param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
*
* param base Pointer to the FLEXIO_SPI_Type structure.
* param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
*/
status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
flexio_spi_slave_handle_t *handle,
flexio_spi_transfer_t *xfer)
@ -919,29 +1147,29 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
switch (xfer->flags)
{
case kFLEXIO_SPI_8bitMsb:
dataMode = 8 * 2 - 1U;
dataMode = 8 * 2 - 1U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_MsbFirst;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_8bitLsb:
dataMode = 8 * 2 - 1U;
dataMode = 8 * 2 - 1U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_LsbFirst;
handle->direction = kFLEXIO_SPI_LsbFirst;
break;
case kFLEXIO_SPI_16bitMsb:
dataMode = 16 * 2 - 1U;
dataMode = 16 * 2 - 1U;
handle->bytePerFrame = 2U;
handle->direction = kFLEXIO_SPI_MsbFirst;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_16bitLsb:
dataMode = 16 * 2 - 1U;
dataMode = 16 * 2 - 1U;
handle->bytePerFrame = 2U;
handle->direction = kFLEXIO_SPI_LsbFirst;
handle->direction = kFLEXIO_SPI_LsbFirst;
break;
default:
dataMode = 8 * 2 - 1U;
dataMode = 8 * 2 - 1U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_MsbFirst;
handle->direction = kFLEXIO_SPI_MsbFirst;
assert(true);
break;
}
@ -949,9 +1177,9 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
/* Configure transfer size. */
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
handle->state = kFLEXIO_SPI_Busy;
handle->txData = xfer->txData;
handle->rxData = xfer->rxData;
handle->state = kFLEXIO_SPI_Busy;
handle->txData = xfer->txData;
handle->rxData = xfer->rxData;
handle->txRemainingBytes = xfer->dataSize;
handle->rxRemainingBytes = xfer->dataSize;
@ -965,6 +1193,12 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief FlexIO SPI slave IRQ handler function.
*
* param spiType Pointer to the FLEXIO_SPI_Type structure.
* param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
*/
void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
{
assert(spiHandle);
@ -978,7 +1212,7 @@ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
return;
}
base = (FLEXIO_SPI_Type *)spiType;
base = (FLEXIO_SPI_Type *)spiType;
status = FLEXIO_SPI_GetStatusFlags(base);
/* Handle tx. */

60
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_SPI_H_
@ -61,8 +35,8 @@
/*! @brief Error codes for the FlexIO SPI driver. */
enum _flexio_spi_status
{
kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */
kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */
kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */
kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */
kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */
};
@ -70,9 +44,9 @@ enum _flexio_spi_status
typedef enum _flexio_spi_clock_phase
{
kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first
* cycle of a data transfer. */
* cycle of a data transfer. */
kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the
* first cycle of a data transfer. */
* first cycle of a data transfer. */
} flexio_spi_clock_phase_t;
/*! @brief FlexIO SPI data shifter direction options. */
@ -85,7 +59,7 @@ typedef enum _flexio_spi_shift_direction
/*! @brief FlexIO SPI data length mode options. */
typedef enum _flexio_spi_data_bitcount_mode
{
kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */
kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */
kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
} flexio_spi_data_bitcount_mode_t;
@ -93,29 +67,29 @@ typedef enum _flexio_spi_data_bitcount_mode
enum _flexio_spi_interrupt_enable
{
kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
};
/*! @brief Define FlexIO SPI status mask. */
enum _flexio_spi_status_flags
{
kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */
kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */
};
/*! @brief Define FlexIO SPI DMA mask. */
enum _flexio_spi_dma_enable
{
kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */
kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */
kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */
kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */
kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
};
/*! @brief Define FlexIO SPI transfer flags. */
enum _flexio_spi_transfer_flags
{
kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
};
@ -256,7 +230,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
* @brief Resets the FlexIO SPI timer and shifter config.
*
* @param base Pointer to the FLEXIO_SPI_Type.
*/
*/
void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base);
/*!
@ -310,7 +284,7 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
* @brief Gates the FlexIO clock.
*
* @param base Pointer to the FLEXIO_SPI_Type.
*/
*/
void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
/*!
@ -339,7 +313,7 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
* @return status flag; Use the status flag to AND the following flag mask and get the status.
* @arg kFLEXIO_SPI_TxEmptyFlag
* @arg kFLEXIO_SPI_RxEmptyFlag
*/
*/
uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
@ -351,7 +325,7 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
* The parameter can be any combination of the following values:
* @arg kFLEXIO_SPI_TxEmptyFlag
* @arg kFLEXIO_SPI_RxEmptyFlag
*/
*/
void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
@ -461,7 +435,7 @@ static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base
*
* @param base Pointer to the FLEXIO_SPI_Type.
* @param enable True to enable, false does not have any effect.
*/
*/
static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
{
if (enable)

140
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_spi_edma.h"
@ -95,12 +69,12 @@ static const uint16_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
static flexio_spi_master_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_SPI_HANDLE_COUNT];
/*******************************************************************************
* Code
******************************************************************************/
* Code
******************************************************************************/
static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
{
tcds = tcds;
tcds = tcds;
flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
/* Disable Tx DMA */
@ -125,7 +99,7 @@ static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool t
static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
{
tcds = tcds;
tcds = tcds;
flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
if (transferDone)
@ -152,8 +126,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
flexio_spi_transfer_t *xfer)
{
edma_transfer_config_t xferConfig;
flexio_spi_shift_direction_t direction;
edma_transfer_config_t xferConfig = {0};
flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst;
uint8_t bytesPerFrame;
/* Configure the values in handle. */
@ -161,23 +135,23 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
{
case kFLEXIO_SPI_8bitMsb:
bytesPerFrame = 1;
direction = kFLEXIO_SPI_MsbFirst;
direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_8bitLsb:
bytesPerFrame = 1;
direction = kFLEXIO_SPI_LsbFirst;
direction = kFLEXIO_SPI_LsbFirst;
break;
case kFLEXIO_SPI_16bitMsb:
bytesPerFrame = 2;
direction = kFLEXIO_SPI_MsbFirst;
direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_16bitLsb:
bytesPerFrame = 2;
direction = kFLEXIO_SPI_LsbFirst;
direction = kFLEXIO_SPI_LsbFirst;
break;
default:
bytesPerFrame = 1U;
direction = kFLEXIO_SPI_MsbFirst;
direction = kFLEXIO_SPI_MsbFirst;
assert(true);
break;
}
@ -186,13 +160,13 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
handle->transferSize = xfer->dataSize;
/* Configure tx transfer EDMA. */
xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
xferConfig.destOffset = 0;
if (bytesPerFrame == 1U)
{
xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
xferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
xferConfig.minorLoopBytes = 1;
xferConfig.minorLoopBytes = 1;
}
else
{
@ -200,22 +174,22 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
{
xferConfig.destAddr -= 1U;
}
xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes;
xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes;
xferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
xferConfig.minorLoopBytes = 2;
xferConfig.minorLoopBytes = 2;
}
/* Configure DMA channel. */
if (xfer->txData)
{
xferConfig.srcOffset = bytesPerFrame;
xferConfig.srcAddr = (uint32_t)(xfer->txData);
xferConfig.srcAddr = (uint32_t)(xfer->txData);
}
else
{
/* Disable the source increasement and source set to dummyData. */
xferConfig.srcOffset = 0;
xferConfig.srcAddr = (uint32_t)(&s_dummyData);
xferConfig.srcAddr = (uint32_t)(&s_dummyData);
}
xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes);
@ -239,8 +213,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
xferConfig.srcAddr -= 1U;
}
}
xferConfig.srcOffset = 0;
xferConfig.destAddr = (uint32_t)(xfer->rxData);
xferConfig.srcOffset = 0;
xferConfig.destAddr = (uint32_t)(xfer->rxData);
xferConfig.destOffset = bytesPerFrame;
EDMA_SubmitTransfer(handle->rxHandle, &xferConfig);
handle->rxInProgress = true;
@ -257,6 +231,23 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
}
}
/*!
* brief Initializes the FlexIO SPI master eDMA handle.
*
* This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master
* transactional
* APIs.
* For a specified FlexIO SPI instance, call this API once to get the initialized handle.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
* param callback SPI callback, NULL means no callback.
* param userData callback function parameter.
* param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer.
* param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
*/
status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
flexio_spi_master_edma_transfer_callback_t callback,
@ -273,7 +264,7 @@ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
{
if (s_edmaPrivateHandle[index].base == NULL)
{
s_edmaPrivateHandle[index].base = base;
s_edmaPrivateHandle[index].base = base;
s_edmaPrivateHandle[index].handle = handle;
break;
}
@ -309,6 +300,20 @@ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief Performs a non-blocking FlexIO SPI transfer using eDMA.
*
* note This interface returns immediately after transfer initiates. Call
* FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check
* whether the FlexIO SPI transfer is finished.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
* param xfer Pointer to FlexIO SPI transfer structure.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
*/
status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
flexio_spi_transfer_t *xfer)
@ -356,6 +361,13 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
return kStatus_Success;
}
/*!
* brief Gets the remaining bytes for FlexIO SPI eDMA transfer.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle FlexIO SPI eDMA handle pointer.
* param count Number of bytes transferred so far by the non-blocking transaction.
*/
status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
size_t *count)
@ -369,20 +381,26 @@ status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
if (handle->rxInProgress)
{
*count = (handle->transferSize -
(uint32_t)handle->nbytes *
EDMA_GetRemainingMajorLoopCount(handle->rxHandle->base, handle->rxHandle->channel));
*count =
(handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(
handle->rxHandle->base, handle->rxHandle->channel));
}
else
{
*count = (handle->transferSize -
(uint32_t)handle->nbytes *
EDMA_GetRemainingMajorLoopCount(handle->txHandle->base, handle->txHandle->channel));
*count =
(handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(
handle->txHandle->base, handle->txHandle->channel));
}
return kStatus_Success;
}
/*!
* brief Aborts a FlexIO SPI transfer using eDMA.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle FlexIO SPI eDMA handle pointer.
*/
void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)
{
assert(handle);
@ -399,6 +417,20 @@ void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master
handle->rxInProgress = false;
}
/*!
* brief Performs a non-blocking FlexIO SPI transfer using eDMA.
*
* note This interface returns immediately after transfer initiates. Call
* FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and
* check whether the FlexIO SPI transfer is finished.
*
* param base Pointer to FLEXIO_SPI_Type structure.
* param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
* param xfer Pointer to FlexIO SPI transfer structure.
* retval kStatus_Success Successfully start a transfer.
* retval kStatus_InvalidArgument Input argument is invalid.
* retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
*/
status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
flexio_spi_slave_edma_handle_t *handle,
flexio_spi_transfer_t *xfer)

28
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_SPI_EDMA_H_
#define _FSL_FLEXIO_SPI_EDMA_H_

417
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_uart.h"
@ -43,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_uart"
#endif
/*<! @brief uart transfer state. */
enum _flexio_uart_transfer_states
{
@ -115,16 +88,47 @@ static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle)
return full;
}
/*!
* brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART
* hardware, and configures the FlexIO UART with FlexIO UART configuration.
* The configuration structure can be filled by the user or be set with
* default values by FLEXIO_UART_GetDefaultConfig().
*
* Example
code
FLEXIO_UART_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_uart_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 115200U,
.bitCountPerChar = 8
};
FLEXIO_UART_Init(base, &config, srcClock_Hz);
endcode
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param userConfig Pointer to the flexio_uart_config_t structure.
* param srcClock_Hz FlexIO source clock in Hz.
* retval kStatus_Success Configuration success
* retval kStatus_InvalidArgument Buadrate configuration out of range
*/
status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)
{
assert(base && userConfig);
flexio_shifter_config_t shifterConfig;
flexio_timer_config_t timerConfig;
uint32_t ctrlReg = 0;
uint32_t ctrlReg = 0;
uint16_t timerDiv = 0;
uint16_t timerCmp = 0;
status_t result = kStatus_Success;
status_t result = kStatus_Success;
/* Clear the shifterConfig & timerConfig struct. */
memset(&shifterConfig, 0, sizeof(shifterConfig));
@ -149,33 +153,33 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
/* Do hardware configuration. */
/* 1. Configure the shifter 0 for tx. */
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.timerSelect = base->timerIndex[0];
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinSelect = base->TxPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
shifterConfig.pinSelect = base->TxPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
/*2. Configure the timer 0 for tx. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->TxPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->TxPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetNever;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerDiv = srcClock_Hz / userConfig->baudRate_Bps;
timerDiv = timerDiv / 2 - 1;
@ -193,33 +197,33 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
/* 3. Configure the shifter 1 for rx. */
shifterConfig.timerSelect = base->timerIndex[1];
shifterConfig.timerSelect = base->timerIndex[1];
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->RxPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
shifterConfig.pinSelect = base->RxPinIndex;
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
/* 4. Configure the timer 1 for rx. */
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex);
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex);
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->RxPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
timerConfig.pinSelect = base->RxPinIndex;
timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset;
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge;
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
timerConfig.timerCompare = timerCmp;
@ -228,18 +232,25 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
return result;
}
/*!
* brief Resets the FlexIO UART shifter and timer config.
*
* note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
*
* param base Pointer to FLEXIO_UART_Type structure
*/
void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
{
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
/* Clear the shifter flag. */
base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]);
base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]);
@ -248,13 +259,26 @@ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
}
/*!
* brief Gets the default configuration to configure the FlexIO UART. The configuration
* can be used directly for calling the FLEXIO_UART_Init().
* Example:
code
flexio_uart_config_t config;
FLEXIO_UART_GetDefaultConfig(&userConfig);
endcode
* param userConfig Pointer to the flexio_uart_config_t structure.
*/
void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
{
assert(userConfig);
userConfig->enableUart = true;
userConfig->enableInDoze = false;
userConfig->enableInDebug = true;
/* Initializes the configure structure to zero. */
memset(userConfig, 0, sizeof(*userConfig));
userConfig->enableUart = true;
userConfig->enableInDoze = false;
userConfig->enableInDebug = true;
userConfig->enableFastAccess = false;
/* Default baud rate 115200. */
userConfig->baudRate_Bps = 115200U;
@ -262,6 +286,14 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar;
}
/*!
* brief Enables the FlexIO UART interrupt.
*
* This function enables the FlexIO UART interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param mask Interrupt source.
*/
void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
@ -274,6 +306,14 @@ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
}
}
/*!
* brief Disables the FlexIO UART interrupt.
*
* This function disables the FlexIO UART interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param mask Interrupt source.
*/
void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
@ -286,6 +326,13 @@ void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
}
}
/*!
* brief Gets the FlexIO UART status flags.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* return FlexIO UART status flags.
*/
uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
{
uint32_t status = 0;
@ -300,6 +347,17 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
return status;
}
/*!
* brief Gets the FlexIO UART status flags.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param mask Status flag.
* The parameter can be any combination of the following values:
* arg kFLEXIO_UART_TxDataRegEmptyFlag
* arg kFLEXIO_UART_RxEmptyFlag
* arg kFLEXIO_UART_RxOverRunFlag
*/
void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
{
if (mask & kFLEXIO_UART_TxDataRegEmptyFlag)
@ -316,6 +374,15 @@ void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
}
}
/*!
* brief Sends a buffer of data bytes.
*
* note This function blocks using the polling method until all bytes have been sent.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param txData The data bytes to send.
* param txSize The number of data bytes to send.
*/
void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)
{
assert(txData);
@ -332,6 +399,15 @@ void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, si
}
}
/*!
* brief Receives a buffer of bytes.
*
* note This function blocks using the polling method until all bytes have been received.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param rxData The buffer to store the received bytes.
* param rxSize The number of data bytes to be received.
*/
void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)
{
assert(rxData);
@ -348,6 +424,26 @@ void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rx
}
}
/*!
* brief Initializes the UART handle.
*
* This function initializes the FlexIO UART handle, which can be used for other FlexIO
* UART transactional APIs. Call this API once to get the
* initialized handle.
*
* The UART driver supports the "background" receiving, which means that users can set up
* a RX ring buffer optionally. Data received is stored into the ring buffer even when
* the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data
* received in the ring buffer, users can get the received data from the ring buffer
* directly. The ring buffer is disabled if passing NULL as p ringBuffer.
*
* param base to FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param callback The callback function.
* param userData The parameter of the callback function.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
*/
status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
flexio_uart_transfer_callback_t callback,
@ -375,6 +471,23 @@ status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ);
}
/*!
* brief Sets up the RX ring buffer.
*
* This function sets up the RX ring buffer to a specific UART handle.
*
* When the RX ring buffer is used, data received is stored into the ring buffer even when
* the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received
* in the ring buffer, users can get the received data from the ring buffer directly.
*
* note When using the RX ring buffer, one byte is reserved for internal use. In other
* words, if p ringBufferSize is 32, only 31 bytes are used for saving data.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
* param ringBufferSize Size of the ring buffer.
*/
void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
uint8_t *ringBuffer,
@ -385,7 +498,7 @@ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
/* Setup the ringbuffer address */
if (ringBuffer)
{
handle->rxRingBuffer = ringBuffer;
handle->rxRingBuffer = ringBuffer;
handle->rxRingBufferSize = ringBufferSize;
handle->rxRingBufferHead = 0U;
handle->rxRingBufferTail = 0U;
@ -395,6 +508,14 @@ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
}
}
/*!
* brief Aborts the background transfer and uninstalls the ring buffer.
*
* This function aborts the background transfer and uninstalls the ring buffer.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
{
assert(handle);
@ -404,12 +525,29 @@ void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_hand
FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
}
handle->rxRingBuffer = NULL;
handle->rxRingBuffer = NULL;
handle->rxRingBufferSize = 0U;
handle->rxRingBufferHead = 0U;
handle->rxRingBufferTail = 0U;
}
/*!
* brief Transmits a buffer of data using the interrupt method.
*
* This function sends data using an interrupt method. This is a non-blocking function,
* which returns directly without waiting for all data to be written to the TX register. When
* all data is written to the TX register in ISR, the FlexIO UART driver calls the callback
* function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter.
*
* note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written
* to the TX register. However, it does not ensure that all data is sent out.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t.
* retval kStatus_Success Successfully starts the data transmission.
* retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register.
*/
status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
flexio_uart_transfer_t *xfer)
@ -429,10 +567,10 @@ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
}
else
{
handle->txData = xfer->data;
handle->txDataSize = xfer->dataSize;
handle->txData = xfer->data;
handle->txDataSize = xfer->dataSize;
handle->txDataSizeAll = xfer->dataSize;
handle->txState = kFLEXIO_UART_TxBusy;
handle->txState = kFLEXIO_UART_TxBusy;
/* Enable transmiter interrupt. */
FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
@ -443,15 +581,35 @@ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Aborts the interrupt-driven data transmit.
*
* This function aborts the interrupt-driven data sending. Get the remainBytes to find out
* how many bytes are still not sent out.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
{
/* Disable the transmitter and disable the interrupt. */
FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
handle->txDataSize = 0;
handle->txState = kFLEXIO_UART_TxIdle;
handle->txState = kFLEXIO_UART_TxIdle;
}
/*!
* brief Gets the number of bytes sent.
*
* This function gets the number of bytes sent driven by interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param count Number of bytes sent so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
{
assert(handle);
@ -467,6 +625,31 @@ status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_ha
return kStatus_Success;
}
/*!
* brief Receives a buffer of data using the interrupt method.
*
* This function receives data using the interrupt method. This is a non-blocking function,
* which returns without waiting for all data to be received.
* If the RX ring buffer is used and not empty, the data in ring buffer is copied and
* the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
* After copying, if the data in ring buffer is not enough to read, the receive
* request is saved by the UART driver. When new data arrives, the receive request
* is serviced first. When all data is received, the UART driver notifies the upper layer
* through a callback function and passes the status parameter ref kStatus_UART_RxIdle.
* For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer,
* the 5 bytes are copied to xfer->data. This function returns with the
* parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is
* saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer.
* If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
* to receive data to xfer->data. When all data is received, the upper layer is notified.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param xfer UART transfer structure. See #flexio_uart_transfer_t.
* param receivedBytes Bytes received from the ring buffer directly.
* retval kStatus_Success Successfully queue the transfer into the transmit queue.
* retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished.
*/
status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
flexio_uart_handle_t *handle,
flexio_uart_transfer_t *xfer,
@ -503,7 +686,7 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
}
else
{
bytesToReceive = xfer->dataSize;
bytesToReceive = xfer->dataSize;
bytesCurrentReceived = 0U;
/* If RX ring buffer is used. */
@ -542,22 +725,31 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
if (bytesToReceive)
{
/* No data in ring buffer, save the request to UART handle. */
handle->rxData = xfer->data + bytesCurrentReceived;
handle->rxDataSize = bytesToReceive;
handle->rxData = xfer->data + bytesCurrentReceived;
handle->rxDataSize = bytesToReceive;
handle->rxDataSizeAll = bytesToReceive;
handle->rxState = kFLEXIO_UART_RxBusy;
handle->rxState = kFLEXIO_UART_RxBusy;
}
/* Enable FLEXIO_UART RX IRQ if previously enabled. */
FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
/* Call user callback since all data are received. */
if (0 == bytesToReceive)
{
if (handle->callback)
{
handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData);
}
}
}
/* Ring buffer not used. */
else
{
handle->rxData = xfer->data + bytesCurrentReceived;
handle->rxDataSize = bytesToReceive;
handle->rxData = xfer->data + bytesCurrentReceived;
handle->rxDataSize = bytesToReceive;
handle->rxDataSizeAll = bytesToReceive;
handle->rxState = kFLEXIO_UART_RxBusy;
handle->rxState = kFLEXIO_UART_RxBusy;
/* Enable RX interrupt. */
FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
@ -575,6 +767,14 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Aborts the receive data which was using IRQ.
*
* This function aborts the receive data which was using IRQ.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
{
/* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
@ -585,9 +785,20 @@ void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle
}
handle->rxDataSize = 0U;
handle->rxState = kFLEXIO_UART_RxIdle;
handle->rxState = kFLEXIO_UART_RxIdle;
}
/*!
* brief Gets the number of bytes received.
*
* This function gets the number of bytes received driven by interrupt.
*
* param base Pointer to the FLEXIO_UART_Type structure.
* param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
* param count Number of bytes received so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
{
assert(handle);
@ -603,10 +814,18 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart
return kStatus_Success;
}
/*!
* brief FlexIO UART IRQ handler function.
*
* This function processes the FlexIO UART transmit and receives the IRQ request.
*
* param uartType Pointer to the FLEXIO_UART_Type structure.
* param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state.
*/
void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
{
uint8_t count = 1;
FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType;
uint8_t count = 1;
FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType;
flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle;
/* Read the status back. */
@ -662,7 +881,7 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
}
}
/* If ring buffer is still full after callback function, the oldest data is overrided. */
/* If ring buffer is still full after callback function, the oldest data is overridden. */
if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
{
/* Increase handle->rxRingBufferTail to make room for new data. */

50
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_UART_H_
@ -49,8 +23,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO UART driver version 2.1.4. */
#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
/*! @brief FlexIO UART driver version 2.1.5. */
#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/*@}*/
/*! @brief Error codes for the UART driver. */
@ -60,7 +34,7 @@ enum _flexio_uart_status
kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */
kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */
kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */
kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */
kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */
kStatus_FLEXIO_UART_RxRingBufferOverrun =
MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */
kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */
@ -78,15 +52,15 @@ typedef enum _flexio_uart_bit_count_per_char
enum _flexio_uart_interrupt_enable
{
kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */
};
/*! @brief Define FlexIO UART status mask. */
enum _flexio_uart_status_flags
{
kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */
kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */
kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */
kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */
};
/*! @brief Define FlexIO UART access structure typedef. */
@ -202,7 +176,7 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
* @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
*
* @param base Pointer to FLEXIO_UART_Type structure
*/
*/
void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base);
/*!
@ -229,7 +203,7 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig);
*
* @param base Pointer to the FLEXIO_UART_Type structure.
* @return FlexIO UART status flags.
*/
*/
uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
@ -242,7 +216,7 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
* @arg kFLEXIO_UART_TxDataRegEmptyFlag
* @arg kFLEXIO_UART_RxEmptyFlag
* @arg kFLEXIO_UART_RxOverRunFlag
*/
*/
void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask);
@ -344,7 +318,7 @@ static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)
*
* @param base Pointer to the FLEXIO_UART_Type.
* @param enable True to enable, false does not have any effect.
*/
*/
static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)
{
if (enable)

113
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexio_uart_edma.h"
@ -43,7 +17,6 @@
#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma"
#endif
/*<! Structure definition for uart_edma_private_handle_t. The structure is private. */
typedef struct _flexio_uart_edma_private_handle
{
@ -111,7 +84,7 @@ static void FLEXIO_UART_TransferSendEDMACallback(edma_handle_t *handle, void *pa
/* Avoid the warning for unused variables. */
handle = handle;
tcds = tcds;
tcds = tcds;
if (transferDone)
{
@ -136,7 +109,7 @@ static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle,
/* Avoid the warning for unused variables. */
handle = handle;
tcds = tcds;
tcds = tcds;
if (transferDone)
{
@ -151,6 +124,18 @@ static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle,
}
}
/*!
* brief Initializes the UART handle which is used in transactional functions.
*
* param base Pointer to FLEXIO_UART_Type.
* param handle Pointer to flexio_uart_edma_handle_t structure.
* param callback The callback function.
* param userData The parameter of the callback function.
* param rxEdmaHandle User requested DMA handle for RX DMA transfer.
* param txEdmaHandle User requested DMA handle for TX DMA transfer.
* retval kStatus_Success Successfully create the handle.
* retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
*/
status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
flexio_uart_edma_transfer_callback_t callback,
@ -167,7 +152,7 @@ status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
{
if (s_edmaPrivateHandle[index].base == NULL)
{
s_edmaPrivateHandle[index].base = base;
s_edmaPrivateHandle[index].base = base;
s_edmaPrivateHandle[index].handle = handle;
break;
}
@ -204,6 +189,18 @@ status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
return kStatus_Success;
}
/*!
* brief Sends data using eDMA.
*
* This function sends data using eDMA. This is a non-blocking function, which returns
* right away. When all data is sent out, the send callback function is called.
*
* param base Pointer to FLEXIO_UART_Type
* param handle UART handle pointer.
* param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
* retval kStatus_Success if succeed, others failed.
* retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going.
*/
status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
flexio_uart_transfer_t *xfer)
@ -226,7 +223,7 @@ status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
}
else
{
handle->txState = kFLEXIO_UART_TxBusy;
handle->txState = kFLEXIO_UART_TxBusy;
handle->txDataSizeAll = xfer->dataSize;
/* Prepare transfer. */
@ -250,6 +247,18 @@ status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Receives data using eDMA.
*
* This function receives data using eDMA. This is a non-blocking function, which returns
* right away. When all data is received, the receive callback function is called.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
* param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
* retval kStatus_Success if succeed, others failed.
* retval kStatus_UART_RxBusy Previous transfer on going.
*/
status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
flexio_uart_transfer_t *xfer)
@ -272,7 +281,7 @@ status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
}
else
{
handle->rxState = kFLEXIO_UART_RxBusy;
handle->rxState = kFLEXIO_UART_RxBusy;
handle->rxDataSizeAll = xfer->dataSize;
/* Prepare transfer. */
@ -295,6 +304,14 @@ status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
return status;
}
/*!
* brief Aborts the sent data which using eDMA.
*
* This function aborts sent data which using eDMA.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
*/
void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
{
assert(handle->txEdmaHandle);
@ -308,6 +325,14 @@ void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_
handle->txState = kFLEXIO_UART_TxIdle;
}
/*!
* brief Aborts the receive data which using eDMA.
*
* This function aborts the receive data which using eDMA.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
*/
void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
{
assert(handle->rxEdmaHandle);
@ -321,6 +346,17 @@ void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_ed
handle->rxState = kFLEXIO_UART_RxIdle;
}
/*!
* brief Gets the number of bytes received.
*
* This function gets the number of bytes received.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
* param count Number of bytes received so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
flexio_uart_edma_handle_t *handle,
size_t *count)
@ -341,6 +377,17 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
return kStatus_Success;
}
/*!
* brief Gets the number of bytes sent out.
*
* This function gets the number of bytes sent out.
*
* param base Pointer to FLEXIO_UART_Type
* param handle Pointer to flexio_uart_edma_handle_t structure
* param count Number of bytes sent so far by the non-blocking transaction.
* retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
* retval kStatus_Success Successfully return the count.
*/
status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)
{
assert(handle);

32
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_UART_EDMA_H_
#define _FSL_FLEXIO_UART_EDMA_H_
@ -62,8 +36,8 @@ typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base,
void *userData);
/*!
* @brief UART eDMA handle
*/
* @brief UART eDMA handle
*/
struct _flexio_uart_edma_handle
{
flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */

115
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.c
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexram.h"
@ -60,18 +34,9 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
*
* @param tcmBankNum tcm banknumber
* @retval register value correspond to the tcm size
*/
*/
static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum);
/*!
* @brief FLEXRAM configure TCM size
* This function is used to set the TCM to the actual size.When access to the TCM memory boundary ,hardfault will
* raised by core.
* @param itcmBankNum itcm bank number to allocate
* @param dtcmBankNum dtcm bank number to allocate
*/
static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
/*******************************************************************************
* Variables
******************************************************************************/
@ -104,6 +69,11 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
return instance;
}
/*!
* brief FLEXRAM module initialization function.
*
* param base FLEXRAM base address.
*/
void FLEXRAM_Init(FLEXRAM_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -119,6 +89,10 @@ void FLEXRAM_Init(FLEXRAM_Type *base)
base->INT_SIG_EN = 0U;
}
/*!
* brief Deinitializes the FLEXRAM.
*
*/
void FLEXRAN_Deinit(FLEXRAM_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -130,38 +104,40 @@ void FLEXRAN_Deinit(FLEXRAM_Type *base)
static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum)
{
uint8_t tcmSizeConfig = 0U;
uint32_t totalTcmSize = 0U;
switch (tcmBankNum * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE)
/* if bank number is a odd value, use a new bank number which bigger than target */
do
{
case kFLEXRAM_TCMSize32KB:
tcmSizeConfig = 6U;
if ((tcmBankNum & (tcmBankNum - 1U)) == 0U)
{
break;
}
} while (++tcmBankNum < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
case kFLEXRAM_TCMSize64KB:
tcmSizeConfig = 7U;
break;
case kFLEXRAM_TCMSize128KB:
tcmSizeConfig = 8U;
break;
case kFLEXRAM_TCMSize256KB:
tcmSizeConfig = 9U;
break;
case kFLEXRAM_TCMSize512KB:
tcmSizeConfig = 10U;
break;
default:
totalTcmSize = tcmBankNum * (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE >> 10U);
/* get bit '1' position */
while (totalTcmSize)
{
if ((totalTcmSize & 1U) == 0U)
{
tcmSizeConfig++;
}
else
{
break;
}
totalTcmSize >>= 1U;
}
return tcmSizeConfig;
return tcmSizeConfig + 1U;
}
static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
{
assert(itcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
assert(dtcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
/* dtcm configuration */
if (dtcmBankNum != 0U)
{
@ -173,6 +149,7 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
{
IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
}
/* itcm configuration */
if (itcmBankNum != 0U)
{
@ -184,21 +161,27 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
{
IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
}
return kStatus_Success;
}
/*!
* brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
* This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
* is needed.
* param config allocate configuration.
* retval kStatus_InvalidArgument the argument is invalid
* kStatus_Success allocate success
*/
status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
{
uint8_t dtcmBankNum = config->dtcmBankNum;
uint8_t itcmBankNum = config->itcmBankNum;
assert(config != NULL);
uint8_t dtcmBankNum = config->dtcmBankNum;
uint8_t itcmBankNum = config->itcmBankNum;
uint8_t ocramBankNum = config->ocramBankNum;
uint32_t bankCfg = 0U, i = 0U;
/* check the arguments */
if ((FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) ||
((dtcmBankNum != 0U) && ((dtcmBankNum & (dtcmBankNum - 1u)) != 0U)) ||
((itcmBankNum != 0U) && ((itcmBankNum & (itcmBankNum - 1u)) != 0U)))
if (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum))
{
return kStatus_InvalidArgument;
}

131
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXRAM_H_
@ -48,37 +22,35 @@
/*! @name Driver version */
/*@{*/
/*! @brief Driver version 2.0.2. */
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U))
/*! @brief Driver version 2.0.4. */
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U))
/*@}*/
/*! @brief flexram write read sel */
enum _flexram_wr_rd_sel
{
kFLEXRAM_Read = 0U, /*!< read */
kFLEXRAM_Read = 0U, /*!< read */
kFLEXRAM_Write = 1U, /*!< write */
};
/*! @brief Interrupt status flag mask */
enum _flexram_interrupt_status
{
kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */
kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */
kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */
kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< ocram maigc address match */
kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< dtcm maigc address match */
kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< itcm maigc address match */
kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */
kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */
kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */
kFLEXRAM_InterruptStatusAll = 0x3FU, /*!< all the interrupt status mask */
kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */
};
/*! @brief FLEXRAM TCM access mode
* Fast access mode expected to be finished in 1-cycle
* Wait access mode expected to be finished in 2-cycle
* Wait access mode is a feature of the flexram and it should be used when
* the cpu clock too fast to finish tcm access in 1-cycle.
* Normally, fast mode is the default mode, the efficiency of the tcm access will better.
*/
* Fast access mode expected to be finished in 1-cycle
* Wait access mode expected to be finished in 2-cycle
* Wait access mode is a feature of the flexram and it should be used when
* the cpu clock too fast to finish tcm access in 1-cycle.
* Normally, fast mode is the default mode, the efficiency of the tcm access will better.
*/
typedef enum _flexram_tcm_access_mode
{
kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */
@ -89,16 +61,16 @@ typedef enum _flexram_tcm_access_mode
enum _flexram_bank_type
{
kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */
kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */
kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */
kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */
kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */
kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */
kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */
};
/*! @brief FLEXRAM tcm support size */
enum _flexram_tcm_size
{
kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */
kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */
kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */
kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */
kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size 128KB */
kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size 256KB */
kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size 512KB */
@ -108,7 +80,7 @@ enum _flexram_tcm_size
typedef enum _flexram_bank_allocate_src
{
kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */
kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */
kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */
} flexram_bank_allocate_src_t;
/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */
@ -118,6 +90,15 @@ typedef struct _flexram_allocate_ram
const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */
const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */
} flexram_allocate_ram_t;
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
@ -262,42 +243,6 @@ static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable
}
}
/*!
* @brief FLEXRAM OCRAM magic addr configuration
* When read/write access hit magic address, it will generate interrupt
* @param magicAddr magic address.
* @param rwsel read write select, 0 read access , 1 write access
*/
static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
base->OCRAM_MAGIC_ADDR =
FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(magicAddr >> 3U);
}
/*!
* @brief FLEXRAM DTCM magic addr configuration
* When read/write access hit magic address, it will generate interrupt
* @param magicAddr magic address.
* @param rwsel read write select, 0 read access , 1 write access
*/
static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
base->DTCM_MAGIC_ADDR =
FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(magicAddr >> 3U);
}
/*!
* @brief FLEXRAM ITCM magic addr configuration
* When read/write access hit magic address, it will generate interrupt
* @param magicAddr magic address.
* @param rwsel read write select, 0 read access , 1 write access
*/
static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
{
base->ITCM_MAGIC_ADDR =
FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(magicAddr >> 3U);
}
/*!
* @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
* This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
@ -318,6 +263,22 @@ static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src)
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src);
}
/*!
* @brief FLEXRAM configure TCM size
* This function is used to set the TCM to the target size. If a odd bank number is used,
* a new banknumber will be used which is bigger than target value, application can set tcm
* size to the biggest bank number always, then boundary access error can be captured by flexram only.
* When access to the TCM memory boundary ,hardfault will raised by core.
* @param itcmBankNum itcm bank number to allocate
* @param dtcmBankNum dtcm bank number to allocate
*
*/
void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif

725
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c
View File

File diff suppressed because it is too large Load Diff

220
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h
View File

@ -1,35 +1,9 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2019 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_FLEXSPI_H_
@ -50,21 +24,21 @@
/*! @name Driver version */
/*@{*/
/*! @brief FLEXSPI driver version 2.0.2. */
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*! @brief FLEXSPI driver version 2.1.3. */
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
/*@}*/
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
/*! @breif Formula to form FLEXSPI instructions in LUT table. */
/*! @brief Formula to form FLEXSPI instructions in LUT table. */
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
/*! @brief Status structure of FLEXSPI.*/
enum _flexspi_status
enum
{
kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */
kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */
kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout
error occurred during FLEXSPI transfer. */
kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution
@ -76,33 +50,33 @@ enum _flexspi_status
/*! @brief CMD definition of FLEXSPI, use to form LUT instruction. */
enum _flexspi_command
{
kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */
kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */
kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
dummy cycles decided by RWDS. */
kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
dummy cycles decided by RWDS. */
kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the
@ -110,19 +84,23 @@ enum _flexspi_command
};
/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */
enum _flexspi_pad
typedef enum _flexspi_pad
{
kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */
kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */
kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */
kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */
};
} flexspi_pad_t;
/*! @brief FLEXSPI interrupt status flags.*/
typedef enum _flexspi_flags
{
kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */
kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */
#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN
kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */
#else
kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */
#endif
kFLEXSPI_SckStoppedBecauseTxEmptyFlag =
FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command
sequence because Async TX FIFO empty. */
@ -132,7 +110,7 @@ typedef enum _flexspi_flags
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */
#endif
kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */
kFLEXSPI_IpTxFifoWatermarkEmptyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */
kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */
kFLEXSPI_AhbCommandSequenceErrorFlag =
FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */
@ -141,7 +119,7 @@ typedef enum _flexspi_flags
FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */
kFLEXSPI_IpCommandGrantTimeoutFlag =
FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */
kFLEXSPI_IpCommandExcutionDoneFlag =
kFLEXSPI_IpCommandExecutionDoneFlag =
FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */
kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */
} flexspi_flags_t;
@ -153,36 +131,36 @@ typedef enum _flexspi_read_sample_clock
and loopback internally. */
kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller
and loopback from DQS pad. */
kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */
kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */
kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */
} flexspi_read_sample_clock_t;
/*! @brief FLEXSPI interval unit for flash device select.*/
typedef enum _flexspi_cs_interval_cycle_unit
{
kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */
} flexspi_cs_interval_cycle_unit_t;
/*! @brief FLEXSPI AHB wait interval unit for writting.*/
/*! @brief FLEXSPI AHB wait interval unit for writing.*/
typedef enum _flexspi_ahb_write_wait_unit
{
kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */
kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */
} flexspi_ahb_write_wait_unit_t;
/*! @brief Error Code when IP command Error detected.*/
typedef enum _flexspi_ip_error_code
{
kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */
kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */
kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */
kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */
kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR
used in DDR sequence. */
kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
@ -190,16 +168,16 @@ typedef enum _flexspi_ip_error_code
kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole
flash address range (A1/A2/B1/B2). */
kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */
kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */
kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */
} flexspi_ip_error_code_t;
/*! @brief Error Code when AHB command Error detected.*/
typedef enum _flexspi_ahb_error_code
{
kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */
kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */
kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction
used in the sequence. */
kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used
in DDR sequence. */
kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
@ -211,17 +189,18 @@ typedef enum _flexspi_ahb_error_code
typedef enum _flexspi_port
{
kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
kFLEXSPI_PortA2 = 0x1U, /*!< Access flash on A2 port. */
kFLEXSPI_PortB1 = 0x2U, /*!< Access flash on B1 port. */
kFLEXSPI_PortB2 = 0x3U, /*!< Access flash on B2 port. */
kFLEXSPI_PortA2, /*!< Access flash on A2 port. */
kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
kFLEXSPI_PortCount
} flexspi_port_t;
/*! @brief Trigger source of current command sequence granted by arbitrator.*/
typedef enum _flexspi_arb_command_source
{
kFLEXSPI_AhbReadCommand = 0x0U,
kFLEXSPI_AhbWriteCommand = 0x1U,
kFLEXSPI_IpCommand = 0x2U,
kFLEXSPI_AhbReadCommand = 0x0U,
kFLEXSPI_AhbWriteCommand = 0x1U,
kFLEXSPI_IpCommand = 0x2U,
kFLEXSPI_SuspendedCommand = 0x3U,
} flexspi_arb_command_source_t;
@ -239,7 +218,7 @@ typedef struct _flexspi_ahbBuffer_config
uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */
uint16_t bufferSize; /*!< AHB buffer size in byte. */
bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows
prefetch disable/enable seperately for each master. */
prefetch disable/enable separately for each master. */
} flexspi_ahbBuffer_config_t;
/*! @brief FLEXSPI configuration structure. */
@ -264,8 +243,12 @@ typedef struct _flexspi_config
uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */
struct
{
bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */
bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */
#endif
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */
#endif
uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant,
timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */
uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access,
@ -276,11 +259,11 @@ typedef struct _flexspi_config
bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer
when FLEXSPI returns STOP mode ACK. */
bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation.
when eanble, there is no AHB read burst start address alignment limitation. */
when enable, there is no AHB read burst start address alignment limitation. */
bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI
will fetch more data than current AHB burst. */
bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled,
FLEXSPI return before waiting for command excution finished. */
FLEXSPI return before waiting for command execution finished. */
bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */
} ahbConfig;
} flexspi_config_t;
@ -292,7 +275,7 @@ typedef struct _flexspi_device_config
bool isSck2Enabled; /*!< FLEXSPI use SCK2. */
uint32_t flashSize; /*!< Flash size in KByte. */
flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */
uint16_t CSInterval; /*!< CS line assert interval, mutiply CS interval unit to
uint16_t CSInterval; /*!< CS line assert interval, multiply CS interval unit to
get the CS line assert interval cycles. */
uint8_t CSHoldTime; /*!< CS line hold time. */
uint8_t CSSetupTime; /*!< CS line setup time. */
@ -304,7 +287,7 @@ typedef struct _flexspi_device_config
uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */
uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */
flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */
uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, mutiply AHB write interval
uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, multiply AHB write interval
unit to get the AHB write wait cycles. */
bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask
when writing to external device. */
@ -404,7 +387,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
{
base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
{
}
}
@ -552,11 +535,11 @@ static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFi
*/
static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
{
if (txCount)
if (NULL != txCount)
{
*txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
}
if (rxCount)
if (NULL != rxCount)
{
*rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
}
@ -618,7 +601,8 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
*/
static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
{
return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT);
return (flexspi_arb_command_source_t)(
(uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT));
}
/*! @brief Gets the error code when IP command error detected.
@ -629,8 +613,9 @@ static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FL
*/
static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
{
*index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT;
return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT);
*index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT);
return (flexspi_ip_error_code_t)(
(uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT));
}
/*! @brief Gets the error code when AHB command error detected.
@ -641,9 +626,9 @@ static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type
*/
static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
{
*index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >>
FLEXSPI_STS1_AHBCMDERRCODE_SHIFT);
*index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
return (flexspi_ahb_error_code_t)(
(uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT));
}
/*! @brief Returns whether the bus is idle.
@ -654,7 +639,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty
*/
static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
{
return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK);
return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
}
/*@}*/
@ -663,6 +648,13 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
* @{
*/
/*! @brief Update read sample clock source
*
* @param base FLEXSPI peripheral base address.
* @param clockSource clockSource of type #flexspi_read_sample_clock_t
*/
void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
/*! @brief Enables/disables the FLEXSPI IP command parallel mode.
*
* @param base FLEXSPI peripheral base address.
@ -698,14 +690,14 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
}
/*! @brief Updates the LUT table.
*
* @param base FLEXSPI peripheral base address.
* @param index From which index start to update. It could be any index of the LUT table, which
* also allows user to update command content inside a command. Each command consists of up to
* 8 instructions and occupy 4*32-bit memory.
* @param cmd Command sequence array.
* @param count Number of sequences.
*/
*
* @param base FLEXSPI peripheral base address.
* @param index From which index start to update. It could be any index of the LUT table, which
* also allows user to update command content inside a command. Each command consists of up to
* 8 instructions and occupy 4*32-bit memory.
* @param cmd Command sequence array.
* @param count Number of sequences.
*/
void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
/*!
@ -740,7 +732,7 @@ static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
* @param size The number of data bytes to send
* @retval kStatus_Success write success without error
* @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
* @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
* @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
* @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
@ -764,9 +756,9 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
* @param xfer pointer to the transfer structure.
* @retval kStatus_Success command transfer success without error
* @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
* @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
* @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
* @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
*/
status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
/*! @} */
@ -794,7 +786,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
* @note Calling the API returns immediately after transfer initiates. The user needs
* to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
* the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
* is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or
* is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
* FLEXSPI could not read data properly.
*
* @param base FLEXSPI peripheral base address.

33
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c
View File

@ -1,38 +1,17 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexspi_nor_boot.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.ivt")))

40
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h
View File

@ -1,34 +1,8 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FLEXSPI_NOR_BOOT_H__
@ -37,8 +11,14 @@
#include <stdint.h>
#include "device.h"
/*************************************
* IVT Data
/*! @name Driver version */
/*@{*/
/*! @brief XIP_DEVICE driver version 2.0.0. */
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*************************************
* IVT Data
*************************************/
typedef struct _ivt_ {
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
@ -76,7 +56,7 @@ typedef struct _ivt_ {
((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
(((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
/* IVT header */
/* IVT header */
#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */
#define IVT_SIZE 0x2000
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)

54
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c
View File

@ -1,36 +1,10 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016 NXP
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_gpc.h"
@ -40,10 +14,15 @@
#define FSL_COMPONENT_ID "platform.drivers.gpc_1"
#endif
/*!
* brief Enable the IRQ.
*
* param base GPC peripheral base address.
* param irqId ID number of IRQ to be enabled, available range is 32-159.
*/
void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
{
uint32_t irqRegNum = irqId / 32U;
uint32_t irqRegNum = irqId / 32U;
uint32_t irqRegShiftNum = irqId % 32U;
assert(irqRegNum > 0U);
@ -63,9 +42,15 @@ void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
}
/*!
* brief Disable the IRQ.
*
* param base GPC peripheral base address.
* param irqId ID number of IRQ to be disabled, available range is 32-159.
*/
void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
{
uint32_t irqRegNum = irqId / 32U;
uint32_t irqRegNum = irqId / 32U;
uint32_t irqRegShiftNum = irqId % 32U;
assert(irqRegNum > 0U);
@ -85,9 +70,16 @@ void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
}
/*!
* brief Get the IRQ/Event flag.
*
* param base GPC peripheral base address.
* param irqId ID number of IRQ to be enabled, available range is 32-159.
* return Indicated IRQ/Event is asserted or not.
*/
bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
{
uint32_t irqRegNum = irqId / 32U;
uint32_t irqRegNum = irqId / 32U;
uint32_t irqRegShiftNum = irqId % 32U;
uint32_t ret;

Some files were not shown because too many files have changed in this diff Show More