According to their cmsis.h, FPU is present, so change targets.json to
use it.
* ARM_MPS2_M4: already was Cortex-M4F
* ARM_MPS2_M7: Cortex-M7 -> M7FD
* FVP_MPS2_M4: Cortex-M4 -> M4F
* FVP_MPS2_M7: Cortex-M7 -> M7FD
If they do not in fact have FPU, then cmsis.h should be modified to set
`__FPU_PRESENT` to 0. This will currently cause compilation problems
with ARMC6, but I'll be submitting a fix for that.
On NUC472, on wake-up from power-down mode, we may meet hard fault or some other
unknown error. Before its cause is found, we enter idle mode instead for a workaround.
To simulate power-down mode with idle mode, we also disable us_ticker during
power-down period.
PDL Flash API requires that the data buffer is 32-bit aligned, otherwise
programming can hung. Buffer declared as uint8_t array is not always
properly aligned, e.g. with gcc 6 when -Os option is used.
Flash driver 3.30:
Moved ipcWaitMessageStc structure to the RAM section called ".cy_sharedmem"
Added support Secure Boot devices
Moved CY_FLASH_EFFECTIVE_PAGE_SIZE to flash_api.c (the macro is Mbed specific).
GeneratedSource folders are BSP specific. No parts of the kit BSP can be reused
as generic chip support package. Remove TARGET_CY8C62XX directory,
and use flat BSP inheritance model:
MCU_PSOC6 -> MCU_PSOC6_M4 -> CY8CKIT_062_WIFI_BT
MCU_PSOC6 -> MCU_PSOC6_M0 -> CY8CKIT_062_WIFI_BT_M0
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN382(ARM_MPS2_M0). Add "IAR" to supported_toolchain list.
Change-Id: I2b2ad7645166c4f973a8baa9c394521514183767
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN383(ARM_MPS2_M0P). Add "IAR" to supported_toolchain list.
Change-Id: Ib2278d34e265e53ad070aecd318ed4e6a355e3c0
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN382(ARM_MPS2_M0). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I7046b698834c82e94015e51eef9a0f5e1315ddaa
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN383(ARM_MPS2_M0P). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I48020b4f0f1b6e0aef3c53f5a3586bc9e9fca9c9
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN385(ARM_MPS2_M3). Add "IAR" to supported_toolchain list.
Change-Id: I038b05b8b21bd146a1568de897ed030ccd52ab79
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN386(ARM_MPS2_M4). Add "IAR" to supported_toolchain list.
Change-Id: I4f43617c870197b9d39a4d4c9c12456adcc6f96f
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN500(ARM_MPS2_M7). Add "IAR" to supported_toolchain list.
Change-Id: I0b8f018fc937727382b27ea0669940ae6675c834
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN385(ARM_MPS2_M3). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I3110d4ab37a3294488a80a8dc1c929bfd87ce989
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN386(ARM_MPS2_M4). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ib8cea952e1ce0a5ef11ab623cca6f3786eab56f5
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN500(ARM_MPS2_M7). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ife109e9e1f2ec8e075e566f9d5c2ec7e3c5067f2
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
These file changes provide small fixes for various targets
on MPS2 platform in order to work properly and pass all
Greentea test cases. The __initial_sp has been explicitly set
in the targets' startup files, and also INITIAL_SP has been
given a different value. The values have been extracted from
the specific targets' Application Note documentation.
Affected targets are: ARM_MPS2_M0, ARM_MPS2_M0P, ARM_MPS2_M3,
ARM_MPS2_M4 and ARM_MPS2_M7.
Change-Id: I3d5d0e1ae386cdcc3ba5eb63be929267a257b139
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
Spotted in compiler warnings - code was trying to access a non-existent
second security control block, rather than access the settings for the
second APB bridge in the first and only security control block.
The hal code for this target uses "const volatile" types inside of
structs, which are non-trivially copyable in clang (used by ARMC6). This
causes the build to fail.
Here's the commit that changed this in clang:
a3d727ba77
It seems this was reverteed some time ago in clang, but ARMC6 may not
be up to date.
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:
1. Fixed size and small sections moved to SRAM2 (32K)
Vectors
Crash data
Remaining section - RW / ZI
2. Large memory space should be used for variable sections
RW/ZI
Heap - (Minimum - 0x12000)
Stack - At bottom
Please note the heap address of the both the banks must not be contigious else
GCC considers it to be single memory bank and does allocation across the banks,
which might result into hard-fault
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:
1. Fixed size and small sections moved to SRAM2 (32K)
Vectors
Crash data
Stack
Remaining section - Heap memory
2. Large memory space should be used for variable sections
Data
BSS
Heap - Remaining section
Heap is moved to the end of both sections as GCC allocates till 4K boundary,
if end of heap is not aligned to 4K, that chunk of memory will go unutilized
Fixes test failure seen with tests-mbed_hal-stack_size_unification
under IAR and ARM toolchain
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This change moves all PDL drivers into common source and include
directories to alleviate issue with Windows version of GNU Make 4.x
maximum command line length limit.
New `target.console-uart` option added to indicate whether a target has
a console UART on STDIO_UART_TX/RX/RTS/CTS pins. (The existing option
`target.console-uart-flow-control` indicates whether RTS and or CTS is
available in addition to TX and RX).
The option defaults to true, and is currently true on all platforms. It
only applies if DEVICE_SERIAL is true, so no need to go through and mark
it false for non-SERIAL platforms.
An application can turn off target.console-uart to save ROM/power/etc if
they don't want to use the serial console. If this is turned off, the
console won't be activated for stdin/stdout, but the application is
still free to open `UARTSerial(STDIO_UART_TX, STDIO_UART_RX)`
themselves.
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
Fixed interrupt vector settings on M0 core. Wrong vector settings prevented
LP_TICKER from working, resulting in deep sleep tests failing on M0
or PSA variant.
Martin Kojtal
Kevin Bracey
ccli8
Leszek Rusinowicz
Lei Zhang
Hennadiy Kytsun
Shawn Shan
Deepika
j3hill
jeromecoutant
Shrikant Tudavekar
Brian Daniels
Cruz Monrreal
Marcus Chang
Mahesh Mahadevan
Qinghao Shi
Vincent Veron
Kari Haapalehto
Ganesh Ramachandran
Ashok Rao