In case of off-line compiler, there is no problem about the frequency setting processing.
But in case of online compiler, the frequency setting processing will be error.
So, modify frequency setting processing of SPI to pass in online compiler.
Issue originally reported on mbed site here:
https://developer.mbed.org/questions/5695/FRDM-KL05z-hardfault-when-compiled-with-/
The RAM base address was incorrectly set to the beginning of RAM
instead of at a 0xC0 byte offset to reserve room for the interrupt
vectors. Without this fix, the global variables and the interrupt
vectors were occupying the same space in RAM once the user enabled the
timer interrupt.
The user who originally reported the issue on the mbed site has tested
this fix and verified that it corrected the hard fault issue that they
were encountering.
- Change default setting of CMSIS-RTOS RTX for Cortex-A9 to align with Cortex-M.
- Change the interrupt priority of Ether driver to align with other drivers.
Changes as below.
-I2C
Change communication wait time and Frequency accuracy improvement of I2C.
- Frequency accuracy improvement
- Changed the wait time between one communication completed and the next communication start.
The wait time will be Low clock width by this changing.
-PWM
Modify processing of pulsewidth() of PWM
- Modify processing of pulsewidth() to match the specifications of the RZ_A1H.
-SPI
Fixed a bug that SPI driver is not able to communicate when transfer bit length is 16bit or 32bit.
- Frequency accuracy improvement
- Modify transfer processing when transfer bit length is 16bit or 32bit.
-Serial
Change the reference register macro of Serial
- Change the reference register macro to align with other driver codes.
Changing original STM Cube Driver to call _start instead of main to
initialise the rtos when using it. Without using rtos the behavior is
the same as before.
Original STM32Cube F4 driver sets SYSCLK for STM32F429 to 16MHz. This
adds a 168MHz and 180MHz configuration to system_stm32f4xx.c generated
by STM32CubeMX code generator. The rtos clock configuration is changed
too. In singletest.py run everything is OK.
- Changing original STM Cube Driver to call _start instead of main to
initialise the rtos when using it. Without using rtos the behavior is
the same as before.
- Adding DISCO_F429 to rtos
- Adding targets to RTOS_xx tests.
- All tests are OK. Tested with Nucleo and Disco boards. Not tested with
MDOT_F4 but that uses the same hal like nucleo_f411.
Fix a bug as below.
- Period can not be changed.
Restructions: 1. The upper limits is 491us
2. Change all period of the same channel when changing period.
Fix some bugs of Serial as below.
- TX/RX terminal of XBee(P7_4, P7_5) setting is reverse.
- P5_6 and P5_7 terminals can not be used.
- Tx interrupt will not occur at the right timing.
- There are no settings of WIFI Module terminals(P11_10,P11_11).
- There are no settings of Xbee Module terminals(P6_6,P6_7).
Timer value wraparound operation had not been considered in common wait process.
By defining the EXPIRE_US non-zero value, wraparound operation is enabled.
The EXPIRE_US will be define the value of each vender-specific.
If EXPIRE_US is 0, the common wait process is same as before.
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Fix IAR serial fgets fgetc
Taken from PR #770:
setbuf(_file, NULL), and std::setvbuf(_file,NULL,_IONBF,NULL) should both give an unbuffered stream (the data is directly written to the input buffer). IAR sets a buffer anyway of size 512 bytes for these calls. Calling setvbuff(_file,buf,_IONBF,NULL) with a buffer that is not a NULL pointer sets the buffer to size one. Which means that as soon as a char is read it is written to the real buffer. If people are interested in looking at this further they can look at the files under ARM/src/dlib: fgets.c, fflush.c, xfrpep.c and xfwprep.c
Three changes, first it fixes:
https://github.com/mbedmicro/mbed/issues/761 (which was reported
slightly wrong because K20 has again different clocking from KLXX for
uarts).
Second it adds mcgpllfll to clk_freqs, which again is different for K20
compared to KLXX .
Finally it adds the fractional baudrate divider for more accurate serial
baudrates.
Change I2C driver transfer sequence to go according to H/W manual.
Changed contents are as below.
- Access procedure of ACTBT bit of MR3 register
- Issuance procedure of stop condition
When read the timer value, it have a potential to read abnormal value.
Because we used 16bit + 16bit cascade timer and read timer count separately.
Changed usticker timer from 16bit + 16bit cascade timer to 32bit timer to fix the bug.
Updates startup files to actual versions of STM32 Cube drivers without
any changes of STs drivers:
- DISCO_F303VC
- DISCO_F334
- NUCLEO_F030
- NUCLEO_F072
- NUCLEO_F302
- NUCLEO_F334
- CoIDE options: wrap main and linker option DiscradUnusedSection=1 was
missing in some targets
- CoIDE options: corrected flash loader config for Nucleo_F030 and
Nucleo_F072
- CoIDE options: corrected memory layout (not used per default but now
it is the same as in linker script)
- gcc linker script: changed the memory size from hex number e.g. 0x2000
to decimal 8K
The bugs of IRQ Edge Interrupt as below.
- Not call a function that was registered in rise, always call a function that was registered in the fall.
- If there are multiple interrupt sources, there is a possibility that end the wrong interrupt processing.
- Fix a bug reported here:
https://developer.mbed.org/questions/4872/SPISlave-Class-dosnt-work-on-LPC1114/
- Add IOCON settings to enable proper pin functions
- Remove non-busy check in slave_receive() function, since the SSP/SPI
is always in busy state when received a valid data according to the
device user manual
- Add bit mask in spi_slave_read() function
- Add TARGET_LPC1114 pin config in SPI_SLAVE test
- Tested with LPC11U24 SPI master and LPC1114 SPI slave
GR-PEACH does not have any device that connected external address area of RZ_A1H.
The External Bus Controller settings are needless at GR-PEACH.
Terminals settings will be input mode(It is default setting).
When making I2C communication freq, we used a fix value 33.3MHz as peripheral clock as below.
pclk = 33333333 / (2 << count);
But it is not dynamic when system clock is changed.
So, implement peripheral clock determination process.
Peripheral clock will be decided by RZ-A1H system clock mode.
albert361
Masao Hamanaka
Martin Kojtal
Toyomasa Watarai
Adam Green
ohagendorf
bcostm
Przemek Wirkus
Martin Olejar
mazgch
Yihui Xiong
Mike Fiore
Rohit Grover
vincent rabbit
Richard Osterloh
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Nick DeLisi
Sissors
Michael Brudevold
dinau
modtronix-com
Bogdan Marinescu