Datasheet (Table 82) says MSEL bits should be 5, and the PSEL bits should
be 1, for the correct FCCO frequency of 288MHz. The current configuration
has FCCO = 144MHz, which is technically out of spec.
Tested on a custom LPC1549 board with crystal oscillator running at 12MHz.
Modified the LPC1549 AnalogIn implementation to use the ADCs in
synchronous mode, which is consistent with the LPC11U68 implementation.
This improves performance, and allows the IRC oscillator to be powered
down if necessary.
Use only the index, not the UARTName any more.
In case of app with 2 serial (using DMA) + 1 serial (stdio), we have found a bug. The dma handler is overwritten by the last initialized serial object.
Therefore read and write functions did not work anymore.
We have reworked this file to save 1 handler per UART IP, and align it with MBED OS file.
Tests have been passed. Same status as before (OK except MBED_37, manual test for SERIAL_ASYNC also OK).
We modified the following to support the export function to the IAR.
- In tools files, add RZ_A1H to the target of IAR.
- In tools files, add the tmpl files.
Can contains 2 fifos. Both generates its own interrupt.
IRQ_RX occurs when a message has arrived in FIFO-0 , FIFO-0 is full or
overrun.
IRQ_RX1 occurs when a message has arrived in FIFO-1 , FIFO-1 is full or
overrun.
Flush errors and current data register at reading start
Allow separate serial obj for TX and RX (= do not initialize [TX/RX]_DMA
when not needed.
Char_match: make it work with long buffers and return the correct
position of the char_match.
* Allow pins to be configured as NC without failing or asserting
* Fix putc() to not return before the entire character has been physically shifted out.
* Use MBED_ASSERT
* Fix baudrate calculation to avoid wrong configuration on startup for stdio
* Setting the PWM period now correctly updates all other channels to keep their duty cycle
* No longer keep values in RAM that can be read directly from a register
* Setting the PWM duty cycle to 100% no longer makes the signal glitch on every period
* Code condensation
* Added PD9 back in (for some reason it was at some point removed from the pinmap, not sure why because it is a usable pin when you remove the on-board sensor or use the Pearl chip standalone)
* Fixed PWM locations to match the pin-CC channel combinations.
Allows clocking the device from RC oscillators (HFRCO, LFRCO).
Note that we can not use the em_cmu.h enums directly as the
preprocessor can not do comparisons on them.
Related changes in serial_api, so that LEUART clock is within
acceptable limits on Pearl.
Contains quite a bit of indentation changes to make the preprocessor
logic more readable so recommend viewing the diff in ignore whitespace
mode.
Keep a counter of sleeps blocked for every device, and do not try
to unblock sleep modes we did not block. This fixes problems where
serial events would cause EM1/EM2 to be unblocked too early,
causing the MCU to go to EM3 and not being able to wake up.
When initializing for use with the board controller, the LEUART must
be clocked from HF clock as the baud rate is otherwise too high.
Do this by first initializing to "standard" 9600, then call serial_baud
which will handle setting up the clocks and dividers.
Switch caused a phantom 0xFF frame to appear on the line when we switched
from LEUART to USART due to a baud rate was increase. This was short
enough that it was only visible at high (~115kbps) speeds.
As a fix, skip disabling the GPIO pins (as their configuration does not
change), and defer disabling the LEUART routing until at the very last
moment. Additionally, do not call serial_format, but immediately
initialize the UART to correct params.
- Do not attempt to disable the transmitter. Did not find a robust
way to do so - see comment in file for more info.
- Do not unblock sleep when abort is called externally, this leads
to jams as EM1 block gets disabled and the next sleep call places
the hardware to directly to EM3.
- Retain more status when switching over from LEUART to USART in
Pearl: keep registered IRQ handlers and other IRQ status.
Changed SPI implementation: #1 To avoid clearing data from buffers, during splitted DMA transfer
RX/TX buffer clear is done only when transfer is started.
USART transmit is completed instead of DMA/LDMA transfer completed.
When doing a large transfer over the LDMA it is required to wait TX to be completed
before transferring the next part of the data. Added a loop, to wait until TXC flag is set in function USART_STATUS_TXC.
+ minor code cleanup and EM1 sleep is allowed again.
Second, the TX interrupt was not cleared after processing, causing
it to stay in an infinite loop.
Conditional when dispatching LEUART irq would always select the RX
side due to a bitwise AND being typoed as a logical AND.
Second, the TX interrupt was not cleared after processing, causing
it to stay in an infinite loop.
Previously, all pins in an mbed Port were set to the same value.
Use GPIO_PortOutSetVal to directly write the desired value to
the pins.
During port initialization the pin mode for input pins was set incorrectly.
Now, input pins are directly set to Input (gpioModeInput) and output pins to
PushPull (gpioModePushPull).
GPIO_IntEnable/Disable was called with incorrect params due
to missing parens. Operator precedence of & vs << caused the
call to be blank if the port (MSB) nibble of pin was not zero.
spi_buffer_tx_write fixed to work correctly with 9-16 bit frames,
if transfer length > 1. If frame is 9-16 bit client can use uint16_t or
uint32_t buffer for data storage, spi_api's default is to use uint16_t.
Added precompiler condition USE_UINT16_BUFFER to change assumption for
DMA and IRQ -transfers.
LDMA descriptor fixed to support 9-16 bit long frames. Prevented
sleepstate EM1, because USART requires EM0, and entering to EM1
during transfer can crash the system.
Previous comment on issuing a TXDIS command was incorrect. Actual
root cause was a non-DMA RX interrupt causing the code to run the
TXC handling code as long as the TX DMA interrupt had fired,
which was too early.
Reenable usage of TXDIS on Pearl.
Pearl STK is offically known as SLSTK3401A, but we well go
with the same naming convention as with Happy so Pearl's
name in Mbed will be STK3401.
Renames all files and directories that previously had the
placeholder STKXXXX. Build, target and export scripts
modified accordingly.
Serial HAL now allocates the LEUART first, and will switch
to using a standard UART only if the parameters require it.
Note that this switch can currently only happen one way, from
LEUART to USART. So once a higher baudrate or invalid frame
bit amount has been used, that instance of Serial object
will be locked to using an USART.
TODO: Parts of the UART (re)initialization code are now spread
between three places. They should be combined into single,
generic function.
Part of condition to detect active TX was not only incorrect
but also not needed in the first place. TX active state is
now always detected only via active TXBL/TXC interrupt.
UARTs are no longer fixed to certain pins on Pearl, so
we need to allocate them as needed, and allow for free
pin selection.
TX and RX pin locations in the main serial struct have been
separated, and pin routing modified accordingly.
serial_api_HAL.h interface keeps track of which UARTS are
currently in use, and provides alloc/free functions. Serial
and SPI components modified to use the new API.
TODO: Magic to support LEUART. This code will also need to
be able to dynamically switch from LEUART to standard USART
if the user later sets params (baud rate or format) that can
not be supported on LEUART.
Issuing a CLEARTX to LEUART command together or after TXEN caused
the DMA transfer to jam or cause repeated interrupts.
Also cleanup duplicated interrupt clears and add correct LEUART
branches when disabling RX/TX.
- Allow emlib to read the HFPER clock when initializing
USART. This corrects the baud rate on the serial line.
- Always use the TXC interrupt to signal when a transmission
is over when using (L)DMA. Removes a race condition
between flipping from TXBL to TXC, and TXC activating.
- With the previous change, serial_tx_active can now poll
the TXBL/TXC interrupts to see if a transmission is active.
previous code would fail in cases that the DMA transfer
had ended, but TX was still active, occasionally leading
to partial transfers when CLEARTX command was issued on
the next transfer.
- Add some sync points (SYNCBUSY poll) when twiddling around
LEUART registers.
Known issue: Using LEUART and DMA transfer on (at least) Leopard
causes the device to enter an infinite DMA interrupt loop.
When the requested timeout was not a integer multiple of the
LF clock tick the timestamp was set too short due to rounding,
sometimes causing the ticker event to be missed.
Read as not returning correct values, because RTCC (or RTC in other
Gecko's) was not initiated. This was a problem in every Gecko.
If RTCC is initiated for lptimer it is done without binding it to
irqhandler (since irq not needed). Also implementation for geckos
using RTC added.
Tested with pearl and happy geckos
Number of interrupt slots reported by different files before this commit:
giant happy leopard pearl wonder zero
spec 39 21 39 34 39 17
nvic 39 21 39 34 40 19
startup.s 39 21 40 34 40 19
gcc link 40 21 41 34 40 19
arm link 40 22 40 - 40 16
reserved 0 0 1 0 0 2
spec - reference manual
nvic.h - cmsis_nvic.h
startup.s - assembler startup files
gcc link - efm32*.ld linker script for GCC
arm link - efm32*.sct linker script for ARM (RVCT)
reserved - number of 'reserved' slots at the end of irq table in startup.s files
Fixed amounts to reflect those in the startup files, including reserved
slots:
Giant
Reduce amount in GCC and ARM linker files to 39
Happy
Fix comment in GCC linker file
Reduce amount in ARM linker file to 21
Leopard
Increase amount to 40 in cmsis_nvic.h
Reduce amount to 40 in GCC linker file (this bug caused by
emlib 4.1.0 port commit 1923e8b4)
Wonder
No changes, but note that ref. manual does not list FPUEH
interrupt that is included in startup files at index 39
Zero
Increase amount to 19 in ARM linker file
LDMA now functional for both RX/TX.
One hack remains - need to check if TXC interrupt check can be
removed from older platforms, or if flagging is necessary.
Any channel can be used. It is possible to have 4 pwm outputs
active at a same time, if PinMap_PWM configuration is done properly.
Future improvement proposal: dynamic channel selection!
Channel selection shifted to right place. Now It seems to work
at least with channel PC11. Weird thing is, that floating pin gives
result 0.4. Should be 0.0.
LDMA support for serial HAL. Adds callback support for emlib LDMA
code so that most of the old serial code can be reused.
Note: Serial shows some signs of life on the bus, but DMA mode
is completely untested.
analogin_api.c changed to make it compile.
Compilation error will be generated if _ADC_SINGLECTRL_POSSEL_MASK ||
_ADC_SINGLECTRL_INPUTSEL_MASK is not defined. This is because NEGATIVE
voltage measurement is not supported by MBED API.
Use RTCC API for lp_ticker on Pearl. Basic adaptation, but more
work is required.
Now frees RTC when ticker is not used (detected through interrupt
disable), so that sleep modes below EM2 do not remain
permanently blocked.
PWM pin mappings. Since the pins can be freely chosen (unlike
in previous HW), there should be no need to use the other channels.
Also corrected frequency for HFXO in ref devices.
The function vsnprintf does not properly handle a size of zero for
the destination buffer, and will write data to it. If the buffer is
set to null this will cause a hardfault. This patch adds a workaround
for this bug by using a buffer of size 1.
mtkrtk
dc37
Martin Kojtal
adustm
neilt6
Kevin Gillespie
dbestm
bcostm
modtronix-com
tomoyuki yamanaka
Parthasarathy.S
Moin Shaik
Mac Lobdell
Paul Staron
sg-
dinau
anpilog
Steven Cooreman
leibin
Mikko Polojarvi
Aksel Skauge Mellbye
jhokajar
ytsuboi
Russ