mirror of https://github.com/ARMmbed/mbed-os.git
SiLabs Pearl: Support for ARM compiler toolchain
Startup files and linker scripts added for standard and micro variants of the ARM compiler toochain.pull/1501/head
Mikko Polojarvi
Steven Cooreman
parent
73db782a73
commit
f6b0c37982
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@ -0,0 +1,15 @@
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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LR_IROM1 0x00000000 0x00040000 { ; load region size_region
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ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 0x200000C8 0x00007F38 { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,259 @@
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;/**************************************************************************//**
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; * @file startup_efm32pg1b.s
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; * @brief CMSIS Core Device Startup File for
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; * Silicon Labs EFM32PG1B Device Series
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; * @version 4.1.0
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; * @date 03. February 2012
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; *
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; * @note
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; * Copyright (C) 2012 ARM Limited. All rights reserved.
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; *
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; * @par
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * @par
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;/*
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20008000
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000C00
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY, ALIGN=8
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD EMU_IRQHandler ; 0: EMU Interrupt
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DCD 0 ; 1: Reserved
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DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt
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DCD 0 ; 3: Reserved
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DCD 0 ; 4: Reserved
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DCD 0 ; 5: Reserved
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DCD 0 ; 6: Reserved
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DCD 0 ; 7: Reserved
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DCD LDMA_IRQHandler ; 8: LDMA Interrupt
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DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt
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DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt
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DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt
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DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt
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DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt
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DCD ADC0_IRQHandler ; 14: ADC0 Interrupt
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DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt
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DCD I2C0_IRQHandler ; 16: I2C0 Interrupt
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DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt
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DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt
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DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt
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DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt
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DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt
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DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt
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DCD CMU_IRQHandler ; 23: CMU Interrupt
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DCD MSC_IRQHandler ; 24: MSC Interrupt
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DCD 0 ; 25: Reserved
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DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
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DCD 0 ; 27: Reserved
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DCD 0 ; 28: Reserved
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DCD RTCC_IRQHandler ; 29: RTCC Interrupt
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DCD 0 ; 30: Reserved
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DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt
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DCD 0 ; 32: Reserved
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DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT EMU_IRQHandler [WEAK]
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EXPORT WDOG0_IRQHandler [WEAK]
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EXPORT LDMA_IRQHandler [WEAK]
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EXPORT GPIO_EVEN_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT USART0_RX_IRQHandler [WEAK]
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EXPORT USART0_TX_IRQHandler [WEAK]
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EXPORT ACMP0_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT IDAC0_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT GPIO_ODD_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT USART1_RX_IRQHandler [WEAK]
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EXPORT USART1_TX_IRQHandler [WEAK]
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EXPORT LEUART0_IRQHandler [WEAK]
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EXPORT PCNT0_IRQHandler [WEAK]
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EXPORT CMU_IRQHandler [WEAK]
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EXPORT MSC_IRQHandler [WEAK]
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EXPORT LETIMER0_IRQHandler [WEAK]
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EXPORT RTCC_IRQHandler [WEAK]
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EXPORT CRYOTIMER_IRQHandler [WEAK]
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EXPORT FPUEH_IRQHandler [WEAK]
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EMU_IRQHandler
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WDOG0_IRQHandler
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LDMA_IRQHandler
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GPIO_EVEN_IRQHandler
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TIMER0_IRQHandler
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USART0_RX_IRQHandler
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USART0_TX_IRQHandler
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ACMP0_IRQHandler
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ADC0_IRQHandler
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IDAC0_IRQHandler
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I2C0_IRQHandler
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GPIO_ODD_IRQHandler
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TIMER1_IRQHandler
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USART1_RX_IRQHandler
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USART1_TX_IRQHandler
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LEUART0_IRQHandler
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PCNT0_IRQHandler
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CMU_IRQHandler
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MSC_IRQHandler
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LETIMER0_IRQHandler
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RTCC_IRQHandler
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CRYOTIMER_IRQHandler
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FPUEH_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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@ -0,0 +1,15 @@
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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LR_IROM1 0x00000000 0x00040000 { ; load region size_region
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ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 0x200000C8 0x00007F38 { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,259 @@
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;/**************************************************************************//**
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; * @file startup_efm32pg1b.s
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; * @brief CMSIS Core Device Startup File for
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; * Silicon Labs EFM32PG1B Device Series
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; * @version 4.1.0
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; * @date 03. February 2012
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; *
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; * @note
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; * Copyright (C) 2012 ARM Limited. All rights reserved.
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; *
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; * @par
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * @par
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;/*
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20008000
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000C00
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY, ALIGN=8
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD EMU_IRQHandler ; 0: EMU Interrupt
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DCD 0 ; 1: Reserved
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DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt
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DCD 0 ; 3: Reserved
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DCD 0 ; 4: Reserved
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DCD 0 ; 5: Reserved
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DCD 0 ; 6: Reserved
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DCD 0 ; 7: Reserved
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DCD LDMA_IRQHandler ; 8: LDMA Interrupt
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DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt
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DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt
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DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt
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DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt
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DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt
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DCD ADC0_IRQHandler ; 14: ADC0 Interrupt
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DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt
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DCD I2C0_IRQHandler ; 16: I2C0 Interrupt
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DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt
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DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt
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DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt
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DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt
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DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt
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DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt
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DCD CMU_IRQHandler ; 23: CMU Interrupt
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DCD MSC_IRQHandler ; 24: MSC Interrupt
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DCD 0 ; 25: Reserved
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DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
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DCD 0 ; 27: Reserved
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DCD 0 ; 28: Reserved
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DCD RTCC_IRQHandler ; 29: RTCC Interrupt
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DCD 0 ; 30: Reserved
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DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt
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DCD 0 ; 32: Reserved
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DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT EMU_IRQHandler [WEAK]
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EXPORT WDOG0_IRQHandler [WEAK]
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EXPORT LDMA_IRQHandler [WEAK]
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EXPORT GPIO_EVEN_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT USART0_RX_IRQHandler [WEAK]
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EXPORT USART0_TX_IRQHandler [WEAK]
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EXPORT ACMP0_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
|
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EXPORT IDAC0_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT GPIO_ODD_IRQHandler [WEAK]
|
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT USART1_RX_IRQHandler [WEAK]
|
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EXPORT USART1_TX_IRQHandler [WEAK]
|
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EXPORT LEUART0_IRQHandler [WEAK]
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EXPORT PCNT0_IRQHandler [WEAK]
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EXPORT CMU_IRQHandler [WEAK]
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EXPORT MSC_IRQHandler [WEAK]
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EXPORT LETIMER0_IRQHandler [WEAK]
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EXPORT RTCC_IRQHandler [WEAK]
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EXPORT CRYOTIMER_IRQHandler [WEAK]
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EXPORT FPUEH_IRQHandler [WEAK]
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EMU_IRQHandler
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WDOG0_IRQHandler
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LDMA_IRQHandler
|
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GPIO_EVEN_IRQHandler
|
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TIMER0_IRQHandler
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USART0_RX_IRQHandler
|
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USART0_TX_IRQHandler
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ACMP0_IRQHandler
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ADC0_IRQHandler
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||||
IDAC0_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
GPIO_ODD_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
USART1_RX_IRQHandler
|
||||
USART1_TX_IRQHandler
|
||||
LEUART0_IRQHandler
|
||||
PCNT0_IRQHandler
|
||||
CMU_IRQHandler
|
||||
MSC_IRQHandler
|
||||
LETIMER0_IRQHandler
|
||||
RTCC_IRQHandler
|
||||
CRYOTIMER_IRQHandler
|
||||
FPUEH_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
Loading…
Reference in New Issue