As the `psa` library is not included in the baremetal profile, perform
a TFM system reset only if the `psa` library is included in
the build otherwise perform a normal CMSIS system reset.
ARM Compiler 6.13 testing revealed linker errors pointing out
conflicting use of `__user_setup_stackheap` and
`__user_initial_stackheap` in some targets. Remove the unwanted
`__user_initial_stackheap` from the targets - the setup is
centralised in the common platform code.
Looking into this, a number of other issues were highlighted
* Almost all targets had `__initial_sp` hardcoded in assembler,
rather than getting it from the scatter file. This was behind
issue #11313. Fix this generally.
* A few targets' `__initial_sp` values did not match the scatter
file layout, in some cases meaning they were overlapping heap
space. They now all use the area reserved in the scatter file.
If any problems are seen, then there is an error in the
scatter file.
* A number of targets were reserving unneeded space for heap and
stack in their startup assembler, on top of the space reserved in
the scatter file, so wasting a few K. A couple were using that
space for the stack, rather than the space in the scatter file.
To clarify expected behaviour:
* Each scatter file contains empty regions `ARM_LIB_HEAP` and
`ARM_LIB_STACK` to reserve space. `ARM_LIB_STACK` is sized
by the macro `MBED_BOOT_STACK_SIZE`, which is set by the tools.
`ARM_LIB_HEAP` is generally the space left over after static
RAM and stack.
* The address of the end of `ARM_LIB_STACK` is written into the
vector table and on reset the CPU sets MSP to that address.
* The common platform code in Mbed OS provides `__user_setup_stackheap`
for the ARM library. The ARM library calls this during startup, and
it calls `__mbed_user_setup_stackheap`.
* The default weak definition of `__mbed_user_setup_stackheap` does not
modify SP, so we remain on the boot stack, and the heap is set to
the region described by `ARM_LIB_HEAP`. If `ARM_LIB_HEAP` doesn't
exist, then the heap is the space from the end of the used data in
`RW_IRAM1` to the start of `ARM_LIB_STACK`.
* Targets can override `__mbed_user_setup_stackheap` if they want.
Currently only Renesas (ARMv7-A class) devices do.
* If microlib is in use, then it doesn't call `__user_setup_stackheap`.
Instead it just finds and uses `ARM_LIB_STACK` and `ARM_LIB_HEAP`
itself.
We should not block in case the UART is busy transmitting. The
API has been updated to check the status of all UART's and return
1 in case any of them is busy transmitting.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The code checks if any of the UART's is still transmitting.
If so then prevent from entering deepsleep
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Use the updated API's provided by the SMC driver
2. Wait till debug UART has finished transmitting data
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update to handle 12-bit resolution
2. Properly handle the pin configuration
3. Update the pin setup to handle the ADC B channel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The IRQ disable was always disabling both rising
and falling edges of the interrupt thereby causing
failures in cases when one of the two should stay enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update the clock divider setting
2. ADC resolution is 12-bits, update the API return value
to return 16-bit result
3. Update IOMUX setup
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
An extra start signal was observed on the bus which was
discovered by the FPGA test shield.
This is because the hardware sends out a transaction as soon
as a write to the START bit. Hence the write to the START
bit is delayed by using a flag.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
As the build tool in mbed-os 5.13 cannot appropriately deal with a segmented
bootloader when combining it with an application, this commit adjusts the
size reserved for interrupts (via the linker file) to avoid a bootloader
segmentation due to an unpopulated ROM area.
The microcontroller has a total of 60 vector interrupts + 16 exception
handlers. The allocated ROM flash for interrupts should be (60 + 16) x word
size in bytes = 76 x 4 = 304 = 0x130.
This commit changes the interrupt reserved space from 0x140 to 0x130.
The file 'fsl_powerquad_data.h' declares several dctXXX_cosFactor
arrays with sizes twice larger compared to the actual definitions in
'fsl_powerquad_data.c'.
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
Spotted in compiler warnings - code was trying to access a non-existent
second security control block, rather than access the settings for the
second APB bridge in the first and only security control block.
Fixes test failure seen with tests-mbed_hal-stack_size_unification
under IAR and ARM toolchain
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
The flash driver for the LPC55S69 is different from
prior LPC family. Move the Flash HAL driver to SoC
specific folder
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Linker files for LPC11U68 and LPC1549 updated as Mbed OS memory model
1. LPC1549
Has multiple memory banks, 4K bank used for stack exclusively and 16K for Heap
Its is mbed 2 only target hence 4K for stack.
2. LPC11U68
Added Heap and Stack sections in linker files. Resolved build issues.
Add the functions qspi_master_sclk_pinmap, qspi_master_ssel_pinmap and
qspi_master_data0_pinmap-qspi_master_data3_pinmap to all targets with
qspi support.
The DEVICE_FOO macros are always defined (either 0 or 1).
This patch replaces any instances of a define check on a DEVICE_FOO
macro with value test instead.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
StackTop calculation was not adjusted when ram size was increased by using al 3 ram regions.
This caused memory allocation failures althogh enough free heap was reported
### Description
The Mbed 2 release was broken for FF_LPC546XX as it would include
the entire mbed 2 build of the LPC546XX. This PR seperates these 2
builds completely by:
* Removing non-shared extra labels from the MCU_LPC546XX target
* Moving the target implementation to a shared target directory
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Breaking change
--legacyalign, --no_legacyalign are deprecated from ARMC6 compiler, in order to
remove deprecated flags all linker files (GCC and IAR as well to have uniformity)
should strictly align to 8-byte boundary
1. Add Pin defines for missing PWM pins
2. Update the hal to account for the number of PWM instances
3. Fix the register reload policy
4. Configure the XBAR to put the PWM fault inputs in inactive state
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Added a flag to issue START command
2. Do not send START command inside i2c_start function as
the LPI2C hardware will issue a STOP on reception
of a NACK
3. Remove the i2c_address global variable, this is not
required
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Remove the repeated_start flag and code as this is not needed
for the LPI2C module
2. Enable the SION bit on the I2C pins
3. Enable 22K Pullup option of the I2C pins
4. Update the 0 byte write implementation to ensure the START
command gets flushed out of the FIFO
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Low power functions related to powering off FLEXSPI and SDRAM needs
to be copied to internal memory
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This PR provides implementation of ticker_free() function for the following boards:
ARCH_PRO
EV_COG_AD3029LZ
EV_COG_AD4050LZ
K22F
K64F
K82F
KW24D
KW41Z
LPC546XX
NRF51_DK
NRF52_DK
NUCLEO_F207ZG
NUCLEO_F401RE
NUCLEO_F429ZI
NUCLEO_F746ZG
REALTEK_RTL8195AM
1. Add the IVT header to the binary as this is required for boot up
This was earlier added by the DAPLink firmware. As it is no longer
handled in DAPLink, the header needs to be added inside mbed.
2. Update drivers
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Problems were seen on the LPC54628 as the ADC clock source was too
high
2. Moved the pin configuration to set Analog mode to the end of the
function
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Sleep - within 10us
Deepsleep - within 10ms
Note about mbed boards with interface, moved to lpc176x, as they are target related,
should be documented in the target documentation.
The tests will come as separate PR, to conform to this updates to sleep API.
Patch to LPC546XX SDK code - write the low Ethernet MAC address
register last, as that synchronises the update.
Without this change, the ENET_SetMacAddr call only seems to work prior
to MAC initialisation, causing problems for the new mbed OS EMAC system,
which expects it to be changable later.
Updated emac greentea tests #6851.
Qinghao Shi
Martin Kojtal
Hugues Kamba
Przemyslaw Stekiel
Maciej Bocianski
Kevin Bracey
int_szyk
Mahesh Mahadevan
Jaeden Amero
Chris Snow
David Rauschenbach
Seppo Takalo
Arto Kinnunen
Mathias Brossard
Wajahat Abbas
Deepika
Michael Schwarcz
David Saada
Oren Cohen
Alexander Zilberkant
Cruz Monrreal
Russ Butler
Nir Sonnenschein
Ari Parkkila
Anna Bridge
Alastair D'Silva
fluidblue
JojoS62
Derek Miller
Jimmy Brisson
Jarkko Paso
alrodlim
thesupershan
Aleshandre Diaz
Yossi Levy
canhkha
Wilfried Chauveau
Bartek Szatkowski
Martin Kojtal