- some minor error correction
- add pin definition for 3 tests (MBED_A5,6,7)
- add new target disco_f401vc to travis_build
travis_build and all test are OK except missing STM32F4 target
MTS_MDOT_F405RG
This is a fix for issue #285. This fix is similar to that proposed by
@oresths in the original issue.
There is code in rt_init_stack() which compares the task_id against the
value of 1 before writing MAGIC_WORD to the bottom of the stack. This
is supposed to stop the write from occurring for the main thread but
svcThreadCreate() doesn't initialize the P_TCB's task_id field until
after rt_init_stack() is executed. If any dynamic memory allocation
has occurred before the main thread is started (from the standard C
startup code) then this write could overwrite data in that allocation.
This change:
* moves the task_id initialization in svcThreadCreate() to happen
before the call to rt_init_context() is made.
* cleans up some comments in svcThreadCreate() which appear to
reference older versions of the code which would automatically
allocate stack memory if size == 0.
* still keeps the call to rt_dispatch() occurring after the call to
rt_init_context() so that the task is not dispatched to the
scheduler until the task fields have been populated.
I stepped through the rt_init_stack() code on my mbedLPC1768 after this
change was made to make sure that the write of MAGIC_WORD is now
skipped.
-----------------------------------------------------------------------
(gdb) break HAL_CM.c:95
Breakpoint 1 at 0x482c: file ../../external/mbed/libraries/rtos/rtx/TARGET_CORTEX_M/HAL_CM.c, line 95.
(gdb) c
Continuing.
Note: automatically using hardware breakpoints for read-only addresses.
Breakpoint 1, rt_init_stack (p_TCB=0x10000774 <os_idle_TCB>, task_body=0x4899 <os_idle_demon>)
at ../../external/mbed/libraries/rtos/rtx/TARGET_CORTEX_M/HAL_CM.c:95
95 if (p_TCB->task_id != 0x01)
(gdb) p *p_TCB
$1 = {
cb_type = 0 '\000',
state = 1 '\001',
prio = 0 '\000',
task_id = 255 '\377',
p_lnk = 0x0 <_reclaim_reent>,
p_rlnk = 0x0 <_reclaim_reent>,
p_dlnk = 0x0 <_reclaim_reent>,
p_blnk = 0x0 <_reclaim_reent>,
delta_time = 0,
interval_time = 0,
events = 0,
waits = 0,
msg = 0x0 <_reclaim_reent>,
stack_frame = 0 '\000',
reserved = 0 '\000',
priv_stack = 128,
tsk_stack = 268437480,
stack = 0x100007a8 <idle_task_stack>,
ptask = 0x4899 <os_idle_demon>
}
(gdb) c
Continuing.
Breakpoint 1, rt_init_stack (p_TCB=0x10000120 <os_thread_def_main+16>, task_body=0x620d <__wrap_main()>)
at ../../external/mbed/libraries/rtos/rtx/TARGET_CORTEX_M/HAL_CM.c:95
95 if (p_TCB->task_id != 0x01)
(gdb) p *p_TCB
$2 = {
cb_type = 0 '\000',
state = 1 '\001',
prio = 4 '\004',
task_id = 1 '\001',
p_lnk = 0x0 <_reclaim_reent>,
p_rlnk = 0x0 <_reclaim_reent>,
p_dlnk = 0x0 <_reclaim_reent>,
p_blnk = 0x0 <_reclaim_reent>,
delta_time = 0,
interval_time = 0,
events = 0,
waits = 0,
msg = 0x0 <_reclaim_reent>,
stack_frame = 0 '\000',
reserved = 0 '\000',
priv_stack = 26968,
tsk_stack = 268467136,
stack = 0x100012a8,
ptask = 0x620d <__wrap_main()>
}
(gdb) n
97 }
When the p_TCB for ptask==__wrap_main() is encountered, the task_id
now has a value of 1 and the write of MAGIC_WORD on line 96 is
skipped.
This issue was originally reported on the mbed site:
http://developer.mbed.org/questions/5570/mbed-rtos-memory-utilization/
The cause of the 64k limitation is that even though the user can set a
stack size larger than 64k in the osThreadDef_t::stacksize 32-bit
field, this size is truncated to 16-bit when it is copied to
the priv_stack field in the OS_TCB structure.
This commit corrects that problem by making the OS_TCB::priv_stack
field 32-bit. Due to word alignment, this introduces another 2 bytes
of padding in the structure which I have made explicit with the
addition of the reserved2 field.
The tsk_stack field which follows priv_stack is referenced directly by
assembly language code responsible for context switching. This context
switching code used a fixed byte offset, TCB_TSTACK, to access this
tsk_stack field. I had to update the TCB_TSTACK definition in various
locations from 36 to 40 to account for the extra alignment padding and
increased size of the priv_stack field.
TESTING
* GCC_ARM - mbedLPC1768 and mbedLPC11U24
* Online mbed Compiler - mbedLPC1768 and mbedLPC11U24
NOTES: I had to change assembly language code that was specific to IAR
but I don't have that toolchain so those changes aren't tested.
They do however follow the same pattern as the tested GCC
modifications.
Reverting the DEFAULT_STACK_SIZE changes in cmsis.oh.h and adding
changes to RTOS_x tests, to create threads with the neccessary reduced
stack sizes for these targets.
The mcu STM32L053C8 seems to have a problem in the RCC - LSE hardware
block. The Disco_L053 don't have a 32kHz crystal connected to LSE port
pins in contrast to NUCLEO_L053.
During initialization the HAL tests if it can start the LSE oscillator.
The Flag LSERDY in RCC_CSR is set to 1 by RCC clock control when the
oscillator runs stable. Without a crystal the flag shouldn't be set and
the HAL trys to start the internal LSI oscillator.
But the flag is always set to 1 also without a crystal. That's why the
RTC doesn't start.
Stack should be 8 byte aligned on ARM.
Fix the automatic correction of the alignment in rt_init_stack,
and make sure that all stacks are aligned by the compiler.
Decreasing OS_SCHEDULERSTKSIZE to 112 bytes solves the problem of the
failed test RTOS_3 (Semaphore resource lock).
The test itself was successfull but the final printf failed.
With the reduced stacksize now every test is OK.
There exists an inconsistency between official STM schematic of Nucleo
boards and the existing hardware. Each board should have an 8MHz
external clock source. That is not the case. At some boards the solder
jumper is existing and with that the external clock source. At some
other boards the solder jumper is not available. The Nucleo_F302 should
run with 72MHz but that is only possible with an external clock source.
Because of a missing solder jumper it runs only with the internal clock
source, and that's why only with 64MHz.
In case of off-line compiler, there is no problem about the frequency setting processing.
But in case of online compiler, the frequency setting processing will be error.
So, modify frequency setting processing of SPI to pass in online compiler.
Issue originally reported on mbed site here:
https://developer.mbed.org/questions/5695/FRDM-KL05z-hardfault-when-compiled-with-/
The RAM base address was incorrectly set to the beginning of RAM
instead of at a 0xC0 byte offset to reserve room for the interrupt
vectors. Without this fix, the global variables and the interrupt
vectors were occupying the same space in RAM once the user enabled the
timer interrupt.
The user who originally reported the issue on the mbed site has tested
this fix and verified that it corrected the hard fault issue that they
were encountering.
- Change default setting of CMSIS-RTOS RTX for Cortex-A9 to align with Cortex-M.
- Change the interrupt priority of Ether driver to align with other drivers.
Changes as below.
-I2C
Change communication wait time and Frequency accuracy improvement of I2C.
- Frequency accuracy improvement
- Changed the wait time between one communication completed and the next communication start.
The wait time will be Low clock width by this changing.
-PWM
Modify processing of pulsewidth() of PWM
- Modify processing of pulsewidth() to match the specifications of the RZ_A1H.
-SPI
Fixed a bug that SPI driver is not able to communicate when transfer bit length is 16bit or 32bit.
- Frequency accuracy improvement
- Modify transfer processing when transfer bit length is 16bit or 32bit.
-Serial
Change the reference register macro of Serial
- Change the reference register macro to align with other driver codes.
Changing original STM Cube Driver to call _start instead of main to
initialise the rtos when using it. Without using rtos the behavior is
the same as before.
Original STM32Cube F4 driver sets SYSCLK for STM32F429 to 16MHz. This
adds a 168MHz and 180MHz configuration to system_stm32f4xx.c generated
by STM32CubeMX code generator. The rtos clock configuration is changed
too. In singletest.py run everything is OK.
- Changing original STM Cube Driver to call _start instead of main to
initialise the rtos when using it. Without using rtos the behavior is
the same as before.
- Adding DISCO_F429 to rtos
- Adding targets to RTOS_xx tests.
- All tests are OK. Tested with Nucleo and Disco boards. Not tested with
MDOT_F4 but that uses the same hal like nucleo_f411.
Fix a bug as below.
- Period can not be changed.
Restructions: 1. The upper limits is 491us
2. Change all period of the same channel when changing period.
Fix some bugs of Serial as below.
- TX/RX terminal of XBee(P7_4, P7_5) setting is reverse.
- P5_6 and P5_7 terminals can not be used.
- Tx interrupt will not occur at the right timing.
- There are no settings of WIFI Module terminals(P11_10,P11_11).
- There are no settings of Xbee Module terminals(P6_6,P6_7).
Timer value wraparound operation had not been considered in common wait process.
By defining the EXPIRE_US non-zero value, wraparound operation is enabled.
The EXPIRE_US will be define the value of each vender-specific.
If EXPIRE_US is 0, the common wait process is same as before.
nRF51822 from Nordic Semiconductor
Bluetooth Low-Energy v4.1 compliant - interface to smartphones, tablets
System-on-Chip (SoC) solution - easily transformable into a deployable solution
Drop-in solution for production - no need to design your own antenna
FCC and CE Certified
3x LEDs, 3x Buttons
Powered by interface board or external 3.3V
Y5 Design LLC Interface Board
LPC11u35 from NXP
Low Power, ARM(r) Cortex-M0 suitable for a wide range of applications
On-Chip Bootloader - In-System programming (ISP) and in-application programming (IAP)
ROM-based USB drivers - Flash updates via USB supported
SPI, GPIO, i2C, UART, ADC
3x LEDs, Reset Button
3.3V powered via USB or external
USB interface - shipped with USB-A, male connector, pads for Micro female
Fix IAR serial fgets fgetc
Taken from PR #770:
setbuf(_file, NULL), and std::setvbuf(_file,NULL,_IONBF,NULL) should both give an unbuffered stream (the data is directly written to the input buffer). IAR sets a buffer anyway of size 512 bytes for these calls. Calling setvbuff(_file,buf,_IONBF,NULL) with a buffer that is not a NULL pointer sets the buffer to size one. Which means that as soon as a char is read it is written to the real buffer. If people are interested in looking at this further they can look at the files under ARM/src/dlib: fgets.c, fflush.c, xfrpep.c and xfwprep.c
Three changes, first it fixes:
https://github.com/mbedmicro/mbed/issues/761 (which was reported
slightly wrong because K20 has again different clocking from KLXX for
uarts).
Second it adds mcgpllfll to clk_freqs, which again is different for K20
compared to KLXX .
Finally it adds the fractional baudrate divider for more accurate serial
baudrates.
ohagendorf
kazu-zamasu
Adam Green
Per Kristian Gjermshus
Martin Kojtal
albert361
Masao Hamanaka
Toyomasa Watarai
bcostm
Martin Olejar
mazgch
Yihui Xiong
Mike Fiore
Rohit Grover
vincent rabbit
Richard Osterloh
GustavWi
sg-
Nick DeLisi
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