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2302 Commits (ab8d84a46c5fe5d5ef3f98d75da8ba4f74aefa6b)

Author SHA1 Message Date
MarceloSalazar e43ece13aa Rename EMW3166 target 2020-04-09 15:32:41 +01:00
MarceloSalazar 831c475a46 Remove Silica target 2020-04-09 15:32:41 +01:00
MarceloSalazar 1e4c707cc5 Remove ELMO target 2020-04-09 15:32:41 +01:00
MarceloSalazar 3ad6c4fa2b Remove Ublox ODIN targets 2020-04-09 15:32:39 +01:00
Rajkumar Kanagaraj 3d128e861b - Fix the CI build issue. 
- Incorporate the review comment.
 2020-04-08 10:35:07 +01:00
Rajkumar Kanagaraj 9739b565b2 Fix the CI build issue 2020-04-08 10:35:07 +01:00
Martin Kojtal a6ef9db8dc
Merge pull request #12626 from jeromecoutant/PR_F4 
STM32F4 update drivers version to CUBE V1.25.0
 2020-04-01 10:50:32 +02:00
Martin Kojtal eb2457f59d
Merge pull request #12690 from jeromecoutant/PR_GCC_ETEXT 
STM32: solve GCC Unspecified RTOS error
 2020-03-31 09:27:05 +02:00
jeromecoutant 33fc5000a9 STM32F4 V1.19.0 -> V1.25.0 : adaptation 2020-03-30 16:04:02 +02:00
jeromecoutant aa22c4b4d5 STM32F4 V1.19.0 -> V1.25.0 : Driver part 2020-03-30 16:04:01 +02:00
jeromecoutant 480fd2ab92 STM32F4 V1.19.0 -> V1.25.0 : CMSIS part 2020-03-30 16:04:00 +02:00
jeromecoutant 3c3b17d601 STM32F4 restructuration for better maintenance 2020-03-30 16:03:59 +02:00
Martin Kojtal 92cdcfb302
Merge pull request #12662 from artokin/workaround_for_stm32f4_sleep 
Add workaround for STM32F4 hardfault in sleep mode
 2020-03-30 14:08:48 +02:00
Marcelo Salazar 5aa66b5c9a
Add workaround for F429 hardfault 2020-03-27 11:58:46 +00:00
jeromecoutant a1c159e0b5 STM32 GCC Unspecified RTOS error 2020-03-24 17:32:13 +01:00
jeromecoutant 249752e7bc STM32H7: enable QSPI 
- DISCO_H747I board has MT25QL512 embedded QSPI
 2020-03-23 18:46:26 +01:00
Teemu Takaluoma 40672c5e0f Disable sleep on STM32F4 as an workaround for stability issues. 
This workaround is related to Mbed OS issue
https://github.com/ARMmbed/mbed-os/issues/12294
 2020-03-20 12:16:06 +02:00
Anna Bridge d61187c23a
Merge pull request #12611 from jeromecoutant/PR_UART_PARITY 
STM32F4 UART issue when parity enabled
 2020-03-13 11:07:21 +00:00
jeromecoutant 6752a2d555 STM32F4 UART issue when parity enabled 
Bits 8:0 DR[8:0]: Data value
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.
 2020-03-10 17:22:02 +01:00
Rajkumar Kanagaraj 2f4cf1a052 Fix the CI build issue 2020-03-10 07:50:32 -07:00
jeromecoutant 1fa78eb5a8 STM32F7: add ARM_LIB_HEAP definition in ARM linker scripts 2020-03-05 16:35:40 +01:00
jeromecoutant 0871db277b STM32F7: allow multiple SetSysClock call 2020-03-05 16:34:56 +01:00
Martin Kojtal a17866e623
Merge pull request #12559 from jeromecoutant/PR_DISCO_L4R9 
DISCO_L4R9I correct LED pins
 2020-03-04 07:48:32 +00:00
Martin Kojtal b3583f04cf
Merge pull request #12464 from jeromecoutant/PR_ETHERNET 
STM32 EMAC : add configuration choice and connection check
 2020-03-03 16:04:18 +00:00
jeromecoutant 3e30033822 DISCO_L4R9I correct LED pins 2020-03-03 13:36:57 +01:00
Martin Kojtal bad9c57085
Merge pull request #12460 from mprse/spi_init_nc_fix 
Allow MISO/MOSI set to NC during SPI initialisation (fix for issue #12435)
 2020-03-03 09:56:47 +00:00
jeromecoutant 1b40076376 STM32 EMAC : more configurable 
- PHY default configuration can be changed
  - AutoNegotiation
  - Speed
  - DuplexMode
- PHY register offset can be updated depending on chosen PHY

All unused parameters are cleaned.
 2020-03-02 16:19:26 +01:00
Martin Kojtal 2d93a4578d
Merge pull request #12451 from jeromecoutant/PR_QSPI_TRACE 
STM32 : enable MBED trace for QSPI
 2020-02-27 10:02:46 +00:00
jeromecoutant 9977ace2c9 STM32 : enable MBED trace for QSPI 2020-02-20 12:20:24 +01:00
jeromecoutant a1570f936f STM32WB : Add ReadMe file 
Help on FW update procedure
 2020-02-20 09:20:44 +01:00
jeromecoutant 9d016022b6 STM32WB clean SetSysClock 2020-02-20 09:20:44 +01:00
jeromecoutant ebae0e56d4 STM32WB align deepsleep functions with CubeFW 2020-02-20 09:20:43 +01:00
Martin Kojtal 9f5ced30dc
Merge pull request #12415 from jeromecoutant/PR_H7README 
STM32H7 : add readme file for dual core use
 2020-02-19 12:52:10 +00:00
Przemyslaw Stekiel 713be4fd77 STM pin_function(), pin_mode(): return immediately when given pin is NC 
Additionally, remove redundant pin checks against NC when above functions are used.
 2020-02-19 11:46:59 +01:00
Przemyslaw Stekiel c6a6984ab8 Allow NC for MISO or MOSI while initializing SPI 
Static pinmap extension required to use pin_function() and pin_mode() functions instead of pinmap_pinout(). Unfortunatelly pin_function() does not allow passing NC pin.
Call pin_function() and pin_mode() only if MISO/MOSI pin is not NC.
 2020-02-18 13:38:43 +01:00
jeromecoutant 065a79e48a STM32H7: add README file for dual core use 2020-02-17 16:21:20 +01:00
jeromecoutant d66b39de18 STM32L5 : Add DISCO-L562E support 2020-02-14 17:49:40 +01:00
jeromecoutant f0969022b8 STM32L5 : add QSPI support 2020-02-14 17:49:33 +01:00
Martin Kojtal 7658681a9e
Merge pull request #12409 from LMESTM/Fix_lpuart_deep_sleep 
FIX: LPUART clock source selection should be left to serial driver
 2020-02-13 09:45:41 +00:00
Laurent Meunier 3fd071404e FIX: LPUART clock source selection should be left to serial driver 
The clock source selection of LPUART depends on System clocks but also on
the serial baudrate. There is a specific computation done in serial driver
targets/target_STM/serial_api.c

At first start-up the LPUART1 clock selected in SetSysClock was anyway
overridden by the serial driver, so this was of no effect. But in case
of deep sleep SetSysClock is called again, while the driver isn't, so
SetSyClock was corrupting the serial clock configuration.

So let's remove these few lines of code which are causing trouble.
 2020-02-11 17:14:45 +01:00
Martin Kojtal c1eaf2c358
Merge pull request #12380 from mprse/DISCO_L475VG_IOT01A_add_gpio_pinmap 
DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing
 2020-02-11 11:58:53 +00:00
Martin Kojtal 7fd5119b89
Merge pull request #12341 from fkjagodzinski/fix-stm-hal_fpga 
STM32L4: Fix the UART RX & TX data reg bitmasks
 2020-02-10 13:21:31 +00:00
jeromecoutant 2368a07244 STM32: Fix the UART RX & TX data reg bitmasks 2020-02-07 16:23:50 +00:00
Przemyslaw Stekiel 3a71f86235 DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing 2020-02-07 11:41:32 +01:00
Filip Jagodzinski ae635d5cd4 STM32L4: Fix the UART RX & TX data reg bitmasks 
The existing logic was insufficient to properly handle odd and even
parity setting, e.g. serial_getc() returned 9-bit data for 8O1
transmission format.
 2020-02-06 14:07:51 +01:00
Martin Kojtal 32675cc6ac
Merge pull request #11874 from fkjagodzinski/armc6_build-enable_lto_for_release 
ARMC6: Add a build profile extension with the link-time optimizer enabled
 2020-02-05 14:42:16 +00:00
Martin Kojtal e3ad1cae55
Merge pull request #12334 from AriParkkila/cell-c030-r412m 
Update cellular drivers/tests for UBLOX_C030_R412M
 2020-02-05 12:50:11 +00:00
Martin Kojtal 841b846b46
Merge pull request #12362 from ABOSTM/L0_CUBE_HAL_REWORK_NO_MORE_OVERRUN 
TARGET_STM: L0 CUBE SPI async mode send next byte after previous one is read
 2020-02-05 10:17:13 +00:00
Martin Kojtal cee2a352a7
Merge pull request #12357 from ABOSTM/F103_ADC3_NOT_SUPPORTING_COMMON_SETTINGS 
TARGET_STM32F1: don't set ADC common register when ADC doesn't support it
 2020-02-04 15:24:51 +00:00
Alexandre Bourdiol 315220832f TARGET_STM: L0 CUBE SPI async mode send next byte after previous one read 
In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.

So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
 2020-02-04 13:26:49 +01:00