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7278 Commits (75544a7ce0e3d89abc27b12b23f8045d73695e45)

Author SHA1 Message Date
Martin Kojtal 75544a7ce0
Merge pull request #13565 from m-ecry/feature-stm32g4-can-support 
Feature stm32g4 can support
 2020-09-17 15:08:46 +01:00
Martin Kojtal 3801f6e389
Merge pull request #13406 from Allmoz/master 
STM32F1 USBDevice
 2020-09-17 08:56:03 +01:00
m-ecry 73493b909a STM-can-api: Fixed variable name for H7 
- can_frequency uses f instead of hz for can frequency
 - Also added comment to system_clock
 2020-09-16 17:35:32 +02:00
m-ecry 2a13fa199d STMG4-sys-clk: If can PLLQ=160MHz, else 170MHz 
- with 170MHz as can-core-frequency, the accuracy for many baudrates is
too low. 160MHz is better for a broad range of frequencies
 2020-09-14 18:15:41 +02:00
m-ecry d0c8ad75e1 STM-can-api: Support reading of remote_msg 
- Previously a received msg was fixed of data_type
 2020-09-14 18:10:48 +02:00
m-ecry 13b663397f STM-can-api: Added usage of prescaler 
- This enables more frequencies, but without regard to the accuracy.
May still require manual clock setup, to remain in tolerance window
 2020-09-14 16:29:12 +02:00
Martin Eckardt 35c9e7a5ad Use HAL function for FDCAN_CLK-calculation 
- Thanks to @jeromecoutant for showing the HAL funtion
 - Added #ifdef guard to FDCAN2/3 handler functions
 2020-09-14 15:24:14 +02:00
Martin Kojtal 6bfd89e656
Merge pull request #13196 from gbrtth/musca_s1_support_mbed6 
Add ARM_MUSCA_S1 as a new target platform
 2020-09-10 16:53:14 +01:00
Martin Kojtal f7d5dfbe3b
Merge pull request #13587 from jeromecoutant/PR_G031 
MCU_STM32G031xx : decrease boot-stack-size
 2020-09-10 15:04:47 +01:00
Martin Kojtal 47e943af2d
Merge pull request #13558 from jeromecoutant/PR_L4PLUS_SRAM3 
STM32L4+ : SRAM3 is powered off in deepsleep
 2020-09-10 14:03:32 +01:00
Mark Horvath 37f26692b1 Workaround to fix clang build 
Change-Id: Ib0d207d4ca22ae239f6b40b95618b66eb329a29c
Signed-off-by: Mark Horvath <mark.horvath@arm.com>
 2020-09-10 13:59:32 +01:00
Gabor Toth bdf2306f16 Add platform support to Musca S1 
Change-Id: Iebdd4bc402446caba6b7bd894eddb0a85ed884d8
Signed-off-by: Mark Horvath <mark.horvath@arm.com>
Signed-off-by: Gabor Toth <gabor.toth@arm.com>
 2020-09-10 14:53:41 +02:00
jeromecoutant 2441e150a4 MCU_STM32G031xx : decrease boot-stack-size 
As a small RAM target,
default boot-stack-size is decreased
for baremetal full support
 2020-09-10 14:38:09 +02:00
Martin Kojtal 468372e759
Merge pull request #13492 from talorion/fix-PwmOut-resets-after-suspend 
Fix pwm out resets after suspend
 2020-09-10 12:40:18 +01:00
Martin Kojtal a17a481c54
Merge pull request #13583 from jeromecoutant/PR_ARDUINO_PIN 
STM32: correct few Arduino pins value
 2020-09-10 12:38:02 +01:00
Martin Kojtal e2077197d9
Merge pull request #13452 from Patater/conf-boot-stack-size 
Use boot stack size from config system
 2020-09-10 12:32:05 +01:00
Martin Kojtal 267a5ac5bf
Merge pull request #13538 from sparkfun/ambiq-apollo3-dev-squash 
Ambiq AMA3B1KK and SparkFun Artemis Boards Target Update
 2020-09-10 11:53:04 +01:00
Jaeden Amero 612b148fd4 stack: armc: Workaround config passing bug 
Workaround a bug where the boot stack size configuration option is not
passed on to armlink, the Arm Compiler's linker. Prefer
MBED_CONF_TARGET_BOOT_STACK_SIZE if present, as this is what the
configuration system should provide. Fall back to MBED_BOOT_STACK_SIZE
if MBED_CONF_TARGET_BOOT_STACK_SIZE is not defined, as in the case of
buggy tools. If both MBED_CONF_TARGET_BOOT_STACK_SIZE and
MBED_BOOT_STACK_SIZE are not defined, then we fall back to a hard-coded
value provided by the linkerscript. See
https://github.com/ARMmbed/mbed-os/issues/13474 for more information.
 2020-09-10 10:08:38 +01:00
Hugues Kamba 2ed7403e3e NRF52: Fix failure if boot stack size is not provided 
The same default value is provided in the GCC_ARM linker file.
 2020-09-10 10:08:38 +01:00
Jaeden Amero 39e69d328d Use boot stack size from config system 
To allow overriding of the boot stack size from the Mbed configuration
system, consistently use MBED_CONF_TARGET_BOOT_STACK_SIZE rather than
MBED_BOOT_STACK_SIZE.

Fixes #10319
 2020-09-10 10:08:38 +01:00
jeromecoutant 668412ccde NUCLEO_L433RC_P: wrong D0 and D1 pins 2020-09-10 10:05:41 +02:00
jeromecoutant 5bcb02a013 DISCO_L072CZ_LRWAN1: wrong A1/A3/A4/A5 pin values 2020-09-10 10:05:41 +02:00
jeromecoutant e695db9944 NUCLEO_F207ZG: change default SPI_MOSI pin to match Arduino standard 2020-09-10 10:05:40 +02:00
jeromecoutant 3e653223d2 NUCLEO_F303ZE: wrong D1 pins 2020-09-10 10:05:40 +02:00
jeromecoutant d20385e396 STM32G4: remove ADC support 
Waiting for implementation and test
 2020-09-10 10:05:40 +02:00
jeromecoutant 88fcd669d4 NUCLEO_L552ZE_Q: wrong D0 and D1 pins 2020-09-10 10:05:40 +02:00
Wenn0101 c2bddbbc57 Apollo3 and artemis, remove dead code and include relevant header 2020-09-09 16:43:59 -06:00
Wenn0101 e97ebc033a Apollo3 and artemis code review changes, remvoe dead code, add missing spdx identifiers, fix style 2020-09-09 15:47:23 -06:00
Martin Kojtal 3b5ab54618
Merge pull request #13542 from jeromecoutant/PR_DISCO_L4S 
B_L4S5I_IOT01A: new ST target
 2020-09-09 15:54:27 +01:00
Martin Kojtal 1f6fe470e1
Merge pull request #13564 from More-Wrong/LSI-for-STM32Gx 
STM32Gx: LSI clock selection when LSE is not available
 2020-09-09 15:16:44 +01:00
jeromecoutant 423bea50e6 B_L4S5I_IOT01A: BLE support 2020-09-09 15:19:21 +02:00
jeromecoutant 7dfe7024f0 B_L4S5I_IOT01A: HW crypto support 2020-09-09 15:19:21 +02:00
jeromecoutant d804167816 STM32L4S5xI: B_L4S5I_IOT01A new target 2020-09-09 15:19:21 +02:00
jeromecoutant c65ad59ccd STM32L4S5xI introduction 2020-09-09 15:19:11 +02:00
Martin Kojtal ae8d5a4fb6
Merge pull request #13574 from amq/patch-4 
Fix a typo in PeripheralPins.c for EFM32GG11
 2020-09-09 09:51:40 +01:00
Martin Kojtal 511c89728f
Merge pull request #13572 from jeromecoutant/PR_H7_ADC2 
STM32H7 ADC: clock selection lost after deepsleep
 2020-09-09 09:51:34 +01:00
Martin Kojtal 0190014103
Merge pull request #13547 from OpenNuvoton/nvt_nuc472_sd 
Nuvoton: Fixed NUC472 SD buffer alignment
 2020-09-09 09:51:17 +01:00
Martin Kojtal 2fe10ddb21
Merge pull request #13516 from romanjoe/pr/064b0s2_rename 
Cypress: Rename CY8CKIT_064B0S2_4343W to CY8CKIT064B0S2_4343W
 2020-09-09 09:49:19 +01:00
Wenn0101 68d59d3781 Add new targets, Ambiq Apollo3 and Sparkfun Electronics, SFE, boards 2020-09-09 01:13:05 -06:00
talorion b1eedc0a7c fixed order of operations 2020-09-08 17:08:06 +02:00
talorion 0361627c33 fixed order of operations 2020-09-08 16:53:29 +02:00
amq 6da9237f6f
Fix a typo in PeripheralPins.c for EFM32GG11 
- PF13 had the same value as PF15
 2020-09-08 12:04:32 +00:00
jeromecoutant b65afe028e STM32H7 ADC: clock selection lost after deepsleep 2020-09-08 11:40:02 +02:00
talorion e117ef5c3c use descriptive variable names 2020-09-08 10:54:09 +02:00
Robert 14ac4064b7 STM32Gx: LSI clock selection when LSE is not available 2020-09-07 14:47:11 +01:00
Martin Kojtal 1f735a63d9
Merge pull request #13536 from OpenNuvoton/nuvoton_fix_downgrade_qspi 
Nuvoton: Fix degrading QSPI to SPI
 2020-09-07 10:11:04 +01:00
jeromecoutant e650470206 STM32L4+ : SRAM3 is powered off in Stop 2 mode 
By default, SRAM3 content is then lost.
 2020-09-07 09:48:02 +02:00
Roman Okhrimenko 877078003c Rename CY8CKIT_064B0S2_4343W to CY8CKIT064B0S2_4343W, which fits in 20 characters limit 2020-09-07 08:25:31 +03:00
Martin Eckardt 08ce2f2de8 Calculate FDCAN_clk instead of assuming fix 10MHz 
- The FDCAN_clk is calculated on runtime from the according
RCC-registers
 2020-09-07 02:08:59 +02:00
Martin Eckardt f32efe4c28 Changed PLL to 160MHz, PLLQ to 80MHz 2020-09-07 02:04:13 +02:00