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STMG4-sys-clk: If can PLLQ=160MHz, else 170MHz 

- with 170MHz as can-core-frequency, the accuracy for many baudrates is
too low. 160MHz is better for a broad range of frequencies
pull/13565/head
m-ecry 2020-09-14 18:13:15 +02:00
parent d0c8ad75e1
commit 2a13fa199d
1 changed files with 5 additions and 1 deletions
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6
targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c
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@ -105,9 +105,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6;
#if DEVICE_CAN
RCC_OscInitStruct.PLL.PLLN = 80;
#else
RCC_OscInitStruct.PLL.PLLN = 85;
#endif
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL