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Add new targets, Ambiq Apollo3 and Sparkfun Electronics, SFE, boards

pull/13538/head
Wenn0101 2020-09-09 01:13:05 -06:00
parent 7f60090ddb
commit 68d59d3781
195 changed files with 113126 additions and 0 deletions
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96
connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp Normal file
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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "AP3CordioHCIDriver.h"
#include "AP3CordioHCITransportDriver.h"
#include "am_mcu_apollo.h"
#include "stdio.h"
#include <cstring>
#include "wsf_types.h"
#include "wsf_timer.h"
#include "bstream.h"
#include "wsf_msg.h"
#include "wsf_cs.h"
#include "hci_drv_apollo3.h"
using namespace ble;
AP3CordioHCIDriver::AP3CordioHCIDriver(CordioHCITransportDriver &transport_driver)
: CordioHCIDriver(transport_driver)
{
AP3CordioHCITransportDriver *p_trspt_drv = (AP3CordioHCITransportDriver *)&transport_driver;
_ptr_to_handle = &p_trspt_drv->handle;
}
AP3CordioHCIDriver::~AP3CordioHCIDriver() {}
void AP3CordioHCIDriver::do_initialize()
{
#ifdef USE_AMBIQ_DRIVER
HciDrvRadioBoot(true);
#else
MBED_ASSERT(*_ptr_to_handle);
_ble_config = am_hal_ble_default_config;
MBED_ASSERT(am_hal_ble_power_control(*_ptr_to_handle, AM_HAL_BLE_POWER_ACTIVE) == AM_HAL_STATUS_SUCCESS);
MBED_ASSERT(am_hal_ble_config(*_ptr_to_handle, &_ble_config) == AM_HAL_STATUS_SUCCESS);
MBED_ASSERT(am_hal_ble_boot(*_ptr_to_handle) == AM_HAL_STATUS_SUCCESS);
MBED_ASSERT(am_hal_ble_tx_power_set(*_ptr_to_handle, 0x0F) == AM_HAL_STATUS_SUCCESS);
MBED_ASSERT(am_hal_ble_sleep_set(*_ptr_to_handle, false) == AM_HAL_STATUS_SUCCESS);
am_hal_ble_int_enable(*_ptr_to_handle, (AP3_STUPID_DEF_OF_BLECIRQ_BIT | AM_HAL_BLE_INT_ICMD | AM_HAL_BLE_INT_BLECSSTAT));
NVIC_EnableIRQ(BLE_IRQn);
#endif
}
void AP3CordioHCIDriver::do_terminate()
{
#ifdef USE_AMBIQ_DRIVER
HciDrvRadioShutdown();
#else
am_hal_ble_power_control(*_ptr_to_handle, AM_HAL_BLE_POWER_OFF);
#endif
}
ble::buf_pool_desc_t AP3CordioHCIDriver::get_buffer_pool_description()
{
static union {
uint8_t buffer[9000];
uint64_t align;
};
static const wsfBufPoolDesc_t pool_desc[] = {
{16, 64},
{32, 64},
{64, 32},
{128, 16},
{272, 4}};
return buf_pool_desc_t(buffer, pool_desc);
}
ble::CordioHCIDriver &ble_cordio_get_hci_driver()
{
static AP3CordioHCITransportDriver transport_driver;
static AP3CordioHCIDriver hci_driver(transport_driver);
return hci_driver;
}

53
connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h Normal file
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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef APOLLO3_CORDIO_HCI_DRIVER_H_
#define APOLLO3_CORDIO_HCI_DRIVER_H_
#include "CordioHCIDriver.h"
#include "am_mcu_apollo.h"
namespace ble
{
class AP3CordioHCIDriver : public CordioHCIDriver
{
public:
AP3CordioHCIDriver(
CordioHCITransportDriver &transport_driver
/* specific constructor arguments*/);
virtual ~AP3CordioHCIDriver();
virtual void do_initialize();
virtual void do_terminate();
virtual ble::buf_pool_desc_t get_buffer_pool_description();
private:
void **_ptr_to_handle;
am_hal_ble_config_t _ble_config;
};
} // namespace ble
#endif /* APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ */

142
connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp Normal file
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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "AP3CordioHCITransportDriver.h"
#include "am_mcu_apollo.h"
#include "stdio.h"
#include <cstring>
#include "wsf_types.h"
#include "wsf_timer.h"
#include "bstream.h"
#include "wsf_msg.h"
#include "wsf_cs.h"
#include "hci_drv_apollo3.h"
#define PRINT_DEBUG_HCI 0
#if PRINT_DEBUG_HCI
#include "mbed.h"
DigitalOut debugGPIO(D28, 0);
DigitalOut debugGPIO2(D25, 0);
#endif
using namespace ble;
#ifndef USE_AMBIQ_DRIVER
static uint8_t ample_buffer[256];
void *ble_handle = NULL;
#endif
AP3CordioHCITransportDriver::~AP3CordioHCITransportDriver() {}
void AP3CordioHCITransportDriver::initialize()
{
#ifdef USE_AMBIQ_DRIVER
wsfHandlerId_t handlerId = WsfOsSetNextHandler(HciDrvHandler);
HciDrvHandlerInit(handlerId);
#else
am_hal_ble_initialize(0, &handle);
ble_handle = handle;
#endif
}
void AP3CordioHCITransportDriver::terminate()
{
#ifdef USE_AMBIQ_DRIVER
#else
am_hal_ble_deinitialize(handle);
handle = NULL;
ble_handle = NULL;
#endif
}
uint16_t AP3CordioHCITransportDriver::write(uint8_t packet_type, uint16_t len, uint8_t *data)
{
#if PRINT_DEBUG_HCI
printf("sent tx packet_type: %02X data: ", packet_type);
for (int i = 0; i < len; i++)
{
printf(" %02X", data[i]);
}
printf("\r\n");
#endif
//Temporary workaround, random address not working, suppress it.
if (data[0] == 0x06 && data[1] == 0x20)
{
#if PRINT_DEBUG_HCI
printf("LE Set Advertising Params\r\n");
#endif
data[8] = 0;
}
uint16_t retLen = 0;
#ifdef USE_AMBIQ_DRIVER
retLen = ap3_hciDrvWrite(packet_type, len, data);
#else
if (handle)
{
uint16_t retVal = (uint16_t)am_hal_ble_blocking_hci_write(handle, packet_type, (uint32_t *)data, (uint16_t)len);
if (retVal == AM_HAL_STATUS_SUCCESS)
{
retLen = len;
}
}
#endif
#if CORDIO_ZERO_COPY_HCI
WsfMsgFree(data);
#endif
return retLen;
}
#ifdef USE_AMBIQ_DRIVER
//Ugly Mutlifile implementation
void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len)
{
#if PRINT_DEBUG_HCI
printf("data rx: ");
for (int i = 0; i < len; i++)
{
printf("%02X ", data[i]);
}
printf("\r\n");
#endif
CordioHCITransportDriver::on_data_received(data, len);
}
#else
extern "C" void HciDrvIntService(void)
{
uint32_t status = am_hal_ble_int_status(ble_handle, false);
if (status & AM_HAL_BLE_INT_BLECIRQ)
{
uint32_t len = 0;
am_hal_ble_blocking_hci_read(ble_handle, (uint32_t *)ample_buffer, &len);
CordioHCITransportDriver::on_data_received(ample_buffer, len);
}
am_hal_ble_int_clear(ble_handle, 0xFFFF);
}
#endif

55
connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h Normal file
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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_
#define APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_
#include "CordioHCITransportDriver.h"
#define AP3_STUPID_DEF_OF_BLECIRQ_BIT 0x00000080 // AM_BLEIF_INT_BLECIRQ
namespace ble
{
class AP3CordioHCITransportDriver : public CordioHCITransportDriver
{
public:
//AP3CordioHCITransportDriver(/* specific constructor arguments*/);
virtual ~AP3CordioHCITransportDriver();
virtual void initialize();
virtual void terminate();
virtual uint16_t write(uint8_t packet_type, uint16_t len, uint8_t *data);
void *handle;
private:
// private driver declarations
};
} // namespace ble
extern "C" void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len);
#endif /* APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ */

1330
connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c Normal file
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connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h Normal file
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//*****************************************************************************
//
//! @file hci_drv_apollo3.h
//!
//! @brief Support functions for the Nationz BTLE radio in Apollo3.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.3.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef HCI_DRV_APOLLO3_H
#define HCI_DRV_APOLLO3_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// NATIONZ vendor specific events
//
//*****************************************************************************
// Tx power level in dBm.
typedef enum
{
TX_POWER_LEVEL_MINUS_10P0_dBm = 0x3,
TX_POWER_LEVEL_0P0_dBm = 0x8,
TX_POWER_LEVEL_PLUS_3P0_dBm = 0xF,
TX_POWER_LEVEL_INVALID = 0x10,
} txPowerLevel_t;
#define HCI_DRV_SPECIFIC_ERROR_START 0x09000000
typedef enum
{
HCI_DRV_TRANSMIT_QUEUE_FULL = HCI_DRV_SPECIFIC_ERROR_START,
HCI_DRV_TX_PACKET_TOO_LARGE,
HCI_DRV_RX_PACKET_TOO_LARGE,
HCI_DRV_BLE_STACK_UNABLE_TO_ACCEPT_PACKET,
HCI_DRV_PACKET_TRANSMIT_FAILED,
HCI_DRV_IRQ_STUCK_HIGH,
HCI_DRV_TOO_MANY_PACKETS,
} hci_drv_error_t;
typedef void (*hci_drv_error_handler_t)(uint32_t ui32Error);
bool_t HciVsA3_SetRfPowerLevelEx(txPowerLevel_t txPowerlevel);
void HciVsA3_ConstantTransmission(uint8_t txchannel);
void HciVsA3_CarrierWaveMode(uint8_t txchannel);
//*****************************************************************************
//
// Hci driver functions unique to Apollo3
//
//*****************************************************************************
extern void HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg);
extern void HciDrvHandlerInit(wsfHandlerId_t handlerId);
extern void HciDrvIntService(void);
uint16_t ap3_hciDrvWrite(uint8_t type, uint16_t len, uint8_t *pData);
extern void HciDrvRadioBoot(bool bColdBoot);
extern void HciDrvRadioShutdown(void);
#ifdef __cplusplus
};
#endif
#endif // HCI_DRV_APOLLO3_H

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c Normal file
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/*
SPDX-License-Identifier: Beerware
"THE BEER-WARE LICENSE" (Revision 42):
<owen.lyke@sparkfun.com> added this file. As long as you retain this notice you
can do whatever you want with this stuff. If we meet some day, and you think
this stuff is worth it, you can buy me a beer in return
Owen Lyke
*/
//*****************************************************************************
//
//! @file HM01B0.c
//!
//
//*****************************************************************************
#include "am_mcu_apollo.h"
#include "am_bsp.h"
#include "am_util.h"
#include "HM01B0.h"
#include "HM01B0_Walking1s_01.h"
#include "platform.h"
#define read_vsync() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_VSYNC))
#define read_hsync() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_HSYNC))
#define read_pclk() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_PCLK))
#define read_byte() (APBDMA->BBINPUT)
const am_hal_gpio_pincfg_t g_HM01B0_pin_int =
{
.uFuncSel = 3,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE,
.eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN
};
//*****************************************************************************
//
//! @brief Write HM01B0 registers
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui16Reg - Register address.
//! @param pui8Value - Pointer to the data to be written.
//! @param ui32NumBytes - Length of the data in bytes to be written.
//!
//! This function writes value to HM01B0 registers.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_write_reg(hm01b0_cfg_t *psCfg, \
uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes)
{
am_hal_iom_transfer_t Transaction;
//
// Create the transaction.
//
Transaction.ui32InstrLen = sizeof(uint16_t);
Transaction.ui32Instr = (ui16Reg & 0x0000FFFF);
Transaction.eDirection = AM_HAL_IOM_TX;
Transaction.ui32NumBytes = ui32NumBytes;
Transaction.pui32TxBuffer = (uint32_t *) pui8Value;
Transaction.uPeerInfo.ui32I2CDevAddr = (uint32_t) psCfg->ui16SlvAddr;
Transaction.bContinue = false;
Transaction.ui8RepeatCount = 0;
Transaction.ui32PauseCondition = 0;
Transaction.ui32StatusSetClr = 0;
//
// Execute the transction over IOM.
//
if (am_hal_iom_blocking_transfer(psCfg->pIOMHandle, &Transaction))
{
return HM01B0_ERR_I2C;
}
return HM01B0_ERR_OK;
}
//*****************************************************************************
//
//! @brief Read HM01B0 registers
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui16Reg - Register address.
//! @param pui8Value - Pointer to the buffer for read data to be put into.
//! @param ui32NumBytes - Length of the data to be read.
//!
//! This function reads value from HM01B0 registers.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_read_reg(hm01b0_cfg_t *psCfg, \
uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes)
{
am_hal_iom_transfer_t Transaction;
//
// Create the transaction.
//
Transaction.ui32InstrLen = sizeof(uint16_t);
Transaction.ui32Instr = (ui16Reg & 0x0000FFFF);
Transaction.eDirection = AM_HAL_IOM_RX;
Transaction.ui32NumBytes = ui32NumBytes;
Transaction.pui32RxBuffer = (uint32_t *) pui8Value;;
Transaction.uPeerInfo.ui32I2CDevAddr = (uint32_t) psCfg->ui16SlvAddr;
Transaction.bContinue = false;
Transaction.ui8RepeatCount = 0;
Transaction.ui32PauseCondition = 0;
Transaction.ui32StatusSetClr = 0;
//
// Execute the transction over IOM.
//
if (am_hal_iom_blocking_transfer(psCfg->pIOMHandle, &Transaction))
{
return HM01B0_ERR_I2C;
}
return HM01B0_ERR_OK;
}
//*****************************************************************************
//
//! @brief Load HM01B0 a given script
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psScrip - Pointer to the script to be loaded.
//! @param ui32ScriptCmdNum - Number of entries in a given script.
//!
//! This function loads HM01B0 a given script.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_load_script(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum)
{
uint32_t ui32Err = HM01B0_ERR_OK;
for (uint32_t idx = 0; idx < ui32ScriptCmdNum; idx++)
{
ui32Err = hm01b0_write_reg(psCfg, \
(psScript + idx)->ui16Reg, \
&((psScript + idx)->ui8Val), \
sizeof(uint8_t));
if (ui32Err != HM01B0_ERR_OK)
{
break;
}
}
return ui32Err;
}
//*****************************************************************************
//
//! @brief Power up HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function powers up HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_power_up(hm01b0_cfg_t *psCfg)
{
// place holder
}
//*****************************************************************************
//
//! @brief Power down HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function powers up HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_power_down(hm01b0_cfg_t *psCfg)
{
// place holder
}
//*****************************************************************************
//
//! @brief Enable MCLK
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function utilizes CTimer to generate MCLK for HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_mclk_enable(hm01b0_cfg_t *psCfg)
{
#define MCLK_UI64PATTERN 0x55555555
#define MCLK_UI64PATTERNLEN 31
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
//
// Set up timer.
//
am_hal_ctimer_clear(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment);
am_hal_ctimer_config_single(psCfg->ui32CTimerModule,
psCfg->ui32CTimerSegment,
(
AM_HAL_CTIMER_FN_PTN_REPEAT |
AM_HAL_CTIMER_HFRC_12MHZ
)
);
//
// Set the pattern in the CMPR registers.
//
am_hal_ctimer_compare_set(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment, 0,
(uint32_t)(MCLK_UI64PATTERN & 0xFFFF));
am_hal_ctimer_compare_set(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment, 1,
(uint32_t)((MCLK_UI64PATTERN >> 16) & 0xFFFF));
//
// Set the timer trigger and pattern length.
//
am_hal_ctimer_config_trigger(psCfg->ui32CTimerModule,
psCfg->ui32CTimerSegment,
(
(MCLK_UI64PATTERNLEN << CTIMER_AUX0_TMRA0LMT_Pos) |
(CTIMER_AUX0_TMRB0TRIG_DIS << CTIMER_AUX0_TMRA0TRIG_Pos)
)
);
//
// Configure timer output pin.
//
am_hal_ctimer_output_config(psCfg->ui32CTimerModule,
psCfg->ui32CTimerSegment,
psCfg->ui32CTimerOutputPin,
AM_HAL_CTIMER_OUTPUT_NORMAL,
AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA);
//
// Start the timer.
//
am_hal_ctimer_start(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment);
}
//*****************************************************************************
//
//! @brief Disable MCLK
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function disable CTimer to stop MCLK for HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_mclk_disable(hm01b0_cfg_t *psCfg)
{
//
// Stop the timer.
//
am_hal_ctimer_stop(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment);
am_hal_gpio_pinconfig(psCfg->ui32CTimerOutputPin, g_AM_HAL_GPIO_DISABLE);
}
//*****************************************************************************
//
//! @brief Initialize interfaces
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function initializes interfaces.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_init_if(hm01b0_cfg_t *psCfg)
{
void *pIOMHandle = NULL;
if ( psCfg->ui32IOMModule > AM_REG_IOM_NUM_MODULES )
{
return HM01B0_ERR_I2C;
}
//
// Enable fault detection.
//
#if AM_APOLLO3_MCUCTRL
am_hal_mcuctrl_control(AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE, 0);
#else // AM_APOLLO3_MCUCTRL
am_hal_mcuctrl_fault_capture_enable();
#endif // AM_APOLLO3_MCUCTRL
//
// Initialize the IOM instance.
// Enable power to the IOM instance.
// Configure the IOM for Serial operation during initialization.
// Enable the IOM.
//
if (am_hal_iom_initialize(psCfg->ui32IOMModule, &pIOMHandle) ||
am_hal_iom_power_ctrl(pIOMHandle, AM_HAL_SYSCTRL_WAKE, false) ||
am_hal_iom_configure(pIOMHandle, &(psCfg->sIOMCfg)) ||
am_hal_iom_enable(pIOMHandle))
{
return HM01B0_ERR_I2C;
}
else
{
//
// Configure the IOM pins.
//
am_bsp_iom_pins_enable(psCfg->ui32IOMModule, psCfg->eIOMMode);
psCfg->pIOMHandle = pIOMHandle;
}
// initialize pins for camera parallel interface.
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD0);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD1);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD2);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD3);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD4);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD5);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD6);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD7);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD0);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD1);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD2);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD3);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD4);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD5);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD6);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD7);
am_hal_gpio_fast_pinconfig((uint64_t)0x1 << psCfg->ui8PinD0 |
(uint64_t)0x1 << psCfg->ui8PinD1 |
(uint64_t)0x1 << psCfg->ui8PinD2 |
(uint64_t)0x1 << psCfg->ui8PinD3 |
(uint64_t)0x1 << psCfg->ui8PinD4 |
(uint64_t)0x1 << psCfg->ui8PinD5 |
(uint64_t)0x1 << psCfg->ui8PinD6 |
(uint64_t)0x1 << psCfg->ui8PinD7,
g_AM_HAL_GPIO_INPUT, 0);
am_hal_gpio_pinconfig(psCfg->ui8PinVSYNC, g_AM_HAL_GPIO_INPUT);
am_hal_gpio_pinconfig(psCfg->ui8PinHSYNC, g_AM_HAL_GPIO_INPUT);
am_hal_gpio_pinconfig(psCfg->ui8PinPCLK, g_AM_HAL_GPIO_INPUT);
am_hal_gpio_pinconfig(psCfg->ui8PinTrig, g_AM_HAL_GPIO_OUTPUT);
am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_AM_HAL_GPIO_DISABLE);
// am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_HM01B0_pin_int);
// am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(psCfg->ui8PinInt));
// am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(psCfg->ui8PinInt));
// NVIC_EnableIRQ(GPIO_IRQn);
return HM01B0_ERR_OK;
}
//*****************************************************************************
//
//! @brief Deinitialize interfaces
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function deinitializes interfaces.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_deinit_if(hm01b0_cfg_t *psCfg)
{
am_hal_iom_disable(psCfg->pIOMHandle);
am_hal_iom_uninitialize(psCfg->pIOMHandle);
am_hal_gpio_pinconfig(psCfg->ui8PinSCL, g_AM_HAL_GPIO_DISABLE);
am_hal_gpio_pinconfig(psCfg->ui8PinSDA, g_AM_HAL_GPIO_DISABLE);
// initialize pins for camera parallel interface.
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD0);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD1);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD2);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD3);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD4);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD5);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD6);
am_hal_gpio_fastgpio_disable(psCfg->ui8PinD7);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD0);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD1);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD2);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD3);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD4);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD5);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD6);
am_hal_gpio_fastgpio_clr(psCfg->ui8PinD7);
am_hal_gpio_pinconfig(psCfg->ui8PinVSYNC, g_AM_HAL_GPIO_DISABLE);
am_hal_gpio_pinconfig(psCfg->ui8PinHSYNC, g_AM_HAL_GPIO_DISABLE);
am_hal_gpio_pinconfig(psCfg->ui8PinPCLK, g_AM_HAL_GPIO_DISABLE);
am_hal_gpio_pinconfig(psCfg->ui8PinTrig, g_AM_HAL_GPIO_DISABLE);
am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_AM_HAL_GPIO_DISABLE);
return HM01B0_ERR_OK;
}
//*****************************************************************************
//
//! @brief Get HM01B0 Model ID
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param pui16MID - Pointer to buffer for the read back model ID.
//!
//! This function reads back HM01B0 model ID.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_get_modelid(hm01b0_cfg_t *psCfg, uint16_t *pui16MID)
{
uint8_t ui8Data[1];
uint32_t ui32Err;
*pui16MID = 0x0000;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODEL_ID_H, ui8Data, sizeof(ui8Data));
if (ui32Err == HM01B0_ERR_OK)
{
*pui16MID |= (ui8Data[0] << 8);
}
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODEL_ID_L, ui8Data, sizeof(ui8Data));
if (ui32Err == HM01B0_ERR_OK)
{
*pui16MID |= ui8Data[0];
}
return ui32Err;
}
//*****************************************************************************
//
//! @brief Initialize HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psScript - Pointer to HM01B0 initialization script.
//! @param ui32ScriptCmdNum - No. of commands in HM01B0 initialization script.
//!
//! This function initilizes HM01B0 with a given script.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_init_system(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum)
{
return hm01b0_load_script(psCfg, psScript, ui32ScriptCmdNum);
}
//*****************************************************************************
//
//! @brief Set HM01B0 in the walking 1s test mode
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function sets HM01B0 in the walking 1s test mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_test_walking1s(hm01b0_cfg_t *psCfg)
{
uint32_t ui32ScriptCmdNum = sizeof(sHM01b0TestModeScript_Walking1s) / sizeof(hm_script_t);
hm_script_t *psScript = (hm_script_t *)sHM01b0TestModeScript_Walking1s;
return hm01b0_load_script(psCfg, psScript, ui32ScriptCmdNum);
}
//*****************************************************************************
//
//! @brief Check the data read from HM01B0 in the walking 1s test mode
//!
//! @param pui8Buffer - Pointer to data buffer.
//! @param ui32BufferLen - Buffer length
//! @param ui32PrintCnt - Number of mismatched data to be printed out
//!
//! This function sets HM01B0 in the walking 1s test mode.
//!
//! @return Error code.
//
//*****************************************************************************
void hm01b0_test_walking1s_check_data_sanity(uint8_t *pui8Buffer, uint32_t ui32BufferLen, uint32_t ui32PrintCnt)
{
uint8_t ui8ByteData = *pui8Buffer;
uint32_t ui32MismatchCnt = 0x00;
for (uint32_t ui32Idx = 0; ui32Idx < ui32BufferLen; ui32Idx++)
{
if (*(pui8Buffer + ui32Idx) != ui8ByteData)
{
if (ui32PrintCnt)
{
am_util_stdio_printf("[0x%08X] actual 0x%02X expected 0x%02X\n", ui32Idx, *(pui8Buffer + ui32Idx), ui8ByteData);
am_util_delay_ms(1);
ui32PrintCnt--;
}
ui32MismatchCnt++;
}
if (ui8ByteData)
ui8ByteData = ui8ByteData << 1;
else
ui8ByteData = 0x01;
}
am_util_stdio_printf("Mismatch Rate %d/%d\n", ui32MismatchCnt, ui32BufferLen);
}
//*****************************************************************************
//
//! @brief Software reset HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function resets HM01B0 by issuing a reset command.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_reset_sw(hm01b0_cfg_t *psCfg)
{
uint8_t ui8Data[1] = {0x00};
return hm01b0_write_reg(psCfg, HM01B0_REG_SW_RESET, ui8Data, sizeof(ui8Data));
}
//*****************************************************************************
//
//! @brief Get current HM01B0 operation mode.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param pui8Mode - Pointer to buffer
//! - for the read back operation mode to be put into
//!
//! This function get HM01B0 operation mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_get_mode(hm01b0_cfg_t *psCfg, uint8_t *pui8Mode)
{
uint8_t ui8Data[1] = {0x01};
uint32_t ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODE_SELECT, ui8Data, sizeof(ui8Data));
*pui8Mode = ui8Data[0];
return ui32Err;
}
//*****************************************************************************
//
//! @brief Set HM01B0 operation mode.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui8Mode - Operation mode. One of:
//! HM01B0_REG_MODE_SELECT_STANDBY
//! HM01B0_REG_MODE_SELECT_STREAMING
//! HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES
//! HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER
//! @param ui8FrameCnt - Frame count for HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES.
//! - Discarded if other modes.
//!
//! This function set HM01B0 operation mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_set_mode(hm01b0_cfg_t *psCfg, uint8_t ui8Mode, uint8_t ui8FrameCnt)
{
uint32_t ui32Err = HM01B0_ERR_OK;
if (ui8Mode == HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES)
{
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_PMU_PROGRAMMABLE_FRAMECNT, &ui8FrameCnt, sizeof(ui8FrameCnt));
}
if(ui32Err == HM01B0_ERR_OK)
{
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_MODE_SELECT, &ui8Mode, sizeof(ui8Mode));
}
return ui32Err;
}
//*****************************************************************************
//
//! @brief Activate the updated settings to HM01B0.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! Some settings updated to HM01B0 will only be affected after calling this function
//! 1. AE settings
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_cmd_update(hm01b0_cfg_t *psCfg)
{
uint8_t ui8Data = HM01B0_REG_GRP_PARAM_HOLD_HOLD;
return hm01b0_write_reg(psCfg, HM01B0_REG_GRP_PARAM_HOLD, &ui8Data, sizeof(ui8Data));
}
//*****************************************************************************
//
//! @brief Get HM01B0 AE convergance
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psAECfg - Pointer to the structure hm01b0_ae_cfg_t.
//!
//! This function checks if AE is converged or not and returns ui32Err accordingly.
//! If caller needs detailed AE settings, psAECfg has to be non NULL.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_get_ae(hm01b0_cfg_t *psCfg, hm01b0_ae_cfg_t *psAECfg)
{
uint32_t ui32Err = HM01B0_ERR_OK;
uint8_t ui8AETargetMean;
uint8_t ui8AEMinMean;
uint8_t ui8AEMean;
uint8_t ui8ConvergeInTh;
uint8_t ui8ConvergeOutTh;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_AE_TARGET_MEAN, &ui8AETargetMean, sizeof(ui8AETargetMean));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_AE_MIN_MEAN, &ui8AEMinMean, sizeof(ui8AEMinMean));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_CONVERGE_IN_TH, &ui8ConvergeInTh, sizeof(ui8ConvergeInTh));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_CONVERGE_OUT_TH, &ui8ConvergeOutTh, sizeof(ui8ConvergeOutTh));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, 0x2020, &ui8AEMean, sizeof(ui8AEMean));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
if ((ui8AEMean < (ui8AETargetMean - ui8ConvergeInTh)) || (ui8AEMean > (ui8AETargetMean + ui8ConvergeInTh)))
ui32Err = HM01B0_ERR_AE_NOT_CONVERGED;
if (psAECfg)
{
psAECfg->ui8AETargetMean = ui8AETargetMean;
psAECfg->ui8AEMinMean = ui8AEMinMean;
psAECfg->ui8ConvergeInTh = ui8ConvergeInTh;
psAECfg->ui8ConvergeOutTh = ui8ConvergeOutTh;
psAECfg->ui8AEMean = ui8AEMean;
}
return ui32Err;
}
//*****************************************************************************
//
//! @brief AE calibration.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui8CalFrames - Frame counts for calibratoin.
//! @param pui8Buffer - Pointer to the frame buffer.
//! @param ui32BufferLen - Framebuffer size.
//!
//! This function lets HM01B0 AE settled as much as possible within a given frame counts.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_cal_ae(hm01b0_cfg_t *psCfg, uint8_t ui8CalFrames, uint8_t *pui8Buffer, uint32_t ui32BufferLen)
{
uint32_t ui32Err = HM01B0_ERR_OK;
hm01b0_ae_cfg_t sAECfg;
am_util_stdio_printf("[%s] +\n", __func__);
hm01b0_set_mode(psCfg, HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES, ui8CalFrames);
for (uint8_t i = 0; i < ui8CalFrames; i++)
{
hm01b0_blocking_read_oneframe(psCfg, pui8Buffer, ui32BufferLen);
ui32Err = hm01b0_get_ae(psCfg, &sAECfg);
am_util_stdio_printf("AE Calibration(0x%02X) TargetMean 0x%02X, ConvergeInTh 0x%02X, AEMean 0x%02X\n", \
ui32Err, sAECfg.ui8AETargetMean, sAECfg.ui8ConvergeInTh, sAECfg.ui8AEMean);
// if AE calibration is done in ui8CalFrames, just exit to save some time.
if (ui32Err == HM01B0_ERR_OK)
break;
}
hm01b0_set_mode(psCfg, HM01B0_REG_MODE_SELECT_STANDBY, 0);
am_util_stdio_printf("[%s] -\n", __func__);
return ui32Err;
}
//*****************************************************************************
//
//! @brief Save HM01B0 exposure gain settings.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t
//!
//! This function saves HM01B0 exposure gain settings.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_save_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl)
{
uint32_t ui32Err = HM01B0_ERR_OK;
uint8_t ui8IntegrationH;
uint8_t ui8IntegrationL;
uint8_t ui8AGain;
uint8_t ui8DGain_H;
uint8_t ui8DGain_L;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_INTEGRATION_H, &ui8IntegrationH, sizeof(ui8IntegrationH));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_INTEGRATION_L, &ui8IntegrationL, sizeof(ui8IntegrationL));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8AGain, sizeof(ui8AGain));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8DGain_H, sizeof(ui8DGain_H));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8DGain_L, sizeof(ui8DGain_L));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
if (psExpoGainCtrl)
{
psExpoGainCtrl->ui8IntegrationH = ui8IntegrationH;
psExpoGainCtrl->ui8IntegrationL = ui8IntegrationL;
psExpoGainCtrl->ui8AGain = ui8AGain;
psExpoGainCtrl->ui8DGain_H = ui8DGain_H;
psExpoGainCtrl->ui8DGain_L = ui8DGain_L;
}
return ui32Err;
}
//*****************************************************************************
//
//! @brief Restore HM01B0 exposure gain settings.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t
//!
//! This function restores HM01B0 exposure gain settings. The call flow shall be
//! hm01b0_restore_exposure_gains() -> hm01b0_cmd_update() -> hm01b0_set_mode()
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_restore_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl)
{
uint32_t ui32Err = HM01B0_ERR_OK;
uint8_t ui8Tmp;
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_INTEGRATION_H, &(psExpoGainCtrl->ui8IntegrationH), sizeof(psExpoGainCtrl->ui8IntegrationH));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_INTEGRATION_L, &(psExpoGainCtrl->ui8IntegrationL), sizeof(psExpoGainCtrl->ui8IntegrationL));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8Tmp, sizeof(ui8Tmp));
ui8Tmp = (ui8Tmp & ~(0x7 << 4)) | (psExpoGainCtrl->ui8AGain & (0x7 << 4));
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8Tmp, sizeof(ui8Tmp));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8Tmp, sizeof(ui8Tmp));
ui8Tmp = (ui8Tmp & ~(0x3 << 0)) | (psExpoGainCtrl->ui8DGain_H & (0x3 << 0));
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8Tmp, sizeof(ui8Tmp));
if (ui32Err != HM01B0_ERR_OK) return ui32Err;
ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8Tmp, sizeof(ui8Tmp));
ui8Tmp = (ui8Tmp & ~(0x3F << 2)) | (psExpoGainCtrl->ui8DGain_L & (0x3F << 2));
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8Tmp, sizeof(ui8Tmp));
return ui32Err;
}
//*****************************************************************************
//
//! @brief Hardware trigger HM01B0 to stream.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param bTrigger - True to start streaming
//! - False to stop streaming
//!
//! This function triggers HM01B0 to stream by toggling the TRIG pin.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_hardware_trigger_streaming(hm01b0_cfg_t *psCfg, bool bTrigger)
{
uint32_t ui32Err = HM01B0_ERR_OK;
uint8_t ui8Mode;
ui32Err = hm01b0_get_mode(psCfg, &ui8Mode);
if (ui32Err != HM01B0_ERR_OK)
goto end;
if (ui8Mode != HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER)
{
ui32Err = HM01B0_ERR_MODE;
goto end;
}
if (bTrigger)
{
am_hal_gpio_output_set(psCfg->ui8PinTrig);
}
else
{
am_hal_gpio_output_clear(psCfg->ui8PinTrig);
}
end:
return ui32Err;
}
//*****************************************************************************
//
//! @brief Set HM01B0 mirror mode.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param bHmirror - Horizontal mirror
//! @param bVmirror - Vertical mirror
//!
//! This function set HM01B0 mirror mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_set_mirror(hm01b0_cfg_t *psCfg, bool bHmirror, bool bVmirror)
{
uint8_t ui8Data = 0x00;
uint32_t ui32Err = HM01B0_ERR_OK;
if (bHmirror)
{
ui8Data |= HM01B0_REG_IMAGE_ORIENTATION_HMIRROR;
}
if (bVmirror)
{
ui8Data |= HM01B0_REG_IMAGE_ORIENTATION_VMIRROR;
}
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_IMAGE_ORIENTATION, &ui8Data, sizeof(ui8Data));
if (ui32Err == HM01B0_ERR_OK)
{
ui8Data = HM01B0_REG_GRP_PARAM_HOLD_HOLD;
ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_GRP_PARAM_HOLD, &ui8Data, sizeof(ui8Data));
}
return ui32Err;
}
//*****************************************************************************
//
//! @brief Read data of one frame from HM01B0.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param pui8Buffer - Pointer to the frame buffer.
//! @param ui32BufferLen - Framebuffer size.
//!
//! This function read data of one frame from HM01B0.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_blocking_read_oneframe(hm01b0_cfg_t *psCfg, uint8_t *pui8Buffer, uint32_t ui32BufferLen)
{
uint32_t ui32Err = HM01B0_ERR_OK;
uint32_t ui32Idx = 0x00;
am_util_stdio_printf("[%s] +\n", __func__);
uint32_t ui32HsyncCnt = 0x00;
while((ui32HsyncCnt < HM01B0_PIXEL_Y_NUM))
{
while (0x00 == read_hsync());
// read one row
while(read_hsync())
{
while(0x00 == read_pclk());
*(pui8Buffer + ui32Idx++) = read_byte();
if (ui32Idx == ui32BufferLen) {
goto end;
}
while(read_pclk());
}
ui32HsyncCnt++;
}
end:
am_util_stdio_printf("[%s] - Byte Counts %d\n", __func__, ui32Idx);
return ui32Err;
}

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/*
SPDX-License-Identifier: Beerware
"THE BEER-WARE LICENSE" (Revision 42):
<owen.lyke@sparkfun.com> added this file. As long as you retain this notice you
can do whatever you want with this stuff. If we meet some day, and you think
this stuff is worth it, you can buy me a beer in return
Owen Lyke
*/
//*****************************************************************************
//
//! @file HM01B0.h
//
//*****************************************************************************
#ifndef HM01B0_H
#define HM01B0_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "am_mcu_apollo.h"
#include "am_bsp.h"
#include "am_util.h"
#define HM01B0_DRV_VERSION (0)
#define HM01B0_DRV_SUBVERSION (5)
#define HM01B0_DEFAULT_ADDRESS (0x24)
#define HM01B0_PIXEL_X_NUM (324)
#define HM01B0_PIXEL_Y_NUM (244)
#define HM01B0_REG_MODEL_ID_H (0x0000)
#define HM01B0_REG_MODEL_ID_L (0x0001)
#define HM01B0_REG_SILICON_REV (0x0002)
#define HM01B0_REG_FRAME_COUNT (0x0005)
#define HM01B0_REG_PIXEL_ORDER (0x0006)
#define HM01B0_REG_MODE_SELECT (0x0100)
#define HM01B0_REG_IMAGE_ORIENTATION (0x0101)
#define HM01B0_REG_SW_RESET (0x0103)
#define HM01B0_REG_GRP_PARAM_HOLD (0x0104)
#define HM01B0_REG_INTEGRATION_H (0x0202)
#define HM01B0_REG_INTEGRATION_L (0x0203)
#define HM01B0_REG_ANALOG_GAIN (0x0205)
#define HM01B0_REG_DIGITAL_GAIN_H (0x020E)
#define HM01B0_REG_DIGITAL_GAIN_L (0x020F)
#define HM01B0_REG_AE_TARGET_MEAN (0x2101)
#define HM01B0_REG_AE_MIN_MEAN (0x2102)
#define HM01B0_REG_CONVERGE_IN_TH (0x2103)
#define HM01B0_REG_CONVERGE_OUT_TH (0x2104)
#define HM01B0_REG_I2C_ID_SEL (0x3400)
#define HM01B0_REG_I2C_ID_REG (0x3401)
#define HM01B0_REG_PMU_PROGRAMMABLE_FRAMECNT (0x3020)
// #define HM01B0_REG_MODE_SELECT (0x0100)
#define HM01B0_REG_MODE_SELECT_STANDBY (0x00)
#define HM01B0_REG_MODE_SELECT_STREAMING (0x01)
#define HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES (0x03)
#define HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER (0x05)
// #define HM01B0_REG_IMAGE_ORIENTATION (0x0101)
#define HM01B0_REG_IMAGE_ORIENTATION_DEFAULT (0x00)
#define HM01B0_REG_IMAGE_ORIENTATION_HMIRROR (0x01)
#define HM01B0_REG_IMAGE_ORIENTATION_VMIRROR (0x02)
#define HM01B0_REG_IMAGE_ORIENTATION_HVMIRROR (HM01B0_REG_IMAGE_ORIENTATION_HMIRROR | HM01B0_REG_IMAGE_ORIENTATION_HVMIRROR)
// #define HM01B0_REG_GRP_PARAM_HOLD (0x0104)
#define HM01B0_REG_GRP_PARAM_HOLD_CONSUME (0x00)
#define HM01B0_REG_GRP_PARAM_HOLD_HOLD (0x01)
enum
{
HM01B0_ERR_OK = 0x00,
HM01B0_ERR_I2C,
HM01B0_ERR_MODE,
HM01B0_ERR_AE_NOT_CONVERGED,
};
typedef struct
{
uint16_t ui16Reg;
uint8_t ui8Val;
} hm_script_t;
typedef struct
{
uint16_t ui16SlvAddr;
am_hal_iom_mode_e eIOMMode;
uint32_t ui32IOMModule;
am_hal_iom_config_t sIOMCfg;
void *pIOMHandle;
uint32_t ui32CTimerModule;
uint32_t ui32CTimerSegment;
uint32_t ui32CTimerOutputPin;
uint8_t ui8PinSCL;
uint8_t ui8PinSDA;
uint8_t ui8PinD0;
uint8_t ui8PinD1;
uint8_t ui8PinD2;
uint8_t ui8PinD3;
uint8_t ui8PinD4;
uint8_t ui8PinD5;
uint8_t ui8PinD6;
uint8_t ui8PinD7;
uint8_t ui8PinVSYNC;
uint8_t ui8PinHSYNC;
uint8_t ui8PinPCLK;
uint8_t ui8PinTrig;
uint8_t ui8PinInt;
void (*pfnGpioIsr)(void);
} hm01b0_cfg_t;
typedef struct
{
uint8_t ui8AETargetMean;
uint8_t ui8AEMinMean;
uint8_t ui8ConvergeInTh;
uint8_t ui8ConvergeOutTh;
uint8_t ui8AEMean;
} hm01b0_ae_cfg_t;
typedef struct
{
uint8_t ui8IntegrationH;
uint8_t ui8IntegrationL;
uint8_t ui8AGain;
uint8_t ui8DGain_H;
uint8_t ui8DGain_L;
} hm01b0_snr_expo_gain_ctrl_t;
//*****************************************************************************
//
//! @brief Write HM01B0 registers
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui16Reg - Register address.
//! @param pui8Value - Pointer to the data to be written.
//! @param ui32NumBytes - Length of the data in bytes to be written.
//!
//! This function writes value to HM01B0 registers.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_write_reg(hm01b0_cfg_t *psCfg, \
uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes);
//*****************************************************************************
//
//! @brief Read HM01B0 registers
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui16Reg - Register address.
//! @param pui8Value - Pointer to the buffer for read data to be put into.
//! @param ui32NumBytes - Length of the data to be read.
//!
//! This function reads value from HM01B0 registers.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_read_reg(hm01b0_cfg_t *psCfg, \
uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes);
//*****************************************************************************
//
//! @brief Load HM01B0 a given script
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psScrip - Pointer to the script to be loaded.
//! @param ui32ScriptCmdNum - Number of entries in a given script.
//!
//! This function loads HM01B0 a given script.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_load_script(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum);
//*****************************************************************************
//
//! @brief Power up HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function powers up HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_power_up(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Power down HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function powers up HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_power_down(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Enable MCLK
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function utilizes CTimer to generate MCLK for HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_mclk_enable(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Disable MCLK
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function disable CTimer to stop MCLK for HM01B0.
//!
//! @return none.
//
//*****************************************************************************
void hm01b0_mclk_disable(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Initialize interfaces
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function initializes interfaces.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_init_if(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Deinitialize interfaces
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function deinitializes interfaces.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_deinit_if(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Get HM01B0 Model ID
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param pui16MID - Pointer to buffer for the read back model ID.
//!
//! This function reads back HM01B0 model ID.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_get_modelid(hm01b0_cfg_t *psCfg, uint16_t *pui16MID);
//*****************************************************************************
//
//! @brief Initialize HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psScript - Pointer to HM01B0 initialization script.
//! @param ui32ScriptCmdNum - No. of commands in HM01B0 initialization script.
//!
//! This function initilizes HM01B0 with a given script.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_init_system(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum);
//*****************************************************************************
//
//! @brief Set HM01B0 in the walking 1s test mode
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function sets HM01B0 in the walking 1s test mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_test_walking1s(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Check the data read from HM01B0 in the walking 1s test mode
//!
//! @param pui8Buffer - Pointer to data buffer.
//! @param ui32BufferLen - Buffer length
//! @param ui32PrintCnt - Number of mismatched data to be printed out
//!
//! This function sets HM01B0 in the walking 1s test mode.
//!
//! @return Error code.
//
//*****************************************************************************
void hm01b0_test_walking1s_check_data_sanity(uint8_t *pui8Buffer, uint32_t ui32BufferLen, uint32_t ui32PrintCnt);
//*****************************************************************************
//
//! @brief Software reset HM01B0
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! This function resets HM01B0 by issuing a reset command.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_reset_sw(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Get current HM01B0 operation mode.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param pui8Mode - Pointer to buffer
//! - for the read back operation mode to be put into
//!
//! This function get HM01B0 operation mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_get_mode(hm01b0_cfg_t *psCfg, uint8_t *pui8Mode);
//*****************************************************************************
//
//! @brief Set HM01B0 operation mode.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui8Mode - Operation mode. One of:
//! HM01B0_REG_MODE_SELECT_STANDBY
//! HM01B0_REG_MODE_SELECT_STREAMING
//! HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES
//! HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER
//! @param framecnt - Frame count for HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES.
//! - Discarded if other modes.
//!
//! This function set HM01B0 operation mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_set_mode(hm01b0_cfg_t *psCfg, uint8_t ui8Mode, uint8_t framecnt);
//*****************************************************************************
//
//! @brief Activate the updated settings to HM01B0.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//!
//! Some settings updated to HM01B0 will only be affected after calling this function
//! 1. AE settings
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_cmd_update(hm01b0_cfg_t *psCfg);
//*****************************************************************************
//
//! @brief Get HM01B0 AE settings
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psAECfg - Pointer to the structure hm01b0_ae_cfg_t.
//!
//! This function checks if AE is converged or not and returns ui32Err accordingly.
//! If caller needs detailed AE settings, psAECfg has to be non NULL.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_get_ae(hm01b0_cfg_t *psCfg, hm01b0_ae_cfg_t *psAECfg);
//*****************************************************************************
//
//! @brief AE calibration.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param ui8CalFrames - Frame counts for calibratoin.
//! @param pui8Buffer - Pointer to the frame buffer.
//! @param ui32BufferLen - Framebuffer size.
//!
//! This function lets HM01B0 AE settled as much as possible within a given frame counts.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_cal_ae(hm01b0_cfg_t *psCfg, uint8_t ui8CalFrames, uint8_t *pui8Buffer, uint32_t ui32BufferLen);
//*****************************************************************************
//
//! @brief Save HM01B0 exposure gain settings.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t
//!
//! This function saves HM01B0 exposure gain settings.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_save_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl);
//*****************************************************************************
//
//! @brief Restore HM01B0 exposure gain settings.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t
//!
//! This function restores HM01B0 exposure gain settings. The call flow shall be
//! hm01b0_restore_exposure_gains() -> hm01b0_cmd_update() -> hm01b0_set_mode()
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_restore_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl);
//*****************************************************************************
//
//! @brief Hardware trigger HM01B0 to stream.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param bTrigger - True to start streaming
//! - False to stop streaming
//!
//! This function triggers HM01B0 to stream by toggling the TRIG pin.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_hardware_trigger_streaming(hm01b0_cfg_t *psCfg, bool bTrigger);
//*****************************************************************************
//
//! @brief Set HM01B0 mirror mode.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param bHmirror - Horizontal mirror
//! @param bVmirror - Vertical mirror
//!
//! This function set HM01B0 mirror mode.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_set_mirror(hm01b0_cfg_t *psCfg, bool bHmirror, bool bVmirror);
//*****************************************************************************
//
//! @brief Read data of one frame from HM01B0.
//!
//! @param psCfg - Pointer to HM01B0 configuration structure.
//! @param pui8Buffer - Pointer to the frame buffer.
//! @param ui32BufferLen - Framebuffer size.
//!
//! This function read data of one frame from HM01B0.
//!
//! @return Error code.
//
//*****************************************************************************
uint32_t hm01b0_blocking_read_oneframe(hm01b0_cfg_t *psCfg, \
uint8_t *pui8Buffer, uint32_t ui32BufferLen);
#ifdef __cplusplus
}
#endif
#endif // AM_HAL_CTIMER_H

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/*
SPDX-License-Identifier: Beerware
"THE BEER-WARE LICENSE" (Revision 42):
<owen.lyke@sparkfun.com> added this file. As long as you retain this notice you
can do whatever you want with this stuff. If we meet some day, and you think
this stuff is worth it, you can buy me a beer in return
Owen Lyke
*/
#include "HM01B0.h"
const hm_script_t sHM01B0InitScript[] =
{
// ;*************************************************************************
// ; Sensor: HM01B0
// ; I2C ID: 24
// ; Resolution: 324x244
// ; Lens:
// ; Flicker:
// ; Frequency:
// ; Description: AE control enable
// ; 8-bit mode, LSB first
// ;
// ;
// ; Note:
// ;
// ; $Revision: 1338 $
// ; $Date:: 2017-04-11 15:43:45 +0800#$
// ;*************************************************************************
//
// // ---------------------------------------------------
// // HUB system initial
// // ---------------------------------------------------
// W 20 8A04 01 2 1
// W 20 8A00 22 2 1
// W 20 8A01 00 2 1
// W 20 8A02 01 2 1
// W 20 0035 93 2 1 ; [3]&[1] hub616 20bits in, [5:4]=1 mclk=48/2=24mhz
// W 20 0036 00 2 1
// W 20 0011 09 2 1
// W 20 0012 B6 2 1
// W 20 0014 08 2 1
// W 20 0015 98 2 1
// ;W 20 0130 16 2 1 ; 3m soc, signal buffer control
// ;W 20 0100 44 2 1 ; [6] hub616 20bits in
// W 20 0100 04 2 1 ; [6] hub616 20bits in
// W 20 0121 01 2 1 ; [0] Q1 Intf enable, [1]:4bit mode, [2] msb first, [3] serial mode
// W 20 0150 00 2 1 ;
// W 20 0150 04 2 1 ;
//
//
// //---------------------------------------------------
// // Initial
// //---------------------------------------------------
// W 24 0103 00 2 1 ; software reset-> was 0x22
{0x0103, 0x00,},
// W 24 0100 00 2 1; power up
{0x0100, 0x00,},
//
//
//
// //---------------------------------------------------
// // Analog
// //---------------------------------------------------
// L HM01B0_analog_setting.txt
{0x1003, 0x08,},
{0x1007, 0x08,},
{0x3044, 0x0A,},
{0x3045, 0x00,},
{0x3047, 0x0A,},
{0x3050, 0xC0,},
{0x3051, 0x42,},
{0x3052, 0x50,},
{0x3053, 0x00,},
{0x3054, 0x03,},
{0x3055, 0xF7,},
{0x3056, 0xF8,},
{0x3057, 0x29,},
{0x3058, 0x1F,},
{0x3059, 0x1E,},
{0x3064, 0x00,},
{0x3065, 0x04,},
//
//
// //---------------------------------------------------
// // Digital function
// //---------------------------------------------------
//
// // BLC
// W 24 1000 43 2 1 ; BLC_on, IIR
{0x1000, 0x43,},
// W 24 1001 40 2 1 ; [6] : BLC dithering en
{0x1001, 0x40,},
// W 24 1002 32 2 1 ; // blc_darkpixel_thd
{0x1002, 0x32,},
//
// // Dgain
// W 24 0350 7F 2 1 ; Dgain Control
{0x0350, 0x7F,},
//
// // BLI
// W 24 1006 01 2 1 ; [0] : bli enable
{0x1006, 0x01,},
//
// // DPC
// W 24 1008 00 2 1 ; [2:0] : DPC option 0: DPC off 1 : mono 3 : bayer1 5 : bayer2
{0x1008, 0x00,},
// W 24 1009 A0 2 1 ; cluster hot pixel th
{0x1009, 0xA0,},
// W 24 100A 60 2 1 ; cluster cold pixel th
{0x100A, 0x60,},
// W 24 100B 90 2 1 ; single hot pixel th
{0x100B, 0x90,},
// W 24 100C 40 2 1 ; single cold pixel th
{0x100C, 0x40,},
// //
// advance VSYNC by 1 row
{0x3022, 0x01,},
// W 24 1012 00 2 1 ; Sync. enable VSYNC shift
{0x1012, 0x01,},
//
// // ROI Statistic
// W 24 2000 07 2 1 ; [0] : AE stat en [1] : MD LROI stat en [2] : MD GROI stat en [3] : RGB stat ratio en [4] : IIR selection (1 -> 16, 0 -> 8)
{0x2000, 0x07,},
// W 24 2003 00 2 1 ; MD GROI 0 y start HB
{0x2003, 0x00,},
// W 24 2004 1C 2 1 ; MD GROI 0 y start LB
{0x2004, 0x1C,},
// W 24 2007 00 2 1 ; MD GROI 1 y start HB
{0x2007, 0x00,},
// W 24 2008 58 2 1 ; MD GROI 1 y start LB
{0x2008, 0x58,},
// W 24 200B 00 2 1 ; MD GROI 2 y start HB
{0x200B, 0x00,},
// W 24 200C 7A 2 1 ; MD GROI 2 y start LB
{0x200C, 0x7A,},
// W 24 200F 00 2 1 ; MD GROI 3 y start HB
{0x200F, 0x00,},
// W 24 2010 B8 2 1 ; MD GROI 3 y start LB
{0x2010, 0xB8,},
//
// W 24 2013 00 2 1 ; MD LRIO y start HB
{0x2013, 0x00,},
// W 24 2014 58 2 1 ; MD LROI y start LB
{0x2014, 0x58,},
// W 24 2017 00 2 1 ; MD LROI y end HB
{0x2017, 0x00,},
// W 24 2018 9B 2 1 ; MD LROI y end LB
{0x2018, 0x9B,},
//
// // AE
// W 24 2100 01 2 1 ; [0]: AE control enable
{0x2100, 0x01,},
// W 24 2104 07 2 1 ; converge out th
{0x2104, 0x07,},
// W 24 2105 0C 2 1 ; max INTG Hb
{0x2105, 0x0C,},
// W 24 2106 78 2 1 ; max INTG Lb
{0x2106, 0x78,},
// W 24 2108 03 2 1 ; max AGain in full
{0x2108, 0x03,},
// W 24 2109 03 2 1 ; max AGain in bin2
{0x2109, 0x03,},
// W 24 210B 80 2 1 ; max DGain
{0x210B, 0x80,},
// W 24 210F 00 2 1 ; FS 60Hz Hb
{0x210F, 0x00,},
// W 24 2110 85 2 1 ; FS 60Hz Lb
{0x2110, 0x85,},
// W 24 2111 00 2 1 ; Fs 50Hz Hb
{0x2111, 0x00,},
// W 24 2112 A0 2 1 ; FS 50Hz Lb
{0x2112, 0xA0,},
//
//
// // MD
// W 24 2150 03 2 1 ; [0] : MD LROI en [1] : MD GROI en
{0x2150, 0x03,},
//
//
// //---------------------------------------------------
// // frame rate : 5 FPS
// //---------------------------------------------------
// W 24 0340 0C 2 1 ; smia frame length Hb
{0x0340, 0x0C,},
// W 24 0341 7A 2 1 ; smia frame length Lb 3192
{0x0341, 0x7A,},
//
// W 24 0342 01 2 1 ; smia line length Hb
{0x0342, 0x01,},
// W 24 0343 77 2 1 ; smia line length Lb 375
{0x0343, 0x77,},
//
// //---------------------------------------------------
// // Resolution : QVGA 324x244
// //---------------------------------------------------
// W 24 3010 01 2 1 ; [0] : window mode 0 : full frame 324x324 1 : QVGA
{0x3010, 0x01,},
//
//
// W 24 0383 01 2 1 ;
{0x0383, 0x01,},
// W 24 0387 01 2 1 ;
{0x0387, 0x01,},
// W 24 0390 00 2 1 ;
{0x0390, 0x00,},
//
// //---------------------------------------------------
// // bit width Selection
// //---------------------------------------------------
// W 24 3011 70 2 1 ; [0] : 6 bit mode enable
{0x3011, 0x70,},
//
//
// W 24 3059 02 2 1 ; [7]: Self OSC En, [6]: 4bit mode, [5]: serial mode, [4:0]: keep value as 0x02
{0x3059, 0x02,},
// W 24 3060 01 2 1 ; [5]: gated_clock, [4]: msb first,
{0x3060, 0x20,},
// ; [3:2]: vt_reg_div -> div by 4/8/1/2
// ; [1;0]: vt_sys_div -> div by 8/4/2/1
//
//
{0x0101, 0x01,},
// //---------------------------------------------------
// // CMU update
// //---------------------------------------------------
//
// W 24 0104 01 2 1 ; was 0100
{0x0104, 0x01,},
//
//
//
// //---------------------------------------------------
// // Turn on rolling shutter
// //---------------------------------------------------
// W 24 0100 01 2 1 ; was 0005 ; mode_select 00 : standby - wait fir I2C SW trigger 01 : streaming 03 : output "N" frame, then enter standby 04 : standby - wait for HW trigger (level), then continuous video out til HW TRIG goes off 06 : standby - wait for HW trigger (edge), then output "N" frames then enter standby
{0x0100, 0x00,},
//
// ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
};

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/*
SPDX-License-Identifier: Beerware
"THE BEER-WARE LICENSE" (Revision 42):
<owen.lyke@sparkfun.com> added this file. As long as you retain this notice you
can do whatever you want with this stuff. If we meet some day, and you think
this stuff is worth it, you can buy me a beer in return
Owen Lyke
*/
#include "HM01B0.h"
const hm_script_t sHM01b0TestModeScript_Walking1s[] =
{
{0x2100, 0x00,}, //W 24 2100 00 2 1 ; AE
{0x1000, 0x00,}, //W 24 1000 00 2 1 ; BLC
{0x1008, 0x00,}, //W 24 1008 00 2 1 ; DPC
{0x0205, 0x00,}, //W 24 0205 00 2 1 ; AGain
{0x020E, 0x01,}, //W 24 020E 01 2 1 ; DGain
{0x020F, 0x00,}, //W 24 020F 00 2 1 ; DGain
{0x0601, 0x11,}, //W 24 0601 11 2 1 ; Test pattern
{0x0104, 0x01,}, //W 24 0104 01 2 1 ;
};

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/*
SPDX-License-Identifier: Beerware
"THE BEER-WARE LICENSE" (Revision 42):
<owen.lyke@sparkfun.com> added this file. As long as you retain this notice you
can do whatever you want with this stuff. If we meet some day, and you think
this stuff is worth it, you can buy me a beer in return
Owen Lyke
*/
#ifndef HM01B0_PLATFORM_H
#define HM01B0_PLATFORM_H
#ifdef __cplusplus
extern "C"
{
#endif
#define HM01B0_PIN_D0 AM_BSP_GPIO_CAMERA_HM01B0_D0
#define HM01B0_PIN_D1 AM_BSP_GPIO_CAMERA_HM01B0_D1
#define HM01B0_PIN_D2 AM_BSP_GPIO_CAMERA_HM01B0_D2
#define HM01B0_PIN_D3 AM_BSP_GPIO_CAMERA_HM01B0_D3
#define HM01B0_PIN_D4 AM_BSP_GPIO_CAMERA_HM01B0_D4
#define HM01B0_PIN_D5 AM_BSP_GPIO_CAMERA_HM01B0_D5
#define HM01B0_PIN_D6 AM_BSP_GPIO_CAMERA_HM01B0_D6
#define HM01B0_PIN_D7 AM_BSP_GPIO_CAMERA_HM01B0_D7
#define HM01B0_PIN_VSYNC AM_BSP_GPIO_CAMERA_HM01B0_VSYNC
#define HM01B0_PIN_HSYNC AM_BSP_GPIO_CAMERA_HM01B0_HSYNC
#define HM01B0_PIN_PCLK AM_BSP_GPIO_CAMERA_HM01B0_PCLK
#define HM01B0_PIN_SCL AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN
#define HM01B0_PIN_SDA AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN
// Some boards do not support TRIG or INT pins
#ifdef AM_BSP_GPIO_CAMERA_HM01B0_TRIG
#define HM01B0_PIN_TRIG AM_BSP_GPIO_CAMERA_HM01B0_TRIG
#endif // AM_BSP_GPIO_CAMERA_HM01B0_TRIG
#ifdef AM_BSP_GPIO_CAMERA_HM01B0_INT
#define HM01B0_PIN_INT AM_BSP_GPIO_CAMERA_HM01B0_INT
#endif // AM_BSP_GPIO_CAMERA_HM01B0_INT
// Define AP3B's CTIMER and output pin for HM01B0 MCLK generation
#define HM01B0_MCLK_GENERATOR_MOD AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD
#define HM01B0_MCLK_GENERATOR_SEG AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG
#define HM01B0_PIN_MCLK AM_BSP_CAMERA_HM01B0_MCLK_PIN
// Deifne I2C controller and SCL(pin8)/SDA(pin9) are configured automatically.
#define HM01B0_IOM_MODE AM_HAL_IOM_I2C_MODE
#define HM01B0_IOM_MODULE AM_BSP_CAMERA_HM01B0_I2C_IOM
#define HM01B0_I2C_CLOCK_FREQ AM_HAL_IOM_100KHZ
#ifdef __cplusplus
}
#endif
#endif // HM01B0_PLATFORM_H

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "lis2dh12_platform_apollo3.h"
/*
* @brief Write generic device register (platform dependent)
*
* @param handle customizable argument. In this examples is used in
* order to select the correct sensor bus handler.
* @param reg register to write
* @param bufp pointer to data to write in register reg
* @param len number of consecutive register to write
*
*/
int32_t lis2dh12_write_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len)
{
uint32_t retVal32 = 0;
lis2dh12_platform_apollo3_if_t* pif = (lis2dh12_platform_apollo3_if_t*)handle;
am_hal_iom_transfer_t iomTransfer = {0};
if( bufp == NULL ) { return AM_HAL_STATUS_FAIL; }
if( pif == NULL ) { return AM_HAL_STATUS_FAIL; }
if( pif->iomHandle == NULL) { return AM_HAL_STATUS_FAIL; }
// Set up transfer
iomTransfer.uPeerInfo.ui32I2CDevAddr = pif->addCS;
iomTransfer.ui32InstrLen = 1;
iomTransfer.ui32Instr = (reg | 0x80);
iomTransfer.ui32NumBytes = len;
iomTransfer.eDirection = AM_HAL_IOM_TX;
iomTransfer.pui32TxBuffer = (uint32_t*)bufp;
iomTransfer.pui32RxBuffer = NULL;
iomTransfer.bContinue = false;
if( pif->useSPI ){
// ToDo: Support SPI w/ CS assertion
}
// Send the transfer
retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer);
if( pif->useSPI ){
// ToDo: Support SPI / CS de-assertion
}
if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; }
return 0;
}
/*
* @brief Read generic device register (platform dependent)
*
* @param handle customizable argument. In this examples is used in
* order to select the correct sensor bus handler.
* @param reg register to read
* @param bufp pointer to buffer that store the data read
* @param len number of consecutive register to read
*
*/
int32_t lis2dh12_read_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len)
{
uint32_t retVal32 = 0;
lis2dh12_platform_apollo3_if_t* pif = (lis2dh12_platform_apollo3_if_t*)handle;
am_hal_iom_transfer_t iomTransfer = {0};
if( bufp == NULL ) { return AM_HAL_STATUS_FAIL; }
if( pif == NULL ) { return AM_HAL_STATUS_FAIL; }
if( pif->iomHandle == NULL) { return AM_HAL_STATUS_FAIL; }
// Set up first transfer
iomTransfer.uPeerInfo.ui32I2CDevAddr = pif->addCS;
iomTransfer.ui32InstrLen = 1;
iomTransfer.ui32Instr = (reg | 0x80);
iomTransfer.ui32NumBytes = 0;
iomTransfer.eDirection = AM_HAL_IOM_TX;
iomTransfer.bContinue = true;
if( pif->useSPI ){
// ToDo: Support SPI w/ CS assertion
}
// Send the first transfer
retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer);
if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; }
// Change direction, and add the rx buffer
iomTransfer.eDirection = AM_HAL_IOM_RX;
iomTransfer.pui32RxBuffer = (uint32_t*)bufp;
iomTransfer.ui32NumBytes = len;
iomTransfer.bContinue = false;
// Send the second transfer
retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer);
if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; }
return 0;
}

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _LIS2DH12_PLATFORM_APOLLO3_H_
#define _LIS2DH12_PLATFORM_APOLLO3_H_
#include "am_mcu_apollo.h"
#include "lis2dh12_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct _lis2dh12_platform_apollo3_if_t {
void* iomHandle; // IO Master instance
uint8_t addCS; // I2C mode: the 7-bit I2C address (either 0x18 or 0x19 depeding on SA0 pin)
// SPI mode: the Apollo3 pad to use for chip select
bool useSPI; // Set 'true' if using SPI mode, else 'false'
}lis2dh12_platform_apollo3_if_t;
int32_t lis2dh12_write_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len);
int32_t lis2dh12_read_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len);
#ifdef __cplusplus
}
#endif
#endif // _LIS2DH12_PLATFORM_APOLLO3_H_

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/*
******************************************************************************
* @file lis2dh12_reg.h
* @author Sensors Software Solution Team
* @brief This file contains all the functions prototypes for the
* lis2dh12_reg.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
// SPDX-License-Identifier: BSD-3-Clause
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DH12_REGS_H
#define LIS2DH12_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include <math.h>
/** @addtogroup LIS2DH12
* @{
*
*/
/** @defgroup LIS2DH12_sensors_common_types
* @{
*
*/
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
/**
* @defgroup axisXbitXX_t
* @brief These unions are useful to represent different sensors data type.
* These unions are not need by the driver.
*
* REMOVING the unions you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
typedef union{
int16_t i16bit[3];
uint8_t u8bit[6];
} axis3bit16_t;
typedef union{
int16_t i16bit;
uint8_t u8bit[2];
} axis1bit16_t;
typedef union{
int32_t i32bit[3];
uint8_t u8bit[12];
} axis3bit32_t;
typedef union{
int32_t i32bit;
uint8_t u8bit[4];
} axis1bit32_t;
/**
* @}
*
*/
typedef struct{
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
uint8_t bit3 : 1;
uint8_t bit4 : 1;
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
} bitwise_t;
#define PROPERTY_DISABLE (0U)
#define PROPERTY_ENABLE (1U)
#endif /* MEMS_SHARED_TYPES */
/**
* @}
*
*/
/** @addtogroup LIS3MDL_Interfaces_Functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
typedef int32_t (*lis2dh12_write_ptr)(void *, uint8_t, uint8_t*, uint16_t);
typedef int32_t (*lis2dh12_read_ptr) (void *, uint8_t, uint8_t*, uint16_t);
typedef struct {
/** Component mandatory fields **/
lis2dh12_write_ptr write_reg;
lis2dh12_read_ptr read_reg;
/** Customizable optional pointer **/
void *handle;
} lis2dh12_ctx_t;
/**
* @}
*
*/
/** @defgroup LIS2DH12_Infos
* @{
*
*/
/** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/
#define LIS2DH12_I2C_ADD_L 0x31U
#define LIS2DH12_I2C_ADD_H 0x33U
/** Device Identification (Who am I) **/
#define LIS2DH12_ID 0x33U
/**
* @}
*
*/
#define LIS2DH12_STATUS_REG_AUX 0x07U
typedef struct {
uint8_t not_used_01 : 2;
uint8_t tda : 1;
uint8_t not_used_02 : 3;
uint8_t tor : 1;
uint8_t not_used_03 : 1;
} lis2dh12_status_reg_aux_t;
#define LIS2DH12_OUT_TEMP_L 0x0CU
#define LIS2DH12_OUT_TEMP_H 0x0DU
#define LIS2DH12_WHO_AM_I 0x0FU
#define LIS2DH12_CTRL_REG0 0x1EU
typedef struct {
uint8_t not_used_01 : 7;
uint8_t sdo_pu_disc : 1;
} lis2dh12_ctrl_reg0_t;
#define LIS2DH12_TEMP_CFG_REG 0x1FU
typedef struct {
uint8_t not_used_01 : 6;
uint8_t temp_en : 2;
} lis2dh12_temp_cfg_reg_t;
#define LIS2DH12_CTRL_REG1 0x20U
typedef struct {
uint8_t xen : 1;
uint8_t yen : 1;
uint8_t zen : 1;
uint8_t lpen : 1;
uint8_t odr : 4;
} lis2dh12_ctrl_reg1_t;
#define LIS2DH12_CTRL_REG2 0x21U
typedef struct {
uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */
uint8_t fds : 1;
uint8_t hpcf : 2;
uint8_t hpm : 2;
} lis2dh12_ctrl_reg2_t;
#define LIS2DH12_CTRL_REG3 0x22U
typedef struct {
uint8_t not_used_01 : 1;
uint8_t i1_overrun : 1;
uint8_t i1_wtm : 1;
uint8_t not_used_02 : 1;
uint8_t i1_zyxda : 1;
uint8_t i1_ia2 : 1;
uint8_t i1_ia1 : 1;
uint8_t i1_click : 1;
} lis2dh12_ctrl_reg3_t;
#define LIS2DH12_CTRL_REG4 0x23U
typedef struct {
uint8_t sim : 1;
uint8_t st : 2;
uint8_t hr : 1;
uint8_t fs : 2;
uint8_t ble : 1;
uint8_t bdu : 1;
} lis2dh12_ctrl_reg4_t;
#define LIS2DH12_CTRL_REG5 0x24U
typedef struct {
uint8_t d4d_int2 : 1;
uint8_t lir_int2 : 1;
uint8_t d4d_int1 : 1;
uint8_t lir_int1 : 1;
uint8_t not_used_01 : 2;
uint8_t fifo_en : 1;
uint8_t boot : 1;
} lis2dh12_ctrl_reg5_t;
#define LIS2DH12_CTRL_REG6 0x25U
typedef struct {
uint8_t not_used_01 : 1;
uint8_t int_polarity : 1;
uint8_t not_used_02 : 1;
uint8_t i2_act : 1;
uint8_t i2_boot : 1;
uint8_t i2_ia2 : 1;
uint8_t i2_ia1 : 1;
uint8_t i2_click : 1;
} lis2dh12_ctrl_reg6_t;
#define LIS2DH12_REFERENCE 0x26U
#define LIS2DH12_STATUS_REG 0x27U
typedef struct {
uint8_t xda : 1;
uint8_t yda : 1;
uint8_t zda : 1;
uint8_t zyxda : 1;
uint8_t _xor : 1;
uint8_t yor : 1;
uint8_t zor : 1;
uint8_t zyxor : 1;
} lis2dh12_status_reg_t;
#define LIS2DH12_OUT_X_L 0x28U
#define LIS2DH12_OUT_X_H 0x29U
#define LIS2DH12_OUT_Y_L 0x2AU
#define LIS2DH12_OUT_Y_H 0x2BU
#define LIS2DH12_OUT_Z_L 0x2CU
#define LIS2DH12_OUT_Z_H 0x2DU
#define LIS2DH12_FIFO_CTRL_REG 0x2EU
typedef struct {
uint8_t fth : 5;
uint8_t tr : 1;
uint8_t fm : 2;
} lis2dh12_fifo_ctrl_reg_t;
#define LIS2DH12_FIFO_SRC_REG 0x2FU
typedef struct {
uint8_t fss : 5;
uint8_t empty : 1;
uint8_t ovrn_fifo : 1;
uint8_t wtm : 1;
} lis2dh12_fifo_src_reg_t;
#define LIS2DH12_INT1_CFG 0x30U
typedef struct {
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
uint8_t yhie : 1;
uint8_t zlie : 1;
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
} lis2dh12_int1_cfg_t;
#define LIS2DH12_INT1_SRC 0x31U
typedef struct {
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
uint8_t yh : 1;
uint8_t zl : 1;
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
} lis2dh12_int1_src_t;
#define LIS2DH12_INT1_THS 0x32U
typedef struct {
uint8_t ths : 7;
uint8_t not_used_01 : 1;
} lis2dh12_int1_ths_t;
#define LIS2DH12_INT1_DURATION 0x33U
typedef struct {
uint8_t d : 7;
uint8_t not_used_01 : 1;
} lis2dh12_int1_duration_t;
#define LIS2DH12_INT2_CFG 0x34U
typedef struct {
uint8_t xlie : 1;
uint8_t xhie : 1;
uint8_t ylie : 1;
uint8_t yhie : 1;
uint8_t zlie : 1;
uint8_t zhie : 1;
uint8_t _6d : 1;
uint8_t aoi : 1;
} lis2dh12_int2_cfg_t;
#define LIS2DH12_INT2_SRC 0x35U
typedef struct {
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
uint8_t yh : 1;
uint8_t zl : 1;
uint8_t zh : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
} lis2dh12_int2_src_t;
#define LIS2DH12_INT2_THS 0x36U
typedef struct {
uint8_t ths : 7;
uint8_t not_used_01 : 1;
} lis2dh12_int2_ths_t;
#define LIS2DH12_INT2_DURATION 0x37U
typedef struct {
uint8_t d : 7;
uint8_t not_used_01 : 1;
} lis2dh12_int2_duration_t;
#define LIS2DH12_CLICK_CFG 0x38U
typedef struct {
uint8_t xs : 1;
uint8_t xd : 1;
uint8_t ys : 1;
uint8_t yd : 1;
uint8_t zs : 1;
uint8_t zd : 1;
uint8_t not_used_01 : 2;
} lis2dh12_click_cfg_t;
#define LIS2DH12_CLICK_SRC 0x39U
typedef struct {
uint8_t x : 1;
uint8_t y : 1;
uint8_t z : 1;
uint8_t sign : 1;
uint8_t sclick : 1;
uint8_t dclick : 1;
uint8_t ia : 1;
uint8_t not_used_01 : 1;
} lis2dh12_click_src_t;
#define LIS2DH12_CLICK_THS 0x3AU
typedef struct {
uint8_t ths : 7;
uint8_t lir_click : 1;
} lis2dh12_click_ths_t;
#define LIS2DH12_TIME_LIMIT 0x3BU
typedef struct {
uint8_t tli : 7;
uint8_t not_used_01 : 1;
} lis2dh12_time_limit_t;
#define LIS2DH12_TIME_LATENCY 0x3CU
typedef struct {
uint8_t tla : 8;
} lis2dh12_time_latency_t;
#define LIS2DH12_TIME_WINDOW 0x3DU
typedef struct {
uint8_t tw : 8;
} lis2dh12_time_window_t;
#define LIS2DH12_ACT_THS 0x3EU
typedef struct {
uint8_t acth : 7;
uint8_t not_used_01 : 1;
} lis2dh12_act_ths_t;
#define LIS2DH12_ACT_DUR 0x3FU
typedef struct {
uint8_t actd : 8;
} lis2dh12_act_dur_t;
/**
* @defgroup LIS2DH12_Register_Union
* @brief This union group all the registers that has a bitfield
* description.
* This union is usefull but not need by the driver.
*
* REMOVING this union you are complient with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
typedef union{
lis2dh12_status_reg_aux_t status_reg_aux;
lis2dh12_ctrl_reg0_t ctrl_reg0;
lis2dh12_temp_cfg_reg_t temp_cfg_reg;
lis2dh12_ctrl_reg1_t ctrl_reg1;
lis2dh12_ctrl_reg2_t ctrl_reg2;
lis2dh12_ctrl_reg3_t ctrl_reg3;
lis2dh12_ctrl_reg4_t ctrl_reg4;
lis2dh12_ctrl_reg5_t ctrl_reg5;
lis2dh12_ctrl_reg6_t ctrl_reg6;
lis2dh12_status_reg_t status_reg;
lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg;
lis2dh12_fifo_src_reg_t fifo_src_reg;
lis2dh12_int1_cfg_t int1_cfg;
lis2dh12_int1_src_t int1_src;
lis2dh12_int1_ths_t int1_ths;
lis2dh12_int1_duration_t int1_duration;
lis2dh12_int2_cfg_t int2_cfg;
lis2dh12_int2_src_t int2_src;
lis2dh12_int2_ths_t int2_ths;
lis2dh12_int2_duration_t int2_duration;
lis2dh12_click_cfg_t click_cfg;
lis2dh12_click_src_t click_src;
lis2dh12_click_ths_t click_ths;
lis2dh12_time_limit_t time_limit;
lis2dh12_time_latency_t time_latency;
lis2dh12_time_window_t time_window;
lis2dh12_act_ths_t act_ths;
lis2dh12_act_dur_t act_dur;
bitwise_t bitwise;
uint8_t byte;
} lis2dh12_reg_t;
/**
* @}
*
*/
int32_t lis2dh12_read_reg(lis2dh12_ctx_t *ctx, uint8_t reg, uint8_t* data,
uint16_t len);
int32_t lis2dh12_write_reg(lis2dh12_ctx_t *ctx, uint8_t reg, uint8_t* data,
uint16_t len);
extern float lis2dh12_from_fs2_hr_to_mg(int16_t lsb);
extern float lis2dh12_from_fs4_hr_to_mg(int16_t lsb);
extern float lis2dh12_from_fs8_hr_to_mg(int16_t lsb);
extern float lis2dh12_from_fs16_hr_to_mg(int16_t lsb);
extern float lis2dh12_from_lsb_hr_to_celsius(int16_t lsb);
extern float lis2dh12_from_fs2_nm_to_mg(int16_t lsb);
extern float lis2dh12_from_fs4_nm_to_mg(int16_t lsb);
extern float lis2dh12_from_fs8_nm_to_mg(int16_t lsb);
extern float lis2dh12_from_fs16_nm_to_mg(int16_t lsb);
extern float lis2dh12_from_lsb_nm_to_celsius(int16_t lsb);
extern float lis2dh12_from_fs2_lp_to_mg(int16_t lsb);
extern float lis2dh12_from_fs4_lp_to_mg(int16_t lsb);
extern float lis2dh12_from_fs8_lp_to_mg(int16_t lsb);
extern float lis2dh12_from_fs16_lp_to_mg(int16_t lsb);
extern float lis2dh12_from_lsb_lp_to_celsius(int16_t lsb);
int32_t lis2dh12_temp_status_reg_get(lis2dh12_ctx_t *ctx, uint8_t *buff);
int32_t lis2dh12_temp_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_temp_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_temperature_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff);
typedef enum {
LIS2DH12_TEMP_DISABLE = 0,
LIS2DH12_TEMP_ENABLE = 3,
} lis2dh12_temp_en_t;
int32_t lis2dh12_temperature_meas_set(lis2dh12_ctx_t *ctx,
lis2dh12_temp_en_t val);
int32_t lis2dh12_temperature_meas_get(lis2dh12_ctx_t *ctx,
lis2dh12_temp_en_t *val);
typedef enum {
LIS2DH12_HR_12bit = 0,
LIS2DH12_NM_10bit = 1,
LIS2DH12_LP_8bit = 2,
} lis2dh12_op_md_t;
int32_t lis2dh12_operating_mode_set(lis2dh12_ctx_t *ctx,
lis2dh12_op_md_t val);
int32_t lis2dh12_operating_mode_get(lis2dh12_ctx_t *ctx,
lis2dh12_op_md_t *val);
typedef enum {
LIS2DH12_POWER_DOWN = 0x00,
LIS2DH12_ODR_1Hz = 0x01,
LIS2DH12_ODR_10Hz = 0x02,
LIS2DH12_ODR_25Hz = 0x03,
LIS2DH12_ODR_50Hz = 0x04,
LIS2DH12_ODR_100Hz = 0x05,
LIS2DH12_ODR_200Hz = 0x06,
LIS2DH12_ODR_400Hz = 0x07,
LIS2DH12_ODR_1kHz620_LP = 0x08,
LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09,
} lis2dh12_odr_t;
int32_t lis2dh12_data_rate_set(lis2dh12_ctx_t *ctx, lis2dh12_odr_t val);
int32_t lis2dh12_data_rate_get(lis2dh12_ctx_t *ctx, lis2dh12_odr_t *val);
int32_t lis2dh12_high_pass_on_outputs_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_high_pass_on_outputs_get(lis2dh12_ctx_t *ctx, uint8_t *val);
typedef enum {
LIS2DH12_AGGRESSIVE = 0,
LIS2DH12_STRONG = 1,
LIS2DH12_MEDIUM = 2,
LIS2DH12_LIGHT = 3,
} lis2dh12_hpcf_t;
int32_t lis2dh12_high_pass_bandwidth_set(lis2dh12_ctx_t *ctx,
lis2dh12_hpcf_t val);
int32_t lis2dh12_high_pass_bandwidth_get(lis2dh12_ctx_t *ctx,
lis2dh12_hpcf_t *val);
typedef enum {
LIS2DH12_NORMAL_WITH_RST = 0,
LIS2DH12_REFERENCE_MODE = 1,
LIS2DH12_NORMAL = 2,
LIS2DH12_AUTORST_ON_INT = 3,
} lis2dh12_hpm_t;
int32_t lis2dh12_high_pass_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t val);
int32_t lis2dh12_high_pass_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t *val);
typedef enum {
LIS2DH12_2g = 0,
LIS2DH12_4g = 1,
LIS2DH12_8g = 2,
LIS2DH12_16g = 3,
} lis2dh12_fs_t;
int32_t lis2dh12_full_scale_set(lis2dh12_ctx_t *ctx, lis2dh12_fs_t val);
int32_t lis2dh12_full_scale_get(lis2dh12_ctx_t *ctx, lis2dh12_fs_t *val);
int32_t lis2dh12_block_data_update_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_block_data_update_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_filter_reference_set(lis2dh12_ctx_t *ctx, uint8_t *buff);
int32_t lis2dh12_filter_reference_get(lis2dh12_ctx_t *ctx, uint8_t *buff);
int32_t lis2dh12_xl_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_xl_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_acceleration_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff);
int32_t lis2dh12_device_id_get(lis2dh12_ctx_t *ctx, uint8_t *buff);
typedef enum {
LIS2DH12_ST_DISABLE = 0,
LIS2DH12_ST_POSITIVE = 1,
LIS2DH12_ST_NEGATIVE = 2,
} lis2dh12_st_t;
int32_t lis2dh12_self_test_set(lis2dh12_ctx_t *ctx, lis2dh12_st_t val);
int32_t lis2dh12_self_test_get(lis2dh12_ctx_t *ctx, lis2dh12_st_t *val);
typedef enum {
LIS2DH12_LSB_AT_LOW_ADD = 0,
LIS2DH12_MSB_AT_LOW_ADD = 1,
} lis2dh12_ble_t;
int32_t lis2dh12_data_format_set(lis2dh12_ctx_t *ctx, lis2dh12_ble_t val);
int32_t lis2dh12_data_format_get(lis2dh12_ctx_t *ctx, lis2dh12_ble_t *val);
int32_t lis2dh12_boot_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_boot_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_status_get(lis2dh12_ctx_t *ctx, lis2dh12_status_reg_t *val);
int32_t lis2dh12_int1_gen_conf_set(lis2dh12_ctx_t *ctx,
lis2dh12_int1_cfg_t *val);
int32_t lis2dh12_int1_gen_conf_get(lis2dh12_ctx_t *ctx,
lis2dh12_int1_cfg_t *val);
int32_t lis2dh12_int1_gen_source_get(lis2dh12_ctx_t *ctx,
lis2dh12_int1_src_t *val);
int32_t lis2dh12_int1_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_int1_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_int1_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_int1_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_int2_gen_conf_set(lis2dh12_ctx_t *ctx,
lis2dh12_int2_cfg_t *val);
int32_t lis2dh12_int2_gen_conf_get(lis2dh12_ctx_t *ctx,
lis2dh12_int2_cfg_t *val);
int32_t lis2dh12_int2_gen_source_get(lis2dh12_ctx_t *ctx,
lis2dh12_int2_src_t *val);
int32_t lis2dh12_int2_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_int2_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_int2_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_int2_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val);
typedef enum {
LIS2DH12_DISC_FROM_INT_GENERATOR = 0,
LIS2DH12_ON_INT1_GEN = 1,
LIS2DH12_ON_INT2_GEN = 2,
LIS2DH12_ON_TAP_GEN = 4,
LIS2DH12_ON_INT1_INT2_GEN = 3,
LIS2DH12_ON_INT1_TAP_GEN = 5,
LIS2DH12_ON_INT2_TAP_GEN = 6,
LIS2DH12_ON_INT1_INT2_TAP_GEN = 7,
} lis2dh12_hp_t;
int32_t lis2dh12_high_pass_int_conf_set(lis2dh12_ctx_t *ctx,
lis2dh12_hp_t val);
int32_t lis2dh12_high_pass_int_conf_get(lis2dh12_ctx_t *ctx,
lis2dh12_hp_t *val);
int32_t lis2dh12_pin_int1_config_set(lis2dh12_ctx_t *ctx,
lis2dh12_ctrl_reg3_t *val);
int32_t lis2dh12_pin_int1_config_get(lis2dh12_ctx_t *ctx,
lis2dh12_ctrl_reg3_t *val);
int32_t lis2dh12_int2_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_int2_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val);
typedef enum {
LIS2DH12_INT2_PULSED = 0,
LIS2DH12_INT2_LATCHED = 1,
} lis2dh12_lir_int2_t;
int32_t lis2dh12_int2_pin_notification_mode_set(lis2dh12_ctx_t *ctx,
lis2dh12_lir_int2_t val);
int32_t lis2dh12_int2_pin_notification_mode_get(lis2dh12_ctx_t *ctx,
lis2dh12_lir_int2_t *val);
int32_t lis2dh12_int1_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_int1_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val);
typedef enum {
LIS2DH12_INT1_PULSED = 0,
LIS2DH12_INT1_LATCHED = 1,
} lis2dh12_lir_int1_t;
int32_t lis2dh12_int1_pin_notification_mode_set(lis2dh12_ctx_t *ctx,
lis2dh12_lir_int1_t val);
int32_t lis2dh12_int1_pin_notification_mode_get(lis2dh12_ctx_t *ctx,
lis2dh12_lir_int1_t *val);
int32_t lis2dh12_pin_int2_config_set(lis2dh12_ctx_t *ctx,
lis2dh12_ctrl_reg6_t *val);
int32_t lis2dh12_pin_int2_config_get(lis2dh12_ctx_t *ctx,
lis2dh12_ctrl_reg6_t *val);
int32_t lis2dh12_fifo_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_fifo_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_fifo_watermark_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_fifo_watermark_get(lis2dh12_ctx_t *ctx, uint8_t *val);
typedef enum {
LIS2DH12_INT1_GEN = 0,
LIS2DH12_INT2_GEN = 1,
} lis2dh12_tr_t;
int32_t lis2dh12_fifo_trigger_event_set(lis2dh12_ctx_t *ctx,
lis2dh12_tr_t val);
int32_t lis2dh12_fifo_trigger_event_get(lis2dh12_ctx_t *ctx,
lis2dh12_tr_t *val);
typedef enum {
LIS2DH12_BYPASS_MODE = 0,
LIS2DH12_FIFO_MODE = 1,
LIS2DH12_DYNAMIC_STREAM_MODE = 2,
LIS2DH12_STREAM_TO_FIFO_MODE = 3,
} lis2dh12_fm_t;
int32_t lis2dh12_fifo_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_fm_t val);
int32_t lis2dh12_fifo_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_fm_t *val);
int32_t lis2dh12_fifo_status_get(lis2dh12_ctx_t *ctx,
lis2dh12_fifo_src_reg_t *val);
int32_t lis2dh12_fifo_data_level_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_fifo_empty_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_fifo_ovr_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_fifo_fth_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_tap_conf_set(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val);
int32_t lis2dh12_tap_conf_get(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val);
int32_t lis2dh12_tap_source_get(lis2dh12_ctx_t *ctx,
lis2dh12_click_src_t *val);
int32_t lis2dh12_tap_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_tap_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val);
typedef enum {
LIS2DH12_TAP_PULSED = 0,
LIS2DH12_TAP_LATCHED = 1,
} lis2dh12_lir_click_t;
int32_t lis2dh12_tap_notification_mode_set(lis2dh12_ctx_t *ctx,
lis2dh12_lir_click_t val);
int32_t lis2dh12_tap_notification_mode_get(lis2dh12_ctx_t *ctx,
lis2dh12_lir_click_t *val);
int32_t lis2dh12_shock_dur_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_shock_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_quiet_dur_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_quiet_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_double_tap_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_double_tap_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_act_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_act_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val);
int32_t lis2dh12_act_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val);
int32_t lis2dh12_act_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val);
typedef enum {
LIS2DH12_PULL_UP_DISCONNECT = 0,
LIS2DH12_PULL_UP_CONNECT = 1,
} lis2dh12_sdo_pu_disc_t;
int32_t lis2dh12_pin_sdo_sa0_mode_set(lis2dh12_ctx_t *ctx,
lis2dh12_sdo_pu_disc_t val);
int32_t lis2dh12_pin_sdo_sa0_mode_get(lis2dh12_ctx_t *ctx,
lis2dh12_sdo_pu_disc_t *val);
typedef enum {
LIS2DH12_SPI_4_WIRE = 0,
LIS2DH12_SPI_3_WIRE = 1,
} lis2dh12_sim_t;
int32_t lis2dh12_spi_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_sim_t val);
int32_t lis2dh12_spi_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_sim_t *val);
/**
* @}
*
*/
#ifdef __cplusplus
}
#endif
#endif /* LIS2DH12_REGS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
Copyright (c) 2019 SparkFun Electronics
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D0 = 25,
D1 = 24,
D2 = 35,
D3 = 4,
D4 = 22,
D5 = 23,
D6 = 27,
D7 = 28,
D8 = 32,
D9 = 12,
D10 = 13,
D11 = 7,
D12 = 6,
D13 = 5,
D14 = 40,
D15 = 39,
D16 = 29,
D17 = 11,
D18 = 34,
D19 = 33,
D20 = 16,
D21 = 31,
// Analog naming
A0 = D16,
A1 = D17,
A2 = D18,
A3 = D19,
A4 = D20,
A5 = D21,
A6 = D2,
// A7 = ??
A8 = D8,
A9 = D9,
A10 = D10,
// LEDs
LED_BLUE = AM_BSP_GPIO_LED_BLUE,
// mbed original LED naming
LED1 = AM_BSP_GPIO_LED0,
LED2 = A5,
// LED naming by digital pin number
LED13 = AM_BSP_GPIO_LED13,
// I2C
I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN,
I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN,
// Qwiic
QWIIC_SCL = I2C_SCL,
QWIIC_SDA = I2C_SDA,
// SPI
SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN,
SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN,
SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN,
// UART
SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN,
SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
SERIAL1_TX = D1,
SERIAL1_RX = D0,
// Not connected
NC = NC_VAL
} PinName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#ifdef __cplusplus
}
#endif
#endif

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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// PDM Microphone
//
//*****************************************************************************
#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT
#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA
#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK
#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA
#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK
//*****************************************************************************
//
// Primary SPI Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_SPI_IOM 0
#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK
#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI
#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO
#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK
#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO
#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI
//*****************************************************************************
//
// Primary UART Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX
#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX
#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX
#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX
//*****************************************************************************
//
// Qwiic Connector.
//
//*****************************************************************************
#define AM_BSP_QWIIC_I2C_IOM 4
#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA
#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL
#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA
#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_LEDS 1
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
// LED Device Array Indices
#define AM_BSP_LED0 0
#define AM_BSP_LED_BLUE AM_BSP_LED0
// Corresponding GPIO Numbers
#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED13 AM_BSP_GPIO_LED_BLUE
//*****************************************************************************
//
// PWM_LED peripheral assignments.
//
//*****************************************************************************
//
// The RedBoard Artemis PWM LED is pad 5
//
#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0
#define AM_BSP_PWM_LED_TIMER 2
#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA
#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA2C0
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.c
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#include "am_bsp.h"
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 13.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE =
{
.uFuncSel = AM_HAL_PIN_5_GPIO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA =
{
.uFuncSel = AM_HAL_PIN_36_PDMDATA
};
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK =
{
.uFuncSel = AM_HAL_PIN_37_PDMCLK
};
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX =
{
.uFuncSel = AM_HAL_PIN_48_UART0TX,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX =
{
.uFuncSel = AM_HAL_PIN_49_UART0RX
};
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS =
{
.uFuncSel = AM_HAL_PIN_11_NCE11,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO =
{
.uFuncSel = AM_HAL_PIN_6_M0MISO,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI =
{
.uFuncSel = AM_HAL_PIN_7_M0MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK =
{
.uFuncSel = AM_HAL_PIN_5_M0SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL =
{
.uFuncSel = AM_HAL_PIN_5_M0SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA =
{
.uFuncSel = AM_HAL_PIN_6_M0SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS =
{
.uFuncSel = AM_HAL_PIN_14_NCE14,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 1,
.uNCE = 2,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO =
{
.uFuncSel = AM_HAL_PIN_9_M1MISO,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI =
{
.uFuncSel = AM_HAL_PIN_10_M1MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK =
{
.uFuncSel = AM_HAL_PIN_8_M1SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL =
{
.uFuncSel = AM_HAL_PIN_8_M1SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA =
{
.uFuncSel = AM_HAL_PIN_9_M1SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 2,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO =
{
.uFuncSel = AM_HAL_PIN_25_M2MISO,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI =
{
.uFuncSel = AM_HAL_PIN_28_M2MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK =
{
.uFuncSel = AM_HAL_PIN_27_M2SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL =
{
.uFuncSel = AM_HAL_PIN_27_M2SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA =
{
.uFuncSel = AM_HAL_PIN_25_M2SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS =
{
.uFuncSel = AM_HAL_PIN_12_NCE12,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 3,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO =
{
.uFuncSel = AM_HAL_PIN_43_M3MISO,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI =
{
.uFuncSel = AM_HAL_PIN_38_M3MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK =
{
.uFuncSel = AM_HAL_PIN_42_M3SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL =
{
.uFuncSel = AM_HAL_PIN_42_M3SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA =
{
.uFuncSel = AM_HAL_PIN_43_M3SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS =
{
.uFuncSel = AM_HAL_PIN_13_NCE13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 4,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO =
{
.uFuncSel = AM_HAL_PIN_40_M4MISO,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI =
{
.uFuncSel = AM_HAL_PIN_44_M4MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK =
{
.uFuncSel = AM_HAL_PIN_39_M4SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL =
{
.uFuncSel = AM_HAL_PIN_39_M4SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA =
{
.uFuncSel = AM_HAL_PIN_40_M4SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS =
{
.uFuncSel = AM_HAL_PIN_16_NCE16,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 5,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO =
{
.uFuncSel = AM_HAL_PIN_49_M5MISO,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI =
{
.uFuncSel = AM_HAL_PIN_47_M5MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK =
{
.uFuncSel = AM_HAL_PIN_48_M5SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL =
{
.uFuncSel = AM_HAL_PIN_48_M5SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA =
{
.uFuncSel = AM_HAL_PIN_49_M5SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 =
{
.uFuncSel = AM_HAL_PIN_19_NCE19,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 =
{
.uFuncSel = AM_HAL_PIN_41_NCE41,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 =
{
.uFuncSel = AM_HAL_PIN_22_MSPI0,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 =
{
.uFuncSel = AM_HAL_PIN_26_MSPI1,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 =
{
.uFuncSel = AM_HAL_PIN_4_MSPI2,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 =
{
.uFuncSel = AM_HAL_PIN_23_MSPI13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 =
{
.uFuncSel = AM_HAL_PIN_0_MSPI4,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 =
{
.uFuncSel = AM_HAL_PIN_1_MSPI5,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 =
{
.uFuncSel = AM_HAL_PIN_2_MSPI6,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 =
{
.uFuncSel = AM_HAL_PIN_3_MSPI7,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK =
{
.uFuncSel = AM_HAL_PIN_24_MSPI8,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE =
{
.uFuncSel = AM_HAL_PIN_3_SLnCE,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO =
{
.uFuncSel = AM_HAL_PIN_2_SLMISO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI =
{
.uFuncSel = AM_HAL_PIN_1_SLMOSI,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK =
{
.uFuncSel = AM_HAL_PIN_0_SLSCK,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL =
{
.uFuncSel = AM_HAL_PIN_0_SLSCL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA =
{
.uFuncSel = AM_HAL_PIN_1_SLSDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN
};
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO =
{
.uFuncSel = AM_HAL_PIN_33_SWO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK =
{
.uFuncSel = AM_HAL_PIN_20_SWDCK
};
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO =
{
.uFuncSel = AM_HAL_PIN_21_SWDIO
};
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 13.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_BLUE 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE;
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_DATA 36
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA;
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_CLK 37
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK;
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
#define AM_BSP_GPIO_ITM_SWO 33
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D0 = 0,
D1 = 1,
D2 = 2,
D3 = 3,
D4 = 4,
D5 = 5,
D6 = 6,
D7 = 7,
D8 = 8,
D9 = 9,
D10 = 10,
D11 = 11,
D12 = 12,
D13 = 13,
D14 = 14,
D15 = 15,
D16 = 16,
D17 = 17,
D18 = 18,
D19 = 19,
// D20 = ??
// D21 = ??
D22 = 22,
D23 = 23,
D24 = 24,
D25 = 25,
D26 = 26,
D27 = 27,
D28 = 28,
D29 = 29,
// D30 = ??
D31 = 31,
D32 = 32,
D33 = 33,
D34 = 34,
D35 = 35,
D36 = 36,
D37 = 37,
D38 = 38,
D39 = 39,
D40 = 40,
D41 = 41,
D42 = 42,
D43 = 43,
D44 = 44,
D45 = 45,
// Analog naming
A11 = D11,
A12 = D12,
A13 = D13,
A16 = D16,
A29 = D29,
A31 = D31,
A32 = D32,
A33 = D33,
A34 = D34,
A35 = D35,
// LEDs
LED_BLUE = AM_BSP_GPIO_LED_BLUE,
// mbed original LED naming
LED1 = AM_BSP_GPIO_LED0,
LED2 = D42,
// I2C
I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN,
I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN,
// Qwiic
QWIIC_SCL = I2C_SCL,
QWIIC_SDA = I2C_SDA,
// SPI
SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN,
SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN,
SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN,
// UART
SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN,
SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
SERIAL1_TX = D24,
SERIAL1_RX = D25,
// Not connected
NC = NC_VAL
} PinName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#ifdef __cplusplus
}
#endif
#endif

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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// PDM Microphone
//
//*****************************************************************************
#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT
#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA
#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK
#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA
#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK
//*****************************************************************************
//
// Primary SPI Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_SPI_IOM 0
#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK
#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI
#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO
#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK
#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO
#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI
//*****************************************************************************
//
// Primary UART Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX
#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX
#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX
#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX
//*****************************************************************************
//
// Qwiic Connector.
//
//*****************************************************************************
#define AM_BSP_QWIIC_I2C_IOM 4
#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA
#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL
#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA
#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_LEDS 1
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
// LED Device Array Indices
#define AM_BSP_LED0 0
#define AM_BSP_LED_BLUE AM_BSP_LED0
// Corresponding GPIO Numbers
#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_BLUE
//*****************************************************************************
//
// PWM_LED peripheral assignments.
//
//*****************************************************************************
//
// The ATP PWM LED is pad 5
//
#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0
#define AM_BSP_PWM_LED_TIMER 2
#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA
#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA2C0
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.c
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#include "am_bsp.h"
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 5.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE =
{
.uFuncSel = AM_HAL_PIN_5_GPIO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA =
{
.uFuncSel = AM_HAL_PIN_36_PDMDATA
};
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK =
{
.uFuncSel = AM_HAL_PIN_37_PDMCLK
};
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX =
{
.uFuncSel = AM_HAL_PIN_48_UART0TX,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX =
{
.uFuncSel = AM_HAL_PIN_49_UART0RX
};
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS =
{
.uFuncSel = AM_HAL_PIN_11_NCE11,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO =
{
.uFuncSel = AM_HAL_PIN_6_M0MISO,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI =
{
.uFuncSel = AM_HAL_PIN_7_M0MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK =
{
.uFuncSel = AM_HAL_PIN_5_M0SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL =
{
.uFuncSel = AM_HAL_PIN_5_M0SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA =
{
.uFuncSel = AM_HAL_PIN_6_M0SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS =
{
.uFuncSel = AM_HAL_PIN_14_NCE14,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 1,
.uNCE = 2,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO =
{
.uFuncSel = AM_HAL_PIN_9_M1MISO,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI =
{
.uFuncSel = AM_HAL_PIN_10_M1MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK =
{
.uFuncSel = AM_HAL_PIN_8_M1SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL =
{
.uFuncSel = AM_HAL_PIN_8_M1SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA =
{
.uFuncSel = AM_HAL_PIN_9_M1SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 2,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO =
{
.uFuncSel = AM_HAL_PIN_25_M2MISO,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI =
{
.uFuncSel = AM_HAL_PIN_28_M2MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK =
{
.uFuncSel = AM_HAL_PIN_27_M2SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL =
{
.uFuncSel = AM_HAL_PIN_27_M2SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA =
{
.uFuncSel = AM_HAL_PIN_25_M2SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS =
{
.uFuncSel = AM_HAL_PIN_12_NCE12,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 3,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO =
{
.uFuncSel = AM_HAL_PIN_43_M3MISO,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI =
{
.uFuncSel = AM_HAL_PIN_38_M3MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK =
{
.uFuncSel = AM_HAL_PIN_42_M3SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL =
{
.uFuncSel = AM_HAL_PIN_42_M3SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA =
{
.uFuncSel = AM_HAL_PIN_43_M3SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS =
{
.uFuncSel = AM_HAL_PIN_13_NCE13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 4,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO =
{
.uFuncSel = AM_HAL_PIN_40_M4MISO,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI =
{
.uFuncSel = AM_HAL_PIN_44_M4MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK =
{
.uFuncSel = AM_HAL_PIN_39_M4SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL =
{
.uFuncSel = AM_HAL_PIN_39_M4SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA =
{
.uFuncSel = AM_HAL_PIN_40_M4SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS =
{
.uFuncSel = AM_HAL_PIN_16_NCE16,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 5,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO =
{
.uFuncSel = AM_HAL_PIN_49_M5MISO,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI =
{
.uFuncSel = AM_HAL_PIN_47_M5MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK =
{
.uFuncSel = AM_HAL_PIN_48_M5SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL =
{
.uFuncSel = AM_HAL_PIN_48_M5SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA =
{
.uFuncSel = AM_HAL_PIN_49_M5SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 =
{
.uFuncSel = AM_HAL_PIN_19_NCE19,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 =
{
.uFuncSel = AM_HAL_PIN_41_NCE41,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 =
{
.uFuncSel = AM_HAL_PIN_22_MSPI0,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 =
{
.uFuncSel = AM_HAL_PIN_26_MSPI1,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 =
{
.uFuncSel = AM_HAL_PIN_4_MSPI2,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 =
{
.uFuncSel = AM_HAL_PIN_23_MSPI13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 =
{
.uFuncSel = AM_HAL_PIN_0_MSPI4,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 =
{
.uFuncSel = AM_HAL_PIN_1_MSPI5,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 =
{
.uFuncSel = AM_HAL_PIN_2_MSPI6,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 =
{
.uFuncSel = AM_HAL_PIN_3_MSPI7,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK =
{
.uFuncSel = AM_HAL_PIN_24_MSPI8,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE =
{
.uFuncSel = AM_HAL_PIN_3_SLnCE,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO =
{
.uFuncSel = AM_HAL_PIN_2_SLMISO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI =
{
.uFuncSel = AM_HAL_PIN_1_SLMOSI,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK =
{
.uFuncSel = AM_HAL_PIN_0_SLSCK,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL =
{
.uFuncSel = AM_HAL_PIN_0_SLSCL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA =
{
.uFuncSel = AM_HAL_PIN_1_SLSDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN
};
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO =
{
.uFuncSel = AM_HAL_PIN_33_SWO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK =
{
.uFuncSel = AM_HAL_PIN_20_SWDCK
};
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO =
{
.uFuncSel = AM_HAL_PIN_21_SWDIO
};
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h Normal file
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//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_BLUE 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE;
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_DATA 36
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA;
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_CLK 37
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK;
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
#define AM_BSP_GPIO_ITM_SWO 33
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D13 = 13,
D16 = 16,
D23 = 23,
D24 = 24,
D25 = 25,
D26 = 26,
D27 = 27,
D28 = 28,
D29 = 29,
// D30 = 30, ??
D31 = 31,
D32 = 32,
D33 = 33,
D34 = 34,
D35 = 35,
D36 = 36,
D37 = 37,
D38 = 38,
D39 = 39,
D40 = 40,
D41 = 41,
D42 = 42,
D43 = 43,
D44 = 44,
D45 = 45,
// Analog naming
A13 = D13,
A16 = D16,
A29 = D29,
A31 = D31,
A32 = D32,
A33 = D33,
A34 = D34,
A35 = D35,
// LEDs
LED_BLUE = AM_BSP_GPIO_LED_BLUE,
// mbed original LED naming
LED1 = AM_BSP_GPIO_LED0,
LED2 = D24,
// I2C
I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN,
I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN,
// Qwiic
QWIIC_SCL = I2C_SCL,
QWIIC_SDA = I2C_SDA,
// Accelerometer
ACC_SCL = QWIIC_SCL,
ACC_SDA = QWIIC_SDA,
// Camera
CAM_SCL = QWIIC_SCL,
CAM_SDA = QWIIC_SDA,
// SPI
SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN,
SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN,
SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN,
// UART
SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN,
SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
// Not connected
NC = NC_VAL
} PinName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#ifdef __cplusplus
}
#endif
#endif

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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
// artmbed hardware version: v01 (there will need to be changes when migrating to v02 or v10)
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Camera
//
//*****************************************************************************
#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 18
#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1
#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA
#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL
#define g_AM_BSP_CAMERA_HM01B0_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA
#define g_AM_BSP_CAMERA_HM01B0_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL
#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 1
#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERA
//*****************************************************************************
//
// PDM Microphone
//
//*****************************************************************************
#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT
#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA
#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK
#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA
#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK
//*****************************************************************************
//
// Accelerometer.
//
//*****************************************************************************
#define AM_BSP_ACCELEROMETER_I2C_IOM 1
#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19
#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA
#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL
#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA
#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL
//*****************************************************************************
//
// Primary SPI Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_SPI_IOM 4
#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM4_SCK
#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM4_MOSI
#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM4_MISO
#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM4_SCK
#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM4_SDO
#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM4_SDI
//*****************************************************************************
//
// Primary UART Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX
#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX
#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX
#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX
//*****************************************************************************
//
// Qwiic Connector.
//
//*****************************************************************************
#define AM_BSP_QWIIC_I2C_IOM 1
#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA
#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL
#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA
#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL
// //*****************************************************************************
// //
// // Button definitions.
// //
// //*****************************************************************************
// #define AM_BSP_NUM_BUTTONS 0
// extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS];
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_LEDS 1
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
// LED Device Array Indices
#define AM_BSP_LED0 0
#define AM_BSP_LED_BLUE AM_BSP_LED0
// Corresponding GPIO Numbers
#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED23 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED_STAT AM_BSP_GPIO_LED_BLUE
//*****************************************************************************
//
// PWM_LED peripheral assignments.
//
//*****************************************************************************
//
// The ARTMBED LED0 is pad 23
//
#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0
#define AM_BSP_PWM_LED_TIMER 3
#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB
#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB3C0
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// CAMERA_HM01B0_D0 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D0 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0;
//*****************************************************************************
//
// CAMERA_HM01B0_D1 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D1 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1;
//*****************************************************************************
//
// CAMERA_HM01B0_D2 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D2 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2;
//*****************************************************************************
//
// CAMERA_HM01B0_D3 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D3 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3;
//*****************************************************************************
//
// CAMERA_HM01B0_D4 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D4 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4;
//*****************************************************************************
//
// CAMERA_HM01B0_D5 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5;
//*****************************************************************************
//
// CAMERA_HM01B0_D6 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D6 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6;
//*****************************************************************************
//
// CAMERA_HM01B0_D7 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D7 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7;
//*****************************************************************************
//
// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC;
//*****************************************************************************
//
// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 17
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC;
//*****************************************************************************
//
// CAMERA_HM01B0_PCLK pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK;
//*****************************************************************************
//
// CAMERA_HM01B0_TRIG pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG;
//*****************************************************************************
//
// CAMERA_HM01B0_INT pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_INT 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT;
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_DATA 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA;
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_CLK 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK;
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labeled STAT.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_BLUE 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE;
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
#define AM_BSP_GPIO_ITM_SWO 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D0 = 0,
D1 = 1,
D2 = 2,
D3 = 3,
D4 = 4,
D5 = 5,
D6 = 6,
D7 = 7,
D8 = 8,
D9 = 9
D10 = 10,
D11 = 11,
D12 = 12,
D13 = 13,
D14 = 14,
D15 = 15,
D16 = 16,
D17 = 17,
D18 = 18,
D19 = 19,
D20 = 20,
D21 = 21,
D22 = 22,
D23 = 23,
D24 = 24,
D25 = 25,
D26 = 26,
D27 = 27,
D28 = 28,
D29 = 29,
// D30 = NC
D31 = 31,
D32 = 32,
D33 = 33,
D34 = 34,
D35 = 35,
D36 = 36,
D37 = 37,
D38 = 38,
D39 = 39,
D40 = 40,
D41 = 41,
D42 = 42,
D43 = 43,
D44 = 44,
D45 = 45,
// Analog naming
A11 = D11,
A12 = D12,
A13 = D13,
A16 = D16,
A29 = D29,
A31 = D31,
A32 = D32,
A33 = D33,
A34 = D34,
A35 = D35,
// Not connected
NC = NC_VAL
} PinName;
#ifdef __cplusplus
}
#endif
#endif

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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#undef AM_BSP_NUM_LEDS
#ifdef AM_BSP_NUM_LEDS
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
#endif // AM_BSP_NUM_LEDS
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.c
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#include "am_bsp.h"
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX =
{
.uFuncSel = AM_HAL_PIN_48_UART0TX,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX =
{
.uFuncSel = AM_HAL_PIN_49_UART0RX
};
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS =
{
.uFuncSel = AM_HAL_PIN_11_NCE11,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO =
{
.uFuncSel = AM_HAL_PIN_6_M0MISO,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI =
{
.uFuncSel = AM_HAL_PIN_7_M0MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK =
{
.uFuncSel = AM_HAL_PIN_5_M0SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL =
{
.uFuncSel = AM_HAL_PIN_5_M0SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA =
{
.uFuncSel = AM_HAL_PIN_6_M0SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS =
{
.uFuncSel = AM_HAL_PIN_14_NCE14,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 1,
.uNCE = 2,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO =
{
.uFuncSel = AM_HAL_PIN_9_M1MISO,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI =
{
.uFuncSel = AM_HAL_PIN_10_M1MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK =
{
.uFuncSel = AM_HAL_PIN_8_M1SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL =
{
.uFuncSel = AM_HAL_PIN_8_M1SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA =
{
.uFuncSel = AM_HAL_PIN_9_M1SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 2,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO =
{
.uFuncSel = AM_HAL_PIN_25_M2MISO,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI =
{
.uFuncSel = AM_HAL_PIN_28_M2MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK =
{
.uFuncSel = AM_HAL_PIN_27_M2SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL =
{
.uFuncSel = AM_HAL_PIN_27_M2SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA =
{
.uFuncSel = AM_HAL_PIN_25_M2SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS =
{
.uFuncSel = AM_HAL_PIN_12_NCE12,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 3,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO =
{
.uFuncSel = AM_HAL_PIN_43_M3MISO,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI =
{
.uFuncSel = AM_HAL_PIN_38_M3MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK =
{
.uFuncSel = AM_HAL_PIN_42_M3SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL =
{
.uFuncSel = AM_HAL_PIN_42_M3SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA =
{
.uFuncSel = AM_HAL_PIN_43_M3SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS =
{
.uFuncSel = AM_HAL_PIN_13_NCE13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 4,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO =
{
.uFuncSel = AM_HAL_PIN_40_M4MISO,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI =
{
.uFuncSel = AM_HAL_PIN_44_M4MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK =
{
.uFuncSel = AM_HAL_PIN_39_M4SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL =
{
.uFuncSel = AM_HAL_PIN_39_M4SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA =
{
.uFuncSel = AM_HAL_PIN_40_M4SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS =
{
.uFuncSel = AM_HAL_PIN_16_NCE16,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 5,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO =
{
.uFuncSel = AM_HAL_PIN_49_M5MISO,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI =
{
.uFuncSel = AM_HAL_PIN_47_M5MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK =
{
.uFuncSel = AM_HAL_PIN_48_M5SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL =
{
.uFuncSel = AM_HAL_PIN_48_M5SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA =
{
.uFuncSel = AM_HAL_PIN_49_M5SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 =
{
.uFuncSel = AM_HAL_PIN_19_NCE19,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 =
{
.uFuncSel = AM_HAL_PIN_41_NCE41,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 =
{
.uFuncSel = AM_HAL_PIN_22_MSPI0,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 =
{
.uFuncSel = AM_HAL_PIN_26_MSPI1,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 =
{
.uFuncSel = AM_HAL_PIN_4_MSPI2,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 =
{
.uFuncSel = AM_HAL_PIN_23_MSPI13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 =
{
.uFuncSel = AM_HAL_PIN_0_MSPI4,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 =
{
.uFuncSel = AM_HAL_PIN_1_MSPI5,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 =
{
.uFuncSel = AM_HAL_PIN_2_MSPI6,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 =
{
.uFuncSel = AM_HAL_PIN_3_MSPI7,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK =
{
.uFuncSel = AM_HAL_PIN_24_MSPI8,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE =
{
.uFuncSel = AM_HAL_PIN_3_SLnCE,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO =
{
.uFuncSel = AM_HAL_PIN_2_SLMISO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI =
{
.uFuncSel = AM_HAL_PIN_1_SLMOSI,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK =
{
.uFuncSel = AM_HAL_PIN_0_SLSCK,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL =
{
.uFuncSel = AM_HAL_PIN_0_SLSCL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA =
{
.uFuncSel = AM_HAL_PIN_1_SLSDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN
};
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK =
{
.uFuncSel = AM_HAL_PIN_20_SWDCK
};
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO =
{
.uFuncSel = AM_HAL_PIN_21_SWDIO
};
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h Normal file
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@ -0,0 +1,552 @@
//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D0 = 13,
D1 = 33,
D2 = 11,
D3 = 29,
D4 = 18,
D5 = 31,
D6 = 43,
D7 = 42,
D8 = 38,
D9 = 39,
D10 = 40,
D11 = 5,
D12 = 7,
D13 = 6,
D14 = 35,
D15 = 32,
D16 = 12,
// Analog naming
A0 = D0,
A1 = D1,
A2 = D2,
A3 = D3,
A5 = D5,
A14 = D14,
A15 = D15,
A16 = D16,
// LEDs
LED_BLUE = AM_BSP_GPIO_LED_BLUE,
// mbed original LED naming
LED1 = AM_BSP_GPIO_LED0,
LED2 = D8,
// I2C
I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN,
I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN,
I2C1_SCL = AM_BSP_GPIO_IOM3_SCL,
I2C1_SDA = AM_BSP_GPIO_IOM3_SDA,
// Qwiic
QWIIC_SCL = I2C_SCL,
QWIIC_SDA = I2C_SDA,
// SPI
SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN,
SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN,
SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN,
// UART
SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN,
SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
SERIAL1_TX = D9,
SERIAL1_RX = D10,
// Not connected
NC = NC_VAL
} PinName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#ifdef __cplusplus
}
#endif
#endif

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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// PDM Microphone
//
//*****************************************************************************
#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT
#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA
#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK
#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA
#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK
//*****************************************************************************
//
// Primary SPI Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_SPI_IOM 0
#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK
#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI
#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO
#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK
#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO
#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI
//*****************************************************************************
//
// Primary UART Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX
#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX
#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX
#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX
//*****************************************************************************
//
// Qwiic Connector.
//
//*****************************************************************************
#define AM_BSP_QWIIC_I2C_IOM 2
#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM2_SDA
#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM2_SCL
#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM2_SDA
#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM2_SCL
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_LEDS 1
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
// LED Device Array Indices
#define AM_BSP_LED0 0
#define AM_BSP_LED_BLUE AM_BSP_LED0
// Corresponding GPIO Numbers
#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED19 AM_BSP_GPIO_LED_BLUE
//*****************************************************************************
//
// PWM_LED peripheral assignments.
//
//*****************************************************************************
//
// The RedBoard Artemis Nano LED is pad 19
//
#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0
#define AM_BSP_PWM_LED_TIMER 1
#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB
#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB1C0
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.c
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#include "am_bsp.h"
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 19.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE =
{
.uFuncSel = AM_HAL_PIN_19_GPIO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA =
{
.uFuncSel = AM_HAL_PIN_36_PDMDATA
};
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK =
{
.uFuncSel = AM_HAL_PIN_37_PDMCLK
};
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX =
{
.uFuncSel = AM_HAL_PIN_48_UART0TX,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX =
{
.uFuncSel = AM_HAL_PIN_49_UART0RX
};
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS =
{
.uFuncSel = AM_HAL_PIN_11_NCE11,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO =
{
.uFuncSel = AM_HAL_PIN_6_M0MISO,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI =
{
.uFuncSel = AM_HAL_PIN_7_M0MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK =
{
.uFuncSel = AM_HAL_PIN_5_M0SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL =
{
.uFuncSel = AM_HAL_PIN_5_M0SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA =
{
.uFuncSel = AM_HAL_PIN_6_M0SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS =
{
.uFuncSel = AM_HAL_PIN_14_NCE14,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 1,
.uNCE = 2,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO =
{
.uFuncSel = AM_HAL_PIN_9_M1MISO,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI =
{
.uFuncSel = AM_HAL_PIN_10_M1MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK =
{
.uFuncSel = AM_HAL_PIN_8_M1SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL =
{
.uFuncSel = AM_HAL_PIN_8_M1SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA =
{
.uFuncSel = AM_HAL_PIN_9_M1SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 2,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO =
{
.uFuncSel = AM_HAL_PIN_25_M2MISO,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI =
{
.uFuncSel = AM_HAL_PIN_28_M2MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK =
{
.uFuncSel = AM_HAL_PIN_27_M2SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL =
{
.uFuncSel = AM_HAL_PIN_27_M2SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA =
{
.uFuncSel = AM_HAL_PIN_25_M2SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS =
{
.uFuncSel = AM_HAL_PIN_12_NCE12,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 3,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO =
{
.uFuncSel = AM_HAL_PIN_43_M3MISO,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI =
{
.uFuncSel = AM_HAL_PIN_38_M3MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK =
{
.uFuncSel = AM_HAL_PIN_42_M3SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL =
{
.uFuncSel = AM_HAL_PIN_42_M3SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA =
{
.uFuncSel = AM_HAL_PIN_43_M3SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS =
{
.uFuncSel = AM_HAL_PIN_13_NCE13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 4,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO =
{
.uFuncSel = AM_HAL_PIN_40_M4MISO,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI =
{
.uFuncSel = AM_HAL_PIN_44_M4MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK =
{
.uFuncSel = AM_HAL_PIN_39_M4SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL =
{
.uFuncSel = AM_HAL_PIN_39_M4SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA =
{
.uFuncSel = AM_HAL_PIN_40_M4SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS =
{
.uFuncSel = AM_HAL_PIN_16_NCE16,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 5,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO =
{
.uFuncSel = AM_HAL_PIN_49_M5MISO,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI =
{
.uFuncSel = AM_HAL_PIN_47_M5MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK =
{
.uFuncSel = AM_HAL_PIN_48_M5SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL =
{
.uFuncSel = AM_HAL_PIN_48_M5SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA =
{
.uFuncSel = AM_HAL_PIN_49_M5SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 =
{
.uFuncSel = AM_HAL_PIN_19_NCE19,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 =
{
.uFuncSel = AM_HAL_PIN_41_NCE41,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 =
{
.uFuncSel = AM_HAL_PIN_22_MSPI0,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 =
{
.uFuncSel = AM_HAL_PIN_26_MSPI1,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 =
{
.uFuncSel = AM_HAL_PIN_4_MSPI2,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 =
{
.uFuncSel = AM_HAL_PIN_23_MSPI13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 =
{
.uFuncSel = AM_HAL_PIN_0_MSPI4,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 =
{
.uFuncSel = AM_HAL_PIN_1_MSPI5,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 =
{
.uFuncSel = AM_HAL_PIN_2_MSPI6,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 =
{
.uFuncSel = AM_HAL_PIN_3_MSPI7,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK =
{
.uFuncSel = AM_HAL_PIN_24_MSPI8,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE =
{
.uFuncSel = AM_HAL_PIN_3_SLnCE,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO =
{
.uFuncSel = AM_HAL_PIN_2_SLMISO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI =
{
.uFuncSel = AM_HAL_PIN_1_SLMOSI,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK =
{
.uFuncSel = AM_HAL_PIN_0_SLSCK,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL =
{
.uFuncSel = AM_HAL_PIN_0_SLSCL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA =
{
.uFuncSel = AM_HAL_PIN_1_SLSDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN
};
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO =
{
.uFuncSel = AM_HAL_PIN_33_SWO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK =
{
.uFuncSel = AM_HAL_PIN_20_SWDCK
};
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO =
{
.uFuncSel = AM_HAL_PIN_21_SWDIO
};
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 19.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_BLUE 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE;
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_DATA 36
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA;
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_CLK 37
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK;
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
#define AM_BSP_GPIO_ITM_SWO 33
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D0 = 25,
D1 = 24,
D2 = 44,
D3 = 35,
D4 = 4,
D5 = 22,
D6 = 23,
D7 = 27,
D8 = 28,
D9 = 32,
D10 = 14,
D11 = 7,
D12 = 6,
D13 = 5,
D14 = 40,
D15 = 39,
D16 = 43,
D17 = 42,
D18 = 26,
D19 = 33,
D20 = 13,
D21 = 11,
D22 = 29,
D23 = 12,
D24 = 31,
// Analog naming
A0 = D19,
A1 = D20,
A2 = D21,
A3 = D22,
A4 = D23,
A5 = D24,
A6 = D3,
//BUTTONs
SW1 = AM_BSP_GPIO_BUTTON0,
// LEDs
LED_BLUE = AM_BSP_GPIO_LED_BLUE,
// mbed original LED naming
LED1 = AM_BSP_GPIO_LED0,
LED2 = D2,
// I2C
I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN,
I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN,
// Qwiic
QWIIC_SCL = I2C_SCL,
QWIIC_SDA = I2C_SDA,
// SPI
SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN,
SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN,
SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN,
// UART
SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN,
SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
SERIAL1_TX = D1,
SERIAL1_RX = D0,
// Not connected
NC = NC_VAL
} PinName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#ifdef __cplusplus
}
#endif
#endif

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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// PDM Microphone
//
//*****************************************************************************
#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT
#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA
#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK
#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA
#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK
//*****************************************************************************
//
// Primary SPI Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_SPI_IOM 0
#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK
#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI
#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO
#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK
#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO
#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI
//*****************************************************************************
//
// Primary UART Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX
#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX
#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX
#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX
//*****************************************************************************
//
// Qwiic Connector.
//
//*****************************************************************************
#define AM_BSP_QWIIC_I2C_IOM 4
#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA
#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL
#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA
#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL
//*****************************************************************************
//
// Button definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_BUTTONS 1
extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS];
#define AM_BSP_GPIO_BUTTON10 AM_BSP_GPIO_BUTTON0
#define AM_BSP_GPIO_SWCH AM_BSP_GPIO_BUTTON0
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_LEDS 1
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
// LED Device Array Indices
#define AM_BSP_LED0 0
#define AM_BSP_LED_BLUE AM_BSP_LED0
// Corresponding GPIO Numbers
#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED18 AM_BSP_GPIO_LED_BLUE
//*****************************************************************************
//
// PWM_LED peripheral assignments.
//
//*****************************************************************************
//
// The Artemis Thing Plus PWM LED is pad 26
//
#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0
#define AM_BSP_PWM_LED_TIMER 0
#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB
#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB0C0
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

874
targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c Normal file
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@ -0,0 +1,874 @@
//*****************************************************************************
//
// am_bsp_pins.c
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#include "am_bsp.h"
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA =
{
.uFuncSel = AM_HAL_PIN_36_PDMDATA
};
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK =
{
.uFuncSel = AM_HAL_PIN_37_PDMCLK
};
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 18.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE =
{
.uFuncSel = AM_HAL_PIN_26_GPIO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// BUTTON0 pin: Labeled 10 on the Artemis Thing Plus.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON0 =
{
.uFuncSel = AM_HAL_PIN_14_GPIO,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX =
{
.uFuncSel = AM_HAL_PIN_48_UART0TX,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX =
{
.uFuncSel = AM_HAL_PIN_49_UART0RX
};
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS =
{
.uFuncSel = AM_HAL_PIN_11_NCE11,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 0,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO =
{
.uFuncSel = AM_HAL_PIN_6_M0MISO,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI =
{
.uFuncSel = AM_HAL_PIN_7_M0MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK =
{
.uFuncSel = AM_HAL_PIN_5_M0SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL =
{
.uFuncSel = AM_HAL_PIN_5_M0SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA =
{
.uFuncSel = AM_HAL_PIN_6_M0SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 0
};
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS =
{
.uFuncSel = AM_HAL_PIN_14_NCE14,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 1,
.uNCE = 2,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO =
{
.uFuncSel = AM_HAL_PIN_9_M1MISO,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI =
{
.uFuncSel = AM_HAL_PIN_10_M1MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK =
{
.uFuncSel = AM_HAL_PIN_8_M1SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL =
{
.uFuncSel = AM_HAL_PIN_8_M1SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA =
{
.uFuncSel = AM_HAL_PIN_9_M1SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 1
};
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS =
{
.uFuncSel = AM_HAL_PIN_15_NCE15,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 2,
.uNCE = 3,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO =
{
.uFuncSel = AM_HAL_PIN_25_M2MISO,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI =
{
.uFuncSel = AM_HAL_PIN_28_M2MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK =
{
.uFuncSel = AM_HAL_PIN_27_M2SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL =
{
.uFuncSel = AM_HAL_PIN_27_M2SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA =
{
.uFuncSel = AM_HAL_PIN_25_M2SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 2
};
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS =
{
.uFuncSel = AM_HAL_PIN_12_NCE12,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 3,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO =
{
.uFuncSel = AM_HAL_PIN_43_M3MISO,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI =
{
.uFuncSel = AM_HAL_PIN_38_M3MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK =
{
.uFuncSel = AM_HAL_PIN_42_M3SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL =
{
.uFuncSel = AM_HAL_PIN_42_M3SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA =
{
.uFuncSel = AM_HAL_PIN_43_M3SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 3
};
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS =
{
.uFuncSel = AM_HAL_PIN_13_NCE13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 4,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO =
{
.uFuncSel = AM_HAL_PIN_40_M4MISO,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI =
{
.uFuncSel = AM_HAL_PIN_44_M4MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK =
{
.uFuncSel = AM_HAL_PIN_39_M4SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL =
{
.uFuncSel = AM_HAL_PIN_39_M4SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA =
{
.uFuncSel = AM_HAL_PIN_40_M4SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 4
};
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS =
{
.uFuncSel = AM_HAL_PIN_16_NCE16,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 5,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO =
{
.uFuncSel = AM_HAL_PIN_49_M5MISO,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI =
{
.uFuncSel = AM_HAL_PIN_47_M5MOSI,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK =
{
.uFuncSel = AM_HAL_PIN_48_M5SCK,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL =
{
.uFuncSel = AM_HAL_PIN_48_M5SCL,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA =
{
.uFuncSel = AM_HAL_PIN_49_M5SDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,
.uIOMnum = 5
};
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 =
{
.uFuncSel = AM_HAL_PIN_19_NCE19,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 =
{
.uFuncSel = AM_HAL_PIN_41_NCE41,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6,
.uNCE = 1,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 =
{
.uFuncSel = AM_HAL_PIN_22_MSPI0,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 =
{
.uFuncSel = AM_HAL_PIN_26_MSPI1,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 =
{
.uFuncSel = AM_HAL_PIN_4_MSPI2,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 =
{
.uFuncSel = AM_HAL_PIN_23_MSPI13,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 =
{
.uFuncSel = AM_HAL_PIN_0_MSPI4,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 =
{
.uFuncSel = AM_HAL_PIN_1_MSPI5,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 =
{
.uFuncSel = AM_HAL_PIN_2_MSPI6,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 =
{
.uFuncSel = AM_HAL_PIN_3_MSPI7,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK =
{
.uFuncSel = AM_HAL_PIN_24_MSPI8,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,
.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI,
.uIOMnum = 6
};
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE =
{
.uFuncSel = AM_HAL_PIN_3_SLnCE,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE,
.uNCE = 0,
.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW
};
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO =
{
.uFuncSel = AM_HAL_PIN_2_SLMISO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA
};
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI =
{
.uFuncSel = AM_HAL_PIN_1_SLMOSI,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK =
{
.uFuncSel = AM_HAL_PIN_0_SLSCK,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL =
{
.uFuncSel = AM_HAL_PIN_0_SLSCL,
.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE
};
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA =
{
.uFuncSel = AM_HAL_PIN_1_SLSDAWIR3,
.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K,
.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN
};
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO =
{
.uFuncSel = AM_HAL_PIN_33_SWO,
.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA
};
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK =
{
.uFuncSel = AM_HAL_PIN_20_SWDCK
};
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO =
{
.uFuncSel = AM_HAL_PIN_21_SWDIO
};
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

592
targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h Normal file
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@ -0,0 +1,592 @@
//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_DATA 36
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA;
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_CLK 37
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK;
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 18.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_BLUE 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE;
//*****************************************************************************
//
// BUTTON0 pin: Labeled 10 on the Artemis Thing Plus.
//
//*****************************************************************************
#define AM_BSP_GPIO_BUTTON0 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON0;
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
#define AM_BSP_GPIO_ITM_SWO 33
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D1 = 1,
D38 = 38,
D36 = 36,
D3 = 3,
// // Analog naming
// No analog pins
// mbed buttons
BUTTON1 = AM_BSP_GPIO_BUTTON0,
// LEDs
LED_RED = AM_BSP_GPIO_LED_RED,
LED_BLUE = AM_BSP_GPIO_LED_BLUE,
LED_GREEN = AM_BSP_GPIO_LED_GREEN,
LED_YELLOW = AM_BSP_GPIO_LED_YELLOW,
// mbed original LED naming
LED1 = AM_BSP_GPIO_LED0,
LED2 = AM_BSP_GPIO_LED1,
LED3 = AM_BSP_GPIO_LED2,
LED4 = AM_BSP_GPIO_LED3,
// I2C
I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN,
I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN,
// Qwiic
QWIIC_SCL = I2C_SCL,
QWIIC_SDA = I2C_SDA,
// SPI
// The SFE_EDGE does not expose a complete IOM peripheral for SPI
// UART
SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN,
SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
// Not connected
NC = NC_VAL
} PinName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#ifdef __cplusplus
}
#endif
#endif

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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Camera
//
//*****************************************************************************
#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 13
#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1
#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA
#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL
#define g_AM_BSP_CAMERA_HM01B0_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA
#define g_AM_BSP_CAMERA_HM01B0_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL
#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 0
#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERB
//*****************************************************************************
//
// Accelerometer.
//
//*****************************************************************************
#define AM_BSP_ACCELEROMETER_I2C_IOM 3
#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19
#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM3_SDA
#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM3_SCL
#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM3_SCL
#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM3_SDA
#define AM_BSP_ACCELEROMETER_INT1_PIN 17
#define AM_BSP_ACCELEROMETER_INT2_PIN 0
//*****************************************************************************
//
// Primary SPI Pins
//
//*****************************************************************************
// The SparkFun Edge does not have a complete IOMaster broken out
//*****************************************************************************
//
// Primary UART Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX
#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX
#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX
#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX
//*****************************************************************************
//
// Qwiic Connector.
//
//*****************************************************************************
#define AM_BSP_QWIIC_I2C_IOM 4
#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA
#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL
#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA
#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL
//*****************************************************************************
//
// Button definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_BUTTONS 1
extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS];
#define AM_BSP_GPIO_BUTTON0 AM_BSP_GPIO_BUTTON14
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_LEDS 4
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
// LED Device Array Indices
#define AM_BSP_LED0 0
#define AM_BSP_LED1 1
#define AM_BSP_LED2 2
#define AM_BSP_LED3 3
#define AM_BSP_LED_RED AM_BSP_LED0
#define AM_BSP_LED_BLUE AM_BSP_LED1
#define AM_BSP_LED_GREEN AM_BSP_LED2
#define AM_BSP_LED_YELLOW AM_BSP_LED3
// Corresponding GPIO Numbers
#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_RED
#define AM_BSP_GPIO_LED1 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED2 AM_BSP_GPIO_LED_GREEN
#define AM_BSP_GPIO_LED3 AM_BSP_GPIO_LED_YELLOW
#define AM_BSP_GPIO_LED46 AM_BSP_GPIO_LED_RED
#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED44 AM_BSP_GPIO_LED_GREEN
#define AM_BSP_GPIO_LED47 AM_BSP_GPIO_LED_YELLOW
//*****************************************************************************
//
// PWM_LED peripheral assignments.
//
//*****************************************************************************
//
// The Edge LED0 is pin 46
//
#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0
#define AM_BSP_PWM_LED_TIMER 6
#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA
#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA6C0
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// CAMERA_HM01B0_D0 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D0 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0;
//*****************************************************************************
//
// CAMERA_HM01B0_D1 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D1 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1;
//*****************************************************************************
//
// CAMERA_HM01B0_D2 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D2 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2;
//*****************************************************************************
//
// CAMERA_HM01B0_D3 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D3 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3;
//*****************************************************************************
//
// CAMERA_HM01B0_D4 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D4 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4;
//*****************************************************************************
//
// CAMERA_HM01B0_D5 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5;
//*****************************************************************************
//
// CAMERA_HM01B0_D6 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D6 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6;
//*****************************************************************************
//
// CAMERA_HM01B0_D7 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D7 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7;
//*****************************************************************************
//
// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC;
//*****************************************************************************
//
// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC;
//*****************************************************************************
//
// CAMERA_HM01B0_PCLK pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK;
//*****************************************************************************
//
// CAMERA_HM01B0_TRIG pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG;
//*****************************************************************************
//
// CAMERA_HM01B0_INT pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_INT 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT;
//*****************************************************************************
//
// CAMERA_HM01B0_DVDDEN pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN;
//*****************************************************************************
//
// MIC0 pin: Analog microphone near camera connector.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC0 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC0;
//*****************************************************************************
//
// MIC1 pin: Analog microphone near LEDs.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC1 29
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC1;
//*****************************************************************************
//
// BUTTON14 pin: Labeled 14 on the SparkFun Edge.
//
//*****************************************************************************
#define AM_BSP_GPIO_BUTTON14 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON14;
//*****************************************************************************
//
// LED_RED pin: The RED LED labelled 46.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_RED 46
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED;
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 37.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_BLUE 37
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE;
//*****************************************************************************
//
// LED_GREEN pin: The GREEN LED labelled 44.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_GREEN 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN;
//*****************************************************************************
//
// LED_YELLOW pin: The YELLOW LED labelled 47.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_YELLOW 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW;
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
#define AM_BSP_GPIO_ITM_SWO 33
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h Normal file
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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "am_bsp.h"
#include "objects_gpio.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define NC_VAL (int)0xFFFFFFFF
typedef enum
{
// Digital naming
D16 = 16,
D31 = 31,
D45 = 45,
D44 = 44,
// Analog naming
A16 = D16,
A31 = D31,
// LEDs
LED_RED = AM_BSP_GPIO_LED_RED,
LED_BLUE = AM_BSP_GPIO_LED_BLUE,
LED_GREEN = AM_BSP_GPIO_LED_GREEN,
LED_YELLOW = AM_BSP_GPIO_LED_BLUE,
// mbed original LED naming
LED1 = AM_BSP_GPIO_LED0,
LED2 = AM_BSP_GPIO_LED1,
LED3 = AM_BSP_GPIO_LED2,
LED4 = AM_BSP_GPIO_LED3,
// LED naming by digital pin number
LED19 = AM_BSP_GPIO_LED19,
LED18 = AM_BSP_GPIO_LED18,
LED17 = AM_BSP_GPIO_LED17,
LED37 = AM_BSP_GPIO_LED37,
// I2C
I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN,
I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN,
// Qwiic
QWIIC_SCL = I2C_SCL,
QWIIC_SDA = I2C_SDA,
// SPI
SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN,
SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN,
SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN,
// UART
SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN,
SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
// Not connected
NC = NC_VAL
} PinName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c Normal file
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//*****************************************************************************
//
// am_bsp.h
//! @file
//!
//! @brief Functions to aid with configuring the GPIOs.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.0.0 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_H
#define AM_BSP_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#include "am_bsp_pins.h"
//
// Make individual includes to not require full port before usage.
//#include "am_devices.h"
//
#include "am_devices_led.h"
#include "am_devices_button.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Begin User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Camera
//
//*****************************************************************************
#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 26
#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1
#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA
#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL
#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 0
#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERB
//*****************************************************************************
//
// PDM Microphone
//
//*****************************************************************************
#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT
#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA
#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK
#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA
#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK
//*****************************************************************************
//
// Accelerometer.
//
//*****************************************************************************
#define AM_BSP_ACCELEROMETER_I2C_IOM 3
#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19
#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM3_SDA
#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM3_SCL
#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM3_SDA
#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM3_SCL
//*****************************************************************************
//
// Primary SPI Pins
//
//*****************************************************************************
// Note: Edge2 can use SPI via the Qwiic connector and GPIO 44
#define AM_BSP_PRIM_SPI_IOM 4
#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM4_SCK
#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM4_MOSI
#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM4_MISO
#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM4_SCK
#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM4_SDO
#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM4_SDI
//*****************************************************************************
//
// Primary UART Pins
//
//*****************************************************************************
#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX
#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX
#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX
#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX
//*****************************************************************************
//
// Qwiic Connector.
//
//*****************************************************************************
#define AM_BSP_QWIIC_I2C_IOM 4
#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA
#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL
#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA
#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL
// //*****************************************************************************
// //
// // Button definitions.
// //
// //*****************************************************************************
// #define AM_BSP_NUM_BUTTONS 0
// extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS];
//*****************************************************************************
//
// LED definitions.
//
//*****************************************************************************
#define AM_BSP_NUM_LEDS 4
extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS];
// LED Device Array Indices
#define AM_BSP_LED0 0
#define AM_BSP_LED1 1
#define AM_BSP_LED2 2
#define AM_BSP_LED3 3
#define AM_BSP_LED_RED AM_BSP_LED0
#define AM_BSP_LED_BLUE AM_BSP_LED1
#define AM_BSP_LED_GREEN AM_BSP_LED2
#define AM_BSP_LED_YELLOW AM_BSP_LED3
// Corresponding GPIO Numbers
#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_RED
#define AM_BSP_GPIO_LED1 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED2 AM_BSP_GPIO_LED_GREEN
#define AM_BSP_GPIO_LED3 AM_BSP_GPIO_LED_YELLOW
#define AM_BSP_GPIO_LED19 AM_BSP_GPIO_LED_RED
#define AM_BSP_GPIO_LED18 AM_BSP_GPIO_LED_BLUE
#define AM_BSP_GPIO_LED17 AM_BSP_GPIO_LED_GREEN
#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_YELLOW
//*****************************************************************************
//
// PWM_LED peripheral assignments.
//
//*****************************************************************************
//
// The Edge2 LED0 is pin 19
//
#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0
#define AM_BSP_PWM_LED_TIMER 1
#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB
#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB1C0
//*****************************************************************************
//
// UART definitions.
//
//*****************************************************************************
//
// Apollo3 has two UART instances.
// AM_BSP_UART_PRINT_INST should correspond to COM_UART.
//
#define AM_BSP_UART_IOS_INST 0
#define AM_BSP_UART_PRINT_INST 0
#define AM_BSP_UART_BOOTLOADER_INST 0
//*****************************************************************************
//
// End User Modifiable Area
//
//*****************************************************************************
//*****************************************************************************
//
// Print interface type
//
//*****************************************************************************
#define AM_BSP_PRINT_INFC_NONE 0
#define AM_BSP_PRINT_INFC_SWO 1
#define AM_BSP_PRINT_INFC_UART0 2
#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3
//*****************************************************************************
//
//! Structure containing UART configuration information while it is powered down.
//
//*****************************************************************************
typedef struct
{
bool bSaved;
uint32_t ui32TxPinNum;
uint32_t ui32TxPinCfg;
}
am_bsp_uart_pwrsave_t;
//*****************************************************************************
//
// External data definitions.
//
//*****************************************************************************
extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES];
//*****************************************************************************
//
// External function definitions.
//
//*****************************************************************************
extern void am_bsp_low_power_init(void);
extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode);
extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice);
extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions
extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode);
extern void am_bsp_debug_printf_enable(void);
extern void am_bsp_debug_printf_disable(void);
#ifdef AM_BSP_GPIO_ITM_SWO
extern void am_bsp_itm_printf_enable(void);
#else
extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg);
#endif
extern void am_bsp_itm_string_print(char *pcString);
extern void am_bsp_itm_printf_disable(void);
extern void am_bsp_uart_string_print(char *pcString);
extern void am_bsp_uart_printf_enable(void);
extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config);
extern void am_bsp_uart_printf_disable(void);
extern void am_bsp_buffered_uart_printf_enable(void);
extern void am_bsp_buffered_uart_service(void);
extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer);
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// am_bsp_pins.h
//! @file
//!
//! @brief BSP pin configuration definitions.
//!
//! @addtogroup BSP Board Support Package (BSP)
//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
//! @ingroup BSP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_BSP_PINS_H
#define AM_BSP_PINS_H
#include <stdint.h>
#include <stdbool.h>
#include "am_mcu_apollo.h"
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// CAMERA_HM01B0_D0 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D0 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0;
//*****************************************************************************
//
// CAMERA_HM01B0_D1 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D1 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1;
//*****************************************************************************
//
// CAMERA_HM01B0_D2 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D2 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2;
//*****************************************************************************
//
// CAMERA_HM01B0_D3 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D3 34
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3;
//*****************************************************************************
//
// CAMERA_HM01B0_D4 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D4 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4;
//*****************************************************************************
//
// CAMERA_HM01B0_D5 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5;
//*****************************************************************************
//
// CAMERA_HM01B0_D6 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D6 35
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6;
//*****************************************************************************
//
// CAMERA_HM01B0_D7 pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_D7 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7;
//*****************************************************************************
//
// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC;
//*****************************************************************************
//
// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC;
//*****************************************************************************
//
// CAMERA_HM01B0_PCLK pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK;
//*****************************************************************************
//
// CAMERA_HM01B0_TRIG pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG;
//*****************************************************************************
//
// CAMERA_HM01B0_INT pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_INT 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT;
//*****************************************************************************
//
// CAMERA_HM01B0_DVDDEN pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN 32
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN;
//*****************************************************************************
//
// MIC_DATA pin: Data line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_DATA 29
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA;
//*****************************************************************************
//
// MIC_CLK pin: Clock line for PDM microphones.
//
//*****************************************************************************
#define AM_BSP_GPIO_MIC_CLK 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK;
//*****************************************************************************
//
// LED_RED pin: The RED LED labelled 19.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_RED 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED;
//*****************************************************************************
//
// LED_BLUE pin: The BLUE LED labelled 18.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_BLUE 18
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE;
//*****************************************************************************
//
// LED_GREEN pin: The GREEN LED labelled 17.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_GREEN 17
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN;
//*****************************************************************************
//
// LED_YELLOW pin: The YELLOW LED labelled 37.
//
//*****************************************************************************
#define AM_BSP_GPIO_LED_YELLOW 37
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW;
//*****************************************************************************
//
// COM_UART_TX pin: This pin is the COM_UART transmit pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_TX 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX;
//*****************************************************************************
//
// COM_UART_RX pin: This pin is the COM_UART receive pin.
//
//*****************************************************************************
#define AM_BSP_GPIO_COM_UART_RX 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX;
//*****************************************************************************
//
// IOM0_CS pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS 11
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS;
#define AM_BSP_IOM0_CS_CHNL 0
//*****************************************************************************
//
// IOM0_CS3 pin: I/O Master 0 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_CS3 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3;
#define AM_BSP_IOM0_CS3_CHNL 3
//*****************************************************************************
//
// IOM0_MISO pin: I/O Master 0 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MISO 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO;
//*****************************************************************************
//
// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_MOSI 7
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI;
//*****************************************************************************
//
// IOM0_SCK pin: I/O Master 0 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCK 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK;
//*****************************************************************************
//
// IOM0_SCL pin: I/O Master 0 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SCL 5
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL;
//*****************************************************************************
//
// IOM0_SDA pin: I/O Master 0 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM0_SDA 6
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA;
//*****************************************************************************
//
// IOM1_CS pin: I/O Master 1 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_CS 14
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS;
#define AM_BSP_IOM1_CS_CHNL 2
//*****************************************************************************
//
// IOM1_MISO pin: I/O Master 1 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MISO 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO;
//*****************************************************************************
//
// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_MOSI 10
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI;
//*****************************************************************************
//
// IOM1_SCK pin: I/O Master 1 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCK 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK;
//*****************************************************************************
//
// IOM1_SCL pin: I/O Master 1 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SCL 8
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL;
//*****************************************************************************
//
// IOM1_SDA pin: I/O Master 1 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM1_SDA 9
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA;
//*****************************************************************************
//
// IOM2_CS pin: I/O Master 2 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_CS 15
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS;
#define AM_BSP_IOM2_CS_CHNL 3
//*****************************************************************************
//
// IOM2_MISO pin: I/O Master 2 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MISO 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO;
//*****************************************************************************
//
// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_MOSI 28
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI;
//*****************************************************************************
//
// IOM2_SCK pin: I/O Master 2 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCK 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK;
//*****************************************************************************
//
// IOM2_SCL pin: I/O Master 2 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SCL 27
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL;
//*****************************************************************************
//
// IOM2_SDA pin: I/O Master 2 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM2_SDA 25
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA;
//*****************************************************************************
//
// IOM3_CS pin: I/O Master 3 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_CS 12
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS;
#define AM_BSP_IOM3_CS_CHNL 0
//*****************************************************************************
//
// IOM3_MISO pin: I/O Master 3 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MISO 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO;
//*****************************************************************************
//
// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_MOSI 38
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI;
//*****************************************************************************
//
// IOM3_SCK pin: I/O Master 3 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCK 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK;
//*****************************************************************************
//
// IOM3_SCL pin: I/O Master 3 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SCL 42
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL;
//*****************************************************************************
//
// IOM3_SDA pin: I/O Master 3 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM3_SDA 43
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA;
//*****************************************************************************
//
// IOM4_CS pin: I/O Master 4 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_CS 13
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS;
#define AM_BSP_IOM4_CS_CHNL 1
//*****************************************************************************
//
// IOM4_MISO pin: I/O Master 4 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MISO 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO;
//*****************************************************************************
//
// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_MOSI 44
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI;
//*****************************************************************************
//
// IOM4_SCK pin: I/O Master 4 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCK 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK;
//*****************************************************************************
//
// IOM4_SCL pin: I/O Master 4 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SCL 39
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL;
//*****************************************************************************
//
// IOM4_SDA pin: I/O Master 4 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM4_SDA 40
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA;
//*****************************************************************************
//
// IOM5_CS pin: I/O Master 5 chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_CS 16
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS;
#define AM_BSP_IOM5_CS_CHNL 0
//*****************************************************************************
//
// IOM5_MISO pin: I/O Master 5 SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MISO 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO;
//*****************************************************************************
//
// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_MOSI 47
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI;
//*****************************************************************************
//
// IOM5_SCK pin: I/O Master 5 SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCK 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK;
//*****************************************************************************
//
// IOM5_SCL pin: I/O Master 5 I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SCL 48
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL;
//*****************************************************************************
//
// IOM5_SDA pin: I/O Master 5 I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOM5_SDA 49
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA;
//*****************************************************************************
//
// MSPI_CE0 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE0 19
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0;
#define AM_BSP_MSPI_CE0_CHNL 0
//*****************************************************************************
//
// MSPI_CE1 pin: MSPI chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_CE1 41
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1;
#define AM_BSP_MSPI_CE1_CHNL 1
//*****************************************************************************
//
// MSPI_D0 pin: MSPI data 0.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D0 22
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0;
//*****************************************************************************
//
// MSPI_D1 pin: MSPI data 1.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D1 26
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1;
//*****************************************************************************
//
// MSPI_D2 pin: MSPI data 2.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D2 4
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2;
//*****************************************************************************
//
// MSPI_D3 pin: MSPI data 3.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D3 23
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3;
//*****************************************************************************
//
// MSPI_D4 pin: MSPI data 4.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D4 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4;
//*****************************************************************************
//
// MSPI_D5 pin: MSPI data 5.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D5 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5;
//*****************************************************************************
//
// MSPI_D6 pin: MSPI data 6.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D6 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6;
//*****************************************************************************
//
// MSPI_D7 pin: MSPI data 7.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_D7 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7;
//*****************************************************************************
//
// MSPI_SCK pin: MSPI clock.
//
//*****************************************************************************
#define AM_BSP_GPIO_MSPI_SCK 24
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK;
//*****************************************************************************
//
// IOS_CE pin: I/O Slave chip select.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_CE 3
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE;
#define AM_BSP_IOS_CE_CHNL 0
//*****************************************************************************
//
// IOS_MISO pin: I/O Slave SPI MISO signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MISO 2
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO;
//*****************************************************************************
//
// IOS_MOSI pin: I/O Slave SPI MOSI signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_MOSI 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI;
//*****************************************************************************
//
// IOS_SCK pin: I/O Slave SPI SCK signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCK 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK;
//*****************************************************************************
//
// IOS_SCL pin: I/O Slave I2C clock signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SCL 0
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL;
//*****************************************************************************
//
// IOS_SDA pin: I/O Slave I2C data signal.
//
//*****************************************************************************
#define AM_BSP_GPIO_IOS_SDA 1
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA;
//*****************************************************************************
//
// ITM_SWO pin: ITM Serial Wire Output.
//
//*****************************************************************************
#define AM_BSP_GPIO_ITM_SWO 33
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO;
//*****************************************************************************
//
// SWDCK pin: Cortex Serial Wire DCK.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDCK 20
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK;
//*****************************************************************************
//
// SWDIO pin: Cortex Serial Wire DIO.
//
//*****************************************************************************
#define AM_BSP_GPIO_SWDIO 21
extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO;
#ifdef __cplusplus
}
#endif
#endif // AM_BSP_PINS_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

55
targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct Normal file
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#! armcc -E
;
; Copyright (c) 2019-2020 SparkFun Electronics
; SPDX-License-Identifier: MIT
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
;
#define MBED_APP_START 0x0000C000
#define MBED_APP_SIZE 0x000F4000
#define MBED_RAM_START 0x10000000
#define MBED_RAM_SIZE 0x60000
#define MBED_RAM0_START MBED_RAM_START
#define MBED_RAM0_SIZE 0x100
#define MBED_RAM1_START (MBED_RAM0_START + MBED_RAM0_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE))
#define Stack_Size MBED_BOOT_STACK_SIZE
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+MBED_RAM0_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM0 MBED_RAM0_START UNINIT MBED_RAM0_SIZE { ;no init section
*(*nvictable)
}
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK MBED_RAM1_START+MBED_RAM1_SIZE-8 EMPTY -Stack_Size { ; Stack region growing down
}
}

345
targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S Normal file
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;******************************************************************************
;
;! @file startup_keil.s
;!
;! @brief Definitions for Apollo3 interrupt handlers, the vector table, and the stack.
;
;******************************************************************************
;******************************************************************************
;
; Copyright (c) 2020, Ambiq Micro
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; Third party software included in this distribution is subject to the
; additional license terms as defined in the /docs/licenses directory.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; This is part of revision 2.4.2 of the AmbiqSuite Development Package.
;
;******************************************************************************
; SPDX-License-Identifier: BSD-3-Clause
;******************************************************************************
;
; Indicate that the code in this file preserves 8-byte alignment of the stack.
;
;******************************************************************************
PRESERVE8
;******************************************************************************
;
; Place code into the reset code section.
;
;******************************************************************************
AREA RESET, CODE, READONLY
THUMB
;******************************************************************************
;
; The vector table.
;
;******************************************************************************
;
; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
; am_usagefault_isr does not work if am_fault_isr is defined externally.
; Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
;
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors
DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; The MPU fault handler
DCD BusFault_Handler ; The bus fault handler
DCD UsageFault_Handler ; The usage fault handler
DCD SecureFault_Handler ; Secure fault handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall handler
DCD DebugMon_Handler ; Debug monitor handler
DCD 0 ; Reserved
DCD PendSV_Handler ; The PendSV handler
DCD SysTick_Handler ; The SysTick handler
;
; Peripheral Interrupts
;
DCD am_brownout_isr ; 0: Reserved
DCD am_watchdog_isr ; 1: Reserved
DCD am_rtc_isr ; 2: RTC
DCD am_vcomp_isr ; 3: Voltage Comparator
DCD am_ioslave_ios_isr ; 4: I/O Slave general
DCD am_ioslave_acc_isr ; 5: I/O Slave access
DCD am_iomaster0_isr ; 6: I/O Master 0
DCD am_iomaster1_isr ; 7: I/O Master 1
DCD am_iomaster2_isr ; 8: I/O Master 2
DCD am_iomaster3_isr ; 9: I/O Master 3
DCD am_iomaster4_isr ; 10: I/O Master 4
DCD am_iomaster5_isr ; 11: I/O Master 5
DCD HciDrvIntService ; 12: BLEIF
DCD am_gpio_isr ; 13: GPIO
DCD am_ctimer_isr ; 14: CTIMER
DCD am_uart_isr ; 15: UART0
DCD am_uart1_isr ; 16: UART1
DCD am_scard_isr ; 17: SCARD
DCD am_adc_isr ; 18: ADC
DCD am_pdm0_isr ; 19: PDM
DCD am_mspi0_isr ; 20: MSPI0
DCD am_software0_isr ; 21: SOFTWARE0
DCD am_stimer_isr ; 22: SYSTEM TIMER
DCD am_stimer_cmpr0_isr ; 23: SYSTEM TIMER COMPARE0
DCD am_stimer_cmpr1_isr ; 24: SYSTEM TIMER COMPARE1
DCD am_stimer_cmpr2_isr ; 25: SYSTEM TIMER COMPARE2
DCD am_stimer_cmpr3_isr ; 26: SYSTEM TIMER COMPARE3
DCD am_stimer_cmpr4_isr ; 27: SYSTEM TIMER COMPARE4
DCD am_stimer_cmpr5_isr ; 28: SYSTEM TIMER COMPARE5
DCD am_stimer_cmpr6_isr ; 29: SYSTEM TIMER COMPARE6
DCD am_stimer_cmpr7_isr ; 30: SYSTEM TIMER COMPARE7
DCD am_clkgen_isr ; 31: CLKGEN
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
;******************************************************************************
;
; Place code immediately following vector table.
;
;******************************************************************************
;******************************************************************************
;
; The Patch table.
;
; The patch table should pad the vector table size to a total of 64 entries
; (16 core + 48 periph) such that code begins at offset 0x100.
;
;******************************************************************************
EXPORT __Patchable
__Patchable
DCD 0 ; 32
DCD 0 ; 33
DCD 0 ; 34
DCD 0 ; 35
DCD 0 ; 36
DCD 0 ; 37
DCD 0 ; 38
DCD 0 ; 39
DCD 0 ; 40
DCD 0 ; 41
DCD 0 ; 42
DCD 0 ; 43
DCD 0 ; 44
DCD 0 ; 45
DCD 0 ; 46
DCD 0 ; 47
;******************************************************************************
;
; This is the code that gets called when the processor first starts execution
; following a reset event.
;
;******************************************************************************
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
;
; Enable the FPU.
;
MOVW R0, #0xED88
MOVT R0, #0xE000
LDR R1, [R0]
ORR R1, #0x00F00000
STR R1, [R0]
DSB
ISB
;
; Branch to main.
;
LDR R0, =__main
BX R0
ENDP
;******************************************************************************
;
; Weak Exception Handlers.
;
;******************************************************************************
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SecureFault_Handler\
PROC
EXPORT SecureFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
am_default_isr\
PROC
EXPORT am_brownout_isr [WEAK]
EXPORT am_watchdog_isr [WEAK]
EXPORT am_rtc_isr [WEAK]
EXPORT am_vcomp_isr [WEAK]
EXPORT am_ioslave_ios_isr [WEAK]
EXPORT am_ioslave_acc_isr [WEAK]
EXPORT am_iomaster0_isr [WEAK]
EXPORT am_iomaster1_isr [WEAK]
EXPORT am_iomaster2_isr [WEAK]
EXPORT am_iomaster3_isr [WEAK]
EXPORT am_iomaster4_isr [WEAK]
EXPORT am_iomaster5_isr [WEAK]
EXPORT HciDrvIntService [WEAK]
EXPORT am_gpio_isr [WEAK]
EXPORT am_ctimer_isr [WEAK]
EXPORT am_uart_isr [WEAK]
EXPORT am_uart0_isr [WEAK]
EXPORT am_uart1_isr [WEAK]
EXPORT am_scard_isr [WEAK]
EXPORT am_adc_isr [WEAK]
EXPORT am_pdm0_isr [WEAK]
EXPORT am_mspi0_isr [WEAK]
EXPORT am_software0_isr [WEAK]
EXPORT am_stimer_isr [WEAK]
EXPORT am_stimer_cmpr0_isr [WEAK]
EXPORT am_stimer_cmpr1_isr [WEAK]
EXPORT am_stimer_cmpr2_isr [WEAK]
EXPORT am_stimer_cmpr3_isr [WEAK]
EXPORT am_stimer_cmpr4_isr [WEAK]
EXPORT am_stimer_cmpr5_isr [WEAK]
EXPORT am_stimer_cmpr6_isr [WEAK]
EXPORT am_stimer_cmpr7_isr [WEAK]
EXPORT am_clkgen_isr [WEAK]
am_brownout_isr
am_watchdog_isr
am_rtc_isr
am_vcomp_isr
am_ioslave_ios_isr
am_ioslave_acc_isr
am_iomaster0_isr
am_iomaster1_isr
am_iomaster2_isr
am_iomaster3_isr
am_iomaster4_isr
am_iomaster5_isr
HciDrvIntService
am_gpio_isr
am_ctimer_isr
am_uart_isr
am_uart0_isr
am_uart1_isr
am_scard_isr
am_adc_isr
am_pdm0_isr
am_mspi0_isr
am_software0_isr
am_stimer_isr
am_stimer_cmpr0_isr
am_stimer_cmpr1_isr
am_stimer_cmpr2_isr
am_stimer_cmpr3_isr
am_stimer_cmpr4_isr
am_stimer_cmpr5_isr
am_stimer_cmpr6_isr
am_stimer_cmpr7_isr
am_clkgen_isr
; all device interrupts go here unless the weak label is over
; ridden in the linker hard spin so the debugger will know it
; was an unhandled interrupt request a come-from-buffer or
; instruction trace hardware would sure be nice if you get here
B .
ENDP
;******************************************************************************
;
; Align the end of the section.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; All Done
;
;******************************************************************************
END

194
targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld Normal file
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/*
* Copyright (c) 2019-2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* stack: dynamic */
/* heap: dynamic */
#define MBED_APP_START 0x0000C000
#define MBED_APP_LENGTH 0x000F4000
#define MBED_RAM_START 0x10000000
#define MBED_RAM_SIZE 384K
#define MBED_BOOT_STACK_SIZE 0x400
#define MBED_RAM0_START MBED_RAM_START
#define MBED_RAM0_SIZE 0x100
#define MBED_RAM1_START (MBED_RAM0_START + MBED_RAM0_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE))
ENTRY(Reset_Handler)
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_LENGTH /*Modified from 0xC000 to work with SparkFun SVL*/
RAM_NVIC (rwx) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE
RAM (rwx) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE
}
SECTIONS
{
/* text: executable code */
/* located in _flash_ */
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector))
KEEP(*(.ble_patch))
*(.text)
*(.text*)
/* __init_array_start = .;
KEEP(*(.init_array*))
__init_array_end = .; */ /* does this mess up _init()?' it was from Arduinoland (aka owen) */
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* .rodata */
. = ALIGN(4);
*(.rodata)
*(.rodata*)
KEEP(*(.eh_frame*))
. = ALIGN(4);
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = ALIGN(8);
.data : AT (__etext)
{
__data_start__ = .;
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM
/* Uninitialized data section
* This region is not initialized by the C/C++ library and can be used to
* store state across soft reboots. */
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
/* bss: zero-initialized symbols */
/* don't require flash memory to remember their value */
.bss :
{
. = ALIGN(8);
_sbss = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(8);
_ebss = .;
__bss_end__ = .;
} > RAM
/* heap: RAM memory that can be dynamically allocated in the upward direction (increasing memory addresses) */
/* _sheap is used to identify the beginning of available dynamic memory */
.heap (NOLOAD):
{
. = ALIGN(4);
__end__ = .;
PROVIDE( end = . );
_sheap = .;
. = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE-8;
__HeapLimit = .;
} >RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later*/
.stack_dummy (NOLOAD):
{
. = ALIGN(8);
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section*/
__StackTop = ORIGIN(RAM) + LENGTH(RAM)-8;
__StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;
PROVIDE(__stack = __StackTop);
PROVIDE(_sstack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit*/
/*ASSERT(1, "region RAM overflowed with stack")*/
/* test test test */
}

347
targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c Normal file
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//*****************************************************************************
//
//! @file startup_gcc.c
//!
//! @brief Definitions for interrupt handlers, the vector table, and the stack.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2019, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#include "apollo3.h"
#include <stdint.h>
//*****************************************************************************
//
// Forward declaration of interrupt handlers.
//
//*****************************************************************************
extern void Reset_Handler(void) __attribute((naked));
extern void NMI_Handler(void) __attribute((weak));
extern void HardFault_Handler(void) __attribute((weak));
extern void MemManage_Handler(void) __attribute((weak, alias("HardFault_Handler")));
extern void BusFault_Handler(void) __attribute((weak, alias("HardFault_Handler")));
extern void UsageFault_Handler(void) __attribute((weak, alias("HardFault_Handler")));
extern void SecureFault_Handler(void) __attribute((weak));
extern void SVC_Handler(void) __attribute((weak, alias("am_default_isr")));
extern void DebugMon_Handler(void) __attribute((weak, alias("am_default_isr")));
extern void PendSV_Handler(void) __attribute((weak, alias("am_default_isr")));
extern void SysTick_Handler(void) __attribute((weak, alias("am_default_isr")));
extern void am_brownout_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_watchdog_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_rtc_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_vcomp_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_ioslave_ios_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_ioslave_acc_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_iomaster0_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_iomaster1_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_iomaster2_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_iomaster3_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_iomaster4_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_iomaster5_isr(void) __attribute((weak, alias("am_default_isr")));
extern void HciDrvIntService(void); //__attribute((weak, alias("am_default_isr")));
extern void am_gpio_isr(void); //__attribute((weak, alias("am_default_isr")));
extern void am_ctimer_isr(void); //__attribute((weak, alias("am_default_isr")));
extern void am_uart_isr(void); //__attribute((weak, alias("am_default_isr")));
extern void am_uart1_isr(void); //__attribute((weak, alias("am_default_isr")));
extern void am_scard_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_adc_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_pdm0_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_mspi0_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_software0_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr0_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr1_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr2_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr3_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr4_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr5_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr6_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_stimer_cmpr7_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_clkgen_isr(void) __attribute((weak, alias("am_default_isr")));
extern void am_default_isr(void) __attribute((weak));
// // Entry Point for mbed boot sequence
// extern void __main(void);
// extern void _start(void);
extern void mbed_init(void);
//*****************************************************************************
//
// The entry point for the application.
//
//*****************************************************************************
extern int main(void);
// '__stack' accesses the linker-provided address for the start of the stack
// (which is a high address - stack goes top to bottom)
extern void *__stack;
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
// am_usagefault_isr does not work if am_fault_isr is defined externally.
// Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
//
//*****************************************************************************
__attribute__((section(".isr_vector"))) void (*const g_am_pfnVectors[])(void) =
{
(void (*)(void))(&__stack), // The initial stack pointer (provided by linker script)
Reset_Handler, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MemManage_Handler
BusFault_Handler, // The BusFault_Handler
UsageFault_Handler, // The UsageFault_Handler
SecureFault_Handler, // The SecureFault_Handler
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
//
// Peripheral Interrupts
//
am_brownout_isr, // 0: Brownout (rstgen)
am_watchdog_isr, // 1: Watchdog
am_rtc_isr, // 2: RTC
am_vcomp_isr, // 3: Voltage Comparator
am_ioslave_ios_isr, // 4: I/O Slave general
am_ioslave_acc_isr, // 5: I/O Slave access
am_iomaster0_isr, // 6: I/O Master 0
am_iomaster1_isr, // 7: I/O Master 1
am_iomaster2_isr, // 8: I/O Master 2
am_iomaster3_isr, // 9: I/O Master 3
am_iomaster4_isr, // 10: I/O Master 4
am_iomaster5_isr, // 11: I/O Master 5
HciDrvIntService, // 12: BLEIF
am_gpio_isr, // 13: GPIO
am_ctimer_isr, // 14: CTIMER
am_uart_isr, // 15: UART0
am_uart1_isr, // 16: UART1
am_scard_isr, // 17: SCARD
am_adc_isr, // 18: ADC
am_pdm0_isr, // 19: PDM
am_mspi0_isr, // 20: MSPI0
am_software0_isr, // 21: SOFTWARE0
am_stimer_isr, // 22: SYSTEM TIMER
am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0
am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1
am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2
am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3
am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4
am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5
am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6
am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7
am_clkgen_isr, // 31: CLKGEN
};
//******************************************************************************
//
// Place code immediately following vector table.
//
//******************************************************************************
//******************************************************************************
//
// The Patch table.
//
// The patch table should pad the vector table size to a total of 64 entries
// (16 core + 48 periph) such that code begins at offset 0x100.
//
//******************************************************************************
__attribute__((section(".ble_patch")))
uint32_t const __Patchable[] =
{
0, // 32
0, // 33
0, // 34
0, // 35
0, // 36
0, // 37
0, // 38
0, // 39
0, // 40
0, // 41
0, // 42
0, // 43
0, // 44
0, // 45
0, // 46
0, // 47
};
// //*****************************************************************************
// //
// // The following are constructs created by the linker, indicating where the
// // the "data" and "bss" segments reside in memory. The initializers for the
// // "data" segment resides immediately following the "text" segment.
// //
// //*****************************************************************************
// extern uint32_t _etext;
// extern uint32_t __data_start__;
// extern uint32_t __data_end__;
// extern uint32_t _sbss;
// extern uint32_t _ebss;
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.
//
//*****************************************************************************
#if defined(__GNUC_STDC_INLINE__)
void Reset_Handler(void)
{
//
// Set the vector table pointer.
//
__asm(" ldr r0, =0xE000ED08\n"
" ldr r1, =g_am_pfnVectors\n"
" str r1, [r0]");
// //
// // Set the stack pointer.
// //
__asm(" ldr sp, [r1]");
#ifndef NOFPU
// //
// // Enable the FPU.
// //
__asm("ldr r0, =0xE000ED88\n"
"ldr r1,[r0]\n"
"orr r1,#(0xF << 20)\n"
"str r1,[r0]\n"
"dsb\n"
"isb\n");
#endif
// // Start mbed boot sequence https://os.mbed.com/docs/mbed-os/v5.15/reference/bootstrap.html
// SystemInit();
// _start();
//
// Copy the data segment initializers from flash to SRAM.
//
__asm(" ldr r0, =__etext\n"
" ldr r1, =__data_start__\n"
" ldr r2, =__data_end__\n"
"copy_loop:\n"
" cmp r1, r2\n"
" beq copy_end\n"
" ldr r3, [r0], #4\n"
" str r3, [r1], #4\n"
" b copy_loop\n"
"copy_end:\n");
// //
// // Zero fill the bss segment.
// //
__asm("LDR R0, =_start\n"
"BX R0\n");
//
// If main returns then execute a break point instruction
//
__asm(" bkpt ");
}
#else
#error GNU STDC inline not supported.
#endif
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
void NMI_Handler(void)
{
//
// Go into an infinite loop.
//
while (1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void HardFault_Handler(void)
{
//
// Go into an infinite loop.
//
while (1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void am_default_isr(void)
{
//
// Go into an infinite loop.
//
while (1)
{
}
}

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// SPDX-License-Identifier: Apache-2.0
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define STDIO_UART UART_0
typedef enum {
UART_0 = 0,
UART_1,
UART_NUM,
UART_ANY
} UARTName;
typedef enum {
IOM_0 = 0,
IOM_1,
IOM_2,
IOM_3,
IOM_4,
IOM_5,
IOM_NUM,
IOM_ANY
} IOMName;
typedef IOMName SPIName;
typedef IOMName I2CName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// SPDX-License-Identifier: Apache-2.0
#include "PeripheralPins.h"
#include "PeripheralPinConfigs.h"
/************RTC***************/
const PinMap PinMap_RTC[] = {
{NC, 0, 0},
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{NC, NC, 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{NC, NC, 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{AP3_PER_IOM0_SDA, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SDA},
{AP3_PER_IOM1_SDA, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SDA},
{AP3_PER_IOM2_SDA, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SDA},
{AP3_PER_IOM4_SDA, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SDA},
{AP3_PER_IOM5_SDA, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SDA},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_IOM3_SDA, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SDA},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
{AP3_PER_IOM0_SCL, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCL},
{AP3_PER_IOM1_SCL, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCL},
{AP3_PER_IOM2_SCL, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCL},
{AP3_PER_IOM4_SCL, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCL},
{AP3_PER_IOM5_SCL, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCL},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_IOM3_SCL, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCL},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{AP3_PER_UART0_TX_1, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_1},
{AP3_PER_UART0_TX_7, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_7},
{AP3_PER_UART0_TX_16, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_16},
{AP3_PER_UART0_TX_20, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_20},
{AP3_PER_UART0_TX_22, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_22},
{AP3_PER_UART0_TX_26, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_26},
{AP3_PER_UART0_TX_28, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_28},
{AP3_PER_UART0_TX_39, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_39},
{AP3_PER_UART0_TX_41, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_41},
{AP3_PER_UART0_TX_44, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_44},
{AP3_PER_UART0_TX_48, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_48},
{AP3_PER_UART1_TX_8, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_8},
{AP3_PER_UART1_TX_10, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_10},
{AP3_PER_UART1_TX_12, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_12},
{AP3_PER_UART1_TX_14, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_14},
{AP3_PER_UART1_TX_18, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_18},
{AP3_PER_UART1_TX_20, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_20},
{AP3_PER_UART1_TX_24, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_24},
{AP3_PER_UART1_TX_39, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_39},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_UART0_TX_30, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_30},
{AP3_PER_UART1_TX_35, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_35},
{AP3_PER_UART1_TX_37, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_37},
{AP3_PER_UART1_TX_42, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_42},
{AP3_PER_UART1_TX_46, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_46},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{AP3_PER_UART0_RX_2, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_2},
{AP3_PER_UART0_RX_11, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_11},
{AP3_PER_UART0_RX_17, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_17},
{AP3_PER_UART0_RX_21, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_21},
{AP3_PER_UART0_RX_23, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_23},
{AP3_PER_UART0_RX_27, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_27},
{AP3_PER_UART0_RX_29, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_29},
{AP3_PER_UART0_RX_40, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_40},
{AP3_PER_UART0_RX_49, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_49},
{AP3_PER_UART1_RX_2, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_2},
{AP3_PER_UART1_RX_4, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_4},
{AP3_PER_UART1_RX_9, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_9},
{AP3_PER_UART1_RX_13, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_13},
{AP3_PER_UART1_RX_15, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_15},
{AP3_PER_UART1_RX_19, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_19},
{AP3_PER_UART1_RX_21, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_21},
{AP3_PER_UART1_RX_25, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_25},
{AP3_PER_UART1_RX_40, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_40},
{AP3_PER_UART1_RX_47, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_47},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_UART0_RX_31, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_31},
{AP3_PER_UART0_RX_34, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_34},
{AP3_PER_UART0_RX_45, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_45},
{AP3_PER_UART1_RX_36, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_36},
{AP3_PER_UART1_RX_38, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_38},
{AP3_PER_UART1_RX_43, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_43},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{3, UART_0, AM_HAL_PIN_3_UART0RTS},
{5, UART_0, AM_HAL_PIN_5_UART0RTS},
{13, UART_0, AM_HAL_PIN_13_UART0RTS},
{18, UART_0, AM_HAL_PIN_18_UART0RTS},
{41, UART_0, AM_HAL_PIN_41_UART0RTS},
{10, UART_1, AM_HAL_PIN_10_UART1RTS},
{16, UART_1, AM_HAL_PIN_16_UART1RTS},
{20, UART_1, AM_HAL_PIN_20_UART1RTS},
{41, UART_1, AM_HAL_PIN_41_UART1RTS},
{44, UART_1, AM_HAL_PIN_44_UART1RTS},
#if defined (AM_PACKAGE_BGA)
{34, UART_0, AM_HAL_PIN_34_UART0RTS},
{35, UART_0, AM_HAL_PIN_35_UART0RTS},
{37, UART_0, AM_HAL_PIN_37_UART0RTS},
{30, UART_1, AM_HAL_PIN_30_UART1RTS},
{31, UART_1, AM_HAL_PIN_31_UART1RTS},
{34, UART_1, AM_HAL_PIN_34_UART1RTS},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{4, UART_0, AM_HAL_PIN_4_UART0CTS},
{6, UART_0, AM_HAL_PIN_6_UART0CTS},
{12, UART_0, AM_HAL_PIN_12_UART0CTS},
{24, UART_0, AM_HAL_PIN_24_UART0CTS},
{29, UART_0, AM_HAL_PIN_29_UART0CTS},
{11, UART_1, AM_HAL_PIN_11_UART1CTS},
{17, UART_1, AM_HAL_PIN_17_UART1CTS},
{21, UART_1, AM_HAL_PIN_21_UART1CTS},
{26, UART_1, AM_HAL_PIN_26_UART1CTS},
{29, UART_1, AM_HAL_PIN_29_UART1CTS},
#if defined (AM_PACKAGE_BGA)
{33, UART_0, AM_HAL_PIN_33_UART0CTS},
{36, UART_0, AM_HAL_PIN_36_UART0CTS},
{38, UART_0, AM_HAL_PIN_38_UART0CTS},
{32, UART_1, AM_HAL_PIN_32_UART1CTS},
{36, UART_1, AM_HAL_PIN_36_UART1CTS},
{45, UART_1, AM_HAL_PIN_45_UART1CTS},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{AP3_PER_IOM0_SCK, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCK},
{AP3_PER_IOM1_SCK, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCK},
{AP3_PER_IOM2_SCK, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCK},
{AP3_PER_IOM4_SCK, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCK},
{AP3_PER_IOM5_SCK, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCK},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_IOM3_SCK, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCK},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{AP3_PER_IOM0_MOSI, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MOSI},
{AP3_PER_IOM1_MOSI, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MOSI},
{AP3_PER_IOM2_MOSI, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MOSI},
{AP3_PER_IOM4_MOSI, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MOSI},
{AP3_PER_IOM5_MOSI, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MOSI},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_IOM3_MOSI, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MOSI},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{AP3_PER_IOM0_MISO, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MISO},
{AP3_PER_IOM1_MISO, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MISO},
{AP3_PER_IOM2_MISO, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MISO},
{AP3_PER_IOM4_MISO, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MISO},
{AP3_PER_IOM5_MISO, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MISO},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_IOM3_MISO, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MISO},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{AP3_PER_NCE_0, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_0},
{AP3_PER_NCE_1, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_1},
{AP3_PER_NCE_2, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_2},
{AP3_PER_NCE_3, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_3},
{AP3_PER_NCE_4, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_4},
{AP3_PER_NCE_7, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_7},
{AP3_PER_NCE_8, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_8},
{AP3_PER_NCE_9, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_9},
{AP3_PER_NCE_10, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_10},
{AP3_PER_NCE_11, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_11},
{AP3_PER_NCE_12, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_12},
{AP3_PER_NCE_13, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_13},
{AP3_PER_NCE_14, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_14},
{AP3_PER_NCE_15, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_15},
{AP3_PER_NCE_16, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_16},
{AP3_PER_NCE_17, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_17},
{AP3_PER_NCE_18, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_18},
{AP3_PER_NCE_19, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_19},
{AP3_PER_NCE_20, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_20},
{AP3_PER_NCE_21, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_21},
{AP3_PER_NCE_22, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_22},
{AP3_PER_NCE_23, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_23},
{AP3_PER_NCE_24, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_24},
{AP3_PER_NCE_25, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_25},
{AP3_PER_NCE_26, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_26},
{AP3_PER_NCE_27, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_27},
{AP3_PER_NCE_28, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_28},
{AP3_PER_NCE_29, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_29},
{AP3_PER_NCE_41, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_41},
{AP3_PER_NCE_44, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_44},
{AP3_PER_NCE_47, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_47},
{AP3_PER_NCE_48, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_48},
{AP3_PER_NCE_49, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_49},
#if defined (AM_PACKAGE_BGA)
{AP3_PER_NCE_30, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_30},
{AP3_PER_NCE_31, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_31},
{AP3_PER_NCE_32, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_32},
{AP3_PER_NCE_33, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_33},
{AP3_PER_NCE_34, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_34},
{AP3_PER_NCE_35, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_35},
{AP3_PER_NCE_36, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_36},
{AP3_PER_NCE_37, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_37},
{AP3_PER_NCE_38, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_38},
{AP3_PER_NCE_42, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_42},
{AP3_PER_NCE_43, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_43},
{AP3_PER_NCE_45, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_45},
{AP3_PER_NCE_46, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_46},
#endif // defined (AM_PACKAGE_BGA)
{NC, NC, 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{NC, NC, 0}
};

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/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
* Copyright (c) 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// SPDX-License-Identifier: Apache-2.0
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
//*** I2C ***
#if DEVICE_I2C
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
#endif
//*** PWM ***
#if DEVICE_PWMOUT
extern const PinMap PinMap_PWM_OUT[];
#endif
//*** SERIAL ***
#if DEVICE_SERIAL
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
extern const PinMap PinMap_UART_RTS[];
extern const PinMap PinMap_UART_CTS[];
#endif
//*** SPI ***
#if DEVICE_SPI
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_SSEL[];
#endif
//*** ADC ***
#if DEVICE_ANALOGIN
extern const PinMap PinMap_ADC[];
#endif
//*** DAC ***
#if DEVICE_ANALOGOUT
extern const PinMap PinMap_DAC[];
#endif
//*** QSPI ***
#if DEVICE_QSPI
extern const PinMap PinMap_QSPI_SCLK[];
extern const PinMap PinMap_QSPI_SSEL[];
extern const PinMap PinMap_QSPI_DATA0[];
extern const PinMap PinMap_QSPI_DATA1[];
extern const PinMap PinMap_QSPI_DATA2[];
extern const PinMap PinMap_QSPI_DATA3[];
#endif
#endif

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "am_mcu_apollo.h"
#include "cmsis_nvic.h"
#endif

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 32 + 16) // CORE + MCU Peripherals + BLE Patch
#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2019, STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
// SPDX-License-Identifier: BSD-3-Clause
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
//=======================================
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#include "extensions.h"
#include "us_ticker_defines.h"
#endif

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _MBED_APOLLO3_EXTENSIONS_H_
#define _MBED_APOLLO3_EXTENSIONS_H_
#include "pinmap.h"
#ifdef __cplusplus
extern "C" {
#endif
void pinmap_config(PinName pin, const PinMap *map);
void pin_config(PinName pin, am_hal_gpio_pincfg_t pincfg);
#ifdef __cplusplus
}
#endif
#endif // _MBED_APOLLO3_EXTENSIONS_H_

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "flash_api.h"
#include <string.h>
int32_t flash_init(flash_t *obj)
{
return 0;
}
int32_t flash_free(flash_t *obj)
{
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
if (!ISADDRFLASH(address)) {
return -1;
}
uint32_t status = am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, AM_HAL_FLASH_ADDR2INST(address), AM_HAL_FLASH_ADDR2PAGE(address));
if (status != AM_HAL_STATUS_SUCCESS) {
return -1;
}
return 0;
}
int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
{
memcpy(data, (void *)address, size);
return 0;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
if (address & 0x03) {
return -1;
}
if (((uint32_t)data) & 0x03) {
return -1;
}
uint32_t words = (size + 3) / 4;
uint32_t status = am_hal_flash_program_main(AM_HAL_FLASH_PROGRAM_KEY, (uint32_t *)data, (uint32_t *)address, words);
if (status != AM_HAL_STATUS_SUCCESS) {
return -1;
}
return 0;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if (address > AM_HAL_FLASH_LARGEST_VALID_ADDR) {
return -1;
}
return AM_HAL_FLASH_PAGE_SIZE;
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return 4;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return AM_HAL_FLASH_ADDR;
}
uint32_t flash_get_size(const flash_t *obj)
{
return AM_HAL_FLASH_TOTAL_SIZE;
}
uint8_t flash_get_erase_value(const flash_t *obj)
{
return 0xFF;
}

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
/** Set the given pin as GPIO
*
* @param pin The pin to be set as GPIO
* @return The GPIO port mask for this pin
**/
uint32_t gpio_set(PinName pin)
{
MBED_ASSERT(pin != (PinName)NC);
return (uint32_t)AM_HAL_GPIO_BIT(pin);
}
/** Checks if gpio object is connected (pin was not initialized with NC)
* @param obj The GPIO object
* @return 0 if object was initialized with NC
* @return non-zero if object was initialized with a valid PinName
**/
int gpio_is_connected(const gpio_t *obj)
{
MBED_ASSERT(obj != NULL);
return (int)(((PinName)obj->pad == (PinName)NC) ? 0 : 1);
}
/** Initialize the GPIO pin
*
* @param obj The GPIO object to initialize
* @param pin The GPIO pin to initialize (may be NC)
*/
void gpio_init(gpio_t *obj, PinName pin)
{
MBED_ASSERT(obj != NULL);
obj->pad = (ap3_uart_pad_t)pin;
return;
}
/** Set the input pin mode
*
* @param obj The GPIO object (must be connected)
* @param mode The pin mode to be set
*/
void gpio_mode(gpio_t *obj, PinMode mode)
{
MBED_ASSERT(gpio_is_connected(obj));
MBED_ASSERT(mode < (PinMode)PinModeElements);
am_hal_gpio_pincfg_allow_t pinConfigBools;
obj->cfg.uFuncSel = AP3_PINCFG_FUNCSEL_GPIO; // gpio
if (mode & (PinMode)PowerSwNone) {
obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_NONE;
pinConfigBools.ePowerSw = true;
}
if (mode & (PinMode)PowerSwVDD) {
obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_VDD;
pinConfigBools.ePowerSw = true;
}
if (mode & (PinMode)PowerSwVSS) {
obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_VSS;
pinConfigBools.ePowerSw = true;
}
if (mode & (PinMode)PullNone) {
obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_NONE;
pinConfigBools.ePullup = true;
}
if (mode & (PinMode)PullUp) {
obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_WEAK;
pinConfigBools.ePullup = true;
}
if (mode & (PinMode)PullDown) {
obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN;
pinConfigBools.ePullup = true;
}
if (mode & (PinMode)DriveStrength2mA) {
obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA;
pinConfigBools.eDriveStrength = true;
}
if (mode & (PinMode)DriveStrength4mA) {
obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA;
pinConfigBools.eDriveStrength = true;
}
if (mode & (PinMode)DriveStrength8mA) {
obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA;
pinConfigBools.eDriveStrength = true;
}
if (mode & (PinMode)DriveStrength12mA) {
obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA;
pinConfigBools.eDriveStrength = true;
}
if (mode & (PinMode)OutDisable) {
obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE;
pinConfigBools.eGPOutcfg = true;
}
if (mode & (PinMode)OutPushPull) {
obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL;
pinConfigBools.eGPOutcfg = true;
}
if (mode & (PinMode)OutOpenDrain) {
obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN;
pinConfigBools.eGPOutcfg = true;
}
if (mode & (PinMode)OutTristate) {
obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_TRISTATE;
pinConfigBools.eGPOutcfg = true;
}
if (mode & (PinMode)InAuto) {
obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_AUTO;
pinConfigBools.eGPInput = true;
}
if (mode & (PinMode)InNone) {
obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE;
pinConfigBools.eGPInput = true;
}
if (mode & (PinMode)InEnable) {
obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE;
pinConfigBools.eGPInput = true;
}
if (mode & (PinMode)ReadPin) {
obj->cfg.eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN;
pinConfigBools.eGPRdZero = true;
}
if (mode & (PinMode)ReadZero) {
obj->cfg.eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_ZERO;
pinConfigBools.eGPRdZero = true;
}
ap3_hal_gpio_pinconfig_partial((uint32_t)(obj->pad), obj->cfg, pinConfigBools); //padRegMsk.byte, GPConfigMsk.byte, padAltCfgMsk.byte); // apply configuration
}
/** Set the pin direction
*
* @param obj The GPIO object (must be connected)
* @param direction The pin direction to be set
*/
void gpio_dir(gpio_t *obj, PinDirection direction)
{
MBED_ASSERT(gpio_is_connected(obj));
MBED_ASSERT(direction < (PinDirection)PIN_DIR_ELEMENTS);
am_hal_gpio_pincfg_allow_t pinConfigBools;
if (direction == (PinDirection)PIN_INPUT) {
obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE;
pinConfigBools.eGPInput = true;
obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE;
pinConfigBools.eGPOutcfg = true;
} else if (direction == (PinDirection)PIN_OUTPUT) {
obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL;
pinConfigBools.eGPOutcfg = true;
obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA;
pinConfigBools.eDriveStrength = true;
obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE;
pinConfigBools.eGPInput = true;
} else {
MBED_ASSERT(false);
}
ap3_hal_gpio_pinconfig_partial((uint32_t)(obj->pad), obj->cfg, pinConfigBools); //padRegMsk.byte, GPConfigMsk.byte, padAltCfgMsk.byte); // apply configuration
}
/** Set the output value
*
* @param obj The GPIO object (must be connected)
* @param value The value to be set
*/
void gpio_write(gpio_t *obj, int value)
{
MBED_ASSERT(gpio_is_connected(obj));
(value) ? am_hal_gpio_output_set(obj->pad) : am_hal_gpio_output_clear(obj->pad);
}
/** Read the input value
*
* @param obj The GPIO object (must be connected)
* @return An integer value 1 or 0
*/
int gpio_read(gpio_t *obj)
{
MBED_ASSERT(gpio_is_connected(obj));
uint32_t ui32BaseAddr = (obj->pad) / 8;
uint32_t ui32BaseShift = (((obj->pad) % 8) * 4) + 1;
uint8_t output = ((AM_REGVAL(&GPIO->CFGA + ui32BaseAddr) >> ui32BaseShift) & 0x03);
return (output) ? (int)am_hal_gpio_output_read(obj->pad) : (int)am_hal_gpio_input_read(obj->pad);
return 0;
}
/** Get the pins that support all GPIO tests
*
* Return a PinMap array of pins that support GPIO. The
* array is terminated with {NC, NC, 0}.
*
* Targets should override the weak implementation of this
* function to provide the actual pinmap for GPIO testing.
*
* @return PinMap array
*/
const PinMap *gpio_pinmap(void)
{
MBED_ASSERT(false);
return NULL;
}

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "gpio_irq_api.h"
#include "objects.h"
#if DEVICE_INTERRUPTIN
#ifdef __cplusplus
extern "C"
{
#endif
uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir);
/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
*/
typedef struct gpio_irq_s gpio_irq_t;
typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
extern void am_gpio_isr(void);
static ap3_gpio_irq_control_t gpio_irq_control[AP3_GPIO_MAX_PADS];
/**
* \defgroup hal_gpioirq GPIO IRQ HAL functions
*
* # Defined behavior
* * ::gpio_irq_init initializes the GPIO IRQ pin
* * ::gpio_irq_init attaches the interrupt handler
* * ::gpio_irq_free releases the GPIO IRQ pin
* * ::gpio_irq_set enables/disables pin IRQ event
* * ::gpio_irq_enable enables GPIO IRQ
* * ::gpio_irq_disable disables GPIO IRQ
*
* # Undefined behavior
* * Calling other function before ::gpio_irq_init
*
* @{
*/
/** Initialize the GPIO IRQ pin
*
* @param obj The GPIO object to initialize
* @param pin The GPIO pin name
* @param handler The handler to be attached to GPIO IRQ
* @param id The object ID (id != 0, 0 is reserved)
* @return -1 if pin is NC, 0 otherwise
*/
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
//grab the correct irq control object
ap3_gpio_irq_control_t *control = &gpio_irq_control[pin];
//Register locally
control->pad = pin;
control->handler = handler;
control->id = id;
control->events = IRQ_NONE;
//Attach to object
obj->control = control;
//Make sure the interrupt is set to none to reflect the new events value
ap3_gpio_enable_interrupts(control->pad, AM_HAL_GPIO_PIN_INTDIR_NONE);
//Enable GPIO IRQ's in the NVIC
gpio_irq_enable(obj);
NVIC_SetVector((IRQn_Type)GPIO_IRQn, (uint32_t)am_gpio_isr);
NVIC_EnableIRQ((IRQn_Type)GPIO_IRQn);
return 0;
}
void am_gpio_isr(void)
{
//call the handler for the interrupt
uint64_t gpio_int_mask = 0x00;
am_hal_gpio_interrupt_status_get(true, &gpio_int_mask);
uint32_t pinNum = 0;
while (gpio_int_mask) {
if (gpio_int_mask & 0x0000000000000001) {
am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(pinNum));
ap3_gpio_irq_control_t irq_ctrl = gpio_irq_control[pinNum];
((gpio_irq_handler)irq_ctrl.handler)(irq_ctrl.id, irq_ctrl.events);
}
gpio_int_mask >>= 1;
pinNum++;
}
}
/** Release the GPIO IRQ PIN
*
* @param obj The gpio object
*/
void gpio_irq_free(gpio_irq_t *obj)
{
}
/** Enable/disable pin IRQ event
*
* @param obj The GPIO object
* @param event The GPIO IRQ event
* @param enable The enable flag
*/
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
//Clear state
obj->control->events &= (~event);
if (enable) {
//Reset if enabled
obj->control->events |= event;
}
// Map enabled events to a value the reflects the ambiq hal/register values
am_hal_gpio_intdir_e ap3_int_dir = 0x00;
switch (obj->control->events) {
case IRQ_NONE:
ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_NONE;
break;
case IRQ_RISE:
ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_LO2HI;
break;
case IRQ_FALL:
ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_HI2LO;
break;
case (IRQ_RISE | IRQ_FALL):
ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_BOTH;
break;
}
ap3_gpio_enable_interrupts(obj->control->pad, ap3_int_dir);
}
/** Enable GPIO IRQ
*
* This is target dependent, as it might enable the entire port or just a pin
* @param obj The GPIO object
*/
void gpio_irq_enable(gpio_irq_t *obj)
{
am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad));
am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(obj->control->pad));
}
/** Disable GPIO IRQ
*
* This is target dependent, as it might disable the entire port or just a pin
* @param obj The GPIO object
*/
void gpio_irq_disable(gpio_irq_t *obj)
{
am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad));
am_hal_gpio_interrupt_disable(AM_HAL_GPIO_BIT(obj->control->pad));
}
/**@}*/
uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir)
{
//GPConfigReg_t GPCfgMask = {.bit.INCFG = 1, .bit.INTD = 1};
// uint32_t ap3_hal_gpio_pinconfig_partial(ui32Pin, bfGpioCfg, 0, uint8_t GPCfgMask, 0);
uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg;
bool bClearEnable = false;
#ifndef AM_HAL_DISABLE_API_VALIDATION
if (ui32Pin >= AM_HAL_GPIO_MAX_PADS) {
return AM_HAL_STATUS_INVALID_ARG;
}
#endif // AM_HAL_DISABLE_API_VALIDATION
//
// Initialize the PADREG accumulator variables.
//
ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0;
//
// Map the requested interrupt direction settings into the Apollo3
// GPIOCFG register field, which is a 4-bit field:
// [INTD(1):OUTCFG(2):INCFG(1)].
// Bit0 of eIntDir maps to GPIOCFG.INTD (b3).
// Bit1 of eIntDir maps to GPIOCFG.INCFG (b0).
//
ui32GPCfg |= (((eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | (((eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S);
//
// At this point, the configuration variable, ui32GpioCfg
// value is set (at bit position 0) and ready to write
// to their respective register bitfields.
//
uint32_t ui32GPCfgAddr;
uint32_t ui32GPCfgClearMask;
uint32_t ui32GPCfgShft;
ui32GPCfgShft = ((ui32Pin & 0x7) << 2);
ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3);
ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft);
//
// Get the new values into their rightful bit positions.
//
ui32GPCfg <<= ui32GPCfgShft;
AM_CRITICAL_BEGIN
if (bClearEnable) {
//
// We're configuring a mode that requires clearing the Enable bit.
//
am_hal_gpio_output_tristate_disable(ui32Pin);
}
GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key;
// Here's where the magic happens
AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg;
GPIO->PADKEY = 0;
AM_CRITICAL_END
return AM_HAL_STATUS_SUCCESS;
} // am_hal_gpio_pinconfig()
#ifdef __cplusplus
}
#endif
/** @}*/
#endif //DEVICE_INTERRUPTIN

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#if DEVICE_I2C
#include "i2c_api.h"
#include "iom_api.h"
#include "PeripheralPins.h"
#include "mbed_assert.h"
#define DEFAULT_CLK_FREQ (AM_HAL_IOM_400KHZ)
static am_hal_iom_transfer_t xfer = {0};
I2CName i2c_get_peripheral_name(PinName sda, PinName scl)
{
uint32_t iom_sda = pinmap_peripheral(sda, i2c_master_sda_pinmap());
uint32_t iom_scl = pinmap_peripheral(scl, i2c_master_scl_pinmap());
uint32_t iom = pinmap_merge(iom_sda, iom_scl);
if ((int)iom == NC) {
return IOM_NUM;
}
return (I2CName)iom;
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
MBED_ASSERT(obj);
// iom determination
I2CName iom = i2c_get_peripheral_name(sda, scl);
MBED_ASSERT((int)iom != IOM_NUM);
// iom configuration
obj->i2c.iom_obj.iom.inst = (uint32_t)iom;
obj->i2c.iom_obj.iom.cfg.eInterfaceMode = AM_HAL_IOM_I2C_MODE;
obj->i2c.iom_obj.iom.cfg.ui32ClockFreq = DEFAULT_CLK_FREQ;
obj->i2c.iom_obj.iom.cfg.pNBTxnBuf = NULL;
obj->i2c.iom_obj.iom.cfg.ui32NBTxnBufLength = 0;
// pin configuration
if ((int)sda != NC) {
pinmap_config(sda, i2c_master_sda_pinmap());
}
if ((int)scl != NC) {
pinmap_config(scl, i2c_master_scl_pinmap());
}
// invariant xfer settings
xfer.ui32InstrLen = 0;
xfer.ui32Instr = 0;
xfer.ui8RepeatCount = 0;
xfer.ui8Priority = 1;
xfer.ui32PauseCondition = 0;
xfer.ui32StatusSetClr = 0;
// initialization
iom_init(&obj->i2c.iom_obj);
}
void i2c_free(i2c_t *obj)
{
MBED_ASSERT(obj);
iom_deinit(&obj->i2c.iom_obj);
}
void i2c_frequency(i2c_t *obj, int hz)
{
MBED_ASSERT(obj);
if (hz > AM_HAL_IOM_MAX_FREQ) {
hz = AM_HAL_IOM_MAX_FREQ;
}
obj->i2c.iom_obj.iom.cfg.ui32ClockFreq = hz;
iom_init(&obj->i2c.iom_obj);
}
int i2c_start(i2c_t *obj)
{
MBED_ASSERT(obj);
MBED_ASSERT(0);
return I2C_ERROR_NO_SLAVE;
}
int i2c_stop(i2c_t *obj)
{
MBED_ASSERT(obj);
MBED_ASSERT(0);
return I2C_ERROR_NO_SLAVE;
}
int i2c_read(i2c_t *obj, int address8bit, char *data, int length, int stop)
{
MBED_ASSERT(obj);
int handled_chars = 0;
xfer.uPeerInfo.ui32I2CDevAddr = (address8bit >> 1);
xfer.eDirection = AM_HAL_IOM_RX;
xfer.ui32NumBytes = length;
xfer.pui32RxBuffer = (uint32_t *)data;
xfer.pui32TxBuffer = NULL;
xfer.bContinue = (stop) ? false : true;
uint32_t status = am_hal_iom_blocking_transfer(obj->i2c.iom_obj.iom.handle, &xfer);
if (AM_HAL_STATUS_SUCCESS != status) {
return I2C_ERROR_NO_SLAVE;
}
handled_chars += xfer.ui32NumBytes;
return handled_chars;
}
int i2c_write(i2c_t *obj, int address8bit, const char *data, int length, int stop)
{
MBED_ASSERT(obj);
int handled_chars = 0;
xfer.uPeerInfo.ui32I2CDevAddr = (address8bit >> 1);
xfer.eDirection = AM_HAL_IOM_TX;
xfer.ui32NumBytes = length;
xfer.pui32TxBuffer = (uint32_t *)data;
xfer.pui32RxBuffer = NULL;
xfer.bContinue = (stop) ? false : true;
uint32_t status = am_hal_iom_blocking_transfer(obj->i2c.iom_obj.iom.handle, &xfer);
if (AM_HAL_STATUS_SUCCESS != status) {
return I2C_ERROR_NO_SLAVE;
}
handled_chars += xfer.ui32NumBytes;
return handled_chars;
}
void i2c_reset(i2c_t *obj)
{
MBED_ASSERT(obj);
MBED_ASSERT(0);
}
int i2c_byte_read(i2c_t *obj, int last)
{
MBED_ASSERT(obj);
MBED_ASSERT(0);
return I2C_ERROR_NO_SLAVE;
}
int i2c_byte_write(i2c_t *obj, int data)
{
MBED_ASSERT(obj);
MBED_ASSERT(0);
return I2C_ERROR_NO_SLAVE;
}
const PinMap *i2c_master_sda_pinmap(void)
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap(void)
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap(void)
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap(void)
{
return PinMap_I2C_SCL;
}
#endif // DEVICE_I2C

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "iom_api.h"
#include "mbed_assert.h"
void iom_init(iom_t *obj)
{
MBED_ASSERT(obj);
if (obj->iom.handle) {
iom_deinit(obj);
}
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_initialize(obj->iom.inst, &obj->iom.handle));
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_power_ctrl(obj->iom.handle, AM_HAL_SYSCTRL_WAKE, false));
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_configure(obj->iom.handle, &obj->iom.cfg));
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_enable(obj->iom.handle));
// this merely configures the internal peripheral - the desired pins still need to be configured
}
void iom_deinit(iom_t *obj)
{
MBED_ASSERT(obj);
if (!obj->iom.handle) {
return;
}
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_disable(obj->iom.handle));
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_power_ctrl(obj->iom.handle, AM_HAL_SYSCTRL_DEEPSLEEP, false));
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_uninitialize(obj->iom.handle));
obj->iom.handle = NULL;
}

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_IOM_API_H
#define MBED_IOM_API_H
#include "hal/dma_api.h"
#include "hal/buffer.h"
#include "am_mcu_apollo.h"
#include "objects_iom.h"
/** Asynch IOM HAL structure
*/
typedef struct {
struct iom_s iom; /**< Target specific SPI structure */
// struct buffer_s tx_buff; /**< Tx buffer */
// struct buffer_s rx_buff; /**< Rx buffer */
} iom_t;
void iom_init(iom_t *obj);
void iom_deinit(iom_t *obj);
#endif // MBED_IOM_API_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "am_mcu_apollo.h"
#include "lp_ticker_defines.h"
volatile bool someFlagThatGetSetinISR = false;
void am_ctimer_isr(void)
{
uint32_t ui32Status;
//
// Check and clear any active CTIMER interrupts.
//
ui32Status = am_hal_ctimer_int_status_get(true);
am_hal_ctimer_int_clear(ui32Status);
// //
// // Run handlers for the various possible timer events.
// //
am_hal_ctimer_int_service(ui32Status);
//am_hal_ctimer_int_service(am_hal_ctimer_int_status_get(true)); // get enabled interrupt status and then service those only
}

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "lp_ticker_api.h"
#include "lp_ticker_defines.h"
#include "platform/mbed_critical.h"
#if DEVICE_LPTICKER
static bool lp_ticker_initialized = false;
/* LP ticker is driven by 32kHz clock and counter length is 24 bits. */
const ticker_info_t *lp_ticker_get_info()
{
static const ticker_info_t info = {
LP_TICKER_FREQ,
LP_TICKER_BITS
};
return &info;
}
void lp_ticker_init(void)
{
if (lp_ticker_initialized) {
lp_ticker_disable_interrupt();
return;
}
am_hal_ctimer_int_register(LP_TICKER_AM_HAL_CTIMER_CMPR_INT, lp_ticker_irq_handler);
am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER,
LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER,
(LP_TICKER_AM_HAL_CTIMER_TIME_KEEPER_FN | LP_TICKER_AM_HAL_CTIMER_SRC));
am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER,
LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER,
(LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN | LP_TICKER_AM_HAL_CTIMER_SRC | AM_HAL_CTIMER_INT_ENABLE));
am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT);
NVIC_EnableIRQ(CTIMER_IRQn);
am_hal_ctimer_start(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER);
lp_ticker_initialized = true;
}
void lp_ticker_free(void)
{
am_hal_ctimer_stop(LP_TICKER_AM_HAL_CTIMER_NUMBER,
LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER);
am_hal_ctimer_clear(LP_TICKER_AM_HAL_CTIMER_NUMBER,
LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER);
lp_ticker_initialized = false;
}
uint32_t lp_ticker_read()
{
return am_hal_ctimer_read(LP_TICKER_AM_HAL_CTIMER_NUMBER,
LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT);
am_hal_ctimer_clear(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER);
// am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER,
// LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER,
// (LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN | LP_TICKER_AM_HAL_CTIMER_SRC | AM_HAL_CTIMER_INT_ENABLE | CTIMER_CTRL0_TMRA0IE1_Msk));
am_hal_ctimer_start(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER);
uint32_t delta = (uint32_t)timestamp - lp_ticker_read();
am_hal_ctimer_compare_set(LP_TICKER_AM_HAL_CTIMER_NUMBER,
LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER,
LP_TICKER_AM_HAL_CTIMER_CMPR_REG,
(uint32_t)delta);
}
void lp_ticker_fire_interrupt(void)
{
am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT);
am_hal_ctimer_int_set(LP_TICKER_AM_HAL_CTIMER_CMPR_INT);
}
void lp_ticker_disable_interrupt(void)
{
am_hal_ctimer_int_disable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT);
}
void lp_ticker_clear_interrupt(void)
{
am_hal_ctimer_int_clear(LP_TICKER_AM_HAL_CTIMER_CMPR_INT);
}
#endif // DEVICE_LPTICKER

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
// #ifndef MBED_US_TICKER_DEFINES_H
// #define MBED_US_TICKER_DEFINES_H
#include "am_mcu_apollo.h"
#define LP_TICKER_FREQ 32768
#define LP_TICKER_AM_HAL_CTIMER_SRC AM_HAL_CTIMER_XT_32_768KHZ
#define LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER AM_HAL_CTIMER_TIMERA
#define LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER AM_HAL_CTIMER_TIMERB
#define LP_TICKER_AM_HAL_CTIMER_NUMBER 7
#define LP_TICKER_AM_HAL_CTIMER_TIME_KEEPER_FN AM_HAL_CTIMER_FN_CONTINUOUS
#define LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN AM_HAL_CTIMER_FN_ONCE
#define LP_TICKER_AM_HAL_CTIMER_CMPR_REG 0 // CMPR0 reg used with CTIMER_FN_CONTINUOUS mode
#define LP_TICKER_AM_HAL_CTIMER_CMPR_INT AM_HAL_CTIMER_INT_TIMERB7C0
//#define LP_TICKER_AM_HAL_CTIMER_CMPR_INT1 AM_HAL_CTIMER_INT_TIMERA7C1
// Automatic configuration
#if (LP_TICKER_AM_HAL_CTIMER_SEGMENT == AM_HAL_CTIMER_BOTH)
#define LP_TICKER_BITS 32
#else
#define LP_TICKER_BITS 16
#endif // (LP_TICKER_AM_HAL_CTIMER_SEGMENT == AM_HAL_CTIMER_BOTH)
// #endif // MBED_US_TICKER_DEFINES_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_MBED_RTX_H
#define MBED_MBED_RTX_H
/* This file is required, but doesn't actually need to do anything. */
#define INITIAL_SP MBED_RAM1_START + MBED_RAM1_SIZE - 8
#endif /* MBED_MBED_RTX_H */

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// SPDX-License-Identifier: Apache-2.0
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "am_mcu_apollo.h"
#include "am_bsp.h"
#include "am_util.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "objects_flash.h"
#include "objects_gpio.h"
#include "objects_uart.h"
#include "objects_iom.h"
#include "objects_spi.h"
#include "objects_i2c.h"
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_OBJECTS_FLASH_H
#define MBED_OBJECTS_FLASH_H
#ifdef __cplusplus
extern "C"
{
#endif
struct flash_u {
uint32_t reserved; //No information needs to be passed to api right now
};
struct flash_s {
struct flash_u flash;
};
#ifdef __cplusplus
}
#endif
#endif // MBED_OBJECTS_FLASH_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_OBJECTS_GPIO_H
#define MBED_OBJECTS_GPIO_H
#include "am_hal_gpio.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C"
{
#endif
typedef uint32_t ap3_gpio_pad_t;
typedef enum {
PIN_INPUT = 0x00,
PIN_OUTPUT,
PIN_DIR_ELEMENTS
} PinDirection;
enum sPinMode {
sPowerSwNone = 0x00,
sPowerSwVDD,
sPowerSwVSS,
sPullNone,
sPullUp,
sPullDown,
sPullUp1K5,
sPullUp6K,
sPullUp12K,
sPullUp24K,
sDriveStrength2mA,
sDriveStrength4mA,
sDriveStrength8mA,
sDriveStrength12mA,
sOutDisable,
sOutPushPull,
sOutOpenDrain,
sOutTristate,
sInAuto,
sInNone,
sInEnable,
sReadPin,
sReadZero,
sPinModeElements
};
#define PinModeEntry(e) e = (1 << s##e)
typedef enum {
PinModeEntry(PowerSwNone),
PinModeEntry(PowerSwVDD),
PinModeEntry(PowerSwVSS),
PowerSwDefault = PowerSwNone,
PinModeEntry(PullNone),
PinModeEntry(PullUp),
PinModeEntry(PullDown),
PinModeEntry(PullUp1K5),
PinModeEntry(PullUp6K),
PinModeEntry(PullUp12K),
PinModeEntry(PullUp24K),
PullDefault = PullNone,
PinModeEntry(DriveStrength2mA),
PinModeEntry(DriveStrength4mA),
PinModeEntry(DriveStrength8mA),
PinModeEntry(DriveStrength12mA),
DriveStrengthDefault = DriveStrength12mA,
PinModeEntry(OutDisable),
PinModeEntry(OutPushPull),
PinModeEntry(OutOpenDrain),
PinModeEntry(OutTristate),
OutDefault = OutPushPull,
PinModeEntry(InAuto),
PinModeEntry(InNone),
PinModeEntry(InEnable),
InDefault = InEnable,
PinModeEntry(ReadPin),
PinModeEntry(ReadZero),
ReadDefault = ReadPin,
PinModeEntry(PinModeElements)
} PinMode;
typedef struct _gpio_t {
ap3_gpio_pad_t pad;
am_hal_gpio_pincfg_t cfg;
} gpio_t;
typedef struct ap3_gpio_irq_control_t {
ap3_gpio_pad_t pad;
uint32_t id;
void *handler;
uint8_t events;
} ap3_gpio_irq_control_t;
typedef struct gpio_irq_s {
ap3_gpio_irq_control_t *control;
} gpio_irq_s;
#define AP3_PINCFG_FUNCSEL_GPIO 3
#define AP3_GPIO_MAX_PADS (50)
#define PADREG_FLD_76_S 6
#define PADREG_FLD_FNSEL_S 3
#define PADREG_FLD_DRVSTR_S 2
#define PADREG_FLD_INPEN_S 1
#define PADREG_FLD_PULLUP_S 0
#define GPIOCFG_FLD_INTD_S 3
#define GPIOCFG_FLD_OUTCFG_S 1
#define GPIOCFG_FLD_INCFG_S 0
#ifdef __cplusplus
}
#endif
#endif // MBED_OBJECTS_GPIO_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_OBJECTS_I2C_H
#define MBED_OBJECTS_I2C_H
#include "objects_iom.h"
#if DEVICE_I2C_ASYNCH
struct i2c_s {
iom_t iom_obj;
};
#else
struct i2c_u {
iom_t iom_obj;
};
struct i2c_s {
struct i2c_u i2c;
};
#endif // DEVICE_I2C_ASYNCH
#endif // MBED_OBJECTS_I2C_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_OBJECTS_IOM_H
#define MBED_OBJECTS_IOM_H
#include "am_hal_iom.h"
#ifdef __cplusplus
extern "C"
{
#endif
struct iom_s {
uint32_t inst; // IOM module instance
void *handle; // IOM handle
am_hal_iom_config_t cfg; // IOM configuration
};
#ifdef __cplusplus
}
#endif
#endif // MBED_OBJECTS_IOM_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_OBJECTS_SPI_H
#define MBED_OBJECTS_SPI_H
#include "iom_api.h"
#if DEVICE_SPI_ASYNCH
struct spi_s {
iom_t iom_obj;
};
#else
struct spi_u {
iom_t iom_obj;
};
struct spi_s {
struct spi_u spi;
};
#endif // DEVICE_SPI_ASYNCH
#endif // MBED_OBJECTS_SPI_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_OBJECTS_UART_H
#define MBED_OBJECTS_UART_H
#ifdef __cplusplus
extern "C"
{
#endif
typedef uint32_t ap3_uart_pad_t;
typedef uint32_t ap3_uart_inst_t;
typedef struct _ap3_uart_pad_map_elem_t {
ap3_uart_pad_t pad;
uint8_t funcsel;
} ap3_uart_pad_map_elem_t;
typedef struct _ap3_uart_control_t {
ap3_uart_inst_t inst; // UART module instance
void *handle; // UART handle
am_hal_uart_config_t cfg; // UART configuration
uint32_t serial_irq_id;
} ap3_uart_control_t;
#if DEVICE_SERIAL_ASYNCH
struct serial_s {
ap3_uart_control_t *uart_control;
};
#else
struct serial_u {
ap3_uart_control_t *uart_control;
};
struct serial_s {
struct serial_u serial;
};
#endif // DEVICE_SERIAL_ASYNCH
#ifdef __cplusplus
}
#endif
#endif // MBED_OBJECTS_UART_H

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "extensions.h"
#include "am_mcu_apollo.h"
void pin_config(PinName pin, am_hal_gpio_pincfg_t pincfg)
{
if (pin == (PinName)NC) {
return;
}
MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_gpio_pinconfig(pin, pincfg));
}
void pinmap_config(PinName pin, const PinMap *map)
{
// fully configure a pin by a pin map entry
if (pin == NC) {
return;
}
am_hal_gpio_pincfg_t pincfg;
while (map->pin != NC) {
if (map->pin == pin) {
pincfg = *((am_hal_gpio_pincfg_t *)(map->function));
pin_config(pin, pincfg);
return;
}
map++;
}
MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "could not pinmap_config", pin);
}
void pin_function(PinName pin, int function)
{
// am_hal_gpio_pincfg_t cfg = {0};
// cfg.uFuncSel = function;
// am_hal_gpio_pinconfig((uint32_t)(pin), cfg); // apply configuration
#define PADREG_FLD_FNSEL_S 3
uint32_t ui32Padreg;
uint32_t ui32Funcsel;
MBED_ASSERT(pin < AM_HAL_GPIO_MAX_PADS);
//
// Initialize the PADREG accumulator variables.
//
ui32Padreg = 0;
// Get the requested function
ui32Funcsel = (uint32_t)function;
ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S;
//
// At this point, the configuration variable ui32Padreg,
// values is set (at bit position 0) and ready to write
// to its respective register bitfields.
//
uint32_t ui32PadregAddr;
uint32_t ui32PadClearMask;
uint32_t ui32PadShft;
ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (pin & ~0x3);
ui32PadShft = ((pin & 0x3) << 3);
ui32PadClearMask = ~((uint32_t)0x38 << ui32PadShft);
// Get the new values into their rightful bit positions.
ui32Padreg <<= ui32PadShft;
AM_CRITICAL_BEGIN
GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key;
AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg;
GPIO->PADKEY = 0;
AM_CRITICAL_END
}
void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(0);
// gpio_t obj = {
// .pad = (ap3_gpio_pad_t)pin,
// .cfg = {0},
// };
// gpio_mode(gpio_t * obj, PinMode mode)
}

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#if DEVICE_SERIAL
#include "serial_api.h"
#include "mbed_assert.h"
#include "PeripheralPins.h"
// globals
int stdio_uart_inited = 0;
serial_t stdio_uart;
bool value = false;
// interrupt variables
static uart_irq_handler irq_handler;
static ap3_uart_control_t ap3_uart_control[AM_REG_UART_NUM_MODULES];
// forward declarations
extern void am_uart_isr(void);
extern void am_uart1_isr(void);
void uart_configure_pin_function(PinName pin, UARTName uart, const PinMap *map);
/**
* \defgroup hal_GeneralSerial Serial Configuration Functions
*
* # Defined behavior
* * ::serial_init initializes the ::serial_t
* * ::serial_init sets the default parameters for serial peripheral (9600 bps, 8N1 format)
* * ::serial_init configures the specified pins
* * ::serial_free releases the serial peripheral
* * ::serial_baud configures the baud rate
* * at least 9600 bps the baud rate must be supported
* * ::serial_format configures the transmission format (number of bits, parity and the number of stop bits)
* * at least 8N1 format must be supported
* * ::serial_irq_handler registers the interrupt handler which will be invoked when the interrupt fires.
* * ::serial_irq_set enables or disables the serial RX or TX IRQ.
* * If `RxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever
* Receive Data Register Full IRQ is generated.
* * If `TxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever
* Transmit Data Register Empty IRQ is generated.
* * If the interrupt condition holds true, when the interrupt is enabled with ::serial_irq_set,
* the ::serial_irq_handler is called instantly.
* * ::serial_getc returns the character from serial buffer.
* * ::serial_getc is a blocking call (waits for the character).
* * ::serial_putc sends a character.
* * ::serial_putc is a blocking call (waits for a peripheral to be available).
* * ::serial_readable returns non-zero value if a character can be read, 0 otherwise.
* * ::serial_writable returns non-zero value if a character can be written, 0 otherwise.
* * ::serial_clear clears the ::serial_t RX/TX buffers
* * ::serial_break_set sets the break signal.
* * ::serial_break_clear clears the break signal.
* * ::serial_pinout_tx configures the TX pin as an output (to be used in half-duplex mode).
* * ::serial_set_flow_control configures serial flow control.
* * ::serial_set_flow_control sets flow control in the hardware if a serial peripheral supports it,
* otherwise software emulation is used.
* * ::serial_tx_asynch starts the serial asynchronous transfer.
* * ::serial_tx_asynch writes `tx_length` bytes from the `tx` to the bus.
* * ::serial_tx_asynch must support 8 data bits
* * The callback given to ::serial_tx_asynch is invoked when the transfer completes.
* * ::serial_tx_asynch specifies the logical OR of events to be registered.
* * The ::serial_tx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm.
* * ::serial_rx_asynch starts the serial asynchronous transfer.
* * ::serial_rx_asynch reads `rx_length` bytes to the `rx` buffer.
* * ::serial_rx_asynch must support 8 data bits
* * The callback given to ::serial_rx_asynch is invoked when the transfer completes.
* * ::serial_rx_asynch specifies the logical OR of events to be registered.
* * The ::serial_rx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm.
* * ::serial_rx_asynch specifies a character in range 0-254 to be matched, 255 is a reserved value.
* * If SERIAL_EVENT_RX_CHARACTER_MATCH event is not registered, the `char_match` is ignored.
* * The SERIAL_EVENT_RX_CHARACTER_MATCH event is set in the callback when SERIAL_EVENT_RX_CHARACTER_MATCH event is
* registered AND `char_match` is present in the received data.
* * ::serial_tx_active returns non-zero if the TX transaction is ongoing, 0 otherwise.
* * ::serial_rx_active returns non-zero if the RX transaction is ongoing, 0 otherwise.
* * ::serial_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise returns 0.
* * ::serial_irq_handler_asynch takes no longer than one packet transfer time (packet_bits / baudrate) to execute.
* * ::serial_tx_abort_asynch aborts the ongoing TX transaction.
* * ::serial_tx_abort_asynch disables the enabled interupt for TX.
* * ::serial_tx_abort_asynch flushes the TX hardware buffer if TX FIFO is used.
* * ::serial_rx_abort_asynch aborts the ongoing RX transaction.
* * ::serial_rx_abort_asynch disables the enabled interupt for RX.
* * ::serial_rx_abort_asynch flushes the TX hardware buffer if RX FIFO is used.
* * Correct operation guaranteed when interrupt latency is shorter than one packet transfer time (packet_bits / baudrate)
* if the flow control is not used.
* * Correct operation guaranteed regardless of interrupt latency if the flow control is used.
*
* # Undefined behavior
* * Calling ::serial_init multiple times on the same `serial_t` without ::serial_free.
* * Passing invalid pin to ::serial_init, ::serial_pinout_tx.
* * Calling any function other than ::serial_init on am uninitialized or freed `serial_t`.
* * Passing an invalid pointer as `obj` to any function.
* * Passing an invalid pointer as `handler` to ::serial_irq_handler, ::serial_tx_asynch, ::serial_rx_asynch.
* * Calling ::serial_tx_abort while no async TX transfer is being processed.
* * Calling ::serial_rx_abort while no async RX transfer is being processed.
* * Devices behavior is undefined when the interrupt latency is longer than one packet transfer time
* (packet_bits / baudrate) if the flow control is not used.
* @{
*/
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, serial_tx_pinmap());
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, serial_rx_pinmap());
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
obj->serial.uart_control = &ap3_uart_control[uart];
obj->serial.uart_control->inst = uart;
// config uart pins
pinmap_config(tx, serial_tx_pinmap());
pinmap_config(rx, serial_rx_pinmap());
if (!obj->serial.uart_control->handle) {
// if handle uninitialized this is first time set up
// ensure that HAL queueing is disabled (we want to use the FIFOs directly)
obj->serial.uart_control->cfg.pui8RxBuffer = NULL;
obj->serial.uart_control->cfg.pui8TxBuffer = NULL;
obj->serial.uart_control->cfg.ui32RxBufferSize = 0;
obj->serial.uart_control->cfg.ui32TxBufferSize = 0;
obj->serial.uart_control->cfg.ui32FifoLevels = AM_HAL_UART_RX_FIFO_7_8;
// start UART instance
MBED_ASSERT(am_hal_uart_initialize(uart, &(obj->serial.uart_control->handle)) == AM_HAL_STATUS_SUCCESS);
MBED_ASSERT(am_hal_uart_power_control(obj->serial.uart_control->handle, AM_HAL_SYSCTRL_WAKE, false) == AM_HAL_STATUS_SUCCESS);
MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS);
// set default format
serial_format(obj, 8, ParityNone, 1);
}
}
void serial_free(serial_t *obj)
{
// nothing to do unless resources are allocated for members of the serial_s serial member of obj
// assuming mbed handles obj and its members
}
void serial_baud(serial_t *obj, int baudrate)
{
obj->serial.uart_control->cfg.ui32BaudRate = (uint32_t)baudrate;
MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
uint32_t am_hal_data_bits = 0;
switch (data_bits) {
case 5:
am_hal_data_bits = AM_HAL_UART_DATA_BITS_5;
break;
case 6:
am_hal_data_bits = AM_HAL_UART_DATA_BITS_6;
break;
case 7:
am_hal_data_bits = AM_HAL_UART_DATA_BITS_7;
break;
case 8:
am_hal_data_bits = AM_HAL_UART_DATA_BITS_8;
break;
default:
MBED_ASSERT(0);
break;
}
uint32_t am_hal_parity = AM_HAL_UART_PARITY_NONE;
switch (parity) {
case ParityNone:
am_hal_parity = AM_HAL_UART_PARITY_NONE;
break;
case ParityOdd:
am_hal_parity = AM_HAL_UART_PARITY_ODD;
break;
case ParityEven:
am_hal_parity = AM_HAL_UART_PARITY_EVEN;
break;
default: // fall-through intentional after default
case ParityForced1:
case ParityForced0:
MBED_ASSERT(0);
break;
}
uint32_t am_hal_stop_bits = 0;
switch (stop_bits) {
case 1:
am_hal_stop_bits = AM_HAL_UART_ONE_STOP_BIT;
break;
case 2:
am_hal_stop_bits = AM_HAL_UART_TWO_STOP_BITS;
break;
default:
MBED_ASSERT(0);
}
obj->serial.uart_control->cfg.ui32DataBits = (uint32_t)am_hal_data_bits;
obj->serial.uart_control->cfg.ui32Parity = (uint32_t)am_hal_parity;
obj->serial.uart_control->cfg.ui32StopBits = (uint32_t)am_hal_stop_bits;
MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
obj->serial.uart_control->serial_irq_id = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
MBED_ASSERT(obj->serial.uart_control->handle != NULL);
if (enable) {
switch (irq) {
case RxIrq:
MBED_ASSERT(am_hal_uart_interrupt_enable(obj->serial.uart_control->handle, AM_HAL_UART_INT_RX) == AM_HAL_STATUS_SUCCESS);
break;
case TxIrq:
MBED_ASSERT(am_hal_uart_interrupt_enable(obj->serial.uart_control->handle, AM_HAL_UART_INT_TXCMP) == AM_HAL_STATUS_SUCCESS);
break;
default:
break;
}
// NVIC_SetVector(uart_irqs[obj->serial.index], vector);
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + obj->serial.uart_control->inst));
} else { // disable
switch (irq) {
case RxIrq:
MBED_ASSERT(am_hal_uart_interrupt_disable(obj->serial.uart_control->handle, AM_HAL_UART_INT_RX) == AM_HAL_STATUS_SUCCESS);
break;
case TxIrq:
MBED_ASSERT(am_hal_uart_interrupt_disable(obj->serial.uart_control->handle, AM_HAL_UART_INT_TXCMP) == AM_HAL_STATUS_SUCCESS);
break;
default:
break;
}
}
}
int serial_getc(serial_t *obj)
{
MBED_ASSERT(obj->serial.uart_control != NULL);
uint8_t rx_c = 0x00;
volatile uint32_t bytes_read = 0x00;
am_hal_uart_transfer_t am_hal_uart_xfer_read_single = {
.ui32Direction = AM_HAL_UART_READ,
.pui8Data = (uint8_t *) &rx_c,
.ui32NumBytes = 1,
.ui32TimeoutMs = 0,
.pui32BytesTransferred = (uint32_t *) &bytes_read,
};
do {
am_hal_uart_transfer(obj->serial.uart_control->handle, &am_hal_uart_xfer_read_single);
} while (bytes_read == 0);
return (int)rx_c;
}
void serial_putc(serial_t *obj, int c)
{
MBED_ASSERT(obj->serial.uart_control != NULL);
volatile uint32_t bytes_sent = 0;
am_hal_uart_transfer_t am_hal_uart_xfer_write_single = {
.ui32Direction = AM_HAL_UART_WRITE,
.pui8Data = (uint8_t *)(&c),
.ui32NumBytes = 1,
.ui32TimeoutMs = 0,
.pui32BytesTransferred = (uint32_t *) &bytes_sent,
};
do {
am_hal_uart_transfer(obj->serial.uart_control->handle, &am_hal_uart_xfer_write_single);
} while (bytes_sent == 0);
}
int serial_readable(serial_t *obj)
{
MBED_ASSERT(obj->serial.uart_control != NULL);
return !(UARTn(obj->serial.uart_control->inst)->FR_b.RXFE);
}
int serial_writable(serial_t *obj)
{
MBED_ASSERT(obj->serial.uart_control != NULL);
return !(UARTn(obj->serial.uart_control->inst)->FR_b.TXFF);
}
void serial_clear(serial_t *obj)
{
// todo:
MBED_ASSERT(0);
}
void serial_break_set(serial_t *obj)
{
MBED_ASSERT(obj->serial.uart_control != NULL);
UARTn(obj->serial.uart_control->inst)->LCRH |= UART0_LCRH_BRK_Msk;
}
void serial_break_clear(serial_t *obj)
{
MBED_ASSERT(obj->serial.uart_control != NULL);
UARTn(obj->serial.uart_control->inst)->LCRH &= ~UART0_LCRH_BRK_Msk;
}
void serial_pinout_tx(PinName tx)
{
// todo: vestigial?
MBED_ASSERT(0);
}
#if DEVICE_SERIAL_FC
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
// todo:
MBED_ASSERT(0);
}
void serial_set_flow_control_direct(serial_t *obj, FlowControl type, const serial_fc_pinmap_t *pinmap)
{
// todo:
MBED_ASSERT(0);
}
#endif
const PinMap *serial_tx_pinmap(void)
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap(void)
{
return PinMap_UART_RX;
}
#if DEVICE_SERIAL_FC
const PinMap *serial_cts_pinmap(void)
{
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap(void)
{
return PinMap_UART_RTS;
}
#endif
static inline void uart_irq(uint32_t instance)
{
void *handle = ap3_uart_control[instance].handle;
MBED_ASSERT(handle != NULL);
// check flags
uint32_t status = 0x00;
MBED_ASSERT(am_hal_uart_interrupt_status_get(handle, &status, true) == AM_HAL_STATUS_SUCCESS);
MBED_ASSERT(am_hal_uart_interrupt_clear(handle, status) == AM_HAL_STATUS_SUCCESS);
if (ap3_uart_control[instance].serial_irq_id != 0) {
if (status & AM_HAL_UART_INT_TXCMP) { // for transmit complete
if (irq_handler) {
irq_handler(ap3_uart_control[instance].serial_irq_id, TxIrq);
}
}
if (status & AM_HAL_UART_INT_RX) { // for receive complete
if (irq_handler) {
irq_handler(ap3_uart_control[instance].serial_irq_id, RxIrq);
}
}
}
}
extern void am_uart_isr(void)
{
uart_irq(UART_0);
}
extern void am_uart1_isr(void)
{
uart_irq(UART_1);
}
#ifdef __cplusplus
}
#endif
#endif
/** @}*/

267
targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c Normal file
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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#if DEVICE_SPI
#include "spi_api.h"
#include "iom_api.h"
#include "PeripheralPins.h"
#include "mbed_assert.h"
#include <string.h>
#define DEFAULT_CLK_FREQ (4000000)
#define DEFAULT_SPI_MODE (AM_HAL_IOM_SPI_MODE_0)
static am_hal_iom_transfer_t xfer = {0};
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
{
uint32_t iom_mosi = pinmap_peripheral(mosi, spi_master_mosi_pinmap());
uint32_t iom_miso = pinmap_peripheral(miso, spi_master_miso_pinmap());
uint32_t iom_sclk = pinmap_peripheral(sclk, spi_master_clk_pinmap());
uint32_t iom;
if (miso == NC) {
iom = pinmap_merge(iom_mosi, iom_sclk);
} else if (mosi == NC) {
iom = pinmap_merge(iom_miso, iom_sclk);
} else {
uint32_t iom_data = pinmap_merge(iom_mosi, iom_miso);
iom = pinmap_merge(iom_data, iom_sclk);
}
if ((int)iom == NC) {
return IOM_NUM;
}
return (SPIName)iom;
}
void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap)
{
MBED_ASSERT(cap);
SPIName iom_ssel = (SPIName)pinmap_peripheral(ssel, spi_master_cs_pinmap());
cap->minimum_frequency = 0;
cap->maximum_frequency = AM_HAL_IOM_MAX_FREQ;
cap->word_length = 0x00000080;
cap->slave_delay_between_symbols_ns = 0;
cap->clk_modes = 0x0F;
cap->support_slave_mode = (iom_ssel == IOM_ANY) ? true : false;
cap->hw_cs_handle = false;
cap->async_mode = false;
cap->tx_rx_buffers_equal_length = false;
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
MBED_ASSERT(obj);
MBED_ASSERT((int)ssel == NC);
// iom determination
SPIName iom = spi_get_peripheral_name(mosi, miso, sclk);
MBED_ASSERT((int)iom != IOM_NUM);
MBED_ASSERT((int)iom != IOM_ANY);
// iom configuration
obj->spi.iom_obj.iom.inst = (uint32_t)iom;
obj->spi.iom_obj.iom.cfg.eInterfaceMode = AM_HAL_IOM_SPI_MODE;
obj->spi.iom_obj.iom.cfg.ui32ClockFreq = DEFAULT_CLK_FREQ;
obj->spi.iom_obj.iom.cfg.eSpiMode = DEFAULT_SPI_MODE;
obj->spi.iom_obj.iom.cfg.pNBTxnBuf = NULL;
obj->spi.iom_obj.iom.cfg.ui32NBTxnBufLength = 0;
// invariant xfer settings
xfer.ui32InstrLen = 0;
xfer.ui32Instr = 0;
xfer.bContinue = false;
xfer.ui8RepeatCount = 0;
xfer.ui8Priority = 1;
xfer.ui32PauseCondition = 0;
xfer.ui32StatusSetClr = 0;
// pin configuration
pinmap_config(sclk, spi_master_clk_pinmap());
if ((int)mosi != NC) {
pinmap_config(mosi, spi_master_mosi_pinmap());
}
if ((int)miso != NC) {
pinmap_config(miso, spi_master_miso_pinmap());
}
if ((int)ssel != NC) {
pinmap_config(ssel, spi_master_cs_pinmap());
}
// initialization
iom_init(&obj->spi.iom_obj);
}
void spi_free(spi_t *obj)
{
iom_deinit(&obj->spi.iom_obj);
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
MBED_ASSERT(obj);
obj->spi.iom_obj.iom.cfg.eSpiMode = (am_hal_iom_spi_mode_e)mode;
iom_init(&obj->spi.iom_obj);
}
void spi_frequency(spi_t *obj, int hz)
{
MBED_ASSERT(obj);
obj->spi.iom_obj.iom.cfg.ui32ClockFreq = (uint32_t)hz;
iom_init(&obj->spi.iom_obj);
}
int spi_master_write(spi_t *obj, int value)
{
uint32_t rxval = 0;
spi_master_block_write(obj, (const char *)&value, 1, (char *)&rxval, 1, 0x00);
return rxval;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
{
MBED_ASSERT(obj);
int chars_handled = 0;
// perform a duplex xfer for the smaller of the two buffers
xfer.eDirection = AM_HAL_IOM_FULLDUPLEX;
xfer.ui32NumBytes = (tx_length > rx_length) ? rx_length : tx_length;
xfer.pui32RxBuffer = (uint32_t *)rx_buffer;
xfer.pui32TxBuffer = (uint32_t *)tx_buffer;
if (xfer.ui32NumBytes) {
uint32_t status = am_hal_iom_spi_blocking_fullduplex(obj->spi.iom_obj.iom.handle, &xfer);
if (AM_HAL_STATUS_SUCCESS != status) {
return 0;
}
chars_handled += xfer.ui32NumBytes;
}
// handle difference between buffers
if (tx_length != rx_length) {
bool Rw = (rx_length >= tx_length);
// set up common config
xfer.eDirection = (Rw) ? AM_HAL_IOM_RX : AM_HAL_IOM_TX;
xfer.ui32NumBytes = (Rw) ? (rx_length - tx_length) : (tx_length - rx_length);
xfer.pui32RxBuffer = (Rw) ? (uint32_t *)(rx_buffer + chars_handled) : NULL;
xfer.pui32TxBuffer = (Rw) ? NULL : (uint32_t *)(tx_buffer + chars_handled);
uint32_t status = AM_HAL_STATUS_SUCCESS;
if (!Rw || (write_fill == 0x00)) {
// when transmitting (w) or reading with a zero fill just use a simplex transfer
status = am_hal_iom_blocking_transfer(obj->spi.iom_obj.iom.handle, &xfer);
if (AM_HAL_STATUS_SUCCESS != status) {
return chars_handled;
}
chars_handled += xfer.ui32NumBytes;
} else {
// when reading with a nonzero fill use a duplex transfer
uint8_t fill[xfer.ui32NumBytes];
memset(fill, write_fill, xfer.ui32NumBytes);
xfer.eDirection = AM_HAL_IOM_FULLDUPLEX;
xfer.pui32TxBuffer = (uint32_t *)&fill;
uint32_t status = am_hal_iom_spi_blocking_fullduplex(obj->spi.iom_obj.iom.handle, &xfer);
if (AM_HAL_STATUS_SUCCESS != status) {
return chars_handled;
}
chars_handled += xfer.ui32NumBytes;
}
}
return chars_handled;
}
int spi_slave_receive(spi_t *obj)
{
MBED_ASSERT(0);
return 0;
}
int spi_slave_read(spi_t *obj)
{
MBED_ASSERT(0);
return 0;
}
void spi_slave_write(spi_t *obj, int value)
{
MBED_ASSERT(0);
}
int spi_busy(spi_t *obj)
{
MBED_ASSERT(0);
return 0;
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
#endif // DEVICE_SPI

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c Normal file
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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "us_ticker_api.h"
#include <stdio.h>
/**
* \defgroup hal_us_ticker Microsecond Ticker
* Low level interface to the microsecond ticker of a target
*
* # Defined behavior
* * Has a reported frequency between 250KHz and 8MHz for counters which are less than 32 bits wide - Verified by test ::us_ticker_info_test
* * Has a reported frequency up to 100MHz for counters which are 32 bits wide - Verified by test ::us_ticker_info_test
* * Has a counter that is at least 16 bits wide - Verified by test ::us_ticker_info_test
* * All behavior defined by the @ref hal_ticker_shared "ticker specification"
*
* # Undefined behavior
* * See the @ref hal_ticker_shared "ticker specification"
*
* @see hal_us_ticker_tests
*
* # Compile-time optimization macros
*
* @{
*/
/**
* \defgroup hal_us_ticker_tests Microsecond Ticker tests
* Tests to validate the proper implementation of the microsecond ticker
*
* To run the microsecond ticker hal tests use the command:
*
* mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*,tests-mbed_hal-us_ticker*
*
* @see hal_ticker_tests
*
*/
/* HAL us ticker */
static bool us_ticker_initialized = false;
/** Initialize the ticker
*
* Initialize or re-initialize the ticker. This resets all the
* clocking and prescaler registers, along with disabling
* the compare interrupt.
*
* @note Initialization properties tested by ::ticker_init_test
*
*/
void us_ticker_init(void)
{
if (us_ticker_initialized) {
am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE);
return;
}
NVIC_SetVector(STIMER_CMPR0_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(STIMER_CMPR0_IRQn);
am_hal_stimer_config(AM_HAL_STIMER_CFG_CLEAR | AM_HAL_STIMER_CFG_FREEZE);
am_hal_stimer_config(US_TICKER_FREQ);
us_ticker_initialized = true;
}
/** Deinitialize the us ticker
*
* Powerdown the us ticker in preparation for sleep, powerdown, or reset.
*
* After this function is called, no other ticker functions should be called
* except us_ticker_init(), calling any function other than init is undefined.
*
* @note This function stops the ticker from counting.
*
*/
void us_ticker_free(void)
{
am_hal_stimer_config(AM_HAL_STIMER_CFG_FREEZE);
am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE);
us_ticker_initialized = false;
}
/** Read the current counter
*
* Read the current counter value without performing frequency conversions.
* If no rollover has occurred, the seconds passed since us_ticker_init()
* was called can be found by dividing the ticks returned by this function
* by the frequency returned by ::us_ticker_get_info.
*
* @return The current timer's counter value in ticks
*
*/
uint32_t us_ticker_read(void)
{
return am_hal_stimer_counter_get();
}
/** Set interrupt for specified timestamp
*
* @param timestamp The time in ticks to be set
*
* @note no special handling needs to be done for times in the past
* as the common timer code will detect this and call
* us_ticker_fire_interrupt() if this is the case
*
* @note calling this function with timestamp of more than the supported
* number of bits returned by ::us_ticker_get_info results in undefined
* behavior.
*
*/
void us_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t instance = 0;
switch (US_TICKER_STIMER_INT_COMPARE) {
default:
case AM_HAL_STIMER_INT_COMPAREA:
instance = 0;
break;
case AM_HAL_STIMER_INT_COMPAREB:
instance = 1;
break;
case AM_HAL_STIMER_INT_COMPAREC:
instance = 2;
break;
case AM_HAL_STIMER_INT_COMPARED:
instance = 3;
break;
case AM_HAL_STIMER_INT_COMPAREE:
instance = 4;
break;
case AM_HAL_STIMER_INT_COMPAREF:
instance = 5;
break;
case AM_HAL_STIMER_INT_COMPAREG:
instance = 6;
break;
case AM_HAL_STIMER_INT_COMPAREH:
instance = 7;
break;
}
am_hal_stimer_int_enable(US_TICKER_STIMER_INT_COMPARE);
timestamp_t now = (timestamp_t)am_hal_stimer_counter_get();
am_hal_stimer_compare_delta_set(instance, (timestamp - now));
CTIMER->STCFG |= (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << instance);
}
/** Disable us ticker interrupt
*
*/
void us_ticker_disable_interrupt(void)
{
am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE);
}
/** Clear us ticker interrupt
*
*/
void us_ticker_clear_interrupt(void)
{
am_hal_stimer_int_clear(US_TICKER_STIMER_INT_COMPARE);
}
/** Set pending interrupt that should be fired right away.
*
* The ticker should be initialized prior calling this function.
*
*/
void us_ticker_fire_interrupt(void)
{
am_hal_stimer_int_enable(US_TICKER_STIMER_INT_COMPARE);
am_hal_stimer_int_set(US_TICKER_STIMER_INT_COMPARE);
}
/** Get frequency and counter bits of this ticker.*/
const ticker_info_t *us_ticker_get_info(void)
{
static const ticker_info_t info = {
3000000, // 3 MHz
32 // 32 bit counter
};
return &info;
}

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/*
* Copyright (c) 2020 SparkFun Electronics
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef MBED_US_TICKER_DEFINES_H
#define MBED_US_TICKER_DEFINES_H
// * US_TICKER_PERIOD_NUM, US_TICKER_PERIOD_DEN: These denote the ratio (numerator, denominator)
// * of the ticker period to a microsecond. For example, an 8MHz ticker would have NUM = 1, DEN = 8;
// * a 1MHz ticker would have NUM = 1, DEN = 1; a 250kHz ticker would have NUM = 4, DEN = 1.
// * Both numerator and denominator must be 16 bits or less.
#define US_TICKER_FREQ AM_HAL_STIMER_HFRC_3MHZ
#define US_TICKER_PERIOD_NUM 1
#define US_TICKER_PERIOD_DEN 3
// *
// * US_TICKER_MASK: The value mask for the ticker - eg 0x07FFFFFF for a 27-bit ticker.
// *
#define US_TICKER_MASK 0xFFFFFFFF
#define US_TICKER_COMPARE_INSTANCE A
#define US_TICKER_STIMER_INT_COMPARE_CONCATENATOR(a, b) a##b
#define US_TICKER_STIMER_INT_COMPARE_EVALUATOR(a, b) US_TICKER_STIMER_INT_COMPARE_CONCATENATOR(a, b)
#define US_TICKER_STIMER_INT_COMPARE US_TICKER_STIMER_INT_COMPARE_EVALUATOR(AM_HAL_STIMER_INT_COMPARE, US_TICKER_COMPARE_INSTANCE)
#endif

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//*****************************************************************************
//
//! @file system_Apollo3.h
//!
//! @brief Ambiq Micro Apollo3 MCU specific functions.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef SYSTEM_APOLLO3_H
#define SYSTEM_APOLLO3_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
//*****************************************************************************
//
// External function definitions
//
//*****************************************************************************
extern void SystemInit (void);
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif // SYSTEM_APOLLO3_H

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//*****************************************************************************
//
//! @file system_apollo3.c
//!
//! @brief Ambiq Micro Apollo3 MCU specific functions.
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#include <stdint.h>
#include "system_apollo3.h"
#include "apollo3.h"
//*****************************************************************************
//
// Defines
//
//*****************************************************************************
//
// Clocks
//
#define __HSI (6000000UL)
#define __XTAL (32768UL) // Crystal Oscillator frequency
#define __SYS_OSC_CLK (48000000) // Main oscillator frequency
#define __SYSTEM_CLOCK (1*__SYS_OSC_CLK)
//
// Initialize SystemCoreClock with the system core clock frequency value
// achieved after system intitialization.
// This means system core clock frequency after call to SystemInit()
//
uint32_t SystemCoreClock = __SYSTEM_CLOCK; // System Clock Frequency (Core Clock)
//*****************************************************************************
//
//! @brief Set the global clock frequncy.
//!
//! This function sets the global clock frequency.
//!
//! @return None.
//
//*****************************************************************************
void
SystemCoreClockUpdate(void)
{
//
// Calculate the system frequency based upon the current register settings.
// This function can be used to retrieve the system core clock frequeny
// after user changed register sittings.
//
SystemCoreClock = __SYS_OSC_CLK / (CLKGEN->CCTRL_b.CORESEL + 1);
}
//*****************************************************************************
//
//! @brief Initialize the system.
//!
//! This function sets up the microcontroller system.
//!
//! @return None.
//
//*****************************************************************************
void
SystemInit(void)
{
//
// Initialize the system
// Do not use global variables because this function is called before
// reaching pre-main. RW section maybe overwritten afterwards.
//
SystemCoreClock = __SYSTEM_CLOCK;
CLKGEN->CLKKEY = 0x47; // Enable write to CCTRL
CLKGEN->CCTRL_b.CORESEL = 0; // Div by 1 for 48MHz
CLKGEN->CLKKEY = 0; // Disable write to CCTRL
}

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Last updated: August 15, 2019
This file contains origination information about the various
CMSIS header and library files located in this folder.
ARM/Include/:
AmbiqSuite SDK file: Pack Origination:
cmsis*.h CMSIS/5.6.0/CMSIS/Core/Include/
core_cm4.h CMSIS/5.6.0/CMSIS/Core/Include/
mpu_armv7.h CMSIS/5.6.0/CMSIS/Core/Include/
arm_math.h CMSIS/5.6.0/CMSIS/Include/
ARM/Lib/ARM/:
AmbiqSuite SDK file: Pack Origination:
arm_cortexM4lf_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/
arm_cortexM4l_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/
libarm_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/
libarm_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/
iar_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/
iar_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/

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//*****************************************************************************
//
// am_sdk_version.h
//! @file
//!
//! @brief Defines SDK version.
//!
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_SDK_VERSION_H
#define AM_SDK_VERSION_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macros to define HAL SDK version.
//
//*****************************************************************************
//
// Define the current HAL version.
//
#ifndef AM_HAL_VERSION_MAJ
#define AM_HAL_VERSION_MAJ 2
#define AM_HAL_VERSION_MIN 4
#define AM_HAL_VERSION_REV 2
#endif // AM_HAL_VERSION_MAJ
#ifdef __cplusplus
}
#endif
#endif // AM_SDK_VERSION_H

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//*****************************************************************************
//
// am_mcu_apollo.h
//! @file
//!
//! @brief Top Include for Apollo class devices.
//!
//! This file provides all the includes necessary for an apollo device.
//!
//! @addtogroup hal Hardware Abstraction Layer (HAL)
//
//! @defgroup apollo3hal HAL for Apollo3
//! @ingroup hal
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_MCU_APOLLO_H
#define AM_MCU_APOLLO_H
//*****************************************************************************
//
// Define AM_CMSIS_REGS to indicate that CMSIS registers are supported.
//
//*****************************************************************************
#define AM_CMSIS_REGS 1
//*****************************************************************************
//
// C99
//
//*****************************************************************************
#include <stdarg.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#if AM_CMSIS_REGS
#include "apollo3.h"
#else // AM_CMSIS_REGS
#ifdef __IAR_SYSTEMS_ICC__
#include "intrinsics.h" // __CLZ() and other intrinsics
#endif // AM_CMSIS_REGS
#endif
//*****************************************************************************
//
// Global HAL
//
//*****************************************************************************
//
// Define the following macro to disable API parameter validation.
// Defining this macro will result in smaller, more efficient HAL code, but
// will disable parameter checking/validation throughout the HAL.
//
//#define AM_HAL_DISABLE_API_VALIDATION
//
// Define the following macro to disable assert messaging.
// Defining this macro will result in smaller, more efficient HAL code, but
// will eliminate debug messaging.
//
//#define AM_HAL_DEBUG_NO_ASSERT
//*****************************************************************************
//
// Registers
//
//*****************************************************************************
#include "regs/am_reg_base_addresses.h"
#include "regs/am_reg_macros.h"
#include "regs/am_reg.h"
#include "regs/am_reg_m4.h"
#include "regs/am_reg_jedec.h"
//*****************************************************************************
//
// HAL
//
//*****************************************************************************
#include "hal/am_hal_status.h"
#include "hal/am_hal_sysctrl.h"
#include "hal/am_hal_adc.h"
#include "hal/am_hal_ble.h"
#include "hal/am_hal_ble_patch.h"
#include "hal/am_hal_burst.h"
#include "hal/am_hal_cachectrl.h"
#include "hal/am_hal_clkgen.h"
#include "hal/am_hal_cmdq.h"
#include "hal/am_hal_ctimer.h"
#include "hal/am_hal_debug.h"
#include "hal/am_hal_flash.h"
#include "hal/am_hal_global.h"
#include "hal/am_hal_gpio.h"
#include "hal/am_hal_interrupt.h"
#include "hal/am_hal_iom.h"
#include "hal/am_hal_ios.h"
#include "hal/am_hal_itm.h"
#include "hal/am_hal_mcuctrl.h"
#include "hal/am_hal_mspi.h"
#include "hal/am_hal_pdm.h"
#include "hal/am_hal_pin.h"
#include "hal/am_hal_pwrctrl.h"
#include "hal/am_hal_pwrctrl_internal.h"
#include "hal/am_hal_queue.h"
#include "hal/am_hal_reset.h"
#include "hal/am_hal_rtc.h"
#include "hal/am_hal_scard.h"
#include "hal/am_hal_secure_ota.h"
#include "hal/am_hal_stimer.h"
#include "hal/am_hal_security.h"
#include "hal/am_hal_systick.h"
#include "hal/am_hal_tpiu.h"
#include "hal/am_hal_uart.h"
#include "hal/am_hal_wdt.h"
#endif // AM_MCU_APOLLO_H

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//*****************************************************************************
//
// am_hal_adc.h
//! @file
//!
//! @brief Functions for interfacing with the Analog to Digital Converter
//!
//! @addtogroup adc3 Analog-to-Digital Converter (ADC)
//! @ingroup apollo3hal
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Copyright (c) 2020, Ambiq Micro
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// Third party software included in this distribution is subject to the
// additional license terms as defined in the /docs/licenses directory.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.4.2 of the AmbiqSuite Development Package.
//
//*****************************************************************************
// SPDX-License-Identifier: BSD-3-Clause
#ifndef AM_HAL_ADC_H
#define AM_HAL_ADC_H
//*****************************************************************************
//
// CMSIS-style macro for handling a variable IOM module number.
//
#define ADCn(n) ((ADC_Type*)(ADC_BASE + (n * (ADC_BASE - ADC_BASE))))
//*****************************************************************************
//
// Maximum number of slots.
//
#define AM_HAL_ADC_MAX_SLOTS 8
//
// ADC clock selection.
//
typedef enum
{
AM_HAL_ADC_CLKSEL_OFF,
AM_HAL_ADC_CLKSEL_HFRC,
AM_HAL_ADC_CLKSEL_HFRC_DIV2
} am_hal_adc_clksel_e;
//
// ADC trigger polarity
//
typedef enum
{
AM_HAL_ADC_TRIGPOL_RISING,
AM_HAL_ADC_TRIGPOL_FALLING
} am_hal_adc_trigpol_e;
//
// ADC trigger selection
//
typedef enum
{
AM_HAL_ADC_TRIGSEL_EXT0,
AM_HAL_ADC_TRIGSEL_EXT1,
AM_HAL_ADC_TRIGSEL_EXT2,
AM_HAL_ADC_TRIGSEL_EXT3,
AM_HAL_ADC_TRIGSEL_VCOMP,
AM_HAL_ADC_TRIGSEL_SOFTWARE = 7
} am_hal_adc_trigsel_e;
//
// ADC reference selection.
//
typedef enum
{
AM_HAL_ADC_REFSEL_INT_2P0,
AM_HAL_ADC_REFSEL_INT_1P5,
AM_HAL_ADC_REFSEL_EXT_2P0,
AM_HAL_ADC_REFSEL_EXT_1P5
} am_hal_adc_refsel_e;
//
// ADC clock mode selection.
//
typedef enum
{
AM_HAL_ADC_CLKMODE_LOW_POWER, // Disable the clock between scans for LPMODE0.
// Set LPCKMODE to 0x1 while configuring the ADC.
AM_HAL_ADC_CLKMODE_LOW_LATENCY // Low Latency Clock Mode. When set, HFRC and the
// adc_clk will remain on while in functioning in LPMODE0.
} am_hal_adc_clkmode_e;
//
// ADC low-power mode selection.
//
typedef enum
{
AM_HAL_ADC_LPMODE0, // Low Latency Clock Mode. When set, HFRC and the adc_clk
// will remain on while in functioning in LPMODE0.
AM_HAL_ADC_LPMODE1 // Powers down all circuity and clocks associated with the
// ADC until the next trigger event. Between scans, the reference
// buffer requires up to 50us of delay from a scan trigger event
// before the conversion will commence while operating in this mode.
} am_hal_adc_lpmode_e;
//
// ADC repetition selection.
//
typedef enum
{
AM_HAL_ADC_SINGLE_SCAN,
AM_HAL_ADC_REPEATING_SCAN
} am_hal_adc_repeat_e;
//
// ADC measurement averaging configuration.
//
typedef enum
{
AM_HAL_ADC_SLOT_AVG_1,
AM_HAL_ADC_SLOT_AVG_2,
AM_HAL_ADC_SLOT_AVG_4,
AM_HAL_ADC_SLOT_AVG_8,
AM_HAL_ADC_SLOT_AVG_16,
AM_HAL_ADC_SLOT_AVG_32,
AM_HAL_ADC_SLOT_AVG_64,
AM_HAL_ADC_SLOT_AVG_128
} am_hal_adc_meas_avg_e;
//
// ADC slot precision mode.
//
typedef enum
{
AM_HAL_ADC_SLOT_14BIT,
AM_HAL_ADC_SLOT_12BIT,
AM_HAL_ADC_SLOT_10BIT,
AM_HAL_ADC_SLOT_8BIT
} am_hal_adc_slot_prec_e;
//
// ADC slot channel selection.
//
typedef enum
{
// Single-ended channels
AM_HAL_ADC_SLOT_CHSEL_SE0,
AM_HAL_ADC_SLOT_CHSEL_SE1,
AM_HAL_ADC_SLOT_CHSEL_SE2,
AM_HAL_ADC_SLOT_CHSEL_SE3,
AM_HAL_ADC_SLOT_CHSEL_SE4,
AM_HAL_ADC_SLOT_CHSEL_SE5,
AM_HAL_ADC_SLOT_CHSEL_SE6,
AM_HAL_ADC_SLOT_CHSEL_SE7,
AM_HAL_ADC_SLOT_CHSEL_SE8,
AM_HAL_ADC_SLOT_CHSEL_SE9,
// Differential channels.
AM_HAL_ADC_SLOT_CHSEL_DF0,
AM_HAL_ADC_SLOT_CHSEL_DF1,
// Miscellaneous other signals.
AM_HAL_ADC_SLOT_CHSEL_TEMP,
AM_HAL_ADC_SLOT_CHSEL_BATT,
AM_HAL_ADC_SLOT_CHSEL_VSS
} am_hal_adc_slot_chan_e;
//
// DMA priority.
//
typedef enum
{
AM_HAL_ADC_PRIOR_BEST_EFFORT,
AM_HAL_ADC_PRIOR_SERVICE_IMMED
} am_hal_adc_dma_prior_e;
//!
//! ADC control function request types for am_hal_adc_control().
//!
//! AM_HAL_ADC_REQ_TEMP_CELSIUS_GET:
//! pArgs must point to an array of 3 floats. To assure that the
//! array is valid, upon calling the 3rd float (pArgs[2]) must be
//! set to the value -123.456F.
//! AM_HAL_ADC_REQ_TEMP_TRIMS_GET:
//! pArgs must point to an array of 4 floats. To assure that the
//! array is valid, upon calling the 4th float (pArgs[3]) must be
//! set to the to the value -123.456F.
//! On return, pArgs[3] is set to 1 if the returned values are
//! calibrated, or 0 if default calibration values.
//!
typedef enum
{
AM_HAL_ADC_REQ_WINDOW_CONFIG,
AM_HAL_ADC_REQ_TEMP_CELSIUS_GET,
AM_HAL_ADC_REQ_TEMP_TRIMS_GET,
} am_hal_adc_request_e;
//
// ADC Sample structure.
//
typedef struct
{
uint32_t ui32Sample;
uint32_t ui32Slot;
} am_hal_adc_sample_t;
//*****************************************************************************
//
//! @brief Configuration structure for the ADC.
//
//*****************************************************************************
typedef struct
{
//! Select the ADC clock source.
am_hal_adc_clksel_e eClock;
//! Select the ADC trigger polarity.
am_hal_adc_trigpol_e ePolarity;
//! Select the ADC trigger source.
am_hal_adc_trigsel_e eTrigger;
//! Select the ADC reference voltage.
am_hal_adc_refsel_e eReference;
//! Whether to disable clocks between samples.
am_hal_adc_clkmode_e eClockMode;
//! Select the ADC power mode.
am_hal_adc_lpmode_e ePowerMode;
//! Select whether the ADC will re-trigger based on a signal from timer 3.
am_hal_adc_repeat_e eRepeat;
} am_hal_adc_config_t;
//*****************************************************************************
//
//! @brief Configuration structure for the ADC slot.
//
//*****************************************************************************
typedef struct
{
//! Select the number of measurements to average
am_hal_adc_meas_avg_e eMeasToAvg;
//! Select the precision mode
am_hal_adc_slot_prec_e ePrecisionMode;
//! Select the channel
am_hal_adc_slot_chan_e eChannel;
//! Select window comparison mode
bool bWindowCompare;
//! Enable the slot
bool bEnabled;
} am_hal_adc_slot_config_t;
//*****************************************************************************
//
//! @brief Configuration structure for the ADC DMA
//
//*****************************************************************************
typedef struct
{
//! ADC DMA dynamic priority enabled.
bool bDynamicPriority;
//! ADC DMA static priority.
am_hal_adc_dma_prior_e ePriority;
//! Enable DMA for ADC
bool bDMAEnable;
//! Transfer count in samples
uint32_t ui32SampleCount;
//! Target address
uint32_t ui32TargetAddress;
} am_hal_adc_dma_config_t;
//*****************************************************************************
//
//! @brief Window configuration structure for the ADC.
//
//*****************************************************************************
typedef struct
{
//! Scale window comparison
bool bScaleLimits;
//! Window limits
uint32_t ui32Upper;
uint32_t ui32Lower;
} am_hal_adc_window_config_t;
//*****************************************************************************
//
//! @brief Capabilities structure for the ADC.
//
//*****************************************************************************
typedef struct
{
uint32_t dummy;
} am_hal_adc_capabilities_t;
//*****************************************************************************
//
//! @brief Status structure for the ADC.
//
//*****************************************************************************
typedef struct
{
//
// ADC power status.
//
bool bPoweredOn;
bool bLPMode1;
//
// DMA status.
//
bool bErr;
bool bCmp;
bool bTIP;
} am_hal_adc_status_t;
//
// Transfer callback function prototype
//
typedef void (*am_hal_adc_callback_t)(void *pCallbackCtxt, uint32_t status);
//*****************************************************************************
//
//! @name ADC Interrupts
//! @brief Interrupt Status Bits for enable/disble use
//!
//! These macros may be used to enable an individual ADC interrupt cause.
//! @{
//
//*****************************************************************************
#define AM_HAL_ADC_INT_DERR (_VAL2FLD(ADC_INTEN_DERR, 1))
#define AM_HAL_ADC_INT_DCMP (_VAL2FLD(ADC_INTEN_DCMP, 1))
#define AM_HAL_ADC_INT_WCINC (_VAL2FLD(ADC_INTEN_WCINC, 1))
#define AM_HAL_ADC_INT_WCEXC (_VAL2FLD(ADC_INTEN_WCEXC, 1))
#define AM_HAL_ADC_INT_FIFOOVR2 (_VAL2FLD(ADC_INTEN_FIFOOVR2, 1))
#define AM_HAL_ADC_INT_FIFOOVR1 (_VAL2FLD(ADC_INTEN_FIFOOVR1, 1))
#define AM_HAL_ADC_INT_SCNCMP (_VAL2FLD(ADC_INTEN_SCNCMP, 1))
#define AM_HAL_ADC_INT_CNVCMP (_VAL2FLD(ADC_INTEN_CNVCMP, 1))
//! @}
//*****************************************************************************
//
//! @brief ADC Fifo Read macros
//!
//! These are helper macros for interpreting FIFO data. Each ADC FIFO entry
//! contains information about the slot number and the FIFO depth alongside the
//! current sample. These macros perform the correct masking and shifting to
//! read those values.
//!
//! The SAMPLE and FULL_SAMPLE options refer to the fractional part of averaged
//! samples. If you are not using hardware averaging or don't need the
//! fractional part of the ADC sample, you should just use
//! AM_HAL_ADC_FIFO_SAMPLE.
//!
//! If you do need the fractional part, use AM_HAL_ADC_FIFO_FULL_SAMPLE. This
//! macro will keep six bits of precision past the decimal point. Depending on
//! the number of averaged samples, anywhere between 1 and 6 of these bits will
//! be valid. Please consult the datasheet to find out how many bits of data
//! are valid for your chosen averaging settings.
//!
//! @{
//
//*****************************************************************************
#define AM_HAL_ADC_FIFO_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value) >> 6)
#define AM_HAL_ADC_FIFO_FULL_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value))
#define AM_HAL_ADC_FIFO_SLOT(value) (_FLD2VAL(ADC_FIFO_SLOTNUM, value))
#define AM_HAL_ADC_FIFO_COUNT(value) (_FLD2VAL(ADC_FIFO_COUNT, value))
//! @}
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! @brief ADC initialization function
//!
//! @param ui32Module - module instance.
//! @param handle - returns the handle for the module instance.
//!
//! This function accepts a module instance, allocates the interface and then
//! returns a handle to be used by the remaining interface functions.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_initialize(uint32_t ui32Module, void **ppHandle);
//*****************************************************************************
//
//! @brief MSPI deinitialization function
//!
//! @param handle - returns the handle for the module instance.
//!
//! This function accepts a handle to an instance and de-initializes the
//! interface.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_deinitialize(void *pHandle);
//*****************************************************************************
//
//! @brief ADC configuration function
//!
//! @param handle - handle for the module instance.
//! @param pConfig - pointer to the configuration structure.
//!
//! This function configures the ADC for operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_configure(void *pHandle,
am_hal_adc_config_t *psConfig);
//*****************************************************************************
//
//! @brief ADC slot configuration function
//!
//! @param handle - handle for the module instance.
//! @param pConfig - pointer to the configuration structure.
//!
//! This function configures the ADC slot for operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_configure_slot(void *pHandle,
uint32_t ui32SlotNumber,
am_hal_adc_slot_config_t *pSlotConfig);
//*****************************************************************************
//
//! @brief ADC DMA configuration function
//!
//! @param handle - handle for the module instance.
//! @param pConfig - pointer to the configuration structure.
//!
//! This function configures the ADC DMA for operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_configure_dma(void *pHandle,
am_hal_adc_dma_config_t *pDMAConfig);
//*****************************************************************************
//
//! @brief ADC device specific control function.
//!
//! @param handle - handle for the module instance.
//! @eRequest - One of:
//! AM_HAL_ADC_REQ_WINDOW_CONFIG
//! AM_HAL_ADC_REQ_TEMP_CELSIUS_GET (pArgs is required, see enums).
//! AM_HAL_ADC_REQ_TEMP_TRIMS_GET (pArgs is required, see enums).
//!
//! This function provides for special control functions for the ADC operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_control(void *pHandle,
am_hal_adc_request_e eRequest,
void *pArgs);
//*****************************************************************************
//
//! @brief ADC enable function
//!
//! @param handle - handle for the module instance.
//!
//! This function enables the ADC operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_enable(void *pHandle);
//*****************************************************************************
//
//! @brief ADC disable function
//!
//! @param handle - handle for the module instance.
//!
//! This function disables the ADC operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_disable(void *pHandle);
//*****************************************************************************
//
//! @brief ADC status function
//!
//! @param handle - handle for the interface.
//!
//! This function returns the current status of the DMA operation.
//!
//! @return status - DMA status flags.
//
//*****************************************************************************
extern uint32_t am_hal_adc_status_get(void *pHandle,
am_hal_adc_status_t *pStatus );
//*****************************************************************************
//
//! @brief ADC enable interrupts function
//!
//! @param handle - handle for the interface.
//! @param ui32IntMask - ADC interrupt mask.
//!
//! This function enables the specific indicated interrupts.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_interrupt_enable(void *pHandle, uint32_t ui32IntMask);
//*****************************************************************************
//
//! @brief ADC disable interrupts function
//!
//! @param handle - handle for the interface.
//! @param ui32IntMask - ADC interrupt mask.
//!
//! This function disable the specific indicated interrupts.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_interrupt_disable(void *pHandle, uint32_t ui32IntMask);
//*****************************************************************************
//
//! @brief ADC interrupt status function
//!
//! @param handle - handle for the interface.
//!
//! This function returns the specific indicated interrupt status.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_interrupt_status(void *pHandle,
uint32_t *pui32Status,
bool bEnabledOnly);
//*****************************************************************************
//
//! @brief ADC interrupt clear
//!
//! @param handle - handle for the interface.
//! @param ui32IntMask - uint32_t for interrupts to clear
//!
//! This function clears the interrupts for the given peripheral.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_interrupt_clear(void *pHandle, uint32_t ui32IntMask);
//*****************************************************************************
//
//! @brief ADC sample read function
//!
//! @param pHandle - handle for the module instance.
//! @param bFullSample - true to get a full sample including
//! the fractional part.
//! @param pui32InSampleBuffer - Ptr to the input sample buffer.
//! If NULL then samples will be read directly
//! from the FIFO.
//! @param pui32InOutNumberSamples - Ptr to variable containing the number of
//! samples.
//! @param pui32OutSampleBuffer - Ptr to the required output sample buffer.
//!
//! This function reads samples from the ADC FIFO or an SRAM sample buffer
//! returned by a DMA operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_samples_read(void *pHandle, bool bFullSample,
uint32_t *pui32InSampleBuffer,
uint32_t *pui32InOutNumberSamples,
am_hal_adc_sample_t *pui32OutBuffer);
//*****************************************************************************
//
//! @brief ADC FIFO trigger function
//!
//! @param handle - handle for the module instance.
//!
//! This function triggers the ADC operation.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_sw_trigger(void *pHandle);
//*****************************************************************************
//
//! @brief ADC power control function
//!
//! @param handle - handle for the interface.
//! @param ePowerState - the desired power state to move the peripheral to.
//! @param bRetainState - flag (if true) to save/restore peripheral state upon
//! power state change.
//!
//! This function updates the peripheral to a given power state.
//!
//! @return status - generic or interface specific status.
//
//*****************************************************************************
extern uint32_t am_hal_adc_power_control(void *pHandle,
am_hal_sysctrl_power_state_e ePowerState,
bool bRetainState);
#ifdef __cplusplus
}
#endif
#endif // AM_HAL_ADC_H
//*****************************************************************************
//
// End Doxygen group.
//! @}
//
//*****************************************************************************

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targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c Normal file
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