From 68d59d378159ebc6142795f5b593c46d43a09131 Mon Sep 17 00:00:00 2001 From: Wenn0101 Date: Wed, 9 Sep 2020 01:13:05 -0600 Subject: [PATCH] Add new targets, Ambiq Apollo3 and Sparkfun Electronics, SFE, boards --- .../TARGET_Apollo3/AP3CordioHCIDriver.cpp | 96 + .../TARGET_Apollo3/AP3CordioHCIDriver.h | 53 + .../AP3CordioHCITransportDriver.cpp | 142 + .../AP3CordioHCITransportDriver.h | 55 + .../hal/apollo3/hci_drv_apollo3.c | 1330 + .../hal/apollo3/hci_drv_apollo3.h | 104 + .../COMPONENT_hm01b0/hm01b0/HM01B0.c | 949 + .../COMPONENT_hm01b0/hm01b0/HM01B0.h | 501 + .../hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h | 243 + .../hm01b0/HM01B0_Walking1s_01.h | 24 + .../COMPONENT_hm01b0/hm01b0/platform.h | 60 + .../lis2dh12/lis2dh12_platform_apollo3.c | 121 + .../lis2dh12/lis2dh12_platform_apollo3.h | 49 + .../lis2dh12/lis2dh12_reg.c | 2399 ++ .../lis2dh12/lis2dh12_reg.h | 764 + .../TARGET_SFE_ARTEMIS/PinNames.h | 117 + .../TARGET_SFE_ARTEMIS/bsp/am_bsp.c | 1063 + .../TARGET_SFE_ARTEMIS/bsp/am_bsp.h | 254 + .../TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c | 861 + .../TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h | 584 + .../TARGET_SFE_ARTEMIS_ATP/PinNames.h | 138 + .../TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c | 1063 + .../TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h | 255 + .../TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c | 861 + .../TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h | 584 + .../TARGET_SFE_ARTEMIS_DK/PinNames.h | 120 + .../TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c | 1063 + .../TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h | 294 + .../TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c | 1017 + .../TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h | 688 + .../TARGET_SFE_ARTEMIS_MODULE/PinNames.h | 106 + .../TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c | 1026 + .../TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h | 186 + .../bsp/am_bsp_pins.c | 819 + .../bsp/am_bsp_pins.h | 552 + .../TARGET_SFE_ARTEMIS_NANO/PinNames.h | 110 + .../TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c | 1063 + .../TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h | 255 + .../TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c | 861 + .../TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h | 584 + .../TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h | 117 + .../bsp/am_bsp.c | 1063 + .../bsp/am_bsp.h | 267 + .../bsp/am_bsp_pins.c | 874 + .../bsp/am_bsp_pins.h | 592 + .../TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h | 90 + .../TARGET_SFE_EDGE/bsp/am_bsp.c | 1066 + .../TARGET_SFE_EDGE/bsp/am_bsp.h | 290 + .../TARGET_SFE_EDGE/bsp/am_bsp_pins.c | 1073 + .../TARGET_SFE_EDGE/bsp/am_bsp_pins.h | 728 + .../TARGET_SFE_EDGE2/PinNames.h | 96 + .../TARGET_SFE_EDGE2/bsp/am_bsp.c | 1066 + .../TARGET_SFE_EDGE2/bsp/am_bsp.h | 302 + .../TARGET_SFE_EDGE2/bsp/am_bsp_pins.c | 1061 + .../TARGET_SFE_EDGE2/bsp/am_bsp_pins.h | 720 + .../TOOLCHAIN_ARM_STD/AMA3B1KK.sct | 55 + .../TOOLCHAIN_ARM_STD/startup_keil.S | 345 + .../TOOLCHAIN_GCC_ARM/AMA3B1KK.ld | 194 + .../TOOLCHAIN_GCC_ARM/startup_gcc.c | 347 + .../TARGET_Apollo3/device/PeripheralNames.h | 56 + .../device/PeripheralPinConfigs.c | 2219 ++ .../device/PeripheralPinConfigs.h | 1818 ++ .../TARGET_Apollo3/device/PeripheralPins.c | 258 + .../TARGET_Apollo3/device/PeripheralPins.h | 73 + .../TARGET_Apollo3/device/cmsis.h | 30 + .../TARGET_Apollo3/device/cmsis_nvic.h | 30 + .../TARGET_Apollo3/device/device.h | 43 + .../TARGET_Apollo3/device/extensions.h | 40 + .../TARGET_Apollo3/device/flash_api.c | 97 + .../TARGET_Apollo3/device/gpio_api.c | 229 + .../TARGET_Apollo3/device/gpio_irq_api.c | 248 + .../TARGET_Apollo3/device/i2c_api.c | 196 + .../TARGET_Apollo3/device/iom_api.c | 56 + .../TARGET_Apollo3/device/iom_api.h | 45 + .../TARGET_Apollo3/device/isr.c | 43 + .../TARGET_Apollo3/device/lp_ticker.c | 108 + .../TARGET_Apollo3/device/lp_ticker_defines.h | 48 + .../TARGET_Apollo3/device/mbed_rtx.h | 31 + .../TARGET_Apollo3/device/objects.h | 39 + .../TARGET_Apollo3/device/objects_flash.h | 44 + .../TARGET_Apollo3/device/objects_gpio.h | 146 + .../TARGET_Apollo3/device/objects_i2c.h | 42 + .../TARGET_Apollo3/device/objects_iom.h | 44 + .../TARGET_Apollo3/device/objects_spi.h | 42 + .../TARGET_Apollo3/device/objects_uart.h | 64 + .../TARGET_Apollo3/device/pinmap.c | 117 + .../TARGET_Apollo3/device/serial_api.c | 413 + .../TARGET_Apollo3/device/spi_api.c | 267 + .../TARGET_Apollo3/device/us_ticker.c | 203 + .../TARGET_Apollo3/device/us_ticker_defines.h | 45 + .../ARM/Lib/ARM/libarm_cortexM4lf_math.a | Bin 0 -> 5359640 bytes .../sdk/CMSIS/AmbiqMicro/Include/apollo3.h | 23505 ++++++++++++++++ .../CMSIS/AmbiqMicro/Include/system_apollo3.h | 70 + .../CMSIS/AmbiqMicro/Source/system_apollo3.c | 114 + .../sdk/CMSIS/version_cmsis_info.txt | 24 + .../TARGET_Apollo3/sdk/mcu/am_sdk_version.h | 75 + .../sdk/mcu/apollo3/am_mcu_apollo.h | 156 + .../sdk/mcu/apollo3/hal/am_hal_adc.c | 1276 + .../sdk/mcu/apollo3/hal/am_hal_adc.h | 679 + .../sdk/mcu/apollo3/hal/am_hal_ble.c | 3165 +++ .../sdk/mcu/apollo3/hal/am_hal_ble.h | 1004 + .../sdk/mcu/apollo3/hal/am_hal_ble_patch.c | 705 + .../sdk/mcu/apollo3/hal/am_hal_ble_patch.h | 106 + .../sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c | 390 + .../sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h | 106 + .../sdk/mcu/apollo3/hal/am_hal_burst.c | 282 + .../sdk/mcu/apollo3/hal/am_hal_burst.h | 149 + .../sdk/mcu/apollo3/hal/am_hal_cachectrl.c | 460 + .../sdk/mcu/apollo3/hal/am_hal_cachectrl.h | 289 + .../sdk/mcu/apollo3/hal/am_hal_clkgen.c | 410 + .../sdk/mcu/apollo3/hal/am_hal_clkgen.h | 367 + .../sdk/mcu/apollo3/hal/am_hal_cmdq.c | 848 + .../sdk/mcu/apollo3/hal/am_hal_cmdq.h | 293 + .../sdk/mcu/apollo3/hal/am_hal_ctimer.c | 2294 ++ .../sdk/mcu/apollo3/hal/am_hal_ctimer.h | 555 + .../sdk/mcu/apollo3/hal/am_hal_debug.c | 96 + .../sdk/mcu/apollo3/hal/am_hal_debug.h | 141 + .../sdk/mcu/apollo3/hal/am_hal_flash.c | 1883 ++ .../sdk/mcu/apollo3/hal/am_hal_flash.h | 365 + .../sdk/mcu/apollo3/hal/am_hal_global.c | 78 + .../sdk/mcu/apollo3/hal/am_hal_global.h | 167 + .../sdk/mcu/apollo3/hal/am_hal_gpio.c | 1560 + .../sdk/mcu/apollo3/hal/am_hal_gpio.h | 899 + .../sdk/mcu/apollo3/hal/am_hal_interrupt.c | 225 + .../sdk/mcu/apollo3/hal/am_hal_interrupt.h | 84 + .../sdk/mcu/apollo3/hal/am_hal_iom.c | 3752 +++ .../sdk/mcu/apollo3/hal/am_hal_iom.h | 844 + .../sdk/mcu/apollo3/hal/am_hal_ios.c | 1151 + .../sdk/mcu/apollo3/hal/am_hal_ios.h | 378 + .../sdk/mcu/apollo3/hal/am_hal_itm.c | 435 + .../sdk/mcu/apollo3/hal/am_hal_itm.h | 110 + .../sdk/mcu/apollo3/hal/am_hal_mcuctrl.c | 564 + .../sdk/mcu/apollo3/hal/am_hal_mcuctrl.h | 368 + .../sdk/mcu/apollo3/hal/am_hal_mspi.c | 3438 +++ .../sdk/mcu/apollo3/hal/am_hal_mspi.h | 781 + .../sdk/mcu/apollo3/hal/am_hal_pdm.c | 651 + .../sdk/mcu/apollo3/hal/am_hal_pdm.h | 318 + .../sdk/mcu/apollo3/hal/am_hal_pin.h | 495 + .../sdk/mcu/apollo3/hal/am_hal_pwrctrl.c | 638 + .../sdk/mcu/apollo3/hal/am_hal_pwrctrl.h | 261 + .../mcu/apollo3/hal/am_hal_pwrctrl_internal.h | 340 + .../sdk/mcu/apollo3/hal/am_hal_queue.c | 294 + .../sdk/mcu/apollo3/hal/am_hal_queue.h | 165 + .../sdk/mcu/apollo3/hal/am_hal_reset.c | 314 + .../sdk/mcu/apollo3/hal/am_hal_reset.h | 308 + .../sdk/mcu/apollo3/hal/am_hal_rtc.c | 651 + .../sdk/mcu/apollo3/hal/am_hal_rtc.h | 185 + .../sdk/mcu/apollo3/hal/am_hal_scard.c | 1575 ++ .../sdk/mcu/apollo3/hal/am_hal_scard.h | 660 + .../sdk/mcu/apollo3/hal/am_hal_secure_ota.c | 222 + .../sdk/mcu/apollo3/hal/am_hal_secure_ota.h | 228 + .../sdk/mcu/apollo3/hal/am_hal_security.c | 573 + .../sdk/mcu/apollo3/hal/am_hal_security.h | 185 + .../sdk/mcu/apollo3/hal/am_hal_status.h | 89 + .../sdk/mcu/apollo3/hal/am_hal_stimer.c | 642 + .../sdk/mcu/apollo3/hal/am_hal_stimer.h | 218 + .../sdk/mcu/apollo3/hal/am_hal_sysctrl.c | 279 + .../sdk/mcu/apollo3/hal/am_hal_sysctrl.h | 118 + .../sdk/mcu/apollo3/hal/am_hal_systick.c | 351 + .../sdk/mcu/apollo3/hal/am_hal_systick.h | 87 + .../sdk/mcu/apollo3/hal/am_hal_tpiu.c | 394 + .../sdk/mcu/apollo3/hal/am_hal_tpiu.h | 198 + .../sdk/mcu/apollo3/hal/am_hal_uart.c | 1516 + .../sdk/mcu/apollo3/hal/am_hal_uart.h | 724 + .../sdk/mcu/apollo3/hal/am_hal_wdt.c | 417 + .../sdk/mcu/apollo3/hal/am_hal_wdt.h | 188 + .../sdk/mcu/apollo3/regs/am_reg.h | 282 + .../mcu/apollo3/regs/am_reg_base_addresses.h | 99 + .../sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h | 77 + .../sdk/mcu/apollo3/regs/am_reg_jedec.h | 370 + .../sdk/mcu/apollo3/regs/am_reg_m4.h | 93 + .../sdk/mcu/apollo3/regs/am_reg_macros.h | 111 + .../sdk/mcu/apollo3/regs/am_reg_macros_asm.h | 64 + .../sdk/devices/am_devices.h | 82 + .../sdk/devices/am_devices_button.c | 226 + .../sdk/devices/am_devices_button.h | 129 + .../sdk/devices/am_devices_led.c | 556 + .../sdk/devices/am_devices_led.h | 115 + .../TARGET_Ambiq_Micro/sdk/utils/am_util.h | 77 + .../sdk/utils/am_util_ble.c | 632 + .../sdk/utils/am_util_ble.h | 82 + .../sdk/utils/am_util_debug.c | 52 + .../sdk/utils/am_util_debug.h | 115 + .../sdk/utils/am_util_delay.c | 138 + .../sdk/utils/am_util_delay.h | 69 + .../TARGET_Ambiq_Micro/sdk/utils/am_util_id.c | 220 + .../TARGET_Ambiq_Micro/sdk/utils/am_util_id.h | 133 + .../sdk/utils/am_util_regdump.h | 185 + .../sdk/utils/am_util_stdio.c | 1258 + .../sdk/utils/am_util_stdio.h | 88 + .../sdk/utils/am_util_string.c | 614 + .../sdk/utils/am_util_string.h | 162 + .../sdk/utils/am_util_time.c | 146 + .../sdk/utils/am_util_time.h | 67 + targets/targets.json | 65 + 195 files changed, 113126 insertions(+) create mode 100644 connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp create mode 100644 connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h create mode 100644 connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp create mode 100644 connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h create mode 100644 connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c create mode 100644 connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_Walking1s_01.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/platform.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis_nvic.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/device.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/extensions.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/flash_api.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_api.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/i2c_api.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/isr.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker_defines.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/mbed_rtx.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_flash.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_i2c.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_iom.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_spi.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_uart.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/pinmap.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker_defines.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/apollo3.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/system_apollo3.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Source/system_apollo3.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/version_cmsis_info.txt create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/am_sdk_version.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/am_mcu_apollo.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pin.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl_internal.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_status.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.c create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_base_addresses.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_jedec.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_m4.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros.h create mode 100644 targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros_asm.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/devices/am_devices.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_regdump.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.h create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.c create mode 100644 targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.h diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp new file mode 100644 index 0000000000..4e4e50498c --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.cpp @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "AP3CordioHCIDriver.h" +#include "AP3CordioHCITransportDriver.h" +#include "am_mcu_apollo.h" +#include "stdio.h" +#include + +#include "wsf_types.h" +#include "wsf_timer.h" +#include "bstream.h" +#include "wsf_msg.h" +#include "wsf_cs.h" + +#include "hci_drv_apollo3.h" + +using namespace ble; + +AP3CordioHCIDriver::AP3CordioHCIDriver(CordioHCITransportDriver &transport_driver) + : CordioHCIDriver(transport_driver) +{ + AP3CordioHCITransportDriver *p_trspt_drv = (AP3CordioHCITransportDriver *)&transport_driver; + _ptr_to_handle = &p_trspt_drv->handle; +} + +AP3CordioHCIDriver::~AP3CordioHCIDriver() {} + +void AP3CordioHCIDriver::do_initialize() +{ +#ifdef USE_AMBIQ_DRIVER + HciDrvRadioBoot(true); +#else + MBED_ASSERT(*_ptr_to_handle); + _ble_config = am_hal_ble_default_config; + MBED_ASSERT(am_hal_ble_power_control(*_ptr_to_handle, AM_HAL_BLE_POWER_ACTIVE) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_config(*_ptr_to_handle, &_ble_config) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_boot(*_ptr_to_handle) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_tx_power_set(*_ptr_to_handle, 0x0F) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_ble_sleep_set(*_ptr_to_handle, false) == AM_HAL_STATUS_SUCCESS); + am_hal_ble_int_enable(*_ptr_to_handle, (AP3_STUPID_DEF_OF_BLECIRQ_BIT | AM_HAL_BLE_INT_ICMD | AM_HAL_BLE_INT_BLECSSTAT)); + NVIC_EnableIRQ(BLE_IRQn); +#endif +} +void AP3CordioHCIDriver::do_terminate() +{ +#ifdef USE_AMBIQ_DRIVER + HciDrvRadioShutdown(); +#else + am_hal_ble_power_control(*_ptr_to_handle, AM_HAL_BLE_POWER_OFF); +#endif +} + +ble::buf_pool_desc_t AP3CordioHCIDriver::get_buffer_pool_description() +{ + static union { + uint8_t buffer[9000]; + uint64_t align; + }; + static const wsfBufPoolDesc_t pool_desc[] = { + {16, 64}, + {32, 64}, + {64, 32}, + {128, 16}, + {272, 4}}; + return buf_pool_desc_t(buffer, pool_desc); +} + +ble::CordioHCIDriver &ble_cordio_get_hci_driver() +{ + static AP3CordioHCITransportDriver transport_driver; + + static AP3CordioHCIDriver hci_driver(transport_driver); + + return hci_driver; +} diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h new file mode 100644 index 0000000000..86cd236c8a --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCIDriver.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef APOLLO3_CORDIO_HCI_DRIVER_H_ +#define APOLLO3_CORDIO_HCI_DRIVER_H_ + +#include "CordioHCIDriver.h" +#include "am_mcu_apollo.h" + +namespace ble +{ + class AP3CordioHCIDriver : public CordioHCIDriver + { + public: + AP3CordioHCIDriver( + CordioHCITransportDriver &transport_driver + /* specific constructor arguments*/); + + virtual ~AP3CordioHCIDriver(); + + virtual void do_initialize(); + + virtual void do_terminate(); + + virtual ble::buf_pool_desc_t get_buffer_pool_description(); + + private: + void **_ptr_to_handle; + am_hal_ble_config_t _ble_config; + }; +} // namespace ble + +#endif /* APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ */ diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp new file mode 100644 index 0000000000..d71c99a0db --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.cpp @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "AP3CordioHCITransportDriver.h" +#include "am_mcu_apollo.h" +#include "stdio.h" +#include + +#include "wsf_types.h" +#include "wsf_timer.h" +#include "bstream.h" +#include "wsf_msg.h" +#include "wsf_cs.h" + +#include "hci_drv_apollo3.h" + +#define PRINT_DEBUG_HCI 0 + +#if PRINT_DEBUG_HCI +#include "mbed.h" +DigitalOut debugGPIO(D28, 0); +DigitalOut debugGPIO2(D25, 0); +#endif + +using namespace ble; + +#ifndef USE_AMBIQ_DRIVER +static uint8_t ample_buffer[256]; +void *ble_handle = NULL; +#endif + +AP3CordioHCITransportDriver::~AP3CordioHCITransportDriver() {} + +void AP3CordioHCITransportDriver::initialize() +{ +#ifdef USE_AMBIQ_DRIVER + wsfHandlerId_t handlerId = WsfOsSetNextHandler(HciDrvHandler); + HciDrvHandlerInit(handlerId); +#else + am_hal_ble_initialize(0, &handle); + ble_handle = handle; +#endif +} + +void AP3CordioHCITransportDriver::terminate() +{ +#ifdef USE_AMBIQ_DRIVER +#else + am_hal_ble_deinitialize(handle); + handle = NULL; + ble_handle = NULL; +#endif +} + +uint16_t AP3CordioHCITransportDriver::write(uint8_t packet_type, uint16_t len, uint8_t *data) +{ +#if PRINT_DEBUG_HCI + printf("sent tx packet_type: %02X data: ", packet_type); + for (int i = 0; i < len; i++) + { + printf(" %02X", data[i]); + } + printf("\r\n"); +#endif + + //Temporary workaround, random address not working, suppress it. + if (data[0] == 0x06 && data[1] == 0x20) + { +#if PRINT_DEBUG_HCI + printf("LE Set Advertising Params\r\n"); +#endif + data[8] = 0; + } + + uint16_t retLen = 0; +#ifdef USE_AMBIQ_DRIVER + retLen = ap3_hciDrvWrite(packet_type, len, data); +#else + if (handle) + { + uint16_t retVal = (uint16_t)am_hal_ble_blocking_hci_write(handle, packet_type, (uint32_t *)data, (uint16_t)len); + if (retVal == AM_HAL_STATUS_SUCCESS) + { + retLen = len; + } + } +#endif + +#if CORDIO_ZERO_COPY_HCI + WsfMsgFree(data); +#endif + + return retLen; +} + +#ifdef USE_AMBIQ_DRIVER +//Ugly Mutlifile implementation +void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len) +{ +#if PRINT_DEBUG_HCI + printf("data rx: "); + for (int i = 0; i < len; i++) + { + printf("%02X ", data[i]); + } + printf("\r\n"); +#endif + CordioHCITransportDriver::on_data_received(data, len); +} +#else +extern "C" void HciDrvIntService(void) +{ + uint32_t status = am_hal_ble_int_status(ble_handle, false); + if (status & AM_HAL_BLE_INT_BLECIRQ) + { + uint32_t len = 0; + am_hal_ble_blocking_hci_read(ble_handle, (uint32_t *)ample_buffer, &len); + CordioHCITransportDriver::on_data_received(ample_buffer, len); + } + am_hal_ble_int_clear(ble_handle, 0xFFFF); +} +#endif diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h new file mode 100644 index 0000000000..55f922081f --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/TARGET_Apollo3/AP3CordioHCITransportDriver.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ +#define APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ + +#include "CordioHCITransportDriver.h" + +#define AP3_STUPID_DEF_OF_BLECIRQ_BIT 0x00000080 // AM_BLEIF_INT_BLECIRQ + +namespace ble +{ + class AP3CordioHCITransportDriver : public CordioHCITransportDriver + { + public: + //AP3CordioHCITransportDriver(/* specific constructor arguments*/); + + virtual ~AP3CordioHCITransportDriver(); + + virtual void initialize(); + + virtual void terminate(); + + virtual uint16_t write(uint8_t packet_type, uint16_t len, uint8_t *data); + + void *handle; + + private: + // private driver declarations + }; +} // namespace ble + +extern "C" void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len); + +#endif /* APOLLO3_CORDIO_HCI_TRANSPORT_DRIVER_H_ */ diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c new file mode 100644 index 0000000000..79ab1a2d7f --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.c @@ -0,0 +1,1330 @@ +//***************************************************************************** +// +//! @file hci_drv_apollo3.c +//! +//! @brief HCI driver interface. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#if USE_AMBIQ_DRIVER + +#include +#include + +#include "wsf_types.h" +#include "wsf_timer.h" +#include "bstream.h" +#include "wsf_msg.h" +#include "wsf_cs.h" +#include "hci_core.h" +#include "dm_api.h" +#include "am_mcu_apollo.h" +#include "am_util.h" +#include "hci_drv_apollo3.h" + +#include +#include "stdio.h" + +extern void CordioHCITransportDriver_on_data_received(uint8_t *data, uint16_t len); + +//***************************************************************************** +// +// Use the interrupt-driven HCI driver? +// +//***************************************************************************** +#define USE_NONBLOCKING_HCI 1 +#define SKIP_FALLING_EDGES 0 + +//***************************************************************************** +// +// Enable the heartbeat command? +// +// Setting this to 1 will cause the MCU to send occasional HCI packets to the +// BLE core if there hasn't been any activity for a while. This can help catch +// communication issues that might otherwise go unnoticed. +// +//***************************************************************************** +#define ENABLE_BLE_HEARTBEAT 1 + +//***************************************************************************** +// +// Configurable buffer sizes. +// +//***************************************************************************** +#define NUM_HCI_WRITE_BUFFERS 8 +#define HCI_DRV_MAX_TX_PACKET 256 +#define HCI_DRV_MAX_RX_PACKET 256 + +//***************************************************************************** +// +// Configurable error-detection thresholds. +// +//***************************************************************************** +#define HEARTBEAT_TIMEOUT_MS (10000) //milli-seconds +#define HCI_DRV_MAX_IRQ_TIMEOUT 2000 +#define HCI_DRV_MAX_XTAL_RETRIES 10 +#define HCI_DRV_MAX_TX_RETRIES 10000 +#define HCI_DRV_MAX_HCI_TRANSACTIONS 10000 +#define HCI_DRV_MAX_READ_PACKET 4 // max read in a row at a time + +//***************************************************************************** +// +// Structure for holding outgoing HCI packets. +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32Length; + uint32_t pui32Data[HCI_DRV_MAX_TX_PACKET / 4]; +} +hci_drv_write_t; + +//***************************************************************************** +// +// Heartbeat implementation functions. +// +//***************************************************************************** +#if ENABLE_BLE_HEARTBEAT + +#define BLE_HEARTBEAT_START() \ + do { WsfTimerStartMs(&g_HeartBeatTimer, HEARTBEAT_TIMEOUT_MS); } while (0) + +#define BLE_HEARTBEAT_STOP() \ + do { WsfTimerStop(&g_HeartBeatTimer); } while (0) + +#define BLE_HEARTBEAT_RESTART() \ + do \ + { \ + WsfTimerStop(&g_HeartBeatTimer); \ + WsfTimerStartMs(&g_HeartBeatTimer, HEARTBEAT_TIMEOUT_MS); \ + } while (0) + +#else + +#define BLE_HEARTBEAT_START() +#define BLE_HEARTBEAT_STOP() +#define BLE_HEARTBEAT_RESTART() + +#endif + +//***************************************************************************** +// +// Global variables. +// +//***************************************************************************** + +// BLE module handle +void *BLE; + +//fixme: set the BLE MAC address to a special value +uint8_t g_BLEMacAddress[6] = {0x01,0x02,0x03,0x04,0x05,0x06}; + +// Global handle used to send BLE events about the Hci driver layer. +wsfHandlerId_t g_HciDrvHandleID = 0; +wsfTimer_t g_HeartBeatTimer; +wsfTimer_t g_WakeTimer; + +// Buffers for HCI write data. +hci_drv_write_t g_psWriteBuffers[NUM_HCI_WRITE_BUFFERS]; +am_hal_queue_t g_sWriteQueue; + +// Buffers for HCI read data. +uint32_t g_pui32ReadBuffer[HCI_DRV_MAX_RX_PACKET / 4]; +uint8_t *g_pui8ReadBuffer = (uint8_t *) g_pui32ReadBuffer; +volatile bool bReadBufferInUse = false; + +uint32_t g_ui32NumBytes = 0; +uint32_t g_consumed_bytes = 0; + +// Counters for tracking read data. +volatile uint32_t g_ui32InterruptsSeen = 0; + +void HciDrvEmptyWriteQueue(void); +//***************************************************************************** +// +// Forward declarations for HCI callbacks. +// +//***************************************************************************** +#if USE_NONBLOCKING_HCI +void hciDrvWriteCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext); +void hciDrvReadCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext); +#endif // USE_NONBLOCKING_HCI + +//***************************************************************************** +// +// Events for the HCI driver interface. +// +//***************************************************************************** +#define BLE_TRANSFER_NEEDED_EVENT 0x01 +#define BLE_HEARTBEAT_EVENT 0x02 +#define BLE_SET_WAKEUP 0x03 + +//***************************************************************************** +// +// Error-handling wrapper macro. +// +//***************************************************************************** +#define ERROR_CHECK_VOID(status) \ + { \ + uint32_t ui32ErrChkStatus; \ + if (0 != (ui32ErrChkStatus = (status))) \ + { \ + am_util_debug_printf("ERROR_CHECK_VOID "#status "\n"); \ + error_check(ui32ErrChkStatus); \ + return; \ + } \ + } + +#define ERROR_RETURN(status, retval) \ + if ((status)) \ + { \ + error_check(status); \ + return (retval); \ + } + +#define ERROR_RECOVER(status) \ + if ((status)) \ + { \ + am_hal_debug_gpio_toggle(BLE_DEBUG_TRACE_10); \ + error_check(status); \ + HciDrvRadioShutdown(); \ + HciDrvRadioBoot(0); \ + HciDrvEmptyWriteQueue(); \ + DmDevReset(); \ + return; \ + } + +//***************************************************************************** +// +// Debug section. +// +//***************************************************************************** +#if 0 +#define CRITICAL_PRINT(...) \ + do \ + { \ + AM_CRITICAL_BEGIN; \ + am_util_debug_printf(__VA_ARGS__); \ + AM_CRITICAL_END; \ + } while (0) +#else +#if 0 +#define CRITICAL_PRINT(...) printf(__VA_ARGS__); +#endif +#define CRITICAL_PRINT(...) +#endif + +#define ENABLE_IRQ_PIN 0 + +#define TASK_LEVEL_DELAYS 0 + + +//***************************************************************************** +// +// Function pointer for redirecting errors +// +//***************************************************************************** +hci_drv_error_handler_t g_hciDrvErrorHandler = 0; +static uint32_t g_ui32FailingStatus = 0; + +//***************************************************************************** +// +// By default, errors will be printed. If there is an error handler defined, +// they will be sent there intead. +// +//***************************************************************************** +static void +error_check(uint32_t ui32Status) +{ + // + // Don't do anything unless there's an error. + // + if (ui32Status) + { + // + // Set the global error status. If there's an error handler function, + // call it. Otherwise, just print the error status and wait. + // + g_ui32FailingStatus = ui32Status; + + if (g_hciDrvErrorHandler) + { + g_hciDrvErrorHandler(g_ui32FailingStatus); + } + else + { + CRITICAL_PRINT("Error detected: 0x%08x\n", g_ui32FailingStatus); + CRITICAL_PRINT("BSTATUS: 0x%08x\n", BLEIF->BSTATUS); + } + } +} + +//***************************************************************************** +// +// Other useful macros. +// +//***************************************************************************** + +#define BLE_IRQ_CHECK() (BLEIF->BSTATUS_b.BLEIRQ) + +// Ellisys HCI SPI tapping support + +// #define ELLISYS_HCI_LOG_SUPPORT 1 + +//***************************************************************************** +// +// Boot the radio. +// +//***************************************************************************** +void +HciDrvRadioBoot(bool bColdBoot) +{ + uint32_t ui32NumXtalRetries = 0; + + + g_ui32NumBytes = 0; + g_consumed_bytes = 0; +#if !defined(AM_DEBUG_BLE_TIMING) && defined(ELLISYS_HCI_LOG_SUPPORT) + am_hal_gpio_pincfg_t pincfg = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + pincfg.uFuncSel = 6; + am_hal_gpio_pinconfig(30, pincfg); + am_hal_gpio_pinconfig(31, pincfg); + am_hal_gpio_pinconfig(32, pincfg); + pincfg.uFuncSel = 4; + am_hal_gpio_pinconfig(33, pincfg); + pincfg.uFuncSel = 7; + am_hal_gpio_pinconfig(35, pincfg); +#endif + +#ifdef AM_DEBUG_BLE_TIMING + // + // Enable debug pins. + // + // 30.6 - SCLK + // 31.6 - MISO + // 32.6 - MOSI + // 33.4 - CSN + // 35.7 - SPI_STATUS + // + am_hal_gpio_pincfg_t pincfg = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + pincfg.uFuncSel = 6; + am_hal_gpio_pinconfig(30, pincfg); + am_hal_gpio_pinconfig(31, pincfg); + am_hal_gpio_pinconfig(32, pincfg); + pincfg.uFuncSel = 4; + am_hal_gpio_pinconfig(33, pincfg); + pincfg.uFuncSel = 7; + am_hal_gpio_pinconfig(35, pincfg); + pincfg.uFuncSel = 1; +#if ENABLE_IRQ_PIN + am_hal_gpio_pinconfig(41, pincfg); + am_hal_debug_gpio_pinconfig(BLE_DEBUG_TRACE_08); +#endif + + am_hal_gpio_pinconfig(11, g_AM_HAL_GPIO_OUTPUT); + +#endif // AM_DEBUG_BLE_TIMING + + // + // This pin is also used to generate BLE interrupts in the current + // implementation. + // + // 41.1 - BLE IRQ + // + //am_hal_gpio_pin_config(41, AM_HAL_GPIO_FUNC(1)); + + + // + // Configure and enable the BLE interface. + // + uint32_t ui32Status = AM_HAL_STATUS_FAIL; + while (ui32Status != AM_HAL_STATUS_SUCCESS) + { + ERROR_CHECK_VOID(am_hal_ble_initialize(0, &BLE)); + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_ACTIVE)); + + am_hal_ble_config_t sBleConfig = + { + // Configure the HCI interface clock for 6 MHz + .ui32SpiClkCfg = AM_HAL_BLE_HCI_CLK_DIV8, + + // Set HCI read and write thresholds to 32 bytes each. + .ui32ReadThreshold = 32, + .ui32WriteThreshold = 32, + + // The MCU will supply the clock to the BLE core. + .ui32BleClockConfig = AM_HAL_BLE_CORE_MCU_CLK, +#if 0 + // Default settings for expected BLE clock drift (measured in PPM). + .ui32ClockDrift = 0, + .ui32SleepClockDrift = 50, + + // Default setting - AGC Enabled + .bAgcEnabled = true, + + // Default setting - Sleep Algo enabled + .bSleepEnabled = true, +#endif + // Apply the default patches when am_hal_ble_boot() is called. + .bUseDefaultPatches = true, + }; + + ERROR_CHECK_VOID(am_hal_ble_config(BLE, &sBleConfig)); + // + // Delay 1s for 32768Hz clock stability. This isn't required unless this is + // our first run immediately after a power-up. + // + if ( bColdBoot ) + { + am_util_delay_ms(1000); + } + // + // Attempt to boot the radio. + // + ui32Status = am_hal_ble_boot(BLE); + + // + // Check our status. + // + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // + // If the radio is running, we can exit this loop. + // + break; + } + else if (ui32Status == AM_HAL_BLE_32K_CLOCK_UNSTABLE) + { + // + // If the radio is running, but the clock looks bad, we can try to + // restart. + // + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF)); + ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE)); + + // + // We won't restart forever. After we hit the maximum number of + // retries, we'll just return with failure. + // + if (ui32NumXtalRetries++ < HCI_DRV_MAX_XTAL_RETRIES) + { + am_util_delay_ms(1000); + } + else + { + return; + } + } + else + { + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF)); + ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE)); + // + // If the radio failed for some reason other than 32K Clock + // instability, we should just report the failure and return. + // + error_check(ui32Status); + return; + } + } + + // + // Set the BLE TX Output power to 0dBm. + // + am_hal_ble_tx_power_set(BLE, 0x8); + + // + // Enable interrupts for the BLE module. + // +#if USE_NONBLOCKING_HCI + am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ | + AM_HAL_BLE_INT_BLECSSTAT)); + + am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ | + AM_HAL_BLE_INT_BLECSSTAT)); + +#if SKIP_FALLING_EDGES +#else + if (APOLLO3_GE_B0) + { + am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_BLECIRQN | + AM_HAL_BLE_INT_BLECSSTATN)); + + am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_BLECIRQN | + AM_HAL_BLE_INT_BLECSSTATN)); + } +#endif + +#else + + am_hal_ble_int_clear(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ)); + + am_hal_ble_int_enable(BLE, (AM_HAL_BLE_INT_CMDCMP | + AM_HAL_BLE_INT_DCMP | + AM_HAL_BLE_INT_BLECIRQ)); +#endif + + CRITICAL_PRINT("INTEN: %d\n", BLEIF->INTEN_b.BLECSSTAT); + CRITICAL_PRINT("INTENREG: %d\n", BLEIF->INTEN); + + NVIC_EnableIRQ(BLE_IRQn); + + // + // Initialize a queue to help us keep track of HCI write buffers. + // + am_hal_queue_from_array(&g_sWriteQueue, g_psWriteBuffers); + + //WsfSetEvent(g_HciDrvHandleID, BLE_HEARTBEAT_EVENT); + // + // Reset the RX interrupt counter. + // + g_ui32InterruptsSeen = 0; + + return; +} + +//***************************************************************************** +// +// Shut down the BLE core. +// +//***************************************************************************** +void +HciDrvRadioShutdown(void) +{ + BLE_HEARTBEAT_STOP(); + + NVIC_DisableIRQ(BLE_IRQn); + + ERROR_CHECK_VOID(am_hal_ble_power_control(BLE, AM_HAL_BLE_POWER_OFF)); + + while ( PWRCTRL->DEVPWREN_b.PWRBLEL ) + { + } + + ERROR_CHECK_VOID(am_hal_ble_deinitialize(BLE)); + + g_ui32NumBytes = 0; + g_consumed_bytes = 0; +} + +#if USE_NONBLOCKING_HCI +//***************************************************************************** +// +// Short Description. +// +//***************************************************************************** +static void +update_wake(void) +{ + AM_CRITICAL_BEGIN; + + // + // We want to set WAKE if there's something in the write queue, but not if + // SPISTATUS or IRQ is high. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) && + (BLEIFn(0)->BSTATUS_b.SPISTATUS == 0) && + (BLE_IRQ_CHECK() == false)) + { + am_hal_ble_wakeup_set(BLE, 1); + + // + // If we've set wakeup, but IRQ came up at the same time, we should + // just lower WAKE again. + // + if (BLE_IRQ_CHECK() == true) + { + am_hal_ble_wakeup_set(BLE, 0); + } + } + + AM_CRITICAL_END; +} +#endif + +//***************************************************************************** +// +// Function used by the BLE stack to send HCI messages to the BLE controller. +// +// Internally, the Cordio BLE stack will allocate memory for an HCI message, +// +//***************************************************************************** +uint16_t +ap3_hciDrvWrite(uint8_t type, uint16_t len, uint8_t *pData) +{ + uint8_t *pui8Wptr; + hci_drv_write_t *psWriteBuffer; + + + // + // Check to see if we still have buffer space. + // + if (am_hal_queue_full(&g_sWriteQueue)) + { + CRITICAL_PRINT("ERROR: Ran out of HCI transmit queue slots.\n"); + ERROR_RETURN(HCI_DRV_TRANSMIT_QUEUE_FULL, len); + } + + if (len > (HCI_DRV_MAX_TX_PACKET-1)) // comparison compensates for the type byte at index 0. + { + CRITICAL_PRINT("ERROR: Trying to send an HCI packet larger than the hci driver buffer size (needs %d bytes of space).\n", + len); + + ERROR_RETURN(HCI_DRV_TX_PACKET_TOO_LARGE, len); + } + + // + // Get a pointer to the next item in the queue. + // + psWriteBuffer = am_hal_queue_next_slot(&g_sWriteQueue); + + // + // Set all of the fields in the hci write structure. + // + psWriteBuffer->ui32Length = len + 1; + + pui8Wptr = (uint8_t *) psWriteBuffer->pui32Data; + + *pui8Wptr++ = type; + + for (uint32_t i = 0; i < len; i++) + { + pui8Wptr[i] = pData[i]; + } + + // + // Advance the queue. + // + am_hal_queue_item_add(&g_sWriteQueue, 0, 1); + +#if USE_NONBLOCKING_HCI + // + // Wake up the BLE controller. + // + CRITICAL_PRINT("INFO: HCI write requested.\n"); + + update_wake(); + +#else + // + // Send an event to the BLE transfer handler function. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); +#endif + +#ifdef AM_CUSTOM_BDADDR + if (type == HCI_CMD_TYPE) + { + uint16_t opcode; + BYTES_TO_UINT16(opcode, pData); + + if (HCI_OPCODE_RESET == opcode) + { + + extern uint8_t g_BLEMacAddress[6]; + am_hal_mcuctrl_device_t sDevice; + am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &sDevice); + g_BLEMacAddress[0] = sDevice.ui32ChipID0; + g_BLEMacAddress[1] = sDevice.ui32ChipID0 >> 8; + g_BLEMacAddress[2] = sDevice.ui32ChipID0 >> 16; + + HciVendorSpecificCmd(0xFC32, 6, g_BLEMacAddress); + } + } +#endif + + return len; +} + +//***************************************************************************** +// +// Save the handler ID of the HciDrvHandler so we can send it events through +// the WSF task system. +// +// Note: These two lines need to be added to the exactle initialization +// function at the beginning of all Cordio applications: +// +// handlerId = WsfOsSetNextHandler(HciDrvHandler); +// HciDrvHandler(handlerId); +// +//***************************************************************************** +void +HciDrvHandlerInit(wsfHandlerId_t handlerId) +{ + g_HciDrvHandleID = handlerId; + + g_HeartBeatTimer.handlerId = handlerId; + g_HeartBeatTimer.msg.event = BLE_HEARTBEAT_EVENT; + + g_WakeTimer.handlerId = handlerId; + g_WakeTimer.msg.event = BLE_SET_WAKEUP; +} + +//***************************************************************************** +// +// Simple interrupt handler to call +// +// Note: These two lines need to be added to the exactle initialization +// function at the beginning of all Cordio applications: +// +// handlerId = WsfOsSetNextHandler(HciDrvHandler); +// HciDrvHandler(handlerId); +// +//***************************************************************************** +void +HciDrvIntService(void) +{ +#if AM_DEBUG_BLE_TIMING + am_hal_gpio_state_write(11, AM_HAL_GPIO_OUTPUT_SET); +#endif + + // + // Read and clear the interrupt status. + // + uint32_t ui32Status = am_hal_ble_int_status(BLE, true); + am_hal_ble_int_clear(BLE, ui32Status); + +#if USE_NONBLOCKING_HCI + // + // Handle any DMA or Command Complete interrupts. + // + am_hal_ble_int_service(BLE, ui32Status); + + // + // If this was a BLEIRQ interrupt, attempt to start a read operation. If it + // was a STATUS interrupt, start a write operation. + // + if (ui32Status & AM_HAL_BLE_INT_BLECIRQ) + { + // CRITICAL_PRINT("INFO: IRQ INTERRUPT\n"); + + // + // Lower WAKE + // + //WsfTimerStop(&g_WakeTimer); + // CRITICAL_PRINT("IRQ Drop\n"); + am_hal_ble_wakeup_set(BLE, 0); + + // + // Prepare to read a message. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + } + else if (ui32Status & AM_HAL_BLE_INT_BLECSSTAT) + { + // CRITICAL_PRINT("INFO: STATUS INTERRUPT\n"); + + // + // Check the queue and send the first message we have. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) ) + { + uint32_t ui32WriteStatus = 0; + + hci_drv_write_t *psWriteBuffer = am_hal_queue_peek(&g_sWriteQueue); + + ui32WriteStatus = + am_hal_ble_nonblocking_hci_write(BLE, + AM_HAL_BLE_RAW, + psWriteBuffer->pui32Data, + psWriteBuffer->ui32Length, + hciDrvWriteCallback, + 0); + + // + // If it succeeded, we can pop the queue. + // + if (ui32WriteStatus == AM_HAL_STATUS_SUCCESS) + { + BLE_HEARTBEAT_RESTART(); + // CRITICAL_PRINT("INFO: HCI write sent.\n"); + } + else + { + // CRITICAL_PRINT("INFO: HCI write failed: %d\n", ui32WriteStatus); + } + } + } + +#else + // + // Advance an event counter to make sure we're keeping track of edges + // correctly. + // + g_ui32InterruptsSeen++; + + // + // Send an event to get processed in the HCI handler. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); +#endif + +#if AM_DEBUG_BLE_TIMING + am_hal_gpio_state_write(11, AM_HAL_GPIO_OUTPUT_CLEAR); +#endif +} + +#if USE_NONBLOCKING_HCI + +//***************************************************************************** +// +// This function determines what to do when a write operation completes. +// +//***************************************************************************** +void +hciDrvWriteCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext) +{ + CRITICAL_PRINT("INFO: HCI physical write complete.\n"); + + am_hal_queue_item_get(&g_sWriteQueue, 0, 1); + +#if TASK_LEVEL_DELAYS + + // Set a WSF timer to update wake later. + WsfTimerStartMs(&g_WakeTimer, 30); + +#else // TASK_LEVEL_DELAYS + + while ( BLEIFn(0)->BSTATUS_b.SPISTATUS ) + { + am_util_delay_us(5); + } + + // + // Check the write queue, and possibly set wake again. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) ) + { + // + // In this case, we need to delay before setting wake. Instead of + // delaying here, we'll post an event to do it later. + // + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + } + +#endif // TASK_LEVEL_DELAYS +} + +//***************************************************************************** +// +// This function determines what to do when a read operation completes. +// +//***************************************************************************** +void +hciDrvReadCallback(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext) +{ + // + // Set a "transfer needed" event. + // + // CRITICAL_PRINT("INFO: HCI physical read complete.\n"); + g_ui32NumBytes = ui32Length; + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + +#if TASK_LEVEL_DELAYS + + // Set a WSF timer to update wake later. + WsfTimerStartMs(&g_WakeTimer, 30); + +#else // TASK_LEVEL_DELAYS + + while ( BLE_IRQ_CHECK() ) + { + am_util_delay_us(5); + } + + // + // Check the write queue, and possibly set wake. + // + if ( !am_hal_queue_empty(&g_sWriteQueue) ) + { + am_hal_ble_wakeup_set(BLE, 1); + } + +#endif // TASK_LEVEL_DELAYS +} + +//***************************************************************************** +// +// Event handler for HCI-related events. +// +// This handler can perform HCI reads or writes, and keeps the actions in the +// correct order. +// +//***************************************************************************** +void +HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg) +{ + uint32_t ui32ErrorStatus; + + // + // If this handler was called in response to a heartbeat event, then it's + // time to run a benign HCI command. Normally, the BLE controller should + // handle this command without issue. If it doesn't acknowledge the + // command, we will eventually get an HCI command timeout error, which will + // alert us to the fact that the BLE core has become unresponsive in + // general. + // + if (pMsg->event == BLE_HEARTBEAT_EVENT) + { + HciReadLocalVerInfoCmd(); + BLE_HEARTBEAT_START(); + return; + } + + if (pMsg->event == BLE_SET_WAKEUP) + { + // + // Attempt to set WAKE again. + // + update_wake(); + return; + } + + // + // Check to see if we read any bytes over the HCI interface that we haven't + // already sent to the BLE stack. + // + if (g_ui32NumBytes > g_consumed_bytes) + { + CRITICAL_PRINT("INFO: HCI data transferred to stack.\n"); + // + // If we have any bytes saved, we should send them to the BLE stack + // now. + // + CordioHCITransportDriver_on_data_received(g_pui8ReadBuffer + g_consumed_bytes, + g_ui32NumBytes - g_consumed_bytes); + g_consumed_bytes = g_ui32NumBytes; + //g_consumed_bytes += hciTrSerialRxIncoming(g_pui8ReadBuffer + g_consumed_bytes, + // g_ui32NumBytes - g_consumed_bytes); + + // + // If the stack doesn't accept all of the bytes we had, we will need to + // keep the event set and come back later. Otherwise, we can just reset + // our variables and exit the loop. + // + if (g_consumed_bytes != g_ui32NumBytes) + { + CRITICAL_PRINT("INFO: HCI data split up.\n"); + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + return; + } + else + { + CRITICAL_PRINT("INFO: HCI RX packet complete.\n"); + g_ui32NumBytes = 0; + g_consumed_bytes = 0; + bReadBufferInUse = false; + } + } + + if ( BLE_IRQ_CHECK() ) + { + if (bReadBufferInUse == true) + { + CRITICAL_PRINT("Read buffer already in use.\n"); + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + return; + } + + // + // If the stack has used up all of the saved data we've accumulated so + // far, we should check to see if we need to read any *new* data. + // + CRITICAL_PRINT("INFO: HCI Read started.\n"); + bReadBufferInUse = true; + ui32ErrorStatus = am_hal_ble_nonblocking_hci_read(BLE, + g_pui32ReadBuffer, + hciDrvReadCallback, + 0); + + BLE_HEARTBEAT_RESTART(); + + if (g_ui32NumBytes > HCI_DRV_MAX_RX_PACKET) + { + CRITICAL_PRINT("ERROR: Trying to receive an HCI packet " + "larger than the hci driver buffer size " + "(needs %d bytes of space).\n", + g_ui32NumBytes); + + ERROR_CHECK_VOID(HCI_DRV_RX_PACKET_TOO_LARGE); + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + // + // If the read didn't succeed for some physical reason, we need + // to know. We shouldn't get failures here. We checked the IRQ + // signal before calling the read function, and this driver + // only contains a single call to the blocking read function, + // so there shouldn't be any physical reason for the read to + // fail. + // + CRITICAL_PRINT("HCI READ failed with status %d. " + "Try recording with a logic analyzer " + "to catch the error.\n", + ui32ErrorStatus); + + ERROR_RECOVER(ui32ErrorStatus); + } + } +} +#else +//***************************************************************************** +// +// Event handler for HCI-related events. +// +// This handler can perform HCI reads or writes, and keeps the actions in the +// correct order. +// +//***************************************************************************** +void +HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg) +{ + uint32_t ui32ErrorStatus, ui32TxRetries = 0; + uint32_t ui32NumHciTransactions = 0; + uint32_t read_hci_packet_count = 0; + + // + // If this handler was called in response to a heartbeat event, then it's + // time to run a benign HCI command. Normally, the BLE controller should + // handle this command without issue. If it doesn't acknowledge the + // command, we will eventually get an HCI command timeout error, which will + // alert us to the fact that the BLE core has become unresponsive in + // general. + // + if (pMsg->event == BLE_HEARTBEAT_EVENT) + { + HciReadLocalVerInfoCmd(); + BLE_HEARTBEAT_START(); + return; + } + + // + // Check to see if we read any bytes over the HCI interface that we haven't + // already sent to the BLE stack. + // + if (g_ui32NumBytes > g_consumed_bytes) + { + // + // If we have any bytes saved, we should send them to the BLE stack + // now. + // + CordioHCITransportDriver_on_data_received(g_pui8ReadBuffer + g_consumed_bytes, + g_ui32NumBytes - g_consumed_bytes); + g_consumed_bytes = g_ui32NumBytes; + // g_consumed_bytes += hciTrSerialRxIncoming(g_pui8ReadBuffer + g_consumed_bytes, + // g_ui32NumBytes - g_consumed_bytes); + + // + // If the stack doesn't accept all of the bytes we had, + // + if (g_consumed_bytes != g_ui32NumBytes) + { + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + return; + } + else + { + g_ui32NumBytes = 0; + g_consumed_bytes = 0; + } + } + + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_01); + + // + // Loop indefinitely, checking to see if there are still tranfsers we need + // to complete. + // + while (ui32NumHciTransactions++ < HCI_DRV_MAX_HCI_TRANSACTIONS) + { + // + // Figure out what kind of transfer the BLE core will accept. + // + if ( BLE_IRQ_CHECK() ) + { + uint32_t ui32OldInterruptsSeen = g_ui32InterruptsSeen; + + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_02); + + BLE_HEARTBEAT_RESTART(); + + // + // Is the BLE core asking for a read? If so, do that now. + // + g_ui32NumBytes = 0; + ui32ErrorStatus = am_hal_ble_blocking_hci_read(BLE, (uint32_t*)g_pui32ReadBuffer, &g_ui32NumBytes); + + if (g_ui32NumBytes > HCI_DRV_MAX_RX_PACKET) + { + CRITICAL_PRINT("ERROR: Trying to receive an HCI packet larger than the hci driver buffer size (needs %d bytes of space).", + g_ui32NumBytes); + + ERROR_CHECK_VOID(HCI_DRV_RX_PACKET_TOO_LARGE); + } + + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS) + { + + // + // If the read succeeded, we need to wait for the IRQ signal to + // go back down. If we don't we might inadvertently try to read + // the same packet twice. + // + uint32_t ui32IRQRetries; + for (ui32IRQRetries = 0; ui32IRQRetries < HCI_DRV_MAX_IRQ_TIMEOUT; ui32IRQRetries++) + { + if (BLE_IRQ_CHECK() == 0 || g_ui32InterruptsSeen != ui32OldInterruptsSeen) + { + break; + } + + am_util_delay_us(1); + } + + // + // Pass the data along to the stack. The stack should be able + // to read as much data as we send it. If it can't, we need to + // know that. + // + + CordioHCITransportDriver_on_data_received(g_pui8ReadBuffer, g_ui32NumBytes); + g_consumed_bytes = g_ui32NumBytes; + // g_consumed_bytes = hciTrSerialRxIncoming(g_pui8ReadBuffer, g_ui32NumBytes); + if (g_consumed_bytes != g_ui32NumBytes) + { + + // need to come back again + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + // take a break now + + // worst case disable BLE_IRQ + break; + } + + g_ui32NumBytes = 0; + g_consumed_bytes = 0; + + read_hci_packet_count++; + } + else + { + // + // If the read didn't succeed for some physical reason, we need + // to know. We shouldn't get failures here. We checked the IRQ + // signal before calling the read function, and this driver + // only contains a single call to the blocking read function, + // so there shouldn't be any physical reason for the read to + // fail. + // + CRITICAL_PRINT("HCI READ failed with status %d. Try recording with a logic analyzer to catch the error.\n", + ui32ErrorStatus); + + ERROR_RECOVER(ui32ErrorStatus); + } + + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_02); + + if (read_hci_packet_count >= HCI_DRV_MAX_READ_PACKET) + { + // It looks like there's time that we won't get interrupt even though + // there's packet waiting for host to grab. + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + + break; + } + + } + else + { + // + // If we don't have anything to read, we can start checking to see + // if we have things to write. + // + if (am_hal_queue_empty(&g_sWriteQueue)) + { + // + // If not, we're done! + // + break; + } + else + { + // + // If we do have something to write, just pop a single item + // from the queue and send it. + // + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_07); + hci_drv_write_t *psWriteBuffer = am_hal_queue_peek(&g_sWriteQueue); + + ui32ErrorStatus = am_hal_ble_blocking_hci_write(BLE, + AM_HAL_BLE_RAW, + psWriteBuffer->pui32Data, + psWriteBuffer->ui32Length); + + // + // If we managed to actually send a packet, we can go ahead and + // advance the queue. + // + if (ui32ErrorStatus == AM_HAL_STATUS_SUCCESS) + { + // + // Restart the heartbeat timer. + // + BLE_HEARTBEAT_RESTART(); + + am_hal_queue_item_get(&g_sWriteQueue, 0, 1); + + ui32TxRetries = 0; + // Resetting the cumulative count + ui32NumHciTransactions = 0; + } + else + { + // + // If we fail too many times in a row, we should throw an + // error to avoid a lock-up. + // + ui32TxRetries++; + + if (ui32TxRetries > HCI_DRV_MAX_TX_RETRIES) + { + // we need to come back again later. + WsfSetEvent(g_HciDrvHandleID, BLE_TRANSFER_NEEDED_EVENT); + break; + } + } + + } + } + } + + if (ui32NumHciTransactions == HCI_DRV_MAX_HCI_TRANSACTIONS) + { + CRITICAL_PRINT("ERROR: Maximum number of successive HCI transactions exceeded.\n"); + ERROR_RECOVER(HCI_DRV_TOO_MANY_PACKETS); + } + + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_01); +} +#endif + +//***************************************************************************** +// +// Register an error handler for the HCI driver. +// +//***************************************************************************** +void +HciDrvErrorHandlerSet(hci_drv_error_handler_t pfnErrorHandler) +{ + g_hciDrvErrorHandler = pfnErrorHandler; +} + +/*************************************************************************************************/ +/*! + * \fn HciVsA3_SetRfPowerLevelEx + * + * \brief Vendor specific command for settting Radio transmit power level + * for Nationz. + * + * \param txPowerlevel valid range from 0 to 15 in decimal. + * + * \return true when success, otherwise false + */ +/*************************************************************************************************/ +bool_t +HciVsA3_SetRfPowerLevelEx(txPowerLevel_t txPowerlevel) +{ + switch (txPowerlevel) { + + case TX_POWER_LEVEL_MINUS_10P0_dBm: + am_hal_ble_tx_power_set(BLE,0x04); + return true; + break; + case TX_POWER_LEVEL_0P0_dBm: + am_hal_ble_tx_power_set(BLE,0x08); + return true; + break; + case TX_POWER_LEVEL_PLUS_3P0_dBm: + am_hal_ble_tx_power_set(BLE,0x0F); + return true; + break; + default: + return false; + break; + } +} + +/*************************************************************************************************/ +/*! + * \fn HciDrvBleSleepSet + * + * \brief Set BLE sleep enable/disable for the BLE core. + * + * \param enable 'true' set sleep enable, 'false' set sleep disable + * + * \return none + */ +/*************************************************************************************************/ +void +HciDrvBleSleepSet(bool enable) +{ + am_hal_ble_sleep_set(BLE, enable); +} + +//***************************************************************************** +// +// Clear the HCI write queue +// +//***************************************************************************** +void +HciDrvEmptyWriteQueue(void) +{ + am_hal_queue_from_array(&g_sWriteQueue, g_psWriteBuffers); +} + +#endif diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h new file mode 100644 index 0000000000..6fab82281c --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_Ambiq_Micro/hal/apollo3/hci_drv_apollo3.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +//! @file hci_drv_apollo3.h +//! +//! @brief Support functions for the Nationz BTLE radio in Apollo3. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.3.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +#ifndef HCI_DRV_APOLLO3_H +#define HCI_DRV_APOLLO3_H + +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** + // + // NATIONZ vendor specific events + // + //***************************************************************************** + + // Tx power level in dBm. + typedef enum + { + TX_POWER_LEVEL_MINUS_10P0_dBm = 0x3, + TX_POWER_LEVEL_0P0_dBm = 0x8, + TX_POWER_LEVEL_PLUS_3P0_dBm = 0xF, + TX_POWER_LEVEL_INVALID = 0x10, + } txPowerLevel_t; + +#define HCI_DRV_SPECIFIC_ERROR_START 0x09000000 + typedef enum + { + HCI_DRV_TRANSMIT_QUEUE_FULL = HCI_DRV_SPECIFIC_ERROR_START, + HCI_DRV_TX_PACKET_TOO_LARGE, + HCI_DRV_RX_PACKET_TOO_LARGE, + HCI_DRV_BLE_STACK_UNABLE_TO_ACCEPT_PACKET, + HCI_DRV_PACKET_TRANSMIT_FAILED, + HCI_DRV_IRQ_STUCK_HIGH, + HCI_DRV_TOO_MANY_PACKETS, + } hci_drv_error_t; + + typedef void (*hci_drv_error_handler_t)(uint32_t ui32Error); + + bool_t HciVsA3_SetRfPowerLevelEx(txPowerLevel_t txPowerlevel); + void HciVsA3_ConstantTransmission(uint8_t txchannel); + void HciVsA3_CarrierWaveMode(uint8_t txchannel); + + //***************************************************************************** + // + // Hci driver functions unique to Apollo3 + // + //***************************************************************************** + extern void HciDrvHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg); + extern void HciDrvHandlerInit(wsfHandlerId_t handlerId); + extern void HciDrvIntService(void); + + uint16_t ap3_hciDrvWrite(uint8_t type, uint16_t len, uint8_t *pData); + + extern void HciDrvRadioBoot(bool bColdBoot); + extern void HciDrvRadioShutdown(void); + +#ifdef __cplusplus +}; +#endif + +#endif // HCI_DRV_APOLLO3_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c new file mode 100644 index 0000000000..d28ba41102 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.c @@ -0,0 +1,949 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +//***************************************************************************** +// +//! @file HM01B0.c +//! +// +//***************************************************************************** + +#include "am_mcu_apollo.h" +#include "am_bsp.h" +#include "am_util.h" +#include "HM01B0.h" +#include "HM01B0_Walking1s_01.h" +#include "platform.h" + +#define read_vsync() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_VSYNC)) +#define read_hsync() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_HSYNC)) +#define read_pclk() (AM_REGVAL(AM_REGADDR(GPIO, RDA)) & (1 << HM01B0_PIN_PCLK)) +#define read_byte() (APBDMA->BBINPUT) + +const am_hal_gpio_pincfg_t g_HM01B0_pin_int = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN +}; + +//***************************************************************************** +// +//! @brief Write HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the data to be written. +//! @param ui32NumBytes - Length of the data in bytes to be written. +//! +//! This function writes value to HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_write_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes) +{ + am_hal_iom_transfer_t Transaction; + + // + // Create the transaction. + // + Transaction.ui32InstrLen = sizeof(uint16_t); + Transaction.ui32Instr = (ui16Reg & 0x0000FFFF); + Transaction.eDirection = AM_HAL_IOM_TX; + Transaction.ui32NumBytes = ui32NumBytes; + Transaction.pui32TxBuffer = (uint32_t *) pui8Value; + Transaction.uPeerInfo.ui32I2CDevAddr = (uint32_t) psCfg->ui16SlvAddr; + Transaction.bContinue = false; + Transaction.ui8RepeatCount = 0; + Transaction.ui32PauseCondition = 0; + Transaction.ui32StatusSetClr = 0; + + // + // Execute the transction over IOM. + // + if (am_hal_iom_blocking_transfer(psCfg->pIOMHandle, &Transaction)) + { + return HM01B0_ERR_I2C; + } + + return HM01B0_ERR_OK; + +} + +//***************************************************************************** +// +//! @brief Read HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the buffer for read data to be put into. +//! @param ui32NumBytes - Length of the data to be read. +//! +//! This function reads value from HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_read_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes) +{ + am_hal_iom_transfer_t Transaction; + + // + // Create the transaction. + // + Transaction.ui32InstrLen = sizeof(uint16_t); + Transaction.ui32Instr = (ui16Reg & 0x0000FFFF); + Transaction.eDirection = AM_HAL_IOM_RX; + Transaction.ui32NumBytes = ui32NumBytes; + Transaction.pui32RxBuffer = (uint32_t *) pui8Value;; + Transaction.uPeerInfo.ui32I2CDevAddr = (uint32_t) psCfg->ui16SlvAddr; + Transaction.bContinue = false; + Transaction.ui8RepeatCount = 0; + Transaction.ui32PauseCondition = 0; + Transaction.ui32StatusSetClr = 0; + + // + // Execute the transction over IOM. + // + if (am_hal_iom_blocking_transfer(psCfg->pIOMHandle, &Transaction)) + { + return HM01B0_ERR_I2C; + } + + return HM01B0_ERR_OK; +} + +//***************************************************************************** +// +//! @brief Load HM01B0 a given script +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScrip - Pointer to the script to be loaded. +//! @param ui32ScriptCmdNum - Number of entries in a given script. +//! +//! This function loads HM01B0 a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_load_script(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + for (uint32_t idx = 0; idx < ui32ScriptCmdNum; idx++) + { + ui32Err = hm01b0_write_reg(psCfg, \ + (psScript + idx)->ui16Reg, \ + &((psScript + idx)->ui8Val), \ + sizeof(uint8_t)); + if (ui32Err != HM01B0_ERR_OK) + { + break; + } + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Power up HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_up(hm01b0_cfg_t *psCfg) +{ + // place holder +} + +//***************************************************************************** +// +//! @brief Power down HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_down(hm01b0_cfg_t *psCfg) +{ + // place holder +} + +//***************************************************************************** +// +//! @brief Enable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function utilizes CTimer to generate MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_enable(hm01b0_cfg_t *psCfg) +{ +#define MCLK_UI64PATTERN 0x55555555 +#define MCLK_UI64PATTERNLEN 31 + + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0); + + // + // Set up timer. + // + am_hal_ctimer_clear(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment); + + am_hal_ctimer_config_single(psCfg->ui32CTimerModule, + psCfg->ui32CTimerSegment, + ( + AM_HAL_CTIMER_FN_PTN_REPEAT | + AM_HAL_CTIMER_HFRC_12MHZ + ) + ); + + // + // Set the pattern in the CMPR registers. + // + am_hal_ctimer_compare_set(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment, 0, + (uint32_t)(MCLK_UI64PATTERN & 0xFFFF)); + am_hal_ctimer_compare_set(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment, 1, + (uint32_t)((MCLK_UI64PATTERN >> 16) & 0xFFFF)); + + // + // Set the timer trigger and pattern length. + // + am_hal_ctimer_config_trigger(psCfg->ui32CTimerModule, + psCfg->ui32CTimerSegment, + ( + (MCLK_UI64PATTERNLEN << CTIMER_AUX0_TMRA0LMT_Pos) | + (CTIMER_AUX0_TMRB0TRIG_DIS << CTIMER_AUX0_TMRA0TRIG_Pos) + ) + ); + + // + // Configure timer output pin. + // + am_hal_ctimer_output_config(psCfg->ui32CTimerModule, + psCfg->ui32CTimerSegment, + psCfg->ui32CTimerOutputPin, + AM_HAL_CTIMER_OUTPUT_NORMAL, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA); + + // + // Start the timer. + // + am_hal_ctimer_start(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment); + +} + +//***************************************************************************** +// +//! @brief Disable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function disable CTimer to stop MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_disable(hm01b0_cfg_t *psCfg) +{ + // + // Stop the timer. + // + am_hal_ctimer_stop(psCfg->ui32CTimerModule, psCfg->ui32CTimerSegment); + am_hal_gpio_pinconfig(psCfg->ui32CTimerOutputPin, g_AM_HAL_GPIO_DISABLE); + +} + +//***************************************************************************** +// +//! @brief Initialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function initializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_if(hm01b0_cfg_t *psCfg) +{ + void *pIOMHandle = NULL; + + if ( psCfg->ui32IOMModule > AM_REG_IOM_NUM_MODULES ) + { + return HM01B0_ERR_I2C; + } + + // + // Enable fault detection. + // +#if AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_control(AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE, 0); +#else // AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_fault_capture_enable(); +#endif // AM_APOLLO3_MCUCTRL + + // + // Initialize the IOM instance. + // Enable power to the IOM instance. + // Configure the IOM for Serial operation during initialization. + // Enable the IOM. + // + if (am_hal_iom_initialize(psCfg->ui32IOMModule, &pIOMHandle) || + am_hal_iom_power_ctrl(pIOMHandle, AM_HAL_SYSCTRL_WAKE, false) || + am_hal_iom_configure(pIOMHandle, &(psCfg->sIOMCfg)) || + am_hal_iom_enable(pIOMHandle)) + { + return HM01B0_ERR_I2C; + } + else + { + // + // Configure the IOM pins. + // + am_bsp_iom_pins_enable(psCfg->ui32IOMModule, psCfg->eIOMMode); + + psCfg->pIOMHandle = pIOMHandle; + } + + // initialize pins for camera parallel interface. + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD7); + + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD7); + + am_hal_gpio_fast_pinconfig((uint64_t)0x1 << psCfg->ui8PinD0 | + (uint64_t)0x1 << psCfg->ui8PinD1 | + (uint64_t)0x1 << psCfg->ui8PinD2 | + (uint64_t)0x1 << psCfg->ui8PinD3 | + (uint64_t)0x1 << psCfg->ui8PinD4 | + (uint64_t)0x1 << psCfg->ui8PinD5 | + (uint64_t)0x1 << psCfg->ui8PinD6 | + (uint64_t)0x1 << psCfg->ui8PinD7, + g_AM_HAL_GPIO_INPUT, 0); + + am_hal_gpio_pinconfig(psCfg->ui8PinVSYNC, g_AM_HAL_GPIO_INPUT); + am_hal_gpio_pinconfig(psCfg->ui8PinHSYNC, g_AM_HAL_GPIO_INPUT); + am_hal_gpio_pinconfig(psCfg->ui8PinPCLK, g_AM_HAL_GPIO_INPUT); + + am_hal_gpio_pinconfig(psCfg->ui8PinTrig, g_AM_HAL_GPIO_OUTPUT); + + am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_AM_HAL_GPIO_DISABLE); + // am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_HM01B0_pin_int); + // am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(psCfg->ui8PinInt)); + // am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(psCfg->ui8PinInt)); + // NVIC_EnableIRQ(GPIO_IRQn); + + return HM01B0_ERR_OK; +} + +//***************************************************************************** +// +//! @brief Deinitialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function deinitializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_deinit_if(hm01b0_cfg_t *psCfg) +{ + am_hal_iom_disable(psCfg->pIOMHandle); + am_hal_iom_uninitialize(psCfg->pIOMHandle); + + am_hal_gpio_pinconfig(psCfg->ui8PinSCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinSDA, g_AM_HAL_GPIO_DISABLE); + + // initialize pins for camera parallel interface. + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_disable(psCfg->ui8PinD7); + + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD0); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD1); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD2); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD3); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD4); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD5); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD6); + am_hal_gpio_fastgpio_clr(psCfg->ui8PinD7); + + am_hal_gpio_pinconfig(psCfg->ui8PinVSYNC, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinHSYNC, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinPCLK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinTrig, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(psCfg->ui8PinInt, g_AM_HAL_GPIO_DISABLE); + + + return HM01B0_ERR_OK; +} + +//***************************************************************************** +// +//! @brief Get HM01B0 Model ID +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui16MID - Pointer to buffer for the read back model ID. +//! +//! This function reads back HM01B0 model ID. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_modelid(hm01b0_cfg_t *psCfg, uint16_t *pui16MID) +{ + uint8_t ui8Data[1]; + uint32_t ui32Err; + + *pui16MID = 0x0000; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODEL_ID_H, ui8Data, sizeof(ui8Data)); + if (ui32Err == HM01B0_ERR_OK) + { + *pui16MID |= (ui8Data[0] << 8); + } + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODEL_ID_L, ui8Data, sizeof(ui8Data)); + if (ui32Err == HM01B0_ERR_OK) + { + *pui16MID |= ui8Data[0]; + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Initialize HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScript - Pointer to HM01B0 initialization script. +//! @param ui32ScriptCmdNum - No. of commands in HM01B0 initialization script. +//! +//! This function initilizes HM01B0 with a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_system(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum) +{ + return hm01b0_load_script(psCfg, psScript, ui32ScriptCmdNum); +} + +//***************************************************************************** +// +//! @brief Set HM01B0 in the walking 1s test mode +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_test_walking1s(hm01b0_cfg_t *psCfg) +{ + uint32_t ui32ScriptCmdNum = sizeof(sHM01b0TestModeScript_Walking1s) / sizeof(hm_script_t); + hm_script_t *psScript = (hm_script_t *)sHM01b0TestModeScript_Walking1s; + + return hm01b0_load_script(psCfg, psScript, ui32ScriptCmdNum); +} + +//***************************************************************************** +// +//! @brief Check the data read from HM01B0 in the walking 1s test mode +//! +//! @param pui8Buffer - Pointer to data buffer. +//! @param ui32BufferLen - Buffer length +//! @param ui32PrintCnt - Number of mismatched data to be printed out +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +void hm01b0_test_walking1s_check_data_sanity(uint8_t *pui8Buffer, uint32_t ui32BufferLen, uint32_t ui32PrintCnt) +{ + uint8_t ui8ByteData = *pui8Buffer; + uint32_t ui32MismatchCnt = 0x00; + + for (uint32_t ui32Idx = 0; ui32Idx < ui32BufferLen; ui32Idx++) + { + if (*(pui8Buffer + ui32Idx) != ui8ByteData) + { + if (ui32PrintCnt) + { + am_util_stdio_printf("[0x%08X] actual 0x%02X expected 0x%02X\n", ui32Idx, *(pui8Buffer + ui32Idx), ui8ByteData); + am_util_delay_ms(1); + ui32PrintCnt--; + } + ui32MismatchCnt++; + } + + if (ui8ByteData) + ui8ByteData = ui8ByteData << 1; + else + ui8ByteData = 0x01; + } + + am_util_stdio_printf("Mismatch Rate %d/%d\n", ui32MismatchCnt, ui32BufferLen); + +} + +//***************************************************************************** +// +//! @brief Software reset HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function resets HM01B0 by issuing a reset command. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_reset_sw(hm01b0_cfg_t *psCfg) +{ + uint8_t ui8Data[1] = {0x00}; + return hm01b0_write_reg(psCfg, HM01B0_REG_SW_RESET, ui8Data, sizeof(ui8Data)); +} + +//***************************************************************************** +// +//! @brief Get current HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Mode - Pointer to buffer +//! - for the read back operation mode to be put into +//! +//! This function get HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_mode(hm01b0_cfg_t *psCfg, uint8_t *pui8Mode) +{ + uint8_t ui8Data[1] = {0x01}; + uint32_t ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_MODE_SELECT, ui8Data, sizeof(ui8Data)); + + *pui8Mode = ui8Data[0]; + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Set HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8Mode - Operation mode. One of: +//! HM01B0_REG_MODE_SELECT_STANDBY +//! HM01B0_REG_MODE_SELECT_STREAMING +//! HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES +//! HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER +//! @param ui8FrameCnt - Frame count for HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES. +//! - Discarded if other modes. +//! +//! This function set HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mode(hm01b0_cfg_t *psCfg, uint8_t ui8Mode, uint8_t ui8FrameCnt) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + + if (ui8Mode == HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES) + { + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_PMU_PROGRAMMABLE_FRAMECNT, &ui8FrameCnt, sizeof(ui8FrameCnt)); + } + + if(ui32Err == HM01B0_ERR_OK) + { + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_MODE_SELECT, &ui8Mode, sizeof(ui8Mode)); + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Activate the updated settings to HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! Some settings updated to HM01B0 will only be affected after calling this function +//! 1. AE settings +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cmd_update(hm01b0_cfg_t *psCfg) +{ + uint8_t ui8Data = HM01B0_REG_GRP_PARAM_HOLD_HOLD; + + return hm01b0_write_reg(psCfg, HM01B0_REG_GRP_PARAM_HOLD, &ui8Data, sizeof(ui8Data)); +} + +//***************************************************************************** +// +//! @brief Get HM01B0 AE convergance +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psAECfg - Pointer to the structure hm01b0_ae_cfg_t. +//! +//! This function checks if AE is converged or not and returns ui32Err accordingly. +//! If caller needs detailed AE settings, psAECfg has to be non NULL. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_ae(hm01b0_cfg_t *psCfg, hm01b0_ae_cfg_t *psAECfg) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8AETargetMean; + uint8_t ui8AEMinMean; + uint8_t ui8AEMean; + uint8_t ui8ConvergeInTh; + uint8_t ui8ConvergeOutTh; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_AE_TARGET_MEAN, &ui8AETargetMean, sizeof(ui8AETargetMean)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_AE_MIN_MEAN, &ui8AEMinMean, sizeof(ui8AEMinMean)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_CONVERGE_IN_TH, &ui8ConvergeInTh, sizeof(ui8ConvergeInTh)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_CONVERGE_OUT_TH, &ui8ConvergeOutTh, sizeof(ui8ConvergeOutTh)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, 0x2020, &ui8AEMean, sizeof(ui8AEMean)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + if ((ui8AEMean < (ui8AETargetMean - ui8ConvergeInTh)) || (ui8AEMean > (ui8AETargetMean + ui8ConvergeInTh))) + ui32Err = HM01B0_ERR_AE_NOT_CONVERGED; + + if (psAECfg) + { + psAECfg->ui8AETargetMean = ui8AETargetMean; + psAECfg->ui8AEMinMean = ui8AEMinMean; + psAECfg->ui8ConvergeInTh = ui8ConvergeInTh; + psAECfg->ui8ConvergeOutTh = ui8ConvergeOutTh; + psAECfg->ui8AEMean = ui8AEMean; + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief AE calibration. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8CalFrames - Frame counts for calibratoin. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function lets HM01B0 AE settled as much as possible within a given frame counts. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cal_ae(hm01b0_cfg_t *psCfg, uint8_t ui8CalFrames, uint8_t *pui8Buffer, uint32_t ui32BufferLen) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + hm01b0_ae_cfg_t sAECfg; + + am_util_stdio_printf("[%s] +\n", __func__); + + hm01b0_set_mode(psCfg, HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES, ui8CalFrames); + + for (uint8_t i = 0; i < ui8CalFrames; i++) + { + + hm01b0_blocking_read_oneframe(psCfg, pui8Buffer, ui32BufferLen); + + ui32Err = hm01b0_get_ae(psCfg, &sAECfg); + + am_util_stdio_printf("AE Calibration(0x%02X) TargetMean 0x%02X, ConvergeInTh 0x%02X, AEMean 0x%02X\n", \ + ui32Err, sAECfg.ui8AETargetMean, sAECfg.ui8ConvergeInTh, sAECfg.ui8AEMean); + + // if AE calibration is done in ui8CalFrames, just exit to save some time. + if (ui32Err == HM01B0_ERR_OK) + break; + } + + hm01b0_set_mode(psCfg, HM01B0_REG_MODE_SELECT_STANDBY, 0); + + am_util_stdio_printf("[%s] -\n", __func__); + + return ui32Err; +} + + +//***************************************************************************** +// +//! @brief Save HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function saves HM01B0 exposure gain settings. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_save_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8IntegrationH; + uint8_t ui8IntegrationL; + uint8_t ui8AGain; + uint8_t ui8DGain_H; + uint8_t ui8DGain_L; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_INTEGRATION_H, &ui8IntegrationH, sizeof(ui8IntegrationH)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_INTEGRATION_L, &ui8IntegrationL, sizeof(ui8IntegrationL)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8AGain, sizeof(ui8AGain)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8DGain_H, sizeof(ui8DGain_H)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8DGain_L, sizeof(ui8DGain_L)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + if (psExpoGainCtrl) + { + psExpoGainCtrl->ui8IntegrationH = ui8IntegrationH; + psExpoGainCtrl->ui8IntegrationL = ui8IntegrationL; + psExpoGainCtrl->ui8AGain = ui8AGain; + psExpoGainCtrl->ui8DGain_H = ui8DGain_H; + psExpoGainCtrl->ui8DGain_L = ui8DGain_L; + } + + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Restore HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function restores HM01B0 exposure gain settings. The call flow shall be +//! hm01b0_restore_exposure_gains() -> hm01b0_cmd_update() -> hm01b0_set_mode() +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_restore_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8Tmp; + + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_INTEGRATION_H, &(psExpoGainCtrl->ui8IntegrationH), sizeof(psExpoGainCtrl->ui8IntegrationH)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_INTEGRATION_L, &(psExpoGainCtrl->ui8IntegrationL), sizeof(psExpoGainCtrl->ui8IntegrationL)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8Tmp, sizeof(ui8Tmp)); + ui8Tmp = (ui8Tmp & ~(0x7 << 4)) | (psExpoGainCtrl->ui8AGain & (0x7 << 4)); + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_ANALOG_GAIN, &ui8Tmp, sizeof(ui8Tmp)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8Tmp, sizeof(ui8Tmp)); + ui8Tmp = (ui8Tmp & ~(0x3 << 0)) | (psExpoGainCtrl->ui8DGain_H & (0x3 << 0)); + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_H, &ui8Tmp, sizeof(ui8Tmp)); + if (ui32Err != HM01B0_ERR_OK) return ui32Err; + + ui32Err = hm01b0_read_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8Tmp, sizeof(ui8Tmp)); + ui8Tmp = (ui8Tmp & ~(0x3F << 2)) | (psExpoGainCtrl->ui8DGain_L & (0x3F << 2)); + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_DIGITAL_GAIN_L, &ui8Tmp, sizeof(ui8Tmp)); + + return ui32Err; + +} + +//***************************************************************************** +// +//! @brief Hardware trigger HM01B0 to stream. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bTrigger - True to start streaming +//! - False to stop streaming +//! +//! This function triggers HM01B0 to stream by toggling the TRIG pin. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_hardware_trigger_streaming(hm01b0_cfg_t *psCfg, bool bTrigger) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint8_t ui8Mode; + + ui32Err = hm01b0_get_mode(psCfg, &ui8Mode); + + if (ui32Err != HM01B0_ERR_OK) + goto end; + + if (ui8Mode != HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER) + { + ui32Err = HM01B0_ERR_MODE; + goto end; + } + + if (bTrigger) + { + am_hal_gpio_output_set(psCfg->ui8PinTrig); + } + else + { + am_hal_gpio_output_clear(psCfg->ui8PinTrig); + } + +end: + return ui32Err; +} + +//***************************************************************************** +// +//! @brief Set HM01B0 mirror mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bHmirror - Horizontal mirror +//! @param bVmirror - Vertical mirror +//! +//! This function set HM01B0 mirror mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mirror(hm01b0_cfg_t *psCfg, bool bHmirror, bool bVmirror) +{ + uint8_t ui8Data = 0x00; + uint32_t ui32Err = HM01B0_ERR_OK; + + if (bHmirror) + { + ui8Data |= HM01B0_REG_IMAGE_ORIENTATION_HMIRROR; + } + + if (bVmirror) + { + ui8Data |= HM01B0_REG_IMAGE_ORIENTATION_VMIRROR; + } + + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_IMAGE_ORIENTATION, &ui8Data, sizeof(ui8Data)); + + if (ui32Err == HM01B0_ERR_OK) + { + ui8Data = HM01B0_REG_GRP_PARAM_HOLD_HOLD; + ui32Err = hm01b0_write_reg(psCfg, HM01B0_REG_GRP_PARAM_HOLD, &ui8Data, sizeof(ui8Data)); + } + + return ui32Err; + +} + +//***************************************************************************** +// +//! @brief Read data of one frame from HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function read data of one frame from HM01B0. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_blocking_read_oneframe(hm01b0_cfg_t *psCfg, uint8_t *pui8Buffer, uint32_t ui32BufferLen) +{ + uint32_t ui32Err = HM01B0_ERR_OK; + uint32_t ui32Idx = 0x00; + + am_util_stdio_printf("[%s] +\n", __func__); + + uint32_t ui32HsyncCnt = 0x00; + + while((ui32HsyncCnt < HM01B0_PIXEL_Y_NUM)) + { + while (0x00 == read_hsync()); + + // read one row + while(read_hsync()) + { + while(0x00 == read_pclk()); + + *(pui8Buffer + ui32Idx++) = read_byte(); + + if (ui32Idx == ui32BufferLen) { + goto end; + } + + while(read_pclk()); + } + + ui32HsyncCnt++; + } + +end: + am_util_stdio_printf("[%s] - Byte Counts %d\n", __func__, ui32Idx); + + return ui32Err; + +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.h new file mode 100644 index 0000000000..4d1dd97e4b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0.h @@ -0,0 +1,501 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +//***************************************************************************** +// +//! @file HM01B0.h +// +//***************************************************************************** +#ifndef HM01B0_H +#define HM01B0_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "am_mcu_apollo.h" +#include "am_bsp.h" +#include "am_util.h" + +#define HM01B0_DRV_VERSION (0) +#define HM01B0_DRV_SUBVERSION (5) + +#define HM01B0_DEFAULT_ADDRESS (0x24) + +#define HM01B0_PIXEL_X_NUM (324) +#define HM01B0_PIXEL_Y_NUM (244) + +#define HM01B0_REG_MODEL_ID_H (0x0000) +#define HM01B0_REG_MODEL_ID_L (0x0001) +#define HM01B0_REG_SILICON_REV (0x0002) +#define HM01B0_REG_FRAME_COUNT (0x0005) +#define HM01B0_REG_PIXEL_ORDER (0x0006) + +#define HM01B0_REG_MODE_SELECT (0x0100) +#define HM01B0_REG_IMAGE_ORIENTATION (0x0101) +#define HM01B0_REG_SW_RESET (0x0103) +#define HM01B0_REG_GRP_PARAM_HOLD (0x0104) + +#define HM01B0_REG_INTEGRATION_H (0x0202) +#define HM01B0_REG_INTEGRATION_L (0x0203) +#define HM01B0_REG_ANALOG_GAIN (0x0205) +#define HM01B0_REG_DIGITAL_GAIN_H (0x020E) +#define HM01B0_REG_DIGITAL_GAIN_L (0x020F) + +#define HM01B0_REG_AE_TARGET_MEAN (0x2101) +#define HM01B0_REG_AE_MIN_MEAN (0x2102) +#define HM01B0_REG_CONVERGE_IN_TH (0x2103) +#define HM01B0_REG_CONVERGE_OUT_TH (0x2104) + + +#define HM01B0_REG_I2C_ID_SEL (0x3400) +#define HM01B0_REG_I2C_ID_REG (0x3401) + +#define HM01B0_REG_PMU_PROGRAMMABLE_FRAMECNT (0x3020) + +// #define HM01B0_REG_MODE_SELECT (0x0100) +#define HM01B0_REG_MODE_SELECT_STANDBY (0x00) +#define HM01B0_REG_MODE_SELECT_STREAMING (0x01) +#define HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES (0x03) +#define HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER (0x05) + +// #define HM01B0_REG_IMAGE_ORIENTATION (0x0101) +#define HM01B0_REG_IMAGE_ORIENTATION_DEFAULT (0x00) +#define HM01B0_REG_IMAGE_ORIENTATION_HMIRROR (0x01) +#define HM01B0_REG_IMAGE_ORIENTATION_VMIRROR (0x02) +#define HM01B0_REG_IMAGE_ORIENTATION_HVMIRROR (HM01B0_REG_IMAGE_ORIENTATION_HMIRROR | HM01B0_REG_IMAGE_ORIENTATION_HVMIRROR) + +// #define HM01B0_REG_GRP_PARAM_HOLD (0x0104) +#define HM01B0_REG_GRP_PARAM_HOLD_CONSUME (0x00) +#define HM01B0_REG_GRP_PARAM_HOLD_HOLD (0x01) + +enum +{ + HM01B0_ERR_OK = 0x00, + HM01B0_ERR_I2C, + HM01B0_ERR_MODE, + HM01B0_ERR_AE_NOT_CONVERGED, +}; + +typedef struct +{ + uint16_t ui16Reg; + uint8_t ui8Val; +} hm_script_t; + +typedef struct +{ + uint16_t ui16SlvAddr; + am_hal_iom_mode_e eIOMMode; + uint32_t ui32IOMModule; + am_hal_iom_config_t sIOMCfg; + void *pIOMHandle; + + uint32_t ui32CTimerModule; + uint32_t ui32CTimerSegment; + uint32_t ui32CTimerOutputPin; + + uint8_t ui8PinSCL; + uint8_t ui8PinSDA; + uint8_t ui8PinD0; + uint8_t ui8PinD1; + uint8_t ui8PinD2; + uint8_t ui8PinD3; + uint8_t ui8PinD4; + uint8_t ui8PinD5; + uint8_t ui8PinD6; + uint8_t ui8PinD7; + uint8_t ui8PinVSYNC; + uint8_t ui8PinHSYNC; + uint8_t ui8PinPCLK; + + uint8_t ui8PinTrig; + uint8_t ui8PinInt; + void (*pfnGpioIsr)(void); +} hm01b0_cfg_t; + +typedef struct +{ + uint8_t ui8AETargetMean; + uint8_t ui8AEMinMean; + uint8_t ui8ConvergeInTh; + uint8_t ui8ConvergeOutTh; + uint8_t ui8AEMean; +} hm01b0_ae_cfg_t; + +typedef struct +{ + uint8_t ui8IntegrationH; + uint8_t ui8IntegrationL; + uint8_t ui8AGain; + uint8_t ui8DGain_H; + uint8_t ui8DGain_L; +} hm01b0_snr_expo_gain_ctrl_t; + +//***************************************************************************** +// +//! @brief Write HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the data to be written. +//! @param ui32NumBytes - Length of the data in bytes to be written. +//! +//! This function writes value to HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_write_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes); + +//***************************************************************************** +// +//! @brief Read HM01B0 registers +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui16Reg - Register address. +//! @param pui8Value - Pointer to the buffer for read data to be put into. +//! @param ui32NumBytes - Length of the data to be read. +//! +//! This function reads value from HM01B0 registers. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_read_reg(hm01b0_cfg_t *psCfg, \ + uint16_t ui16Reg, uint8_t *pui8Value, uint32_t ui32NumBytes); + +//***************************************************************************** +// +//! @brief Load HM01B0 a given script +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScrip - Pointer to the script to be loaded. +//! @param ui32ScriptCmdNum - Number of entries in a given script. +//! +//! This function loads HM01B0 a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_load_script(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum); + +//***************************************************************************** +// +//! @brief Power up HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_up(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Power down HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function powers up HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_power_down(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Enable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function utilizes CTimer to generate MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_enable(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Disable MCLK +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function disable CTimer to stop MCLK for HM01B0. +//! +//! @return none. +// +//***************************************************************************** +void hm01b0_mclk_disable(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Initialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function initializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_if(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Deinitialize interfaces +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function deinitializes interfaces. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_deinit_if(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Get HM01B0 Model ID +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui16MID - Pointer to buffer for the read back model ID. +//! +//! This function reads back HM01B0 model ID. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_modelid(hm01b0_cfg_t *psCfg, uint16_t *pui16MID); + +//***************************************************************************** +// +//! @brief Initialize HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psScript - Pointer to HM01B0 initialization script. +//! @param ui32ScriptCmdNum - No. of commands in HM01B0 initialization script. +//! +//! This function initilizes HM01B0 with a given script. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_init_system(hm01b0_cfg_t *psCfg, hm_script_t *psScript, uint32_t ui32ScriptCmdNum); + +//***************************************************************************** +// +//! @brief Set HM01B0 in the walking 1s test mode +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_test_walking1s(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Check the data read from HM01B0 in the walking 1s test mode +//! +//! @param pui8Buffer - Pointer to data buffer. +//! @param ui32BufferLen - Buffer length +//! @param ui32PrintCnt - Number of mismatched data to be printed out +//! +//! This function sets HM01B0 in the walking 1s test mode. +//! +//! @return Error code. +// +//***************************************************************************** +void hm01b0_test_walking1s_check_data_sanity(uint8_t *pui8Buffer, uint32_t ui32BufferLen, uint32_t ui32PrintCnt); + +//***************************************************************************** +// +//! @brief Software reset HM01B0 +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! This function resets HM01B0 by issuing a reset command. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_reset_sw(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Get current HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Mode - Pointer to buffer +//! - for the read back operation mode to be put into +//! +//! This function get HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_mode(hm01b0_cfg_t *psCfg, uint8_t *pui8Mode); + +//***************************************************************************** +// +//! @brief Set HM01B0 operation mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8Mode - Operation mode. One of: +//! HM01B0_REG_MODE_SELECT_STANDBY +//! HM01B0_REG_MODE_SELECT_STREAMING +//! HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES +//! HM01B0_REG_MODE_SELECT_STREAMING_HW_TRIGGER +//! @param framecnt - Frame count for HM01B0_REG_MODE_SELECT_STREAMING_NFRAMES. +//! - Discarded if other modes. +//! +//! This function set HM01B0 operation mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mode(hm01b0_cfg_t *psCfg, uint8_t ui8Mode, uint8_t framecnt); + + +//***************************************************************************** +// +//! @brief Activate the updated settings to HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! +//! Some settings updated to HM01B0 will only be affected after calling this function +//! 1. AE settings +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cmd_update(hm01b0_cfg_t *psCfg); + +//***************************************************************************** +// +//! @brief Get HM01B0 AE settings +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psAECfg - Pointer to the structure hm01b0_ae_cfg_t. +//! +//! This function checks if AE is converged or not and returns ui32Err accordingly. +//! If caller needs detailed AE settings, psAECfg has to be non NULL. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_get_ae(hm01b0_cfg_t *psCfg, hm01b0_ae_cfg_t *psAECfg); + +//***************************************************************************** +// +//! @brief AE calibration. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param ui8CalFrames - Frame counts for calibratoin. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function lets HM01B0 AE settled as much as possible within a given frame counts. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_cal_ae(hm01b0_cfg_t *psCfg, uint8_t ui8CalFrames, uint8_t *pui8Buffer, uint32_t ui32BufferLen); + +//***************************************************************************** +// +//! @brief Save HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function saves HM01B0 exposure gain settings. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_save_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl); + +//***************************************************************************** +// +//! @brief Restore HM01B0 exposure gain settings. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param psExpoGainCtrl - Pointer to the structure hm01b0_snr_expo_gain_ctrl_t +//! +//! This function restores HM01B0 exposure gain settings. The call flow shall be +//! hm01b0_restore_exposure_gains() -> hm01b0_cmd_update() -> hm01b0_set_mode() +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_restore_exposure_gains(hm01b0_cfg_t *psCfg, hm01b0_snr_expo_gain_ctrl_t *psExpoGainCtrl); + +//***************************************************************************** +// +//! @brief Hardware trigger HM01B0 to stream. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bTrigger - True to start streaming +//! - False to stop streaming +//! +//! This function triggers HM01B0 to stream by toggling the TRIG pin. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_hardware_trigger_streaming(hm01b0_cfg_t *psCfg, bool bTrigger); + +//***************************************************************************** +// +//! @brief Set HM01B0 mirror mode. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param bHmirror - Horizontal mirror +//! @param bVmirror - Vertical mirror +//! +//! This function set HM01B0 mirror mode. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_set_mirror(hm01b0_cfg_t *psCfg, bool bHmirror, bool bVmirror); + + +//***************************************************************************** +// +//! @brief Read data of one frame from HM01B0. +//! +//! @param psCfg - Pointer to HM01B0 configuration structure. +//! @param pui8Buffer - Pointer to the frame buffer. +//! @param ui32BufferLen - Framebuffer size. +//! +//! This function read data of one frame from HM01B0. +//! +//! @return Error code. +// +//***************************************************************************** +uint32_t hm01b0_blocking_read_oneframe(hm01b0_cfg_t *psCfg, \ + uint8_t *pui8Buffer, uint32_t ui32BufferLen); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CTIMER_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h new file mode 100644 index 0000000000..0b40f624ed --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_RAW8_QVGA_8bits_lsb_5fps.h @@ -0,0 +1,243 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +#include "HM01B0.h" + +const hm_script_t sHM01B0InitScript[] = +{ +// ;************************************************************************* +// ; Sensor: HM01B0 +// ; I2C ID: 24 +// ; Resolution: 324x244 +// ; Lens: +// ; Flicker: +// ; Frequency: +// ; Description: AE control enable +// ; 8-bit mode, LSB first +// ; +// ; +// ; Note: +// ; +// ; $Revision: 1338 $ +// ; $Date:: 2017-04-11 15:43:45 +0800#$ +// ;************************************************************************* +// +// // --------------------------------------------------- +// // HUB system initial +// // --------------------------------------------------- +// W 20 8A04 01 2 1 +// W 20 8A00 22 2 1 +// W 20 8A01 00 2 1 +// W 20 8A02 01 2 1 +// W 20 0035 93 2 1 ; [3]&[1] hub616 20bits in, [5:4]=1 mclk=48/2=24mhz +// W 20 0036 00 2 1 +// W 20 0011 09 2 1 +// W 20 0012 B6 2 1 +// W 20 0014 08 2 1 +// W 20 0015 98 2 1 +// ;W 20 0130 16 2 1 ; 3m soc, signal buffer control +// ;W 20 0100 44 2 1 ; [6] hub616 20bits in +// W 20 0100 04 2 1 ; [6] hub616 20bits in +// W 20 0121 01 2 1 ; [0] Q1 Intf enable, [1]:4bit mode, [2] msb first, [3] serial mode +// W 20 0150 00 2 1 ; +// W 20 0150 04 2 1 ; +// +// +// //--------------------------------------------------- +// // Initial +// //--------------------------------------------------- +// W 24 0103 00 2 1 ; software reset-> was 0x22 + {0x0103, 0x00,}, +// W 24 0100 00 2 1; power up + {0x0100, 0x00,}, +// +// +// +// //--------------------------------------------------- +// // Analog +// //--------------------------------------------------- +// L HM01B0_analog_setting.txt + {0x1003, 0x08,}, + {0x1007, 0x08,}, + {0x3044, 0x0A,}, + {0x3045, 0x00,}, + {0x3047, 0x0A,}, + {0x3050, 0xC0,}, + {0x3051, 0x42,}, + {0x3052, 0x50,}, + {0x3053, 0x00,}, + {0x3054, 0x03,}, + {0x3055, 0xF7,}, + {0x3056, 0xF8,}, + {0x3057, 0x29,}, + {0x3058, 0x1F,}, + {0x3059, 0x1E,}, + {0x3064, 0x00,}, + {0x3065, 0x04,}, +// +// +// //--------------------------------------------------- +// // Digital function +// //--------------------------------------------------- +// +// // BLC +// W 24 1000 43 2 1 ; BLC_on, IIR + {0x1000, 0x43,}, +// W 24 1001 40 2 1 ; [6] : BLC dithering en + {0x1001, 0x40,}, +// W 24 1002 32 2 1 ; // blc_darkpixel_thd + {0x1002, 0x32,}, +// +// // Dgain +// W 24 0350 7F 2 1 ; Dgain Control + {0x0350, 0x7F,}, +// +// // BLI +// W 24 1006 01 2 1 ; [0] : bli enable + {0x1006, 0x01,}, +// +// // DPC +// W 24 1008 00 2 1 ; [2:0] : DPC option 0: DPC off 1 : mono 3 : bayer1 5 : bayer2 + {0x1008, 0x00,}, +// W 24 1009 A0 2 1 ; cluster hot pixel th + {0x1009, 0xA0,}, +// W 24 100A 60 2 1 ; cluster cold pixel th + {0x100A, 0x60,}, +// W 24 100B 90 2 1 ; single hot pixel th + {0x100B, 0x90,}, +// W 24 100C 40 2 1 ; single cold pixel th + {0x100C, 0x40,}, +// // +// advance VSYNC by 1 row + {0x3022, 0x01,}, +// W 24 1012 00 2 1 ; Sync. enable VSYNC shift + {0x1012, 0x01,}, + +// +// // ROI Statistic +// W 24 2000 07 2 1 ; [0] : AE stat en [1] : MD LROI stat en [2] : MD GROI stat en [3] : RGB stat ratio en [4] : IIR selection (1 -> 16, 0 -> 8) + {0x2000, 0x07,}, +// W 24 2003 00 2 1 ; MD GROI 0 y start HB + {0x2003, 0x00,}, +// W 24 2004 1C 2 1 ; MD GROI 0 y start LB + {0x2004, 0x1C,}, +// W 24 2007 00 2 1 ; MD GROI 1 y start HB + {0x2007, 0x00,}, +// W 24 2008 58 2 1 ; MD GROI 1 y start LB + {0x2008, 0x58,}, +// W 24 200B 00 2 1 ; MD GROI 2 y start HB + {0x200B, 0x00,}, +// W 24 200C 7A 2 1 ; MD GROI 2 y start LB + {0x200C, 0x7A,}, +// W 24 200F 00 2 1 ; MD GROI 3 y start HB + {0x200F, 0x00,}, +// W 24 2010 B8 2 1 ; MD GROI 3 y start LB + {0x2010, 0xB8,}, +// +// W 24 2013 00 2 1 ; MD LRIO y start HB + {0x2013, 0x00,}, +// W 24 2014 58 2 1 ; MD LROI y start LB + {0x2014, 0x58,}, +// W 24 2017 00 2 1 ; MD LROI y end HB + {0x2017, 0x00,}, +// W 24 2018 9B 2 1 ; MD LROI y end LB + {0x2018, 0x9B,}, +// +// // AE +// W 24 2100 01 2 1 ; [0]: AE control enable + {0x2100, 0x01,}, +// W 24 2104 07 2 1 ; converge out th + {0x2104, 0x07,}, +// W 24 2105 0C 2 1 ; max INTG Hb + {0x2105, 0x0C,}, +// W 24 2106 78 2 1 ; max INTG Lb + {0x2106, 0x78,}, +// W 24 2108 03 2 1 ; max AGain in full + {0x2108, 0x03,}, +// W 24 2109 03 2 1 ; max AGain in bin2 + {0x2109, 0x03,}, +// W 24 210B 80 2 1 ; max DGain + {0x210B, 0x80,}, +// W 24 210F 00 2 1 ; FS 60Hz Hb + {0x210F, 0x00,}, +// W 24 2110 85 2 1 ; FS 60Hz Lb + {0x2110, 0x85,}, +// W 24 2111 00 2 1 ; Fs 50Hz Hb + {0x2111, 0x00,}, +// W 24 2112 A0 2 1 ; FS 50Hz Lb + {0x2112, 0xA0,}, +// +// +// // MD +// W 24 2150 03 2 1 ; [0] : MD LROI en [1] : MD GROI en + {0x2150, 0x03,}, +// +// +// //--------------------------------------------------- +// // frame rate : 5 FPS +// //--------------------------------------------------- +// W 24 0340 0C 2 1 ; smia frame length Hb + {0x0340, 0x0C,}, +// W 24 0341 7A 2 1 ; smia frame length Lb 3192 + {0x0341, 0x7A,}, +// +// W 24 0342 01 2 1 ; smia line length Hb + {0x0342, 0x01,}, +// W 24 0343 77 2 1 ; smia line length Lb 375 + {0x0343, 0x77,}, +// +// //--------------------------------------------------- +// // Resolution : QVGA 324x244 +// //--------------------------------------------------- +// W 24 3010 01 2 1 ; [0] : window mode 0 : full frame 324x324 1 : QVGA + {0x3010, 0x01,}, +// +// +// W 24 0383 01 2 1 ; + {0x0383, 0x01,}, +// W 24 0387 01 2 1 ; + {0x0387, 0x01,}, +// W 24 0390 00 2 1 ; + {0x0390, 0x00,}, +// +// //--------------------------------------------------- +// // bit width Selection +// //--------------------------------------------------- +// W 24 3011 70 2 1 ; [0] : 6 bit mode enable + {0x3011, 0x70,}, +// +// +// W 24 3059 02 2 1 ; [7]: Self OSC En, [6]: 4bit mode, [5]: serial mode, [4:0]: keep value as 0x02 + {0x3059, 0x02,}, +// W 24 3060 01 2 1 ; [5]: gated_clock, [4]: msb first, + {0x3060, 0x20,}, +// ; [3:2]: vt_reg_div -> div by 4/8/1/2 +// ; [1;0]: vt_sys_div -> div by 8/4/2/1 +// +// + {0x0101, 0x01,}, +// //--------------------------------------------------- +// // CMU update +// //--------------------------------------------------- +// +// W 24 0104 01 2 1 ; was 0100 + {0x0104, 0x01,}, +// +// +// +// //--------------------------------------------------- +// // Turn on rolling shutter +// //--------------------------------------------------- +// W 24 0100 01 2 1 ; was 0005 ; mode_select 00 : standby - wait fir I2C SW trigger 01 : streaming 03 : output "N" frame, then enter standby 04 : standby - wait for HW trigger (level), then continuous video out til HW TRIG goes off 06 : standby - wait for HW trigger (edge), then output "N" frames then enter standby + {0x0100, 0x00,}, +// +// ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_Walking1s_01.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_Walking1s_01.h new file mode 100644 index 0000000000..13de4596d0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/HM01B0_Walking1s_01.h @@ -0,0 +1,24 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +#include "HM01B0.h" + +const hm_script_t sHM01b0TestModeScript_Walking1s[] = +{ + {0x2100, 0x00,}, //W 24 2100 00 2 1 ; AE + {0x1000, 0x00,}, //W 24 1000 00 2 1 ; BLC + {0x1008, 0x00,}, //W 24 1008 00 2 1 ; DPC + {0x0205, 0x00,}, //W 24 0205 00 2 1 ; AGain + {0x020E, 0x01,}, //W 24 020E 01 2 1 ; DGain + {0x020F, 0x00,}, //W 24 020F 00 2 1 ; DGain + {0x0601, 0x11,}, //W 24 0601 11 2 1 ; Test pattern + {0x0104, 0x01,}, //W 24 0104 01 2 1 ; +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/platform.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/platform.h new file mode 100644 index 0000000000..f906e4a213 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_hm01b0/hm01b0/platform.h @@ -0,0 +1,60 @@ +/* +SPDX-License-Identifier: Beerware + +"THE BEER-WARE LICENSE" (Revision 42): + added this file. As long as you retain this notice you +can do whatever you want with this stuff. If we meet some day, and you think +this stuff is worth it, you can buy me a beer in return + +Owen Lyke +*/ + +#ifndef HM01B0_PLATFORM_H +#define HM01B0_PLATFORM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define HM01B0_PIN_D0 AM_BSP_GPIO_CAMERA_HM01B0_D0 +#define HM01B0_PIN_D1 AM_BSP_GPIO_CAMERA_HM01B0_D1 +#define HM01B0_PIN_D2 AM_BSP_GPIO_CAMERA_HM01B0_D2 +#define HM01B0_PIN_D3 AM_BSP_GPIO_CAMERA_HM01B0_D3 +#define HM01B0_PIN_D4 AM_BSP_GPIO_CAMERA_HM01B0_D4 +#define HM01B0_PIN_D5 AM_BSP_GPIO_CAMERA_HM01B0_D5 +#define HM01B0_PIN_D6 AM_BSP_GPIO_CAMERA_HM01B0_D6 +#define HM01B0_PIN_D7 AM_BSP_GPIO_CAMERA_HM01B0_D7 +#define HM01B0_PIN_VSYNC AM_BSP_GPIO_CAMERA_HM01B0_VSYNC +#define HM01B0_PIN_HSYNC AM_BSP_GPIO_CAMERA_HM01B0_HSYNC +#define HM01B0_PIN_PCLK AM_BSP_GPIO_CAMERA_HM01B0_PCLK +#define HM01B0_PIN_SCL AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN +#define HM01B0_PIN_SDA AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN + + +// Some boards do not support TRIG or INT pins +#ifdef AM_BSP_GPIO_CAMERA_HM01B0_TRIG +#define HM01B0_PIN_TRIG AM_BSP_GPIO_CAMERA_HM01B0_TRIG +#endif // AM_BSP_GPIO_CAMERA_HM01B0_TRIG + +#ifdef AM_BSP_GPIO_CAMERA_HM01B0_INT +#define HM01B0_PIN_INT AM_BSP_GPIO_CAMERA_HM01B0_INT +#endif // AM_BSP_GPIO_CAMERA_HM01B0_INT + + +// Define AP3B's CTIMER and output pin for HM01B0 MCLK generation +#define HM01B0_MCLK_GENERATOR_MOD AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD +#define HM01B0_MCLK_GENERATOR_SEG AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG +#define HM01B0_PIN_MCLK AM_BSP_CAMERA_HM01B0_MCLK_PIN + +// Deifne I2C controller and SCL(pin8)/SDA(pin9) are configured automatically. +#define HM01B0_IOM_MODE AM_HAL_IOM_I2C_MODE +#define HM01B0_IOM_MODULE AM_BSP_CAMERA_HM01B0_I2C_IOM +#define HM01B0_I2C_CLOCK_FREQ AM_HAL_IOM_100KHZ + + +#ifdef __cplusplus +} +#endif + +#endif // HM01B0_PLATFORM_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.c new file mode 100644 index 0000000000..04e3425268 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include "lis2dh12_platform_apollo3.h" + +/* + * @brief Write generic device register (platform dependent) + * + * @param handle customizable argument. In this examples is used in + * order to select the correct sensor bus handler. + * @param reg register to write + * @param bufp pointer to data to write in register reg + * @param len number of consecutive register to write + * + */ +int32_t lis2dh12_write_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len) +{ + uint32_t retVal32 = 0; + lis2dh12_platform_apollo3_if_t* pif = (lis2dh12_platform_apollo3_if_t*)handle; + am_hal_iom_transfer_t iomTransfer = {0}; + + if( bufp == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif->iomHandle == NULL) { return AM_HAL_STATUS_FAIL; } + + // Set up transfer + iomTransfer.uPeerInfo.ui32I2CDevAddr = pif->addCS; + iomTransfer.ui32InstrLen = 1; + iomTransfer.ui32Instr = (reg | 0x80); + iomTransfer.ui32NumBytes = len; + iomTransfer.eDirection = AM_HAL_IOM_TX; + iomTransfer.pui32TxBuffer = (uint32_t*)bufp; + iomTransfer.pui32RxBuffer = NULL; + iomTransfer.bContinue = false; + + if( pif->useSPI ){ + // ToDo: Support SPI w/ CS assertion + } + + // Send the transfer + retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer); + + if( pif->useSPI ){ + // ToDo: Support SPI / CS de-assertion + } + + if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; } + + return 0; +} + +/* + * @brief Read generic device register (platform dependent) + * + * @param handle customizable argument. In this examples is used in + * order to select the correct sensor bus handler. + * @param reg register to read + * @param bufp pointer to buffer that store the data read + * @param len number of consecutive register to read + * + */ +int32_t lis2dh12_read_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len) +{ + uint32_t retVal32 = 0; + lis2dh12_platform_apollo3_if_t* pif = (lis2dh12_platform_apollo3_if_t*)handle; + am_hal_iom_transfer_t iomTransfer = {0}; + + if( bufp == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif == NULL ) { return AM_HAL_STATUS_FAIL; } + if( pif->iomHandle == NULL) { return AM_HAL_STATUS_FAIL; } + + // Set up first transfer + iomTransfer.uPeerInfo.ui32I2CDevAddr = pif->addCS; + iomTransfer.ui32InstrLen = 1; + iomTransfer.ui32Instr = (reg | 0x80); + iomTransfer.ui32NumBytes = 0; + iomTransfer.eDirection = AM_HAL_IOM_TX; + iomTransfer.bContinue = true; + + if( pif->useSPI ){ + // ToDo: Support SPI w/ CS assertion + } + + // Send the first transfer + retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer); + if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; } + + // Change direction, and add the rx buffer + iomTransfer.eDirection = AM_HAL_IOM_RX; + iomTransfer.pui32RxBuffer = (uint32_t*)bufp; + iomTransfer.ui32NumBytes = len; + iomTransfer.bContinue = false; + + // Send the second transfer + retVal32 = am_hal_iom_blocking_transfer(pif->iomHandle, &iomTransfer); + + if( retVal32 != AM_HAL_STATUS_SUCCESS ){ return retVal32; } + + return 0; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.h new file mode 100644 index 0000000000..a1c45df181 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_platform_apollo3.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#ifndef _LIS2DH12_PLATFORM_APOLLO3_H_ +#define _LIS2DH12_PLATFORM_APOLLO3_H_ + +#include "am_mcu_apollo.h" +#include "lis2dh12_reg.h" + +#ifdef __cplusplus + extern "C" { +#endif + +typedef struct _lis2dh12_platform_apollo3_if_t { + void* iomHandle; // IO Master instance + uint8_t addCS; // I2C mode: the 7-bit I2C address (either 0x18 or 0x19 depeding on SA0 pin) + // SPI mode: the Apollo3 pad to use for chip select + bool useSPI; // Set 'true' if using SPI mode, else 'false' +}lis2dh12_platform_apollo3_if_t; + +int32_t lis2dh12_write_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len); +int32_t lis2dh12_read_platform_apollo3(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len); + +#ifdef __cplusplus +} +#endif + +#endif // _LIS2DH12_PLATFORM_APOLLO3_H_ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.c new file mode 100644 index 0000000000..9c87e1d19d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.c @@ -0,0 +1,2399 @@ +/* + ****************************************************************************** + * @file lis2dh12_reg.c + * @author Sensors Software Solution Team + * @brief LIS2DH12 driver file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +// SPDX-License-Identifier: BSD-3-Clause + +#include "lis2dh12_reg.h" + + +/** + * @defgroup LIS2DH12 + * @brief This file provides a set of functions needed to drive the + * lis2dh12 enanced inertial module. + * @{ + * + */ + +/** + * @defgroup LIS2DH12_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_read_reg(lis2dh12_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_write_reg(lis2dh12_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + + /** + * @defgroup LIS2DH12_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float lis2dh12_from_fs2_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 1.0f; +} + +float lis2dh12_from_fs4_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 2.0f; +} + +float lis2dh12_from_fs8_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 4.0f; +} + +float lis2dh12_from_fs16_hr_to_mg(int16_t lsb) +{ + return ( (float)lsb / 16.0f ) * 12.0f; +} + +float lis2dh12_from_lsb_hr_to_celsius(int16_t lsb) +{ + return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f; +} + +float lis2dh12_from_fs2_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 4.0f; +} + +float lis2dh12_from_fs4_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 8.0f; +} + +float lis2dh12_from_fs8_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 16.0f; +} + +float lis2dh12_from_fs16_nm_to_mg(int16_t lsb) +{ + return ( (float)lsb / 64.0f ) * 48.0f; +} + +float lis2dh12_from_lsb_nm_to_celsius(int16_t lsb) +{ + return ( ( (float)lsb / 64.0f ) / 4.0f ) + 25.0f; +} + +float lis2dh12_from_fs2_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 16.0f; +} + +float lis2dh12_from_fs4_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 32.0f; +} + +float lis2dh12_from_fs8_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 64.0f; +} + +float lis2dh12_from_fs16_lp_to_mg(int16_t lsb) +{ + return ( (float)lsb / 256.0f ) * 192.0f; +} + +float lis2dh12_from_lsb_lp_to_celsius(int16_t lsb) +{ + return ( ( (float)lsb / 256.0f ) * 1.0f ) + 25.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Data_generation + * @brief This section group all the functions concerning data generation. + * @{ + * + */ + +/** + * @brief Temperature status register.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temp_status_reg_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, buff, 1); + return ret; +} +/** + * @brief Temperature data available.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tda in reg STATUS_REG_AUX + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temp_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_aux_t status_reg_aux; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, + (uint8_t*)&status_reg_aux, 1); + *val = status_reg_aux.tda; + + return ret; +} +/** + * @brief Temperature data overrun.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tor in reg STATUS_REG_AUX + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temp_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_aux_t status_reg_aux; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, + (uint8_t*)&status_reg_aux, 1); + *val = status_reg_aux.tor; + + return ret; +} +/** + * @brief Temperature output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temperature_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_TEMP_L, buff, 2); + return ret; +} +/** + * @brief Temperature sensor enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of temp_en in reg TEMP_CFG_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temperature_meas_set(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t val) +{ + lis2dh12_temp_cfg_reg_t temp_cfg_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1); + + if (ret == 0) { + temp_cfg_reg.temp_en = (uint8_t) val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1); + } + return ret; +} + +/** + * @brief Temperature sensor enable.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of temp_en in reg TEMP_CFG_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_temperature_meas_get(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t *val) +{ + lis2dh12_temp_cfg_reg_t temp_cfg_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t*)&temp_cfg_reg, 1); + switch (temp_cfg_reg.temp_en) { + case LIS2DH12_TEMP_DISABLE: + *val = LIS2DH12_TEMP_DISABLE; + break; + case LIS2DH12_TEMP_ENABLE: + *val = LIS2DH12_TEMP_ENABLE; + break; + default: + *val = LIS2DH12_TEMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lpen in reg CTRL_REG1 + * and HR in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_operating_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_op_md_t val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, + (uint8_t*)&ctrl_reg1, 1); + if (ret == 0) { + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, + (uint8_t*)&ctrl_reg4, 1); + } + if (ret == 0) { + if ( val == LIS2DH12_HR_12bit ) { + ctrl_reg1.lpen = 0; + ctrl_reg4.hr = 1; + } + if (val == LIS2DH12_NM_10bit) { + ctrl_reg1.lpen = 0; + ctrl_reg4.hr = 0; + } + if (val == LIS2DH12_LP_8bit) { + ctrl_reg1.lpen = 1; + ctrl_reg4.hr = 0; + } + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + } + if (ret == 0) { + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of lpen in reg CTRL_REG1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_operating_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_op_md_t *val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + if (ret == 0) { + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if ( ctrl_reg1.lpen == PROPERTY_ENABLE ) { + *val = LIS2DH12_LP_8bit; + } + if (ctrl_reg4.hr == PROPERTY_ENABLE ) { + *val = LIS2DH12_HR_12bit; + } else { + *val = LIS2DH12_NM_10bit; + } + } + return ret; +} + +/** + * @brief Output data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of odr in reg CTRL_REG1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_rate_set(lis2dh12_ctx_t *ctx, lis2dh12_odr_t val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + + if (ret == 0) { + ctrl_reg1.odr = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + } + return ret; +} + +/** + * @brief Output data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of odr in reg CTRL_REG1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_rate_get(lis2dh12_ctx_t *ctx, lis2dh12_odr_t *val) +{ + lis2dh12_ctrl_reg1_t ctrl_reg1; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1); + switch (ctrl_reg1.odr) { + case LIS2DH12_POWER_DOWN: + *val = LIS2DH12_POWER_DOWN; + break; + case LIS2DH12_ODR_1Hz: + *val = LIS2DH12_ODR_1Hz; + break; + case LIS2DH12_ODR_10Hz: + *val = LIS2DH12_ODR_10Hz; + break; + case LIS2DH12_ODR_25Hz: + *val = LIS2DH12_ODR_25Hz; + break; + case LIS2DH12_ODR_50Hz: + *val = LIS2DH12_ODR_50Hz; + break; + case LIS2DH12_ODR_100Hz: + *val = LIS2DH12_ODR_100Hz; + break; + case LIS2DH12_ODR_200Hz: + *val = LIS2DH12_ODR_200Hz; + break; + case LIS2DH12_ODR_400Hz: + *val = LIS2DH12_ODR_400Hz; + break; + case LIS2DH12_ODR_1kHz620_LP: + *val = LIS2DH12_ODR_1kHz620_LP; + break; + case LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP: + *val = LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP; + break; + default: + *val = LIS2DH12_POWER_DOWN; + break; + } + return ret; +} + +/** + * @brief High pass data from internal filter sent to output register + * and FIFO. + * + * @param ctx read / write interface definitions + * @param val change the values of fds in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_on_outputs_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.fds = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High pass data from internal filter sent to output register + * and FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fds in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_on_outputs_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + *val = (uint8_t)ctrl_reg2.fds; + + return ret; +} + +/** + * @brief High-pass filter cutoff frequency selection.[set] + * + * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz + * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz + * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz + * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz + * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz + * + * @param ctx read / write interface definitions + * @param val change the values of hpcf in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_bandwidth_set(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.hpcf = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High-pass filter cutoff frequency selection.[get] + * + * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz + * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz + * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz + * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz + * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz + * + * @param ctx read / write interface definitions + * @param val get the values of hpcf in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_bandwidth_get(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + switch (ctrl_reg2.hpcf) { + case LIS2DH12_AGGRESSIVE: + *val = LIS2DH12_AGGRESSIVE; + break; + case LIS2DH12_STRONG: + *val = LIS2DH12_STRONG; + break; + case LIS2DH12_MEDIUM: + *val = LIS2DH12_MEDIUM; + break; + case LIS2DH12_LIGHT: + *val = LIS2DH12_LIGHT; + break; + default: + *val = LIS2DH12_LIGHT; + break; + } + return ret; +} + +/** + * @brief High-pass filter mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of hpm in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.hpm = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High-pass filter mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of hpm in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + switch (ctrl_reg2.hpm) { + case LIS2DH12_NORMAL_WITH_RST: + *val = LIS2DH12_NORMAL_WITH_RST; + break; + case LIS2DH12_REFERENCE_MODE: + *val = LIS2DH12_REFERENCE_MODE; + break; + case LIS2DH12_NORMAL: + *val = LIS2DH12_NORMAL; + break; + case LIS2DH12_AUTORST_ON_INT: + *val = LIS2DH12_AUTORST_ON_INT; + break; + default: + *val = LIS2DH12_NORMAL_WITH_RST; + break; + } + return ret; +} + +/** + * @brief Full-scale configuration.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fs in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_full_scale_set(lis2dh12_ctx_t *ctx, lis2dh12_fs_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.fs = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Full-scale configuration.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of fs in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_full_scale_get(lis2dh12_ctx_t *ctx, lis2dh12_fs_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.fs) { + case LIS2DH12_2g: + *val = LIS2DH12_2g; + break; + case LIS2DH12_4g: + *val = LIS2DH12_4g; + break; + case LIS2DH12_8g: + *val = LIS2DH12_8g; + break; + case LIS2DH12_16g: + *val = LIS2DH12_16g; + break; + default: + *val = LIS2DH12_2g; + break; + } + return ret; +} + +/** + * @brief Block Data Update.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of bdu in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_block_data_update_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.bdu = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Block Data Update.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of bdu in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_block_data_update_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + *val = (uint8_t)ctrl_reg4.bdu; + + return ret; +} + +/** + * @brief Reference value for interrupt generation.[set] + * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_filter_reference_set(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_REFERENCE, buff, 1); + return ret; +} + +/** + * @brief Reference value for interrupt generation.[get] + * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_filter_reference_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_REFERENCE, buff, 1); + return ret; +} +/** + * @brief Acceleration set of data available.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of zyxda in reg STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_xl_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_t status_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = status_reg.zyxda; + + return ret; +} +/** + * @brief Acceleration set of data overrun.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of zyxor in reg STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_xl_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_status_reg_t status_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = status_reg.zyxor; + + return ret; +} +/** + * @brief Acceleration output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_acceleration_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_X_L, buff, 6); + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Common + * @brief This section group common usefull functions + * @{ + * + */ + +/** + * @brief DeviceWhoamI .[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_device_id_get(lis2dh12_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_WHO_AM_I, buff, 1); + return ret; +} +/** + * @brief Self Test.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of st in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_self_test_set(lis2dh12_ctx_t *ctx, lis2dh12_st_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.st = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Self Test.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of st in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_self_test_get(lis2dh12_ctx_t *ctx, lis2dh12_st_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.st) { + case LIS2DH12_ST_DISABLE: + *val = LIS2DH12_ST_DISABLE; + break; + case LIS2DH12_ST_POSITIVE: + *val = LIS2DH12_ST_POSITIVE; + break; + case LIS2DH12_ST_NEGATIVE: + *val = LIS2DH12_ST_NEGATIVE; + break; + default: + *val = LIS2DH12_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Big/Little Endian data selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ble in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_format_set(lis2dh12_ctx_t *ctx, lis2dh12_ble_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.ble = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief Big/Little Endian data selection.[get] + * + * @param ctx read / write interface definitions + * @param val get the values of ble in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_data_format_get(lis2dh12_ctx_t *ctx, lis2dh12_ble_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.ble) { + case LIS2DH12_LSB_AT_LOW_ADD: + *val = LIS2DH12_LSB_AT_LOW_ADD; + break; + case LIS2DH12_MSB_AT_LOW_ADD: + *val = LIS2DH12_MSB_AT_LOW_ADD; + break; + default: + *val = LIS2DH12_LSB_AT_LOW_ADD; + break; + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of boot in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_boot_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.boot = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of boot in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_boot_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.boot; + + return ret; +} + +/** + * @brief Info about device status.[get] + * + * @param ctx read / write interface definitions + * @param val register STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_status_get(lis2dh12_ctx_t *ctx, lis2dh12_status_reg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t*) val, 1); + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Interrupts_generator_1 + * @brief This section group all the functions that manage the first + * interrupts generator + * @{ + * + */ + +/** + * @brief Interrupt generator 1 configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val register INT1_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Interrupt generator 1 configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val register INT1_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Interrupt generator 1 source register.[get] + * + * @param ctx read / write interface definitions + * @param val Registers INT1_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_src_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_SRC, (uint8_t*) val, 1); + return ret; +} +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 1.[set] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT1_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int1_ths_t int1_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1); + if (ret == 0) { + int1_ths.ths = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1); + } + return ret; +} + +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 1.[get] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT1_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int1_ths_t int1_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t*)&int1_ths, 1); + *val = (uint8_t)int1_ths.ths; + + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT1_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int1_duration_t int1_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1); + if (ret == 0) { + int1_duration.d = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1); + } + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT1_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int1_duration_t int1_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t*)&int1_duration, 1); + *val = (uint8_t)int1_duration.d; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Interrupts_generator_2 + * @brief This section group all the functions that manage the second + * interrupts generator + * @{ + * + */ + +/** + * @brief Interrupt generator 2 configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers INT2_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Interrupt generator 2 configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers INT2_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t*) val, 1); + return ret; +} +/** + * @brief Interrupt generator 2 source register.[get] + * + * @param ctx read / write interface definitions + * @param val registers INT2_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_src_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_SRC, (uint8_t*) val, 1); + return ret; +} +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 2.[set] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT2_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int2_ths_t int2_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1); + if (ret == 0) { + int2_ths.ths = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1); + } + return ret; +} + +/** + * @brief User-defined threshold value for xl interrupt event on + * generator 2.[get] + * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg INT2_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int2_ths_t int2_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t*)&int2_ths, 1); + *val = (uint8_t)int2_ths.ths; + + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized .[set] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT2_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_int2_duration_t int2_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1); + if (ret == 0) { + int2_duration.d = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1); + } + return ret; +} + +/** + * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be + * recognized.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d in reg INT2_DURATION + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_int2_duration_t int2_duration; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t*)&int2_duration, 1); + *val = (uint8_t)int2_duration.d; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Interrupt_pins + * @brief This section group all the functions that manage interrup pins + * @{ + * + */ + +/** + * @brief High-pass filter on interrupts/tap generator.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of hp in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_int_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + if (ret == 0) { + ctrl_reg2.hp = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + } + return ret; +} + +/** + * @brief High-pass filter on interrupts/tap generator.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of hp in reg CTRL_REG2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_high_pass_int_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t *val) +{ + lis2dh12_ctrl_reg2_t ctrl_reg2; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1); + switch (ctrl_reg2.hp) { + case LIS2DH12_DISC_FROM_INT_GENERATOR: + *val = LIS2DH12_DISC_FROM_INT_GENERATOR; + break; + case LIS2DH12_ON_INT1_GEN: + *val = LIS2DH12_ON_INT1_GEN; + break; + case LIS2DH12_ON_INT2_GEN: + *val = LIS2DH12_ON_INT2_GEN; + break; + case LIS2DH12_ON_TAP_GEN: + *val = LIS2DH12_ON_TAP_GEN; + break; + case LIS2DH12_ON_INT1_INT2_GEN: + *val = LIS2DH12_ON_INT1_INT2_GEN; + break; + case LIS2DH12_ON_INT1_TAP_GEN: + *val = LIS2DH12_ON_INT1_TAP_GEN; + break; + case LIS2DH12_ON_INT2_TAP_GEN: + *val = LIS2DH12_ON_INT2_TAP_GEN; + break; + case LIS2DH12_ON_INT1_INT2_TAP_GEN: + *val = LIS2DH12_ON_INT1_INT2_TAP_GEN; + break; + default: + *val = LIS2DH12_DISC_FROM_INT_GENERATOR; + break; + } + return ret; +} + +/** + * @brief Int1 pin routing configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int1_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Int1 pin routing configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int1_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t*) val, 1); + return ret; +} +/** + * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled + * on INT2 pin when 6D bit on + * INT2_CFG (34h) is set to 1. + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.d4d_int2 = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on + * INT2_CFG (34h) is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.d4d_int2; + + return ret; +} + +/** + * @brief Latch interrupt request on INT2_SRC (35h) register, with + * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) + * itself.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lir_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.lir_int2 = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief Latch interrupt request on INT2_SRC (35h) register, with + * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) + * itself.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lir_int2 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int2_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + switch (ctrl_reg5.lir_int2) { + case LIS2DH12_INT2_PULSED: + *val = LIS2DH12_INT2_PULSED; + break; + case LIS2DH12_INT2_LATCHED: + *val = LIS2DH12_INT2_LATCHED; + break; + default: + *val = LIS2DH12_INT2_PULSED; + break; + } + return ret; +} + +/** + * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit + * on INT1_CFG(30h) is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.d4d_int1 = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on + * INT1_CFG(30h) is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.d4d_int1; + + return ret; +} + +/** + * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) + * register cleared by reading INT1_SRC (31h) itself.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lir_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.lir_int1 = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) + * register cleared by reading INT1_SRC (31h) itself.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lir_int1 in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_int1_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + switch (ctrl_reg5.lir_int1) { + case LIS2DH12_INT1_PULSED: + *val = LIS2DH12_INT1_PULSED; + break; + case LIS2DH12_INT1_LATCHED: + *val = LIS2DH12_INT1_LATCHED; + break; + default: + *val = LIS2DH12_INT1_PULSED; + break; + } + return ret; +} + +/** + * @brief Int2 pin routing configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG6 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int2_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Int2 pin routing configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CTRL_REG6 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_int2_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t*) val, 1); + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Fifo + * @brief This section group all the functions concerning the fifo usage + * @{ + * + */ + +/** + * @brief FIFO enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_en in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + if (ret == 0) { + ctrl_reg5.fifo_en = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + } + return ret; +} + +/** + * @brief FIFO enable.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_en in reg CTRL_REG5 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_ctrl_reg5_t ctrl_reg5; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1); + *val = (uint8_t)ctrl_reg5.fifo_en; + + return ret; +} + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fth in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_watermark_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + if (ret == 0) { + fifo_ctrl_reg.fth = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + } + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fth in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_watermark_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + *val = (uint8_t)fifo_ctrl_reg.fth; + + return ret; +} + +/** + * @brief Trigger FIFO selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tr in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_trigger_event_set(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + if (ret == 0) { + fifo_ctrl_reg.tr = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + } + return ret; +} + +/** + * @brief Trigger FIFO selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of tr in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_trigger_event_get(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t *val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + switch (fifo_ctrl_reg.tr) { + case LIS2DH12_INT1_GEN: + *val = LIS2DH12_INT1_GEN; + break; + case LIS2DH12_INT2_GEN: + *val = LIS2DH12_INT2_GEN; + break; + default: + *val = LIS2DH12_INT1_GEN; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fm in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_fm_t val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + if (ret == 0) { + fifo_ctrl_reg.fm = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fm in reg FIFO_CTRL_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_fm_t *val) +{ + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t*)&fifo_ctrl_reg, 1); + switch (fifo_ctrl_reg.fm) { + case LIS2DH12_BYPASS_MODE: + *val = LIS2DH12_BYPASS_MODE; + break; + case LIS2DH12_FIFO_MODE: + *val = LIS2DH12_FIFO_MODE; + break; + case LIS2DH12_DYNAMIC_STREAM_MODE: + *val = LIS2DH12_DYNAMIC_STREAM_MODE; + break; + case LIS2DH12_STREAM_TO_FIFO_MODE: + *val = LIS2DH12_STREAM_TO_FIFO_MODE; + break; + default: + *val = LIS2DH12_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief FIFO status register.[get] + * + * @param ctx read / write interface definitions + * @param val registers FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_status_get(lis2dh12_ctx_t *ctx, + lis2dh12_fifo_src_reg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*) val, 1); + return ret; +} +/** + * @brief FIFO stored data level.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fss in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_data_level_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.fss; + + return ret; +} +/** + * @brief Empty FIFO status flag.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of empty in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_empty_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.empty; + + return ret; +} +/** + * @brief FIFO overrun status flag.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_ovr_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.ovrn_fifo; + + return ret; +} +/** + * @brief FIFO watermark status.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of wtm in reg FIFO_SRC_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_fifo_fth_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_fifo_src_reg_t fifo_src_reg; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t*)&fifo_src_reg, 1); + *val = (uint8_t)fifo_src_reg.wtm; + + return ret; +} +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Tap_generator + * @brief This section group all the functions that manage the tap and + * double tap event generation + * @{ + * + */ + +/** + * @brief Tap/Double Tap generator configuration register.[set] + * + * @param ctx read / write interface definitions + * @param val registers CLICK_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_conf_set(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Tap/Double Tap generator configuration register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CLICK_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_conf_get(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t*) val, 1); + return ret; +} +/** + * @brief Tap/Double Tap generator source register.[get] + * + * @param ctx read / write interface definitions + * @param val registers CLICK_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_source_get(lis2dh12_ctx_t *ctx, lis2dh12_click_src_t *val) +{ + int32_t ret; + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_SRC, (uint8_t*) val, 1); + return ret; +} +/** + * @brief User-defined threshold value for Tap/Double Tap event.[set] + * 1 LSB = full scale/128 + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + if (ret == 0) { + click_ths.ths = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + } + return ret; +} + +/** + * @brief User-defined threshold value for Tap/Double Tap event.[get] + * 1 LSB = full scale/128 + * + * @param ctx read / write interface definitions + * @param val change the values of ths in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + *val = (uint8_t)click_ths.ths; + + return ret; +} + +/** + * @brief If the LIR_Click bit is not set, the interrupt is kept high + * for the duration of the latency window. + * If the LIR_Click bit is set, the interrupt is kept high until the + * CLICK_SRC(39h) register is read.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lir_click in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + if (ret == 0) { + click_ths.lir_click = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + } + return ret; +} + +/** + * @brief If the LIR_Click bit is not set, the interrupt is kept high + * for the duration of the latency window. + * If the LIR_Click bit is set, the interrupt is kept high until the + * CLICK_SRC(39h) register is read.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lir_click in reg CLICK_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_tap_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t *val) +{ + lis2dh12_click_ths_t click_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t*)&click_ths, 1); + switch (click_ths.lir_click) { + case LIS2DH12_TAP_PULSED: + *val = LIS2DH12_TAP_PULSED; + break; + case LIS2DH12_TAP_LATCHED: + *val = LIS2DH12_TAP_LATCHED; + break; + default: + *val = LIS2DH12_TAP_PULSED; + break; + } + return ret; +} + +/** + * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse + * between the start of the click-detection procedure and when the + * acceleration falls back below the threshold.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tli in reg TIME_LIMIT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_shock_dur_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_time_limit_t time_limit; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1); + if (ret == 0) { + time_limit.tli = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1); + } + return ret; +} + +/** + * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between + * the start of the click-detection procedure and when the + * acceleration falls back below the threshold.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tli in reg TIME_LIMIT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_shock_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_time_limit_t time_limit; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t*)&time_limit, 1); + *val = (uint8_t)time_limit.tli; + + return ret; +} + +/** + * @brief The time (1 LSB = 1/ODR) interval that starts after the first + * click detection where the click-detection procedure is + * disabled, in cases where the device is configured for + * double-click detection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tla in reg TIME_LATENCY + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_quiet_dur_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_time_latency_t time_latency; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1); + if (ret == 0) { + time_latency.tla = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1); + } + return ret; +} + +/** + * @brief The time (1 LSB = 1/ODR) interval that starts after the first + * click detection where the click-detection procedure is + * disabled, in cases where the device is configured for + * double-click detection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tla in reg TIME_LATENCY + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_quiet_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_time_latency_t time_latency; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t*)&time_latency, 1); + *val = (uint8_t)time_latency.tla; + + return ret; +} + +/** + * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse + * after the end of the latency interval in which the click-detection + * procedure can start, in cases where the device is configured + * for double-click detection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tw in reg TIME_WINDOW + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_double_tap_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_time_window_t time_window; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1); + if (ret == 0) { + time_window.tw = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1); + } + return ret; +} + +/** + * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse + * after the end of the latency interval in which the + * click-detection procedure can start, in cases where the device + * is configured for double-click detection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tw in reg TIME_WINDOW + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_double_tap_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_time_window_t time_window; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t*)&time_window, 1); + *val = (uint8_t)time_window.tw; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Activity_inactivity + * @brief This section group all the functions concerning activity + * inactivity functionality + * @{ + * + */ + +/** + * @brief Sleep-to-wake, return-to-sleep activation threshold in + * low-power mode.[set] + * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of acth in reg ACT_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_act_ths_t act_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1); + if (ret == 0) { + act_ths.acth = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1); + } + return ret; +} + +/** + * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power + * mode.[get] + * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g + * + * @param ctx read / write interface definitions + * @param val change the values of acth in reg ACT_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_act_ths_t act_ths; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t*)&act_ths, 1); + *val = (uint8_t)act_ths.acth; + + return ret; +} + +/** + * @brief Sleep-to-wake, return-to-sleep.[set] + * duration = (8*1[LSb]+1)/ODR + * + * @param ctx read / write interface definitions + * @param val change the values of actd in reg ACT_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val) +{ + lis2dh12_act_dur_t act_dur; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1); + if (ret == 0) { + act_dur.actd = val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1); + } + return ret; +} + +/** + * @brief Sleep-to-wake, return-to-sleep.[get] + * duration = (8*1[LSb]+1)/ODR + * + * @param ctx read / write interface definitions + * @param val change the values of actd in reg ACT_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_act_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val) +{ + lis2dh12_act_dur_t act_dur; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t*)&act_dur, 1); + *val = (uint8_t)act_dur.actd; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LIS2DH12_Serial_interface + * @brief This section group all the functions concerning serial + * interface management + * @{ + * + */ + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sdo_pu_disc in reg CTRL_REG0 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_sdo_sa0_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t val) +{ + lis2dh12_ctrl_reg0_t ctrl_reg0; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1); + if (ret == 0) { + ctrl_reg0.sdo_pu_disc = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sdo_pu_disc in reg CTRL_REG0 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_pin_sdo_sa0_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t *val) +{ + lis2dh12_ctrl_reg0_t ctrl_reg0; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t*)&ctrl_reg0, 1); + switch (ctrl_reg0.sdo_pu_disc) { + case LIS2DH12_PULL_UP_DISCONNECT: + *val = LIS2DH12_PULL_UP_DISCONNECT; + break; + case LIS2DH12_PULL_UP_CONNECT: + *val = LIS2DH12_PULL_UP_CONNECT; + break; + default: + *val = LIS2DH12_PULL_UP_DISCONNECT; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sim in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_spi_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_sim_t val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + if (ret == 0) { + ctrl_reg4.sim = (uint8_t)val; + ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sim in reg CTRL_REG4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dh12_spi_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_sim_t *val) +{ + lis2dh12_ctrl_reg4_t ctrl_reg4; + int32_t ret; + + ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t*)&ctrl_reg4, 1); + switch (ctrl_reg4.sim) { + case LIS2DH12_SPI_4_WIRE: + *val = LIS2DH12_SPI_4_WIRE; + break; + case LIS2DH12_SPI_3_WIRE: + *val = LIS2DH12_SPI_3_WIRE; + break; + default: + *val = LIS2DH12_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.h new file mode 100644 index 0000000000..3ca4f6224f --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/COMPONENT_lis2dh12/lis2dh12/lis2dh12_reg.h @@ -0,0 +1,764 @@ +/* + ****************************************************************************** + * @file lis2dh12_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lis2dh12_reg.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ +// SPDX-License-Identifier: BSD-3-Clause + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LIS2DH12_REGS_H +#define LIS2DH12_REGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/** @addtogroup LIS2DH12 + * @{ + * + */ + +/** @defgroup LIS2DH12_sensors_common_types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +/** + * @defgroup axisXbitXX_t + * @brief These unions are useful to represent different sensors data type. + * These unions are not need by the driver. + * + * REMOVING the unions you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ + +typedef union{ + int16_t i16bit[3]; + uint8_t u8bit[6]; +} axis3bit16_t; + +typedef union{ + int16_t i16bit; + uint8_t u8bit[2]; +} axis1bit16_t; + +typedef union{ + int32_t i32bit[3]; + uint8_t u8bit[12]; +} axis3bit32_t; + +typedef union{ + int32_t i32bit; + uint8_t u8bit[4]; +} axis1bit32_t; + +/** + * @} + * + */ + +typedef struct{ + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +#endif /* MEMS_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @addtogroup LIS3MDL_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*lis2dh12_write_ptr)(void *, uint8_t, uint8_t*, uint16_t); +typedef int32_t (*lis2dh12_read_ptr) (void *, uint8_t, uint8_t*, uint16_t); + +typedef struct { + /** Component mandatory fields **/ + lis2dh12_write_ptr write_reg; + lis2dh12_read_ptr read_reg; + /** Customizable optional pointer **/ + void *handle; +} lis2dh12_ctx_t; + +/** + * @} + * + */ + +/** @defgroup LIS2DH12_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ +#define LIS2DH12_I2C_ADD_L 0x31U +#define LIS2DH12_I2C_ADD_H 0x33U + +/** Device Identification (Who am I) **/ +#define LIS2DH12_ID 0x33U + +/** + * @} + * + */ + +#define LIS2DH12_STATUS_REG_AUX 0x07U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t tda : 1; + uint8_t not_used_02 : 3; + uint8_t tor : 1; + uint8_t not_used_03 : 1; +} lis2dh12_status_reg_aux_t; + +#define LIS2DH12_OUT_TEMP_L 0x0CU +#define LIS2DH12_OUT_TEMP_H 0x0DU +#define LIS2DH12_WHO_AM_I 0x0FU + +#define LIS2DH12_CTRL_REG0 0x1EU +typedef struct { + uint8_t not_used_01 : 7; + uint8_t sdo_pu_disc : 1; +} lis2dh12_ctrl_reg0_t; + +#define LIS2DH12_TEMP_CFG_REG 0x1FU +typedef struct { + uint8_t not_used_01 : 6; + uint8_t temp_en : 2; +} lis2dh12_temp_cfg_reg_t; + +#define LIS2DH12_CTRL_REG1 0x20U +typedef struct { + uint8_t xen : 1; + uint8_t yen : 1; + uint8_t zen : 1; + uint8_t lpen : 1; + uint8_t odr : 4; +} lis2dh12_ctrl_reg1_t; + +#define LIS2DH12_CTRL_REG2 0x21U +typedef struct { + uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ + uint8_t fds : 1; + uint8_t hpcf : 2; + uint8_t hpm : 2; +} lis2dh12_ctrl_reg2_t; + +#define LIS2DH12_CTRL_REG3 0x22U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t i1_overrun : 1; + uint8_t i1_wtm : 1; + uint8_t not_used_02 : 1; + uint8_t i1_zyxda : 1; + uint8_t i1_ia2 : 1; + uint8_t i1_ia1 : 1; + uint8_t i1_click : 1; +} lis2dh12_ctrl_reg3_t; + +#define LIS2DH12_CTRL_REG4 0x23U +typedef struct { + uint8_t sim : 1; + uint8_t st : 2; + uint8_t hr : 1; + uint8_t fs : 2; + uint8_t ble : 1; + uint8_t bdu : 1; +} lis2dh12_ctrl_reg4_t; + +#define LIS2DH12_CTRL_REG5 0x24U +typedef struct { + uint8_t d4d_int2 : 1; + uint8_t lir_int2 : 1; + uint8_t d4d_int1 : 1; + uint8_t lir_int1 : 1; + uint8_t not_used_01 : 2; + uint8_t fifo_en : 1; + uint8_t boot : 1; +} lis2dh12_ctrl_reg5_t; + +#define LIS2DH12_CTRL_REG6 0x25U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t int_polarity : 1; + uint8_t not_used_02 : 1; + uint8_t i2_act : 1; + uint8_t i2_boot : 1; + uint8_t i2_ia2 : 1; + uint8_t i2_ia1 : 1; + uint8_t i2_click : 1; +} lis2dh12_ctrl_reg6_t; + +#define LIS2DH12_REFERENCE 0x26U +#define LIS2DH12_STATUS_REG 0x27U +typedef struct { + uint8_t xda : 1; + uint8_t yda : 1; + uint8_t zda : 1; + uint8_t zyxda : 1; + uint8_t _xor : 1; + uint8_t yor : 1; + uint8_t zor : 1; + uint8_t zyxor : 1; +} lis2dh12_status_reg_t; + +#define LIS2DH12_OUT_X_L 0x28U +#define LIS2DH12_OUT_X_H 0x29U +#define LIS2DH12_OUT_Y_L 0x2AU +#define LIS2DH12_OUT_Y_H 0x2BU +#define LIS2DH12_OUT_Z_L 0x2CU +#define LIS2DH12_OUT_Z_H 0x2DU +#define LIS2DH12_FIFO_CTRL_REG 0x2EU +typedef struct { + uint8_t fth : 5; + uint8_t tr : 1; + uint8_t fm : 2; +} lis2dh12_fifo_ctrl_reg_t; + +#define LIS2DH12_FIFO_SRC_REG 0x2FU +typedef struct { + uint8_t fss : 5; + uint8_t empty : 1; + uint8_t ovrn_fifo : 1; + uint8_t wtm : 1; +} lis2dh12_fifo_src_reg_t; + +#define LIS2DH12_INT1_CFG 0x30U +typedef struct { + uint8_t xlie : 1; + uint8_t xhie : 1; + uint8_t ylie : 1; + uint8_t yhie : 1; + uint8_t zlie : 1; + uint8_t zhie : 1; + uint8_t _6d : 1; + uint8_t aoi : 1; +} lis2dh12_int1_cfg_t; + +#define LIS2DH12_INT1_SRC 0x31U +typedef struct { + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t ia : 1; + uint8_t not_used_01 : 1; +} lis2dh12_int1_src_t; + +#define LIS2DH12_INT1_THS 0x32U +typedef struct { + uint8_t ths : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int1_ths_t; + +#define LIS2DH12_INT1_DURATION 0x33U +typedef struct { + uint8_t d : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int1_duration_t; + +#define LIS2DH12_INT2_CFG 0x34U +typedef struct { + uint8_t xlie : 1; + uint8_t xhie : 1; + uint8_t ylie : 1; + uint8_t yhie : 1; + uint8_t zlie : 1; + uint8_t zhie : 1; + uint8_t _6d : 1; + uint8_t aoi : 1; +} lis2dh12_int2_cfg_t; + +#define LIS2DH12_INT2_SRC 0x35U +typedef struct { + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t ia : 1; + uint8_t not_used_01 : 1; +} lis2dh12_int2_src_t; + +#define LIS2DH12_INT2_THS 0x36U +typedef struct { + uint8_t ths : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int2_ths_t; + +#define LIS2DH12_INT2_DURATION 0x37U +typedef struct { + uint8_t d : 7; + uint8_t not_used_01 : 1; +} lis2dh12_int2_duration_t; + +#define LIS2DH12_CLICK_CFG 0x38U +typedef struct { + uint8_t xs : 1; + uint8_t xd : 1; + uint8_t ys : 1; + uint8_t yd : 1; + uint8_t zs : 1; + uint8_t zd : 1; + uint8_t not_used_01 : 2; +} lis2dh12_click_cfg_t; + +#define LIS2DH12_CLICK_SRC 0x39U +typedef struct { + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; + uint8_t sign : 1; + uint8_t sclick : 1; + uint8_t dclick : 1; + uint8_t ia : 1; + uint8_t not_used_01 : 1; +} lis2dh12_click_src_t; + +#define LIS2DH12_CLICK_THS 0x3AU +typedef struct { + uint8_t ths : 7; + uint8_t lir_click : 1; +} lis2dh12_click_ths_t; + +#define LIS2DH12_TIME_LIMIT 0x3BU +typedef struct { + uint8_t tli : 7; + uint8_t not_used_01 : 1; +} lis2dh12_time_limit_t; + +#define LIS2DH12_TIME_LATENCY 0x3CU +typedef struct { + uint8_t tla : 8; +} lis2dh12_time_latency_t; + +#define LIS2DH12_TIME_WINDOW 0x3DU +typedef struct { + uint8_t tw : 8; +} lis2dh12_time_window_t; + +#define LIS2DH12_ACT_THS 0x3EU +typedef struct { + uint8_t acth : 7; + uint8_t not_used_01 : 1; +} lis2dh12_act_ths_t; + +#define LIS2DH12_ACT_DUR 0x3FU +typedef struct { + uint8_t actd : 8; +} lis2dh12_act_dur_t; + +/** + * @defgroup LIS2DH12_Register_Union + * @brief This union group all the registers that has a bitfield + * description. + * This union is usefull but not need by the driver. + * + * REMOVING this union you are complient with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union{ + lis2dh12_status_reg_aux_t status_reg_aux; + lis2dh12_ctrl_reg0_t ctrl_reg0; + lis2dh12_temp_cfg_reg_t temp_cfg_reg; + lis2dh12_ctrl_reg1_t ctrl_reg1; + lis2dh12_ctrl_reg2_t ctrl_reg2; + lis2dh12_ctrl_reg3_t ctrl_reg3; + lis2dh12_ctrl_reg4_t ctrl_reg4; + lis2dh12_ctrl_reg5_t ctrl_reg5; + lis2dh12_ctrl_reg6_t ctrl_reg6; + lis2dh12_status_reg_t status_reg; + lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; + lis2dh12_fifo_src_reg_t fifo_src_reg; + lis2dh12_int1_cfg_t int1_cfg; + lis2dh12_int1_src_t int1_src; + lis2dh12_int1_ths_t int1_ths; + lis2dh12_int1_duration_t int1_duration; + lis2dh12_int2_cfg_t int2_cfg; + lis2dh12_int2_src_t int2_src; + lis2dh12_int2_ths_t int2_ths; + lis2dh12_int2_duration_t int2_duration; + lis2dh12_click_cfg_t click_cfg; + lis2dh12_click_src_t click_src; + lis2dh12_click_ths_t click_ths; + lis2dh12_time_limit_t time_limit; + lis2dh12_time_latency_t time_latency; + lis2dh12_time_window_t time_window; + lis2dh12_act_ths_t act_ths; + lis2dh12_act_dur_t act_dur; + bitwise_t bitwise; + uint8_t byte; +} lis2dh12_reg_t; + +/** + * @} + * + */ + +int32_t lis2dh12_read_reg(lis2dh12_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); +int32_t lis2dh12_write_reg(lis2dh12_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); + +extern float lis2dh12_from_fs2_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_fs4_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_fs8_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_fs16_hr_to_mg(int16_t lsb); +extern float lis2dh12_from_lsb_hr_to_celsius(int16_t lsb); + +extern float lis2dh12_from_fs2_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_fs4_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_fs8_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_fs16_nm_to_mg(int16_t lsb); +extern float lis2dh12_from_lsb_nm_to_celsius(int16_t lsb); + +extern float lis2dh12_from_fs2_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_fs4_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_fs8_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_fs16_lp_to_mg(int16_t lsb); +extern float lis2dh12_from_lsb_lp_to_celsius(int16_t lsb); + +int32_t lis2dh12_temp_status_reg_get(lis2dh12_ctx_t *ctx, uint8_t *buff); +int32_t lis2dh12_temp_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_temp_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_temperature_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LIS2DH12_TEMP_DISABLE = 0, + LIS2DH12_TEMP_ENABLE = 3, +} lis2dh12_temp_en_t; +int32_t lis2dh12_temperature_meas_set(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t val); +int32_t lis2dh12_temperature_meas_get(lis2dh12_ctx_t *ctx, + lis2dh12_temp_en_t *val); + +typedef enum { + LIS2DH12_HR_12bit = 0, + LIS2DH12_NM_10bit = 1, + LIS2DH12_LP_8bit = 2, +} lis2dh12_op_md_t; +int32_t lis2dh12_operating_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_op_md_t val); +int32_t lis2dh12_operating_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_op_md_t *val); + +typedef enum { + LIS2DH12_POWER_DOWN = 0x00, + LIS2DH12_ODR_1Hz = 0x01, + LIS2DH12_ODR_10Hz = 0x02, + LIS2DH12_ODR_25Hz = 0x03, + LIS2DH12_ODR_50Hz = 0x04, + LIS2DH12_ODR_100Hz = 0x05, + LIS2DH12_ODR_200Hz = 0x06, + LIS2DH12_ODR_400Hz = 0x07, + LIS2DH12_ODR_1kHz620_LP = 0x08, + LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, +} lis2dh12_odr_t; +int32_t lis2dh12_data_rate_set(lis2dh12_ctx_t *ctx, lis2dh12_odr_t val); +int32_t lis2dh12_data_rate_get(lis2dh12_ctx_t *ctx, lis2dh12_odr_t *val); + +int32_t lis2dh12_high_pass_on_outputs_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_high_pass_on_outputs_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_AGGRESSIVE = 0, + LIS2DH12_STRONG = 1, + LIS2DH12_MEDIUM = 2, + LIS2DH12_LIGHT = 3, +} lis2dh12_hpcf_t; +int32_t lis2dh12_high_pass_bandwidth_set(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t val); +int32_t lis2dh12_high_pass_bandwidth_get(lis2dh12_ctx_t *ctx, + lis2dh12_hpcf_t *val); + +typedef enum { + LIS2DH12_NORMAL_WITH_RST = 0, + LIS2DH12_REFERENCE_MODE = 1, + LIS2DH12_NORMAL = 2, + LIS2DH12_AUTORST_ON_INT = 3, +} lis2dh12_hpm_t; +int32_t lis2dh12_high_pass_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t val); +int32_t lis2dh12_high_pass_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_hpm_t *val); + +typedef enum { + LIS2DH12_2g = 0, + LIS2DH12_4g = 1, + LIS2DH12_8g = 2, + LIS2DH12_16g = 3, +} lis2dh12_fs_t; +int32_t lis2dh12_full_scale_set(lis2dh12_ctx_t *ctx, lis2dh12_fs_t val); +int32_t lis2dh12_full_scale_get(lis2dh12_ctx_t *ctx, lis2dh12_fs_t *val); + +int32_t lis2dh12_block_data_update_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_block_data_update_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_filter_reference_set(lis2dh12_ctx_t *ctx, uint8_t *buff); +int32_t lis2dh12_filter_reference_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +int32_t lis2dh12_xl_data_ready_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_xl_data_ovr_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_acceleration_raw_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +int32_t lis2dh12_device_id_get(lis2dh12_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LIS2DH12_ST_DISABLE = 0, + LIS2DH12_ST_POSITIVE = 1, + LIS2DH12_ST_NEGATIVE = 2, +} lis2dh12_st_t; +int32_t lis2dh12_self_test_set(lis2dh12_ctx_t *ctx, lis2dh12_st_t val); +int32_t lis2dh12_self_test_get(lis2dh12_ctx_t *ctx, lis2dh12_st_t *val); + +typedef enum { + LIS2DH12_LSB_AT_LOW_ADD = 0, + LIS2DH12_MSB_AT_LOW_ADD = 1, +} lis2dh12_ble_t; +int32_t lis2dh12_data_format_set(lis2dh12_ctx_t *ctx, lis2dh12_ble_t val); +int32_t lis2dh12_data_format_get(lis2dh12_ctx_t *ctx, lis2dh12_ble_t *val); + +int32_t lis2dh12_boot_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_boot_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_status_get(lis2dh12_ctx_t *ctx, lis2dh12_status_reg_t *val); + +int32_t lis2dh12_int1_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val); +int32_t lis2dh12_int1_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_cfg_t *val); + +int32_t lis2dh12_int1_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int1_src_t *val); + +int32_t lis2dh12_int1_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int1_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_int1_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int1_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_int2_gen_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val); +int32_t lis2dh12_int2_gen_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_cfg_t *val); + +int32_t lis2dh12_int2_gen_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_int2_src_t *val); + +int32_t lis2dh12_int2_gen_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int2_gen_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_int2_gen_duration_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int2_gen_duration_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_DISC_FROM_INT_GENERATOR = 0, + LIS2DH12_ON_INT1_GEN = 1, + LIS2DH12_ON_INT2_GEN = 2, + LIS2DH12_ON_TAP_GEN = 4, + LIS2DH12_ON_INT1_INT2_GEN = 3, + LIS2DH12_ON_INT1_TAP_GEN = 5, + LIS2DH12_ON_INT2_TAP_GEN = 6, + LIS2DH12_ON_INT1_INT2_TAP_GEN = 7, +} lis2dh12_hp_t; +int32_t lis2dh12_high_pass_int_conf_set(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t val); +int32_t lis2dh12_high_pass_int_conf_get(lis2dh12_ctx_t *ctx, + lis2dh12_hp_t *val); + +int32_t lis2dh12_pin_int1_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val); +int32_t lis2dh12_pin_int1_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg3_t *val); + +int32_t lis2dh12_int2_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int2_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_INT2_PULSED = 0, + LIS2DH12_INT2_LATCHED = 1, +} lis2dh12_lir_int2_t; +int32_t lis2dh12_int2_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t val); +int32_t lis2dh12_int2_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int2_t *val); + +int32_t lis2dh12_int1_pin_detect_4d_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_int1_pin_detect_4d_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_INT1_PULSED = 0, + LIS2DH12_INT1_LATCHED = 1, +} lis2dh12_lir_int1_t; +int32_t lis2dh12_int1_pin_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t val); +int32_t lis2dh12_int1_pin_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_int1_t *val); + +int32_t lis2dh12_pin_int2_config_set(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val); +int32_t lis2dh12_pin_int2_config_get(lis2dh12_ctx_t *ctx, + lis2dh12_ctrl_reg6_t *val); + +int32_t lis2dh12_fifo_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_fifo_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_watermark_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_fifo_watermark_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_INT1_GEN = 0, + LIS2DH12_INT2_GEN = 1, +} lis2dh12_tr_t; +int32_t lis2dh12_fifo_trigger_event_set(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t val); +int32_t lis2dh12_fifo_trigger_event_get(lis2dh12_ctx_t *ctx, + lis2dh12_tr_t *val); + +typedef enum { + LIS2DH12_BYPASS_MODE = 0, + LIS2DH12_FIFO_MODE = 1, + LIS2DH12_DYNAMIC_STREAM_MODE = 2, + LIS2DH12_STREAM_TO_FIFO_MODE = 3, +} lis2dh12_fm_t; +int32_t lis2dh12_fifo_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_fm_t val); +int32_t lis2dh12_fifo_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_fm_t *val); + +int32_t lis2dh12_fifo_status_get(lis2dh12_ctx_t *ctx, + lis2dh12_fifo_src_reg_t *val); + +int32_t lis2dh12_fifo_data_level_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_empty_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_ovr_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_fifo_fth_flag_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_tap_conf_set(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val); +int32_t lis2dh12_tap_conf_get(lis2dh12_ctx_t *ctx, lis2dh12_click_cfg_t *val); + +int32_t lis2dh12_tap_source_get(lis2dh12_ctx_t *ctx, + lis2dh12_click_src_t *val); + +int32_t lis2dh12_tap_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_tap_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_TAP_PULSED = 0, + LIS2DH12_TAP_LATCHED = 1, +} lis2dh12_lir_click_t; +int32_t lis2dh12_tap_notification_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t val); +int32_t lis2dh12_tap_notification_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_lir_click_t *val); + +int32_t lis2dh12_shock_dur_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_shock_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_quiet_dur_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_quiet_dur_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_double_tap_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_double_tap_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_act_threshold_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_act_threshold_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +int32_t lis2dh12_act_timeout_set(lis2dh12_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_act_timeout_get(lis2dh12_ctx_t *ctx, uint8_t *val); + +typedef enum { + LIS2DH12_PULL_UP_DISCONNECT = 0, + LIS2DH12_PULL_UP_CONNECT = 1, +} lis2dh12_sdo_pu_disc_t; +int32_t lis2dh12_pin_sdo_sa0_mode_set(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t val); +int32_t lis2dh12_pin_sdo_sa0_mode_get(lis2dh12_ctx_t *ctx, + lis2dh12_sdo_pu_disc_t *val); + +typedef enum { + LIS2DH12_SPI_4_WIRE = 0, + LIS2DH12_SPI_3_WIRE = 1, +} lis2dh12_sim_t; +int32_t lis2dh12_spi_mode_set(lis2dh12_ctx_t *ctx, lis2dh12_sim_t val); +int32_t lis2dh12_spi_mode_get(lis2dh12_ctx_t *ctx, lis2dh12_sim_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIS2DH12_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h new file mode 100644 index 0000000000..4246531a69 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/PinNames.h @@ -0,0 +1,117 @@ +/* +Copyright (c) 2019 SparkFun Electronics + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. +*/ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 25, + D1 = 24, + D2 = 35, + D3 = 4, + D4 = 22, + D5 = 23, + D6 = 27, + D7 = 28, + D8 = 32, + D9 = 12, + D10 = 13, + D11 = 7, + D12 = 6, + D13 = 5, + D14 = 40, + D15 = 39, + D16 = 29, + D17 = 11, + D18 = 34, + D19 = 33, + D20 = 16, + D21 = 31, + + // Analog naming + A0 = D16, + A1 = D17, + A2 = D18, + A3 = D19, + A4 = D20, + A5 = D21, + A6 = D2, + // A7 = ?? + A8 = D8, + A9 = D9, + A10 = D10, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = A5, + + // LED naming by digital pin number + LED13 = AM_BSP_GPIO_LED13, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D1, + SERIAL1_RX = D0, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.c new file mode 100644 index 0000000000..50dd4ab751 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.h new file mode 100644 index 0000000000..a1346b9f0d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp.h @@ -0,0 +1,254 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED13 AM_BSP_GPIO_LED_BLUE + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The RedBoard Artemis PWM LED is pad 5 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 2 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA2C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..291e05ed58 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.c @@ -0,0 +1,861 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 13. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..a68be4540a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS/bsp/am_bsp_pins.h @@ -0,0 +1,584 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 13. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h new file mode 100644 index 0000000000..073a6aec36 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/PinNames.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D4 = 4, + D5 = 5, + D6 = 6, + D7 = 7, + D8 = 8, + D9 = 9, + D10 = 10, + D11 = 11, + D12 = 12, + D13 = 13, + D14 = 14, + D15 = 15, + D16 = 16, + D17 = 17, + D18 = 18, + D19 = 19, + // D20 = ?? + // D21 = ?? + D22 = 22, + D23 = 23, + D24 = 24, + D25 = 25, + D26 = 26, + D27 = 27, + D28 = 28, + D29 = 29, + // D30 = ?? + D31 = 31, + D32 = 32, + D33 = 33, + D34 = 34, + D35 = 35, + D36 = 36, + D37 = 37, + D38 = 38, + D39 = 39, + D40 = 40, + D41 = 41, + D42 = 42, + D43 = 43, + D44 = 44, + D45 = 45, + + // Analog naming + A11 = D11, + A12 = D12, + A13 = D13, + A16 = D16, + A29 = D29, + A31 = D31, + A32 = D32, + A33 = D33, + A34 = D34, + A35 = D35, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D42, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D24, + SERIAL1_RX = D25, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c new file mode 100644 index 0000000000..50dd4ab751 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h new file mode 100644 index 0000000000..0c1d8b6692 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp.h @@ -0,0 +1,255 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_BLUE + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The ATP PWM LED is pad 5 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 2 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA2C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..0461c4043c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.c @@ -0,0 +1,861 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..d7d63c3475 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_ATP/bsp/am_bsp_pins.h @@ -0,0 +1,584 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h new file mode 100644 index 0000000000..553cbb93d2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/PinNames.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D13 = 13, + D16 = 16, + D23 = 23, + D24 = 24, + D25 = 25, + D26 = 26, + D27 = 27, + D28 = 28, + D29 = 29, + // D30 = 30, ?? + D31 = 31, + D32 = 32, + D33 = 33, + D34 = 34, + D35 = 35, + D36 = 36, + D37 = 37, + D38 = 38, + D39 = 39, + D40 = 40, + D41 = 41, + D42 = 42, + D43 = 43, + D44 = 44, + D45 = 45, + + // Analog naming + A13 = D13, + A16 = D16, + A29 = D29, + A31 = D31, + A32 = D32, + A33 = D33, + A34 = D34, + A35 = D35, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D24, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // Accelerometer + ACC_SCL = QWIIC_SCL, + ACC_SDA = QWIIC_SDA, + + // Camera + CAM_SCL = QWIIC_SCL, + CAM_SDA = QWIIC_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c new file mode 100644 index 0000000000..50dd4ab751 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h new file mode 100644 index 0000000000..b423be0403 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp.h @@ -0,0 +1,294 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +// artmbed hardware version: v01 (there will need to be changes when migrating to v02 or v10) + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Camera +// +//***************************************************************************** +#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 18 +#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1 +#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_CAMERA_HM01B0_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_CAMERA_HM01B0_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 1 +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERA + + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + +//***************************************************************************** +// +// Accelerometer. +// +//***************************************************************************** +#define AM_BSP_ACCELEROMETER_I2C_IOM 1 +#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19 +#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 4 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM4_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM4_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM4_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM4_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM4_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM4_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 1 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL + + +// //***************************************************************************** +// // +// // Button definitions. +// // +// //***************************************************************************** +// #define AM_BSP_NUM_BUTTONS 0 +// extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED23 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED_STAT AM_BSP_GPIO_LED_BLUE + + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The ARTMBED LED0 is pad 23 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 3 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB3C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..782e9ab941 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.c @@ -0,0 +1,1017 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0 = +{ + .uFuncSel = AM_HAL_PIN_0_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1 = +{ + .uFuncSel = AM_HAL_PIN_1_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2 = +{ + .uFuncSel = AM_HAL_PIN_2_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3 = +{ + .uFuncSel = AM_HAL_PIN_3_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4 = +{ + .uFuncSel = AM_HAL_PIN_4_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5 = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6 = +{ + .uFuncSel = AM_HAL_PIN_6_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7 = +{ + .uFuncSel = AM_HAL_PIN_7_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC = +{ + .uFuncSel = AM_HAL_PIN_15_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC = +{ + .uFuncSel = AM_HAL_PIN_17_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK = +{ + .uFuncSel = AM_HAL_PIN_19_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT = +{ + .uFuncSel = AM_HAL_PIN_10_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_11_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_12_PDMCLK +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labeled STAT. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_23_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_22_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..712c70bb10 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_DK/bsp/am_bsp_pins.h @@ -0,0 +1,688 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D0 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D1 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D2 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D3 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D4 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D6 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D7 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 17 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_INT 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labeled STAT. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h new file mode 100644 index 0000000000..05ef59dc7b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/PinNames.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D4 = 4, + D5 = 5, + D6 = 6, + D7 = 7, + D8 = 8, + D9 = 9 + D10 = 10, + D11 = 11, + D12 = 12, + D13 = 13, + D14 = 14, + D15 = 15, + D16 = 16, + D17 = 17, + D18 = 18, + D19 = 19, + D20 = 20, + D21 = 21, + D22 = 22, + D23 = 23, + D24 = 24, + D25 = 25, + D26 = 26, + D27 = 27, + D28 = 28, + D29 = 29, + // D30 = NC + D31 = 31, + D32 = 32, + D33 = 33, + D34 = 34, + D35 = 35, + D36 = 36, + D37 = 37, + D38 = 38, + D39 = 39, + D40 = 40, + D41 = 41, + D42 = 42, + D43 = 43, + D44 = 44, + D45 = 45, + + // Analog naming + A11 = D11, + A12 = D12, + A13 = D13, + A16 = D16, + A29 = D29, + A31 = D31, + A32 = D32, + A33 = D33, + A34 = D34, + A35 = D35, + + // Not connected + NC = NC_VAL +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c new file mode 100644 index 0000000000..f1586a4de7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.c @@ -0,0 +1,1026 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = {0}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h new file mode 100644 index 0000000000..b7c8952cd2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp.h @@ -0,0 +1,186 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#undef AM_BSP_NUM_LEDS +#ifdef AM_BSP_NUM_LEDS +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; +#endif // AM_BSP_NUM_LEDS + + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..f2533e8676 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.c @@ -0,0 +1,819 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..ab71bdd6f7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_MODULE/bsp/am_bsp_pins.h @@ -0,0 +1,552 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h new file mode 100644 index 0000000000..dcb283dc30 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/PinNames.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 13, + D1 = 33, + D2 = 11, + D3 = 29, + D4 = 18, + D5 = 31, + D6 = 43, + D7 = 42, + D8 = 38, + D9 = 39, + D10 = 40, + D11 = 5, + D12 = 7, + D13 = 6, + D14 = 35, + D15 = 32, + D16 = 12, + + // Analog naming + A0 = D0, + A1 = D1, + A2 = D2, + A3 = D3, + A5 = D5, + A14 = D14, + A15 = D15, + A16 = D16, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D8, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + I2C1_SCL = AM_BSP_GPIO_IOM3_SCL, + I2C1_SDA = AM_BSP_GPIO_IOM3_SDA, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D9, + SERIAL1_RX = D10, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c new file mode 100644 index 0000000000..50dd4ab751 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h new file mode 100644 index 0000000000..4c1a0aec82 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp.h @@ -0,0 +1,255 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 2 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM2_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM2_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM2_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM2_SCL + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED19 AM_BSP_GPIO_LED_BLUE + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The RedBoard Artemis Nano LED is pad 19 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 1 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB1C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..b733343cd7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.c @@ -0,0 +1,861 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 19. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_19_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..25284be900 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_NANO/bsp/am_bsp_pins.h @@ -0,0 +1,584 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 19. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h new file mode 100644 index 0000000000..91a299b551 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/PinNames.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D0 = 25, + D1 = 24, + D2 = 44, + D3 = 35, + D4 = 4, + D5 = 22, + D6 = 23, + D7 = 27, + D8 = 28, + D9 = 32, + D10 = 14, + D11 = 7, + D12 = 6, + D13 = 5, + D14 = 40, + D15 = 39, + D16 = 43, + D17 = 42, + D18 = 26, + D19 = 33, + D20 = 13, + D21 = 11, + D22 = 29, + D23 = 12, + D24 = 31, + + // Analog naming + A0 = D19, + A1 = D20, + A2 = D21, + A3 = D22, + A4 = D23, + A5 = D24, + A6 = D3, + + //BUTTONs + SW1 = AM_BSP_GPIO_BUTTON0, + + // LEDs + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = D2, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + SERIAL1_TX = D1, + SERIAL1_RX = D0, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.c new file mode 100644 index 0000000000..50dd4ab751 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.c @@ -0,0 +1,1063 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.h new file mode 100644 index 0000000000..36c8593d6a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp.h @@ -0,0 +1,267 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 0 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM0_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM0_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM0_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM0_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM0_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM0_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// Button definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_BUTTONS 1 +extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + +#define AM_BSP_GPIO_BUTTON10 AM_BSP_GPIO_BUTTON0 +#define AM_BSP_GPIO_SWCH AM_BSP_GPIO_BUTTON0 + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED18 AM_BSP_GPIO_LED_BLUE + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The Artemis Thing Plus PWM LED is pad 26 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 0 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB0C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..470fe84596 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.c @@ -0,0 +1,874 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_26_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// BUTTON0 pin: Labeled 10 on the Artemis Thing Plus. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON0 = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..b7d4b0fbd3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_ARTEMIS_THING_PLUS/bsp/am_bsp_pins.h @@ -0,0 +1,592 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// BUTTON0 pin: Labeled 10 on the Artemis Thing Plus. +// +//***************************************************************************** +#define AM_BSP_GPIO_BUTTON0 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON0; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h new file mode 100644 index 0000000000..fe674b0bee --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/PinNames.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D1 = 1, + D38 = 38, + D36 = 36, + D3 = 3, + + // // Analog naming + // No analog pins + + // mbed buttons + BUTTON1 = AM_BSP_GPIO_BUTTON0, + + // LEDs + LED_RED = AM_BSP_GPIO_LED_RED, + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + LED_GREEN = AM_BSP_GPIO_LED_GREEN, + LED_YELLOW = AM_BSP_GPIO_LED_YELLOW, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = AM_BSP_GPIO_LED1, + LED3 = AM_BSP_GPIO_LED2, + LED4 = AM_BSP_GPIO_LED3, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + // The SFE_EDGE does not expose a complete IOM peripheral for SPI + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.c new file mode 100644 index 0000000000..75f7aadef2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.c @@ -0,0 +1,1066 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED1, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED2, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED3, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M} +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.h new file mode 100644 index 0000000000..1aa2bc5e69 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp.h @@ -0,0 +1,290 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Camera +// +//***************************************************************************** +#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 13 +#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1 +#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define g_AM_BSP_CAMERA_HM01B0_I2C_SDA g_AM_BSP_GPIO_IOM1_SDA +#define g_AM_BSP_CAMERA_HM01B0_I2C_SCL g_AM_BSP_GPIO_IOM1_SCL +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 0 +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERB + +//***************************************************************************** +// +// Accelerometer. +// +//***************************************************************************** +#define AM_BSP_ACCELEROMETER_I2C_IOM 3 +#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19 +#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM3_SDA +#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM3_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM3_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM3_SDA +#define AM_BSP_ACCELEROMETER_INT1_PIN 17 +#define AM_BSP_ACCELEROMETER_INT2_PIN 0 + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +// The SparkFun Edge does not have a complete IOMaster broken out + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +//***************************************************************************** +// +// Button definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_BUTTONS 1 +extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + +#define AM_BSP_GPIO_BUTTON0 AM_BSP_GPIO_BUTTON14 + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 4 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED1 1 +#define AM_BSP_LED2 2 +#define AM_BSP_LED3 3 + +#define AM_BSP_LED_RED AM_BSP_LED0 +#define AM_BSP_LED_BLUE AM_BSP_LED1 +#define AM_BSP_LED_GREEN AM_BSP_LED2 +#define AM_BSP_LED_YELLOW AM_BSP_LED3 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED1 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED2 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED3 AM_BSP_GPIO_LED_YELLOW + +#define AM_BSP_GPIO_LED46 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED44 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED47 AM_BSP_GPIO_LED_YELLOW + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The Edge LED0 is pin 46 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 6 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERA +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERA6C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..fc0d917812 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.c @@ -0,0 +1,1073 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0 = +{ + .uFuncSel = AM_HAL_PIN_24_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1 = +{ + .uFuncSel = AM_HAL_PIN_25_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2 = +{ + .uFuncSel = AM_HAL_PIN_26_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3 = +{ + .uFuncSel = AM_HAL_PIN_27_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4 = +{ + .uFuncSel = AM_HAL_PIN_28_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5 = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6 = +{ + .uFuncSel = AM_HAL_PIN_6_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7 = +{ + .uFuncSel = AM_HAL_PIN_7_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC = +{ + .uFuncSel = AM_HAL_PIN_15_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC = +{ + .uFuncSel = AM_HAL_PIN_22_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK = +{ + .uFuncSel = AM_HAL_PIN_23_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG = +{ + .uFuncSel = AM_HAL_PIN_12_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT = +{ + .uFuncSel = AM_HAL_PIN_4_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN = +{ + .uFuncSel = AM_HAL_PIN_10_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// MIC0 pin: Analog microphone near camera connector. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC0 = +{ + .uFuncSel = AM_HAL_PIN_11_ADCSE2 +}; + +//***************************************************************************** +// +// MIC1 pin: Analog microphone near LEDs. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC1 = +{ + .uFuncSel = AM_HAL_PIN_29_ADCSE1 +}; + +//***************************************************************************** +// +// BUTTON14 pin: Labeled 14 on the SparkFun Edge. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON14 = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 46. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED = +{ + .uFuncSel = AM_HAL_PIN_46_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 37. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_37_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 44. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN = +{ + .uFuncSel = AM_HAL_PIN_44_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 47. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW = +{ + .uFuncSel = AM_HAL_PIN_47_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..4245ffe1a4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE/bsp/am_bsp_pins.h @@ -0,0 +1,728 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D0 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D1 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D2 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D3 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D4 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D6 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D7 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_INT 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN; + +//***************************************************************************** +// +// MIC0 pin: Analog microphone near camera connector. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC0 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC0; + +//***************************************************************************** +// +// MIC1 pin: Analog microphone near LEDs. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC1 29 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC1; + +//***************************************************************************** +// +// BUTTON14 pin: Labeled 14 on the SparkFun Edge. +// +//***************************************************************************** +#define AM_BSP_GPIO_BUTTON14 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BUTTON14; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 46. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_RED 46 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 37. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 44. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_GREEN 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 47. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_YELLOW 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h new file mode 100644 index 0000000000..d6f6656dd0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/PinNames.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "am_bsp.h" +#include "objects_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NC_VAL (int)0xFFFFFFFF + +typedef enum +{ + // Digital naming + D16 = 16, + D31 = 31, + D45 = 45, + D44 = 44, + + // Analog naming + A16 = D16, + A31 = D31, + + // LEDs + LED_RED = AM_BSP_GPIO_LED_RED, + LED_BLUE = AM_BSP_GPIO_LED_BLUE, + LED_GREEN = AM_BSP_GPIO_LED_GREEN, + LED_YELLOW = AM_BSP_GPIO_LED_BLUE, + + // mbed original LED naming + LED1 = AM_BSP_GPIO_LED0, + LED2 = AM_BSP_GPIO_LED1, + LED3 = AM_BSP_GPIO_LED2, + LED4 = AM_BSP_GPIO_LED3, + + // LED naming by digital pin number + LED19 = AM_BSP_GPIO_LED19, + LED18 = AM_BSP_GPIO_LED18, + LED17 = AM_BSP_GPIO_LED17, + LED37 = AM_BSP_GPIO_LED37, + + // I2C + I2C_SCL = AM_BSP_QWIIC_I2C_SCL_PIN, + I2C_SDA = AM_BSP_QWIIC_I2C_SDA_PIN, + + // Qwiic + QWIIC_SCL = I2C_SCL, + QWIIC_SDA = I2C_SDA, + + // SPI + SPI_CLK = AM_BSP_PRIM_SPI_CLK_PIN, + SPI_SDO = AM_BSP_PRIM_SPI_SDO_PIN, + SPI_SDI = AM_BSP_PRIM_SPI_SDI_PIN, + + // UART + SERIAL_TX = AM_BSP_PRIM_UART_TX_PIN, + SERIAL_RX = AM_BSP_PRIM_UART_RX_PIN, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + // Not connected + NC = NC_VAL +} PinName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c new file mode 100644 index 0000000000..75f7aadef2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.c @@ -0,0 +1,1066 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED1, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED2, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, + {AM_BSP_GPIO_LED3, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M} +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.h new file mode 100644 index 0000000000..b1f646f62b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp.h @@ -0,0 +1,302 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_fpga_bsp BSP for the Apollo3 Hotshot FPGA +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Camera +// +//***************************************************************************** +#define AM_BSP_CAMERA_HM01B0_MCLK_PIN 26 +#define AM_BSP_CAMERA_HM01B0_I2C_IOM 1 +#define AM_BSP_CAMERA_HM01B0_I2C_SDA_PIN AM_BSP_GPIO_IOM1_SDA +#define AM_BSP_CAMERA_HM01B0_I2C_SCL_PIN AM_BSP_GPIO_IOM1_SCL +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_MOD 0 +#define AM_BSP_CAMERA_HM01B0_MCLK_GEN_SEG AM_HAL_CTIMER_TIMERB + +//***************************************************************************** +// +// PDM Microphone +// +//***************************************************************************** +#define AM_BSP_PDM_CHANNEL AM_HAL_PDM_CHANNEL_RIGHT +#define AM_BSP_PDM_DATA_PIN AM_BSP_GPIO_MIC_DATA +#define AM_BSP_PDM_CLOCK_PIN AM_BSP_GPIO_MIC_CLK +#define g_AM_BSP_PDM_DATA g_AM_BSP_GPIO_MIC_DATA +#define g_AM_BSP_PDM_CLOCK g_AM_BSP_GPIO_MIC_CLK + +//***************************************************************************** +// +// Accelerometer. +// +//***************************************************************************** +#define AM_BSP_ACCELEROMETER_I2C_IOM 3 +#define AM_BSP_ACCELEROMETER_I2C_ADDRESS 0x19 +#define AM_BSP_ACCELEROMETER_I2C_SDA_PIN AM_BSP_GPIO_IOM3_SDA +#define AM_BSP_ACCELEROMETER_I2C_SCL_PIN AM_BSP_GPIO_IOM3_SCL +#define g_AM_BSP_ACCELEROMETER_I2C_SDA g_AM_BSP_GPIO_IOM3_SDA +#define g_AM_BSP_ACCELEROMETER_I2C_SCL g_AM_BSP_GPIO_IOM3_SCL + + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +// Note: Edge2 can use SPI via the Qwiic connector and GPIO 44 +#define AM_BSP_PRIM_SPI_IOM 4 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_IOM4_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_IOM4_MOSI +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_IOM4_MISO +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_IOM4_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_IOM4_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_IOM4_SDI + + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + + +//***************************************************************************** +// +// Qwiic Connector. +// +//***************************************************************************** +#define AM_BSP_QWIIC_I2C_IOM 4 +#define AM_BSP_QWIIC_I2C_SDA_PIN AM_BSP_GPIO_IOM4_SDA +#define AM_BSP_QWIIC_I2C_SCL_PIN AM_BSP_GPIO_IOM4_SCL +#define g_AM_BSP_QWIIC_I2C_SDA g_AM_BSP_GPIO_IOM4_SDA +#define g_AM_BSP_QWIIC_I2C_SCL g_AM_BSP_GPIO_IOM4_SCL + + +// //***************************************************************************** +// // +// // Button definitions. +// // +// //***************************************************************************** +// #define AM_BSP_NUM_BUTTONS 0 +// extern am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS]; + + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 4 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED1 1 +#define AM_BSP_LED2 2 +#define AM_BSP_LED3 3 + +#define AM_BSP_LED_RED AM_BSP_LED0 +#define AM_BSP_LED_BLUE AM_BSP_LED1 +#define AM_BSP_LED_GREEN AM_BSP_LED2 +#define AM_BSP_LED_YELLOW AM_BSP_LED3 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED1 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED2 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED3 AM_BSP_GPIO_LED_YELLOW + +#define AM_BSP_GPIO_LED19 AM_BSP_GPIO_LED_RED +#define AM_BSP_GPIO_LED18 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED17 AM_BSP_GPIO_LED_GREEN +#define AM_BSP_GPIO_LED37 AM_BSP_GPIO_LED_YELLOW + + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The Edge2 LED0 is pin 19 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 1 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB1C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.c new file mode 100644 index 0000000000..b657a7edcb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.c @@ -0,0 +1,1061 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0 = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1 = +{ + .uFuncSel = AM_HAL_PIN_11_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2 = +{ + .uFuncSel = AM_HAL_PIN_25_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3 = +{ + .uFuncSel = AM_HAL_PIN_34_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4 = +{ + .uFuncSel = AM_HAL_PIN_6_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5 = +{ + .uFuncSel = AM_HAL_PIN_5_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6 = +{ + .uFuncSel = AM_HAL_PIN_35_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7 = +{ + .uFuncSel = AM_HAL_PIN_28_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC = +{ + .uFuncSel = AM_HAL_PIN_15_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC = +{ + .uFuncSel = AM_HAL_PIN_27_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK = +{ + .uFuncSel = AM_HAL_PIN_7_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG = +{ + .uFuncSel = AM_HAL_PIN_13_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT = +{ + .uFuncSel = AM_HAL_PIN_23_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN = +{ + .uFuncSel = AM_HAL_PIN_32_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_29_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_12_PDMCLK +}; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 19. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED = +{ + .uFuncSel = AM_HAL_PIN_19_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_18_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 17. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN = +{ + .uFuncSel = AM_HAL_PIN_17_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 37. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW = +{ + .uFuncSel = AM_HAL_PIN_37_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO = +{ + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.h new file mode 100644 index 0000000000..23b3ea328d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TARGET_SFE_EDGE2/bsp/am_bsp_pins.h @@ -0,0 +1,720 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CAMERA_HM01B0_D0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D0 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D0; + +//***************************************************************************** +// +// CAMERA_HM01B0_D1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D1 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D1; + +//***************************************************************************** +// +// CAMERA_HM01B0_D2 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D2 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D2; + +//***************************************************************************** +// +// CAMERA_HM01B0_D3 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D3 34 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D3; + +//***************************************************************************** +// +// CAMERA_HM01B0_D4 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D4 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D4; + +//***************************************************************************** +// +// CAMERA_HM01B0_D5 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D5 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D5; + +//***************************************************************************** +// +// CAMERA_HM01B0_D6 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D6 35 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D6; + +//***************************************************************************** +// +// CAMERA_HM01B0_D7 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_D7 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_D7; + +//***************************************************************************** +// +// CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC; + +//***************************************************************************** +// +// CAMERA_HM01B0_PCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK; + +//***************************************************************************** +// +// CAMERA_HM01B0_TRIG pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG; + +//***************************************************************************** +// +// CAMERA_HM01B0_INT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_INT 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_INT; + +//***************************************************************************** +// +// CAMERA_HM01B0_DVDDEN pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN 32 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 29 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// LED_RED pin: The RED LED labelled 19. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_RED 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_RED; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labelled 18. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 18 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// LED_GREEN pin: The GREEN LED labelled 17. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_GREEN 17 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_GREEN; + +//***************************************************************************** +// +// LED_YELLOW pin: The YELLOW LED labelled 37. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_YELLOW 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_YELLOW; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AM_BSP_GPIO_ITM_SWO 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_ITM_SWO; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct new file mode 100644 index 0000000000..2ae349928a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/AMA3B1KK.sct @@ -0,0 +1,55 @@ +#! armcc -E + +; +; Copyright (c) 2019-2020 SparkFun Electronics +; SPDX-License-Identifier: MIT +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; + + +#define MBED_APP_START 0x0000C000 +#define MBED_APP_SIZE 0x000F4000 +#define MBED_RAM_START 0x10000000 +#define MBED_RAM_SIZE 0x60000 +#define MBED_RAM0_START MBED_RAM_START +#define MBED_RAM0_SIZE 0x100 +#define MBED_RAM1_START (MBED_RAM0_START + MBED_RAM0_SIZE) +#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE)) +#define Stack_Size MBED_BOOT_STACK_SIZE +#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+MBED_RAM0_SIZE) + + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM0 MBED_RAM0_START UNINIT MBED_RAM0_SIZE { ;no init section + *(*nvictable) + } + RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { + .ANY (+RW +ZI) + } + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { + } + ARM_LIB_STACK MBED_RAM1_START+MBED_RAM1_SIZE-8 EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S new file mode 100644 index 0000000000..ccfea3ae73 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_ARM_STD/startup_keil.S @@ -0,0 +1,345 @@ +;****************************************************************************** +; +;! @file startup_keil.s +;! +;! @brief Definitions for Apollo3 interrupt handlers, the vector table, and the stack. +; +;****************************************************************************** + +;****************************************************************************** +; +; Copyright (c) 2020, Ambiq Micro +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; Third party software included in this distribution is subject to the +; additional license terms as defined in the /docs/licenses directory. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +; This is part of revision 2.4.2 of the AmbiqSuite Development Package. +; +;****************************************************************************** +; SPDX-License-Identifier: BSD-3-Clause + + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** +; +; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +; am_usagefault_isr does not work if am_fault_isr is defined externally. +; Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +; + + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; The MPU fault handler + DCD BusFault_Handler ; The bus fault handler + DCD UsageFault_Handler ; The usage fault handler + DCD SecureFault_Handler ; Secure fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug monitor handler + DCD 0 ; Reserved + DCD PendSV_Handler ; The PendSV handler + DCD SysTick_Handler ; The SysTick handler + + ; + ; Peripheral Interrupts + ; + DCD am_brownout_isr ; 0: Reserved + DCD am_watchdog_isr ; 1: Reserved + DCD am_rtc_isr ; 2: RTC + DCD am_vcomp_isr ; 3: Voltage Comparator + DCD am_ioslave_ios_isr ; 4: I/O Slave general + DCD am_ioslave_acc_isr ; 5: I/O Slave access + DCD am_iomaster0_isr ; 6: I/O Master 0 + DCD am_iomaster1_isr ; 7: I/O Master 1 + DCD am_iomaster2_isr ; 8: I/O Master 2 + DCD am_iomaster3_isr ; 9: I/O Master 3 + DCD am_iomaster4_isr ; 10: I/O Master 4 + DCD am_iomaster5_isr ; 11: I/O Master 5 + DCD HciDrvIntService ; 12: BLEIF + DCD am_gpio_isr ; 13: GPIO + DCD am_ctimer_isr ; 14: CTIMER + DCD am_uart_isr ; 15: UART0 + DCD am_uart1_isr ; 16: UART1 + DCD am_scard_isr ; 17: SCARD + DCD am_adc_isr ; 18: ADC + DCD am_pdm0_isr ; 19: PDM + DCD am_mspi0_isr ; 20: MSPI0 + DCD am_software0_isr ; 21: SOFTWARE0 + DCD am_stimer_isr ; 22: SYSTEM TIMER + DCD am_stimer_cmpr0_isr ; 23: SYSTEM TIMER COMPARE0 + DCD am_stimer_cmpr1_isr ; 24: SYSTEM TIMER COMPARE1 + DCD am_stimer_cmpr2_isr ; 25: SYSTEM TIMER COMPARE2 + DCD am_stimer_cmpr3_isr ; 26: SYSTEM TIMER COMPARE3 + DCD am_stimer_cmpr4_isr ; 27: SYSTEM TIMER COMPARE4 + DCD am_stimer_cmpr5_isr ; 28: SYSTEM TIMER COMPARE5 + DCD am_stimer_cmpr6_isr ; 29: SYSTEM TIMER COMPARE6 + DCD am_stimer_cmpr7_isr ; 30: SYSTEM TIMER COMPARE7 + DCD am_clkgen_isr ; 31: CLKGEN + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;****************************************************************************** +; +; Place code immediately following vector table. +; +;****************************************************************************** +;****************************************************************************** +; +; The Patch table. +; +; The patch table should pad the vector table size to a total of 64 entries +; (16 core + 48 periph) such that code begins at offset 0x100. +; +;****************************************************************************** + EXPORT __Patchable +__Patchable + DCD 0 ; 32 + DCD 0 ; 33 + DCD 0 ; 34 + DCD 0 ; 35 + DCD 0 ; 36 + DCD 0 ; 37 + DCD 0 ; 38 + DCD 0 ; 39 + DCD 0 ; 40 + DCD 0 ; 41 + DCD 0 ; 42 + DCD 0 ; 43 + DCD 0 ; 44 + DCD 0 ; 45 + DCD 0 ; 46 + DCD 0 ; 47 + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; + ; Enable the FPU. + ; + MOVW R0, #0xED88 + MOVT R0, #0xE000 + LDR R1, [R0] + ORR R1, #0x00F00000 + STR R1, [R0] + DSB + ISB + + ; + ; Branch to main. + ; + LDR R0, =__main + BX R0 + + ENDP + +;****************************************************************************** +; +; Weak Exception Handlers. +; +;****************************************************************************** + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SecureFault_Handler\ + PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +am_default_isr\ + PROC + EXPORT am_brownout_isr [WEAK] + EXPORT am_watchdog_isr [WEAK] + EXPORT am_rtc_isr [WEAK] + EXPORT am_vcomp_isr [WEAK] + EXPORT am_ioslave_ios_isr [WEAK] + EXPORT am_ioslave_acc_isr [WEAK] + EXPORT am_iomaster0_isr [WEAK] + EXPORT am_iomaster1_isr [WEAK] + EXPORT am_iomaster2_isr [WEAK] + EXPORT am_iomaster3_isr [WEAK] + EXPORT am_iomaster4_isr [WEAK] + EXPORT am_iomaster5_isr [WEAK] + EXPORT HciDrvIntService [WEAK] + EXPORT am_gpio_isr [WEAK] + EXPORT am_ctimer_isr [WEAK] + EXPORT am_uart_isr [WEAK] + EXPORT am_uart0_isr [WEAK] + EXPORT am_uart1_isr [WEAK] + EXPORT am_scard_isr [WEAK] + EXPORT am_adc_isr [WEAK] + EXPORT am_pdm0_isr [WEAK] + EXPORT am_mspi0_isr [WEAK] + EXPORT am_software0_isr [WEAK] + EXPORT am_stimer_isr [WEAK] + EXPORT am_stimer_cmpr0_isr [WEAK] + EXPORT am_stimer_cmpr1_isr [WEAK] + EXPORT am_stimer_cmpr2_isr [WEAK] + EXPORT am_stimer_cmpr3_isr [WEAK] + EXPORT am_stimer_cmpr4_isr [WEAK] + EXPORT am_stimer_cmpr5_isr [WEAK] + EXPORT am_stimer_cmpr6_isr [WEAK] + EXPORT am_stimer_cmpr7_isr [WEAK] + EXPORT am_clkgen_isr [WEAK] + +am_brownout_isr +am_watchdog_isr +am_rtc_isr +am_vcomp_isr +am_ioslave_ios_isr +am_ioslave_acc_isr +am_iomaster0_isr +am_iomaster1_isr +am_iomaster2_isr +am_iomaster3_isr +am_iomaster4_isr +am_iomaster5_isr +HciDrvIntService +am_gpio_isr +am_ctimer_isr +am_uart_isr +am_uart0_isr +am_uart1_isr +am_scard_isr +am_adc_isr +am_pdm0_isr +am_mspi0_isr +am_software0_isr +am_stimer_isr +am_stimer_cmpr0_isr +am_stimer_cmpr1_isr +am_stimer_cmpr2_isr +am_stimer_cmpr3_isr +am_stimer_cmpr4_isr +am_stimer_cmpr5_isr +am_stimer_cmpr6_isr +am_stimer_cmpr7_isr +am_clkgen_isr + + ; all device interrupts go here unless the weak label is over + ; ridden in the linker hard spin so the debugger will know it + ; was an unhandled interrupt request a come-from-buffer or + ; instruction trace hardware would sure be nice if you get here + B . + + ENDP + + + +;****************************************************************************** +; +; Align the end of the section. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; All Done +; +;****************************************************************************** + END + + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld new file mode 100644 index 0000000000..8445c55e80 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/AMA3B1KK.ld @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2019-2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +/* stack: dynamic */ +/* heap: dynamic */ +#define MBED_APP_START 0x0000C000 +#define MBED_APP_LENGTH 0x000F4000 +#define MBED_RAM_START 0x10000000 +#define MBED_RAM_SIZE 384K +#define MBED_BOOT_STACK_SIZE 0x400 +#define MBED_RAM0_START MBED_RAM_START +#define MBED_RAM0_SIZE 0x100 +#define MBED_RAM1_START (MBED_RAM0_START + MBED_RAM0_SIZE) +#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE)) + +ENTRY(Reset_Handler) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_LENGTH /*Modified from 0xC000 to work with SparkFun SVL*/ + RAM_NVIC (rwx) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE + RAM (rwx) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE +} + +SECTIONS +{ + /* text: executable code */ + /* located in _flash_ */ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) + KEEP(*(.ble_patch)) + *(.text) + *(.text*) + +/* __init_array_start = .; + KEEP(*(.init_array*)) + __init_array_end = .; */ /* does this mess up _init()?' it was from Arduinoland (aka owen) */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* .rodata */ + . = ALIGN(4); + *(.rodata) + *(.rodata*) + + KEEP(*(.eh_frame*)) + + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = ALIGN(8); + + .data : AT (__etext) + { + __data_start__ = .; + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + + /* bss: zero-initialized symbols */ + /* don't require flash memory to remember their value */ + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(8); + _ebss = .; + __bss_end__ = .; + } > RAM + + /* heap: RAM memory that can be dynamically allocated in the upward direction (increasing memory addresses) */ + /* _sheap is used to identify the beginning of available dynamic memory */ + .heap (NOLOAD): + { + . = ALIGN(4); + __end__ = .; + PROVIDE( end = . ); + _sheap = .; + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE-8; + __HeapLimit = .; + } >RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later*/ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + *(.stack*) + } > RAM + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section*/ + __StackTop = ORIGIN(RAM) + LENGTH(RAM)-8; + __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + PROVIDE(_sstack = __StackTop); + /* Check if data + heap + stack exceeds RAM limit*/ + /*ASSERT(1, "region RAM overflowed with stack")*/ + /* test test test */ +} \ No newline at end of file diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c new file mode 100644 index 0000000000..8e6da1257c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/TOOLCHAIN_GCC_ARM/startup_gcc.c @@ -0,0 +1,347 @@ +//***************************************************************************** +// +//! @file startup_gcc.c +//! +//! @brief Definitions for interrupt handlers, the vector table, and the stack. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "apollo3.h" +#include + +//***************************************************************************** +// +// Forward declaration of interrupt handlers. +// +//***************************************************************************** +extern void Reset_Handler(void) __attribute((naked)); +extern void NMI_Handler(void) __attribute((weak)); +extern void HardFault_Handler(void) __attribute((weak)); +extern void MemManage_Handler(void) __attribute((weak, alias("HardFault_Handler"))); +extern void BusFault_Handler(void) __attribute((weak, alias("HardFault_Handler"))); +extern void UsageFault_Handler(void) __attribute((weak, alias("HardFault_Handler"))); +extern void SecureFault_Handler(void) __attribute((weak)); +extern void SVC_Handler(void) __attribute((weak, alias("am_default_isr"))); +extern void DebugMon_Handler(void) __attribute((weak, alias("am_default_isr"))); +extern void PendSV_Handler(void) __attribute((weak, alias("am_default_isr"))); +extern void SysTick_Handler(void) __attribute((weak, alias("am_default_isr"))); + +extern void am_brownout_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_watchdog_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_rtc_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_vcomp_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_ioslave_ios_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_ioslave_acc_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster1_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster2_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster3_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster4_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_iomaster5_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void HciDrvIntService(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_gpio_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_ctimer_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_uart_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_uart1_isr(void); //__attribute((weak, alias("am_default_isr"))); +extern void am_scard_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_adc_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_pdm0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_mspi0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_software0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr0_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr1_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr2_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr3_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr4_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr5_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr6_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_stimer_cmpr7_isr(void) __attribute((weak, alias("am_default_isr"))); +extern void am_clkgen_isr(void) __attribute((weak, alias("am_default_isr"))); + +extern void am_default_isr(void) __attribute((weak)); + +// // Entry Point for mbed boot sequence +// extern void __main(void); +// extern void _start(void); +extern void mbed_init(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +// '__stack' accesses the linker-provided address for the start of the stack +// (which is a high address - stack goes top to bottom) +extern void *__stack; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +// am_usagefault_isr does not work if am_fault_isr is defined externally. +// Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +// +//***************************************************************************** +__attribute__((section(".isr_vector"))) void (*const g_am_pfnVectors[])(void) = + { + (void (*)(void))(&__stack), // The initial stack pointer (provided by linker script) + Reset_Handler, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MemManage_Handler + BusFault_Handler, // The BusFault_Handler + UsageFault_Handler, // The UsageFault_Handler + SecureFault_Handler, // The SecureFault_Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // + // Peripheral Interrupts + // + am_brownout_isr, // 0: Brownout (rstgen) + am_watchdog_isr, // 1: Watchdog + am_rtc_isr, // 2: RTC + am_vcomp_isr, // 3: Voltage Comparator + am_ioslave_ios_isr, // 4: I/O Slave general + am_ioslave_acc_isr, // 5: I/O Slave access + am_iomaster0_isr, // 6: I/O Master 0 + am_iomaster1_isr, // 7: I/O Master 1 + am_iomaster2_isr, // 8: I/O Master 2 + am_iomaster3_isr, // 9: I/O Master 3 + am_iomaster4_isr, // 10: I/O Master 4 + am_iomaster5_isr, // 11: I/O Master 5 + HciDrvIntService, // 12: BLEIF + am_gpio_isr, // 13: GPIO + am_ctimer_isr, // 14: CTIMER + am_uart_isr, // 15: UART0 + am_uart1_isr, // 16: UART1 + am_scard_isr, // 17: SCARD + am_adc_isr, // 18: ADC + am_pdm0_isr, // 19: PDM + am_mspi0_isr, // 20: MSPI0 + am_software0_isr, // 21: SOFTWARE0 + am_stimer_isr, // 22: SYSTEM TIMER + am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0 + am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1 + am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2 + am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3 + am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4 + am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5 + am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6 + am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7 + am_clkgen_isr, // 31: CLKGEN +}; + +//****************************************************************************** +// +// Place code immediately following vector table. +// +//****************************************************************************** +//****************************************************************************** +// +// The Patch table. +// +// The patch table should pad the vector table size to a total of 64 entries +// (16 core + 48 periph) such that code begins at offset 0x100. +// +//****************************************************************************** +__attribute__((section(".ble_patch"))) +uint32_t const __Patchable[] = + { + 0, // 32 + 0, // 33 + 0, // 34 + 0, // 35 + 0, // 36 + 0, // 37 + 0, // 38 + 0, // 39 + 0, // 40 + 0, // 41 + 0, // 42 + 0, // 43 + 0, // 44 + 0, // 45 + 0, // 46 + 0, // 47 +}; + +// //***************************************************************************** +// // +// // The following are constructs created by the linker, indicating where the +// // the "data" and "bss" segments reside in memory. The initializers for the +// // "data" segment resides immediately following the "text" segment. +// // +// //***************************************************************************** +// extern uint32_t _etext; +// extern uint32_t __data_start__; +// extern uint32_t __data_end__; +// extern uint32_t _sbss; +// extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. +// +//***************************************************************************** +#if defined(__GNUC_STDC_INLINE__) +void Reset_Handler(void) +{ + // + // Set the vector table pointer. + // + __asm(" ldr r0, =0xE000ED08\n" + " ldr r1, =g_am_pfnVectors\n" + " str r1, [r0]"); + + // // + // // Set the stack pointer. + // // + __asm(" ldr sp, [r1]"); + +#ifndef NOFPU + // // + // // Enable the FPU. + // // + __asm("ldr r0, =0xE000ED88\n" + "ldr r1,[r0]\n" + "orr r1,#(0xF << 20)\n" + "str r1,[r0]\n" + "dsb\n" + "isb\n"); +#endif + + // // Start mbed boot sequence https://os.mbed.com/docs/mbed-os/v5.15/reference/bootstrap.html + // SystemInit(); + // _start(); + + // + // Copy the data segment initializers from flash to SRAM. + // + __asm(" ldr r0, =__etext\n" + " ldr r1, =__data_start__\n" + " ldr r2, =__data_end__\n" + "copy_loop:\n" + " cmp r1, r2\n" + " beq copy_end\n" + " ldr r3, [r0], #4\n" + " str r3, [r1], #4\n" + " b copy_loop\n" + "copy_end:\n"); + + // // + // // Zero fill the bss segment. + // // + __asm("LDR R0, =_start\n" + "BX R0\n"); + // + // If main returns then execute a break point instruction + // + __asm(" bkpt "); +} +#else +#error GNU STDC inline not supported. +#endif + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +void NMI_Handler(void) +{ + // + // Go into an infinite loop. + // + while (1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void HardFault_Handler(void) +{ + // + // Go into an infinite loop. + // + while (1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void am_default_isr(void) +{ + // + // Go into an infinite loop. + // + while (1) + { + } +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h new file mode 100644 index 0000000000..4c3a534e2d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralNames.h @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define STDIO_UART UART_0 + +typedef enum { + UART_0 = 0, + UART_1, + + UART_NUM, + UART_ANY +} UARTName; + +typedef enum { + IOM_0 = 0, + IOM_1, + IOM_2, + IOM_3, + IOM_4, + IOM_5, + + IOM_NUM, + IOM_ANY +} IOMName; + +typedef IOMName SPIName; +typedef IOMName I2CName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c new file mode 100644 index 0000000000..c1cfec5e51 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.c @@ -0,0 +1,2219 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_bsp.h" + +//***************************************************************************** +// +// UART0_TX_1 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_1 = { + .uFuncSel = AM_HAL_PIN_1_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_7 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_7 = { + .uFuncSel = AM_HAL_PIN_7_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_16 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_16 = { + .uFuncSel = AM_HAL_PIN_16_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_20 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_20 = { + .uFuncSel = AM_HAL_PIN_20_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_22 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_22 = { + .uFuncSel = AM_HAL_PIN_22_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_26 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_26 = { + .uFuncSel = AM_HAL_PIN_26_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_28 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_28 = { + .uFuncSel = AM_HAL_PIN_28_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_30 pin: UART0 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_30 = { + .uFuncSel = AM_HAL_PIN_30_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_TX_39 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_39 = { + .uFuncSel = AM_HAL_PIN_39_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_41 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_41 = { + .uFuncSel = AM_HAL_PIN_41_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_44 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_44 = { + .uFuncSel = AM_HAL_PIN_44_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_TX_48 pin: UART0 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_48 = { + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_8 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_8 = { + .uFuncSel = AM_HAL_PIN_8_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_10 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_10 = { + .uFuncSel = AM_HAL_PIN_10_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_12 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_12 = { + .uFuncSel = AM_HAL_PIN_12_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_14 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_14 = { + .uFuncSel = AM_HAL_PIN_14_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_18 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_18 = { + .uFuncSel = AM_HAL_PIN_18_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_20 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_20 = { + .uFuncSel = AM_HAL_PIN_20_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_24 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_24 = { + .uFuncSel = AM_HAL_PIN_24_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_35 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_35 = { + .uFuncSel = AM_HAL_PIN_35_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_37 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_37 = { + .uFuncSel = AM_HAL_PIN_37_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_39 pin: UART1 Tx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_39 = { + .uFuncSel = AM_HAL_PIN_39_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_TX_42 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_42 = { + .uFuncSel = AM_HAL_PIN_42_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_46 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_46 = { + .uFuncSel = AM_HAL_PIN_46_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_2 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_2 = { + .uFuncSel = AM_HAL_PIN_2_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_11 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_11 = { + .uFuncSel = AM_HAL_PIN_11_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_17 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_17 = { + .uFuncSel = AM_HAL_PIN_17_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_21 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_21 = { + .uFuncSel = AM_HAL_PIN_21_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_23 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_23 = { + .uFuncSel = AM_HAL_PIN_23_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_27 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_27 = { + .uFuncSel = AM_HAL_PIN_27_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_29 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_29 = { + .uFuncSel = AM_HAL_PIN_29_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_31 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_31 = { + .uFuncSel = AM_HAL_PIN_31_UART0RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_34 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_34 = { + .uFuncSel = AM_HAL_PIN_34_UART0RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_40 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_40 = { + .uFuncSel = AM_HAL_PIN_40_UART0RX +}; + +//***************************************************************************** +// +// UART0_RX_45 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_45 = { + .uFuncSel = AM_HAL_PIN_45_UART0RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_49 pin: UART0 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_49 = { + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// UART1_RX_2 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_2 = { + .uFuncSel = AM_HAL_PIN_2_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_4 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_4 = { + .uFuncSel = AM_HAL_PIN_4_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_9 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_9 = { + .uFuncSel = AM_HAL_PIN_9_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_13 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_13 = { + .uFuncSel = AM_HAL_PIN_13_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_15 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_15 = { + .uFuncSel = AM_HAL_PIN_15_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_19 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_19 = { + .uFuncSel = AM_HAL_PIN_19_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_21 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_21 = { + .uFuncSel = AM_HAL_PIN_21_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_25 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_25 = { + .uFuncSel = AM_HAL_PIN_25_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_36 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_36 = { + .uFuncSel = AM_HAL_PIN_36_UART1RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_38 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_38 = { + .uFuncSel = AM_HAL_PIN_38_UART1RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_40 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_40 = { + .uFuncSel = AM_HAL_PIN_40_UART1RX +}; + +//***************************************************************************** +// +// UART1_RX_43 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_43 = { + .uFuncSel = AM_HAL_PIN_43_UART1RX +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_47 pin: UART1 Rx Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_47 = { + .uFuncSel = AM_HAL_PIN_47_UART1RX +}; + +//***************************************************************************** +// +// UART0_RTS_3 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_3 = { + .uFuncSel = AM_HAL_PIN_3_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_5 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_5 = { + .uFuncSel = AM_HAL_PIN_5_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_13 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_13 = { + .uFuncSel = AM_HAL_PIN_13_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_18 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_18 = { + .uFuncSel = AM_HAL_PIN_18_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_RTS_34 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_34 = { + .uFuncSel = AM_HAL_PIN_34_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_35 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_35 = { + .uFuncSel = AM_HAL_PIN_35_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_37 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_37 = { + .uFuncSel = AM_HAL_PIN_37_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_41 pin: UART0 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_41 = { + .uFuncSel = AM_HAL_PIN_41_UART0RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_10 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_10 = { + .uFuncSel = AM_HAL_PIN_10_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_16 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_16 = { + .uFuncSel = AM_HAL_PIN_16_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_20 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_20 = { + .uFuncSel = AM_HAL_PIN_20_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_30 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_30 = { + .uFuncSel = AM_HAL_PIN_30_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_31 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_31 = { + .uFuncSel = AM_HAL_PIN_31_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_34 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_34 = { + .uFuncSel = AM_HAL_PIN_34_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_41 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_41 = { + .uFuncSel = AM_HAL_PIN_41_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART1_RTS_44 pin: UART1 RTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_44 = { + .uFuncSel = AM_HAL_PIN_44_UART1RTS, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// UART0_CTS_4 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_4 = { + .uFuncSel = AM_HAL_PIN_4_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_6 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_6 = { + .uFuncSel = AM_HAL_PIN_6_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_12 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_12 = { + .uFuncSel = AM_HAL_PIN_12_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_24 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_24 = { + .uFuncSel = AM_HAL_PIN_24_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_29 pin: UART0 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_29 = { + .uFuncSel = AM_HAL_PIN_29_UART0CTS +}; + +//***************************************************************************** +// +// UART0_CTS_33 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_33 = { + .uFuncSel = AM_HAL_PIN_33_UART0CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_36 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_36 = { + .uFuncSel = AM_HAL_PIN_36_UART0CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_38 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_38 = { + .uFuncSel = AM_HAL_PIN_38_UART0CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_11 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_11 = { + .uFuncSel = AM_HAL_PIN_11_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_17 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_17 = { + .uFuncSel = AM_HAL_PIN_17_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_21 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_21 = { + .uFuncSel = AM_HAL_PIN_21_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_26 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_26 = { + .uFuncSel = AM_HAL_PIN_26_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_29 pin: UART1 CTS Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_29 = { + .uFuncSel = AM_HAL_PIN_29_UART1CTS +}; + +//***************************************************************************** +// +// UART1_CTS_32 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_32 = { + .uFuncSel = AM_HAL_PIN_32_UART1CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_36 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_36 = { + .uFuncSel = AM_HAL_PIN_36_UART1CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_45 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_45 = { + .uFuncSel = AM_HAL_PIN_45_UART1CTS +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS = { + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS3 = { + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MISO = { + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MOSI = { + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCK = { + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCL = { + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SDA = { + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_CS = { + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MISO = { + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MOSI = { + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCK = { + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCL = { + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SDA = { + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_CS = { + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MISO = { + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MOSI = { + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCK = { + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCL = { + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SDA = { + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_CS = { + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MISO = { + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MOSI = { + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCK = { + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCL = { + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SDA = { + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_CS = { + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MISO = { + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MOSI = { + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCK = { + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCL = { + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SDA = { + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_CS = { + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MISO = { + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MOSI = { + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCK = { + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCL = { + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SDA = { + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE0 = { + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE1 = { + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D0 = { + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D1 = { + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D2 = { + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D3 = { + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D4 = { + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D5 = { + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D6 = { + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D7 = { + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_SCK = { + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_CE = { + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MISO = { + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MOSI = { + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCK = { + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCL = { + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SDA = { + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// NCE_0 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_0 = { + .uFuncSel = AM_HAL_PIN_0_NCE0 +}; + +//***************************************************************************** +// +// NCE_1 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_1 = { + .uFuncSel = AM_HAL_PIN_1_NCE1 +}; + +//***************************************************************************** +// +// NCE_2 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_2 = { + .uFuncSel = AM_HAL_PIN_2_NCE2 +}; + +//***************************************************************************** +// +// NCE_3 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_3 = { + .uFuncSel = AM_HAL_PIN_3_NCE3 +}; + +//***************************************************************************** +// +// NCE_4 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_4 = { + .uFuncSel = AM_HAL_PIN_4_NCE4 +}; + +//***************************************************************************** +// +// NCE_7 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_7 = { + .uFuncSel = AM_HAL_PIN_7_NCE7 +}; + +//***************************************************************************** +// +// NCE_8 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_8 = { + .uFuncSel = AM_HAL_PIN_8_NCE8 +}; + +//***************************************************************************** +// +// NCE_9 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_9 = { + .uFuncSel = AM_HAL_PIN_9_NCE9 +}; + +//***************************************************************************** +// +// NCE_10 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_10 = { + .uFuncSel = AM_HAL_PIN_10_NCE10 +}; + +//***************************************************************************** +// +// NCE_11 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_11 = { + .uFuncSel = AM_HAL_PIN_11_NCE11 +}; + +//***************************************************************************** +// +// NCE_12 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_12 = { + .uFuncSel = AM_HAL_PIN_12_NCE12 +}; + +//***************************************************************************** +// +// NCE_13 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_13 = { + .uFuncSel = AM_HAL_PIN_13_NCE13 +}; + +//***************************************************************************** +// +// NCE_14 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_14 = { + .uFuncSel = AM_HAL_PIN_14_NCE14 +}; + +//***************************************************************************** +// +// NCE_15 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_15 = { + .uFuncSel = AM_HAL_PIN_15_NCE15 +}; + +//***************************************************************************** +// +// NCE_16 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_16 = { + .uFuncSel = AM_HAL_PIN_16_NCE16 +}; + +//***************************************************************************** +// +// NCE_17 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_17 = { + .uFuncSel = AM_HAL_PIN_17_NCE17 +}; + +//***************************************************************************** +// +// NCE_18 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_18 = { + .uFuncSel = AM_HAL_PIN_18_NCE18 +}; + +//***************************************************************************** +// +// NCE_19 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_19 = { + .uFuncSel = AM_HAL_PIN_19_NCE19 +}; + +//***************************************************************************** +// +// NCE_20 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_20 = { + .uFuncSel = AM_HAL_PIN_20_NCE20 +}; + +//***************************************************************************** +// +// NCE_21 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_21 = { + .uFuncSel = AM_HAL_PIN_21_NCE21 +}; + +//***************************************************************************** +// +// NCE_22 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_22 = { + .uFuncSel = AM_HAL_PIN_22_NCE22 +}; + +//***************************************************************************** +// +// NCE_23 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_23 = { + .uFuncSel = AM_HAL_PIN_23_NCE23 +}; + +//***************************************************************************** +// +// NCE_24 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_24 = { + .uFuncSel = AM_HAL_PIN_24_NCE24 +}; + +//***************************************************************************** +// +// NCE_25 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_25 = { + .uFuncSel = AM_HAL_PIN_25_NCE25 +}; + +//***************************************************************************** +// +// NCE_26 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_26 = { + .uFuncSel = AM_HAL_PIN_26_NCE26 +}; + +//***************************************************************************** +// +// NCE_27 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_27 = { + .uFuncSel = AM_HAL_PIN_27_NCE27 +}; + +//***************************************************************************** +// +// NCE_28 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_28 = { + .uFuncSel = AM_HAL_PIN_28_NCE28 +}; + +//***************************************************************************** +// +// NCE_29 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_29 = { + .uFuncSel = AM_HAL_PIN_29_NCE29 +}; + +//***************************************************************************** +// +// NCE_30 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_30 = { + .uFuncSel = AM_HAL_PIN_30_NCE30 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_31 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_31 = { + .uFuncSel = AM_HAL_PIN_31_NCE31 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_32 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_32 = { + .uFuncSel = AM_HAL_PIN_32_NCE32 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_33 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_33 = { + .uFuncSel = AM_HAL_PIN_33_NCE33 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_34 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_34 = { + .uFuncSel = AM_HAL_PIN_34_NCE34 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_35 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_35 = { + .uFuncSel = AM_HAL_PIN_35_NCE35 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_36 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_36 = { + .uFuncSel = AM_HAL_PIN_36_NCE36 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_37 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_37 = { + .uFuncSel = AM_HAL_PIN_37_NCE37 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_38 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_38 = { + .uFuncSel = AM_HAL_PIN_38_NCE38 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_41 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_41 = { + .uFuncSel = AM_HAL_PIN_41_NCE41 +}; + +//***************************************************************************** +// +// NCE_42 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_42 = { + .uFuncSel = AM_HAL_PIN_42_NCE42 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_43 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_43 = { + .uFuncSel = AM_HAL_PIN_43_NCE43 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_44 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_44 = { + .uFuncSel = AM_HAL_PIN_44_NCE44 +}; + +//***************************************************************************** +// +// NCE_45 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_45 = { + .uFuncSel = AM_HAL_PIN_45_NCE45 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_46 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_46 = { + .uFuncSel = AM_HAL_PIN_46_NCE46 +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_47 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_47 = { + .uFuncSel = AM_HAL_PIN_47_NCE47 +}; + +//***************************************************************************** +// +// NCE_48 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_48 = { + .uFuncSel = AM_HAL_PIN_48_NCE48 +}; + +//***************************************************************************** +// +// NCE_49 pin: NCE Pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_NCE_49 = { + .uFuncSel = AM_HAL_PIN_49_NCE49 +}; + +//***************************************************************************** +// +// PDM_DATA_11 pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_11 = { + .uFuncSel = AM_HAL_PIN_11_PDMDATA +}; + +//***************************************************************************** +// +// PDM_DATA_15 pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_15 = { + .uFuncSel = AM_HAL_PIN_15_PDMDATA +}; + +//***************************************************************************** +// +// PDM_DATA_29 pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_29 = { + .uFuncSel = AM_HAL_PIN_29_PDMDATA +}; + +//***************************************************************************** +// +// PDM_DATA_34 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_34 = { + .uFuncSel = AM_HAL_PIN_34_PDMDATA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_36 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_36 = { + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_45 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_45 = { + .uFuncSel = AM_HAL_PIN_45_PDMDATA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_10 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_10 = { + .uFuncSel = AM_HAL_PIN_10_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_12 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_12 = { + .uFuncSel = AM_HAL_PIN_12_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_14 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_14 = { + .uFuncSel = AM_HAL_PIN_14_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_22 pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_22 = { + .uFuncSel = AM_HAL_PIN_22_PDMCLK +}; + +//***************************************************************************** +// +// PDM_CLK_37 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_37 = { + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_46 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_46 = { + .uFuncSel = AM_HAL_PIN_46_PDMCLK +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_15 pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_15 = { + .uFuncSel = AM_HAL_PIN_15_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO = { + .uFuncSel = AM_HAL_PIN_22_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO_24 pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_24 = { + .uFuncSel = AM_HAL_PIN_24_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO_33 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_33 = { + .uFuncSel = AM_HAL_PIN_33_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_41 pin: ITM Serial Wire Output. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_41 = { + .uFuncSel = AM_HAL_PIN_41_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// ITM_SWO_45 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_45 = { + .uFuncSel = AM_HAL_PIN_45_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_46 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_46 = { + .uFuncSel = AM_HAL_PIN_46_SWO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// CORE_SWDCK_14 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_14 = { + .uFuncSel = AM_HAL_PIN_14_SWDCK +}; + +//***************************************************************************** +// +// CORE_SWDCK_20 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_20 = { + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// CORE_SWDIO_15 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_15 = { + .uFuncSel = AM_HAL_PIN_15_SWDIO +}; + +//***************************************************************************** +// +// CORE_SWDIO_21 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_21 = { + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.h new file mode 100644 index 0000000000..faa977bc1a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPinConfigs.h @@ -0,0 +1,1818 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef _APOLLO3_PERIPHERAL_PIN_CONFIGS_H_ +#define _APOLLO3_PERIPHERAL_PIN_CONFIGS_H_ + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// UART0_TX_1 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_1 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_1; + +//***************************************************************************** +// +// UART0_TX_7 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_7 7 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_7; + +//***************************************************************************** +// +// UART0_TX_16 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_16 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_16; + +//***************************************************************************** +// +// UART0_TX_20 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_20; + +//***************************************************************************** +// +// UART0_TX_22 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_22 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_22; + +//***************************************************************************** +// +// UART0_TX_26 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_26 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_26; + +//***************************************************************************** +// +// UART0_TX_28 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_28 28 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_28; + +//***************************************************************************** +// +// UART0_TX_30 pin: UART0 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_TX_30 30 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_30; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_TX_39 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_39 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_39; + +//***************************************************************************** +// +// UART0_TX_41 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_41; + +//***************************************************************************** +// +// UART0_TX_44 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_44 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_44; + +//***************************************************************************** +// +// UART0_TX_48 pin: UART0 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_TX_48 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_TX_48; + +//***************************************************************************** +// +// UART1_TX_8 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_8 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_8; + +//***************************************************************************** +// +// UART1_TX_10 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_10; + +//***************************************************************************** +// +// UART1_TX_12 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_12; + +//***************************************************************************** +// +// UART1_TX_14 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_14; + +//***************************************************************************** +// +// UART1_TX_18 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_18 18 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_18; + +//***************************************************************************** +// +// UART1_TX_20 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_20; + +//***************************************************************************** +// +// UART1_TX_24 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_24; + +//***************************************************************************** +// +// UART1_TX_35 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_35 35 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_35; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_37 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_39 pin: UART1 Tx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_TX_39 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_39; + +//***************************************************************************** +// +// UART1_TX_42 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_42 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_42; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_TX_46 pin: UART1 Tx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_TX_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_TX_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_2 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_2 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_2; + +//***************************************************************************** +// +// UART0_RX_11 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_11; + +//***************************************************************************** +// +// UART0_RX_17 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_17 17 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_17; + +//***************************************************************************** +// +// UART0_RX_21 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_21; + +//***************************************************************************** +// +// UART0_RX_23 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_23 23 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_23; + +//***************************************************************************** +// +// UART0_RX_27 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_27 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_27; + +//***************************************************************************** +// +// UART0_RX_29 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_29; + +//***************************************************************************** +// +// UART0_RX_31 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RX_31 31 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_31; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_34 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RX_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_40 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_40 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_40; + +//***************************************************************************** +// +// UART0_RX_45 pin: UART0 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RX_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RX_49 pin: UART0 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RX_49 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RX_49; + +//***************************************************************************** +// +// UART1_RX_2 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_2 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_2; + +//***************************************************************************** +// +// UART1_RX_4 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_4 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_4; + +//***************************************************************************** +// +// UART1_RX_9 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_9 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_9; + +//***************************************************************************** +// +// UART1_RX_13 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_13 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_13; + +//***************************************************************************** +// +// UART1_RX_15 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_15; + +//***************************************************************************** +// +// UART1_RX_19 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_19 19 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_19; + +//***************************************************************************** +// +// UART1_RX_21 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_21; + +//***************************************************************************** +// +// UART1_RX_25 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_25 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_25; + +//***************************************************************************** +// +// UART1_RX_36 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RX_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_38 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RX_38 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_38; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_40 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_40 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_40; + +//***************************************************************************** +// +// UART1_RX_43 pin: UART1 Rx Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RX_43 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_43; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RX_47 pin: UART1 Rx Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RX_47 47 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RX_47; + +//***************************************************************************** +// +// UART0_RTS_3 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_3 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_3; + +//***************************************************************************** +// +// UART0_RTS_5 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_5 5 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_5; + +//***************************************************************************** +// +// UART0_RTS_13 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_13 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_13; + +//***************************************************************************** +// +// UART0_RTS_18 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_18 18 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_18; + +//***************************************************************************** +// +// UART0_RTS_34 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RTS_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_35 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RTS_35 35 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_35; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_37 pin: UART0 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_RTS_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_RTS_41 pin: UART0 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_RTS_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_RTS_41; + +//***************************************************************************** +// +// UART1_RTS_10 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_10; + +//***************************************************************************** +// +// UART1_RTS_16 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_16 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_16; + +//***************************************************************************** +// +// UART1_RTS_20 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_20; + +//***************************************************************************** +// +// UART1_RTS_30 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RTS_30 30 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_30; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_31 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RTS_31 31 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_31; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_34 pin: UART1 RTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_RTS_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_RTS_41 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_41; + +//***************************************************************************** +// +// UART1_RTS_44 pin: UART1 RTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_RTS_44 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_RTS_44; + +//***************************************************************************** +// +// UART0_CTS_4 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_4 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_4; + +//***************************************************************************** +// +// UART0_CTS_6 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_6 6 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_6; + +//***************************************************************************** +// +// UART0_CTS_12 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_12; + +//***************************************************************************** +// +// UART0_CTS_24 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_24; + +//***************************************************************************** +// +// UART0_CTS_29 pin: UART0 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART0_CTS_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_29; + +//***************************************************************************** +// +// UART0_CTS_33 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_CTS_33 33 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_33; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_36 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_CTS_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART0_CTS_38 pin: UART0 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART0_CTS_38 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART0_CTS_38; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_11 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_11; + +//***************************************************************************** +// +// UART1_CTS_17 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_17 17 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_17; + +//***************************************************************************** +// +// UART1_CTS_21 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_21; + +//***************************************************************************** +// +// UART1_CTS_26 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_26 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_26; + +//***************************************************************************** +// +// UART1_CTS_29 pin: UART1 CTS Pin. +// +//***************************************************************************** +#define AP3_PER_UART1_CTS_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_29; + +//***************************************************************************** +// +// UART1_CTS_32 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_CTS_32 32 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_32; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_36 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_CTS_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// UART1_CTS_45 pin: UART1 CTS Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_UART1_CTS_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_UART1_CTS_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS; +#define AP3_PER_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_CS3; +#define AP3_PER_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_CS; +#define AP3_PER_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_CS; +#define AP3_PER_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_CS; +#define AP3_PER_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MISO; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_MOSI; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCK; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SCL; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM3_SDA; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_CS; +#define AP3_PER_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AP3_PER_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_CS; +#define AP3_PER_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AP3_PER_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE0; +#define AP3_PER_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AP3_PER_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_CE1; +#define AP3_PER_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AP3_PER_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AP3_PER_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AP3_PER_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AP3_PER_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AP3_PER_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AP3_PER_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AP3_PER_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AP3_PER_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AP3_PER_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AP3_PER_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_CE; +#define AP3_PER_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AP3_PER_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AP3_PER_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AP3_PER_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AP3_PER_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AP3_PER_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_IOS_SDA; + +//***************************************************************************** +// +// NCE_0 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_0 0 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_0; + +//***************************************************************************** +// +// NCE_1 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_1 1 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_1; + +//***************************************************************************** +// +// NCE_2 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_2 2 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_2; + +//***************************************************************************** +// +// NCE_3 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_3 3 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_3; + +//***************************************************************************** +// +// NCE_4 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_4 4 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_4; + +//***************************************************************************** +// +// NCE_7 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_7 7 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_7; + +//***************************************************************************** +// +// NCE_8 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_8 8 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_8; + +//***************************************************************************** +// +// NCE_9 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_9 9 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_9; + +//***************************************************************************** +// +// NCE_10 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_10; + +//***************************************************************************** +// +// NCE_11 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_11; + +//***************************************************************************** +// +// NCE_12 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_12; + +//***************************************************************************** +// +// NCE_13 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_13 13 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_13; + +//***************************************************************************** +// +// NCE_14 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_14; + +//***************************************************************************** +// +// NCE_15 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_15; + +//***************************************************************************** +// +// NCE_16 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_16 16 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_16; + +//***************************************************************************** +// +// NCE_17 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_17 17 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_17; + +//***************************************************************************** +// +// NCE_18 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_18 18 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_18; + +//***************************************************************************** +// +// NCE_19 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_19 19 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_19; + +//***************************************************************************** +// +// NCE_20 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_20; + +//***************************************************************************** +// +// NCE_21 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_21; + +//***************************************************************************** +// +// NCE_22 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_22 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_22; + +//***************************************************************************** +// +// NCE_23 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_23 23 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_23; + +//***************************************************************************** +// +// NCE_24 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_24; + +//***************************************************************************** +// +// NCE_25 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_25 25 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_25; + +//***************************************************************************** +// +// NCE_26 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_26 26 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_26; + +//***************************************************************************** +// +// NCE_27 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_27 27 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_27; + +//***************************************************************************** +// +// NCE_28 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_28 28 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_28; + +//***************************************************************************** +// +// NCE_29 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_29; + +//***************************************************************************** +// +// NCE_30 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_30 30 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_30; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_31 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_31 31 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_31; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_32 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_32 32 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_32; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_33 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_33 33 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_33; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_34 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_35 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_35 35 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_35; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_36 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_37 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_38 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_38 38 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_38; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_41 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_41; + +//***************************************************************************** +// +// NCE_42 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_42 42 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_42; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_43 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_43 43 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_43; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_44 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_44 44 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_44; + +//***************************************************************************** +// +// NCE_45 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_46 pin: NCE Pin. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_NCE_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// NCE_47 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_47 47 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_47; + +//***************************************************************************** +// +// NCE_48 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_48 48 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_48; + +//***************************************************************************** +// +// NCE_49 pin: NCE Pin. +// +//***************************************************************************** +#define AP3_PER_NCE_49 49 +extern const am_hal_gpio_pincfg_t g_AP3_PER_NCE_49; + +//***************************************************************************** +// +// PDM_DATA_11 pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_DATA_11 11 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_11; + +//***************************************************************************** +// +// PDM_DATA_15 pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_DATA_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_15; + +//***************************************************************************** +// +// PDM_DATA_29 pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_DATA_29 29 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_29; + +//***************************************************************************** +// +// PDM_DATA_34 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_DATA_34 34 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_34; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_36 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_DATA_36 36 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_36; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_DATA_45 pin: Data line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_DATA_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_DATA_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_10 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_10 10 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_10; + +//***************************************************************************** +// +// PDM_CLK_12 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_12 12 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_12; + +//***************************************************************************** +// +// PDM_CLK_14 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_14; + +//***************************************************************************** +// +// PDM_CLK_22 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AP3_PER_PDM_CLK_22 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_22; + +//***************************************************************************** +// +// PDM_CLK_37 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_CLK_37 37 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_37; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// PDM_CLK_46 pin: Clock line for PDM microphones. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_PDM_CLK_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_PDM_CLK_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_15 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_15; + +//***************************************************************************** +// +// ITM_SWO pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO 22 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO; + +//***************************************************************************** +// +// ITM_SWO_24 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO_24 24 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_24; + +//***************************************************************************** +// +// ITM_SWO_33 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_ITM_SWO_33 33 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_33; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_41 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#define AP3_PER_ITM_SWO_41 41 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_41; + +//***************************************************************************** +// +// ITM_SWO_45 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_ITM_SWO_45 45 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_45; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// ITM_SWO_46 pin: ITM Serial Wire Output. +// +//***************************************************************************** +#if defined (AM_PACKAGE_BGA) +#define AP3_PER_ITM_SWO_46 46 +extern const am_hal_gpio_pincfg_t g_AP3_PER_ITM_SWO_46; +#endif // AM_PACKAGE_BGA + +//***************************************************************************** +// +// CORE_SWDCK_14 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDCK_14 14 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_14; + +//***************************************************************************** +// +// CORE_SWDCK_20 pin: Cortex Serial Wire Debug Clock. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDCK_20 20 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDCK_20; + +//***************************************************************************** +// +// CORE_SWDIO_15 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDIO_15 15 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_15; + +//***************************************************************************** +// +// CORE_SWDIO_21 pin: Cortex Serial Wire Debug I/O. +// +//***************************************************************************** +#define AP3_PER_CORE_SWDIO_21 21 +extern const am_hal_gpio_pincfg_t g_AP3_PER_CORE_SWDIO_21; + + +#ifdef __cplusplus +} +#endif + +#endif // _APOLLO3_PERIPHERAL_PIN_CONFIGS_H_ + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.c new file mode 100644 index 0000000000..1eb737ddfc --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.c @@ -0,0 +1,258 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#include "PeripheralPins.h" +#include "PeripheralPinConfigs.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, 0, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {AP3_PER_IOM0_SDA, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SDA}, + {AP3_PER_IOM1_SDA, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SDA}, + {AP3_PER_IOM2_SDA, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SDA}, + {AP3_PER_IOM4_SDA, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SDA}, + {AP3_PER_IOM5_SDA, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SDA}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_SDA, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SDA}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {AP3_PER_IOM0_SCL, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCL}, + {AP3_PER_IOM1_SCL, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCL}, + {AP3_PER_IOM2_SCL, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCL}, + {AP3_PER_IOM4_SCL, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCL}, + {AP3_PER_IOM5_SCL, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCL}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_SCL, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCL}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {AP3_PER_UART0_TX_1, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_1}, + {AP3_PER_UART0_TX_7, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_7}, + {AP3_PER_UART0_TX_16, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_16}, + {AP3_PER_UART0_TX_20, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_20}, + {AP3_PER_UART0_TX_22, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_22}, + {AP3_PER_UART0_TX_26, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_26}, + {AP3_PER_UART0_TX_28, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_28}, + {AP3_PER_UART0_TX_39, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_39}, + {AP3_PER_UART0_TX_41, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_41}, + {AP3_PER_UART0_TX_44, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_44}, + {AP3_PER_UART0_TX_48, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_48}, + {AP3_PER_UART1_TX_8, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_8}, + {AP3_PER_UART1_TX_10, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_10}, + {AP3_PER_UART1_TX_12, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_12}, + {AP3_PER_UART1_TX_14, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_14}, + {AP3_PER_UART1_TX_18, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_18}, + {AP3_PER_UART1_TX_20, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_20}, + {AP3_PER_UART1_TX_24, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_24}, + {AP3_PER_UART1_TX_39, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_39}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_UART0_TX_30, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_30}, + {AP3_PER_UART1_TX_35, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_35}, + {AP3_PER_UART1_TX_37, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_37}, + {AP3_PER_UART1_TX_42, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_42}, + {AP3_PER_UART1_TX_46, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_46}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {AP3_PER_UART0_RX_2, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_2}, + {AP3_PER_UART0_RX_11, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_11}, + {AP3_PER_UART0_RX_17, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_17}, + {AP3_PER_UART0_RX_21, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_21}, + {AP3_PER_UART0_RX_23, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_23}, + {AP3_PER_UART0_RX_27, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_27}, + {AP3_PER_UART0_RX_29, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_29}, + {AP3_PER_UART0_RX_40, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_40}, + {AP3_PER_UART0_RX_49, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_49}, + {AP3_PER_UART1_RX_2, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_2}, + {AP3_PER_UART1_RX_4, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_4}, + {AP3_PER_UART1_RX_9, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_9}, + {AP3_PER_UART1_RX_13, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_13}, + {AP3_PER_UART1_RX_15, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_15}, + {AP3_PER_UART1_RX_19, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_19}, + {AP3_PER_UART1_RX_21, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_21}, + {AP3_PER_UART1_RX_25, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_25}, + {AP3_PER_UART1_RX_40, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_40}, + {AP3_PER_UART1_RX_47, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_47}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_UART0_RX_31, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_31}, + {AP3_PER_UART0_RX_34, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_34}, + {AP3_PER_UART0_RX_45, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_45}, + {AP3_PER_UART1_RX_36, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_36}, + {AP3_PER_UART1_RX_38, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_38}, + {AP3_PER_UART1_RX_43, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_43}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {3, UART_0, AM_HAL_PIN_3_UART0RTS}, + {5, UART_0, AM_HAL_PIN_5_UART0RTS}, + {13, UART_0, AM_HAL_PIN_13_UART0RTS}, + {18, UART_0, AM_HAL_PIN_18_UART0RTS}, + {41, UART_0, AM_HAL_PIN_41_UART0RTS}, + {10, UART_1, AM_HAL_PIN_10_UART1RTS}, + {16, UART_1, AM_HAL_PIN_16_UART1RTS}, + {20, UART_1, AM_HAL_PIN_20_UART1RTS}, + {41, UART_1, AM_HAL_PIN_41_UART1RTS}, + {44, UART_1, AM_HAL_PIN_44_UART1RTS}, +#if defined (AM_PACKAGE_BGA) + {34, UART_0, AM_HAL_PIN_34_UART0RTS}, + {35, UART_0, AM_HAL_PIN_35_UART0RTS}, + {37, UART_0, AM_HAL_PIN_37_UART0RTS}, + {30, UART_1, AM_HAL_PIN_30_UART1RTS}, + {31, UART_1, AM_HAL_PIN_31_UART1RTS}, + {34, UART_1, AM_HAL_PIN_34_UART1RTS}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {4, UART_0, AM_HAL_PIN_4_UART0CTS}, + {6, UART_0, AM_HAL_PIN_6_UART0CTS}, + {12, UART_0, AM_HAL_PIN_12_UART0CTS}, + {24, UART_0, AM_HAL_PIN_24_UART0CTS}, + {29, UART_0, AM_HAL_PIN_29_UART0CTS}, + {11, UART_1, AM_HAL_PIN_11_UART1CTS}, + {17, UART_1, AM_HAL_PIN_17_UART1CTS}, + {21, UART_1, AM_HAL_PIN_21_UART1CTS}, + {26, UART_1, AM_HAL_PIN_26_UART1CTS}, + {29, UART_1, AM_HAL_PIN_29_UART1CTS}, +#if defined (AM_PACKAGE_BGA) + {33, UART_0, AM_HAL_PIN_33_UART0CTS}, + {36, UART_0, AM_HAL_PIN_36_UART0CTS}, + {38, UART_0, AM_HAL_PIN_38_UART0CTS}, + {32, UART_1, AM_HAL_PIN_32_UART1CTS}, + {36, UART_1, AM_HAL_PIN_36_UART1CTS}, + {45, UART_1, AM_HAL_PIN_45_UART1CTS}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {AP3_PER_IOM0_SCK, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCK}, + {AP3_PER_IOM1_SCK, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCK}, + {AP3_PER_IOM2_SCK, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCK}, + {AP3_PER_IOM4_SCK, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCK}, + {AP3_PER_IOM5_SCK, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCK}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_SCK, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCK}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {AP3_PER_IOM0_MOSI, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MOSI}, + {AP3_PER_IOM1_MOSI, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MOSI}, + {AP3_PER_IOM2_MOSI, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MOSI}, + {AP3_PER_IOM4_MOSI, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MOSI}, + {AP3_PER_IOM5_MOSI, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MOSI}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_MOSI, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MOSI}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {AP3_PER_IOM0_MISO, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MISO}, + {AP3_PER_IOM1_MISO, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MISO}, + {AP3_PER_IOM2_MISO, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MISO}, + {AP3_PER_IOM4_MISO, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MISO}, + {AP3_PER_IOM5_MISO, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MISO}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_IOM3_MISO, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MISO}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {AP3_PER_NCE_0, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_0}, + {AP3_PER_NCE_1, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_1}, + {AP3_PER_NCE_2, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_2}, + {AP3_PER_NCE_3, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_3}, + {AP3_PER_NCE_4, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_4}, + {AP3_PER_NCE_7, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_7}, + {AP3_PER_NCE_8, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_8}, + {AP3_PER_NCE_9, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_9}, + {AP3_PER_NCE_10, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_10}, + {AP3_PER_NCE_11, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_11}, + {AP3_PER_NCE_12, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_12}, + {AP3_PER_NCE_13, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_13}, + {AP3_PER_NCE_14, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_14}, + {AP3_PER_NCE_15, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_15}, + {AP3_PER_NCE_16, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_16}, + {AP3_PER_NCE_17, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_17}, + {AP3_PER_NCE_18, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_18}, + {AP3_PER_NCE_19, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_19}, + {AP3_PER_NCE_20, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_20}, + {AP3_PER_NCE_21, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_21}, + {AP3_PER_NCE_22, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_22}, + {AP3_PER_NCE_23, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_23}, + {AP3_PER_NCE_24, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_24}, + {AP3_PER_NCE_25, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_25}, + {AP3_PER_NCE_26, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_26}, + {AP3_PER_NCE_27, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_27}, + {AP3_PER_NCE_28, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_28}, + {AP3_PER_NCE_29, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_29}, + {AP3_PER_NCE_41, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_41}, + {AP3_PER_NCE_44, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_44}, + {AP3_PER_NCE_47, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_47}, + {AP3_PER_NCE_48, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_48}, + {AP3_PER_NCE_49, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_49}, +#if defined (AM_PACKAGE_BGA) + {AP3_PER_NCE_30, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_30}, + {AP3_PER_NCE_31, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_31}, + {AP3_PER_NCE_32, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_32}, + {AP3_PER_NCE_33, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_33}, + {AP3_PER_NCE_34, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_34}, + {AP3_PER_NCE_35, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_35}, + {AP3_PER_NCE_36, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_36}, + {AP3_PER_NCE_37, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_37}, + {AP3_PER_NCE_38, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_38}, + {AP3_PER_NCE_42, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_42}, + {AP3_PER_NCE_43, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_43}, + {AP3_PER_NCE_45, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_45}, + {AP3_PER_NCE_46, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_46}, +#endif // defined (AM_PACKAGE_BGA) + {NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {NC, NC, 0} +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.h new file mode 100644 index 0000000000..f0d1c3c54b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/PeripheralPins.h @@ -0,0 +1,73 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2018-2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +//*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM_OUT[]; +#endif + +//*** SERIAL *** +#if DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif + +//*** SPI *** +#if DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** ADC *** +#if DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +//*** DAC *** +#if DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +//*** QSPI *** +#if DEVICE_QSPI +extern const PinMap PinMap_QSPI_SCLK[]; +extern const PinMap PinMap_QSPI_SSEL[]; +extern const PinMap PinMap_QSPI_DATA0[]; +extern const PinMap PinMap_QSPI_DATA1[]; +extern const PinMap PinMap_QSPI_DATA2[]; +extern const PinMap PinMap_QSPI_DATA3[]; +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis.h new file mode 100644 index 0000000000..840f172867 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "am_mcu_apollo.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis_nvic.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis_nvic.h new file mode 100644 index 0000000000..41e919f831 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/cmsis_nvic.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 32 + 16) // CORE + MCU Peripherals + BLE Patch +#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/device.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/device.h new file mode 100644 index 0000000000..8bafaf48de --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/device.h @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" +#include "extensions.h" +#include "us_ticker_defines.h" + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/extensions.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/extensions.h new file mode 100644 index 0000000000..dd3890ae46 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/extensions.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _MBED_APOLLO3_EXTENSIONS_H_ +#define _MBED_APOLLO3_EXTENSIONS_H_ + +#include "pinmap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void pinmap_config(PinName pin, const PinMap *map); +void pin_config(PinName pin, am_hal_gpio_pincfg_t pincfg); + +#ifdef __cplusplus +} +#endif + +#endif // _MBED_APOLLO3_EXTENSIONS_H_ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/flash_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/flash_api.c new file mode 100644 index 0000000000..4f6863ddb1 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/flash_api.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "flash_api.h" +#include + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + if (!ISADDRFLASH(address)) { + return -1; + } + uint32_t status = am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, AM_HAL_FLASH_ADDR2INST(address), AM_HAL_FLASH_ADDR2PAGE(address)); + if (status != AM_HAL_STATUS_SUCCESS) { + return -1; + } + return 0; +} + +int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + memcpy(data, (void *)address, size); + return 0; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + if (address & 0x03) { + return -1; + } + if (((uint32_t)data) & 0x03) { + return -1; + } + uint32_t words = (size + 3) / 4; + uint32_t status = am_hal_flash_program_main(AM_HAL_FLASH_PROGRAM_KEY, (uint32_t *)data, (uint32_t *)address, words); + if (status != AM_HAL_STATUS_SUCCESS) { + return -1; + } + return 0; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (address > AM_HAL_FLASH_LARGEST_VALID_ADDR) { + return -1; + } + return AM_HAL_FLASH_PAGE_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return 4; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return AM_HAL_FLASH_ADDR; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return AM_HAL_FLASH_TOTAL_SIZE; +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + return 0xFF; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_api.c new file mode 100644 index 0000000000..8ca3e342ea --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_api.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "mbed_assert.h" +#include "gpio_api.h" + +/** Set the given pin as GPIO + * + * @param pin The pin to be set as GPIO + * @return The GPIO port mask for this pin + **/ +uint32_t gpio_set(PinName pin) +{ + MBED_ASSERT(pin != (PinName)NC); + return (uint32_t)AM_HAL_GPIO_BIT(pin); +} + +/** Checks if gpio object is connected (pin was not initialized with NC) + * @param obj The GPIO object + * @return 0 if object was initialized with NC + * @return non-zero if object was initialized with a valid PinName + **/ +int gpio_is_connected(const gpio_t *obj) +{ + MBED_ASSERT(obj != NULL); + return (int)(((PinName)obj->pad == (PinName)NC) ? 0 : 1); +} + +/** Initialize the GPIO pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin to initialize (may be NC) + */ +void gpio_init(gpio_t *obj, PinName pin) +{ + MBED_ASSERT(obj != NULL); + obj->pad = (ap3_uart_pad_t)pin; + return; +} +/** Set the input pin mode + * + * @param obj The GPIO object (must be connected) + * @param mode The pin mode to be set + */ +void gpio_mode(gpio_t *obj, PinMode mode) +{ + MBED_ASSERT(gpio_is_connected(obj)); + MBED_ASSERT(mode < (PinMode)PinModeElements); + am_hal_gpio_pincfg_allow_t pinConfigBools; + + obj->cfg.uFuncSel = AP3_PINCFG_FUNCSEL_GPIO; // gpio + + if (mode & (PinMode)PowerSwNone) { + obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_NONE; + pinConfigBools.ePowerSw = true; + } + if (mode & (PinMode)PowerSwVDD) { + obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_VDD; + pinConfigBools.ePowerSw = true; + } + if (mode & (PinMode)PowerSwVSS) { + obj->cfg.ePowerSw = AM_HAL_GPIO_PIN_POWERSW_VSS; + pinConfigBools.ePowerSw = true; + } + + if (mode & (PinMode)PullNone) { + obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_NONE; + pinConfigBools.ePullup = true; + } + if (mode & (PinMode)PullUp) { + obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_WEAK; + pinConfigBools.ePullup = true; + } + if (mode & (PinMode)PullDown) { + obj->cfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN; + pinConfigBools.ePullup = true; + } + + if (mode & (PinMode)DriveStrength2mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA; + pinConfigBools.eDriveStrength = true; + } + if (mode & (PinMode)DriveStrength4mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA; + pinConfigBools.eDriveStrength = true; + } + if (mode & (PinMode)DriveStrength8mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA; + pinConfigBools.eDriveStrength = true; + } + if (mode & (PinMode)DriveStrength12mA) { + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA; + pinConfigBools.eDriveStrength = true; + } + + if (mode & (PinMode)OutDisable) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE; + pinConfigBools.eGPOutcfg = true; + } + if (mode & (PinMode)OutPushPull) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL; + pinConfigBools.eGPOutcfg = true; + } + if (mode & (PinMode)OutOpenDrain) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN; + pinConfigBools.eGPOutcfg = true; + } + if (mode & (PinMode)OutTristate) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_TRISTATE; + pinConfigBools.eGPOutcfg = true; + } + + if (mode & (PinMode)InAuto) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_AUTO; + pinConfigBools.eGPInput = true; + } + if (mode & (PinMode)InNone) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE; + pinConfigBools.eGPInput = true; + } + if (mode & (PinMode)InEnable) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE; + pinConfigBools.eGPInput = true; + } + + if (mode & (PinMode)ReadPin) { + obj->cfg.eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN; + pinConfigBools.eGPRdZero = true; + } + if (mode & (PinMode)ReadZero) { + obj->cfg.eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_ZERO; + pinConfigBools.eGPRdZero = true; + } + + ap3_hal_gpio_pinconfig_partial((uint32_t)(obj->pad), obj->cfg, pinConfigBools); //padRegMsk.byte, GPConfigMsk.byte, padAltCfgMsk.byte); // apply configuration +} + +/** Set the pin direction + * + * @param obj The GPIO object (must be connected) + * @param direction The pin direction to be set + */ +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(gpio_is_connected(obj)); + MBED_ASSERT(direction < (PinDirection)PIN_DIR_ELEMENTS); + am_hal_gpio_pincfg_allow_t pinConfigBools; + + if (direction == (PinDirection)PIN_INPUT) { + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE; + pinConfigBools.eGPInput = true; + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE; + pinConfigBools.eGPOutcfg = true; + } else if (direction == (PinDirection)PIN_OUTPUT) { + obj->cfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL; + pinConfigBools.eGPOutcfg = true; + obj->cfg.eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA; + pinConfigBools.eDriveStrength = true; + obj->cfg.eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE; + pinConfigBools.eGPInput = true; + } else { + MBED_ASSERT(false); + } + + ap3_hal_gpio_pinconfig_partial((uint32_t)(obj->pad), obj->cfg, pinConfigBools); //padRegMsk.byte, GPConfigMsk.byte, padAltCfgMsk.byte); // apply configuration +} + +/** Set the output value + * + * @param obj The GPIO object (must be connected) + * @param value The value to be set + */ +void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(gpio_is_connected(obj)); + (value) ? am_hal_gpio_output_set(obj->pad) : am_hal_gpio_output_clear(obj->pad); +} + +/** Read the input value + * + * @param obj The GPIO object (must be connected) + * @return An integer value 1 or 0 + */ +int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(gpio_is_connected(obj)); + uint32_t ui32BaseAddr = (obj->pad) / 8; + uint32_t ui32BaseShift = (((obj->pad) % 8) * 4) + 1; + uint8_t output = ((AM_REGVAL(&GPIO->CFGA + ui32BaseAddr) >> ui32BaseShift) & 0x03); + + return (output) ? (int)am_hal_gpio_output_read(obj->pad) : (int)am_hal_gpio_input_read(obj->pad); + return 0; +} + +/** Get the pins that support all GPIO tests + * + * Return a PinMap array of pins that support GPIO. The + * array is terminated with {NC, NC, 0}. + * + * Targets should override the weak implementation of this + * function to provide the actual pinmap for GPIO testing. + * + * @return PinMap array + */ +const PinMap *gpio_pinmap(void) +{ + MBED_ASSERT(false); + return NULL; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c new file mode 100644 index 0000000000..06fcb40995 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "gpio_irq_api.h" +#include "objects.h" + +#if DEVICE_INTERRUPTIN + +#ifdef __cplusplus +extern "C" +{ +#endif + +uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir); +/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL +*/ +typedef struct gpio_irq_s gpio_irq_t; + +typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); +extern void am_gpio_isr(void); +static ap3_gpio_irq_control_t gpio_irq_control[AP3_GPIO_MAX_PADS]; + +/** +* \defgroup hal_gpioirq GPIO IRQ HAL functions +* +* # Defined behavior +* * ::gpio_irq_init initializes the GPIO IRQ pin +* * ::gpio_irq_init attaches the interrupt handler +* * ::gpio_irq_free releases the GPIO IRQ pin +* * ::gpio_irq_set enables/disables pin IRQ event +* * ::gpio_irq_enable enables GPIO IRQ +* * ::gpio_irq_disable disables GPIO IRQ +* +* # Undefined behavior +* * Calling other function before ::gpio_irq_init +* +* @{ +*/ + +/** Initialize the GPIO IRQ pin +* +* @param obj The GPIO object to initialize +* @param pin The GPIO pin name +* @param handler The handler to be attached to GPIO IRQ +* @param id The object ID (id != 0, 0 is reserved) +* @return -1 if pin is NC, 0 otherwise +*/ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + //grab the correct irq control object + ap3_gpio_irq_control_t *control = &gpio_irq_control[pin]; + + //Register locally + control->pad = pin; + control->handler = handler; + control->id = id; + control->events = IRQ_NONE; + + //Attach to object + obj->control = control; + + //Make sure the interrupt is set to none to reflect the new events value + ap3_gpio_enable_interrupts(control->pad, AM_HAL_GPIO_PIN_INTDIR_NONE); + + //Enable GPIO IRQ's in the NVIC + gpio_irq_enable(obj); + NVIC_SetVector((IRQn_Type)GPIO_IRQn, (uint32_t)am_gpio_isr); + NVIC_EnableIRQ((IRQn_Type)GPIO_IRQn); + return 0; +} + +void am_gpio_isr(void) +{ + //call the handler for the interrupt + uint64_t gpio_int_mask = 0x00; + am_hal_gpio_interrupt_status_get(true, &gpio_int_mask); + uint32_t pinNum = 0; + while (gpio_int_mask) { + if (gpio_int_mask & 0x0000000000000001) { + am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(pinNum)); + ap3_gpio_irq_control_t irq_ctrl = gpio_irq_control[pinNum]; + ((gpio_irq_handler)irq_ctrl.handler)(irq_ctrl.id, irq_ctrl.events); + } + gpio_int_mask >>= 1; + pinNum++; + } +} + +/** Release the GPIO IRQ PIN +* +* @param obj The gpio object +*/ +void gpio_irq_free(gpio_irq_t *obj) +{ +} + +/** Enable/disable pin IRQ event +* +* @param obj The GPIO object +* @param event The GPIO IRQ event +* @param enable The enable flag +*/ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + //Clear state + obj->control->events &= (~event); + if (enable) { + //Reset if enabled + obj->control->events |= event; + } + + // Map enabled events to a value the reflects the ambiq hal/register values + am_hal_gpio_intdir_e ap3_int_dir = 0x00; + switch (obj->control->events) { + case IRQ_NONE: + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_NONE; + break; + case IRQ_RISE: + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_LO2HI; + break; + case IRQ_FALL: + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_HI2LO; + break; + case (IRQ_RISE | IRQ_FALL): + ap3_int_dir = AM_HAL_GPIO_PIN_INTDIR_BOTH; + break; + } + + ap3_gpio_enable_interrupts(obj->control->pad, ap3_int_dir); +} + +/** Enable GPIO IRQ +* +* This is target dependent, as it might enable the entire port or just a pin +* @param obj The GPIO object +*/ +void gpio_irq_enable(gpio_irq_t *obj) +{ + am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad)); + am_hal_gpio_interrupt_enable(AM_HAL_GPIO_BIT(obj->control->pad)); +} + +/** Disable GPIO IRQ +* +* This is target dependent, as it might disable the entire port or just a pin +* @param obj The GPIO object +*/ +void gpio_irq_disable(gpio_irq_t *obj) +{ + am_hal_gpio_interrupt_clear(AM_HAL_GPIO_BIT(obj->control->pad)); + am_hal_gpio_interrupt_disable(AM_HAL_GPIO_BIT(obj->control->pad)); +} + +/**@}*/ +uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntDir) +{ + //GPConfigReg_t GPCfgMask = {.bit.INCFG = 1, .bit.INTD = 1}; + // uint32_t ap3_hal_gpio_pinconfig_partial(ui32Pin, bfGpioCfg, 0, uint8_t GPCfgMask, 0); + uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg; + bool bClearEnable = false; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (ui32Pin >= AM_HAL_GPIO_MAX_PADS) { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the PADREG accumulator variables. + // + ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0; + + // + // Map the requested interrupt direction settings into the Apollo3 + // GPIOCFG register field, which is a 4-bit field: + // [INTD(1):OUTCFG(2):INCFG(1)]. + // Bit0 of eIntDir maps to GPIOCFG.INTD (b3). + // Bit1 of eIntDir maps to GPIOCFG.INCFG (b0). + // + ui32GPCfg |= (((eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | (((eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S); + + // + // At this point, the configuration variable, ui32GpioCfg + // value is set (at bit position 0) and ready to write + // to their respective register bitfields. + // + uint32_t ui32GPCfgAddr; + uint32_t ui32GPCfgClearMask; + uint32_t ui32GPCfgShft; + + ui32GPCfgShft = ((ui32Pin & 0x7) << 2); + + ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3); + + ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft); + + // + // Get the new values into their rightful bit positions. + // + ui32GPCfg <<= ui32GPCfgShft; + + AM_CRITICAL_BEGIN + + if (bClearEnable) { + // + // We're configuring a mode that requires clearing the Enable bit. + // + am_hal_gpio_output_tristate_disable(ui32Pin); + } + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + // Here's where the magic happens + AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_pinconfig() + +#ifdef __cplusplus +} +#endif +/** @}*/ +#endif //DEVICE_INTERRUPTIN diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/i2c_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/i2c_api.c new file mode 100644 index 0000000000..669068d95e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/i2c_api.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if DEVICE_I2C + +#include "i2c_api.h" +#include "iom_api.h" +#include "PeripheralPins.h" +#include "mbed_assert.h" + +#define DEFAULT_CLK_FREQ (AM_HAL_IOM_400KHZ) + +static am_hal_iom_transfer_t xfer = {0}; + +I2CName i2c_get_peripheral_name(PinName sda, PinName scl) +{ + uint32_t iom_sda = pinmap_peripheral(sda, i2c_master_sda_pinmap()); + uint32_t iom_scl = pinmap_peripheral(scl, i2c_master_scl_pinmap()); + + uint32_t iom = pinmap_merge(iom_sda, iom_scl); + + if ((int)iom == NC) { + return IOM_NUM; + } + + return (I2CName)iom; +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj); + + // iom determination + I2CName iom = i2c_get_peripheral_name(sda, scl); + MBED_ASSERT((int)iom != IOM_NUM); + + // iom configuration + obj->i2c.iom_obj.iom.inst = (uint32_t)iom; + obj->i2c.iom_obj.iom.cfg.eInterfaceMode = AM_HAL_IOM_I2C_MODE; + obj->i2c.iom_obj.iom.cfg.ui32ClockFreq = DEFAULT_CLK_FREQ; + obj->i2c.iom_obj.iom.cfg.pNBTxnBuf = NULL; + obj->i2c.iom_obj.iom.cfg.ui32NBTxnBufLength = 0; + + // pin configuration + if ((int)sda != NC) { + pinmap_config(sda, i2c_master_sda_pinmap()); + } + if ((int)scl != NC) { + pinmap_config(scl, i2c_master_scl_pinmap()); + } + + // invariant xfer settings + xfer.ui32InstrLen = 0; + xfer.ui32Instr = 0; + xfer.ui8RepeatCount = 0; + xfer.ui8Priority = 1; + xfer.ui32PauseCondition = 0; + xfer.ui32StatusSetClr = 0; + + // initialization + iom_init(&obj->i2c.iom_obj); +} + +void i2c_free(i2c_t *obj) +{ + MBED_ASSERT(obj); + iom_deinit(&obj->i2c.iom_obj); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + MBED_ASSERT(obj); + if (hz > AM_HAL_IOM_MAX_FREQ) { + hz = AM_HAL_IOM_MAX_FREQ; + } + obj->i2c.iom_obj.iom.cfg.ui32ClockFreq = hz; + iom_init(&obj->i2c.iom_obj); +} + +int i2c_start(i2c_t *obj) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +int i2c_stop(i2c_t *obj) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +int i2c_read(i2c_t *obj, int address8bit, char *data, int length, int stop) +{ + MBED_ASSERT(obj); + + int handled_chars = 0; + + xfer.uPeerInfo.ui32I2CDevAddr = (address8bit >> 1); + xfer.eDirection = AM_HAL_IOM_RX; + xfer.ui32NumBytes = length; + xfer.pui32RxBuffer = (uint32_t *)data; + xfer.pui32TxBuffer = NULL; + xfer.bContinue = (stop) ? false : true; + uint32_t status = am_hal_iom_blocking_transfer(obj->i2c.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return I2C_ERROR_NO_SLAVE; + } + handled_chars += xfer.ui32NumBytes; + + return handled_chars; +} + +int i2c_write(i2c_t *obj, int address8bit, const char *data, int length, int stop) +{ + MBED_ASSERT(obj); + + int handled_chars = 0; + + xfer.uPeerInfo.ui32I2CDevAddr = (address8bit >> 1); + xfer.eDirection = AM_HAL_IOM_TX; + xfer.ui32NumBytes = length; + xfer.pui32TxBuffer = (uint32_t *)data; + xfer.pui32RxBuffer = NULL; + xfer.bContinue = (stop) ? false : true; + uint32_t status = am_hal_iom_blocking_transfer(obj->i2c.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return I2C_ERROR_NO_SLAVE; + } + handled_chars += xfer.ui32NumBytes; + + return handled_chars; +} + +void i2c_reset(i2c_t *obj) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + MBED_ASSERT(obj); + MBED_ASSERT(0); + return I2C_ERROR_NO_SLAVE; +} + +const PinMap *i2c_master_sda_pinmap(void) +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap(void) +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap(void) +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap(void) +{ + return PinMap_I2C_SCL; +} + +#endif // DEVICE_I2C diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.c new file mode 100644 index 0000000000..bb86f37a15 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "iom_api.h" +#include "mbed_assert.h" + +void iom_init(iom_t *obj) +{ + MBED_ASSERT(obj); + + if (obj->iom.handle) { + iom_deinit(obj); + } + + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_initialize(obj->iom.inst, &obj->iom.handle)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_power_ctrl(obj->iom.handle, AM_HAL_SYSCTRL_WAKE, false)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_configure(obj->iom.handle, &obj->iom.cfg)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_enable(obj->iom.handle)); + + // this merely configures the internal peripheral - the desired pins still need to be configured +} + +void iom_deinit(iom_t *obj) +{ + MBED_ASSERT(obj); + + if (!obj->iom.handle) { + return; + } + + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_disable(obj->iom.handle)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_power_ctrl(obj->iom.handle, AM_HAL_SYSCTRL_DEEPSLEEP, false)); + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_iom_uninitialize(obj->iom.handle)); + + obj->iom.handle = NULL; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.h new file mode 100644 index 0000000000..d0bba0f256 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/iom_api.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_IOM_API_H +#define MBED_IOM_API_H + +#include "hal/dma_api.h" +#include "hal/buffer.h" + +#include "am_mcu_apollo.h" + +#include "objects_iom.h" + +/** Asynch IOM HAL structure + */ +typedef struct { + struct iom_s iom; /**< Target specific SPI structure */ + // struct buffer_s tx_buff; /**< Tx buffer */ + // struct buffer_s rx_buff; /**< Rx buffer */ +} iom_t; + +void iom_init(iom_t *obj); +void iom_deinit(iom_t *obj); + +#endif // MBED_IOM_API_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/isr.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/isr.c new file mode 100644 index 0000000000..0558ab24ff --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/isr.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "am_mcu_apollo.h" +#include "lp_ticker_defines.h" +volatile bool someFlagThatGetSetinISR = false; + +void am_ctimer_isr(void) +{ + uint32_t ui32Status; + + // + // Check and clear any active CTIMER interrupts. + // + ui32Status = am_hal_ctimer_int_status_get(true); + am_hal_ctimer_int_clear(ui32Status); + // // + // // Run handlers for the various possible timer events. + // // + am_hal_ctimer_int_service(ui32Status); + + //am_hal_ctimer_int_service(am_hal_ctimer_int_status_get(true)); // get enabled interrupt status and then service those only +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker.c new file mode 100644 index 0000000000..a285de718d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "lp_ticker_api.h" +#include "lp_ticker_defines.h" +#include "platform/mbed_critical.h" + +#if DEVICE_LPTICKER + +static bool lp_ticker_initialized = false; + +/* LP ticker is driven by 32kHz clock and counter length is 24 bits. */ +const ticker_info_t *lp_ticker_get_info() +{ + static const ticker_info_t info = { + LP_TICKER_FREQ, + LP_TICKER_BITS + }; + return &info; +} + +void lp_ticker_init(void) +{ + if (lp_ticker_initialized) { + lp_ticker_disable_interrupt(); + return; + } + am_hal_ctimer_int_register(LP_TICKER_AM_HAL_CTIMER_CMPR_INT, lp_ticker_irq_handler); + am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER, + (LP_TICKER_AM_HAL_CTIMER_TIME_KEEPER_FN | LP_TICKER_AM_HAL_CTIMER_SRC)); + am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER, + (LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN | LP_TICKER_AM_HAL_CTIMER_SRC | AM_HAL_CTIMER_INT_ENABLE)); + am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); + NVIC_EnableIRQ(CTIMER_IRQn); + am_hal_ctimer_start(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); + lp_ticker_initialized = true; +} + +void lp_ticker_free(void) +{ + am_hal_ctimer_stop(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); + + am_hal_ctimer_clear(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); + lp_ticker_initialized = false; +} + +uint32_t lp_ticker_read() +{ + return am_hal_ctimer_read(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER); +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); + am_hal_ctimer_clear(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER); + // am_hal_ctimer_config_single(LP_TICKER_AM_HAL_CTIMER_NUMBER, + // LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER, + // (LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN | LP_TICKER_AM_HAL_CTIMER_SRC | AM_HAL_CTIMER_INT_ENABLE | CTIMER_CTRL0_TMRA0IE1_Msk)); + am_hal_ctimer_start(LP_TICKER_AM_HAL_CTIMER_NUMBER, LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER); + uint32_t delta = (uint32_t)timestamp - lp_ticker_read(); + am_hal_ctimer_compare_set(LP_TICKER_AM_HAL_CTIMER_NUMBER, + LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER, + LP_TICKER_AM_HAL_CTIMER_CMPR_REG, + (uint32_t)delta); +} + +void lp_ticker_fire_interrupt(void) +{ + am_hal_ctimer_int_enable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); + am_hal_ctimer_int_set(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); +} + +void lp_ticker_disable_interrupt(void) +{ + am_hal_ctimer_int_disable(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); +} + +void lp_ticker_clear_interrupt(void) +{ + am_hal_ctimer_int_clear(LP_TICKER_AM_HAL_CTIMER_CMPR_INT); +} + +#endif // DEVICE_LPTICKER diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker_defines.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker_defines.h new file mode 100644 index 0000000000..f46cf8aafe --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/lp_ticker_defines.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +// #ifndef MBED_US_TICKER_DEFINES_H +// #define MBED_US_TICKER_DEFINES_H + +#include "am_mcu_apollo.h" + +#define LP_TICKER_FREQ 32768 +#define LP_TICKER_AM_HAL_CTIMER_SRC AM_HAL_CTIMER_XT_32_768KHZ + +#define LP_TICKER_AM_HAL_CTIMER_SEGMENT_TIME_KEEPER AM_HAL_CTIMER_TIMERA +#define LP_TICKER_AM_HAL_CTIMER_SEGMENT_INT_COUNTER AM_HAL_CTIMER_TIMERB +#define LP_TICKER_AM_HAL_CTIMER_NUMBER 7 +#define LP_TICKER_AM_HAL_CTIMER_TIME_KEEPER_FN AM_HAL_CTIMER_FN_CONTINUOUS +#define LP_TICKER_AM_HAL_CTIMER_INT_COUNTER_FN AM_HAL_CTIMER_FN_ONCE +#define LP_TICKER_AM_HAL_CTIMER_CMPR_REG 0 // CMPR0 reg used with CTIMER_FN_CONTINUOUS mode +#define LP_TICKER_AM_HAL_CTIMER_CMPR_INT AM_HAL_CTIMER_INT_TIMERB7C0 +//#define LP_TICKER_AM_HAL_CTIMER_CMPR_INT1 AM_HAL_CTIMER_INT_TIMERA7C1 + +// Automatic configuration + +#if (LP_TICKER_AM_HAL_CTIMER_SEGMENT == AM_HAL_CTIMER_BOTH) +#define LP_TICKER_BITS 32 +#else +#define LP_TICKER_BITS 16 +#endif // (LP_TICKER_AM_HAL_CTIMER_SEGMENT == AM_HAL_CTIMER_BOTH) + +// #endif // MBED_US_TICKER_DEFINES_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/mbed_rtx.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/mbed_rtx.h new file mode 100644 index 0000000000..6448395a11 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/mbed_rtx.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +/* This file is required, but doesn't actually need to do anything. */ + +#define INITIAL_SP MBED_RAM1_START + MBED_RAM1_SIZE - 8 + +#endif /* MBED_MBED_RTX_H */ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects.h new file mode 100644 index 0000000000..f94c642258 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "am_mcu_apollo.h" +#include "am_bsp.h" +#include "am_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "objects_flash.h" +#include "objects_gpio.h" +#include "objects_uart.h" +#include "objects_iom.h" +#include "objects_spi.h" +#include "objects_i2c.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_flash.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_flash.h new file mode 100644 index 0000000000..e9e2ccb754 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_flash.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_FLASH_H +#define MBED_OBJECTS_FLASH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +struct flash_u { + uint32_t reserved; //No information needs to be passed to api right now +}; + +struct flash_s { + struct flash_u flash; +}; + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_FLASH_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h new file mode 100644 index 0000000000..67685c3fec --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_gpio.h @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_GPIO_H +#define MBED_OBJECTS_GPIO_H + +#include "am_hal_gpio.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef uint32_t ap3_gpio_pad_t; + +typedef enum { + PIN_INPUT = 0x00, + PIN_OUTPUT, + + PIN_DIR_ELEMENTS +} PinDirection; + +enum sPinMode { + sPowerSwNone = 0x00, + sPowerSwVDD, + sPowerSwVSS, + sPullNone, + sPullUp, + sPullDown, + sPullUp1K5, + sPullUp6K, + sPullUp12K, + sPullUp24K, + sDriveStrength2mA, + sDriveStrength4mA, + sDriveStrength8mA, + sDriveStrength12mA, + sOutDisable, + sOutPushPull, + sOutOpenDrain, + sOutTristate, + sInAuto, + sInNone, + sInEnable, + sReadPin, + sReadZero, + + sPinModeElements +}; + +#define PinModeEntry(e) e = (1 << s##e) + +typedef enum { + PinModeEntry(PowerSwNone), + PinModeEntry(PowerSwVDD), + PinModeEntry(PowerSwVSS), + PowerSwDefault = PowerSwNone, + + PinModeEntry(PullNone), + PinModeEntry(PullUp), + PinModeEntry(PullDown), + PinModeEntry(PullUp1K5), + PinModeEntry(PullUp6K), + PinModeEntry(PullUp12K), + PinModeEntry(PullUp24K), + PullDefault = PullNone, + + PinModeEntry(DriveStrength2mA), + PinModeEntry(DriveStrength4mA), + PinModeEntry(DriveStrength8mA), + PinModeEntry(DriveStrength12mA), + DriveStrengthDefault = DriveStrength12mA, + + PinModeEntry(OutDisable), + PinModeEntry(OutPushPull), + PinModeEntry(OutOpenDrain), + PinModeEntry(OutTristate), + OutDefault = OutPushPull, + + PinModeEntry(InAuto), + PinModeEntry(InNone), + PinModeEntry(InEnable), + InDefault = InEnable, + + PinModeEntry(ReadPin), + PinModeEntry(ReadZero), + ReadDefault = ReadPin, + + PinModeEntry(PinModeElements) +} PinMode; + +typedef struct _gpio_t { + ap3_gpio_pad_t pad; + am_hal_gpio_pincfg_t cfg; +} gpio_t; + +typedef struct ap3_gpio_irq_control_t { + ap3_gpio_pad_t pad; + uint32_t id; + void *handler; + uint8_t events; +} ap3_gpio_irq_control_t; + +typedef struct gpio_irq_s { + ap3_gpio_irq_control_t *control; +} gpio_irq_s; + +#define AP3_PINCFG_FUNCSEL_GPIO 3 + +#define AP3_GPIO_MAX_PADS (50) +#define PADREG_FLD_76_S 6 +#define PADREG_FLD_FNSEL_S 3 +#define PADREG_FLD_DRVSTR_S 2 +#define PADREG_FLD_INPEN_S 1 +#define PADREG_FLD_PULLUP_S 0 + +#define GPIOCFG_FLD_INTD_S 3 +#define GPIOCFG_FLD_OUTCFG_S 1 +#define GPIOCFG_FLD_INCFG_S 0 + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_GPIO_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_i2c.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_i2c.h new file mode 100644 index 0000000000..2f3e073e07 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_i2c.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_I2C_H +#define MBED_OBJECTS_I2C_H + +#include "objects_iom.h" + +#if DEVICE_I2C_ASYNCH +struct i2c_s { + iom_t iom_obj; +}; +#else +struct i2c_u { + iom_t iom_obj; +}; +struct i2c_s { + struct i2c_u i2c; +}; +#endif // DEVICE_I2C_ASYNCH + +#endif // MBED_OBJECTS_I2C_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_iom.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_iom.h new file mode 100644 index 0000000000..635cd7ff18 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_iom.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_IOM_H +#define MBED_OBJECTS_IOM_H + +#include "am_hal_iom.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +struct iom_s { + uint32_t inst; // IOM module instance + void *handle; // IOM handle + am_hal_iom_config_t cfg; // IOM configuration +}; + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_IOM_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_spi.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_spi.h new file mode 100644 index 0000000000..3cc8e177fd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_spi.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_SPI_H +#define MBED_OBJECTS_SPI_H + +#include "iom_api.h" + +#if DEVICE_SPI_ASYNCH +struct spi_s { + iom_t iom_obj; +}; +#else +struct spi_u { + iom_t iom_obj; +}; +struct spi_s { + struct spi_u spi; +}; +#endif // DEVICE_SPI_ASYNCH + +#endif // MBED_OBJECTS_SPI_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_uart.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_uart.h new file mode 100644 index 0000000000..576e6f2285 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/objects_uart.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_OBJECTS_UART_H +#define MBED_OBJECTS_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef uint32_t ap3_uart_pad_t; +typedef uint32_t ap3_uart_inst_t; + +typedef struct _ap3_uart_pad_map_elem_t { + ap3_uart_pad_t pad; + uint8_t funcsel; +} ap3_uart_pad_map_elem_t; + +typedef struct _ap3_uart_control_t { + ap3_uart_inst_t inst; // UART module instance + void *handle; // UART handle + am_hal_uart_config_t cfg; // UART configuration + uint32_t serial_irq_id; +} ap3_uart_control_t; + +#if DEVICE_SERIAL_ASYNCH +struct serial_s { + ap3_uart_control_t *uart_control; +}; +#else +struct serial_u { + ap3_uart_control_t *uart_control; +}; +struct serial_s { + struct serial_u serial; +}; +#endif // DEVICE_SERIAL_ASYNCH + +#ifdef __cplusplus +} +#endif + +#endif // MBED_OBJECTS_UART_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/pinmap.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/pinmap.c new file mode 100644 index 0000000000..9aa95f61df --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/pinmap.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +#include "extensions.h" +#include "am_mcu_apollo.h" + +void pin_config(PinName pin, am_hal_gpio_pincfg_t pincfg) +{ + if (pin == (PinName)NC) { + return; + } + MBED_ASSERT(AM_HAL_STATUS_SUCCESS == am_hal_gpio_pinconfig(pin, pincfg)); +} + +void pinmap_config(PinName pin, const PinMap *map) +{ + // fully configure a pin by a pin map entry + if (pin == NC) { + return; + } + + am_hal_gpio_pincfg_t pincfg; + while (map->pin != NC) { + if (map->pin == pin) { + pincfg = *((am_hal_gpio_pincfg_t *)(map->function)); + pin_config(pin, pincfg); + return; + } + map++; + } + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "could not pinmap_config", pin); +} + +void pin_function(PinName pin, int function) +{ + // am_hal_gpio_pincfg_t cfg = {0}; + // cfg.uFuncSel = function; + // am_hal_gpio_pinconfig((uint32_t)(pin), cfg); // apply configuration + +#define PADREG_FLD_FNSEL_S 3 + + uint32_t ui32Padreg; + uint32_t ui32Funcsel; + + MBED_ASSERT(pin < AM_HAL_GPIO_MAX_PADS); + + // + // Initialize the PADREG accumulator variables. + // + ui32Padreg = 0; + + // Get the requested function + ui32Funcsel = (uint32_t)function; + + ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S; + + // + // At this point, the configuration variable ui32Padreg, + // values is set (at bit position 0) and ready to write + // to its respective register bitfields. + // + uint32_t ui32PadregAddr; + uint32_t ui32PadClearMask; + uint32_t ui32PadShft; + + ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (pin & ~0x3); + + ui32PadShft = ((pin & 0x3) << 3); + ui32PadClearMask = ~((uint32_t)0x38 << ui32PadShft); + + // Get the new values into their rightful bit positions. + ui32Padreg <<= ui32PadShft; + + AM_CRITICAL_BEGIN + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END +} + +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(0); + // gpio_t obj = { + // .pad = (ap3_gpio_pad_t)pin, + // .cfg = {0}, + // }; + // gpio_mode(gpio_t * obj, PinMode mode) +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c new file mode 100644 index 0000000000..83d23f3483 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if DEVICE_SERIAL + +#include "serial_api.h" + +#include "mbed_assert.h" +#include "PeripheralPins.h" + +// globals +int stdio_uart_inited = 0; +serial_t stdio_uart; +bool value = false; + +// interrupt variables +static uart_irq_handler irq_handler; +static ap3_uart_control_t ap3_uart_control[AM_REG_UART_NUM_MODULES]; + +// forward declarations +extern void am_uart_isr(void); +extern void am_uart1_isr(void); +void uart_configure_pin_function(PinName pin, UARTName uart, const PinMap *map); + +/** + * \defgroup hal_GeneralSerial Serial Configuration Functions + * + * # Defined behavior + * * ::serial_init initializes the ::serial_t + * * ::serial_init sets the default parameters for serial peripheral (9600 bps, 8N1 format) + * * ::serial_init configures the specified pins + * * ::serial_free releases the serial peripheral + * * ::serial_baud configures the baud rate + * * at least 9600 bps the baud rate must be supported + * * ::serial_format configures the transmission format (number of bits, parity and the number of stop bits) + * * at least 8N1 format must be supported + * * ::serial_irq_handler registers the interrupt handler which will be invoked when the interrupt fires. + * * ::serial_irq_set enables or disables the serial RX or TX IRQ. + * * If `RxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever + * Receive Data Register Full IRQ is generated. + * * If `TxIrq` is enabled by ::serial_irq_set, ::serial_irq_handler will be invoked whenever + * Transmit Data Register Empty IRQ is generated. + * * If the interrupt condition holds true, when the interrupt is enabled with ::serial_irq_set, + * the ::serial_irq_handler is called instantly. + * * ::serial_getc returns the character from serial buffer. + * * ::serial_getc is a blocking call (waits for the character). + * * ::serial_putc sends a character. + * * ::serial_putc is a blocking call (waits for a peripheral to be available). + * * ::serial_readable returns non-zero value if a character can be read, 0 otherwise. + * * ::serial_writable returns non-zero value if a character can be written, 0 otherwise. + * * ::serial_clear clears the ::serial_t RX/TX buffers + * * ::serial_break_set sets the break signal. + * * ::serial_break_clear clears the break signal. + * * ::serial_pinout_tx configures the TX pin as an output (to be used in half-duplex mode). + * * ::serial_set_flow_control configures serial flow control. + * * ::serial_set_flow_control sets flow control in the hardware if a serial peripheral supports it, + * otherwise software emulation is used. + * * ::serial_tx_asynch starts the serial asynchronous transfer. + * * ::serial_tx_asynch writes `tx_length` bytes from the `tx` to the bus. + * * ::serial_tx_asynch must support 8 data bits + * * The callback given to ::serial_tx_asynch is invoked when the transfer completes. + * * ::serial_tx_asynch specifies the logical OR of events to be registered. + * * The ::serial_tx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm. + * * ::serial_rx_asynch starts the serial asynchronous transfer. + * * ::serial_rx_asynch reads `rx_length` bytes to the `rx` buffer. + * * ::serial_rx_asynch must support 8 data bits + * * The callback given to ::serial_rx_asynch is invoked when the transfer completes. + * * ::serial_rx_asynch specifies the logical OR of events to be registered. + * * The ::serial_rx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm. + * * ::serial_rx_asynch specifies a character in range 0-254 to be matched, 255 is a reserved value. + * * If SERIAL_EVENT_RX_CHARACTER_MATCH event is not registered, the `char_match` is ignored. + * * The SERIAL_EVENT_RX_CHARACTER_MATCH event is set in the callback when SERIAL_EVENT_RX_CHARACTER_MATCH event is + * registered AND `char_match` is present in the received data. + * * ::serial_tx_active returns non-zero if the TX transaction is ongoing, 0 otherwise. + * * ::serial_rx_active returns non-zero if the RX transaction is ongoing, 0 otherwise. + * * ::serial_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise returns 0. + * * ::serial_irq_handler_asynch takes no longer than one packet transfer time (packet_bits / baudrate) to execute. + * * ::serial_tx_abort_asynch aborts the ongoing TX transaction. + * * ::serial_tx_abort_asynch disables the enabled interupt for TX. + * * ::serial_tx_abort_asynch flushes the TX hardware buffer if TX FIFO is used. + * * ::serial_rx_abort_asynch aborts the ongoing RX transaction. + * * ::serial_rx_abort_asynch disables the enabled interupt for RX. + * * ::serial_rx_abort_asynch flushes the TX hardware buffer if RX FIFO is used. + * * Correct operation guaranteed when interrupt latency is shorter than one packet transfer time (packet_bits / baudrate) + * if the flow control is not used. + * * Correct operation guaranteed regardless of interrupt latency if the flow control is used. + * + * # Undefined behavior + * * Calling ::serial_init multiple times on the same `serial_t` without ::serial_free. + * * Passing invalid pin to ::serial_init, ::serial_pinout_tx. + * * Calling any function other than ::serial_init on am uninitialized or freed `serial_t`. + * * Passing an invalid pointer as `obj` to any function. + * * Passing an invalid pointer as `handler` to ::serial_irq_handler, ::serial_tx_asynch, ::serial_rx_asynch. + * * Calling ::serial_tx_abort while no async TX transfer is being processed. + * * Calling ::serial_rx_abort while no async RX transfer is being processed. + * * Devices behavior is undefined when the interrupt latency is longer than one packet transfer time + * (packet_bits / baudrate) if the flow control is not used. + * @{ + */ + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, serial_tx_pinmap()); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, serial_rx_pinmap()); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + obj->serial.uart_control = &ap3_uart_control[uart]; + obj->serial.uart_control->inst = uart; + + // config uart pins + pinmap_config(tx, serial_tx_pinmap()); + pinmap_config(rx, serial_rx_pinmap()); + + if (!obj->serial.uart_control->handle) { + // if handle uninitialized this is first time set up + // ensure that HAL queueing is disabled (we want to use the FIFOs directly) + obj->serial.uart_control->cfg.pui8RxBuffer = NULL; + obj->serial.uart_control->cfg.pui8TxBuffer = NULL; + obj->serial.uart_control->cfg.ui32RxBufferSize = 0; + obj->serial.uart_control->cfg.ui32TxBufferSize = 0; + + obj->serial.uart_control->cfg.ui32FifoLevels = AM_HAL_UART_RX_FIFO_7_8; + + // start UART instance + MBED_ASSERT(am_hal_uart_initialize(uart, &(obj->serial.uart_control->handle)) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_uart_power_control(obj->serial.uart_control->handle, AM_HAL_SYSCTRL_WAKE, false) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS); + + // set default format + serial_format(obj, 8, ParityNone, 1); + } +} + +void serial_free(serial_t *obj) +{ + // nothing to do unless resources are allocated for members of the serial_s serial member of obj + // assuming mbed handles obj and its members +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->serial.uart_control->cfg.ui32BaudRate = (uint32_t)baudrate; + MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint32_t am_hal_data_bits = 0; + switch (data_bits) { + case 5: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_5; + break; + case 6: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_6; + break; + case 7: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_7; + break; + case 8: + am_hal_data_bits = AM_HAL_UART_DATA_BITS_8; + break; + default: + MBED_ASSERT(0); + break; + } + + uint32_t am_hal_parity = AM_HAL_UART_PARITY_NONE; + switch (parity) { + case ParityNone: + am_hal_parity = AM_HAL_UART_PARITY_NONE; + break; + case ParityOdd: + am_hal_parity = AM_HAL_UART_PARITY_ODD; + break; + case ParityEven: + am_hal_parity = AM_HAL_UART_PARITY_EVEN; + break; + default: // fall-through intentional after default + case ParityForced1: + case ParityForced0: + MBED_ASSERT(0); + break; + } + + uint32_t am_hal_stop_bits = 0; + switch (stop_bits) { + case 1: + am_hal_stop_bits = AM_HAL_UART_ONE_STOP_BIT; + break; + case 2: + am_hal_stop_bits = AM_HAL_UART_TWO_STOP_BITS; + break; + default: + MBED_ASSERT(0); + } + + obj->serial.uart_control->cfg.ui32DataBits = (uint32_t)am_hal_data_bits; + obj->serial.uart_control->cfg.ui32Parity = (uint32_t)am_hal_parity; + obj->serial.uart_control->cfg.ui32StopBits = (uint32_t)am_hal_stop_bits; + MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + obj->serial.uart_control->serial_irq_id = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + MBED_ASSERT(obj->serial.uart_control->handle != NULL); + if (enable) { + switch (irq) { + case RxIrq: + MBED_ASSERT(am_hal_uart_interrupt_enable(obj->serial.uart_control->handle, AM_HAL_UART_INT_RX) == AM_HAL_STATUS_SUCCESS); + break; + case TxIrq: + MBED_ASSERT(am_hal_uart_interrupt_enable(obj->serial.uart_control->handle, AM_HAL_UART_INT_TXCMP) == AM_HAL_STATUS_SUCCESS); + break; + default: + break; + } + // NVIC_SetVector(uart_irqs[obj->serial.index], vector); + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + obj->serial.uart_control->inst)); + } else { // disable + switch (irq) { + case RxIrq: + MBED_ASSERT(am_hal_uart_interrupt_disable(obj->serial.uart_control->handle, AM_HAL_UART_INT_RX) == AM_HAL_STATUS_SUCCESS); + break; + case TxIrq: + MBED_ASSERT(am_hal_uart_interrupt_disable(obj->serial.uart_control->handle, AM_HAL_UART_INT_TXCMP) == AM_HAL_STATUS_SUCCESS); + break; + default: + break; + } + } +} + +int serial_getc(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + + uint8_t rx_c = 0x00; + volatile uint32_t bytes_read = 0x00; + am_hal_uart_transfer_t am_hal_uart_xfer_read_single = { + .ui32Direction = AM_HAL_UART_READ, + .pui8Data = (uint8_t *) &rx_c, + .ui32NumBytes = 1, + .ui32TimeoutMs = 0, + .pui32BytesTransferred = (uint32_t *) &bytes_read, + }; + + do { + am_hal_uart_transfer(obj->serial.uart_control->handle, &am_hal_uart_xfer_read_single); + } while (bytes_read == 0); + + return (int)rx_c; +} + +void serial_putc(serial_t *obj, int c) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + + volatile uint32_t bytes_sent = 0; + am_hal_uart_transfer_t am_hal_uart_xfer_write_single = { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *)(&c), + .ui32NumBytes = 1, + .ui32TimeoutMs = 0, + .pui32BytesTransferred = (uint32_t *) &bytes_sent, + }; + + do { + am_hal_uart_transfer(obj->serial.uart_control->handle, &am_hal_uart_xfer_write_single); + } while (bytes_sent == 0); +} + +int serial_readable(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + return !(UARTn(obj->serial.uart_control->inst)->FR_b.RXFE); +} + +int serial_writable(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + return !(UARTn(obj->serial.uart_control->inst)->FR_b.TXFF); +} + +void serial_clear(serial_t *obj) +{ + // todo: + MBED_ASSERT(0); +} + +void serial_break_set(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + UARTn(obj->serial.uart_control->inst)->LCRH |= UART0_LCRH_BRK_Msk; +} + +void serial_break_clear(serial_t *obj) +{ + MBED_ASSERT(obj->serial.uart_control != NULL); + UARTn(obj->serial.uart_control->inst)->LCRH &= ~UART0_LCRH_BRK_Msk; +} + +void serial_pinout_tx(PinName tx) +{ + // todo: vestigial? + MBED_ASSERT(0); +} + +#if DEVICE_SERIAL_FC + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + // todo: + MBED_ASSERT(0); +} + +void serial_set_flow_control_direct(serial_t *obj, FlowControl type, const serial_fc_pinmap_t *pinmap) +{ + // todo: + MBED_ASSERT(0); +} +#endif + +const PinMap *serial_tx_pinmap(void) +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap(void) +{ + return PinMap_UART_RX; +} + +#if DEVICE_SERIAL_FC + +const PinMap *serial_cts_pinmap(void) +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap(void) +{ + return PinMap_UART_RTS; +} +#endif + +static inline void uart_irq(uint32_t instance) +{ + void *handle = ap3_uart_control[instance].handle; + MBED_ASSERT(handle != NULL); + + // check flags + uint32_t status = 0x00; + MBED_ASSERT(am_hal_uart_interrupt_status_get(handle, &status, true) == AM_HAL_STATUS_SUCCESS); + MBED_ASSERT(am_hal_uart_interrupt_clear(handle, status) == AM_HAL_STATUS_SUCCESS); + + if (ap3_uart_control[instance].serial_irq_id != 0) { + if (status & AM_HAL_UART_INT_TXCMP) { // for transmit complete + if (irq_handler) { + irq_handler(ap3_uart_control[instance].serial_irq_id, TxIrq); + } + } + if (status & AM_HAL_UART_INT_RX) { // for receive complete + if (irq_handler) { + irq_handler(ap3_uart_control[instance].serial_irq_id, RxIrq); + } + } + } +} + +extern void am_uart_isr(void) +{ + uart_irq(UART_0); +} + +extern void am_uart1_isr(void) +{ + uart_irq(UART_1); +} + +#ifdef __cplusplus +} +#endif + +#endif + +/** @}*/ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c new file mode 100644 index 0000000000..fb44cbd08e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/spi_api.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if DEVICE_SPI + +#include "spi_api.h" +#include "iom_api.h" +#include "PeripheralPins.h" +#include "mbed_assert.h" + +#include + +#define DEFAULT_CLK_FREQ (4000000) +#define DEFAULT_SPI_MODE (AM_HAL_IOM_SPI_MODE_0) + +static am_hal_iom_transfer_t xfer = {0}; + +SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) +{ + uint32_t iom_mosi = pinmap_peripheral(mosi, spi_master_mosi_pinmap()); + uint32_t iom_miso = pinmap_peripheral(miso, spi_master_miso_pinmap()); + uint32_t iom_sclk = pinmap_peripheral(sclk, spi_master_clk_pinmap()); + + uint32_t iom; + + if (miso == NC) { + iom = pinmap_merge(iom_mosi, iom_sclk); + } else if (mosi == NC) { + iom = pinmap_merge(iom_miso, iom_sclk); + } else { + uint32_t iom_data = pinmap_merge(iom_mosi, iom_miso); + iom = pinmap_merge(iom_data, iom_sclk); + } + + if ((int)iom == NC) { + return IOM_NUM; + } + + return (SPIName)iom; +} + +void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap) +{ + MBED_ASSERT(cap); + + SPIName iom_ssel = (SPIName)pinmap_peripheral(ssel, spi_master_cs_pinmap()); + + cap->minimum_frequency = 0; + cap->maximum_frequency = AM_HAL_IOM_MAX_FREQ; + cap->word_length = 0x00000080; + cap->slave_delay_between_symbols_ns = 0; + cap->clk_modes = 0x0F; + cap->support_slave_mode = (iom_ssel == IOM_ANY) ? true : false; + cap->hw_cs_handle = false; + cap->async_mode = false; + cap->tx_rx_buffers_equal_length = false; +} + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + MBED_ASSERT(obj); + + MBED_ASSERT((int)ssel == NC); + + // iom determination + SPIName iom = spi_get_peripheral_name(mosi, miso, sclk); + MBED_ASSERT((int)iom != IOM_NUM); + MBED_ASSERT((int)iom != IOM_ANY); + + // iom configuration + obj->spi.iom_obj.iom.inst = (uint32_t)iom; + obj->spi.iom_obj.iom.cfg.eInterfaceMode = AM_HAL_IOM_SPI_MODE; + obj->spi.iom_obj.iom.cfg.ui32ClockFreq = DEFAULT_CLK_FREQ; + obj->spi.iom_obj.iom.cfg.eSpiMode = DEFAULT_SPI_MODE; + obj->spi.iom_obj.iom.cfg.pNBTxnBuf = NULL; + obj->spi.iom_obj.iom.cfg.ui32NBTxnBufLength = 0; + + // invariant xfer settings + xfer.ui32InstrLen = 0; + xfer.ui32Instr = 0; + xfer.bContinue = false; + xfer.ui8RepeatCount = 0; + xfer.ui8Priority = 1; + xfer.ui32PauseCondition = 0; + xfer.ui32StatusSetClr = 0; + + // pin configuration + pinmap_config(sclk, spi_master_clk_pinmap()); + if ((int)mosi != NC) { + pinmap_config(mosi, spi_master_mosi_pinmap()); + } + if ((int)miso != NC) { + pinmap_config(miso, spi_master_miso_pinmap()); + } + if ((int)ssel != NC) { + pinmap_config(ssel, spi_master_cs_pinmap()); + } + + // initialization + iom_init(&obj->spi.iom_obj); +} + +void spi_free(spi_t *obj) +{ + iom_deinit(&obj->spi.iom_obj); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT(obj); + obj->spi.iom_obj.iom.cfg.eSpiMode = (am_hal_iom_spi_mode_e)mode; + iom_init(&obj->spi.iom_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + MBED_ASSERT(obj); + obj->spi.iom_obj.iom.cfg.ui32ClockFreq = (uint32_t)hz; + iom_init(&obj->spi.iom_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + uint32_t rxval = 0; + spi_master_block_write(obj, (const char *)&value, 1, (char *)&rxval, 1, 0x00); + return rxval; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + MBED_ASSERT(obj); + + int chars_handled = 0; + + // perform a duplex xfer for the smaller of the two buffers + xfer.eDirection = AM_HAL_IOM_FULLDUPLEX; + xfer.ui32NumBytes = (tx_length > rx_length) ? rx_length : tx_length; + xfer.pui32RxBuffer = (uint32_t *)rx_buffer; + xfer.pui32TxBuffer = (uint32_t *)tx_buffer; + + if (xfer.ui32NumBytes) { + uint32_t status = am_hal_iom_spi_blocking_fullduplex(obj->spi.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return 0; + } + chars_handled += xfer.ui32NumBytes; + } + + // handle difference between buffers + if (tx_length != rx_length) { + bool Rw = (rx_length >= tx_length); + + // set up common config + xfer.eDirection = (Rw) ? AM_HAL_IOM_RX : AM_HAL_IOM_TX; + xfer.ui32NumBytes = (Rw) ? (rx_length - tx_length) : (tx_length - rx_length); + xfer.pui32RxBuffer = (Rw) ? (uint32_t *)(rx_buffer + chars_handled) : NULL; + xfer.pui32TxBuffer = (Rw) ? NULL : (uint32_t *)(tx_buffer + chars_handled); + + uint32_t status = AM_HAL_STATUS_SUCCESS; + if (!Rw || (write_fill == 0x00)) { + // when transmitting (w) or reading with a zero fill just use a simplex transfer + status = am_hal_iom_blocking_transfer(obj->spi.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return chars_handled; + } + chars_handled += xfer.ui32NumBytes; + } else { + // when reading with a nonzero fill use a duplex transfer + uint8_t fill[xfer.ui32NumBytes]; + memset(fill, write_fill, xfer.ui32NumBytes); + xfer.eDirection = AM_HAL_IOM_FULLDUPLEX; + xfer.pui32TxBuffer = (uint32_t *)&fill; + uint32_t status = am_hal_iom_spi_blocking_fullduplex(obj->spi.iom_obj.iom.handle, &xfer); + if (AM_HAL_STATUS_SUCCESS != status) { + return chars_handled; + } + chars_handled += xfer.ui32NumBytes; + } + } + + return chars_handled; +} + +int spi_slave_receive(spi_t *obj) +{ + MBED_ASSERT(0); + return 0; +} + +int spi_slave_read(spi_t *obj) +{ + MBED_ASSERT(0); + return 0; +} + +void spi_slave_write(spi_t *obj, int value) +{ + MBED_ASSERT(0); +} + +int spi_busy(spi_t *obj) +{ + MBED_ASSERT(0); + return 0; +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#endif // DEVICE_SPI diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c new file mode 100644 index 0000000000..9c962b2d63 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "us_ticker_api.h" +#include +/** + * \defgroup hal_us_ticker Microsecond Ticker + * Low level interface to the microsecond ticker of a target + * + * # Defined behavior + * * Has a reported frequency between 250KHz and 8MHz for counters which are less than 32 bits wide - Verified by test ::us_ticker_info_test + * * Has a reported frequency up to 100MHz for counters which are 32 bits wide - Verified by test ::us_ticker_info_test + * * Has a counter that is at least 16 bits wide - Verified by test ::us_ticker_info_test + * * All behavior defined by the @ref hal_ticker_shared "ticker specification" + * + * # Undefined behavior + * * See the @ref hal_ticker_shared "ticker specification" + * + * @see hal_us_ticker_tests + * + * # Compile-time optimization macros + * + + * @{ + */ + +/** + * \defgroup hal_us_ticker_tests Microsecond Ticker tests + * Tests to validate the proper implementation of the microsecond ticker + * + * To run the microsecond ticker hal tests use the command: + * + * mbed test -t -m -n tests-mbed_hal-common_ticker*,tests-mbed_hal-us_ticker* + * + * @see hal_ticker_tests + * + */ +/* HAL us ticker */ + +static bool us_ticker_initialized = false; + +/** Initialize the ticker + * + * Initialize or re-initialize the ticker. This resets all the + * clocking and prescaler registers, along with disabling + * the compare interrupt. + * + * @note Initialization properties tested by ::ticker_init_test + * + */ +void us_ticker_init(void) +{ + if (us_ticker_initialized) { + am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE); + return; + } + + NVIC_SetVector(STIMER_CMPR0_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(STIMER_CMPR0_IRQn); + am_hal_stimer_config(AM_HAL_STIMER_CFG_CLEAR | AM_HAL_STIMER_CFG_FREEZE); + am_hal_stimer_config(US_TICKER_FREQ); + us_ticker_initialized = true; +} + +/** Deinitialize the us ticker + * + * Powerdown the us ticker in preparation for sleep, powerdown, or reset. + * + * After this function is called, no other ticker functions should be called + * except us_ticker_init(), calling any function other than init is undefined. + * + * @note This function stops the ticker from counting. + * + */ +void us_ticker_free(void) +{ + am_hal_stimer_config(AM_HAL_STIMER_CFG_FREEZE); + am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE); + us_ticker_initialized = false; +} + +/** Read the current counter + * + * Read the current counter value without performing frequency conversions. + * If no rollover has occurred, the seconds passed since us_ticker_init() + * was called can be found by dividing the ticks returned by this function + * by the frequency returned by ::us_ticker_get_info. + * + * @return The current timer's counter value in ticks + * + */ +uint32_t us_ticker_read(void) +{ + return am_hal_stimer_counter_get(); +} + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in ticks to be set + * + * @note no special handling needs to be done for times in the past + * as the common timer code will detect this and call + * us_ticker_fire_interrupt() if this is the case + * + * @note calling this function with timestamp of more than the supported + * number of bits returned by ::us_ticker_get_info results in undefined + * behavior. + * + */ +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + + uint32_t instance = 0; + switch (US_TICKER_STIMER_INT_COMPARE) { + default: + case AM_HAL_STIMER_INT_COMPAREA: + instance = 0; + break; + case AM_HAL_STIMER_INT_COMPAREB: + instance = 1; + break; + case AM_HAL_STIMER_INT_COMPAREC: + instance = 2; + break; + case AM_HAL_STIMER_INT_COMPARED: + instance = 3; + break; + case AM_HAL_STIMER_INT_COMPAREE: + instance = 4; + break; + case AM_HAL_STIMER_INT_COMPAREF: + instance = 5; + break; + case AM_HAL_STIMER_INT_COMPAREG: + instance = 6; + break; + case AM_HAL_STIMER_INT_COMPAREH: + instance = 7; + break; + } + + am_hal_stimer_int_enable(US_TICKER_STIMER_INT_COMPARE); + timestamp_t now = (timestamp_t)am_hal_stimer_counter_get(); + am_hal_stimer_compare_delta_set(instance, (timestamp - now)); + CTIMER->STCFG |= (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << instance); +} + +/** Disable us ticker interrupt + * + */ +void us_ticker_disable_interrupt(void) +{ + am_hal_stimer_int_disable(US_TICKER_STIMER_INT_COMPARE); +} + +/** Clear us ticker interrupt + * + */ +void us_ticker_clear_interrupt(void) +{ + am_hal_stimer_int_clear(US_TICKER_STIMER_INT_COMPARE); +} + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + * + */ +void us_ticker_fire_interrupt(void) +{ + am_hal_stimer_int_enable(US_TICKER_STIMER_INT_COMPARE); + am_hal_stimer_int_set(US_TICKER_STIMER_INT_COMPARE); +} + +/** Get frequency and counter bits of this ticker.*/ +const ticker_info_t *us_ticker_get_info(void) +{ + static const ticker_info_t info = { + 3000000, // 3 MHz + 32 // 32 bit counter + }; + return &info; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker_defines.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker_defines.h new file mode 100644 index 0000000000..45a4f4ec4a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/us_ticker_defines.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020 SparkFun Electronics + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef MBED_US_TICKER_DEFINES_H +#define MBED_US_TICKER_DEFINES_H + +// * US_TICKER_PERIOD_NUM, US_TICKER_PERIOD_DEN: These denote the ratio (numerator, denominator) +// * of the ticker period to a microsecond. For example, an 8MHz ticker would have NUM = 1, DEN = 8; +// * a 1MHz ticker would have NUM = 1, DEN = 1; a 250kHz ticker would have NUM = 4, DEN = 1. +// * Both numerator and denominator must be 16 bits or less. +#define US_TICKER_FREQ AM_HAL_STIMER_HFRC_3MHZ +#define US_TICKER_PERIOD_NUM 1 +#define US_TICKER_PERIOD_DEN 3 + +// * +// * US_TICKER_MASK: The value mask for the ticker - eg 0x07FFFFFF for a 27-bit ticker. +// * +#define US_TICKER_MASK 0xFFFFFFFF + +#define US_TICKER_COMPARE_INSTANCE A +#define US_TICKER_STIMER_INT_COMPARE_CONCATENATOR(a, b) a##b +#define US_TICKER_STIMER_INT_COMPARE_EVALUATOR(a, b) US_TICKER_STIMER_INT_COMPARE_CONCATENATOR(a, b) +#define US_TICKER_STIMER_INT_COMPARE US_TICKER_STIMER_INT_COMPARE_EVALUATOR(AM_HAL_STIMER_INT_COMPARE, US_TICKER_COMPARE_INSTANCE) + +#endif diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a new file mode 100644 index 0000000000000000000000000000000000000000..66efc87f62cf9d9ef826342e3463df2d6705da20 GIT binary patch literal 5359640 zcmeEvcUTll5N9t*f})tffDZ-3^N9i?Vn#8bqN1XrqARdVP%=vn>r-DcB4SRMbIv*E zoO8}O=X6ywJ-a=HTA11~{7z?KljE<&0F{lE9wSV+kK|NI}#f!)(OqLOBVN>ftm03oG5`4Wd((}+WG zK5-ZtOdQs(Bo5c^lG3)`q_od4Qaap^lpbA+l-_Wbl)mjp%Gf!PGM+)COur&h=D(Mu z%(|td%&kIFwzdZ;JLn`SJ8A$ayTY54Jz0vB{pdl;Rn?Gk{zdxF8jwk!?|VtPUwq0d zGl=dpcO)tQe46g#n3zL!pCe6)BmFr2<4v57uOt=9*C7@92kJkopOOmF=UoP=KtB~z zRixsck))EtT2iUUUHxayBvR@2M^d?35vd$SNaZCeQu+B;;#~Wt{!=uKIMYv+Ybx?v zRYHDKO(VZ8oU8k|G&)FxPx@WrB7F{ckgCP@lB%6TN!585N!7apNHvFHq*^N#sg{sI zs?B*xs@=>Wt|i=vtDlCrW?m((^Zq5Smy3v7RX5_6{gJrc4Iv?&;*&6d_#7=H4V`jG!x*3^ z5=p~PLB!Y9gZKtsB)(G*l1Ao5q)}%=8ZGiBjk{kYjjxB2ChbB5Wb>9kU$ zS&yZp*`14|d23(N!u>62u_K50)tg3ImIxv(lSY!3moiAJk<&=42O8pELPh*LT_pZ9 zqly2%v&8>tC}~~VjkNBzk+hzDmbAWlk+f-km$XsOC2b}rk~Y^LlD4*Pq;0bx(l#NQ zw4DW?Gj~ZlyMv@%BVW>PU@U1@RExB`9ZdpULP$UeApxVUNx)7w(w?YD``>{Ms!ZCi zyh++W&LbGmfeYz$u`=oOBZPFWw~%yJ4O*6bC1k zLg2*IdroTHaZj-i>ukkVGz>?S8-^pw4Z{)T2H{W`+R?aL4Z;zv`EW!jAC4&H!r^$3X^6pbxc&WM$dCLLVg$T)e3bc ztHWab6V#Edx9(UFib1Gm}t^tRH|4tLWvheVc;4_g8xs^EQV*gtT>8I6#Z$y;uOV~G?fNZ@tX?VM8qaSH4&rn;EYEF;jj&kaR^ftE5slS zgcyN=5ZpJAf$s(~aNI!VV+aQe51ckxUpx)LM4w@Zv38=*oKWIC?5`?6) zY(rKV8JiHM5d|;>qcy}PSW}i-iyUL!P-ZN0(7HlVfz#UxXRNtiKuhQaVs()*v9UT& zL`Jd{G>jF!-YO#!5;Jv0M1~d-8L^0PE)_`&OV*VT&S?QWmuylrDxHmRPHpg9vPq6h z(b)*+)CSKbo5X~4wZ1mWQ9H_s9*T@qEG{Nq2Q8e_BEq>?08e%1>M+J$V59;9LrdVf zu1Hvhz6Ly(3g9`lhf~QMRzQ$yeY_Gc=@VmA%4BtlTB8GHBvQOO8@5zTe2l!1C}7G6 z0;!0wkV_6z#bkJgXNofm_B~D<6Q8C|P7&8@I<*ucXDju5POO8V14B?tw!+OXOcKI< ziOfGi12c*V4bDj>R5*p1Pzh6>37s%Un$QW8stFy=geFvSaf&7^N-eHzuo2?a$t;W6 z6=D_&Nv$L_kgqa4RijZSN5*FA`jI}#zSw+{y-WBV5`8UuR+t1#Mh zw7AJaQtvRRMu$ebq~2F!-Oo!Y>(H#RtYaG}OonMvAvq=)u#l20B{3F;m(V~`z*@lFy6#UzGxRg$S9G~)Fdd!EQpe1Vbqz(@>i zWOx!IG`_c~KE^7f08y2gi1D6%i?EqF}tfZ7k)=nCeabX$=K%CMe#f7mFWf5_Su^Gy^ z)L4B_=EXF5oLF)I#hT=>c>RTqkuXI?8@5zRYPfFnU>SjDN+2(@j|jv419~wLN{AA+ zj38l48H6SZm@`Xv07_^IU7=nS+eT?d)%T7Xknldpg zSrY?2TF7leqCN!?s5K%@PFBZ;Y1BVc2{7W~N zUGO|ULA+ZKR_}TNZy}p(bY`-dMlO{aNGD|l251IAf`Ba|oyWu^Dn3dxGZ7GxwcuMFgd2%^1l7$a`6BGyG|6l0Ba zk&mZ*PGvI28OhGTd%40?3DzsA1S^Y)hshu@0aWtD%H#|rb-Q2DcxrreOrnTZio zB-SZ|MGJi^2?i{LY@S94QNTd3)+*RbhUrwE484#kr4t&Yfzy~QW3*lacXen6e(N>5 zIaHdBqz)L7pp#HH7>P8;NhY$Y^>(s)8L_TXn40zVA)~7b8L1XHmu6U*wNA*E(g}@} z=G#QMwVL_>Fj9s#1UChA1QNqNw+;|x2JQb5qwz= zjOl3#^(t6Fc*5c{gYMs0yzRAGoD zDmbXHC}j$)lagU?p2K1_axg|?h-QeQ8yTXHP+DF}m7q~3CMWO?=*6DnOi4=CujWOD8snam6o+um$feTk9+hw|RfJ!>(O$zY-PvWka4rsVcJ-bT z9mCuyQ%@1%G%EcRCwrZ}@*r7zA1^~Lo$BR?F6xw(v)o|lNS~zZ5(7=t{8=}68ZrqYYAQ~-UYEvh}}mH z$&YV@q_aO;lwJgQ5z}D$WgNF*WH^WX#MCq(>g6oWF1FGh+PGw01@wd$K$x4px3Gri1+9Y4+J zjQI{ES1@g-Q*bh4$i_eg8B>c7V!lR0-A~Gy@PHBH=74^WNor_Ts)uK# zx}^XkDJ(#z%5>*U7L z!zq7Ol5O&DP4HM~DMje#@54weCuDCJQEDT5&G@aX%rB+-}D@B2tm zNSizQQj$bpO26eJmC{AP_^OxbOX_91c}6FquGbSElhtjo(C2798u`kfpoIr(eSCae zT?U2UpL4QHcq)$|%0OV3QqLBIl^1+foqAqX(a`-1d{vVC2w6l~m3&l+6 zKgH+3sM|raXr{2*;6RA^1egdEe>h<~n<=cHz%Vyoflu`}bn-`$nPqMX5PgRfDH>Ji zDTs<)z=GQ`lbxJ!UNW<=oP<`^&=QI+6>pW(W^Gv;(9EohjR6D;3rn~m0P|wK zp|JT98_+nFaRYO6HK@&8$~46D&)}w+TiFh9Zn*&k6A`ISnSOY#fr-V;qiiCan^{|& z0#ozX_@`QhHz2aI_ym88?S}#ib8Ts;vW`7^Xzl{VERuzD>wM5!suhltKw)EHG2gr` zcw;*rys=nV+!4?1ASo7$%AlOsVQPB9S#h*CCnc;c=Gf!`Z~q=K=M@_ZVl!7_KO9nQ zvDnfLRA#Og#Jr^)@Jr0GsCh1euc-6@OiNl=S*RbI$ksa62% zWL3|)GPIQaXDd*6mcetV!$CQSSb5PJE$o+pn^saXe3=DWP`)9~^ zrTj26VmARa)xlZ_`8QI!6J#x4Vb#w%3DJdo_b-j-h`s?mQ(B2Bu&}QMVyiHlbU|xv zkB(V|SHWbNyZ)L`@m5;a$=)5rR(otQOJ=T>?Uz7oR{NaKKpxCo zUF`qBE_T5AyTH2HJCp(Ta0yrF`DU)Q?Dt|HIAYUWVCy(2Q^SeXaaxfFun@or8h|gb z5Wz`WZ&Ujg2zADxwNTd2{%_33S%+YO^>?Y|*=yZCS+q7eHL7|~sO9KmL;q4p=SqIR zytQLp3^>ZHipUptT#a2V#>`smYo#0?LLF8E&8%NQQq5e;I!;DM<0O0!$B|IIRlHew zOQ^@p)!Xq1CO=Wq`#RRdQIu?E>nP}(I>uuCsb+L4@pDYY;hZMfw|4v+CL^nKNgv?Y z2mQ}5E9)$j4|JS|Y0Q@FgB_ z=2!zAoNHDZ$B4P>Q8UL9C|GD#ydKnG?t0bIu@r{1%&b%rq|Ds)rlsR~#8_cw+eEN< zY6iE>#i_E5X81m`kcF9FT!A?)V>OtcHU2 z5DUkt7=KL#?IG4sBL;3|f$&ao&^-25Efm&Y5b7N^zMrBrG6R*vydu~jQY zY2gCxTAbM7i5;{kb-ThztHEZ)xyM~ z&0MV=wb-tInK|NR!pzmpu@YAOw^>O{wV7*x;}^vH$E?n9fe&)5jJf~Utm0O|)ey%^ z*suOGD=!YXXvZd4-*Aafbo>D2tVT$DhT}S{Z=_i%CDe~Ix??8<9A#E2K@j|_a16s> zM~fbqyA~-NSK-hbBSM(F&Q&-%f~i%$Bv`6&ECJ3~jgQ5k=IJRBdPGxYO-0e#UOBOggKpNRtXu* zxet#0>1Ixw1wMn=;jE5~0Od^VuyJr8QNH3!t2{IF7a*vFvyRnxGdpbDN~1AXGtBI; zRC+_|^Fnps$UhX7zb76zT6%35e2O9d=GNwFbjR&xO5w|-!+ zbxDR(;t~&k6fRAmB;b0&ELCijnQJ(oN?C8Tw(AHrIQoLndb4#|Tux#Gw1L!E zZ?P`@5ah5}bDWL(t=8o}3p{js$g=e|$-X$Tz6*1S^>%AZ0%(>93E+pU?H205k4VN8 z{HS&5=PdX!4*a-e58#iXg{)6lTlPb6gaq)*)^?WA14YlTO2!oYnsxcNEckT}{Dx!? z;J(nz);Fy!HzPPgR&cU@Vr^G|;4@)HvVLY=78f#@mbGAG{oK0DOo6v>T#xz}5^w2f z4)d|~OUd5au`{Oem6XQfjxA9CTH;GNmVusN{l>Z)RtDEFXsHmaVLrfHzqPh>1hM5L z(IpETyXsI{bjiv_?ou%uxl7g(PhGN+?5Rt(HZ=LvB|C|yE)}<_hLwpftwWbmv3*O} zST07FaFqjD^0l$aK$l{%c^cbP#pGd@{L!|F4ed;&9L9ga=#JFV9$|$EM zw<_28@vwMG^&gWYLlR|ftdQE%^QrVS!GmEn{hguV#IO?+Tf+Yre$SR zP@4@po07zGKH987m)lfE1+}@Nvw`Fs7Hlx`_LWfqHaPsh!>JItBe8srCa)oUo6b%s zrzTY)P{E`gv2=j*YHIYjn-j{ZNo&bONi4n5WCTpMHa(qCPEDdDlO4pe7n-a^lRi!; zrzRudRLGwe@|T4+=P{=KPN<+ZDhiZ4ZBD{Kvl-%q3TpF0vcddaN1Lr^^S2W!s7)D|%f+}Me`df`dklYUhC88x z+BDSJK>li=jW71m(N3tKHhpzAkiQOS(*iPPQ{aROg`(OEEHQx&)oN!ko+)%xR>RAw z%?vsKt6hYvq|IzP)~bC0S8e9gQB`d_%tkhg>G-LZfhf!ANU3%P`^IW%OyHdI9I6)5 zSO&sJmz>~_&8A8y2e;A00V1+{q~+1#*)H2~TKV&1M+LIt(40~ZBM7{k8#Yx#qyh=VG8qf_VB>$R zgmQ{GPcnHyEXSh>hH3My63VH`AvhJhzX6%r2#oVJtjSDK2{qK{xy}ft-)m^p9@AM& zQ3*BFs0{1{i+O;2ngQdi#C9pJsDv6=%+17(>!6@{aqfz~lvB`Y)p-_9TID5Hm}S)x z;*Z~mWiTRc!jVu>;e;AMY=DzbC5aVgmdR|Hf3Zvt%;RqgC)7Zh0?d+&j{SjwxGCr$ zaej#HQe8nukaH3`^}B)&6KBW~v8k<~W5_ud+qtfS4ix81M6Rb`uQxTz(VYBfK`hGy z<4n+~KGX*cc!O6{8*g3II5+kIjnG$q!0^W+opGx1RXCvna*Z~5l8u&F#-oiBrn-^B z2^G|44x9?@f$M+*H2MUSv`sUG6Kbf@L7fpa{{}Rwj?-*&g%fJ1(KDS9^zf@_l!Iw% zrEo$GH7Z?Rst%f80gQ7Y`t7f9LJc))s563m)Ig)rIP?6uFwTQ;TJ5E9LJc))r!#_l z_@Gfe>~Vb+PN;!=oW(?k%6fPfXoP$~k%3s`AM8Uag%c_$?hM9eG}<)8!4|D>LIv31 z8gLJs3i*KhBg@rjbQs4%oT4&nD9}UJ=mHvfVQonYC)9uu_Qn!U4ANIL8jQ`Ds&GOL zOkRg!oZ7n8EDfC$IQ-7ewz|aa2UFV`66Xd@Vp~(<@?k2nttD~E(0y%xm$+Hrhiz?% zyAR7E+dm|3AC{{laWha?wsu3VNTBv(7(*k8D~B;Ombf0!^tMeTt{2wV zRN|u1>t+(y54~+_?WYgK3fJ7-Jq4>sKEAyZr8njz;QaUGHKk+|N- zHI=w1Fqj-x606xsej*j9h`l{ej#hiED)142f%p++2z4f!tz=i$HFr#3doOUgEUK zZI!rD$nB9f)-YY>91Z0!^`fBOf(#t#qNqs^bZUYyE`(G9rPW$Co<6= zX!S-WDg_O1_k|VJFo)h|XReURszdLzvsXC#>OHGr2ffR#qFjb|nRYegvO)~XOD?m7 zQDWCzE~^3;IlB&WStQ!^l*?2YSh!r~3BB1aUM};4>D4Y<;XDr~5HXuITEJ+r`$sOD z2L0S_oLp8F>zyf=Il`*NZi!sxg1Ootmj$3~k6gABeK{eQErVIh?utxC6b_2&_GRqM z?JL=1%b2+lJG=pAC1ikh3Pt-eC@)?W;Oaq+OO%n>+q3q#WmOU@gztgMD9r6yUny=%bjFcZDujSoPP*EtMFr|5Wh>Gk zDO-sx4?BujBjP%Hi@^)HEsA5ds#riA&FwIU;3+NtTP?7w44vLZIDv4h3h9BSt41M& z1`#1#y-7PL+{n%hJarQpY%pZ2%gs?#L+%8Mgr7#hc!2|Y40H4Zp*abHzh;Ur&=l}< z9O$A1K8lFOq43~eRB~9H3%r9%o#Ij}!`J8c(5U!S7fnJ!Y>Ep!F6E+*3srywoiPHsV$4 z$S{0JPm`Gl528h5JHfMRD)@l`Fwlsx2@!+DGo1-Y!2$|`9A>0swOTTUXECBd2ps|+ ze4`xnK;$BXdZj1cqKQt-J{@O596?};k-b+Go|MBk-T`nc?#+|UilLr{bGI5nunr8I*&cu3;ro-Siku9GNaIl*s!>;WDn2K$b{rU^+WwTb#LEY*+8VBt-A+>1|=s9R7Yr1LfiTK z%lyQ*M?z=90h*Ai;Z)ELiI74K(D)Pr<1JxOj9T|PS>ctl%2qK^QX6wY32m%YYT}gX zs<2Fg@7#lFfuu@}#2-sFU{qY3RtCfJ(8+A(B++ zm%`Jl;$Nv3@goWw20el|7!qYnTw-dnTA8RxCdznqh9=UOkATm;ycptz7ji-p;pI&# z==L-b@QWeFP)Js6LVT2q@JBX&l<)!~O-!6x7+FeXO5652i;@_JtQVW)^X@7Q1gtlU1he<=;e){Tgz+(rNI-rN@ZGDY$`jsfRpVy_i*v|Z0I7aZiKa)rZ#`2Mg?(oBUcwRR` z(+tK4Q6@H!U#OWkgXlVtcvXWJ)UjD(6kJvMoFyiCv`B8+Fa$iqqy zCPp?QVZu$1h=x9%5T2sH)(DpkU(Q$@8xgSyDX?Tvrl?|Ikr^Y$6Gj1KNS6csC;%zb z4ZBLS4qggzwvP&niwhIhG;jusR%vR+FvLMGa~y}ZIID(3*Muu3EMjA0QefK0N14IB z9)SP>l&%3&(qdHlSMuXT3#&4r4W+E(4Gl?Tr#4~1Bh1(MAPv67y(P4TJ~sWbg>MGh zd!*%uZW^U>Xdd0H#7%uTN5TaY23$P+Opv;-#P=IQ@7Aqa#49jAE9j<8u0CNJWM)hK z92b+Kf|P+TJd`xS_z--TXIoevc9W%FoLMkFwoRpu%E*L^p{_UJbyJ@MWi(w4GWOUn zu=|?IkEt0Er#{nh=p%+ZCzIHSA>MZxxznmA1R;A9NQBr;VI>EnUzQ%Rcj8PD*u}r2 zGFTW+LQlfMhdrrVrvz0@WQZvtiZ=hhZO^5Dqsn%vw(ug1)l|mB6wvQw=jH>m%(
  • 9k^%%7p zb`$jXA~0s@MGq#xuvq=lE;T+iMGcF5VO@rk9bBc;Vcngkfyo@kT37}y`joLg-eJO8 zkPQaLsqv+i=u3F)AmPpm9mLs469+gj{hI81LNQtBbSlU6vlYt*hkhL@^l-zqESoIa zpu!9jFHHC8(B|MC{1q1DbZsScE>%i`G8z`p(6PgX`*VD0wm1(c^^tJ>7TXE3C%YpR zu6oSmBTjI-yOKnIs8!ykV&JAGGwDjm_eWu3P)4aW(7n_+ufPCNsSugBq;nfLXG>RV zVdEeLLx8>sD^_u>2l8yR#eW}ArKItb~8)t@lR zh1L~Ezi^jGl;C_Kyi*Y-WED*eEczpbeF_teiWduU-^57c3d)!iWkd$dbSY|_WbkfO zybBP<5555mCI-+kbAo<23+}?oNa)A$abdC0THqx*E?ot5CoP4`0fDWC#xAvR4IeCQ z#lqf%OH0^}Z9}(XU0_opLYY;~UtIln z@+MX#igmIvv$ZO1QC3k-;b`upsGz8*sHCW@sA5(PHxVUBy6%wdk( zn#^I2o0!aD4*Qqzy+3ovH@MAVGg7X{%}M=X4o~*U_3+gPbC|=A0OWeyPS+pi@KmQ< z4}1R1VNUEhJ$&iH9Om#OpS(PL<-{E3q%^08ug93f9Jco5<>8kl%wbN-b9(qy0CSiV zCr%IFX)=d7smSRoGFtrdpfabg%;~Fe`YN2>h10um`f8lM8mD*T^lqHK2B)vV>1%QN zTAaQ%r?1WF>u~xyoW3rn$DyM?%;BkHdHZ?jm2hTGyg0oVr}yUc-kjct)BA9GUrvvs zTz{C8#+<&fUI}OBq$#Iw%ITYP`sSS8kJI~c`c|C26{l~_>05L9ww%5#rw`!t0i3=A zr|-b&137&lr|-<^J9GLVP9MbSyK(w%oIaS-2Xp$KoW3Wg58?D7oW2jI@5AXsIejRn z@6YM`bNT_CegLNr=k(#6Ud8EEoIaA%M{@dTP9M$b2Xgv>oIaM*$8!33j!)$HB#wvg z`Iy6;Xc!L1TPnw=!3-`QNF7KYm{C|hm`FWZ)ORKWWcm&yL&oPEzLN1C@b*!&Pd=;j9pEpC43A;gUm!+=D&VL+nX zFd$Jb?WObh1_4nRaf_X|HV8S~=fZWEYE;dfC3yYKMBI4vyFq~M5gA+?3aAJO+P3(Zi9fxg5*=Cy9iiY9P9)dqJ zGGcESj%aTX4uzo|P3N~LHV8))^Wlh6J{$@m4~Opg8iXV51@qxhxj{Ho&W9txaN$TO z^jj_|N-E~Up;9g!34;52+QiJe1TxlM7&J=s**Jm^UT>n zpEmdw(8zDDFjNCO2*yBW(G zp!`9~AENwW${(TpQOX~q{Bg>kpuFVINyBEde$Jn;5YO~_}Mkk2w9pJGBj-GsczgnTkQUWDzHNcAbWKL$L|a+Fp;noNib z<*QR#pHg2++fv$*(%zKzr!zj#o zew22hv_GYBl;%*1Z-_%brckIB_wT1~>z@@YSrL8ILPH8x$Nt7<5bStHoDSbrgM@oyqUK!$-r?fhyN=oA? z&7&0e>d+n^*G9UW((RNUr}R3d&nf**sXcUfELVlnx|BAj6rZn0eSb>hDb1sF45dYs zuA+1|rE1ul!t%+K4yH7p(jrQ?QF??@+~dM>Pbe)97Zl`cQ0hZzTS|LU8cAsyrGHa8 zfztVuuBY?>r57oEMCoTr?O^W*>#aeD! zpmYSKV=0|T>2ylxQo4rHeUx6H6dzT@`YKWS2c=CY#aDEoKAO@DO8=#F5~YhM-ACy; zO7Btnj#4X_*b%Q9rCyY_qO=>O;glv*I)u{6l&+(6AEoCgy+`RgN-ax>_2JXuSZ^Il z11JrlG@8;(O7V$!wBJkV14?b}MY%hrT`5habTXyeD7{6g1w8$Vcr_{QKxrJMV<}xn z=_N|PQChW>SiUu-QIrm+bQz_mD1Aq11-Kw#z0D{MqcnliTuMh!I+@Z1l&+%`Utxzh zrzm|(sbgtT-k8#Ul>SNSJW3Byim!G>9DEBYQg2FoQL3i&UrLuydVy(;1()cLtL}@6cgDIU$=^;v=Q(DGJEMJXM4@#R;8c1m$N~0-F zqjVUh1(X(1x}4Ijlpdz^BBl2!eM_ksEPyb7r6{dJX&p)%QyM^NPfAskCQ~|?($SR8 zMY@=f)kqf+vJ>e-LXIO{K*&|3^9gy3bRN8mAL(3JuT=y(2iBiRXTv;%bQU2VNQ>ZQ zT1a928Hg0tm3@%Hx-c3ktXI>J!Xj%J(kX-#Ae~G|5zsRW;~kRPP^ux>;O`Eo@%2KqPUeUOeOqzUEQBOOIZXUc~n9SOg0 zqkIC=5rk+cKLqJ;c*im2$0Pj@)=QLMg!EtVpYq#~{zJ%a%AZ2|HzDUKe-G(jkYCDw zLOKjy=0^Dvm4P1$54j_Sc&Z{D0@q{8H$eI)A&n{D9_e6+hw}Z9!Xh`E@<~YZApeyA z3u!JP!zn)*X%4JwD8CG8HuMk5??ReI$bQP7Lz+p*Wy(K7ngK88qWm|c>F{xe5BTqZ zG>xwJ6JU{CHzhL;{zFZm@XJ?$MoVY#NQ{Qm6@EHiH#{YU)P;wV>cam)3%@0=%kDT! zJEOQ2`YRjQKKYdiJP`2niiGW!U)jLs%P&k|E9Ms#!p6)mY;c?A7bdW2W6Fa5QdZb4 z{*}#7QYXQfj+t8gGZov?+-eR*cI>lrmPl0;*6M)PFU&`7e3 z*%`^0F*BoSGiGQkcgE~YB~bs1anreDY)qw1Z(=%QjE$*e=}k=KNpE2~MS2^P+0mQ) zIx)hx<@`Vpa*QZq|NMFKsLjukCz|{`dDP}-$rDX}mORno=gAXoewsYdLEQmcN5WAD{=&8c@e?>g?sgUJVA&&l&wzGVUod=Fyw<=Q!wUjAi}#kngY6vw z6Y&tA#Y22!c$jP!&!U^&Kg5yzgXOmjPh|oRmfFI~xhC-NNf_3@ zUhf3C1fC<90uR3fV*Lwd@Vpqj3=VIt2|WC7(O5hcgXhiQ;hPu%LYKe2Ch#V4 zcp3)Jhr!#y;hi;shyTF|>)$X2&zHfw#o^rrJe(h;1N#9U*EqaFz(YG+4>X34)L(4j zgpK#B2|O#XWBpso;5B9Nyg0nF&~J_TSC_-v%iuL<@cMFibxh#(;_$9Aczz7tP!6xP z2|VG&$WRW;;_;TjYXv;O2;*%rhZkxBZ$9T=@nC&>v}W+maCjOMcqceKHwLdQgZG8Q z8)*XX1Bcg?!3$vUs=;@YY=4<+0kK@kLulVo9NtqCc>i(!O=Iwa7`&Ano&}6kW8-5fhqso&gG-&x zztbFEWfOS#T{GJrM;Sag)#1J8@bJ5NWB%cDBP`xs2CpZBR{?HD*!~h|0TPzG-RgLjz2!~amq7~XykPs8AaGkDK9ysIYg9&vah89Wt(SF)JAzq~bp zX9sp{f0@hRMKXBxIlSU9u#LrAkHg!_;6*cdJvlu5Pd|;}b>r~PGI#?SybKPnsR=v{ zhxe4hi)HYpQ9KX{M=;=(hwoFQ1IHpBlQ=vJ7_=|pcLTUSh=&gp6XrjB-bpG0A~LWl z@Gu8Thosxg*$r})=S8x^|ILwYx3^(pJy>rNe5860ad<-kuaA*>&rv&EW8!hGIw7HD z#B= zd@xqP(;c&|DoQnzPE?BH3P1-lzB^@IOkP)d_H&F!{NEs4;tm>-Mf?X?#_QXakqcZ zd2n-IcG!)6+1IYU$m(-7H|yeM%dC(~!!s{mu*vLqeptq>v!BzW&%~y`ICUv4^JL33 z%MK!q+RY>3*=U$Cwzw7b) zti!?1MN_+%of*@un%% zbUCu#l{_P=~Iy6H*lc)f+=U^jEy!37HQ z!Px#kv=4s#&>n}+I`~Y3&rtXbgilxaG=xtT_*nkuxHp6Gu_ix&N;S&#^ z9^b!eo5IHxKDOV#XkUH%qP_U-vvxat=6(C59SNV5Zy&XN;M4Nk2W>6*l>GKy`|d0D zyLZ|>U*BpM!)NT*H`_e^Rmj_y>FZZ=SKHt;c|9n?_?DHM%+RwMOQ$OF*{`vW)Hv01oZI{p2 zwLYJ(X`Me`)mnVMtbOw7lJ@i`?C%$}MW4=V|NeAV8~5pqHu%$NZIe$YwbeeI(As=D zu6_COsP@9gBiijB4{7IpJg6PJA+HXR%4sUvBKfdm+z41CoyZ?13 z?XuS$wS}((wAruQXv1IoYumr}(|WvargePXMEm^}&J7K;M_+kq*SxByo$|_E`{%3L z+UQp`wOwAhX?a@tKVOKXc>mel_9vbZ+>CC)2W+NLkf zwXQFT*6!uEyw@*2+pP6p6Byzc}~wa=lyuLKJUS^HF?LM zt;k#VY)RgoIyxvdK^ZcHs<~4kb z^Js-UtH)*Yo;@m+clJ^7ye*H4<;{6yo;Uo_kKCk3pL0VVz0dV~^eVUJqi4DHj~?c} ze|R_d+QS>UdmmoTUGfm;;8VF-50B-BJv^A({^6cnkB2*Q9UpGa{r+HG?)?WVbB{e( zn!EPFg4}5jX6FulFg_tU-3xi{~%&pmk0KX=8w=D8E@;oR??tG-t+ zx6{4fbG`4ms>? zPK~>da_sNob>n)@)jJn+_TD*@v*gaPoN;#!=49R3ofCd%Yfk$+8*)7Ftjck^vm}Sy znV<9Uc2UlW+f#Bj+%C+SaeGY8-?#CaGc>2i?cAKEx6^anZYSl~-Hy$9b1O3E%B=x8 zyKnW$S$r!vXY8%cIhnTtat7RLl@oBQX^zJ&pB%?q9yvd5;`Pck=lD(Mob@*ybEe;P z$ocE0T~6Fh%behw-?N+E{Fv=_^L4h}%_rG!Zrsbha^pt!?i-h~7vDIYU2x-QcIFMd z*6qk{e`8a&$Bot5PB)fjlNueoQ}zg8o=(zV~R z&97C+esZ;R_L-}8*;}q!WY50(Eo=DI_gTqT@f!OutJT$8S+%cT&MJNNOxC9>N3(8S z*_UUw2LR--EgSyiu$$g;UIEbG-}ygsL9?YtbH zweWIOR{mvWR>tL!tO1vUvH~u*&+@q3D$D6|<1BKye%8ZFe`KA!*B@CLl;kGuDW}7?_!LAv`nULZ8fz7rJHE zztADG(uG!;<`)`gJ~{7|dG>tm%&q6EWzIccA#>z;hs@OTxTa8KwmJVP!~OiLjB@86 zW_&+)Gvofbiy6nyoygd5?m))Ob2~ErIk!F|;oS0!kaP1h{LW3!sC909hQqm$8K2JL zdL$>~@Y$4%)n^A~OgS5#G4yQjj6r9+W^_LrkkRz4UxwS+h8ZQ!*3Ec#rbfoKGtL?N z&y>wrex`WF#53j@+B3M8d6gb?=25!unVacV&s<2iIdeSy_33@-mrrj^-*b9x`jXR2 z(hE<|PR}_#IbD4^KfTlGf6{$U=cQLUotj?kG_Hdp(l4IslfLUz*YriF+NBqqYM!2T zszG|hsXFN$Pr0UhpQ@Pde5zEs<*8!n&rg0&yKwSd+K!V?(iWb)oi_F)uAxq(g`eD? z*74-FwE8F4q*Xq-IL-28QQET;6VuM07@fA`#IUplC$iJ>Pb8&fo`_BhKhZy}!-?Ru z`X@T3RX&01FWV)}A5*5j zI@%-k^3jf|dyckDU3#=(>iDDXsd-0TQ=^VnNDVq#GPTiBT=#v}*d2YTd3)r(=Gu`f zn*B#kX;vILpqX@Jo953Wt2G0UEYx&AGDFk!$T&^)BmZgakK}1S9@c1X9UiDTd>Ge^ zJv7q}chLNG*iRFGxPd0*@E@9%hg~$a50}%FIc%r-dWdN5A9|m1;?R?njfZZg%sO;F zWyGN)DVjq&Q~Djk_2!Zkk3&T%6%LJ0F*`Io<>^6f%DIE7DccVYOj&qPnKJfZa7xy} z_9?1^%~LuZte@g@uvUu8LFW{kgQZj69Kf~e*W`T%UL~(Ma6fs{fh);F4xCILbYNd{ zj{}>Nn;%$_TvrACx?6|A6G-`*EGyKDpoi=E?2$ z*H8A?Uo*Ml{>sVb`yG;>?Xyh2u0RJiX#QtrN^Nm2WDCUxDnE~)Xp zMM-Y^aE)A$^kMJcNw@Z9Cmq?FkhFHMDrv^vkfeY21|}u%ZJE?}Z-b;Zdw)-=x7RtT z!rszJ=6kJ@p6>aacz)0G#GQL^eSJQ$aL(-ZIP9+Y@&w=!|V?(T_2yW1rW-`ylpv%6km|J}GYFQ4eO+cvTC?(Yd!yI&`~ z+;utIo;{vwh{lvC7=j|)wifx}0_j=oexU1X#i#xC_ zCvMfYgt%$j!sGtl)*~)yTR>djZH?pFZgY?G*ya*fXejune{J0mo49pRY~QWZV%uyT6YH_{&)7;^HL;dkqheof=^cAzOJMB2EiGbK zZt;wrx&`lJ%Eu;dv5D=w<;$S9Tb>W{+;VeJG;63O}hq$ZCW!haMQej4L403SZ&jP150em9{6!1-ajb^p4ixR;O33~ z1LtjQFfe~(&4Jk)D-4X>Xg9Fi#&0prHol0dweeO=nT=;+zHitY^LWGhm~$Hz#_ZfM zC1%M6y!XnD8L}ZECT>GmOvr}rF|9YWj;Xi7C#K?tS}|4|D#W~6Zx?fI{kQ0Y>z_xj zS${Kn=K537!`JVLPFue&I&3}Ow@r%nUH@OS>-y~IlIvrmKdy30{@*ByzfunzC}mPfr>J2UF)+We@4YllRw zU7Hd$bFC_B#M&NF>1*3Yg|BTG)p_mjQH|GDjHco<%-db3O9h8oXcJ z8M$=Ls>n%eW=9TNGcGc5&9KPOHK~ySYa%1P*Yt|~ZB0O=-I_*`A6EY!d1rOS$P=sW zBDbvms$Q`AnR?u6yw^Og9<+Lgy4UKJYX8+m>Uyiksw=G?qAs>NMg3+~g!;y+VD-^e zZPXiAHBir8RYRS>s=PX9RWWt+st>B*Rd}CzN#(xkkgCF}%__@Pi&d{yPE}oBIYM=K zWwvVl%2?Ixm7%IJD?6#OS2j~ct#nrfudJf-TWPPVv+{dHg_U@Zdn4l2iW3pnSL}>9 zykcd83=Zh6b_kIOv6 z?=GtverlOR`1WOr@FmOe-uh%VMeSjS~E!x}Cd6Xv!|8|JVqA?*9o z{$Wp+b`HC^w0YRRrS4&?mpX^dSXv@%#L}+=GM3_f`IQ0PmL3_|ZKKHA*=uy97i!Sziw-EOd*7rNPa9+Rd3k&-#Sva)ca7CsDpyWo82?FIWnPcFcHh}oe_7K{y@ zykKzXKMUeRQy26LjabkzwCjS#p)D5t9$IICV`#+%R-x7l-u8Vz|4!e#^H23XJ%4B4 zo%5IXT|OW8Fh=wpK0mW>#{B5Mk@I`@4W8eoZ>#zB`+Cf;+V{8lrTUhb|Gm$bc~AR1 zns=qog?Wei?3=ft&zgDj`plkJ*e8D;?tdiqiJjNKPv3c+`m~?dq))?nzxSy=&#_P0 zd6s?5=Dq3ta_+6(H|Cz~eQfUb-dpA_?Y(&Jl-`r({@eSXxoN#q=i=T;x8B|6`t|mk zTeo+;xs`i6&$aDceD24P&vWjFJeqShYig}b?cco%dcnLEcc$FvnuxNILo?c<5{@hbEk*Xtdl*8&Dz%E zebJI0_lqX=I9K#nkG)07J=PQr=rOyfQ;&k8#y$Qls?{U0s9cW$MP@y^6uk&;UUW6s zy$JV;HUt+hnj8Fe=GfpTGxLHk&m0tdcxFiOrkQPm7tO36JZYv&@V_%l1gFpZ+&yaM zgYG?Np6%Xt=C1AyW-jkueJ1WR{oCDQW@`60Gs3&ynbEoXnHf#G@19Ys`|26xy3d|r z)_v@Z7v27xakX30j6>bRW~}QLG-Gx*zZqk?dCbV^<}w5KsCsn!F}+o{7t`x?yD`0T zw-eK?yX~0%uIq~Fx4X`qe!T0L>07$yO<&kGetKco{?q^L+If0>*XGmvbgetRUDqnp zaevFD>yK&0yS|wADd@(udqF3roetVDZAZ|GX-k4;PMa7sX4B-yWF0-w9A>Ple_Gh`d61VQ~uTdZu&DskpDUw6o3BNu57U8P@snl*G=L zr-XJsG9{q%mMPwymrkkLdHR$Rokvai)G2Suy-o>JPIVeEWm~79DT_L_oHD+X*A(27 zi|bToO7BhSk{1umL=G;qq~je#R3&kf9(oF5oB zIVZ6HKWTr*3zJrNJTz%W$IX-e z>$qf6YR74l!a9zc6xcCul5fYvNp2m(CY9{iZ4&MUKIqV3(&-L0CT;KFIB8J_n@Qt4 ze4hAchbI$bJ6xL>(&6|-{|-AR*6XlpV#N-#Ct7tVocOB!UlXsjPoH?Oee^`!N1WNd zUvFYqdzXow+LxZ_+unSlYx{Q-O16J6;d8*n3HJjIPdF8@b;8zwWfK+# z%$zVTVC;mvfT0s`53)x<+py>p&0QU*c+Wj`+VmpTkd)k>#Sl;g4 z_$lokjQ^|MrSXaFj*RcyZrk{_?N*HUY&UB>?q6EB`)mB0w&~-qw~ZNpsBPczYuk1j zKeKI%@x$ACjZbasHhw_c^5Z+UwI1)&_H$v?w$BQSx4lvLq0Onn+ims~;@;=RHVX^q zw3$*ks?Dgvj5gZBh&D-uo!h7i8@1_K=+-8nuwB7yeEeq$h z{xB}T_2Y54Z>ny6Vq8$`UE`XxUOTRO>jmRVwVpigi~q=R_x!cvPWmT}+v2YpH_yM< zxP1TiQno*!?HMXEjt6>F=TBR4bwHjDp->P51r&M>oTQv5t-}JHT{PM@n^cy<%Kfm;` zxYyg?uiw}Jzpi7w{92E7_G>t{nBN~`U$v+*_DYM=WB0YN9J{i`r~D}`p5_m0aWg-@ z#hLt&76XY_KitvwrR|OX3NI3 zZ#HX8{bu9GI5+!mOtEIUV_r2)8gr$odd$A2y~nI*+G)(>rY*+|ZQ5W=Y}4Ap{F3eknmixYGHrBVld+>4 zH2G`vZ%wjB+cb$EjeFZy8}}N$zj4RWD;oQap4`}b^w7q?kB)8ZJi2G&(xd$vTaEs` z@t09$8owCzt~1ko6b$UHZPVR3zyQ;|)*2cF)V*z`ySux)OS+L%5V5!0ciq?fd^msWPni2U;~39d zryqJAJ&k*AInDH3aGK&dc}mx_^^~G#!KoXbk*CgjK0hVviJy}4q@3F1sd#FI=h;*9 zz*Ap#>Z8ZElLH>TCtE!#PF8y)o-FY2I+^O>d@{p2RS5CTn96V{~vF0Sl z<3D*Tk70QOk2-l(@Z$sJFL`*#pYUMIOMB?c@9_9beyxX`{1T5%^0PeV$$xSGaAMrO z2`_sQq5NS`HrcIOHp(qUHo(nC_LZB9>|-~YtdpCjtjO)MEW=G&*1~PI ztbyCFBWiAgNA9^*AGzw5eB_Lq&k;GuE^Lo%bJIAo*6s2U3AY1B=D4jo^27Dl;VIXF z!|z?I4tKdGA8vB>K3wVQe7L~X=5V^J`r%mDi-$v8_aF9lMY+ch8F$xy8GF|X8NO?x z49)eejJd0$jGil1M%7hS=C12`nQN|lWzM=TmpSVC?a%?&o`LELk%vU50<-h9?WwoI+*4XeK6ML`N2>Z?4XZ}*}>;7 z_YZoy$RBicL3zuX)Tv9X(gAxrEk0Nr7yb}N}qPQB`xQ2RC>S5 zCg~k6bEG%8j2~Fx(s*E@OXh(;&M2#KKQQUcIxy_4bD-P#+JP45LkDV{*B&Tw{=GlP zd1!x%bM^ih=j8n%&ffcdoSpZ-aJJe1$XRW_v-5@hIOIIb_uDvs-DmFHvrpf-bf3C& z?7j!iFZbPaCiY!&Hs5#3`N2L}=ac*PJ8$2&(|O^(jn0#MS30-uUE-X#cMfDkPxgLx z;_V%GGT1xl^w-`_C)vHtP8;@CJI&f#;xrXarG=j109=Hx2n??jV&?W7^~ zkJBY7cgUAkNQs=j?O{9h?6Gkw-DBnyyGP&YuT#tJ?M^wnH$XP^X!jB)&hEKRdb|I1yuSO3qs;D)j%#-hJO19)=Qy;h z-LZOCqhr#pDo3wf#g2}RYP8G+I9rqpUcHDGK-EkQ*F_#_39c^|T zc2wK3&+)>JosLpFHajlcvDWd+_T`S9+ZQ<&ZJ*;9wf&dF)9qgzgxe<_jJJ~C)VWPf<`g#EhB!}h;7_1O<@>a?%g^v*tUQ@#D$O;z?N1GL;!V6V6- z+y2z1RQny966_alingEJ7-rwHG0;AHqmO;?#@F^98=u)TH$Jx4-uTe|%0?%9>5XFh zl^cbSANFpb+m~*j+Q)35*uU6dY>#cwvp3nGX@7Tviv6(-3ig{e+_9gt;fDR_`pfop z>(AS#u0Lh(yZ)HH^ZFx@J*uwXYkzM2PW#>Kx7aUPzrlWb-D>-`bt~-i)-ACQTerae z@w(aeoOQqLbl3f`yS{G5?$Ej^yVdI^?0&8twnMpP`Pv@4xV7zeFW0u%5o;Ul%+}V} z-CJ93cYJNJ-R8CVc5~Ne+l{SBx2s>1Y?rns-p+STw4KYEa66kd!H{{LTjOoFd(CS* zi8asdrdR)M*S6ZzE^oD)UFd2jyGN_->^Q42JKfa+yKAdCb_Z88>{hL|vHP*g%C2{n zIpn3WtMu(&tkSW=R%zIotWveRvr5tK=&E~m8&}=7o4x9W-N?$TcC{-n+NG>KXXm~0 zl%3CXt!K)uHBavv+TN7{1z9j_$fv??LRAK#QYVX#0D!qif^tM7av|RB3`>< zNc`{ee(}Ka9&yF;PI3J5Hu0x;b>>xvx~YeO!rxL93$YO$Jl`(hRGg2hVW4~rDUO^Y6gGZ)_YI)9t^?)gOm)ZHKcycnl0`pRZc3F)C*D=DHBq6NF61$k<|a^|0wf6N#^^FkmsWe zALaHat4H}f%H&ZFkFs}^x1)?5A$qYND7-YDxv`8LY5QI3tW zYm`@`j2h+AD2qnJ%&Wy5UlqaJM8Rf<(D@OS+%7jr4jIv*p_o9p!<+>=#Mfokt zY*9{&vRRbJq6`-0t|)6o`6|j(QI3kTQ%E$|O+^iLytOH=>LY<%%dvMEN1g3{g&qvO$ywq6`q_ekkih`5wyjP>zSPJCxU< zj1J{;D2qe+8_L{J&W5rzl&7H#4drGiD?|Ah%EV9(hO#e|ccF|6zJMBa|1Rj0ojIC<{XQ56XN{&V#ZYl;@xf2jw;>t3mk; z%4ARugR&Qtx1fv#zAJ3zS!&i~{8n zD2qV(1Iipw&VaH7lqaAJ0p$iLD?s@G$^=jjfV_X?_al!V`TEGqNB%wX?2%88ym{ou zBM%<=?#OFL{yOs1k&lkNbL5vJj~w~p$O}jQH}brZ&yBoov07{vz@ek&lSHL*y4Cj}ZBS$O}aNAM*T=&xgD{YhrBoB zw;_)W`D(~ZL;e}^%#crpyfNg5ArB1sUdZc0{uc7IkdKADE96%pj|%xx$csY$6Y`vp z&xE`s8y3He6ID?-cbycy)jAP)xlF34*^ z{tEI`kdK1A6Xcg5j|BN5$O}RK2l70S&w;!R~WGeAB8@&=F}fII+n_oG`M-S_CGM|V8B-O;^{Zgg~)qgx#H!_du*?rd~h zqk9_N(CBVPw=%kq(M^o*V08PU4jH;}(OrvfS=1*(H!HeR(QS(EQFMc%yA$1-sAq<5 zN_0n}+Yxon(2a=hLUaqF`w!iG=*~m89qOW?8xGxV=vG7b8M?{P9foc%)KNn>7P_m@ zErsqUbTgql3Ef8M9zr(|x_i*AgL-V}ra^ZMx?NDG4c#c{EbIer1Kkrpq7Io>+8y3A=(OVV0Ptltcy+hI46Lsv+8xy@N z(OVMr?a-SMy%W*f5Owd+8xXzw&|43^@6ekLz2nf^4R!L+8x6h7&|3`k^U#|My|d8U z3U&3+8w$Of&|3-h_RyOMy@Sx(2X*++8wb5>&|3!e`OupMy;IQJ1agUSJui0#cczP)9J9 zR5+;sQt0jQg4APDZlq9m5F^DQMI(iJgvO+FNvV@Uox zvh(^y!Wg}RSpqy|ZKlWHYZPpXns@&7uJY2-J7R21|he-ggr_cf`f|LaORlV33@ zKJ+Gk5Z2_^oRq=;I+QBp_a3R6@J9PioF%`-ArmN^en#-i^%UB@-6o- z*|$WU%SlqBqy|W#{$&fPI#T7N3Q1*?N+lKdzg}h#`Sl_75;~eQggf~rbR>nt+we2N zAiq{*XVdh5-AxVht3>K9Db(YKslRHRlf_LQ0@pK9U;#U+=Sn{5F%SA%!}i1*9@bB|{(d0})PkLIX&7K{s@QcuaoX$d0H3^hC!A z4*8{#eNjv3jE)hyF43X+4)e4>0HlmXJ7L(oAT3by4e0C^5@*Qo zaq?D?fqNyN*!ex5*i32-bb0fLMdWu5+3EfD4fT3+h)Gf-r24<1j&C;6LiT)XNtHw2 zH;gcW%snZlivL}+|V zB9utog|2WSaq(LMahlXI=ncmcd&%z(vOl~DI>fQWvTw1(Lh`;k%I{C z*C2vMc9JcjmmEmweGMSUP?k`Hj

    -?W-Sgfz&Cu?R<%YUwsHEQro|x?y@(r>Z=#A zl+*&~F~22#e0f8BCiUS9>NLM5dcV9P+DSD*zxgFm`sD?YPbw3-&d-UMFVBcDQUTC= zeo8$5@(=NtlpA!Q|0YCVo)8>TG`J}r6UJX25xS(*pd0N;-2UQ0Tq8Tu=btIYGaTX;c>`aCJD5eBoM92NGfYAny4nn4+YFspPiiIfwrRxt8C&AN&o;z&Qq!NU zi3w6epQ%I-^tr8whR>En6{!;Fc2kJ-&lDn&?082*&)baf`)o?QA@vM8-zJ31XJf*S zyuF2Re;X1upA85KDI@5D>l3P<^@s;#C;S%l!gYvqpS1~jQnJty*CKX*)+Dx)cl&y{ z-PMUDpVf$Yr2d;m-Emdo)3gdPPIkzLphvDmv`#A$4Wz1|Q~rR+oqj;1Pv0jJr_tSi zj|iE*OZbsJ^Ec2nzfE{f-y&Q{*+K98Cc&D%N!U!^ASlzQgMOXRp1ww?PG2P+kh(Q} zg}5?(nK(yEej0VtFA@hx?Vi3sY=xfsc|vmf9I=G#tIvbZ`WfQer_;nIQsdBHKS^|d zk|$b8HGD!{_TxkesoYP;h;-<+A0?tc$q^x+WC=g$xE~>&eL75dev%3E5A(i36W@5xYMjpJNBHo|NRL z?Zgu3%5Nq9o7zfzpV~rvnnJz#O~eqXo~eyQD|G1B6ID~|iIS;xMD7&wNY)UEq@t%* z6Cu#8UrD@~T1h;ck|aE#XTO}Vn_5l?rlHJeyZYULE_=>NgzP5p=eH~Aa?PHKAcUwnM>7d|xk z6YqiU{tvui@;hEN`3*0D9{(3Seew&QI5~qyL#KZl_n-WPzajMue4R<$b@C%_NA~=M z(Dk3dZ70WZ%H$Ys1ik-JTy1g$SC|~eZ@~s&2tPkLh@T`S3!YFvzGt!z-!|EcZ-8w; z4=yp;jnAL#!vB0kJAn>-`eQpjLFzqh23qm9kMHotk1cpL><60hypK(I#>YlH3AP0F zc<9GE+@IVOyoFss4gUCJHSYSc3b+4=HUCsvhYQ;fTK^_4fqYRM_K=6LvU0A;x*&+u^v?1csYVh;V(_S_p9E2|j*z zf`{LL-313fGr`7>Pq1(q*kCa5ofC9?^8^iF3!a}1zG%W4pEE(l{~br$3`=}++yWmR zr{Dvy(=fwZ#!d0MaTB~^9Bnp?@SJf&JayavkB9w+9v(cdi~El2;IClIp@n;lYvRu1 z8n_sC9cnmpTotz-SHaC;;v0eCi*qrRZ<;J$-2gkPIQs9qn!8eR;##fDP!k5ApWdr_abUprK zbRGVA6zx)0nau`44b*twBnOdh=C0!(@&AKN{Whi!%JO*Xc2Bny)m z$;9Tv4ksP^KAeV452s)gu*pfndWRFSw&4V<5%xK;Sm|&KmOmVgWx`e`5{nrQ$HIog zumITYgkUd*gR#fMftVX?c>FPJ*bn0l`(kwPu)Q#o;kTIH@Ec46wmmPgyTdQA>%-5n zi?H+g2Rk%BAfOP~V){dJnC6fy zrVP6#8SLiJA?(u7LF^1{oc3dfhxTFnhorDwkQMC4)(-8&Rt)XH7Q^;wEB1SE3-)br zGxli^?VvVbgM;g_?!mQKD{P`xV^xDIv64YaEEo1s%do`3rC9W!1QrTgsYTe^!G+kf z!TH!D*iFsF><4FKqQO}h2R2l{MV5pAii`(;iF6^O_%2c${3^OL_(gObwpG)jQ-hyG zM+c`whhS&*L9}CVLbPdcOtc0zSHq%(gYQMN2Zuzz22j4yFPa?a6O9h^hz4Mb)hTKj z=n&Nnw2LZWm-SARGtewb8)ya zC>Gfa6pARY?|&#_LZ0IyGVga58TLDhv|&qT zFM7}~7TxM6L|0%}CKAc_3q-R0e33M4%s8TL{VdUjex_&@WI;61{C*qJpFV5Rk3O_L zvlM;kvk(pUnTz^hhh`#b>N6JA^cjlEV3VdN%Ieb%l zZQB`T(U4pBkxc2O4W;ZuV8Ut@n#? zeeY-CO4!;>3Fr4t3jg$c5dP>vySp*rhn^APaL=%?4>ov%!secSVNFl3unhKiUBaxM zPGL$0w8*Tprh5g+D!j5h~VKeLiy@lo7Z-s^3Z-m*f349@p?|v?f?0zZ?hJD}@ z;p^^4!l&JyLQmKVx(UVIu0lb#vycV5K?fnF+fHcIO$c>hLnsm|bPI&HyZORvkTG(E zr@C3fqumVQA=nn$3b%J#3paLCg{xs_ND(gVHW$wBHWmKrLYqS);bfPAaI{NLH~{-Y zZQ;8vO<{ePy08+qh$_O|E+t`lm!dEMc8T|dAzgQceqFbPZ(yT%Q~0Rsy3n=js?Z*? z%}YW~*99T1>zvRMwu`5QdR-@l8eQ^2CD<_@72fEQ6JF{%B0LS7#)CqcE@|PuuKmKD zkc&zQ*LLj|uISn+Tnt;sZNlH3TZG>_Hwiy=qTSX7?p!F0>0BTTgKgv-p;zZD;fu~cf+w(({3USg{2{##d%?NRL4kbdfIt>@l|6zzon3-$ot=UWu(50vEbVL& zEa+?&{OLehZoS}hN3GyPN3~!WwwD!xj*c=xb4Q7w7Iv70g2Ik`L3T&3AQd*5S%S!p z3_);5n!p!w;AFwmjzocHN4&rVwwlobVMmmJ-4P+Mh23U|z_=qwpxY5BP=^htui#FH zx8QomTfs%hkY5Rob-WPBbUYL6gKg*Eg3TR|1#3Gz1uJ0Z=_Z)l;Uf6m?kxD$jy9k6 zg0Xh7V6Yt*bi@8rC}?Qs3#!_=f)dz*G6fm!3_(&mO%MaSP^uuH-BRGyP7%C-ji{;M zVY{)wvE5LBLw2nzV6^K9sO?$;GuV!*3AEZ(1S;)Hg8Q%|eIU5feot_&{fbdut(h`NNC$3h-%v=2!UjaNrr@C5T-?ma9YFi=T zz-CoKVA-}cJVt}JNV75ZTwo;!M5-VTbuaV ztquHC*u>WGBU`KZ!L1d1UO_)lAl_@1o=d>7ct=J18BS$uYDCf^ozv#EUJ)?~hJ zYa(AAHng$)JFU_D>#dRei_j4W}+51=e0iP z|M%`G|NA?%xqZT)c=w3^{+$QE7xuTV{HAx#{F--;{4&_$iuqaZaDK`=5kC%gxjcT* zI}YFH9gF`8Ho7#v$2%Lo^E)bE4BZ3@pY_g+Z}ZNCPl4^O0blo>9$)>P4qp*=yc+!L z@6`Ag->L9V!=_h(FZ1p`f8V>i{GHHi_=~^x-3|VVch~rfVe5N||GVV^|69vB{-+kS z`#r@UYLVynwjAfT!v2YAr&!2WZ<)_mY?;fy16$%hyo)Wrd8b=` z@s7c+_#1Cu%NO3xme0J+urdC~lWdvbEom9!&4Vt+d*1ivLEdz8KW_rI$KAZ%=1yLF zb33mIcE~NfvgRgUL30By3pUBsy!hryUSxAQFBp0p#k|+eg}kTD`8-e9DrfWTnlpLA z=5!t#cFRdTi{=ELNpl=e4>rtEJf-Fc-reRf-VNx01o6%^2k?$J`|=LMw)rh@SMzJ$ zmgbkd^{{h(%9CjRn>WAtG4D?k+B`qxeQt8)eQ0v#4a5G~p4ZVN<~29rygJxI^La&0 zTwYESo0kT=XgV*d$(9$=WXS>A@G)4Wx%wLZaH z*mR6HyGf4ss}b$45Ah}&rFo-``*{Pf!QR7r*SM3{(72sf1$*qxyu8MZyo|>6yd>CW zui}L@O7a34m-D<~r@e&tcjH2yd*ghb6Ku9;^Z1Q_xXi|Xxz^B^`OYIcw#=|~5o*Uc{%k^uB z=DvZgco_FlLkQQkA&6@ayKz4*r@@;`Z+OeKf(`jgu71Nau4cnOTxIC^JmTJLaOYlW zaO0kXZMhRyw!xk&-5}=fft|UCyRm`KUERRtE`!ZElRLYC#{E@q!~If^`azc5v3hgv zV7)1~8@A{M+=hBRZdJVww*+?S>fFqFRc>;i4;U^>?}6^|!gNpj&jE>rsD| z>s)`CD~9d*IWDXI4A-{)6xRZF?8mse^>SSG`ommB*tAP?Z`AMOUaFVko`GJ{PVV9Q zZQT9!Te!Pn>%N}5zJ4utW&LWd1nl0IbN|#W<^HT&!kwu@8~FL$k-E9u{<>M*PT0f$ z%c-yX!KtkK#wmtv{4^)MZizebkR30#1KocfvroXVPgoMK=E?Bb-?Z097^ zY~{oNFJJ>Fpk^J%t7bLlC9ngQbKGl|a-3?Ga0uWC%;&Ib=5TCkW^pLM6!^u~t@*)L zuldSWgx=XF_Vt=c_NAH$_8DLe46_f{46*mu46t_tcc7cSzNUk{vZjr_6c_|e>{&JS z?4Q-O?3rrRS*u`=R+q5{s*BlOz$VCJH&o}atEw~ECBP|2VP{q+v6HLg*|ESZh++p; zN3eaWL)ovO?-t1RsP<#KRQs^)fMxKS&8~jIrd2;*=inJx|+k50`>u&y|LPcy}FvpUIrWlbM~BS6ZXGVM(nRuh>4)f z9IOTt>KZ#9xCs~8AywztepP4KZ-Ak2 zg8jJaDBG>-2-^WVdeUrO)qXakN{USdw!#j!VbwOacGYIKDsUFov2RzcVPC6S$-V&0 zg{ACcRg2j&RSVhspx-x#y`}08YhBfEmL#wkzO&|6ePR8noM!!~L|ldstdEuBtdYtQ zRzENr23YSZ`&jjr-KlQRO!xI1D!-?*5XP>*4#=v*6#|$h7hr)EBLI53NGtCa3biejtW~= za|M-E2h0d_R#AlsE2qMUl@9y}9aeOO7AvemofQBq2_@ExiU+K}EAFw}fh+MBOI&fC zC8)Tgjz^(Yq zEH9s87M6cx<^aQDgqcwOo*7*}zzl^BW;fHTyo33oyp{O`*cOdUr}8=`QC`Co0Oz8N zX;WUpq?8vjje&WQ%~UVXWGa=XG4DcuGm&|@JdSy`Jeqj|SQueU>GELap7KEEcHm-o zGgp_tWiBs&#asl8jDMKF%bqa5m3cBhm7(sZEAxGs6SKF>p4kEH42)S@CSX>SahXNH z(O@vs%WRp6WmIM~Fg47X0c9pkuQDU%OX!X2Fx|^Ena*YEOfj%F6q)R@2Ta?tyG#q< zZrot%m0e?MlwD>j1B2r%^Jdv;=9Mye<~it`$};834l@sy9b`%Yn`19?Q`v6jnz9|t z6~O7(%$!@cf%#wQTITms#O#n{ekfhW94=kL><50wd}d4O9A(h$aaV1@WIBuaf4 z3rgQIW&t@A_OI#RjB~FY+;E527vJw%apoGuJ2DS)`5nn=Q zM3vYuLVz~Z0W;_Arh%UpiM2kU`s5AJ`&sAdBlssTiO71d@fkkqYp;2;; zp;U62aTmBGXBn4EPBG4v$TQ@DQ6kGYSR%uaDv@UFfNt*|#+s5{j1?u@8H<5kvXSv$ z@j4Qbwwm#|7;#LNGlq*L82!bI7@fd0nZu|r{zI=S{!K3dzR5RwX7LO?x%d-34p=AS z^q}HVx^MA&`fK2x^wJ*{chOyo+vyI#Kxv}$iW}&R;#xWtI>qI5!{QRUPH`b!4cI8z z^gG3w^y|fG^h>}=NuZx7j-?+dj-np`W=aTsTX7(LW3fMdHT03+(iauKqR%OQPXAqm zSSpX{(?uTii6S@pFmP2I=^aIO^p+x=UI&a79=*7TP0uT0&@+IyLZ!zRSV)7 zF@3rav0diUhYM%X`wD;4I)U@@jaFYcL#r(OL@Ng7%Q!8gaD4J?>O+M~jHnplSDWi(!4F^y4JK(hu$Ocu?kFrB7Tm_k#B?sgpQZecX- zMqvc)GO%NUX!3>rG}%HQnlx}^UeUG}KBsLe{D-y%m@*!;#f5IPd4kK&7$Ba%>aX#Q2wZGFR*V0Y@73YZEN$pY%73+(_)*O-)NhjUuT;HOq>ea@cdHS!2BXx zALzN~*gnnAwDrtSvvmblPJ%6#A8X6YkFsR|Hz(NEJU_tJDBsss2N*i9Z58uh*xt>5 zYI_4Z@}9P5^B>yE=eyX-0$azjUZFiokZ5yz79@y68-L);tyJcGlT%N18X?YiI6Z6j5MgyZq-Zmib zn5}o7tnEwa=1bdpYSU=-7+w(?jHsuZ3tO4#%kIj<2PMdjotu}vh z5d)~fW+u1R=3{P^%_#7IN^H7w3vAkQb8Q-d4U}$EmYZTzn44&m4V<7To5b93o9NsS zn=oJo`Pq2qdfB|peQom(>={v#>=lu#wHxwKm`ttk36ETc3jcM2WRbPNDVwoILAYz(Pv5UZ0a^AhQ?XtD4McEqG9AGUeT3cn` zw>HbZV{HiBrEAt|*_W*qvoBcR0S41a>r2_ktd#UxWti{$}vJkUruJw4xnztmpfH+`WtXH8SmO zz;YU)=4B00Gqd`s$-s5$phjl3QiHRasD8kBs-Zs5s-Ql}Dy6!^)+C=Q&dR0=vofe` zU_T{Nt+L{%rdiQc1K>b~P*t-6sR~)X)H}e0dQH8Q^_+S(>mTX~*r~Wv4`#VirLvr; zJAf61Q`cq*sghY-sswPO=+s$R*3@5_meenqh#_T69nUnN4rS_6dx0mVMs3birq*RX zpjHA~>J~LG^Ex#%^9nT?I8$e-k(sBcA(_Xie!!eMOns3lO?{HNkLnKlm>pDc=2ogO za}$*VEUML1tIQQtv&^MbL*P=)r>bSnp(^C!W}DT@%oeMqz_F^enw?o?^>0SG)wc}9v?{Qg$jGr8&d9Xt1HM&~ z)w_&%tA>ndt14h!g<2J41X^Wf_*ta__v*D(bjAy-(2Req0)T<#ZuK(5)#{%NCo50b z^x#(Z83HRTgKNbDHWtmwI>XwEl3`(G44f<@D~$|&E9DFwtNXyrQnk98p=fm>OjUNtKGoTI&HNvL*8ml#!;)~z|}frH7{eo)t_`Js~_ozv9--=GJTWP zSo(UaLEvpkTD7MyvuaLXY*h>FtvOc3>3=Nq(tlZI0EcVFGA{j-Wn}tC%V1z~4O_lV zAFzCp-fQ_J9qo|XES=MvE$z}9EQP@8ssDmLJpTmZQM`vb5|@GqY?++ugyh{d+FL5mH*9qY1K zp4M)$IIYEE9x%viEq@pr0|g-5ELg$uCE1Qu8-$AXv2v|s?& zjA}tirC1oJnpo%o<4o5=IaSNzeyW%b-l+xsDlmcM7ou{NFpQa=xpP3KaxzZ`-W+Zon6+UmX_||GNvCMeNV;!sopjrr0z1O1=DJB2 z%{7wFnkxgV?zs7_Bw6!oNr%iY0=G`e{6x}DbJ?V=<_Cdcx6XWL(kk;UNz2XG!v=Ao z`O>7h<_nW%na=^X-FLI^i8E%O6F-@K1kT;4*gGm}o# zHj{$gq_Wwj#0O?;6YrQw0&DM@*@DDNX0sE|nf;r9xO*qerW54MJ|xJPjR1phuUU7( zF0;0TZDvit<6CD|k+9mVIAMiZ938kin35BLQ!1c>CRZ2)Ty_b+=`WG<% zqD(I&gqfaB2r@kmTTgFO>4ev&QVGvZcL4j(({x?JL(`QB&ZbL&1Bjc>Nf4O+j^~(u zk4H>EThov6R;Huz=B9(d2h=xhkJmA6iPtc#2UehhX=(gj(}MWFOtXO-c-b^D{=8{S z{Ats0UWtUECEJgipi|_1e0HJF(zN*(6%+iWFjuWWF*eVWB}NOFHPFwo|-hpJvONY zj-iW5ah!umUL0YP2~0ztNjz!!Ma9ufLSYw6G4Y8rF?k(lVDb!DhZ-gi<5WzX;uKB9 zz&*TW!il?XLXW#_LInomX%nNk6DE3baweLvsXbuwAa1Y8?YLbg*MW_=$>eO@IurT0 zRVH%4NnB#GFK&U!?zlN7+klz)(|AqXH{%s?pN*Hm9(UY$R@|`huh;?Oud#@w*kSx3 z_MP!aY@_i2a1|?!+hR+Nn_>%%Yk{$tWn3JaW}F|JWSj-O#VF&1*f8Vh*dXIDU@v+Z z`^3I7ejWSF_!)2*J&fIBU5%Y%9gXdP$tW`B#`26Av20^&*a2G`o5Wfe>&KcJYXPfK z*H|G|)A&xTs__lrHr_KnAA8IARP1%*W594cZ+sy3wDF$U6UN(NLo8#wF7|-&%2+Am zrNDOFYCI=)qw(*UwZ`9L5a)53@npWw~N)DbOZ)B z=p@4ju+@$-yb&E{csV-I@Eou&-x?l^erb3(`l;ao;9$BNZjW{`+#Ky-xDJ?@Lc^ue zT*F1tOvAab^R_bl5oKmL6J=yL1*}Xh!}n2YhJ8^=hF!qTylvPRb;GbG>WX1GFf`8? z=0%+_%#4yVOo5H~0mJAhDZ{X+orZzH*4$|LCTgwW^Qe`EPk^(z$j~Kfo}qozEJF;K zo8JvsQ8Na%QBww%urD7mFpL^B(243XPzM(0JA?aCjRv=(Y7MRdm$TI1Y*e9vd{nN1 z956al4E9GQ80?OUG1vy%^bmu!Q2_>$Q9cF|!0vo*FemD7gWr*!2HztQ$J5DRGSbdq zED|#q0;VU+pfi$Y@Gg>S&;Wc-6NBDc827!?m z4SXWc7`z4s=uv|wk%tZ3Bc%;oU=zQ~0E^sez>C~yzydbtN(0NtWd>%Eiwz8c6FSR4 zJ@Q|D<;d^)_kkHYrGGtgLjO|au>M)t)A#5fjqK2uiF~KOA6TL_`r9Kb^fyJ8=&u8= zXpa8U$PE33k;(dVfiW7b|05z?|4T%${uJ;=z4V78Ug`HoJk#$2_Na$`Q-q6tZG?k< z1#n1(`uP!D{j3Ovei|@IE%jp}%=9B7jP!$H$FHgH6``vCGD1=RA7GW<(szrvrtcVW zNuL02=_!3q#BqIk#1VaKV3_XHH;&k?uOG2pUkexj>+}^PR_Wi3SgwB)*rxOKFGS4N zKOON~?*wp8zvvx|n9|!9F`>5$n5Tn!8zXx3)J9_HwNSS^ zELXQJEJL>$Sgr}WRbkP(rD5T^1;BOn*G&)e(oGI~r5gu~*T=e{VeYyCVJ^Bpz*@j{ zpM?o@pM-IA-GTjTt!p1hggDtD{Q`)6lgFQ`R*HChQ$u-LMhGyxM zhNkHh0Dm@CCp|P$Cpk1!Ck|M&K02YHZ*&4epX>Mlm)29~d8n(-lTb$;4`9>^bsR#u zI(R5khYxHCOC4IMnGQA7P{$nDwHi8lp(;9Bp$a;xz_Golb2s#=&R?Mybglx^R$k{! zsGQD;P#GOL;8N_-*&n(?XLsmko$bK7U9Gb&bh*yT&?P#{fO|VzXI|)U?LQ$uw10&l z2JV#hbjY~&hmc|IQQ+ZrYxjnlN+IAthHU?Z>wl*t-u5BAa z)wTl0uCcaJh`zRNh_<#Sur!pk6+-T5-wC;;eG}Nbm$Wa0oYOuXa#H&QaCnbs9}1Dy z-WRf0dp9t7w`y++*{HoPWR3Pp;BZK2FA7iwzpHTa9xbnqvw55Vmm z(HaaM)aniH(dq<-Z;MuAaD!G&aJ5zi@O+E4@`LlVvVya;(tz!os1+L=qZJVxp%nt0 zUw*-6sYMRrJV=?L8~>_1})c= z1orWK&4od;HRlHXtMMlgagaZ2d<~q`m<}A%_yA1gK8>NkE{)#6R*g>JBiCv)23Bg+ z29{`404q6LqaZL%BReojBOSQOks5JhHBtV4MpI)T+sL{ z@U+IYz!Mr5fyI1C<7D7IjiZ6PG!6rod839@;98BHfsz_qfziBBV@=>(4ava&)Fpro z^F@7b;FS8GfC=@V0f^l^pgtYYt^OgPO??zN&UNa&0afaq0j27#z;w=0uMJ37uM9|5 zF9E)DlzL7;sCq^~pn5W}o?oj+2Rv5~3wWX)1l(sA^|t{I>MsLu^{2pqW~)C8ps70t zP}S{$Nn@nW571L*2WYC(feo#oP6@c9ZW3@)T^~5n7u3}QPOB>i99O>&%;8`Vz)tWlQ@kW@beEa?U6djjUDZx8sbwi&q6Gis{>Ce@Y)jH@jH#&o~h z?0_z{-~O#?Kl~93r&evszd~)ozeH^W*wfi+J^pEG9sY@G?|?%cp;qG`tXARguT}y~ z>Q`#n{!i7?{U50%14qY6Ey`c47UnNf3j$U(Q|+z4joM3p3$>@ftu|15=&!Bj?60n7 z4-D&jYJC4&YHa^&YII=moK>Uv%d46AA5}8|w)K8Bb^kqT%KqEc9suWho!U+Rm1$2#LUpJAu<90IVRw^|lQvaJ|7KMQ;9^&*&h;-< z{o_}l`pXY7veQ+k{gPBa`o*e_0WUj5wa?FAwad?2wGG(WPgU#v9;;UQJyb0Nj<%g@ zo}WlH%a5y?3QTPq)mT3Z)kr@R)llFDX{-A9sj0s4Q&N2atnI&4ANgHVb@RKZ>IB?v zc~#6$PL=O>NRBB>O&4iTAy&5)Dl7%PK*>=T!WBPpWtUC+V=tGv5O$Pki^NcmOMWvxOIgl0RawS2LHPhM$HSF(`UWX)@%2^S0DPtw%96f+D=+o+P+kNq zatGyEzPR$gK78fxK8QyxXb;gg}H0!*oRrMo^+ zN`Lu;DqRCMy0_9fpVvyKe4Z&C2TuA!r9(bWO8b56l=c8KovXCPhoQ8=$69F(@Tg3b zBz*Lh7W!x@%>|aaqS7z#yGq}@Zz_ETuKIbUaqm+~!`{c027s|Ht<>QyrS#5whf*W( z*4HaldaqI{^gUnR4Da&r%(v&_-chruQG*HuR?`H;K*kvM0zDFgnGp(1Oih& zMB%NMzrsr|FNLST{d%h4?)6B))yqx65m@ttg2+pt!1H1&uz)*HRiJvAD^R?Q6ik3Y zuc4shrL3UgbzeaRm|@ox?s{ER_{;08!Zl#i%PE}qI;3#gYoEdi;M8wbkn!4}aKLM| zf)p_8mndxYny;|YYnH-V;EjEKu*~bzgT-DG4;BE+zW>30Z@V7+eB1Wm>s!RNuYK_G zZN-DJx5W?skEgqgisEbFIBtM+cXxMpcdMA#7$_E93p+F0yL2z0=pQja#V#zAlokX* zBt${F1Qe;~a?kPcobPL2F+2CN{652QzU%^wqF9i?$KEu8Hn|>_?MScwhg?_bg z`##I>Z9%Hv%L0bqGq{6~`rRwQ`Q0gq^1B5$@z42PEeP_vR1oOLgga;Z{n83{`6U(j z`O)B3zKb7LVDFbuVC5GJck>PWLJPG0&KIcpoq-$rGJb&t;(mt<{`H74-V*6?FM(!Oi_Z&pc7E+W0QZy$09%9#}t|YX+FC7 zi9VY76dzT%Cl~J{mmlpTl^^CK1}%ZpKK%K|eYo=v`>;b-V3*IPd_SMnJWrpcybWW( z-e)$?%4agq)MpHO1KK`=d1^j=d5S(?pgkb&)1D{f(~`&Q(*PX;7N4rTb?=J2zuvE) zNigI6ByZgNLEf+3TnM`^4@!A=Dqe#g>JzkZ)#qdHz}{g z8-<3!74Mk5eDBD-Z0}IGftTogCXeEMG7s|(gtkGncR*g4_ny4--u}=zIPUG0ci7u4 zZ@;%QG!Oi|t@Av*&GVeSP2hf>rMFI=iMM8+zPBp05LCTo^Axx;h-0TxyOsb+~Gxln}2RzIHsdlG}Fc_9NG*_Mc8`2%C+!( zo@?y+1iBHLo_BMVJxg=tJa0flLd5e*F283%E|(`0ZX9m*Ov_#NNX}jKphH_?!h?|e z(*vJ7=n)59t z?jF3kjvidOHXdxyu`u%3l&kBplB40Vl(S)4$a>7?NO(-;2z!h{--6TQdk(8df6lu5 zS7==UGZ-Cc7O+?{fy-RNb$gaQg}k57ezAJI<{wJJPKg zdLC!pYO_zeRb?M_tAMu09=8|SJKUaTd$~P?&WD5B?QCneTiIrA#nAlFcDtOd=9ZtW z=#~TbFU8zavjyFfvU%KS&;r@whGnn1;rLk@eZ-RaTqJ3%K`L>+&$`z019<*DklAW%AIaIP0#5`e1 z>5>MG6PgP>i|9hh!n+XQR%o~jF6)9zOx78fNNArNcDazX-z7N9-z5k-C>}0Hvz%QH zW!bvyhbD@#i+`4`i(i(8i#OaEm2+{)l5la%5_YkLRtkrUSr&_nan`!C0d!O5oi($j zoz=3&oRy%V((f#t^~G5t>yxu6+$gPg=F6&f=E{2O%nogpC(fI*?m4ezmO3wIZa6Df zoaZz1oo6$%ohPBW!f+nWBs+i4M4bnqzY^)(of+cXnHlWd1}&DO&W)J?&UKl)ovWeC z;^q7%)5ZB^roHnsXtbC(KgiT~zMHA#TnfDwdFN}HQqEU1MVv1~yM@a+CzI7VGjo%3 zDs)^HoamV|PUOsSCjvBG2Apu2Jx<^c-kc)gu4;qRh0JQFvzZl6LC|`6;&d$YzSE)1 z+fD({eYxu7pIP9vJu}*WHq22c?aTvC z>Y2NpRG<^%8#aj^Cj%GvL^p@x`$_qrKHh5r)xWOrmH%%LtjVA zp)p<5;X}HBLk+ZcwmDR!Z*q8*zHI*jx;r!WkJ88O@23yh--QOx7yBFO9roAKTkWsH z&E0DIy!5yBIqBv0nb79BXP=y2YR^b7wx>X+C(j;D&$3TQPqmMOW)I0eJRNTzk{)Y+ z9`5yCun$TLjn*?2=VOvVtfGsht z#}Di z9ce^cUuYV|*t(~M+q$Hkw{?WO$bq)jX@_hr()QY#LhH!eRzJefSbykwp?kfw(M!^HmuM_nzva`owiv?9kp3X-Efln zY<{J7+svf4+e|_;sm|tSYNgHh)Ymox&`)}3^Ck7J&F9pcHlLuSbjhYUHP@ygHQlBT zx=IwA_oHgTyd*3qfIts|h-G+})qb=dlB z>No4t&~56p4oq#eK9X8*eGnQ>Z>{&FmRtL$KDOQtH>69fJyVOV-BJs!ouTcNX>FUD zVr`X5vo?p$Q-ZZ&YP7XpYM8YSG@pX3)l!dHE2kc`R)G7{JFKNry{yGkU9Ck@H!LVC zYra$yYwlD%YYyl_DO+z%m9yTIDq+2vvSCE=TK`Vru%1uZYCQ|Rs6SQ{DRWk%DU(*i z(2g3k8c6wS)tmC!>I-zF8m&I1)L4B?sjzB>rqmOwx|I7?)hVS`@8RzC6|2`Nc~<2q zSys=WHAT02kV3R7OTk;+hVE3j)%BF~Rz)d6R#%`wbMT0h#z7-)w(+WvZv5JRIm4sDvim+8g3a?ctG^@5+olRM@Je~5#@+92bp0qrY z^3(EA%AjQcw5&c`?n?P+xg({)(igf`6_)NPFD+eCo>)3Thlh0b@C!e%nLYFJRA|rX1MQXC2MG`c+oGhrx zwicvha|;Y^lj~UElGQ9?lNBwZpxq^E5t1xmaXy*L;w*H$Hd&lZ{%anXykLF=nqH&k z0m(ni_a^t5?}EGL?dE>TP3GRob><$>`g&#Voczq(A^Cy1Ep)$bn42eGH8)KzFgJn* zSgN^BGQ(UenPjdGH_>Cw6_dlw<&w{v%Rn0}&|EC}khyU3UUNa{gn65DC%c++B-@*_ zK{L$6d~>p%`C5{u`Et_6p1Q30Vv>aUuOuP!nWPO%jNN=ZX^Z(t(yG}Ibj4=P29hSs zdXt9DzCdHF$E+i%!>lc-#jF)>u~(VZC%rMNO?qKg4ehbJW^a>jnY~IXGAoA;S+3dR zq;#_fNr`6nphSe()2iV z&c2x*O8RPgAgR-IA2iPzO#PFpO}8h#HT8k}@sCa2lgdn8l1faSk~S=~%ceF-OjFCG z3{!LHqESo@lQ2{LB%G-ZG}1y$)suovRgzAaD#Gpg{iZTW{-%;izNX^PPIELBOtLZM zPck#*fsUG%DSMKtDQl9v=@w|JiI}b?@|pfkOnMTlO}e1LR&LUs_}HX1vCO0yZr)!rsY|?UQj?f#QVDIg zB$GFZ6qA>UsL6Bav_+acO1x zd=c7j9mc_lEykx4>y1xB2kwpW(ZuJ*hY}wdAAly@P2=5({~7xyUNYVecly(ey%H0R zJrc>ruF#5$HFijhFt$y+U~CQDxIkmG#6!l$iF=I=pdsgFtexm;teI$UtOhs!O^g*2 z^^D~bHH>ATEhlR%o+xfCk|<~_1f4lHW8TEg#$1WZM(og>n=#s&IA*jt@rThGW5WmN zHdKqHj5WhN=-&M@%wkL$W-xvlra}X+$B@D3G^8K`7lt@!RB4PFpLcy8M=n{(AZNlv|`8@ znlr=9Ph*ba8_QX#VjS z)X>=ss_2^y-a-FiLH`wfM!%dsrvDsTfPMOp=w15v>FxSu&;_j3FQLEFze#_oUkr`F z`}$YurTUlY#rg%%j>yx`p=au6(UbMlp&f|nC)08I40@D44LX9s`b7E(eT;rs9}i7I zfBiVRkA5`WO+OO46IS{mbW{BcbbbA^&>B?M52DNJpP)ixt)2t@ot_>2rJgl(3h(Qg(@XVC=*4C!XwwCTxun$Wwz^i=3LJtcaio;-cSG7Q#}rk~K0pdZ!~gRbFDJwdv+9zWep zj~5z;R(c$C6FoM%o*oOdGL-c;(Pi~kY2tdzv<>@^TW^uJO>dsIS#J(Hhzq)tv}xUO z+Nka*G!c7sf6%&g2Wf4({m@6O(e0sC=yub}bvvPzcu%*DR-)TNyQbR&-NanoI$FAJ z4J}Ex3L1*2?ps=%?rU0v?n`KNfUoM)j_W?A9nyUWZN(kBcWGX_w`nfACD2*4)GekN z>lV>;b+1BmQBk*mCas%C6V=Uuz6Y0X28~rWjkd0n3@yfAI&|8k4wd#(hXh^5uR18L zQwL9L)xkldu}UYJ_C_a?_ChBN+8}pzF3@i3oTL4xa|YUt**Yg_sXE7L44tFUam4E! zq{Zk2(86@~LDTV+jz8_F&JNlE9Y5%b`004kJapV?PCBm8dNk8XpqqaN0tq3+Y3g2tq`_9)d=`zO_2dkA`y#@gSgy4w9z4ehVco|Mt zL5Gr6yM?;0)kIy=YJeu?lvXWuM5~%QsP!H?DxF$ysI6MBsP$Uq(5if+^_2Qt>k;*# z)&uBP-qgBF{ZH#QwLq%`8kVVA#ZGyTKUv-T1;qL9@WaE256;I zcWI?U=h9s(k?N>Lr&?=Kp?RsVMWAYFp;Q$uJoH;6wBo2jS}{}}tte<=Zq^E=E^A(- zE@+;IF6OA_8R`$sAZnlHNoZuYX&$3CY96N6XdZ<2OS$Gg>SN74)H2Oo(9SH<+)llu z=}XPk^oEXRqNW>_tm#5UG@YQS8LnwZJ+Em)4brrNZp;BqGwN`>SK}8YU1Jtno)nEq z3aT+qiPIQ`uIB}fAC%J?gOosx0cd>g(fCT)uJMK9snG?k8(WP}6myL>ilIg;v_Dlf z8Y%J`^%N$sUAiVRu7?U zSfuRg=P6s%&r(*@&On!RR_!EZThNKJ;qqb3DSq0MSylx0;B z%7Us8v{6S@`6)kCc`1FW+|WsFQ)Q<#s&1pysIovawOn-*<+17-xlDD1yx|cQsV%4~dX*>SDwRj%H!2UH+xk$YjC@Ds4*7;kDKuR3Rc?^8REo(dD%YT) zL{Paxj#s%%j#4Rrwrj8olYBxYhkRHi3p%emRno}bDk)@Fm1JnXTB^{=#wt{@t_m6Y zONuH4va||H7FEHMH!N5Vl{oTNm00qsax`>dXO+Xr%E!r1l#f9>wnX_5`I_=U@@3@!=*Xrk?;$5D?;?|x{h=uvtL#S(SN0*F zSN4ML(=lat@&RR6@@{2kXw7;kJCL1}?Z`IDHqf0lP_`s%DVvj3lue;QE1_&e7E(4K z^C;^y@O*RZ5c3tbMK|N`9y$ zLcXIU1ih)NN_^yeC0=rt5;u9nvZX1plL<;}3xBHa- zl6ERBk-U_CL+{p3X`W=EG)FR0nt}GMn$jdmL1~;Mr8Ej1Tt1~?5{J?c(pIHGXyX1> z>?h4C_L9aGd!TdGuh>QER_r9TD|SFDw^s2ZsY0=ZRIbo02vxVNBkL6en*$ijdcXuJCDjZBn4T z7U`h81~i7Z%d3(+<&{a!@=DMmGnbbq8OqC&wB)6sJuD|LL6VRcCke@mLWh`5UWl|= zUVyYL#}7^7X*nL!s2mq*P>vHiW}R}|NUd_LqUxdEcNTpu)#wdHz>g$@Q|8#46c$#5b}P&|Z5e`}_J8Yzgt8>@DcFZI``H^pw3ube1iG*0QtFyWOIo^vN_OTW|Pe%ZkEj;F3Y4r^KD8dnK&YoL>!c1K%2Q!hDvOep%Ck3 zNYH71BZCp2$)LmsGI(emE7%E=sr_OqbOej>Nb zKH@f+J;QhBP8=MvRpKF8_9i(OmmQvFMW2s4K zU8_rt6BMOJ3DQy{(7oo98X|B={UB_W`VI~3-;x7_S;>CFxMVLh{rV((2wjrhgf_`8 zXk*t%b`UBgKM`I?wnHcTu4F6Wreq7@KgnijW@k$_5K<)T2{g$%=mEw{))1m3s|aAC z23p$3CEpPaNxmiQm3#wTZ7<1}1Q*G2g018WXlxrwJ|$>NJ|U<|K8BW{q~rsFkmP*= zk7OCNw>L}PAuLPWCM-ylK!V3mj^tcgcM|8Pz`k}x42 zK^PVfBWzgU-QppHcJYgZCh-f<1%D@gmhe(MnDAKq3^c-TiJu}AiJv4~5*SbQI0pZH$FPVwE)6n7E#C)kPaBv^>=fbOD> zxGzCX+=n19?hUPRVR26auedvbUEB@2 z7qcQ%iCGffh*?0J{DGJm;kKA5;kuYHbjtI@3<()x281LreQ1`WV!DJlF>OMGm=^RN zgTyol$HdeL2gK9}8g#Oo`wqrU+egQ!#mhzL*?ALrfML=Q3ha1Tis5f`FI= zv?5u=#0YDmqJ%%9!q7gS5EUd0i3$+k#>dwTKKri@j2$4|^r@6?-bugKfC%r6S!}u}BwoS>!V`+S5fkutbqh z7+Itp+L$pSAF(izR_vTe3$)vhiZo&SMH(@Gkp}3vyNT3c4kERfrAQ4l-E~E(Fm;hi zOi|=LbTvgpDlk5gw-|@W8)&_+2*1J>glJ>6eHMNS4fqD($5^%S zBkYavLuhh76uyt$5x$4r5H5o@e4g+fEK~S4mMmNfop@CE78WOb6N?bO0nPZ+!o}Dz z;cM6d;UegH`UzjfJcO@cj>3i5h9z$*dG16qCk`WKOquU zAVkEng$U3Qr3s-JK?uR(h49d-zbF)sodF#e!a=uwk5DYOT_^_g6pDt1y{%9rW+oJY z83=_#gH%N*6q6GQ!Ni3wLff8O=sdPf=p42#cn&)EzXXG^Nx?JNPr=jBy#FG23i~8@ z5^EMb0sYcfw>57$Ls|CFbhFn%uvt=(-!o`R6+8B zUYLZSCnhB5f$<2sV{C$M&`td-;DXJArUaa^5dkOcn}8$MBjA8_2-ssS0(RI30bA_7 zfDQHv^i;qayDwmcl?Yg3*90t}xtc3rhNXiT0;U*Azy!k!7-KO4Mp&qTA$C^406Pgf zBA}1$7tq6Y3g}|q0y>zhfHr0itkw;$)kr`S(-F|X)CANq1pzfoQa}|G2Js50VC(|Q z*k%DGY?)sXTi{o~ra>e8^4K819QKu87Fw^Z{L29gTSN=_7EmTAgKr*9NcF-1{Qgns86kX&lfrjuXaD=~e-$Z-4Z=ju^R_^O)J*bMi7=6us z4SfcBz+Hsi=Kc>Y1{HE&MVX)s?kmtACUX~}2=`?)mirPK20F)GfSv*!<<3XISms&P6S`b5LWDE_XJxixs%DP$}+AR2am|oq@80ws5DT%Uo&b0%)2m6&(c) za;2bOL7iO5Xe(C|`T?}z9=`@X<6@xqx#(yqsF;g}7J_oQsAxJUk&A+oxyUFU6vIVA z!$9Y_i0DbshMBw{z7ar9Csc|Ks@*qjBcvP4Rhw_5hxZ=>w zpbc+%0W`%KgN}d(Iiu09pbpL`v<38mGZL)?z2b~OpK^wy_d%tcVdyo`W#BY#Sj}mi zAt(bx;=G9BLD8HS&`{7>&hzL=&|%JV=swU+&a zgHQ>O5a%hB2gJsC65Ry)%W(po2TgGtM}LC8aRj10pbp?eZy3>a97oajpjRA6&?lgK z9N>?uK}8&g&`Y2kP#VWUlnx?t96%F5(HsG22x!BXJ^?z+u@Bt~+QG3G^#VDAY&rIz z<{(3k-KZ8wg<}^g2a@3MM+HILz@^@>sW*X^*mt16K$Gm-(P7X4yC3=m^a<3&?u*uf z-m&|jFF}vlz0oqzEzpK*T>#2v_e4`cGkC21N=JZ$~J8@50nW?+NOn4Kqx3~nfe1RRl z;fFhbthTA4CLmpq`ZiTm5hMi?0r729K{-HMKr5`u=ptwuGz#4D4ST#7)Cp>3RYdDS zRiM|b3g|P?15hcbm{lGv1TjJBphV!6lR+D9c?_#88U{KCIte<$DueC^`GdScuB_6i zJ;(xN1kwS{xf)0wv|*kLvr3{oAU4ou&@zhzIuDuxjerJO#L*s52dD*92aNRhpjV&` zFZ~{iC|Ux#2D${w0j05spbQWZlmLom5k^Bn!JreM!=SyuS>LeMy+AG?TaY=6AZiHG z0;z!HKoTqhs33?Nv<je~|j{h%&T8}Q^CLDirQTmA*;5$F!+2I%S*HZ%{E2}%Z0K`1B= z6ahL9EczhOG0=ufzYF9GatAqrthTVCCLleKI!F;D4H5xMLRw^1sk!!;q%PG_@grxd>DQEY4B(PZZ&tub@$g_*ti@&s} z$Z{^rLaJ#XQluU6YjLkRB5m_ywkn+i>FC-uQ!~_oH{h$8TG@RWpFV9infc=g-j7~7 zK9(tie>pBQmU^l)K~Xhh#Qq2)p~{Wz=LBkz@a0It(8K2M@i__e-}}7i@lyBC4Nfg< z#FMuT52OuN<9?(b?JwMV2xoQRYp>Gr={PKU|JMVo32{ZgK7YA8#Tpmax3~L&5+k>R_iZi4-H!Fz|`~;%~GoOHg}{@44v0g{hBpkM5|#yD_ac_Z*@gS+caW zkgrEt+)i(DX=jOy~$;F5DAIG1BPxQNdXsu)m-+r#AmaM%ytXVOkZ3`ndgHgguXvNr<`=AKqBWER(Rud)0o%O*L<&oPG_<_ zk;ht2am!acYG3X>X?+?0P?bJ%;((a_gEYhG<_1(Vy1_|J!R4{(;oU#>m0O zfK!x&>&z1;_TQNbEZ)`YxKF;{>)PKbnZ2Yy^P;xmh22p^_5Zv$>vx5FOJAMQEbwow z6}oak@XXG4>%4_ojYd0mt?^v;Il1f?(!_u1`p8?~FHvFzRe_j~4vS*`e7~Ld0A4?j zd2ZR$X~vOhB=Xn;IkrFdMGa&637VchEne(esXoOl49UW5lK4aihPKSB?-4AAt%VvNgVRa zlu>*fMGPizN&6Z|6IHJgB!!V0g7x!1;uTjT34Pt?#X|Em2rj~dBBJL8u?JDRh0jY} z#V+#K39^(1Vl6Wk0+y1Rn3mdYKI;pM=#TeOyqvdc(ZlVD+@T*XqpYWwIe9+CpdM+# z9Nr)Hp@j#!*@8=L(D-h*ZDBEL=pl)xEcV8t=vz(Yt@u6;R9+@y^Nr{&|Nr@?t*#@i zeZ%Vti|Yv2tETma(RD;H|M5DdYaNk^DOlg}ejU-?Ls-|oxsKQwpIMint|R*dx37x^ zt|Kusrt8Y)>&Vq+nRO?Qb)@wU%X(PH8p4@4zV`6a8sc}RZEfq3HRP(>i?x%|Ysjj~ z)wR!`R*@hU>e|2O&XnmYa^~HxwakGPWXn~nH4pL%atE)t#;3A^oH@j?HvD!Ov9z99 zZQi|%$Vz=)tsVZ0i2r@P`Z4S;qS0NvIERWBkvYUy%w^@!-dRN9kJd^|)(j%qEx1zLIE`48FD-vt zpF+@rfn|N&DP$(Tb~%0TBtk!2w!9^N0`alWUM3feBQ}ch%aTvWko_#jm;XIyW4?|c zQXlk}9Y%g4?{AAOOHU6Y1u1KP*=L84;?SYL+opaX1G^gkiVlBA{LCNyHSZooeo5v3 zJzM(?X;?@9KDa-CeEA;qmp!{5QK<9%8yeAvT)AWNcfz+9*_$r?7Z7%cd(_sy5({6D z$OB_b^%dPnpZ&+Bf6w<59-ooZ+*g*ow{;?nIr5V0n@`AO*SRJC&~_yKt^ZP(TpJQ~ z!*c0bT`N+Utgtk4t_9(YWM8u7Zbn`noc?q3MkDgjx$}>bbptZ3{rba`{zC~w?&qa~aD@e4y!Q$2O%Seub_@aGH0U|E6zA)dI zhpey+FT8HfMVx*&F61|4BQv9q7LqD6kuAOX3t3Oo5nL;_aKAVeIZ$l%)fv|&)gcr#y{QDe@-AqQNlgHWfW1sy_iorfk%#oU7bIz z8jtV?Q|AM|$07!S7v=*CqLJ!=-Sen#B+}q-J^y$m3~}*MnqRvff|$5*&L8%?faE*O z{`xd}7Kyg*`gM$S25B&R`-@dF2w@uC`1Q8*1TvtP{OjN6cl7Hc$biOyUy*i)kODQw zUyN4)NV|&0uV=>l5QZ}UufI2UBkz=c&+QiVM`D%w=4z4c$U~*-xg9@zkPFIp=H{Hd zkh?0GbESpuNT^!e9B$qPDc3kQcihDZVQ9P0ok+JwzUk@B#dp~t6-J_ScO|V54fEC6 zfA0-@(@c;6Dk)HipB#UGdw$94llR}h}$7W)miX-mKk26!xMUc(K&u8MF3L-o1 zUzt(4$A?(Frp){-;zr8r&(HjOUn$3JLl{4;W*UxeMZPR5&Mew*Lh810&R9#Y;{C;D zr!UVf;p5f2rp2ok@h+Bcr_0iQ;mf>lOds7hgMSXb)~+ozi9Z=0F)iFZihn{qFfEob zj4!?9IBn|s9q;r|V>)D^A5W~~pRT#`6(8LHd&=CU8^5&JH}&s5DHLnN3#s3oG81pX zUv!HbshZj=tY@|;UcWyE8%cUpVof>@s~~uLXklQx2VIK7zwL`0krHg+=2RW9%km3d8Z|i&ZD)pIpS>YUP<2 zuRDvswK_k(^>YyZg4Wk@tAXSA<^7f8|K1C^e;mM{dyzhVvu`hc=UB{m;3t1Pi}cZP z+iE{N=Ib_Y{lE)fkLivdV7lSIJrNnd6z2q#^p&yoy>|FG`5$9MeJlL>o`x|^7Bl>w zl!s&UZH9P!P2O1lC0%^nIyyFaOcU>6ae7QnQ58QG?l%_RtAIaq&vfkH`zXmp0zahA zI_5Yhj2}5QF{+%;kFUPoKB{5EjZYXVAKlr*hUZr;8oe5^6^{kcM+G?66PimxMsG3y zCM-|v9Su}kOkgvx8+9z1O_+~V9d*;3OnCp2XEfx-NJ99Qg^>!G9|>%pUq_77`V-KM z%8};PFA04;r6d2|gCpxdCisNLj$j&13CCU^9eGTwOE|>oKEl&onc%!nZzNgcZGz}c z(Glaw@`O)|t3S8AdXj*+4gLJHdOtxdukojd)t!VZ zpyP5v*T|WlV(ZKV6}ufjSCq06PUe{ZQppgWu;^I zOC~OXXaDQrCk0UnqECy5%L_vjB!!cPM=zaAkO&VScFYM%5NQt>u3-cw@EAJ|N5maU zV9C)K_BpvPVd)S5@OCf%gz1BSh7fJvgrRr+L*48i3B78yLx%^P61q~#hWH-YCVXDZ z9{Ts*zu;k<@cqMyAuV3LgkQ$qLrF~<37r2K4N1|I6Eu0HhB|HJ68z)0485I_NT807 z{^-aTPN+HX@rSr0UxGl>^B;5|XP>dV`a_+-lF<5)`eQ+IJ>Es_;*XiKrTB(RdwxjT z&c_D|+5QNxn~LX5RQa*&Ga6sBmFLI5^9IwiFFx*1&-b!-UGWhSmEV6Ewa1fYOTVA_ zuPOfS#f~;w`mal)+ekV?|yo1;NSVmq)#b+;d;}+qn9%AOxGs^L0Mw)p(B?D{7(zSBZ;Je zXfv+(D!p?9ZJSx+9Xk96PS&pB7I9Vs`m{f|Atj{&W9K;>ZxiQ0$nrQYJbJEw`0fx+ zSm{fD)`5Q9ua)f?e4pEHyU@s!=}%JGZgooOQlaOFc|lsg}cw`$#GnB z)_m{3^Q5WI9^4it`!gL9fR?DcC<#qD?_**i2PhkKs3rS}z&1TN;p*w=P7L0qOq+gEKHE*v|5`PW(> z7TlMg|9vgqzZ%E!j{f!i(Z#r&g3z!3&at&eN8*}xIeabK|1B=oNaJgl&zCrwkib_L zoA$Ur^M87Nt2M?oeIDqU;Hi$=_NuN&W%_ko@qhPwiW{EB-J&sjg09_*6AndtE=Jvo z8x1(!^UC?ZI91o}J==Nn7siPTasPe2`GtokD9)oj^-I_NBXP$YqQ8v$?TeePI`YMBYh7wxTzJ_^s1%%qKa}{R>iaK=0fSXPt{kt zV}wNF(i*AV=ZQRVwVy6_|2wx^>|Tq#J!;o2@N6;mz@l2Wsql0xgN48Q=DDA-7Q%nJ zPE_>A2CEEoUF7SEl`*gDs@vZhyVLuA*M%!}vD|^ouE2qcSg%;Lt62I)EMLayE|Xmk zVgv4M?-HSw#Ol?1@d-;*dxL3J`e1U ziw#dL`8*dC7AyKR{qwHK;8?f5*w5_vz*u(nz|XvdfY<{@o}YuTow0UD4L=LUd&WLV zk^Iab<``S?X3OVe$1P)z%#3wz+in<}snp)NW~Lc?c;CxTFDb>?ij-@e6H5}YDVarI2yZLIz?c{+NGH$42 z*|jSsu%fBs+HyQ_lDp4#f|j9wmmy+=_efDT)1T z%-pBEPjAt{m{EPgC%^gqG07>xpRA7Wi0Pl)`H9%%9y8!;^-06XJ|_Kv(kHDfvzT8Z z+@BI>bYr%~&$oNHtHv~a|Jr`CKqkh`r@Fm=R5&K;`Q7&CM%*z0Dmm@5FJ z?q#rr*=WBgzxHnJ(P+Ujv-b2O1JS8R=bV{&@5a;^&Wa-GJywp^A?&VmqRFuHX9DyzCZz z!94wAVvlWfUQ_JHdrwWG(@q3_v`p5H-nr`eQRj$K^kA;hN1C=|w4Jf^NACrGptQ1l zjD5it9TYa%${V{DWh~s;%4@t3)%NU7YxLN7l;feBtzMS~qbMwCt^e+!4Ch*+689Zz zb<3%V@@4gGtu=Wa_4AQo>ti5{?mr>b$`e!?bxo9|we8QWcZBmd6>SsNHinS_}knQKNTLTcndiqXN#xv_x$^9aXA%ti?X^aMYJ^kCxcMT~Xs@ zhAm27UQvDFQZ4`Pzv_6+qt0%fY_2+^8^zw-(QHtm9L30g(<~q;6*YJIX7lkQ0#S|@ zY0c`l*rH;&Vw;antVZVbA8Y2)o{ubg;@PYjG!~hgY}EYv@<3#CkaTl(OJ}5$6Kk{M zYGdSz{8W>%YGq{crq4~6JYPgw4!&)|1>cK&SADDL-@RMGrGiMXhS1bomL9o=JKn^6 zMUC_c@@}fHPKZq3WzrN`A0AonB-@l%e)nwyGTn_|?|DV; z7JlFO^Rh$aNuJw{=cs0pq3l_W=g#Rw#;_(dj(96Y;#f{K4ya2+#k-SikJg6`?k?{2~A8rU)IGp$`?pi{b8j zn?GE*FdiP4`Rv2B%7O6ek5@k&6YdOG6J&h2b+jS8cvtv`m|GR$mU#z1{JYoMw*Tcm>NEKv3P}s-_@8lb=D_cUsWsZHS^H7WoCqI5&7wQ@u&dYhT zPW9B0@bY76b*Hgi;q;fWb>>WuaGcojx|~wm@XSc>I^uJq@YW8Ky7hPJ;l}22b)2;_ z;cqXo*Ifq^WBAs&+JE<|NiSEz_I|Fa?Jk=QqdS+?KD#^|_VZD0tvanIEKCKf)w<9c zrkNL9`_8XAOn`4!?U;6Xm>Sil_9pASu=AVMYJYcM3;U74U)x*43`<^Fs@WTv9Cjw* zdrgovAuM)NQw`60RM>0s(;D~JXT!{RuGUCJ9}WANL$CRFpG)cW2%EfrutuI?8|Lib zTC>B@D6F$xuSU94Ev)FYL=74#9ag%&r3TM05H`h}s207+8g|jRv)aSrZ>VnD+iKC; zsZi~(l4^AO_t0SB%xZGS=g`sT@ztt(8beEtoT@(ARuOueeS5Wo=abOcM;6uPuS-JX zjwx0DyGN$yW`rK9T&(I_rG!3@9;j+Rf(t#MTVHkh^~F%vpO308i=GILE4o}2aduzm z(h+La_)G85_i~|C;CGv$pT7lERrr~NTHJ81lFQTx9XY34CEq3!I&30dRn09J3Vu&f z#p|>!w6%G>awXz#$eY5B%9Nt1kkyd4mH+Oqi)T7RqNFn`)ddBhVT$vb_8uDWgZ{>OnF+|h$&wFWHbV!5R;QQ|} zXG3a*8sF~@I}#$d<>~v-Apek0b64J5>~jnGIYfVd*V!s$Ur+e^CT+bCjrK$D|J|Dl z&xnRhd@y)#-M|_0txoE_VA0w|^Lp0zxe;?0e>F|Nt9Kl}DEO)ST^aY6i@9Gb-#N53 zUBrIgeMioGck$DF?z_0{PcA025Z)-3@|DN~3g1cXxLyg8CPE z_c?TTw{%H&qauohi3*B>qI7qCUVQt#IycNP!@vyl{MK5#Hn5q&Z{)v$!axNgLBpwpLk!x0i1fqzc>hr>o? z0%tB&4-1(J2WlCo4X00Y1@a)F!_Cfgfj1ty4@b=s2a3-a4%0Xu1$fcQ4qHvG2GHs7 z4qNKZ21rLx3{&-e40t`bKNNB4dBDu^>`-%3e}K2btD(I0rT{-o*N}o?dBEc6gCV#R z^qj>7SXtd3$}kQK(5ZA95-7P5(7UZO1pc}P)M!WzWe8gaFcfeOc?9SL5N?tV?bj&; z1nX`O>dc7-xL1E4v}5EA_(J%6P*jsK;H^j7;Aqgf0E6+OLALx8e?!sOL8*at|H<5- zLF(x_|9O1-!Is@m{`YTc4#Isxo^!zex*6Lbzi_kvo##Y@)6(VsQYsq*X7btopl@m* zLm|%J;@Z=JT-p2neO=81?h=9i4`m7l4lld-iw;H&STULVtE%4^KnS$_f4{aF2w0Z& zXR%cuxI7{3Kf53@(9p!?uMo;Ia1>ALFGNW=K<`52-(0!Y4|kC!{AIt;uTT0#UVry{ za<{4fe&$=hO6L6jT#F}uoCA^l;dEVo60U*$a<6OsX31>&A4e4W33XlXXOl|tqjeYQ zSD(fD<_=N~^xZR-%2Oy+3?^@v-*#h`sl1 zJ|gTBs~GjY_;$VbElsztTJ2P?c37S7`N*fe1#^YI80VJWG4&MRQkBBqSLIk=f8Lnh z#*u@~xho zQ(E7Mg6};eSBZRMv!D0)`R)6tX14e27cTm=W|s80J)idZoD<*Ey7AhlvnZrzmVU%X zuga-sTdK{cphdT5!MM_=Vo17Y#5>2wbAr1kEG*7ve(rn^M^dN{_u*bQ+@GjQ9ev(h zdEM>&FE)Bzzo$FDOwH$RKt*>?k(7^rdP?_5=4GD?J@>ksW0-yNX5G8vZjJfHv%`tn^)U0=Q#FBYO5lwe02%LD0dyaMXjIDajzG&^_ zcmCn^O1!u;W%sRDQej-@Ld;_?ZqkrWS^5sI#Jf(NaBmyp$@Ti}c(rr4BF^j6mCKR2z1%6&?69*lBR1RJvM!!3vv4&nOA0|2qR+YVsZ2CLuEycZD=Bhio`gy!e z12Z}X+3CG5oFW~M?-6-Tr1*4)L45LS-5ALXj^-)@-0vGnd0{0n{J-NsqyXO z#pa$o>bKiJk7;<`ICgGdT)ygA)2ZK%N5StoeoLmEOOVC$v&6;r>(|LV-|tej2U;I{ z^z|RNJ@8raNRRs4Hht&2ho$j{Hn=bPM-O|nZq&Cuj%o4Gewx$98&&4((4c#sGiMh>|^dVRG zg@f-c{vKxT1hg+&97)yPc|^Ked~2lKH4VyJQq(TF-@K91^6D#tdudi^%f$d<_sIdz zmfVv)H~IzB7PzOrrTXGluO-xyoB7<0FpQ}sjIP(sr=6e$q}I88U0rW3B`I*T5c<~q z<9>qM55MQlN-LpmcbYqzhpheF*!LbZJ3X>gwk^_1>x8oOWWN?BRfq|=t_`j#Q3Y4(685CZl*2S3yL$=|ioUYX%-mQ`9K8D@#04liN3H*I~M?#+w_su2E$(jc`9^ zq?mOH9_wywV|eFM>`>W=us(8G+D~f?Wovb@%|;sQn9E$&rF|RE)26%Bf3<9UKoahf zfW6-6eR$I)T~Msir#dcfo}7v#=WvsoaL0>vZfN-sWp|?q$(= z$h1)6e7qw4aIZ4OIp7J;LmEfmOjAtt(2p+A`R~1x2K=WE&YL!i4PS2=IEyMyHmtKN zI+yc4Y0!Kk?5s=C((v7b-I@QWsG*CH+*xrczTsWzu~WkLI}LCzfBRy}>CJ27hA!I| zPGc_=8-D)jbvk?@*kE*{&dK`?Qv=~no)hgS!Uo*iaZX1woAuYX?mBU<%+$Z}^Kyzf zd0AgJYw2{6y0?DFOw);&ue$!?V`(RT)y(=&!k3(q9I^FpGwGegF#+|=`vgub6}I&c zEw>#tUTD?BoxY#!y`v8gPyIEgM~-f0RP_WcEshnjCv}{srH(?wi*@musg6g7lXV(N zz>!8~w9fQRfa9%ut#xhW4vri{C3Wsv`i`{3Np-$J-qFrSQ>+bGCUfw7FIda<{m_2Qp1D@y<$`_q5>ah+=V$wz``a~;OK8V* z+P|xLQ)B28jt@&@^rhO%UbWL@ylfA~fTQzdAhW1*B zbInx~Mf*Bo!xm};(B9N3YN6V<3t{I#=wwN>5m z=#w2~+Ry6DTcdUYR&S~y50N)sW|z5MS3Pti&F=R|ZnYUL#;!O!y4tEWz-~Aoxca5O zy`8>}OLg;aT{|^?qiVu?vUZhZiq$XA@!JJ&2v!s2GTJqMWv*`JCbF{}Bd&f|y>08? zwNvFOFlW12H&=DD_O0!o2XCv^d53Lv3x}%y6gJv&=Rd519EMDIg6)OUxT@^6|7;Cv z?o|0(d)cnGxmOJgS=iz~Hm!=ipl+M^QKjlNR>C%6Nu(s)v=MQ_D6Y9)Byt_@`{5l0H>-+cF zjebfc>5DP>;{d6!SsqE>#1 zvgI2A99Fst{N>f+=dFe|7|ZuJ4=kV65|#gI`eW(gzEkG!{n4_3_g7gu=VMEcKkv#c z-Zfi3e>hUsjV-nuz0+LQE1YO)tzJ@Q`{_T+7>4AsqEJsu!=?LW7^?-I6EQZ6g-H zNah|GU2U?M#C`XmrmN7x?{xS$Z2R+j)77ltk4+2z4EEqjx9zecl9)HdpsbG9i=Qv?5@|@@a zXZL`4+{R9+26?@CBKz-BF2`JRIsFf%4u)|NO^VVt ze<+$(y82Ysyf+9_N=V3Oe!Dxc^n((;`A=NOQoB2N=EnvGrG@otX3t6#O0%b@&8}|? zl|rtlSF+2@w1%v7-nPQ*5AjjSYmjCp;=5RKs}wO4c=x4ba=_PYO8$At!K9U$N_}_9 z)T+9f1A9$L7@mZgSVm6CPZ}<>{_`;oDk8~S0(qto?pV_+j`$^y=t4}j4>yY^30zDsCQAuxlBJ-e_DGJXtb1AiW)p^ZiwG>mFE;nsLYICEQ zfabZ$Uk0aQjo%$6@sozd79C|K>jg^1*TPdwSlvX57j^HOkcn~@Lyl_nqq&LV`_rQJ zELD^6y49jp6A_c-sP9FO&a;`gy1g#)c}!x0t2tP-czeg#OSrK}`SPrBK4WoFz=zky zIfThYAxNLG<6c;i`NbOJ?PdQWs^^);7W4K+mEKt6s5$*2dg1`%@Lvi=E)Q&s^%sPT z60d0*FKnAZ2_h1J6OkOQMo+3$t^C%=t^EM6CW#J)3X4jC-u z#2+#u&TA~x$JQH33>OzV9OoEGE+rS51xFg4V*!OC3pb29^#ThwZ0wC>A{-0zo@*Or z3>X&jOGz7z9w`+*D7s+uMnSX?51-PgErP2Ma$^xs{uq+5;ucnLeK5S|w^7jY->~7c zk)H+iZyF4@Sl$(6T*xy#yz{8QJ1ENV`{&kzD?>L8OBKos=13e2RjM)y;tX{RM`$7o zxH6;-xgvrK>fT>4blP((xI|59hz&F^$kshFh*(lDI12w`;N>e_VBYoKKxFMw0p!(| z7#a+`@JI^yRdWrd()RP6d?F1bE-vJ!q}(vL+5aWKr^U`7%W^#b+k}?EgWcZz<7G*M zjJ*1MMj~#50Oi7bQ8sb|v8BX(4UvO?CHSy>8>Qd+!FmDt0eWxsckmqZ!z~8%od*o_ zv+Zm3dqS1-8=SNBj}^r7AtyKE_}P5I_HdnYzAlz;>RlwwS)$_1}5- zyq)(Q@Cr8XFy@5m+_xc9^~_C8wK@vW4ZGJ?lI~) zX3^xStKsXVRpI9eldkFZ_ig9$z5J^CBOhHryHMgt+ZQp8EBv7rs5at@?Go6 z{ni_&EA3pDs~i}jtDIbr+sEast1*2nHLn%xra38C^fO@WUf8P84w}T>2S-) zaela=J^d{*M}Y5}_Bq?zIjp76v{j}(b0Cix98;qGbWtZ~W;b4&@veN%E!W%HH%YJL zNW5~^o-F3f;gHnV*1SfYBb|Fq`|(G-oX`UvZQVQD*{hb6+CSLlv(wrRwZflHX1ko9 z*AfqYp6%}PR%`uYUv^$czt-SXL-rYAjaETcadwVrhE}X;YPMT3q7_9So((z30zq@F z_Dc6`k^p6`KesHi>mLeg32SI)M=vsHMYG9e=kelcZSD$X&)cqO27lzp_D}t+d9Ir( zTjbGW&CX)HY@v-t%{y`1S)T0qnnri$|8=^fG?jcmXJz=`(A0Dp&x%d6)%39M&+2d0 z&@8cQ%o2Mmrn&A|ng#jG8A1}x*`UZQ7Pc*oi16E4c_QC6l(N0D?3ABtFgDs`xf`@= zoFCWAYPT-Y;8;}5(s7B`FrX02;`0j8D3s>OGVpcMAaSM78uZoG$jl(ly6Y{iq4ew^ zGt7-!gA8{$^R?Z1jeUjhnZ71_>V#k-(?We#UFylBOvrsQ@pP-7*i>h(lb5S!HRNS7 z?&YRo}jjKm$Bf$w7 zUW>og`q+_-mHY{{U*k72K4|r+DcpC>;MlHI8x^z2cvYCHhAe4i{8SB9^Qx80u$^~T zi}bycAs=I;_EwBLBkH1@n(;9$%DEcZP^m2y9i)F)KU5_QSx$c(`CHY@XeOP5VM6tb z$h-9UieA-p+R=1Yu}anOqptM9-W1iEKXvI7D)&^0J{P5%K6O(qc$u26u4Sm|H5!p# zHzuR%|LAr)_ByX>!(;FC7lRb4ywB~@s9=3FT&m@%>s+8$1Z|q+=m2y#$OWH{j$D5_`A}M=;_p;iffct( zC)=B}#C9?j67xrCN94Q8`Dq<#i*7%Z{omE3S@n!7V;Kw6G{`!XKRKnOb=s6D`!|NC z)l|nRYvSBagIq6ztb_97X1laZpr!0dX_S`pNL<+{NG**UpItfZi*%Z}3bFF~b%C_; z`x{EN?d)mG9aBm*eAH?GPVq{sr37iOxtf(i+4oaZP4bnDikDKqVI!3ScxF<&8v~R+ zG`vgY{$iyRA^S9y8COjy>}5}C=_O&MVV8%gkSBKb!Byfb%uFqeT~gFnicR&c_^3EI zADa4VU`X+PdSL3~54DOhs;;R<3mJ+tyB4Xpj=~h9n{-lz$h;Io{S;FHlZoPxuz0FB zkG!JE*2UCS!ApwL1I(%9;#7*>3FN8Iqz)BU?Qv5%ul`baBDs@7C;eJsnQ|coa?F!L zWeO7SCsJy76BSJRo}@6d-2OLibf*ZBJ1L~(Hl+MK(N?HWDov4DmQY}i`S)k@nO)&m zWNgZ(5n=`0nENSgwHxvwNjFkRlc(gBbKO#kZ;Z-2S6iigHENQd>eWjbzLF>Z@SSps z(YXlu&#RIt@pFFic9i@mKaKyd{2OFXoucY2AWx7$m?A1hC%@T$ko@ZOL{4sNSa>@V2{j?kdY)>!*ZE> z7dn$5FV5_JTjqCcNz(I8N11Nb%p|pY+A>=>aY->};xc)U!;*5s*<@$9yC)>TluIXP%vjcdkcY%|+@HHHrhTe$6XQ+}yFcn$nY%7^ECWXiMIcWu;23?6E!9$r1d_Up?v&Pk8ECIc>Vs_35Dmd!%1hN=3Ps`_8Cjo8(&F? z8JCr$rr=G8pX8C;f6bhbFneCoC6h8CZfQqC-+>VI0iyQCBpS}v<0B87CAcQ%^|UHs2UN{JUT zrSZfs_QgG=vg4)ue~KqaCB_HVkBdvohR3(%wuyVG-HpeKEEMN44v2T~j}muxbwfP_ zC0R@Hs4S!Sr|in&ZXFu&c4vIzFTcpg6Uw?6c*5+~Ctdv7*w|IEoxAv9*<7akt%7#NH@P z#qEm;h{oN!(WC#o;$);~MXwM$#@R0% ziEQPX$5j{n644XUi(}S%B_cDf8rOQ*A=2Y56BkllEb^LM6!k9d9R-SXxU$C$mRX6! z(bL6U(NYoFd~q)Bs=g z=evSCR2U0=kMisT;koMgSPt%4VTE#R?8n-1Ve#_2v16ib!jGy0V|P0Wgx8uqV%=mS zg}VpsW2yT5ggM@t#U9I=3v>U~jpgf65FWu-i_Mn0Bz(pr8>`VwAv~oe7AwQQCu9-C z7kjgGMkuh9Gj^5!nb76;46!Y7%|hTD1?ric_rnTN#vI2~ef1X7dbt%7uW2I0&9D^H z(<&=e;5Hj0!Nw!h)%7LjFoH}dgz{|+`Qnz~N8e{Lfdan(gdKgd$#`!O7b`aC>S|H_BQ{?X}2yO-s;J)-Zh z%v|o%afp6@b?oxeU5n@{)27QW>J6ed{Bthb&1pn;{3{t2b1Fq|7kOSzce)zg*k*Y7 zT9ruj+}PF2Y3rAxv%hj)E>z-*9$O;5Y@NXrefwzb()bcpbS3HMOKV!B(dG=pm&WRF zQIAMQF!fT#{mrNw5_d1fE-yw2$vRyUcb<##Q_{MW_H`;sLQV8imDPtRtUA-B8&fZ% zEH!X0ZMcj^b*lfp$hS5SRiZX=ksi|-MWft(v4_4XidwGpB7JjpRFP!tMLxsQs4k%! z7q>QZqa1mxF5WIki^^tFzSyD_kNQhp|4bW`me8oOwLRW$zu+jYnHk=20vmjoMSZ z&0|-E7j=orfk&qGC~|*Io#(@&?MVNp!aTyCS0ZBz=y|Sh&PQqmo?Kw1{t?-v^7}%I z5(HVZ60A68c)=zGN2$bP6L4MYp)W6lF!SZ-3?P+DVQq?0m#+WfB|t=1v`VUmG^E z<7zthPv+1_!`=V5$0LIyOWT~e?`-==RtIWx|MBvSbQcigW|?)0oStLirg5@~JYR^z z{btrQa@XW9mywTtWFg4}SJtjZWLk2$8ZsKOGIY93*d6G6pq}$T5v@k zU5X?ZRpj!k;EG(HzR1O5!V;MjOU{)_Ko_|wzQg&lk35ofdYW_M4sqnUf91G>Yq*g^ z0u7v3P7fpGCo(wWo^3~9gF`tV=B!4fFuHQ)`TmXY>e1oUzdjp5W+Tq|f_pjw`f1%c zxSSW3-b6f>T;MqV^gN~VyKZ#M_Uz(B+ZK`DnuS62jiQ4EK6XG?^TWFQA) zZ+!&ExCKY^qsoZi4vHLf6D1Mhn-@8*&*nw!M3QqTA7n%*G3>At(CmM2PC&W&Ip>6rMBe$a;r$H+)T8llAYwzkXT8 z6;?s_rSSjg7+6)P=ffXHoUjNy`VszV;}^^CJ5%Ai4lh}P#Xp6Uzi4CmxG@pVE?vMv z*7+hFdVu_-J}eu0BjJ2EjakY#`@?xYUt_tv*BQ>L$i;$v-x5w;PR!EW-VjbqyvE#? zUmbqz{fRj-sw{l##Q?KxNKyEbP$l!AcW(Hf#6)IB*NpJ_rCZDz&dK46+P2KPZgJsT zRjSOF{362%@CBGZ-v!}p4%E!f@%K>w(3AQH(_Y_=@B;5KCW2|-@TuWOrUe|&a6ZOt zrYZrK@NmB{CRuCy@Wo*_rs_niaA!I_rllvQ;R_xTOeA=Q;n;2#rc*VYa3NAWrkC;R z;fq!ajJG~1hxb=cFm7Fv4=>;8V${2THM~T%gb{oa4{uA3W=xQ}f_je^c+DBb@h*mA z{N)*626BZTbnq}L&$5Omot$G#wPp-gyuQiM^N}X}eEb)NK?{oTgV)0h#nYtWgtRpb zR-T06;ua|kYr8n%Aon(dQ^GNJ{fj+ABkw*of<>KS^3fJn&PIq~+IeGKZdWOZVm81`Q^8_0`!%B}^GyJb@g-`Dm)sN-WS){AnD z;Xf>)`E^<|%Mk2As35ID+D)uz84az#gg>@!?0{yT)(7je{DUUa&I9#JdnKA^+>afw z`WD$VHKw*${<~o`ubM2e26=8YAE?Z*gFU)51GkN^|9ugsiT$aE#q2ZFNE>ToKQiFb zjE$;e?@IoqmQ_;4`WU~VP90FhKJ@RT9#@vbs>Bsh&p*40y<8DVJ#Q|FbsF@ge*Q-k zyE17)oq`CXUMn#vH}$jLOW15K5^7l|9&FgvHLBEeT-X8qPgLVQY*-7|0jdRmW~}br z3aaHx4A_Fi1ga0eXs}wPK~$yHlvtBCYbuk#^Vq&oWvah&q}a&G%T%u9MA(OaDX5;z z;bE^G>`THd{YEKOa*Vmn^n_9)@&E&US`DdmN@n{l%$Vwblv76Qm?lFf%1G@M z%$cnwC5`4HrrYxhWsLS8%ybYv<*d;!jBnU61+V>2j7Q8IglJe%)*0QiYr4OF~zljVsq{t=5ezJMG^S~#`=8@F+}w zKfx%!Tp*9U{0PH2F+pA!Foe1NzKgu5w;!YNshB*9tQV8=If~rExeH_Z)sLK_za5i4 zWlG+}+KMrlmL-?LG+|<)DS1~WZc)heffAl*SBlS%Ad`W0FChqa&^Fj=n7>_}U^JN`r zm>1nUWOz0yn7-C&GClkxj8wy8GE7T6My|4stk^9U^QI_`tcoofvz~RAEcZ(UrXrchzBW#KRkbr2m{%;`PUTTZf{J%=>j#?+ZSKlddm7-Of|e2z0H z2vaGSbI!>21|~`bIp?PxfH}S3elA$v4@1SEcg{o72Qxq-aZXLl3qx?keD1u22j=fG z&beV3H;m8sKcr6TE||DCuSu88oiJL%9i%S44w&lZLeeKuc9`nY2vV9#8`PIh0mh_3 zn--Y60oO<)xy&&{_MD_xQ&WtrE)l73f-#0cW`#uMnIR_c(gzZPa|W1E+CGw2BRxz$ zP8o@Qp$>+1C6?slvKB`3%fDicswReO)Pkh8Q2pQcQy|$rQp0>J;3W}tQpG%qCL^(U zu8gs~xk>DERSEU9bJd55EicGp)J3X^#Y$u`)lA96`&=^r+7%(h4b@jMiHo+x1`^U3 z>i4R|-yTb14Ep$qt*s?6>g80#kG8}xyYYKOOc|mWm!R)N_E$wP@z$e6$v=cKfyxa; z50iy3w3jo8dQ}85x5@7jwIA?fa<`m_3Oo5wKm5Yb6(VV+OPGWTdZIt)E@HaljtQfu zcrdjAbA)s)7ckDIoERw_K$vxn14I7Ho$%Quc1+8d z9^oQ08-}Z1g7A=<6=RpoLby-Cf^olzOZbb58KY?SmtcsI3G-X}4M8jqBkHAB9~BbJ zYtv&Me~Tapb)&uHi zF0J6l`cnRD`Fy}Huc5%S{_VwoxJZt1dj0^vQj8q4SR0F<7kB*24GkM7tPb7&D^OsN+PllNgGy97VPrQx*^Yk$#9*Z&oCZ}u{ zcjGHQ#ti!nx9c80=G5^Cu0JO}CP%Rzm*zPh>fz@d-Noe>#KYi!b;K>0!^JptYv7)g z;$m8|g>emBaWT8Wbhya^xEN8>Bb84kniJInH7c4yIY zp|=nHeCXjr-yVAP(4U8%JoMqA_YVDb=&?gz9eU}|KZl+<^vR(&4*hWGfkWRLdfm|9 zhMqR`v7vVj{c7k@Lth$t(a?W}o-_2Bp|=eEWauG7-xzwu&>x1LF!X_;_Y3`A=n3l0YcvodVSE}gPtDr z@t}7H{W|E;L0=AfanOH*o*VSpptlD7H0Ys0-wb+X&>w@I81%uQ_XYhf=y5?`3wl}5 zzk;3>^r@gX1^p=KK|$XMdQH$@f}Rrek)U@3{UYcQL0<@ZLD2t!o)7eSptl449O&Ud z-v)X$(4T>x4D?~3_X7PE=&?Xw1$rsaKY^YJ^huyM0{sx^fk58_dL7W;fSv~QF`#z= z{R-$&KwkoS5zv2to&)q5ptk`11n40^-vD|A&>w)F0Q3PM_Ye7g$nis7A9DGSzlWSX zg`6(raUpjL`C7=) zLS7bfv5-WRAa4h`I>^sK zP7d;Lkb8rC8|2s^uLij^$e%&Z4Dw`<8-sipr0&f_xR^s30!| zxhTj#LCy*COpsfGd=li4Aa4Y@BFGOxP6+Zqko$pr59D|tuLHRp$lpND2J$qJn}K`` zc`vcT>2J!W|Uu zop9HLJu|pd!aWl1j<9nEcSN`s!d(#Ve{ko6dmh~FU>6PUaBy#fyBgfj;7$hjFt~fc zjvCyt;9doHDY!quoeAzqa5sYc5Zr;_-UD|X*kgk`4cuek?gBe)a7TfA3EV|szYXpj zaL<6d1?;-P9RltRa94o)0o)1T9suwDumcD0`0!p2@AB~e4)5&no(}Kkup0;O;PBoJ z@7k~@2k+GI9u4o#@V*T1$naha@4~P@2k*S_o(u1`uuBK;u<+gr@2c>A3h$)w9t!WC zuww`BnDAZ+?~<@@2k(sVo(S)TuzLsZfbiZ2?|Sfl2k&(79tZDku#*SxXz*SJ?_#i@ z2k%_)o(1n#u&W2}Q1IRa?@F+@2k%7i9t7_`u)_!MIPhKr?=rB@2k$KKo&xVCu-gak zAn@J+?;5b@2k#W{9s%zTu=5A+2=HD2?*g#@`Q={+6x(%h=JM|oFL3Lu==AJg_jBb8 zb^$LQpMmJCA7{4?&j5-3*R!DgGZ07c0qq5bZ=Hd}TVrRL>t}#MaOBK#CZF3NLq8I|LqLq4?jTrf`RY<^#et+&PZRM0p35!XJ*gNKy`5}+8sRY zI|I$+_s{G)&VbZt$eCZ`8R)$qi1rAJOU}UPlFQjh&Kb}xw>!&BIRkHPEYMD&A#w(0 zo@<{;hnxXVtlHTt-!rgwO#$r}Qdyk=+#1odKK(P0;3#m$sCEYE8F|sJ;jGXZ5R7I# zGv+=6T?*7^LG))pZRZ@?I~+Ye1rBbfr~7NCV3~FQ^xNzy2z|eC3Ok5BW2gW6X1`CH zdrpDi;rCPP`cp8_@)_+T4kVp|S+19-{~@Q~_UF;l-vR&niK#KFU@+QWyd8W3u=$>+s!k_>$He(`SoZ{slG>iaF5_$N6F~l-!Kvf<6VN8A zby~W63~c_YpuNVc9dHfK3ZRtAkd3Xqly<1MyQxAa) zcRkvVq%c1O>#4;j$I^$OM=STFkm(Ra;-sTp$(64Mfa6BgNon5!Sh);N@Cy&Xz|38= zH~G!>0Js_YotViT02yMBlTeleKsDrub|}A3?t{lyOi!3Q_d&_L-U(smKDb}3f%Yla z4fcToh3v_i;6C7dDsfUmvJVIlVYFLGJF*Aft#F-uD%=D8l`JPZclSWGJssM!)VQ(- zB3==nye8QL!BMy;#B;mAQ{m_sb}kdLcY(>n)#J&)U7+j!_xOX>E>LHmMf;aO4|af3 z(#PYCxBouX-yFBr?f{jOXUDLMsb#eT^!)pe*+q7M*~QM|GQu6;@U02$We&G&gS-0W z$JR01AeOM`xZG|V6bxje9ZhYbZSYh${T^7KvzjbfQ5WrT>dkKe%p1ky-Odfr z7IW>`IA#MZD2bz;PL|6Xz^?h?aqR9o$n)Ynt{zP9I&erke=H=n4l1>Y zjw#R9z$z{d+Vxz_TLUpcTSq@V*1%_hm7`dRH6S=QkM=&7U#x=9reBY$b5?=G`4305 zuB#yR$t$!2dbYm;Or%DRkjE>aYo+(7DQN|8R<)yjP#*3Tu**<$ zZ?rRd7`h1l^xGXJs4RlJAr?okh!(;5D@JI4)Gc)Z$d{-c^_ne!FO~{N!%Pd{F4ff| z*d_f@@)rza1&$6~{sM1V-lNfre*xVVJK8G^sQUwg-KdZB{QdwwcCw=>;XmNVM*_5C zO5QvVtTguzn{UhmW}MAKe6e}(t$PXWn+`Vr1_1&yhZk@B2J&;C4;4gygY$*&(C#U= z;TPy4e|p&9^9!Us9XgET`vn3(586XDFP{Sv8x4o*PIG{zuIg}}Z4MB+mZF_hxvW|6 z>qExjn$axyoRoBEets5AXvCoXREhAPV7&X@VT1fn@bYHx;iugn;H^La+ErEX`2qeE zIv?KS`2qIKZ4bStXTUj1bF{Z=tv>_guv&*UgfqZeR`rm4;5)dtC5LucqXoZ%XYL}0 z`m^7_HV6OVliY8B=ko=$&-#?$8%Wk+I5h5^2G8)R4wC|>0nq>{+HGa}G6j-FP7XYi zroiOi-2+dRDZpE{egJ!}_iMg_ak^gzDYjq1h1cH>%qYGBBxVxrylw`40jh`N2jje7 zKyBNT1Jh5R0lohq+JC)w?K9Y$X*pnAm;?cN^#|^GlVHK5@&I;W=?*@D#nIe@keW~6 zCP+VswfqE*uO*_r*pc>+fV}}6{BijR+TH&<7^M0L3^;G09a)U;2auZXap1%B0bJE{ zIv^T-4`vB%(7voO`+IQxKm7xo=kLIgxaNUV@H^18tc-SNrN-X^StrSZn&7tpkLAk2 zD~`9|_4~_ck5({f0^HJMJ#b~60D8Fe2l`Lm0RBD-v{NfV{|2mI!8;Hecn!Y(J=&jf zdkvnK?d-$7!LaQWXk}Q~r?zD(uY8VCFjn)eC$$AO-09ooUAzVRG9cvG~`Mf)7Qi_6*n+3^ez zUr$5(xOWc60H!-~U$<}!JPAVf-ztoO^TK!0ZtgmG3hEyC?#FRG1vqx@`|pQGfh~h0 z+S9#{GYU8pO!mK)JOQ!ldix8CPr%NZI@;M~z5f`@1k3CzusjB~A`<)5-H*WZf)Lu@ zeYrUTmL0hE+fznBC^O5xzR(Du`aru6yS!;`!$4D;cwZ4`7%bxB?iUmcf%L({J=p8@ zc{>Q!C06&QdYu$6!a?9#`xEW>n#&A;1&)t<3Gezr`YQ_cbl- z0}|)@_Y5Ta0L^H}-rR^|0i;@SPwjmxcPz2Uj&7BHN7aW9my z1#lQ~?mek)23Rs?v_tGO)>&+m;{G=WzNM0+29Hv)}=vt77j5#l!jof})bm(w1C z4}vSZha3-q+n;%~TihfwU8n&h`ww=1HdKReZ3SrmSZ25iWDBP32547-`+s70 zE#6fE&+_nH*hRiJR{@MzZ|{oxRsj8f|3u7emII>% z6lEYM!U*js2eCW=Ge>H>dnKiStXpCC%EeNk7q�UgT%yZf!h;IM{wcU!s` zsJnBZ-Q`n-BCzs}dY62p5a{NU?Y>qk1dSGiXph-ds{q8j+26T3o)1nEHg^Ve^TB^w z%V?*0T0aj&j?C=bew_Bi6 z*O^==3)ELV+!1@03H)5EcZf7Hfh5-hwD$VifS2*w}_$YKGg9AWZl7 zw%cL^pdp>vc5{dTjZZ(Lz3Mya;owN+<#v2G7Sx}OZW{_>f$P8!+Ob}t#DG87+P0r! z0chK8*f!ciKy-T*+PD7iV;E2s&EIC!2m^wv8QY$n_W?^o6573H%?Gs|J`}}lki=TRcMQLvP($rfFmZu?c|W#KxR^F z`^szxK(bWPes)A}FyNq(-oAP%82mROvR#yR3rr{Tqh0O$oF@;k z!3}87yB6^PC7UH%XS43$VN2c?k)}I%bRz@peDhPd0m8NDt?M^kfmkDEi~55L@bJHf z_P>X6ox%K)|5oXt6A-KS+>)?!0#QEBTd)i6$KeRn7R4&I<*DWRZ?4h_O?LALj>)Jld;->klz=!6#ugZoRw@_+>=(|ts4W{7e7g} z1bV+nw{})707C`-R*9~~zsc-m6L!am3CuzH-1_FIqZvplU)+@JGX=o)7uqAgeA5Jk z&P{ICzc2<-u`t}oC|x#Jf@@NsT%vsT;?;8b*PRwNhz3Aa|XU*06I4_baz zZVqPZfs=}oO|YyBjNS9lt~o=24xpJ&++5nw21r%(W{{RP*!IAnz4Od%O|bXp)~2YA zCWxx>-wZ3!0Ic4gXa`+TTOBwr+H58kT?f?lW}77&YT&uA0oq6ZlB)_#S5!7}msJ37 zquk~fMHO%wAcc0*OXrlp%XPlZBq=2@+;U-4C`J+V2eF|&b%b95yxykV6uT!6esz#; zW{=AOygT@4XFbG67FZwbZmjmmfVAHA4Q5gq@Gf)_?XO2xT?K)s-!>j^OM~&D$&GeZ zX>bMmb^~_V>%U0?DuU6C76D0+JUY1Hbw>iw$8@8;_9aSjpm?rfqsvwd%)F@FkgOI3 zaY-d;$Njp32soh1*!UE41q{AR++cnu3=%V=(Y||!yAV)iy0<~zBnSk*-r8W?7Xa*q z{%H4IDUKhoayf6SWmt~3q)2b(QZB44mAk7 zmACFMK@D1^GuCh1qyifUiD=J0VVMFXU@+_D{1o7i+P!r@4|1SK9E^7E>1N1)c(UjE zCJPy8H+EhRw>Srs>21;eeb-A8aI4T@-Hw<9usLb1x2h0>*F380u!|quK?n@%rPgOw z2>@rH$olbR0-soZaPH{ zl26ut{60arP50IyH=|>6j3iGju93zbA@56mt=$_qM0ni3quu?Rmk*Gc<+p2lw)==) z%ZoLU)IH>J$SB(5Z`<2JCQiH8a0GV{_s6Ykr}o8EpAoKYdXum%;ZVk!gjahT)T}AFKVAfU_R}kOEduZ36Rd*TjxfZb2e{Tu-@5FPB zvThMcf8>nz{>O`2rG@@nx5Mq#C}o>eFq?O=r@AvBER-{`4{4HS$eIU z`4{qPSpwe7XwX6Uco&g(y~Ttg>x=Mc90oR*l)dB7|bU(RT*k`hQ0D`aiF-WlthF5${%+ z20tOR+Aq=f2QHC+L~K3|tzMJ-fFu?4tRC6CM_xF$t-^N+a;x7W9;;QWH(pI3PufdY zk2c>R!lC)-dj%I2ULzbN$*ZHzuaN53F{_NxFA=#cEc%YY#H(>6;zG#k)s5%K)rEjn zL%Qe4Zj%@KzCpJ27?P=Aw>ld76uCuUv07O)ia5M5MBhEQ_v0~QYOS^!i2E3E;8Iv+ zyzmGK`6G?Khj7nj7_sm)lgU;a(MeSoCmTcYng)G(DI#92BkUcx2FNBiq5UsQ^b zhnE!5_aEMR7b4hhu@$SZ0wfG8xRREdk3{NRT!HUGFm>i49n(xJp3icSnM#@!&#&1C zUEq22y$Iwa6Dh~VS;?fxM2^M}mhCt*5U0$oW%!N+o^l$Zclpoq55rXC!}^cq8;&W6 zXYW_^eTk~DB&1dU^|EeaBI3>XY`Hu?0TKE+g1$T9)ftC;4DML|_&65nS8Q6|nTSCe zNovveD6|)&kgmeQWn?!JdF7G4?2Z?Stc#|i?^Nh8ha*;_5zCsqSfn^5YTg^9+7(zPq zeT>U}0m!EU;^p(h{s^Tf?sC}^Kg2@(XbHZXG5^vBA%4EPlriCr1ZDnR+I;VYEIQ7j z?`b^!;(?s*eq559c1H>xy;*Yk?uMu*KS$r$c>2=?8MrvGgg@tuByMyrZO%C%o&(M3 z`y2DW91u10ilyaW_Q-Ya;-&Imc8JMJ&Jui=gKy3T$%sl=+WBdXJT;D53i)A$5ODzX zy^i>43#6elXo>5qIYJZRx8yZxhC~{ApznB4yfr~m|5`8ky)s7lJ4~1EKQ}^NWA)MZ zJz9qi5M@@Cr7wN@$oaprOD&yx$gg%u^xcoU^*Ttu0pF5mr8d&XdSQvAL<@QLmlb^v z#3@Y!A&#J2VvJWuWQ<6cu;JH{|Jd=-cS5{_R1wbZ-NglO6(l-peUa5!896jrMBfj| zGEhWFR=+KNyRLwg_f0NN%E}|Uac|LgMP@I`A|t$`i(4!*Nb2U`Vh80l#BaD8eQ(5g zUkcH)YgiOqmP8B%sunwEBoL?l67(ICxlu8sHZx-}s#_HK>5{bgrA`F7EEa>lPm+@? zjC_4{ZxIh8glHB9FLK@#L>~DBpzoFhnD8Sr#4d|vs(c9clkH-R_+><_(j0xy#EbeO z(xa-q=!V0Kq*1Fa(yU!T?);EP-#LkT!G-uBqKi5`oXA~$fyI$34kUw(7k&R^6vKvW z_A)M-`m-WZ@zjgy)+|VjHQ6G37lluZ2{G9}T>xy1$jh<)g&1N6#58Af0lt^gG);>n zNY5|4eoBML6a82yZKg&JKYl^qQL%}jL`p(lEvWiYAkpe$3)5!g$UXWI^nDe+i)2Vr zNBhE;^XHKIsKy0_Z4zYCyas)Dh2;?u@;{>P{2j{gf8e+lS(1<@)U#-)WOdl=SI`@7&+N;6B%N|8UNAuJd|6 zF3zP)J$R)UmM2M?D!;ojOyf~J=&|hgT^{z=>c1(X{j#uFWnc=vO(D#riwrs~$WMQO zC^~$K+O!CqIC*W#s`xjczv(jQx70BffGPgDsppsHfw8+Mr%WAw0$&21LD$7Y@dvPb zxy{t)@o&JD7KRBK&(;W0(=5Nmcp00*dLGUktKv!>y?*19DnO+AvFcOuIz@<2) zsh^Y6z|!SqQ{7clz`K3FC*|*SOKwa6$6G&77G50(jIt*ugN}^>YpBDZ8`Jb_7|__% zKAF@p1nl@Mn_OKq2%HkufS$}+WIs@GjX#;@+6QP^u_t@C_5wJScc3#v=2ZiR}Ow=aWHyX3@S4=$OAVX|S;scv2TNIrFs{Kt8=bDR*gd(;ER>C&J`I zx(qn1gPOGPlmaf(p`ce2sZbBZ-1D70)KLpm1Yej;&8q>FtDFvI%r=J}mNqFLaH`MHvt1 zIHNi#Naq65tt&wf$KSOCn5_LdacCn4P4gMLn7Lq3p!l1vz-y#Xy7W8@So~Hs{Wx*3I@DyM$F<@eo z2K0YUZNCjzZeBK_`r#%}{QcKBvmhF9uKPYNcY(-J7NZ_2u@c3a-1hB=V z7xaRv-LC^vEwb@V>i@W;*EQotO-$fxga~wmoW1FQ^*;9aRb3i@S9&*Y(M1YSeOkvFtK{=I;evqoN__SS0T(;J)_b*h``Z5I;Ev`ba9Hr+||w zU1KgOCxLQe%h(}Lcfj>b1L!905x4?3mX(hkBDnyEdrHT?nmGf@iiEB%zAb`Fa zJLm2IupQIKI+pAK!KPHuS^5=v6!_a1KbEX#3s}FoJvP;F7>J1a5A>JP4_E_Ehbd#L z#}5Hz+PJYD$(F#0FYqzB%S8Td0mNrs9($d;A8@~ZaqND;K0wFU6ZD!WWxIjFwJu|1 zv^mf}Z9itZc^B}p(gt*#GMT1;4RiMxde;ts=Cfn$L)Uho#=;2not7+(fs`rjvBVK0 zz@SontmmE~@GrUxx=%Nz4FIK!i=$%?Hv#nr=0+DB^??^_XGY~7l=Tx`0H_)nz2>X~ zL}m1i9-mncq+Ra-ov4k@>wv#jb)%YJGy!+*%295z29PyV2KrH^AJzbObKZ}BNK^y# zqjN`tY*z!NSF=G^>e|0eW#^_Rqu&lF0l()HM-TQW0)1_9pf@EmT>-SlM~v>2Ed!>I zj8RLH0-)|r0v#%-@DDR?C2TYObagaD^*8gZz#sIf_MV?-`q0mg8vdMPe)n-7 z6+ijGOt*9b-KuRvvrLPxR-;4zePwFP_K%)3nPDpB?E*ck6Yx(=L)ezlrqv&rF0LC# z)$*p9!1i^ZbCvpef@wIsYINrAIP;EBVf5#oF{bjfUnBDQjVv>=8TS-CoNy`flgBGQ=Yrz(b(wNjbI zdw8H5_HqAXrslW&VMO^Orf*x$aN602%wl#1=!xm06PfAEN5i3u_n8L+?+=H>++%h) z+yR|2W>y^2OX>RX1B+PZzG>=kpdg01sR0lAV;Y?|ndXV1!{39WnI7bz;n*)Xm^Uu@ z4$ED#cEw1hiQ$>yTld15i7VWOKj~d(YEC$SURmQFCe!7u14<({A{o<`XBG-}fMgkToZm8tX$rhmBk1 z!i*fcG=y<+W_DDaALP}d)MHG(Cy4ce#@ZTg;Vn0 z%3OB0YA~+BkZDLRACx$4VV=Lt1--cQ7Mqx}d-4afU+FO~>*NgPZQjW2|C|)tC=m@Sr;v{#u2( zYGdf&Q3GYB|MH;0xACi(l^-sF9$gM$1+%H_^x(mDHZFYiwUFOd@hL*a)U|r}BhUff-!R)qgjF-b2ple5dKf{P& zuN*`eeqn4(UmDQ9`-#Deoga{Ucj3@!hTYYV15Ry|j7_J<2e=Ls40Y>4(7_XL9A)fL zZyoTC8fN$}Gz_H73^LM2t3V&mLDI+Y=W+*L?CWK8Wfu<=Kj~(`6Y@bf?FU_0<6tCX=@^$_UweL=Dr`J+1rOd5+B>dnRjng@y)kpctI@mn!pz{q~0IiTX3 z&+xvrdO*a@W9X9=LErCu*lWh{xrKhyfme(X`)~d4>|Zi|?fwM1fBkH z2hp$l2j3<#js;|be&7V;9wX^Ua{s*OE@Qwfp`X7cj$x-43%Y_=+ix?h7q0go-+znI zHc9L6xD(BY?j(TTp#HJ{7$zJ@f9>N4#`;%R`uBYM_lzRh4|E7MvY3oOsz-nPA3Ea& z^hAG!7mYE0@i^!cIx3PGqc&Fk_x*_sy4n8z#6mn{oBl4)Eqot@VXzlB_cyXojOU+p z`_t8sjHmrtpl2AwhBCT@tNKr?K^Pm}EA)R33SmGpe)Y+n!&53(87HDY_o)N~F}f*} zeYAqhjBwa6=pT~3{TQmJ+xwR1Tw;8&YwUCU?ZcSbSKB9d5&NHBU>K|~>pMK-$?#U< z^tn5nV`MJ81HHuP;nR$W{;a-t7N;0%o1XREk923e7d-|YMWm4{!#XFf4~lhW=%?Q7 z(-9nJtc#BTeZ>U7V~pb@QeQxh9fJYI^!3i!GHU!_pu70$t{hGvij&V((|_v#j^Gt#$7dfn#L z818yP(1)yyP+{~c7WHaLlo*x2^Ln*ZS1~HTz69OKefO6$6#G+pPq!*CTw0TQH|zYR zr`E=Uo@8IjZ~7hff4y~m3v}bRKreF3JiR%S0y>lRFTT^U35ec1!?X0D+abMwwtl6D zh6jTFge5@NAs!bLvQMbKfZa=W)y4as3f` z-jThaS84WWfbPG`xYw_>kAA_}px0irmmaLI13H%5V>;;-t5^4$NZRSzD;0Ztm$lIu zi%UK7x!hoC6Fv6RY|o)W8U4`s#~$9N2Krq8IOtxEU#X>+Ge$uhZzKY@K@idsFBUR(7Dz z`O`j`zHg63&w1QKdd^Pso@?n3=r-F;K({k}#eI6(CcU1<1Mzg6u6ED+;5fR!wmRr} zCRW_0Q`DCCBz(O|&sJXSb}@{me_T1&Eq6Zan2~h;pQ-ND*Wq-xUnAW{oniFpxjxYU zJYm70<7b+>KVGKMFMg`)K7NNn_nxlomb;*9M+o$!(UR^P>UetRP+@nT4VJ!tAP@9H zH^n3AJG)L~(~g=)0S4cgF+<(@kanb^F}9LOoQtlNjE9|1bU~1&im-YE$dPJG1%WstlJxss{eN-!_t#o1e zyRPD^hIB>Io34rQ&GakcEYMAb@$~3{Rgb$$x^(HwYZAN4<~Gpzwg0lC|L3WW?_Ecy zOC!2ePHEDajf}2A$Xa?*GYNE7-#%SU*XV$CWtOPWab3Y(XIho$(>(#8zgn)ml5RY7 zt}ABia{9=~$u1>Z1v+=!xl8V{8lo3zg&%FYc+tOTEng0FsXd#gt^T$f^jhnr-)W)+ zqpri_v$W%X^t%H7%+R_OHh_++$m|o%Q(3i3(cuHlLTzQ&Z|^DEPK~8b`CPqHD8PJ_iR+NlFl(1Rs!ZKtg| zTG44?*-BG#y0zISI`PU>G zQTtDa>{lW!b<@udxpS+kc8_MY`$LDd_FYW)^q6ILoA|MCXHEZksQaHkX{yaXpYs zOH5De=np2++;Sg*jxHC0r7a5Xbl70fw8fgJ4kR8)Ti<#e^mV^dptOWZLWdJQlr}eu z>Nv%`M#KMsfbK5+dJv7R<=^ol{4(vjfp-TG;ZF-PJqvogUXd4RXgjBlvytAkCnxMW zmPKBm4PLMYo!-dsvosdMyujky9oj-`R6BEGJ?-4c_4d}j zb+n4FG|(B&tXWH&RY$iQ2-eWv89>|Ji&oQan_mU};mR~6+D&)wcC7?OTJEK@?dzjg z&^|!j+vP6t5!7EQ>!w|MK+qqm<0I?#L+5`}C$lX;uXvU9Piln3q{tQ%#?J-g)ET#*ZBF^4)WS<&+tQv6 zQ{&+uK=&BK?594A9cY_`_fmyvU2Qs-x~VJkTR;yv>0mpxr>UxK)Tot;8Yyp^Qg5bi z{J{mCWUa{ts!+F}&8oGI$~Al4rX{SQHri%_e)7b_N~+tH$}XUa3<5xh znR+vqTHti9?Fafb)#KvHHdF6cR3)S{=riXVXHu&YZQ53-rc-4v545SxJfnW)?grgv zdu|H##;8#n{P|<*+`N92=mhMN2`tF>|`ifUE%40NQG zC!o~o4~eaZD?_QA<#$`RW?Z9+Hr@h#>2;Tbs5{-5t(%TqrbY#lTYGf;slUls(4D3= z`cQ4MueJK-dQlb1F1LQUd7e7lb`kWbZS6d$bBd>1zw4f+?%eF!dgYrtm2$`dbgKPd zx=@25maWs_PSoY$dt3MVI#PMbJ3+s?YqcFUqSm0*ZuAH>c0{MumuEwLzo-ei*6$IP zRFA!@TE93Rpi0~nT8B68r(U}Ht3~czPfN_HvZT)~OQ~km!u-jWYP>1+ea$fFU|%=b zMqRPg-h!AlqMp}nYFSgYg(|eD1AS~fMxQzj5wsjSzLEMWvZSS8gAO$!tq^px#XK!) zRLjejpm+`HyU#CL-d$0r{!~c?J#CVrDz)R-y_TtVB`VfGrbX+OB6S<}2Iy=@pIAm6 z$fve6ZTw3aufw-APc2fECy}7PJ$GxK^33o`%f^dylyyh_T4qhYQ!+1kwa8uWO3@dJ zPU49c;r&mPU-`#daDg8v^YuqTuX}D`oZ_Zr(NZHBr99qd-r|`!Oj+e<0y^IR=3giW z0KFEApFNasPqbSSE4nB$jymXjQ!lnry1y@PS=`z}QCat=+455(<--1-&2sm zyylD;4uuuPY7RZeqIhH#fPVPe{&$qN(ah!_8TpiomCu^*!SX0|+a80i`1H3|l>H%b z%{iQG%H61&%?3awMJYQ1^u~88KBt_XAT7JISz%EJVTD9;o0$s0G`rPR&1G;i$rcktG7Xx^B5o8olv2Gtt;l;YQ_p!Z&xtxmE3wbb~-M~$*~>q29%vMS}M`?p59178nQq~t%DXl&oO zg0fCD)cB}Ifs*v02lU}>O&7^CwvCNO9Sh`|klIFG)K9YDt{8OVHw@2`mk)6o+u~=) zXH^RuPageDEo_Is7A6|GdW{7q*3nDXQecdVlLyGF0O0`mG>)}UiQ(_2dJ958Qe{EtH( zTfL(()Qm;eur>mHdk*;>S#WQCBYsmp`8a=V<7jylUWWRtZCWJ+(1>;v*1nW-w4$$MBj1$W4Up&Xh0x!Yv>r1!GTv(aR(C|6dLaD(hM zn=M;*AdDlnOKOp_)1h#3&aY6Jyu;=FJcL~1>nHnU8%$nx z$4hpkD~NoB>mfTvx=il=a6-1I;ZMeGa*|oN$w};%N~uokwdfA%PIgDvRcPlS>^^Oa-*`U zOy2*BbG0WIBA28O25iaAPv@ncl*43=rdesVx-}WG;*<1ymL+-2azff^dw>i;hotzH zedGfvJyJ1j4_R5-CT;k;i~L)mQ5u`HldN{IR=Q%>4zevoEZr~MMvi$>Ce`uUO8(iv zkrqyEAxA7Ll&%UhAn&rwlghheEm^wc&eRvuQ#KpOeT^wnX8k&{g5pDIaG)mH(dM3X z*{nJ_9Tg+>xuHfjOur$$wn3H5Zx552zEUF7R@0;zHj3o)#|YB4+U4X^B$QO(r$7#V z4Uqv>p`(GDFC_I?H#PjSE+g&7)%_FE zxuooz%7#?;64K#eLBp~Z7U{EIX@h}Z5lMKys9|RK9qC={+Xe1CfQr3H9-EpB<12BHOTvJUsh+3Mn~^7NbWx;F!Ok)*JBwT8#FFw(+7rG}3u zAf!axvWEHUYoya}f7f$euaZnY{HV8-1d_Ix&eTJk0!Y>&)Ai>neE+RuwEmm@MN-v3 zf4#hC=YRM-snxfoemnatDJHq0KJ&mCQeb;keQ*9rl9zTxeci4TB$y|!9{J!Q>dQdrI7dgM(j5>EL+z3wtg z(toaZ>jAn2sW|#p{o`+YNlKE)dU;20e$5i>-R z!MD1QzE4EOpigxpXFd>%(Z-z7bC=IM0=f@))0~Xwz1AA zvY)6tTU#gZ29mCH5mjk|y7!IkL@uwS?v;HjF;1bV&g*Rx@w(I7I_@SJ@&2t>b)7Nw zL~(t3UEX{RQAaba?r>-oF~;jrU3iO_Xz=8I9dN9I*wlZg&LU4h%rcIyd$y5Jd;$%x z6GxR2^YiF+FTS#gqqD@iLjlFa!`7HOd9U#HfdZndD7en$X&!M&`Engs`3D`=UIFXNHn$ zo5wte&vxCbHFr5p)F8*y+Go2HGlVy4RadzYy;onajSF!m?((M9R*M~phA#-UJmX_T ztB)4j-&7*=|f^?b%ys#}i7m&ws5U(jG0VmG>ys z^OT8m7IQUSimQkd;WIS>msb!Mq|-G|SPI1524gk-Y)igr6;hgM8YKct25 z;OdQ(I|r%x;w>T!yI!rK zz7i4+KlZOFS>O|jroC$l-MNIbw&!X>Q#gb*cTd*H`E0SH?G?e1v9pF=okjTAU|ci1A%nm%++4FYbAF$gvV;#)o&NB6AZ4jRv&W$2;yRCbNQG1Vu?Rz075Kio`45snE6T0LxxfkPsxPZ+?m`HXz!%ls z?bis;i&LsIH(w>Bu6|f8?~Pu`^C$db$5eZNzeEU7kE&jA#D_3^?Rqsd;sW6|msWkV z>KwsSi&!1F#)EJahOYkNd5UmS2(7kGK0#pU1XmyKb0J940o8LxP6S7ZPc=N$fzV~( zS^e;}9U+l)s+#%v2m#&TQmt=cLqKhJsK%2H5#oR&)$-2i>EHVZmV5S9%Z~0L@T1MD zRl|1?AOqW~|CXB)4q9)i&Rt-R@3?ui>c3z%{>GS9Rr}*2{7NT_sv+4s{L6InDtS+K`;lC{caTw)KQ;${ zRiIyWIx8Fh4_~bM*_DAG1vIMs)L-Cz`&6qaj!*Hkwu)7!$tn1^sedJXIm!6A#RbXs zz9f9S|98m_jYNDg@3UmY@gDxqrYVUJDGm<szlz;-FwLsZy1e|Bu07QA5K9e1@BJb_np2fiS9dr|5V^F z*`VTzZ_xIU1RZq3H&M??f&(4!3%w^LhB0<{CkGeF!=fYj!mMMG%6@CSi|P?czVadb zBHB`N&f);Ry=AZDt=~R;tF@U#d}BBMN7^wi|7POrm5EM_aiG&J#_|3x9= z4yogl|BhGs_^-x8LWe55B9!r$8hR=>yi~+v4z^dS)i1~Aq%>CYX8z)oR@7B)U;hVp z8(vu{?*(rU_=%ghDXrv%f5(lzD5_M;{EGXjl3%%@>NCz9pHtaA^#K>%ol)tdHicVp z{Ap$Uo^f2(o8-#yvm-dTc4DO&eh_y7h^vfG?899dzgd}A)QwB@h^&li>%dKMn3Xzn zt+?Q=l*+3cnsExTxJt+&8Lr|7qEg-|enzUn71jh*Hb0Qyh7b5v3JOKIgHOFGLz;!S zH_B%#D`)sP7lM1`fI1ha*zZ(XXwJb+x!G4bxEJHT7TQ$ag1pBWY&lpNb0Z&zirG`? z{2~`O^ux5Wl%Ip6Uoozn>dMAhH5gR>yWqlYw9&03X}-X1$%T-^UB8pojw zip3jl;LOIl#UXnmaOIwDVu5QIjwzIhTLKw4zdg0$7ZfTkFjXwx8BfC9R27Jk*?3$l zwL~oMGH-50;(EQ_isPqYxJTkw;t~Z2j(i|PoVMW_j-H+-wl%+k%g{^~KXAB=n+Z=4 zzx4LQU7d*)6A>423xPMqzpi`XiewSuBM&@r5A2!ZL$5q=$@ygQ2kt3c#TJ~{S9SuY zaStKBG3gb z;$>GXaCtiR;@`NvIM>@Y;(|zXoZ{~T;w_0gag)eBVz&$v+)Tfzcvqn@&fuJ}xVpj+ zhY=Zw4Vw*c0KqUyhAP2TZ_9&TojQ^)o|>I zInk)43U0sOSCRVhRk%j!2hps@3fu$7anU`01suQ{6iq?@VDFgqh!%;zuw_r%L^a_* zu^ZMkiq6J<$0pva6(v0SiaoR_7Trz%jQxWZh@A62V5i4QM8)h$?4oaxXsCP)d$94X zNZ!8=Z5zO9aWh21{$4C+-&0ZBL>D$HJ6V)D(~c!?N)+v0Xu-xM#EEdrny@v>w?r5f zDc0=X$hDcGO5ZK57{GIn8lv*;Zv3A^>$Mv((H0gLTh zC%S`=$Bufdi|!F)u|T7;=q&j**4BN6sFo6qH5C7;koUen)55X7oY{(GI)Kf$_*C(S zPRE+%O;l`RP_T77hAZaiMC|?a-ijDH4jX3BQPD+1W8;&XDn_UXY}LB@ikB29c3Zrp z!h{@xeW_Yr5k$O-JsZuf@WKaTw=8E>ti<|bwZjT3P^e4TJ-=R8B*49~XmVDCyfeP~ z+F5K6=1E0R&}ppJ#|IS{e|PK@G`_;-qAPY{>~=-jc_*xD@QsQ;XB@B>2E!`mPuO8a z0kn!drz6;lJ%kDadu!~vOXvz$8%ykuc4)=!0~XlD3&9l)=6kU_TLLOfP0X>(a~CV@ zw(P|IkaGJT*g%amJ;U z%X{u-|CM2GQ4`8z@LWvrVr+Tl6%HmO{AM}*Y%wNoWn}qk`}dgMTg-Bw-T4^LHI(u| z{anoF`?zu=l^jgL24wluxh%}%l+f~yk#tOs;g#~b#%Gv;EWdIZKNWLymv{L{&SQ+Q z;B2|_!-p8ep_AoP5s4UEo^!dpBj0l|4&zyUxct-c7|f$HmgS{;Zemun?JalQcmtE< zXI37)A_C(vysiAkCjhe-wx!&zgN`{gv$4ETNWomAXqS)X5HXx3^>SGP4s$SCrJT$_ zW7^lOEbk0PV4fu{3Fl5iG4TcqLg|4JOm@~c;Z^;sn33I|h4OwqZ^{qTYBwT`Y`lnx zuIdx6V0&Q#&vpurrFmk4x|)U7|9N0;UTqM5fS$s%f2b1ro;iUzNvaV3cfbWRvBVR? zbdO`+++qt={@7!ZwB8FthHNp}skuU+(grhN@>1xLa|mPi?uD>F_5h~xNUCrLb{~cy zc_@^3^FLXdVVrvJ2%)+=Fc3(z@cA!e%)8leVM4DV#yE^2bSN{xa8<~{*U$7Yj3lg3 z7OsQ2YJ?CLT+zm0^FoBD95pf7HbKISt?HN+5?>)}`D)BfPcLEAuoA{%z(csUVkJfq z=`Qqou?({`?+MqqW_) z2?a$T&_|FzAa??a6(nd$Y@Z;#y8_*| zsZ(&WNPu3Q*DNTADM+hK z=zE&)1%&50=-%{P!7oZS+T-9$!BLM4^mOG5!4Z?^=v<#v!H>mM^rNYV0z}JWbPnUb zK<*R#s|TT-o<|D~dfh`yEg}Su&EnA4D;a{4zqipBFOmfhTcgpJK41lVbN)j|gdqg~ z0paLo%}_z&IRNdR6(k7UPDf8$`w1rI$>{g>UV>fq1ax}PS%KLzEV}f&yI>rLLjStu zEC_Idqpuho6WrSXL4SRBSRi*1%u0jMw|e#p?%xSO$79U|MgG2Mf#P;S;%*=GhLkOW zJxk}&5BKQ_Zb;9fk4m%!kDi`Jukl|i2t~W26=zihGe=#~+itBCSgmnFBRBsov*|sC z?k!pH8v*gd9I+F2ao>8Armk*%IcAcI^t&u{? zgxV9RG3eDY&E65z_=+C&l|Kn6s&6}=&W}eu zUTEaM0%B1k$#wk1qqkAs))KzWpD5I9hmfDfi$t+0Tt1I+9hIrW;wK+wqPXk={{96j z>X*+Oel(kex;mf5e?-Egz9m2BhaAA5@@!K0GcyR({q7{b)mtbkjd72E7!iVM-gJjA z_ckb_mr?A%aDKsaKNMscgP-kx5p^ts#J{NPg>rPp@+B?jP^bwwfA;PfRQc@?e)ox! zD0}lDe%MMk)R@$lKTzg`D#m&7|4_B9Ts*d8QYzY{&*Or=jY5X&$2?@U9#sl zT|S61Pe06msukxFJ0IvE) z1Jv&=>-pUVdZ=OXT7GQn2GlG}mH#_t9m;&IBHzS80~KHNm$&w(8cN^y7q2K+1=aNT zJ8%8fRj7ijFT8^~D^MjTr+I7Z{~|wp9p$|YUqrh6i(<%qku_64khHN@UT^9w@@%Y( z2RZu%dG0_hFMq{HB%@o*D`HI|Wf1}%2{wj2y|a|}U4Iz)y|IY5SK5yhQ}cN{!h4Wq zhOc?O`#X_C)tS6ABdy3ixMw`(gC=Cw#wR?evlQuE@qni>SBqSWi06^BtB}jJV|a4c zgtDp}84`M(w~oa}wy&l0kRhc=ObL+}sm(?n2*&WdM1@GhHE`Z2t^jGpzQ)^cn1`fX z3FIA-<{*bx`|_4Cvyo)h1zyz74CKKp9z03=Go-$nJ5TgqD$<4fb=Ul$dh|2b%S@1a~fv6L$SAz%lX@QfmTsSYuFZ^^Kb+*dA%NQGBylp zRH4mtvtl6I&}(@iLlk78zADfD4iQ;ey^_~)5QqFo`pezbk3zZ{|Kc9K2}jm9e&?>< z2SGB!zHlFP1|z-9r@4dSLCA~Uqug=R0A$py0j}I}F{64TFORiyAzRKPRUgQ>S0x_E z0moXd9_kcw;H#J$zwQK5`GtU6UgC`OKU>Ou7wCxW{#(QiP_#!z=I3*(ULQeT2z<@` z;$e+EyEcp4^8Fx^B6!9nJ>HM3!aU)&9^HdVh#0Qik147* zM7E4v=SnaJNTVb=H%Utm`PhZTH7eeKw4KLr;Xdn-DzD*O+`?Mqzy2iGGDQt(q#nd& z*{UE>LSOEWK1JjR-i!M+Y&r73?Ps~KxBNw%>2&8B34bGw-*M)816@DP{ zz8>bzJ^P9<%Ch9j-J00`X+(_LE-n$6Kmfw+T-{Bhh*Y8>mr**17&X=BKDpS3@abF6 zrOb69e%#mKYCUL2@Lg7O;rm+<1-})!;ZhkwTA;u^kElni5B*&_qEv&pr9W4?KeH0C zy=kWO=&=gKr|1u*t9r{21GeL(aTG3Madxm&?&Y-P6(NcP+e;JN-XT0UG?lI$$wTNh z)Rmq9UL(|QNJ<@aULtlLDKGt5kb%I?a!cXv&k-XztkRT`R7Cidccn4R#|XELxuu8J zKSUgE$}WALmw>o<`$cJ$b3Ed?LuzSm-yOudUk^(?NVgF0-rq0HSBpZ>5V56lrzhud z7~)P}M5$vF9nt!bS^5}4LAafzl)n8#KuoCMOCu7oh<74nspd`;A{&5|2A07Pl~z|v z5$8h@8ngbT2Pdy0qH}#pdCWkB3BnWq20r$(nsS7cp8O!m5#imkm6s>zO}j`imd z-sg{&UJpEjkg8jk%6*`HQLYHP=-s8+I!*{HN7K@-oMQ;TrLCoPM~)(1ml~AP8*C8U zD7vK+mk%Lo4y-HHnz2AUo>^1+JA5x9DNnidg{C=z3tv&XD%}*Z#&oH~)M7g#W^BGh zxxxrxk@2nM<+;s>RaZWjtQgWmtlTnHVt~~_?CBdRk-J29;xrH|e7i~p^w%Krbz4im z=BOZ|JESG$R;v)V9@dn2R4zxbyu>9>JpaPg*9%HA2Y$m7TT4oi$a%QqgQAkz`R{Op z3;897qQ1h7wO^N5Ykr1%wPu#gr%uD)KX_I`Hl2VU_IgtCzHkKod3{nzuH7KKp*_At z?jiM@?}DpeiYi&#-v-C(g_kUcHpBn)&`aKbmBLwRq!J@W9sEfkw&cvpYWQm-M2StD z7(O-`KD;05SAsSvg{SWFF7bTJf=7QoTk_qq5T5exWXT17KD?Lc zQi6BNg}Yfhl$@!11t0uLs~c*&jaDIJyMRVkw1LbTs6lw{UZE5U&Q&c)e9aHRmQoJaSrZux`dNp zd@{u;=d4~g3}Ua$k=<{H zom;blqps2dgY^7iuMU^Na&qR`RdaPPUFtWs1F9NU=<=B@ceV(Z%3z3CjDB&p3=#MHI$3l8)IL==I;yGN(x!9 zb5~2*#e^5Ic8g-R(L@^T=86LLDc>iskk;31%Z7(AY*rS#-#!uclKhJm2iO|jPOy};J?tSD z2UsV5CmUCI6z1r*jV;`A7}jO5g)O~v2=?^bMs~_i3)tNnZMJFfURdt4wQPcP7wjiV zl^ted3d5XIWV>Z_b`c(;*(BIDbeQ71Efz`yatx$kj#@Dlsn*D*+LaJDQ?k_-N zk5#aMg&$DnMm~!hGz(3hWwT1EK0}A=-m}PiK0q&J<*~j!n1KEXd&S!Gdju-In8A`e zYNL`~=z`i~R)BdI)N>+{_3(Zhw5$9sD}JsC8kc&T<>DuWqA536d_gUg>3N;?&A1B6 z*-d9n-4sEMR7k9+9|Ta&D2BDpg9l{_;Vjqp94IO^gmrj*F*KGM#QH>e2kpGz#|rGu zgPz;(&AMm%8alt`982!E?N`WvN~>I0FRna;E@e8fnkrJDev!5;fpIc)EYOODzVQH> zcGQB^J9-ZqslS`0;v5G}TG+vw%e)P3@7T&pUl|Q`Vi~a1uSG%!9_X@cL}Abz!aCNr ztqkZhPj!|woB|c^S7BKX5TF}0SF)}i#X^&2mWt(W-1m7XbaTP?Vt?-tsL8!A#WxDC zKm)MT#Ym0I(DJim#p_VM(DVBTi)l69P%W*V;^*7XL;udU6-P&SK=oQ1i_QB^LW7Iz zitk&yLAxJHidl(H&@gIwamwdo(6he0V*3+Ep=WK`#hDp4(6G(#i>v-vLc0|5isfG2 znRk1jdXn_wcdEOfe_y2)w+8QkYQ-iOvw6nQ^O(fqOY04x6`psCxu{Lh%ZF|k_f_gb zck10JE;CpU-MSQ397NKDx((Bc%j?%b(=VPjS3mN%GU5q%Z3F&JEQ&?6Zpdcu-NjcM+94)KO^eG7TOfYhjEjc|GKgUH z=3=3w4s!0BZgJqoYKT_Py5cf~7@{CjFYeslMuzx(%P1;6Mu0dEJT3Bz!$2&^9ZE1%Cl(tqZQ;8>vYjQ z%Y%^DS#Cu?fPIjj2gi#xNz5TfZrBwqSKkS#CD;_@cx{K=3_e(-k!A!ToZnkyJ!$~C zd)%zZaF-sW^T76^YTO3Mxow6;`#D;Wd2Rh7-z9a3RPlc_-S;=ue*nkv7K)P6GFoV8 zNoh#J<>I>cy6$xMbg!gA(NGB`qNuy~a<4mGTqRJ%U0*x4T{V3s~s;NkZbH-@`e^Ap=EKKZ?4EhfLJcyp+o z6$^h}aklz3>qgk)ir?eSEY#Nf73+eYv0T>Nt@!6JHq|t;eCAxO08XiAWlp_RaRhjW zHR*R*#h%l*Sk_@v#nQTKtP4HG6#}~}EM=>z;$g%^R@)P4MQu(w3v^FVakQ?4)qRy+ z@zvJIDl0!%u{yk%Wz^+Xcx9_u&txYn+H2*k)!g(7+$0Ihns=mv7c5{UWTsU7b04Fx z6|&;??W$<}na|R*m=)8uf;rSLAsgVbumg zD$X)fS)Q9CDqyN)mUSJV;@O)$tmGAe6$=*ZVo{cCtyqX;v5vWHtmryNXEn@TSCLpx zW&x*rS5!ChyhkK!cAtI4CPEnN z^?RF&T23&lseMAl><8OfKVSW_dQ9U4deobbb*Ogh%_)K7xYfV-IW1KljQ*6x_{9tCO zRo1nQBg_pdsrAC2A?7Tlz}tIXaaxOMpbWhPe(vBo=BGLv-?Rt2DpnQj1Bg~?{-Ra2l9q0}>1 zTDDprJ<>4mmTk2Db3Lc6mN5%2d0QK>BIdO#Ue>77Jf_R_#n!VG7nsGjT&;y~&oLQy z=2}rR@|ZF8PS#fc)66{&9IPI!EN1l+TkC3eI&;g5iPmq|)0o|_#>=z%4l--nzn4Fr zbAb8e{g?9gpnXiozE9v zSZ3<dnsgjuoVcKO84NanK@*UBl=fJ{%H%jFrqAxzC? zYdIYk$VBfbDYwb=XKoJHmnZ5sF(aaj$}c?jWuC#v%a43p%lt(am3uB+#gxZ$%l|p1 z*AhIKDM#|kjfIPt`mF47!bMl+^s^b|4`0t?DtSlCCrof=G8G5QN4;h;35MiyGsuCN zQL(#x*R8KD_T>2X~_Zg{t!RudfzuU0o!r$NH=Jp}WUoH7R**+3o z{w8!NuH`SNT*(@U%X9#i|MOG#n!4iRJp;-QKYSaf_Ssw>_W4bm<96Tjr%tcpOp$BK zmuz?ucLcqn+!y&Y?hxIhd`im0xZ-^a%Z1#AIGf`O%0E}$jpOAxm)pI#9fuJ*mUoU^ zkBcmxR(^a=b=UW&V3^S5jaVT}uZI#%{3*%CL}FGf(yz%wPNF{k!Q*R zM^SOlSf|RO9pQ2AX(!4&RzTwf=hDimffq(2bE$d;c8|IA++GdC?ToIp?wFD>Q>!k$ zlP6_tx-Ba`B@{BwwFygYi@A(>W1P~cit~)8^9oDhx6U%IZ_F!odzi~;jma+6y*kBM zy*H!uTXzP-oPV@*>X%~-is4}Co8N~Sp>@fn2d1Sm@ZGyh|9QZDi}x_xJs72Rs}dM> z!Q|3}O-zP{f-8L(L}OH>qe@3WB*usgR@#QdF<955O7lo)hC>^$^d}3>=o}9&U7ZAF z^to>@U3>(@@Ce*e+MEew6p%KQ#^i-CR;RBmJ;x4YjLBD)o)h~se%HPPi{ttDi^BYMv%rG@QspH4MNEIQYF z^yy7}OS)SP{o{`d78my$^k0k5Sq`~Z(|1JVT7>SG=#_g7qp6(XYTg=Kj$PfSn9rCDaq<nw}F2vZ$tJ(epFIEPHLz>9jRB`>*YdA^m`ILZ;FfMM;nfQdi@*= z>m{0gkvP*LY=YD0ow2u^djO>yFWOju_dxXIcM~kPZUX7MW{#KqtqP&@w|_60WDTT` zBz!5UGy2oB1)oabMVsi6cR!T;bEZo;Yw7VzJ4!P1z3H{E*Cq2$E~CTKUzF@mTS}i@ z@}%T^@4s|8-D0AuA+iFVE(X;4IyRMfQ!87QOMO7uDkZJT=4HYGj zEjIM7pO%uEH52IptBfV%OMlbu;I$<`=l!H*+79Z)x)?PnJMx-_SPqq?fQRy`-I4kX90Acut!MPA%z{JfYPe zPbvWyJfKyUC6=UQ)YG25|9^?ue}}egKE1>#?iS4$MJhRkzDA>^V@s}uSJ5C=WXa_% zm9$+w(Ix*}?Vk(Gv>h;DN$@m1ZS-VtNz~6GT1Qnt$$~xwZT!>b65~q=4eYt0WJ0}w z_6WPS#N{%FmR+#2 zC*LE}zTo@K&&u(%R8F@!UWTEqe(=_OBNsuNWAn!R`am>o{f-uMH93lwaj3~m0)^8i zmp?S$-3Xvv>902rE!;sX^15SwYqyPdi+t0}8Qw&55>=ZWT77BUXBW-?9P#iHZ`vl1 z*=)~WMnj&`nc3+}X_}jAb31Dx&HI)b3d*KD3kd$^x#CM=po8?Y3bFWbzZ z?f95yemO9ec4x(D^R;JFXz6j8W@hySTB7Qhxk))r&2K+so}BZ8+TnJ<{B!pRH6FLu zY()%FJp>8ne}4J?g&(LJovG%-le(y9-~@AMZwGbud5rmKV=MLXBe>bCtc7}O2GktD zeMaqqM4IOxeoWndHq?BX&`7Oo++lVLs-xyOY%_;?)Kb&Ho6PHNZc>%`>&>0L)zq=Z z)n?57OVr%yE6jyvD>Vx0VLn%2p#~Q$H2-tcTj0gidrouA9vjtE3}U9)caEIu#N7#+9H-_Qx=dkT4^tO^>M%`cN}=|zZ#89MWZDaVFL9c;W|QooC(E}KO;iNc zZl%stzCM&1vR7?Nm>xtetCX3#d$&;$zl5e`wVSEl0Iq43d;`_*OrdGy@H*;&CwZom z$W_#y`KL|)ocKXI59&_cG1L9dh15fz51A6Lx=^ofIbeFqolD)2vDY-dXBM@+KEX5) zK7)E=7Sp6$JdN6frAUP{JD{ zO@G!6Q8;tMOwP6gl)2O()8Lz4N~3X`>7P&kBO>#?D6+{Juq|q)YcH=~rD$`}6NnTI}YUwo+>-aVRI#9lsltWhw{LoN3h* zw?SKzciTluc)%pnl=5p5cdU9F}3O8#tI{6|SybF1Ij z^h8Rz;Mik~DiTswkvfgJsa(nr(;H)6#CgiEu@)oT=!cwaUmAMd3cNV6Kl6uT&}#uDSt zy(|jF-C#VhgHF-x(HJXckSU99DvVWcaFhp55@VJLO(~`GjkD6=l)B0bMrI_G;%s-$ zcw!!i!o}qp$z5TTDDz3@x*ot5|L&UL$*@%+EinKiyvkE&m?0+j}K)K zvfFsqx|;G<8E>3+VgAoH6B{E2a7i%J|^_6TLDb#`y8@ zY|48n*!U>akrMeO+<3^*p3)fsF!sE(p_Ix3jjlx#Ddk_c8lCt2Cij8-j88ZJBx965 zM)ZVH^7n76jEaUK@+0VSqlG;{ex+Gz%p!asyNhPHS&0(UkujxM75I1h<6Wt@TuYWg`QftU%^S&Aa zR@@*@N*Xlef4V}>Yv?nmD=v~FJi86)N6N|m$KM(j2bGX%Ev<%}DF*U&-xfnfgN7V^ zw#iUjpd`=jeP|#frQ}(F2E&{ALNY*h$FTSfhphi`)38!mNDf0?HGF5}ljoFOGUTtw zA-hhu8oK+l$mpFV1{+H{`R*OPp+6~&oVZkD;B7oe4o_DYY`-OwF|A@lVAUS7WGmm` zpO!$L$G>104`7n-eLZV9^_xmI!*dN!ZxG4%N>3WPPhiRO98VZ-1f$5(-Dw8W#29jH zW2&L%Hkcf-D%tQUGlIPP%x*(_NGQ4PL%e}IF^G(fWEh-oZzC_%lMTp>&19FUcmpA5 z0~xdvZSelHmRwdJW4M0Jn+*1b80H^cMt0AOFl_c;O7{E+Ft~qrCsQCh4E2=@$WKfB z4gUM*kPpw?WJvaLBBPVn8}<%3kmH}NHf%81kxMtNFkEF$Ca)2C7#uwQk~+o~8kV$= zk?Ke;hH=q1QqQe9208i*$=}P#U^8owRGZ^q*!ZB2l=acpup+0MbPzVl&>7N6QdRuc z)5hPBCNB7?*Ijx^5*!=RS0p_r(K|ouvsXPKF~UFU7j`w0#HJqoFRr;DoQqt4em3nQqkW`RXs*m2zC1t!b>aTw(BKj87bW?ujL2j^`5h!pxs|6s(w9uqdY{(2$@h?s zaWeHM5ecNc-^cV;TPEpY{9(PWno0_9I-sZTC6c~v->2_diY2w`cInr?K$5=AX6XZR zVWh}(n%*e@OnTf$)SEwrlg^>BdPgOIlyMuW--6gdGOmT`mrvP7vKL3`TQ6=RDQ&~` zvGKm7-3LPS;st9-d*5!?7d5OT6+^e`_osQ0=3L#VpSF4l>B>qUJ+sw~#Nn^fpUIz3 z(o9*d-yh&i`nZ3o-t(g)DWTI{FBaRA++!B#TR^rX+ndh%H$Ntlmam(s*Xe!}kIC%y zTQNV0Q)k%f&rca8HXfU(FSQO4?+lFVc+>&nSK<#{h~oz$?%`Km<<yMS{MEBK1?vPP;I7Lnr#1-onEfN!-yj1D(>v+ToC)woq5?a*lX=Ggo)4 zCYSi!RH(B_JVjizG+&2u&LGP9r*(-}j}p<-vviS+LqtHWFY(si z6kR@U7ZKjQPj_kpi|9g3)B$xg;{0bU-2*6z2#uoaTt~3Ps@o*pdNGPf@W<(91ji8l z%2B$qZZI*_J4WZ0A3@AhfpyUJp+q~^2p#an4&qfdKxdP-ji`0lp*y>1GqLWJzpk~$ zm$>+kpKge?mS{P&UiZM>o0u}ZT9;(;A|@rS(6z#s5R1A!bTdZXh%=~*bhg6zM9XUz z-Mwwj#M9`xy684XBJYWlPI|(g_!>N2XI*MbjIFcN71mB9+J{co`7wVJMsEBmR@(j~ z%ncYTZqkhq_FNt1Q)CG@JE78gf8B&=QXuvpz&PcX^ri~k=L3Dkvmiif;z z5x~-$#i6xV347hH7L#a~3H9Pj#XJ652{>14aj(=uSSl_lj@@P?EOGt+7;e!LFk(&d zxfB)Qj;pd5HA_a=DUlSvD-jaH+y%v3qPT=u8M_$OQ%F!PDk%2P$|raz&lGnr%pts9 znq7>&l0~>*lu^tB^IYIClEgFz!qP>i6Km`MHb(|A_#~GSTSc9N_f>6 zRlF(>L=eP;7w38a31?q~6kDo;30Lre#Zts}!os&(i{brS2v?YX#g8&K67oO#6g#{4 z5ctWfi`z?Xl1ubnly3!iwTL(AZI;E9u4wa2|%@!98^ zwUlek_@4Pq+G(&Re7gFf_GsrreDvA|?ZpEPcy!er?PZ(0cwXo&ZKmKB-r@08?QHLB z_-g!R?e6N!cx8`OTL7-W-`H=_9)4rN&-rW6uHIwBtMav4?QbofwLqoqJ*UDmv{LQx zLK$ALL8!e`BE(O*#nF-jxp+OaP<#79A^ucro_2tcj~67I)^_xt#=rlbsTCi|!m~~v z*Djozj$b&%Y$oe+Di{U&>S z(_0&@<+=?%HFcuaHGCpI#{Rbk_Glc(Q2fw9Fh6h>zY)#s_OCeK`=2!`=4adh<)h}u zKtJy7Xpd%oN)K-O*>{@1W1YApk9JL2W*ct$l~)??sjqNvVJ|eh3ZCOW^*qs}&Uu2{ zkp4guA#TK#&aKzHUtEWaE2-5)Xlrl?;7v`+svEe&ZPl8D(kr;;)JvKbeiw0j9IYBl zRT*x(u0->DyBQZ6Y|zZTt;1!#(rCVg72(GAD>ce`InFd)s+kQD<2c0v4fHV&R~gLF z#2_x<99s)C3tybYDO2+_*4SL!E~nEPr`IQOdrX;{&BPNpefV+B^7b^G+q=V>cFMv3 z<&6{#r8604c1hA0=zDMt7ZWwt-tWXMLd0u?ad9~FAYHS)n}R!#Pu3Wj1l<0Wc+J~x z49;*Dt?6JQa4rnEM%N9+)l7hDwlYDuB6*~S-4%wrzCBEHkr9k@Y7NpT-v!{rM*=ix z+7=vn!4}Q4jtw~ckn*n`_H1~m0z)O8KXssKA*8xkKv*;V?TD=-GL&+vL5VM{D-2iicaiT z`>rCAYa4c%rK9LP_a*i`ytU}8<8!RvXmb%F_c7K<)Kt_tu@Sp0@c*2|(Rvqd+KXJMT~sG>EyBCtfim?Bgg0K23EToe(r1G_LUqG(dBKNhtqv?yoOCT#879YxK$_1N8K zw-tSMS%ZzKp)-p%o%|D<^vk~J$Csb6^#!(ApUUq-fW5ENl-j{x=yGnawS7wmHMdz~& z%cAb9zcDYyzW#MrjcF>2Z78{|&e&m&{X)5}K48?vqGn%F`_3zh9lBGguF90h-aS;N zw*MrGeYVQ1UWVnxy0`1p_O<6@7Sq4`K`&b$Kkcu;CAqw$P-ry(i!a7MOTHhXt$-KI>n>}Y%}?Bg+Yd>1`-mg=y2 z3_^~b5u2jMUc|+Q&PY;cEJVjzYZKM`vtwcjY4K{GPvF=cz6|w6R7C9mzjkWdYk=5t z1zx?xb4P4QEJkgU=O61Z6QRC166k+{0`I_o`GCw=rE)->cf@T*utM*RJYHt-|!3dab(HT!9GDaEu*Y*Jko z7%|#g4^_S2wV09<4XXFCD$LN1yDI%)pKh75^P9o#$*lR7(G^`~$a z=I+Z7RZQP>3|tYY+6$P9na}c9#Y!e)=C9qPvLE?_hL5aQoq>#@>#nX*HEBlC2T!h4 z^^OmrX<#qaJ=6d?+j)s9+1!inYIRffOn#3}*UVR~Ahe?qdz@7ptgq0t%`;WgroBL$ z{@SaIlqYDP23ytqOO5DH>`5xv^g478@sAQtuR*)67*j5;x{f|GJgTgkaRt5M+OTpV zqY^zg=aUjrRf_gQ^eMwLrqb4uOvF!YY6xyr7CLFjhXDdph3ZRqO# z8OoY@o6%20|G%ta`Jz4M9#%fOxCUL?b3kchvl4xW$^i{=pkrOy>`D8>$D0K z_3bwWU{H*jbLES|V+$WOg*~Wvbm9WaC$V1vtUrt5h4m=TIOU=?FM6jCVo#!G|7cSj zP^P0+HN8@}emH_UZhoOS=aY(>p7T`k;9wG}nf6f8ay=2%y1hYRnG%n3TX0tq1E!+{ zUvDXHULc`hkFP0ywqQ{qrYgmRMJUw1oJvI#1BQCVC{rXGqEP9`Q{L0y}kqd1IlLsfpvQnZTZp?dG9E9~25q0q)Oh0T%~sJ~|pDjw3OqPi3ID`?uu zDBGyLirc+^kc?Hk6ra4ukiYC%itfZwto zTgmT`2a@56OV&1IG7_pd{PiW$xCx}N^?Qz7ya1@6raVSI84FgNuDp-D-nLzFWaKWg z`_@*4zu#>nNaLrtbKn}XFK4~Nz2Y+RZsHn6@E0rc4Q!>t*Vlsd@$*s)?lT~-FIb{D zWYHjVf4eCj4k(ZX@8&CpR!NXg>YNqrJNd}yl9>uo@dczE$3d~Q>n!s3VLL_Y(p=;^ z%47wPd=e=E{*`A*(ve|ne#y7LJc3;5{9Rr%Clv`A`y!tMPeN)t2jv^jB_ek;^vf4F zu#mIMd*m%s=tvLIJ2^3!gxs6iE-yKXMSe?oEpNPpL{=l3?7i3RDazCDzi?97goPT*%-uLwfqTz0?+-CI%BCz6=e314TF{sRtYlQuX z*9FJqD;{?vCLcd6KWNj5*qN9jX9v7NOv5M1k0!SudLwtsH|UxW6SnS@UwrcrfmsnJ zpEA1v@nIfSzBJ+v;*u>aq1j$=J$PmhN0rIu(BE;DfTjUTJ7jZFpqkL;tA;K-rM?PGc zhq#7WEkD$ojSz!Y$nU#kA}Y6g%KO2`5Dx1X%Ug~gLdZSchX^0BmuI9<5O#gG^6gqYVoLiY`P~<2#ExfwWbU?bL}mS$EO;{n z5r5;G%$F5`z*K&b4ezp`KUd}J%4P|zd$<>`k=DtIRwMED>IvfE{) znX3?e$6m_<%a$Qdq%_M!?Mo2I-A%HZ>Fx+d+#^}lw)u!s;(giCowE`C=zFs1{27Qp z&>GpU+Np?%5jSM~p~;Bg;A&an!oTpV{+DE!s4@6~jaFIz!BP0mwH6t;Xb3J|@qb+Z z@kjVnk7C)uUp;WEyIK~!;vHN(UoLAww83x87R$D$zl1M#GkrhT4!H4@3WP(F-`075UY>!d|SNGCnP7Pc*riUcU7%qf|cjII? zUGm`vy3n%5kkjzC_i&juArqec9x8)eI0oPO9we)&Is`xS9w@VUyC2^BK14RxZZABm zD^NDFHUW<7_LnJ9aqzu8n`Ev>De#-UzB0NB4~O=xl^w1_!(Bdl%ZQ(1;7dO(lg)63 zz*(P{%Fb?$fcO1B3cMl#;QA34*+^C(T=RXdtWCES-ZnN%#(l66j`}l0<}$nvZa2wZ zmN<76{JV{8@GZ_`(%YJOaQ6k@q^|X|;DHOjNP|C4 zhf6&MrJEe5!ndyMmwsPA89r-Wk2DwgCuW7;J84hq&zPgz+NI9Ikr;=N*U}l)pJQG{ zG)tRX`(wJIo1}YwcgL*3Jd!po>WnET-Iv+~zlk}(yeGA#wZt6QQzLzm*%VWjdPBNj z{V--#dbPB@raq?g^d;&1_q8!E3a!$`lW)e@i7e7lkLs9%YNJ#PxESMUE|yNGm&HuK zq?ST6O)(p9$)!YPag5-;Sn7XM732ScFYRiR#>{`qmXgN>F@7Hlq{XhBm~-Fqq}R6= z#CT20k*Y9fVt&jxDMh86im`V+A$@V-L=0~EQR%YMw3zMh5&#(Y%7O8qU- zF-i+kDrx}5aIV9obzNaGwGY73JAZ>>eBVS!3taBEyNVusfENmVkBn8$(ZrJ#tcNSkybug5ED*aDIMu^j%iQ!l1`dD zGp6F?5^0B2x8&QGHduJ*Pf7Q*SFqc$qY}-M=diTh!xG;u zk73D~pCsp?_hH5SKFMXqUDyJ1x1{{YEm-~S&i`ZeS7Dc0+9XceOR#sJUP%sCm&3qQ znkA;kX4qHPCP`_R4))UbktFk{8a5VrU*h2?hY_gvBpeSBZ0t~tq-ir3)?9c)@;0gv zHl(YTTqozjB5z%iB<#`GM*4`uuHy?yKd+8+WZYIN&fkl$; zr@LW^u?oqqu6S5VvP5$88y$8nUm$rul?)3h=17`daj+@33njueD45Nge2MoC7%c32 zj^qq13U+(;DM=L-2s^qiLvkrO7?u)sOmZqK0A^wxmMr0HhAlanA~{>+3wx$WlGIhK zf!(>bTk^Da1?=mqof6|S4;b}(oCNWHAOgN#ZnV4$K{nlPsS#6PCFT zEpb?45A!O3OKz>Rf!UToC82>6V9OtXBz*9%=#w9Tk}BM{=*12Ii7|dS`sb=0lEl=3 z=vm-xl3!W9(K{12OYrC4MUUrikerdVML#yLljIm*M!$WyN`k)pEZXPua>o6)Zi&X=4Rsg9Q_&lj^@&FgoQT#&b&Ijb)1om+o#L~nQ=`N9ZQ{bhr0C>puf%j= zVszWP7h)R~D>`RdllYK<7QJu%Bk`4TVl*%IzWDx?*yvyB_r#{#h-i6njhNT~jm~&< zL)`WxGFtVmTD0Qt|kJUo=N#66b&Qi5{rYiTi)9 ziaz}Zc$=f&&YXGHsc zJS*O@bZT_^yfb3A<&&fB0ome)Rezu__GF5~eSSjQMaRXQjU&)y_l}6mwtR+~zod#~ z0sYYA#rwthpl)aiWUsgv@D_UM$S!eMcq?>^jwMb8HABBYr;GPOo_f4EB zene(KpZPh6(@A7#>P|cH9|8^eDoU5RcIrEGMD9zFX=w93a3I^)iLQQ4|#(Dq;VM0U%kKnFM0 ziqvqE)s%kfUeJBEJcp z5MZrdG;^#K0{yKKUH#e&;cZcgwtRXDao;Z!o$7f2d2bepR2_AY54}85;maDxT2Hnp z`ssB@Ik`a8)=&jW5$A~lYbqcIn@@}OR$CyKXP*@9vl<{V^$ z?Q_9FI<|(2q8(8X&XFL|pGh!CPIZ9j#CH(n>aQ)Lrys*0>jM2mBOO7IxBowm?tQim z(sXN$$XvGxGI_GM2yk^hBn7xkWU#D;c;zk?b*h#_oEsO4`nXFW07q9*ZH_yn96nF9 zH*G$I!kaDX-#r@wdF3eDLYV|uUb*#(&@e0nPtUq2 zmQU0VGj$yoOu>uTlE?6W|~nLpg#q6F&7IHc_+ZzzpI6NveLkEfI=9&FBKeI zAQ5&ElE5CX1wwpeA~6sw!7HYp5z>BOz>&CY;oy5X z*if7)gg%CVK_kb7>D3Y7Re&^Mh86&hI)6}zJRb-)w(l4IOxp^MTDwn}#M}s8bu3X> z1zQJ>YK#{)`Fn#6u5rQ}o?c+kE~@b8jK$!U)kLBFcNg&glesYQ?HsTUj~2=rW`e^_ zaG}a-4_-bF6&{ku_#X8w$`cSIoDeu11>gn<2fYTO zR6SdSrPF((g8lu3AtRkpi_fkXYFpn#1$C?uzOHGBl5g-9zB4pM1)g3eyn6m&)WX+G zh4F{#qqeVGB-xEDU$5j0(t{DRlT|iIOxs2-U5I zsDL$7g$}nhQEpjNgur4&)b^JXgou1`lyu#1!TKa#RABZ`K_}{b)S@?|0)~HnRM5sR zf~tk5qm+4rg7%4-QGj>-f|l;1QJ&j+1?q-_Q9$;4!H$yTC|!Stpyd4SC{XAd!Qg@T zs5R1;f{C&8DA?$8L61Kv${PJtAa}<`q4f_1EB+#){3qQPWOYKLh{St>vf9X~+m~tt zW!lgv=B%57tehQDQM<1SmM8c}?W?;ikVW}LJ@=>-^sM%YN=q*jOq{VQiu&3t82scF zm9yC(D0#Fv>JwWl2r6}r;(k^MiVEjO9fQaPulG4cX$)e)JD5Y%bUT6Ix{qzt#W;>2 zapuG*c}=09fAANme#u$E_DA198&2d3XeGm-H*Kc`v1bQBb=xxqOA~uRUnIu`*Ff(; zdfv(z}{KUT*sY|CgUY?4yYSH)TC2$f<%2Td#l~|0N1G&aDKUpy32lzgR#?wP-=(h2u=m@K%dG&1(9y&LG(Gnf{t%_p!tWl3nH7cK{MWL6`U%`0EGr`60mcR zf~qyXf&+|$pyX-m1S@tVgLds*C9o{m4JvxJTwwQ=1#{!D`lhzt6} z=Vip}1U-9m3WboU&{2P~BBMTul{FUdLBNtz} z!DrH+Mh-2z%1_<$AaWAtG9Nd+E)qSVl0UQac4Xh4GQQ~Iwa6Q-X8!1z%aPAO2L3X# zHF8yzmcMdCNo37(HUF=TK2pMy^YyRPk(E;<{ADGw$eAeueoBTg()6Cg7a%#2xybYU zg5?E~+S;@H*q^zPQ~b{GM;cE?YBbsWIC*+x_S`JKF6l_5?sPi;1|TKU{zn>LKWATL zX~H2svnL^v+j@XMdO0q#8k)q%ouNc}+}h1QkH<$gZb;xuR-+>;wM_nzaad%>0y=-y z!>CB`Su(#=28{gq7tf!%H#oBQKrDabj)2JdACUYFj+-NMi7|Ye_VtnePa%9$$?C|p z;UK=(@#T@Ut3ZA-WNBo}dH|p8<{o*jcnAM<|Gdc4?g4!0m06KD*<1J@a;8W6PxIr) zV(cPEPps#Qye36{`L>2%`ei)Acds{JbnAOWS@$wNrr=9NGRcGAL--Vt@?sG`%KJma zWvClJ>)X4C?f2&M3u@aUCI!vm?>YZ6!oJFhzl8KG0_i)0uk(Hs(Po^+pZKjl!r*1g z_o=CkxFny%_bs>)F~#LC&lZ0rg3I~ED_vF@!F2q=TQh8lICN%&cl??mqH)SFPo1NQ zpk;jGi4ls3t>b;X_=Vz#n8Q6hyARw5!^k_{QEOoYFu8+Qb1W}n>0m3bJv=)iDDfrl zp;JbL;=^;^h1Y2j!K|mem73HD&#s3&&Yq-*2>N~Av(1SS=C}8FJ%5=INJ=g5VLdfs zd;3jZ?gc^wi*$`QACHM>dQ-(q^MFU3AYSB^_k$z$zA5KjvxY|~h!&nCEhJ)An~@g{ z*dB3*q~pDqwk6_9dlAp~sc*y(MaiQI*F+?AN_h;*iU?1Jh!?QjBVtiEkJmfk9zl#} z^WrP!N3`}8@T!l@j*#rm=lu_XN60_t@H%X!M!eg9idWh=DI)$`1`l=Nceqd5ao$7B zkMOO3j__RFzlNX8I>-y?{1iUZ?f}oX_(OPG{yyHXUGKv`Iql|&eA>f<_&a$HBQL|7 z+?YH>)w6KDipJY>>{0m56=WVUxFLML1(A6~kO_oX;3e3^MUZ{^O^aOq}G-bU}F zaMbO^yxIM`!lNPXyn9AwcwWl_UUVWgd@5ru&$OBlUOzaC*Y*(|em~8T_udo}?r7)0 zyO9VE=W^_Ldsc^s6PHZked!MlXO&FgMHvIa%eVdJ9!}UC9#sF6o3_$7d?w}_7v8%% zd}-Gg?r-h#@YMaExyR#{hC56g;5K=xxaKFW02X3!3au;}30e|ClT*r1R@b6#|_qDJD7~8_bGd60P6BVN%jTwf zqyuB`W^y^Lhk+Z3>D(Od0U-Qq8W#rL3oOq&#QkKG07QADaH%&KK>z9_uKpkyNJZ@7 z-dl$Q-tSM~R`no(2T!uN8S-c#)1ARxhyell7b)EHGs1w=U_@@qogKiNAF$k!qyE6l zS!iz020!4iJA!NJTL;{GIhqSrdIQ%Yz})K?FQCt-2=0^_i-8An!?;UpU4UbrAzbGp zbAYus1G%m1W&$4*ws8-4O#?3cv6=f(GzD0~-N@Yl`x}+ zta}_Lzcq{7fxjPSPj%!X9q)!+`D@RW-M$%SQrK~?r&Nb^1Wn;uS6mFkyq&;3{<<`5 zX6A3s!gIzj2ahohCrBF>Rr`(8F{}t{jQh%&pb>`^+75BPqj_O`{Q&2V-TAPNs6I~o zmAtUTPu-l3UD;vV&cEZVb6Ma|JKa|>H?LcuXTn;Vv}LdrRn=@d5lSjh47aR{qD%;Q{nV-xmbDVsAV zZ$g-NV*w|8%dgPeDft{|*J!9@Q7&iog`v=@`cs^az>lE|4rFq6_IHO~U6{_P=f4eA z)u(a(09r%uA2`IZ|NJ6!)8Z7)C-IZeuKP(GZFpm7^T9nFzb|(~?LBvKM6z3~i=k2VuIc_35h-;+4bq7iNAU0)36j9eM|xC6myh?Io7 z7r;1gzwkm$+aa8X((|F|A0s&z!t+D9VjySLP6GU(4ntR zcyYGp#DqTeUCNp60}h?uwUATM3=GZZyK;QfgF_*p`JC)!0ip15XHMyZO`)PvCr;Uc z^`Tyj8Jrx~)uCVK*>g7CUKTo~(Uwykza$iQVlrp0qg&|k#tEE=%DJHrK8&+t@J^v0 zWk1OS_OfFZ#0cin88 zxBUQj(K~kSscrx&rh|?3ehYYF_l8~j@HOE4&6jMO{VxFQLofbMY(D|K@@Zl_R^JEE zKRjYTC*1}3s2bV(C*A@C;p^EwnrZ;s`7YZx@*=?d;cYhZV<}*A&J8xWzzA3xa+U4o zs|95Jy3D@)OaWMasgfOZPz-QPE@yKV@BrJ^SlBnJ3jz9GBl{LH4}dSyu|YxW^T<8K?FE8sGx^(eq&+Z;A95(e0L_avM60R#v;mB9w(h5;C%$Jvf6g8+4t(%8m2 zf54uagY1RzegJIN0d~Bt58yN)iJhzU27I5ihn*Sb1u)kpuw&jY0%%XM*xxf<0G&Vv zJ9Wt%0L_ldZoJ_L@M<8kzZ0hcR_Ei`zs4p54ni^PX5pU@8z&_D%;ujVEln`C^YgDE z13U;jC3!F;90y{X9s5GwyN9!{ncj!oc?)0{MYe~0&;+q*-7iC861M;Uoo6BAYyH{G zMUO%TzHDL}s_R1*S8ZV5#nguIkNdE%e7PP14_(7PRZtZIo94}4zN#YR!sBIZ<=v8y z`Fs!dFjXJYNnFf!9ao2Z_H<{v31lI`9~ZE{`U*o{Sm(0U57;4=wApO$_;VqRfSK&v ziMb(b9Hz5xNU}nnJe$gH+;lvoN@~L{|Bsw*;Xdcy=ehTubMEi=;s{yfO3K43=N91-AjPJc?w zTjTG9{1_MGbG)3oYrl$1E!~_Bz@y@or%p~pzhSXa7}d!`Ye;OoOm-^z`cAwi&C+RW zb-%b0YvyDG_KGRZ7$+~^SK>>1(N6cYUWj|9G@TBAeJw8rV_OucyU^a_2;qgwHb>;nCwxLQ10_>+D#^p3d2Zk(QM zd0QOyVwC=B?M?Cb@Q?JESJ%Z(%Wvskh1bM!!d`mp$*bZshTZhOZTaH8_dDnSDpxG; z^O%0(TediV_#wTpK2t1px{j_PNE5qms;2iH6pBOgZ_|6Ncw!%`GP=4nTddk%M8EPD z5#I~Ur^nm^#TJt}^b{~voC;*nU+zg3mnaMAQMg3$^%6GSZOth$K!NEIz5j`cUFYbX zWwGK12NLP0&PR*2XX5FH_8b)lz{lyCW=F(FRgcm)tve*%b^Q?i@xTGGDkX&8QV}Gs ze72V^#o8w}4BkoSAJ`*4G3ia;YqL|Fk?Ky5koOadwm8%4$GpUcuQ9+&~@wdv&^zx(TVxp5Y{ilnmcxU%o`WZcAvG;-BjxN6q#JZCUj=TEx#2v}gj-^%F zVxLVDj$6eV;{_` zcZweQgg932c`8B=>~(}FZKA+KI~_0Sw1|%V@OE63XcFx{?e3U0_CTb**4Z(o^S-E> zf*JNx^b=vYxNt?^5e z=#ObP&GqFO(b38dn$m*=(Jhn*XeksP!6|7Cx#k`ekfMt9zp>k}kv1c6VrrCUF=Vxj|iYyIha9zd}{C z9j{4yT&N^^SfN5o$l4;3C2pY|<;sf4cQ?`sQ#Xoitk=`@PfClFs#hIGBPB&oNXrhB z!D~eU_vRd^JO2us$Wsn4+*gF_YQ8y?(3XU{HlH0@t>=ZRH6I)>xEbLW@_@s0^psF^ zug9TIZ9=F_e(o?K|4kTI{lwvr^cP{Nb&G@U>aeixZi9o~;*hYISnF_PYEbwOO6V{% zHXz(YD0g`Du}=u!Dsku^=n=j#yXs)o(=C*|k?YXY*(KbB&2qTk)*<{+EOr=aY8PHN zoDZxuRRWjJiO*DSoL3plK+Y!oi!COK@qSua%AIOWh@QY%Ddop2BrRtqPUjyV+M z-w_sw4m-?Wx-B%5J?J3Jz9~#&2Ra1oFA!EF zx;PYY^Mw26X%27M7lnf->>T#7vV?XMRu0Y5)Sv|Q?-S{CjXUOw@d8d|bfIQsP=wg1L$p>${+HNC=LC^=9?&8+qn zzV*9JeOKotVlf7Q*e4iXlGi+`p6)22s)j4I-d|a` zPDrQz7px%cSZ7Z?9w{e`IYXjW#BUOQpTJXXQa1>Uj^p^e%L?P85L-BjM;xQ9~OwI!}higLxPc8gZ8~%gMuySH}@`tGB0DbO=z-s_omF+XY*x z74~U8tpfM*GW(*@W&u{`n*GXRqhM5!Z=bXAfgoiy$39v6zTjtUhJ7*No`CjIV6WnG zR}ksPw(kh25JWdY_K%O13%m&D?4{0^38V|o*z+<<1efLG?e~=y3AUuh*he>B5d=?0 z*thmv7BGUt><@jrB;a%g*}JV~3y#_c*vF|{5Ez#2uph>y3+mLo?6bFu1ZGTE`;2{j zLE=2!{>=%F;L0I;`vWYd;Mz-)y?FsFfE@|;PPKr*vE0=DQujGQpN5e=^;?p_ouzB9 zFOew7oL9H^(L5z+3{$pmwvHFHypXd`^f@6Yq{`Tzj*Jn6l&-UX07eNGRQ^)j@*)IB z!6gc+He66MIYY7N2^D+_{6XPPh6u*m#wZpWg9J~B!xR)|pMY_Bkm9;^k3e_h8%ll1 zPCioN_+!S2P| zluPE0|L6c^6elmLK&P{aVsXq);7!h_gmTD&fPx&#+fpk5ZDR%{=P5z3=A?jf`J1^Q z?>&q1O$H}Gxj~d9QxicJz{EyPd*A-kCkEWczttHsMD}oaD zQeE)pK`5nkR#kA;D2RelRTjMF@1cCRRS?K5_)+He%Lz0?JSi@zn*4yCkk zjvu*3of7|any(n4L;7{%@-dl#|qNeEW+Mlz>BD_aHU4g?WIOc!t9q`TV+PC+vRS%jMhtTRf-H9DbVU zu-$-C7XRtY0lV6*8T|LV0`1<%iTPdkcG9*!-vOob9YE z8GJJbn%(_Sh=1&|tsNunJfFErw99Ep;h#TfZZ|u3mcP5%*e(NehQC2y-!5ry0zV7X zvMc5M$6q(1YNy>0%lC9vup5|)=EoIovU{f=#gAVnWoNJ_g71H5jon>#IA5-1*_Pc9 z$}iTRx4kwU!q)<)Y-KP({Nta#+1?G@$G=SfY+EGU!!OJKVEe9hCqMmfzwN$dKmNYp z9$Q_45C3<4m#yg$Pkyq-6Wf$rcmBYcN4Bax+xSXv9@s9(IP*x;)`W2*{i-Ryqy9%1Ty zqw8U|7xGm3vXa5JrUOd+*9QV@*Q+S}!x-}FY2P( z+DJ?BOHJ%;Pr9t*=R+jhU%(pve;@F+tq=e3^zBS--~3tTRiqo*5~xc&%}E{G?z8i} zaCddv+WRv+&Q&GbFH2KA{%={^{kA`N$M%mpadjm^HG&?MUHuxarw==APwk%GI#B zJ9e69`cv5^%qoFr>>_WoH}yZBM7E4g=CfE{{rEZ?4Ye4azvEx>Xm}K_J#C5nt1^P8 z@nwd*b2XgjY4?LX?-j<|&l@9uxOjl)KJC01k{*b(>)r+UBS4YMxZ|BX%Rgo`-yYVVoZjrsKU3gw9 zrDQj$t-Q7)g=AKMBTuI`kE~EifB~8>$aG(19 zAn7Q5=g#Dfk+NdOxXa%^kpiB4=66Jx-0d&BNp5ckxt-e2NEq^4 zu0_;il6Tr0?(usMNe?Dpa|IH0r2jl$ad|#fq!ZU)aF1TRMXFxk#WnhJo#cF|gWF_T zNJ2HYbL~>{NY=WKxoJPy`vLF>ONb}9gYkq)x9g@{=5@HnxJ0ie)zqY zbolZ$?hV(SB+QyZZh**}gbyp=4iC7I&bQ`qy$rUJ)Qm52Goz`bC3ZHqv6@Um|H$OF z{Uwk@e(BtDHyp{mO2my98Ij!81YETNU6L@F%gse=kaRw=xND-6N%PwnT<1G-B;^|r z_sH@FQqmTH8?kjA347`s*PZjnT5m9kyW!QMb;#C4?sfGU>(AFuag9SKtnbR7tF_fw zD3_VtXifJ!!2R^0);jZk5Ld(KuC!uuit|=C-wqtUIo5=W5Avtq;h#b9eY7*3`4xxJR;5twXPt)Yhw+>yh_tb>%C1l?lxyvYacw8yTG7Zb1!4K%npjRf}A0DNtR?il!E4Z?7&;k{m|i_ z&A?jwhiGv*Zw#!Lo~v_{G<2-LIHI_o!D`mpmCD?ee?J;7=__)%!<((cGUT}{hSJt2 zq-43Z&Ouzh5ul`zS1Nqk_{ z`+b}tVfvQink2A#eDw`yv5sZ6L9>^`S_Z8$(qD0Y*`-)TZ0_cGCZ4u}kSc%q}bSuttuYrLPs?eLW{E z*27A$_dX}9+}Vos`X1-TxPz6UUlr#H*48ShvyyWvf@t;5{Wiz!nweG6#tIgxw-63hU!R8X@ zpUi`(d@q|L{cMRCLAt;JrDutf)#;oM&OeA>t;HOT^J7HSY5|A*;1iKc;&H5(-Vr_S zu{ny?eMCPSCZ{{Ln|Qev=EUCUAd)E{XX;BUQT0J8$4~zukw#1TH;?)u<#uu$DFH+z(~sjDzk|3%+lNEH=}8Rmd2rga z>BR7AS5Dv_3Q>XP!g(RECQ7wCag5q6h}--eIYFx?#LfXKC&9*mcEBFMCj*k>^T+M=$f~+APFT!ye9xPkh6R@12**QzU z2N=#L(<#excSFwO&~KKzdeIzq_K2l(m@bF#;=SeBDJ@RT`hLrmWDSlk^_6AoMm5gS z|2i%EvQ;=4*V`;Djg>f8J~UaruHM2CD%V>!xyW%swpUxu_iWdY3H=lq5KLyR$8widNZGoHR=u=?}a7Afg82{iCN`(ogC z!col{wm$DO;eAyVo7eDxaM9-uyMMBuQ1JCOTS~8oFa?&gRd#d{nA$hkQeZnFvi3Ur z?VVQ} z9OX@DzIBSNm*YnG=6jMI+U`UMoQ`9|^Y#Rl^jJ3AfJ{&$#jxXc5D16gM6oHUri7Km zNcNYThJ?3TN7xB(bqEqohuB}F)d}&3LfLjCC4zO*#}=H;FoH2*=JW`@zsa4*{6-7@DJoQ z*?WA$@tYs0vDFhp@Wqj;?8d8m@oW`kwri(9zWR{@yJFr8k2@jH{;T7L|E?{|ws3dC z&pg}6c8asdyPVy?wz){c51B}@x3u8#t#8(`JIAs38OB=nF=a#iQSvJ52UQ1e`sFuk z$6+Z|| zoybm$o`ONv4?&y7r(JJZ1=UR!6q$Y&X|T@XT|+PHmPEBh+kZW*jo8~3E5(^z(UEYMd9^tKM(D#WYUHYKUJofBcQdD!lN^e58cKioQQPBP zD*HQTzBB@{bkM`*4ut^gl=GnZv#?awox^?RMfxeMm&|VSw&Am^-qH?pV&NIqgJ-Sg z|H!f|#*aqxF~gHAlKg#h!k0K!JK?VRqmo#bgMYbs{?Qm#R(y&1W85)TZ^jjK(qtrS zq56{fRK*e2@4ig)nfP$l=%Ub^ZWG43tHv>ZvwVORZU>v!HU_hP?K@{a0`6!1clL~V zfZIOSi;Mr6t8NZpZK;no*Lk^%MS6F{{KN%+7H#FA`KBO07EW`&`83*x^_#NW9R1ak zRT=1Oe({zEYx`Lb^WX$GR(p=Kc@%XU%jCX;dGk7FR!qN*dFV4bD{Ilx+$){NDpEBw z2li807f2ZMRRap^*e*Tu_6Zx7QM`uvKsAZgDpocprCPCEE9A`Ixm&VsKHp&eOcBpo zoRBb=d~e3WZ2DuyDlui*VHeHz{Aa?lbelGdalo)-509HY-(bk<0!PixzDBd+3Wm&L z3v^k_4FhJkqP1BO?|RH^>@-=mOI>CgrPNuIDo@OedsJB)tR9&O3zS(>eh4(=tlIOx3Q3xeRSGOOSubEXiAMrt{@FlTx#aQ)uX9R(Aiw`DAo3 zWxvnjdXGI}`mCG86+5>vPilR|J<@Dtrjmwn#&gZgSf4@Mo6d(!mxw;x%WDnHzp33g z)zo@sUUmnrXzzWdUS%sTg;>L6KW)V2Z?0y(`BaPBJa&hMtyh?DY9QQ? zEBQ>+ixiwwY97i%8_C=# z{n_-wfg{Xh%@3x{F5%2q_B#;r_xM53v5DV^D$7;hSr zPGj!o#hB`xqcUqRN0_P~r7+i4hMI=#vSkul_M1*Rl9}6jcbh)NSu^QlzNV8XB2({| zhiR}RfjPF(#S}Gd&P>;$nQDE&F^w#2O^-dpGA}z4P1oNyX8!gwGyPU<#H5E|Ow}?C zm{IY1reX-qOoBB`cmJo$jLTFuJrt_V^e&b&ec-3b+)}f_^dMcGS=%mQ>O(*=-THrH znR+VB`mYPvjS5Ok)n7lc{c9DN0W#y*=@~iZIrUNOuFsp9T~l zW0o0-)umYbuq6i4T8Qo0v%omrlZU!^4!`1F2R$1x`D;w)*pX#_G8}She@>7)3lkY+LUDgK%*>_Tlq4jH@LsScxaSjFl=HR@B_Xpggk0 z9<6`LIQW8yl-uAHHFqupdRJ^5^k3tj1`FzIGVxGwo zkjD^6WSdk$mlzvm(@Y*9IgH~do{2mwi*X;#FuBReWQ^m^n`H3Q8It6)Cha0ILy~^d zWLt)i@!jLNiCi|HQM)tJL_e3yhzSle0SefRjS)d6xNA%X|HK{>y)uNcnCNG6;5NkY zfVP`_uL2kV&&A|nT`J>BCe7qyQwrnyWm^-^_9VuI5~9i4=ZTEy3Nw>+y{8!__c12E zg9(hzW<8THBk_!Y4h@qh|5W!+Un!d`%*HYd-pQF9{~f~!AK74Hxjve~8<#L~l#62I z&i*#eMny8xRu+t@=p&4{b<@UXxNrt})41^wQW#@IanyL+@gU>0#*lIS_7KJ_dcgS2 z?jXh%-+XdvSXq04wOdM~5Lrrmh_%pS%Bt=X7}>|*@bR&U%Y_Gk2YRU2Qu?8hkH zdE5Be4If5uV5u?fz8B;7!9wFdZQB`8M4qv9uRCKpCd)Wz#FgQ8Qf&Nt+Jyn1<5z>T@$(KGWBHMTG3Py& zG16{hEdFWCsOq#d9$ANB#Jt2ApGO%oxs! zFst7%g%a|N28qv@Hg#EsgVYBM$#N6pnoK`t%3X#rzxfqr?w~Zod`l8&Td586 zQM`_^TeS((UbdF8O}!5Dt7R3@)~dpsdjAJ`uX79IxVVBa(AP0L6_ycI!>gD(xFtl0 z$;AY@E+9WmE@1pa=MX!b2$P;XgB&yGVDz$oA}}7tEZ&_&7?$TS8r>7f39B<0*2H(j zne-oKtIRj#FF6|Hh8aVy*dD=TIgcV{l!F*z=m?T;ABa&;{e-MgcVRs9h7dZ<2lKT4 zJreEcjuF3ohk*30m}|cVkW?osX1#hpa(F8lQ(@bOSUD3g#d}{P-#`9aX+cP?b4Cf*n~}AylSZY_9wPU)eKj(fYCv{w8#bCze1HtN3>rz>)FEyzeMXV{ zYmt2CZX=cR_mB@;JB(znRUy(_TaElW?jUMTjYdOL6^J6e*66;@t*Tia@No+6^nF4Pek7_a?_UvNAA-7;WhiC` zAh+_xhQkfJ5&T82;klWeNOlHdc*NKrnGmEJ<^=g6ChSB*^)w&E7m7C=Y4<`xQeq63 z|7=J0o{lgKvi3kIaiNAAkGUbz$MzdaUfqT?gzq-=7;r{{LVOM1ZP|*926!0OxYLon zJDd$ao~I#I+Z_yd-KQeU&Nhb1GZe(s!O~CK1qQTy8N^~g%OK;UH1d82Xh71JLK57Q z4Gh91kww}mgP>vwB%E}@VEF4Aqz)Hla2K}XF=`k| zdr5zTNxLQ3aM{zq{@en*G_}p(^`klX-l(HNt@JD$^3KlStJgF<-EC!XIBg1!X)`x4 z@Bab!)*Bl*=}f?wO0>b1@b7R~v8I9djju54l8S-L%ojLYByYg78->#m83Q$71U_?i zox$vrPq2IJAAL=QkFZ4eqP}q72e@SKw7$>PL7414t{*u57QXE?s$Xe604tG)^mm!9r`oCtL!zGh-`r))L_~dYv zz9#1xY}R*6U$^fm{Nm|#{p0#i;NXU<`ZBR?aBoGf{?GbW*rw=$zM)JDjAV)Q3->g` z4IGaC@uG+D#}rtfG1CD5IB`z@8~p)1dgzRPwy+L_X><*q4XE8 z=EF6K3i?$Gc`)(VCjEx(xo}REhN4f;#lTHh_oMZ8M8lop-DuTYQE=;dU-aHhN8yrK z5A;}M1e_4!jBai_4CB2W&|eM1;n(&y=>1R_eAv_ytucHM{-lOOWBzp@dq^9h&lLp2 zdGk7G{WU@G;D{Pp@n9e<^-2-#+q4(fZrY6Q*9(AkZb_lbf!*-t+%@PI!#m+o_OhOX zi$7d;dQNZgnjai^cvA0=v@g8i|5eW~${RjMAJ&`d^n_>32ld|Kx5GO$`}7pj-QnB~ z-Fle|u5i!%Q@taB+u-@(7Co@h8D7`jpf|3+75@96Mz4TLhd-BA>Rp|n!POUT=>6Q` z0LMeu^f)#4u-1uuy%X9L_)bucULj-)TY04G8GI+h1th-Sq#p_Xg=XqW)mp(cIY952 zE)kAhKC7q6B*45cC-u~(Ea1#n$MwPj%wbMrq~6j)9DJ-SOz*9UDQtToNKYos1fB-= z=)o%(_(F`Ip66jB*m&P|y#p@{;35|ny@z)Cuq=V57hR+WAJVkdJ1nmY7fBKI%Fb%T zucmQ&)GwOw#GsL$hQ9_p)2^$xtx*mBd`DgHfhh`pl&7S3K1&7Wvt;!|lFG14ytLj# zoFY6HyjCxBXbXJGeMOh!Ef3ES=XE>lW#N6=Q@Vkso8ep1-*ibi8{x_6Vcnn&GO*_0 zpl*fVW!nlhax(n?R@J6^*_mb^e_;pO9F28gY;s(^}c53{E z@J@Gh19-ooho(1mE&eV;_R7V&{wIDxMSt>jTZR{*ONn0 z$bJ?=t}=DO+tU!A3+Tof{Dgp$NxJ1(lTc`If-Y(E4+!rXtGf{xhrU@H)x|A*gM_F< zx;e+bLi%fhb$5RH0$u&OM>jBF6q0-Cr(51N0!7~6uIueG43%GT(WTUXgg&xqy79yz zXf@7O_gCqAXj33j_ZfN+lH6*h`#t9^^c{=Q-K{tPJy6iomF2#Hl76Y{DoXZ2#-EgQ z52d_@nx4q&u3dZuZL5&h9Y66Bs?A!ft3Un%LZzH-f>3-wt=@jd1v%L>BOBU$3*3>{h zzvt*=kncg8U#9C=+^d3AYxp{<!XtAnb$0kx_h)#2x$)hZ;Wz>7eK(kWR-Qor*`-py=CvIv2JTK_wa6 zb)G)C3cW~l(Q)^>0*!{ybdZ&bHu75IAF`<1(BB zQQqk4h$6C~kM-(0*dG_5lLbmTa`BnaJS?k2|CJ6MIx4O6Ff|Q&=)G2lBPE755LdLX z@`aG2>b$nJiU2zF55##tmj@+$_^MrN$b}Lf4QsC}XG3AdgW8u!EQreK(>~wGfFzH1 zYu|B0pt>C$+Ju)76hdm%UI_%DDYZszrP1?H%`4?~_Wowb*K9D+jbI%o%<3xh&3ZM3(@heF<`Ew$wf z4nU^+aN7GVL!fzzk@no9An2BsuJ+qq`=MQb)wE^D_Ceo<6t#JYd!gv&&D#4m2SD$y zN@@R>zZ-IZ*J$?>cR`%P%UZlPf9SF6oE9%|2Q+0osWmX^3rWd*)ryCFpv~VuX$7iz zLu;PB(-M?>LL)bNwd9<)Lw9*Ev&IR6kXr71rSdp}Whp{)Ez@go+}qFTZF|t?06rW|{-^?L@X#o+%ZQ*^#Cd-9mv> zEqPk3AUjA&fuS`$Zv*}LnW|MHBtw1OiCSe?5|mdFueID_1??2YXk~>Ep{3XeE#Mac z;`)Ya)n?$K&G`LVRDuPR{11>U+i3>9{o$j9i^M_3UG7>JBu$~Pn_IQKub4nQE>+8) zW(-}6B5M`BGlFh<5VV{V4WX+hrdoKE0mP6t)QYS|L;JpHYfbLdgESwbw3=shpl5{& zTA#$)P!#wNd}FBvEgf91CG%1PN^o4&+!Ch_eboM?8LprPQGU;8uD_!SL2oBC=loTm zy4o+A_&Fu$aMmm;YE`Y9i`!ow$=D^X!oti4qv*3SwyfyokXTT|< zo95SspWuFZC(UgUQ{cUEissaoNpS5GYt6B`36N4`p@};@4jwvhqS+w-9ZU++*UYW^ z3PQG8nokaofr-khnobH|zym+!HKiLqgVvognwm#Pz+WZnG?P_^!E)%2hUue^px=Q- z4Wrm0aD+0g5u^11JghpdA<;1i_Dz4*7(M+CwCVbwp@Mk}GOzb*q`mG3+o4w)LC_m; zA*55|B(V=vrnG7Fe|in-t2AkF#66(i&-)r|r&pltv%4C-)7{{=YvmfTS6_hl&X;KH z+4&rd+kZuaBiRLNlP_s(y7vsM*^;R-5YYi{9T#ZKt3L%FJZ5Qxbhd+-0#HLawGB)? zo2-E%J_eucI;9ag+5)b{pU{xXc?4o*qBN$xnn9@SzgUNqs8n5WJph3T_hVkM(@O~vxqoceUbmW?8 z)P+}p)!`V8Ma{dQCQVNR=&1zbP#PNhxE0{NpGq3%oNt2@Ph~ZJu9Slch0+=oRX0K7 z$LpZ9^pyJDizVRT&{y?^UB%$l+F^A>{u&q{9#jwO zC`5=F`Mg3jvWpMUcgE}Q45A-OiQ6IC+1%=6# z>YpYrf{%CIP{-cP0msd*sW%?Y1|`<#s}~q&fimy2)nANef~!?&>Rv?|;24jmjyjYM zHik3QE%ehs2KBsp#wQU-Q$DNidPN9+8IMc-!$hfb9w&iXAqwiDoU>rP z^(J-LHxcyQv|fEd`3(5%(_gi!x2HgA?UGtkK>~PLFr%gsaT5F)KB3lR9uHdCe^INR zivuGRKB_I&p8&aI18NK?7A$D!Q48}t4qi*|QsXPdfR~Q8t4R(X13|}TwWmcrPPp+cvevbbqj= z!BK4}YzG*eW~b&&^aH;gu~OS0;R_zNH&;`5>ZL^#UzF>#1#y_XL4j4Yj|{ z+rdXXWiE z%DS!K_r2dx@qKi#+H3@+Q|1VsSo0pGc8&&WzwSeY_&b0PO1e?A7%J$M)Pd?wuUTz7teN96}Aq23so`>2Mj0f)u7$`2u0?Y_KkJ=(<4j!>SiyHZY1F_O4QIbuj z;D>=2R9p@gL~cf)%;QZ!?bJ{d+1nT_*|8tRH^zYahPzQj2_sOr;Da)JZvaj{aYr4h z)dy*pwxXuf(ct+QDylP953F(|qvkzz!2tyV>X?ZR_;Un{!mrl`e^ncx=);=eEK?g* z@K6IB+J{1U=c$7YI0ckjk{ZbWvk@iQhXQ?HNTM*ds-VP`zp64Q6|m&LB~{9T5=e8I zQN7=*2)3(Cs4}V*K&P=$)q>0|;H}yr)eWcQ!Offj)y6$?V9@>^)n*%6FyE|8RZ)F2 z*z>1NwQ_kQ`0II->g7QhP@$kswZCx#s2NwKdhm)gh}wEfl>|$H>y@sn?u}Rvj*eVW zeY#x|tf{)B%CcAoCLx)s8Hy4hagR`SYGDod7Q8F@n0F>VFeX&0p$9k2{smkC$>;_wUjIS{OR%Ww(6mIbJ`Y+3|%pWUHq zJUb7>Z}(K~e>(?28rxLgJema<-)X9bH)epdb+)RF>C-?chp1Yd{1dPbG*cZsJOxOZ zVpI?MP6DmJbXAFVKY)a%>Z&^oCIGb@CDlgRaiBa>RyA?y8(?iKtqP2M1#U^NRqcO1 z257!nR!Oe=0wfmCsT?mJ1)e2Ls+6aF2IRJVRk2SU0k$a*tEff~12H4-R2=tx0$6u? zRqnZd1TFwCRFbTRfGoeKDt!G909&_3Wpc}VAa?SBO77}Az^&n)O7`SiK#^CW^6C8m z@FK8GC9$g?NW~VZgfzSX&`WtLY2|%DOGBzO(nKg3n}o7w|lh=|J3 zxK{vUO{xm|&`V(8`56`C-Q9q0-hV1dZZCj(wl;;3wcSL2gc^6P1eNbh)UMEo5 zyHBN8=^0Q}xKrh}bO%rt=dIGW@&w3mbW`#C*$$kLbyATXZ37(NQB-u^J_gp7TC1eI zXa%ZIS*Tziw*bK|CMpK?kANiweU)RC%>ZLaQ)TV-CP1oOMP>BzL*VRLc@@-!M&Og1 zj7k>20idX?Qwc{N0LO_lJ z@*_$GKsen9k49y{ zE)Tx)DT7krmI_mOANo45{OP;d)$oPO}KOr5LFk ztXT*=_zKnzmIF9GXj57`#RfJq zo0Kk|V*wpI>Xf()CXk|4rPLu{0ET1bN>@UXH(iC6#w-pN;#_Lo9Hx9cUPmv=zG zRUuR9!UF)Pd?!#UZ95Oh7qgT$zDxzePJl}H-<<=lQ<9bLeMtd^B~K}>ok<3^yogo0 z^d||h$~me8$|M0EhYl&#sGJ3Mng=UU^b-O9#XU-!@Mi#*Wa1=n9{wEyocMiRu~{Jm(0qJV zG0Hd?sN?4`ovTyI0Z7*&nz&y+g4p zXa~@E-&3*SlpoLlY*Snj`2u%592FTie1J;|c8Ukvyn)04q9W^)7vOp2f1a)~EUK*w z&kO@Y3^0HoU;qXPDxj3qStueBDvFALgrKOTAYHRZF|oV5y9;J7MG>(JJFbC>-J%%Z z`t!|w?tRV$CeGPs?X}(-=w|xwcbLj-yuImZ%P`dyS6kCt?x8ByY-Q>>I7DTC(#*6m zqrd9ZG(*#;GlNwTgJh=8+xn>*EX1aDwLz+ZkA9i#dDd5@-u%_%xwx;&Hsig?INLx~ zq5CTnALyg1ZFyo66W?1UJAL1zzAQi`%xo~3x*AlegRhv(Qwyp}%X*WhhyJP!k84ck z|MgSt-coHc)rO84M@-HK_^LLz?=y)_@=?uh*>2)n;jK!q*=UlwrI)JrjMXMD&UvZy zBbJ)%f8(jDx0r8IZ{(>edpOg?wWo*5VN-?4i(&4n+SGEBrXn|0bdN$4-!(l|Pk&^a z(BCpsCGs?r`j@V%8x>$=vepDvvecCfb|3 zsV0u@XL9aBSJf7$0F!&4om5vodYkxIJE`6saWi?<+fgMd>u&OVd>55opo59a0tb~$ z&(7rB342w`WowhY&pNA~FKT7-T;5q#6JumD&a;zhiLI`QPhv+^!V9rU%*+m|_PbgX z=MLGaZe)K`OnGdpD)aiFn5S>6YWwGvqRGQXb)e>{V*aT1D!=Iu6jNunQ>h2sQk*~D zR^?`PRT1~1jcU!EdWFAP8`Zznrxob|)~eyjYDH6qm1<*`ql!Z-Eme*0_9-scw^p?~ zxI^LDY@rG(+@yGGZ=uTcU!(Xm%v?21vP{u;N-Ncpy7`L6LuRU#vnmxgpPQ-{51yhh zH8)jFwNNV71evJP?-wcx^A)Q8>v9z9wi>If$D}J--!)P_aZFJ>&^J=8eV?HC=x3-J zaxhvkBulRPT@a~|Y%ox*^c$cMHR!8c#leaJy85cB+5p8XUpu zO){08nX_W<9UWE0Z3jiNp^oa|N;}2WKH948iER`=3Z$x>PUeauyR}riUl}RRJd>y% z@6uJ+T1!;2Y>DE0gjm(d{$RZJ`(GBQYBHYe{FiwLJu^O> z@`u^$Jv8=M`5nQk|6sF|_Zx?}{a{@kb{hL-erG3NZ!#|5{*8t2Sz~O}_?2DGUS|B(_ABe>vB20W z?h8BATxq;$`DbQTJ;gZg)+d&yR2t`*ePVTeij40^d}PKt6OHH1`M?I&ryDQ4_?}Ik zm16u{|2^9~DABkg<#-D8*FSE{F=42?``Ze zt%<#V;$yt8?iIVU$=x_t_Z2%f*4cPk$V)cYsf+QenJ-w}J3HfL7aN(~zBa~7j2hX4 z9CPER5zpBi4`bu9h0mC0v#xQja+!OW#z8f{K`;V1KJ{q-Y ze9XR`X)>DS_?V?kdu9}#`G{Q(d1w@K@FD9azio81`2m}B`KnQp@PJ*Ocit$r;yyEp zJY%%+{5=+C&W*fH?y=I_M~&K#xXU&z-)}T{?HzVHcBj#e7q{7+cAJehI^SlEkJlKT z%D=^$)-N-1#s>B*d4W-rtbsLjo@MkU;wIxSrx=B;xWU$JR~mhOcAe#>6&bzkex3E{ zKGDdj@EVhSNH?mkxynxOOEFq)c$F38BpO{DafR8r#~6idy3A_6MH-oZyu@OU4lr`@ zyTslU1{*D#ev#$)^fnsQaDjbn@i7|K;Q~uhyBlrKI?t|`I~#?o>zQXj7bAazdNyC& z!KgI)9D82V#z=o#9doWQH+uQ~EXxWqHZtvZmTlG1Gpbx%%Wl_6j3OJ)u)ouP8>V`k zVQoXd8(x`mn)NjJXgKLs4GXx~WLV))!}`vCW_Yvk6bl&m&~W1Ulg!=twqau1lg#Go zRl`-8$RzX68#oMLc-H7;3ZI63h+D~VcQc=hlxre`_JFx}u7n|o)9;qXyMnS8m@ zaL&;qY*KWQp}El!_TFlu;p@?dS>(NRL!;_LZ10K`LzUSfrWKoL*eC5E8`LJoaPa8^ zY{C6V!@X?|uuCfk7>>-{&qO1G4WlmYV_n{24Q=o3VI?D- z4Trh!VN=?6F}yoxH=Fjr&TwbbE~Z*VvQyt(Y~o0BL*I2fSzKFV!=EiX7(AfA?m1!y zvs@)H9Cc_rdmZ~*ZeX&V9cuGku9dls<=_7x54o_FxvXrGKkl-XJ&AcHubH}qRa!rk ze|x@}b-#B@o*%fG)h)j&58AMaMMs~PCyO_+XO?H=R}(j~F?ZDR%99(|e@lN%@ei=s$=`_oEhdo@Sid)P`Q%uSd7I<|sE4os1Y+pS=u z3=`#1s^x6l#b|j;<1&^~87Y4sx{Sqz4v@R0LMH3oMjqO@fSvf)NP%5LGH)7?832c29lV$Y)HWegU6@mu4eIY!vZwFr4a$Nlna8fv25kRKMp~A^ z^>#B^U6-QJN$U5f%BfJ z?8@r-23y)rWlv%&4bm&8uy_G38Z5gznZ1b2F<2flnKhWC z8#EoC#Q2pl2Gg7-v9+@k402bhSaDdi!9KZ))-BS&r<^gXx^M%tk4pBqqMw0pl9H|N z6JW6aW;q)s@-fH{E@#@@&0xlfGPbv*yTRM;Wo(GIgTboxrR@E8TZ2{RrEKycYlGJ_ zN|;GbD}!l&i`g<4BZG+(i<#9snZfQ?MQp(iv4LlN5z`*mqE8!_Wq1Cj?-p9fZa;mm zzwKlJ^IZ2zKi#W<&5nDjU%n@wJ+^+J|G0BLbG*}_KWB9w%UFCxf0lV3+cBhG|L*Ku z_Qd$Kex6P)Gr3f)pP-z`d}bceU)G$%Mh5TGx5>$2h0-1R-``}jIj1)2Tc>2R)#a=8 z=lnN;ZT4NN9}zo&ZEc>XKk8N%+i-ZM{;9!PY-vt~e%7T-HpQh}KRqOqWxOrWKUSN; z25ryQkL;7doKn*C{V<*V?J!0^*Dsx2d>pU;>v$Slv}%O@6|XclEP9Ckm&2({VG*vM z;-1QCuLtQn930Ok&INt1p5s}YaBux3`^Pc0uA6>fk8x~7Z8v?`KbE~y+3U~jF_x7I zw)&k8q%diVmA>39g-ttZrXP4{4AaUr)UWp#!-`yG`m2wQX0P6g^iO(^W<$3B((75B z%npzFs`o`mW@a7U>q%;oSn8vfdWk_vtZKy*J$d~orW18vPj|p57G~C|1b+o?c=Cvy)cq&1sBh{ZAg&OG=Ap<4gDIReXwL6}`6WeJhA# z%f4>VJN$Pf+q!R+-kB*Q*}n88dUl2**}*RJ^e!)oW&57b&^y;QmTg@(S01|9xEHpjDPgid#F2{ojoAv%~&*y6=wF*tFRr$Iyv>!yR>U4JKxw< zZ;ba)mbSjLUijHarW0qQr;3bZt1PYbbe;@h-ENxd-OU`rj?9(owfr8;e8P0}(kchD z6FMTjuGWK@Tg^{h@9hz6YuOjwCA}h;h4(w%-sc7}<<}Rwej^64r+fd?o$_iR3rM@C z+pcIJTW)_-SE@gdy?t^?*L&pv=Cis^SKVy@n>6B-?mQmOYR#&24@87B$(2L89iN3! zUGC9+nis}0g0|^?)D2@RL>qJmtO{kPt5)j%bO~jR`HOYGoDN}HJ?HBBj|gFH-c8qS zc-x;jZ=0lBrRvZ8l1p_zS@dUp+vn@%?FweWce8Z+_X%b}i^l7w-s#7LLCL!JGyAcg z`f<7|wfiyK+Tps}R|PSB7NM)-9>m`Jgz6r+(3f5M7O1;Bxi8&6f8FmbfvhymOLxwq zKo)M_LpQH`AZz`^Nq6VjKJ4MjPP(p%ec0;Z?RB+&^=8o~mb#r6^=68TCb~XhjmSwF37M1;3mg)uUW7oH`gEs^=P6YOPelg)Y^D;wzM$qsEACTqFn!EVP7k~J55u3vOpUTW^$vC?BQv5<}lk&Ry)p} z^$PZs{V{ZBL1I_gB2*kmEwAKsG%ZB)o= zzVu*Tar!d5l|7h!YpLu?pB_wc?T^l-*RJgQ%pW?I3tidmzMpgs`ns}1e_!jYe(u6% zAA7FTFx!PCatX4a*XSB5-%!%b27V8}P>ByvY6Lku=IkLGdL#Hyz zky-eR)p@Jq$d-Lc)LC_;3v0bQMrUP87q%c}s7{kb7p7-BP-kkL11r57tdmpdz}_tA zt+U(FfklP;>UiF_XPkrvquKVX13K$?f<2p5*hOd8r_StAj}AK7n>sVkH*It(qB^t6 zP3Af;^*gf%amG5!c_-%BT2E(rPA8UgRig9Cz7sn(e}aIozb})6#)$&wQrcYJUgz(BYxB-`EaJ{^XYS!FC;3uN7Cd>GLmaROET>xs`To zs{D-hmp*oEYpq&)%P(72TYgk~>j7K#*lWLbbE+--{&9!)(vG%FZ^tI>sSj+JRq`6` z(~E7GecNT)g9h0!mxlS;PI@-XeNLtJ(9`XiXYds5OJ(huhe)ZtxL14Tdc073=a+V@ zOHPiq$=-IXZP#?|+SGQ;@c9_+bN206%c=xz>t}7*i(%2)RcqU_OGc5}J4d!<`|HBB zUt6_h3s^txg4=CamUn>m(8X<7$Y*bDWn>#>yVFhkmq{D;HMzU?>8sZ4Oj`%-`*W?? zf(BddK7*{;$T`;9%|_O&V{j|&KbNi8%YTO25p%8Bwqr8wFN3Vum~653bA=VNb!w4z zzHZ6xJpC#?w9t~xTKQhOV3;KnhQ5+wYfJW4{#5FFuQgj*dta)vx-|4AQj6@nPPG;>D6l{Y=Uo3>AO`X?9!L6(&%v} ztjn&>(pK&!jE%OD+K5b8Lt86p;Y9`O(qJmJS*~D3v*l8Y6a}jb(vgmIQ!vxN|Fk}d z6fE}0PpzAmjoF6GFIuwI#_WatJFV$y#;nWZ7h2Ii#%%1;|FjDAjM=6^_q1NzF=CHp zH?=lyGh(ezUeelIXv78-)@kX77%}F0O6!o75j*hegx2oYhU~v}hqS&`88XA@JzABs z4Vjn8Hm&RgLzY;-UTbp?LpDXVQp-_l$hLbg)@r#WXXii7(Q3Ox&R%byt~IMn&SXiG zw896=SqJM*!AdHh5;1R`O*7Hm1*bt+90RY=IzpD(Hq`Kj!e^KePbFWPRY8=+4QmGouJDs z&fk%U+UT<1s_T+bKVUXhNrx^n)_TSk$u1ok`xvlJGNn<6)ip1d>^h^vR_$9T>9|RUO&B*@@@ldU3$&dk z`ID@}%IN5@K}_1a94HA?b%hc>%y zA1iU0t6Z21=F;(Ps7o`%6xGXtP(^eI(vi+H9NJS0ef&Wn=R^B(0xF zS?BI9lCoMUd-}YKq~{JPTfM4-#AB|MMGb8$nVu_U#&QdZV~mt=l(ED*K*~x>^d!;t zQr5#wOY%}KWzS##7T12!VoNuC7k|2^#rns56sOl{u^%R{#hyE~*p~Wd;z0|v*ih9& z@zG)}Ci1>5&P>)~J3n3(=Z0&sVcX7&>pisC--I*b3>$iUYc5XI(_#az92KwsB4J;q z?icrbBwt_Er|^L{Z)Jl0SAXPuaR&k7K?nJ;ED9el*oRASctv70zB zN6hvw=`J3aEM|cN9mHFQidloUoj9VOm~;zkad0nsUT!P#949fG(#=TRv7MN;dM*>| zD#UEVO0n2iOUzs&TSV&bBBs{=CYtkF#6oJ`i}pSev4)~oqV_jLEV0K^(Ste>d-LkP zsHs}S^42wof)0q-zo;vsk6T4-x^cbe^=c6_sjCsWEfTTi<<+9|GeykK^N47_O2oFk z+beomC}J*~w~Nvzh}hwg8$~cq#C%(=79}N$*r^LkL^nr>Sii~hM2iNC*ae@NqD`S9 z7V&wqNYYotZf-9V?e!P2=uritU0x#gz%pC(qX(VW)l|{^ZX)(<+GtU+gNUU-yy##D z5o`J$CGu%6VrhE@ixk!(_I^y5$iqU!CbSC@Z8sIM&o>28y0M7m&gvy9my6i9z@DPV zdLmZP(p5A^CSuJ8I*Vp&i&$~0jp)9Xh_%>Ri3%kmn)9ZjWU+|-ohKKq5s8?xzmCX( zj`S~x=pU07CCoDlsSbRrgnjz;)k|+Eq1$N-wefx>xVH3H@2pTlZr2iZ#y}-#Z(pJw zVWb3hWUo5oOgVU}&#CuKC2!JwDwy1qLnnk4Ntq4S8-ac#K~%R9$$(m(`Af*D;^CUB5)Q@ZWc? z&Evr#?l&i22%f(bq4lCz@L#2csh^`^QkV`#_8$Q&zv*J*;^C0C!T@{R9}4%pjWEPA z5-#0Pp#Olu;55z*ZHfoM-S6foSvvquDlM_ODh$p_+MwyR5V)pnhhrWE!-elQsP#Mu zmXGa#qNjn-`FbauaHls6_jJIqbpYmz9P#HKe+Yfk6@BOW!Xsa2>@&_As;0PNM;|Y! zKi3n#NIii5L;8Q9?;-sR=rKr-1$qwBbAet1>9v4f6X~^q-UI2qfZh}7y@AdF>0E%$ z3F+K`&JpQcfzBD}+<~qE=~{rU3F+E^t`X^4fvy?p+JV*pX)S=(1Zi!6)(B~>fYuCY z?SR%0X)S@)6lrY*T4SWO7HG|p)?T1{fOIbex+h5YMxc9ybgu-uXGr%>pnHgPF9o`% zNcUEtdyI6i1-j=*_g+S5pT+mH4*(q8wYJ&*t2|1JNNaMw8G#9KNx7}uY;Nyqya zEUNa?@vL!3)f75zk1VMgNJr{kI#N%r+WAKbB|iGq z-gF#s!J?Y~rtgpJSnW+m$vcN;@2x)nK?zfP9;x2?UI{CUtE-FO(e>2SX!@PxjS}__xl(_pA)G?kEoBn)l!dqpoAoaOuhG>5?tK%)y;R5@IA^Zcc!aA9yq^@DmPjLx%HU#z3oS>~udP^*MV z)!o!{Pb)$8pNo3bDJ4wNa#K5@5`Nozs++2nkRIx-UUP!(XNI3TAEt&)O6ak3gnIsZ zx=)v5)%VsYA>mWJ+Hw`GZ>uErfaOX^^%|otTte3!GfusHp%Mm{rK$JNqx-ckQ_W{9 z!TfZ#x@M*lni_M}RnwGkP`6MsSLUmf&~;$BI-{J<`xsLPlqi9ROj7F>DnbALWOZGx z5{9HtQI}-Xefcw0ZJ()x>vN{7>r(0GwlmcUW0l~yzf%1+na-onY;{&5UFVHC>ZXxO zI5c{mIyzbjSHI0y<1i(>oVrlmW{47gwqC56XGcQmb$phozxJc!h2?6;K$>$SSE`2s zJ?`x)b)GLhuWXHamX{K)7_C#UaHBc7cD;JFixOtJZd5Prs)SLeHmRpMP@NCiqR!|@ z_3?D8I>d(RW8!vo+crwbm+n+Qx1j4>yi2{&l=fTaJ(@YHrLP3L;Qi`N+DfRpeL(Fe zR>Ht>ht&1I%i&)0VfBFKa!8nQR9*L_93EO7S9^UZhoL)8s8_!(htodQ>Yt6}(Cva+ z9sZ;oX2+s>@q==B@#duZ=IwIuF0E1P-6)62@-u4p%jIx(RjqnheK|`Px}%ET&+wsoe+j+Lsz+*% z{BkJk_MZkf*rk=jt*~e6>0` z^t(FVhSq7(4|P8)TEC7zHF)KRyd0+W{;jUjDTf7D|EMR4%3)E$KXtEPWe`*#;*DR* zpjr^~>F>(GSx3U{UY5biOA@~SzcP?4*5aP`%3#b$DL-(d3~D-R^G=t_pv@a?KI?25 zWFFArZ;+l}B;x_c%RsxgE}waz4EpQp@&Dr_t<7bCOZ2(xnlktjXTXOpEd#sGa-KP_ z3_{<^dHIYo$T(=or%Wn?%3>ovsiX`x^)}|Yxn*!vSHa^m%HYfu1@})WgNsW{xLHCO zT#hs4kD|)pd?z!$E}{%hy)om_A!TsjKr1fmQwH?M&^7oh*sTnbWv%(0u4UkVxiwGh zR0bxCE&0Q?W$<6D6(4L~2HQGV^J>E~NNcj@ZFS1PVP6|Q@oybFNNQa zy6{o?rO(V8W@ssR@@~9ucqxpk=+3JGOJPc= zvj&e=_AG_tw_JFmV=2_Ha^>!JrEoo|2QRiPg_~V^@}tJ3aOHhZ-lS6sXAZe>)4wHf zpxB-F_*MeT0z7!|+Y%_$@#K-uN+9B*Cm(jN1UfA6;sdUgz}u)^-1l4w>}%)EZLtK> zpLz4&hfBb2yN?D3FWy)J`R;x^azzQ4|MKIq`6aL${rQ1uB_K=@cw~7A)P(|nom&DS ziU3}iRsv@l0{HJyCE&HPH_snY0vi+i@RtKiKxQAv2L_eE=r@6Ur*8=y-`AJ_?Lptq z590m1l)wPretdfS5~vgfYw-6Q{Sx>zvp+Wymw;tN2=DTv7{K7tZUg03VbW1T<`A6{RRmJd0 zOn-WPK{1>M3jpHW+ir_@$c;45e2#N-!a&#;L7qc|(+P(-L+)C5%obNhxp79wx zw51Ss+GX;^9}2;(F_YhVRtN{SWpSfBh0rB^0{6XG2#Z{@dE&`J`0+WLmmDgD!AElV ztZjv`zGxy}xT+9d`Q`HY^9sRUl*gx56hh4DJf2-x2ver!^C9VluqC8`J0%tZmltaI zRdsM7TwPGa3w#UV!mwiQ=u!yPmL>dJheFtNzl3L56vCu6rCh3C2*XE}@wtBrz_wF4 zS9~gfCojtR^ydYzY`c>GxLp7pJQ*K(p#XB1GJcd3Z);{;??3_Q#;Ew<%>@uzrQ-9J z6~OeilQg{UQ+WY=eKd)i<cHE$o(*#cUqed5fL-^ruq3`zkddAQ;`opOlI=w`T1}< zXC{9;E+1yzn92La=0li!C0{xqA7qOw`6I{&^|wmire{864xhy%I^~1)(OJCMA|Fn+ zp3PV3=EJDM+5F(IJotTQHm`Y`2MfICXn1VR)jZh!YYsnHlLtLx=kisD^58(#Twbyz z54yFT$0L^I!TQp9yzR_9P&}N+AC=@mk^g+YG$RiluAa|>6Y{|C?|l9)A`ceDFW@u! zpd`ss%C{r%v4z2S5A1~yqb@QMF7HRl%)|*^N5-sNS4{~94;$m)n zITsF|T+EX&7p~hb;p_J0!dte4H>}SE(UT=yv@jQpdN1W2DsrLq`lZ|_FBh!D%Xmmi zE?A6O#s@{^g5jxUJgk2%{Iy-q1@ByFV#~RMQ!ZToZ#kE>$%WkkD>S@)$M1;{En3Ml z-%SLE#Ff0uqlxeySMs};C&FHvRa}J=Ayv7G+w7YNwvSiwL+d8O6=5}p`4gdV&1!y1 zH4)nUUCq67Cc?3}HGEsrL>Q!A!;K;*!sE7Ud0HSnzjQ6iICyDPNNr; zOD96quXTLa*Bq#cUeB*S&w(z-*Yh_wb6}d~2LAg@4*XZJflCkPfZOd2Tx)XzG44XNyLs_$tW(oA+Dztk2oddB9d~{gjTow(_;tvcbk+8*g(e8%$HT@j3gl;qSR^ z{KwjCXmr@lqvmGAnW@|Pp7Ly1-MF2%WMo5D-yIy{vcY%b4qhCd4PwbozRNcoFmWfp z>68rxxRZae$_B^wyEOVptL6z%cz+jf{c-}B`|Rc>w`PJpw+ z_VBYCCP2ucJ$&W-2~cagm#44^;FGwWyD;{<3QvY(H&oB(NC_w&y>6JVeA0gW#6=2;dv)EwY3*Rx=R?Lm$wvtUyBLEdI> z7HocSkY}#Wf>S<+__4|?xV7vMZ!XG$#_xx?>$ogeQ{Ky2TeMg37^)}Z<0Hd2?zci z<1QOAAwBLmZ=Rb8?W>OSqh*z84GoUg_&An?gsJ_)29qReo3|Ldl zdH2~F@a8t>>BSk~>VbUy*bK;8fc)~%4A}eu`RCpl&=7u-%Uv?y&-RnNUE2(3FFVCM z>t%q~=u^DYclwPgr%rL}XXy~xzJ|-Lro*t38veRE9R}a2;kDb-p|8hjzGO){^jL6O zqkpxZkPe^2&hVQf)8X8y4`8;<#iozS)K-^!RL7R)HL|B@f=^AlLiH% zdfpJ922CUDHM*O(R~j5PKhNVkrhy{oJTEd%gXGKS`K*>y*yD78FMgQ{pQh6BMk;iB zc7e~rR7ix2ykuu8RIa?p6PKpK-X9ma-(=G7A}?{{tWhdsBi@Z0~5hna3ydD6x45I^@Se|~g4IK8>b<2H_m z_x-N%i*v@qjt$qiTQU9o?=?Pu%y`g?xz1lijECKauk)UMT9`2{#;CoER z!`O2-_~Sq0;C08FT-G!WMk{Y}`J?5w9Zes@1-%|y8a1Q932CxEl>D^bz@-Vu%~?8%rS6g?^7O=I|iQV zJ>v%PW8hcvGfsc47j*eEKD5UeFtU8k-&l_U{ha5#NIC}oUU<&`z8eiqof~<{?a^>S z*~s6Y91WZ9Hfr?Ts)eJ$Z}tn`s%$j0ym-OKq>P6B0WbNkL8BpV#Y_IC*Ju!beaY=Q zjD}SMUh#njqrrLWD?agSG8`2(@i`BZ!7HYTuRog%dk!}7oqLm^t>J6FYgsa=QeN}T zs$_VGuleHCWN@{5!%HHQp*ZJ_Mn`t(oD5$&z2(0Rlfkb1E%B)&2)_N6mpo2_WLNs7 zndg!qf5tn0dtVYzc#Rh>PXd+id#;$21VxM9^L437F!tShZXcNh;r%}FO}~Vnax-J{e2>gD)`Dj-%5o2 zSHAK_o(Rnj-}sd+iQvJ$@qKd=VceZ>d`5mEEOh0f@jOFV>*|I2HQ<6-j2 zznp)Mg9EMq@x2e@Xx{weOV7l?m)d_ke`g#_G7{l{1#zI`Bf>UCaWG|!2%jXx!M}MT zT+=TOa;ru7f1lu=SsV;96XV8TBjK>!A(fA^=JJAr9uY;@9(O|S*2OT#?!=(#4xO;juO#Mz@ zXGVjMoeWn+M#HNx8R~jR!-9MnrnZj;&-F5_)ry9O3o^858Ub0~Wtez*1Zdgm;`)Ol zU_qEJ-di>T+UDz`LHP(+zfKq3l1G5;1zn9FliGa*C~Wnx$aDlKL-mmTh=QhEJybr3 zf`M!GFz-|p?5WqotoB%C}_^n$2#vQ@L#Quv)V^N zS)D%i*NTFppXlc=hr`=82DtU&aA@1l07Lf=hkg?bG(J#a@o=a-V}O!`;jsC=0agSK zhZB}^{Od3r>ifuXf_ymKNSEW?kHg^h5;^)b(D9@k7aku5S6|EV+3I0X+sY8TO&SIV z1w%|v83wDz8RDkUVW3)Ih&P>wK|-}5wwMlsUM~#M`o~a^D~vS$QveQy4ar6rym2Uu znQeqY(}qIFqekePHWcpvXM|3JhQb_uV>EUf3cl{f_|9S|JdHEP)4w92Vwy3|dlU(F z`;Bo}O(YzA|XVoz`7Zc(9m6hxfziV8>K+Y!IAKQDe$m+Bt-2{Xne1RmLcH( zM}g6ghrm{Q6Ktp%0`dqG4B0XS(uz#*(2OBayTJr4GlqcGMH8GDF$BhbGr_ZNLttNf zQ#5Hk1il2D;?Q4%!8O|y=RO<^<5rkr&B?*A;tG0&Z-${}gCXLC8TS1i0kO}_(CcmlB*cv3lU1NdI&kck} zuPsp6IS}&ATI0Og13~838t-KdgoUG9W7{DE!E$zM9PU04mK|=5Gb{#z>7&+ouz3JX z)3L;cdjsH`vn7749sqGsmKuN2P&EMBZL>s0@&K54)e`lC2EdtSOZ;O$0F3Rd@RjZW z7#3oM7hZ?MqHHVNaxok(Ew{p=J>ej#vBIEv;o$t*3UzbBVVJ2ko{0>H0v~HE^azKA zN!Hl0bvSIBX^nNwVQ}n#H74H+gPMER8eg+wbr_s>YJ+;pFsK^R2B##3!S3QV_^Wpq zEZ@)u$94<@<@q*vQ5psbpWC3*i%{rg-4>N3ipl%5#Y@{l;okVRXf`txHq38}gVRDG z`FLBL79I*VPuk*74p<`|c zEdAaN?S_RwhxYB!#4`l82DQgu79n7t(H`&p=nrcbwa0^Z`h#h8dz^B-Ka@Xfj{{fq zhemxHRFw3Gpq@5(K9(LAZG)wL{oxCX#C^0XM!Mm zP6zD1DTr`o2lT240;2~V(0gmrcx4uEJz_BCRcM5{Ah>mC?4T3-U9r4?9qkQCBOUPQlHM?Gk^^4NqvJLQd@{5*jJoWAuibjX(60{o*0eVS zSa-pfp8~)>pbOr+8UWfUU9fg<06ePfg4^c=z`p%maB4;Xl-}-wBf|rLeg!Q$bqxSf zM@Rgq7XZilJL29~0OKB{NXfwPkwreH8 zgp#h9`Pmcl;eo$N28}-rEnxPVSC(Tl+!u zw(eN{%@_J!>W<59_=4l-?wGOP7i6uSHMs93g6|Gzbky;M zAD5l+#xoz-{l%H)un)vqx}ajM4`}(j;HFX^*gVPwd&KwvOm)GdUOsSRhYNa``#|Cq z7u@yP8(w^I!FE@@VT`3KPTB1ZkNjNmf9`=F`t$X0A6TKkKw+CKW+6#6k^uVvVy`X7w540H4i~42{bam+kVHbN~pu87k zf9!z~OWPsXy`XwzPYh*VP{(?rPn;KA+|*N(!;rT2f|GB1;^Qx# zuvg)R2d{dT|}_2swE$fc(zO9yBhs}3U9%>4LTdrECP-@ov_?p41+->JYX`K3NNWkSrbufGw8ltl z4YcM+YY%h}knRQ0JwduRK=%mgUIE=Rq0Sffb4}ibY5}Mw zkZJ>{Mv!U+sAiCA2dIXSY6+;OkZKF4#*k_asOFGr52yx_Y7wX=k!lmDMv-b2sAiFB z7pR7jY8j}ek!l;L#*u0rsOB{}8`=v%dje^10PPW^y#lmnkoFGH9zxnnKzj;lZvpKw zq`d~T=aBXu&>lqEi$Hr4X>S7UQKY>Jv}cj_F3=uE+RH$D8fk9>?Qx{N4z%Yr`5x*8 zKs^DeHvshrq+S8kGmv@*P!B=sB|tp|skZ?27^GeU)N_z}4^R(6>P0|338^;$^(drX z1=O>UdKXX+L+WKfJq@Y10rfbfUI*0kG`S+`g+M(KsW$@kNTgl~)H9KKCr}SX>ZL$E z6{)uZ^;o1{3)FLwdM{89M(V{tJsGJt1NCU6UJcZ%?PAf0W>oRSK9;45TscGG*ggf3($-~nl(T(2Wj>I%^;*%1T>S7 zW)skiLYh@TGYe^U0nIR^Sq3!IkY*duj6<4rKr>I1qoP>|G!v0#BhZXQnw3B^6KQq= z%}}IS3N%xZW-HK)MVhrhGZ$(00?lBgSqwCjk!CZ{j7FN(KrPEChs!kgyRDMnb|$ zK$r;$I{{%RBrFAlsgST05XM5nT0oc!33~xyFeEGngvpSw84yN8!fHU64GFseVK^i# z2ZZU6upJP_L&ADMm`{^eBP^Jn%t+W72ty-bX&_9Egsp)vHWJnb!rVyM8wi6VVR0Z#j)cugZ>PtFSOH;n zB&ekTos73B5_wB4vWNPfjBJ^w*}(3 zNL&|)^J;RC#D#%4F%mZh;>bu`8Hh6@ac3Y7jl`vaI5iTt2IAOATpNgUBXMsa4vxgd zfjBu5HwWVANL(F=vmZ z21wcgkcNPyB>-s(NZJCB#(<5J*}CkS2koO#o>WNLmGuW`U$#0BIOV zS_Y7&fuwB!X&gve2ax8W$$gR*0;Gu`X(K=y36fR_w&0n%WQv=|^w21%O%(rA#h8k)mVNZJjMhJ&Q#0BJf%+76J$gQWEUX+D~~ zDQQ7Knh=sU1f&rmX+=Pq5t4QUq#+?`NkEzslC}h-F(GM9K$;Vh_5`FsA!$)SniP^Y z1*B0SX;na)6_R!Zq+uaxSwNZ=lC}k;aUp44K$@2(=So@_kS2ztjR9$7NLm??W`?Al z0cmJRS{jh1hNP_lX>3SZ8<6IPq`d)Ya7bDlkS2$u%>ik2NLn3`W{0HR0cm(hS{{(5 zhotQRX?#dpACTs!$=8w=2&4%jX@fu-A(B=Iq!}V%4l9mXhDI#f$KpG>G)(E6I zB59968YGey38YCPX_G)2C6ZPNq*)?qmp~dOl9maiX(DNxKpH2K)(NC}YI41#g#u}! zNZKfnMvA1B0%@j5+9{BRiln6iX{t!tsz4emlGZAa=8B}f3Z%gzX|V!nvPjyjKpHKQ zRx6NZi=^EOq~RiIxdLgrNZPJI8ZVO8E0E@^$rF%t%_ZK$_DsKhGXY797D$su(xwHgLkUP)wLqFRl6EbShK;0U z3#4fyY1;y6+(=rtK$I;ia?$UlD8s|$AaXw2;{jSc`pKaFi2jEK%NYeHzSZogXGl+`S%ExSTIXv5dA3O2tw0_wl9wxx zr;Ft63gq!3dA$O8zM9VikQXeFCye9`3*-?adBp;G#z@|=KprxZmn@K{jN~l~sGONZzwR9yF2{Es!UTK%h(kQno;#i~&;CK%mS4QuaWg3<6RXL7+?mQZ_-Li~>?tL7>b6 zQg%V03$i~~~EL7>co=5rU6g%Btcfs~C9C?kQCl@KU1fs~yPC_{mi zr4T4nft0NfC}V+?wGb$Cft0-vD1(8N#Skcyft1YY^$;lYq4~TAWkCeWgdk-@1j>jYWkm$aj38x41j>-myg4FJrUWTlB2dNz zDQhB7<^(BwB2WeeDT^XdCIu;*B2Y#JDXSt-W(6s`B2b0}Da#^IrUfb6B2dN!DeEFo z=0)>46UxF+AD@7fjS(m#gOrsKC^JKP`#ym(G)P$*fig8n*&2Z|Hb_|;figEp*&Bf} zI7nF>figKr*&Kl~I!IX^figQt*&Ts0JV;p{figWv*&cy1K1f*~figdu&$mz(NT5s* zQZ`7Sj1W>*NTAFRQg%q73=vY6NT5s+QnpB-j1f}SNTAFSQuauo3=&cnNuW#;QZ`AT zj1p2-NubOUQg%t83=>k8NuW#uk{-phBIf*46yfo-IqYtNpWhAGI131r0- zWX1%tV+t~40$DNznKFTFnSzX&K-Nq_=1d@arXYhRkVR9FNfXGXDOL94>+LZLGHU|a zH3buXYo{P{Cy>2Ukiiqk;wi}F31ssWWb_2GdI~ao0@*zU89sq5pMp%EK(8!3NnKN*+HdJ%W#1#p@K}IK(-c>!~2~sqtFKf-1;_3S>hSWJCqBq6#vj z0@+ao8B&2Pse(+YK(+fT1hTZs*h~2O z)>9N@Y{kkQb_JPRf$Xh<46Z;HS3xFMAe*ZoqbrcrRgl>g$nGl0@Csyk6=Zq^vb_p2 zz5-ca1({!sPeT@1K_*xr8>}EBERYpekQo-p4lBqI3uK8EWQql{#R@XU0$F1PnPY+M zv4RY;Ko(g+CRrextRSN-kX2TYSr*7HE66YlWSJFYngz1W3Np?DS!V^AXN`+P7Ft0j zS|A&(AR{f1l~$0M7RXL3$WRMpsTE|Z1+vu&GS&iFYXzBWf$X({47NZPTR|pUAe*fq zqb-otR*=~i$Zjjha0_I)6=b>vvfTkPBqV6=cc68_CSD*LuOK5Ykd;@EnHR{;E6C6bWa$-T>IJg( z3NrQrS$hSUdx7k|f(*Vu7GFUoUm%;WAfqpk)mM<&7s&1_$nXnf`4wdP1+x7LGX4Tt ze+8L;jXwknpnwSwU;`8|0s^dn0%kyf9Z5MUD&FbV?OvI>|5q0CeiFbo1Lg94^OfNfB~I0&!~3YZ6tdjt!ifQb-bBNQ+a z0<44rWBf!ciU}gl^83hcD0868QsS#jn6fiadtPTF2vIwv@3K$## z7DoY-Bf#b;U~~jn9RxuQM}YNF!2D=@DOex{OppK@q<|3; zV1*PgLjvrO0)|L{B~ri?39v;97$X7JNC9&sz#b`JkOWvH1x%6vo1}nI5@3}SFiQgL zk^+WFfMrs^GzqXx3K%B=)(Jnaom?weCtHGaZ;S0rpG> z22FrP(}777VAFJ9)C5>H9hfx%c1_oIv`v6z(}8IdVB2(H+yq!R9hf(b;{^++0~05} z#_7Pw39xcHFmnRzoDK|~086I>QzyXI>A=_tuy#5ycLMC44h)_Ei>CvVC&1?Ez~~9E zdO9$B0_>g+44(kYrvuX`!1n3vaW(j;#D8LHpzzhnogE}yT z0xY2pOrcnSB_l9~0<579%%K2#r~`v2z#{6vBnq&JIxva?tfCIgq5!+71H&l5GU~uI z3b2hjFpdJOqYliY#w~+|)Pac(~WY zOC6X?0rpY{22+5=)PczqU^8`KG{rM(tS-ERU4Y%xf#DQjIdxz>n`B=LEOR57?D!`WNz?cfKraCaE0_>>{45|Q& zssocMz^3ZJs0y&EIxwpO?5Zwbgk6AT)q!ahU|V%yTm@KHUDQ-3rwtZX7eCuBz{cvp z$O^EsI$mHGU}tp)7TX0_S{;~L0k&2bu^h+I#$DHMl^y$klXYcd>;f#V4ot29o2vt( zE5PdN!0ZaJyE-tu0xYi%Os@djt1GnIF2MTgmhN@(;b4JvV1fnMU>z7?(I$#?V1@1z2Pqm}CJqS(kLqF2E}5?q0A9u*#uU^z*q~g*1A>qaeegq;Q|I*fW>wJlP$nzyMWOaV6|PqYzwg4E?~F?SZ){BEV}^P z?E=PIfc16(^R4mlV8LBXuk8YCxC;fiTfK7J+qb|UzyMS32VAoxGf3*v+>@Eeq*#+2kms6Nv-CY8{ zJ2`x?@GfBD1=x6(c0cjDjIH6qm|*8!z|ae@^e($F!Pa*u@!KxI+IIkRFTmb+IEx7u zzeC|ab^$iOLw`)L`W?XR3$Xhg4q$@i?{EVXY=3(&{sOFj`yZH+|Hpm)a{hR%zdXO> z_KW@aUoQxr!(R>`&-E{FFS+_Iuk3&OLL?_Id3d~Lf4TP+*ZZ7!~b%~_^kiS8%wUZW{Lmxok&ht^1zb&m3*({cqOkZ zxm?+gA~{>h(@Jhu_NGVjkFv)_a*UE!lw6|hcafZ-yv#jlGBqsp5*RiPmJW~Brk`*Y3V;MPWH!0&Q0=cl3SC#GLl1+yqV<6WZ#VB#3TrIW z7c_qQ|N3tv=OcL@$?eEq9LeEG-bQjYvM)z+GLnap+>7kd!5T3A$FWFWMRF;!Uq^B# zk|&Yei0s{w9EjvSB-bJPcqFGGc?`*2$etd_QAl1wauKq>M{*95XOP^2?Ddfxg5(V( zS0MX-u*dY56OcTB%>B!Jzs&K=yuQrk%YGo4vzK{#nVXlrK{5v~^X@X&F8hRJPF?2F zW$s+|49Oh1%!|uhxa=R2Id7Tgmbq=&OC)pHGH)$&)v~Wh=A>mFTIQZ*kCDtV%e=D8 zCCh#znKPDoVwoG3y+<+!Ec3oH*DL#wWKLJ+ab@mS_9V$1t<1~HT&(O*k~vqIXO+2C z*{dXTs4{OVbEUFxN#;al9#rN&We=0gamu_VGF5+bnX;cr<}78NQsyRQZjA4}$JWS&OmW@K-c z%)!XKi_EpiJ}sG3k$DuEJCQwGGDjlwA~F{u`?qAyL*_YTZbSBR$sC5vTgY66?CX*_ z37LnGxd++fC36fiuOM>?vfoSQ3}l`_<_2W%m&^gk{eHQxFZ;mcKE2$Jm;3H=e_igQ z%l&e>FE0DT3gd=S=P+%KbvQFDU!ZNP3{B9{T{imBm3Co zK8@Uuk^3&Pr%mpo$o&$zFCzQf*lgIPOgK?^=`SYE&Jr;I<;Jnmg~;4XHKpo%k^TpE-d@! zf}19To0A&p0dYIu4BseO1Um6`|ad9qg+pv>xQ!T zPObyW^**_-C;RZ^I-OjPlk0A>Cr_@U$@Mb1E++f)prrFPp;$0^%}V@Bm4Q}I*VLSk?SV1w@%jnIZd1Z(>?lWfQ zrR8z&G4HoJ{m?^KD#K&VM z*<9k~y2CcyKDmBad<^D^W|QNiFb|v#(0T_Wa2uVf@xGYoSdAZtiOyB6kC1R1oviUq zG11W)Uj-ALt?^hB`P)g!(GeRz3lp8O z@mOQ|+iN%)6P>d0T`th2+Zo+N@)Fv6>xje+j5RyKkbxIqLL#6^GBPiT5n=3Zo5yZ?XY65 z-dxWy1~d75L#os1jT04?4SC49^^(@Z7?cW>7F&?u?VrNHN%!x0$ zY5j}OzvKKj@9Q{)`F8jK#|q3!=D`lEQT^>@?22hTGtyBGbL+D)j@RgCyk1~}*4G$~ z+YN@gJ3KLmM|e5fVNQwh)p{J$v3_*@aj;`I=FfcL4l`!WMiE-SV_Dn|3AZ_(e!+E- zG{tcU^Zxj0TJK|D+|D(9rlSmI=~A;DndpJ6vn^8VgAB**UYF)M6wJ}%7C7=?`n+AJ z^+YcFY^OOTmN>>>uG+HHQ4Mojn`K&mogK5%5rBE^^(sd*%=`8=TCe2MkLUs1 z6zecx=5D>-(H67V`3+j%^Bp#5t}1^3zMK z%UT^=s~aivCH*BgbG&pZ-rAU!UOo zJb0@0Zg#@${<&T_o;=3;YWYh?Bxc*XueCnT%a80-weLGe0A`7d_l_c%d4fJ_J)Qm0 z*ZF+uzmC@r@%dKkt79JK#be*J{?5b)cs}Vr9g{Iv`2TkNzK=f5KYtupW2XOlJzHY# zi^{GhXV_`W=p3pi=9(HgwZ6}l_i+Csxzr|@CR=Vb@vfZ$dgRf1KtH78eQ`UlIvcas z#(Zi8Oc&pOw0_Xeckuc2E5Ca4HjY2Bfa-~vdr?8HH+0S|^iNhTtd_&P^}MjUJ3b=yf3(_l zJC&VZM%{4@-*;G9wK?YdO6649OWH97-)~=eHSsDw$091IeKFT|s;Kpq4!eT)@AXRR z?PNQRiK(oP#q8={Me8x0cp3elU#hAPlkD_MR8uEoK8~!e^_xz*WT%7WYpM?};<|ZM zQyq_K+g(fRJsouc=S``j-aK!o#(C?igD{Io-u_W3Kzy zKAX6-UfwEomwXK;SEH&u^sAm%wBFW($I!z%x}#bF^GWqi z>hz=N34Pf~>vJ7+#7>^pF6yzvxURZ)RV!f@Ez(Wvd3|~iy|e4PtGzMjdG}EF9I(^4 z<~_Ck*Wmqj%6_(&dTk#*|K|5rTVQS))yb^{j_22Ch}sO(`0o&P?lxQ>VyMw&}7C0p#Yq1*`d`DW|`WRB2!XQMaa^EY&q`g|jPPPvR$70g+=$7p@DkJsb4R*Y5K zV5UtNr_Nc2_h;SlD)z+w_SDwLtR6Q(HLb<@n>JCs7=zFMK9jWmTF*6hs(){?dU!Q{ zK5ubVvt#ZIaMOBiSFN;Dy=)%p;}y70&U>hhF}Fl{YJIn-mf?D+;jQM!On>RE4vxm> z^I;#Y2lv4eI~DBir`E77@g+75Gjvmn*7&`#sO2Wh>z z*%sjUo_Qf^r}_A~Iy6+BHV;4VD}`x&y4mO2DQ0iD+Hnqk&KUHnEfTM1M}vwz#lJnf zUuWU^Pl-@lVwPHMRD)*X_l(IVt$+9Fbex}0X0-}tio>Fgnuhn^Osk4L%D=t57pCC6 zmbR;Cj;HDO?P?ployrWIqV@G|vZ5Ed;#BpP1+V+mscJz?pC?nb9^X(CeqQdKrfxCf z_n6|-)wBp)kNW9azi&GOu1A`odh78yyJ?2HG91UBZ>HA!`#BWXBrOH0wZ9(`vnKWCy7HFrIiL=#T0XWY3k*e$o9_Wvs4<94d2tRx-kC>yb_qCHF zevZ~3{Knf(BWBE1OJZ)$nya?=!t2p@p4KZo-2*?jO3hcdx!dW6alU%d4X<~`e64S| zuq*bXwk}YcOvdk7`4_4KC)ufI;6km3c+muWKDAk-?j3KZ8ZnF1q;cpu&bCYE|>Jz_w#nj7=Tp=hn=xY;0lE?AbS-3H>id$3F$J-|+e9Y= zp1~{BEq(Cw@#YFu_97?t!v0_EN;S17K0k7-QlIv~_2{um>r2kr9q;=ltJR|2@bybq ztChOq?|?6>wI1bGo$b{53FQIRB9`TEFr*1=sVSwW^2CPC-Z3ssS!` z+FdSI>s_|A$Ir*iSan)E{Cw%YPK|79r)4|WX?@I5t?iUAbiEqg%1#~A)~hR8;`gWy z8?>J0nC5oM%DGWp+YGOp*G4tAshx%;;dYb%^*66=jPnt_NsVb_r!QYOsjC~}e2&|! z^*Tq_$M>tXMO|FaP8a5EQRmmi&#~8Aw7%zQwej=e=vLKS3->F(O%1P!=WpAl^+3B< z$LB|n?dsTS`2BR(c6CTqyuL+tsB)i@D&un}ZHL;jlAX%A>{RPk#Pzd&r`8)?q&%)m zuU%^Pa(I6x?NUFM!FASjx7H_pvlOo1Z@blmlDO{2?NJYxz~}9$Jt{I4e|x5*irFdW z+`X#3D0;=;>{b1W;QoX6Y5mh(3*q;l^83{$1@ZZB+pm@@V5jey`&HRX{VE@hXV(Gs zW?nl57CES@dGI_#4{CkY^K#+uy$*-e;GFpVVf`U>L=JqO<~pqPSXa%4-w%=wtGWKz zXj#)E>a$-qIv#yQ>$l$Z!$v>H9#!Xmw^5~2M^*oCHd1OG(|WHPezB4L^)a=;zcyMo z=(zg)la2Vuajg$~^9S@hTTiG{-rJ~L<_UG|JM>O>k5gq&cCj}$3Mw40zI z`nflz+Nke?(`w*N8%^kXMs>Miqu}jlwBGI;DL8LIXVvvrZM5~qS=Hx?jgGcW(E7Z8 zC80k%TcVnH$wp7y64iwlZS?7UqSo_W@jSk7)H(H0BF^vUbL#d48`U3mUhDsEcE(1X zt6fk(pR!TEnHSXKCv7zH`2`gjp})Q0I<}GDfs5*I2cCDSOR9*skkC&-*l1y= zB=y%Z8!g|Gq{bh$QOrM=RoNrn`ml|5q+C`%9JJBiR>|t#12#IeDp~6nuer}g@sqBo z8GCFb60WE#cH8K5y{lU9c)p$JEq{MiJ-OXR=Z2-I`fcbTKaryKk!Nnk?Wxz)6`L@h zTvPjQ#Ql0**LunitwT?Gu^Xy;?0}W@+lUY0kd$MK+px>XsV4&_)rpZmYDwMgenf zYdz>o=GtiVpgU@ZIW`(_0^?reP-&D<1U-;W7=Zs8srk{;oKg(2QFMGT*wmGL3p1I zdZ9KSXd}mw7g`_uz#cuL1J||Jzp7_-d=4c2t3Ik~qe)G_sN<{r zuh0H=B^!PD@rqmKV&rN|Q5IO&I#JiBFMnVZ@2)k-yY zWaFY=tdu=H8=F5{>3+fNTJQdV4^~ivyy&ecCPvsk9Wh_$N%=FmGZaE!NXrz z>4|p^c4S%Uum!(Vf9 zYPyvc)X$~$`Y*qQUi^i*_;ae2N}kNcLvLE?<$Gt}f6;3=zG1o9@2ZsoXXoY%$?yi8 zaC!jjm#p-zVjjM8!Ac4J^KgsvR$4tJkLCw>a@I(mU6^y(@jNpMa~G?XGKv(@JPE>RCGXH8{L=t`!hve< z53ypMwkW>{vXbIglxqg!I*fIC6_)#2X;$`Poa}9-UM-4o9xq&P?!`3ULa5t+=cgF& zm~5r~--~g^L@O0;Se&JYq5C*1EnHNbO=GOo?^JQ#J<3W2KRW#kMTc8y&hQf4X{eQY zM3&&-!B)x@=kzvQ>2F0JV@dwq*Ge4*l;nnetn_6{NzLalvj;pAk4y4_Zn&;Xm*Tr! ztn|1?Db4fHtfQ4i?kdG&6nGu(mEsvLR=QNUwB~=f(bh^XA*K08Yb$-)RGO=`veNFG zrCE9*{F+&*e7iCn)x=6EK4thwBP-30arz>D)PuL;PZ_RM7oLb_WtnPQX`E|W%_A|T zx|I?W%kuiFRx*Aq%c8QC8r3hyGWYhQyp@(LD97c>;e8{@ajP$ zM;60*pH-eW7O_(NF{h8>W&s>ug$n%oANVf%R^Z(E@O^9*G*3l~TvodIumbnW0Uue3 ziab7>m6~>|sQD{q|FqED?G<_TcX%T1ROCHhEtFZH5_(ww=e0=rWTAF}l{oW*g&wc3 z#2??`->*4+7sX%W{;eu=wU-u}=UJJXJhxEGRZb5^uP5+L{H)Bw9$Bbi<0?GqA-ob3 zs<6!Y>F-&n+L8sRo}tWTB9oHTcv43l+^%_{vCK72U2CD*Uutp08VjAQ zTbun?S!mSg+M4%c#4@}-YHjYb)I!zY)@CKjLUC2=Xg-h{3oMj1y$+Y0XCd2>I-Gls zg-SkidP1Jeun_gG%QvRsyqoLt=_wZS+T-+xthHEZanX7_*JPm@o$Ika0=~M?dYV_H zZRYW5yZ5(H>flD2&!k3g3%xkfh_m;!Q0TKpoY4(ll(LOA&&i5T7Aj`^UO#uhr=t|=F3XrXSt zO*LQ2i8?s0^L^tEx6>6@9h-fPJ|U(8gcNGr|X^7Vt6iiNad^_`jK zY-+{R-k2%-O{dqTzzZ|IZPS{QpP9+syEQLt&E^wMI&zZi{l-lXnvb9GtIQ&sKU9Xn<-b8!n>!K$)g-;-ka}cGu5*YuQ%fL*+bmTV5S!t zP9M&q5Hs!Q)RCJ9;rxbnD!sw*Gv;ebm0oU z&2%iX3m@rWrowSf56{!iW{RuWm8~7kRJ4CrE~(%;vUk<|JRRHNd}ns$)YfL2RH7UE zw8ZPzwVUScS<=KzqqcS9nvKk~>sB{DTHj1R|LLyzd~Vk=(^|jo>|Mi5uh(|xZ&l6Y za>eQSDN_;WyIBw3T+U2&U3+lzGG+>ocKUz%6vy#?>A|T*%rv@gPo7i=?~_qIS$cuO z^O>oGqbL8)ZKj#8d-ANDxK1ng(tJV7f17C1)LvZir-^nP?8O_undsdkr$=bdCllGa z_vU6FOmx=Jn-9M=QT`oHzfjx@6Ga#3!!B7Sy5-V`)h8yZ7|=)a4yg}JwDBr#XPD@5 z_P*>$H&N{teKjA^u~ZXnU)Gmf-Y`*CVqZRxVxqcVot~oYNhaDlx*u1+h_9d5k7Lfk zAEY|{MGH@xD5gq(&U4a4w+HrTn`)v`)B0;(Bj4jDn)kRrKRjZhgi-@|_#qSh={`X7 z9noGB1@9QZ2Y2E5-x3^>hvR>U-jSf z8N_W?m}s=yAl@8pqJ_(x-Xz;16MgzJh+oXd{pto3!cBDJk<-8A8Dyfy-G_3LKfb?VC^z-R zac&>V(#!P4-9&fu593j;Cd%V7jN>PosEPkD2FptS`I@X_Of>b%Fupeu&p+F6b{TG> zlxD*&$!^-d=G5$E(i z-RxkZj+I7o<8~&R+yvBHai;v=m4NR1?>nP0=HMcgt ze(NaCs9~bpLSgvW(+5uZ`4k&p2-V(nv!x#%bQF(@%_~?>L_GJu=el;PKq= zfss~jbo#7r-Z9d#TobtLEqJe5P2kZtjda6fg66rpcg09=&rjgWmyPuE+XNne(Mb6k zOw{~Wch4HB@`8z6{&knU;rS)I^1~%Yiu~jBZuM9I|JEcoHqOPrFLC2tvvI#OP9ImnX-1k+%bi{9Mw&X@ zoqa7vvdwnaJYDDYIDgOG`E#g|g3Ehw^F^V%*(x-i;X^MhsTjI_()%{e<5Y0YbIuG!W|b1VC3-Y~c3M)I8E z!_%AKydUu44GoRdInzh;iQTPjqzYYq`CAPm_&Pd{Bd1J z(7AU`U)lJt5wvh{00)1LprGjiJpDri4L*Kp>?}} zubUXm0}>;sM^rG6JQG1xPCGqm*r}!D8X+7I7eQNwhH&_?2r|zM(fnys4#1c8EQDw5 zjiB#kLOF65?%y+%rB`jymIw;l8Ol)`BdB|NC@)zTL1hbuX}-1SRS|T;Ka8W7M^I!e z{(Wf#jkx0Uuq|4E=iM}%7tD>IQtn zxznuq8FHyMa=M+IY|x15KN0<7S@>)cmN^U-$Mk{BmXN zoczK-x}J94^~^voBkY>j&i$c*y56yKrwju{ zJf`sUWccyyP7hwo^9DM%ZwePkFi?f_Q~2R20|h*A`tcUT8>mFFsXXbpf!ym&287~mJ1#@`kiDAe8Q-;0VgP~qj%ciA_EPmeIr{36r2PdFa0&UDS!cPGF={v)UJdS3$_51P&%UIxlB$LaBVH_1TD zPE6;+;|+8_WjaTUF;LwXPQTx;q4>J;GnfY%C|ipeZ0~QNo_(C&zid4Xlxm*AqN{-_ zMbBVcCj+_dcKQInwKve)yEFJ`8w0iaJcC188pu>=rsfHJ-pD{Xm6^P`zJYoSpULCv z7-(LA(;s-Xs)35Ho5_)t3^eT6Os4V%T5-kc72Hz-uUocR>{`@7Sn*>#0}FY%X_8PqPj?eTIQ4diwPk|DLR; zw!dcc>5F;_DHW-C4ojTX)3a`o9CuPr)y7BiBvntN^-llco}+q7+8W7&59ukFh~zK( z^yHEj$S^)AIc%G)r?cOje#K)`^wgmKTpnW8)A-JF`HfLeQKOyS#pN;+;Om>F#>uq2_Y=$$EO3a~|&>ucrzX=V_kC^bvY8^_|Co zL-n-NZ64&Z1?9{1~l-U9Ze%k4k#-e>R`rm($aV zKTbbnt`d5B-edvKFQTVnJr{7vf_iE<(dmt>o?B0mix=>Y?0VX_eE~QA9Zsnyoj%F7 zU&5*S`vvUy7*0L@S;+J*ocyaT)I5`2pNG@YK?^zINjU!QUC7-t!|C@_r+>10dN_4E zi2qLuC$EbOx$BK^nwN>MzxqEfC0!1uE5#SF<3c#StG|fbCWce7E{il@C7StZNa!No z5g$&W^A>USx+2)9(?`FMVxDAI2F#dm?f9{eq%WGZn>B})`gR2 z-^HB1CY)xtIlY%>qr*v!Ud(Nx!s+(z#k_MtIDJ0r^kFWT6;2I4FXrFV@H`4daiBe% zCf175JemC>!fENSD0YN}({BGLt{)su2{WDk%v?TrydzN@)alhc zFeaP^mtMjZMuwAj<0U*}XgJxsFVTFP!}^8OPW=*g^a>}ja0%Dw9!}S{Iz60k75Fw& zm+;UI;Z)@952phcp&Q^9b0RVP~We16XrPXCOI=3&{xsZ3Bb z@BbA>H6xw=PxpVrNI4$O{2`3`T#e>3Z^LLrRy0d5XyUUl3MjjbD?JV)W7B0E`XG#^ z_jLL~E8h;I6%qLNn_;wJ@iIP_5=J|>J3XTQ7sDw2)-o1}VRYu*GA?!|j4tI{uK7g| z#)r}Ew#zxk@i2NYa5)b;97a#QoZitlyTj@X@d$LTNio)Si7Ppsg5 z7I;ikR`BNt%;!$8sXZ9C%dO-y{1-qT)A-|4)`VN}w%k}r=BqvBC3x$u}U z?B6>*sEdY#QU2R2Ie9=B<$1r73-t}79RIA+{HT##!{}SvRh-Z%`k*Fs6;jnVwBxh{oLY?~Nvd@ht042Z$+?^vn!bb4QR#D~(z6)~K0ER?$Mi{Y<_ zLaD{M7)ICLUmt9@-Jw+QOAPyL52de#*Ycvxq4cQsTFn!i786Qw!`Jfnm7%mbU@cc# z7D@|et=0Uo6BmTiq@!zj>YPyOoxGMe%*5kAb$VqVSVJji=~(`445b&1V!5I|lv29I zYQEXw0XY8fSPt)`p-Sg(0*%T^7gK10@X-HM@9&v!kyEgMRCr#t<(!;6N}>4WRptstJq z#q}JVFOlq!1f4#W#vV~If;v0DR&k!n9e*+7Uu~DsR#} zz1cT}(4hXC_)km-)$rKFKUap(C#%!n`)P3qE#I?=-_8#qkAzM9A~J+p-*b9>Gp2;l zje?sw%@RVJYHsE$5g`=pvRU)}a!?2r^xMow{6gsV^v%4>D}=VLae9E4O$;IB(q^7B zHiZ6pw3)3V@p#{zeqh&uA>>_u3lHrJzi{U*+`VTA{T$`=2G{8rLJQ|?;nFT4Gym-x=_V0xH)8=v|fOq(igI`^cerV7fg@OY~zgE`1tM)zp?#t zFx{=bohMufrd92?vo0Z+h7WdnkH0yBDS7I4PCXt>b5?EVgNK8u>j9?^*?V^|op`XF zyKWDrkgwah^5$S_Sab(VPx93@@FUX>-o7H3hK<<4Q)eAWHFPHj zPQr1{+sV?yTx3)*y^h<-8AF3<-L;*(dtfjPeBtyn_vjf+2g>c@l3j6Ln(g8T6ih{X zIlayLHo+7Sv5Pyk2&RgQcX5Fx!E|w()8`yhJD6&w?P9m;!Ibi57dNaNOx8TRHP7>j zQo(ei)o!*I3nqKN-Q2ZMFx7W=`k#|>;r`LPc~Q1ts4i@H7=--v zZeH;=h|cBT!y{h?QDF5wnlCynGl(36_VBWdAe!vGhlkz?qP$a`9_i$iAR4rP56`_E zM4!*?;qDiLXw`kEU)pgpi0&8O%X&u;O{=|^n;s9Mn#x|yJH26F5PACVwFAnG)3KYYMJbUV!H!S2u#$Gv$!Kj{)g>*DwGLJFc**PVXs`>lg$VvYkm zt2xe3xdYs&aS+XIc0luHn`#Bo!HEaBO0^*B7IA>jR1Bh9i<~~~0wsg!7a!ogMS^Hy z>H!{DAP7Ejr)PU<4jfmdgWU3WAYE;FkZ*hoq=|i<{_W!L1IcDS$opRfQo*GMxqnt5 zt=f5zrI$PMejpvbeUNLW2U5rP2U(;BQc}J{ny>rQF%& zNb`7)a0F6;<%jsqu|VuUAL5yZ0;y7h)9-y?XCO8Dbcnle#rG+2nD1-|qz*L>v-E!F zSQSV;1|R0==s>#ceVA)64y3_Toj&khvjb_&{=<0R22#ek!|ZJfq{;W4p77b>f#g~E z2$u>Dga`NtZ}JNyU)>RweL4=;K=SuH!aXMh((CC*`1)wvUUNkAif0YN{VyKj;C_Mh z;^7hg-ZPNAzBzs4`8x)ZYu%%~q(dM*prc&2O(2aO;q;K#Y#c~KW*z12^#Un*?NM%2 zE0B5}ar((yRtzNF=273cHURI36I^mt0Ck^#f@ej;v%bmcSNED1Ky$C1 z;9Ii-==1Xv+;dt0O~@XndDm+j1E@vQI9?hSKx=!%arU49$~_@Y^ReId2%yvjaolZk z0O_{G@&0iEwAtbGw9gnCK*2BL_{{*^FGoBN?-M{S<>NJfd+pA6yk7CVKo>yX6XW?~ z+W<;3IKA%NB!HG|jprH-0_c+(&$DX>(6F2Fn(w`Tr2u$t9K64502wMcxOm9`N^9=W zJn%R22hg%f4sMwTUmxM%rP%{$@M5PQe&APsDkvPh_oF{~r#iU6TYpM;?exZ9rR=1(7Uv*w@A+T%~_S~BZ)_|xY;%u$>Dsh2CW^wPIk<4+%=nCC9{r*1o#)1&-p zWn-WrMT`?5;xIazpD>z@UKV5YdJj~CZs+ygC``45G zN!=m1-FSa0a7yruQT{aYmeYG*b|Aigo|8POk3T7uPx8+0{xrAMNk-Q^p>v+w>F{`N zCwWR+fATS(N$MZjRl9$)=r-ipp@|~*wl=}80%Ra1$W&Fvl z@+sa}+@E%}I>nC*`P2Kprx+dggsyw`$c6K7KE+%A_|eHFr})WtKgzxH6r&5D(238k z@BL{0ty8@Il^-R)J;fQ%{HR#o(~Qo1LU%q7&+wz@R;PK%Z9g3EX}){|y<2XlS@v*s zy5vX8mYil&q95JZaheaF@}uIXPBS|A30?eHPw}ILZ%^~6LwX+v%3!@*+taO&&hWU}BgE1P*QJN9y7PURB4BUTsTYI1C6b1Abh|k9wsh@IU4J$nZLW8 z?mRz<^`$XQ&$H}VE4s{=){Z~VwHEslho9$m^L!~|{&|K2g5ZMS2~&NkQv7)ivG`Jl zYv*}}!IwroKhJPQ5S$Ub)!&z*%Us~2UcPjo@dZwF^`*<*E-;)D1h)h~8s$s5!Y=Up zp}tgQ-Ua?Mz?a%>yuh;Gt!#H+^1FJ0Yj*Obna?h86Bl2K{e6Mqs35p1xJz?9Uc-yr zuaPf3?sAcb)%B(Cqc1XC76hjSyI1z5T5~S4e>q=jzy2bJmh`0o$1XCQ7Xeq2k=vK%{JhAK*?cLc#3h!!a*O`;A<^j)N4@uZLiJoAVT>HU*<%6=c3IwOf?pI!J?A6j-Wi32wHQ0#>y_KfkNZ4Z(djt_$CgGVm$ zp`(Q_^MD0D#I-JS_edW)>vEal0wFj-xS0*d?Q@xH8-3{J)XQ8U%m@Cc%M51-!5zXm ze0(S~@iKpQ^PwmAF7vYqK9u$8GIB;fgzg@`ILwD$RZr%)fj;!QT{7?N<3n!-CNmr) z1Q!X<>4a%ZW`hgk%YS6KGa z_s*NPzPZAMUwYHp+*kSI6K{&Hc$MK&AvjeyKHZz9^uEfmsooSm=_*f2@g|>$s|@D~ z!M(y=&Uw?|tyj6`X>aPLUgcb>H?_TSm1S?>nS6o%`C;C$h2bG&Kgi4>kX!<%MaP2tgYZwh{v z!f?V6+%Q})+?#rpy2g(Jy{ToxYaHj}O;x&FW7${eInf(@%{A7I@us`8uW_;A-jon~ z4Zp{G6I?SK*9Xrx=^8KS?oF0Q*LY$lZ<_r58pB0HaMEzjHr~{@?sdM=%$rKkb>7m@ zo4yRY&T!Tc+%?>_x;KgG*SUBlZ`!!}IzKFf<2-PkWly5H5FY3Lb?%wZo9g|0olEBQ zru>C&FdR4p7Y^_I>O~jY-{7#1UbKDC4OZTGVZY@D!<9pD=J1tAUetN{4PKGqMOF6P z;0d?A=*O8G45tpkt;4U9z3AZk8+`DB7cIzllMQFR$g9dtmi>&`;=HIrzngsKuor!F zy~(roc~O$-Cd1J~aP@HhEnZ~aev^~ddC_2TljpDYqPnR!87?1!(}xQ#_M+=KQ~AL>F!0{x}-5&Lj>m#pXlI44}#J- zu(cQMo}I?Ent4$~Y#PH!1fO*pFRblFg_F{_b2Trzm6^t$D|peyZ)sW|<>+Ew)UwVk zE?Cfue(G+qn#YUI4!y;291&bcTf`MoFJ*S8ohB!Ux()1G>g z=e=7zH$yscJemE!9;K|@zt%Kq=ETjKE3X6{`sC%YvLW=JIj+E=8j2u+4XPnckC%#NXjI!Jc$JRMJ za7wX92Tyu(IGwY%_N0}U(mAH7C-uopXE>(_?kT=n%aisMxy#;FJ!xX?yPUm(Cl%A( zW!d}Ltf(gi`P}7m`8}!1)Vn-Bwp{~# z+-10~2+k``d+b5CtK4Is`yMo-^*#Q18~@(#9>a-6aAR@hD;_k}bdUF5@Syrp_gHt< zgRX76$Fgs9%n1*wdh;IE8$9UT%X_Tf>p^}wG8m36f@_NxZStUFO)|JbtOxkx4BooZ zgZ_-oV7RylPA-mH-~r!p26v70pl9nd`0_LlnsY3J;q0RN$r*gl;6WE3XRup{2l@QS z;Fo?Ll)w0WmOZCmCV5Z~y3dxe9`t0`ea&S`h*pZt(x9PV`Q@k5rqt}_m})0bkI$d9?xjJlcZvlWj+nGA;-!KKFi*SJ${ zzf2a(-08ryOm4c^o!YO;WVqG{&NVJF)1CSzX0pxhPB-sn@+%{b?_(yz$wqLq@wotZ z@~QfWTY9_GyVj3*y{kKg_j|;$PgXw?$8UPX4+pzbj;Kf6r=L5`+V+Uycq6#pxKd|# zns?(7&vbF8f-fKO>(=hHAp2v63y$D~uj3cx2jSO1jZ z$RoJ&xcEXh+Oz2?dq=uarMRaorn%Alt4|p&J%Uq@y$x>U{p%@nup6b7c*e#2+^B2) zXAI{a!M(@FCgSTxJmdUh+$hrj8IKv}Mjxj?W7*sLtCt&{+y9LFb#LB5gZO3Q-9CqBu&XdF7&iA&8Fjc$885i{zdp&63mlP((d zTRX9F$wlLTn>%s;>x;(fb)882@uHzwlhDjb!(>$_w)}U|2wK(&Q=3ah`I1g#`d>0M zlM4p!;Rx@77KnbGdAoHFUxu>aw9(n9xj2Bd??rQ=2avkLPt_^Rt(Y zX&IfkHvO`pnVHb+Ok-<&CtAP0Y@CSf#N0iXjR(P<*md%<(Un6T@7alnK39wi=T3C^ zT``8+>v2g}49(z#W^o$tn|I>Y<5!H0CY`d@T`>;a?Lh6^D~4uuLNhxJ)5{%L%PWS< z*$(`5=!y|}sslC`t{9r>3C;F2nttuTQ0J@0$e%m#R>W0f>YffT`>N5Ef4zzwaCqjb zVQlO`>MK``{aC+r%D=m2 zbmeZ(Ywy6IgV&5DjUAYJ_L{Mxx&uoeT{ASp6q;pfY|8Jz$fokBBDjl)qLsGfS=I2O`@kqfUIC;d7wdXeO(1d4D^${d2>(@I$-iI^QtPZg0nFyPJk)wnDR8jT0N%VUc#z zIQC_`a&vAPhdymbz>_zPuAK4R@3$-0?5440VLQq{y=iQGs~yc-ZyK5b3(bNxmQQcT z=u0<^#Z%fbvBxdrt?})6)%BL4S+UT}Sk=?*csKW!G3v>7EN#AJJU*x$pFVrb&`eoq zwyaTH-;Pa-Zy9No?f7o(EhDP99Xo%xWpw46+o!i<->qAQX;M25THiLV#F^0@)L&0cGo`1Cs$usU4U3u>2FSWsQ z-5ukf=i1aK==o2#;o-?UhGzUivwn>UgWB*%@4H4*Ya90X-Zci+w_!u#T|={gp_#zO z#iBOM8GP5+ozsSw#@#hOL>r!%eb*S5*apoGHmYOWkoxUiBP_fP0SE6IJp$WcbM~&$ zl_US9Ya9M_xMxgvXv5Bsdqzv2Hhh|X&(I8FXcn>2)3goG55H#|yVr`QDff)eZngpo z?ird@49zSys?WBEJOhGrx~vyu(-C9Qbwhx^8X z1+Az!ao>1vPAfuh-8VE#8JekVL{DqQA3hI^yAxZnZr}rB+t^mTQS!jh%w=fyvQagn z70F{C7_LKFVK?i6aiYBy|1N!Cbmis`uWrSx{W?x*D?0yuVBE}WMg08-hGsZJvz(2W zl3Q^k@S%Zty`R*FhG}FgUaWd(Xx1|dpLl4z+`knr6CWBm?yWfU)o>ydH&R10hx z9vPZ34b7T1p7^x|OQt?D{C;l1kcE$oKYnOI_!o~1&7#Kj9gmDMqXip|Ju-T3&~dIl zGPtHi`-KTLvl^OR&G2O{802EYQ;S=W<7dJJ3tA8mX~M2K0o`72!N1ui{QBh<>?||k z6BAqHS2CeyU_-O8x%XK;|7jCW9NvPgaVCs@yahhfOsHAe(9CSkZfLNP=nvs998#QZO-)A?DpV^Enx4O}F zdNa0lGv$WK&3N0|l$uEn%_isd(alKdZ^~IuHKR|sDMN=gwu< zZbntTDd&|o!|yRuYQ{M<>zunXnz8)_Q?@5JiPiA55v4>Co(SzSyT3iTh01$D$eLM@{)bw`S#`nzCyS#I74n7=G83 z^_QA3(5ySpoo+&R+wRm1c4!tmt&TO}9sllJ_)8N8MRjNJ-X=sOcc*5xLo?f%yQK+R z%e(WJO-*>MsXIH?Hlh0Q?$k_oXtq1YE^op=HE42r^=3dp!#LshkP_yo#nfJVQ zwGri?^x(+zjj&nUgXjNl#9pHZha7Lj8{hZfU%xh@=$9UB{<#sBfA-+v9~!aqY!7zL z+xY(5Mr1td!Ho5dcwlL!xrdF|9h|M$17}?o~ z(eupMHRr>wrV)RyG~?vbM!fsA8L#9uqUt*{wq-P;*B&$OO=`qA~*NEp%nDLYF zM&-Sk(J`a4fyT6IlJbX^q$gy*ls;Jd|U%gSoP$d(G7URu_uF{YCw`tPrfpw z0sn^f{YJz168fV7UD{0#d2u%5I?)Z?G) z$&Q!?Bv0z>>Te}6{SW=G{hgtCG zf_k_=XTiWZ^)Mz`aP({SXnW0qoLUc)w=HNjp&lQ+Z^7E<>yfd_g6}_FkCR_p@Z1yi znEaguV;`%B_Z|z5Z>|RqS#W!e&g+B)t;_21;G6}!=EuB~QI7-@OP)xo$KhU<^pC5@ zsD74wGQ1wP-j@74pdO!wSn|48J@Vr%Il!eJf5Vbv?dvhI(2|?2>fu^r$%j4a@pYRe z@vshMPg-))?K+$tZOJWH>g3n7WVds5@R(uA^iy?M_m(BQ=GJ_Bs1Bz;vE;qIb(px; zk_o%(;6zJ~*;0qkzPIF>O?Alm#gZ4ls>AQcEg7`B4x`Rm^0ANWV0pum?=7hlUuDT( z7t|rnvKMXV)ZzQSy_o-69a=qmanjT}Tnp;O4KLMUT5K;~ey$F#X}#DrFQ@s5I%HJ! z;_S{k9Bk>uolSLkd}uG;tFFU;&-P+uX&q*~)Qg>Yb#R;Bi}TX!@addh+?7~|)c1Pv zPD~wsTHcExVS2qUd$GyC4i`7~;_IGucxhKJe&bXJ>jS-b-nI^le(yz>UUdjQt@G<% z2hG;tnESQJx!;Q)-K@m{b1Tg+two!i74My{#RWGj2A-_N*Z?b59<7C0v=v`ESc^B4 zt+@QhTDa$0asQ55EHAg>9itX8O;+r`p%$A5Td{CWEpnf>;t=8v#i)PAE?)?THIJ_#mMQk82`Byt0&i@`z9;C@M0}q+it~0qiSKl&q{=TEfyTH z;)%hv@cP?|rfs!YcFBsq^|c7SW5w)>T71#nnu7{!5#Ps}Q?qKZ$=RA8rPLzL*P2`7 zYq2%lnkOQ3UJ2IhnoH#7Q;XsfYbLnXVqcv#tNYfXqSKmBTi4>?aBIG1R*RbFt-0)B z4GvGXCU4iE?saP(xl)5)-?rwpvo)yyz?!{I)!?^P*6jbg{=UwdNr&|J@2pv|w+6L) ztT|*?4SqRf&6mEbLFEZ+cFjXt@nsE4Z%To&ss?)=S#$r=8szut%~S8yV249*-g>(R z8D71$-q+yU;NEn7wFU`sy%{#824AK1X6m>aL=^O9$>`HH1o9T7$^=99P)tGPA zhpxA)VQt%oK3A$S$+Zsy&sGc1>BF$Usxc(854+|+4fv%R#o2wB^iwrh+J~t-s}bGM zhv}@whmZAP)`n_0Jk^KUYpU_`3w@ZovKlw1^kLpd)foJSe!g3cL-X}>UNv$))Zb@T zW9_GXnDa_CeAnxFld3UiOCM&8t%k{ueTZkP@zmiy?3z23FsK^&=ld|Wr5az~?8C^~ zYV<_k~O>8xi<7{XVR*hw8Hhkn)4VwZR z-twr%*eV-dbgaf-EjB!5Q;njbHaudX^Lo~Xd%IP`{UsZA&AVEEy$Tm*+i>NDDpb8| zqxtq#s-tcA=J6`{tg+#gU#sxSH#Qu-zX}(3*l_Uodfa{+)@-f9hNCvj`KAgU|JX2o zZ51Y8*7>fk!asLxX#a5)3VPVmWJwiP_p#-r`BkuWvE{Kht1!yfmR)nUzM4{nfeE%; zJgy4wWZLr8(N(xxY|GIjs?bzt%ht!Mu(`vQd2Lm2A8yO2`YMcn&X&#^aux0@vE|osRj6BO%Z1@p_)=KP$03 zz>bN(Riaz89i4x!L}RiYZ+~BjuX5~oXlo^`%k4D(y%K{O?fB-}N^Blv$Kk6h;V{yU zU310!mQ-Tv|Lpi^ekELH+VSX{l^D6ej%#17#EuW`ICDxRTvyw1$TRM3;;+Z; zS$($xQP0@Z?|KC$j=++H=+)6&SkEo-Kzf@byxAhU}|=>F4&m zwW|W98|~ROM{VZD3jF(%JsZBPK=g0+^j%ef@qgL#;zt$Ob-|wN->rb%ZF^3fSAnK( zeVISA0?VxQO}&v{T3Z&2OOUvL2yu7F{ zfAFcm_sjZnhHC|Sf6r z<cCC&%Q0`L1D|=b90#6tVBo9euzAUWe@re% z(JKy|^I|z(neD*5QRUdS$bt8VmE++u2X@V?d#t4#qc=IQUu`))+wQ>KrR6xY*MVd6 z%HeawfuZT;XguY>V+rM$d(nZfN0;Nr+YU?)DMt^}emvj59Ld)GxX`T}qa6D&-=Q2U zz5DT&wcbxiKYnCZu6%%gEPq&r67=K!TVPH44bF*tk>jn(FlLq`yXFFZb-xt5KXPQr z%~D)l?Z`71OX0G?k(2)|MaEV~y8T&-Cw_F~SHG5G_F+dB?=QuM6OR0QcPWmabL6-! zr7*kcNc&Bt2z}(p63Qv?IQ)VWUvDVIe^Z?3URes~ zH=MYtuoQ{&otTtWiiQuIxI4KNV^=w`Hm(#4zINi@VWn74CqC`3=YQ|S2Og#3p`6$? z2hqW%6j5iKxTI$(O0GFE*rXIs-gn|x|CQhsb7!VpEx|{&&fIaf1cs|KOa3asQ9oxM zI$DC85zcHmSOVKbXP(+qf{-j{KDoUF*(J`rvbh8;bO$jc~b>?f+OJKg(nY|~Mz+;6oXO1mF?3d28dA0-vo1OXQ zlO<@~=}giDKEG#gNY z^VTk$98sbiM;HG8+()kx_=LLfhLc_=-i1%u>iprtGZrPNDR5zDw-OAla^bN%#Te7# z!m4Y`LGKQ&M$`V2^Z$PS&WEtE?hUg7zsCA z7&N&UnGapKU~DmpEnI2wY%yx=UHQV3#b|YR<>}613<+>$ZBsEuM!9l(RWY7Va%D_$ zF(zcYa!GbErj@$VDzzA|*Xw!l#n5a(o(eCYI&$)7=r{2#bSNb{?W5o?$A7Nuny=Zkwg@||-N;Y%dq+3+U#7=-yK(A! zdR~Yd|DC7f#JMqVrjDED#ud}_I{9w2oT%5WbmP$Hbso)b+&!`gUq9}~z@bH0^RydZ zZZE>>7u|TOz6hU8bz??F5thz$O#H!(TilB9{4Z{Fb11^d<8B;nU4$WL-1uXUBD7s|qu+x<)ZTaF_?v|&Hh1U2 zi-pLvb!W)Gg-CF9=cMC>i12ggp~HpnjnMD+6~Z~eon7-p53&#@#qJE;P>35f?tJl! zLY!`M=T9pNar6mydVNrcA4j?KnRg1om)yB^b|Joa#hra;6yn3#?tE-YA?7Y}=T|Ql z;(yEBX*#M9qd#|N#jrv=w$YtS9xFuEHg{fZ(s}*l&ZO!>ME~l}t~sU$vkTGtyj~}@ z5ch7lb69*K&OCJIy6{3AvhbiuKq0o+d$7>65UbriIM=Zd?*w@8_dbP~8s$O%o`o2h zOTo3-au>jNG^I-ok3ovrI2M4VzQ0|NeKmM=)$=`VJ%)$cr?C@al+ya>I z^Wc-O72y1D9$fjq0_^+CgXhK-;HwMz`{)A9zvaQ9!wWFZ#FHNnDnLswPyXFpfOH2> zcFk>VEh#{cAWtsLDZszco;;jdfL+O+v>Q->}a~E_(9ZC;5oEt;c)^#NX5`~-PcNRBl8>i?yl6WvA2~5z#Hf6@r+D$HVfnb8 ztlQ*G z$HY8L*zV2f=se`?^=5H!9;|=!<`ADe960IC$u4<#=e#!;+U243rZ>N`%!A(}Z~oXV z4`(fW`1hS$thV>z{j0fn#@&Z~&*dUMz=vJ)fYXoWVsoMoYY*gNLY5DQ{g8`{5+6?5 znv3prK74CaF1EM(sIJJx%TN07o0Yl99qq%tALhb*f)7tD%*D=Ee0Xh6E~d@)VUO2x zk+aB${r;DW9?N{_KQ0$rKl5Sys9a3i;KQ6@xk%gU!>&2RolUveaL9*GSLI^#pFW&W zl#8gdK71`J7ZQ)cra$d| z$$|N}{&e~=2b-t%r~CFCJTtSu>hK%{Ea=aGwK+KUL4SsPnxj1G{tRE5BYkCmM!%bb zTSkAzzLkSdcK2ue>p5sX(4PaR=Ah5-{h2U62jBhEpNXS$@a$#%9G(N;JNh{&2b#sp zgytMfwf5z}>Kw#6`ZB&aM>!+DjLpu$oM2x@r{o|b)|U}+Ik=qSE1WF{@8$Y3z%K_y z<-Y9io`e4yeCgqkgJqBT(#bjp6(f9U*CPiHp7W*E{cNn5?)oMhw}0~G=C87`vN7+5FW;D(jpT>Eob*~YPWJTUv;WJ+D|UVyG%g!qZhovCm5rbM z{FpZ^8)G8;*fnQ5uqhkgX86&mDjV%Zel#!2M)w*&-ptf_wEFQ>Qa193`tj$OY@B<> zk48u~UK{7fRsD6`m;E^3H5)(9^yB~RvoT_UpYZE!SbylpM$>G3y2_8)ce7CVwI3s{ zW#O!$*EyGkS9bfcYrgf_BU!?ebo`&Q(DsiXH-4Xm`e^z~xg(v&@GvR|Q^zibh$2(bA66DWrv$K#8AyKX*^c!mu2Fu6iL0 z-OK#>#?x6?RPWD`L$eUu>CdjY+A;N6=p5ru`|>ROH^HCR^Rh5=x<3yf3x0F_xn^J% zHZJn#n~_;4UFOfH0<&=HGk+F)W#Rb^{tR}?g4I@kn%iVy@g9HvWuArTL;f@#W@7ts ze=fY0iP|&%9DOMhXRi9Q?B7g`y{G3L&xB@1)AVpA7WE0>v7a&#>KwqeJ2LT&PXJ&4 zHWP)R0UY#oCXU1fFnM(*hNcD3ZdoR7Xm~4tU30{nsxtA^@&JYvWh&nyfDbY= zF?myfcpshL_5d!9$;6zW0{B!&CR~3FU~2zNe0U;&R<4-{ITygAcA5C%dH|POW@6xj z0FLRFiEqsVnRzDzS+;@fb2S6IT>^RZOa@AP1G(%(1`dP;vTJ^M^8O4QMIg;~XP~7Z zko%Z{6P1Bnus#Ew&4FzHJOlp>4rI{s3_LzEkXIIG;LHnwT>o|khE56OgqayQ`&uA# zre)xXd4cRTLH}MH$o*sV_Z5MhHzEV4*95X*a0Ui{6G)Gi4E()4kX>`rmlkK>_^*L{ zJUatTC-pih8Tjp7AkW2Sp!!B2SA}L^|ARmd_su|2&me}mWniam5HHwgAl)^Ht9oT< z?n)4!G|f1bpSL?5 z<3|Ru{JV5qdm)Hc8`AZ@g1F=JbR2&zh!dBmqiS9d6PBc7_u?R4eLEc~D}wmR%yfLQ zM#r6&4&QHr=rSQ4^S1}-eW$~6ZxE-A&~bkaV#?rjTsjfNYt89sI~T;|)#=!OJ&0X% z;%&3jvBo@@+mqAbV;jupW79F)C72b}*ej1~zUC=GOP1eDYw9mzd8n4OXhUhWY>%O;?@PYA!L1U5K@u(l9z_X*+s3_!Eq z`C%e(DmH|9(Lio$2+s!rD{@0P%Nyub9>Q2>V0c3a58D7gb%yYToy@4&jnN(qOeHggBIjCzgir_>XDWwK{|^ZBK*$dOd%0 z8Z>jB8^21!@$W-ew<-dU*f}(m)7|y^XG680rQzvuq5RS+4LhcWGPir0 z@X=5ny_<^R^F#U6wN&u^Q1NQ1uwNOfMt z3=?jjikLxRT%M4M@gu?*6_tt|&xLVAU@B}Tg)!YL6?LzMakpbC-k%f3vOYSGMPWQ_ zmZ~|vVQhYog6BR9<6k#Y@a=lN?u8U|-x9_Pr&3VxLl~bvmV#La!+7IB3V!)Lj4%9< z0_T6jcyCJzS}yCnHm2bH|H5dpCPn$d;hel81%X!K?EZcVo^S}~)cGk`wbWf`};neL@OGCWdp$m=t`G8P0AaQgEdxoD&D7AhIT$_nY+h)^LukO2O(O;k;Ft zf(uWF^V!T4guEEeONl8M^1pCC8J&WquZQ#RpcI^(7tS{C6nHEN=MkqA^&{b|v`N9d zHR0T2o`U_G!kPUrS?hi{H{VP~_D|uAyO@j#hr_w*?__NFGhF;uGOnBn=YoUD2)-81 zK6{eUaZl&HH5u>ph~S-#$=KgJLi=?xdOAh$|=WLSL=!LdQfNM0Gif4q`0?5hY?IwfP_<_H>n zlJWhH2nL%cv5llIjgd_JOxa>d@ z%*-R%`-db%*+hyTPC}D&B>&iuglRsJ%>E(?UxY+*aiLQPpD(_c=)OZAalIz9=@IwEN?Itf2M8OhbD!R4h$MmHt_(;_*y zA_;?MMe=5T5@sxjWNms9KK~$+>jx&`;L1okMJD0)SCM=^APKJDM)I&n5>j_YGQM9D z+V@5BE$bvq`7M&yx+h`j$w-#nOT>?OSza=8q zCW;>W6EWC1iqG###8jUs9xxK|VMr9i)+OS**eJfdIuXZHqWI_1MBK}X;=p$k;anEQ zS#uK+S0BaGGZInW5yiAAi5T`|6z7di#I#XSyzq1)J{TXx%%O?+=H)2PZ%f24Gxhu0 zL|mF5#f(y&&j)&ZP9nTkM)7P)A_jgHCH+YvN;m8Hp^3`LiQ>uri5R~(im|SVnDeX7 z$1V{oPDJsrMIwx|Q4BOm#KCJi|Jw;TeJ_f;E+ybzk7zpnn*f_W(H#6o0{S~e^Q&JH z5bqt$Za*d3Fje@a@oO?ZXN9@tJ6@dMN?NUX13A(Fr*Fzi6foPr$9$qdD!d1oU`2ntK})V7Eli zt4t8S8O@f01O%^%=F)VX$EIkW8<>FfZPAR1OhD0((R?l-L4N;ee&dmVw&T%!}K`PqS(?GVE`CkA4HM+^`CIuMHk zV(74MAeKeOux95#tW1dEyl)5M^NbiCT00PH3-$L;2Vz52468mGh|SG0+J^?>yTLKs zH+vwqJ*DHnIuJXak741Yf!H-EhOaz7P;&`mxb3Nd_+d^A9}XUfJ&R(P)G`o1E{)-s zYW-Xt!_SNK`*krqo2kb!hQ3L9-tHJSN9#C0$MCHn9rtJqfAZ4noQh!&C%x{47^d{m zdEAWQC^Mbc!x(;Ye*o6@jOCx#2jFwtSoS+V04rT$S@_ogEbAZ3iAM%tNoXv;+CKmb z;$nGv*8t2;jioCGU`B2%OV$m*lrlYT^#HtBAImS74!|=Vu{^bC0ERvpONY4w&^9WT zIWq>JW_&EiOdcTKAePHs7=ZMdu{<<#0OIGzvd54C2!217F|7mO@kuP(YX-pf%UI4V z9)RxO#PXZ00l2j-mS>U%;LMLYZp;82Jrv9I-~rfkJeI?~2VnE*Sk8AEfYn!Gxuwql zymu#-=gkJ-b<;TZdk~LtR&h+b5sxPw;yC1dJnB8-_~u{n$PI|&h9mKai;Ux+`{Uu0 z5J&Uf@#viq$8g5uPC*>2*2UwW$~cZ)9gqD@aa_DKUV8XAZd(+OWh3HvdQLoMJr_r- z8Sxl9F^-Xw@&;AH{KFOFT?JjpNbkc${4u$9qNb z*!OK5-LvBH_0Bk^B*kOVzBqlK@tE{m9LEL4WAMp1F7%2=!8x6;V?4sI$MJCQc-Y>L zc@}2K8FdYf`Tbodb0)&^b}(2Av~y zuFyGC=MKFG>b*ekiF$9)d!*hg^q#5r4t)mHXCYoLp89N{&xrc0pwEo@?4Zw(`YfT( zl=^I;&zSnGq0gN9?4j>~`YxdFg!*ov?}+-Ypzn(Dh%UHi~IK-~+_Jwe?Y&^KS zS_G|0T7P1oHHuoRpf!tHyP!3UTFam{jau8FHI7>Apf!(L`=B+DS_`2yky;y}HIiB@ zp*53QJE1j{T1%ldm0DY&HI`ayp*5FUd!aR$T8p7InOd8nHJVzhp*5RYyP-9lTFap| zom$(WHJ)1Q)#oNqYd^FHPv`0{T1+-^Sdk3_KP3hlAfUJLEH)ZPp2!PH(1?a9>M4DHd>UJdQp)ZPv4 z;nZFZ?dj5=L}?CNBDL2;dp@=ILp1?Mekxn>@N>I&2)lN_iB|TCkR8vv46;xwUwH8!!QMDITgHg2@RFhG)8C0WD zwHj2jQMDUX!%?*yRMSzl9aQ5{wH{RSQMDgb15&jhR1;FQAygw$wIWnAQne#gLsGRQ zR8vy5B~)WlwI)<^Qne>kgHp99RFhJ*DO96UwJKDzQnf2o!&0>@RMS$mEmY%DwJuci zQnfEs15>pyR1;IRF;pW{wK7yQQ?)ZxLsPXhR8v#6HB@5@cZh&$ZmRZ%YH+F+hiY=F zHiv3-s#b?;cB*!VYIv%ahiZDNwufqbs@8{Ueya9|dH|{yfO-O|H-LHss#kz|2C8>} zdI+kQfO-n5w}5&Ks@H&e4yyNndJw7?fqD|EH-UN-s#k$}7OHnq-H=T6GEh%L^)||{ zNuhcjsOO=2AE*bSdLgJMqIx5!N1}QqsAr;jC#Z*_dMT)HVfqy&BZBQN0_~!%@8))YDPD9n|Ady&lx_QN17315&*p)Du#@A=D#M zy&}{zQoSS8L(=)*FsP@bdP}Isq~ps)@I^PsQ~2m_(85C{{Yun`C&p|BDNGoi2(2t%Q;6bMtHuoVbn zp|BPRbD^*o2!o-p7zmT0uo>0CX%toiVKx+YqkSli!g3%?hr)IsjEBN{Ak2rtejp5p z!h#@7h{A>-jEKUD1em2!*b#&wQCJd$DN)!GgfUTA6NEWY*b{_7QCJj&Nm1Aogi%pg z6@*z)*cF6fQCJp)X;Ih~gmF<=7le6H*cXI>QCJv+iBZ@XgppBL8HAZp*cpVOQCJ!_ z4FiR(K^Pl_wLzF0g}p%-9EHU}m>h-8VZ=O8SRI7fQP>@X;Zax~gy~V(9)$5xSfA8X zps+s(1EjD(Y}yA38x*f5srd83(usq@4j~MY!V)1&k-`=sjFG|`A5KnN!%g-ggFtr9+rHg{?yvJB77Fn7iIrpynuNP*^;K$y3-ogwa!2J%rg) z*gb^dQ&>KP>8sBTgfM;z>xVFZ)(!}SH~@+ZfH(n)8-O?hiYtIP1ByFQ=c#2HcC z5yT-;ToS}7QQQ*5F;QF-#5qyi6U0GLTolAfQQQ>7QBhnK#92|?6~tjtT$XgCSroSg zaa7Gt3|2z$h*Z;>0L!4C2Trt_#bK^!2(1wx!4#SKCn zA;lF!oFT;>LL4H+B|@Ac#VtY{BgHjBoFm0OLL4N;MM9h;#Z5vSCB;=joF&CwLL4T= zWkQ@L#ce_yC&hI_oF`oq{2&gL;zA)#l;TDqj#T`PAHxr@M@@0n z5NAzs*ARzIaoG^3O>x^0$4znF5a&&C-w+2*ap4drPI2Q9M^16&5NA$t=MaZZap@4J zPI2oH$4+tW5a&*D?+^!1aq$o*PjT}QM^AC}5NA(u_Yj9qarqFZPjUMY$4_zn5a-W# zhV+Lt0F)L0(gaZ207xT1X$2t70Hqy(Gz65E0MZmt+5$*pKxqvi%>ku7fHVk{76H;E zP}&4Yqd;jDAk6}$U4S$Ul$HU~G*H?GNaH|h9U#pE@9pt{G!T>)Li0p(DQyI#k)X5^ zkY<9?PCyz8N=pH0DkyCQq_Lp17LewG(q2Fs3`&auX)-8n2BguTv>K3RgVJt58V*X! zq5RfdPRR0sG#-@J1JZo(PNWZ{0im=YkS2uEhCmt-N-F|sMkwtFq#>cSB#@?r(w0CP z6H03WX-+8Z38X<0ujUPDQYdW-q*0-?Dv)M{(yl-n7D~$kX<8_43#4(Ov@Ve5h0?x2 z8W>6oBfn7|rHz3!GL%*Z(#%lW8AwAzX=xx$4W+GtG&Yph2GZP6+8aoNLuqj!O%A2a zfiyalRtM7TP}&_x!$WC#AWaXY?SV8tl-38*{BX}LFGvGKX@MY35Ty-*G(v1V;st4j z`073{NJB(vi6Bi8r7eOqMwHeF(i~CRBS?cpX^|jJ5~WRoG)k0K3DPW4+9gQCL}{5I zO%tVUf;3JX^OzT;dE$}=9lt4`(n3L+C|=L;f;3W;RtnNgQQ9d;Lq%z+AWapet%5XG zl-3H;Tv6I9NP|Ubu^>$rrOkpgT9j4`(ri)MEl9&fX}KUx7p3ijG+va}3(|biezPZ} z0i(2FkS0w1h$o~GqqJg>W{lE~K^ihjO9pAmC~X;}F{89*n!jE^Y0n@H8l^>pG-;GJ z4brGlS~WL7F^Dn+Iw1D6Jl(*`u_3kcN-a@h5Yh-zT0uxNNNEQl4I!l^gfxYewh+=7Qd&bu zb4Y0qAq^s>MT9holr|C4C{kKQNV6!*p$DX4q_m8XrjgP%LK;U(>j-Hc>2=Z_(m+yL zNJtY&X(J(xB&C&vG?SEe64FpoT1rS$Nogw~jU}bEgfy3w_7c)yQd&$%lSyeaA&n-b z)r2&gly(!+a8g=MNYhDaJ0XoHrS*g~pR~?&hcuv+78KHiQrb{RBT8vSAu2s+3k0(yUV2RY=21X;~pnE2V9P zG_I7^71F%&oe$k04J@UFl|G?}(#Ap>SxPGlX=W+ytk#DjN=plAYAJ0kq_L&6wvgtQ z(%wQETuO@zX>uuTE~L?=w7QUHm(uP+8eU4v3u$^OZ7-zprL?|~=9fE7-5?Dxr3HpG z!IU-_(g;&pVMsGfX@?;VF{LGjG{uy*7}6M1T4P9aOlglH4Kk%ghBV2PHd+4fVoIwF zX_hJNGNfUqw9JsEnbI~x8fQxD3~8Pz?K7l-rnJzICYsVlLmFvHD-CI;DeW|*p{BId zkfxf_Rzn(VN^1>it|{#`q`{`N*pMch(q=;%ZAz;RX|^ftHl*REwA_%Uo6>ee8gEML z4Qakt zlolP*q*K~-NTV(vybGjRr?l&khMm%~Lz;F<+YV{mDXlxkdX><|#|6^BQ(AaP6HjU5 zA&oqxm4`I*ly)A{&{JA^NK;Q~>miLjrL~7N_muV?(%@5CeEH2wC~ZEZ(WkWfkY-=_ zrZc4Br?mW#rk~RGLmGcd>kn!E`Q1ck$OAxm0U%ER9&P+kzo6GC}IAdd*; z6@fe>ly?O3kWgL{)fIZ)BS*+%LU~OvZc8cUJ%KzZ+;GAX@}yAS6v(4Oc~v0K3guma zJS>!#1@g2|-WJH?LU~;v&kL8ljQay zc;r?;$O9zbV?W3fM0tZCj}YY*f;>Z%cL?$jQC=d*Q$%@-AdeB{HG(`xl=leoAW>c< z$dg2QlOT^0Hp;9hMKgd%>d8;6g73H;pJXe(W3i4o4UM$FyMR~Izj~391EFB{}(qr7d9$Bpv3L7q3Z zSvx=;ILZqLdEzK<9ORLsymF9dj`Gey9y-cP2YKo!Zyn^Zqr7&I=Z^B;K^{EHiwAk~ zC~qF*(WAV2kY|tb?m-?t%F73N`Y3N7MAL3DdaJwyrz)nl=7ZJ9#qPU3K`%i zZz|+brM#+;XO;4|H}3wdZMFD>M$rM$I}$CmQiLY`a7dkcARDK9SM$)&uxkVlvD>O!7f%DW4BcquP0 zsAs^UI$O+Cm;+$_p%Cbrt0(g*?KPR~YgPQ{G|7Lri&zAx|;oErvYC zl-C&Y98=z7$b-!B&)GtrWXhY2ytXRJs|O)D$45&d7gPF z+!pdcQ(kDu6HR%er9Y{nywZ?on(|IV9%{-<4SA|5Z#Cqxro7gW=bG|fLmq6(iw$|Q zRoB}<9&O624SBXH?>6M&ro7ycr<+yp+Q|1GDdF>(3J>|WJJouCsAM)f=-h9nPs;0d9kY}Ir?n54a%F8c3QZ?o6hdln2*B|oy z^JropC;Nc3fXWhpG6kq?0VrdD${JAaR}Gat0A&ye zPwEY25>VL$P(}fjRRCocP}v1ghJo}uy`fA4D%$|cIH0l)pv(hKp3@u3K%lY^piBfR z8v)8lpt2I6%mgYs0m@LIvJ{|91u9zs%2=SX7NE=pDtiISV4$)XpiBmS8{AvSk1j-;1$3Ph}RF({s zDMMw;Kp8Vs)(n(6LuJoE88lQD4U|bkWz#?zHB?p&lvzV%*N7jklk?XS%Cw=fZJ>-B zD(eQyykY4QODF?}%EEy%aj0w@@oIHcRt}VzLuKbc89G#!js)FxRJIP3u|s9;V6#;{ zmAwOH@K9MiP$mzR%>!lhP+2`tW)GF!17-M7Sw2vv50&i$W&BWCKTzfm7u~dgGJvQo zASe?^I&ljqBZz9;q0AsEI|#}UqOydbOd%>;2+A0uvWB3{Au4+a${?b$h`_1!R5lTm zQAA}GL77EVc9G^F)KghTP^J-;Z3JZ;QCUY&<`L%L}m4yXmVo}*x_&8_ZNAjB16MYKBqmFjEaNswHNsDMq!$Of|-+)|jd07}Xv#)gYr< zWTu*ARGUoKpY)_!WqRMIC)F-9gBtdvT4tu2W>nkERO5_lotbK$vHY@>rW$Be3(Zs$ zjcTKrYNS!EG*itqs-0%4p{CE9r!>`6quOew8f#Q*%~W%ZYOm?}z9-dUGu33H+H9s8 zZB(nxRI`n0x0!0VQ7t!9O*g9TW~%WXL<_tqFQ&Rns=PoT+5g5MYZruHSwr6o~cG2)ygx~%%j?QrW$%wOV3nO zPoMuzq0hnhqFQ^VntN1x&s2ktYVnzB@=T_AWsn(*Y<|5TzRCm2M)nYW& zWTe`RrW%b@tI<@mk!m-ZYB*9YM^jBls_kg1@kq5EO*J36?N2S&zc=gqJZ>aG~UxnXL^Of6k{e~K_R0|er z!s>Ybf*P?@D;8?TQteo%AxpJnp{6X=mW3L#RBIM$&Qk4Js6k7$XrU%8)ux3SwN$GX zzIuJBb}iJfrCPR7)0S%6LXBIhbqh6b8NdH0)WD@$xKI<9YU4tUT&k4|HFK$UF4WM~ zb%j5nrY_aig&Mn5YZq$ns{8d5YVcAmUZ}}SwRxdNFV*UWn!QxJ7i#!YEnleVOSOHW z#xK?Sg_^%q`xj~eQ!QYq2~4$tp++#(3Wl1&R67`I2vaR#s3}afg`vhU)f$GH!&G}1 zY7kQ`VyH<>wTW@_dta(m3^j|Xb}_1@38GrY=#w#sY8xXudl2tt|Bmf>gVgc-hMR?h zs1`C(lnSES$S7YSh-xLHbG0D7Px}p?Izd!R87s^n`aIvD#xm7f#_Lu=RC^g&I|flL zW~j+bwVBbYZxC;1_y+%=AgbMrt*rdr!jbDL^!Lk(`K#SJyNsWvy%=%!lT zP_vtAcS8+ts^twey{Wc0)cB@a-%#_Lr|4mHnNBkB{>K&M*hP!pYMqeG2!s+A5k)2Vhk)KI5d>QGaiYO6zyb*i-vHP@;3 zI@Dm-?}v|2lbvd_LydN-)ebe=sdhWmaHm@CP}7}iyF-n4s`U;v-!F4{)v|}0_Eg&*YTQ$;d#HKOMhD(Q4ScGF4>j?rHa^tIr&{??Ghf%kzeg{B zf2ySqHT9{sKGfK!TKiCQpK9+z4SuS{4>kFzHb2zpr&|3`v!81BLk)kb49OaaOkfQ$jk8i33J${v6W z0?HzQOajU#fQ$mlDuB!a$}WHm1IjXhOasa`fQ$pmI)Kare*gRyG7u;W0WuLN8v!yB zC@TRn6DT_YG88CF0WuXRTLCf_C~E;S7btrHG8ia}0WujVn*lN!^!q~hA2fin8z94h zvK%1OfwCPS4~Ng0dhW6N0iKAR~gZA|Nw@vLhfvg0dtaQ-ZQ3AY+2E zCLnWyvL_&eg0d(elY+7-Aftk^Dj>6hvMV6Ng0d_i(}J=sAmf6vE+F%Q11rCV3=GP` zfJ_X^#(<0r%F2Mu49d=c3=PWCfJ_bT_bUV?8%S9jkhwwG8<4?4SsakbLD?LT(Lq@q zklCTvb6!D)2W5FcrUzwvK*k4UeL&_1<4?at&-w!?3j{JjC>sPaLMST)GD9dk1TsV@ zO9V1SC|d+FMks3pGDj$T1Tsh{iv%)BD4PT_N+_!YGD|4C1Tsu0%LFn_DBA=wPAKaH zGEX>a$P36op)3^0M4@aH$Vj2A6v#}W>=ejQp)3{1RH1AY$XKDQ706tn>=nphp)3~2 zWT9*p$Y`Og7RYR&>=wvyp)423bfIh)$atZw7s!0!o+Qs91BS9-AQMLKLp_6x7*+7sHL|H+Q8Kmnb9z%u@WeGv15M>KN#t>xD9DVW>?p{PqAV%Ml%i}Y$e5z6Daf3n>?z2gqAV)N zq@rvp$f%;MD#)y&>?+8x(yQtZAk&JntsvuyvaTTWiX*EXvA) z%q+^zf($Ln(t=DabtLXX#ujC5LFN`^Z$SnZWpP0!7fCb1sPwI^#z$YygK<>bi@6OM zag-H@g6D@&b{u5LQI;HJ%2Bo)WXw_49AwT>_8er;Q5GF!(or@Y3Va$uS#^+EN7;3d zVMkeZkZDKRc93yLS$B|m$HY#zAOnxG@E{Y9vhg4zkFxS0Gmk&N+=L80%F=^OJ<8UD zj6KTQgUmh3-h&K2`X=0jOg_rygN#1P>VwQa_GxqzGW;mZ4>J8I+Yd7SDC-Y0{}}b` z24nzI79eB-QZ^uD1X5NYWCl`pAY=$qmLOybQnnyu3{uu0WDZjHAY>3y79nI3QZ^xE z6jD|pWEN6(A!Ha*mLX&sQnn#v98%UHWFB&#_c~-CQWhd)B2qRYWF%5nB4j2~b|Pdb zQkEiQDpIy0WGqtFB4jR7_9A33QWhg*GEz1pWHeG%BV;yGb|YjsQkEkQq#8!qj*#(4 zS&xwU$dQ?^VO`E)lm!WykdzGx8Ik%w;VNWC>iWv7kReG~l8`A$*^-bkNm-NFS8tf+ z`6^^kQWhm-Qc^Z0WK>dCC1h4ob|qw3QkErTT2i(pWL#3#C1hT5{>m$mfk|1I`g?j9 zWn)4{CS_$pW+r84LWU+~X+owZWotslCS`3x<|butLIx*gaY801WphGCCuMa)W+!EL zLWU=0c|xWqWqU%#CuMy?<|iB0ybKwjlm!Zzpp*>?8KIOF3Ynpl9SRwulqCw8qLeKP z8KZjszXX}1lsyU=q?APpnWU6W3K^x8RSKDIDrKue#wum4Lgp%EuR;bZWwAmgD`m4n zMk{5tLS`#vw?c+1Ww|0t*Wr}y3K_4I^$MAte~3;gq!t znY)y|3mLqW#S59dl+6nny_D4pnZ1 zOxeYdVN6-ZkZDZW#*lGLS;vrhOxeefflOJ*kcmv$$dHjtS;>%@tjG0P$WWGpa27I^ zDO(vbmMLo)GM6cP88VnDiy1PRDVrHGnklOpGMg#888VzH%Nau#ji792$ato#XUKf! z*2|t|9Z9o6DYt3~b86hD>bA#)gb+%F2e! zY|74t3~kENhD>eNUG^7bY*W@YWNtIF^)JZarYvsA~6^L*85eb zAk&+&y&>b9vc4hno1ONZf(&rV0>|%mBPkmkGQue<95TZxI~+2^DN7tO#VK1HGR7%u z95Tl#dmJ*zDT^F3$tjy0GRi5d95Tx(yBspid1uN=$Ta7{$diz9&c%ICLgqQW%}(O` z{E?J}4w>kbjSd;6D!g8S0d!4w>rQm~a9z)+uWpGS?}49WvM{iyboADVrTK z+9|6YGTSM;9WvZ0%N;V^Dcc<~-YM%HGT&L|@^Q$3r!08Xc|DS{;UOcQvf?2#p0eX1 zL!PqaAyb~R99b5b5dREuB^d~+0C+Xl1p z)uSlaDVRTa6iK>kxphZzsdq4E#T>=j{=w|)J_`4cV3rS2hgz87} zHX@kg3g|;_u3)xFbrjS6!OZdY2>Ol*=IyITP$4>)s}3E(k14?%5qAWqVuD#^<`K-9 z6U_hIM=)?+YUKmKEv4l{Uuws8?2rJhhg54p!SAZxG2;uZp#Mv<+G~OPBFFJ%TuZn)3 z8p3&p4&r7^2%E$m#H2aee#}ACS{TA5?t^%=G=wb%9z@Kl5PoWP5Jp@GmsUTBXPZLU zvcN&i+8)9WDfRt5Azb|C0G`Hc{8tZP#-R|t;Q`b+7Q#8}4&eSNZ8zosqR)l!k?Q~| z{S(5;0}kNw)eu%`bpW1QA-r1c01Dp^p*Q~l9DN+ZA}J4G*ozPzd!2xEZ$mizN&+^2 z2%)46wEq&qEo&3-{znKq&Pc$lq@n!iOhENip^WXHfJ=XbvS!N!*fNFkYSjc}%^pgJ zKCHPlcc{AI320j&l)GQW<7JUhecnGF6H4m-2jWqzTqtL*iO0c8p{z7L9zCju@{A)M zA8Lnkc)xf|HA0!PMLbIW8Omi<$jFq9LjW;_9JhP zP_9bYkF9+|X{_FlCIhtG)cv?VB$T1{{RkPU^#$!m((q6&Znht@B0^cM@_zlE3gut9 z_hXMQltD@NqxtAietNzS*T#o((%<_qY;q_I#_z+I>7m@dav#Re4rS9R`;dKpD6dEC z!-~bB4DPcJl~#oESCf5+UlYn175AaphENvCwGV%9(fxk!MW3CaZ1ij|p6(6hKNt4G zav+og_U*;D#8AFlz89m9hcar?Ui@)7lo@S%5pzD2i+b%v?n|L8+juXQT+=+3--}|m zwVoV%vF?5-&;Q(m@=rq9>&YH$eG$qh=k}o5+fat@*@N95Liv5^9@PF4%CXUVu>XhF zYuSUkNy9j|#~#F|3}c}`_4OZNTw7K@<u^*|dDNFz)`o8@qFb(Rj2Q)$@n($eG>P zS~!d?cI`%m5@9^IcsJIS31g@6yHUJinBKqHjU`pX*t^?q7q1xuSS^;>u0S%)yb+P({YyM{4j;V%5sGmNjt>_YP( zeI2|D2?O=>&bv@~n3gwoVP$ZbUa#1N9F{N+&A1B_BE$Ijzn%Ev3gdvgJ2BiJ#ycl= z;`-O7;c0}I| zW2wX2@$z99=da(6w$H+te%5wueHBK(XFIaK3**~?+hO|@#(u50kKUZ}nu)qjPt zVS(+Kl`NcFQ*PJme+psxPIDa18hIHA(Idbhb49y+RYty&kNd9m( zac)DQBH`TLZyVet!dbAzHe4zb&Pi3ap+d!Qe#)~ANO9iWy)5>v<}zfVXOX*4`;(ZTT!=5IOCdV`5xiSTyZPz z_X(#X=T=l75YF4bwqX2_a5j3n1y@IebKUtZC><8g412f0WecZu*%q91g!4-D7UcGZ zv#w;6>=ykU8O~!_w_ssRI7@!tjHj{TobYfnsxAoU zv(ua5T@ua~J2&I_3TnrA&e0_| z!=4b%yBRkl;ZQj1f8K+{;1aPDF_H_qFHELXyrdekO# zzM=gZz6r5+!kN%v6Rti8XO6m?kn3qU!-{S~_m|;3@y902eH+fgA2#C3hj2P?ZbbGk z;XHq2BRc*FXQ_=FF+GWezS$dbCWVEUyc>}wt%YR=Z$#q^76#gEL?Da4Ut=To<*?{| ztZeI8gWl}od(MtEl{FMV4DUw13hK3s)~y{*LQReFESO6!hQST@MYH49f^ z!!Rqak6DFX!B(aZUWJ3ZFv2xC)mH0SA`xmsB-)H5dwJVVHfR($ZufXp^ zR^D^0z>lL={?Ts*zMizQdh-?dbVkcpUV(ovSUDm03cS2z<<=xC@c5dQ*PboMom*BW zxwu^a*IQY7-*Q}dWM#YM%W?9VRqrP)2VYsa$g&)}|F!aPkLB3-(aL8Hmt*-CD>IZ` zjyXT9teSN>CMU76+qY%#r?AoUU>PiFY+Ul!G7L&@#fIVibtAaaHJIe4A(E{;rF0b&-wdu^2m-+4!*JVoYCU^^r9;^H;_z#@#IjozV)(EW&w zQ`;><#S_~9T8oh4w2fN|EyDG4HZt`hZ2nu@d%F;$uV`MbE=1QGnqMwN={q+5T)Pn8 z@7tJe#zLHVY-1khLM(Z1W2t@%5&GJu^J*dR&c=q77b3$a8{6bwh+AK5?2%+4*8i|^ z@UsPQCW&D9g#~DmB7&a13y?KU1jjF1fZORJI3s!i;xa{WLHGjLvPE!J_XRL=MQ~Gt z1xTGQg1bvEz=eVlJeYX_<`s?L@h|hyuVe(z-J6e6Wg~d`%C)s1w0A!{#HI5y6k`=i^v|2!5?SAJL5?_^a@Iv}zu~WNGIkL+c2pdN&W} z+C}h>>+>+ZQv@?4&O^Iy5zHJn4;gz!Fl)>_ob4OI?5=s3JRpKO`_Ds*ArZ{gVjfbB zh+yt2^Kc|2f_d`HL%^cjr1MZWQn%0N;*(Ri7w2M&SIh02i{Vka-}1RAIyQniCeFo; z2@%X@nTwf|BbcSfT(p=T!Hf;(BFU@>rYkcSyXQnOO_sSBxgdfmzRp46B@s+=e-17$ zkKm7!a}d2cLVb%ls23N(_w(l9&Bh46ikgFETO;^n*c^1&8Nqw)=OEeM2wtx}2ixN# z_;=ws7{CagPBRBtjzsXtzp;wsL@@qZEJFT@;EqGF$a^k=>(|BN#Kj0MpAie&)&wZYSaoHltyR%R#S0uNbn1vI0Be`VDEDS3c$!T+EA$8G6`U11CrbHx1 z4xNQ2Wg^+5-7GvTAIWC5W+AF_Bx@9!g#y(hSv2)5?5h>YOmAnRb3JYM%1pdPB%dCf ziHUzk@}D&`QLL%9H*F>oT10ZaeI~lJiRA3QGx558Bm+%n>i@M!4zD;9`MO84W6qh_ z)+>_rf5o6#P$Ww{iNUP_k<4%|2H`^@bv<4TQjE}e7RO+2NF zv%18fjWd!iBL;Uok?dC@24R6nHpvi!U!x;g?$ZoR9UsZew`U;#B(3l046L6T$?F?u zpjJ$zdhj!Fbate=YBSJ&UL?m3nt_`OBRRD73=CNs$(Ge;;N6Nymd`%}o;8uom|_M} ztdHcsFQ;S5rbu4=XF9TPivWiBBf06@G#tJV$;l6 z+EncL7Rf7zrlR66od@ftA}*<&(KDu^Xi7W#JEvk%8awOsn~Ln|?ab1ADyC$z^LeGI zNRiFXL%F8Hozu>_zo+0`9y>#xPQj1@b~ZjgMc0MdnRm|=v@dSw+a*(Qq?Db<#!o@5 za&|5Vor1WEc7}GHf_zo&{1a0!wT7KJOHRSB+IGIkFa@FY?L6>lGVYjm&bU1pZ5r7* z@YrO;H?_0IrpYMN($3VelQFlAo!7jRk-USQ>jzCnSZ6!kttaDVH#=KZpNyux?97*c zGPd@$^JVhM$UDH!_?MF~X0V-;{+WbV!|d!4KM9?K?JTu&65_+`{4{A2irVZvVx5F& zyPYvTC*h6D&c1(6LMNY{<;qUNo+!KC2cCp{W9>Zpbt3!|w4e7U;{GH%dnsboXqufR zw@t*V7(3t1n~0RLb|yqk#Nc^$z27ns#}?YzzWqcLUutKb+7mHmg`E!zO~k#`c5X~P z5s0%h;%zh*Y_zlf)o6U)VrL3QqvH-c&#Z~o^(uDGnih@J`|a#$k4FCkb{6Ryjs1u0 zeA*-$*^b(|sX{bHp0LxJBN~VQva|Nj3CMHK&YzDa=sF=g6VFV*(M#H&o%;SYJ6kN8 zfY6(EW*9pGiFfS0FmeKNJkWMJO~BB{c6O~d0sEfWnY-8oqF){>(X(!P}sq9 zlEqyn=%)F%A{0IOxtW4%X@p*7!6QyK6c4_SRT@ zt?S_WqhnDY4i4Hl7XF3~7MML2Z0z6_&sZdB?%?!+W6_|MgUwrwMWC&NNve&-!43}Y z%{vx9J3APjY%J<_cd+z}F>v|nBqV=!cx?iW4= z%SJjF(tQkWggRKX!5Cz-I(W6z7_^FXa7v~z7~^!X!ROJ~?{VhyI@!jq)?KzUrgVH`bvJ{byP3Y#}L*uy#sw>CSNrspW6 z-R|J-hNDnpmxF`Lj6(mt4ra?T3RB~?{V!42bI`%idr`QbsN;4r3h9nHcw$Qws-JW) zVr~?ApLVctAPQs7Ie2DB6gFIR(9t#u7cXi2HKXwPs)J_>L?Qo82c0RS(D06fjc)`n z_`ZYl;sS_%Cwr&&VqYOASKajBVo@hwuJ_^V;E3(@U-C!f{V_ZK;t zJADLZF4g|uv>|4NlM(A}n7-P{7Bo5K-by`!{d8S zZeJIMD-WIg#}S4TPc-hPVc7Fr=Sj{mta+vRejJL}w@!B48HzFQoeUon3d<+WSI1EF z{o>??BB5yc-N_UGhM?vzCm%8dMUuMsds+z6r*JWE-w^zl%B5~y2=1nJvF(pwoJ{ZH z(9^-#n#sk$f?&+c>f+qt!3gAVaZBxB49@N1vDCq6mCwanS4N_8K^Nbx9*G=9Tuc=? z5?_nCn6L3j+$!nP>$)SsGA{o4U<8(zcd0uw0%Iy^{ZS(@sH%&ub|cWZhKrL5jzIC+ zE-rjM9LejsxFKOU9vCj}pFA9g8n}3>=Wr};?hT&-km-+z1kl5M9qA7-9K{pr6|1%V}o-Wp0F%+%(xM*62qG&%Cn>QGW zuLE3cpJ^!04|cKpogr8~%*CKhL*O3i;t=l;v<-DJxYZC8wYX@>I|QF>F4~_D#!0)2 z?!AMtz~!QU!eET_x;U!qVAKz|IJU%Kq#y0#_>Y5dYpjbCjts(v2`)y@90b=S7bo@~ zgl1E9TX_(&&(QaO55)bMTJGFHY>IVp+~R?7&U0~0@IW+L=wej8fyl7LMeiR2adnxC z&g%oPY^944>jq%h8W+PH15i26#o)95Kjb~^V!^5XaO*Cv!LAZV1#RqePu;_0WFAWJo&&w_zuMvdY*Ie9_A_$jnxVY}0zKFT) z;=C1o(dM4UXX%SH4>f-c`r`0o7YAqR3-2=*JKgDnnlD{!u&EE;ymqmIw-46*tMju} zAN2j;V#>UIkmEm{XU}@$^cS6XdwOHkcWrNcZ=KgJZtc<=FOs-9zj$vfN$%#T553Sa zm760D_d<%aZgz<2h281gtlh5{hGlfKP^DhTlf})Hzk2GrST|ps=?Pa(H_tEZiPCx8 z+&Q8ruHDZphq14N-y-K-SS1@ZmdOjW-NdJJ^))*oH)d9a(? zu6M@lVQ!9J*BO;Zy4lmw8D~P=tk|?OhK9SDG)HG7v$=WcVJ9q#baT!2PN?B@(>baW z&bi%e(Y_Og_}t7}s1tq#G>@-4B6hT!`x82%+&H&hm+gqe3EGdI9np1?n3)DEgP?p=TScJLBfiGHp=dyql%Jw8plJZazES8r3hkxh}Rf_FU1=2en4s z>;E55Yb4y%{gbwaamURS7h2)KJvW1vwu14{&HSPI`mvkW>bFAuXKv0;*9!YzXq-1% zqSk9S|A=deoo{tsIa;F1dpG?}TVm5kjW0(_l>Y4IzYkkr#aE4gdkf_M;b#9)EimVo zo4MP!K*ppVo-fz}{+@wu4M8s z;;m*cQ zFrvDL{j)W}m6{%Ac+eOP>Ug+sYh!Gv=i%T$V`PVincFsouYrgA^EbwmKRq1uvJu)g z(f;mlgk8-%+!Ngh`C57y)U6RlwbuGeHp0`k9&Y*gCt7vzu&@H%FCsjAamPdxhldk4nONrX zu#DHlH;;!WTAJwO*ZuRD*cjzuif2HIF&-}84fGnPH~q%}+b3wgI{|4Xd1x;R^qt~i z)^`SWO!IIP4Wy3o$a^=?YnF!(dK=gr>!G)tfu!?1%<-*0IxX;U^U3;HwaCM!bL->N z5)bbTu8$_mwZ7{05xY|JoxDCCt=4>8tcR-WJgl><9-`Lkya}y`vl}(fMm^-+;^EhH z^)O_chf{CV#kL(D7Ky8iAG>t?9CgujuZPW=*2VPw+TZMTaV^2a;D>ckm>&MxRtLip zJ)9m@2V0JKSh!ss{CCX5tp)0!-boJ|ysC{+e`$OBYvb4%5BpB6jkM=IeATTs+FbO| zU9vW2{G<8(R11G!_AvHHEo8r@<1n)py4=wC`qe`0Ef4Efs)fsUJUsTZCbHl6u>F~u z==4y>Z$VAWc&zhicukyp>fzg3HIeRxht5*1(td z9?ok}164kGSSV8sjQFg_$?fV``PIYn8>{PcY#wfRS4Y-gI!{_uM~ft0CgiG)Kr$~I zJgJ7ADZD(ovl^bK^0N7uYABf2%hMgIp+h<^+Z3*bu^GHP|E4PTWb(4ZfvR|x#mj#t zS4H0JUUu$T6)kgmd8u?&xO404&sDHKuf9H31=sU?*=cqaq%P#;-vg?kdJ!+%SE+*j z#k@TCyE3Mg@Ur!}%Gg)R%TtRg<8c|UJkiR?RNl+Obt|?B&Ga&Zw<6{?^m1Iw ziimII<&WGIai@uwwx<=4w7Hirc2z*JmR|NBTLFz*dwHc}1q^Ph{VGxczB`|8Sms5_Fz@(*G zZdM7*TJB}H0VS|-rOva;C9q<(mxX^9N8DO3$DS>YEpc8xU057DH+b1N5<{+F>B{)+dq>+PcW z>wxBELs6WfmpR-;aWc`%h~`Cc{D{uGoJDc;n3t6w7r~(uUVV+&i%_7F_l+Tld14dDY91l7%txx|b(E z7DCibulnSLV8899C#DdB?`qzI3ZegfFUwafgf0(t-u))(RqVw@aek}N=tW z(vQp3lOD|6y|O&{x9bK+8MjkiHgY^>|!>5Mrsw!XG^ zI|q8f$L=@U~$L-s*qelykFDg6A zxAL)GyX^SY+NW+ocARhPW8%wfSk~Uh6#KKm($U9e(b>?jvyT(IW<%z#n$P0daHpG( z=|5z}#vVSlNzAHTfsfOsXGPOKKA!8771@G(%ve4v?)3Aq?YAt58{p&AlUZOJak4cwgM)5G8E~d+j7vVm7>So4P ztB-rqWJW}UkMFN!LLIx06<24%4~LJ#ZJBhPq>rl_X2NKXk9RUuz&eQVg@MNivJ-_{dh0FgxKYyUzN-a0%550e_@eTR| zyVv+wyxJcaw$8^cN&i6J^_r*iX>n$Q=3#MKcsKdfIZ2E1TQttPX>n_-kImDh#iZ>% zI_?WU`8Z_AFlfRw@FZcV{|8{E3N${yhof-`f`k3HK zjhFQCd9&1*o#0T~Z?R-##8LmJ-|l@$u!m6zF`}$Lxnv;L{a7 zE~cf>_1HcR?wtZPZ)iTsrofe(KJNUI9Fezuym>r1vfcGDS!{A_yQlMdU~;s5;M414 z$?@W$kCDHVVfM8DSga49JY zzxC0+A}RL%tNja4igxccek8@?4?f;apA?=?IuCCqLFUgo4sl7a`isWpNP^nmd>q;& z3C?`?F*;ik^!=&z9rR>U&x^r7jrM8$%$WA4aVM>xtycdqMyB&~Lc<@%=k$Iax&7T3lhMy#uJ1;s%zoC% z`Q4bG#ZTMzZ$|NKer|00&DfOP&&Mym8Z~qJSzy9f<6tgrr`T7cX&yf(^NVpdub+o| zeK9)a_w)1T&&KrvewLs8+2~uy&;FG^8xITn8GGhGV`x!7PY(Ofcu~wR&*(oRq=cUp zmVYwdmh>~o_+(g0`}O+QN8^1NKMzHIG_2+P{5OlfF7Icd%^wU)ML*lN{9wGT-l;0#9O1O;pgvxZ;gZSvviWTM$HC(wp;YZ*woNZd+j$yu||F_zVzCd-&pe$ z{@TdY)X!(>UmIhZ`I#Z^mGQZ`pH-T?GDf!av&;RL#+_DvI(;vV_HF!Jkmse5*w)X4 zT`!EP?ftyd;f1lXgXa15b0cdfjc3wxV{~UfQS!O*Zx=uN9DZi>?WS?{eP*2QuKRy` zYSixOm!tgDSk+6%x$09Rb05vexhICFub=5hJ~18#`B^IU6QgZ^KmT0$*w{0`&)()^ zqwpZ@|IJ56^k6@yJ02NthxoZR+asgPFh9BFp%Fh^^VRC1QDmf_ub)0J#s&MCeCz|` zMTnny3O_K~glYZ~?i*Xf{cP0zzLC}HXSa{{j0l^bBWBz)E=Tz3D}T?ZVb}3GdDn<_ z__<=xUE`zE&mBqb8lBvJ9$j?D*yhoG*S=$9^!fSd(rsg;->=Wt+%`@GbeuBWHj0h% z>;3y%hJUo51)JP5u8r}t-2IzI)p35-^4&BhkJt9|+%z6e&~e#y!>BjW&z>D_7&9mN zIq3CuNBVrKd|FZQbOXqKN# zt6Vi|#`?MX>=h$=j-MNbUoo!F_3L`ZD@K|5e(qX+*>ElJbDwe9IJMBv1J^GZxfcKb ze7s}~UZV3L%OzvSQa_Jv`o~DJ+|Ls&{xMpw(0Tp%Z)5IC-H!U(c(6*h1^zZFtkLbh zi-vuzmg{oSIJC~s$JgmKO=LTHhv}e8NBT;!#L>YfHr>_9{Sn+`6*-XAwS!UJ7s)I z)Ol3olu_k~pEVDhG(wL0S+>VXW8E=5?mwL{9v;{6iaBBAKdIwa;e^rUl%F3@9yg}_ zrRRr1$BpBsbzUVoZu~r>aV|P$R6pnE?%KzU5$F9}bLptD?1G*L!jBr4F6!}^{-}}m zA3rVYju`bX>G9wAh!J+#&(`-28!N8pdB}U%xOCOe61fi>DX(k0I}?o>H~jq3F3}i# z)6XX_4;ity^!zsAka6U;U+&5wT&a6pAq#=&uhMY#;W&z-p;enIPt;H zgS++`&p+zC>#)~I_n)7E*L#fepEcfzdyF<;^!P8a#|ZhV`AytyO!=nq_1IF?<@f8A(Y&Jkd_*p0@coB{r-ywUiOE5M6qHW*3s1h{J01|w76 z0PQI@82R&Qf0nH`O6LzSPyO{q^#TFDxEg1e1q0k~i!)jj3UE@UIHObH0DEp&XY?)- zV3}s?jKM_%{PJL}5mGF`6aKYEWO0o%?^?rCBEW&W*BGNq23Wb{8e>AK0Drz-ZA>X0 zkW0AQm{CT{l~`@eE*oI~#8t-Jasig_v&vXdKETgkRvL>c1bBG%N@H=w0H;*eZKVLa zoLONksT^RTVJnQqRRVmLe1);7YJgjpE;klb3(#3_xiPnTfDNuLGiKKa=yjlFMoi5B z&u3g_OsS>qtzT+H*AD3O$4iaTbu{k}mKff;0Y3FDF(T^)xG~QXBeZ^i;kyw9C3Djl?cxnhlc z9Ru98W44j9Q-GFsvyC^pE&pVnOvBba zzzd&Zj2=C7d}Cq^^bD|3g&3n~uK>TFoMEKu9pKJEGmPiD4Nfw{IMXMRIB=^3k32xcB|MoO#;S^<5ACdHH*k z?Z1DM{AW+Uy8i2zy-9xmGw5}e-Xy>Jne;k7@<#co&$_x^-uOoOd_?tf@dmm0Y^uLM z_Xhc&DHGfqqi<^LzIm+j|VUElr0*UOXVUeWw%Lsp+h?d8peynQ#-`#nScZ_3^S zuap1k`B&H9yyJE9`^Q)GcdK73-}i#6>xaJMwen+Lcy;}6z1Pa?FS@#ZkNX<=N0c`| z_ciioUVL>OfUl9Qd#x%0&9VHv`>DJi zhvl;?`Z>RLB?EkQ{pIqN{8`HVo9>t2`pT>8`(N`4`AM&$_W7}w%k5WRU9bP!ee$;{ zU%Y>x{K22Qy8iT?_sZkfTwRxbyusfRyT z_9-9xis#7h_{FR1xBdQI^3A_=b^XuC&mTWk-h21e^;3UvyZjZ(ck;K(um3eF*QY*3KC`c` z^KZXR{wC#(UwE?o)?dH6er@E*^2KjlT@&e6`8$;V@uDZmzx1A~>+T0N`SLgE`+WV0 z@^>hIz4}D?7v6hy?Ws?Yhwr<(&KQrEzd=cVc}RZ4`>(EF_V2gI-6?Hv4{njaO!@Vv z-z>l41N6SX>#_3MZ&ADdqAEW?`SOG+-}OPNPY-&Goc_?&^*>B*l0QtDpFLWB>~B*$ z`^OvQA5y-kb))=?zeDx$@sE;EK1}ubO^=lSiZbx28{`+vX#4qNMb3VN>f^B@|2E|t zpZy5=k-tmz(SEr6ZOU(c`C;;_e(&m<$v#YO{yw#*hd)&QBg$vJ;vw>5|A5-(?>|`n zF6E#6(}Uz!{~?v%`h(>9AJOZ&70JI#dG^*z`Gz@_qjMpDjq-Irk>z_nO0Vx!mJ@$` zb^WF1N%FfX|LZr0^6{Tgx&Q6C{AtQZ6wc)*evIn(BM0(#DBt=@QNH*8&~|8kCMQ2m z`=x(5mETGEU)!hh-Zj;S+xzlIDIfI9J^2xY_79&wk^h?VHK7yvj!#@&zwi85{%6Vu zUeJ|a_DQNIQ$Y^@>D6`2Ka$@9h1a z_iW35OL_l?w&dIY?CSa*-`JFW%HOSR%6EK@+R0-#(0St0|v0D#|O$dw#7TKle*izyEJu_9@?<&day_Uuwq>&B>ppoZrXDXJ4l8_q$nn zO6h$kBUe2tUoIoRp7P(Hn3h+Rk+-DeXZ_99b>V@e{3Xh@|4zsc{>s($Q7<8Xm{NL9 zT&{nW%I!Cx{5r}f{7p>$A?2M+Oup@JX}kQ0sQdusz4u4tqrao~^$)_bMQMI7B!j=F z_PG&~pGEoJTZ8f!C_ntxfZY4q)%8amAisn1H9z@@^gonuf8PH{clvbv^VR>79-#c= z8-6V9{sZkF|L8xYH&T9OYbAZ3@;kry@6t_Qr{j;nkE9P%M#ujuWxqi`|KI;Wx|@=_ zaVh;dW#^CoS=#?5ZO8cUO9tgb-u6$@w!xo> zH-DSj<;T7ueTeejy{}7=f24Y5`O;G;jp)~;KcIZei~mkaFKGYr^{+}#qkM<@73rgt z@BX+aWxqrF+s>Dzr&GS~SH2|8DL(-JT1tNR>iUB(`77ym%HRH`D}99W!#Dqh6#OST zjv;?8-SSf&eqQ>`pYmOQCjHw_nfR>qknhoYlg~)MK>6F>{`O=q*1=$Mg_|>nGZlwI-^3@Wi{MzlWl75f!^Pk7kw<%wE&;1g+qT{s3-X}eh za`Rv!-ADOf@E++ylwbVj3#6}7{ua4gO8y7!SKsvE|dv{|ZU^Ey`bc(m?tG<*0uu{gASsJCVx& zb#)#5{*g4G{DRYwo=o{Gzqu>Dg7O)7TY5L8aNCCTampW`anj#Ye!9?<{+seG|5BCe z|4r}r=gQK6a{c`U>4}uzeHA0Ui1PPtPfKs1yze|AeUS1Y<(TvUW#We+$*26wKL^r( zQVO^Hcv$!!+Ab%4G~B1W;gkP7dGC8-AB^?eq_a|4ljl{)dN|pHR8H_XEQ=gUSCzozuh6T`1ke&&`R zpZ^2pUv$5I{*RPj%6|6zdz63s{STl2fb#2~d)xVse!Bmb`_5OCf0Mo8{Ku5v_+0t? zzbU_x{p{c;lwZx>FaQ8wLjV{CfFKJ%o&zAv15gwIh>8G|5dcsDfK>rVXaLl708%3W z8e;%5698J6?l%BpOn`zGKzSRW@D!lp44~*7pfUjnIsmaQKnV|^nh#KF0Z?NJP-X>C z3j_d!0n9J~9ApDH&joOp58$E@z)>-P%P4@M62Pn)zzHpYYkB~uMgiOy2XJN*z%3j= z&jp@|3y_*0AgM)wG?oF9Sp`T71nK(+ zL5>N65E}#qE(jug5R`-1Z^K|v5#f}pAfK~f8Xx*i1SQ4lo8L6DsUK^q4#G=eB+ z22scgqJkYnk!cW>W76x0*w&KnIRIg zLZo1aNMsr!rCEr?<{?rcArf~&r0Rx9(hHHgA0p{Rh%}cWl3j&J8-xJ^!;oRZAjgJb zo}*@CbTfD>0y`}g<)eHhM7qiws07*Mp$9YFsNE#C2!NZ z)38#Ug_Y<$tdvPuflgRq-LR7I!b;5#E2%|TX)MD^W))UiAc7beF&HL-a%{xNa}kB% zBSuk(7*R1|lu^WhO2lB*h>_4DMoo_xsZqpej3Y*75;0mhf> zIK^4SiOwTVnM54uL>$(QI0-M})clB(T11@2GU8-b5vK*Bn1NB4W1=|6Mqz=A8VnzW zB_Rr9ViZPD5M7gg$hR7o$QN^==iva6`l1~J0Gn2}>*B*(^#0vB@_K4z4J zm=P0WMg_%;xDqp}YRpJ#F{7@>jPxjGG{-R`JBb->93!j|b8=>kRIQj(uwxE8jX9-R z%!$ooPKCsrxD#`#Zp=w~F{kdwob)2*G?y_ayNWq&NN+s@5o95g=OD=OkSPif=S0Yq z709qEWD*)=YC2?6BgizykjYFS)4~uW45%_D1W603c^ksS6spA;gvmKn%Y+{1K$Uf& zn(&}n^P!qrK((=iYGwu17L1z=6UT8jZsxf-sPb{MD8zA9jGJW?2T3JvvTEE+XmPWq z$Ia9zZZ^hoGc$>sEgVM)BknS093`!|o44aiVj6dgv$&F+$K5iCs|hFWvToc>cyYJp z$KBK-?lzWjH?xYnEtp_(Y=S9p36$d#Oi4(PoS0xLN`k4X2_~r}n7W=|(xU{^94DCU zB*C|u?&*}1vbUzxfIOvDYhu2 zU_nf=Wt3v_N{VIG6jRVrY)z+iMk%&2PO+Iuif!Q(s2M4ZF;k#!rL?@Ag0*Q%E6!4| zK2K?7l45F3N@Lv=Q}o`R%Vj6S~!hrM%rV{G^$%^FK?%n+BEGIXKAHA zPkUvOR%=e$W8Jh`_tIX?PiwVB+G{M+US^f{S|Ee-FvI4U3@)%4w!meKJfC4pLdGbF z8McBlW?sp#RW)N4v3Ro$#x_p)By&w8~*)@v?ld6o6rkm0B?BZg(TJkM}NfiW17;mU{sIfda^ zl|ea;;c7Yq^CO09j2R<8VYn7%K;EF+Oa|pGM$g;y_$i|oXS6(L^fF;U!C`dPWl+Im z^qSAG`30jlmW-8OF?tK;xIB}i?RU=3b2-TJIlCz23|7q9WhG~`TF$QNIanLz?8Z1} z)FwH*MSHxwkz?~_PR(06KX2z)cAE2xvz*1wbAFlRn1Yk@SvRK^yqsV2b8Kyq^Bc>Y zRa@o!7RUn@<{``E5zFSe0+;7lKF^heyv~Ywu7dKQs^qzwsy)?_~wRv8zkUXe6dA;i9QQgbyb)TMNk=L6`T3+S# zHYhMGEU+w7P+7KM7r27L@&&sj6dYD8*cDV@s!GAGss**G73{iRP->%s-5eL3+N5B& zae=8B1-51u)S6ZB=@~S3TJTG=g2&DaeuWg6x>NA0Zh`80!LR!Tt+pum&1J!>tqOh{ z7P%r*1SPgeuek_IVv#Q+x~>#?RxL6mt;pAOx^GnE8{;BdniTmKE`o+pW65HWtNEV_9UItKz5yOI(R5p%PotX^Cg~ z65kL?N=YnD%Svg=YNcsSFY&ceY1$am@}x9v;Sy>XCB0#mP}3^uO}nHtrlnD1R#KYt z(xOaCYQrflShu7$z0#uQm$b&Bv}i0#T60xev_Kg&U>P=;GHS48rNNcC24AM{Th<$5 znXjNSXewpCs+LhxEAw@|%r!@4zBw-I%}JSW<1%g-WxHXPanmZ>O}lI~rsZj4RyLaR z@~A?}X2U6us&3hAdgW2wFI$a8dDL8%t>&scYJ&>XfEBjERMZAr(HdN3#PXFjYVbATvoj1sFbiuY3+fiDS8bN+Fw56wELWeidXunB&7pN&mZ^K}xaQO27wovPWVPCg9k*bW ztFl$S##does2WwVYBZH9SJ$eunqGzVQFYcBSB?6lI&0x7su@+KW>!(%s_J!{9yhJB z%^5Avt5%a#)tXb)YHpS4Yjs)kt89HyT{f0gtG=o(TVie8&}u?`R1=!x8e5;#gtl2D zHLK>-W;MSyuPx{rt~)iO?$$`%tBvb^&8{zM<0d^@eN`K``MS~+>rPXt>vgR@tB>ll z=D66u`y~W4ZWc?#*Ils zY~coI84a#wHbC2IaBaH*Thj*Lnl)g1-r(D$!L*!)&~h70+iM7IzrnT^^tfe%ZLb=W z7Ho1&wkb5l=Cr9a^`_PwH%CprJ!#HcxQSXuQ*W6~)V7*>+iohYX>-(?HI??fIck%p z+H#uXmfKX@UUS^`n_6qpoV1ort-WflTCl~n*p|>zT6#-sja!qJ*fv^ri;jTWR?BYB zT1I=`nzjjDcWBvdnQgB%Yx{KHf^J{7toEukX~Q-;L6?5pYg1WKUyuO^u+*pH00un3K>-jT0_x2G5KsUJsQ?8ufI>RJff2x= zF(82nAR$bTH2@5nw2lRopiRqDU<7Bt0dwF434j3yz>o`+fCrS24~)P97@;L_0xRHz zV1NlS0Tf^ZYLE+n5FapuLO=1ZfE%JdV9*G#K{G&o zuz(h{14?iju!6II5}F6RAfe}S0&K{o$9e%RLHz$M?pI@rsYY{4;i$s8N}4@vqQ6>5t;`VK|g(wtK4gRhN|AbQ3Z)hrhen}UXcAh|J$C4S zeLA0RaYFOZf-e1#NB6;>-5Uk`^d9j*1stUaG#~(lE=P2!)8!b@`^Yc=a4Y}hF&M*q#7ziUFX0Jzz}$cnbj0rvCqw`u{Tk z_T~Vb6FLvz(0KqCfQ|=%k-EWkigM<#0OAb2%vQ_ zfR0fBg_Qs*ssXgA1yD~9py()o%Hsgqo&?Y-{+VBoSTlflD}Y2hfD+RHs?7puZyrGB zB!E&*05#kI>UaSp`2mz!1W;=kK!>XUx&S}(>oLOwF~U2Z@wynq$0&%y zN)Q*-Al}r1xTgnkbQHwpaS(4$g7_5w%&*6+8N|F5#G)OklFHimXH8z5}Tm+=~2r38>v>`^&i4s92HG;OZ2NGRT|`iO89_&@ z2)YDOI+sHIcqWS1*eLFDQ3ClWE(lS)Ax7~DiX!UEc=xNvc|?pmy3}UA0q`JMmEG4IYBX$R$`>2#>kcyBYizaVxt(TjALYH5+i3g zM&btbpsVgCdv2jJ< z;<(7imAnvF*2TDTjN){B8mGVD99K5AxYE<(xHO6@<#Alup2U??9EU|CuCQiY;jOqL z+CTH_mD((>?9JoKIf*MNC$2QyxYF_BisZ+Y%p$I|mT~296<01m0V`K-NeYteG%)D`AK> zEl(3hZI&?h<_Y7RB#e}kFdA;c=y(Z3@)Jg8kuX}zgmJh^7#AQ($Erz(VUiBVCLMuG z;s&2|@GX;086dc$o zhnZ5}f0ly#^AsGC6ihoQ*mP6yz)L~dPr>XW1>4IMJX)pTCH4P{Fs(X}W3Uz)LH#pH{Mqw9;Otm7`T!xda)+!VH~D%NT2H#^`bx z!t&Jjr~dzjm@!UJ233`eQBpI;mX)j4`k? zbS{nh{qpVXIXPuo%);YsjrD0^9s+o0mt*kS! zvrc15eg9e3*`H^fA;~IDC+jrbtaIRH9oeVlMb>FAv(C{f>s-r+*xs1rj(0 zb3DW31%_D{8Ri%}g9@D{^}He+y8 zhN;aMW^c|g=Y)Z44#PBDhUs_=Bl(Q6wqTgnl3@;4408c;V3TU!CX-V+Hm3?)4sY_* zzZY`qx|masQ4VY=Ikl+f)J-j?_VgUy8s*gTIHzt;a_TA0!A&ElvSv=@t(+>_Ib(C0 zQ){!Fx;M|M=OhQWoSfQlb85%Ssgj>FwiY?Hwalr9tDJfP@_>hVhG+67M`soUE{}OW zZ{~%(xi03-W0VKGO5QB0d2>_Cn>{^`cSm`%JkFcjle~F~^N=_4CTr$R-pZSzoj3St z-mJ~?=H5JSo|8P>b@FDz&6^!BZ%TgN*j?n!)-rD%uJYyuD1Z(uFde4ga%{mBxB~9* z1+ya*+;y?w9-{&{Pzr8QEx4On!R_e`aQx87?ZEQDmxSk=eD1%)l-> z+_cElXGLazUSx)(sH{13Zon-v2VRkp{i3tBC^GG3kvUow>2GzH&?YRYoAe#l*pk}i zN@SBSxtl^s-4ILa2`Zs2rKJA!wWXERzFs0*qmo(~m(-m}Nj<|QWz#6BRkNh-S|xR0 zmz>RMNv+RH>i)c>4oOMba_BsPTT&0ak}CTpXKPVX+sl%Av?{5Wpp1A}R(YmuuCZma z%asYwmt9^cn;T-;JV9l&tCZDUwQO!_WwWoB$?m9ZR>oy>XHquLa9QDvvRO6D=B`yX z2X@)vr)9G~E1UcCvN3;oD()Iv zal2fFboh$f5i0J6SaDBK1sy0A^+2t-TUy2K>lJb^s<@SL#od`y+%sHJI!48 zu`DZaEEagy6a ziZ*KqQ#yYzW7)kq%bpV!b{&>&xGdZ8SXS~`qq|_)){QNmV<=RoFACY|pG}yj9gi zyK3~NbWUMb)%NC9?VMC$pUyEf+^W{`s+#0ijsBvlwU$-wa8=bVKn;knMyEV$7RS~s zfvaJWubHAyv)09$b&P6YpwyTFopIaLYF1CL;lZe84#qWWds4GbaSe(_jTOzB#alH? zv}=YqrJU8Qy?M<#Cp9>5YF5LoSskxtNq)^3ENWJ3S+fpTHR}S@fduP}#MC{Gt$PAj z#}Z#RC86%Ei*@f9)q$+k8Ck7+n_AuL>2)lR>ZUxdd)t$`cZ%y!GU}{k);->;d!k)8 zq-oufW_53GUiZ#P9m-DKYq)i<BmGxZQDs-I+AlGu%)FqoE0AgWa_n?7(g~ z!nENDvj)3AZ?HqsP`XZoZMqHiz-zFw-*CDMIuEjJut%!~dkLDT2b*e-X=-b1Q|od~ z(&L+MPiSfzVpBUoP1IMKYF}+?TUt}=>rK)hHQoNWsqIXf+8J&tJ)^1h%%-+$HMN1= zbb8aK*PAu9{drRxlBUvk=y7gSJMfyC>^GhMg3gsJo7&N;sa=8=5@AafnU=N2wyZAK zA|l^%MWJPFh%M^`wa`FmsROlTZD}p5ueZox)N%*ombEi!S!cMVh(=2j&6c%mwXA{N za>QxN6K5@Jf8Mf&q@@g;mNsx()`8cuWWVJM7Icnf*|LsSE$b4rkp$bSL}!ZD*tXZ@ z+C<{pt|YX*4YBQ=pf-|~wkp%vo-M8I_4PK9M{QRgx4oT7+dIQ;MKao&WVXFstL+W! zwj)j3o-}KF`}4LpByB}@+M4XPy#uf9$$s0B7nIAkceHAImyp98!*LwTaRSd_Uf{TO zk>idLNBez_a4N@bY8=;xO2kM zKA$6k%W)l#<0PMh-33R)CC44EIPLD!Yv{S>d!K7S2&%{863)^yQcgT3h*9?aJCz4@Ac zPS$9jzec+5n%?o&bje?X{lyv?EZ6kI)tY_*)@hr!js<2N3hcTqaO;e~uN%CuZm)~$ z_Ay#Vg0fBob=}_7*6p6Yt_q`dhaa!o+mm(s6t8oFv2F$>2qJA%7zcf565^4Hn!V%-s!>-OPl-M#=DpbIx}m)U?_cEcCA4W`R)7`ws- z+Z8wbW3)kSZi95y4S!SH@O%1(+8u2;yW++kpBWyBV zag#ein^f+bWK-SbwzN&IuWvG2qfOEoZ*n`6P43Lt#65G9+qE{ifxW2+(@iYRHo5)z zCO0ITROXwc=WcQb-Xz}`}N(=9B|w)Fk^mOga0NZ;Mk54lx@;ex0Rl@ zZTIzUwKv*!I^%77XR>Xd;cc#GY#Tju+upUd?SZ|m3Da#unr++r^KE-bw)LK~?eyGj z`@q|_Wq(`iF18(Mxosb1Nv|W_n95oXLtNAx5M=L9pgaQVf*5ae}Z;sd$vRR z>WU>rj(_0o__DvF^%pyiyxj4RRy+PBb z-_v>68SySZ=8evT=T8mZ6fB+>ZF=04H^mvx@6CDsobXJ?;a$Py`Hsi)lFzf91@DSW zou}c zoyD#@SniGvSG%JNut)pvJx*lyu*mLB1#S3?k@yxUlIBJktpmtqPV{}M*B!o_H{|!Cz7_m z=;`~4G}<3Y<9$b(>@QC7zA75~R@dBjMQeW{+WVR~-M0p_eNUY4FV4xnDmnXJ*WF)q zy#0mb?`zUx-y1CV7l*6;#Rcqe9j1djY=`gi9qKo9%&yqsPf&;Y4IS=4?cf8g!}s+L zJQ#J{&bVV7Ogj9T(J^~ghacFTkudF;(yTKQ=N*1XI?RF7aeHouKkz!d?049MMaPwv z9sX$5;VW>cGgYkiLFgX~V83$(H zIv5S?gHdmKV9K+Dku*OT4V?qG?;VU}pVnU-xbpH~bhJ7cU4la}fQQ_GIm83@aN6Y# z;ebEn2g0E-5D%v(=#Y+wXl}E5h-K|?+Sd=EJUZm%@u4A44yR}MkQo?%2iD~xB=^-5t9a@9=;dDq28QD4XdhVeqdxulmKV;>_p(ia5r$?*9=_NQq19+qlm?JV^ zj}~3-NEz@)qk(Yb48)_w2|A+v@sTd8M?}_+7JdClkw-@(d3@x^lcU8MK2it9k<~Yk z+<|qp7}!VJV0vW9vmrJ}jQ{2Tpqic7mwf3y;ShTxFZ`!p7v#ue{yW?}x#eJvicipbp_qt=r z?;8C@*B>mqhP>*IFTgRi)nhC&$53RC4Us!$ME;nLwU1d*Jf0n+VV9lPTASQ975vr~M`iN>)ln#a6o9nVDjm|p+!RGb}CTRonglVe?Uj(yQR9*N%Z zO!AM%;^KHAE|0Cj>UeemPN;63-~n?22keP4;7*tUe_{@V6Luh;SOauI$9gAZpq?lL z?PS^0Pt?KagpT!2w87+Ld5TZCfpKCF%oBcKoh(KB#Oh5?ri0muCCyKk=j22mI4AzV zJsAzWlcnUJSpCJxVz4~1 z&+b`0VKD94(yZr*^PVsyJu2It-*bCZwmm`idsMbPUt0E@!Kx=*vVEa1_O*f5ANMEy z@tM)L`&NHEnD%XX)_0_Ne>`;he&6elg1SYl40#GV=wcgjfo zDfK^2SxG##By>vKuTvtar;4PVI+A{>N~2R(8lP&?1;?&b;&vPCHHhBd8aekKOIYp(}lD=^#-fc*(EpwGCadFa|UJh%#gV= zM&{2dld^o=# zLwM;7*-LlGUwXrpS!wY<|k|&o8 zC3|69aFqN7y*^qNFRTl6L9g$EyHx2f6=)asrG5b~M;H9%_`gfwQ$&^RqiW3$}PV!epQ;Zazm zxz&iqa7-j=7%F+C6p2pQ_EIup-lqjOH zc_m;3)qoM!0!CC1;Ls@G1jhjpb$5i0;=Hmy6Q@pu}OkIVx~jL>~f zz@RaCBjN>&m`}@#fJ0;QPGl8uV)UJZAPB-V8z9UEnJ7o&wR}*ev3WHt2GuB{dD;q% zzNkGR&<&1*Zg>)Oqc{k|Mvw`aK_+4anV20k!qcEiVY|IWB(J8Gr3u%#gNQ;pWj5&0> z8?qu^$cp(PBetMihP=osR595ds*27|0kD@S$Dq$n6hV8HxwxfEO ziH^cXWE}RxldvB(!Z>P%xri0!Vm8g;o`!L37S<#4upT4yTu#`Cx?wxwh3%LhW}}O+ z5nG1+$SUl|V1$b>5gcJ7e3Xxv5g}qk#K8v^$4VKTPre-7_muY z5j7%a)Qa#in;tifn6Vix&m*H4i7+uIVntoL&5KN9euRxJBJ>*R|0=SGu~8u^M#oVU zrRS%ySe52nYtdO$k1{kaOJx~lW0UAIYDDd*6%}IBs2!U{4VqUyj*%!AbLhGormSgRYG#Fli;r@7I~*fchad6W)aUr<77 zV+^$`mf8~cGka5j01P0~+?D^eHa1%9Do-S+D14uf5WBu8y?Ny@Bw)E0)Qth0eI#L zfR}&(pwC$VmI(l!4FHh~0EG_#O$dOI7yuI#00|`kYH9%NX#sGq2f!mo0dVU$0PdOu zz`ZyCQbqtY%mCGL3ZF$tom6GUYShbgqZcBS#^0>o|n&nuO53 zID}G02sO+Q>R2Hp*&%e}G=y%Oh0t^7A@p(*LK!E7T5bp(dLeY-htN%n5W0OCLU*r1 z=zbW+^w|o`v0*H5VT|}NR)sLu#V{T#VVqaPcwGzQV?B%?JPPBR$6kKjj+BKX#E1m87@;Cpcdr;G@0 zm=WBuB3QB`_{M1j-!_Zj=guSes6C*7*Mh?9gx$tA;rbUe0zKoH(S21!wqI za|rHnAgH(y?068I`4Bu}0l^cO5Ik!I!Al{1UV@2(T{aE|TpZlM$H9|?IC!=g2QQ;J z7WCN(P*>w%UyFmG9tV#a#le%uaqyf;9NdTFAZ^4!(~N@yD-L8k4jw&?gQv{m;Cb^n zcm;`rtP=-qHx7=xIJorV;4zChc z3zP&Zs0p;8CD4hUKo1!u&@JNxdfFs`USuRt$xNUvD}nlU0zGV+K#!j#&@<)(3zQTts42Xm zrSOTK!Vejx@GavMe%d63Uu2|k$xPubD~0=Z3O{U`!jGS&@H6Hqe2i@hCEitkUPW-d4ZB41vNu9vO%cG)Z$a9MH#pCwNcvgFxfmb^@%&pfDEvae;yP|uP_jk4s)<1Bg3Bunly zXr6?bB?nfP$aa=IdYUCqnPtiI=2`LzCrjFHmK=Fma_MKuV-{KR)Mb`Df0ZRy3`6sv z7)bLVAmSNFr(YnQ+=F9?J@AwXW+vZ41B_pfzMnq@Fg%uBd>}dt%TrVh(92JyX z#|7oCNkO^SC@2lHpmeN)BH0Dy#%V#hZB|g8J1;0NcM3|&EhvXxLAme?%1w)ca{IEN z+`TF&_cKL)@GsJd_eHo5nK`^b`QWJ?xq66(ht_v4N`iBm`? zo%EAVI_acqWMpJyWMpL2$jHdZ$jHd}Tz8c3^Lw5@;l5uoIpzAikFH81`nWuzuaXh{ zxH6(&QAhMg+KB$a7||!q5q;en(NEYT`ZZ@nf8vhlpS%&h=#S{r!HB*Yj_9YN5&cFy zqCZPU^e^ts-IOx_1o&G{!$y& zzw4tqbPW1}IjZkjqxyM!RKM$t>aX2V{iipoH~dk3DS$U}!cqNVG^*c^NA0MH$&nad4j#{Q)X=VC{4h@4*rWegJy>FH23wD{l z=alI;Zkhh&mFcEmrk8^GNCa8#8VMRP0 zRm7WdMSPxA#IH}q|imKv+xGKI&s^TA}ro)}T z4tM_gF|MXx#x?yRU(?@9HGM*^>1(8>A1O8cs#?<@Yc>6&QPZc)n!aJx^pkc?zwXrZ zr*2LE?AP>}pr&tyHT`r{({IK#{drQ;zcO`wmaXgCsIH&k>iR8Q*I)2;{hL(R=jFP- zOX~VLrLNym>-sCLuKzIV`l4Ca_pQ2q!LIA~oVxzTt?R$My598b`f^a$55u~CDXQxa z;=2AWsq253h6nfd9^Bh|$GC=f88^I#e8YP$HM|MA;jNK|cce7Dt7^l0tTnukM#Gyj z8{UT1@J`wd@4D0Qp1KY1v)}M$f`+#hHoVhO!@C(byyr>7`^q%ES+?nIqo#L;YkIeE z(|f@;y>C*}o0ps3E@^t_l%{t_ZF;Y?ruV~WdW&Y$+qatD1-t3pbDG{8x9R=zo8EHJ z^bW(OcPVOm58|fxE@^sySj1q27=c5K1pnv|9xRdCA!1HNh`A9X=2?Q6FL1xkv11I6#u$+sV`MzW zDEt_sNn^~MJjU#hG3Kl?#@trNn3viZ^W7L@7R)hb&l+RS+hfdKXN-C6jxj&|F=ighYx5*gun;n4;) zOOxifv~G<{C+u~#+eN~?JSIM-0T$%Q-sMG!< zZQB1}PW$WDw12{$_OCh9{u6iF{}fF7o8h#7Dw_6h#MAz>WZM72%=jETw_W1c4*^Oc=tw$UtehMQ$>;aTPdKg)cR zW|?_;mf0n<%sFM2xuec9ue4d_hcU}6nzPKlHOpMEXPJA>Ec3>lWq$dy%yKZx9EP*Z zrD&FU5YIC2l3C^tJ14E6Iq4WTCtb#K(nEeudN0pOYh+G3Qs$(q>YVggo0C48bJB)2 zC!MtCr0dR{^wgb`J_mEsRyZe}j^?DB@tpKLnUlV<^U^k&m(FnW(k(nMz2N7iZ}Pmf zOXj6>%Di+(otIu|^U@DvURpHgrG0B&x?s;s_ndj@jXN*>^5>=HU|u>5=cP;0y!0TR zm)<4w(jOM?cF}@yj9V}+;|1d(zhJzV7mPKsU>qq6##ME}c&sfLAI$}0!&)#-+6%^Y zXTf;tE*PJK1!F5*FiuAc#?5%ac%Cd6U)e=t8!Z}VxJBa@UNm0ti^ey3(by%6#yMrt zxT7u_ue3$uhY9z#)}nF2UNr7Gi^dyw(fH*r8q2|=aTqQdm!d`ELA+?ZOBRhk?2-?6 zw*E10$-j)3{D=IK|6X45*T|B8q%8SY)g}M2w&Z^_m;4QD$v z_o>#hf5Be%?>Wo<8+Y0N6)gLQ;j(`zTJ|5r%l^A$+5dwuD{z>VFlGslSyjgDD#7e= z1+!OF%s$dE`@w`eRtvKyY|LJBF#E*C?56;;n;~XTMVP%2WA<5s*)MR1%A*xlblYa(l@bm(zTQ@&g>*fi2-Mr?kn@`+z^HZ>HZiegTsc7B25wDxil6CV7yJ7NZ!xXs< zQ^p&n!f%+GykYK;4fCwBVcu3Z%$M4R`Q6+w_pA-`yuD%GbvDe`?uPj@*f0;m4fA5O zVcw57%(uyg`5SEp0=F4RcrzgUW}uSI;JC6GTv0cJN7`oa!P*Q?*qgyMXES)>ZU&#i z&EQnD8Qh3BgJ;QR@P*w9c(fIW+*Tmttw7x9eg<2?LAVuMjJAUN@mBCQ*$RFmo;}9#>}AZe4|$$_Pk8o7;n}My z&py`RfozLsPue_t-Qn4%F3)}rdG>U~vo~X&eV*{_SG3KZ;kMaZc$Yn*n+cQ5}d*(@d&%EyJ znNQt4^K-aoo{sj+oAI9cJlQk9qJ8rWw{PCU`{oON-~2}Q&2!4Wc}LwhUupa14{P7N zVDFpvoPG0+yKnvq_RYg^-@Fvj;iyW}wV!wE>j0wTPCR3f0` zih!=D0(ztg=z}Go6Sjb^IRbj(3g}ZPpi_~6Zo~q5mI&wzI)+5<7?SZZr0~a(MvkGg z$}x0XJ%(Ot$Iy4{7&>nsLwB8H=(T$c{S1$xi_tN3KR$-uCdbfk?l_U~aYFdxL{*NH zE9!CbNIOnGSjWi;`#8Dg94AlQ({zMvx_az{kQM?~R|h(?ac zS>=e_R*%R_?TCE0j>viYh}?CK$ZPkA{0xuC#psCKkB`XPr79<^ zE9wdBk#@rRV4twAIVY?q?g{Htc)~grov?1iC#+}53F`|wX^GrPOU5THg+FO&fkV zx7E|(OYL;{-8vnfw@-(6ozvlK_jLF(JRM$)PKWp7)8X6XboiSS(Pb>6hrEd1DqK~$St~(-n>Wb)dB%+(Kh@K}R`pTU_x9}PCfn}dKH6u= zb>}R3>YgQ^qqF2@e3m><&XTX(IdTi1BQN-KYwSK2x9!#YPU*yqSS=Nx(C zo+H1)bL3KVjy#CZk$1^C@`pQbUB>6Fhx~c#y>i~Vs-CwVYv-+x_Ic~NbKZLDp0_?n z=dGLZdFy#{-ulX2ux{ZC)(ifE^-Z~8-BB-Cue1x+5Bq|3&$(c|aW7cE!VA`==z{ei zzF@seE?9rKi{WK_F?`5h4Bsmk!>j7W@UeC={AgbcuR9mRr|!k@b96Dh8D9*aCl|x7 z+@we_bidPFWhBL#+NyTzszaMW$w0mnR}^S=DypP zxx3C~?zMZF`x#y4?#Gw8x5;JhH@>0}{)(ciSCmKE73G6{MY-l&QJ%P0luywWR--}stM z_-nSRUb7!**X$3@HT#Ks&HfZ!vv0)L>}Sa}`wMs7mhp94;ji18a^1eIUbkOr*X{52 zb^ES!-G1#}w|_?0?fda{`)zXF{*7-$gufA~>W%1;b|d=W+=!mIH=Quv#ZrreBft2d*U+Rf;@eKWf2+>BnkH>01?&FFr7GkTlcjDBO8d&tY&dsXHh zYcluIk-4X?%zch!?s+0}U-2#O1%HeCrrhH0sJFOR+AZ#feT%#2+~VH2x42)?E$%^l zi+h*c;{M><%0vFP@?O2IJl1Y2AD!FEQ}?#=IliqtPi`w;@g3y_e@FSI-cep@ca$IY z9p#>LM|tDkQGP{tln3!0^JT``&V?&eh}ZY-zE3#Klpz1kiQ?jSMNuUwfoUW=YI6m zy&rv!??=y*`_WhYAbP<+h`y;0qF363=!f$ldgDHbe#H->cgch34^ObF68uOb_=7|6 z6PMsmF~QFgg1_L0Sm7UHO?`-8Y7g;u=OKRWKEyxchxl#s5dY>MsjBu!{op)OpSX|I zPw^x5S@KBzf*-32|5(-3$LdS%vHIP4tiE<1t3Tt%>f7Y8`kQ~^sM-_fgZsq!6hCpE zB~P3$_^G4tPaREt>b%sRI^UhA&TIFn^D}Iy>WiHZ=7H88|Pi}#`(j)jo)i;s0LziIE{ zAMU&OSMo0YqpAD{SLHt?D*uIl&uiLy{=560|Czk!f4d*FPss=E3;$8mw2#_%_oMbR z`KbL)KDl4`&#tC@cE7uy-Ji*4_c#AF(X_A0clT@ZGx?hQ*1qvS+;9A^;e(23khaxWSFfXlt3%s6{=trYTy*=FlS@HoQ(-{ zHWt;QZK~DhP_3LxwFW$xx$$AN{G&z`|8K7ZChDlM~Y>MhdDJsjQ zsD7NH@_dRah+tJnDWO|V3B4pGWR;ZAucm~&mJ$j&%+eUC7R=4GU~ZoEJG|2O-R zwbOdPlh*TYS}*u%4`yCGn0fKCpj!0DX)m9oy#fofEGWa!T!!hx879YPm;pH>!HkPU zD;cRz%}6;dBMq1tqsPh^w4E{foQ#okGsZxW@q5CIPe&QQFV6V6B;yaTFn@x&nJm}M z^y6+O&v!Egxm)Tb-BMQRmipChDX(=)1rz2|tZpL0jk^8* zxZBSs-F^Y}u;2->eYl6s@jdJS>5*xrNA6R5N-qdrWd98aSGg(iI}O>!Dd25j2ub7(8)($+vkhkY>}<`Oy_;IgP6 zXHlNdqJoko{c4uvwJa&vS*zd4T6s5X6{2j|A7{gSk_`*EkIV6W+<@ArgfeB;69F0XW zFuNwD9Lh+!l%EPI7G~AtR7{zvgbGqzillJL0wX3&sVN&wm?-6@;uQS7|L333EJd*h z=4asV{Xf_AzrXjI@PG3*eR9V&{hxpGKiBlX`ME)ZqOvAMl`WW~vnguSp{Tq|QS~;= z)_D{)>{C>KKvC5YX6z!0D#a94NGPgFcT7{71-lfbTK_Xmb3E9k0?g8hV4X_;XPSb2 z(gORW_184jQ>{S*{_f%LzYKr>-FB)q>U948>uvZpc&XN~58s3!)vAW@jfhgMQVidQ zB-LutUBZ8JHZ^Xugqqlyv+0w&gbIPV83pEM)GlE_>k=Az$1u&B zV3k^3Lbu&9O!F>SrR^>u?SXCT|DR#n8-Z;a|1(VKj&nk@={Aef?FLOW=?tx|M|DRb3vvKWG{Ld_M}4pg|*pvStRAtqkh6GicPw zpuC$wbuWX4{S4|4GN>BD++37Fr8t8MNd`6PZVPNui)Onmmg}~_CAD&Vw^b9nts$w~ z>XW;z3hB0bly0l2c3WVQS`EG18Z^4Ctl4dq?QUz->9*jT0ySf|HSBj={Xw@?4ZAIv zg|kX=w^c~GttQ<=U}lEUY!6|%9x{S^2z+BmP3$2sFGKp|9#TY*Bg%D z-Z01ahBdJ_9Fls&KDjrnD7|4(?F|RC-mszfhTw{ZS+h4R+r1%}q9J^j!n)TR4*R`f zf6yCNqu#I-_lAX}H~edfvS5aCe+^OieuEb(f-5ThGei|IMb&?Ps7^D32F+wmnkm~f zGwRSx-ldtkM>E4d&GZK}Q;le*6w^#0p_wKPUMLGDDEHS1HF7+7pd#3z|1&}ra6|v+ zgX&ph(99ZTJ8O(OS@@o3jk=dLhW)J3A7qVclr>6m)+i)dqe=Hk4BIDx6C#b^J_){m zQcdiWhU7k}qV!2%gGd8fpVZL7{4~M%wEw!FQr-pM(*q0C|7U(i;DE;eulMOQY`@QP z{r(8<_j7!|UlaTNA-UhLDE&ToAO3*W?>BTXK25MZ?Z39C58qP1?t%9ifbAK9^BMnh zJ?R`~*c@iL93J6wxF+WCketI6C5MaZ-)}B%=s7%S=5X20;ZY}t^KK5;y&N76a=04h za4F8=LXyKxI`1%S-eI}CGs5ScnwWQn~d?Buhg?LCV#1*9w7qvp%&PE~5;FqXMp@ z26m%4!j zl2NM_!w4M21gt~06oF|N)#Sf+Vbm~7QQ0j;e_g@^ zEJ7aIfBCOH$Tm!tExRmR4_LOEuxyhrn>D#?R~gKpggqc5ojO|8Z^+!|j`YW!a}FR8m7x305ZPqFZCErPjR4%XqF^+GEx zcGm0v47&FJX5V4W&`#?Vg7rFrwF64qlm+&j1?vV2{=Fu!Rwv-jk#t0bT`?8H`XT&l z&aq(2aeu8j1J)4+%(hEiGI((cxO4w==JXWqGE+Ehr<^V~<-otgYFCg_VQxL{N>Xte z*4}BZO9wknPs4gUt#o-^T9*et90xX>{nvv_x}v|{8_bBOJL@4tv9RjlV5*phX<`}v zOK6Hh46I$?zZ)a!?>>dY6vgrs#S5^G5n%>cg0+kcbHD`FGYS}NDy(TVaM)V#|4fG& zVuPZFOqe6KI&RyX18W?&zoVz92_r=fn<;9|g8h!2 zqUN0xRdrL;ZX5PNUW%IWQ&cHPQClJGgQ66*9H*#elA;c2u-cfe7Q=SDHrT_oINa4@ zdGObSj@LFRf!QW^ytbSI_L>R?n+E=x4z8O4zMBcQo7J(}<{a?a+>X@-Gs3NDAAGj} zY`3suwJpWqwIyJ+(dpJ00|q;rZmqzaKkRKIiggGZ8RNRcP)6NJm8!Sxw8KD?t1egsL2BM6x6la7+k`WGQaM_r@ z*17;Tn*e(wVHShA#)G#eg3Bg>&n9`sf{=$q8mRkUhTi9{gmSeEl5^&k*o;G57+6>#72ZlXVo5MYAmhWlvBFy_rJ?#-0 zW`0ReJE!!t7u241P3vjz=`bg3^t6Xem=(5q+I@CUd(P=;SKOZVjt8^Aeowm?bmoBv zqMr6r+|zC(J?#S;{59sUr{4b0V1qqZdlrMM#)GLQg1shz!6tY7HL%p%iz=9E8hC0t zIBf=aZ6;W4R>xkOcfenB!Cv#gX!F5p3&3d$JMP+Y4E91aWvQB9-Ko=&52gGNIpjaDt#*V#0hb7)j?X|&_fXxgVy zF`&_A2z$MVMoTe`8VQXK=qwszvS^Uaq7~TR&BFc;%yhIZX3>SZ4lV=DOt3r zW>Hs^p=RZjK5IekvuawOwWs%4<3^t~WcFFB zcAqup^jQ_R&)V_&tZBc`Dh7SlX4q$en`SM=eO4psvkvHfYmDi)z(}`NxPEIE_gmnj zTias4H6`_1qjJBsLHaH5(XBPf<*1q0vO&I;wu-R{|+5OhM({EMXerwn3w`Tl) zs}%HGTVcOdi2AMNxZi3f{njC!BZ$cnSW6MiRO)c>v=L^Z~1goA7$T;U4gEG~p)z7TGUg>XtLgrjmH+)xVPqFM;+S|Qxm3*m%O2#3u=xMml^ zd8ZJ9S03(qg>c3%gr%SmZbgM~IWC0Fq!1p`|9mozVK~e%EYC2!2qu{XHkk}AnZhs& zD#O$?hS}4>E;GO|Gr=#j8D`F5n2O6VJ06&2KG_69zcr<{-0X4>I%4AX9Y*nO$#? znehjiQZUGDMT5+8JjgVYLFSPD=ZbOQgJE#Ocre05u*4)V#bofr6mY>*@WC{&!E`Xk zOfbi6u)`cM#9Z*hJaEQ*@WukL#v(AoVz9#!aKq?f@T!K56>iv=#luFKA2zndVPi@f zHb&)PV?!A>7S&;+t_>Ue`mix!4jXIsurcop8&!AM*!6~u8GqO)1;fTxG;A!#!$vb1 zHV$d9z}OK9b0ZRmMXx@AAO;^1=HG!1{{7?25teO2F-+i$2W9`j{*FV0HPhPW5@Q=ugT;e_bj1 z3u@7?X+?ieFZ$zV(O@rpjo#QK|2(O-&-ej_RR2lPLGivvdsgQvxV zr6v9|w-m6mR4}wO@UwJqxlC}mZ1A-laJF19wmh)70HM@-GoiYYr8}E8$JQI}hR#e8z zaTzz0GCrg$4g#GEa}|fMY0LZzomfkglnSt*Mx+sT^NZd9kKW$~AResi_NEP2JOL>bO}` zSM8cQ=hoC6ucl51HFYzpsY`K9Z6r1IfUc`xN2x1ZU7h9Y>b6){!HQDBiBcD}y1K8| z)d{n%uGw`JOel5NtE)3XUEPZ6>T(Q*c2ZXl=|+s$MvS>e%<+ww7aQ@U+=$neM!cXk z;yt|)kDHBn)o#RdZX@3D8u4_{h&Q7~yp%NJ1G*W5-xRNK&3Kk?#@k{u2CpgJP@3_g z){OV{W;|gw<2Ab(gUb}}dd+wyXvSMnGhR-b@gWO_5{GDxM>H=YuvQVht{{3rL-d}G z=y4O#t2Uy+SE6@3L{A5Z-i#2vlpy+m9ivycF?yCCqqjw{k7V$Ulrefy8>9F2F?zxr zqu1;)dfpv_u6vB03C8HHXpCM?#^^&99Ham2BOd%BaU6`(aeZAG*B7*Lea{@%SHU#` z(@5X(#&ww0)HkDX9SkG=fCYc(KeLDjcSxK78*@V6P$s|@nb7ym34IMbqIq{h-}NT+ znP5WSiYD~sWI{h=!42XjMUI~od3jP?S0=>;ZBpDbC&g8JQk-)q#T{=_gc(b5Gny2a zl1cG^of5$e5@-1-aa#uON0|~AwJCAmoD$dUDG^K{5lkR)CYTbpqA77XnGz4#X%BPL z9>-66ybNBCGVLvB)83vr?XB9=-kdw_?F7@_W;E?BCDYykJL9czGu|ve<88~}>nLFI zXyEFYGv1m#)zM*$m00~^N#XUG2M<^*8sME{H& zc9vV=XSr>8mfKKfxkYW3+c#&qHG7tucW0ropXIiqS#CL*Y@M@xe?hHF`ukiEswmffdDD(EBHgE5n^Y)rMZ|?^4_Et1+FDLW%Aq&0> z54MZEpsZ^P%AUEPthx)zPOzYCMhnVPvY;HWV7c&Mw8&twXkfCK;JLV9v;^R{ME_hC zb}7RAQpC$k(Ym%2?U_r_s=E~J1WVCovJ@S#V5RWO(Y6dGinbi>n_#85%h7HCCQ7m# z9rBpv<-c|byJy18or~F>0A}hE%pUM7?6$lD_QeXjZ?3Rw?h3mbtgu_j3VX)NWh=dPMN!K%5LteOY^c^xwN8XDLd?wYw9teIQMnt8~t%e=NO@44&pPOvU-ChPJ6 z4=#qbA@92z@@}vpZzUV@A-@^$+GeolZU#HaW^ll71=|{!5bjp6n`{M#8u$(_m=6iq z4%#-q?{4$E$u@tefrpTQfuQZW`^m0*nCxkPtpFPK*bMBWS&D-0o=S0W_K)EVf`>Ey zP6yn|NN^S*|LyKua9`2tR-vWWprhB}4$*+K2@~!SEx6yXp|^LSyLX|v_u!t;hx@{y zb5{s=813#D&MOk=?dcTUe5Ftqn?gNY3U%WYO7khyE2gZBl(OI~!h*)$0{7nPR#R45 zOIf{oie!uwfinrxW2Z>BlOkz1MPQE&H({v|&L+a1C>3_csW6?S!vC83zb!onO+1D+ zo`)`8>@qS^m(e9dL$5#!uR;^AK@YEYNpLqP_1MtMLo*NO7gDbWZG8Z3J#_NjF|_gt zbnLm!W!jmO=58bcHBKo9TqC~2o#O*>%OJH2{Z&6sHw`gaxDcNO-;aVAK|JyAM_ z);;cJGc+{rbT^-&d&P_nUAz9bY1g1lH{l&II|F7wM(hnTUQd+qpjG#JS!m69=*;DA z8_wSCZVmc!6Iyi_y7Qnr>Pet4hdVmx$;}=OnsB#A?u9!z=)Ya)yjv6lcTp@f+Z^03 zVK{%`q0ts81I}N3IDv7X>5eIr^8Pm5@Ou#8_kiH{K;ZYl!0$nV-vfr8nd`maMc z$B8KFZVYER2}S*+{yGfQaVABLvnlEkN>M{xin@YR)GD8%J_wy|`>fRIwqFuxxRp+~ zy`y!y?H)Zvoib9?w3(uwSt+V$r>GlFirREj)R%Ur+rH>`y6v|iG~7|A+dfGCcH7i3 zri&V5yQqf<-pS*-sLQyETH(8>_d@4wyfac4H7j>fF9^Jor*u)b)GlgU>!QB3x~Oiw zi#lm^QB!6Y_0)oQ_3SR{y3<8%xLwreHoT?hbx{}mE^0C8qTYn?u3pqd-HW@Z{iKWf zMW?AFCQVJSY3eabQ^Q=Ex{A}(8lR><3TdieOjGBiG&L`$saGUTRh2Y#M@>_^TAKRN zN>lK=qfQ%XYQ{`c&#g37veVQ}Crxd+Y3ge`O%=Q}b;(at%R!oY7pAFZl%^iUY3eXZ zQ-A18OJFiB#AaFqWm@niUhBVZ8}pf#Dr8#lCSFUFGA&Ndv=owQu}Y>TtC<$BWm=jJ zy|$5Q{nu_ku`;a@yVGv3yPbAB=Ve;w{Y+~i$h2OEnN}^zwC={4)?Sin{iM5F$C>Wd zINRNNgt}WpTzBgV?ryE}-K`Hor`tX&b-L}B1R8Fo({1l)oo*W}hSn*gyEScgx1L$u zt)kuCy5V%UHr?*lmv*PyzUX(l?YAK`+)=07K1lv{+pS|v$IgFAfsHTsv|bQ!@|B*}Eft)6t*7-(?`fShz|}WQMTUDjEbw}-O?P|TPA9`==w9(s|F?(Cjt=?A2?rq(4dRtp=Z|iHj zw^i_ZTbKOa)^gC>dKdP#no)1-LEPIqOnO^?Xj%{$T0kr<5JU@LhLDOmBgh30FCM`U%Xko;rg=-Eith+RL1hkOzXyLq13kv}) zybfuh7SY1pm=^XDTKGw4h2uBa{_}xU6smXN6ThD|`^(T{|%=oRzY|oSYS2 zlB`fsvchdOE9_`l;k%v{P8nHY+RO^itgKM9v%(E0D{Q)1;Y&L!40u`LqMsF(f~@d1 z%nFStE8LH>!atv+GY?sVH5E_B=NJ|XY*2^ai6VKL|v-h_QZJ?azg#eKql z(kJ|)`-LN>UzlL~g~zC080PwgtGHiS)Vzwou)>9#NVoo@SG2n~1C>9!A(zuk6QU~+B5=Gp}P_3zsf z&b2Y0YpY_eElRmIC+FG<$+cM}*Ot{>o7Zw}P0zJY7`gVOnQK3>a_td2*S_ZD+Ustv z{mIL<&-=OdLXc~}4s-2VlxyFObM3t(*ZxW8+sB!Fdz{U;AEA63-n(mG!TI(opKpH< z^X;=zzC9=B+b>DJ4R>tq+iJeOqvhM*^?du3k#A3%`Svp_-!9tu_6;ZB-gNWrFYSDL zz{|HU`g!mM^6j@_zTJrO?fY@QeURkaziDW-nNGL;5JAJub-L{pzSC`=kp|kc@<96q z`Rm)aZ>avW+1l=}TcNqlTHahP!Xdz(G>k!_( zix_k_X3$>3pr7z|-En3RjkAO35rTK@xIuIU5296m5Pc8_(OGE_LAQ-wl0gLbg9y59 zw4)6o=(f=*V-QW7gXozxh>G?gy5S6>O?MD|@dnXFe-J^pjoyZXs1Xe!=(f>8GKhZD zL+BX1v^mBOp@-ZMx{Qa=3O|J2i$my)G=yg5A@qWD-m1H$4xw#r2z}Fs&`DzmO_@XJ zsReJ`*+b~MGlVwWA@tcBLKplYv=|JbHzB-l7Y(6%@etZihR`o~&Gd*FMicN7;$vet7HO`J&kGN6m3Ldpq`BCeGIBK1hMlI;Jt(Rofg1b-)x@~Jm z8?~U@woVzN*0eclJ+nrwqCINea7L|7chvggjanD|Q46|l>uoq{HKI`qx^3$q8MS`X zMe7(-w8q$?^^hxCmvPZr;fvOLv1px=msGe$fIq-g*mQ0!~d1ABVn!}QHmnEM(mYnxl0tP&J9m2bG5limIEZIv~@{=x;<4l>1 z!@F{ixH7qd%Vd==lMiBrRDixE1o*tB?zRg)9aY@+Pd1dQ>6z z;tJVMD&!YkB}Yt^Ou$Q_kGU$jimPOeuab{qm7J5R1p00AN~scPx5=(nCD3k@(?*rd zm{s!Ju9BNhm2A0H^3|)7OMaC=w@u!KRnm;A1iEc;RU}Df~_9Di5lU(xDoCrjqn%U43C&*IKei<$6PbKiksmY-wZ#B&G4Mm458f) zUn$KHy6tdRYlc7cW_a3YhBIa}d~P?xn@%&_a+~2-uNhwQn<2E@;k&3ALbn|rCe82< zT-^yQVhGpiwlNRgwul%}LJTJ(Mo|zWtBBz>#ArJ7+D50{eqwjJ?R6KrZ4WW$eZ+u~ z&b*Egb2moJUV@mP^cZuT8DqxTG3F6B#$3T;%ql;|d=R16mOAbBOQq9o?`Y6%>toC* zV~m+L$CzjK7<0oJV>aC}=8Fftw%=*D-$tEo`yhdCn;vJ5vE$4`Zk)M{$C(v=oOv&f zGiRi6W>y|&UMS|G*7ynLqd38wlO~vXd4hSROfYxU31(NDV1DQm z%xPnSnK37r=k^41)0tql+zIBZH^E%;Cz$16f_WEBFc0Dh<}jIH{?L<#z)l*3>vY?g zhi+S(G(>6A;N(d|Q6>#poiuoD($IA1woPcZ?M}PB?n1lmO&aI@Nn;_HG+sxO#@%?* z*h?mjpY)V*oSiZraZ|<>JY}r%Q^p4odTpuGZogDI-S&-bWW=|P6 zoGD||oie_7&};jhcKdDA>9!9N=(g!;;}|<_JmjX0%Xr#Y;irxF;57;{bbtsMb8*V z?2Pf4n=!898Dou~F+Pej#yM%mn3rdaSIUfWN1ZWtwHf1wK4Y9VXN>3ejB(SMF}B

    v(lVAE4@@^rQ7PPw4=>R-}PDPlsPLsvuC9n&aAZQ&PrdrS?QubD=h`H z(%WcOx*yL<2g$7Tn}%kag)Rb-L}t1iEc{!57#CpKuGlgcp1` zkM&h?!58HPUr`o(SzYjXZNb;{1^jX; zZ~>1c9%EI+Sd=kV6pUpRV_w5p(=k3_V*JF$7`kn|?qdAO!}xrF@#_fVyD^y93C2I^ z6?~js!H>8Vd=k^&S;3p`3jX4) z;ETZuejBY|=(h1evVwoptN0kZiXU>T_%gqW-;1mGjJ%3pD69CEx{9~8Rs2m~#V5^G z{M25>*PT_o;jZG(-YUKjtl~G(D!v!5;{9Y5|DxCM5xa&Tb8Gl2zlJ}GYxtbJhF>Xb z_>Q`UceOSALtn$E%{BboUc)z?HN54n;ji8rz7(wCchMSt5U=6GWDWnJ*ByafcL=xc zNc_5^itCOjuRDse?#Sx81Lx$9rms6E%ys99z3yCd*PTz^x^q5QcV0*9&fR$3*-O@) zpY(=voZWC9aU0GRe#7}7Za8P<4d}VU#cYVV-Wo|gn><#CJv*B#I8_pMR z!?_r2IB%m32fA(NAlYz!)0@sQcGG#tZ913vP3OJ1>70=_ofpccb4vw3THAEK>6^|; zbJKZhZ#viiAIjb{%&F>c+fGlW4+9LL4?Xk&hM7$7Gnw9JGQB3*={t4zz3E0k1O$wT zfCv~6VMIzqL^=@>N1Bl$MM?yOh=8F8&jS44_jAAZ`+j&ij{}Z_j{{j*>pFkeTJHF6 zn)Z+5h$o@D%$v|{^d)q+`V+d-0}0)XND60&rEr@>3YSZzFf5b8 zGPx9nASoOmPz2E=htbq)D(zmIN2blVCNJ1lOZUFy=^tbDc@B!j%NqxRYR;CkZa`Cc%1N z65Q-hf>Q%YFeOTcv&G49rz9D!k|x6zSu$KCPlmNnGTewJ!-OLl&UYrmDpxXG=T3$Z zPcmHQO@@uWWEk|eVQ{}P%!pF_8R8UwnnvJ}5ep5lj~6u%rz@uQ9ue~vT7 z-{ng2SG!aER!@q**qh?l`BMB%ffPR}O7&-nQ~e#1RDY#3)o+%i`U~Z$ehrlBZ$MN1 zxFgk{=S=l0U8(+BcdFm+N%fa{Q~d^Cs=vjb>IXi>Pm9w0nc_5myCltDAx-m}WNH2a zd757hrTOd8G(YA@^XEF#{0di^zs8;Bw|Ub1CEhf@-k0WY4y5@hQMx}{obK3)kW-Crb6_iLeaeP4^pp>HgM0x}Oneh}t9> zqH<{lxce9mIBSVzq%n)_CGDOwx3~)ERh<@64j$wBFvE`%5`Rm6s{~$jXO(Z^JIxiyjdc> zFH6)M$P!WFY*D8qTT~^@7FlH3q9S>=NDF0)8qsVK;m8){JF`V9SGK6moh?E<*`hLU zw#ewq7PSVlMT|Jd(I&}pluL6Quq?+Rljk@fD90g3a~!BM$I<1=aa6l=z&&X>j$&_) zL+8tJGzD@Tq&U~nA<1=AN^>1%S+1i{p6k#+xsC=j*MU279eK`NhtiensCDN$?4Ddl zsW;bQ@Z~yM0=W)aoabnln-_a?_cT`F99Tr)>qe!0b&_el+Ml|0+IP)DUSH7dpo$o+A`HnJg zzQgFtceDob9gJ8eYm>-iI-32ncr$AQfEsz;}1+tbv zfs7Ux%GxD`vI=RT%p@EqK;=!FI9;K_qQ|m7A*gYklQg4aJ;4AU81WG)#xYW}wDfLuHOFbresYeZ!dg{?q z59TcOC|sqU8h5G3<}LN;eWjk}K&gikmw7rRWu7W&na3h8^Jt+mPa|69A)I9%m8;BC z=PvUg-ZGETSLSIAlzABOzrAgFxdejBC33V}f;vHG+XcGYZqVEImP>TLa!FI5TtbQ~ zBps3pNu{(xVwQu>HUzrcDCliFDx zq|RL>LA+HGqpwQR8mN*m;(vSF@@f|ZRlDS9wF`Cr+uin7yL7&4S5u(cMT%=&9numjAP z9*qAx1EiU z%H0SdUeMWo)!hz&-nO{O*CuW9!SW^_gf{t5XOpkX-Q=@+n|!)JlaCZP`#Pk}KC`^p zr$L*2xU<=(bT|9#-e#Y{*X(NvH2Y}rzrAgFi%*TV_%P?cy=`xcPakOUQQ}r#r?k~) zk^kGudj5#~R3U`Ot=Is#c107;Y+9|fkJH=YGQ%pEJ z#VU8F81Z(Bje$-vBkgj+@-8QYb~#aZm(%L)a_RzIPEx9Hn&k>7=xsZ3r^2apE1Y(( z!U=lYPSD$Sn&e8S8dW+mx6*0zDxLa((n(2GPK#XS)S@aU;Z`{jugYl*sGN)xlEWw@ zN8OOz>V@RG03;`+YPngimTOS89CxebcCT7)2&m<>R3ityZ8_%F$ZcMYTp!TLDXCU& zLA7$it(7BQtsL~W<)F9ig;AXsb?dy=fX+)w^1~rzlhlm9>22Esptp^hrI_0+wFS&l3bjZH zw?&EsEK&xwy3v5uO`>ml+x7tHZKHNK7O=Z16mb&)#La*fH;G~>9>74)8~;ylJ3xzo zV~+$LT@1PoF<>r30y+(`U^YX_0x$l8`3xE8XqJN+4LRs$wt+bf2y`-GFsp%rE~W$Y zwHLqXZilV~GaIfq-EDyzbhr0|?x}}0Bd7<=Z+KZV!mfZB4j*eqh#$;x1Xwd7MC=Sv zBzUJ@4BncLdGmgKa4dMIUJBltmx0c9`J4WBSR3eaLvQ-qLiBZid%tKgdq2;~-XFS_ zy`SS^?+@-~?-#h)!0Uj{cF&vscGwlr<@UYlZwmvUzb)d#h$1;LU`8V*RKke?{p}cm zloJy!Teytd z7F5n{16}U6Fo@d*dfaV7l-m~J;9e0e=3W6a99KeJ+$+J|+$#b%_X@c8{7O&{_X_B8 zUkUSZuYex+6=8sTB|-!`++xt*mb~e43#6dOE#pN7mGdI`a$aN@#ET4pd67bt7a8H; zEfzU>i$h&+y4(Uc=yH2_i-UT2i@_TOi^F`p#UXy)Vqt){I6}lP2R+R4Pzk?0IF?@y z=0D2AWuVI~2R&}+O`jXQM^GN&;P;4}{GL!3zbCkx-veesdcb| zdLl%ESkSkO4V4IDgQbGlaG4-BNG^yCg9Nc5FnCV@6~sn31l=O1pgYth=ni%Zy2Cw! z?jWzAJIp8O4)KF`2Lgib2$2v5ok|$I^$rJ1g>bk`2nWf9Fz6P*A*c|Ja0vY(r_dkj z68eMPLO-}m+#lo>`onxee@H;+j}U`*)g|Dqbt!mHT_zF*$wi_tNF)kDMWP6&$Pwxi zIfC6HN4Q7i2=a;?VLp)~Bp`A`h{1d467WX46ug5j50ZhIe_03`B#Uqcc|u)5o?v&7 zC)^w43G)ScLIOda2=TxDZh5dI3<{Qnpuv&|=f53qZ?G%O7wifN1iK={ArR;+LgDg% zd*03vU#L687w-M9p0_w$9x4t)L&Xv9P-nO|)EO2Cbw)_Tvt7quw%g7jpTLjdq0@D*$+OuG3;_MgChqWEeLe8U@(V+f?k#bbiSRS z@9kohv%A4ejvMs8J*-&J-RcH&Q!wal`PpK&gDqjp*iyEKE&s3Hx0lW0u{bON3$&G3 zU zfKOfwn8J$T#t7H4*7DYZPt{s5d9{|iR@laBtZrU6r(4j??&f!cX)2fn^I#4vfY~sZ zu!4ntmY?V6_yvBppYI3LR3es$Cjz%Xh}a^&2;A1-U^#dWaLa>(?ch7WZ45G&j3)!P zLCC;MEHZFwgNNnedBANC9`N#t2i(daVM%xrjs#4hN%#`3MCf9BQs?00!vb|s>@d~9ZDR|*U3RYPum?)D9-7GiH&2fX( z(+#G_++bBl!3!^_0A-_ml#7CuI=~BX0)hZL0H(Fy>^b~7+&RJ=Rt_(RlOxDs=kRm5Il{xN!@R?s!-B)?!~DbC!@`lQk-U+dk%E!z zk^GU|k;3(?^}O|*^@8>6_5AhR^};Sz7q5%cCFo*z@w>QP!t1Q-yz89ng6r(-{OjE7 z!al4%ygr;hf>d0a+#NzI%gVEItO6_B z%C~Z@!iTJfyoa2Jf`{yf{D<6!!cbNyFO(B12xW)zL%E^Cg{+0Vg`9=XPG+!MkHtO>jcoC$&n>@EB)+$};KOUKi3bOIe)$JcRn!n>@yyt|ycg1hXy{JY${!a=M-yg{5nfrEQ{8ijl!X{P|uZhznXks_!;hi=2ysi|mX1i`YwTVn^|#xKYBTtfjoAoTY-L z?4|sr+@-=wRwb{JQz@uqSMn>lmBLf3Q@m50Q-V|MQ~XohQ^KjNsl2J2se-BOsr;$j zslx57?Y!-r?Sk#>?fmWB?Lsrl%rkS$0yEppH*?Lx2doFY2b>3j2kZy@2iyn3U{)|M zm=i1rW(V_wxxvEutogk8ocV(J?D_op-1)*nRw1vDQz$587xD|ag~H>kJ-j`fJ%T;# zJ^Ve~Jwlv?^KcF>z}Yw-=iUua+CrkTgg{)mBO2>o4lKxn}VC{oBW&H zo5E;TG%uPHEr@1E^P{=Z!WFC)ycL`kf)(r){1x04!dg}>ua;9QsAbpkYq_<;bF6c` zbDVR6bL?~cbKG;ncvd_wo)a&KXUFs7x$(kXtX;faoLz!l>|Oj_++9LD%g(cN>;gO6 z&bM>z!pE$~yvLl!g2(K~{KwqK!f;kNFPsxD2xo`$!@1$YMXW`^pdtVz5{oJoR7>`DAd+)2W%tgXDQ zoUMYb?5+H*+^s?b%fK^m3<3k&z&CIW!h5WHynCE`f_v z!ZcPIFO8EXNMon*)3|BEeXM=FeVl!Qee8YwecXLQnnm+y4lSVBG@s_u!WXO;yce7o zf*0%;{1@C8LQq0xdQ($~7R-rUvBg=JnP0+o<753SU9@(mx(NzZ9ahZgD()QA@mE_< z>&}+7%}bgbjdL3u^^4`J>$+<_HP@^8)#IybDrZ;hD!*Gcx~!{oW69m(xZ;^bJ%u9* z(So036J-nY|H!MzbLS4reJAI6wl4c}R!!E4%)HEl85tSrel8PZ?M)@#nnEmF(}Iot z$B9VPS8OFUan_>bW#)`kFX1UHyYan8kM+Mr&eA2_jn+OMy;I$)Xo8x{Lsb)(A6E3g zF{dl-QE_J(J*cBS<*&9c@Ab6Kt=rjhCwXo2$DK=>ZaN)}4X(Kjm)jimmiHFR#l2V8 zxp#EehLm|~X6(6MJ@O}h^}B}gRXxU<%7!mzSNtX3RlaWK-LiE*jxH;`*;P7t^Tv_| zth>dLJ#od+teHjk(VoJ?BSsXixQ!N!asMQHflQRuMK8=BJmZhN8|y0au7R5xubvo| zo3s6$oTs7Bv(X=P**mUZ&KjLlleO#8iOi#)vTlpdzTmJ*|hU3eDm!3wcsXa>3i8G$UaKeW}@wp&B2 zt(I-(r>0EPZ1{ljnIYEDp?_EB)?U>7qwcSs3gxNll${D)m#Nd#VQh!mT3X9n(wfIM zMK=Cbe@5P2H@~*6W?D6;>SV?H z1OR^n9y5;s51GFJ512o}PtwoaXYMh7Fn0lWnA^Znn7z!`%va2A zW*4)A+0J~yY-2uWK4Ug9E@mUMo>|ANWmYq*n3ar^S-~u0mNJW(Ma)8GKI35KF|(PO z48u?i!Jv$tu`(vc$mkgj12GDwlWAjGm`0|asb#8}3Z{%HW(t^mCWpyn(wP({k%?#G zm?_L8W;`QdMlmCp7-ldtfa%BdVR|v)Ob8=lcnq6)K|iAd^dtID`W}6U_R-hrtMsq* zdHQGi4BbQjKz~Ocr4P~H(qGeVdI$Xl{W-mv-bk;b*U%r*@6*fZ#q>hjLC>LQ(iDx+ zHrhn%X*I2&+v#Syp01%Q=n}es&ZRTyR63E4qhsj_w1gf>52Xjv{pctL_)9+Do~qFR886CTat-HLQklOHlm)WB#Mb#B8^BOrV!(Z5yT*(FA+`%2^R4Le}Lb?uj7~SbNG+A2S0%C z!N0_};Op^^@D=#G_*?i49K+4H2Jgh1@M^pS&&AX5cziNG29LqTcrQE%e0e{`9$?hV8SDgh7~6~O#6HJ1U>{-2u|?QCjK=Jk0aIcvSS?nH|^ai?a}s7 z@J0Q^cHefxcER?O&12hV+hN;mTWeckTWFhQLv03Im#x88Zp*W!*rwVfwjs7YwjkR} z>m%zO>s9MH>j~>Y>u&4k)=#WX>mutMD`quXyQ~e?GHb3i$r@`NWgTdZ1V@2q7Qf}D z<$|Tha@6v*rQ5Q>@}Xt1Wv&Ic7%g3vdP|ul$C7B7WEo)*Tf!_H%ird^=Bwtj=HupX z%{$DS%&X1sncp&#W|LWIZZMabbIelnMDuWSv^m85()7^uyXlhYlTA4OqHfQQ?hBYX@setDb&O=J%oMmMffN92>ccNIs7ra9DW<7U=yr>>){eO z6P^x_g$Kit;0PNq-Zfq^o;Dscer?=lTxVQioNuIzCZobAHx?Vyjnj-{j023}Mz-;h z!DqN=_|b6Cu*o4hh^oR7j^qcgn z^zZ6t>1}#Q->5IuXX@khWAp>`q57A)2f7|bj zjnfU*MSug&Bke8iFWM8@ecCUypJ-QT9a>zg*S2aav^m;%twcLO8>W4!`BU?o=B&n} z*`wK_S*=;DnWeF6lp49FP?MsWq>0f)fz9$`wNHIs{k{4d^)~g#>i5)h)pj+cZcrDg zQ`M8z!_-k~p864V3;G2*4()|Lht@!gp;?dxQb4tk3`&H?LxZ3&=%vc9x~e*@I;`5M z+Ng4>-d5o%t*Tj7s!CVIs)nheR9w|VU4HGI?+ybXMJZuXJY5r&i{RD0icUi-tg>usmo4z+D>Ti3RvZDt$X*49?mmfkk0ZE#yy+w<1DtruF4x9(}( z)aq<~s}*Tgw$`-fw8piLXpL%RxB6QyxBS?$ujTWWRV@oz@D_E8yd}RSzGYNPpB8S* zgXXKvJZeKO)HxmO-Pfnsk$k< zX-ZQ}Q+U%qjdvQ)H+mX(H*RQL);O!t)Y#fs(wNdXuCafku<=pD^@dXo`x~}4eAKX@ z0c%h-)HdWaOl^p12yb{^f4lyd`eXGw>p!VqQqR=u>l^C}>J#cm)%UJv*WZ_4l7BCE z%QwoG$!E!7d5gSA4oa(XaM_I9U-xU>iMp@qKCN3`H@gn5YpE-$ORO7H*QbtCcfa;h z?eSW7?S|U-YG>3MY8z_{YU681*7mA>QFFKEmzrZWJ8C|zdAEkFQP58B!Bc z^Q8J__37&U)t^_dtaen}synL7s#B`RR!3KJtNm4%s*YFfu3BHUq>8T6R>`Y!tEN^B ztqQFQRNkmORrzh@mdXz*=T@34TPuqzrIn*9qbgrk+^O(Z9I5!CVs*uW3Z$Z|qP!xt zVq8UZ1-IgU`NeWi`Ofl>%NLd7<*M>3@Bs3Ja&bAo{LivWWyi~Qm8~m#w~Q!Ll~tEz zlualTm+{N~EWK3vUFojUb)}0+@ls`JWocUJxYB;5+|v6c7fOzmd|9%lWI+j1(pgeg zl3X&Tq<6{7;ycCXiVqfVEnZnXuh?ANQe03xy?9u0Sn-ph>qR|9dy8B}?-emc+M?Q` ztfEOp{fqcTe->UW^c3zWTvNE9&|cV4SW=i+II=LZ@L9pFf>QBB1 zvMB*C*}6f z<>lVbIiGVRXIsw7oVhu0PD4&^PHfJ=9Da^J`$G1S?C$Ijv*%{R*^Sw`*|FIJv-#Qn ztn*n%vbJTd%$k#B%xcKW$(o$iKZ~1nFVmZODD(47XXdO-eP&%|X6A&<=uB4Tos6>? z-)3yiSe8L&s57cEQZvS6L}ffrzX{%<{yKd_`n%~^dS`kGc&mDNdT9FNv@2=H({`k- z2CrmW(wfuq)25^i1jn)aslTKiO8q?b{nVMM+SHoVv{XrIRO<7Tn<+ghds5b?EJ{IA z+Ea>Brl$-|2}*g8d@=cGa(D6v$+MI7$#uyY$>WmyB)>?ymGo26*GcP>7A2uc?MX#R zaY;jxL`i=pUPwHgxHZw4I5Sb3Se=-bI3}@I;#28$=?~J~(zVk0Qj4@%nkSts?GNI? zy9s9#_9eIymL%W_T?r)#@d+^rK?x7yFUB8<-x}|XpBb--uZmBN9~~bNADDi1`uEd! zO#f*5yy?d2^66RA$4~Dw{hzp-aX-en<35gC5NC~Rj?0Ui947{$+wEzmr|q4#VcMc; z$h5X;1=FTZ8#s+O?T@MFrhYrsHFfb+Y--2UqN#CH2ZM;_{uJ+&{ZlqgSvrN7(lw=c z%JeBirU<9_W4*BlVmHUW7fZx;#g@dz#}0`V#`-6FCm)!+dGgZ9#N@8Y#gnH`9x_=l z`TivDr2UgNOkiER@LCQg|+U?OMYoe8HW z?47WF!aEae6Iv$ZO_(&H--MUredBw^yT^Y#{_XLm@eSj%#*ZK0d;GI;*Tt4F7d9yvO6 z^utjXM;#uuWz@1! zAF+MJ$`P|hXhu|yNE|V2M9_#ohyOBs|8Upv#lz9zZNu}2PafWH_{(9phMgR?YuM^x z^M>h%)eK7=HfmVtu!k`hV-Cf97V};V4$3-(F;ipu$FO65AKEk2J#@{`w}u*r)(%Y@ zI(lf>&__cq4LLky%aHem5JNhK6b_j>r2h~$m|5=`ynFDP!EX&V46YrVI(XFJ(7_J} zT^Mv|(B?r)2VsNS2gwG-4(d1P<-nT*PY&EU@S}lq2I>Y@4NMw1d|=SPKL>aR>>u#y zfJFoB1DXfq4wx{Y_kd^puk}CP|BL?4{xkZk`j_^P??1RdzyDqFY4O+Mb>g?hCb3+c zE*>Ke7eDHEso&v#pY>bX5AWCBPu4HCU%!4YqHje15WOS%!{}Mjn&^sXY4p%&Vf4Me zXZ!B$yT0#&zUIF5eKY$?`bPA9+~-oCBYn2?d9M%Nr@c=>pV&VA`n>3UqxXs4J9>ZE zdsc6C@ABRWy@&P|^!_92Ow`v=>!RL{GDXRw(xXO4g+)E=b)nb6UYmL?>4o-c?UmPS zVy`~Eo<&}Z{4TOP(izD_DkDoG<01z}aw30^=!w`Ju{vUIgf5~gA}L~6gebxv{&V=g z@D1S$!!6+r;hEu*@QCooVVA-VhkX{dGz<%C3(F6i6xKKFdFXGU$3wpeb%rvb%FvR~ zxX^*2oY3DxdO~)GtPYtQq6?`CNeYPx5r*6gJ{!C@_>C-igRRQ^44g!z_ngLC(0<`d>a<~?QsGmF6(m{Bp!Ocf(zQkkjD7-k?7 z!El+!^zZaV`bYWz{UyDgUQW-W5n4sp(fM=&J(}(VVz57{%hV6l9_mwS88w5_QF1Dq znoRYlc+@@8OCBUYBbSjBsU%CucycfZ&hHSXh_8q>#2i9Hlo4@6f8rnfDt-ia;R|pB zUXD-0`{Iu=FZLDo0fu7@SQ6GBdxCn=UFdSuf>xlD&`|Vu=_&j@{2{D`li^_aym6BeG3FWj7_S+&87M=cp`YP5eYc*}%k;hV zzv?#Wth#hvknXg0l~$>ptPN-mXx`RTX!>ies$FWMI$r$`bO?GIDuen$=T&P|U8=FF zKa^i6ZOTODbH%rcS&CeRQ1M;Yg07OT@U9;_7k5^4_Ub&?P2ZT zx4qq#52WA0R;D$j^-0Ul7E{Z_mfxE#OC}Vbuq!Y*mt~ir3_a8)!^gjRf84wnxvKT|fhEWYeksk2m8`lMu2NqtFBiMtpo?pJ)Y$W}D6=v3j% z!pVh~3g#C`3vSBZlV!;M$X}VCm;YDZn!KXCzjHsyEzNzJvmvKE=UMiK?DFiVSsSv- zvYuqF%Ph`(oUtZDmhor$%Jl5?J8AEwrKDX?U6?v8^+L+*lyNCPC8NnhlaD6pl6oh7 zmDrjnNc>D%A^kgHRYF$6t@wrUQ{vA}C#DabemD+_3ytfZRy{2+b=B02slQE`H)Y(E zA7bIy-myC;%O^jZ^wFgBN!KRMnK*i)XM%b{$b`?wmyW+bZppZ*<4%vYj_o^kr=(W$ zc+C4_62^E(qoc*6-J|5A{vP@M$b^ySM%YL69kFA0_3*!jEgd#xSWk>0CM;&l(88g= z4|!|Is3C_3cMN6?UOgyf(D{Mr!03Tr4yYJ#zyHGiCWd?$tO#ZWuL_a|oe>#DA)-%(S;AihxS+4#3w|-*$D7R?%G<-O<^IWeha=$} zX1B7Ru~x9A{=epb|2q-<|MNHhNe}SprSDEI2cmP(#H~a}w&j0W#?R>+1kb1u19#}o! z@CQgi-|#96eUpdY0W0e(ZvV^gARm2&@4vVOR^C_K{FfUbIeo?TfB6lp%dc|OH(UjI z>MO3i<}z5ZU-9d|Tmm`ktEBZ67yjiuSkqtSuCMU^%g-Q%eU-z$;_PeAfJF8TbNV%> zKsNg-oqa{mYkp*2aq=}kfW-C(=EQ5h2j3L0(%V=0?JGR5IR>)aS8481@GbI+!>>66 zvfYEPIq*8;-4Al!Z(p+y-?g4xSaKC2v>m+y=NP~9*b^yM7&Gy&X z@E1%sVB2f9GFw4X{5iAbHJ^dZcr#$r>*UzQdoV z4PZ6kBfzTHdGM)%31BhcUBDv1JAj3N1%Ua0w*e03 zEx%a00GnYkFX@-`3;G}WIY{=O(NF0oAm9HR@ED~059z-E4?x=Qr|$#q(SOi) zLGFKtz76(1KKd4Y6L14qfZynAfUEQs`ZDkVmjD;(3&0EfLVE!})92{3z!03KPXT@c zrr<~VB(Mc10N>Ncfi>{Z$ACFFN*|#Q1AlN3?5Xwxi|{SIkN$?<3v9w3`YT`*-1KgG z7rhghg)iytz%F#t+W=dEW!OT0228^y+C_f~e8Wb11K5#$0=&b=^jhE^R?{ERtAK&{ zkX}iDKs$knSONBH%joy$rSuZuB;KVL(eD5j(hKPM^xMEtyajf1bAhLrP0s?ZVg~r{ zNdsd+(gckIZ-IiH9zxrJzp&C4+6*iPOdDwfa2YyUOKX79fWS^r3A{!Z-AQ)@ef$>A;Unqo>kSfF+qsPogK%fc@tvU`Aqlp+8g+kUUVdIDq(ae9Rkcs5G|sGK;rUW%Um{)x-Y30 z)IZd7>KXME7?;1P$J8V0Auulws6T;yxkvp$-KFjT3-deW119DMb)EW+x(1BQ73x=D zWiC<|sPoh>z|Neb&H_VonmR@OMDI+~fw*jZKh5C%z49t#;+6e5Eu9dJBrsMXX*)GBHv z^#SFi-lvv>{q}p*Qs8~wr4~`|0Q)nadYf_p2Q-hGL(K*zXePw~8$?kgg##yqQV3-O zX2?RBDH!-61Er_5z!Iq`h*APq)J1ht?Z6ndQY};y)d=}1M@^%q0@E~^nnX>c##7^{vA{Wv zrbbaCsNujp4W))qgQn?b=Q5B6pHslH18{ zavS+MxdohEHUa;&k=y_r*gEoKat*nfTt$9Jen2{b5nB#UHcNpQdzV}U+}HwgKItIe zBIlBG$XVn}u*}mWNfIPRq9j7vfHgCdCejGpnU2%~e+Gdwkpft>4zi7G1um_LY#{4N zIay2AkX2+QSx%ObC1f#KNEVR!WFDDAW|Nt~w55?LWHRt=QgEJ{4y@Z$GM1bS+}i|l z966R81038)as)XHn7AS2AaWqtpA?hPWM8s38AV2t5o8z{LIwjrCj@7)SK~}<@+I*P z@tk-{JR$xj9up6VzlcA9x4TE&CGHTv1AljuxK8{=TqUj$zXFqYf%t{+66b)?J5BsV z^bjYBABgXP+w%}di6g`z;sCLq*hhRrd<{-{ZekbkeP0q^5Z%O9VhiyZu?e`pjl_E5 z6XIiH4Y8V7MSMtnK)g?^AeI3qzl3;~c!yX>%qQL^-Xi9LGvX{_2Kch12m)9_l&}*v z!a|q`m@p7JLQANDHB=H^L?f~9%Es#JlhgybW&wX0#En$LsJKyb78q_%M7ZJ{TW}_s9F;(Rd#`3XjCY@lZS% z7lFYj9vF*a<1ev)uxHp4>~HK5_80ai=Ev?~cd^@;54(w7$F5;luwSu@*m>+1>}TvO zb{hK$`w{yA`yTraJBA&>4q*qdZ?SKHncaiAv0c~>Y&+JCZN;`=n=u!*5nGR~!`5P} zu~pbg%!#eQmSIb=CD^;zJJv1Y6htH^08bj8_UGfu~aM>OT-ee>DV-E3N{&=h>gd_ zVq>sT*a&PGHWV9-4Zy@$G}Z@;!XmM7EEEgIM3?~MVH}Kwy+EI%PtgGS7=4I7K>g?+ z=pFQT^cH#p{SCc}UPdpW7tmkOpV71EY4j)bBzgipj(X6e=wb9Ax*y$#?nU>YZgeO5 zCHe)r4gDPb4Bdo&if%wZLD!Rt6SBo^vtPAewqLZLw|nhp?WgTO*-zR}*pJ(f*^k%{+4tM`+4tJN zvhTLzTIJ;YoBeOX{YU^ z9kU~Lo84@O?RvY`uC^=fUG@%ptG(IYV3*r#?N#;)d#SzHUTDv^=i0OE8TK@LvOUor zZ;!K2wNJKBw2!k(?4#@>?8EFs?1Sw6?fvY1?NRnfdzd}ME&`)`JTT1n()Qf;)b_XS zk?n!aZ@Xu^WBc89({|l<)ppr-(RSYEwVkz{w)NOf+P=4aXFF;;Y&&54*0$HS$L6-} zw0&vowr#b2X4_=jXj^al*tW*D%C^$>zHPZ}sco_C9oqt%!#2-0$2JojZ%7+%Lu@vi z*#_J6Hmwb^DQ%s$c3X?B$yRTxwN=|HY-P4$TcIuAmTSwhW!O?}$u_Ai-ZsrP#Wu+{ z!8X=5#x~M6+&0uU$Tq;%&(_x#Ws9_h*+Oh0o504kv28D`&#X_ZkF5`_e_HQb?^wK%jI@dbOI>Sm?2`g%~SuIxBs<&#bkX32zw6fGmQ$7= zEhj9;EypZ}Ee9;$TJ~DLvh23(uzX?JX4zudWck#x-tw_!jb)YP1Ir4_GRqRnBFjR{ z+m?BjIhL6g+Co?`i``0{|-3Acn;f-C|H*TS;AFh4T~%#X}} znf>NJ%(u-x^9}Pg^JViz^Lg{n<}>D>%s-k>n7=b0H6Jn`Fz+*eZFZY?n!hx6n?E;i zHoMFl%6s~DdSv>`qX^^SEDcaQA6ln@G1)GE>o{4RG0Y8HS@MHKd*bn~!--d6&*Ws)1ukZ!f3!jBg z!9T($;P2q0@F93V{0+PZ-VN`7zks*GpTRD81H2Ai1FwQVfLFlp!HeN{;Q8=d@Emw1 zOv40>!Zz3p8(|%+hLvz9+y*zp4R9S?4OhUWa1ktnbKxvF9ZrE0;dpo&91Bl`$H8OZ zk?=5h2s{uL!+qf>I06oZgFsn?3u+_(7@r#dHvVPw8~-rgHr_H`H(oXVYP?|d8qXR} z8GkgMFn(t|YCL4zZ`^DA%DBt;rLo)ixpA}cQ{#H$$Hvvh4~x|XL3S)_}(3o$`F=iUmjLAl+ak_DeaguSo zQDPir9Bv$H9AxZo>}!lNMi@hlK}La*Yh)Rp8=e>*8~!r*4SyJJ8*UkXGh8uTGMqR3 zY&c{1$?${WxZ#-Lu;GAVpJ9(-w_%6j3&U2!X9kyHz2RfSYQu*Hr(wBaiD8jpfx%&z zYnWxA4TJ$T*bHWa(V#Uz28E%+&}wKj$PG1yN<*2U*dR0H8nO)Oh7^O;Fx@cKFxfD{ zATf+G3^xol3^IrfeGO5D2t%kr1O}cthL`$h`hfnC{(=6!{*KC5%S`T~8PK3kuzPthmph|i~x}Cc1x~;m;bS~X`-N(Asx|O>3b<1>%b?@lr>*ncZ>t^Uk9j3GE z%sQh^r-O6~U5Bnk*Qk^0s&y5*QeB}gUzelH(531Ub@94sy2-i;y0N-Zy5YK^x`8^e zuCK0_E?gI^6N17BOZSiVsrIqF6{>G$J*7}54G=WmuVMk-_g$3&eP5Y@f)edv^K3-YtU-7khV+P zu5H#fXlu1q+H!5Nwm_S!&C;f6leJQ9oOX(KqIR5iw049xMmtE`U)xt3r484HXoXsy zmaY9q^HlR#^Oxqn=B~!4xuLnL`Big4^RwoRrbqLG<~z+%%|Xq#ny)o(%?`~Mnys46 znol*KXx3_0X+F>_*DTd6(k#%trJ19dp`kRG#;!4Ij2f*5(sXIsHO-m^O|7O%Q>H1_ z$TYc{Oih|5Nt2+Nris-|(2UiL(hS!O(G1k|)AZ3qYQi)@pj5%pyi`9^2hO6I}I$fQtma5~_Q`8gH zQq&#a#gWPrpi%es!~;ns(95@ z)g;w8)fm+X)lk(Sl~~nB6{!kS1*!Ndw(5oQsq(S%FXesZ9px?Mb>$W1MWt7HR{4|i z2jzFlqsoKIeabz`-O4YO+mxRvUCQ;!waQh>50uN5OO)>@=PTzaXDMkVp+uAxrBSI> zLdq^>o3cq+udGp4C`*)u$~+bHP zyL0;~c6S$ccVV|!C>DPeTQRW%n}_FZoO69YccH0JSEw$O7m5q{h3rClA*GO5h%H1F z!U`dUS%n#eDTN7zF@+I@A%%g3zJ;EJu7!?;f2}{Q->sjm@2zjFFRV|k53K{%|ExEy z*Q}SVJ=QbU6V{{FZtFhlF6%byChIzDmvy;yiFJW>j&+80igki@tkq_1wKiGntX0-B zYmwD#)mzn8xm98nSUFaPm0~4Yu~w87W`$V6)(mTkHNhHVjj)DT1FSw)kI^L0!TQJY z)AG&o$@0$f+A?T)VtHV>Yq@Q?Zt1mLw4Ae?vK+S@wj8kRvFxyHv23ucv8=Q#wJfyE zwam0kwM?{hTI`lKOS7fkQf(=>6k9A7gGFOeSR@vKg=1k@C>EjxYe89H7KjCGNw*|h z;w{mZa7(bo-{Ng?w>Voy%)iaU<}c=t<{|Sd^K&?~Xa&xiSVm6pHW`$W|7MM9^ zhM8g}nz3e-8D@rNnjmT{T@Yoj08}9XA~|9Wd=N?J#XIZ7{7ituQSyEilb7%`i+a_`rDAc-wg0*lWCKJZC&*JZkJV?lbN(ZZmE&t}}KSmm3!u=NV@i zrx_<1$Bn*A+Ko-dI%Cx+4_ah28}&w&QDzhwc}A9zW+WMLMzj%b%r#~iGmI(5cw@9N z+!$>1H+mc0M`PT7hF^y7hR=rghS!Ec!xO^;!(GE|L!aS_;ez3;;iTcH;hvQ#BeY!qbAFq$nhv|d#etJ*6tKL!nSNB8rRrgW%R`*i(O!r84 zPuH)zp}VTPs5_@Sr8}zY*6q{n(rwjk)UDO6)GgI5)Xmk+&`r@z(2db`=vs6Qx@ujy zu2^T*>2+$IOefOubSxcJSD?e`P&$|nqRZ5!>5_DDx=3B9E>P#A^U%5IMzp`R!`jc< z_u4nwLG2Um1MMB{Ep4CnvbINiMtfX)SbIRbTf1GmS-Vc#rCqLFq@AaorJbsssO{9+ zw5{4kZH=}t`%$fT9%fkC24V5v=*j?Xu;YvZIU)l8>tP|25Nn@9$IJZ zh~~HEyXLdzz2>!MQ1e)GUvo!uQ*%voS#w@_wEKP+kE;)<_p5iSx2ZR&*Q!^k zm#P=4=c;F@r>MuP$Ee%Y&FVUJmAXt_s5Ys!YNcAD7O2^3x|*cMt1)W0I#&%=r>m3H zaq38Qs5(IHqjpz2t4CD7RNqyfRPR);RL@n9R0FDh)eTjz>Z0nb>ZIz3>Y!?mYKLmG zYQ1W;YPo8$YMyGAYN~3YYOKnpYEd<)s#WExB9&RCQ>j!^l~Bb|F;rv~L4{EvRJp1w zRk|u!6{m_)g{lHoJ}M8Dv+AGnm-3tPlX6J;O8HFrNO@1$ue`48RbEh@Ri02DQ65n4 zQEpdmR<2X7QZ7?2RL)h-P)<>fSB_D(E1Q*d$|_~4(yBBnHA;n2tmG?MN}94jiBqDK zdCD9mNSUfkP{t_3mBGqUqCh!HbSVEQh815F?-j2VgNnzB`-=Y*Hx*YE7Zv9eClyB( z2Nio2I~1E0>lIy!<%&g$d5W2eDT)b-F^UdFv!YH>r6^StDvS!PLZJ{V_zISSrYKNg z6(~iXB1ZvIq$m;;(TZ?Ikiu8tsc=z@$bZYf%RkHC$zREz%OA-Hat`8c^<-YRdD*T^g6#d5P;FIUN>a-p0fr_0H5 zyc{Ek%OP^GJWZY`kCjKrgXR8mFS)DSQT|6ZEc+sRFMA^!ls%T+m;EQZA-gKOC_5`V zDLW!NAloC`F54tqCtD?3DqARrtXO82>0~OIR3?ydWONxx zhL@pbFd0OaDNB_l$YNySvLKnC%v0tfbCCU(ewTihzLUO^K9fF@-jm*zUYA~x_DD}l zk4q0p_epn2w@Noi*GN}L7fa_!XGy0@CrHOgJEYChI%$=(RBDwPq#CJQDw6V~OesZ5 zkmgGf(p)K6nl4R}#!4fkAyR*-m-PR!`X9-#6KiNoRJ)t z9G2{t?2>GiY?Q2#tdK00%$LlPOqEQKjFEImnk99TN=d22DltgZ61hYq;Yt`1ii9A+ zNZ=BP1T0CDBuZi=5t3kupTtw*B5{!X7JnCi5)X-AiJyrditmbVi~Gcv#plJR#K*+l z;=SS>;?3gq;x6$r@j~$&@eJ`~@i?(v+$wGq*NDr-MPid!Csv9jV!oIqriu&1STRxz z6=#Vv#L40~ailmz>@W5f|3AV0BN`Tc5xp0^7Cjd|65SK^i>`~Vh zI^ineQsDyOY~eKFL}91UCTtPb3#){sLaWdqR14)ok&r872+2ac5G{lWbA%vasxUzq zEesO|3Vnp`LMP#0!4JV#!3V(`!Jy!=U_j6>xGuON=n=W!1Y!R#%bP1LT z77FGFrVAzsIt6w?tDr$pEhrNd3XB4cKrRpoxB`ZNEWise0=NJo$P}as5(LqLFhQWe zN8m1S68z==;D6!2=fCC;@*ndD`2GCr{44w({%QU(em8$Fe+Pdve;t1ne<^Q&_ ze$Is?x@RRv*{78NX-=FWrcjY_q zfAhZcKJkWlFL_US4|sQYH+ffi7kOuSCwPZ>`+2)~TX`FJt9i?Li+FQ+GkBAE<9K#n zE3bi9%`4*-@{BwUPtFtZxI6}r%)|50JQy#B2jZph;(1ZLP+kDfo9D)J%jfZ`Of*o8RER;Jmoy# z+~M5hT;*KkoaG$n9OCTb?Bs0WtmkxbmT?wx=5VHSCUH7BHcm6Aj#J4g;aE6&j*27Y z2smsGjZ?tEauA$c4w#e1N#w+E!Z|@4UycXIne&(ZgZ+j5p8cBroc)M>kA0in$G*%y z$3DqE!al&>&ECe|$X>%8>>}qxy+sZbu)odAC$mX!=Y!VyG zMzW#oEOt6Oi5<(1UqaC)@#;t)+5$E)@@cF>oV&+>m=(4>i}yv zYa44LYYl5TYY}TMYX)mFYaGkYYGKv0s#v8gE6c!Av!pBmi_N033RqYcl9kH>v(i|J ztQb}}E0E>Ga%VZQ{xW|sKQrGkUooFCA2RPUZ!)hkFEYfIADt%zo#X=rkqh{mDOX(Sqs zhNMAhS+um#raguhP79>@(A;T`v_I5g>SyW@^(FNw^*;4K>J4fywTF6|dW?FIx`(=* zx{nUdndLCdyjM3d&;2Jjx8p zWXd>-jnYD?r&Ll(C>Dy2qNGSDJPMOSq2MWK3XGCX$)F@tVkr@nV2UrrgW^Q_Oa4Lr zOnygxMSeG;$(2h8#u?B>Ry6kBIyxeJ6b)y(PUMJths1`bmAH z%cS$9lcXc0{iI!_t)%s&F49uc0@7^KRMG?zKx!j3lB!8%BrC~4Qj?@40f|MTl87V> z2~Nr(fk-K&I8r1jnB+(DAUTu%75pgpQt+~CkO$D_D+`|*AF z%lLEnlla5<{rH{uE%9kFUg+;LUg)UV#_mxp)Sigva5L zcqkr>Ps1nRqw%5m0K6C81wVrOiTjFsk9&=KhI@#+gS(0A#a+Oi#vQ{Q#O=Xt!)?T^ z#x27w#LdP{!%e`A!L{KUan-mooE2xlsc;e;AIHQ|aCjUVmxs&7rQ?!tF}N^XAkG`- zhI7FE#(u+o#J<4}Vjp4eVsBxuVlQIPV2@+Fv3s%Gu^X{#u*DVM}3^p7ai1op`VI8o)^S|YP%zu;rJpWPt z-TYhmSMx9CpUFR#-<`iFe|!GM{5AQ@^B3mN$)A=#F@H>cTYh7Hb$(gCHD8~v%9rHx z^O^bNe0)ACKQBKkKP^8oKRQ1wKOolZM1U-Q6NB5yGq0gaDpbw+>p?9D+qt~KWpckX(qNk%L zp~s>-&`szXbUC^ZZ9uEhQZygULQ~LqG#Wk1r=!!+iRc(~7&-v$jdn$kpnjpgqTZuk zqn@E2pzfe!hI$ZyDx$T!I6$VbS#$eYNk$P38R$fL-E z$lb`T$PLIY;yL0G;x6JQq8D)iaT;+HaS*W^u@$ia(S=xwn2(r+n1UFG zup?R!b%+W?F~Wq9-|(P0HJEDQmIz(BARSR5<@76kKw zxx*Y`zw^H3eaw54_dM@m-rc;LdA)f(d8hM^<{ik}mA55tecr0PC3*AmX68-K>&)xO zYs#z5E6*#;GvulBq2W*#LEpNGnW=7ICl@)Gi*@YsyDWEM?(E#Dx#M%~xvjbNxs|!axu#rAt~^(m%g&|d5^^!Qu-xq2^xVYU=-jZ} zfLyO!m)w7lACNDQcaWEmCy)V1Kco+G333*49MTQh3)v3Y2w4qT23Y`^4VelV53xg9 zAa#&RNHN3&(LiJn0fY^qLI@BvBoC4WNrxmtq9LIWe~2f<8S*dZN6zP*p_~^vk8=ic zZs%OfxtMb%=UC3coIN?)ayI02ZR=P+}~ zIk+5D4m1axlbREs6PXj7^Iqi*^jdCX5Y;2&F;xQm3<`pK=!We zE!pd`S7tBHo|`=*ds6n;?Dp)&?CR{&Y)iI2TbV7+=4R8g3$pXG;n|REP5Y<75d zV77O*YxYRiudJ_G@3UTIJ{%^Yby*czMOmgSO_nT6kj2WPWZ|<=S@LTX8 z_!0On_$Ig)+yg!ZJ_6nk-UZ$QUI$(YUJRZKo(`S}9s_OzH-M|brC_+RFa%+HxanJ+S*WDaEB&b*d+G4o93vCM;+yEC_D zuFqVRxg>Lb=FH5=nVp#(nN68BnPr*QOns&@Q=G}oWMq;uv6+ZWNG2#VIWsmhJToxU zdlcmw0sRDh0lf#k0zC!Y2la#cK$k#gLB~Pepgo{%pbeld&{EKR&`i)2&^V9{)C{Tx zm4gaF29OFQ0r5Z#5DA0@AwUoi2$T$p1x0{@Kt3QhkOSyf#@CGZ8Lu*)X57!{&*;mz zlyNrWct&@|o{Vi78#1~wmS!x-n3XXlV_b$UqdB8CqdcQ9!;qoMkYw;O7#XAtYz86& zk^#y{&WOzj&j`%$9t8wP(toCZNq?XID*b8t{q+9yzVu7!XVZ_Tcc<@3-66nt(>v0e(rePo(yi(GbY;3YotsWiFG$Z%ho|SHXQU^k$E1g)2c&zYyQKe1 z`;qoJZ7A(!+LN?_wA*Rd(k`Z*NjsKyFl~3**0l9$tJ0RF%}bk+HYsgvT6e|#5sf$wQq)tnnkP4)>rq-ucrWU7~QZ=cvR6!~$m6D22MWsSh z!KtaK@u`ui!Kpr}ZmABbzf!)Yyia+R@-*dsN`FdU%B7UEDaTW~Q}(26OWBapm9jKt ze#*?0$tj&F9VtyIH7R8&))ak;GDV!iO`)e0q~xc-Q*u%=Qj$_)Qo>RKQoK@JQvN0n zCx1$Qn>?8ODEV&k&E($Xp5#->N0Rp^?@ZpDyf%47@}lH9$E<$@R&V$;HX0 zWKFUxnV-x|CMV;Pk;%EqnaL^1amf+MLCHSJZpjYGzmmQty-#|T^fc*yQh!ok(xs%c zNym~7ChbnznzTM?Rnn5Ac}X*pCMAtcYENoRs!l3RvLxw}6iK2ab`mv-kc3XkOUg=0 zOG-$JN(xExOY%r^O8S%dJ@I4Wo5bgd4-)@Nyq-;57<<{)_(+|2cjrelY$~{N4DQ@xAdq@u%XC z#P5&a8NWGxZT#~1h4HiFr^b(ux5u}{*Tq-F7sVUnRq>K|UOXe76pxKZ#6#ji@yYSA z@nP`+@m}#R@&Dp}#C?t%ihB|FIPPxT&A8sUp14zSN8EBh+`_ooaZ}^Q z$Jygr;_Bim;)>!7ajG~;950R$M~cJ7A>tr$ptz*Cn7FXGfHm$-kiKVm<}zKtD> zeH42)_GWBvY)|Z|*dwv~Vt2%Did_@CJa%F1?AWQX<6~{H&9Swy<*|jahFDdsB$gXX zk1dGJkA=tP#Ad`M#m2;j#`?#4#yZFTjTw&l6!SLbdCbF@J25w6uEd;=IT>>}W^c^) zn2j;3W0u7%h?x~LC1zYqM@&;pO-xygHAWw!j1k3fVrVhM7)%T-COalQCLty&CM3o$ z#v{fl=1=tZ=nv7aqn|}Ti2g77di3S!v(d++yQB9+Z;Rd#-4(qwdS3L5=t z>RQyrs54Q=q7FpuirNyjE^1}e;;1=M)1oFs0a2|{^-+~kMN!5mb(A!UAH|F!M`5E7 zQIIH5RB}{oRCrWClvk8X)W66dk)I>qMh-?kio6?nGqN|bC-P+E;mCcFJ0dqlu8CY0 zxgc^@s612{$_}N5 z;zLoP&`@w_YG_<&L}*Z`PpDhyNXXBSFCp(jUWPmlxfgOP9uq2ol%m^k0V}s$rIl&phNx{*uLPb8JP~*(aBtxDzzu<2flCAD2hIqb z6gW1pJ+LvbDzGHb9Hk2>0Yd?U z0gnRi2HXs|5^z4?WWeEoeF578HU_K?SQaopU}nJNfX;ySfX0C8fYJaQ$Yy}muZ zr+g3l?(^N@yUBO8?=s&7zO#HM`*!+v_%``g`rr9KuPt&iMC=)?A*_~3m|K2V=bpA?@sp9r5oA8#L5pAqjL-k-gPykB@f z^1kbR)4SLEy!T1(!`}P6w|j5&UhTcid%pKf@5$a{z1zJTy{o-Tyv^QP?@{K_o8?XM z#(N{ZbGF??3>FoK(5b5C%Oau0U*b$54naR24@)$P68OSdO( z18%q7uDV@tJMDJFZNJ-2x6N*A+?Km7beruq#ciCM&8^9;#;wfF>ZWs3xQX1@Zd5md z8`=%(26jtzi+77~3v%;ub9EbW{ptF}b;$LF>tok@t~XtKU3*+lx*m4j=eomnqw8wd zWv=sGXSz;y?R0H-ZFH@6Ep;`!YF*{70#}wR#TD<0bj@|mbWL`Rbq#k7boFv|asB7= z!{w99TbDtXhc0(qZn#`=Ip=c1<&euBmu)T^T)JGAxXg2z;WEi(j7ytKgG;4Lv5Uz? z<05t8yD(iyE?5_Y3&bVECCMemCDg^=#nZ*v<&X1s=a0^BoS!*AaQ@G^&-s$`S?A-< z2c362Z*^YhywZ8G^IYd?&J&yg=N9KW=L+W{XM?lKS>nufraKon=R3okvz^nO6P=@+ zL!AAb-JKnse>;71dhhhg>8aCz(`~0~P8Xd{I~{d8;Iz|ev(s9q6;2DCW;;!F8s}tl zYIdr1Ds!?r>7A5LA}5X$&57WIcFJ?ga!PfIcZzfha`JIL{>G;L*o#P9~$By?L zZ#nil_Bft$JnXp7afjn3$JLI@92Ypw9ChJ49XlKw9jhHn9nFqfN4cZWk>yBn#5N{3cDqkI*=T&4hRRxsA!+$5aST);P2q+;Or1)9s#b` z{Q_F%e+0^Vo&W@&tH55%e&E>EMZg$-BOrRt1NO~H1dPg$c1-?Zy8;8)M-)W+rp2S> z8`6pl^&4Gx*0C_ZYF#}@wIeO# zY9`D(RUKsbUB!NuTlFj5Tp5FyRdGG2yWD#5ei_^Jw>05dWa(B#Udf#vdhrpQqG;|3 zOW_Gsh4o5Et)=u=t+^tk+H|d=#JJa2Z_qgk^(Zkxcf|{&y@m+T1U>wsn(lW?DZjBx zu^B#9{a{3G- zqok33OrAn}x3rJaM`|N4QznuY51k`sd6y9SPr2hkaqF=+vJ3L({kwyvudGJhjdDQ> zI~T&wJWYe?+54fU9#U>x$(5Wx`LgV4{(Z3HZc`?wb}-}XisJMGv{$Lh=Hir{q`{=F zy{5$I`}gDHF3IEePQMoOA&(LLx;B^&i|!poF@BUbTE&M0QJ8{fcYOsfb&mA z0MDxj5;6z{W-I0sEPE zK=GR)!0a;wRD#|D(@1ZC!_wElFY_yaTk#UuRr3N!tr-Nil|2V&#%I6>;ZtB6?g`MA z{1{NXJ_2}89{{4m_krRW1HdfJJ>XKxT_F7Re?a4=e&D6~Hc%FE3vjr21K8AX9k4|A z0nlStfk1UH;QaYA;4$G6kPv(k;4JR}rX-vP?yWit;G@m}`(~X22o5KKf%4QhO zKKuxfI_D7J|N0={i#q_sP2C4jZtelv!*>Hc@|{5XobAA}^IL)B;myE_q)k8-YXgv1 zz7Fu7yapIv)dl?6vl8$T?}08T?jxg%m=m~n+p(k%m!X8nF*{OGaaZi zPX(03$$%t$B4B+p4w%|K7C1i&-Gwy*jGytJh1$=ui2hJI!z}CwmU~`@TI6j{Xy#2%i za@h=E`U)!GI79+wAcz384F|kGgaOWcMFP7s;lM!+6zHFn1NiO)1G?)OK+pSBfaRVH z3`QjYOF^+f2`mZ_qQe0(Is~YM1p;e9e!%A_Z$Rtr0X%x|0@$uQ0?3{J?4FZ<+lMtj z><-{>_LOg*?B>Jo?MK_*+VhaF>}Q6a+pAYTv7~W*pJ@}XV>}}HB_FG4{+qnr_MvMFn_Jw!W*h{ik z*_F0s_TmeR?DPHR+aC*N+d0#x+i#zlY`1?OZ)c>8wL^F|JF>RbuAALxU$>>!?sKxz zKCiFTj=f)KcYbEF4?Wk}zdcde6Yk0E6}=++-6K4E@p_g$d@9ZUx|C#pK*ig?L}BdU zA-H`)cdp%OOqP8OIm2#sNU^gI#oHy7(RLsv+kn*#?zxyYe#L!$Zp$W-CkSbiXFBa|82Hy^<8hv<)tdu~})OTJVQJ+uM0Qwl6Su8|a#&ZARgr zj)dXw9Z$x6>bUMb)bVlViw>gila6B(2Rh1r-|k?R_jSnoFLlhvo$GL3d7@*@uR|Sm z;(Z+r>vwc){IaRT2fwys?bsC^<);>P6#bdgF+Xp5$5+e5j>)sfbnv^|I+z0u9Zf&0 zI{phP?Wjz*bf8eW4kTI8QOXo`++cA!s_C>2GJ)8^fnqwQ#=|;BJhD5szDw(v(VNh* zVN+DccY8>OUFg?=kM-z)4?1>OHvMkDT=cEIJmEt-_4ccF`GlwKt8?$Sr~P-keX!+P z`-9Mn?EyPZx7$fa+td2?w|lC0wr4!r)ZS@W(;hLfto@B>LHmz0GutW9$?cbxjBTIw zx2=7SwxPZ6KxI46r?}lyXKZ)ctZL8yC~n`K$89gEp|$Ha6WZrKK()L3Lfem`GTZm) zlG|U|W7-YNLfa$u`n3n0cW>w2a%jK&;Ah*kr=QzqJbl}COQo*0%9} zb#0bIWo=UpmbRY`+O}OQq;0zpytbbgXl>IJgtnq5$hPT4khb41(%bf%6WR{ljcD`a z2DYs`bg$*Jw=#9yuXFFv=rlHRt)EPB>D=G8!J9^zIj)OMxSe)4Q<Yt>}=Mts~HhtzjH{D`049#Z*_dQrn7JSC7%R3OnVkVu0Ve zp_$&wFDJCJ)X3IF)STA*%(PahcU)`7%h1-?6TYoMb6s0?#=kB9K;K%vzaMI$?tI?z zs_cHt^Tb;%s9Tp?o{l}!GMIU!g>-FC%eSg6EzVwRTFSbXv}ESZX`!8%+;W&Pre(_I z=9Ycz>X!U-MJ+K{eT#aVtmSJ2ujS1cY75~xw&epE*79$8W=r|!#1*I{_vVvx-Zfu5|GYVGc%b=D(#_^{_NC^16{nilPVH{~wsvRp=I#y6CoimM z#@?FW962zpS^J=~*?FL~+5c8e^Oy_8&5CY)^Zd24X5>_Eb3p~Ac^50cc~TOz`TY0v z=Bo2?&9*tA&EFJ0&Ha(i&58g0Y`Q(`W7Aj4%chPm51MLL-fFr=z1+0q#i^#gaotUI zF*}<&cdc*wM_k_Y>eAdMqG(E!%T1sOEo^EUxKPpb4rghq-ll3Yh6|fc+vrX6AK{wr z;9yPD7l4}fzK(C=V#1mf<9(WLUvg^d@%h=9#s1LfI&QF0a&VwA^yT$NUeJZcU+CkF zv6_922U@l?o}bgz$lI{6k$YfzWzZ_J;E zYqYiHHDYxcjg8p2MsR3IqwbAoqwkTC2F#>y4bS**8+?MEH0Om2*ER&cS=@l0GPB`v^7sbt!>tY7oa%;GcdQM|OzMUkgMx+`g|vn%kMkR5 zD{>p|T}*A*jEZjf*A>uk*VU~7SM<9+?exd`MUgM+=Tr>T2OsIHk9R#^zn6Wa{`$0C z^=%i{*Kc=NR$mUEUBBNlp?>Pjw)&xc)%ExKt@ZM+s(OR3p#FOzwLUrzQ-2MgQy)Z2 zt{-GX)HCV6^|%73`jd#^y8g7GI$Q9Qx`V%O*NuC0sqWeF6LtMd_SI=?HrF+iSJtHm z%&V)oJE@MbvZJnBUt4z~s;EwPLtQs-f}qX_r`DZ&h^{+3KD$nnmQ*+WOjw;l>s@#B z<4En%F<)yHKCf$M&3jO54!co%WB&QtM}9|Yr;guQd*j>M+C%2WwZzNQYYQP`YeBOb zYiGSFt({NO*J9_3YsWvO*H&d=M=M20EqHHo?Y|GophR&(-u`4%Ji&w$~gsuCCc#xu8baG^J*7o2_PQTWw8RQ{iazr5Xi}c{P9e zq#6bWQA3Ca)jV;Ct;u^BPy;>aQuA=yk7}%TsG6SfxZ3gK&Fad%J=Ig|j#MkMcUJ%R zY)!St!iClEC{wG)zq3_en_F9b6;@c?*{7_2Tf(jO{7bBUI2~495|LiLWmQ!5+9bbf z*=on?*c%!`J-Y{p00xnY+t}cdac)hAu1@G)^ujUvDc91XY$F?J$&+uZYSwgj363>XGGcYck56 zpG1{EiuNsEDjq3APWV)|XYaEz|A)8B_%0X9s?rXZ)ls*VDfKJMk{f21U7yfdRyePr z?7{M)GTa(v+1R!0vh7{CvXe`4%8txTC|d;tl~q)@lqJi)m!8GEDiucEEA9DyxfFEm zSZT}Jou&KhSC>8{&MW=yKB4r_<)+e4(@IMF8S2ulBb?IOz4+1$3#9bAUt(#+fuPdg zDwk5*&u=AP=D#e_W!)_~cH&Y=u;6Hk;okO=)uvS?_n*%$@w0Z8pdZzjXyt_^trz7b zbI{C^b!#ytyS>0AM=E1VPF?XWIh#IGe9r!{`0Vv3#itT(79TG^TYO~C{^IU$8;TFW z7Z)F>o>JVsp{@AX-SXnI9=hT_7{BDQv;p9YKm z{^>8Gxm+k(`6iR)k7Jfh0R=A_AywDb` zEwprV3(YEgVe9wo!Y#An3cscJ7itcSSnpFlT3dP_TcMKcR`=VdtiQy2tUkSKtT@U% z>-7EOtiO{RtkY*&t@v+JYk-nwbvuZ##s#HW)umz9!$;k$M4w^H8^ue@;Z^@xc0cQ} zTubh@gc>(l#xGuMiSC_jx&ODt(vw+gc_2|);#*mk8A~yi^lp&l!}UnZ^Ov3$&tE^y zT8}s8M?v?@b0aUAn_~`}XGCu?-ws=97Wz#!|8s0JKlxN@{_#L%rk!V*d$wTAW2b@4 zwIz|}C8SXuJ?y7x-m6!pq62qK4P!2tj?%kL1)iHs4i^@g{&r3>q4JweyWSOGW+y$- zO~~xiP4_>c`}T3W?)25=x-Xli=_Uhhx^d!C-Sb4HZreM$ZeTw`SJ#%JtHTEC?*DMq z?cDQG`>y1Xc2V?I?Y2utwUDN*+PJu-+K$tcwM&C3fKo#~)v=6~xoDE54f@=&Mdb4snoZH7TJ?-Nh6T#VBs z?8?+6ctvVf7~M6C_kL3cIzLx?3T~*!E;^}hxxYjGDRzZ=NHa}cy0BGU+FPt1a*(UP zROdhJV%Ap0;xgzF6x2uiQ{GE&%tix`tuuGb^os@Q8*e)f% zUn-pvFj+bS(kK;j%+ebcfi$EQCk>wlk`62hlbY5$OSf$QC^@j_fn?&oOOlwq2PMrr z)=8FZm?P<2W|zQbluNd^D3lDRoq?@B%T#JB5J$#R)n+P5&Z``Ct}~& zEn3vPQgkA6n&@% zfd4jY4S&6SCSPf5^HIi??S&Y1ONPPZV3<24+~XAPPTQJku zYc4ji9TjGF=Mx?~trWw4|1O1nuR4JJ=KXJ0V);v!{rL@+ljb;U=he-u@x%qJ@!Q9+ zc0^RLoX09y<6n?juu;w5e{&=&%FUG}HGX6sKRCct`SdVT^?R79+gC6ZKPNMflN*?- zDF$X{FPoX?hh)}r6Pd3j`7oE99A+kwQjW zl8C`4;}{l0I^%F_5JNiWFCDt!6VZ>Om{7t^vz$I%45D%$xR6>YXJmA2z` z4lVIaB<<}I7n*m~2kJQDJ*vd-9MyJjC)HuyQtG3!3DihP4RzN?HFe!i8ufd5E_G9C zH1*JZS1NeUN6J6)00sW}9OcT&U6hN=Wt7a16DXhN*HGe78p_^&8f8~~E+y12nliZF zl@f>jNIuhhk9-(%DJWcxF91JFFK9^$D&QIZ5VtIOL7a2FkLcun zg!mV;o;aaw7IDeqRwDMSg;@TMN6ZXC6Wh>9M77$7c%}6_;rhbIgwoxY2n#OmBPbrN zB<%P+nXtmSo{$uzBaq@4grDh90vi%dK*3!JCy^iUFOYZfo8f2h-nrZH-k?SJZSiCA z?}N+nH(X_S)i(mZ^JxZN)Ek69yZ;aF;j$OFRX`uk-EXs;fXu`{4@61j{Dd{P3N&>+%BwbWC^z7C%a-9>2qR)8gL z&%_=#hhV>lj_xCzf0;k8@p}I6#3T7}SJve_G|bFj71@&i_oyj9TF=S<`3IiAWJz59 zADBme;+0PrZ}R}=@VB!V$fO;ZvarRN%C%!L=$vv)?*S<$3s1nvPNicwlt7H%nP2FY z1<%ocj`X545eLzrZC&Ue2~*Ka=GCKpU36$!9UWcw5Q4TcBhgvAoY0p;hftK(+o*Z> zj-!raHlfZeoP%2XsSRahTT#Edc&PesNYo`p0?KKzCo1a2XJkm;edNdXbI4t1b|9sm zi;)kxW0Aa>WyrO?668}aJkpb%hKvOKks$|uAb!1hg18cU88Mx|4}r0*K-}Iu5n;Mj zjd=J+iQp!a5!)GHghN>ff;sgse8Q#|@PlWs!Jj~SohN$Ins=(loL8`olXq<%*$Q&r9C%xmo@iP883HAGBUUEUR>_PS?;;V$R8omU++M=)}De0L|Y(ff9FC# z8`~jrffcgr8yA9Fih#Vs#X+t=aDxnXe8>Ss-O1_Ne=>(9*qoF4a!wA?)|S%|Xvz7p zmXos$4$oP1CMM^I&^0IW{=4iwh5gwR-yP3hRKGEMaClaBU0X{w;kPlH-NwpZGz`s7 zt&hqc9&*a|Eqt3*Ja9A1O?Wix-RX5%QScdAv)49e2?F(5N*g_E`^%gxo-jNs|KJF? zA?6kMAJ7N>?@2e_ve{V<(16c z8~0^S|F%5y3~559Yf{Mu|qfMrF};M#mn%FgntA!{~+DStI80Xrt^TZzJ0(Ya`qFZAK3bMU2>i(}u+t ze;P)4ygAxrqjGsWb!LCqV{Fr7i}9)*S|?`ehBi%&h2_@(t)4OEv1NtG(90`hVfV^t}GM z6<&YE{+K>+ve&<~Usqq%O-$d?ZC3B+{w_Ts=W4x*z4>~A*4Opgcfoo#h7o#(8i(|9 zWi0fH1=RFTENs!cIy9>5|D#R!^~d+Rk6%30HNBOnd*mEVR|prR8{p%jyWeVu?q_9L z-LaKro&2so9gz>8bp&n|>fB@A(&_ez)p@rAt7FH1ROe);jgJ0HEuCv|B04z%)7qii ze`;4RS7ofJ zsDGB$4#f*vTHgs;jVZ^qOuhDMc?jugsaJ?;J!Q>q`)Ay>ZLaU*wxaaBZRQ@=wvm>( z+i*|AwiyI^Zp#)l+cr?Bylp6iciVHJ5l!2I7R^NeV$JNeyP9zi;x$d(NSY6Z{WO1F z+Nb%~NMEz!lelI?wFEd)@vG7(U6AcMwmva$nl{aT|RGdezsC+ucRPiVc zQK{8+RdGn%sq$t@R%Pe$73BxTeaecepOvq|FO@~QGn6mbpH&vR9i@C_@vyS$aVzB) z1?tKNw+bjvMT{xkD{WIcA^%=!8~%aPOywn|ZweHpkJtdEkEISuZIT8`v!^ALj9$(u zl6krnn+{hi?#s+mtQ}5OjI`h?s)JC)iBIl|Kc#mm_68~{^4(uoa2gs^xVy7SL6!1a z;qB|&3iO3o1>eoP{c*030{5M@LiLiSf`zq^LIYz${$k;GdD6rOd0><+UlN`uuX%?m z|MGjFJXzdHK4ib4JeMmeU-x2O&UK($ZdS2I?my3bxe551ob7Y2+=re}Il6?0+?l<* z%0^8$$|7p7Wn0{C%Z8C-WzBD5WcOEk%ib8?BfC>lQ&zxIP*&^2 zxXd~9o6L>}?`2eL9>^RWx+L>em?D#D6d+UR;UFW6(U+-=7ndo0G%GFiu~Yg%ZvGZ>`72U|Ree%f?e$WF;{{Ujd>K-kMVi!a zqe!XS_Fhu24_inXpH`I;qVP$%#EeM(PHvGLxcgS}(DN)wnwjgn)!4A-*Yzonrq<9F#AUXjgwE@m()T!r7Q6p=EJGf@Uj}7FAZwWdr&J%n<911oOrv=N4{|#Cd`+cHcEHLo1*irwN zV$H`g#F~A8nD608u@Fx$u?bfTF(D^au^c--v9FdRTjNbzw$>TG-Fi(cYwNgj+}7{X z_^n!j$mhWwB0Imyh?rL` z3HQDDC2V`APS`f#x$qz}P1rsh7T$LxTzJCPQ}~enZs9;_C1Hitb)mRFgF=s58im;J zUI}eJPYT&zjuA3pMhpFS@`#Z20V|=Srs_iaiu^*a*Z&Hx54H*lG!+Zhzq%`U=+*_n zt7i#x7&OR--7gC-n^+6Ua#i2yxq^Tcuyw9 z@wQ;`ycQn5ya@)jyx#@1c;yC!cs;5nco_G-^V~!~@Dv3<=C@bFU$(6Mg-&8KU?Q>#rWrnDHW&bv5y*Xw1thC>KAuHXxvX1N2neJ^PJXa-)KHUJtgRDs?L zNzib53s9=w{Acdx2wHo$3*DpCjFO!zQMSe_G$214RT)b|Yr8L?kufZE%YRX5PLDqt zlyLyv&c6rM)YeCx|H+~E=vz?dC)0>UaxW5N)Pz_t-XVds9As7JI${`q78%LJBVK0$ zkdwb$kR1}HNcn^^Vi?Ph&^}GT&nw&EK|&R5*pvsK>%9&OJVM|P>XGnUkHav(krn*v zy*m7rR{$ojj6zwtUm=`G3G_$(E~NSAJY*1tg(OmsK!Xem=!3X2lpVOneIEFmJ0@Pk zB{6fk?$;8z2@yo@fxq6|WLtCeu7dv0=m9p`c+Voz{F!)-ZZ zOUj&&u1o9{w{~{!+8cH+CXM|nk;b+Q_hBbanXrq^#n?Z0j<9&UYFO@04_F_AQPw4s z6Ra0+ELn%`;L=Aq4?S!a0A zMC;UPKc7!iE05GryPsrG-Ai%QZ3+9RsFXDItam@f$+L*kvvz?(#|2O{uNhHR>C0q8 z=>~E|)NOJ<8%KV&-;QkGAWD8N)a-^ z*_Wa(#2kq(Qz8cy>vFP$zwcHp$~BLC*eLRF{SE`w7z zV1KIBYU$*IS4AfU=P4(R){Re^H;#lHIsGUk=iTX$Go7j-MO8n7%gHIh1%n5J3$+A; zr*tcV(kD4VUt-LIYC1RdpS4FPZVjD0(Rx$y1VgSRu+aZvU{SbZ;1lb`fYKi?0#x@! z1xyn)0tlGz{_l*F`~^Qa`=fG8e%^at_&wD<<5$w9;`j7a%kgK=;*L+$+8)o$n>_X> zDErvbe*wn?wuv9Jv8eQ|l4JO`R2urG+I1bZj=g$xD$V)mU*??8alKrhu=^)`97n}` zG`Ey{n~spZ@88k(&ffOz2!A9gcc@=6bR;LmMGTcEo+|dQsDe;G{XR{8wdh;*u zzvl30KkDth-)+x|i^l9D7yEc`mv2+c&Z@f~IlH1+>NAe8Id7b9sc$?X|7qvr4$RKwb6a<6$voQ;5O;V-d-vq_F4dInSq^5~ z13cP{+-&GZ_a)_x9yJyjUMBk)rmoBzOcQPx^w;e%cqG!UPc~=k$G9r#%QzP6oze-= zdoa16tN7@K?y}1s-T1~IIt%-lIu~!t>(KjNYcI+k(>}6mMyqH~s@9q9yR|ZfTehWr zC2qTXQG8qZ_I%Cg5>L&K79$$scj7f-|LJL*w5(R|J`<+C_dJh!adMVgQlh=uJiSA8 zmls==Bd4G$-tbDrkm92vBs8f!l$4~*zh%4fZA_ig---yOog$kGlk;80vjlrZv4o!r zAcLu(bW>JACaFOFDaA`()AO&~bNP6=)NeX+qVW~7zQ!T4PwSRsy!_H-I6uu~us+Sw zr^|5C>Dz>*53;kR-q$!v>5Ftr);V(|yQuP#**9NG1ikf=aBLhAzuF!r9^a)Uex|)t zEV?mJtf6>rYxA9ytuG+stxu2Ei>_;*5gi`m5zQ&c6k!vsMQ-YU6F%^hBwTf2tFWtS zj*xVlvrrhdN02Gb6->;Q7wp~hQs8CXA%T6zhWS5spW{Cpp~+u3{BBD+)^7{`?=&Ad z`Z8bNfFa-dscPOW9jADA`L6I(Hl*{+xtQ_HZ}xvVn-|_v!}lTiF2c(gyHd z*Z^I#8$kZw2H=_80Jlds!0^xp80_Ed1$#HZOveV`|FPK(wrl{KhRtrUW&`Xl-vDom zH^9Wp4e;aX1|U7$0429K!0T%pAT)6Ul*MjQKZZ?SS8z6V@ z2Dogt0dx&E08VuSL`ZG`i7gudGrtZPBkN#y*E+cSWgV1Ntb;3s>p(Jl9XO}01HB9D zpoF>UO+~JQIlpy~>9!7LEjO=q*FmxDI?&}?2aZ!~K%!?2Ty9tcABxw&okwfHG<6M7 z(KQf>T?1SF)B&5>J2wwb1+gU&VjDdIlxSt0~Po=@WEvcU{vNn z-PA1jQ9BFLGiQM?brx(tFbmdHXF=@L40u~T1F|w^fE9iQpbj&DEi(gj2LA!@_8&;P z^bdFj{R1UC|AC)t(;)B5G%&t94MIuNz|~zTK~q4@a|#$JO@V>I zN#OHp5|GYLf_+|-pj>$pObt$ewwDti3Yh@;?i1j?>;!P{83*@r$H7zTIEb(x2h9TG zVC>5nD7i5PtWS@DD8n(}J~awD-i`wGO>IlsZ4|r_8wFx*e}UZ1zo7BtUtp#C7kH11 z0JY~M;3jnh)LD&y$IHXOs%#jrVuk@`|1c028U~^DLm(<~2xxc>fjEgFkk$MLL?{0N z{oa3ol=L4k-ZBWF%@^hGk8F0Q5`)02X#m_y901uK10Yan0F+nvga2as!QFlRKzXGP zxV-HHnzYR>)ua#n9r+D@X8#79Q@=rj@^8@8_6x*Z{sjizeu0&ZUQkus3v4O9Al#@I z?EBpV>N9$Ppmz_L5$pk}rQM*9)(!fNx`gAMF+S!^b-u<+?<0yLB?7;Sbp9PBu=-3uTt&cK;?gcNcj)AY5fP9TYdnM zvp>MB$q$g+{T*~Ceg|DP-$ByQH!yzv8`yCA2C637fYt3b5PYBwn9Y0z@3Ovv8IP}^ zd$tv@@3w*(k5*7M(*h`WT0pB?3+S6{2H6?SK+&lg*pGYxGAUm`hV>WF(%S?|E;NB- z#!cXETO-KiGy+e}M)0J%0hC}G09T>`j2C_eQvRR8;Bq~{Wz~ZRPW2#h;1ke|{{%=z zp8&3*4k!`o08^q4TzF9n+`MZ+@l*}yOs)YhcGUpOmTG__RRdp%YA}}n5m+7k2zHND zfu0Lhz)rUccve;d(UX+`TCMo-7Eq)<05ds;x&l(eGN4KyaE{ZD-bUF3P@%a0=#h{;Fi4v zHb*w)&E5jgKq>%P8!v#))fXT@;{|Yd_8k0Y_Z)2d{0yiDJOj0Z`9O!34|en9gXyF^ z5T=|5&Odqz{C7VEogbb6Y4;~!@oO$f4#@>ShjPF-N)9-?@)&fVe+W5^9S{iL0m&PgfE}9&qy;iTQ2cG+FLE33C*IoZwr>II<(t4<;wE@>B?Ekt$N+b) z+yFWfH$c$kbl@VE4!RT4fRRWV(2Ktg+W4;nv)F6EWg`{v!>NG1m;y5CDS$ea43==o zVE52fpc-}+yy?0E`24Scjh4&cx#wjdS)By7?M(vxMTx-QBoQEw6TmTz1kjas3CN3I z0zBt0g3RT3@RuA9M*ds?H-j&L<<>YLejpCCzCRBR>^cvK+2??p(mBwa7z;!Vp+HO>1z#^Cz+)W-6e0``_CVl=7X)NWxqx>k7u>tW0aL;p z@Q=v`j|W&l^e78xl{3Nc4kifAV1Pt^28bfl!E7fDm>r-2?LsQ}s73|y@f4suO$J|1 zkbz}233wTkfMPlkq^uJ_StJ46{(=YFtu}qPJ2()+j{`h7EI8JR0VnogfXtm}0P#hG zw5TW$+87CXc0~fQv@>9AF#;gL5ul4)bBW$e0dC95I+XKMEinIACCf>#!=AB_5s~ry}_NG-az8Q5wNTGFyOa73@#;m zfr{ZnAlLB_aLzagE>C)b1UFA$ea8c2%(#Om9_|2t_W<}c>jnfp-9UGiD>yT=AKX2# zA0*y(0fv*#faSb7X->d!*byY!I)Zyi4j{5;ALudN2ZUnwg1%OJK-9Jec~m=ayUG^W z$=HG`p*A3;z#1Ib*aMzS$=&jj!qn*a@#F&M4b32>r2L8k8xfM#w7GJ{4Sz}N^JVHkqN4+h{UzX3RT zP#>tJ>Vd>|U67}t3(yE1!247i?3vU88WvjM4SO5lDb)n4JeuIiehnaeQ5`5XsDTb~ zHE`Hl70^;ufaf=5@Ks(Ji1{ml#T$wstz7{OC~Z!FJV?)w1Iz!(0!c+#@Z-1)IC5PY zaK1``V^UI}&r1?$B}xG4PvYPezc>(b5(ArJ7N{;31;(=?;DD(Jki`mvlx!hT(IW`% zD+vPgqXL^d9Q=S#y#>gx@d2VGAK(ypf#o9}klnR`ew5un(>&KvrI+LFPKE8rB zXs@910n4cL>+F#Uza(;EA6{6i}iA5J0ak3Mwi0?qZ z6#PW5{A@>g_}Wq3?f;=mK0na2obPDKy>IBlx;E5t;wySZZgXr~QHRql=)<^XwD{>4 z6f`%Xi!+U=wo)UyVb_3OKJ^)GimgY>AALf@KGmUb|JI^qVznsCqz3IfQjM;YKcY=3 zRj5~C<>t+y0uBFHjxI`I>9W;RPzb>p2?l@eF+xmXD@Dd8pR) zr)YTo6V$&t7hUblL49W)qamV?Q6;TMXxyG`G~4STN)La4F0k*TJFeVAWggx|pT5mP zXB+OIQ@xpJ*34~mUGO$4rE&}Xw(};j68cgr5xs7jfEw<-gpxcjqEY_wsC2{ylt7L{ zVfZ|1fAJjp{8}vfH7f?qeR3Av^%|hqG8FaugrKvnFuK1JLfr0Y!^v06Ph&W zh~DUOKz-Zxp&#q_q66jj=-VPY)IQG^rQfqbPo`O;%a`_SiicLHJJk|hK4XEN3^Yd> zhs@A@4!hBk-Mi2~I;Loiyb0SBH7ld1-z%Zrj}=kzR0VVb zmPccwP^ka$xRO*<=swnhn~6^Dh; zP)kAdwWUv^9AWIZ9=xDH6nj-4G7iwGxAcY z9(g!Xha9M`Mef|JK^_yUH$TTmq*<{FnH;S^D$C0ew`*kx5?P8w*?d5@h`mRS_LLyL z1;vO^>|2E3`v!^AEkeBKULj32g~(dkOQiQq0YbNYfxPE`juf@!BcTuSkP7lsq;=mD zBuy+A+1l|KG0%B~NYJy9Ovi^vm)HZOx&0nO&%TQ^kg|{;ws(+JflP$An5@g zo`ImoH;}jUX~@I!>xk3EP4Uq?6-if0K@R=8ioDLbf;1B^Z&nORi27;*;$3wKvAlQ@ zY4VCk6lE_Ua_#4l>dbS9erPOWs~3atjQ|ABN0D3-g2bD_i1Hj433zUYO#bU1{3n)gIfo_QeR5$=e+$^k^Z#T9uOw;x%wbwQ>l zosg_-M`SI)0g({jhqP7LBc60Sgl=Gq_;gq!zmoPKIu2Hd(zFFq{=ghjIcA0!2<%3N zicFCcktWDl1!E+zb_X)R*p6uH86mRY43Iam`iS^$Jw%~b2l<+$jX2qAAz?$B$e!yO zNSUKLvN)!S3}&bxn}rk7KB!*T;&noDOp7GmJBlKB8||-C6TA;638_Nal~|Z zD}pAAB4@2d5X)ae$enmWq}W6NiTl0<5rFv+8*N@h^V0@gOjw8cW!K;>#VhdZ;AL2u zcM0D8XaQbvpNBbPv+$FvGjNjGKUn+w6pUj{!coc-u)_N>m>oO{UtSx5k7o_TE&GPx zwVpw^2OWT^8vSr_>2J6&_!oR~r3Ws%*$ubs>4MY0cfb;~pRlb|JFN8V2mI9IJ3KMi z1`o!3g_G4=;ql^Tc-{94TshGQ@43_fhw6NW_m+NwoBZlvsi_)R;8HdGT&!lc`{EwJ#})6x+}yjcuT2)*Tb~JQoVX23 z{k;jl;bg!PA~#@_j5N4i|2phhlnRqvQegMit8m-NE3nL161;_z2 zTx3FlXNpMhpgj>z_=t!5J#g?uGX{QkJQ~*QjD%fJpMf<7!{MixFnDDAG~7u!1;@;V zz#Z&h_|M7-_%Rx|`5gwp4(I$}Wr5@H;|sp zpoqf5{lYNt6N2kM3BYx>{4hJ85AIgyh3BqpK$RP7kP~?oqWxNiPIxatv*inrlj%I< zoHYy0i_JhMHziT-$Ry<9KLIsXk3oE9qtIB^$mUM@Fx0{N1NHU~KsS!`LwxUlLt6U3 zpxNXe2wLfaiq3RG51M~M`)%5xj0ZoU`&++5A@nw=v8xrD+TQ}z<$r;E*KCTPAEC-$mC%T51yudC4DyvMh0Kunsf6dy`LTSc(JK$Cd;SDsO6Ed8Nspn)=4|Ml=|jl+>U{_^aThw` zl?4swWkQysw;`+Oo6z5y8_-dmbclHNI<&7l6{@mHftJ#)LIcy6p>tkI(2v{%sB6n5 zDE(wS#9tBz>C2vnR`IdWh1#>wM@;~|W+PBwD+Co9aiOvpHUxe$p_yF_NcAEOTIiub z@s?z$A(04G{l-JYJvgW-2?PE59R=lBMMBz%5s*)B7-V4{3VptC3X<;#fn<$?p;~YP z+W9pAa?|yP#(67_=eP8@_Ho_auEmkvNP?ru>1js4Kk zKh99Hg%cDL>#({1xEDIBZVz3?+CqolT0+Wldf`)GZUtL3=B^@*9|T2{?)oA~~5Ra~aHD(5D+%~fMuYrawLai(+$a#%;cV$yTvs&xXFDHaDzK|DUI9m?i!agn!>G8P3C?+c!e7eC2<#?CUDg{ zE^_CEwBNcwQizw+ZL%@ZCwgi z?+A(8%^`3-vTmm^p60GrpX7><2XkBHg186m1G$`V ze{N91aqhnYU+&)je7Jkpj&T2JALa(RAL6nJp4@|}?%dWlZd~!s{oJ*6XYPG%C+@PV z16LTcm-{)T;6>$-1R^yZUIAr ztC%9jHOm*}^3@4*<9`csD_8irFXXpykDBswpSo{w-h{4kSlkuPcX_ktpPuHl2~Tk@Xijj(Eyp+_hyHRpLWeo0S${aUlLj~m_xm^|Z+>y&KlgCbdb&6P z|2jA=0zWycO8;@XcYNp2_O)@!yjwYCVa*&Gy@}Hm*T7jxujhQpspI$+*Kn?V`pAiE zujK3;F6UfaDCJ}be&C#xf5&OpDdq^7z2S^GyynDt6>{266mWh-J?C7Z=W|xhKIN!i z&gINzJm#Fu&gN9Uc))q{?j9$!CW}+qoXPqA^A_iBe+EZmJe}h+f1P8yk;-WoO5tpm zy2>$Ay3Co>Oyq z`V5WJi=lAN5lEaaGJ!Kf!*TMN7>@3yk?RAU;g}=goX=<|NAc__j#5krr#U8wW49S1 z1;_ex%wmsoN@ILE>t}s9GvEj(3-#ix!v{ICkO!xmeSj0fbmgSbTsRQfiK9Yr;E*tT zIqWlboIRm7oV?&YoNxY?oWi5#95=7soT~>+IhUP`IgWNaI8Q8$ICaJboLl;O9BoY< z&S^z0j<2L9XGKt*6S%Iz!OtmiEXEW#g?)0Ifp!^A;}eviq7Yv9A}zvsY8&*vgD^>@mL>Hp3dQ zUnwK(oMkTCyOYf>c+X_l+@`ayLR7X?5Si^}OJtiV;z2*w)~P}DtD2eyPD`#Hq1E0#(?nJC)czJPPcfHd(gnW9d!hSdv}lDbBv9 zwv}x?Ax^_aYpkn-WtiK}Qlb4|ecbzvr7irG zW%ae0#hcm0iapc7Dlw^NJzl6~c~(@j9$u_s6?#{&*h*!r+1~do{hSh(1o15^-=c`c zvr@>~T3NtqyzrdmawwlgmVV0e{gJ~OyY+}=f9fI2S?4}${ZAH){4|qwlW>d0+Lgf) zn@MB&7hT)5ic?rpHdk5bauVyo`vevOUu22zy}&xQc8+zlG=?RB02av}VO?F}vd+9? zv;MJ}EXzG~mdPB2)l*1f?I#mhr;Twe^S{xo504{RD`63=X^k+}osLtijkFM!l1~t8 zXloz~U+c%pJ$sCG+x95SW%dZ`!80#bapXbPc})+NV7nX3A$dQ`#NC+N2a zGtrK#WLPp^Bw3L_oJHNWm1X{0n3b0z$m($7XH`t|vV!k# zFrRy`F^e~rne69_%!%N6rs~#N=0@=}^Je5E^RMhU^IyeZW&vTCsi*RX>0R5;G^hS% zHmLV9RqMN$TJ#QPk48K5X#IC4OlxC?sJAlbYQHdD$c;>Q< zT?JDytc-a^0-X!MhvkA;%t&2=*RUC65 z>>N{UOAK@L0m_VVhM8Y}bC_SxvY3}O8O-%kD$^jC%oJKCFz?*JF-I*h%*obBW*#wu zslGLgc_8N$)4(N!S=Mu6GYtq}%E_XLw=;cC8!{ix=`o)r z=rD#7|&<^G0J1781d2*48eP&411Fi#`X_?7+*XF z7@OffV_!rsLu9&(k%)9KszurvuhYIWg0~R4@&*VA7xhRjJWdDSbUG0gI6e& z;U9OBab`;}V@FINBX`}8(G4AA)Gzulh?|Oa{q!M5H^GyUJ92=r{fsN)%r9q#e~=@C z=f_?~sJ9&h`fSZOxZjHLt<;<$w`Vs)tiXiv-f$;F`@RvwN!fs*l%mVX5!Pmm15L*0 zyc**kL4_ePpvW*kAF=L( z(AAaO=~frN(}fql(o@c~(7(1d(Hor_=*Wvt^gn8~bfJWg^k4H8bZU4R{eAO$`Ukrb zIwR)|{g2FRx+MCNJ~jNDe#tkV-dXyDK46eTf0U9<*I2nv_l~$rw`t0xcUs<}TV&m! zy9uVzrHHBY)bCg64fdDmWe*eR(V`dWpUH9bfgiE-xAtf0&JPg!c_D}n@NBwSD}$b8 zNuyWZB-8J#5$L-^adfyknjT{iN#C0gPA?ogP478;lK!zEh#o2vNPk1~qgQ|Pr6*YW z(1p_v)A!9Eq#OHr(7zSA(aq)eZ|dAmbk(+f^oP6c>HSx2=w0Jh^vee==<~U|=}Lm8 z^nYPH>F3Lh=*_AI^sg*k`js{~_1x?{xKF#s#6Pk`z4y~M&O_MFV zPunJTmo^xfNej=pNxL#yG(0J~m zG~x(EOEcem%te?q@j4pqq!fh~9Z00@cz~ll{u@o}G>fEt;)c_RRi|l9A}47B-a)jY z8v(R^J;!M=y1q0R>rLBL;6=ML=Si!wb*J42t~BdvXWAuUM_THky|iP=wzQVEJv4qr zOWJgx8SO@NBYs>dc`j>h#5N z>XYifR280K>VCUHssXc)`mvywsx;a~)z|BwPMrLYO3L^~ebU-W%@l2>y1O(|pF#E1 z##gn}?9q=@OPxw8I8jDDm-3$K@M%*nUoWB#SiGV(VGF3Fd(Wu#-=9)@M02Tm4v(m2 z^aoUG?p-RbE0d}rb&Hzda)bJUd7XOYNeWfJ>k5@6kwlGkytJv6U!Z<`c#gXC?JRXf z0Ht2Df~fP6Y^ux+26d>GN@dQIsO5SDYUMF36+Rb5oq8ET)%X=k6_hwd&9Mun@?rw1 z^67rm{wiN8cG8>rRP``5`@lh}Kh2$5o#jgXTklN$JnKLW*W62e<6%qvNZUibbjN}! zT(_I*G-X1yP~J)XlDYF6^diSB4v4EjzW-`q1>{ZqQnG@Q?#MK6!^{% zCAoZna`N|Y${=4a#Xz@61g%zOc5O6ED`l4%~L^I$GzDC!aA*|`Ulopya9=u&iX~liG(l~Rs6Q*2TkD8z^Ml#n7DieQ};1=DU$i67ZTIk{|1nG)SWu~#*u zIPcJ-@Y!io5Km1?VW1l2ezY>hlchj;7AH$-xF$t;cwd}i`9hQu`$33ush*$W`Gc2I z)3>R;Ppptfmlw%tg7f5M=^3)J`V{$}!8rMX*&dp6wPe?aAIYLmE6522rR3^2@5sd;-jbuLUXxqv zUXte;pOf2K^T_xgx#WtDN8~R(56J0#cgf0sGRgiUH_1oF(#gD&*T}@_WODkk$v4n$cODWO?tB}WV!(l`L5a;DNcHsq%XKYid~)|-JF;r;rhl&i{Jl} z9P5WjE*}O+yf1!}xc7TV&#!fo?!>i|+*sd9dC^}<4S~(1$DWNOd%JqlS%`9ccGy8j9Z|0R(WTyl{llpROHUx_7MW&;v73?}g&;*gG6GD%??G|~$(0kPJgkkQ!Y4N!zy{Bkh;+A*sxJk@7k{NedMR zNE?s#ld2M&NRFg^B(AR=iL}R>q^W92N?hMfD*SCiN~_*MGS4w2UB0A8dVtd=QN1)t z>n3U>S1DzZ`?Nes@T&~zY@sCSO{y5_F;#@*dsLA0Zub^aj}#B7baIvG|7D5zEPtL@ zmM}w1jGiLOxs4M8bp8?pc!r3w-TlObl3&Eqv~FS^rGt3f>p$W}jo+hGq z$!B8rwL0Q!LN#$SU?U1@l@UFb-w_YAy(RMHzb3NIza%~heojoc$Rj$4$N^B?ZS%tx-oO1d-gzKa8KpNu^*{g*W{@3|!rg3XA+o~Fdjbyec=0YjqvOFd#L zqD^e@&?HvKs}U)`m54q0@tdN5orh5Z$V(loykOa{LY z&OL1)q>(-m!YpbCV~dpp^U^YcWz2iR?EYc`Nw|oR)9{jT`^s~|L7zNAv1~5k_xEf< z?T!0{=)f#Ot;%h}ug)8Ux0%-oo*^lOTk2N`kGm5H#5?hXnc(vTOSKq+c_%^`zsV&; z1h5D<6zGKbZ)AdbDuIxB1WTwCiy}O%4<|TXI8DfO4k5f+4i2&fdp+ z8E4^*I&R^sF5JK?nP126>`lh6CS1l}vP!_W{l0+jOge|ZyXP!^TOW)+mBhgZSuydl zzo__2mq_>zW_WylXEZ+W{26@p&M^Gwx0Co5I0#SG4ZycH9K(-Oeeku)hw&j5p7?^u z1Dh+T`|(!`9r3CGd-36GHh9bfEBwv_=J;o$rue^Ccj5=ljqrE=)5FU`+IUwDO}tg5 zD!xBl34d5n9?#5`#s_&y;MYe*@h2|};UN=#yk9d9euA`y+b^|@^DCIg8F+xHE(23m2`YF}^y0d&>aN?k;ZHYk zw9xCg4@=3os+7yP3q}bzp~?$5w}5jvmq~zIkArbcH4ZMnkb%4BPR0535OEbW9By1V z8rOa&0(aId6!)h#1ScAF0yj3{hf9q0#f`{&U5zW3N@Y%zAnzt`A& z&P(hl&vWc>{8MbUL=ILx?IHHK>OJhi`eSa&4^1cZp zX7(8qnOlni8Xqx!*UK?uA|EhLpcr#}_BF;3^Ac0i{R|^=^eINE_A%y<%|i_B*Zh+lY$8yy^M(pNx_!|g z_eSh6&Bv`VrIi*KtnqHlj|^iBFaLJTC{Z7i_EQ_P=Awzwd#;KRQ&Ped#>in5N2M@! z$HXz3r6QOrJwc4_6+VpX{Cc$B$(87unuTaxr>I&R>q=BLr0>OKMh7(nDj+U zUhj#1veXgHcj~`r)#|qBfB$3Xy#Jwaz&M_gBqi$(XB>CN*&Ggsb8c|Pxjo&UNFk%8 zL|YP-L_<=Pkt7WiEfl3h15pSmWro7{`wu+NZ_n%XJg?95e%o{?k7c$g2PRvTbM$A* zw);&=k;y~lozw@)mcd$O0sgkq@%l~Wz76Hd?3hxe=ykDj()qFyopV7+nm(sAqva|q zYI2l|dRfYKi5bdw?+z=4ZU>ZQr&5)*Q+t&A$vc%BsuGp-P4Pj$X=Zfyrj}=|t9x6_I)+uz4-BnO~ZYwDERSNBtaz%D~siMQ=s^WFb zWkpuQ1%=ked<8KgS3xYxQEXZ~p*Rtgp?H;hSn+x&U6JLQs@R;mM?q@ep&%P2Ds&Zb ziqp4a6kRKkiuWOM#ksR$1!$13;5%{^!ktV7zwa;=ULIZt;;zJ)O$_c_-q zZ}0gaH!rv_W)BhcsaMcHHd>uV3?(vb)92iAAx9g5rXl9HQp)JU29 ztW~MJN>(gCT3jfH4xX3qGe0LU5S)=GU&xm0^<>K94UWmP>4)U8Icak3*L&sh8+OZ2 z1t!ar(znYEA8nJTEJn+V+?Dbpu~NBHnNXfP93g*X#+H||>2k^`vb>=!Og^?YSl;c2 zmmf$DkWbz8lUs~>%XPpA`BNrb?vdprk9uw==Py~yb={!yV^LsvQ=zf^ez$>qyQaSU zCt6z$OWr8AEMG4l99SzC>93YwCM?T}QWj;>TXV9Jp(&Z2!7rI}$hd4SWkj~OYEbt4 zYrm{RuUA%p{~)v8@lKX_y+fA%sZB=R&?*~3K9hNDX_67nH^@xe?#pWa-jQvvtCm4H zm9nKHH)MHtugPYHi)1=_mt>RZ0$KL9v$E;)r)2ssvSf>M8L~@|BQiD80h!aDRGC5P z9@*2*9Wv*Y1R38pP8LRwkuC3wl*QeU$%@~JWapN7GLj8P)VA-)EV;QK$K(_U# zo-AEQTgFCgl>O$emj$P;{lAHd4BfIM9T;Db`fJTe#jaCQJbgksp8Q=($^RzZUH?@o z|NL31v#Lj$YW`kY70@XylDw8O4!o4UEN+&re)dHAZ|ISdua<=ru)=a5I#!=~xl7rHdPxecr`ctH8 ze|JiyfF$Vwmw2f>bgNWD5hab?FPG*Oh^1+F_)^E$9O;EohO}LUDs40hmnOnPq(4Fe zrIu2R6ubu|?K_2(^2!j>OON5wD<7Stk-zPvlWI0n9}}oF2o9D43C7avd;{sf?Rrw3 zqnoAQFK9{+RI5wBJXe*j>RBcIGVxDxaP@*@Tz^)g3!9WIA%9A45XU4&qG3tM_Ae6D z!9K}c?nlYC(k{u3`)?$rFWM!_o>s~D_%n&~za|Mn^Pxn=_<`hvU9F_gyIL|qsFXZr z-H@;q*Cf@6MUwXPi<0u}d`ak~T*=My97)&x6OxC|k4Yjs4@tWF(@T@ z=>$r0CKoA5x`>b%UV}?gE1V?PYwRSsb=DHxV~FH#i9eGA-V==C`<6?T7g5`cd&C%^|T+Ye4)|yH`A} z`$7Cp|DAY0utPj)&?bf&wTO*CPsN>}Msc`ty*SJGo;cgMM$9y>68D43#de@lvA0pN zSktgjd>MFNyr`ci*4H~Np3y!j&eb|D{;PRJ4AD3s)>@Y;ez<0j*m>0svFzV=F@JuW z*k~qNeD0S*-1}W3{xU2Omkn^mh#sc+a2Hja|2kY8+ZrO)coHa9)?>s+?x4h5Dv@Hn z5`=i~CAhfatdsa+mYtY(*jn7S7a~?qG83!EfW$8)Krxx4D=r{uiLc`~hMc^~9 zM2f>NL~%Qxi~OS>i{3^&6xk3Th|s87k*RaF=n=S51l7JF3RAfz@|wIX8XLGE;&q%8 zoqlvibh0vA6n-I7^fu$D$Z*#|5mdQfG(}Gl9mMPu^*ASrW=-Nmof6uzJ#A`hsE44PMqu2d`wr%o*j*Y27V z_6eqhJ8=`j54PWhOIqKA!!uum*&q9as~>(8B8s|%E{EO-CnDR0v0<&kTIXlNCfz3C z$+>zVQ9UnY51$owK077Uxt1ja9Lf;( z$qoynaOuJa(0#&=HM@n^za|NTn&O2wE^QUQO^FgVaOJ|SUSi=_0AFZ4!xkF7p$mH} z$U@1nFyT!(LHH;DCp>M67CJ8a2#$JdEdr~hQ~{Z4QEoJeWXVW+_tlezdr6Fzt}yWzjpBq z-|k^HADEWOZ^0eqqt+kf?`ccr@5|c552Wnicj+bYVehx`G3TQB7F-3t*;vAN{mkc! zFLC&6A%m}PPT`;Z62|YpOyK_%;rNZ_Xg=qQ5C49lC;zj+jo)hO%-_{#$Db^)<~wpA zd}jkQ{z8`#|Hvr-zn7%L|Fdxu|NV>g{Jn?Q^1owL_$I5Cc>4A8ym!enJU09{@5;nD zujcv)FGD)WvoY)EWqka^t2x!pyAt-6$6oh}_pY&(2iWzDX992HjgQy!Qj72LK1I~< z7WJxlU)sueCk~YGRD7=Rkkc1=-Z%1jt3Q5&#zS8Xz?DN z5oZTaM=OE%=E*i5V@EWv$X>y#84&Z1pXT#ygE+jCf9brsN;0oP6vmV35qLw-u{_(I z{ycX(AD((2f>(F~&Rga0#Iu~V<>?ez@t#pEcz$b4d3$dg@(xP$c@$l3-tc2ho`1YL zPh_sj3+h;j__OzKM6|=7h?1VEi0eluBH|I>BUFZmBUm|KA`(%35v(5{BG#OH7mPKj6YDes;)QqSksYjGft%-;{y~3Sz|I77%KgVV6nBuw{ zPH;cnALHUV!`xkq1Kh;?UM|A>1Gnj8Cs$|ZYp$KaOYVld&$-p~$6WK71}-z_K9}Zv zhimw%ihC`(oV%c2%GJMih5IMq61S*7pR2nkmm6k~!wsv+)t5hwz7F#=roHPbezV8Tavin8bY{2Mj*FnB7j?d z$d9|%)SC;eb?5E~bKzbdvgc;+w&4;rtQwab~AJaOw`e;}8rwIG1j` z=j0{ka)4`d zIK0!DoGp-}98C2A&Y*uPC;0Vl&MsauCvH5RqK0!g{lOe)G@f&J4$aX?^X0g2^x~N3xpBHIoH^tQJ5DabnscSeg0nNklmqNC z1Rh^s<|sM1ISby>Dk5^IF;GzdmITDH_?cKkC@86fuUuzuOux#0 zt9F?!Ja(R4yD^X5b@CLuK{t!NHTM{M)Zh@?wqQTo-6Vy*{?ZQiHE;rZL(w+2HzbdrLdEP|S9$Cv#G~4+0WI~*{jpnu+>+VS?_l(vbN66vR=nc zvKD^)VEt5#vaWv}WI6KsSt;*7vCfdYSxGP7u)w%>*6D{WtT%|KtoK!qSl3{6EWe^! zR-sWf>t#*_t5M@RDN8mSQS`HmR~KHm1k|ts>=hiuCLc+33qK`efhqgWyf91LcLtY zGC}@hKD+UU>0va@j5|8POqw5KVim*8zODf#3fs$!u71xHfjgPt6R(&z{<0)q3juXtKuSc2O zu!GD4cT<^3=6jf~8OhB1Gx5yz{H;uAb0l-Uvy6E+PsnsuiC}JzWHM9VP?$_FB6FdT zz?7=vnEBiMnfcvFrqma~oWJ7AWN0`t_r=1P@!e3SlMk4A_cDm7z7EKQZqZ?CyxGXC zb6?N&$X8|VUS45ji2pLA&*vEHZKoK?nLim-zegE0)FHZc66^btex>;Z#nRm)g^_!i^XNI9cBu$1wm5t=FI{6ZM9x{ zG4DNHSo4-XqVbCEC2FNJ?>?oYHa60y#dY+!d$shsjn(uHaRt5VZYiCsSxkQ;yhPW% zlTQb)&!x{tWYY_(j?>qx9-(8H>GYr*d+7#CJL$K>6X`}pvGmZHXgUF}pzGv`>DR`1 z^tDJf-T63;Zq*k~A8`nwC+x-3+g_pRzfFDV{aZch=N`i8W}BSou{>LPX1OIj@h_MT z3pS>g<^k!`-*o8f-8a$4)7I0^b*R#HOjpqv(SK?3dvmmawNtb)@=sdC#Zg-R_d(iK zkAB*&v`;kSS6#HDhHq$(rERq5H=Aj>i;ropxQDd-toyX~k2SP5NEPjDOc~Ab?ls!U zRYkN%gbTF$IeD~wJ*Q}!p;@%8TaMAr)*PfA|CdS&!|tJd%1EZcJL73AqpdW8D3Z3e zR7yKBA)pPqacOIIGibjX$+S|nFq%VX5G^GeLp#^)M@s{F(-1;;+TCJjn(CMx&BVc) zwmQy&cDu%e<~(me+lkbpo!F~Ii*3@NnW(DK&f-;QeMkOLf4%raeWf`~-9en7{>mDo zy1p5r2Ive>O{hK8XQ#TUUhm#ecj>iL57Anvg40i^Yu`PjChI<+-l5!~KFY45=5~}( zy|hZG*Taga!xnlw8kq{r3Z>p@4Wyc>VyJXKKPr2N7Zq0RMtwH!M0K*X zqssVJRK;0yDx$-f+No|p^+D@W<9BYNCfr(2#f+&^`@yTIL9D-&y;*aV)aR3w@TDJ= zAMjBMJ!+70tnf1>v-=~3r`bhWKzC3i$uBAA%AZp%d}*S@02(M7A@?W=`)*UpZ&y;P zMy^x#gRWA{!V4+K(h4X~?&MNhMzbjepiGK4@d%|PHJvh0y_YgFw3AW?NTfsr#Zq4E zjHalS$tjz9MU){;9_6qvi}ELiN^!eLq@Z3AD8OYbrQX4x;>bf%wjTGO?5=a6(7)SL z{u$U%;sPO*+li)>Cszz9g>UpI!7Eyn$Mzd2>o{r@!^0|+h1>tg*9QKO%{NYyBfTcb zdu3x}arO{dr=g#Ga`Y4Vf1@vX*6$6uC$f!v@^mv<`_W^vaIArxqI;jL^sOO-6*tLO zPu?Ie+`mdT8Z0EMYn~@RbvsKY@^Z-64rY>HRvaNe>`Eu^TiQ$BXu0eEH8GKVYI`g> zBR`r>&mK^gNMc$^5B%{1N$bEbla!|TG zIjzK+eC(wKS@6q*yjs_goZz8HzRlJmH|^0NpTD%0jDNg}+%WW)v}WBO5&$+unh*X- zD%~RO$MXq(Xg8ve@24(mqvBdR2Xw#C}^%x;e+mq^v0=}bcT3|WD}E5I+AgQbnp5}(w*iE(*EH?B+!~PQaU(=^uTuq=@Dl;=~VJo zlKbgM($y*{X{b#=njGbj+Ep2(WH6cZ3mHoCUqe0*OByQ z4n}I&Y)RT-3ns0`f=C=5fV4kJo0OcTNkW#cBegfKCOLgv3KvYyhx6CZgxi__3UBuO z9_~sS4&R~}2v6AC6CQG=JN$Rqn{e6Vw(!yq&EXFw9)}mGJ`4{rx*y)^R1*%w-3*6w zZiJg|yBhu>y)ayqR}g-$JU6_*F+2R-yW`>KMh}PE|4R$c(%Ku|Xt6WA(LEtND`;D| zBR49%AVwDcexERWFq<3RaD@>rze5i1e;yic{UI>icPt~%(IxA`)oWLWZ-2T(tav+5ygM*WJUKBz z^!hhOytRIqI1d;gZi4m@XPmo<*L~j*9fRA5X^dv#RqpXV*RAkAt^~VcC_$ zl=Ih#DJ8|kuBEPJ&cF5(%jfqH=T&wP^)_rLuIO$h zJ}{0XVlAb_iw*)}vpa{_($5->~hs=E6$vOomn5{}Gnf zFcN0n^fm1K)4s4T%^$+%UUY_iYJU}$)zKQJ*ZDLovg=XUiT4k}(m&n_3+kx~>+3BG z!+gFLwxj=YSjxcpFzT1HVGCb!!nS?Q47>C7NZ8A->0!72M+Yds?hO0&B_Ry|Wm{Ox zKvbBtUlwNnSs3=TmmB8L!w8doB!_K%9~u_e6&N=8HXtmz!#C_syJuL(3wT&vvtwA& zQ&`yQCTJMH!7MD}zERkbJNjYtTbskC%Qu9H{~!E?S5(5PF8&KWdG1fB|LLjFrV~Fy zb&rmQx~C6@+N69A9Z&igx-a%!=wRgQPy@+}P}7KKp)<6`(1NhKP+fd&DA(^+Xo5$1 zDBrOp)X=IZwAkcA=qmlZPzTLZp|)#Igw8J<2|fEeJ#^j3-q4`FouTZ`gwX#ZCZWF` zMul##k%hKg7l!`4$PFDj#Rx4wLJq~Igoake1%{5w0z#+RzM&mqo}npdc<5g@$IuWP zSZFi|8XB?5EYwWJD71Q7FBJGqD>U?jMkw{g+EBatRiW=H{)P}Q&4rvhIT> z@gpH($=8r6YF`Ky`yu3@TW81-=&KN(UTer2)u$o5ryqtq`FcO3?@dieOXJOugEw!4 z=v=%S5`Vlfq-a+`NU<_EB$<&NVvIc=lH+nXw>8lYJ;89Zw2=%%Y!3`CBc>O zqTn|M7lNCY&IX_OniFi(oEdzo>`3sNtn}c4?R$eCGj|3jArpfCnQjZFu8s;$8I}g` zY!L(pm2rYcGwH#cSW@sMN=R_68$S3F03FPkM+T34^au{Da|zyg-aa@b#X6YEw+Q~{ zXA+!jW)S>zMJITue`9dhBlY0?OKXCi_bn67@fQg1d}jz>jeijy{~aSFd>SGw-0LTh z&VC~7O6(#eQ9B4YmzRWZo1PQcKN<;zt#yQZ*J=q@(r*z&!g9i-PYHo$SVTBFd!CT} z<}6`LMGnF6XeQyD^a$YxDxIJW+DlkJw}a5xv7HcGwv{k&Fp>ZfN(r9c0s>f%L+JTQ zBPg5039W^}gnv76gw<4kLXRDia7fjIu(r>cz_?>a*p+ETh?AKUkiN!*4|+gC;16xW zu_u~@!u)lFBXO$<*r27Lx2E$!ZnINC%9lTbVlR&d1t$*%&4+#t+F|iAsO?W@&~)3Y zpr4mpgYG9i4Pu8p3Tiid5TrX(6J+0VGsy7#ji8U)t_E$v6b8Ko6a;PfekRDE;bhQ! zRz^^n_)w6G`~IMeb$f#DeM}0vR~8p^JY`D|JX{e}0Tu@>PDTWQo-l(ppQZ%8mxle1 zTnGyKvKA8r>Glosyyh8Xo&*o-!#M`U=);0Kh9E)fYD|N)(+z`uk@bQK!CFCCVm%uOnf(=b@$vV-A6dhJn|K3(YixT0+vd6gBcF5xe$09qXcF-} z(A}mf(0ryYaNtpGU_!>Nz)y_wKz)mnK@RgfW;K*NCVAo@4VD3?~Kzou=U@kyE@LjJ~;I|@;z;@-@z{8HK0s%9N z_?`D>@l|_&6JYiD7e8w8 zvo~+yXX4B8E$$`w*!j!&pAXLC{Zh{2C8!)cPbCv?|Ku?K^?@`z9-o5GS+@g!yCoi9 zdNc+f7p%lMGfru}78H9Jwz~HY0`{75{d*PQ`;P~;wj`(ss z3?Hx-im!NLivO|S5U=8|haX$ogfFREkN4iGiofi!g6o@Jz)e)m;NHdj!e!Zh$C-@` z;nJ`4w94NXF zN3txyar)2Tyw07(O;9p$$(o07-Oo~S8vAzRbUl-BlfPqe#n+>8_F_5in2`uq|CWn; zdW?Z93LxWXiy^q)TX>vTBpMeD_Q7p`?|}f0^m5++CMR`2z?I0GmV4i|ym4;!zGlQ_ybr@_; ztuMAj=84VLgJa209I&HtHdq=Mg3Wzpg1x!N0DHk!7c2U(5&Q3;I(7?u4Yqn<3G+I0 z9@FGKjX5^*69YRvin-uFh#CFShtW9q0i%NJ#Ju|5j)_0tf*B8dfiVfcjG z7?+s}%*TtR7&hSwrgHiM=F^2dOmE;ROwD8_MpAGDGm1^eU?x&9iD!3UQvA1LxMMMx z%{fZUd2b13=_?Q8k-@@X;ZzK)Ck!*37KBN*#b5^B_+rdsSAPF-cP%t_ba5nR2K&0zvfbRRR0jGBN z1&o<}2mn5P8vs(a2h43~2`Ih!IKYM45O8wtZb0+7>VS7X6#@79O9Hm16$Pxdyb!Rp z`D{RCWKO`-4VeMe6^8?o!qWnDCies!%t;P-1&B>MzJ0ucetwJrfmbo&5}S*w7FQ|1BJU5x{L-T(rwZqp9< zwox-+xlAo!f}j#`XXG!MdTd(wKECz;xwYN@-kKKwh`h)CAM6|a?V9fTGwId-+_7?h zL`sSO_~s)2 z_oUE&ERE|QtHAcS$GrX7yWIU>YB>Ar7ufnE>@59V>&*Pu zh8X$Z`lRRY9;M}BGI)g=zS@F9!=Ip%8XHjQVfRo`pQ=$XMFpyHx&-BtT7=rAc>#4k?<^`8nuCg} zI*tPP97Yv1??)|A_Mn_UC!tW0aVVRaXw=wVIVyd<2sL+#iwZDhpcJJfl*}~*(O*uS`9ZKR^o=eQ`Z%tCcD$xN_NV zmB)f#R>QR4AMAvmXWOVBg*xbm|J3KFEBfGff8?#7=hk+=?3rf2$GaZ;wXbUMt3Gts zZ<}VdpIT12Uox=7uj%|{zajJUegoHX{c7#9{bW@ceiLqo{7Cmx{f_(Y_PgAa=$D0y z^<%b1`OSyQ{I+)p{933SzqxLj-!ePgufLbzcTRxybNuS(cV6n{H~0G5q$>h@*Kb@(s!2YvEz zsXm(ZyL>pVi9YG2+k6h2M)}B3OMSo^0-u_FY#+!h)h8y3=#$+aYeCEk&KHkq(`7k~IB1vVlNQmig zTsky$pNV~WQ{yUwm?olG)6kw1Ch9M z+DL?&CUWg|HRR3yRYYcZL*(>k8 zfL8Ck{ZG6ze>8XtnD@LjA6I*yv9Iu6%q{WuRw?pkMxXZ%@5=Rtpt8L?OEbI$I)}WQ zcc*%54Da%`B_?`X-QDKBWESOp>xk6bf0FNA#%6m@H&ML-wnT40PLTK1LV)*mk*~LJ zE5f_N+0}dDti8ASij}ve+}wL@JIK2U4)EsWZ}xt@YJ)devDQ1ReZ`9bU-a@hH{-Ru zJmGa-I_3p@G3XWJ^x3QM^aro1g|}V>{B|$NlV&e)Ud#VtyrKk3uj(eT z*Lw)h>*GPD*S!(4*LFgvmqr=hYo8|Ct0M;Kwe-r}OWoPo>(@zJuiKMQFB-+n>rJ(x zmz}Pjmw5XoucS_OF9m#!m)of&&(BkTJmr)r&lk6Tcxq^mc-q8%@r1nY@%-!1?RoQf zhbMach38GeGta*zk31o24?JPg8qW=nD?MMDUH4R^T=D$!>4K-HXP)PlGdZ3qQ^!4{ z!w-9Ul<)WatiH!nDogTw-W2PpW*Y4Y*(LKd=@xj-x^O&iWYRp5V?@s~EWz{7C5)%} zUtdofhNtJoTdtn3HaK|3$gMrUH=285LB^iD69JwlUvKtIgKh96r?2%~?p;9~@mNIs z&YD4Zj7=ce0b>Yu!5{)L(}$P}{eZ~0`WCTzxedW!G$RgIHX+Wc)gun@YZ1iSD#YBz zGQ=L)Rm4F3C4{+NKEglxG{X1s2?WsaDB|_DbcF1A3gV;j4utLYcm%t33qo$DK#&tf z2&0!=L=%{Sz$K9oB`<>!BVZgtEeVBK{n883YvzVHmEeegwb~#qm_QJ};!F@`&w&UB zBOQd{R!zj$CN;z{eHFy!$iE(m^|Ky#wSIfN7k~HYzBA-et={hu!~N)?R@v#1vg(z` zTS|+E+SSJ%27l^3)CqSzy7O;&r2Q!K*ywl7BPpxUqhTQ5W62&A; z4_M+}kCJCQJXQm?d-%#@Jm|Fwk5DzShXo_Tqx&kuBXXAH@d+E^0XvQJU=E@@q^{l` z;rrb@3_Bb>noMCHK`{`IiaHaI$@K;vdMq6e{cD;Yv(suGHE0zNO4eWZSG}|DHnzXr z#mV2@cRd|)kJIjV59EJz|97L)J?l@qy9&0&opSQAds=V3d$!G8_q_?X+(R16+~+o2 zbKlP_bpKwI@9sKr+MVr{z zW;bGDliR(zI=9uUYu#*vs@&iwZnzn}D|Y*8c**UE;GCP*)l+VX-!t7FI2~~tNJw)V zy1&P*bvel`6BFm=d?ebfrcLGs)E2t2=^VE`=V)$w`-pBrbAp?>4CD5s)YlFB1L1bn z$<^&!yuF)Rt(Dul1+d!)66990SKlqLNz1KyjfR^QUe!&0WEppCQn;|72)@7P zJbXXsEL_aZhFcV5z@L6P2*(+v!mqJ+!AJ8F;2Iyc!Zm@B@LzNZy!tc`PVZ#GKWJ0n zKBQ21>IppjYMVd&h6WOz732=5A98~KeFB50sX*alex`7jJqB?0eI2-HP7@vsUkBHV zRe?V&|LYnwHtSkr`P+3x^xf6|;*hJ?r_ZidfRC=T897}T*KHcN$y`1Dahlq2{ ziHmmCDwDZx84|dbnQ&ZRGH9-CSwz>0mLS(y6^yH%x36nnJi>MPhKnn1(9U%W$jUX5 z3U(D_7`fU$(R1xy+~g{8UGMrfa*eC`oeu@6+EZ#oi+*AC;*`vG1IeuNYbGB!Pb9Uql=Y;&H&YmwHI)DCq&slDN+qom6 z!r3^p#5uU(vNPvrfpe%yt}{67q;vP4W6oR44>*tY>~+R%*y)_^z1_JuGRC5}4r z)9RePPC@lMoZ`O4JMGyV;}qqsa6(E&PQNm_P6zMOomK|IowypoPWf=GQ(c6gQ{zET zr_xGSr}+2wPG+mDoo?EgJ6VuHPCIw%J5^uSa(dOe-l=_ZjZ>xJvg3C2ydx-b%CY3+ z4@dob-yG%r1CIG>J&v~=x*W@CuN{x>ZgmVUdg3_I(%_i*>#k$Jezl{6Pq`yce9bZL zNTH*$GT#yN?zH2o#S@N~&5k-+;?f;6qf#6{WF3@1!~UrMPua)t4!f`WJG^S~c33;==3u_g$pLHy zb5O-W9NHu%4m;9-4(gY+9a0``aOmn=>!9;*#U5_7Xz%4YV{gHju>ZY%)V?VDtG(CF zUi+H1ZhPJD9rlcMFYWh2pV?=iAKCBb-?u04zHP6OS7BdTQ(|xX=CXbE&jS0t^||&N ztxnpT2OP6E;vca8vvaTg{WCl4g}37E$J@5pb4TU&H`j>lM@_l*YTk5vb$Yn{uWbbT zx?>po=&Qc=s~QpZyFR(tf0(heH`cPU$HKt&WQ>u008h`}FnN>xyOZkn2{%^TFFg5Y zC+VBByEXUQZdhyFZpmiY?k~FEu8;H4u6TQ=9r<{>-Pht~J61!J-R-VAyP2PN>>#E$>~uYf?MA{b+Fh3A*`ZQ$?4F!HZf9S9$Zpq@RJ+PgyX>A%CfGey-)48sEYfb9 zhs4e}jAvIVVcJ>kBHN{(46%ED4QKbW9%Z-q*30haDBSMZvV&cko{b&U*21nFWo&0i z2iR?i+H6<6Ps8rm=mZI7LavK=Uq+8RIL+xoS!Z1JBdw(#Gfw(C|0+BWKL3XfVT?eVKm{Vb} zABBN1N+lY0u?`7))8Y>M-sJ@Q{uKu6_yvJo_-6tmuQz~=>+8U_SZKoDIjX@R$W<^_ z;G#_eb;c%1FkvHz9<^~!{%Z3rt=HzjiEf+q`5iV1S6|pXuX<{;Quolttofde)!S+t z-M(_0(UEI5SEdSW@JsnNuh*TiLFr`KoHagb(`A)zv*?^+vksYTvxtqe=^{qkJ`vt zpC?d$f! zT7rCP9UJh_T1L2MjV4uFuVt27SMjb{W2A-F4N>{lW^t#jmB}Zp&!rr(u1-(0zI}9$ zbwO5=b<~+yYx9CA>&8NKC=b!{2TTJsjgI=D8}dRradI;GLyI{ulrb@&T6YrWTw z){UJu*7Oe+)^B=^tv$W~tkZ@!Ti1?hSik+LYTY%tY}GV7Z*^v2%8I=7!)kWbh*hfU z7ps|dJyxU*T~?`S)#=oezO zh{9Q|L8Gi@(Oy=s1K?IU7zZm~thH4K*4!!-2ePWd>02$~w5;Ix^;Ts38Y?D#$r6wM zV`++?wET=4w>*p+wlu``Tb{yxw4B3qTB0%SmPrB4mO1Dq%RK)&%R{I;mOQ_kmL|T} zEuSN=STemYSibQ*Yw3o_woG-;u)G65X!+Jy1w z*V4#>Zn@Vi+_KG>V7bN!V+jHJTH5O&EKRjtEEhJ~SvF``T1Krivs|TWXqmc7*K+iq zrlt3Snq|W5D$BgdMd-DkGtl#66VN@wqfqRZuh6;PUTDsTZYbbg2lT+}7to#;Poc)o zA42g>_n_?hYAEAwITTra4Z5MC5c;$vA1W_84V^rH0xCay1o|vH4Z8989;n};Bq%#I z7Ruih1r1G*LLpoE&>;m2nkAw@q1;gDWf~s3p6Czd1bRcy_`5+LcsW8_Ty3C@b{5df zP-AF}2>@yV*bHsjqyZ(YQ-#*AEI|zB|3LV^Cm|JG9X772O)N0 z`ylr*J0Z^A+aWp5F_1nh1w_|G1cB>vA%5%W5Z4tVM0+*}^67g3By+$AV%zNjseb7U zfi~GfQfr}*<}y>re4znEH&+K@n4t+-pQ;8KOjrdeja;-~@@Fh2DH9fnfuj~f$gdW@ z&b=0?&~A%LgAR*k%@-CgRz0=2H`8Eoa`dhRwfB~VN=KQ+xhGdGKzA=$9KCVQ;>(3o z7Le>r3-W=(7Lm#OEw)7MwqWxTEnG?4EM@~DEsESF7DyYO#X}>eg~LX&#i5m8i`Gf3 z#r)v^I`M8#3qXsjh1vsqi-9sLi>nvF7K|(-i^)_yi{$uC7NZh%3oL!LMF#$#`9s8< zd5_I+^FhP!=I=Fz%h)4{cp2ZE zkk2v?IZ842+!1QNS%EiyNB1{Bfb}*vgS(kuGj}vM*lc5-v}|tv=m*Gr=99j;UaOWl z`0jdhgR5)I|K==#U!?v4AJ{qxwu=}CHxP!w-iUs1G4vyNLAw*|z0wAj|9B4G_puS2 z{`>)W`|TQVcwr?Nm{|&bv9kyqB|i_IrR0LQpiY8c+Z_X&8XN$#Rri8Ze+7Q^6uh7pO2|V>4xTNau%H$G>5-btC;|wr@U~dDV5AxnFHJ zGs$W;o7~Z4RxPeG6NcU~TX4T=mTGq0Y)bu#8D;9c*@d25v#zHn%@!+;nQb_Gz-)c$ zUb7kH4zm~Jc(W7UTg?0*a0taQ&;p4({P(_rYx-i z)9|^ErmlURrmLT}n>OBPHjT<|GF`o+&h!xfj_Ex1rYXbjx@nR271N$S=S@{U=bGw0 zJ!z_UMqA*k6!-1x} zEojq7GSXDy;cglXaxyht1v4EOvM@c_YHVs>2{5hA*=*{VtYLbJt7`fUwQOPqoj0MX zPnm4{F>aFFF>JE6rr(5|_t6Bhr_EUT>0h zYK_To!jiEqOL5UoqubrpVDUhg7@5bt6!tBirE9> z{VTVPfA?1yhc%WMpDVm<+?iTn{8xC!SO=YD3^YG#tf7)_{9|B`aeZTw@$SM{W1G|{ z<0k^CaTtnk{M?jf?66EWPVWmbZm!1}FBG7RLA$+-?Kp5_n3sbwz`)vgY7T5%-(_T+ zSfgiba%z)tO`N*17iqO|h2uYv*2X!IaQqkOa_boAb;%&;=fOVEqU1ej7X1d)Z}t*& zZ|Ny0wdWxSasM8uH@6xTmrxFxC0_$6oC-lLn)x8Z@25bl=1kDx;=`cg{rf>x{N12( zWFqLS!8TCrtP-h8abXAx15>CPn~Npb@oiv(f%q4Wo-$sz&9?Wy9;}dBa?zDZ_;6aYJ<5 zu;FrXzhQaGM?(Um)9}4xyCH2|v*F|ZMnmwu2Zmcu)) z!x^UMpbXDOdKnh@!ws{54u%O6R))dPz=oU88yP;2*E5VEY%*L6RyWL?Q!!L)|7)=A z%B(@_&R+(4q%nhVt3iX^|9TD1zU?+BF6}TV+WW#FoA%To*7l)+|EhZiD&4mXs>{j@ zX#1}kj5016MBAS;7*IK7fPa77;C%TZgQ5MY2FA=?1~~f!1A)p`gQ#wWfxJv)KuzTu zIMe9{E3j~bN6SG5v7G@1I;B1aSNC`rz{t)97cFfKR2Lxz+*c+B#YI4azNG&J&mkKO zpk`|gT&9%!uOBBiH1(#q3m|xCRsD^h-VXUdP5yB zyuSu`p}G>-d$1I^kzE9IvOfe47RIy?PXAxg#C89Gn7dHAw~@`W*{|KZyc% zo{<8jNsVE56#fCTO=K-J+F;L!3YVBz&wfZ%d3pfihQr0;+Zb9;9vu zK*%wGedY?lt4SeX(_;<*okIi2#Y8}gYY^bj>Ht96TO=U1$Q?k6cLG=hzyKrK5WvMR z#(n3Y&O5HAH;&`gy|=xWN*PHM z8d_B6`3NOxYDh~AMe+>=h@%!Jon!7 zea<<@r+-#!AL&pNJZw`_+SRP45#6MwJgZTS6>m^`_v(t;se|X$Qc_QG{sFtueTCHqCnA)+v0JRI(ebmkt zyQ@|EI;pMJpRcxbkWrg>%S!FtW>d8dfz#BcPn)dPFg#Apu~9?qR++MzafqziW+QR6 zk0V0WsSp0DhHe{BEeZRfddlRhYJ=c|YU9H+S@pUfJTSdN^RQYSC0@)xbe}Rs9C2e%vryb?Xu{Rf|b8R3G)}tNL7>p!%Xv zOV!>(RrQ#*yej9LgsR(lQPs@_BPzES4ykmj{#4<8_@<(I{G*C`##k=TAvWlKno7 z8>u`Do~jaVsH@UHFjgh?hMG$ES_Ks^cPW+gnj95g*Qm0~i9gCk>A#d~Nw@M_iBHOd z&)zAE?rK%$ggsXtp7u!jXr|%huK^`@5Y}9;0zW`QC>b<+!8!lzAyTmCLND zaX6clH$Gac{9oA$4Uql2P#$B?FK1N}3ucmDr9$ zN^Lb&N{8ciDaD$VD^32lN$EwyI;G5YE0q*obCoJp)0K4F6O?vWM=41~g(}4v1t{Ga z^j1>7=BDJca-mYmf_X~UFX(p_39}7Iy*+`Wu}tSNk&E~ zkHb@%^MF|7RjXI=+xyRoSvBt!*_hXg*(NU(yN8+--LEw&o>5Au8B`We4 zL@V0KhAIAg7NB^f!bj1?&t38BI48x-u6c@r!;E5foRwm)iK(L3kfGwaD|(9J1>+Pw z=4vRGiYqJLdnltgSi(~r<0(`y8S__xwD&8_-`A^vurCTGQ$8qY^t@L1bLxe{!<5Gg z6_)oDy#F;Q$kts|xVrL!LZJOAh5savD6DI$R*>JaTVaD|g#xR-St068k;47Gs}#nE zt6E|Chif+p9}gcZ#{89{z_M`yz!wg^1Gux z$g_rTh@|K(}4d}V2vyo+a`{DA5b`7JH(@_IX*O zW?bjViRB4ppV|DC-8RxM>v^qLRx0<4>}Bf@vVs3z%Z^-mAzPaLSa$sEd$Kjd4YGQ* zS7mo)UXYctIwhO*=dkS4i`BCF>APjq%`0SY43x+U&K1d8q^y#SFwK+Q{EI$P_H?4` zgM?_=_8DQapL+vjza96H?TT@iZ830?z4dLL?4iSq?CJMT~vXeg<%J%HnlRXwP zPBvtMhOE+iCD|)`Wn}#Vc(MapLYczX!!n9H`en*|dSw*UzR0Y8@m}Uv>1!Du_ZKo3 z!cMtR!aYq%awlrFirZ#x&-Np`BBmlqM_2Jb^g*rIo{Iet=yzz2OXt# z&d!y-A8#uiZ)hnk^VL}TzySkki{MGpH??)79bT(TH&!T0W3jaKS$VGXxJLr1HS7M9 z`aJKq6hwNY%C3Ks>dfkpGO%cqiv9gu>hQ@&Qg5U0O3CWiOId!bm0DVPPAb#ygw$sB zLsC`E`=m~k?36m^R3>#!e3R6PTWh7N3sy*Nw$72t`jaZ?<9XXwo1<9K9?-3e<<0Jb4OCovQ9Gm z_hrd_C(cT~j65#Mom3-f+)*j%y>o|Ty4P08EeabYYaSL#UM%EG-kg&y**HQUH+m^f z@>X($tc%_Yxqj3jgFrbv?PiISsc zV(&$Tqj~qmV=QlpPyKaGyz}Tqar%T2@dY|Z#RpsVi|^gCM|`f+Ht{ab z7V#A~){ARot`$={K)`MT07}Z|C>{ zUQ1gqPk!qc-n>O0c=z_Z$amFMYyffuWKinrqNVcyoY z)x0X~<{cX@=bbxS!n+t##Je@f_bu^CT*`yxT4; zH&1++JG1^b_j6_sx5DHzckcHNZf|uPx6H4ZYo*e}ZF_W=o3W;ztHfO49vwQzC8ths zpVKEM1&^=d{%GCF&D>JPWgRzhSBb9Ua<8u7u1d+_vW98g%&vHD-|k3mh*t==S=OIx zch`%1BHxv(X6eYy>$Bs&KV-w5v&@3KZ;UZ_~Zkq9ATX~XD>N$Y7^#gZs=Qc8am84H@D5;G`LRT+z_A0xl*UaIhUcz zIcg-&+4n_)Q&uU;S>rPzmL@+W7S`A&=2q}c%-Zs!m~LOYnAD+HVm||)iZ!b}5WDdB zmRNb=b+J^2-h4E4TFmg|Q8DiF17dHr_lli+xlL@{#w}ug^NYo%jjk3OIiD}~AU0EM z+oWW%(DoRyX=UMJgHAzW*Tj6qR$TQEo1d~sOv2D!?0zQ^E800rY=Os2F|O2fvHFI| zVmVpk#mr1J#d^Lfi&gKF6FrpKa&Ywn3Q+uRh*8MrDs;rIp7yP>BN~LJy$e3lNI@6G%T|E%Wn~d${vy3 z-k(ME<=%^&xzi?Mo!2aK+pI~%x#zCPtNryNfqqv+J}I3SiG6TFq<_UBk*rx&BJ9td zB5MwpiAXKmBvPWjPDJ_13X$!FIU-t2nn>kfyvW28ks>u=AtF=8`imTE_7a(1>?(5F z&QZklubs&GGd3a?Q5GVX#v6;wYMm-_r9@Z6#z9-;xC}{vH3P18hiM-7sJP1V@h`c9_%i_qIT(ALfKz3QgL&3a zUpxzO6D)E4s~L2Tn4%`c7}2UTu&Tijyojlg=IP_;-bwgtJQ2#*$3b?kHbib|Lc(?o zW}i{TnQ_WkvrYlex@B?FQ5u%j5?C|H#o4)HI5$Q}W>ozp65|I+c6lGUEb^WF3+p1; zb?->5VjGe2YbG0ZHxYwZjbxm}O;Tlgjr4k5B-Y8N$(^-F$=!+rB&%{S8B@KTyxUt! zBq}zLCu<8y=a&NFaVdpF~QBx6<| zbA@@u+_t{XY&1E*NKYtcqE$l~i4Vri)rBLrmmX}hEmC-3BNXy6MCqj5q3of=QcNh_ z)Hilh=21Qf_(-J)M)}C6^pEfnM7jBo4^2wsUp`I@Q(yXzk1-VThY$ZDJ`$*JWe!mK z`H1_?hwm>wtbg*M+(+B&<>O!vZKs9`vC*nfwQ>|1;+Xy8Mp zj*q+7_(;FP$Jon!T)x1E(>XqxPxIk%lD2V-57Q%jY^AS1|Gu9Ot13Qn_VRII7ayOt z^C4ZqhyGSRW^d-hZX+La*7IS$mXGnP`4Cybr~9e-sLAFdI)e}0RN8JLA6apHs7CW~ zcsU(^C?BVSXr4bGo0jm==gEh?J0E4ve6%?7p=eLrwBsX!;bYZoKFTfV{4=HYn8C*u z13q#m^ARwS_Nl{%s3w&~l@GomZC94cE5S!HhYzl>02}`mK;};YR{SnNPj3O7zZKwM zR{{Dv3SjZ30Ew>(Q1z?;jgJb@)mVU`n+0I67eH{CmN{2|j*|swI8uP^2MVyfvH%7< z3-GC|0OchGuvuS#w$%lQEhxZXRsqsd3(y^30Q#C;Tn;UOVqgJ+mK5NC2W@9j0Tdhx zU^%A%p4J73G%rB15oIdA2JT-^ATizi=m@v0*i&98ECw<#B=Z|7q3)m%iJ&Be?kxfrU<#i@#11Z~U( zcXckRvT1r!F0Mu7!a6V)XFPK;)+rbHb8^vQnG3xcxrm;Wi-VfzItRM#~~XWn{2E$&c@$K*;uZTjr+3M zm?)Z!UbvlD>E^D zYbF8;GqE}=6IHR9xDb?yI*&}$&(Fjqt4tg;%tVn+Cc+dmVb00K$WR8Ze9J&Wdj>S0 zWPrX>2#e2W;6qIYmhZ?wXK@BR^D}TQF#}qm8A$Y^pB*y5&Z3)ur)3~QCj%Q5GH_Hh z1J?)AarZN&H67O6GX%MSTgU!)2#O_MN)(vSmotK8&@o9J*l!hm6X}CKl z4d+eMutS&DQAvY6Hw|(_sc8C~id8MCFuIqD=a*9vb0ii2cBEqE`c$ylsYr=Q#aq8r zkVUDeut~+IX{ng1or-YTRBRhfL49uuI^L#Ws3`@aH&VbmnF8US6#U$ng4VngT#QS> z`hXO8Ij7M3U{dgOS_%rrra(_7g?c_IYGYLhYlNHUIWPX>2gGJG>_ZdK z=azs?OadlNOTZb81el8_;M71oCUnN5=t(@jUW*5FG#2Z+K zjKelw9JKmlQQi>?@kg;pyc~-s2VyaKODt0IVsR-d7Qek>p=TEhml?5$*Nnv)UMxy~ z$6(vL7;JqIgTjk3NT`m1+ol-kXUAYDJO)?YV~}YZ1H-8?c%>493}H0nd!kX<5)Hju z(WpKd4fUPTSh*$|U5U|P{G+kSAsR1DqoJ%54M)jnqzy!2dq)(`J&3~X3-mYRz9>8@ zj>4_)3MCS1d;Xe>u#fm!os>aunJw#{~W5IIplA%-?X__!th0rf}3; z42R6Va6}h{qb@ld(*EIanIDdIGs1C2J)Hg~3xnwQFlaW1Val~I%s3bZ!%blrmk|c3 zWnt)D5Qe)ZVc4b_hGk+jy(bi}UW8)x^-xT$3B}z_p;(#`icdkIh@f{2e=rV(hejx_ zh=fA(dk7MrhoJ6C2srygFsC>KX(=Jt=NE#Tb3@Q>7=jjG>Rg=zSQB_H)6w zxhoiztAddl6AZFA7-H7JxIQr$2~xq(_`M9ZZOh=%unZp#FGJ+!W%!)24E{mOaNm9z zrq5W0BGqMR9|?kfR}i8e2BG?F5Sn)c;U7N;T9H98bqxY6f?%&5gn67GSak*qji6QLg|5 z+XUd+!~n=k2Eez^AG==q_Lod;zA#tmCxBgsUa-sd zf?1#!bnLt!)bqk?NiQ7h^+eh;Pgq>=MBjE#ROWhO!7@*Lo$HAe`kqjf_QZ}Ki=pv+ zF}7S-4B__0h|FD##-PO*H+M1OCojeY$;BAx@qpn|4=g?B0e*!CDziLr(cc5Ni3c7| z^uT?t2kO4M-VgA~!6L zbwiJf8=_6z@Lt&sE<>(3-|7nGtFDOJO13)gfq5% zUj*Yvi%@@J5f+pz!u`ZWu=7}ibM(H;v8s!ZH{^s@El!wH>xAT;^#5p%6MpzRVLamm zr*Te*7cNB6hlSXEb0H4xUx;I?=`nmEcG)k)TK$EHl~@SJZ;sG;;E3*{jyO~7h=f>2 z=s7#$#dJqx%Q-@$ZvoCcSpb|~fP0%4z%gk78r&Da)N}!MDJ{V0ZwL4^JK)GU2lQ`s zfJLeU=nHLd(98kPR2(okU=O92_Rzmz53_Q6%uch1m6tt?%-P@&Vy*_JZwsu2W9tp*kU{n;tKPS);AaJ zkLSYXTde{#3YwfUfxg8?r+aYd}9b&}n z5YjmZ?hSJ=Yu_Ab7R*6^z#QDMnS&CoIq>)k$hH9umw@;RK$%`8!R4U1L2@GYMQMv z|BN--H(4Vt)*3^O*2vViMnA_I%R6VIxo$SB_RK~__H6X}%%%@ zMo2XNi*!UJUA5laf(=_z)?e}CXVT2Qx`|?>!Q6{7vj0PnC7Jmry05k71u@D`-xalI}vM3C!#QBA`0eB zM6&io1Px7q{gVlpe0T!A)-eGueJ7yWbONHKCtzCFczn4w9=prO!zq3|2JFXU+qm(V z`QJD^csdSCkBmdtigAcqIu2h<$01O99G-sEfz34?RF~;MBu)o@^L21iTL&Y9+L-%T z8>?%yQJ=4kL2qqLGSY^#xHb|y#$wZ@u{c;V78fJNqJfOXUG=fJ)2D^HMlGDJ)Iw#3 z7S_6IAyQupb6HJjv}oe%NllzB)I@rqCd@1}(Icygy`MC&@VW+mmT6#ftOg9{X`oI^ z11|kz(DGmmmR8ea))=_Dk3s#EF_XexFpwqC$1-3s6U&nL4aw)RFU14VSN| z;pY}LOpH>43)GORu7C$D%k6( z0=}UN{6$q@+NKP#)5>^UsEn-v%2;fs3|VPq-29+Ke}5}cA63Hja3%QJC}BWJ35DMj zp;E7iT@{MZj#I?Wxr$KKRK&`k3ixqX0iJsla3Mtj3JVpme7piK4#`8LNgnq5m4Cu*Y(uf?KpUWZnupBn$%i*Y}9BvrM;gL`lFJH-`?YJyjR?6b(5?S1uA&WB{ zS?qW%gS^u+SXwB9nf@~1naZG9Tn4+}N+al;G{zQ5<3*q})|yGfTuK^mJEXwBAO)Rb zDO_A81xE`hv`9-K=z}D^z95NZ8zj*dEQv*ylDHxx3EfT!ti2?GPa7maLL{)&QUV`j zBw*Mnj)Y6%IJrR_UxUS=Z7B|C8F6HM;9<{291j-4oSif285UA966@58-qF5cd;9WQ^Ak zc{MUfiVqADi$#N^wSRyl?iwJh-2hqhy`PAb_LJ0E{p8*I--KEBo0J>n3Q#sXS2IW#E0)>aP4=JHG>{sd?OJ#-^jBG--zkGucRpcD`{2vN_4J% zA%4MMNQw9ta^=Kl(!TgJ85;gXc>6vPIr~pUwx^4Tm3EO|mR;o4+mGbzs*hyN)Q`mV zNheWE>m&~}J4sIc2covfh;-mo_zLxPhv(o$k(b4;_uKw?)AJQhNbVw8q0U2 zrTr}#zw#{!)_+TOJZdNRliJBIwRWO#?G2e6{DzqE-jLbHUK1;~*JS!&8`0R=Mz>?M zk+zSmpv;guNo0Bwvy7Cts2y9xsW(pBH5Rt`|fF zFGyZjGkLqNnV3&+CWX(QlgDY#iJazhVt?ZqNe_8O_VS*Q8%Lj#S1wP<=ig7rj|$4{ zC*3FCfCAllSksW$;+d+$Sdbt zuzIptyq?$}ts_H=>d4-{8-yvnL0Zjjkm#1{WH9SG$)tgn!5h~|bnrFOB6f{1HCM^r z1y{+?_bbF<;}x>S=n8r9td_{9){=Q@wIu2CWwL$gWpZic5_z)s68V5jq`UJX`LX&U z`9Ap~>9}`+JdVCVF34OUlY&?U|iq(0wNn|Gk4Km+l}MraOq{^X)_>c{`C* z+D`sEvyFUk-$ri#svy-{DoD0T1zGg0oQz2-C+`%>N#*G>ved1NDE!PxngXrrw} z?nx;*5noE|EUc3Qw|i9pt;3lOXqrWeZ_jxHGVze))$e9K}BSiU>#Yw zXC3jeSw{ljtR=zOYe}HSTH<}VkSy>iBo;$!h)($$B4W0Nynnu$)F!Pa8x>X)|5K~T zWS3Q>yJsaiR=kodH&{u=-d{nQB36(r-U`Av^2w^g0&@LUKKUWcBdSauG0n*(_Lp;r z+h8_vGtDLr30cJKcqSS1Era~l%OE#H(n(Qe8gXb(CI7~xk{YiRvY<4XynmcT5~P#J zphF@_TAe_;>f?#)XdF2`D~^b##}ehpN}uJV zXlpoG_auzuNr#bWhfw0ODufu+1(VUg%SfZeGO{i?h|D<|NPd3{AUpK}$gE(0@^rT! z32I$RJ}ECHp{~B9b^Q`D|E>=?D&j-LZM}(KrWZMM&XaWiSWNT{78Ad453+WjJ30Es zjoejpBd^_E$)^o2kn9vL+{MV^)cq;k%t+1v0)~8dDoOY5t@)&vrWjU zRAV}yjY#U(8N_+w3_@?QCEv@ZkyB3$NvxzHnKajcyv&_S3NB6|x=(LOQhFo z5&L>gl0B?Jj+knY=P_f*-~n}_^iGW!sH+hhH&wErNQJoER3@(fl*mFeB|_p9iBXLL z(ddvT0(E)v)=iFFDv~7|Zpsk9f6_$HOqzU)l_G}^N|KOw5=32Hg4}f#CyDELM74oS zE(~+1k8#N7XfcwpUzCWpi;yA}5u&<-W#pv<44XZ|eD40s-0~l0Dw_T<^kpE-_)`N+ z%ea1K_2ys9RFR*|?W7-!cV`dN;nB?m-ulM8ocWcRd*Cy3SmhJLS@V%uGWdbnAO4>C z^zt1u&i*aqcJU39HTgBOqoS2L!)sw0(qA(7KQ}Y?yq`1mcb_t+ES@miYMPjIwMUFg z;R8lz=pOSqypcKd@(#0X{%uC_!cFGtqy{Fitd1ELyTNQsxyERIyu$4BsAY6+UScXt zE;78T^Gu?`Ii|Vb3^Swe6tg<;B=fxKIHPHMjPW~ugsIRv%sg0M!~8dVfEgdPpPAEI z#rQkyW0EfJW%zn~n4+>>%m%TYOi}W7hX0|0Np>q|0_(Oi^JbJXllE+8Sm_exW%fqq z;J0EXVaa;Nym1{fXug&?eP9i7E|I#=Q4-qpziL`DrvBFVaC{;;noHdI=e8`>PqqLgF zy0`IhtC)}Y0vfAM=A$=^k9u!D1|9g=Xhmc9Q)nDroyPllbbrYJjZ1eH!2C%8_*V-s z<4^&ZQo6?^w*W=U3vknw#)7RV;|p+0oTmNA$GI2zm~$l`CYAXpTt(x+5&2lUFduEx z@^M{`#(aO~;ndSS+&E45rfklGWI`V1JLloEK_0$~=fSfp7Zd7p;khdp-D$b_>Y5A3 zskx9Br7_aiG&XrA2RGN{Ks$)WGR<|n~k??vaxGPHtG$s;WUy3o2D$3 z?a9L8xGZGaWPvN4h5uSJ;Zc(bm6S}_l1wy7W#Z1u4Cw94KyOqA#?H*Z`G4s+e=8l@ z#p(Fro{lMF((&MJ8eUbWVPQlXrWmFn;YTXQpGn2+lvLE2rQ*b33b+?ja4#(dgJvn% z*q@A&Gszf9YM&|d6{S8rUP80LaU-Oi9qamKyjMUdhz zLKAlpREnMOR^AB)Wef37eIZABi8I&fXImp@MOOOu1#{FF&%pSRnHzZ2j=6r z?tILmFNt;@KM&vb%!Q2BTwLB}hhAkn94(oHUs7|>um%__BoJm1B=j?gjAhWGSg6!ZiprC4N&W7fHP;OVvg2SM6H?v!)|@7@z6(R?PPGrPsa2@J@j=?!Xo!c zn0HYZt(x>YRKY|vcTRwf{RG$@8IRA>+8hnFP;eJ&GeQGK&NmhntlM)W=E8*=5 zMby4gfQ>o5CbCH$v%bjTJds1|Hd)m4$w1pd2FzY*NDb2K6;4v9u9Bqj8wq?{Bmwzq zaeN%&A=HV7(n>Dk`#Bi4=V0beF=+RS;vx}+aEk~A?h1)hG)uU$0-}3rgw(kGBPG9v z$=faekusA% z{Le&Q;}f}a`XlLc=p>uoy(jxqJBX3gJ7QYdPEO8zLk={y5f#5yBItcZ!uchx`PBAwgF zrr-)v|Gtcr2W=&a@3xSc{+r2Y+a{9Wvyl|PC?@Xi>&eZgb>zL{T5{~p8lpRAHF3JO zlIU8lAU+}a<;Kb6_{0QatP)Ffxlv^8U^of*6he-?2qH1J{K>&H zzQniEo2=ikn9Ry@Baz|GM8ka{aj|hA68iJVLd7{m?Vl})>zYm6n=Hwl3uffO9upF> zW(L_5Ye+m6Pa!8~>5-ao6Ui*@I1>9^i!e{dkaOo$Nz*nZvLQ#F3Yniy(70ma~X-ueJ6yyBFpE+&k#*|)| z%Z%zxk%0J3~lmW_5N;l;brGwH+c}BTUsi$0`oS^KdY@=+T z6i|{W;S?Xr0*V!73S|t1M;T;==%hTMT%{bMlu~jj%PFoDE6R9^IOT^xh!>Pv%3jJ! z%5sV$Wg116@?(^?M>$2=M2Vv~QKnG1l+F<$u2Z&Ck|~QQdKAGwAzo2VP*zixQj91Z zO6y-Cj#COK?i5|hz_1W^C}or|iYZ0-pAe5JyC@M9Q_AQcA?{JOP?l13DcwUtoTX$@ z2!%trKPbdTiaSMx@@jyNk>X3yptSYVbBYf|mGbi} zqDE=z6Jiy`iqiW-h$@N~MVxY_SBMzOSV~im5P6holsDZ%tfN>^K7OZtQD##F#S2nEXed({6Z`He#Sxl8p!`Eo~yK+4P8 z)Q*(;TSAyqj@+d7pp-NSAwo&1r#7e)!jp3A1|2)4>N*`4CHI;T->y=7QtGb=VMr;j zrSe{;I;1?kMD0$gyh!_}#9W|h=V?Eb9p|V%&r(03G@PMwP*$H7qU)3p^Co@S zl+{~>cu-39K=Ir{=f`I1wGdrqWKiRb#$#-OUF=1 z>r))p(DqhSe_TcFzfy=9l;tag*u$q~3WSiPF!|ILdDMS$g?ODq{f$DhsefhBwlnFR z%%J+B7^hR6rBQ!NrSmI=`c<+JN)#rE+9XkktqD}0@pLZ5(KaaNu~hCDx}HT-*`uhh zM+)&fg3evatmQN>occ`|wP7f=aR}96FkNew(fLDRf~YKkbS(*>y7m|1j32GPl-k0V zj)kJNgw7uyy3Tpib;?VK98bCyEv7Pf&@s5vb=-}P!O>qbp2gO zVr@pWvJb4h3K~t;;%Iw<7~Rl zQ>16nIbcQC14|*)E$AFHr~Yk5`zXQh5 zd8RIeiyGCJsu0svs9uz*O_ivv73jF-X&Z91zN`=jWvHJ@Q+-NNpOF+|p#=3;aq9a# zI;S{PS7OxXL}@=F)Q&lf|VEEQ;Q< z@b6$T{T=P6oyFrfEcU);5!c4Trj@qQ!lLCRivurMBsSCf&sp%Ev3UA~#m>hpLYr6^ zK4Q`TfW?*jELPlOVc*Eo{j9XiZ5Cy>SS-28LaTwr+d3ANH(1bj=3@Lc7Vodn^I8@G zmudbb7Ht<;l%HqeevXCgSr+$BvsihGj^iYY!Q(7W9HTNEWij>$i{?Xg>@_TygS7Ac zEDlw(SXxEv?PF25mqpSZ787^Vayw}oJE%Uk)BY-0Y$~TRl(G0)O2@W^1vazj-bDM| z$bxL3>FZf+E@EM|jzvcyi^4T5rmbf2Y$dhJ3Kp7tYKMFl!Fepia;eUkm}8V#hEEAjP$Ag^;j58Vo@`Z>UIM4#c?duby#c}OUI%`$E(58|D!BY z)L48|p>|fLGAgoIs6cflN86I6`jTcbMv9I_f|lj6h~=_q7h~ZhO8rMDz*JU%ictZ? zMg&OwE5Muo1aSBxz?ne-v<3uN{ab+Ep8|OG32?nvfJr?9tp6^+&#yG?ivYEs1kmmh zfZr*=$M*uv?+~EotpMWf0z|wPps`he$t|>(<%y#R4H1h{!k0JW<$y;gu5mjqC}C_w0W0nVQlfP03H zOy6A7GSOuwT~m!or3`M4I${COZ9F?Z3UXn z2(ZJ3$~l{sw-P|!QUG&v0sLkPz&8=#fDx@TosPp$09gY8jHU?SHd%nANdjz{D8T9Q z0zA>7b{;E$w3YxBP?$0%~&j-v3*C`#H!v8`nkl`lu>9;{Iue>RG`i+>a- zuEi7L32{$|y9;r5cX#*X=1PEXe$2BwXO7J5m7O{2BgVZ1o`=A96Lc#ls%1-S6SZ-5xgI>0!~W9>(4jG}n8my4pkH z>M-NHcda&Ojp4Bfs2+I>cZ|Gs%`W~8p66;E8=p(|QP-(u3Bd9?nnbVdc0UdXMQLbz~1F!^Jv=inR~!q3=LJ z->(P5zCB#*-NVvv3c7m~gvb@VlPcIJQ82DkL4KP8^A-hvH7QuoprEltcYLXOKB`7!@r(jZyg7ioQD&Y#Yg(~O? zQs5P+;F`aJnZ63Ly%c=#Q1FYJ;Nz^o)=|N6dj&&m6@0cCJLSyDOhNr zAXitx8yy8Jv=kJnD^OAu^ZFp}--~s;Rj~ZE!1+(Xi{}dFJr%T%6x?~BVB$RmL3b45 zJ)_{en?lxg1-q{*Xt*Ti_m_gj7ZfC(6>~eSV9-f1eq6!!qYBFYQ1I-aSjz!1_r2md z{i>jLmxBLxD44uWfyZXS2L+`Y6x>@c=Dt=uzt!T|tWprWT)~N@3Yr!vc)mcvsCf!3 z=7_n^QV=#n!TxCqiYE)16BS6uiFJ)pFmjXv9e&0o$BzH*Gc~vfs)neI;l2e{wvY z$(j5_&dY~#>h1|%|H|>cC15w@Ji9KZ{EEotc}b4lMLC1d%ej6=PSQy^Oa7FLm_0d- ze~7sr6yy8l^xG>JdO$hBI|coAId`|n#eP`M{Ec${TQ4X7Cpjxu%TZb>%(1c94;1E91LQ zGJdv{aobFWow1B!0~w?BWbD)t^=>p}xTwh}{UBgUGPb^z@$V}c)-PmaK9$k;v5XZD zWSqGxL*=#%znd~~7LqaIs*LrQWL&%`L+zXl-_tTmPRJN=T*lHPGX6Lucps2qwpT{v z9vQVeWenXeW7!rNza!($1{pf*WO%I+a#qRcST5u*m9c!0jD7QET$?N7-7FbaGsL>5 z%E+B0qkX)LA!B9C86{)Ga3N!ejH?4>{MS#0ZXcP@Ye@<1k&-EsQX`Qf?~pRIP0F-p zDN7rqP%C9$m6TKEQm&Usc~mInU7i%3Y$@g$Qt|GQ;*%sLEM7`{jFgN>DTQHDDubmo z1WIZ5lOpw&^2I|+A2%ueouv$RkTT3x%1CP|qb;P2F_kjbNHl$M|53oSq>NIRGF(L} zzS~j;zLko2KPlgyi}^i~()mzI(>*EGcchg3BPIKWl;o>YA}>h^xG2T-oD}QRQuI$q zQ8^~%`C%!y4obPOUn=6Nq-@(Q<;NXT=4=(Rev#69qm<@#QW2vlC1#Zr&*f4~mq<}s zDCN#PDJSPh**;UslIc>$O_9DALs znY5d*u5K*ayLr*l&6&n-Hr91Bxw@O~@@_Ipx^XS+MmevWi`m_5%IIc7YB#Nk-NeRq zV;0@by@+mp3+-lBkf8DJ7JkSA?%B;9w{EsO3w(!e>TJ3Ruo8UCyZO_kn+1jfSGSue z?QXO*gk05b7AXtZ+it>Nb))j4nh}&FMpe=0G>4zjb52Tkze{&GfC^6w!^*hHj3n>t^hlZct^8SZi0q)b9+cPKMd?9|GREfdw288R|#!$ z30B<_4s}ZC+a|%YNy7Ph2_tJH1XoD7Rw`j)k%Y)R2{*GPOwJJZDH3iZN*Es}AtXw| z-{BI5he*VGQNo{o5_)+{uy&WQ+eJd7gGB6wC9JfTkYO(2u8D+kh7!DWB^=h4(5Ws# zOGUzRC5iA;m2l;ygnrK@m_L^A^8*Q4{|dRcB*OkGU{@uqy(A&!f`q@$N>H4Xpm|)v z+#?eF4@%g(Uqb1x5^nF3@ZEL^A2&<*VUq-(^%A!KBoV)52^W@2Xk9Gf=>iFZe~_R% zOTx?<5*(*USTj+qXRL%>qa>sblW=UXgp&SZeSIY~eCy&?PZtttmpF@e@ujVc7tLMt zZRp~4O&9$uyLekFu0`US*Tr|)UA#)~qE|{6PZPS3$8>QovWvFRE^(gdqT0WUGd^A9 zdUSEXwToECF0kvu$GVHf7G2_9)WvwiE)k2@#aFE^{!#Cu;zJjQ-**xHx{Edcb&0*6 zz)?BdHi^Tq2%eooIG;Qs3Ii)}~Gj>pE$#>SR}WC#J=nbmn)mJEs$q zj80lpI@y-kiEeBswUM2y3+qHVsFQsEP8Rxf^3bD`7?)1QId*d1wi6etPUL2t>@XHG z^gAig>13{EC;wCJ#7C)SW^mPEOtF#NuWrRo6P1f4P&Z7dvq} z+e!1uPL>_-g7|uns;3br9s=L6vt0Lp?fJ z>C(Y5hYp_FbYNlGL6m6+b%tV0uY;x99UM^a;MRu@G~adL{;Gr2=Yr?s4u(DGV9~!F zBBrN=wrLDPZ`zRvAnf1@IZYQ(6or2tcDm!+kw>@lHN2f(A?@@D zZ09>)(LCGf=PIs_?ew)3a4Rux*3K70fv?++L`%@C2|mj0)Vyt{>}5Oo&)Ug&)K0>^ zcEWGBQ+^)9s>F;)o&bOm}x}8^lwsZeTJ68_2b8=rhd-t@nX-B)*6SOm9Q#-@g z3mL21X;{%t?vi$*7PR9rw;j`&?I=xa=gy>dPLFG6=csm;4{K-QATh6gVh+99g&nC4 zFKHVFoozg8ZR31n8#`*-SWwxY|w_z$2P8Owy{;UjY&#vw7eEHFWS(5BH$0& z;NLbz|0D3Pwc&HAjdvFWpEGUDJJE*ZNE=ZH+tA+E#<@LhEZxzDd~+Mo8{5!a*T%`! zZTzr8@Lb%6-~2XS%xPoS_ic=r+D7(-HjKvzx)B0rNE`M2+i>aA#;vcdtdh6V)zyk` zTPydQT3K7yN_SKiZDr)4Rs#36^7kHbzoS*?pj)}Hv6Ug~TJij`l|Pra(tB|$ zw)0x~ZFVbd(_4iuxRrI|TPYmX%JX5Z%pBB8#CL+OSF5lIwutv=3tKx{C~I!vd3_7h zs$1|cYvD*y3vIbAsARS|UX5n{E@`GLznK%+ z&19xEvp1=k=-6g9iF%dZA(+g|XnZl=ym&=@t7q}vQy&A6#H z^Sx3t8n2s0Y>?ppxS67R&Fs0|jPH$R=3Hq;{bDnUGtK;UqM4K<&8#~pc<*gy@a|@A zZ)+xxW`6m(8JjiD3|-mGttHK5%@=rcnlYZy%(uzSoEzUv_^4)P4{PT2z-B7?Hna6x z6BhC&zI8Qms;!BD#wNzsHgUV6iKOBt=I1x@GOLM#)FysRY(h1riOTRMHUu}J<=;fD zR}-7un$UJ^qQ<64oNJm;Gijnsze&VHHt|}$i7e$N=Duy>?te{0K51gigC@@1X~N}y zO(?E3vGXrMf3}I@6HP2Q+QglMO?=+lM8Dll?AzAFN17;F-^A=SOn%FwBi8n)Bi+&@^bs9OZ z-iVHJBhhaf>3-43yeEwuy)S5QH{yMxk&4TWjJ(*$#xp|3pMw5yBVh*`Y528~aXZCa zwls2iV{tFvfJhzeGzi;H;ltzrkHxe?ck@BI9^cyH-^lfC<*9NZ0 z8c^#P zjty+JX%I154Z?oVz#F{=47D0?Rc#>ReFNFA8bm!*f&Z|9VRsvt{!ar-uQjmg?*{gs z6Z}s$aP6p&aZu3iZ9r>R1EyQWd^R=UwXT8SABD_i4Wun>Ab+lq{k`BfrGeJ*4M;{c z&@;4w-UA!x-?xFmU+Wnrt7l|qJ)>Ld8Cze^xT<=_mx@*(TDIt?)iWlso>4LN3=gko zNKn0qWv{1?XFXq>>yg^k({5EygK0gL2K5x`)RUoJPrPzHVQ=d3eNm6o<9aOa)${RI zJxbT>d2*?q|DCVr?5TQwKUU9{L-nlMSI?~7Le92&dQmUVZS~^+qF$_}9)Ac3o|QxEnKD4krB6NeJ$0mZ*WuG%hjCLK|JByF?bH0xBQ+3!LtK-R`Iu7isWA^SkBwIzz+)Z^DuB+qv zk9BNVR>!b~brjC2!*NC(k0#f#b6g$cM%Gb2xDJjmVl8811Ws5jrk`s$?_0}Uk6LP+YH_d?G?uk2HmRjiuNEh* zTCS_svhaN^buVkNd0NYb2eo{ErYO&o~ z%jr!**1B5aSBbHuVlE46shwRb>@s2=lWOTbwieIfwOkxj%ee1qiTYZ@U0DrtI%`O8 zuHi*p4NEI)#Gb20=oe~Om03e^at-g}YFHUrBkXlGyz#GLiB}C-E;T%{uVJ=z4RNM5 z+%%|RtWFJnYBiixs^QzK8Z4jHuXy{-YJLq68t%ki5Yp5D6@P^eeW?&8WeQMbBrJ9WH zYA&@`qiC!~t)`lp<<)o=RH{!Xk$5?#%kuxiGBt`_f^YL>ZIi(CcO?6wg& z=GB}vs;1#%HTN{C`KDaW`#05$dQpwRBf;-(HFh_vS$ee^uZz{JJ5x>Y@oKjGQBCwd z!DDwd30te#yQ!L#wbdM0RZZ#=ah)&vvjluvHHi}h-e`e8RL~6&^u4QvEw>6UNfpc5 zs<3OQVrF#}hNV@EE~r8&tBPK!RosuSqA{|H^C4Aa`&Y5YtBPQkDpuH6VP#dtIMXWL z=~vOMRmEl1DstXcvEyYG-cPESeZLBgTUC6yR>jr71^wA7HlL`%>2MX}4^#<%!zyaG zRSBI|75?k0`2I)1YiSit^Q$;Cy9&Q)RZN>$#ebu#s2Wl?+I!%lvq@Xc=Srt zbt|dSs1!EVN_5^-QvbXX9#x8bG?mo;uacjy2;LVeg|BfXE00z3`d}qlzg04KXC?n` zt`xEPm5g3f$=T(VxGbzhF{hH9GX(vlN{Yu+vS4^6cLr7x)TfgEUn}1;q^& z!hfhj=q@U7&#yp|S;5aK6+DltAR?lI{=pUO@~c4Eqk=@I3ZWybV6R05sz##!v4SBQ z73@~7;O%RH|Ez*u4=dPkr-J)8D)6{eLF2g!emGgdnIjeGAE+R8PXzraPS=TY#vc)K4wQ3rPdWFtmGf~^Ii73FMgE0yv9~X0$h>mq z&lEDJl#8=WIS)saqdlk`=f34ce<>5O#$`y_${5yI#+>Rh)|ZxXAis>iGRt_BT!va~ z85ZGXczrGtcCRw>+{&nTC_`agCTyQ&Ofe{9p>`Q-Rm<4f>TzB@D(fJVO$BPBTCpBRKh&p5{9^!(Be=+nso_YrX_sTFX5h6 z2}e~*_~~s46JC@cd00Z`of155l%R2`gzM)@*nOgexra;WwZDXdT_t#LDM4*R376KC z@XPWNCN30wXO|E?tpt+^CEOWR!mc4DOzT%d+t*^Eq{ZmB7jvz#n2puN3@~jp>c#w~RLuBS#S}j&#`az@ zH~%SS&DCPQTqq{uR540Ni`n;kF=Ku$CTCkQMw^N`y;ks9Sxm*EVyx#Di`esG=1wXW z?}}nR4K3zE|6*qK67!K2VbW2=@unii)fACdT7*h|5j!)B=$%|dKui&L!ircFSVV)h^NboSg^2&tl34pm{!EX38M1%$ReH%7JR=eBIQdV_qz+3 z-d0FdeIeH>3mH{hh)+%-C(;V}7GH=}WFb3(3#s)jMA^NN#g2s}Sr>A{w2)!?g*a&z z^6Q5}>R%V~?pYyo9uyLGtB_OI3XxqbMCWuN%Z?Qi_j@7de=S6@O~5u4vS@7~5i1J$ zb5S9!a|(Goy^tvr3vnA&$hIMc}*0FTN7wiXwNJRt>~Pb;7; zzJTYE1q=%=z|gmVdF};xIuw9)0r4gU9M&tKM5BN!$_2E)D&W!60{Yx9K>42nMqMpH z??M67P8DEvM9>~6z-e~@%eM+18wyynrU1WX1*}_8K;Wzbex53>9$KfwsrE=7dk*AbvpbJoTk|-vAy4S!@)*7>kH6>V5j-=G@l*1+F*c9LVR=j* zkjKql;$D`^q>fx}H0BaomCKltT>i?<#WyXNK?%A18JUYiP%d(xTz0$VqHmu|wPh|p z8t3xg$6S)saz*|tLGxcOZjW+N+{tD8ja=0J&L!teF5e%|*V$A*&1TSjG4@Y3`>$kk>wGraC$jPSBb&^<*&>!Lo3X!Svua&7zpu>Z z=Avv==VW6)Et}}^*_4mS=F7lrCicl@r6P;pIQ=Azxc|0?d+mkc7JSLOV zLo+$lFH`6PGT7Li!HU)l=G0{{p*({@1sTFlok3$_21QXBBn4-P+&vjMxn*EvpMjEP z2KS9JxTurC@2Z0SZ3YXTXE63b2H*b4pzcZr>E|;DJduI*9~r3Z&EVf18Jr-4&1*B5 zzam3?$1`Z3l|jxFfj2e-(_tC>*I)4bmd*}oI`i7n8CaiAU3ofj1?kvjrt>Z-oxh{g z*%p${Ouux#x}}qEpN@}ZI$B2Q+|Ws9r>Yoxn~wZhIvMxVar!5nS69+GaXww-ND(~$ zNT>L>bUe4G^L|r0Cx1$3`SNs;OC+7_nL^IwbRLaK=eMEhOzoF0;vUlYEJ;J9C5=C8 z(?pK$G$eUxM5L#ok&wp8$Ta2$rP1M?Ce9#fythr`pn00ux1~|3nTC^cny|m8@$-{3 zdf!bW_C^}2e+!&5X-qhlM!|tJ%yy@7eoGp2e@>%jRT_4S)3`D>jfKslrB`Dr`Kd9J!pzpmV8wKAy_WgQ?8?HI?+Osl3{d%8#p4sa%qZ z_7ACSnUPA{gjCE%rt;gMRAjwVv5}{6up@;p4Jp`Frf{f8+-Id=lbj;l1VO4=2Ag2 zy)u*0PfTW6R5H;)$(-^@ro$y!d`8K_zbF|G{bY7%CX=U>%=MSae0!8E(xfLd`+BlC z(m>F) zO(NxP68ry`MC#w-dM1hFqe<*NkVL|+BzA93B6?jCTURC#vM`CCXD8t^C5aVdlW-iG z#N2*Kn0`q_6iY+BIgtT1i99Pwq$?+pYpIEp#U^qjERh8NMDR!y`;kQEStVj%l*mvW zfvb`zY$1u9eVRz>-9&!*Um|XQCo=s^qVT~k@HZk;tTliM*bb zNb}@Gj*Uqqd`KdTzDq>ACqd+tO5j3Mf{0B?V0m$Z@DEI&Cpm$0F$qM6B(Tsg0adpI zTI~`zWRZZkK>`!B5_q7TK<>)~);&%@|4stk*Ah5#F#)fW35-6Rz|Fl0ByLY&{-y+8 zuSpO(&;-`cOF(Bv0?iW=*f}x*^MMISdnJh2p?K`t;`v$^&*AcT9P{Jpl_BmE;<1m2 z=SyHbzk9_Cf7Ey+*758ziO1k$yzqIB=jXTae0Ua5{=Ik>+>GbJrFf#x#549-Jm(I? zi`?_^$bN}u`?`2ER>V`VAfCCi;<-6F9>3A?^d1t=?!NKD$1+ZwUE`S17$^LL;&3dC zqct;*)k$$YjEW;DD2`q}aU%XBjyE=O#F)l0NH2~(>TxK)izEKI=s$=P_Q*KiU5+E_ zY#e=#$HDJ$JlP$G-{v?v*Tu1HWgJ%)#$h!pj-ttNj2{!n{vm>ENP78 zLS-xlg|Q@O#?m(_mYF;#FcvbB^UZn^@ME#&StF7Jao?V&BG!{AaPuzaPud zo3XsP6pQDXSjvvZGWvsv{&!SWa$toJH~LwDu$0nG5Bi7kozG9>8ltf zK8a!NzcC!W9>cwhG3cC(!Q+n@Qhtk}VOtCXH^wk~bqp+t;rQGb{+$+s>bMwehs6-u zPw@E?O>0-Q&>=)Ky*irJ#nJql9nIO~XzoTwqZ}NKsZTWSF408UM3ZA0O`UEu3bkm4 zzKdqs^Jtdbk7nb|XnwmC&51M7Tsa!e{r%Cr*%^%{g8rvy9F|4nJujNj8POz6h$d@9 zG{pm=sreQ~Yj+gVmMD7FMlql?is89Yj7^PVQfw46LZg`D7sY(HC>GmAi9EqktkjR< zM~x`fypLk-izwDT5bYn)E{k?nz>bNr0|IB4!2LzgtQEA&1&{fH*Y|?w#3&|@6fy=1 zS-pfzX(YW`Bazia(pC~lZB8U5DUoEyM3NX1NtkaWKCY2C+D2k#7KyfAByZItdH61p zYtJJ&bw84QHzVOvB+Jf3GUI3@Blbt~bw?zPn6T=LoicieRBh1S391(4i7R z_Ui}&o3pI3|M5 z!4ahP5i;cAylW2^K0D!TC=X|RemE^@;li&e9P_Yn9{7i|-#wfk?8EtD9!`dSICdK0 zJbfR|!50GlARPJ4aFQ;CV|FH-+egFMx<6dlWx}c26pqiDaNaHr=kO2V%$Xie$GC99 zhJ~ZnFPsx!!kFI`MrUIfp_O5LC=BCBW*FZmhEX38hG$?HPdvle<`~9Mt1vPR!!Xhc z6EReR?qwKF55w@d6~_H5Vf=h9jBm%n2tN?Un_Xe-{3VP*Yr{xb7KX~aFn*gMcuWW* zak!AvKaAa9Lm4OuC8{ZuS5=`<6iQEKD87lI+=&cj>E}>tJwvf{4CSO%DC3MmNzw}C zjdCa(Uxo_bwon{zg>vpnC=?hg!+IGbUi}Y;t)cUMF{!^;$Aa^ z#`ht7d?9cigiw7m1hq>ctT_`x(UA~d?GrqAgpjf^gnw6uFlk8$L32VlH#LOs#)e=! zB!oSELuil(quL(K()wUh%7VF>7tHXqV4P!vh5uSG^}fNpcMawT+h8J0gE^xcj6yXS z-8aFkcp6ONzrp-{J(yk>gE2S}%*sQ-#P10fd$wR?>w?99elYVE1QYaqFb5|FQ!^r% zCj){R`7H=*Nsx&B3=;3YAWjwq(VQ8?i^L!iFA;=AU=S-jg9vj7;(%okB?dv<&ND#?;gE+Q5i1H0VT>CMI&P72ynH|J;Q-V+#9mMFt zK^XK7VutK9pISe&u=X=9C7)T9^BJGy&#aIB%;%ub;Qg5}r_XG${w(q%erB8YXCjrw z^`+=P{LJQCp9#JEnN4Ru6L|D9YxjS~YsY7nZ~BbW>d(wu@)^rHpP4%KGrD6wGh)bR z-uL-TFL@vj+5%~<4dha3AVoQW97+i!E;^7+!GU;s2Qtq&5F_hAMi>Y3Qag}NB;ax&3(p3Md>?@f+AsL+2&8&rAb+e5Bz$oo%jN`PJSC8UV*>eia3CeU z1KA@Bz^gTY>9qm8FA1P6JAmWK0fa>buplTv*R`*Bytv~fo{n>oi zAHD1TG+pp#%L#FR(4U6g{;*l#to5gQnLlgi3EJuY6pr&}=`equedkY#!jBmpe*CZA zkDxL?hUWS4XR04|F@AIf`?1Bx4>e~$@~!>&!Pt*m+I|Eo`_ccUANwErVepS1WtaR| zc*c+0NBr>L>qoEce(c=fhw3UnG8XzVah4yaCi!78(vPYEek}Or%XNt_u1&tQRr<2B z(3gKReDRL=74=JeS?w?SZoYWg`ii;?zAV@E6+ULZIKK9!_OUN>@Az`=sxQXpe91ZH zD{>V3^4m^d-fr?GWVJ8S#lEbVpeUKn4tNqufERF7+m(#T!MnH*<=;`8CU%JBi*HMtBn% z;4Nf&GsNCo_`iD#{hc=t)x0rz<4xETZz}J2)Bl<`^Ur&;=eRf54tS%o(;KHv-XyN} zreU!+gXeg&V2U?8M|<PGry-sw`*@<~?1`1NC$2`G z1Za5@rQ}KK3s3Uzds6v7Pn!PnL~_!TuZKM8|Enj%w|FvcohMV4dopXDC-bIzvSgg6 zuyK2`rmrXKy%-RMVY*-n(=DxjTpMxwGwtyU-)L z^TP>u#vODQ{v_^n;!edHchZ))6Eepgrz!3jjCSYEAa`!{a_3aH8@rm_SXJf5v_esM zFvE?uI5+Y`-H7mY!_mbJ?N4qzGIryfw!l?(W9ffx!l%Uz+5g-q`pb>*lWy1?azkm4 z8`n3xv45=_E0zhIAKd7g>PGe$H+%-Wq1)Syds0{7Bk9VI)vn_I$5q&BTuF&{#VO2{ z_kOPY7!RnI> zcZ^-wqV2*cWfw|bxZr%>g~$JMVb@;==1PXS$u73AA$NxuG*#HJ$1I z-kG>(&V0D*%--wH48Pz^%5i5j4mfjQr!ylriT;nys4a5lw^_~%p5#pI2xs2(cV^2M zC%$z!5m@iUy)q|}3)qRqWG8H*oH+a0iOHT$WY{~QV(!E?Jtulpo$!3^#MQ@6%)ISH z&SfW5&p5H=h!fqvIpMff(5-i3%nB!B<~i|jx)Y1XIZ-^s3H3fsY?e9F*5Zg|wIc_M z9O<3uh+DiPXTlsA=I1El-W<8|$&vBKj)ZGDa#P8X$uAsT(=VO?F^;lmi)o z4&3u_V4}SP0cH-I)OFyCiUX#v9N6^8f#QE0czVf!siz$X{KJ9czdF#p*#Vuk4&r<1 zK=ND%u1205^ymjgKxdu}z^Go;cU>wJ3=^I}g{j6FAk?dj)jkFldYt1Rt_ z*SF`ax;`{JV&x||vcwMn)*I9cCj@a|Rz4r9pW{>uIdqjP4eCLU=>GtG}wdcwZ zd!dK2M@eeO#1=bjs_ewR(oX2+>^Kl-M^T6!SAFb|IN9;i%8p@%cIa!^G5ehz&QI<5 z>0diSuiCNuoE_;$?f7$_9p&5Xxbm|dtt;%fKi`fo)9rXQ&W?dY?NIGw$7q=?x-GUM zPQn(GLR-Giu*EXYmbsy}*!b8o-`N&BD_argV2izmxV{tpr?$-d*OpILZJB+}7K@{{ zOy6gV(KcHq{%niR3R_0bw-xVsTl$Z)<;4(NSoBpsj8rVo_{(`oxB|+csRhVngm38}=NrA?P<7mTk2W{>V0r zUT(w7A8hEDYQu#wHe?L4VM{L?+$Eow(ew$`iccu=K5;qq6Is!p*c|i;XU|Vea`?n+ z^G~$se&V?5Cn8>bV#%XV=>GGGZ-0N{(y33R9Qwphdp=?M%P0E%^oi?BK9N3Kz$Smf zc;qK~5BS92U#yAmux3fUHJYW?bY@#~B*_}T2x}$>So7G;nnD|EHkeprtZhw?k~Jq@ zSQBv1nn^dTxqrc$tmD?KJYbFb4r>}VShH)DHC79(`8LCvKgV0+HPo8neXY4Hvm&g; zN_E4EaaKGEu_Ddeiuq1fJhQYSQ{RdO>f-*56&a7Mn0MQX$Cs^0K5fO! z!&dzJs}<3kt(dshimOYl2%KZZkSSK29Azb9!>mwzv1CuDB?k4D)RbDXI>(Y%NtUEW zSTZfZk}GbOc-vUg%fyo3v@Ow9vZU;}C5!G^^6zy^g3nuuI4eu`@3%y6yCo$*Tk^w7 zOK!}!6gF^6uA#&YY@aZoxe!_xT2Q4_e%L0>47UchE!GuK?9GYo?`UDFShFQ@6 zI}0|;%|%WdbG)m~X(=>keug>c;>G#fxfwjH#4W|wK3yP&2;xn6b#&jAK@2yfHAtUENIV?aUbT#EjLq%{Y764CT{i!Zu_^@g6e< zZZ>1ZPi7onV#dqaW;jeTBW;8k(tc*l=rLt`yD8UeO@&U@6rW5}3gS)a6=upDUsHBE zn{v&{6g2}=+|*4)ZW2>EADc4%wkbbdHs$DPQy%#f_FbtloTd>YBM3M#)P6G6Qmg?jEOg4X{ZUid`vj+WWr-h6Lj=V#9q~esMiAT zkqKS@m@xE`3A0a`u(Y(+HP)CD!Ny$oGUkbcu{d)WW2kG4y^1k@FO7+QU`)pUj48WlEb=B8BR^nF z|DDE+-e}CURmLn>V9cr+#%vsC%+4Xk{NCG`Kf8^D?$(HF6-M02GvaZI5ig^RPzp3c z!`%p7TO*83j6@v)BW#q6aC~lr>s=!}uNmQc&WM1cMg;9OB4n!(Ve5>DSY|}zTqB~U zh&IZI=mFyT#gM2DLn7-8i6}87EX$CP1VcWD84}=Yh>x=&o>qpq8W`fJZivkrLo6N} zVsy(8-Ajh3pE5-0kRdO38}b-K?yNTC+9E?P%rxZB35NVW%#fXZ4cRC&U{#9&3#ts5 zUSPoJGz0p_7$E;_K(mJdWp)N+ni>$TV}PHs0S+$=FuG@e%5?*to;TpeF#}HRGvK#v z2K>CG1Y+1QG$Me0m)zV3GC3vwoV_d5`CU!>2oDPpFhI%+2pG)-VgeW zveHMPuTO=VzR>sUlA9h^Z1mV|tS8R7dJKH8N6k|`qVMQo zeMOI#XY@F8SdR_A>M?1v9$jnnNL#Fj^DI5yPt@bWa6OS|SdWQvUD{i8NvP5l?h3j* zP1EIYj4n%pbm`}*OQD@Eo~F7e>*#V;S(i00bQy9_m(pvxc%KvSqq>~ltILY50)L$@ zxl46%n4`;+$-3+tsmu5Mb!k(4B)sh-S~VXzU-Xfc86W8#_mR}#kC=IVJdU%+mBr2mDFq#yf;$-a+V+9qh%f23#GN22C_L~Y7Pj*j}s_X9ps z+oOY9yAJnjb=Xv_L%&QN65@2w4AJ4Jw+>Ssbtp5};ghZoS5$OZ@=}Mk`#N~t5HuHb zSa)0p#XcQ^w(0O}y$-^Gn_fTY5IRMN7o$XffDT`Kvx;F;?_L}4IBjl+ zXtT^)n+6AMY|XW~psUSv6>akV(?O+^w(xhj~0z>T3FU-akNN_p&43)#%l3zuom;Zv?#RKLfuS@Eg!XnPDKlw z7g`*Q97OO{SQSqG?nsQAxwQ5pd zrHNjFCR@`qX^GYpHD5H@?x9Jmt++SQ6#61fn%)bXXPW%-uO_uuG|@Pt$=bu3lhxQtj?o--mQ7YCa)dg^`l$<@q8iUz)fio^CVm@g{FJ69 zbX;ou`B{xdcQu~csxiz&P57v&vE;p)$c3ZEZ+FxvxU9z2(`rZ$squEV8e>qy{6~Sa zP>p~YYU~)NM*3hiPW4iwwo8>e4XS)8Rpni_Dx(rrMXf4T@xD^U$w`&fma4+%PL=Jd zswBQt<{|R#rt-uEK~` z6*Q|<7*n9a$5a)@N2{P0sKP{d74&Vy)mZd31^k^Df1<+J+bU>XQW14#RZu;s!jN4m zyxXWEYI>;fV!jGJ(^R-WMuql)D%|+`f!dA_oUi*JYL9&2aOMY+<36x6+dk0y+6V5R{Xpa452B9Z2eNb$yljL#9MS%_Aj@ZwlC7N?iU^iKP8Xtk|xE?s`GHOo`KT zl?a=x#GH{zyz8e#z5G4DwZ6x>>OCV0-t$lDd(xubvm)?4nr`oD`}CgQjo#y?A;#bS zpQH1R>*@RBcvggz5VA@|Mj}M@xvzK0ii`$|6#1q!gp3Ah7osE?k&KLrlD$qcGK#FE zsI*Ia?>@it`2BGn=bmx*=YH-z=ly=ap26ho8BFQBf@#|JU<%q4OeJfBNq=cDUDOSx zj@iN7<`7JG#|6{S;lX4l8BD2NK{UQ0i1wESQReR;Qu`W2K50Re`z(kw?*`G)>p@f$ z6-3%6gD5O8h{`;JNZ1`jr?v-C#ik&FF<)L9MCH0cB$~tfObMdmaY3|TIA2#Xi1NAu zxvzF0`IH6H_uqk>6Bx*CXn~aWERf{y29n+NKzbMzNRlT5X^+f zYzm}5YXkWlejx4F4Ww7I14(8|AZ;2KNY`ZpsbN4MiMj$Ps6K$cmImwo~d?h!yWE&(*pHh?@f22jeH02;6)fL7=PP^d-# zeOKXq6#{6JOaNW#A3#MN{-j#xPxdAL6qn=A$NT=I{>GnNp7>MJ9e=97>Q8gd`P1$b zyzIxzZvLdP)1P*3^QQ!JfBLt|pVSQe$#$VXT~YU^g310gevChvOZ!tqUw_JM^P?d( zezdg6kG!+}=xK%@HK+Q~tVe!im*7V+m;ERw(vOCR_|XaFyD{F)BR|kq95%T`_VVCFG;relJ-Aeu7BXmefoUq+Xr77km5@V z?)#GcEnhkx?MvyWe5pIwmu7nTlBKIJh1mPj^Uc0gW#UT;%YA9N;7bQIeJOS-Uw^zW zNyzz<`aoZ@==Pz&1|Lc;^Wo!9ACmg&L-W#n$oiQN9Zm9~`?0+Kyblcw^PxEbKD5!p zhkRXpDE>bm`flMvovVFl@?sw{)b^oWvwSF0*@vEw@u4DV9~#upht%7>$)v`c_7{0m zRJJ#zWO!3isy9hK@}_AC-eh#yn|4NeQ`j+YO7`}qAN#zi#lf58w|JA*I&WIPg0D;7 z6gkhE9!%ry6TPWvgg41ad6RYbVTvl_T<;3F7t%yBLexZlyxjWZG-*%X0tma(v zg@-vq_b`1LdYJmQd68D37dfPR(ZvT|lzGXE`W*El&Anb^W97wTl(-JMrWe(Z_o9gd zxpsQPA#(qHh+^L!qOXaZbA9d*P4PcOYj^T`^FwrH(INUc^AI)2AEGgR4iTyj(zdLF z6r6I9Zr?gcUrrsQrb7ow-u@shG&x8XqJ!iy)cNY0gzo zT6LWBq7QhI|5i`Bw9=F7K6}!)NuE?CyrtbW`>dv(# z+{tUWJ0H)uQFy5vUC4B!Yfs!L;i?6=g{kh9i6i)#>xg4P176&ND-~eT-AD|zj575^>2k2APetMs^pI)czrx&;O zb36ZjN;iMjizZu~yVm)u7g^?T`Q?q0g_W-mqD*-PGMIaAqpFRgdlOM2_~(saGO zG-CQ*>Kd_^ihEosz1)@Ves$&VKUX>w>&j#FTxqGhD^1_#O46%bsb0&KzA3uWy}_;& z(Y%ND=5rSE`#m%_c@GW0z&XhQd+3wP9=c_*hXM@t&{p+5BpS_G$$j=v{lDGx;m2;e z!giAf=OUYg?D4~<>4eC#e7)sO4WSG&;dpDyJ7(uEA-Tu3^?g|ZL1P>h`m*&Dmi zY+V;>Q*j|S%!T~hcXCeQPLj#kN#7srq%)Ux(#9h@X@cucDzMy1F-v#y_|}~?Sz#v? z_1j68Yn;hC+nFY$I@9ksXF40Bi0!sOwC6s?O9g%$btgoyf7siEFYt zQSJjL3cKV)OOJ5I@g66-Yw1L`OPy%!Y$wVX>qLk9InkUNM=JX1NT*&p(&9KrYC7de zR}VRov7IA{*E-T|9Y@-z!r8~e94WcYfi@R9(4ce&O1|$vmeCG0AlQL!?{=Vdn;fWT zu>;pjb0EVp4pi62fg-AQkapG%%40jo`{oW(4&OmZ zc2H1@J*gIOj`4eY+LCNfJyG^_F2J7Vx!6;txjpSz#P#-P+S7$m_B3B?N1rO}$o88Z zbw9JC@K`%i3$-KWW=Ezrc2v$e#vb$SXxJn>?t5fMnvL7(&F}4G_I5j!-q}w3&Tgmv zzT4@P<90r`#QDb9PP%H_xn2wJ(`8EqCAQ@7*_N6gaenb-TN-%GmO}U1(r7DNy0pxe z$CTSrf`Tn+_P3=+HUE)_>-)ca`5(W2|8XC(|HzPQ{iko|4CA%`(P!=dXtgrWhw^gk zHcBtpMk_vSqj$;MXz_(@JhpKg_hH#akIlEy+(p~y_6*KA9<_~PdO4f8!iG+MwV^@J zZ0PVc8)`jnLrw>5sBnu7|KGLYv2-?s2{zpS*M^kqw^C%zRvP$vE4d|XrOMM=$^7tE zdT+m#7MN_MSlz8OLUk*7592)Jwk>2)xP{()+(H`nxA3vV7S0FXLe9Ik&`%4_Gd9>l z*Jo}aY56U*S8UDsq}HVO&6;ALS(8+(H94QKrmqLAY2H?Aid> zdMonCv7($;RUSk znY=D+rmTR?G}C1>`I&E~9R1CtF=I3NkKD}tg)C`ixg{O`VoBegSd!{hOWGe|N$>Yr z(im$?+OeE-5aw9YpmCP8zP}}1tJ%a^3Y&;tZlYtiHc@u?CQ?4QiFVpjpXOJk=~naq@mbIYo>0baM_KN)nP%S zi!I1J!-CE|u%Mi13mO}2K^D6$=*&h7`e|T6Bh)R(Sl)t;i_Pg{g*grQW=?v~%*peb zIXyUTPIdduNo|WcZ80>bvzq4gWt=$;9AHjD?FMqq-axlrZlL^I8%XZd25xuTK<>61 zC}B0PTd;v-l{S$6;0?5=X+2%}v!1@aT~B=y*K6n# zL1sPKx3A-zSI#{CxQ@#1ts|L>>v$}|I@;p0j)KhB(H;GDlr?=Fb&gm^ialnuq|A(V zWSY_O$7Ymt*^Is)HKP_+Ga9|wjI@`Uk%fjC*OfKnJ`QH|Je>bJp=cY8`x+!Ol zn9?dYQ*zj9N&zcODQ2!IJsWRISp!U|uGWMG{W2k?R1?yUGoiJoOvwJA33=I?P{e8z zid$epDT*fi9cDrmjmA7y)tH98H72Dy#x(bgF)j8srgb}vX}gIr|5i1o02O08Ep1F! zTi4Rvg0)=Na4lurT}!{tucZ>dwN&r4mb%uhr2({-WYpHu*x_qwa_1VFUc81hGuDvK zgEgcdy@tnhabEJSHDqeBhRheOA1NoQWJ zq~KdC$vu1}?eJVl7XPiJ<*QcG08rHFd3JaG|^2a6Qe{TtyU06b@0ZXXac?rE)zl2WF z656V^gfxaP;X1^N=|jg2w2Sdyqw{@VKHscTTF`67E|T$#dNpR zfZU4>NH4>H20k#L&le52e~1BDxERnxa|0^UGob6!49G#wfYiGdQC;yO?y|dxTpui= zdC`lgC2$cva9KqA%oovo{YBI?jkn7!qFr73q+X&=|1$LH#shuY7OhVcgY+rKMV}(f z^=Y-fJ`I|#PpO=1;?bo?nk9O?uO3}~phxD>dL$F1M{iy9$irNZH1zeTWSSnGmD3}m zE+TR9|J{b^zXwF}(M0b8iQHU>rkNAv=n(}^BU&IwRMrWKCnI~ft#wd;~(p)Otfpi2hHy7c$F zE_wOsl7f>iJu=fJQ$d$%RdwmeFkMn<(;-%%LmS@fP(zXq9XY2%lYMpQse=v~o9a-7 zt`46=(VBy7(545*+O$kZn{p;=lfw{gZg*YC z{rncvxVH-_?)E~`j$BCZycW_ryMqT%6M6zRbk)Z4Tu zdZiXA&C{Z5sqo8OvUoC= zzFeM5%Z|>a7klQ?+)Z=oromjAFmo=2kDSY6jWx-mRFi5xY0{R5n)E$dla>T&(nA+b znrf~|XZ18mYMLgw4cDZKjybfUXb!#oIEQQH&!Njvb4bRYvv8c|P=(nXG85*|OVv3v zW7r&uY@JOK1+&TF9cSbu&L+{>*%a$No1}NlrhUe<>5ukoGMGG@;s(zq*(MFz|67B8 zzt$kV1P!_tp+SQVX^^9>24$|&pgCF^6fseQS|l}SLmlT?XV0QBFK3ba%~|v-Y!)qa zpG9Z3&Y~8>S!Aj?i|#7S;&#Sahu}ht~Z04qGr$%{~6q0YzDsuGe}#QK}S?)P>%ErQfr+~2lA&=TH16PnK+$n&P=DI z!_%q9ZaNvRold70PNzb}>7*_-o%`lZqgOf8Xy~hHv_5Vc=W%m}w#PJ@vuzr=ubf7y zbEnau@zZEc|7mo(T8;kvP$Q)mYGfCyM)AkhsD2-3X&pOQrfPmT+d)CEzzG!{?n#%?Ugj; z6q@Zfh5Knup&O=Cs7QATjaQjM>xWLE&}LQ6=2E3TZ&gX>wkqv8txC5JsZyb>Dve&v zdE8p62=7LaJMM-EtK=I$MRFjZvW*2^E@9 zsZ6WCDwEd}Wx9P?nevV()6hN2q_a_(Yk@0MJ324Mme_kIH0<8akQYG%Hc{A0-<3R*CDdE0N7k6zThQMQS~v$aU8gNyl1|ESD+LAq_=}9<4}BJc;tl zCsA+aB%1Je5{Y6a(Wc-@xSG7r0D?5n>cTA)yg%e5t!$h*YJCP2Y zn@A^pCQ|&4iS)*JBLAzJNUcf}NoMdwn%X#lkUN3aznZ}9D-$@&VFK55m_Ug(6S%hL z1j^Bzz~eY3P~UzNNWN-3P5VBcM9;?4nyce!>#_0V>N=hRHjSr9gYk4@#&~)(Vm!U; z8b{g1aq0o$5_gFK9&lujis`Xu~fZxEHzk; zrMAUmscYs~k{C6X`uB{XL8W78$fq$h?7(xQNp{s}lAb@B22U7Gk^@Fl-x_)9{UJ{s&*iE4 znmpBo$W!HBc`CM)r@Y1T^mC>>Wsa1mcip2XrG#_HGe*&!`=jXkg;8|De-wo~jiO+) zQRF4!OmdY`WIuEiZEhY(#(zfA;x{AtIAtWwh!{x|502z|KO?EH(MZmi8%d?(M$*rI zBPp$F1U>pbg04RsL6KKSP{6SfwAXb6*=!m?YYj#aW{jX2BSz4eE;$-dEXU)GWNE*-ELrHu^0BKdO^}r( zahnYNEs&wqcQSM(QHK1^$k4XKGPKA}h9<9(p*{;_s9>TDF-aM^P&Se34IfI09z)6BW+<7j7|M0~hmwQ>XQ}rY z%5Ael$o=aOGI}zECSD#w^}$0Zb=MFIHy=XV^oGz}wIS3`b_mx{8BA9S2Gj0$gGn!O zFbzAy8R}kxDQ^2?i590QyK~#}Eh?33^q65BzNN^ZL{Y?hZN9{pe+kFtNlNv+{ z4Fjp**Fd`Zav<5?97r?522$ODfs|}LkoGMbNDDLuQiuFNde$pRhsq=gpCw8BK$21} zN|JYgByeu@}>wd*LqX#rq+>kpJC-ZE-zFa_>R+@*XT7(}Ppx z-N<{`jj4g%*tM=3k5#%M(cFdQue)#}ybC|Jc0plI7px_^a5b|N<$*woyH$k%Q765fWvHf>lm zrwyJGZAi{+#lPrQDDG^p z*9>o!W+XN>A@5ZahJ-g^;npVnH@gX8;zm6G+=#M^jgWP2gpQ~Y+lDmaSZ)LE-D*It zTLbzmZ@|>i4KOOJ$L!gx_7tcO>^ z>2C$x6DttlRe_V7-*;hr1#VQ8t!4Q0whToPWvJX%hFZ-s zH1#P%`->dzA2`?W>@PHK|Anvfe<88|FNA#0 z#*Qo5Sh71CN_yGo9+r*lyq~z6@Ds;8f8xItKOv0$iBT0whRN5yp<&NAr09Rc zaoKO!RPYsQcfO+e;8(m{`4z_$zG8jl7brdcf~vqTxWDcT4yk;>lBP^Zzsf{bSSBu5 zXToMyCe(U9qbB_`lFxs}fgPWryYMr5B|jrI>l6I0eZmsgPZ+r96W+^yLU2I_mfy+1 zphFpWw=x3(3K=k{Oh=!`>0p8B@K~1)EtPaMHh#qI)Q_+W`v@iLkNBU*r*^BxlV?{Qz|J?!(}VchL^`0V)(J}cfqbL=~m zl&9hJ!!#@jNJEQh8e%7>!L;Em`o4UNq!VvpwfQZE%zTSSoo}%1!yCw)eS@dl-@tZ0 zU+(_~Prki|&E?k^vg^3SM9IH`erYO7@1^31Zz|M{ zQ}Ja|DqL${V$_S5cy#O~%s0M7huTY=Z%cu8S_*O^QsA~N1*0`n@IWF3CYcO%7a2mF z7}Rtb-bgWQ`Sk*w*I(fDz8BC~`~vUgUSMnCb95#?N4VE>OkedJspFo*{NFRwK7I!O zpl486{|t#L&tTB>6xpdy;TZN5y;e_gQvE5EyPx2}$0t~N?g_H(p1@w~3EKNVLD2Wd z7=7h2Vs|~pTzZUD>Bm^}=MnzIJ%YXaBQ!621aJ9A7*hHWk@p@#(f1+Z);`4CNe}V7 z<^h&Ge}GR%AHdAw0sc&V0GrnPsC;uDE~oCJdFy?+&%Te|-h1%p zhZ6(uLH1`d!mlM`gljS)^pi1Cmgo6*G2-@JgnQn_@D+CvI_55<%ad^QK@tY~C&Aw& z2@*<4@T^Nj>x)F}4oO7S#zfdoOGH829hj%x!Pkg8Fx++rsdMgNp~M{|e!dOWi??yX z@ivBY&S%h|+vxh4fL*Z(C~-}I`Jx1*%O(H?@kqKIkI4t)acV_828@lzzVbMfJ&414 z|2VugiNidlI9#o}h2iWL4u{-A^~PJUn05ri#Qju8FpXp*@Oi~LxmB*a3+GZse-V^KRg7A9ra z@bLaMjP<*QgT~iTFzFifYp>$!^Q-88>?&+6t|D#fRZMBUg1|RdP#S&(i??3ERgEj? z(|Z}#8JF?m{ADQYxQzV^F5~-v%h31{gQHhsP`WDydK826(lKcMeF>}MF5!mTB}gp0 z1dCCZaJM)bgOa1M#XB00R!2j6LNvBjUBr_o7aDKVTT(CJe&_`Z zw7P(eGcO>aGm0}*qpb{$7WIw7sW0bI6n!3=&gbEydmfom=P~iuIXGQE zhbMc_LDJwHOoyLCOu<=H-#&{42hYN9#aVnFa~5OD&%oxv86^0fL96i@aHk^#*GA&Y z^GJ+27Ktquk+?B6616R-G5^hJc!r-wDrd4vYMjQ(o(P1cMgY=SP z&>L|Ku7yW&J@F`V4jsi1qoWWh9L3IxBe?YN2)OSIButNBw$c%7sS8Hfi(sT23r3Aa zFvhC|V?}Ea+};EsHarO5wgf>uD+n`t0%4vW2>)||NVE&Y@A-ik&_58fzXf1pOaT0M z2H=h;0NH~BAd%ybX*c{~yw4x*2L6Z{?vM8ceyF?c2l<135Uuco%@{ufm-*uMeP4X@ z^+nrSUyPsR3%wd2{P)ZUK}UQLzrhEeReez3g}t_C;UIPQkLX>O29JAh?22jJPeABpGpqeyE%Mt6#rYK063EBukPLiLr+=)z`5 z{kFvD1C~%3VTn13n;@**1jF);F!S38>q#52rHF%vTY4soLYk?8f)+%eKqddtwwym)wq6X6=HN(;as*6!d;DURK^It z@hjo6Y$bLVuYld*71%s(1xy|pVwtHSM0LwC``B_QPhAfA*UKPfy$oHQOHmWK6#1G< z@%i%-Foz|$Be?_@uPo+I*J60&8o++P0oKVGV9}jL&{(ku8p>13Htc+L=S1} z^pMyW2&x6MRF?+iRWKLf|LX2AN}bj;p49eoB*$G6yNxS~G| zd-Bw<$XyM?N2%d&(p20rnu>!JQ()*n1@ekhQ2b04i5pbm*`$JHp(>D@p@KhY%D7>p zjNQGHp>uvR`e{u@##bdoI4i+YN(m~lim1|4MDm|WaC4gkjGTo2NfYs57c&mUNTNN<9XDq7Djz#>uv2gq{1~Z(-;NQS8 zxOH_j?6^|el;83w-Y<{Ka`LdcGYaEYj6!zlNSyK+i8T{OV(^m@cxyHShwJ5_6C#J^ zsdBjedN{UQ567e~S^SEW<=_9ZSoT>4;vF)0I6wx@mxn=F7>1l*(g@uvjm5Ik=!hSR zJIjW`rg#YC4-dgdg&{cfa4=?@3`TK{6iy$J!ZKAUbi5pdILkrU)IJbHBL?ER#y~iw zOJcm8Br^I+!ZUgRrs)j8udMzE+}$7Zr2C`rWl_a3zA{Uu3;t^r=pW=wB!N(XADfU2B9L zan(X%VU^H4rb^IW`%gF&R4Jsg3ZZ{%xv*5dTnPTJO!yF0Dh&Q!BCHr(A{^B(7CyKY z34@Xfg{9?x1;2@Zg_r9Jgr1OmLHkXfu(#`vkf`}bsNC^eP`;ciSpLcpPRry7pO*d- z26$x)q6a?(*Xk_cmU5O*uac;^>E{(7dcJnysMKJv2= zxAK$l+c!fP@-$u0ZTKiSsC^X9T7MAUMZOoBKfM!_2D}qii_!!S*SEs;xHrPr!q-Cg znAgITwXcM=L8*cVdnsIPNfFX#rU*^jm@qEtg|O(`bHQHfxe%)NOt^pGsgQf;iO^g6 zSWuquSXgHENN_mzP&oeTfsoX3U-&lrzR+xUPZ)J6S#Pth;T3(bOjEoXYR-PB^ ze9sA!kMv~gbP6yLQKmB;o7$K!i}$HLL9d=Cfqg_?u=V2Bpz8UB()g{NwzD6 zr0<5DA-`O>lekn!n6N~MJ7yrKtlZc^$ ze%~R&>|IjA#QcGRw2`FH^`yU0F}0uY^K>8Kbw3Hgy0}}kFr`Bz8`UZ*-`^xkF{u}w zo>e1q9Q;qDS5_t(^{QA@dGW94g?pYTY+bI%W=^(fzVr`~WaSr8_M1e(DwScP`&CaxKJOlh)?B?W8h7}vsAA(C(S5CWk+iJ%qDJp2BDaN#qTaf( zBL5pBL{iq$q7(81MRK1dMCwCYbmx0i=!zl&D6>KeX#rMpJ!p{`l%EnSO|7j-xL zh3VQf`st>>+Nt|3W}R-1mq@q3QdzfDXRz*%IYm18HHkW3O+9r=(&cr2%NS})NJtP* zDbGKN(Ipl$wEL=U%+&6|;-F zz1YR`jZ(cB!E^cS9>n*E+4pNb(B^sQo*uAnF*DNRWu8k7>p@(Xn5F&h#&Dkd-Rj29 zPBGIv(2dj%G3!~}jUhaLCfAJ>?fkg@cEP(%%(U)wA)!^wnmxPlxkb#94ZBd*EM~h$ zccHmS%rr_n(cUO#waJ}mY7n#A-km6}7c-~To%mQMW;4cj;zq5QRaJJtqejf)A9cW> zTFe{+I?%U@x0`n0aV2k8?7+4Pe%`h17*H-|&d=L%v6OHBXgg+<@awXn9f?JJ|9sAL zTA`TjZEC~00x?^V+6IYyG3z|h2FpKU_QJ9aiMe9tGrbM%zr<{Ddn*=X^Yc$@g;SQ8 zeLB^OGvCE5d}}M7d=)cujaGck6tf9EEy({QX2l;{P?Roaac5ib=L0{_?JdZ7CuR%h zwIKPem`U_)LFj8Sd!N~it*K%bcCi`LQ^d@|u^E-m#Y|bd8PQM0tVXgKhL6SU(T^tl zdmv`MSDN5^Ps~>BYJ$vNF&m2}oVp`sr9+w^oxsm4rxAy4iP_;BjVQj(`|WE4T@$l$ z28}p*S)HX=7#%%0>oV9W(EJCe|VRp|LT#si#VrICi9`XMCe8<(}q>q?2R@A}Si=WTKI_PVjVnpi`kUgT1?p~X5weHc;_HyzmC+x+D^>wZKy@{HZeP)S__vgV&>3P zgGx&=Tbfz}3k!ZdLTiw+PR#mjuE97HF)Nr}1LxIZmeO90hb#F0(yGzCl%ID*HKrMe z*;bosn30$n%&x{hUB2JmDugT$v%wivI6qg+>dsZ+qK26Lu&ctE8DjQyeieeI^7HIh z1!rY`UB3Q<;Us?FF8#y!abmW~`5#K;#cYZ0KU|d)v)NMrU_MOD#%EWe-(dc`h^@r6 z0bHZF=Qq8~ z>|q%^Q+nAN|1unY+RKbg%HaN>ml-OSVMkIgTV7j=weh`d+4EAUU+4KzK2Lp_x0{#Z zLsTzYIi(cAk$nB;5(p=Indz$%R378o4=cg3K)ye#5-9uhGW(e&xa-M}r?VLI_xCc7 z_r*xs)yo1Ri=pJ$%TE4Rj9}Yd7Oh!~QtMuJTcQ{XH}fPqC=D)cgitU_2V=w)-R7Q%TBKknUy*fXP-Z6#h-<@=N7?UQ=h z>EC~`bZjq6zV(-n<$77>fxl=Q+RJK}{KYHDUN&qbpBIbb7YRB&Y$|fGY;F(RJv0};X7sS< zxjERP(!&Pb%0b@v9=85K4va_ju-GLzcrM+;T1VtyykrkEEcyl4-fng==@(wMcC$vW zU+7oY&7bRE5S4ec%j15*si2#6Rc0eRyPIuzoQ*q~-Ryo~HeSB#W+T>R<3ma}b5+j9 z`$yd@tKlbJBzCifFMs0J4ZhtIKXLR@H|xLoCv47iGp89pF(OJFzCf1iaU zuWoiHG7DSxce4q$Ss1jln;oB0&ls->|H@i&YzagK2RWa~t;!>vFr;fPY`H>T4H^c>EQ*@4J|4 z&{rs?bg{?lzM}g<7c)}%icbk$thn(DPG9X}o~d78dcKQ|3j2bAC%f2Pt1n0n>SC+a zdA(N`tL@6fzr9^7^kXL69J`q2xlD9#?PA$>nb>dM#k{mKQNFs1O&ySl)l0hAx9^`3 zugmMNaC^g?E~dWwGnT7$u{`>W;E7!ngYEUPuoso|1hdSBI&X4Hp+Q}k5aNC7_Cv!Oa z5#y~o*&@4-h%)VDzCwqM51GJ`fvh%w?z<**VJFNEs zA4YVt?J^(GU#gR>$$t;6-VUa7`#r3hI@r{M@A;U#gUPRakCS;FY>>ixT=>?(x+>n` z;=2yk@aP>*Kks0bf$!jVw}Tb0dk6dL9jrj*9Sov6SbkF)Muze7t2F%a?_h-|({SFs zgOzVd!|I(KtX3lp9X1`Tz4tB7Z|GqCKEH*gQ3o4-@hx8Jb+E}!Z?SlO2b-t+7Aey@ znBm~Jm_4zBZOM6qvvM8GcRW@3*tFO0N-evz?{Yzrv{tyno6ooD6Gc(?VY%(7&Bo zTfM?=w{{k({t6~e?d)rJDyDB~XVMv|Xg6(VMp3DFzO0=ccSywnUEZ#pifJ0{Y_wD= zzD{muTYkNSi+nqazwr|N2e-5K{Vx&P)5exBeF@oyHgw`Vo;NUroo!=^sSIzAwXwi3h6XRbzBR*$J#B2G z2Ez>7Huk>v1$4~Y*uu{*ptrJ(#b0~@5!#rN^9#(H)5gw;USPCJ8yhk71zP3X*va3| zks;N_WaFRXTz4xwRQ>D70)rMsFhtB`y6k6w6f`y&*1p3l|6j?3M4XWxs8oV(F$fCe%+BO7?!9VZQzt*hh5Ie+U&AAKUTZN z<8luxmp8Kzx(8@CvvV@{Fm-w}iz`URz;Vs&MPf4YhBUM9hm#T4-Nb6vBx7ey6O&R* zhFX3TQ>(v=oX<^c<;%P9Noiuc!tP>HQWHD3$ef}Un9G_|2B4+@qWv0W5MD^c6{`0G|z2heJT=gQ@N2H zc$@%}5sj=NI04Ol8=1330zw)aSk1HqC=@lY-JS8c^tFMteT?U}>jvf%6^|214Q!ZG zJlZZbuxL>{HiR~?InwdCB(GpxeL}E5_l+ z^afU4e+x}x8(3uOEew+4_2IWLvb~-!#CF_~g=j(87sbe+K*HKkm$9}k6$Hs4UEJg1+QeM`v zJHxMITw)!&R1}My7wg#Rd$D+Ytd5=Vk43wC9Xq-%7PIYnJ|z}b>+9I@wrlWPT*o5b zUqiHJ9g9A94M~c1EWzO#o(`*HOqb`~we0&)UjMI_Rpnhp^sibrF!3sU(`wmN@2lKD zp_Z*Mz6y;iwQTp~t7s3cWl>F6@aRx2`@n66&W^RL>+}^USk$uFc2~fb)-wBrS70%( zmc>e4L6uT1E6u$OSD9L-mT(!3-8F32q06xUSHqsIzKpEw8vgsf4DGiyY*RxFP9@i{ zyRTwUa;b(5iHL#v@fv1t8v`eg8umde2AAz>nEId?d^W3LkvW&ps9(eS#$UovjT*N5 z;3Z5LU&BgQU4p7q4YQnd2`a7CEW17$3dPlI-K%H}{8G(+or=c4=he*0HX3hlRkI4M zXhcRvJax zMuAoA&EY7V-c!XwjH8fcRmIjTM`7s7DyG_U9@-14SbN%eSSj=EoIMYBnJRY6;XFdR z{;^=ud7Li)#~g<7{QEz)_U}1_r2Jz#$>-o1|Bp@cKZh-6{;_fE&q3t(j}2El2N{=t zY)I!>WV&T%ko~uk89(N> z(~L^yc=QZP9#yg^<3ih$>6mH5_ zFrAO5;M}KzC0;m%Y1QRyD!0$({VZqK^iLruwVbJp{eMgQX|Wm=96$3`;@bn z$HMW;v78xOg=5|Na#lV&93S<{nNPoPXw4{Ria$@{+^BN)>gGu_iObjy&y!g4uZ)dc zeGKb5kTeYt)3Q7O~RI)Ohi zrEKEO6Noul%7%HKz{b6$tl#Pr7-Ch*x)o30{<2cm(R3VUb4poP+Hq7Vl(IhDUhLk# zlnrq{j^3IQrl5Bmp4laA)`;V%eObbmmW99~u7ue<3Bj{dCCo1*1S1cXu$$H)u-#t5 zzG{XbVND4W4+ufk!V;#La|}w8OW2NtV^}?;gk3w#ZOhHYtiiN!1><0ul&7PH|oM-l5&%w}|!a9}ESRA{Lz;gutOiOo$J{zve<#3z7kX3aAVsd05yYeXzo4g8{)#X4O-CoEh?F+=+)rG8t2hn`dDr9%Y2cmRh zAv;(f!2ib!+1fV&Xs!Lr)Xwtq&%dm{QvgcYU&bka$h`iSWsC^m{zHG+qjG;7+5eYa zf98*kR)1Mks6UjJ{$&x{{P9=)FAHDbkH}HHJj5T1dkWYEZYQrSDPTA6`5`c)fISKF z!`S-;EOV0|VxtP!KMg-j^($af{rzy+p@6CX@`ap90b8Ho3s3C==I`x`---q7k(n>% z4k}=EYQFHP%V#rseDMBfK6C!+g8?j`-HY{sPHaBwb@zc?NIqM=+6Tv6^V!wOKDfRy zpLMr-nL z5Hz^EySonX)t5bg)YA{Mv%51%ch|4(J?DK@S481hhI?A9e-!lFU7cGs3OnxJ)f8S) zSP*wte?J<9fm`nC=c%JmbM{^R7BmXEhuqa9_eSDj>${p`;z%s7d{@K#MxuV{yV~~V z2>i=@SLclxfi=JG=;e|lfQNT9_toLJc;b$BA2}S&x8Ko|#fIbV+&k)X(ca$=yQ9m8 z4#SDIcQkw9VeqYbN0*!(iWxq4w8WsHc$Vdky7Lc3(C^#Y{`3$GeRx|l_8)?SCvNL; zuOWE5?Y2%hF&Me#-qyN(1_MKHYth_;(X7pFO@3?;dRD%z?|KfxkW#nxVGcV7;Cb7A z{uzh?KW^#s?gP>J-Yxx^Z6NBz-O{Y?0r1~^OO40@NF9AkyJsDMn*(m?#v}c)viU82 z+qFMhm%F8sr9ZM2yQK@XAL7#9(%)VBq1&gM+AVWGq`YxcADex#)V!&kyYxkgH8=H( zXJ2fabW^9BeNdw3P4(;22TSYU)VrR2kShG9&NX|ZTi%=6s7r4gOL|iaW$uk^FK_5C zvlrT&yP>zc^unq=H}pj2UbwaJhN|{Nnvpm3NY|bSY=1-Jv-Cv$syFoEksjz)`i3Tn z?13SkH?(xN9`?NXy0&+B$EZ8kb#3?V7~sCH@3VJD`}Nng($Pp%oqAo@^^8Q(-q$r_ zu1NfDa9t-H>xL8I*EL0-ZkU$$y3Wqi4ONp~*WxF;;`j4wda_?vY&dgG`{(P5h+Wsz zJH88^&by|s2X?{Wq1SYO!7fPB`kGEZ*BRp~T+^OIJL7M$Yuc=6XY@{cP3vCjgqt6( zYW}!B8 zd(Z3H_6;z7!FjFa*#P;5p4VGeeQauRUi*J$j}dvL`#QBZk$( z=x67&f_FVUIeAXA-mD93Ij5f{))bkM6lDMP3Ux3! z+d2LGsW$ffIIG!K*T&UbXSGt@+W6o)t5Jz+Bgu-hdSXW{q#J!!bGEL9jP1|rp!Bui zQR%EcG;88d(X-mPM@_s)byjcYsfqYkXSCCq8d!hkjQ$%|14Fi-(X}OOpi=Z1ZFsvn zQuRHfo>QwMuKpRl?Wm5y!Dn>Gs|Xazenz7gN8rSdcpVWDf%doJb-=G`_z@GYLpE2# zxMlG=rCBwk9u=?aJ*r`Rn|M8UxGH{?i`S%)RnfUnyjI9v6=#yg>&*Bn@P2k$Uks~) zQ72AojZ#%`cH?O^?^H(SDW^4jdS%p&Jgu=(853)q*2eEDVSnk<`h9sN+)000*Ve9t z-|tUp%S4sndGVAM+Eoz+cc0QPZ7ZV0oKt$q(|+xLN@I>zK!Jv*bXWfh$P{u)_Y|ps zU)fG+?6vZ^_5GyYnOGisZk*Jl;pH*@&`Aw>RSvZlpVWa%$|2*hlj^Qf4yT)+)SQ3I zVz_ZqN9-tzVqPcpU7NBv{pW;6dX`1UdnfeE(K7g{Cv@_FG8nhwgqAE;2C1S>=&c*D ze-0;f?iAox*%R8_06G^qp}y|~XA+;#3@ZiRkB;l_x`L?K zM;8MP+8@{AxeQFLa9r!3aU!PBah)>KiN{Hg>p4Fsl0G@6c^^BFC+?UIo##O5wa4^H z6$e7c9n+@2!V%u#nBLhMj=+k?G_rL#iWWYmDLliGDcLdI9v6nMkK?rcpfFrK8mEQ5 z!?12moPN3!ioRpx^z6(~gtm{UVcA!d4yCk^_QqGU}*C77s?DC5w{L%Y{Tb)(>vG9OfeSiDmzg{sjXR=+zLi9~_D3}FmXi3d+!1}# zx+G@iKcY{vl!U!T(pRUvvEr`keV`@hR%_u`bQMQoNA^% z{#O(SiX{{ZFaWlJ12X!nA*Vh=`p1Uv>UXIaE7Ym`st{AO2sSunqV{{D)A#slw&G@w- z+z~N4WlKQ}DITMq?FynqiWuFHqaZFnKCIQw7qIWchxO<90?4@HupTf9VD0e3I_7hJ z_%}PO%{J%9fzZQRwrzd{XFaSzIr3xcr$ZWiJ|Da;9MXyt@?re8L)upI;rWz9I`vCl zl<#s#W4GkRyh?{ORr|bnSn!ZG%as?!5*^Z*i(cq>_n?-T?1iO=59+$IUWi|CPI(4IYWp^)Q%jxL%D$+92NRrhk@{^$LAVSY~Rxv*c;*3OAh+xBat zlsQpp%6{E`BnOgp-mh5(=dkw|`*o6E4s_4IUsJ!#j;w$7*?XPrICyiPhBV8L`uq3k zL(lAZK6{@oiO+@sz4mFlaoO;@`aTVnY#3I2pXU0O6`zys(=qT|E8nz~C?oHzGs zwgOoZxOlJn-^zlS1NUmPIa%$mBMX9j_v*FeSuiZkUM+DXGhEO2=#;^k@$Kjy z{pp_>C06dyfv-K$aQGfgyv`Fto9xlWtvs|r=2Q?(_#3z zoqEmArsdnbQ%CrwL(KS{8t^JD>a^XdU)QF^J!7YyXr0#1v+mRlxzgg<=N&r#Y8tdT zze8t7r@`gTJ9K&VG_Zk@dLTs_tZTbN@4G#aRCZ|A5gursV}~{i^T4*x+jZOL)cAgG zyJpyt8qUqzbyT<17(9Nv{;~6J+uLl{DGyWOo^!hvS(XYZvv1e)O;Vx6r)@ehODa@6 zyG?6dNQtH!w`t*NDbacCHceSIC3>~mroWQfui@MD_mLFnnq`}M3{QcU@3(64uoS3v zdaE}0k{rJ4wrcdw(I26297d}mf@fo*j`qjx0@p_BSZj}tF zj&IQ-xs&0@$}M{QdQ$WrwnYcdO^V!&wrFtOq)@*tnk0QvG*7cd@10J9Pfs`NsfkH2 z#@eh$D<(mjC7U%qaT3fJuvs5zVtCZqtf_`4MwItvHNq3)eX`9u>RTc-zQ0K??nz|l z;x}nPpG3$ycayI2NrbLFH))w0|KwoRP1>~nKS@+*lg>K#SIYg_sL!kYwR1-swb`*h zvUAr)eO>mC+?%>l7rXwG(n*!lf*}^)BFE@l*mf!w7{^Bk}Tgkjr#dP7XDbPe+PY#BA3?c;&1O| z>z1|JV8DARHGZv@`tnZJw_2-(`n{7}VQV$)(_5LCX{|=~c`NT;tx@yC8>t<)Moag8 zBb%13(U|wI<|3of z-@lMPGgj;8UN2-(=hfQ(!*hu#yIQmMc`ny;uGT9bpUIm~t8`c2XYxCKmHj?`D#_NZ z(v$t4N{W%IG|9IolC<$EZ8qqM{PbO=7k)gJm#J21r=gGK(!-US>%T{`|L{tEJK~Yd znX^*w{d*|gy06rCqaTX1(n`&n?4hK{yHdMPcp&lLR_KjX4`lNB7209yeJQtbg{Dt` zUp`0Ke?9u1tZ2GIt<3kNQoss5G5@YS^;n^AbKaGakC$t}vOD7GTCVf+-;ot_mut?o zx20&0?*A~9FWWl#(+I-JVNpXIe4hg*}y*4b<12H$`;;3bs zx$F(`X|hab#$A_je#_Lm+I6{_YMDMcdrk5^T&iZhYtsJEQr&m`s;r*1RL{1!Dz~~W z)ufNENZRsCwOQvY5|(SJo_}*$T7O!i9r|9DQKy$^jvtp~(ds4odc-B!Hgt*JOL|FS z>MhX^lP}6q?|`FLT;0){i^S z$sosKy&rl`8hS3)w|Z85UM=`+`XpvrNa7O0#S)^_5#7o0!i!@D# zc*#&;kzRj&TH<~z)YyKfrQd~xdiM7z@!GghzmGj7)~JPAF6}94*?6IDnR`;c`YhC7 zuahz{#X`Ne?u2;WTc8_!PRPQ23pDz`amg`#fi5b0T;_CGpzc%0B&D%HJ?bBmfteR* z-#c+~@6~+$)iF-W#m?8&?~lrgMf0`WkfZXg_k69F^r%#+I$xVjkCi$3=Ifa3v2yd< zJUzY2EjiE4(|}TLX|Qgd9^P-sq~Y_lT{%k*)Ssu`XO74N?|JIk_=qG+GEZ~aqpSiq z=W2x>D&afl>eL^mRG&Ckzl=4dNvpX!B7-Tdg6C?{B`#^5cCNlJ>XPP<=je^yF;eI7 z9DRfsDLZS9rj0)=-d*NsqsE6NLzy}1etbyYWu2ondLNP#Z)WTF{|?IHqq8-3@%wg%~b>HKw;uCBgca-Nx`emD2YvDLHmUZ;H$ zIb@b@`?6Qk)|sVC$Ly62MQ7>OjC)1?MC;wDuS&W*I$uy4LBmS(bH~u64g}l0BHNeJ5>_V_Bx_ zzMPxn!mDYTW6MUlZcWo=hW$E!nwCGeK`wWnrm5O&kW=NS>4%T&<#3K^`eW>RS@&+L z7RQh%AOrGBlH?WZPd@);|o z){4pcufR%q*?+R;+P^|ZMNHPl5i2BP{>i%U-f~&;b&>}4TQ2$IC+XFc%VpKdNxER^ zGRZS=k`D7Gf@*zWcC5uEtN)#uJuE$f}9@DEAVXJ#eDV z*tJ+*RG+9Vsw@^qfr(oE?jo7+ZGyJww@A*$PtcjE7fJe66ZG+lg;IUs1Z@(sP{vfB zpzqJvS>*f^bYuGk^62Y$9s6s(c*Kv_QM2Ytsg>h(S@HQ2F<`vjIWkY$MT}QzJWmGX z8?V;8xiap{IPExLu1r5QPD|#UE3=l5)6Dzl$jpA@)T`DUnOt?8R(m#EMtY6Y1tVum zk56MYMfTa!_{3OUuw$0U(yR2*XgQZ_tomk-mKE>EXt%91 zB{FV|o~Sfa0v3(YO7~~TmmXvE+29$ntNa+<=s82WW*?)|w@#NlZ$|5!%G2evHCkN{ zrb)kfqc!EQX_CF$XziDEn(V`9O|o;U)XqFw_e4yUC(omF!qX|z-xa09qNd2d=qR0? zdy0(j7^P?SPnHypC@ofRvW!U|rR&~KlF!FRX{E`Nye!!}TwkReFU498 z*N1Dz$>!w4^;fxZQgHh)4Y@y7W;Yt9bBB+W?|+ACmRw_{{)VA?;J_GJS9_=qZ#YKY zeIKG7K982tD~D*$S)-+0)gijXceKp-Fj!xmjgp-U2W#{0QF5~EV14fqCD&gJ(i-(g z$(`sy`Y(E<+z1<_-_DJY_y+?uFx?2*Gijjit3F)j_zl$IQ-(>G8v}Imsi6`aH9&8t z8Y(}E4bZ+-hsdt;{k7Jl!P0h6f9-v8kfhAlU$3VcBx{fN({a@XN?6Z+I&jJWiOt$i zx5xLF3T9s|nXbRYbm*(^YW0&6Y5VH8=)N*zPamy#xsSYR)<>_~d2=I4AKlrcw~XJ^ zThA})CCBRY)}Z@6<@fhqdaqzlDZZkYp6k>@YEXk)I;ZMR~b0Dhk7ULD((GxXwrx-QssJgEg0Qd3XJTo6R&lW&xN~dpjRh} ziI3F69XiU;zLDBuO9%1G8L78EwU@g`y6JL9dl}uSn{FJ_PV%Jdraw-%mF;`F>dee- zCA3*rjcn0I4kWVwysowQZ0Mpt-nEjYHM{7>uvU`zOJ`j^rlqu8+*xm*X(7AHcGgze zTgdNcowRtn=3-3mq+#2d$$-F4I^#!ES$ngimaN!R;zxDV4AD*GWs#2RxYJnv#&^&y z#T$!9-wxVtKqE3OdzB~{io;h3T^3)MBL|f{j=GEjz z`<8lpTUGH%-BLRysw%^`x6qLKRm5Gth1ObMS^oTJuG@cB6947RwPDRl(y~Hxt+1-1 zM7?OHL%vp!CDWVfw`vt+TR<~Cyu7>|xZYHce=aA7hBwum)ym240!?-A^0Kn#coUuf zrHo9CY@${~8Hvo;L<3gAK36u@*WX1lH*2hKYKh$X+em}f8?tCkBaQpxl-gAr>C%Qy z`SYfsy0$rF?W~4cD1}4Hg*4Plt-|H{tp8)zMn& zA75JDb*`o1B}&VyG_`c{#8Pr^M@=pGtfZW-UsID*Dk(d@*U*w{y=Cf>8oDg0x3no! zLmRa(A*CKy*QQ5{%f|`Tbxon-vfaD7hK?&H?axKnzyG3=v2TQiR4yv}vPS5d4Mn8> zp=#PBbrE^lqM9~}EG&Z(Rnui>3(21~Rkf5~AsJq!swSILP(Ht^qJ_T|kajbw==7!q zQ6RsJ8C+RMj?X8Ta#vQ5S9vA(kxF{MR$gh*u9E)Q<0bQxSJDnS zz2xM^ikf9q9{E(gqNaVCTe7~dptY*!7XR55^v14SQZcxKZq1QP>fR`?r$*(JhQrFM z&+{BoKW}-xTPufDb(hnt`?E`EhjN-NUv|lxvYf7*m`(m{Dy#iIWRVYq^Cr9L7mq!$-5(>P0MAHsqI9M zY|UtQl0sFy5&Q9+5g6=p)J#k?@XtrJDpBe`a88$XgW!A#i8@o zrj?!p9a_aRt(?x`&&S57NwNZz*(&_~h#jGf5?bn=kDM&t&6jcfPE$Xm@{=hXPmh=1j$-$Q;IeWv;8 z`vSj=j6QxkEZt9I<9T0Q^7Fgl=;Nz(o_#ZpdHU+2%U_LZdwq1E`-^eBp^v`U@!2rG zm)7^oKN(vWmewgVJ{nmarS;Ir560lzrF3Mk_r{gsrSw{xcSec4r8KVITVv3Xl3JzG z8{o>`4-iq)*a*Ng(AAZb=x@Br-&vxbjw)bSw#QsyJ_^@Q&{KjxnY!PP*`=> zbtC!LLOOEiHRIU4LV9_}Rby00A=MpMjKJ#!wam`T#)Clxwc)Ny#>5;2HOZcfM)5-h zwBo)CMr_jpn&;qoqw%l&Iwj_u@pN&1opI!>(ZiWvi^rWY-rdfpjZeiJ-G=8=uk)vk z`+4%|kgKPR+GbvjymQhx*fOtvd3?gi{ntx9-yAmvFZa?DUyd2)VgLDWoRR;29{rp$ z&geEOk3HW%YV63DM~8UD8t;ze*1RR$MzJ=zwP~R}_DJBRjMa>&TmHix#_deF$3IEOwp4;a~3 zW!Iz^_8aNTW!D3b_8EyDX49nK_8M=Zvgy;*dyPx^vuUfmdyG9+R_ztI+nC-at7faV z%V?J3T{qMMAn%QD$HnvKQ~$)pupZ7?$4&8Ufotv6N;&!~+Tt}{yI z$*7g~uQhhZWYE)B)))cJGwAcrtBq~H((BU9tBrz-)9Z`CRmSY_^m?YjO5?v9>9oqg z6-L{^>9pCx<%X3#ou-IcX5>1MR;%4xYV>TBRtqIrYM5Ws==`EfjFj`z=&I_Ajp{*Z zv_hXn#+1t*I8<7i(Gt*Z-+@0mO_=IMN+=&sbN>E;`C>ZI1DA@hv>?^Eft)^m+H zGg4`j$#aZtrBi9lp4o=`OiDd)Zrg6V&3SAUE z!?^i8xz5z-#<>Z})$8pv<4BR@S|QIgV{=?GO;Tg3F|&O#Z8m(0(K|^pjo3EXsIe-k zUcNWUC|EYBe#tn=_;N3aZm%%Wutp@&#DgXnlkz0dH=D;B5iyCi_x*83s%D9GdX{m9 z^&^p1h!|`1Uyw*=M~yKGh9uIV2SytUH~lkzy^As)KKpBCE*53vFZ|b>c4VZ{sO=xK zV894t%<})t*XxEEYj6KHpXC~AxN`h9GtU}q#5eq9_DeO$xG?*tnQZg`Ttv1zH=qTD>(>Z)<6cTKvZR72d+QbM3X6?_@K>H}h+AaO0-NklL@zWG@;U zho`Md_M8Q+@H3gQ83vH^X|&}M%A*<&Crl~MyKJ=%wuQj7()*}H79ncZA|#` z#2o&orZL&?iMf734P$Kg$7a&N>PG*KkIZ@Js~IhxJT#m2sA?GbADRu)RxvWScwmm+ zTFH2{;J*2|W<_J;<$LCk59N)H8SdHIrE*5D>UYfw;bo2E6YiJ;@5AU8d)vG>L5$>o zZ<#}V4P!z0EwlPfhf#3AO|#CpaAWPx8|D*lg)!N!kv*USM% zkkMrMRdejy0Att9E9S8k{zl@gS4^Y6pHZ#OW%ET!Ut{vrOXg{_wBbH}(R|Rql<_g~ zMYB}tl15IsU~YR>!U!9D-fX|BxKU@%IkR@lVn&;HXU$%@iW;3uoHdW%C~S1@aK@~= zu#nMuMZB50X+fj*t<$DQ?gBj7DLIToJLAmSjj|gZULQ5R3uQA>7CmY@KV~u3w23vx zSecE`C2sRyw5Jhw)iU?A%Vbo`Xqn4`Ga4r%j+kcZ3cx*>hhq zqu}fV=8kzujXG!co5cntF$SmDZ(eJf*jQM0pXriB#_pke&7GD0I^*{4F&lgS=RE&z zw;B2Hr}Ikj-R8U9-<_A*?K1CA`06~hbf<}ypPh%U?J(1Xd~~kPxWlZH>AiD&#CG%J zyEo3ZD00#{Y}N|% zlizXY-P6m>nq}ggVab-8IqSqaXUH-g4Nv zvEX8J!^wlr2hA6mSzqjTW}3Iq{G589Q_d|g%lqtcwokdhOww?db8Ol9X5h#j&gDbq znO8P#bMD?f*L-$;iyh;fV|Gim*?GF~9J7^kqw`$L*=Aht_0BW%XPHYju64$pk2W7a zTJ1cLD%xC@Zu% zer`F{ta@a=^T_-urdPUo&I#uyn;lxtaaK(=+4R~u%bC2~B(rMrXs2t)MDuBj8P1-& zCzxONPjlveJ>DFcd8#wE(0H?3-^tF7EykG_E>CnOnK#zl6gt7VNDC|X;75uab%QpZtGEI@QUHi*%wBbmB$TnPAoUvGIoj>2W>h;$NN3W$EfT(?)hO zeeF-zz}p?nO}!$V*Q&QSJvLTx`ncMf^`BOBjwsc}99OKoGj3@sb7{{q&Lrttn#&Fw z&d?Ff&GBg*&JJ&znvL3qIw!YmVy1TmIoF+SWbViv;5;M^&G0B+=do?|%`GoWIZt}k zGgCD2cE(MwV^)hV<~;DHmN~FO5$Bp7HO;A3LFa_K)y>J}^E=zsj4=D0@^XflRn2k@ zb32oiu44Xvn!|Z~X(e;Tux!q;X)BtgvSo3G4=-=7-j~Vw>~&c)NwW;j>CJ7eYtnSi zQt@I&?ecIQbr|OI4yl|CHapDqc~Us<<_tF%-c0IjJvr3uza+8q){kIwK-^zPtu8_4 z_2$1EG1mjk^nboO3RLkob8YdcsUD%x1?t){QUm-I`r!$V7D+-uV{Z2a0 zr_XO%Q{o)YN8~lHZLu6b-{dimUUNB;x5#ZyN^{8J5uej69I?;g;mBbwoW0ADd{Z{_ z$&+o4pV_mTDa&nkJfD!+OuAvc*3fAj;u#N zx^^#bO0ysd*N!=v8JP2=u=n9^Hm&OvpjOOt5M$3`r|!U z-@AsR#<|*BLwjveLByZYQJ=;)XCjO*k> zFNfdnldkLk<#0T?e$2JBWERJ)y|J#GJu^5$XB~0Xit}(>?cs9SA1X)ph(oRiTM|3| zE4tq`bm*_}@k#f%*2R4cPx)Ynt6a#-@G-8fu3G0GgnwJO$#r(-jqnZw*1L`jx)2^; zca5vi#FOEreO9`DnpXHEk7ce3c@Bl&eYVJzX!Wk}Qb*^z{A+IxAFyJM>uRAj;RlCB zyWZtn8vd>Ebl0#7^TK_DrnpATm=WGC<3!h&M3cg!-;8xVSUfuX(8(y*xPt@34_6!J z3YgL@{72#euCtq4g_k#LXu7j z`}85H%jp^zR=w`;n9JK*g>AOp#f09j686vcQB3EG0bw;(T#f1Q(km=F{izt=(;i`G zMz~_4&wdO|@^(i|+mRPS{aUPvxww8;Xp{K)F^?+G3mxW|5>vt)80uGlSj^?yRYKeN zw~IOc(kpaQhH5cM&wUKp_|`Wj!-icU?)Ypm9n66to9h2QeD9@K$ngxP4(HvlEBJQ& z{KHRPdIew2Q0?%umtH|PGn_hPcmET0@IJqhe-7t=?%?0=;D6u2|2+r)_nrLzbMpV+ z$$uUv|M{H!=XLU*-^qU;C;$DN{P%V8-`~lfhm$`aCx2c}{`{Q$c^drr8vJ=1{P`RF zeHi@x82o)1{QVjHeH#4z8vK15{QVnzKNx&}7<|7NeE%4HKN);~8GOGPeE%7IKN@_0 z8hpPReE%AJKO2018+^YTeE%E#JQ)0Z82r2#{QMaFJQ@6a8T`B%{QMdGJR1Cb8vMK( z{QMgHJRAIc8~nT*{QMjIJ}~(GVDS6G;P;2Y?-PUHF9yGF41WI@{5~@H{bca_%Ha2x z!S6GJ-){!L?+kwb8T>vp`28sSz7&3c3cpW<-><^&TjBSw@cUT!{Ve>x7Jh#Vzt4r= z@51kU;rGArejvO*2=5od`-kv;BD}u{?>EBxkMMpZygv!=SHk<3@O~z|zX|Vm!uy}_ zeki;@3h$S~`={`JD!ji6@3+GHukd~>ygv)?*TVa^@P015zYFj8!u!AQJRm$D2+s?` z^Mmj_Av|9Q&l|$?hwwZiJf8^9E5h@O@H`_t-w4k;!t;;tJS03H3C~Ny^ONvAB|KjV z&s)Otm+(9$Jf8{AYr^xJ@H{6x-wDrq!t*# z@4yqzr^559@cb$~&kE1C!t<{1{3|>U3(v>G^Rn>#EIdyO&)359w($HdJdX>{=fd;4 zjrLABzYEXv!t=fGye~Ze3!evs&j-Ti1>y69@OeV`d?9?^5I%nhpGSnxC&K3y;q!~| zc}DnrBYfTwKK}@xhlI~Z!sjL7^ONv-O89&weBKg1e+i$*gwJQf=QZK;oA7x~_E__}WKEDf}=Y`Mr!smVA^S^K& zAe;{f=LN#~fpDH6oG%FH4Z`_@a2_F?PYCA~!uf@8o*|rX2UokoG%LJjl%h(a2_d~PlEGGaDEBS zGr{>LIPV1KpWr+coR5O@QgD6>&QrnpDmZTi=da*A7M#z5^IC9z3(j-F`7Su`1?Ruu zJQ$o0gY#l=ehki&!TB;cZwBYj;5-_fPlNMnaDENWv%&c`IPV7M-{3qPoR5R^a&UeQ z&eOs9Iyi3!=kMS=9-PmE^LlW856<(!`93)B2j~CbJ^AK*R&+>e0!5^#S4?o({$O2U2x+_!-H7jPc~?q|S# z4Y6- zcY*saa32Ql$H09VxIY8;Y2bbh+_!=IH*g;Z?&rXL9k{;(_j%xc58U^G`#*3W2<`{L zeId9%1ow&Hei7U^g8N5s9|`U!!F?sTzXbQ0;C>U_cY^y*a35-Ot`qj7;Jy^xpMv{T zaK8%fTfzM+xQ_+*v*5lK+~0!xTyVb&?t8)gFSri|_ro?PJ7Hf8?vKHJGPqv`_s!t` z8Qe#M`)P1r4eqaPPIrzJP4Q%0rMhYegw>ufcX+IZvy5|z&r|=PXY5PV15P6vw-;)Fz*89U%)&Jn2!PT zGGKlN%+rAR8Zd7I=5N3}4w%mY^EzOD2h8(;`5rLu1Ll9gJP?=<0`o#(ehADHf%zgZ zZv^I#z&sL|PXhBwHa9&XzXax)z?f;{U_w3z`PWgp91q#V7>~>TY>p2 zo8O&~#{%%g=#%Ixt@c=Iy}zo&9r3$m4VEz%z zLxTB8FfR$_C&4@=n6Cu$mSFx8%wvN2Ofatr<~PASr`;t@$ajKyPn(CGkpBeppkO`} z%!`8gQ7}&m=1al6DVRS6^Qd4x70j!G`BgB_3g%nEyepW01@o|AJ{HW&g85l6PYdR2 z!MrV)zXkKSU_KYj>w@`RFwYC-d%?UfnEwUyz+gTY%nO70VK7e&=8M6+F_=FF^T=R6 z8O$q#`DHNA4Cb4`yfc`82J_HhJ{rtRgZXJNPYvd)!Mrt?zXtQzU_KknYlHc1FwYI< zyTQCSnEwXz;9x!+%!`BhaWGE~=F7pnIha2O^XOnc9n7nP`E@YQ4(8jzygQhG2lMb? zJ|4`=gZX(dPY>qn!Mr_~zX$X9U_Kwr>x21yFwYO>`@y_FnEwa+0AN1=>k0Q(hS-vaDk zfPD*iQocN??Bp>@$J=Ca~`W_MgB$6xfdf z`%++k3hYyX{VK3;1@^DNJ{H)|0{dEEe+%q$f&DJ9?*;b1z&;q*4+HyRV1EqklY#v* zux|$T&%iz!*iQrdYG8j2?6ZOWHn8so_TRuh9N3Qo`*L7^4(!u`{W`F32lns4J|5W5 zv%9AWeLb+h2ln~EejnKP1N(nq9}w&Zf_*`-KM3{-ZSPM)zYy#jg8f6Vj|lb?!M-Bc zUj+M%V80RUJA(a3un!6LBf-8T*q;RZlwiLS>|28UOR$d#_A|l0CfMHu`;r@SV6ZO?_J_ef zG1xB#`^I4Z80;g1{baDO4EC47J~P;Fw%uY0eP^)$4ECYHel*yZw%^AI{b{gI4fdCkaq#{FF+m!$j1PA86ZCc~!MycLkY0`gcu zJ`2ce0r@Q;&jsYWfV>xw{{r%0Kt2q}i$VDR_%R?)2IR|tycv)`1M+A-!e*^MxKt2x0%K`a0AWsM6>wvr+kiP@+ctAc6$m;?5Js{5qL;uJ30eL?l z{|Dp&fqWp47X&X9Ia{AioXdxuNy{ z_--KY4dlOpJUEaK2lC=TejLb?1Nm|wZw}ZxG}Uf;>WyPYCh~L4F~~GX(jDAny?5AA&qYkdFxR5u_MV-K>1bLMp zzY^qGf_zJmcM0+@K^`W^#{_wqAU_l2X@Y!Bkhcl)H$fgJ$maxkoglvxD^-D#%*}`Kut0738ymyjGCk3i4b*zAMOk1^KTa4;JLZg1lIe9}Dti zLB1@=n+5r^AdeR0(}KKOkY5Y(Y(c&)$h!skw;&G}gF~~ax`Ntp+8RR2_ykwA{4DysgzB0&L2Kmb%j~V1MgS=*t-wg7cLB2EE z9ZKLmgZyXPS)9Ow2Kmq+FB;@WgFI=FFAeghLH;zzqXzlZAg>zaSA#rjO#UC=8suGr z{A-Yh4f3%;UN*?jwmqH+JZ+G#4f3`@{x-k%N44kXH`!%R!zw$TtUh=OF(a=WCdF%N7KmIz%V+Z-{_Rl$i*ADXAL7qFvcL#azc8(^2{|@rtK|Vali?`hv3H*4F zCvUUR68Q2UZyt{S@#jGvJ;%-0?=Oo`V2t70q8pb{Rf~A0rVq)z68*p0QwX_zXIr60R0P~j{)>EfW8LM-vIg? zK)(a%djS0ppbx?Z5hVB_Kwkvtj{toVpkD&?O@RIh&_@CKDL`KZ=&t~M7NFk(^j(1d z3($uF`Y}LX2I$WKeHx%&1N3cx{teK_0s1*WUkB*#0DT^y-vji0fc_8A2Lk#*Kwk*x z4*`85pkD;^je!0U&_@FLNkCr-=q~|%CZOL0^qqkI6VQhO`cXh%3g}M(eJY?|1@x_e z{uR*20{U4%Ukm7O0evo@-v#u&fc_WI2Lt+HKwk{#j{$u$pkD^`&4B(H&_@IMX+U2M z=&!Ng-w8e&&~F3!Zfw`t?*I4SfIb}1j|2L0Kz|PC(*gZDpl=8C?|?oY(9Z+);BG6w1`iwxo z5$HPt{YRh=3G^d@z9i6}1p1UfzY^$M0{u&%j|ucMfxaft-vs)cK)(~{djkDWpbrZ4 zLxH|1&>sc*q(HwE=$iulQ=pFu^izSpDxCbEzY5L%=d;55|M{&z-xcV;0)1GZ9}Dzl zf&MJerv>`8K;IVV-vWJHpq~r$b%Fja(B}pEy+Gd==>GzJV4xoi^o4=`FwiFk`o%!s z80a4ZePp1Y4D^+O{xZ;K2Kvn~^nboH(0>N{&_F*L=t~3rX`oLH^s9lsHPF8X`q=E} zp9DV}=xYQ0ZJ^H$^t*w+H_-nE`rtr69O#P!{c)gA4)n``zB$l82m0thKON|+1O0WN z&kpq4fxbJ?e+T;Tkhf)m9}o29f&M(urw97=K;NF7GfeRBfj&Oa&jHzDCgB2>KjBza!{-1pSYo4-)i4g1$)5 z9|`&-LBAyEn*{xnppO#tQ-Z!q&|eAqEJ42|=(_~{m!J<5^kag)OwgYR`ZPhmCg|G) z{hOeV6ZCU}zE05J3Hm%izbEMX1pS}(UMIl^3i?4oUnuAg1%0BRUljC>g8os^M+*8$ zL0>88F9m(3px+eqor3;T(1!~8Q9)lS=uZWGs-RyL^sR#aRnW%@`dL9=E9h?peXgM2 z74*G={#Vck3;JO}Uo7a41%0xhUl#Pug8o_1M+^FCL0>KCueDud2|ioUZwvZvLH{l2 z!v+1gpf4Bn=Yl?6(60;nc0vCx=;HfpE2k+27Sk%|Ja@vB>0d)KQib`2K~vPPZ{(p zgT7_ZzYO}AK|eF-YX<$zpwAifJA=Mw(Ekkjpg})0=!*vZ(V$Nn^h<-jY0y6n`lvxa zHR!7b{nen)8uVL(zH9q)o#4L)eb}HM8}wy^{%p{v4f?e~-!=~Y&%X`&xIsTR=<5dk z-Js7K^m~K8Z_xh@`oKXyIOq!p{o$Zb9Q2EWzH!h$4*JMJKRM_t2mR%s&m2wu=Qjs^ z=b--_^r3@(bkLU$`qM$5I_Osiee0lq9rUq-es<8;4*J_cpF8Mx2Yv6L{~h$fgMN6> z7Z3X5L7zP6mj`|Gpno3p(Sv?^&{q%o>p`DA=(h)b_c(t0KV{Va{zY&5^a zbstHsOZIi#z7E;fHYBrF+SgqBnrL4`k=*KOUv2HHAyQaX?aQz)U!=4O*;h9EN{v+3 zA4z3>kkr-_`?_vl@#0~reeISs);jxIC~2)}_BBe=ijv865{YExxvwbZyvRku^9M(Ad8f@gWB8^;@ zO{=o%8M&=WMjk8N@UlwTSAHX}O+U(Kr8M$eznuB4cg_OVLuWzjshZjEr3uzEYatq#tTR%83B?kr`&S=tJ4`dCGrzE)1BpOx0>ZzXaD zSf3q%)-y+tb;}WKoppp*ZbzuK*AZrIbc9<=91d%y!)c9i7}h|CSX~`utd@?lRvkw< ztD>X473!#9m2_0J@;WM6o{lP3az|C`XLvR1O?ZU$AiTPDIlP8-BD|J$IJ~yCJ-m*! zD!i^WFTB1rDZGI-JiMXRE4-1_KD>$5D7>i^5#G#_@D`STcuT8rcq=PMcpEECcw6gV zSUc-eSO@D_SV!w-SZC{OSQpC*>uT){i?lX`b+?v;^|WS$^|Ho<^|1zo^|iW&^|xAt z4Y2Bj4YDeP4YoqVhFacX!>qhvBdkneBdz3NQP$7U(bk*LvDSmo@z&+g3D$|wN!H=e z$=3GJsn)8{>DIi^8P=rGXlr=rY^zu39IJikJgaf&0xKePp@q=JmVf9{t4Qc_D@W)G zD{bg1>tDzk>vPCD>v_m}>sH7{>s-iY%N?@S+846j+8DCKS{ky;iVoRhjSbmn4GKA6 zbqhIUwF-%`>V}wBr4Y5kLoBOQNUW7VB+kkla@!e8zede9pQWe8D;u ze93YJU$J%uU$fQ*->?=0-?F9#-?2sp-?RD#Kd?FlKeCzzKe1{CKex&TzqEpaUt7h4 z-&(nY-&+}iKUztHKU?2|zFDt=epq*depwfT{uyR-m{0Twp1;JJ8p?FVNq;DKN;rG%&;+9T?^w7wB{k3KVx_U|DzT!1C^TftB2q z1FN_lff4S~fi>I(0&Bao2G(__3T)v1FQAe8LqJpalYr*#>jACY@d0h!M*`ZrcL#KG zuMgYbcY2*xl0C&b>|D1;LaQ{ z*_|?As{5D!4EH<#S?)*vbKO_{=etk&FLImyOWnKtSGd>uuXZo=U+bRczrh{lzuDd2 zf1A6r|4w&v|2^*7{`=h({13WA{A1kS{_4)_?{<6o$GMaHpK$;5JMDh!ch>#T?}GcP z-(~knziV!n-%a;UzdP==e)ruA{T{ie`aN}z@_XU#=l9y(+3%gZx!*^3Ex#}B@_ygl zA%4Hy-hO}FdHoW{dio`cP41U6_NT8$>|5V-u@8MS#$NT!9DB+)d#uYhSL{w-uh_M| z`C}LQ7K)wbTP!xp*E_bqZ|T_1zJ9UIeS>0a`-a9=@O8w7`XaWZZ@Jifz7=CL`&Nlf z;affSmrt$OcRqDvANe$lz2?&-_OwrnSoLWgyW6K-?0TP0v5S1V#!mO?5j)zackBS4 zez9GB2F14Y8Tx+|-F0vjNy7&4o>_NyPj<7OY-C*q3-0b5hs)uTLth9Sa`@qLz@djb z96H3^jU*5kh!7Q4=n9w}}|L$wZA^VPeM4HF0Ann}o5$P14vtCS`1d zDKJ)N(#A?n##p8)Bo=21kL@h_P%jc>=om<*i*(y zvHOkFVz(J*#jZ8ZiCt`55IfVjBzCNEdF(*r>R6X?eQdCCV{CwNYb@Uw9ZNRuiv4NW z7u#+)6kBIF8e3vG8JlT18yjo55c||{CH9u#-`ER=+p$Lt_hWY(9>;DnJda&rcpW>> z5EDDakPth%4wHN>PE(u>&C_9=_bV`>!!!O(#?*$ubUTlMYlNav~F44 z0p04j?YgMA^}0=QOLW`fX6bgujo0ms8>~AR=h6KY7pglMr_r5@6X`C-(REkjVBO8Q zFWP%?4cbR>W!nGZa<#AHlC&{#FSUtr_qAzpSG3u2r?dre2eid;+qGqJ>$TN!OSB*3 zW@($_#%tT+25YkJRMH_tTWb+co9!CQVJeQu8UEr)h~N zX*%P7sC(ku)gYlxjY}w1lM}Mk%!GI~FX6dboN!02Ot_@hB%D+m685Pr3ER}xgmr3n z!eVuwgjwpygz@TO34_(66TIq)31RAK2|?=F2@>`E1g3gv0#>~;p*wJWLUZ7zgv!9} z359{X64CT-@J_apFt9d(7TA~o1-2!83Ft~_2lC#0|MqH3IdiSQUg{dLILX&zo<4RHmIT#%T;?4^Hm2EQ&h(iU#m_hK2%*uyso;M zcusXI@rdd{;x5&*#7(N#i7QociStz{iPKbBiKA5oiIJ+(M3<^EF+^3Ls8%&6id3D6 zbk(;+j0#Hnsw5;eDQQWSN={OtQk0aYR3yDsYLcEPjY&6^VM!O1j-+EsU(#OXfTXR; zp-F3$qmvdXCne2P&PW=soRc&}xhTn}T#*#6T$iL%Zc36VwZTa-%OY%9%C*_Nh_sdr#N6XhGN69xQ|0a)4{#Cv=d9wU)@(B5f zJoVK1%sR`XXhMG$v)0G&yB~G%IC>v@m6?^h3&EX-$g%0Ed)tX?u!Z+LI!e zLaAISF_k1`r2drfQ#&Q{)K3ykYPrOenlA}YO_jJ(-%9$XK9LMgy(Jly`j2E{>Iuor z)culqsnL?9sZo;EsmmlAQs+vxrB0FTNgX9Qlo}~Hk?NNGoobO>NezC&ZkzePVIi zcCjigN~}*?Cbp!_6+6xuvJzQ9kZV-MSW@YRbEXar!EYH{=Sf8;% zur*`8U{}U;!NH7if)g1-1m`ml!Lv^9bLOxtrf7b1Q#v=34%k z%%%J(nZNR9XHMZS${fXCnHkCdJ=4SAo*Bm9o2lm?$yD%9XY%=%GO7HVnHc`V%x>O` z%obi;W-Tu*^F1#wGmlrAnZm2de9LRfe9G(0yuV!99pUk_cJmZjTY1{7 zwLDAKQl2Ag4zEwv6yA`m(Y!HPgLqT2yu4qtB6y3l47}A@D&EE{Aul?M&fAxT;~mZV z&OMja&b^ZLk$WerockoJkozVpotu~y$IZ%m!7a*qz%9?Z&i$Bmp4*mnoZFMNpNq+k z=2EgZaJktlxzg-~Tut^Yt~q-G*Ou+yexKc+J1E=59i1J@ot&-X&d!!|7iIIftFo!w zjoBD(baoGCUv?|!Sav<d0oROT+oJfu<$HVEL6V4f)W8h54QE_JE z2s!g}7@XxfcurJKFMC@~2YYW$1N%r$CHqXyJND(AZ1(M(B=(b>H|#e#PuNL0x7pb_ zm)Y-f&af+Uj<6eY_Od&2wy}G2qS*M{Z(y($;a-k96V+L7DA+MnCNI-Xm_I-gt2x}KZOx}TfOdY+52 zVsoFe(sJ*z@^i1U%5u-K>T{2=T66cYdUB&#n7oZFYThaqFK-b`o;RDN%bUy!%^S^f z&-1Z{=h;{j^31GRc^cNjJSl5s9+$NtkHU)1!?5<}^)Qd;wK31*U17H8onwB_JIci6?_<*QqnX0|jZ9VkYNjE7 zF*73nSEe_A3Ug5Y80P5wA?WIWApV!X|-VWi}jGV=2C81M7b7`6FvjF$WtjPCr03{1gI2DRW4gI{o(p(r@Q z&=>4wgcWROcnW@JL>8=Mj4D{fm{KsC@oT{p#?pc@jI{-W8CwhbFm@L>7)J^$j57r~ z#+3pk<8FbF@vMN!h$$d2QVV|4^9#D@Wd)z<^#yhGwt_PH_kuz?t}v6%C`_b_3g6HJ z3ZK$Vg?H(;!fSM-@H~A;;R*VXpuL~XYq(TclyHH0jDOA#H3WfB~g-rU_LLwb5g6PzuZW_O+m8LBE zNHY{w(87z}(Y!@Dv_VBFv@u07v}r}pY4eI6(3Th7q(v27qHQlaL)%yM7wve_KH7z% z9kd%on`n=U*3w=V{YFbFnn%kinn5cqnn@?at3r+A&M^n91 z(v0s!H0wJS4S7eR4S5IC#=YyI&Un{OUGT1fy7FBWb>q8I>dtq0)PwKRsi)t?Q!l@J zO}+E(3H8~#yVRI>*QjalE>H{Journ(J52rbZV$EN-FE7acN?h0;?-16@e-=6crI02 zJcAlqJb~&i9!ZTX9!MQkj8LZ*JE(JuE!1VjdTLa$in_g6Ox;(^p`IwFP%jo^sW*#z zDUXXgDQ}9KDJjKul)U0{%7@}2N_}xQrM)8DCrMyH#`BWmObe8ZbKT8-CQYn$bErlrZ(jKzDw4EGY+DP`6){qC6 zejtx6EhNt<%_1)-O(w4@jUjI;eL?=C^bz@R>230v(yQdFrRT}_N>7nrlpZ0+m;Oo4 zD&0XYF5OJ7DP2eYT)LdxQ@W6heLtJbct4FSdOx15em{a7{C*(W`5qw;c<&&Od>=-h z^4>_E^IlC}_FhJgde0|Ezh{yUyeE-QzK6+|-hU(Ae&0!Y_P&`E`@W8p{=S@4^uCx> z`97D_^gfOB^?d>f{_uuG`|yk;{P2Jj@Zl!O{NXam@!@Y$zYix!BR(7^P5!W#^y`Oc z(r+I&lcGMXBSn8$LE8Ue5$WWIIiyP;rju@em_T~=VH7F$!(dXzhkm4@4{lP`2P>)h zLoliPgN}qLQ<3Op5|XHlM^cy3Ng-uKlCumV4Ji9Y997mqoLbgQoL5#)TwYc|+)!3R z+*y`KJXDrJJX4lLyi)d-c(3dQ@kQBVVnW#+Vs_beVrkhw#JaLG#MZK7#P4MXiG=b! zM0WXhqO5!qQCGf>7+$`D=qq1D98x}qIKF%aac21>;-d1=#5LtZiCfDD5cih*h{wtu z#0%wN#GB@ol++=pUjG3(Gmg%5oa9shmLkS`HC072gQ-icW&4qM4ws@OP?J zR1#bjrG&_e0>bEuEW)&k6vF(9IKs+`*Mvk>_?ba=_RbFv=cT~h7xvF8VN@#HH34OO2YL@G2vk)m+-ohPDrUF5%McBg!0N> zd_!dy{!3*W9;#}@)2eFm!m0{;GgR;A!aSHT9Zz15@fgR6(($5%(7!I^5xarT-L zT)&!p+{l_N+?1MB+`O6u+=`mFxJ@-LaJy=r;EvSX$NgP%3-@o$HQeKxi#W9AEH16) z1g@~=2(GGTKd!lEH?F598i%Xhf@9T2;iR>zak|=NxbWIVIHYziZfNZ++{D_cxY@N6 zaKF`##zoZ*!|kXYh&x!@7k8%CgS%R5$33VG!@a6C+m>D9fS+5`;PV2bzukBwPDBCHDhPheZ(%QtH!RcE5mNDE5;tEE5M$r z%f?=*OT*r;OT@mci@_$ei`<3{bKBu`gz#<^|P_B>ZfCq z>nCCJ>c?Tr>qlZ6>xW{y>Lan3kA1O>j~=Y#qXQfCF&rEAF$C-TXuuBr7=)ehF#tRJ zqYV4oM-le-k6i4Ik4)^Lj}+|Lj|A-Xj~MKuk3TSPKK5WzKYqa!er&~5eQd%sfBcB) z`B;s?e=5hYKb2zSp9(ShPq`TDr%X)WPbruYpAs-rKE+_>eR_>q@##5c)2GLn-JkAb zj()n0x$x;<%&kvXFi$^Sz{Gw!i^=?S5>xW&D5mbyAx!(HeVCu0c45d3(HMTiR!l&{ zMoe(SdW@@KHD+MLa?IF4XZ_zA9Wtc5!ot6{KDZ;FS1X?hDUZF&tyH9d!SG(Ck6H9dsSHr<7< zH{F6CHC>0%rYmq-(?z(b=^R|$bQ*4HIu3tt`U@sCAB1_$`(Rb`ZrI$s6LvOlgCm=_ zz+;*>z%!cH!;6|%!)u#Yz}uRCgZDQtf=@Nihp#sO3O{I`1;1{d4yQCvh6|b}z?IEo z;O6F$a8L6v82@cic zeGY_AepbSlKg-~IpT+RY&jL94GY8K9%!DgG)8MAhWVrh?0mijpVRj1y%UgOOLrV{2 zYw3dewRAuuTUw!MEzQt^mIi2bOFgu;r3U)5r4l;XQU+aaDTVH}yn|l06hKKWxln#f z7F5xa4mGu;K;12g5Uw>2Vz<79B`yb?J+X4+}+X#(ri-M-Nt%DY|t%laNt$?<*ErSlUErCwAErhPN&4(Ve&4J#u z&4yCjWMCg0lc!=0O2I94kf>iCpA#?js$kjdw8rU8QjcxA-&1&xh zEot{c>)YMXj&=uhsNDvgZI6KdZ4ZSWw}(J)+f7hLy8$Y0*Fm-I8mPTJ5c=7!geV0R7d0gD!Mnpj#aPde-p+ z#CLoL*&RLLeaBbuspAXy($Nkuovnb;`58z$n}Dvf0Yr3u1bsT|z=+OjFr~8+%~bfbb;&aK6L= z<(C*>`ho)Im)9Wj%PTPE%L_2`%YR_;m#1L;m&YLb%R_MJ%YAV6%Uy8&%N_9e%PsKs z%MFn6ogJppX$9uIbRj|0cL$AF97qrsi-QQ&#^NRZe)9OQNn1LfUAL1Xt2(A_;4;CcoD zc26Xb_Y45Wp8mkz(+>>j=?g~p^Z_$^5U{An3)b~`!1f+DIN0L?XL_9AdXED<>al~j zJvNZuV+F-M5ummw9JKd@0q`vpP`_D#=vxTTd;&hGlEHebH5qDif?+b z`I`>x`KATOzXgGRzG=YSZ))(;FX>w#$p01qD!!>e^EV~v@gsa!0M2(gP=1#Ilb`du z6hwZPfU)1jV3yyK?;;TOT?lsg9sVu==f3m74ZkPfc_8*X7x<_Cp!7QjeDv%5&IWKV z3()-}y-c9>i|A#5K7J#5>0qkg{9YPZ?YFg;3ikP(?4^J!eh+%d;I&_BF9{U-Rr|H{ z5<#yY=?4Mu{Q~_$e&B(}Z?NBlA2=}EZ<*hQA6T%<@2KAezuP}B;6J|vzZ}1^A24Y2 z`|5}L2?Lg&{3iqqes;eBexv`z{&ad6?|9><; zkzbIX|4sqKZexww;!g1(|%WB26*U)!c36n_YP)(8oxG}4Sv8JK*4Z;0K)}p zKMRHjycj+h>NgQ10CO-xu-tDGMg(?a#Ne3UMT`X8!AQXij0`0DQM%3kNh@1Q6q_AP8pz;W#@$a1JmW=LC~+E-(-01}kwMum$G@ zdvORjf$IY<;rfDmxPIUzu0Ke|4FLJLNKlCz1e$S!!8hCxK)??LT>LPg#198%{7B%$ zj{*bnqrq7G7%&Sz4lKcs2T}M5UY;p#Wle2)4oCECSJTQP<07jFGz;tpk zSVS%bYsnwLc5*p5K&}L*$<^Q*xeh!ee*`GG0i=f5R3LQE^VM2dXIM7WB4|+-wK(Q1N zltqz3r4%_-PfVQ^I-Owhg z7urMZ10AFGgDz4dp*z$;&~xfgD1ka0%B7Bi%BW+Y2I_d|D|I4-rA>jDv}ur(HWSj* zWf-KRf;UeRAbDfHJ+0sSphNsoh?>50%cdJ05fq(dA=7NlV0 zLPkab;C`%M;gPKQ@Kn|!cmeA-cr|MUyp^>Y{*$#HKEc`mUt(>6@3OYRFIYR_MAmLN zm$eTrV;zJWSbxD?tm812eHv!6&%sjmMOeqa0!Of~!+qGd;Nk4M@MQKwcrN=Xyn_84 z-o$ztm_r;c<}62uxz3Sd9&wZyloN=**qjp1++jDp)AW8@CP*tx?n{kfwsqqyTR)3}o`3%JuT ztGTl*Bycxka=2SDAGpz&PuyLYFWh|?h<6A> z;~m9_cqcI$-dRj2?*hilyMh_Q`xi5wcN_By?>=TJ?=dEd_Z+i>_ZoAE7lS#&OTb*? zrC=WNGBIy>xtLU5A*PU5imBw4W14x@m>%9o44&VFVe?xtGX58gp5KG9@_%6Z@-f)q zd;)edpMsssXJS|Ix!6s75q1|}hW(2lfIZI-!rtT?uuu3Q*cg5|HiPfL7V|yW8h&4F zD?bw3%O8p*2}WYMf^k@-U=r3On2xmzW@Gyc=3z$(7GtLgmSN`$R%2HQqOe;8o3MKX z+pxz3JFyo9d$G3!2eHote_`VUC$X7=bJ!BWMQokmDz;5<6Z=DO4@(w4!t#XwVO7G{ zShFw&>kuYl2ME)!qlDSmX~F{R0%0+Bm9PxEMOcm9Bm9UxCTzxD6t-b+3A?b*gx|5T zLI{^B#N$eY6kM&4iE9(`aJ@n?jwF)fxS~LuQl!I~L}r{_6o%_Bvg1aIJh-W%zPNd! zfw+~TVYp4A(YW2B3An#RQ*q}-vv4;=b8$~Zi*Rp6%W&zU)wm*26s}sd1@~DLjr%6r zjl+xgTZ zTO!5}lqm6IB^vw;i2=V*V!^MGSn*pWZv0+JAN+AiB>tjg82*-IH2#@nB0g3!4WA*I zjW3qW$Ja=f;#(vu@!uuu@dW86JX^XQFPHAZ>!thg5z-@gM0yfGOnMGKQF;kKTY4S8 zRC)&=C4GdCmi~u7Abo>BC5^{lk*479Nwe@Tr1|&+X$d|@T7iErt;N?%8}aSZHvCU% z7oIHZ#q(qsf>K5z7-e*VO~xhklZgoM5vV3Z#t z*yN`P{p1%2Bji^JljXMvbL0;Q%jC}pzsp|}cF5xh2jwY*)AB6B6?p;Sp1hRsLS9Ko zkk=Ek<;{drc_*Px{*BNkhlss$0+Fbo5jhGDQLYdX^$G`G#)lE{a>H+D4>KUnC^@h~0N+A7ErICmMxg<_NF-aa!PSOR`k-`I- zN#1}?(%^t^q;UZ-c}4(~csvbodubxPmsh&w$ zq@G7vtzJsmtX@sot=>R6qTWV1tKLJoranZuuRcL}q5hi^uf9UbQs1T&s~=IS)h{TY z)iIQAbqWQe$)?aWMHHc?oD!g^qnI?!6q}}#(pS?<8K%KfCuk_tSsD&?kw#2iqft?} zX!O+G8VmJ^#z8%+L8we!%o>hz#=>inQQ>dK%}>c*fd>dv4B z>cOCP>Zza}>ZKr23`CVdIH0$XEJU z#x?y)#(n+oj2HUtj5z&XMuz?fqfmdEQK7%Y_@uwd=+Hl8^y*(Q2!=QY(~!mx8}b-| zhEj&fP{Xhpniz4^6<7ifbaWX5@IGa^uT*Rt0u3|M9H?lg6(X3wMJ{I0|jKwgWV+l=H zSt`?AmeKT-6=6bIUQ;q_pedU*%2dpnY^q|-HZ`yon>tvlO}(s5COmtmiOxP?60lF0 zl1Xh2~#4<>p14kLFdJHuFYKk9h|N z6TF{84L;7{1)t~0g0FLeg70%ef}eBj!Lgh^!D*Z!!TFpq!DXDO!S$Ru!L6Jn!9AQc z!5Hr5U@CWKFpqm6Sk65WtmB>!4&`1Cc5&|o_vii>Je(U7Jb{}MJd2wfypUTGypmfT zyn)*o9L?`_*Ynt@Jv{#@KRW<@J85Y z;e)Vl;qx$z=xrEHlpH1yWre9kMPWu!d6-pH7lw#FhYb;Rg^d&a2%90ohc6J(!dHrT z;TuJ=@SP%c_(72={In=M{IbX$en-?V{F!KIc#LRFc$#QRc!B7b@N&_@@K2)U;T@v& z;Xg!M!inNP!a3so;WF{DaIN@kc&PYNxLbTPJW~81e3bZk_*C)R@VVlo@MYqx@F;O% z_;ztw_&#xM_z7`S_(gGN_)YQm@W*0I#2YasB1O!O$PN+xB}XIn zOU^``ko*(zkK{(gEy?|eCz59oZzXRcQY8ry`I7XAa!FpqCrL>}r=&9Cr{q%vN!l90 zm41zoOMgb_rFd(&lxFoxxz@o_iFK?rz&b;!w=R%ctgEDU>n5qs`iC^qdRRK#dPX|V zdR02rdQUpr`a-(E8ZTXD&62LQ7E3o-YoyWE&(git9_e8#R(8_Lke#=RWLK_wnfYL+V;y2*-pw&*e=P>*>1}(+n&j9+G6GRZ5i@swj%j! zTa`TC)+|r8b<1;X7)6ndt|+sK6g4)rqQMrTXtOyLUu^>vKW(EFIQvuu)jm(bwl7x* z?Hd#d`%Z<%en?@mpHYO_uP7Y$dkVzFOWM8EG*SK0%vaeQEB!~lZ&LMh>{1PO98ryQoKuZ=TvttXJXHPSc&(c6 zNKq|ut80aqOZ0&Y1*1w3#} z4S4357x3D#A|TeWF(BEoD!642(z59o4~2lP4` z0x-@m0VF3BNO#f#xlUoA*clk8a0UlzoUTBlGcwTP935zLP78E97Xy9GPo3pFsV;C{QkOXI zsLP$t)wRxeb%QfY-Qp}&e{t5Szd8N;#$7+uco#`Saq%=vmr}!bnKTlYU88jM(`Z~H zHAdGIjm0%jV|A_2xLlhwh-;T7(se{L)b+P!l4NsV!h?>ukf0N;p+RR|6N4_gW(Qq${T6i76%};P zwIk@U>tN7x*O{OLxS6)z&t32qvt1+n3)fH6h!e|>@bZv`E ztnGAZv^}m+?N66ii**mylHB99boVSR+r309aIe=&-P^S)_W^B?`;^w;zM>6r-`7UC zUuvE1B(2Y#>pzRUOgqTkpdIf1q8;sqbrall-BhvU-`s)f++8{JEETixq*JKWoKyWIzL``xE?N8DF*$KCgJXWXxJ=iSM=%kDhgzwUC~ZFi&Y zfxAoh#EsFva5MC8+!B49J4m184%4T*efn(oP2TmQlRo4(5ZyS~o7L*M8= zq;GMb)pxqD>$}~L^u6vkdf1by$9oF(WKWfz;c3=$JUx1W2XByi*am+}&!G0`4SJ8& zVD|JignC98Y@R6wmuH^A=UHLs=hk43 z^^_PEdg=^IJ?(}So}Y#_9 zQ?^HH%J=9@?>rHv_ntnca?fy6wP&)a-ZR(K=viTE@oX}6cy^nTQWM)-Z{mA9OkyuE%e+*x$}2Q$ylS(~YcZR=9<#+e*c{;&4@S3+|RqiJkWc{Jj8p}Ji>e3JjVOTJl>0%CwtS()4WCIS>9^%9B+$xzW2L% zv6mG5o0k{7(yIzy<246Id7Z%v6duIgy;awEG$GbLozjs^kA@Ba+zr3e{ zPk65epY}co{@eRH_@Xx@__DVk_`0_;_@=ix_^!7n_<`Om8edFeHVyz$yY zV!ZuB61<~AlD*SH(!2{ovb<|Ta=rfxDe&$KdFMSD^4@znq}+Qiq{{m;q}H1p^3j_g z(&ViOY4J9Nw0pZlzIbt#ZZF&N-7B~J^cpM}pUr~z^|O$CBP~?lGz-JGz{2*ew(xvg zEkfU)7K!hqMee(7QTgs!)V`M%tuM)9@a0>~z6y)Q*JKIzbz5vcT&UB>4)yrtp@`2A z+RtYTjr8>o9qbzwI@C8UbcAm~=xE=X&~d*1g--PC3!UOS89Lo}IdrD)e&}r9tI)Z= z5w^i+4BPDU=j40?!nXTHhwb!D58Lfq z6t>s5Hf+CdTi7Arfv_XK(_zPaSHn*F9)z9ty$L(#OAR~kD-8R`R~>f6*AjNk_dV=} zj~IT-#|yvfQ-$C6nZqCXT;WfA1H=FGjSYX{n-%`rw z{tZv_Jr2+Gy$#RyWrXMXio*+hwc$m+_V5zl&+zv?N<_I&7*Xj{M^yVP5p_Oq#7Ezd zhz8$;h$i2!5iP!D5pBMW5goo=5naB&BD#GSBEI=$Wk-W7}Bdt!+G#VVj5)+a@D*wy8+FZ5r~^ zHUpvBXCXrSY(!)K6$!P^MSS-8$WZ%2WRiUmGRM9IS#JLg*<@da?6$8!j@efs7wxN& zJNC86bNhNE(H@25+BYEO_KirReKXQ+-|An)`yaw`Y)9mdXvE;yiP#-~ApIS?kvfXhIIp8>qoN*jMt~rh(j~vGk)Nukycbr7tIZh$9jx$J`<1F&i z@i#(oo=1ev3y9kJ4-)FUgm|5ok)h73$VBHgWRCMXvfOzC+2p*5>~`KljyZ257oB&J zJI;H^bLV{|(fI($bv{DMosW@5=M$vc`4qvqo*``4e~8@m0x`N?B6im+WPs~6GTQY9 znc+f_MXtBVI#(>R-4%x%bj2fQTnWf^S0eJrm4v)?B_rvs6r|XdiqyK&kakx(0^Au0 z)t!lm+*ydmosERKa}fU*1{vngLngWNk-2^=+y%&HcOkOJU4$HWzeE0U7bADwCCE#6 zDU#%u?|zR|xIZAx?lPpuU5*eu zZODAT)!uewtKU9v2XfNyinkMa;P=}51xfWQ^mZZDel32z-meJB_Z8v$x{*M?5I>Kv z2N~=)!Ed(j8?wxAgWoRScjTzw1;5*V|M_~61iu`=GQURO59F&K4*7ww{N#QHP!s7ovc>~Y zPt+Ntb0k1V*BwBb=Kyr!#O=tejR4&lzZMyE%-EI7Kv(tP?`LzkEVpt zgZmqNq6sic?fu|8yAMW>F3s_sNPtmYX}ph&!JtXQ{_}P8#h`0m-11F~#-PE*3%-y< z4BC16FW>)YSTu#a%Qtu;7QM4!gKzgmEPCL`2aM zEndd|h-lR7DsO!~5seHf^g70qQ0;{j@6Wd+RL*+s^@fpA)Asw`_RC~+O#5Z8QcOYj z&pqjlJ4`_<^8fUfQ>f^OL0i46c2m)uXRExM2sCtsVZOI_Hx1RDo#O4J($Q|(2=Cm# z=xFWMKHi~H2HMmb?!A7EfimZ6y_>8|baa8(n;6eTZw{t=_fBS^>KBkVwuyzlFn4;^ z>|~?MFVuU^C^%?8PN~QFl7mM4k?9#Zjf+Nh$9RgrbJ6unpLpJ1;Gs!n|9U13;-l_y z=RAX2_-JOrAE)6+a#j6Nri^;{E4 zP}SB*PeHB(z18mUY&s-GXDl>%PK}bG5$_cqBTJ5kj^%i)`Eqo8BHr`(i~>FH>2cqj zt3=rkn%qK*3caPRaDVGnp)1bixyNS&pwl`2W`&D^=;}Q$+>6(#(T6|pxV0lSsC?Z& z?kTz;^ikt6H;mJwYv=57tE#o=oZ?OHC-MH?g)uAKZ~xV!aY=LB{SFyWXP-%K=kG?e zF0)olaO(}6e_bbAn* ze&MS#yLd3_mNz>2l%Z(tnKEalcNm%`%60x&H5_d@k>I>|V+1;e|J?bkdL-I%^tLln zH5yIlTy#eMG6wy0keSoJ%H@bCHP-`CO{8Tf^0s1bE^uUv#u?>=;# zC|isMhhKACAGH)c_4KqOIOaEWgy(=G$i5sM_I8`&$ek7Fk%4O+D|M?-b=pEl?B&%c zG@lu0BZr_N;x62%XF`LleHnJRN zMr}doVsMU~Wn0mI|NLsNT)7SPaU1Oq@X=_%xiWjlxgF@Fpj`XE{(g$my9xHJ++FBH z=X3kwReR8q*xUAXoIlYCBQM%JpX@^e-W|2qOh173o4eaS79*J2Za9tp;tsX1u0DerlGXNk7tW!> zCJF6HGtZ-OH5B_f#YOb^nxD3+%70K4({4L+{W3b>uUcE&imRw9u-G=!eI1?hFx|G8 zcmr+h|JGJpcoTh>_sEv_?`<@2{&idUmb++j*BKi;;XazW=b)`$@I%xnjkdLu9;5Yl z*4cRVPf$$1#kOln&(O{JGi*0*K1U}m8e@|keu*CJ9bkige~s#nIBXN z)(8DQpkC%GD>S|w{ol=b*4GOvQRAQ~)`rd1C{i`t`p5BF^wrir)LX2wr$&XS8cD_)*!ZRyRp;ry!$$T?CU!F z?6ulv@crKRdG7nG&>+@-ihld=-|w{kuLpPjE}rz+f6ER=wY%|||MPcj)xj&b{l`{u zRjoZP_|H)aRJoal{WF(~RNeP&_YZllqvATP_P4E(sQQJ@^DhdJsj62^_BY$7uaX-K z_x}=MsCxXlmw%ACiR$%iZ~wk4%v4@HM}Oy^7ApJaCjQ$DtW_r_>iBnGVXIo+*6Fu6 z&|dZHey!hMJ15o2QAK{-eJ-l#hE%`Jd9JDxw^>7pbR*2=BjTGvlS|%Bd2`pzO7QZVf!(fw^pTT z*ywv#xIvZwVyW+?x0_T)7ti#qpS@M}!DgKAH^~mw($s;z6+d^W?q3M-J+ywWYVjDQ z?@`48)fgb9-E$4^=_~9d7pMx)#GcfkL&FV zD)rVxAO7M?s-%EWpHW^{Ra=_A`?R!PS3UUj+D8(4OEr7z1E1qp@2Vbkzv8ocLZ{2O|{tC&FA8PpQ`bNRzABuRI2Fba-S%3ttw|D&*z{xSarB}i}#)O zP}MJfrMG=egz8jGj<>iZT2*r`!Fy_MoT_Y5h_`NLqH4R(cWx|hGNwK&IWH0yIj>8x7fQ-R;3zsf4aAe zeT}Ny#xdRzUFuc82M_R08rh`EGwJF*cwwvRZkemM$({~X+Yc-6F*g`>-8s2;$v2Mr z$YP#%Q6^vgwP%ahFt%8IT#nmPTqWw3;vBE86J%=PuLLjkE(7(4OCerwo*An-YrcDN zGR)MqLtlG+mRhOz**)-z8EC71+jiM&J;ukuSElTsGSSCdexlltv1uTd1a;cQ@?#+ z?d9$|NL_nK-z#JLP<84OzE@?`2=$T?t)8=;#;9+4RC)UB92xI_H$<)N3o% zGl%W-JS|+S?&Z75(|+3qb*SYsPveTsYOZjW=kj^m)s=PQJS|gqsSoB1^7NdzPaPiF z&GUBjLAC0eyXWdLN7YN7+IrrIKB4|`)zH&*;u*E}n9$QO^}KrL_I8h1^De22R{Zhc zRa{kbW*2yfx7}37jZ5)ZCA_PiG$_Ku^V$RT@ov98MteR{Z}fQY5vqNrHgI_2ac|Zu z^%Aoi9x2Ul)oW#EJyu@&sP+;b^qAT8tNJ0c)#JaEAL`ha6&@3Isnj3p=6FnV3{;P= zn&|N@GDQ8bbg0L+Z4v4>g*`nky2PlrRZW(W);ronoAO6}x^AKrS^cfqCaJaww%XJPKkAD>Ig_B)0 zCJQayH}z6#wCiQ=vz@#&0sFb`w`6{rHRqd^0i9hnEALk*U8;I$yguY8*XH!md<{-e z$`S`?bkakVf`}m+hwAUje*#BnxZF3&_TOVPFU%e)TYgT^*mz%6j{fzJX2#G{$|lux z&D=Trl+8i2HC|gcDaS?4*Myy0rtC;wtnqq2OUWu&u9+J=UOA(7wPsfSV5OL|LF2;o zQ0f_P(fqXXR4%7GY>+0J4cw!dG{abFJ?nsG(hjk5>$W2r#~Yn)E>})yG(T$H+`gRA z_~aD1?a#QNS<6Xx^I~7o>~V>9^THiBb4O|14o_`&3)ek&7~{P+!U{$Xexi* zcH5f!Tw_vl!Og@PPgd?zG#jwTI<&M6ww_Dm&4jd7&Tf>R8mGX&wH{ z_2|G(jl=$TuD$NFwTf?#UHkC_T2aGw*Ne+^w836yT?1nDvbmNI zskTeuO4q+~EA2{$d9FG8?6mvmPj;2nJ88Gx8}52$shf68es9;A*`8XSldtQRsealU zOPpPE;{&wD&&*w~j_;*iS1onD728ky%Aey}J8`f!dV7=Ne9CZbysBKWcg`5?S5c1Q zd&vat;Ry+fK^v!N18#&U%-A!vkwxDXJ(nLN@?&|xdK zM?BRoT-4}t`M@jfg5PB>9lhRb$602(ylDQcRc?!SdGzszwmvD?rDU^O`=ZNtm-XF) zwUhsS?J~GCTwB@jz-4Y=jCS*st1g<;iQ4Kfr(D)dPt#7b+V3)7k*)o>Z?nsd=6o%; zc)5#pc!_rK=s7OMw=1>V-cNLC+FYx>YdOqi%(y1)_d~s0DwOToh-z<_7!fNlcDj>G zTPZIvJjl#tMT9u;o1fIh?u}mH-MefTt1E_qyJbzzbM~19PS{)ST(r_U(5fce`R#Ov zz})!>&YBU5z#EAn&ZfOR0>=;k;r!0WH}LO|H_qo2xJ$_Ik@I`IUV+1&UURmv>K|BW zcg8u$d`RHVYX_X)n~w~X8E$nhv>X?B`}9iZ>2{L?-Nf^p^%c_t-yNRpEb*BW*o`~F zc|@;;f#3J{aSj{4EU*vT&-vuE)qy|vyEva+u_3TG*U~v@&(^^2hh@&QF6|2JDdssl zzuF)8?R1NiPuP*bo`zLUJBv>Se!rIIBov$v>}Q|sl&H8I82B{YDSyV5Qg z;6{VBPD6hN2HHJb=ybL*EHE)(nv&OfbzmrmC@zI*UD@PV?} z@lFFb=tpR}W9Tq(P~OrQN6%Y&L58A0$LI#bpb1aEI6fb19&~fmOGoW9o1n((dyb}J zr=VFEFFQV3?iLh}W^7HQSJ0H4y^b4vy9AXV+2r`&az4k74h|K*Nls#aE!}h(}pzHi`4m0h-f;NN?a#*j8 z4q9@qyTi|Ai9wsEdOGx$rw84$b#VCeH7BUN)WjiqaZ%9t_qqOM?BT8^Yi&$3yLZPmu<1ocYtfkC9<;g4a9y z$^^6Ef4EQVqb}J5H>cjP&zbHN{NwdGdj~sZ@Png=?Jt*l2fv!P!@k%1uE7~S*V@bX z^$PYhS!8cKZb0z;x@q>K?1lyRjvZtFrhasA`>TQWL&7Eo=bq_iFTOV|xO}aLedmrj z!Il&4?QN$n3f|b&#C~1Z6~T4py7qsJ*9Bi?SoSwtHU}>)Zm`>ywKI55beY}$!2Q8{ zK4;r~d3iKAXJx_<)y*zR;IA!}!yOmq61>afv&Th)GJHZ#GJh59n>rwEV zp*QW`One^Ph9=o|)Z5_o$|H7PhkOn;ve{|3Z{W}1LW6a7>j!9q^F@p8&I}9-ma%5o zB@KxQUfwd+Zs@3_;JVsDcKH)Cf}dA*w|hD(FZkb5PrGZ&N`hY$IoQ41QWe}-U~1QR zq&|3Ufy8e9wbo$ELbhGgOD3eHsLA$2AU{M@R$+TROE+X>Rj%!SE&3sL!4yV`^dWvgs8Q=CGk>U^|ayF(dr%jlWyz`H&n=5}{%`-BFBgnRsJJEyL9$lIRB zZ6DbT3W*-E$JTJnh!Dpa8*Lx&9vAX@Ta|6t{}8-pQlZeTpIfGvxCi(gNC6|e@tyQx0r|8yGd>4ueA&PzK~(Pscg_>rotvMBALhsstwoceE zIdsF47uKqd8KI|M+_MfnHb1nc{<3w2$+FN}y-!)YJy{ca>BxTT13fl}ro?TrZiw0$ zy2xgg_5MW%Li?&9bk;()_1v$4p?!WeS+y>S2wiPa zY4yw`KD2skp4EoX)KFD&veo!qIiUpskyb>}qU_WxMs7F!kta%frm(utDJk zmbL{u!|X<+S%!rk2%8obZF%s`@vw@KftF*gp9@Qm`fBNN z*4CCY#c1$%eU~R%q{aD$N9l%JgjIGAk9z&vLL=@U?*Gq63$5$0a8}1Ni^vgU!~GxLwa8xe zPk7Xr%NEV&XN5<%oU}0ex-h)kqx}~B^H+q6CT+D?E8P%2fV0}-VbAU1h3^(v*gcg%0C z(23A{cFEjEqaX3#wv*;}EX^a{58rQYztt|n$6~Ab{X|8CUDYac$1dIx2h|JAA6^QG zn095Fxl?POi2G~Cn%|!@Bx3Hc!REHXqa)7S_cXumJvpLVr?&0dW-7V%tBW~Q$_8^M?5 zn62%5B_g#s(Jbuy?Fgs*a5L*(k0VN>;A#AL8R7E%liBBfA0x7#zA$SK{1G9)e&4Le z=)j1dC$E~VONxjn+H=P2-n@i}V;c{dMO39nJXyZOta?{|#K8IM%*1--5z}WZF|)c? z8&N%ZmYHinYXob;L^EX+EAs5v;bu-tM3J|~^ffbP%Ol;!b}{R`Wg6LKywWVAw{7IF zNp@zhvs@xWrWDs(CF@#DuWlL=S--Q|G{AODHyyWQR;1(OSkrLjqR4KagH5|e86CCd2MC6kmMbD~DDPMH`hmqbYhA28`{wI*ur@ogq! zRGMsW{1}CS*yMHFIUO-;ht!BKN7q$ZI%(NQM`@l4(uCr6FE z)n>fcAv@}JOO3IQZ*kPIe@cvl2UJH1KV%vApWGB>Wt3=qd)eQp(9Pk-xqAfBI%z6n z-W9#*f?hDC4l*ks&!V_dZ9?G?rbK~tm0>(4h9*36A|Ix^Kb(`s4t#f~w?=SHoI zzP$;J#I9}8L#lfkUw*YO`si|BO^D`Pj5oSF zIV0N0F3f1vt%B&FSHF#nN-Ltx`h7CG+@&E}68FNW{y<0c{Y4Lq+!A;(>8;m{x;sl_ zKAbyeWWU`w#@FqrQ9-nI%mnRjqunkpF~)N@8P)9dirLk%!l-9PK+Lfl^NnV8?-$df z_cWt_t_+JglRehRxn*3;u>(VlB4B?BE8+Bq_9pefCAiJS+TaIR0;PjQfK(hF$mM z#7tfI#IS-Xjq!HAZMgnmP0YK}e+@%LtuX~JPa6I?%Z^oTI$&6ArV~4|&vwHX4-8@t z2-g`7@Ue_tmaxR|(J#l?j=QrBQ^$J5_FFgEFg3SJtnYwPhEF#2iH$cLXgEk`XsknN zcf%L=#>P7S@;1!tIW;!%l8a$s(%jg9wbq93HY|%BG1ACzwEp^7sY2KA-P`T42l*Vs zf=LHrUlg?%nJ36DZzot@qom`{t1y=VBuKp{zsjpyAq=uqdyer^8O;M(@` z*eR7K4LbblW1r<8FmS1EkNudw-N58IFK%1nI)jMi(zv>qr3S;4CUMSDa}17F+Qi8t z|1miAMiKWuaW`t*o%N$6?NML007Db?3tMEuCOeYvg%c6TPl1(n$v zd|y2)E~vr8z^w1$xV>yWgKqLQaZNJ5fob8EI9Iz4{cm6Q#+mxn>sy~c7N;3fuHS#f z`8egwJbmXO*W<=*NYxLse-P()GDhE%^&&3eQLz5_+z)YnnxFdkPaOVlef95GY-GEKK=~x__OHa&lHb8n?C-G z@%XdqCkyq5ZSP2=&}%JCY<fX}uZpYa5I*5&xjC*ZR$$9EtB-vv3o6AAck$nhOXz;{KC?@R)| zJ2HHS67XG;;X9Rp@0JYTu>^eAWcbb{;JYWocQ66pMH#-63HWZx@EuLScU6Y(Yy!T! zGJJ;<@LiVSJDq^Siq#MvXm8I*{#NQN^h5oePOXH+82DjCkKM4VkRoMDML z%Vapy5^=W4aKfsDc#969` zGc^%ss~*nSM4YvHICB$m_UhpbPQ+QPhch`5XR{v8=tP{=dN{L_aCYnA3{S#Yu7@){ z31_<=&iEvp^?Eq-lW_Ly;Te#GXMrA`2}yW1=;0ZWglB~wo*7AacIe?5l7wf89-b*l zc(&-_8Iy!(jUJvkNqF|?;Te>KXOSMBNlAD%>ERibglCl=o>@tFcIn|6mV{@S9-e7Q zc(&=`8JC1-ogSWfNqF|@;Tf2OXQ33Vc$rFcdr;aMrgGcyU#PAQ(DNqCk@@k~v^ zvsH>`Y%-p;Qap2$@$8l28Jvt~v6Mn8Je#F>MknK0EyXiC8P9Ghp5e)OmP_$WPsX!d zif4Q>p7l~Z^ON!HmtqD;#w;MkOpuJ(K#Cb58MA^EGea_F2PtNVWXuv$%oNF(Eu@$+ zk}+#YF>@qi_K;!*NyaQ9#Y~cn*+hyNB^k4d6f;XQW)~@Dm}JZ{Qp_~Tm~Et(ags6X zNHOyyWA>3^21>y!B*jdWg4sxd87T#`k_0nT3T7t>W~da*QWDHmDVVJ!n6XkYYe_J3 zrC|1wU*Pj*i_8263n!zm~ADPaZ@qtN-*=LV)m6_22RB+ zEWu2iirH9#895cRvMy%kRLsu0n4wcKOY35$PQ`4kiy1o=v$if~?o`a)x|qRJF^lVB zCQrp|u8SEx6|=f7X7*If?z))aQ!&fyVx~{UY_E$MKNYjSE@u8z%>KIA0aCFG=wc^G z#crUB9U&FFf-ZK3RO}AA*dfxeOXy;!NW*TSiyb2kyM``yjx_8Zy4XR|u#4zoCrQI@ zqKh3R4ZDgic9t~kF1pxZ(y+_uVy8*NZljAGCk?xfE_R+Y>^{2Kfzq%G>0&2J!)~OD z9VrdFk}h_pH0(~g*rC#}OX*;zO2clYgB>dkyOs`it~BgkI@rO|u#4$nCriU_rh^?V z4ZE5ScD6L^ZaUcE(y+_vV5dvRZl{ACFCDv{4tBnD?0!1f0n@Py>R=~K$8M;D9Wfod zq7HV(bnK2g*df!gOX^^!Ovi4igB>#+yQU6y&UEaaI@m$ev5V?pCr!t0s)HRh9lNRy zcGh(4t~%IZ)3M9yV5d#TZmWYGHyyjK4tCyj?7lkKfzz=I>tH8N$8M~H9XTDlvJQ6U zbnMPL*rC(0OY2~#PRDMogB?2qyS5H??hNeSI@rN8u#1balV@Nz7h^}yz^*RF&YpqY zU5p(*1G~H!JADRrdogzW4D9-1?ED$n{l&-tGLQv`kqKlV8xSKS$Us&gMrM$K>_ChR zAp=>07@0x_vIQ|Rh74p4Vq^{($R5PVATp3eh>=NTAe#^)qsTy3Ax37Af$Tzz3?lSWk;RCS$z&p%5hJ6?L{=k4W|N8RMvM$66IqTJnNB9M z9T75~Ok_PGWImb5eniNCGLZ#|kO^fX8xkQS%0yNqLS~eS>_~(RDHBJEh3ra%3@Zy+mI#?v7P2i7GOjFS zT_R*&S;)Rb$iT9Yg^7@fWg#0AAtTE|RwhDbmWAw0gbXbUS(*r$S{AZ35i+(cWNjj3 zZdu6QM9AQ>kj06R$z>s%6CtC^LRKe2W|xKRPJ|3E3t65BnO+vMJrOd#Y-D{RWPaJm z{zS+CvylagkO^iZ8x$cU%tlryLS~qa>`;UZF&kN;5Sd~&vPB^>#%yGbLS&BF$R35r zAhVH03Xw@>BbyW=qs&HDDMV(OjqFm03^N;9rVyECHnL42GR|ydokC=u*~mVH$Uw7^ zg$j|0W+NLFA|uU4Rw_hhnvLvKhzvCwS*j43YBsV}Au`q+WUWGEt~tnFg~(uYki`m- z$>t!N6(Xa}K~^h7W}AcTR)`EY2U)HVnQjiUT_G~w9Av#hWWG7beuc<@bC3lKkqPG@ z8x|rX&OufzL}r|W>{y5lIR{y?5SelgvSlGM<{V_rLS)W4$exABpmUH#3z13ZAe$B< zqs~EAEktIWgX~&}3_Ax|wh)hc0W$VnWbFcE?zza`1<2rYk;My;$>$=Q7a*h0MOH6B zW}l1fUVscg7g@dlnSL&^eE~B5Tx9(MWd6Cx{srg&a?u3{&f2+&F7p_>q(qsT*7AwXx5hwegv z4kHg;h5(&L9=Z(yI*vSa9RhS7dFVa_=s@z&g$U4zgD%;iIF;Ls!E`XOoZahK~*>A6*U~ zolZWw9X>jqd~`j0bUyj$e)#Bs^3etH(Fx_F8{(rQ%12kkM`x6e?ud^LDIZ-DADvP@ zx+Ok3rhIfwd~{Cv=$`oKpz_g0@zF`;qnqNRqsm8D#YbnAkM4?(4l5sB79X8fKDsSF zI<9T^b*qS^>H>K03An zbZvZeZUyMx_~_sY(8cl5$rYfRf5nADv5#LUg@6biPICetGDCi_iu0 z&e{51n!mx@8_Z<|1^>Jao=Q=$?7#po`E&^Uz5b zp_}HRqb@>M%|mBhgzlP$4!a0lHV>V45xQ+2I_@HL-8^*OMd-eH=)jB6h4avf7oi*H zp(8IsSI$FcUWD$PhYr06T{;h)dNI0n9y<17bnQHJ?#1ZddFbGa(Z%!7$rq!W=c1!8 zMpw^8XJ3r&o{J8@7+pRWoqjR8eJ(owVs!mnbpFNY{<&ZPiopVK!2}e84d8+iC5$D4qPw~C14-8U?57sLU6%Elz@%kf{`czE5QXbQ37^? z3x=WuECm-#MG4pnE*Ogvuohe}7bRdXxL`0!z+!O0WR!r-;DXU80jt3Uvrz(egA0bE z1S|&^Oh*aW4lWpv60jazFdrpgKe%8(O2C3}!Gx584dH?jDFrLS1v63#c7zLtq!cU( z7feYh*b*)nlTxrITrel4U{APUP)fm~aKWUMf=%IqQ7Hwh!UeNZ3U-AHhNToN3l~gF zDcBY+7?)D8E?h7#rC?vUU|>qY!f?REl!A@nfRQN$E5iXZQwny51BRv)EDZ-tO)1zK z4j7wKur?epH)UXNIACzfz~XSgh-(%D@6~zyy_n4dQ?iDg!IT0W(wvc8CLps0=I-2TV~J*dh)XqcX5Y z956>^V2?OpkjlU!alj;%flcCoQ7Qwg!~wHZ26l-9hN%oJ69-IFIoKu+7^iZuP8={# z=p+MS21z0*Zn7RtEb!;$p6=3byVD2iw-m$^pRf5H1gUPD| zo5u#DR|!^+4Q8(r>>e8oUnN*RHkiIjuzk3td1574KQ@@ZO0a)yFo2a{0oh;zE5Qb` z!3b7@6=Z`MtOPsA218g0mXHmmuo7$`8;oHkSVK0L!%DD+Y%qwGU=i715-Y(bvcV`; zf>mULS*!%R$Ogk$36_x!rm+faBO8ok6<9|$n8zxxk8CiIRbV06U?Qu)MzX<3R)Ljd zgPE)XJIMw^Sp}Ao4W_aRY$Y3vWffRUHkivQu$OEwm{njg*CPd1p(DzKkyFrZanLD^tJtH6e`!H8Ca6=j1Ntp+>F z218m6mXr;qv>I$F8;of+SW`Bb(`vA%Y%r+RU{Tp%QmetHvcafUgH>gNS*-@U$_B$) z4VIM+rnMSuD;tb!HCR_RnAd8suWT@|)nH-SU}CGm#&yc4Tm$x*1qQkXEHn#DbPd>O78vOou+l6r(=}kHSzxGZz*4ioRM&v5W`VJ; z0c*_yb6o@Wngs^C1}ruUOm+>}Y!(>p8nD_dFxxd?w^?AgYrt}|z;xGu?Ph`Tt^w=K z0`px1_L~I;yap^d3ru(|*l-pY@mjFrEHLA>V8>Zt$ZNrpv%r+sf-Pr(F|P${&H{5@ z3-+7^2E7(6ItxsCE!cDx81-7P>MStpwP4p-VAyNHva`Un*Me&^o6UJLe} z1qQwrEIbQLd@a~`78v%j7}!1ULF?Pr1UuLJAP0`p%7_MZg@pbjno z3r;{C+yE9FfjYPXEI0#oa0gg$27zha2V?0GO*w@)WdCH!EvaE>%fBZP!IQk1qY%YE(8lsL_ORH z795FsxDqTl6ZLQ>Sa2xn;Zm^RRMf+*V8OAdhik!tb5RfXf&~Yo9xet8PDVZ434+aiM16&XWPDlgX5C)D&16&aX z&PW5?5e5!P16&dYPDumY5(bV*16&gZ&PfB@69x`S16&jaPD%sZ6b6n;16&mb&PoH^ z6$TDV16&pcPD=ya76y(>16&sd&PxN_7X}VY16&vePD}&b7zU0^16&yf&P)T`83qnb zBU~B=PE8}+8U~I{BU~E>&P^lS8wL(eBU~H?PEI4-90ra~BU~K@&Q2rT9R?0hBU~N^ zPERA;9tMt2BU~Q_&QBxU9|jIkBU~T`PEaG+*&QcTHB?b;t6I><+PE!-yCI*gE z6I>?-&QlZICk75w6I>_;PE-@zC|<&QufJDFzNz6I?0=PE`}!Dh7^K6I?3> z&Q%lKD+Uf$6I?6?PF54#EC!BN6I?9@&Q=rLE#|)y%}sE*7&u+caJv{dUd?d57&u?e zaK9KhV9jvB7&u|gaKjilV$E>H7&v3iaK{)pWX*8N7&v9kaLX7tX3cQT7&vFmaL*Vx zXw7iZ7&vLoaMKt#YRz!f7&vRqaMu_(Y|U`l7&vXsaN8I-Zq0Dr7&vduaNig>aLsVx z7&vjwaN`&_axHM>7&vn+aOW5_)-7=97&vt;aO)U2b}ex27&vz=aPJs6cr9@87&v(? zaPt^AdM$AE7&v<^aQ7HEd@XSK7&v_`aQhfIel2kQ7&w0|aQ_%MfGuzV@%sg}zzt;J z2)4i#WZ(?8z#U}Z5VpW2WZ)FGz%69p7`DPSWZ)dO!aZc*AhyCqWZ)#W!cAo0D7L~? zWZ*2e!d+zGFt);FWZ*Qm!fj;WIJUxdWZ*ou!hK}mK(@k#WZ*=$!i{9$NVdY2WZ+D; z!kuK`P`1LQWZ+b`!mVWBShm8oWZ+!3!o6hRV79`=WZ-1B!p&shXtu)DWZ-PJ!QEuw zaJIqaWZ-nR!R=(=c(%dyWZ-wiD z*tWy9W#HVl!@XtT;I_lXW#Htt!_8&j=(fYvW#H_#!`)@z@V3L{W#II-!|i3@__o9K zW#Ig_!~JF80Jp;hX5a+3!wqKO2)Dx(X5b8Wz#V4b5O=^OX5bWez%6Fr7Q|$NO!=MX5dVBz@28`PR_#>xA3Q!13;c>&?LV?j+eA4tOVAa0X6z zC){ubj(8_raR$zKC){xc4tXbBat2O$C){!dj(I0sa|X_NC){%e4tghCbOug(C){)f zj(R6tbq3CQC){-g4*OrY>*0{x95l1`hpSxbzI1`oD1N894TT;o38B?*GEQXW-!fg^SO?$^Q#CpMj(Q7p^`7 zXa6tUeFhHyU%bo=oc_P~aTz%Nf8qKwaQ^@Q{(t-$`0t%(bs75K+w9C3`sbV8Ix+O` z*9`P!=+`St=)=&jpSx%zL%&}_;}nK|f9;Wl4E=dto33N%&v)g&T@3wscl0>U(4T*5 z_$7vZ9`Bj=8T$Fym9H53c_VgxXXxiYD-C7n^%!+Kk)hY;uU8&Juh-MxRoF;a%*gR= z485NDxdIlwzU$T-vgq}$XWOyp^!b#l-|7QKIQ33FKV ze(Ee*$)fkSYXfFByx$WJ9b(b@KgZ}ii#`vt9^PWn=VN4-XDs@>C;~sR==0MsNz0`aI^_bJ+Cx?DtlWO`q4J{Vmz_`TZ87VAJP0 zbxs#HeZKRm`m^ctp0H~Sn?C=qbZ4;X`>^5q5;lE5Y}_`o>HG5T^IkT6e>{htV$=8O zY~ocmeZNu`JYv)LO;G!mP2WHBy}#J>eKe3pu<85x=Xwg8zOS!c3)%Gjo&2eWP2cB? zL7i;+eh-clbLjhiZjK3uzW+b*w++#G5V6ghL+8Uces2z)7soCP=g|4l&GsJ-ohO0M z=X2obht9hQ`y39Pf6*^0ICLI9@7BVh^KqVr$EEYKYP3F=&d*6H)?7MI&(6o+ ztAO+MK}7(U&f8O)2XX2A9gV+ZfzIQ+W3#w)K94e3&ZYDE#Es2dI=^o^9pKV=e&FR9 zE}iea0&Z~Wybu2MgiGhY)36U*dLB%QQE}<{FllNOm!21nIcZ#aegrNl=F;<|OLZNW zo-Z3WGdz0U?C;R!(er2aK{FmbkAynTJbFIuIp@ox=at5!FOQyI@i#~E=y~?iVJeTF zZ7SOyjf2yB==BMa{z5<%3>c@=|(0mmaF;zhG z){r1^%B=HbQ_{|RY6_Qu~TNb|D61htUn=Q~>5YK?h1scX8B=IakniiI?9_cE^+ z()_*r1S6t(ykEPni01R}E6qeSuV-gCiD-U*Jjz!@^St5rJ|dd$U6dn5H1B6#og$+7 zKR~!pMEgLO&1*%pA0+1Q6w$t5I{ui5_J@ui|B7gzIN)|qMEk|lOE2+PQT$}qvA>CE z|43OCETVlRJ0)I3`^lk!IU?FuLSIyfXn%Qb(juaL#(f`8O#997GP#)c9nM5+G3`Io zzPX8M9~$8hAg28&`S?IF?Mt0CW5u*T{hm5gO#76@ucczzuVhY}#I$eSJibp%`+RqX{KN8cvrm}n|ru}W;-d|$c=Vs)Gi)p_T4M`ExzBlqoftdC`dvT4J z_Q6vtI>fXeo{SLb(7tHpVXQ;@C!&# zBX-uM{e070UtQYQ`+w}COZ)pposqh<&##_4MVI#bsP_wWY2SY*T&qj_zxB+Wx|9b< zUmew@d|*HRE)dEKwokmPOZh>=gBQA#C)723(WQK0!;m0d${RLciqob1p`|cOm-2{C z|8iZ*Ck`BF(xtrOSS&|E`GwR*CZRk-zS2@c`NqZ13JK*M|8l!XDE}}R*Iz<;i1hks z3FRY)3#UmaFWKR>SVH+p`PTIk%2Se5yCsyb^cJ6xP~KuS;j)DCm#tUtODK;Sne$3Q z`OFpP?-I&uW~~g7P=0gmO@f5-oUx5L63TaW^r)0j-ea}9MMC*c7Zp!Rd60&qFQt4a zXt1@E@}fRR+@zErxrKChje3;#WrXk5qx|n@`$;{@1Nk0T^(Y^FKl7m; z<%J<9-sn+&*zfBPJ<1cUOG5Q1Uz}ro4V8ReG(QyUrOna%x_GRikcE(?%R-q~?>pp5cQ>F2RB%0u^L&5%((I)=McMtSKD z*NrmDPx)i^$|z5*T6a=L`Ks@~S7em8#(#Psqx>}{^|g%hSVh}+8RfHS7NIiAYm0j( z$|%1bGb2|RCBQ=V<0`$|sv_D-8`a>~2A_y)@<|L!{|UQT)V)ydg%%Et#TE|*hY-fMG{obvO7 zhdBC_r<-5Y)2DpBP#-fx^UHwxndXn-2GrNY|Cek){Y~lhd;{up zdY!5^pnfNG7yj-U^gZWR2@I+Kxj56nkout55jKX@4-M(2G^D<$!7;#)`lC$QKtt-2 z+S|q$Qol5@Xu2WwO}WvF4XJ;6_<6k{^-*{3>^7u+D)z{6L+Y!#uD)bQ{Z;J5dxq3! z-Rbtykov9rmR}92?@Ij}Xh{9nfV@~k>cg@$nTFJlJ%3PYNPXG!gAIn%pJgmy8Bw3s zdw|4<`n6~qGb8HT&bB)mQUA6t#oLJbxI6E98Bsr1b!wOq^>xdaOfsVW&Y<61BkJ=? zO;#FFzgJPU#fbVoi@*a$)cO1)#`x#UJnYn9}G4-J-gQgl&KiVW-XiR-+_n0-t)SuqGxWkzGREMcY zjHzD@H@{#^ee1=HTgKGC?!NidnEKeGvpyPAKl|2FZA^V_TUw+s^|uSJq#9G7TQ;fC znEKr_vKnLRd&h^j8&m)5b4X}HeXvI#Llf$Uhcw!lP+z?Lh0=ujmx@NW~NO{gEA){$mHeYx(VA`|M*<44z;P@n#?zQct2 z^&8hjrqs9J>}zC7{rl^DTT|-e6A!zaQa`Wj+Rc>u`iWr!O{u?swtTE9_4x+k8K%_l zAAhpgl=^=8koBh2|3A*#WlB82h~39bi4SNu{nwOufp2f`m=Zs5WaM*G;tA&De=;S$ zV9<7rDe(sWvS?G{54;|xnG%oCrF)Sn@d<+?YD|e&m@~V>l=y}H)j~7k8D8!&G$Xzt zUutVcyo1e6r5W)L3*7?Dh=+Lfaex`|5v&1Y%!rqm9x=^~_=(Sx7nu=HVUe}gjQEO! zi*}k3Z}F%6h#B!0^VVH3BOW8E;g%Wk8Kbv7H6valr0s(l@f(A7smzGyP~Ds$pj5_Gqj6VKwe>!3ODEhj6^ zm=o`kJ^i{l@h{4dN9M%Ctn+_sPJGO(+ds^Smnjs5niD^xzahb#c$$FpY;)pkCJrb! zC*Ee!lSXsmZ&pg!7R2K$Unj93K4)fvsRi*m1G_p}5Wi!6*~@}>o{GjE7R2|woIJ#W zc%KFD##<2oBbLpwARg%cilr9B2YCc-upnOOKbt)k#19#5J#Ilf(Yok=Er>7r;dIx6 zc%zo>&n<{Qa)|z9K|E3~dyNJ0Ndq=USrD%j5SVH~{F13rp#||wMGO8|5Z`p?O`8Sr zPD48Rmc&1$4A-|L9%|A>D@)>|zGW&biI>uK_O~Q{YUrxImc&!7csIh5_^PeVlP!t2 zTGeZwCGl4y_N=rd9!sj)Vo7|~7uEqw;wB_>L5$v!Hz$UwIn`lc6Np(@nS~CC6>gGy&73(Nj#ZyZ>J^kWyju$tcW)Y zEi|+u{;bs4){1zvvLQ;W#Zp1|rmj}RtDU^x--`G(_n1*u#IrqZn_@+Lo6vcI74dEZ z$F8;_{%z)#ZC1p?jlXr!iugE3?HMcL<>E@NSrI=sOZSl#@pKx`H&(>gamRhPBHqqs zZLk&bcSdL8tcb@ec%ErReBQ~>5-Z~MB!zWW#P2Qn+i68S-xX7_HSv9Sy^XAi_uDtr z)|&XgZnKou!~+Jd>uODWpyE(}YvKjxULIvl{NSo5Q>=+69Q%2`HSvYK;8oVd8=g+s zYEArMdCmcA;t?$>PFoY7Xw`Vtns~)Ooe!*uU%bSBZB0C*MDop=_{K^4LDs}Ot}u?Z zCjN1vS%x+7kYbBsYvLo%TGUz-FIiyTVNLv`z)WaEJY|!SferDMALQ0H#9Q{&b+sY> z@)FPAhIq^`9er$w&wNrp+=h6~`DK%Ah~F&AnqxyeXP3C;HpF+1(QdLK-qYv9UK`>+ zGaj6`rq(a&ab|AklYaBPWRJ-bh8OFZkSd1ki6w}$m~v?bnE$I8o=_*cD_ z?zY6kCd3c2B|dh>i?O!E%icdU-In;-=Q9`C5>LCycdae)wVnJOw#3^GNjqdq{O#!H zXKjhcHQ06CmiXMuqaN83ubXQA#+LZql;Ur;#Pk09F36VnUdirQTjG5O49&15{?}Kp z*p_(Uti&2y;)4fWZ?`30c+nhz9r45c?Dg%4Cr-?_v?IRQ;em@C@y4zTeC>!oF0t)x zM?CVJ%%OI~C!e}9!H#(44HIVB5x=abv(%1w=K1RNcEmR?-@40=cxQ#jQ9I(Fujib% zBOY3P{-z!A(YFRZu_IpEv+k`O@zd+>{;(sSddZj&JL0SLTI1}9w_g4r(~kJ-&7(`~ zh{yJCsI?4VzCpkPmRB z02SaVRvQDkgqUWpXEsY!oW>Bj^r~WCK)-B-@py9btK;*>R&fU@*jNb{2j@M@EzON zk^G2=|Asq~FY%W>$&vhti0QK($*1srv(%CN3LpLkNAfK~rtNYh|Dx&H5l8Ydezu=; zBtOGq)D1`SHT14MawLD_YSC*)@;Scxd~+nfW6h30NAf+sYN8#<|F|Yjb0i-`IM?>*_>) zO7-4;PUNeYejedO{z`1+Bq#D&%64?X_*uGE>jL~a3cR@)W=;;B>?Kl6CWBPa4{W}SWQM1IYkPhXwLw^^O3bt3;Jgca>XKF)K;R44Lt zEQaJek*{O8xYCLIoy!NCoXF?7cbDZ%eow#;9cS`=CM6p=lmF9NZR1Qnkc+_0nf#!1 zOMhqbg-m?J`YltCzxT0oy@Gtcy01GG;t;eFgb}Z^pe) zkS}Po)k zv+3hq$)CJmJKdFhO7^jZuH;vSTCH{^-?HiT7FY5wPY&4UN4k`H>-G})E>P|IsMuH=hy z%*$NKA02h2&Xs)9M#BzQ@=G~q`EKN!t`*7L$Up77&&-W{)YVP)ZsezStZ;WDU$s1| ziyQf?J;wEQBcHYS*DyEoTkAX~xRLKV>)H%A@?V{Ji`>YE9l3h78~L$OiCf&rmwnlD zpBwqJWw(#JkxzSoebJ5l+ARxix{+@iq<-W^{_Q&3*KXwFZrS<8Z3O(>q$IT)`MPJl zBHYN|y?;2-jeK5NMwT1-y@_5WZshyc?W=Jk|94qjs~h>i0d`y^`N1<+OO)gbr+zV3 zl0W>MW2+>eIB}$_lKkSy=Y5sr8@naRcuH z%cG5#E6HcJ9KS(HeskaBJC)=+e^4D#lK;G`>9mr3=*!A0O7f#Qv+pX&m;QbFsgnHZ zs2}f?yL_UlJNe&FSKGOh5B~9pn>+d8(%XLS@(e);V3DemN(d$i7VC;xniV7WW_=>O?&a3?=~vgJ;9^3_K;9&#st{fOIX zcke6`m%ck<&?m0EZ5_PVp3?974gYF+FF+b`-_Ys6to%Nvm35tJT^`QF-2A#X-LH8GA z&w1uS_ZfV2fA2x}8-zD~_n`X@ELDLXbpOHAqfs7oAHs$)$sTk+!dCqp54tbmb3%y+ z-Jjt9Z;c1tr%*bv)r0O=NR@Fs>AnR{gpMcOzp(g_p(owP!0Bz}N%u3P)H-?6eGNsA zJU!|D2KQ+Jo^+qXQ&B%py5C{$=V6|7-@~Xy<2~vAhqbclo^byS!oJM+r28SJ&s*V1 z_eIzWHhR+i5th$(deVIoqema|r28e_Ri5&s`zA)8yyQvuPguC#_N4nLthJ9l>3)id zvtE1BeHGv9KYP;s6;qF^Jn23Q7wa%jy5GX(b(|;NcQL(Rx+mR#@iQvllkUTqIHSUo z?#D1Is`sS(GGuEyJn8<7fJUAd+<(Kf*0NI5t};Qi|+eq7`4EQ?*AD4bA=b( z2cq)W=tcK~EW5tbi|z~QB{<|o_lNXYcgl8U@4+K4x_=~% z|H_N*BYC>ylNa4jazE&o7u{D9=n&#X_m}AHiSeTQO!lXwc+vePmfpEubl*wVp;9lp z|0FoI#*6MlNm90Y(fug8JK5fJU&^vDu{YhHQf_SEP4}r>m}lWl_p8i#>flZHt&Fcx zdei+YOS<}d(|s)Ww)OJ<-~BA#26@wcEeBdhdDHzZif)s=={}b~8)kXa{VwS*7J1Ws zFQtX6yy^ZIQ_IcXbRW#Jal5_gewd8?hrQ{(m^JTCd(-_f4tbZn={}ie>1}ViU#7DA zV{f`|hP~jGH{Cze_4p@mx{v1At6$!9KTTU)us7XTbFx0#o9?gaX_(?o_t^-2bG+$( zo4U~@-gMth+mb)tbpMUb-ezyQ4`<#b#)t05`Sn!jL-*x${~`0C`*WfrO?}}08}H4q z^`ZN9MwKdj=)N7ldT$@Pf2T`FHy^r>XB@Y`58cmmSTx*+?(0d^9q&W;_wD&cpU%GF}d!DB+-M^IM-qn}xW4hDW+n4TVTKjXbFWuKP z?%-%&y1%L4u*tr3pHm<4EML0cX;j!kU%KyU>Cu(GbpO+ZK^uMPKB$P!9lmrwl>Vm! zzI0#I;#DVn>Her-y9>T_pH!EGYrb^9)a!%yeCfWau6|E_>HewE>^Hu2AJvlMUwr?M zqx+7lvH#;ZZm$U0TVzF)_8ISYW+aJ96qSagtzoZZ@4Yj#Z+p+|O=cvatcWP>aemk5 z_s9MCKF)Qnb9L&F>ps`{yq?mhYN%w^rB`+5?Y-X8ubMwAxwrJJoDJXfmcEtIjSs!0 zcU5KFx8Bmf`ceM7xAd^yZ7S$3eXLhz6}_dGm2$7Tx%9I#$JR5Ko>sx1#^%!3Y8cnr zTzXp;4UNpDzvY$C-CTNHE4!JSOP}k`NtL3^+C3N)7<*l%^Xx%9z?pNTb>Uf8)Fv&^L*)?xR2bLok#YO>s1`eKzA zt}~b3SWLlIbLo#|`|UATX8&6TJUwJCeX@@>C(Wf-Hg@L)bLp48tA5>FdS;$M_spel zmiFMOx%AG)8mE{`|15oBy1Dewd@{e7OCRl%=9jtj(tOwbGnal^Mpmi0^wh>_t6E53 z?Zb*X7SdbuOmAqR%>K80)xCv<^w@?@Zf_xdwwp;^ETq?FRjZeU^xO6gwX%?&o55lY8$s z*+Tkq?bgq-klviM>E&O&;3+We~)(!aAZxMLwbyv`<%Eu@cEci>A4>E-GcETpHm zFh0vd`g#M`|FMwXUg@4f3+eAA9CbJZNO8%>K82|D>g* z^!$cCGqjYx--%~kEv5HYE4i1Y^#4XYva*yO;L1B%OX&k%yV~DUdV!x#53!Vf;J*VS zETtz{vSqZT^acMe@v)TN;M*yImeL#%uzi^sv zv8D73t9@E!DSgA4NgFMtclc#{f~E8iHB%EUrH2?d;)ta(``_kFw^NqVOH8S_U@85? zZ_kn}rKgy=`>v(*6`w>tv6S9oB3@Zae{n+XG)w6*ws@XlDSgH>o3bpW*Qg!)$5Q%@ zC)yQSO3$(3$8t;QJ9;Kmvy$H9Di1v?=|3KCY+xll$cvAfTS*`CSX?_R=|wKL>TD(b zNVo5bB&PHvYiu&NlD_250V*r$O?LciXC?i~6m@{uLwvt}vYxh-F z($8%CeS?+sG_7N|TS;G&RrXp*Z?ng;Lsrt?EN^teN_w29HlI^Y+1|8uY;)C0dY$(Z zZdpmc(^xT2rRN#8^_i9QJ=ZsVVtTwx_WQD58Y*3uW2%Oq`mdws94S8M6h zy4Uz+Expcv`n$6)_py;4@4yT8 zHqz()cxtGP^m>OKaj}tp@0#7CZKUUWaD%sv^nKSY3b2vh?}#bEHq!si42ZOm9;Bfa2-iU%wGV80rRZKNmMAZvw<^o3X6UuPq|;g9>b*hqi4O8ib6=@A!< z-De|x;)|9?Y@}B_Oz)(P^oviYpR1Hno*L^xkw!Tj@nFn60*zezbYpKDN@6K5}uOt@NdTyE@uRZ@MgdxUKZ3U&OiF zN{>3G=~!FoQ-9p=Yb(9#Ce{;drC;6nR;aD?tkayLY^84uCSF}w$5jrt@N||rfs&Bp7s#89k$ZfZvAMlt@O4}+a0o%{&u5N z$84p?ZQJpTt@OD&t-fe0z3!BbyU(PKVa8DrOf_!+P$cWO8VvAPg<&^XP(}$y-ND#?OZykq<7wNjj>Al z=ii_7Qb`XzqPC?<`sf$>s8rHRzd4yI>8Gza++QU<^_K4ktE8_USa+C8dh5})t}5xT z_w^sGk{)~VGB1_%+1s4*Q%SGAd&&fr^xKPyLRHG_f2a87Q7Y-XKee2qlHPl&^Gua8 z``>v_P@GD7@Wyi%s-zDev2K}4dhyZwR;!fR|ISutH>jj1fA;29mGtHFp6pa9v;Uoc zrzEPRKff>ikV<;=tul|Pq)+eo<+MtA^{OuyRLbms=PwyoRnoI}Ouwm;zI}MgJ(cwC zhdz0%lK%bo8_!kJ!`GfkQAr=)DKSkYz5JGIKdGdjziZZ4l`{L^B{T4+O8WXAoc^e! zx4+&zUnTwh>P<^j(&INRs8C6tzwyheYU%Z#JXT9B{r=jE>#3#Z-@?a0Eq(tCi)L!+ z{rlH!tyX6LyCkHvSBnR*Ild;o2vv0A)Fu;Px5T6}@#i?wR; z20RA$Rf|91Qqx{79zoTcL)79E1kG?(i&wC~+)b^_{&)5GK3XlF!RIYrYVi#^4)Ifq zchI6ZP%Zw!t-T>?@en#WMXJR|(B#Lc#Y?EUWtv+2goT>fYVi~qjt$dGKJcr9m52(d==-=!= z_5ZzxohQ`dKZJETs}>JJ|HwtP_z=E5uc^h02t0aIEq+A19{1GZNi5#~NG-m^-uBPb z;!Q+ue5DqD;*VacT0DyOv(nY#Q&j$)p%$-Vt>-tj_!Y12{8Wo)alh9ewfGhx8~&-q zyGSZ2Qj33aYfQOXJd7!qD{I8ZNNZ6;BVNXz=sFtlGfqC%*NCTKWYkC_zQ%wl%{1a| zG=0!YBmTy^7VS0SaoiYhq!FJZ;Y3%BGW&1bwWNne{0<*GGmUs21LG|<;(Mgtw$+ID z(W*K$;(yfX+gBqV$i5i^HOlP2an5N6jd&qnemH5w4_VaKMI)Zbn_=!6@kL(F^3;eo zGUKqfM*NXyulzLPkvuC8)QC?qt7C{pypq=gBQ)ZdybX-jh-b2B!4!@7CKl*Q2-Zs3g5fA2m<@*|C_P>X3&LfR@F}qWfHR8uCz4=ljo=mGlZ#3e|j98JT5pTvU z;-g0VnRCNFYn0jl9-kGbS$vxFHM2G1)%5&wub~wm=knq@TJdrMhv{p@&pBscpcPN&zZXrk;_D1r(?ToW z&LXEaT4na%B&3$1Ry>}9Yerh}c{;{))r!|s(4~h~{GO0Ey|m)_EL>o&72jt-Z)>f1 zKl|UQwBr99je}M^AonhPwc-Qqy+1&!%>J9K3mU8yKd5WXp<3~TymmWl#TT+xyK2Q7 zI`zz5EB?^)08g!WL~9GZwBi#LEb!GTv;QWgjmB%0*?*Hg2|-%%jIuk2YQ;B7ITE22 z@5tXYS}Xq1niG??%Its7ai-I?;v+pjGD|C7(&x@`TJe)MB+S=}r}U%IVy*Z}=?j)= z#ao(GxKbKHH!bpD9%|EXdKkDV{OIq=yI&{9K6m*6%VVt<5#WtSi@YiwBltUE?cY2{`Y$DUyfFp{qL3cI#(;c*7@>$ zt$154I}~fh-)i2!Oe-GONk5%de6FlHRUls1rLEPW%>J7ipRNV*yeuB*L42>b@AV&$ZS=QDhzD1`FB;;* zsr)BHytsPpra}C;DJe6c%>MVDzI-;smuuW74&u!X$c=~ib9Hwugm`olhc1Embl!!_ zAYR?igq0A#u3rB&5YO(;*L4uzuF1lU5bv(kXbZ%@i%r@F@$eRn-U0FPdi~i2@$y3A z_d@(UHr)^L^bRB*g!p>e2k#g6L>Aimo;sf@gfUNn^6472&ZNgPjXsN3yLq2sx`&a)PHJA@ik8+sVUy(w_{q0zj=5YDITY8 zK_80GnHkoP;&qO69YFCrM_b!dJkOua22*^`dIb&?@AK+2M~eShamb0{fj*w=Oz}Z` zj2uDnLR)rqrTC#63f(B4=f++rJX6{6ahq`Td2*pRu92Q3LQqPx!Q~cCc zdm<^Gs@~uzim$pPJDTFHZde{m@mEcIOrdzJ?)RornfpPv|wK^5gpfdY!-FC$+ zisw4L{Tzz#8gP6r#e03Pok#IsGw#JxJlN>r3n)J9nv{hUFBYDQDSqtav?UZzR_nQp z;>)f~Sx)h0!-lV<__L|^R#80K=h`(CpLW#owNz&RZGzgbr}(usS8Skow!MotQheL* z<2F;7{kQ3HZwr;#f1A?o+bACH$mQE9J}$BoC|>T#K|3ja?#bP|D4wpiWH*)Be_OX< zdnw*-@vcOQzuPr;AC=jE+e{vy_`JqT4^q6|@)w6Fey?ZCBNWeffY*N%-}lmvqZIG= zQu;9}v;Ve(TAfh7-W^+Sx04hfxXSWV6ffB9#%YQl{NvvliYMHw(>W@$|0>;x^AvB` zW7Y+VKWw-EBE=&<@%R$OC;sp6Wr|m9(da70FCN(Y8pSitbV{Q5#&v?OQiJzNv;QiGclRj1@|{ojsm%VX9)Ed2 z@t3{6J*0Td)4o2U_{{AyA5*+$=l4%2ezV@Irxee5*n?z>@7(svGm7^-`M>8B|Jh^f z3o5h!>bnbGQknf%Uk!gn@uE5MHN}s1P^C~j=?|^mP<-i%k~dUl|JD0b-ctPOw|@B8H5pA`T5Zoh1b2OjV-o8p5n zoA!(1g=-CdQ~dDQ{l6)mxUDLO;)};W$f0=SqelIq_~U0Y|4=;gZ6SXtKDl1rUy4^= zb#gAnFOM(ErFiBmCg)Ln^Y;JpDBigy>>tHH|M=w}#Y3;>nNMZ*UwiX$KE+F~i~@?E ze(!Jr#ZzzItdQcX|D9b(@zzItEu{GC8iyi^$A0v15yfXeRHvBYwVMPMQUuGi z*?&B3UPAHRvqMX$%>H9dQVEsWe_U@+O7Y;Qc$HFo`11!#`F}4yx0K??KeH*Lc=Cs4 zlu>;7x>w66-h4q>8O5IuvMr~0^!`!h6rcXvp>m2>pZB4h;@2-SsGxZEd;3;Ue0zt8 z3W|3>d20og*?*ecs-QCa&yXJ#RA&F#TVF?I_MdURbW~>lIoe4_W%i#JChDln{&QEn zj>_ym4Yuj1%>GmFgpSJWKbPIqQJMYch8H?2v;XY+Nk?V&pZ&6RRA&GA^`DN)>^~cp z>Zr{A^Hzn9l`2*G|9>4?RAQ-4hyJ}QFF`Wp_!F9Us)e*s6;1a z{e7$w^_8{3{Yr8im}OLAgtEGnR$?P%jcHt&hs$-?Xi}NB%6fiaWnL}QA=O*Ct*m8J zD)UgO4sF&{mgfT=uFS9!9ei$8=JjG7=Dx2?J!RcfP?-)zI^3#Xg>wpZ_|mlsj}+)o zqi+>H$=9KaXBGLrFethT|K;g0VR;o6%LnKkHEIWmO)_P`XXq}>b|J$lDnNJb7D(O0%nTr95*LAQtQJu!ul-J=wb!J`G zAw07>6D}&>Pg!*iKCeS!lN$VSMu%%XYcTGV4sY#iu>J`h{`u74+M_zun^uGMjws*P z+8UgBPzSps%DK}%9XxK=AouDpDZK_)@6usuVGX7xD6db0nryyJhfCdRa_D9qUi7W0 z{EpJ$r)N!WUaLcun3_DXO8Gul)a2FWI`rCKlQ)(qKd+>kytGhh<~uyWoOnOl>q z=jyOfuNFgR>9EbH7VW0%a6(&)wWjEBdt@!%jaHs-cr8wk)Zy2nTI?LAL*?Dd_K7+) zzEq3efy(oKS&P|zI@tcI#c&_xb*)jGSz~k<+pac8kJcf~rZ%s+=`d$_ZMGVr!>Wn3 z8S13GPV;K>tb_9Pw$Trv> z4zdhty?Lt%l$h1+*Ajz zj5^$7p!|6)t;13J%Fng29;?>TVTOqw_g2?o{y;ryDl4zQw;u18RbayuJq|6ZK*DN0 z-p#8(;vqd+=TzW`GBUjVM+Hu$>9P1r1uo?4(eYCSuIkt2`m_q%>Qa|4Qz~%Jt}bi8 zsKBGqb!qXW0?Cu=((Qf)UM#K4&|4LFy|*r>U#q~ID|I>hVg*uP*X7hR6?m6ZmqEuX zkXEZ6oex*wy{D*5>ao%;Wp$~?`&*U$L+WwSh6=o$Uys_=%JCBFF>9%E{B!lV zbb<2qlIyYKT;=O$)#Hij%JZqBPs`W}+-#-K;}I3OVxdpN;0l}@s?S9M6*w_opI^Ky zaA>wZZ9FQldy_unTr05Ugg&o3Rbcf4eHIR?z`{&@cI;PynPvJMsI5R$llt_suE2zz z^%-hbfid>=IjMUEoPCtrohs08s&aq33RteG&w(u}(B*J_8a1jw^IP>OuN!dLopM;`G~mx`bKm!nx_ z14c)eqqv0uy+X_JwzmPbVnRK@dlieEg{K^Z=_YQp2Q%5c!43CG2jVbahhtQA%U)%Ygd7f^=Evzt&g zwhVVSHsLMTGAujZg#8`MF#LWKUg}qd#u-i6Rb7UZk|tc*y9}EfHC4`O%iz(YDJ=}k z&}u+aPHSF<)Ui!@u6`Ld#WrPDjWUc}*^~wqrD$}ZDb4ar@ieI^?Xyd<1nbU#~kC$Li&6eD_uLNk{lB2hk;Ehd78muWn66hq&wH7D#V#;VZP?6KoPbtY|FLVico!L zTdrPJgy8dSxgfp>&yw3Ra!L^_v)Xb*ND($wZbxIEBIWl+I~KVV!J~IOUbZj71&4N= ztS&-xzjo}_s|YdE+wob4A|$VE$MB{_=zgRftJP87f4S98dC#E`X=&});BO(!^V@OJ z=Rz#5*Pewbg?QhoJ;yvOgeltd+|@$Fjcm`_Ckyc+tUZS(7NWz#_FT285D`1t^Y+q0 zTshaCe`gh5X$9p+6^g$v6&$?P#!nfkUh-`aeAB~ zn;8|NV5%VtnifL2{LM$T3o+%8Avc#5;M@&Edgc`1U#cOSWE8+O&ycrX79d!!1B34t zAhBZy*1TAN_v#MZa-;x_T|3ZdM*$o{I&kmm0?dlEkJXxj@(wO0F3R( zQziNEU(t~_vh%TMUq{|a&&T1b%I)NQJbta*eci5vT9VN7r^nbl#MY z{?CCWSc__{4 z%&zHq$gbIiZ=dAhUAr!vdo2(5th=z?@jRR!)`h2c<{=@l3%NQE3ukxX^|^Tn+t`J+ zlk(tttP2nL=E3G}7wWs@q2-4z4DOeQvVtzWYOWklzbk7R<>5l-uC#BQhYje;S=I6o zIkGE{{L6(ySXU;0&P9g>UHS86E{e8yW!bGvGYj zyemJ)=b}NAZpwLTF4B5*<4*rv9O&PT5w6O9W4h70zw&-&bT|Gp&qbwW-FTp5E^hDX z#u1H_PZL~HwpYo;;1}JvEcY*J|Ln$=8Gn`YBxCM)_80LjjoIq@U)c3F=8EHgQ9Rg~ zg**P@#5iNRul$R^sm44y>n~cbHfCw)UpzfvOpg7FIZ4Kx=J*$;Z;W|F{TJyu#(Zh~ z7fWh(XI_iHux!_zwQ4Kdt-7;u(I3or>dt20{-FE#?riw_51!8K&dRs{AaZ?oW}W&2 zga5ko&h9@rajQGGuKok3wC)@~=MR45b!XS`KZw`s!B1oVpmoO{TeGu8e*D6oQN8#og+O?mrZHkN%h<%SK} zxLs;WuX))hH!x${h-~yWHsi}N*$C)k#yNwtv2m0cjjXb9H{6WZI%Fe%ff=3aXQO?B z8Q+%vgu@v#j{5!+lOCDz$;+SEoM}e&^`E#>V#b~S{ltfcy;-{XCv;tV({aI1w6*Ka z^^<-=<=&gGynezhtT*cp`H9f^y=iOx6Y<-6)2pL$oKw9ywf;{We$boCN`K(;C*^V9 ze&At|vcC9%H}%cA?Ai}xb~fkq!#|L%HK)(UAINhxr)J&{6a|~Je)tcR#+mc2#}AZk zHs_Xs%I)Lk9MN03|E@VJw^jB}H|PG^%H#9R*)Kl}nRP9g@-YiPs>8w1`DnZ$U^Xc7X0d*g%P(b*jtkY>vtB6?vjO; zxfVQXkcE<3mi$ou9dFxNvS!wIoVBuK=a=8HYN#bO*S;gj-;#q5eFvvo(sBKFG+tv# z`#In7^?)U9gO&ZSS+e8E@0kDEl2!YB$M9d4Ozr+1t*Tk^K-2HYY-z>N%HMI&%!=Kz zzaeyx72m)9hMwM5TzLH(e#a==k9@=7Wmdet;Tr^8 z**7abu=@s9SkbEcH~eXA&CN}|VMljs=IOp-NMCCX`0*75qpZ37eMbVHKywGAg1f5D~UHuTE;0>=q9R6qWLce8BR;M^AkuD4;@&M)|T*oHfoe8JQkHuQ-8 z0^J)M>Un)ZT#gM-+kZjT8n$#b`+|9`ZTYk17gRF0<^hma4!1&MD_|=w2hJ8k*a^-k7pApzd zMZ*rC@u-`MPI{lw(@w>xf0{n=(;&OvS{x znQ*+L;`)i1*pa5A6KY3Wpf7FCaT#WE(0Ey)Z95S18bkD+1Vun55B3nSDgV}xtcAF zGGNwN!v%FSFwR)RAOAjKrJaTY-haZyks5Bg{Ry8#H2n16C)AmzVTTRM^}5X(dd~WU z;m0&wGX4`HZ)@JriIxKUH9{2u>=H*K^m`27*t=F08YA5k$_ z%P&_yqMnbIPxpO9%UCUsulR^g%d}h^`w=F)we;}%2=nt=8V>vjt0!81H2DbY&suJ1 zqTDXgvVZvp^lkuVeg1$RoxufGA_5-e71K+j(fW5Ck^I9LU_$N3wCmj9lvgqR}0?b>^t(<`}dgn zm)v;kJ^IwNW9;GgsM^MkL)W~=&E9rwHT6B_46@@V@Apu7*)d_@d*nvh(Z%FF4lK5# zuF-pV?y%#Yk~HX@u_HdE;lcwuKD(QSfRA?cJemgm0z2heP#VtYDcAa@r(v{VAKo38 zh7zkj>@_G2n;rXbMb9)?`S#)0#%V~N+=mvW?-01W52t;4hqB#$c>eA?tUTXGxhD4x zZJ+dE%XRN?B(o1O?H#O(`_RMZ9j@v3W!S)X7+}{BO})Y+t3^ z4ttA#iOT&hZ!!2%Ki0B+i>=AZoSpkqPq|*bDxg2j{odg5wElD%^aiz7_2)#BH?T|WA)5OcA=@_us) z_CM{<*=Z?A`P`o|*Hcifq(A-krJz^+0UWe61@1-z*f}BvGi(R2)HMY=oCff&Z3?dX z4dAl2DM*{5>{m4f13)_DV2YVZm*YT2`8;Y<8#ZBMgz zFY(OGo_5z>;?zKU+V6RZHJ7@%gX)xp2PRqAf8_Q9Cg1c zj}Lv0(JR1}^XDk;IG7EaJ;x@S!E`No28*GCx$^xpJRUcgHu;WI4UF_^{^pP|X=!PE|YhMo5Y)86zMy1pMwheprv-`~OPUyuyb8Vr>OVMfy*~OMQEu5+f93l2la>W;FzZ{G8)3}e2VEd zLzrmz6i*$M0j_FKVK{CG=YD;H@R%X|eD4V^EgnJ~eu8QVL%3@B6AV5%gsI_Aun!9Qi8sF^+Y2NZLV)a4Ndn+@d@%SUh>Fq9peJ;IpLLwUF8A;yIcRj#c* zgx}nuEV}d%zUzlFe)~gs9URKqvme6!%23Ytc?id6Ls`=2A^2q|13NxMui~M6RP7;J z*K?xr*9WL!=)~D~AK;gT6CWRVfMMcOllL+2n-jaOy${DyWsSa%hV_Th(Ct26b{NKn zR`;>iY8XqJ-iNcpFs2sXLv62NJoV-tu0;;x{0sLmY5p)eZMlbzn}@N%^m|A?GK>#A z?_pZfFwW52gW=0z?9%2QZhup@m)}J|=`aSQ-$m8>&Mdxq7YQAl8NcH$EUlbbYtCIf z80@V49PYw%tTRjO?jkF~nSq9P5gqT$N0slQY@;$FRd}vBl0@+V2j2)*a4E9q(Xl`{B&2dIyiqhqLPE+px7C&epeXW0%Kp zn(V!enqk9f9e*1W=MJZ>|83k~H=O4EZ==(J;p}X58?!DAXTxf@@$$)V=4akQmyF?j zcJme{=MQJ%o?EzCYXm3FyM=nKN6^~u7F>FbV1D0Q*wA+b4|lkQ*KQ-|QRNm4f<~}X z#!WcR7{Q&_Zz68x2-@tri8H%L@ZOx8_;O|hhx^=w!Tk|@&YRGrji6(@oAAvU!K)QF zFu#fmyQSYyu4}n)*_9i((ba|Dx81-ywF@;fZXnmmg^N9Jpt`RMpQvu2NsJ5iTHb)+ zA{X{8zK-r&T^RA^I?Rr`aMQW#u(|%avmslQ3tsD~-D+ zVa#4v{;8b=%X6+g_Wc^_JaA>;-D`NC=E`RKuHi_IE0f}{VR98W`ubgiT@yE!^|^-X zUER2{{WaWGxv`b*Di#cNM$KAPi#znNh z=}t3`iwJt<&U4lmar~P*Et_0KUa>omjzu_0!Q&vhYJXrI*MH?UBK$4qZsi1JkD+(#cdbQBjwmAKHPX7|E`bX zzv%O*|8f+YjyR7_Uq{ij*Lm0$jbgvL=P|g>XgX(|gInv-bh~p7UOh+CWzRYI+l{8f zoO2jIVzhEy;v53}N3)~q9DHI&vs$xr7`13LKjfW-3O3W(*7*2R`+0&@-x`d%!B9Op24JU9&|Z-27}Zd{I=!{ zS`77IO!ygm_wr!rkTW@z%!7n3DBQ4v57QIemX@&B5z0B-FBWr#{r&n zn{f(BBRx57)G3Uf;K@xEr|@U0CyzBy_FL-7r0kPuxZRWY@14Z=U_ar(cdGhX@ zlQ{THIqsN~FwXSkA)Avp@XwR08=pjn8e@VAu(i%u`aC^`cdf?q#i3(pVKSCna10|b zmWktzVbQR$tg1bROFm=i+58x?BFFN-yrXC`Z!8O+9EE1xSgH>lg-_yGPMLocbI*?D zQJ)kkse%~;lKc2v1OI+opX|3iAoSoVMXAF}nlIQqbUC~WP;z>(7Y9E$f}e3-?3H)~X=}Y$f6fs+*z3h_9!GHc zj2ACh9>JD7UYy_H2xg{u(c$M|jQQ@xT6YdB=l@>3w(~Ib>v%I_`e9_W^k%D(hjFUA zH?Nu=#%zr@J@pP_&`@vYemMkvFK@;r9m3NvZ|ZG5gyplnxgzEe2CedD9p^)+*y+tV z#)oj?gttO19D>gcZ@Path`KMldEvrAoX+%SlXV9%>Yq1*!VaRSnh(zpI*9d6d|0XD zLGA66fK0C`h<*xBv?Vi)_+uH^yb zZ}y?epfU-f zUYJz&<&ndC;nvWXJ?8JlG(%tR^V*ATX1;7`vlkco_;O*xy?8O)m%o4P!S`{#9Cm9D zN+NxEaQhzAj`L-C>>e~)_(MbUv3WEjlY%sc*$-z-Z%7PN{ijNW9Y~1++8?i=Eu^9yRf8>AFCzqLf~*e z)|j;mcH{h5)qNM5MEbF~*DidW^gZs!wQF~xT9Tjg zS<9Wc@zjs%0Xs3{gL0gikIj{q0>(9J7%61cf?ijrT zi?se6(0d2E4E5)iIy-PNWc7)XoV7%#eylWc3 zSGBgIf9C+U`?L)QECc9wVH;`>2;lD3+c4fWfT=;-kmMJ@x_!5yNmKxBS}NP)0_dH) z6{lARaQ1_(DBl^t&AYdv-|+zcH*G88uLbbZh^@HsB!D-Kx1#KQ0Pj@Uir&8hcq4TS z{L2D({^S;{(HqYLOSa&0%kf<6y9F8D#&fc23#!?Ur<=hRbQmLp?hOoNP0dE^a0_H?qm7v4AIS6{8_*{zkbQ1!K;5`N?%2EmFIEMzAYubH>$TRd5hX{mv9O@^to zaRRs8T!VYRCvd`+H83upK-0)ISgaSsJo`1sY!SrcZP&oIYY+qTS7Vt~5L-N2jnw`@ zyuEuhj9h{kJasiDjtgR4=hZk89>o2fSL4UbAZp83!Dv|!AHP@yk1auTKeP(V4g@i6 z&MI6y8$?g{Rmi**#8)P(Q2Rv?2UlB#?w^8qK6NDqqRvVrSWe`-k1MdJ-$Zsir>w&#GGO@%?DU?<-F_>uIdmdZZC7CV z^ogw7UGg?JrVNn#WFl`jUXJ@| z6Pf&D8MgnJ$dsgI2q{w54a;CtBbYBjmOFGe?`5N^$1gw19lZ2xc(sxySUb}mAwV+dQvF2b|XAzU+L5ljO^ zSk-V5mPUs#ykH?R=7#Xq!-cS18A2;%{v&>yvR~{%JUJM`??V=%$+-}!3>U)vRtOgq zEWo;FA$pboC8o{J(gZhlg_c{dlNngmQI4Jg_*F zE2H9}*$~RbgW_SmCzP|=#KYuxC_{7Sq1}~Gy5F6LdJjUW-8K(}uS3};avst$Ls>Ln z9RVR$Wx8h*mER4N3$Dx@~82^RFA=5OBC;GZIEW`^+$=AzP)Fb-=p7l$^4@$9T(sY99<|;;?CO zJ`>L0g;TNadN@sXPQ~-b;q)Ce74=fXx#G_h^!pmlA;f)n1vAkZa(mUCh-$vc8Y zU1BgbID#jhMq~Qq2#%W^jj8h@ShHO;qE<$5@0}=2*cw5buqce)AHf?v*IOo?CG&3VgJ0@?o;a4wuU&aZk1n zZqpfz!g%i}PQ5x711CoDjo(;wh>2p)+G9~NJBl-oj=|$4QM~Rl23yxhvAoC=0Xw5; zmf(r*hod;QpC_`x#cx$mNB{L>j`UzPh;IwRyyG?$n=V|Ph3kERU6i)t}^Fnt&*)sJC%yJ6_oB8ES1 zI$>zX82%1)LWqfSTh9p#t(E(a4Mjp9Wq+5UI6fqX#|j;B#Vv+Qw>sjEcMN^#h=)Nj z?2$PH529lDcfk>s3_|&%7|yUCgyh#T%==-FgpV=wU15*FAIkGEvqz7AG3@qg zAhOG27&m1g4%Ce0^Hu}l-7uD|t_^@et5}Zl9e^aGSZ=63026!0^4@{|sBaU?+#&sO ztWPYPPjq4Er|_xV)-)# z$bA~iglT}o+gLiZ0k&nt^7l0@e*BF6A4}&QpVRsNaWkQ zNJ1hJ*?IQefl^hYR8dt`HCv;tm7I^gTB|imDXLbjqO>B$@BDl}e_XHgsuJ?#8TYxa z>+^n#*%K5s`e~)`ZLFxKSCwMZ8iTsiu}Z}DH>girRf%o)lGKp)RU&L|k~+R~mG~ke zNu3j1C7Pc}RJX@eiK5Cx^^#g8esoV%U-YRGUeyU|yJ1zLFe5Df6nt{$sJ~kR?_6=S{5I{mUwG zvsJ7bwxLSg+Zv;~f3IIh#;7l9s>F?dqt#0XtHilaqt)#vs>I&JX!WCCtHkO{QEKMZ zD)Fv8N)7p|N~HKissBEz5?%L2s=J<7iNCWWRZ~Nw*xWc$jc#ES1#2SIJ8g`@t6zk= z%+sj%+r!nq{zg&qVYvDz)F@hohN}zXjAHG{Fg5Beqev_XQ&03Yii0j;YW6Ur==Xi7 z`edw892ym>zB9on4F83wO$&_r96Ch(u*@jj5<}ExR--Up3|6O2Gm10TV72x`qX_T{ zRwpkqimKf~>bd1cu{$$JRlYWg`VE5AFTOR3q*a0Ht8GRxwO61zX17t#Lj!olN3jNf$Lf&?Hv4bWw*!nndY$erk52 zNr;htYH1IXX#BLZYVEK8zD1qYcZQpUjP0zxn`#nKzjjjX6HMZ2RVTG#vPrz}-bu|X zHHmIJebv!slh`-bR~7G?#F*zks^16t-?!99ZM487rX=~OSC*K>gNxqk4=YV#vejFC zf1OEO>FBMF++q?#G%wY2r%CL{@KUetF^LYZJk=F?=Fs@Lrb25u> z-fFM9x|zj^s~+l#j%M-K+a78cKeKq{_m z(Qais_3eIU;oQBQdS|Fv)cd2YIyA*B?!Dbs-7?-Re(`CmI!!W*@AkNa1q{YZeO@lRCJOMPwPB zRHeB^>}ltuc5|_a_S;*i&K?#~G`fZQx3@)TPn)Yh`CEkJqUP$V5Q`WP-CV7Vwulc- zH&c5hS;YR*W~x&Ui}t&NqW+L= z5#NL~Q725ch`q-g)n+9YajL*k?{izkZ_OOlfp&|yvd%%hIZeOzbxwd9_{?+x>Mi(riNosvH{fhqopVd>py`lem z7uQqk?&^O&ww}IUZV{iZd#%iTW)Xkfe5D+IWf4ApuapLjtzvZ6OC_$kRlNK83nj0$ zReW`^PFdK_Dr(&8lp0T~_-WL0<#K1MIJKZwc@bb0$4)*|+`_E_EuJX>u~zYQzyFkY zgH=qQ@vqXehgGERf2#EBYZdLu7BMR zjws_lu!(&K4=cUq+QjU7hZVntHZdsakn;Ldn{cc=sGMDH6FWB_P}Y2D6FGPHD`ji+ zU-#dyByF^bRhj#gSDS4jZrNU?<_DWNaCVPUu}l9xTJ2E+ciY6_{=1b6`)xv<4rSUA zoA_q8rUV|h3Ag7p%8x(WL}hf1GU=R6oGhwVUj1ehzUy`=^RC!L;h#Gduj@9k*>k7z z^=+HDH)e+tcwc{f7i?G7J<`ALW80L@|JsDnVVkn#xlMff)(=Y4*EX@${Jm1q&@K*q z|DAHt(JoFt*s3Tk?BYzft;*6?cJa%EEz09Ic5(Ex%}Q?%yV!Ydld{m$F1~EFN%`H^ zE~fYYR_Ww#7g^K3Q6>c1MJzTd%R}v=(X$Q8=}5ac7O_ET6lWK63f3zTNp{h9^*SX* z*u{&>YZXgRyIAkOR{6A#T?`w(M%gmJE*{VRS~)nxEe~ z*~QhgB}(`LyJ)@WQ{~vWv#uXDUyx*hP)$eWmxGc2Tr-hO*$MU39oRUAgd=UF_>T zUFmS&E^^bSDJc)_qQRo~l==VI#j@k?DhK|xi%^Gmm49mWKd-){bbM(S$yIMF-RnuQ zaJ*Eq8cMO?lufZZNb!DmtFoY}6lGh@%BmJpjO=VuHno%@cwv>Y%|(j3MwQA=H!1d1 zlq=iZrLf*CRW@~yB6LiNvdT+}Uk^`J7Whh08DFGW{iJYOSEyulm13z!fzmxt3hxi{ zm5w3$e?On3JPwnhMZrYnK&1ZrFXkxoVx%}XAX`a^*S}s(meL_f3R`fda$b?*z-Qx> z`EN{Lc6Zx5B?;5Q?b zwj-oC;yGMdJ4*jLbA~E0DN<~IIatwBrC2p(kRmdqnDP4nMH?^0ghBn4xCv6kYJHUr zIr`rh(no1ONs2?CB`eeNrFgGJFXc{w6baTIO8+7$Zr*)M`MOw&Ica+9vQ&SZeo~ad z6;kX^G$_le^v7>~qVlInir+mF6o0D}<7dSwxppajdlsX7{7Zoq zl6uajvC^nU|Nj>oDqm<)pkD(eZnqSLJL)M%_vqi};8%vx`=lrjsxw^PFU5CFo*A+Z zO7Yi?Cx$DBq;T8+$dGbGiuf-c7>*y6Vwml&!SIv*b4$H#SaVGOcf{Q=v^XL4`QJ6e zl#}}7{phmc=qV`%p15f6{zZz24d)Fdr=@V7dDeh4Qe4aV#o%yGicQ^58v6aJKkvPc z8D^f>AJ4iYhP@Z0xc=)w!_(jN@ALb82ER-C^KSlb!;s&lI6I}rP<~neclY0ESad~- z7yjD}Tdqnmz2SF;!+%KOcy*KE!Zj)0t=VX}`KJ{Be!9-^;JW^Nt@zsT=!O(O4O?aS z`=%5jp za||i>r3j1uz!3UC|GrzjZ>aaT6!Y%AXE?53cOH4$u<)V&{OD&fjCrI#Kk8Q)+#c&+ zZwgnmsa%`?3Fj}+#>35Lig`p@NBn&Fau{d(yr!#hv)$6@#oL#KcB=S{PI22H=N z+ttnGJ>;`gKNRtfBOo{`lSrGt}zW-d_e7thG{fOzmuVu3zu9_B50|mtxz| zwuW2!)%;E?!{|Ew=ataRut&c>e%R2^<%JZwzdmWYe${>UNq^|q*J0O^;$G@Mrxjepkonxu}e^w;72O-bYRYk2yqq~-cG<)=@Q&gxf7;s;4hU+cdMUE&4(dZ^{m#5?-+;!mF>{;OZl zw(OVqO21xcc{HJ3y|+b9;K^?M@16YryZHNe@z3w#*W1OfU(LU-nty*a|2@_G_f_-X zTg`ueHNT%~et*^ceyjQYSM%|x=HpY%$E%u;Uo{`k8a}=?e7tM;_}B2~QNy244S!xW z{Q1@J=UKy_Zw-ImHT?P4@cB@~=SK~nFExDr)bROK!{=8GpKmpM{?+jLSi|RM4WF+y zeE!z(`CP;2cMYHKHGKZp@byr`*GCOsFExDq)bRCG!`D|0UvD*h{nhaGSi{$64PUP{ zeErt={qOZ$!`F8WU+*=1{nzmQpoZ@cHGIFQ;rmAo-%o1z{!+vDn;O3V)bRbNhVM@` ze7~yU`&SL$&uaMoR>SwZ8ovM4@cpoc?~fYaFEze@YJ5M{`2MQ#{Z`}qug3RdjqlGI z->)^ke`|a{*ZBUfIsfndUgP_}#?J$dpAQ;8FEoCBXw}Q#e4c3he9`!Mqw(`c4Z<9SZw`A*|`PviMd<9Sfy`B39|QRDeh<9Sl!`BLL~Q{(wl<9Sr$`BdY1Rpa?p z<9Sx&`Bvk3SL69t<9S%)`B>w5S>yRx<9S-+`C8+7TjTj#<9S@;`CQ|9UE}#(<9S}= z`Cj9BU*q{-mU-p^^gztecX zr}6$zabB*`w8t>mV-p^~izt?!bukrq0 zV?RJ+e?ViuKx6+vV?RM-e?eovL1X_xV?RP;e?nuwLSz3zV?RSe??=zMPvU(V?Rb?e@0`!Mq~d*V?Re@e@A1#M`Qm-V?Rh^e@J7$ zNMrvV?Rn`e@bJ&N@M>@V?Rq{e@kP(OJn~_V?Rt|e@tV)Ok@8{ zV?Rw}e@$b*O=JH}V?Rz~e@YlKiK~V z=K_3q0Ot|ld;*+Tfb$D*o&nA`zG2na#oY#Q!8*rWj&Ue6h4>;Cu|6mx1#$aGnOv*T8ujIDZ4@ao~IooY#T# zJ8+%{&iBB1A2|O5=YimS5S$l+^Fwf+2+kM5c_TP~1m}_9d=i{jg7Zsoo(ax3!FeY* z{{-iu;CvLEmxA+CaGnazSHXEJIDZA_vEY0boY#W$TX3EW&Ue9iFF5}N=fU877@QY_ z^J8$H49=Iqc{4bF2ItY>d>WirgY#=}o(;~o!Fe}0{|4vb;CvjMmxJ?jaGnm%*TH!^ zIDZG{@!)(OoY#Z%dvKl)&iBE2KREvf_W{8D0B~Ob+#dk<3BdgVaNhvjKLGa;!2JYp zUjf`-0QVWd{RVK~0o;E8_aVUj2ykBl+@ApVDZu>-aNh#lzX10!!2JwxUjy9V0QWh- z{SI*71Kj@r_d&q@5O7}v+#dn=Nx=OQaNh*nKLPhq!2J|(Uj^J>0ry$J{T6WF1>AoD z_hG>O7;s+(+@AsWX~6v&aNh>pzXA7g!2KL>UkBXZ0rz>p{T^`N2i*Sw_kqCuAaGv@ z+#dq>iNO6LaNh{rKLYoW!2Kj}UkTh_0{5A~{U&hV3EY1I_o2Z3C~#j2+@AvXslfdz zaNi2tzXJEM!2K+6Uklvd0{6MV{Vs6d3*7$#_rbvZFmPWC+#dt?$-wA?LuaNiExzXSL2!2LXMUk}{h z1NZsB{XTHt58VF)_W{BEKyY6W+#dw@3BmnBaNiKzKLqy?!Tm&VUlH721os)i{YG%# z5!`B0SaaNi!>zX$j6!To%2Umx7x2lx5G{eE!YAKd>3 z^8jEz0L%-3`2jFb0Okw8yaAX$0P_f7J^{=tfcXV5&j98dz`O&Pe*p6kU_JuOOMv+a zFi!#IE5N)3n7;t?7+^jF%xi%84KU9E<~zW=2bli=^B`b81k8(o`4KQr0_ID=ya|{; z0rMzeJ_XFHfcX_L&jRLKz`P5Xe*yC_U_J)S%YgYAFi!*KYrwn>n7;w@IAA^p%H- zyc3vz0`pK{J_^iBf%z#gPX*?yz`PZhzXJ1EU_J}XYk~PKFwX_%yTH5`nEwLvU|>EB z%!`5fF)&XC=F7mm8JIr<^Jri`4a}>7`8BBj%d>&`HZbo7=HI|P9GH&-^KxK*4$RYm z`8qIf2j=gb%rk=dMlkOP<{!a4B$$r`^O9hG63kPA`ARTv3Fa@sJSLdW1oN6;eiO`d zg85D`?+NBV!8|CK4+Zn0V15+LlY;qDFmDRxPr*DYm`?@ss$hN<%(H^|Rxs}h=3l`) zESQf4^Ri%m7R=Lv`C2e<3+Hif^0#0f7t-)1p9|)7ajpHE{4SX11@paN-WSaOf_Y#t z9}MP&!Td0oCkFGyVBQ$aAA@;hFrN(OmBIWnm}ds_&0yXc%s+#9XfPiQ=B2^>G?=Fb z^VMM98q8mVd2BGB4d%7M{5F{92J_uu-W$w+gL!Z;9}ecl!TdOwCkON8VBQ?epM!aH zFrNE4Kz;zo69D-FAa4NV4}d%ZkWT>e3P64V$TI->1|aVM)QC3&?W;`7R*u z1?0bgJQ$D<1M*@(ehkQy(fb&0_%a}G2IS9xJQ|Qs1M+G>ehtX80r@r{?*`=GfIJ+K zj|1{@Kzjx=fgKVB9Ko6@`^xy5y&$F`9>h`2;?7uJS32h1oDzVeiF!20{KcHZwcft zfjlOV&jj+CKz%op1@f{$eiq2n0{L1XZwusafjlmd&js?jKzi~JUoz(2lDbjejdov1NnL&Zx7_}fjmBt&j<4Q zKz<*{^8@*QAny<4|A9O}kPis*0zrNt$P)zlf*@}YcX`Gz3x z5ab_%JVcO>2=Wp^ej>i$&j|7wL4G61a|HR0Any_6KY~0+kPiv+ zB0+v6$dd&5k|1vq669ZkJWP;}3Gy;QekRD%1o@gE zZxiHif;>);&k6E6L4GI5^VHA(Z}^@d?-S&If;>==4+`=^L4GL669xIAAa4}pkAgf> zkWUKoN`Klmq738miJXVm;3i4V(ek;gx z1^KQZ?-k^~f;?D|4-4{QL4GXGu6x6i1^KcdZx-awf;?J~PYd#DL4GaBvjzFKAnz9B z--0|`kdF)UazTDB$kPS+x*%^C{EycT^4me4JIHqjdG8?q9pu4-e0Y!- z5Ax$do;=8x2YK@#e;(w~gM50BR}b>*L7u%nw|K+12YL4({~qMwgM56Dmk;vuL7qOy z*9Up~`aJOse;?%WgM5CF*AMdhL7qRz_Xm0ZApalq0f2r0&=&yu13;eu=obKe1E7BZ z^bvr50?=0g`U^mx0q8dXeFvcb0Q4b%egx2$0QwU^p91Jt0DTLfe*yF{fPMzh*8ut( zK%WEXcL044p#K5%L4bY;&=&#vBS4=7=$8O}6QF+r^ihC*3eZ;p`YS-61?aZ`eHWnr z0`y^kehko;0s1pQp9bjH0DT*ve*^S!fPN0p*8%!FK%WQb_W*q#p#KB(fq;Gx&=&&w zLqMMh=obNfBcOi-^pSvm63|xy`b$8c3FtQgeJ7y*1oWYReiYD`0{T-xp9<(#0evf= ze+BfhfPNOx*8=)mK%WcfcL9Abp#KH*!GL}k&=&*xV?dt_=$8R~GoXJ4^wEHR8qik* z`fEU+4d}N4eK(;02K3>8ejL!31Nw77pAP8P0ew55e+TsOfPNm(*8}={K%Woj_W^xB zp#KN-0fBxX&=&;ygFv4U=obQgL!f^M^bvu6BG6X^`inrH5$HDpeMg}G2=pO=ek9PB z1p1RepAzU-0)0!Me+l$4fqo{?*97{TK%W!ncLIG+p#KTzqd=b&=$8V0 zQ=oqe^ihF+D$rL2`l~>n73jADeOI9W3iM%tek{U=o1G0 z!k}*$^bdnRV$e?v`ien+G3YY}{l=j081x^5K4j334EmBme=_J(2K~yQZyEG2gFa@^ z&kXvSL4PyobJouVZ~V@n?-}$zgFa}`4-NXFL4P#plLr0Lpl=%VPlG;c&`%BeszHA> z=(7g>)}ZfNe_g-vUxPku(2ouJvO#|~=+g%M+MsV6^lyVcZqUyS`no}XH|X;Q{obJO z8}xsJK5%`m^~Mhl`ockfIOr1x{ovzg2mR)t?;IZg^Phu0 zbkL6u`qDvvI_Oge{pz4^9rUk*K6cR04*J?be>>=N2mS7#?;Z5NgFblB4-fj{L4Q2x zlL!6spl=@Z&x1aC&`%Hg>Op@!=(7j?_Mq<`o(t-W)^)G(!dPFd*RQ{guP+i_yvB~+ z^#%0n;t>76U%o~~oBCpdejQO)Pq@B%jfiXYM6rHtb+n#1pkE(sswbRZzs9jo>WRVn zb-k^gn66)E=F}5g^y|a{^~4$d+AFf2xTjw`dDIhi`nBF$_1<#Q%R?`Jy(0AzdJWJk zMXy}FO7ybp^}$=O#bUiy>9tv}8oiF{bxyBqZ@m(K>s6;$lkTrX8@+tHzZ9W*CF<2j zuMyo}h)lf-^)l%-qkElLpw|k$Hgtb3cIb6Lub;cuir@9Rqt}1kpNWP&o{3gH{u3Sb z3eYR2$G@V7UW0o)6={0q^>`x6^?IkrKVptvOM5&PU+eWnA-EUu?uPvmnStRIO!`^+X z#PGfqVtn5+QP8(k82c8BX?=^te4T~7yl;V6*Ee5m>zgO`=}h#KeRIUcz7xdlzFFc) z-|?b;zYO8jFHLy#OBMe8Qbc6G(L(eaDF*Z#E>ijp6FL2ch~j>Ogsq?MN$S^6eA2Iv z__ANJ*wnA5sP5N89Pam)IMYuRSNj>n{eFp}wqLw(=pQRw`bP_|{*fZ6f4GS2A1ZqF z4;DlF2a5Fm-9&zWe^JrjPrTc|llZ8=k67B@ORVYNQGD0mL+sH94#)btiSzwk#f|>0 z#iRZ$#moLqqS=6EqV0etqVoU;5jLQaNE*;U^wnRpBL}=xGY9BC?*X-{N%tR5AMiw7 zFyOKJ`GAM&h5`50?YcX2|A4>LQv+_Pmj+x{Zx6VpJ{@pXtv~R0)oI{Gwf(^Js{g=q zYUIE(su=jQI$+>Qb`j%Tpc`UshT?IQ+48? zMY?}|fhq^hQ)dsFqb?q#bGZl2R5uTruGS2CS3NT5ZT0LRoBGEfvwD9}m0CNfLUkBi zs=5rGs(KABRD%XjR^tXwQhN^0QHKo9Qqu>IQ}YI=>&}I->f3`ys~-*?p)MIbR9!uI zkh*1Xe^ndYSN(BtvU+ZC5B1t$p*|RFQ0oRKsE$KoRo5X=s`rp^HE2kP8b2gZ?KPyU zI&_Ginm)u=%^TvSRt)K&zB9yKoioHuT{6T)T|K0wx^+kk6+@b;KMrwF&kbp)UK{dS zc`)RKQa7YlaUA-u;yUyn#e3*OC1~h=6T%Gsg2l|P2oDEEi%RGtt0L2($iRdE@%N%0!C zK?xkTR*4<!@66L>PQ@21=y-bHyb z+*heL!c%E6qP^liqOIaL!bJ%m;j9=&G*|kLa8yQ)XsBe4cx@;gQD-oYcxIS3;)!A2 zh=+#HM%**39dX<6{fO&^JtM9fj*a-;aDK!E!}Sqo4G%~BY^WP?+~7F!sKIsQL4)_m zy@sHXnjvoFPD9U;KNyCL++s)@`Hf-H$aRLYk*f`Ia1{kJ|>TQ@es)u3ODAllLRHEU#QL%>IqaqAHjS4aRIx4_$ zZIqwk!6+ZY^HCiQ4x`%{Tt>SZJV&=Q1dMKGh#Bo*=svoEVc_VONhzailX6BsO)4J! zFv&XlUef!cZzX*^`p={lqc10I82ww)w$bO3_Kp5I>BQ*cNxzLgl5}JAfuu*HcPG6Z zU7gf)%(kR9W40#wjQJ)hc+9$_xG`TP^&GPzX~>vmNoiv~Nt!rjK~m|MIZ5_0Gm~bG znU=I@j7(ZN#*(ygOl8uJF(pX{#!N{%IVLaZ;+X8DTVuv2Jsy*q^lHqgq-H5YliX4U zCi$lHNeW5nkrbbzCiO~5NE(t7os^ammNY3PFsU@fKgpirn=~t>W749Oc1bH!T#`1X zI4A8$X_~Y@rBTw!l-G$DQ=TW@OnI94IOSpD%apr`O~>9$Y%}&+qR-gh6NAT|PmCLT zI26N!Vz9!*Rgdmu4)?C!*pvAYtjV}D4TId*g6$744nt{D4u;`*^G6Ss~1EOGDH z#fitqE=W8-c245;u`?6@9{X-$-B??qL#i>+CABQkGqor&AT>WRIyEQpt<>>}15(E( zj!7MvI3aaNVo_@UL{n;V;2b(u9X;3lmVMF|7a^Abja-+>B4jxEi0GaWTFq<7~Vs<7E8wjHB`MGWN$W%Rv0s z89U;)WNeME$=DcwIOFU1(-|w{FJ~-^|0`or{F98i@vk#x#Wx%GUcB2lTfEP>s`#LB zCGoN23gUZ=n;1W6TxNXAxYYRUaU zeDyfL_(S8o;(s3J9)D?^OZ=^I&Ep@BYaIV_-0Qd|<7?ww$Nv-OHU55F!1!Bn(c}M! z6XP$&^&fvWZq)b_ahc=HL4(>rc{rhDA7OqaN?Gh4)M$!r`~lleOKaOShv zpEDoFUdp^1dn@xs?BmQUu`e^v$2w;H66=!nQ>gtJ5vycviS3)UA$CO8 zSFssc%VYDh7RQ!l&5N~VeGoe{>%G{Ivuv@SXH~|o&6*nfT~>Z9vL?hH$x4qsoi!@< za@OG3+gW{M|HngoiP<33p;H#9FqQ~W| zkIv8eGP*2hS+p%@Vf4(LInfJpW<-CMBcs>kR7G#eDUPnr$&WsmGa>p^PFnPDIU}O4 z=M0SgJ1051Hb;$am>V1Ilp7Z9p4%Q^rsJ0WQM)^$4iwc~W85KQoY?L~2SXAGM{iB9Y>=Bhd zF)3=|#Hgr}iNR5piGESjCwfNBo#+;|WTI2ls)-I!-%NZJxqae)k$Wfp9r@G5Tajlc zUX8pm@qFZ86Hi6{Gx2ET%ZYm<9VhLIY&~gfWcx|$BmE|=iVU5!EHZx5$B{iI&5j&6 zXlI`4KwhrFv1UGmOHgyo%zh|fC` z(Ian9#K63r5u@|AL}cczi^$Jg8BvzEB*K3NOk(5^l`j6aG&Aj_}#}o5C07uL=J=e?|D3 z{Kes0^5=$E=f59*Am1K-BEK^H*ZiXJKk_Gr-^tGif092c{AK>2aL38X;jJbc!rM=d z4(~iUI6Qc=UwG`~4&h?5Yk0rO&BKRJZV;Y6`FU9G;7%%H-)`wT>RIoYpWWn0d^93tHuN5o~ zy<6~6=#zr!p)U(;p$>)Rp)CswLfs3qLwyTVLxT#3g+>?l3snl=3hiAO7doUcEHtIi zKQyb*GjwvHTWDEfi%@G}!_eu4&qF>cd>pd4@UM_B3a^H&EBrNNYvIX|>cT@I2MV>2 zowQ(nG?gj0lOJ z(m$m8lbHU$FIUcM{IS_nkN_FtbDO-boow6?Y>Xa{n|C+Km`0?K&C^{dsw&-Ng=AuJEJBzfSeMR2~{aCai=ycJ_po>MH23;?j z8+5N|M$pqDThPm*vLJ`4lY^Y6W(BpIniAwQb#PF(smVd%Qw>20Q=@{qPYnp_Kh-B_ z_|$emX;YnovZpo*Dx6vuSU&Y}pl#~y!0A)31kRayF7T77#{xf}x<7Eu)SZEwrfv@0 zK6Opto~g?Nk4#+{cxvkGzzb8~3H)QKG4RgRqQJ*fa|54GO%H5PJUp;@alb&P1z~bUH0V|3>4_H&YFkn;h?0_A`?*!~AHU=CiE($nRoEvbyI4$66@vwl~ z#eD-F7OMfZ#W4Z(OM(KLmiPv=E^!a=C~*$(Eol@GP*T?|qU2Gxgpym`x|dw;*01DD zw_zneb{ku=w_8@p_HOwl-*hV}`Kp_#WNEi|O6GN&RWhU7{1RKYB_(CuR+i*aM*@mvtRnI=}0v(wSW|O6^^9OUt`X zDV^N4yfm|`wRCjXX{7_Z&MxiI_2bg`uFFb8yRItr>$<+Qeb=p}t-J0jb?myg^ripN z(trF_zVwR!)zY*6w@QEV|GRXr|9_?1{a=-SHdCY z7XRR~691^OiT+7t>Ha;+hWqy~>+3(PO!XgI7VV!|7U-W>=HoxLtgU}lSqp!ASp)wW zWzV|IDZAfgQQ4neJ}bM>WmVb9E*r`YcG+51-DOwVmM(kCzV33Q?6WSX$`*9_wQOdW zD`oaBH_OVq+%L=T^0aJxmltKDx-={w(4~2K_bx8wv0XgMgS+^Yck0ru+`UU!xl@;*-^1uBCmS6W9QU04>TKOrz3FQa<^2@9Jip#h7Rh6&tljWcJ%_v{sH>Z52 z-@lq>ALuMHNY%D=NY}TPyrKzgN+r^9L2JJI}9h z==^ELi%u&l9(7t>ajVnDic6iotN5kUu8PB*_Eyw%I#RK<(}{{Toz7M)?{ukRL8m_} zW_G$$Ve9m;qO{Y06?vUrRb+H(Tsfjs^UA)RTq>1L9+gp@d@8$j@~`yj6jJHhDY~*r zr^L!vzTGST@$FlA+jnr~W#3Vir+w2akN8fggl~T3cfM0A*ZNjge(r0l{Mh%s%9*|& zRN8#!RhIcKuFUgYUYX(hRpkiZ4V8U;w^S;=J1Qf6QQ6J+V5O(;Pn9mdzf?Nj1VV~EPH9n22w)nKD`r5~(YMGCF)qEfCsu@0Asw_Ui zRmDD$Rk=R#RcSt=YN$_gRkF{3szjgRRbf6URet($+QTQes-;gsRU@C0s#@==st4Zo zsz1G_Rh{?#pz65yysCZPi>tPKFR$9@y{hUQ%h zGQCe!jq*NQ)!+MKm98GFiuS%$72tip%FFwoDp&8?swUpAt6q9FHa_-hZoK8?V!Y(# zZv5HH%XrAk&sgmhXx!`-Zd~mZYh3DOFwXVrVVvgG*J$z@Y%KB`Y0UOYHKurF8V7kz zH1_Z+Fvfb77=yg3j6PmAqnp=z#%5l#jITZC8lQMBGXCYc%y`*zrSY`q*T%!18;v!d zTa8;hcNo9+gmIbYe&amPqsHl;Cygf0v&JINi^govtHu=1o5n$&_l!L}9~)ym|1$=8 zzBKxHHZ-|;HZ?W#bT+;2*v9lv$M&Y%9lcGzckE*NrDKrkP{(jnb;nrK=8j3G)g8N= zmUQf6`l#bT(|a9HTiX@GkJ8VXLjn~U~bT%x%t2L zt;~1Zw>4jF-@$yQy^r~5`z~g*4>E6UA8uaLKE}MPeWH0@dtsi|KG|$)-``x+eu#NO z`;q1`?Z=u2v>$JNt9_0+x_!PmpnZ|qvwfM_rM=PY(B5XQ^LW?%x5rHLb&omb^BxP# z$2}IC_j-J0-sZ8=yx!w$^9qj*=8ru#n`e6bV77YfGM9MlHs^XAFsFJPH4pYUVeaX1 z+8pO`-W=@lyV=L%nz@a~O>J{Y@wzE34?Pz`O=3{-}=4ZX;7GV9=EyVhh zTZDDDTdegvw?yk2H`Th#t%r4+ZgLew=`=%w@jWIE3|sJ6!dc{Sku~Uu?}hTgSBUyoz}QEnl-4+UaNPTgI3ozN3D)+ zj$7+of3`k!J!`%0dck_$^>^zr*Q?e&uGg*KyWY00b-ic(%=Mvlp6e6qG}mWVqidbD z(Dk)7)3u>(q^qN?uWNIg!PVIo?&@Omb8TyLcWrNL;p%Ct=jv;F;?l)-+ohZBl1s4d zluNknfJ?M(hfADoqf3(Q3m0Kq=+eVB)1|k~>eA0v>@vuf<1);a;xf`U&?Uw8mP?u~ z+GV`0n@hH>qsv5FE0@W(MlMrq|Ftf$-ECcNyVBZdJKfr1JKS2@s$0Kn+thl7ZB^@8 zw#BXI*k-q$XOpczww1MBY@5`2sV%kj=eEJESK4~C{>m2HdaW(6^#+?)>rFP7)>~~3 zt$(mRZ?)5Qzg3Oxk5;>FXIt&F9c^{UrnNe1+tTWoZFQ?twk54j+dgb{&h~bz3%2rB zzuWR!UA3jR`qMVF)lFNkR)5*zTHUt=wR&jtZuO7Nwbj2i$5yqrx|T0&4_dyqU2ECU zey*j1{l}I~?P%G;zO`jb`|6f1_9ZRd>~mVW+uv!~!CukQ%bwTL*Ph8A@-n_;dbwqQFhmsv3AFn3HCZ?gZ+WCuwQfTVL#`bZ2!@@uU&KQZ{OlP$iCWn zsC|j^2>XZ5qwQ}ykF}ROr`z+K$Jx`Jv+P5hbL>5xC)wkiC)%L$T3|1AT4bN- z^r=17X{mj%({g)vrxo@Xr!VaRPOI%5oz~b}Ijy%ha@uHr)?$qz%_HSFjzOuz0`=S>6?Xy}Ov|C#ou@|@a(Vo-dn0-u(llB2EezuDiXY7$J z&e{E2oVT}canbJ7;&*%f7FX?0n_sivZhqZp8(kxawG>ezDO%vt)rUrSnsVdJjeM=s0+Cx@1?I|}k zO_pCa?IS;F+E31EIzZZ*4wA)9hsd0!!(>X+;c`IJky11rEhC$zNdKm((xYjbbZVL* z>o*-QpESvmx0_6m7n|hBlT9YdeNFP@wkG*Dc6LS?Bn!{M+$8dChUUJm)w=9(9~4HOE}mE(tUvExT_w&PrBcbqRv9T&)4$AxmN<03iGaj|^M@lzS)xI}h!TqfH)ekPqA zKbQ3#SIDOhU&z}IU&>1ktK>fv7lkFQH zmrjjO$a;-W$|sFZ$y<$nmKPiSB2P3rE%!A#BY$XgR<6_QvqtCSyhgvu_Zpp-RgEsl z$&G%K;~HI*!x~+Zz4VH2^t%jdbXj^gx*}Z~U6l@c)i(S?-fwtKUTyfNJfqj)hSz0v z!yEG3hBxI(y%sgRC1*CgEvu-DvPoUeN1UgGX|YUf(r%EWg%kX@h^{9KGIY@I;pDmDk{@Ow(&{gMVcYy>*NZ(7U(sj{tIc+t5B~@y++i3 zDf{S^s8^_7zV%b;id^g60njb5AeTBX-wy*|*(u2+d(xq7AO zH9#++SEOG4dU@#Oq*pz?{(1dc-qPzgy-w)0SFa!RTC3MGz2@rmu3nXTgtC#YMUccydNUxo*UdV6s`a-XTdcFUuPMY;9(ktuL zb2&<{zIqv6)ygovI_uT;)ic>tua__XlMnT}uGg%*7- zNU2xZ%g1t}Ua2o1$w7L(_41*N)~oBwzhwu#oL@eW4PM@tPhZ@Zf4#UTFX?sa#a+4o z#T~g#uk|nflFMJ*mh<(R_TrW_zPKq1^cw%-h8+Ilx=eoYr%cc*_{BBp^WqQb`r@i| z)a!ZO75Sj(0s?y~fm? zkpt>ZOSSG78CmzU>{541deohiE$Z~wOWkq#&+}vQ=JTKAZ_j^}$DbdSd!HYX-#T+vL64ALP~A@8#**t@3c~7P+f-v;4MplU!N*ja*c_QO>O0Ag#6Q<<#1>GP`z- z99{dh>|gtpRBBhrh}tiuU+ovty>^9cUi-Ox{p>UO_}Maf^Vt%4;n}D1__M`w&$C7H z`)3Q~nr92-vS;)EkD;@UYwG*M_)k$V5D~latI}PAvF*~$M%ULS-7y1091ulPdA%Wky5YMk!h~*b7#PEMCMDaf? zu=!6HSp3@y41UrAjn7$#;L{hv`Gf@u-*X|9Z?_P_$1D)}+6%$_lM6xoeG376=>Kc7?J-&@-tE6wfTADr9H z-#)jEFEO`;KR>&PKRheRZ=2n~ubN%Y&zt=pKWBE8modA-dosJkyE(hSyD&S;OPHPJ z(Pk%k!LwsL_t_Di?d%W_Jv+eDn(gJCnC<56o9*Onoo(Z-&9v}lW*T|@GxfaYnOa`? zOchTsQ^ET(Q_6cYQ_OoXQ^-r1$>Sx?hCqjo_BOQhPQJ%iYGPA;w?|ndE--5 zUiVZOuWpLWE1DwmeoY1OvZwrc&!>EOcc;90m!|+vO}X+Sr<{1?DMucD%8rMdvf-Ie zS@H~~%y=qO5bwwoiYGT^#M?M!z+0Ns<&8~h@wz6}d3BR2yuwLE-p|PsysXJ%yyufg zcy}ic@-9v8R3_KBM<)MrN!j+u($Xy=KoG^}gE3of%9s^5am0=jId1Ey z47YN0D_1-!#myO&;AV`jah{B>aBht*a*{@8Ih@f+4r6qbLmVCCc#ZaQ97a1iCZlZ} zz0oF)(r6v$&}bD$cC?JMakPlDG?K>|8xe52Mt*VXM!s{3M!s-sIL@tMdrs1@6^Aoy#$gO&IHY0l zhV`%k$8lJjV>+zP(H~akC=Z|D92u79$PFLjNDlAiED!DEj1O(+^bBp`Gz>{{N`}^R z{tT@qd>&d#cs(?i@L*^%A!TSZA#rFRA#SKAA!4XKA!w*M!F{Mc!EUH30W(yVpfgmM zpfDs(I5_ktVf#>Sg2d3*goVM638RDW6FLXqB-9Q*PbeCEobYQfEg^d_HQ~kJjfDGy zR}!ucCMBF1OiYLw$M(OAkLZ6HAJqRe-lP9Pyj}mD zc&PtIyl(%Mc%}ZN_(T0?;&=3O<2Uxl#xM7={J-A+#n1Gv#0~V$$F=rO##Q!?#O3w&$NlK-jQh~r5|`dvA9uI6GVXG3 zN!;n)ytwFII4-O=H!h&}OPpJ8R-8@m+cF*j*QUqq`#ZLU&PYLboWE(fvD?)SVOS)BQ0P*PRh- z(fu;ksQYQGdUsmvf8DoZ_jX^4mF`ZCUDtg!cD{=nJJJ;s+u6m8t?LSpE$#}5{oNH9 z`>D$(_H~zA?87c>?2Rs)*b7}|v79bcEVIiXHl#}{7T={3>(q53*0SqJEV64~tY(*7 z?1`?evHQC=#>#Z9#Yl85#VmHt#Ef;0#dLQL#58nv#gulo#0Wa;V!n2k$Gqz-jCs;2 zjJe(UGv;FF*BE|hR!n5)n;1%GdW?VP!x*>DJ2AGMDKVJNi!r*Li7`r@yqLqCF)?zT z%owT8@R+|Hq?oA=|CoUeub9>jmzb&!`1JFy=*vPE1;dT1-mE$(VB; zM`PkU_QlXU1`l9!DbVSQ^G)7BwR7Wqh zmqd@Z=SBCl|Bh~K&xtN?&yE(gzl+Xke;)n5{b6)^`<>{!?J3b$+Al_*Z9f|w+s=)S zXpfE#Zl_0kwNs)U+k>Oc+I^!9+uftp+p*FAwcAARYd4MF){cx`->w(E*rpym)}|2M z-6kL1*tS2qtW7Rj)V4J`r)^{O`?h~k>1_*9ciSeTuC@(Foo(xhifwC+qP5jU5!%Y5 zyxR(+ux)}Ui?$z8Ms1&>G}CvqtaR(qOP}EMxAfPL~&XXQLI+2C~~WElwa$AQ7)|q zqikAtMWI`_Md`LmMk%+hMILEgjNH{a6}h=}IC8C}J94h2C33i>HnOv&EV8a8KeD9d zPo$tFC-Q4cc4S7&+sJ1v&m!-%q(xq7xfOY~0b8;8Hv4e%752{N^XyH{Jodk)81`%voju$X%I<6mWY;%&vrC(t*}^6}c21KS z`$Lm4`+1Wt`+k!e`&!cp_PM6R?1ZM>Y-ZCoHn~ZX?bq~=<=V8svTd4Rfv*8(={I$< zRGS)E$C@fxdz*?_+nNL{iKZW{rN)n}iN?3A{>F4xYhxO#y74Bfu<;V>cVi;!b0dfK zwlR|Rq%ne(+DKwuZuDcFX>@1BHey-yMk^Mn5yQea8nB!jHCWb-iY#>FQI>AwUY1JZ zc9wjj6l+i88dJJ)k-5HclDXJ0$ed{CWcD>QGFuudnNG~ba!TQb2j{0@Xy80zXN&O^4SUI)e+>S0DweGY?PpUH@-f5o8IKV}5i-(h&yUt{3vFEA|Yc??v2G()GJ#!#*g zVH~aZW9+GSXGqsOG9>CP8B292#$=ryqrXm#(N=eYQCoMAQCzo^A*kER_*S=`@u6;+ z{=9CQo>n(ZzfspkPpWI8^Xn?R!>U>mJe3b*Xf{x+`>* zx^whnbzJ(sx=6ZA9hJVZjzIrgi>J@jy3mJe?dYAgru2qdBYIh_7F}GcM9;02r+=*7 zOMhJ}Lw{T=Nl&d^rCq6=qn)iCrN!6w(wMa^w9wibT0m_v&AnDgbEy4JGq25}A!}dL zv}+&JlxpwLj?`YI?XEpXldk2`Bx)mR%QfM&sTu-pu*QehQR7UjtFfh()|k*lH3-^| z8ckYujRNg;&0*T(n%%V28fn^<8VOor&2mIS&2$8-W+;ME(-{$1(-7fVQxSo!$&awC z`4xex`5d8J^DaWACOzU<&HaddHP<7y*Ca(q*6<@%tD_@kt7#D<)uf2-YTt;aYS)OW zYP*QSYSV~6)rJvYt2HCuS1U$5uRaoyR=qpoMzwUr#cGL&)78t=*y<@Ny?T%uQr$uI ztFEWISC>&8s>M|E>Rc+a`Xg1l`VCdN`UzFO`VMt(^;N1&^*O3!HHW%d#iq_yg;7VU zf~Y-JUex9)9JQ*-ids~KrovTv)NfU))Xb`5)R$HJs1K{QQ*T#EQZHAnhM%pP4Ns^V z31?Mxhf}H=!-J|S!o8~U!=0*rg*!ors;gTkjPy~2kovEiMSmf?++sPM{4-SC1+E3?9!D_@1#Rz3_fsk{|tSa~T- ztMYW1Vr6XD(Mnp_o=Q@fOr>v_WTi{kzY5#1xe6$3tim9yuR<-Xwc>bKZN-7G(hAuy zafMV^ZpA9)Q^hRhUBxgZy`qb9zoLP1qoSO0u|iBaQ;|!FtH`D>D_&736^|%E6}Kqf z6_+T^6{jgS6|oeP3L3?*f<)1(z*CeeoGJ1ZHk5r87>aC#K1HfRm9kcTjIvO^k1|m% zLm4RFKNlq&ZBi}3wBwsG`ASaeNkU3>${oVx>`}IZ zj4hKQTa~SX?S^MU5M@IlT4fy}N@aB+@?|9<`^y9&JIcO=Y%Y5rvc4=mWV!TS$V}?Azw=|A(^FmA+JhRLY|b$hukgQ6LP&& zIwZMteaM;8MN)j}7>QllLkcf#A`wd~NPeYxB=^!>61Fs(WL5f-1eHD@8J6B4X_Y3C zluLP}W2KR#1Emzw&e8zV)>3!UhEjXdYKbXnuEc;eUZO@CDEW`nS+bARSh9^&RU$zu zE?FW9OD2f9CB4MYCC$Y5C6&Y%C3(b0CAq{qCE3K3l2^p!k_W`oB{zuiB}qhf371GM zVG~Iu6rz8LKhdMajfg9;BifWeMAH&|BCcBVY#@BFjFidj27n*`iegg+KbZ(4aN5emBm*HMa78(VR1Ymx0p`&TudUo zFZLn4EOsJ1F194xD>f$FDApoeDpnvQ79S*Vi+2#BizNy4;=jS6#Z$pS#RI|k;?`id z;_6_>;(}nS;-A4#@yB4p;#a{s#Sep3i*E#&@Mo=5DGY1s26awP&r_K;gNuyg*yYb z6>bWUDqQtnS2*pzQZV2@SJ3J|UQp#fSdj1EU6AYFT9D;mU+}`evf#ddaltizaY3U0 z?}9l0oC2Ev#{z&>> z-s_*OkAm8+S58sFR_P%%X zA>SMMdcIfkm3=SdAMrhtFXzk2m-3Ct|BGklPvWWhefW_4W_(b7IUb)c!h7WB;GOa_ z@b>vn@s|0ic$55#c;kFNUOzt)uazH)SIPIopUii`%ja9+59Ax;cjs&2W%Ezqx8(1~ zZ_Edu8_!>lU(Q?bnadmTnau0-8P2Qq>B}qf>CF4>(~|emr!Mc6Pi0=3Pf1>iPkvsa zk03A3CpVAg^EEHnCp*v6CnL|^=T)AG&(l0Tp9gu$K6mmC``pNr^SP2I>64VV;(a!6 z!kd@Z>m8fd=*`Y6^QPqqyeWBKy@`2my#w+dd;8?w^mfln@^;GOc-!YOy{+;{-llmz z-l#mRHzLp6TPF|Ut)8dmt&}J4eLQcM_mRBK-Usqly>{nKd&%bYdu`2Y@siA|@LHEA z^7<>z@mdgPcuk9+dX0;3dku+`y?VtwuMRQGt65C;su$zEs>C?2Qn7_sf!NSXC|39S zEk5S;UA)`tvv`YFmiV9NJMpyVOYwl`Q*n#uLve-YU9s5nrZ~s*nmEJrqWG!jIq_}J z)8b@Lj+o~eD`t7J#UY+FG2SywjPoRk%{_y}2v1+Jny05&-qTgQ%M&Z!>}e-n^{^CA zd6q@>_rGSYmus(x#*}HB--g_ERu3Vh*n&6MU$?YqFz^3 zQKPG(sMPhi2zHeheRe%0dhNPT^uTqOD8*G)l;|ogign#2qPlJr1-h;ixw)e48zbg31JT`Gk+E~UZ@mm=X4 zmptJu7lAOz<+qUI@Tg>5LUFJJ}1zoUDaiP8PyCCsSdO6Gr&U z2`S8WLI__t=?U*SX$dbosS8gzsR$#T6osKq$A!L5@aBnZ9*xhEy5L?lyDrkLD-F3C#=V<3W{;dg5S6W!AIPz;010wxPluIoW>0b zqHukJP+Ygb7uO+h!nF!4a7_Y3T)jXQS0gxzs}$_Sl?kM9#ex-VfnXdf7Ib3;f_m(4 zK`}O0@C%zG$i{vZyuf}E+{0!GE@R&dPGR2)BC)Roq1fjFU+gmh4*OVOj(s3NVDAZ3 zv8jS1*joZQ>~(=8_NrjX@seQ7F%cwSKFcvb+`$q9Zs@&s9q34-U2v4T5}(Sl2k zYysbqAz(Su1R;*$0w2dv0oE}@VCqN^=sN}plpXyAhaB+&Sx0Zd21gIUqJx`Y#KBq6 z;eZp=I5-IM9qa@@9IOQ&94rM-9n1u`9ZUqt4rl?#!C1g>Fcc6S3(pn7l`cl3clIz7QD0HDR^Wr zE4X1VBRFR-Er_$SsxJ*zb;DQfI^i>R?QoP`D@?I#hJEcCVJEwK z*ut(BM%Y!us&}YzyHr+kCjwRt(qL3gH4<7|yl*4QJZ^f}h#u z!l}03;bhxyFxU1A%&`3g6K%6$FWXGm-u43w*=E2xwr^nt+t=`Z+n4Y*+ZXUU+jMx= z<|#aA^B8Wic?4J3Jb;BZ_u;QLci}fSci@LMx8dtHH{nE^8*r>m3LI{86%Meu0=w8; zf~{fm}E_Zy{)ORgLOD;VoiZ{twUi&YchPmngq*O6XA8%!SI|_ z5IkrV2)A1K!xdJ3u*k|6{%Yj|zqRs)A6j|A*R4F@L@ReV*2)bIw{nF8tejyND<{~> z3I`imVPSPE2Uy<99^PeT2TNJm!Yh_G@VKQl+-+$I*I8P?MV999PfIg6%hD81w={w8 zSVHhcOEk>0M8Ql;W0+)#guN_{U7_vmbx|Rm8f~7uuz)}z1W~mGR&r%1Twa|tK zEVSSj3r)D(LIW0BsKZ|@)ZjN3s_+A#6blvjtc5ZhW1$3xSt!E(77DPl#Yx!0;sk66 zq-t>-K5FqFEN5{Hmb8$Em(1niG4rEvr}+`M*8DJB0F-Nf2>xJx5PoWY0KN^BWWFEf znD2w>Km_x>u!s2`*bWG7z8lsu-vyrl+H1ZO-U{^3Ob(tl+X43hHJQo6r9iORcK8#} zOEVexKF}4jZSZNJNHb|T6bNs&6~+RYnQejfft1ZQ!-s%mfh5c}!3(CF;9*lKxDBWZ zNNg$z=K#F}dThE8z5#R|D9&^POa%%Aas{$Bm4J~z8bHT@cA2h+Hvz4ftcNFnx`FCV z*1<(UKY_A<(t+*(T?7K_^-%A_&L0Nr{b8`~AO7F} zzzzUF|5Bt)z&--d%CY?>U_SzA;p0h@{@FEX%3R09d~^*OuEm%rb*({NBzu$8nl-3) z-qYl=XbloyAewB=2Kxc*W17f4ScC4q;hH>6T!Rvj7frs0twCNTsV3goHAu@h-Qgkd)o#|MGn5g?66677(X8Lx^5;P$(Z2IBdBE-Hq zZ;G;8gnIsyFmvf&fJ{DaH=E)wKuM;D%=YbFfO0F9%nIMlLrnqtX6rEXQ1`g0nW$_I zs^wzMw&CZXOliDXXWuNuP9vM4XtU5!l}I!B*%|0l&MC92F*A^c^%b+k#c3#|?w*-M z%rw+UcxkqEW(ty;{%H1qIt3j#^~daM&m^={rqs;KYZ97FYcxwNo`ABH`^=1x6OjA2 zDYNKT<4~)`KQpx4IAmG9#r$&o7<4^guQ{o66#6}S+`Itne^45yW&ZK`2$U;{Hdl}s zfs$|9nja4sh79FB%-`e;L3tU$=HIsuLE1)ia~I+ul#rKT9{F_udgh#DepGS*dewHz z+|9KgN}@b9mwVI)S7EI;h~!Ym0*Owa`hMFBU#&HIQ4Sz#`^-HRR@1ZgJ#S6?CGr*#cKw z3FVOoEVkBFK>8Ci7EW#DP-OJ~EaiL3pfjt|mht_ikbmNSOaFlqXwy~&%d);=h<{zj zGQX<`677X7?OF<eCAp%-4;Qc zj4oRKJSBu0ex+J&p$H(lS-NEp7KSSGGcB!j{y>X%KP~lk{)Pt13oYMI{e&L5)LCYi z{}97s1n%1ZO(Hz==br`7Q67w7;{-b!2e8Pe-l zvs!=U6C@jIWEJ545y~90w6Zyv4atVPSmm~7Lb{{=R=JNqKzky>tt|cDL%Cxy;MOPu zI!a5lTCI5tS&XMxsa$#kDbgNV^+2zoqOmttO4BbP<%q9VOHW@wHlso-cieO6czA^s zdifcYJJe$J@!3;wyg{pvHcue={#h%`=p$%^u+G}!%0r0Nwat1(^#SzB|A4hx;eF^s zi-PrF&^;*FOV?Uw=?+v;3t3BDO@(Hi9IPqwx1s7%FKe%?n-JNCWL=HE0euoNt(yx| zpf4DnHO=`NMEicx`dY&ks8#olH5z{zT6>>v9n*RdYEaCw#^947!qcDDHySQL=?99e zBc0DfsW+UtSN`7(NYzPzPph2%Y{=*ros39zN^`nf#TuC3)hZ zpVa-fsB7L(N9#%3XJSw2m4l9L>ViA8>nFzcfRY=esA_Mk=HUXh-Sf09JM9D^HW6+A zy~RTM(G1()RSr;H565=fydAX9IoWn(uPwCt>$a^o!WufO^32x5%@TT>`oXq`W)3me z=i08FH-#D_3T)p!fS``X8ry+PG<43q6Ht{gRP=t-R;I!T%GkSPyWEU`)J|`-i|*Bj zY=?K)ogUGJBwUZ!9iG&NymM9T?4~s#yWn>x3%wZwhCpJ**7DUcPpZ zyA`2>e?sjZHJ*fIPe$2klpcp3UOa7w{dEiyO@~RzkNg!S{&7|e={ZlnK&5RJN;M(?SE%&pPaac zIkVZ#-pyeZ!yyOSXYW|SNaj)PpVls7j{X;CfBg15rhs?O-q3Xx^SAlBeW%Pc1~zzP zf1q#zv*X5F`vKkIuUbM;iuy+(=!-9YN2Do z6+Y&EcCBM<0|$ef?{wUDG#-)&3OBW9DJkX6jQ;orByN+XZ`iwF1mzJ@dIYUgmP!bm?VSq7R zlEbyj=wjHKM{)CewJ_UBs<_uj)G>SRBXG0-sbJ2Ro8wweC}INFJK_9JoWP{(`{Lq` z9m8NlLvdP%z_+5^kHnqXbr929atcS^vJdn7?`7P=>Mo3=`aRsii5-~FzAtc1Z8Dg` zOW8QR;;k5yAHQ%apEqHS3>M*X(>7uPcGu&EPOZmmH0#EFB&?yg(Z+H6EdHY7?k(dE z{I`U*5=%Petj?jM$K{-6>Zj3C`;Iylzn?%any5Nq&Wxh%DF`Q=+Yov+#oTH2ct2Vu z2j^rn)s5!2e1uO%T5aw)o7jDcb#Ug zR-kLXJ$JfdUy815%5uuvScFzu`RSDQD-Yd#u*hjUTZkSou5K))smJjH}@x#t(3h&T=H>)^H6}>{2oG@^f zqdZ4XV$7U>Nj^n~d10M5J$r~oGJTw#qQ?0~ zb`1KSdxtYoD-vxUGUD8j!9b&;7o0~GBG8HFBwW%TQP2l&ZFgDO8G>GYdeCM5d@x!g zQ_r-Q^a= z7G1TF;PSl45{+NG;Nq!hhSrq4#N|~B5}mmt!^KhufyVF2ak+3_7mYh0 zcA++EqLU9-y38x8p*PF7x*U&ELRTCcbeaEi0^Rc8tP6G1F|^w8|G6e%52FSDNxRzI z*pI${Y@h4t>__M=>XCT~GM+->9fRUnBL$-23EF04nZ zYz=gMsIrEt-avIt#;>4qS7TfcUR*%+%$;?0{W^oPAG_wN(>Z~f?n!gaks3ucG`(`| zRU1Stmw$5ohU-P)MSoni8J(!buO+T7S6fjvZyH<=zHLMerS-U864jzmS0-GaHCLjF zxGS!~6Q!u@5n%V3bw#LKzB}ETcI2U|?2fvn92KCf3{~AGRequ7P9WTtbibq8WX;{) zBEO*iu3+6ZK-nnQejhg})Ay*ZiV(L?CT~zLa#(JgF)vV0z!z0*GJ1-tx^U4gOZy?p zfR^eep>z*b<@(HR?ci#Z25ilh78dB>@!l)oq3t5(UV z(~Vm0Rdoc^lTRpj&bt8A_!S%XS{@!1Ms{;=#Cf82ngqHh9dShs?WMZ+4P#NG<1y|N zpY2cw^Uk`z zM^3T3(y|(AM{>RUqiiKqidVP0FysWvP;uP-)_!@E)ZCK$p5lY3Rl!CN%h!6a<71f&D(|?m$7JLdlI+@{s4X8}lB% z^_bk+Y@Fox)q{Db&iLaYp~rLiD&v*rGLPg}rN+d&O&&+p3XO-|`aH-VM8?--r#yl+ z{un!#{PmE@_+hMlZj&cX@vE^qW|!xwC)vhU^G7``_P#fcf3NEK^U`bMA_Bs5U^U%X zcfYx3Uc_VLoHDGZXUlzK&(l7h53N#-x9f#?-pRaf+}X$UwAgdSxHy&T`7%DqxYR1y z^JnW>Umz*-T1-%&0Z9alkr1nx0i&--Z-mA z-pf_W+PLn#nwO8QnX$C8q1V1-w6SZkx!2WvL*sX0IIrAwdd54q;Juz8HH|O64)H=W zRg8C7vAnLoIBEQ$V4vZ&IeD9L zK+iX?kC~f{E#gI9yJ{tj^<*o&wC4XIHD5G)ZQQer)Hmw)x~)5hv@D(S>cCDS1N>LL zddMTlGZUM*i1gTiWL=2tUs$MQ1d zIy0;{y`d24Q|j&Q&@MvexRbp5x_=`NwllnueczFZB#yU3-)H3H$OZ3%J( zP^7WDp3mV=1mvd@$fxqMKT^rm-p7pSjlB28!za?n4JoA@>_e8uAsJ~AJ_p)tk+srs zK3CsaAa%KkKB5>1d3p4j&v#QKvco6Mhp|~7sap8bXRuro$<+JkbNq%1GV}2-pQElP zk$szseA;)&Bjwn&J^|$ikcgHJpJz$Ck*;PVKCew=k)+r2KFs+oNb0ur_|-QXkzvej zct^0$k#FrjeBhQ9BXffjc*M6kqa$}T@zp_-Mx*mcy!Mt6qYv&@c(<%RBf=+Vupw5b z(H2=h{NP-(QF?eN-sg6mk$OHGe_f~2=*>|+{z_S~(eBubcw9)H5wqepzTxj5qhBYV z;!j@xVYC#Vfj2t-#prm&H~h{|nMSDpMEK7pZ;i|%%khUwpBo|an(+4SkB#>2?!%k4 z-ZSbaOybu9Zy7zwUcsO1xoTwfPtv!VkZjawE9X1db=Ju3)?wd#Kb}!;o02cJA=XG* zLC?1p%Qmu(fP8m}BaFg7+4=59gc`*zy8Cv%3O0&B1^Gtp@iVgHQ+;dBcpAwFVtoIO zIvagoch+~@&B4gt^r~;h4=W=v|DLbz5mTdMzn=S^=NlW5mNI>xx9b~S(aZI{YOG~+ zkCyLima1ZO@l}L(l?F;uH`@Y|`{ zZ}@h_(@%%eX}C#&;3xm0+0YzE^J{CbHS~>%^P}vkFm!&D=qI)>GCU!^<~P9;8CDP8 z_Z!aqW#}jU((iNoH$#y|wjXZmN5c(HKmC5_XBZx36!^`9{hfAStM*%;_{6X`qs_1L z)qTUuMT36Vif$Qh>znbD9lB~rUi;@qkW4nbyKjsCg=1$8pK9&)=OMX*7vt({{G z4gFO8dq_;fJf?xaOKiBI(m7NATS+9tz&j59Z&CvcBVK#@-+1P2h|3A~$7Q%0ZY+rK z@BHLwc(pdx-|D-y;YjCMfBsKX!-Jz&{jdHqHat9k&!72I-*EEZbAOfZnue*8S^nQY zDI0Fvmg|2w(hACWd1 z_8wUE-|W1GklMc~z#h4TSlGQYfOKpI@ny%608hy=1SG8-aBQd_k-AYYKvdL;_`Zq> zK)-HAyq>iUNJ*?k1P{9f{PHhH^tT6qH=GI)`qg0pPo;$jtT-ybr!yC!{pD1^X!aLG z>+?$i-lsDWPB&8no?zb~E}wcDAl#phxK7Oo_}%>g;p_P=AoWcuV!}iiU`tCu*eI6; zG-_Q$kYyVK%%{#G9OkGxtl#z`jP-V=$yq_!|b%4wNE)0;$u zL(u-fMk{|rF?1r(VbK$@^{{5(qgT#|?Mp_1e%_7}WI~3MzUeHaPxVG05TY zZv$n5PSB@&-wX!j(Lt*_vkd~;tb^1pzcsjW*ChyA|J;D>;unO7erT|LYiQ7}!Bm4_ zAuFifGsPe*mK(&)OEyqaPYT+qebykY^F|QwKF2_K<6%(4x@dz(=C6bHlIaE-GarL6 z#i0hwr@w+6RD%u3*uo&wi+F?W%hf@L2iy$8p0@>cn_>;39S4K1-nTZ;o0|?gK4oH% zp0*nF#1d&BG}#m^c~{rqMz373`=FY^jthr_uNWv8KuSu%nP-j~94gca{!zNm;B^Q( zIBS=jLAQiWaEi}XgW|_7!T3iT4E&LP!8hw);V5cr-xxQ9Mc5u(L0{!BMpTPrFu)g$4 zesIIT@A`}9tAf8Mf6~9aqc!-9ONM^o{r+H7+zb78|4jw=J$$5Z@Ma~L3*XTvYe*6{ zbfxHHKFSi}*OK*r>K!C>9z3hx@#Q4Jz<{Iw3heI1!A9xt`ivxeB+~RxYFiSTV#)f= z892h!#Xx;sMIXZQeQ$k@Cq%;RYZv{}y>vp?XM6o^SK|nOep~2ItWP9d%SY?8qpuQN zN)7by4&Ehfs?^l?_f98dS1IX>3*QqQtB&ax8{~iwA0N=Crwa*z#XI#s$&?WqMbi4I zu?+-^+>QEsySfN3vi|8IY(@zy=?i)@@8=0twta$)XVgAX7q>#a`}2XIEaXz`>j{{#+Hbx|E9OL-i@gHB}=c= z$DerY#v47I>`>ySh-Z4*l5FCDWtv{0H<$S5&@H`%cNd5$Qkko{&eJ69wu05LFN#Ui8tszonUIigVSI zaq1;@?r_lCeQTVUP;H@?Rli7-yN=fD*egML>1d$$#B&?TV3Vfa%N}=v6@=H?7 zMuDzhN*2lQ$#>l+-+quf4L|DA+QcMM#arFNbrqyhLb`6oi6&Cie46e-s~*z23%7K4 zg^ZC>c3;uGlej?o@7X!sXHVCKd{g7;B7SWRasCpm>(;P4WZampyF76;Bn2kxDoUw@ z7?=m@wj9z6=@xnE?$ySG+%R+2Z8EnBvH4@Gd(7P>WCPMncY^2}lK&B@YsL-39By?9dhH?7J#SCSUxnBYjquT-1@R!;3yZHqd>mLkm4Y&Psfy z)9R%`)~~&6m6 z$e~G89j<^)b|@z5l)T`QF z)`m=Sr<#GzosJx`R*;5{-ghDS`b`BL+v}xd3Goq~I&wYv!t@@UMpP&H(9!KWF0#X9 zk*$=DY4;47!&=jR^>LMKb8kWW^l7P3#orU!m00k}%B}(JTL%t?9$DY1UD|sh6mhIk zJNCUsC=pYseK*oD^o4h!whGcLbcF?LYyPtj4Y`=3{StN$9eA9jopL%Ll=JDe_OJ;h zR4MO?_Sb)`(Bay<+A}{mp`z{-?I%&^LqCouY5&ql3C&qNrES-LFSP!DaoSc7(nF=C znA+J+??b(}QnW8gd<*@vEl9iiGaQPM@zzcv7KheJJ8Qp_s|`KB*;d>5Pg|(d22*WB z*g&ZMs-gCiol~K@vs&6wxyzvrLrU6Tf;Lc2waRM;Ny<vHntS4k@4F=w#j2XSs${c%0 zS(JIK)e`%Pa=bfLi@H9WLjQDCE9l}6O6!^PT0dmP6p9m1EB1C7W#6G_t$X_#C_{Y_ zT8Hj;Qd-`Vv?LA;QzqGdS`K$-C`yLzTJyVBDQA}*v?Nj_!~U0Rp~cuN8}=*?r3Ibd zA4WFN)1oc>7v?;rsr+pAI|I*r+-D_+r?0ex>Hw z^|!+Eju&di5FUo5=l{{n7rqR8Oa7+Gl+OxlmdwDXM>XDk1>g6!Y-{G2wV;jQf90;1e zv~A&4O+K1U-}i(!6J0bjB;>=lkK1b2*(-;$qf9m3Z|H_~LW$CLL&_z!8{{C5w zFM@O7uJ}<6?!wjZ-{n0TcU13&`wxYtF2hWg0Q z@Sn3e8f|;>!(IKdG+Iq6!jFhwX{b^f!w)Jy)+oBx74CRBRpaaD;qXsmS2U&@X2KmE z&uMU${)QiV$I)=zFG-b`iqwchY^VAJg=>ts?xPle57u}~J4R*5`e=N;ph9&ZIcvx~ z)};pK*l1*bMp55xHqm%eXh~J`MrbrQW2yZwH8lK3JgJS-CpFZU1E~_|!x~mnVbqXw zyENX&v8fWJTQ%Gdai~qQ5*l_V&QXV4m(?$*T&3#Wo>JeYd54-)JE-2Q{e&7T*Qq|C z^M=aCHmE!3e5AfjDp#M-%%vU@Jk9SfUOdNK$WTUmsy<$yXmN-5Svi_WDDA-xcxaR)l(8 z`r(M???m;i%L)+&ZFu!Ewq`{2KNod1Z^MYpBX;U#DANcab?|cp_?TM+5#XHF zz_~|&YfuB%5&^DB4P09UxJET_tr6gw)xfn!fH6=5V-W$yL=B8h1Q;VVFjf&@%+$cx zMSw9>17jHh##9ZAEe(vZ8W?LD7;`l+_B1dDYG5vCU{2J)+|a-rse!qofjLtHb4LSn zs0QYe2If=^%q2w8LkB&i3VMkSdP)`a z79I4MD(E#j=s8u;dvwr)s-PF?peI#9Z_+`Js)AmngPv6dy-No@tO|OW4tiP@^fn#z zxGLy%I_P;-(ED`Y0V==?=)e_0Iy^K&r|{4$p9Xz0=$#~JXHmFD+73}3h-J6@LUz( zy$s;ND!_{wz>`&gH#2}os{pTN0MAwi-pv3Wt_-}K0X$t9csm1lyfW~52Jn1k;Qb7c z0m>i?7$6grK{hZzMks@97GF2I5D-&d_63AL6$Xq3my-bk7N+64wAd{6q zHZws+D}k(Lg3ML|+06tQt^~522{K&?WIGdNyb{QICdhmxko`=+07`%bn1BhC02?p? zBPan@U;<`P0_?y9450*Af(e*H39tndFoqIf4JKd?CBPm`z#vM1MVNp|lmMGB0i!4Z zR$&5WQ3CA31Pr4DScVChMhUPD6EKbvU>zo49wop&Ou#^356CqpU?N4pMl8Tcihz|^ zfSD8lJFx&mDFT*a0j5#}Y{deMr3hGy1(-__uonw3m?B^?7GN?(z-BDKXo`T9wjHd`#j|G@d5wIT%FrXq}K^9;_MZktEz=(=~6 z0G4F|rd0rJ%L0t609cm=m{$R?FAFfR0$^blU}6Qp#w@_d3V@Z_fSDBlJF@{pD*%>e z1Ey90Y|RFYtpHe?4VYU2us0hpxB_5tHehlEz~*eg=n8<<*?`#<0K2mR!z%!mX9K2J z0Bp|&jIRJ#pADE_0kA(C+yf|pdjU4MCr|+Q25fMTpzwc|&H_5BbKl}|B_VFa1ub42 zGPqlDhvIJWWM&TT#f!VQNbyo6b7tb65Fzdf2{EEX2)w=TdT*__?!7G}Gv|EY%=!L% z|MtdN!3$@G&Nw@G;SAw{vxFDU6dpKRc;SrUfwP7e&Kw>%dwAgt;(@b>7tSOeIGcFk zjN*Z_iWkl-9yq&r;SA$}vy2zcG#)tHc;SrWfwPVm&O9DC`*`6D-Z*o* zjWen{&Z^!xv%2H#>Wwq3JI=D+IMcf0Z0n6Pt~<`U-Z=BRPHI8(dhZ0(IRwj0jc-Z*o+;q2{=Gq@Yh;yyT&yWwo^ zgEP7t&gwomv%BH!?t?SD8_x1RIMch~Z100Jz8lW^J~;Ec;q32&8GsvR0X~=sxM4Qn zgBgJvW(7W&8Mt9~;DZ^08)gYUm?^knw%~&qgBxZIKA1VUVfNsI8H5{V5k8nnxM4Qo zgBgVzW)(h|S-4?#;e#258)g|km}$6Sw&8;rhbv|sKA3s9V)o&K8Hg)pAwHOixMDWq zgBgh{W+gtDnYdzh;)5BAD`qJ^n5np8w&H^siz{X=KA5?vnJS-D_#<%=1X3ualqm}$9Sw&jZ%mkVZHzLD`_cIb;4qBCZRewZmbW47pr8KX01jeeLpI%D?ehZ&?ZW|4lFNjhUT z>4zDmGiH^3m{~ewcIk&1rZZ-lewb-GW47ss8K*O5oqm{kI%D?fhZ(3dW}$wVi8^C8 z>W3MrGiIfJn3+0bcIt;2sxxM(ewe8`W47vt8LJa!t$vufI$`$ehZ(FBX0d*l$vR;+ z>xUVw6K1u3nAtjEcI$^3t`latewgVxVYcgs8Lty&y?&VaI$`$fhZ(RFX2E`#2|Hmn z?1ve#6K2JJm>D}^cI<~4vJ+;>ewZmcVYcjt8M6~+&3>3UJ7M6_NjqUS z?S~n)6K2(Zm{~hvcI}55wi9OAewb-HVz%v%8Mh;5-Ts()J7V_jj~TclX5s#ri92F8 z?vEL{BWC6Pn3+3bcJ7ZEx+7-k{+OvdVz%y&8M`B9?f#g#J7V_kj~TopX7T=*$va{; z?~fV1BWCsfnAtmGcJGfFz9VM&{+Q`IVz%#(8NVZD{r;HwJ7V_l4-LQ(T7W+^0Y_*9 z{?G^ zC>)?w_(QXBfOg>z4Z{IihCeh72WT7q&^R2Rb@)T`aDevV4-LctT8KY15eH}^{?JGq zpq2PTGjV`+;tvhQ0a}VbG!+MEEB??}9H6!MLvwL}_Tmo>#sOMP05ll~XfpxOXdIx` z1VFQ~hjtSH4aXi@P5?9=duTfW(0J^j^#nlkv4{2(01e0;0nmu-p%n!{ zGqQ(v6aWp$9$HcWG$ngzO99ZB?4dOUKy$K(_7ngO${t!&05mCkXj1{usO+It1wga1 zhjtYJ4a*){Rsb|DduUq$(75cObp=54vWNB+01eC@T37%yF?(oZ0no@gK`RS@X4VPX zSpYP&PSDZE&!TbCunm4(C9irs|$c;*9qEP z05rT#(DDMH>2-p(7XXc~6STenXnvib{RKb+>;x?^0GePYXoCUJ2s=S541i|X3EE)* zG{jEO5(A(qc7nDT0FAK|w8lVaj-8-A210}E1T8WUnxq}H$v|k7cF-yVp;_8Ny9|Ve zX$LJc5SpePw9Pbi z5Sp$XwB0~xymruf1EKlaLi-Jb25bv0I1rk!Ewtf4XvDVAiUXk;+d?}IgobPjEjbXH zvMsdbKxoXi(3%6GIom>e4ul463oSYjnzSvn=|E`Iw$Q2rp;_BPyAFhgZ3`_s5Sq3v zwCzA>+_uoV1EG1_Li-Mc25t*2JP?|=Ewu4KXymrg$^)U9+d?}JgobVlEjH7Z2fzkifFO7RY~T$Df=9pxUV$KZ25jIR2!e;e23~?7cnWObEeL|g zzy@A}Ab1XJ;5`U}2f+qjgdlhlY~W1@f=9syUWFid7Odf22!e;f8eWDVcp9wXZ3u$L z!5UtNAb1|E;e7~#2f`X&h#+_(tl^Caf=9v{UWp)hCamF|2!e;g8eWPZcq**ntq6k0 z!Wv$SAb2jU;k^ig2g4d(j39V2tl`ZFf=9y|UX37lHmu>@2!e;h8eWbdcsi`%?FfR$ z!x~RcuK6`EeV3h z#0p-MAb3u!;5`X~2gM3rlpuIgtl&)vf=9&)UX>ttR;=J%34({k3SO2Vcv`IBZ3%+M z#R^`RAb4J^;C%^#2gV9s7%4n4R`AA1;gPX|S4IlYj1{~yQg~>r;H8nmQ)2~hjT9am zD|l_B@Z4C!dn1Jh#}Zx~DLgrr@a9P2(XoVAM+(o5CA>RQcz7(~<&nbEV+n7M6doT- zczvYs{8+;KBZUXZ5?&xFJVBQ521(%&vV>Pi3eS)wyhBoWh%DhHlEPDD32%`U9wSS5 zjim4#S;BiHg$KzJUL+|zNtW;?N#RklgjY!l&ypp)OHz24Ea7F6!qa2{Z<7=rCkuF; zr0_gh!22YH2g(9oC@DNq7Vt(%;gPa{S4s-clm)y~Qh2B=;H8qnQ)K~fl@uN;3wW)h z@LXBIdnJVj%K~03DLh#g@McNj(XxP7OA61H1-x5Qc(^R!<&whFWdU!O6do@Nc)g_X zd|ANzC4~pf0$wmFJYg2_hDqTOGly493eT81ykk;$$jsp-lfqMG4sV$h9y4=z&7|<0 zng2VZSPBoCIlO36c+$+_O_Rc-W)82K6rMG6c-N%xu$jZlCWWWX{P5y7DLiiG@VZIi zc{7LiO$HB~IlOQ(c;d|Ajg!G6XAZBN44yf2c;{sB(3!(aCxfTX9Nsz^Ja*>r+R5O# zGl%z11`nPYym&Hr^334Plfk2B2CtqBo;@>o_hj(!nZe5^gQw37-ae!>KQe>YPX^DQ z8N7cocmU1d1(d-PXa;Yf3?4xMRJcVZP7Rul;G=tYr2G5}x zyoWM)5Y6C4l);l|25+Ja9z`>F6=m=&n!&p$gNM-!UPc)_ji&H6%HVM{h1XFA&!Z{4 zk1}{5P2q)YN*O$rrtntE;ITA?*HQ-0r766Z zGI%ge;l-4}lW7WXrVJiUQ+PFH@NAmGyD5W*(-dA#89be)@OH}J@ic|kQwGncDZHOD zctB0z1(m@QY6@?t3?5MvctvIKjGDkZDuajA1YS}ZJf$Y^mdfBUHG$Vu2G6Mpyr(jF zP)*=PmBEv00&l7e9#s=~Rb}w3n!vj%gNM}wURD`AttRlc%HVM|f!9?A&#MW%uQGUG zP2h!$U+Srd3=W$?_Jz&k60ht>pMS{XdGCU4psW$@UVz-udm=e8rfw=#He zJHm@AgD1Bmyt#6CbUVVUD~D&dBfPtEcz8R)%PWVcwfBfP_Mc!)c~ODu<{xFfv9a(Ik8!fPyt=eQ%h$8va( zJHm@BhbOrsyvcHSlsm$!EQe>gBfQIUc$kghWtPL!Yz%L+93E$5c%9|&JR8INEQbf$ z7+z>OJkiGRM$6%mHilPP4$rhPywh@csEy&JmcvtR3~#j@9&2NGt>y4s8^e1ohX>mj zUTir$*~ai@%i+;BhF4n-&$cnV+j4lgjp5~%!_#dHZ?_yCZ)149 zbU8ffM)0P~;ZZk&S6vRzx)HqVa(LK{;ANM?({2QByBr>OBY55A@Vpzr`!0tE-UwcJ zIXv-3@W#vGkvD=@UJlQ^5xnzqc<7DbrI*7~Zv=0>93J})@Y>7ax$gk)y&N9=4)Eg3 z;mPj+Z@wHJ{SNTz%i-DY0PnsW9{vvS^2_1r?*MPV93KA;@cPT)`R@SlzZ?ue2e1Hg zFaaIF2FSq(bO0+L2Q$zC?0_5$K?kq|axeuQz!u2C7<2$@AO~~M0qlVs3_=I62y!q9 z9l$2Y!6Ctf876JZE8 zLJmg45Uhk8%!DD>2{{-FL$DNbFcpSiE977-48dB+!CV-Ey^w>!Fa(Ps2a{n4HbVfT zVF*@30JC8Tc0&NeVF;E(0MlUzwnG5pVF=bk0P|r0_Co*zVgMFI025*WHbej;VgOb| z05f6$c0>R}VgQyz08?TBwnPA9VgS}e0CQph_Cx@KVgMFJ0Fz<>HbnrVVgOb}0JCBM zc0~ZgVgQy!0MlXswnYHrVgS}f0P|u1_C){#V*nOL025;XHbwv=V*pl005f9%c18e0 zqYsuw08^t6wnhMBqYu_b0CS@c_C^4MqYoBG0F$E+Hb(%XqYqX`0JEbHc1HliqYsux z0MnxnwnqTtqYu_c0P~{{_D28%qz@KI028DSHb?*?qz_g|05hZyc1Qq2qz{%z08^w7 zwnzYDqz~3e0CS`d_DBGOqz@KJ0F$H#Hc0@Zqz6_>0JEeAc1Zxkqz9Hs0Mn!gwn+fv zqzBeX0P~~=_DKK(r3V&D028GLHc9{^r3Y3@05hcrc1i$4r3aQu08^z0wn_kFr3cnZ z0CS}W_DTSQr3V&E0F$K$HcJ4br3Y3^0JEhBc1r-mr3aQv0Mn%lwo3rxr3=0q5PXN=W1GY~9QQ5WjDT4%k2e zjGzu!K>^I54%k5f451EKLIF&n4%k8gjG;DILjla8HrPV}45BtzL;*~qHrPY~jG{JJ zMFGsBHrPc045Kz!MgdHtHrPf1jH5PKM*+;EHrPi245T(#NC8ZwHrPl3jHEVLNde5H zHrPo445c<$N&!rzHrPr5jHNbMO99NKHrPu645l_%OaV-$HrPx7jHWhNO##fN7T8Sz z45t=YP614(7T8V!jHeb@PXWxQ7T8Y#45$`ZPytM+7T8b$jHnh^Q31@T7T8e%45=1a zQUOe<7T8h&jHwn_QvuAW7T8k(45}7bQ~^w?7T8n)jH(t`RRPSZmbON&0ESfyEUN&f zRSRsZ0LE1dtg8U#RTJ#100veQEUW+~RugQj07h05tgHZLRuk;30ESi*EUf^hR@3ZS zi2%k{6RfQO=2jEztpEmB6D+O(CRY<|t^h_?6RfTPW>*vJt^kHt6D+R)rdJbeuK>nZ z6RfWQ=2sK!uK)&E6D+U*CRh_}umDC_6RfZRW>^F4umFZw11zxsrdR`Pu>i(c1FW$C z=2!#lu>b~H11z!tCRqb)vH(U|1FW(DW?2L5vH*rz11z%urdb1QvjE0f1FW+E=2-*m zvj7HK11z)vCRzh*v;an01FWR_=2Fxl#0vjs5P>R`16Fx%>2w*@fV>R`DAFx~24y9F@b>R`PEFyHE6zXdSh>R`bI zFyZQ8!v!$n>R`nMFyrcA#|1Ft>R`zQFy-oC%LOpz>R`R{0YFzM=G z(*-c<>R{CcFzf1I*99=_YGBy~Fzsq!+XXQ0YGB<3Fz;$$-vu!6YGC07F!5?&;{`DC zYGCCBF!O3)=LInIYX5EgDS)Y016wbEu~!3YFMzpM1A8xk!B+!|FM!Ec1Dh{^(N_bj zFM!!s1G_JP;a3C8FM#P+1KTfv@mB-uFM#=1`-${^@c;k&-x}NMfAZgJ=a&BDpVyz3 z`ICRY!Y6N@RQeTp2YMg zuivXDT0eO`9UPl~@cN$kqv8jzcZc@eAH4o&H-G%W`_VN!><8~p;0*n>$%H~=ytAeN7LYTuJ>Q|JZtCr|E>N`JNLsMt1q;3e-xx1ZRdWOhOch!pO0^L zwsSvi@4mL3`>X4fh3(vLEk@JYx&KPhalrjpRolOv`_p7~mv-*gnQ3tB!Qc7$wsie3-}!m>YmU=*e*X2HW&WL?hjSuyzVq|(`ta5^eqNeAuWIAx=c6tK zZTvjlel?|ypRY^IBis0S>vi~D8$W+v{Cv{J&tpg5TW$P&ep&fv8$YjoRvm8R=l7~i zX&XP!Wxs82&S^rLM z@?|T(&t_%cZ{_#f!+Dom`F%Ge>3A!@|JtYQY327}bGT0{zaP7e-q6bL%TphgwDSA2 z&ybm|{65utHKvu{ueN;$wetIR<>T(H{QfQJ=Ge;bW`${nzv1E&Trf&FXCnp9j94ecZz5gE;e>Eqq@1a{6ow zpC87V9ctn8M8T<`7Cv9RH{I64=Z%b0D_i*dG01FQ3!g_mou1Uf=aV<)BU<>pl5@6C z3!h)cS-H3HdFJbR>lQxWZ{oB6zT@!w0$eEym?{CG2;$EGNEH}m=I^mw0UKCijQ zu5ae^oBFIJ&3vBgmOi7I&v#dsjcMld-qMnR&3yjbxVd{Xp9jP09h&)kxFyK6na_)> zHMN`h{P@?==5KtS^t7n_#^+1dt9jq}yg9#f@;5$zX8#lZjnAVmhP?g8=hLi^$KUw8 zI(PcbZ+w1r%{cpw&$FXfANt1U+gCL~-}t;M3)=RL&%YOSSAFC2u)*1R-}ro-=sfuw zpO>p1kNC#t=M}^He&h3W_bB&oe7>GC-{u>iw?j(|zw!C|ocGTrK97r<^-X*}AA6>> ziO=gUZkbJdeqZ<^u8Gg{m1C4me7?^}dD+D0eYdp_n)v)5_3d&K&jT@sPc-p-(8GRj z6VD4}Pkftre$X7fv5DsiS?bazo-gKY_^pZOjT7x-n|S`{dU|jZ&m%5fere+QBCRyXpz)BdQSk>{WLV^bS>9(tV}*~s%zH=p;7 zJTGY&KW*gsY2^LejXY14j6C1S^VQePBaJ+7t@4pK^87WzWM||5&SMYPH1d4bW5U8l zp4TKrQyY1H`+&|3p6Bk`|Jum&-M9a`H1fRnYJR6ip8s+ijT?C$^g652$n&9h|E30> z7mGfYH}L!zyfdeP=Se;Dqz0ZZ#TTIsJa2xU^QM94PkGbB2A)UvUAW%B^J(kQGYvei z7UUdg;Q4jP?!X3~XSF=GHt>8qGU|8qbyUe~w#;qd`PbBZQUlM!_umX};Q9FJvOWzw zFZb4VZ{Yda^^tW0&(lX|8#eHKy|L{_JU+jaFke;=D#TF>)%LSsff&*w+4$JO(^ zu9&2(=lOke!^?V}=TBdMP|x#yzbRMhdETG)?Lp7R64#k1-;PcSkVU(fl%AO8)h=e*&_hMx7DKj_-I)N>x85o1x$`GicWSI>Ec zU$5_VoL|)C*VJ*IQFErKj`NMp6F${(-m$4Ix{mXYs(*s(I1i~?{k)FzkwCk9b)1*% zPrO*i`HAJhKk7J7>F&9^j`Nj}M(;Y#TZ$g9ujBmX(Ap(+oX5O!npwyB%=(Nmb)47S zJ~OC}^P9EPd(?5B^Gx5Vj`N-UVPTF#&D4Y^Rud6cZ}Xf5Ycg&%}k&a2XP zdDU`$wQ%gZTF$e!=q;}0e9JU$dM)Q&6Hbq=<^0QN!N6M1!`3=>ujPE~w-Se1&dU-W znbvZCmhY`y%X!*?5iMUiUsLE*edWCEkHq}1oWIpxO8Lrp+?O?xUpb!(?EC&J=XE#Q z|M|-K-O}jWFjhOtpPxVfmGiypYmR>9ywCkt;Vb8Vqcy$0avs?FaqU;m2dCa%^p*3% z!QRuqa(*a|8~v5@#6s(VUpZgA`K8-e&Kui4IDF;&vHq0lSI#33uGRj^`Q+PS=t{x7 z@`!0w4d<6FpYv-t&(u?-)NsD}>Reuj%7ah|{3bSIxhQ^Z%rlO;ywbUezzJqCW6j_3SF@1$WCQ zR8c>8Rx+%LdV*hJ?<(pG-}2n5s5kV@wXUN6;E`ikMLi-V`)4Kf2}w?UCH0E6xt}Yk zUrf%=s-&Lrr7)qA`o_f4kV@(utG@hON&RC)&BIFSA!!ZQE2)q4YCBU&y=0ump-So} z4hGUn>M5_xwpUVLF}7b_Nxh|8=LMD2Uv&CTt)w1vclgLk>N9$ieyyZl({ouZ-1W(>Q&LFHdIi*>iuYG z1@){I5x-SX-&$HUu7Y}37qy`k)W3oqdR0&la~K4-S`-!Ihb&Rux;h5B8U;`$fr zdDdlTzEIz@Fg^5zdSA&<=@;sMN7iirLOoFX)aozP2j_fP@P&F|z?Z3Cs2_UUjQT=7 zar}ea_}hcDD0BhyX4P>*ae(D_1rQq!}woO)&Hj_Pvim$&Z~mQ&9h zmYr5keeYr|VUX)W0?fUM1IrUNf#>?f@OCx%pET?|DYSX@Q>Zv*R z{mZGZ4k+1NPQ7)r+wbMnU-zt>TTVUJ|JI~(>a){}MwC;p)%NIDPW|@Ey3Xa)bFCiQ zl~do{QDasz53Vxe9Nd`+Zk*sqn=&9czGH1 z?VC?#mr?H?qcO3J`gg*-;bqjr$35y(Mt%IghDRCo@`i=z^MQWe^SMzO_4HYW8fDbi zSFdUMOuc=T_~kS8_nG#2pQ*?92uS`+eZC1UX=tD=Uqt2j-U2uQ6C_aw+{A@Ar6?($C?k(Z7`b zj^I6AO6m6)p=Do6|Hu0SCZ+U)3^UL!r9b4|@s<+$MTS{am(V}*{!(EH{Ujq@Kb6p5 z683jY3H>J1ennIy{3q$bFH7i0SvUEw68ckG(yo@!uX1wr=@R-^eyKlDLO)B~o}d!? zTfEJ;m(cIxa(8tJ{V%D57M9Qtb0TJ13H>p@tr%TGzf7m5fhF|MR3Gb6LO)HEyK@Qs zHIF}7l+bT;dA@!L{WoXp+KcJOId{CSnEsqQJw6xHuk#@)tC;?s!u5&8^z&HghZWP` zGwbjFis|>cI`v60{Xb1Lw~FZpT6*?;G5tZwLyi^GFEl@YS26uV6$gEa=_fkTXJaw_ zMPo9T71M8|yMJ~u{YN={CKl6=6q+-M9Rc|Sx|EcTisv`QK9&IWtqCaY!>!%|6r5Z9~is+yE@3dG%Kh>X8Ulq|` zbx8N`BKob)gj_44|LXOwGez`c)p;H&qCacG4`~toTCak46w$vmeAn6{`nmE(FD|0L z>$1+wBKp0&V#XHH|F!PakRtlQd>8a8qCf1Gvs)4UVio1qMf8vT_Oe3}{bZ?vdJ+9) zG#t`zHps4`kp464^1MR&(X9SUDWpGbz>%mz`qjLb1Q*i3meTu0A^mLgv>p`F-`1RQ zrI3EN4^K}O(*Jhn(1Akw;r{tOsF41+>|xsr>6hzey{3@DQ~b>rhDl-bFR_Li+jEe{L+Gzi)ZM zmje3zgg1Ew^#4WPN-3ZpaMMO41@tr4*NrWpzwuGk zkOKN0|19rSK>y?8Qnv#7A)AVA3h0mAUTjoAzodPMMgjekEv4V`>8I5HQkhSG<&^4z zeEKbw^=bL^Uv6xT$)_K4f`&4m{>%l2uk-2Gyk_|@pZ-ldmmB%?bH?=iGoSv>=fjTV z)9;xuS;(jV(|xgbKK-CiH*d(NKh#@TmQTOvwllNy=^wrGU}8S~q^61y`Sh2*N$ZzS zzv;!AF8TDIzSMWfryte8!z`cv)XSrE^XXSzxBPn^{j1yMwR!ZjzPwhNM}O-;F)NRL z*T%xcJo;a2b;9%LhyCT3cX{;3-ktR{kAB&ufp_!hpPh62QXc)ZN8?W9(O;|4vM-N* z+qWKpdGz1Dn7u8Je%z`(tMlm3-SA>z9{svqN~Y)0zuVPjY##l*o2CxQqrbO)cdtD9 zeS_b)<6u});-RpU-^&6w{q!Uu5CD;-+b=io?QB! z(?9y<(*L~1X-h8s(4JdX=F%U%^8Nf=`lUa1n3hZb^oeDobLpqP_-s%v{nfSFJ#*=| zKDXF4m;UP`&#iOm$Bs2H%B4Sh>1vH!`n5e3-*V{R-rA`uhkouF|H2&lyOp0l<vw!5!U!LB+Cx?FX z)9d|n=s&-evL%Opbe+*a<>5~kpDxIuUp>)zdJg^T15c01p`X1$Ye)|L?Ro*da_D#W zu6E0z|9$Wp+Z_7g=jIsa&>tT?Pb-Ih`HM*{+4Rq=rqyKAPd_%MIGg@@m&uvg^xH3t zPROSJzH&-fHvRZn@o%%~&+k0@X*T`(ap`xn>EHjj{Bkz^{J)l+%%;D;e#e1q`u$DY zgR<%W|KsqEZ1Mo>t=DCf54d%2Nj7oRQ<>zzwqHmLl$|49^JlVk#G1OnU_W0q2I>T zEb`<_XjWW|HJO!6g08_P1un{@4&n@RrU zS#5GAd6d8YjmjjSVk#&y$*Yu2c$G7FSAdzDwF)o!V3#C$U{$}ux zKAGfk=45rwB%f3ApM55Ioyv=5ndEmi1nFgx=UKMwM+W(xsL>4>{gOfcN5>>T zgFH}1b7}_pAdjM$4Dv$d@yZPHLtWngn?ar^@9)PM;Y0>` zq{H6(Gsq`B*cg;SUTMtA9U0`87A;S_NI(f1l=eDMkFWdflbvk*o;pvOg$)6o>o0(1?ZG-cK zbn--@YyWieYdtP>ODE6PHN+{MeA|;6OLV{e+@WyjkWT(>;WUkO@^FH@ z`4joLKF_K@k(b+CQv8Yh+^?OoK9Q$8G%M*7`MUK-BR-M0OAGt(iTquX`pZw`@fJz` z{zN`+yZpu{@_JT^bDzlXO;-Qo6L~(PaeF_J?^|&s;1hYjF-hA#k^g&byY>@#z_+WG zd?Ft>pZJOVV6Q2XPvi;xFAw-czHn|;k5A+c!|*^%{xIrKn@{8sS5z8* zBA@ppi)BOhA4 z#wm@wXnToe8u`(e>pG;7CpDH~mr}{YzB+X(m3(Z!?uSyz z%gzdwr;?wwTH%vQo>tbrDV2Qf;VUas$=ePcu`reV?TNe@spN4F?;W2?KDT?f5vk;L zwbCBM5gpnEEL-mh*hspNZmBwDAE_cf9mr;`6Y-%~r4JaANQTMGH$JE!VW$P0HF zU!FpKc+U5{6!OG9UZ$mxFMhZsE`_{tTG!AN^2ZNL-lmX8{^icI6!OUnRzFA~uiU5e z^%U~UFUtQ+Ah5aMt)5u?``?$b29nwd8cxd$%9Y!PfaEtUbiAPnY{RnDIv+^ z$5#w`n@pa(v&XY!^5wTI9wd`DPu9MkO#b|B^PkD&(dSnkOD3QGuxM{GdG*&>fyw08 z15$S+lV`6_T%Sz7y>tBXWb*E&ar2VNzrT!|mP{VrG;wS)`S>m=!;;C%f6M5XOn!cM zLAPY`^x`dHilJ?H|eK+w^bvNM1i=e8ord`#qKv zek9L7(<|d6`TqXL5HZ1Ng1r)ko$7^iqHPk$C~pu6I5%KcMsY z%O9C1Fly83kIWZvJbm~h^9J6%-Sv_A12!doADKrm*mT=R<`dXT)_!DO!TYUCKQh0- z<;I+k%rlsrJmn+v4F>3q`N+J3V$Y!;nSU_PukT0ZA^h>I>qq7z9IA5q$h?G!J*+=6 zKOuIb@kiz0QYgDS0Co*qippc)){Egp!eoAB>hv)8uMCNm}Yegh7uj7v+ z!HLZ8s5O0^$UKkEmmeoG-=lZuyNO``HyOUTlF0mzccacGG7m)Z@n|CRLC&w^P* zDdz_?CNMw6vb-{Zc`9436(=xX<>uV%1m>;$W1Nz}{FRGQF$v6LS#}^K;eYuoa_m+D^IbeMU3IyE*u>TvbqsNi?IHTr% zi)UU=#ORuM=I8Y7_c`2o_RZQh6(Y^--*$Ph-V(p)3)Gvu>b1= zn_kB=uct@-lX&L$sA})UGtXyK-L-h;``m9h7tg$(hUVk(%>U{B^FTcFfF|k+@yrLB zZt54$yr2;d+v1rYWYuF`JoALohc1t2zRQUJoASx`Amps9+CDRl6dA5 zExtD>o_R%Al)dAbUlf(wC7yXkh3!u9%r`1?w25clQN}2fc;+9yS*sTh_J7^JKh)xx zk2K zd>r$sYGOU(m{&El^Po89R|W0v9mhPYr@39?m~WLm!a0t4S3j=V#4-QMO2agcc~~Cn z^y8S1)gxX#j(J(#2DQdAKg;1(T`cpo3_4cCGGD7kRus#;t=Q_USmtlt`aLCC${~|&RFJ){q)}y3-*7_QT^4i%pbG3vLu#y zWS9HQjb%O=S^#62S9W{(_*mwbd9-@QGSBSpxk0fYKGwJo=o8Dlv)id%W0`;E>hBWE zJhU73cCpMya|$twWnS8~O@^_|Pjj@=ie;YKb=CJ6=Bv5vXpCXr+Fh6G80N3_NGXkB z9@~pUc`?jq8zD)LVP0GGx5OCcw=H@e6~jEY>aD66=DY3h`7VZeZ_d>(VwnG?c={-Y zd2p+I?#3`5&T#m(80N+Or*%FC?EmUb2`6HhC+BwMPz>1r)dd@O$1rd1?y$fZ=Fe?6 z_KIO1-Ke5XG0dm4eY-k_d3DXFm&P!^E^o`c80OiW9^j54s%Yi|jvDnYnt6dvQ(i_hKd{66$I;9a)LC;cn)!kqeXd6{Z?Mb3 z3(?FUoPPOKH1i1eJv$Q3e8T9cz0u4obS{=gGr#bFnr}4o48J>Wi)OyzUdj4s<{frI ze<<@0Lk}#9W*(ya@$6{kBTh-18qK`KZtCNsnV)FeOA^gIMTez>qnWSR?|9#6<}EH( zc8_NM;)N!+Xy!3~?&%QCe8ws3tfHCM7;>v)H1iv0{*)Zvv;%-2-5FOFi~ zW{TI`DCTc!R!)y%9_O^R6Qh{V`Lb|S6!SU-X)58 zpDVY!L^1!219&e=ne%wP4JxhIl&tRIY}kzoIqcTMn#WM1pPr?y2hzjfoh4Uu5~mydQ>70G;8 z&(bB4%zIt&Y+fYuU+>FjMlui9V*2Dr=EL4|8XL*H*yZ&jBAFlS88s-9d9q_}_Kjq| z?Dn7@k<6P7neP$F{Miu$og$e>n`dPk$$Z+sTFfGuS9>|PLnQNSUxn#JGSBwg6SYX@ z+pfIS8o|8Vrh^R;%)fo%R~^AT+)EqEBAAc+_tL@$=H(X6&W>Py?u4mn5zNy~8=n}# zeBBdcq9d5MyK{7C1oL-yj|q-o9`D=nZz7n_>pb;&1oL{I&3+WY{NAlg??o`rcm9SO z5zP19>~|@GdB0B%o{eDsufwI|5zGVr@5!ME<^%5u+Y`aO;DB6d1oMNhw)jRcPx!0V zjtJ%p?-;l#f_cNv3)Vz1fA~kx@(AV;8{AqL!F=NJ(X%6%SNyDDS_Jcpr@BmxV4ktn z%+V3dH#XfpJc4=0!(R@JVE*y>@;(vFLw0lN5y5=q{6!uS%u9|x=M=&G&OGTk zoH7vapC)-rz*&iv_~vIpVJqdr=GD;(_q66Xb1!nU5W0zayM^+3MFfg)=`p*lle% z^R!?6y&|0X+Qt1Bhcj<`s$y<9^S7&}&J1TBcSQE&aOQJoZ5#>7It=XpBI)O2Va#{$8+|a0dGDS7*%QY6_oe4#Va$V16a2%N4}Wr#R~Yl+kD-s3 z`SH<{HiR)xe)90uVa%5|>bpFQdGlsn7lko@ev!-EFtGm%OYCQcF`xdW-IOrq)rZ@S z4`Y6PCkJ%)BG3M%%kVJf+n?$>D2#dcFZ%WiWB$F(h@N3!{}+Z#?i$8?d?dk#F)zP# zvttlnto{Y|k3Va(reE7uNV9)F^~dKmNhD|>toWnTaE zncqU0-~Y|GE|huxpRZSiGT+}ZrYw|s|5uueLYe=+vTI%_`vA5r$_!;cK*;gbQ1%6^ z2uloQf55mOF`?`e*f}I36zuqKKx}U`w7nP{U?-t z1%a`Dhl2f|f6w|}DEkcT*W3&R`#(SD<&{wO9emcg5X%08;fv3NvJWBa+3`^JBZL|p z31weG%bNY6>`w>?*%it@g|TkZQ1&Y<+V2<2zJ>SYJ44yOuwmxbQ1&sb`fo!h`x*Xn zUlYo{hGC~ygtEWER%1yh`y9r4&ktq4!~3#Xq5tc9SUx?J{ST+pCxx;PqHgxMQ1(My zOBxx7=ngJCH9E=FqWhO+-+_-&0)_F)_v^CN`) z81AJlA?(XAIocQk_J7{=ezhU&)5y-M3}L^LfFUQc`+-5 z{TwT&e+qevzK(S5H$vDy(!2YW5cZMu z*0>PDev&=eXF}Ll(*3^^A?z>da^YwQ`%L@;4u-Jb#BnLQlhJo#J4Og$|H;N4K_Toz z>1gE_0``B7fu>go`%)IyZ4F_6ihA+J5ca9Ge_9*DewCT=D?`Bk&uI={7Q+6OZ^}g> zVE^Y#Q_KrtKTAvStPu9Kd>5yOu)k$q*yIrQx#-4@4`IKHN$Thj_PuP+_Y7hGOPA`Q zA?$-0^kZNM`(dt`^bcWQ%rcMOAz=S!`wZ_9!akXjxm`loFY{!FTL}AR5>7aUuzzOK z(@r5^|7Y7LTZgcpW@58>2>WW{olHX5U-NiUhY|eg9*st?uOR0)|JO0lKRbc;T zo&A=pVjqve$Sf86d2)_?Qn9bcAU#>d{+_d45>@Q;2?&T)vES!iT%?M9KMUQ%RP6tm zB~z-{2lQ9^2NnB)mJEEWVqehabFWok|7WE)KUc9&=+@GIRO}au3VoUHUkihV>|^lqxyPh=2qRmHv{?aGTP_7^Sv{hW$@Miv>TRqQwFHv5E%eMeUkj;h#y zv~~I+75k8`C+t(PAF0>u-75Aa*=NX9>`&VGd!UMaN>-Kl;6cBVYk-%EeM`snwyW5` zwBXWa75kX>_S&FgKa+9T8WsDRnwPFrvA=0d%Q6-FoT|?)R}PmmFy!kC`(YXpUky3R>{7y8{eap>@VAA5TRtBS-f4SlKp1#o=PSA&d!bwR^$-cC&Po68;pQfAmj}q+v^aJ&eluGyuVjDRp{{$CVE?D>-?>Z4e!0qEnUZ~T?~H+0WaQL@i&sO=^t`|T?H*DKj~r=7J% z$^N?|l2uCf;rZWNp=3W^QpaUV_T`-oTC8M$p0a#_l6`s$7R^(#UvE*|Y$f~l!bkt6 zWdGjPx6_sEp=2MT?QSzA`w>eAnJC$p=v-^0WPf7hBSR(o6mvG}E5ZIxS>8ie$-c!I z)mlpSFFtyqp=2MUUyz!T{ftk?{SevLIN$8M$o|Gn1uY``9IKyy6WQ;Wcc4*Z-=pW! zdXfE)h68Iw_CZcCtr6J|SzBExvM*9U;fu)r$dk{?M6myp51cC%!TwLKkQIyUn+#r8 zD6)T2eNMi}KFa5#b4B)3e(awuvafPwmrRlUmA^Zri(vmJCs?M5?6-Vuk|MJ2veoFL z$o|XMMu{T(FpE0Ii|oe~EMi6WWgh7iEwVpT$0Jf?pJrX3aFP9*(=zB)eoqAZKk4#=J0kl> ziwbXv>?6JEbW>zMY2>o&BKu0$+_)-&{h#Pnd|70lX?^!gBKu8?y)KCCJDsRFCxZQ- z=wS4x$UfB7OV5bxM|F65N(B2qaiaD~k^QM9OOA`|Q*C^GOk}^RulZ4teXARH9v0cZ znwWf0WFPBagAR!7XKlE;Ph?-~bDg~+*#C)zJ9dlgbKRdOi0pU0JVP$B@6}Bu71{sl zI4DSDAMCLw0V4Zhw|4ax*%zz2<14a1_OP3e$UfPSJ6#i2uI{o$BKvpK zjTVaR<8=_{i|pr3^PVTNuUGSzxgz^}@0QFK+2{N2<}4BH|M+n$eiPaEJI-aM$o}6q z#nbWohK#@Y_cW3Hz(00Q71=#ylJV9jN@V(vRMX>+l zQ2Z{kk9bDEu_F74XB&?Z!TyhntsEt?zxZw3NRfTU4$mYa`;D8{EX2J_t}`zi~qy2a4=l?r%3hWdHIl zn_ortF(0t)FS4IG-@c#7zUHT{eMR;+H+JtMvd{V1fZih5|FMOmdx`9OK0K?Z2=;&M zz16>nVE@Ms3FslRAA0o3?jrl5m49^;*&qEntgFaAX_w+IBKxH^w7ZDxn_k$pv&jDG zF4H|k_EB&2br;!B?S9iuWMB21cvlhZ|Jb&67mL zQXNJ1VfQd~6xok`afXA)zHI49dy)OwX~~^L_G#a@?If~ayZU!Kk$u~b9@&cQ-!5pe z5!uImY?6)0e(ooitwr{APxxvjvcG%&1S^q!-Z?icMX>*4GQV4h?E9X+*g|Cg_mKDI zBKyEEJDH2@2lw7@CW8GR9a3c~vOoOD0#lKF;t^pcBKyUq158BrjX${GQDp!4Wc!XH z`^Z>#r5JoJ>I$o_L@J42Cu z==FCDME0YP=w~3ZFa4)dUu1v!;5qst`_#+I^hEZncig2XvTyx~t)9sK_0U(kBKz29 z&CwOv&pxkFM`T}n@&z4{{q5nNIwIKrQGGvai(vmpS)A4u+4sIxqAjxjT~ebZvJd{y zO)ZiA@Dt~0iT~@1H_{T>AKyDdQ)Hj~yuF$t`{f%(X^QNdH_+4+**||iTtj3Z{gq=H zBKzrW=W2-Tt2c7i5ZPbvU!^Xx&wj}Vb&>t{uTQ9p?7Kg_T3rPDKQeikx(N1vfO!N6-kZzs`-=_4=O?13yHL=>5K6gxB-d5eF0WJ@<~Z@_hBs z)$^7~Z_k9S!#q`C6Fk)|=XjbgS>Y*M+Uyyd;O{BQ_IRE-e#q1H(s9pzH_mz2ePYgRq?>^}C5=Ol+ba{d({sk@d{3YL zrJnC%Dm=d|s`ZS?Z}RN2^t)&AXEn))E1Hr$Q*N^~vv{0jP3{DVS<)m)^Sdb$jqB4S z&Ve%|Bc}Z(nPf9t(l=|4q~y?pt3;*ik=8^K5^~1+xIj)rbIzhF72@*dj<0_b5oxb(mBV zrI1P<4V6h^AIc~@8|2_>*4F->*MR>>*ed_>*xF6 z`{DcI`{VoM`{n!Q`{#Aw_26~k_2G5m_2PBo_2YHq_2hNs_2qTu_2zZw_2+%y{osA! z{o#G${o;M&{o{S){p5Y+{pEe;{pNk={pUL1df>X?`rta@df~d^`r$g_dg8j``reqIR^YxXaQ_up2MVkQ1=fWE>qCKcqQH7lVBILN zeiT?o3alpu)|CS5OM!K!zKX;2MX*51@?sk`$K_!qQHJpVBaXPe-zk93hXBZ_LTzr zOM!i+z_-Lmr2_j?fqkmLepO)KDzN_**vAU&X9f1P0{dHmeXhWM zS784uu>b$}pZwqa=lu8lbNuuF`+NBN{5kx2{JH%3{5|}A{Js4Bd>wo}d|iBfe4Tu~ zeBFHgd>?#2d|!Nje4l*3eBXTkybin`ye_;xyiUAcyl%XHypFt{yso^yyw1GdyzadI zybrt|yf3^zyidGeyl=dJypOz}ysx~!ywAMfyzjjKTnAhaTo+s)Tqj&FTsK@lTt{3_ zTvuFQTxVQwTz6c5T!&nbT$fy*T&G;GT(?}mT*q9`T-RLRT<2WxT=!i6+y~qb+!x#* z+$Y>G+&A1m+(+C`+*jOR+-KZx+;`l6+=twc+?U*++^5{H+_&7n+{fI{+}GUS+~?fy z*#Gab|99aDK;2#Qwbn$P4BbuoZ3f3W*c(6WIMg)KY_3J2w`dw=hy&l^ceidkouwXhrbzNE%6>1KdSSX zps{h|942g>_;OO) zUb&+7_qvretIAjBu1Q?`Vcq@p$2M%;IAxRj=9bOTTh4D?zRhiW(e`UQ=I+$ya#mhe}i(LA0$<@Vs7Oh@5W`X1Urn%8`F3;XD z>(}4fW{A^wPa8S4ZSu=W8z(wUh#MC)w)2?yQQjl1C2vN|A6`H7k0Bm|-wvEUAg}+{ ze&72X>}}fX;xA4;?sV(Y^+D&Z9{1hcU9UUaIh}FnV87R{#b&E@q2*kQNVB1)4?Ef$ zAM4O&ut`5dccRW~EqBe+>S}6Re`J53-1erWOY@&i+Kt}z#kF(4hF1@+dRXE3<#d_u zXIV)@(U!u}{NMAka~5W&XD-Od__QRgAZ1;0O;SLjR>J8xm)Pgg zDi@C_`UPjc-~X=v+oCt;{+;?-`<3`Ycs}x(_S4uW=O3?mH1MIp--Qo8+`n>9es|TK zskaB;>UPuqhQ;-c*Nm^4Ua`LHda2LFF&7q|_da*}&sS%&&*+{RczVOBn<-EX@8_P(L}()Rl8wci`Q$9GTn zJ%zh(>|V9I`|hS)k-M(#3fQ%9m*=i7yR3E@?9$k!hW|IffA4~Swh;gB8vabvuI~8r zH+C29?vB47zQ-OvD{b%4eYf|S;^(*S_dU>bAn2g>p|gj&91cFb=t$d<8%HM}Yd-ey zkCn$APUM`pd2++4fv0uPWS@C;_Vl0L=N6tHbD_^g*GtxyO|KYV?Rd@Ny8VrAHwWLE zdVAF!`Q0n`KHM*SVDR_Ahie|4e;oTn`{~GM!gKM3_N%F{&;48UrvKah?=s)_3qGbO z7bmLz3NZ@v3eSodAN4%iCH8cjRzg5xP13sLf|Mm`8J`wpq-QS7&d&KguQY#4VMCFu zMECRQGRH3uD+X7ESI_-gTiBY@O`4Uw00>ck-D(`?Y!al z`n?(PW|FnUq0VdM8prri1C$Ozdy@a?*v(ZIc`FBvV6I z?w)qHOfh}hnzk8dWBdQM)ojD8uiY=to?;L^=i{BmxvkX>^XKG@UT|Uc>V=mA_AHuX zdUbKW^UEdDs}W0&NIxz6<3-W(K7%V)NYrY7f23Zw@?^i7RhwDrVeN;G zAJ*-@c5nS=_hTFGT-dTPplFRRtamiXf3H$H*jQD4i@8L-qzFE^Z`yKwT)z4zzKL4J7 z=?6S>I}-4?T03yDwk*(XRZZYE&80yn3&Vn{+qy|}ryQ0(k1vu|?izwa;St%1wP~_1 zXB^~bikHj3&%G)SFG-b$p3)bZ<_{K53|uMH_c$oL9C%+iH&-PbKbS6vG3CM@mnLD+ zp>}~eaQsjHZ~k-sd;U58dHy~Aef}K&JpNq%eEuH(KK@?*e!dRA9=?q}|6?r-jM?sx8c z?*IJ4Ek8!3W_`b1I;m}6=Qk}Y?{sedciW#$ZRfQbZ~fw3Z$F~AHZ^_D*S;OYt54Mo zs+w{5?}~R74qse5pDqiXp!+#s<|6f|r}nq^FW%J}~y>OA0UzQ6ykYP3eJmX=tRnpLZ|+>cR3%zo_|LWznI z#K^ig%ZL?%P(r9pYmXxLZB(roMU_Ssq19GP6*Wq~=Xt!Z{vVJ2{_Qu(y`Rtf{XXZs z&g*^7dF2{%cFFxezFG45gwtCaa@X5EweBGu< z!9&R{*BkTxyB57Qf9Hu`+wKTS z$+f*exqVxkq{VFMU83pct)J%F6j~?qi#fl~|Gev34R2?x z4q3El)!<3dD>wWRyrSHXZ9hv0Zm@h@eC1_h+WDoQK3r_+{(oOv(&bsfv{5GtFaCa9 ziAB|Oz5VHx7>Q1InlEq<=$SePlR%GPlv)vv{>Ub%9Qs*L%6IVWtOZ;JR;l$v7mM4rV-6)}GuJiG4ZyOii zp_X6#>+Y}P_N9l%g)OWSS3LAu?C?_QvANa-$2KZiHMYr!2cCRu4tv6mrg;jUo8W18 zw1?-Dbpf8y6DoO{zF*uEbNN-zs__y71qbr~^WXgM{G8w8_xU^ip3mX)_*_1p@8SFS zUcR5_;CXm1o{#6`d3kQ0pZDN>crV_M_tf{5_vZas2iAjiVSQL9){Avx{a8oVlXYc% zS!dRpb!YwA2lj(~VSm^s_KSUE|JX*=P2feP{nU2b>4a1?Piv!g=A`aDF&P zoF~o|=Zka3dE?x1{y2x6N6sbZlXJ>><=k?9Imeu5&Nb(obIy6^+;jf11MC62z&@}O z>;=2Qey}6#3A@6+ururpyTkslL+lZ|#6Gc8>=nDkez9Zh8N0^5v2*MlyT|_J2nZj< zEKs*Iwb0SV@I%SM5&U$|?d&)@zX=@CCgBaLTy;BNwt3QIf$&A|3YReJpxeoNrA7eU zQ4Qf2-dyZXXM;FC7Uj}>|0Ppmka2OR@#5m&`{1MVEqqMXa){9N!^vTr?Sj*T2OD#5ptCc_FE02!xUs@u#O_PTsQj zT=0HyXqDoFoa*V1TyTK!YTgHZoh>E)b-@S1wH+SN$JyLGr*ebvZ=JsCFFSI^n|a~^4V~yd>7xzcf+sp zEIbp>2ItDN^2|ItJS^|RJMnJ3Bk#&P^X~AqtOaYr+9>xfYsH$ecJR8aC2Pvs!u7J& ztT}7X9K9s--eIF*WvT< zeR^LYz7U^?Z^TF9EAg55PJAf76rYN3#mC}n@wxb3d@#NkpNwzDN8_vU+4ydJIKCX8 zj&H}uGuD~K7y4q^zggqT8XA;u7Eh&jX_Vi2*2m_%$MMiHxs zS;Q`47_p3)Mr?H;h zi;2m^W@0q4nwU-OCWaHsiRr|4Vmz^)m{05n1IT~x;lJhQd-=Ki{$74x{(diiFQ2!U z&y&y3;Pd7CGWb6E{tUifo+pFnk>|_c`Q&*scwTw_44z-!CxiEam*oBAeKUApxJuq% z)+2-UkoC!6ePq2dST8tD)=$>c%X-TCdRbptZ!hZ&_sROpet6jr*&i?aBm3oLzu-vO zKiN+&`w4H#{>pxP*>AX1_Fv9}m-7I>%K4D<;^n-+xpIEwJb5`!@UWaOId5Lh8{91C zPtK#4^9Wzd`IPhO<-Ee-a(?AJdpXbWx}0x`{a((yoPRIpU+lq)J;48BA7U?F>_zOy zi~Wc_d9f#WV(d%o&5OOk9bVioJTVS2$+uSM1q~J&S#Nv2U?=FZK=> zjs1&1@Zt~Pr|}QsFTD5*IBWce_!BSw1RfjzBL2pUzk%Dv|A;^G;*a3F@lWEfy!b0P zaQv6}GcW!OUL5}>{?3cP6aVMM|A{~J;t%1^@sHv!z4%Kwb^NFJQ!oA$o*n-x{?_1c z;okAT;*Smf7(Sl6Lh;uIe+@^E{}z94@aORM_;>O527eEikN=l=V2B6s`@{!{7lwEN z=TH2Qcw&er+yf9_B;FX}4R-^?ABjhXc*K1H@k!#9AzpEZK>U)}Z-{5yD-ho#-WlQ@ zcMZfpiHC-GDDlw{A0=KI;w5(y#7~K*hIq<71@Tqlts&lWcR~D>cx;Hr+-DGMNrLj0G1H(&tnN5BB`y9Nxvoe3B~KFfdsxJLm4$afhq z0Cy{30C^Sz29RgtE```{zyRFAfC1!P3>ZM(jXM@%zX1bqR|5u+wJ=}+?r*>VvQ`GX z#GMWpK-SWL0l4P@1ISt%FaUQyU;x<*0|t=2F<=1MD+31LjtC4OduhM`+#7)bWUmbv zfV(6xfSd&b2H<`P3?OI4fC0F30t3idGKvA@9tsQ~XU%{CxSIk4$XPUC0Pd^60CH9h z7(mW0_d>*e0|ww;3k)D<-GBk)>>DtE*n$BAaQ_7c5L+=|0Pe)V0Afo948T1Z7(i^z zfC0EW0|SUH8ZZF&XA7(jfP0RwO^2nG;e zXTSj56@mf87aH;*?hiFTYCq0^0k~5H1Bfp*U;yqJ!2sfG4H!UtuK@#yFE(HR?jykf z;;Ri9fICVsfcSC)2H@Tj3?RPVfC0q!8!&*x0s{u%eiIBJvBH1>Bz71ufW#652H+kP z3?Q+_fC0E01p`PdGGGAiOThpVs|*-GVwV8}NGvm80Pa=6021pA7=XK4Fo48D0|wy! zRrBK-ZUYA3P8JLxvDAP8xTggJNUSwr0ExW@3?Q-CfB_^n8!&*xY6Aw~ju#9dvD|zMNUS$t0Eztu1YrMrkNr8ZpWi3;^Y_GlK5wu6d}2S}N9^bOiTykev7hH7_Vc{N zex9G$&-)Pjc|T%5?@R3G{fYgo2eF^^A@;Lg#D3N%W>pY{`AKlV!O$9{?Z*fX&o`zH2d@5FxWpV*H-Aok-Qi2e8rVn6v0v}*t-mMs?i&Z`-w-yeytg>@ru~5bp$q^5&N~az{Wdb zzt$Vrcu4FgJ`($hm&AUpOR({j*srw;Hr^8ZwSK|IV`9J7G}w4e>?eK``-$hoeyx45 z@m^~ozyKBx=+F2aix>27`3#FE^t1U6i#PPUc?OF|^x1eui&ym7c?XMU^xb$zi+A+h zSp$oQbZuB8ie=9oSiGobhcjgHq}F>-i(>Jno;}W>#iPW2ty!^nRnIPG*y33|+njNWclGRJ0~Qaf zZD1o7FRSffLl#e~ZDC^;Z>#NLgBFjgZDOMqudD51!xqo0ZDZpW@2lVKG^1C>YMS=HeXZUjSsi^oceZryv_I2_Y(tbKB%#Q7-928 zjUB`gn@?(NA;#EzQ)3S?$mXLOn}|_1U)9(}472&H#x`P{&385S5d&>Ltg(?8Y4c@` zoy1U^Pit%?#@c*aV=pn-=HtYE@^g*V#B7_tYb+k#d=@>%l{}A1Or%pNUCQ16Y0xdr`~` zcE*0d(qI6~uPN3B16ck|u{apO@^gyS!2p)OQ!Eb#u>784eK3IK|1=i>16Y1ga|JK} zxdZ-#TmlSW`9;k&zyOwi#2;x+V);qURloq2ztmg?3}E?9&2_*4mjBdT2n=BPQO%XW z0G2=1TnY?e`BlxezyOwi)m#h=VENhSxtd@A%in4)2L`bGuI74R0L%YsE(iv&{IKSV zU;xV>Yc2@}u>7*-nqUCSKWi=u2C)3J=Bi)-%U^3Q3kI88_+F$_7ziTcI2C)3R=IUSo%in7*4+gOOzUKO10CIogKU@G90B!(| z0ImQG0Cxa>fJ*=az%9Trz%_sY;2z*0;3B{Pa1(G8a1~$xxC=N8xC}4=+y?jtt^*7J z_W=h27Xk)=8-XK%D**$*oxq{MrGNq8R^V9RTEGBsFW@h@7%%|b4EPML1`Ggq1BU~b z0|tQG0pG#(fC1osz<+Q-U;wxwI3lU9Fo0HQf>)+3D*P$fO`Ue!bO1r;HJO; za8+OcxGV50ToxDrZVP-1*98WE`vU*Mg@FO!#=ysLWncifGw?H98W;d>4SWsP1_pq8 z1AoKCfdSy=z~^vvU;wdQ2mB6~2L^!K1K-2-fdSzD!2fW8U;wy5@&mX+FaX>k`2$=c z7yxdO`~t2K3;_2?{s9*W27sF+KY^Esde}YQ|1Hi44U%|D40pMQAzu;oQ0C2P9XK=M(0JvN7H@I9d0NgJ59b7LM zKw`f`{s$Kf27ntTKZGj=1Hc`VKf)!00pOO&FX5WO0C3ObpK#G&0Jv%LQ@Cm{0NgeC ztHd$~3;?%Hehb$P27vn}|Ah+&1Hg@Ie*FBtT)A`dXSj4Q0NgtHwZvKn3;_2|{tXuo z29VgS96ek;`8wP^7(imbLq0FDT{(V<{mS{H1p2T0XpX1uIWIkS_s;pi?ft4|Y#0(B9p-U;}rl z*UG!IUwhTPzR;bR(S^T_X;@@;%u7YnVvZDb$IL7i6w~!}C#KXJrDLwW@i=--@$=Ec zOKgg+^JY@?!#9JYGu~<#9apkYbgNR?QThFLMxFAT8kJJIS5&t$RifT1`!MoS*+Y>_ z%gu=#P+ls_-mVyV7~&rtQTd(b5jWq-9kHh3k%>bpB~7eYIdI~Q%CAoR ztjggD1F9xWC|j-RgiF;Pk6-Zaw((u7hmJ4uUWM_Q?_C@>xyH*gPutKRl8yXysw8CgH?82<(vM_*{rb@cRxkHeZa zS`v1*QM0g>jjxUB)+ByZ-hc|Db_MJo8R7~WS;BcT;*c|c#F(ZvN0e`NZ1~A$!NVh( zKMH-P#jMcNE&M|xKG-$Pzh&UC6D==&68_=vPyAXv9eS|U^r1srzcsW_n^hs(+SCr| z5tuRLN#KV=mb5)J*lE{&@YQxdd>q?;;K$`V+#F;&gbwQ0@%F$c9m58ucDfr}=cBOT zlOO##VCerw4#?U0R{uqvL;Bb0k{xucOTVE0UBByhziX#{N!QyMFz<_LEP` z4yw~7L_Ymi|D2si%D4SF;G}$WosaGYr*;aHr@1|_U&l~+x|@T_cNi#7`@_dq<;k6P zrv@)+`=Pu|#*iL?wdL(rg%oP@mb~qBdF!V`{aOu|Rk-xY30V>Umb->UeBdvuG)q?N zQD{W-U|GFm!^=0TDXTeOR`tn<5>Ak;^8S&#WX1Ca#LMbm8?~}=Gue$LvMZ0nrZ?;= zyR>n%e}lZTYeBMm+sEXpmtS@>NOpD0*vqoR73*}B-CilXelPrqoPcIEXUb`~I4)C8 zMv?bI<&C zw%AaWd{wOZ7qRL)V%-nK${&lhKNYKgZvFNC{ntJG z*;Dt5r;puP|2%LP{pXIm&68i;p2t_+yB=L|-+p+~UGd=oci+FayXQSv?asWP>dtk4 zvb)K>aQE21g54YLws&9uvw_?1&+_grcV2bRxP2!^s*qxy{k}V<{_klqVYl2d>wXK0 zx&EsYQ~KA^G2MT896jge`RL4_H$~_DIVrmNPr=dAHyTFox?V^so3f*7X77v&y*4#! z?bTjUKV7L3RpH9R$o@Y{UFqdHk(Ykx8(H#)ijh4p-Huq0wIkxY@1rA1eBV5x`^DT5 z3oaa)c=5ZWi6y@aoY?35s}q-edw9Z?a|shFoNGE^$l1r^*PYom{*P}$$JhC$!uScN zFOKt`nmI1lsb=E>Pu>fkePU(!#muhZ#JsAYY$!<_3%Las8$Cmj7r_Vf8@=5K_eUOdop6W znLpyPx8{gi-ebcPGlGYIzxPpSjlHu%6ZiOsX6@cJtoH7}VM$+J`XqbT@K2iTdOCFe z&gnz%?09Qv+a0SyR&TEzl52a$kOA919I|igsljEob{`zG<%f?iZyxw@)6F*rE!z}2 zDA%Uj14A~34b1%FZg8zH!h+|2{^x+F8%7QowBc6&%=IDt>#olZTDq=ZP`-8F^$TCy zso%9Vhx>M1UsXNb3NLA*1X65 z<(s-USYEpO#$`#}Dlfa=by<49v73$M1TxzK6%<$@(`n=g10cp|k&V9(TT zZGM_xsLh!9LtE#Zf3Ve@d48=b%nSc;``i;PTg~-vnUxap!KjqeE%Kzi(;{t7MDx0H zPBuF=yL_{uv&S^eHT#g0o?OClC5N~!&Ds?ZH7jpG=~>;HcxSF`JYeSCM!9D;ZM1I2 z^oE^gTxjrcx_^W8=_Bh0PTyVc-n3lx(xo_n#zPuCp$wVx3+|BWmYQ+Fr{$ z^-0aJsm*FuoI1J2r74;3rA#UEUfU^MtLL7w;9WEMQnkp*WvexqJfP}>NuO2OKIul~ z@JSUb*Pk?`(&NN66*CfVz7v;N`JFb2L;MRTuBvb`;l|s`6DqttJYhijMhQ#H`D>E)WrF84~Q+|H&`Tg$1wJP;>TwKYtxQw^L;~u`*F|N*=RpN%1$Q`$) z__f$;Z|sXL^+tMZ*VjFYR#v)rB)Pha(9{Zq(O^q=CMHc!fUJdZ1Rc0H=) zx&1J}Q}JP-r|;iAJo6recrx!#@Z`Fmz*mb|{i@pBqwb;_X=8o(BOO?1eH#^2<{u~~c_vf^@ z=0ANM7k%SS+^*|>@%OS@$Jfjr7aw|UW&GN!=i`66k~g8kl|~8ue;l5$Ov;o$zPU7|&NmgOPBVPXbb$@#D&3(CMH`+IJ_H=V<_GNF~IkmiLa}qQ1qj)TNp0{nG2MUzWafUFBu@)@@uCzP7>gYisr|@3^MzXBn%{e^zaE@QOvNZm%e? zDtcw~$^!Cli&h1%s3t$jSl#xsj`Ew=)-+fizILPhb>(GC*DaGz^GnZMpDLeTZ0XYt z$?|QlEvY5nocTq;w2+N6XM%LknvTNzG zdx6uR9K9#InJ&B9ep-3i;ftB;WVd_CuIEq6B`3gpDojp8#i@1VWc=|>ikyBi0ivR@73gsj662q1Y~W9*C7)7Hc~!R<}j0FHNj4Nvv^#SY?PUvD#W7ppEL*8Qqjd2X@xoMQDkJoJEY|5rTtU-y(kM|02*QdW8c zz8U@4{awZ0Iq3~C(l0Q6u4v9z{QYJ6MCc(Hc38CBbGUQQke-n!=__y*IO+c2v%-1l zAEDP^%fRjKPjf7Pgp%9>e>{uFv4o^^L(5`Qf9#xK&V@`3b6tX}XqI(M-(#b-+23Oy5lKiw34b8wwE z9qD1AkK#~LaP-~d8E?_g@{aUYyxF`^^zGWMN^O?j7WysxEA5QhI{lR257OsC4@Sp; zUQuO^bt^;93w;?ir#y@-dFfKwSQ}dhjja07Fbi&9Em#R&X{u+8oek`$V{F6pqtJ7;k ze@XSA3ggR!WWF~=`flhsS^3(`as3ZBtJy?)aOgwH_wK#$zJc3o(T_uKO52RC;Rmi& ztkY6@bLdxzKeA1(MtIB3j=OGehGe}`U| zRk=5gPI-2rL4x%1(Erj}vZimUH*G{;4?QutUTGFqrOe94^!U&x^K3%=sBib@4Ol4s zJ}aenCNX9I$anLHxHe1g&ra#5DH`--MCz?W&SL2UqQ|C9cFhr=_9)+so}fX}ck{SX z@bJ^kBAP#u{vdjB{OZmMz4hto7W4|ypL4qCu3>w-`L~=PeM9u@3_5!0lS(1sAJRkg zll1Wf4tP5By#ohZ(N8o;dV9)czcuua?uFXWTSULly6&|@()@Y^?v*~HROtcw?(m00 zX1%AU#U-84Z0L7ChqI$&XypuSDFi>@9oDUbE-yJ!gQkz?tA|a7H*QoEgpz zXNa@Jnc{45#yD%7InEwukh92{zsMcJ~n_YU=!E| zHiE5SGuRF`ge_rH*cLX1tzmQ69yW+AVw2b=Hj1rcv)C>+j4fl+*futftz+}pK0W|n zfKR|T;3M!A_zZjpJ_KKaPr1|pUxrV^x8dXP zb@)7dA3hLYh)={f;v?~u_)L5!J``VyPsO+5WAU~4TzoG+7+;J}#y8`m@zwZjd^bKE zUye`5x8vjS_4s^zKQVw~c#0+8wF@#t`Od+-qV~91x9AXbKh*(5SA~q4D zh*iWaViz%tSVl}Ewh`lqb;LYkA2EkJiPgkxVmC3ISWZkQwiDxt^~8K)KNw)boqGTB-}D9X^U4=jJmvT472@yT zx>)odK5x175ApfO|MfiP`{Jdii0|Li=k`OMXMpq>@q8cu+xKstcZc*I@%%0R&b-h2 zJeGbW-tSoFCii&XWzwU>`w#cuaF_LZo>>2m{$aP+j}FoY#r{N;yZ$TtMQ;@Q_vBXhU)ay`(l5pSmROkiGy8o|dZ^g{ zg6}u~iSs~T73ZVyiCxz@FY|yHB%O3ao*|i;`|5hF7Z9~K;IYkQ6PB1 z1?=TJ=>@}nw$Cj29ri?j820t7!;){Yx7Vd-4EsyoT;Uw{*i!n)u+LnF)}6s#=`F*4 zucp@d276AEelzTQX#?*m?0t*$pke>Zw+EiYA2g7@H0@0;eK8Y%F+qCO@E@C^haShD z(7%R%sdVGXQTz=(ZTO$v1Co#6kLYv5KZU+j=`jB4g!I1Qzur4z4&l#QOFta`?YpbJ zzQW(lk{&tyUscz`1NcMw=J1ba@1^d?U(!p5{|qVCXdnLcn)KJ!2rvjZCnNh zpr;ZH(C+TCbTGhZ>9Yg_)JjQR3I?F}5)3f+x8x;Y0Qxb(0P}OtOat$9mL5$oK%L)a zE(Qb8w+RMlx+-N67~rDxa)JSdH(mTG7~oy$?*s#UaB$5+FaSNDV1UXEzFYtXpbr!b z&~?p;R4_n{^oD`~e)RikJ{W+0Q82*vB{}DV0eVXhDHvc;y$bWd0Q8lD0c!l-YAzUH zsq~tH0j?h#l>!E!{}c?6`$F0rFu-rplL`jd;dg2_7=S)iFu?EWxn_d_=v@T^M1;DM z!2tBLf&pHd95o9J&`5e*!2nPG_Ra(YRF}S2Fu+b>8NdMa!h!*MKJGLF3_yP@7~tZ< z^yy##dS<}@xi{RK1_q#y77P$ozx^~Yz;5ZS1p{nrzAgz2P*eJC!2tKq=1&3x(1QyG z==EpVR4@Sj$Y6l8>6fN}0sN&m84OVFX4@%X0Qz^q0N-Vr$zT9_dcgqwx-^&!2B6Ou z4Dd(%_DNuX4$}Jz2AI>o{vnixdYHigujK3)2L_<884S>4NbWc=0KLv&fS1j4H}eZT;$ z7Z`x`0|T(0V1S0QzKQ{4y}^~TQ z^8g0me1HKsFJJ)94;X;+1P0)IfdM#gU;xe^7=ZH#2H<>x0XVN<0M0KMfb$Fn;CzDt zIPYKp&OaCcdjJDqA7B9N1q^`wfB~>4FaY)i2Eg9H0N5WG0DA-jV4q+B>=g`v{el6o zXD|Tv4FX(){+<6# z=OM`N@VopCf6Hg^S$rm+&3Eu!d?(+{Gw>`t6VJvo@~k{F&(1sWF1!=(rtc{4$~*J! ztO0Amny@yk5o^Vov39H>Yss3jwyZI0&6>0J>;Zehp0GFU5qrg+v3Kktd&!=%x9l-{ z&7QOOoB_@PXM(fA8R4vOW;i>XAbw5PS(f1>b^?!Pnq(@ICk-d=Wkg z--M6CSK+hpUHCA389oi)hL6M7;q&l)_&|IiJ`vxDkHlBvGx44HP<$yq72k@F#n<9< z@xAz9d@(*5-;9sOSL3ts-S}{PIX)fVj*rLJlpQC{En@wq&81K!`6A~XY(Dl?o_{s}hKe3-29Gt6ch{Oe zY64jUY71EdY7|)mY8`n$Y9?6&YA;y>dMH=}`I%vT=xJaL=uKb^=rLdo=oMgnsrhFO z)PYph6AkSvlA8O)R19^7C{>i%-)__`b)_|IE)K(KlIsnM!R47?7V~BPklGu(e5|z?qLmB3)aM*4_zzPfVJcASxeS{ zwdM0!Yu13Z=lj_U)_}d?`RsYsz2o`WOV)tB<^9-e*1(>BJqxUX{LEo}I4i7y{H??K zS$i__*$(T=Sz`_4yB*e_v&b6AvpMV!XO%UOXLr~?&N6Gj*=B#Oy=TAxQsYM*AGLba z<56=*T^+S^)W=Z+N1YqBY}Bh!lSbVcwPn2(-05;}%iXN+ z{?&Jn>bnp1-D~>pCw=#fzWYMoy`S&?&UX*zyHE4oi}~)ieD_qo`zGJL5!?^|z~S(} z`R-$U_bR^o5#K$B@4mu!@8G*XfCJ!}e0;u-m-q4OKAzmicl&s2d=G2j*G8u;=JU*6!u|2`b=!{a_&?Zd}Doa@7@KHTZUk3Jme!*f1d=EGM$ zoaDnhKHMU&@9_TCkGZTr#HZm`^=JGJK92vk@q!uh>U;6s_V4*`uP>h1-{)r@e#d^^ z3x8|B&x`-V$Kl8DRrn)(4t@pS!C&J8uybtLXRkiH^VyHj4tN%R$9FD$=gW6ah1sjz&TCV;(q~ScdBEmmx6>ef1pVjKp9j1$LF&=7;^|ALEC2>r@lSl=sz*e_Yb$z_fFk=z`5^YoQ6>c zUf|E6n_`@uPfyY(Pn~?gv`H~e{pc+E=c%6$XwWOh`SkJ6^wm>WA27OFjI%HN-ivv0 z4IW23Eyw5389emiPyagF8L=e~{rS}AyGA5OJAt+BzUy-LXy=%JF>n%b()EL1 zv~#8RTP|DY?+X1f%88s^mi~Y0|6NH-qnzo7-eE2PeF3gUeWRRQ534aRfPMj2#G6sh zxyrR&wvWKo{+meWR`&+X7ofkuwPkXo<4SZfcYwYF*ZRhh&X=1$0BaDhUG;yDa5{b; z$eaTD6kI(QM>v1J^bzw5=wEOZZWH0ms??pi2J|(!`u#Q0DcQEK%l13CS}dCA#D@-K z4g!4;u6<1>I=iP0Wj+G^5w7#u6Pzt;Mlv^nz6sZ)gb7ZsgW+HtaD(fcwvlSQIGM?sGJGRWuPy^)%*51=lgt#@$WatoOsLH~&B;>j`2#)rT-NgJ0`d?h7HjZ>wUfRlB4EkbRo63!J4rcCf*?t+Im~Y=-+WofAWd*Mb+cX^`NiEb+Okc&ae4T(yK?mkL&u*p-$D`PSdkTACT*dqC=e_ zN6xxze~_!;un=eAXXlw4Lf?>U^8O*tmr)nNu;5D9!Z(IE`#WEvr;k1(SJ;rj&f3a9 zGJk~rBUj;_A3L8sxyoD;`jT7|bA9YQJAR#cCG;z~Hgp{1^!@Z_=9tjOZ{4r_p0H;O9UFM|FC*?Y|s=rg$bD#Ms z^iR2dxgO*kY5I`4D)d#kvdRTHe?NQ7ycPPbT&sHZbN1|h`eJTi`#F7`JdK{uW}}Dj zo5OvaG4ozxZVP=|&ihY#J4lp9?qP$&u7KabLhU*-RZFORh=Qn9GTWHcXxLF`QQA(XO+4+N1H#NImg_Y z6@guy*f|9qi}#(z!@4+GSN@wzcz9}O=iBPfXV+ji=CXH0?%jQF$ZVO?T*gQ&d+D#(Zg6GS4U^*!s5)$p>NKaTD*f(^zwi644+nP z?-VNke8wJgb|%zq=cELeWd08Qch2KxZJmY7OX*BL=JHH#7wD9|`ro|6@?G0FZ-x^R2G3_J(u3*#yq*)$-+=-231g{fB?&f8%HLX7aoIjqTsm&*C%rYbvkxyc_SxyYkL9FV(eRO;{UxJ6S8%%=Vw^TC%3nqZ_N(e%uqW&dd&FL` zXY3t4pzI}k%HGlo%3ibQHb2(0z?tA|&>PBG;mp|nSv^afDb5zXqMS9(ob9*Ov&fm` zY|=Z*S>?>y{#-rFoN3NBy`-FV&b-aj)fTV`Yy%s?R7ifZ6h{o`-|0xg-l$I)0wOe8iE zBZ-y7Oxypiv6Pr<`{Fg$5_5^Y#9(4EF`3v*j3!nSvu%I9#&Tjhv7H!CtS9E%JVmhp zm;h`5MgS{-8EpT)VhJz>*aD0J)&O(Zet*RxU=pwi7zL~XW&yi^VZbtA8n6u*2do3; zvAmXIAutix2#f?)0yEk91B#`76X&nIR=W=z-)HDfnqr@9oPyY!1`;Y^X3y~9%8<8WCE0HsiJCQ??OOaENThZ%G zu0_se=XGcjz_LX&S&{o%>~H`$qmU7$rZ^N?fekU zCCMqtEtxAyu1U^m=Z$DCN=`~{syV9Us^qM8K8fbCi8 zT$!Ai+?gDjT$-HP&PCB&o1B~6n;e{6oSfXwQPEtToSodA9G+aBoSxjCUTkuGa(=i0 zH~{(YJ^Z))d=EdD-`~sc%in7cx8(kN`8;~M;Q-|O_VRu5{o3;_x&L0ChaPZx!R2`~ zcwRdnhWE+fedrm71CZQ5gZGv9S8iC=BZKv@b7okt4AzU@b2tFW{WFvUuybA|_s?Lx z=~agVkp0MDKkOVE_A7(^qPHCmK=w0({j_s$*zXMX8*UnoTFyfT=fTd&;k;yUUg({N z1CaBS!FjTCbvSPsoHu&y>A9El=;b`xIXs+KFXvUxulDH6dG>Oi?c5&DyO;BB?+M8L zz1V}D^Mk#3u@`#(;Q+**yx5bS3xvISu{UM~zyXLoda*}4M+kfMVz0~=fCCVF_F~U= z?hy9w#opoS;Q+)Rc<~2zP7(gXi@#uY0UUt%6EFURnFjb5$^E_f8)hBA0f;~H;*abc zB>a^Zf5mJBH~{fyUi_Jzn}omf;_tXKfCCVJ=*1t3f7DqElKXp=1F-XL#h-fdr*pYZoy{5^LUZ~zhyyu<@LCyIFC zC0;N)0uDfOe=qTbnG$dS5^uc38;L(Ub3$@|FY$;O6mS5N`+JF3%%*??ka*@Lp4quo z#5*tXjyn`M0EvfQ;vq9Gh>sF4y~In2pE?6W;;EN-YUg4RZ@t7@W@W$uNIdoukL?^S z;b;yE)ni0_j7dx`g!w*(J(!2@3>Fe=m54J0&;($^E_HA;CvF zYeaH?FL;UBBX9tMr@Y`PW|DxfB=`4%x0qD|2OxON3m&s`%)o12@EWsC-~a^AdBJmb z?iqN`3*O^yi#smCgI@5Uos$M$^nw?eodO3Sc+v}=v~$(Kn_loHvsT~$1dn>bqk>Pp z%wmz;-+)({&BBZp!LtTDYv;CscMW*g-ZO%S4S3kjc>^yS@UqSpl=;Gfrww>o@U;P7 zOYU#L+suk#W{lu*10H9F4ES7fe*<1;whS|71kW4ryq!A--Z$WV?)t$0k`Ea20XwIT ze8G?}FuR5sHj+;m@(DZFj(o$AZ!qhInKzP;81fN22akNkkgqTshZ#AN&lvI<$!~Oa zj^zG^e8=9qk`Ed3Avr#} z@-=4rFylw^IYT~Y=l+rJ8S*{uKDh&xe9({&+Bt#bi-vqr@<*K^B>AKvpR{uY$u|x8 zCbNc^IVAb0As=N15wnOS_c!FL%qC(+k>s<6eAdn_B;PgUyWGKYFE9D9As@DL4#}4d z`7*PQn1Lkuv>~6C{90!tN$zjRx0#j1%p}Rj4f(j8qe#AP$k&;z#Ed1$=MDM1ox4cx zZ^-w3_Z#x>1`fc^X(abIZ~%6GBYc8^Pq1?x$^8u+fSvc~$g>#u2;bahc~%1lVCO@^ zXBhYlW=6pQ$h#Ui0AC$~tc8IOk=$QrP03mrH~?ll!U4!y8u%1uQo#YpS{pb3W4}lHA|G0ob{h*qJd8o-=ee4#Mc-&0A^Lf0f;X$@R8!1bQYTU zDx-X*%&vq35MO5CGws||a(@E{;HxtcUufV%nXv{3AimPT0r=)yi!U|ssdg?axxaw} zVAdrZfcRnqAIl6kH~{h01`dGPmv8{$%ME-kGvD9<#Mc`*0BR@T03;R|_+Vzl!2w9D zFmM3O#)JcqSYqIlCHFVVFLxYd-~c4{7&rilMFu`vVv~UbkXU8l0GOQ#2OzP`z-QaJ zweZ~rzMC2jH~@)-20mP3qk#jESZUw@n5_v1AhFcIr%P-#Z~zi(4Sc)g{ss;}VzGe( zklf$E0Z6PiZ~)BSgaeRRZs7Boxd#UzvEIM|`0h0Y3mEPL1REGQ0Kp0d4uIL5Z~%fO z4EG7l^n(KstYP2)nAHgfAXvn3AHfVjH~_&a1`dGPop1nxWegmEU>gGmAXvx10Z`Kd z2OwC;a38{qK{x=xN(K&q*`9C!f~5@iDa<5<0}!lbxNl)rAsm2UF#`u+=NNNeW4Nzj z_9q;GU^&Bm4l@to00iq9H~?yE-~a>*8t#Lbkq8GMSkb@%2zE4Z0D>hA_eqlb>ug2A znuhx(W`)852o^QmM=^sD4nVM~fdgQ6C>(%bS;KvnoP+}qtZ(1|1p6B}0LcXm_kql)gaeRV!N379n-mT}atXtIA~P-F03_EiZ~&5f z7&rjQMGW_mlKUGt0LfJh900RR;Q%C;G2Ca`x!L6Y1`dFlCpZAfg$x{k<)+%T4ZY-~jBrZti0Z_py@u8#n;T)eIZ}vrpjwB$qSX=SuEx-~c4o zGjIU5{*3!z!+o&i{ss;}azz6Nz-&}F0Ldi{_sMpyIJv)p1F-YPxsNv7M@#N+-~c37 zHQZNA?rPuwB$qYZXG`vH-~c4oHE;mFx;V*&4fo-a8yh$P$(0TF<;*^X1CU(WzyUC0 z6%IghZNq&#vr^#zBo{Yu0Fs*L+;OcVy+(Ni`<{{_F`VVJ&(-cV|FaLKj)R) zpYu!Z&v|BUALpCgpYu+g9Os|hAA9gx`yltnUda8iA98=}$!qP4+#h=*_s9Oo{jo={ zwNG+??3LUf`z80sp1sz-$^Ef+a)0cf+#i3yoI?Bqxj+7b+#mlz?vFnq_s74G`{QrO z{qaBK{`e#2AmX3M{qa}i{`fC)fBYG96Y+24{`fm`fBYZ0KmL&1AOA@1kH35|-`@ID z<}%`6$^G%S*ZOC2fBZGMKmMECAAio=NBldvKmMNFAOBD8Pds2wB=LdV zpLjv;Py8VFC!Ub|8#n+PZ^-?LKji+zBXWP@6S+U}irk<0Mea{LV{Rq!johDjNA6Gj zBljmBlKT@M$^D6!L0ko$vo$o;`TUKlq8|n3Ot2&z<4#47B=C*=w$^F5*)Y($IOYRRIexWO1@$w6O z0gI=}{lVAd{^0EwdIJ`Zllz0u$^F6W{@{OdfAWDBx&$^~ zc%e^V^9knKl3$SflW)AxE3o+pb8rnDfX!E4=oi?0hTNb0hTNZghq_|}2VnCdWAh_& zfAS@AfAS}CfAT5j@)|e*n{Sc(8#n-)k1@xW{EXb6e2v_n8OY@RDl89T0Tn8CTG<0ReE+g! zo31|2@}27Y@PU>ORo{q@w0tS^*VTtwK2?1yKGyQB>U;6QmXB56jE}Z_t@>_!xaD)z zx8vh2->bf#7-0EejSa*I%NJ|xAcj~zSz`+^#`4V?dx$}nkJi{kjIw;S#x7!*<+C-m z5#uc1t+9_7X!&rBjl@XHmuu`KhFU&dV=FP%^6eUXiNThSC->JFZTWhQ-NbOq=WA>y z##_E$V?P+c-Ulc)03+D@0>uts2z#HP*aD0J)&O(Z`v=7$U=n*jp;!gXV(%{$%YbR@ z{f1&4Fps_eP%H!{viBp3mB38){zS19n9AO-DAodVfxW+4~>Gf?z^>KcrX@%xLeA6ib3BeL5lbzDcns7}VZJDK-V8+WRVU|K}L? z`F)mRTQIJ@?^5gw2DbNMijBd@_P$K9GZ-2y4W_pDYl^kO-1h!Wu{fCA-p?sk2eaGz zJH_%~dV9a8SRc%9@BcIxASbZ*gPJRlGuZn>%_Ybw?ERwV8sr@I{!w!gauRz#sksU{ zi@m?pT!x&+-fwEIL(XIGKQ$L3C$jgWnk$hr+51z?rO2u5{VKUX_pRu4XbxuYV>LG; zN3-{}n!Az1+5240?a1-$eJ}l2ngiPVU~+%W5$%1k=8oi$_CEQAPKv#6*4&dE)ZRyH zZmK!z^ZRPeUCCkXeYWPdV0#~~xiLAiy)W0?nH<{Qr<40@j&1MTHTNb5 zxA*ayo0Fs4`+CjY$>HsNzUKDi`1Zb^+}{HSVCw;t8{p@*UO>46{vIv?4#3tIDAxc7 z0QbQ6!$rUW*!l$JD&PQY{ep5CZ~(TxLAee%0LlH81Az;H1F-cG%9X$Y*!l_OQj`OD zUSFYH3mky0zfdj)4#3uDC|3gqVCy%O%Yg&1^&QIfzya9$59Na30Bn7Taz$_ewthsp zBsc(DU!q(S9DuDqQ7($}XzNorugY1$UBLm^dKS*Na$L6FMY%6H09y}(eJDo;SBAa7 zoxuUvdK%@{-~iy-us66jH~?FZqud-E09+mR3U>zw0GEe7+xi~m`mlGnKR5te52V~6 z8~|J){sQh04#3tE;a^;E0C0`?8@NX}09%iw+$0)-U1Dl+(2JP0Dq`0oeK{ zI)>q+gm2_<(lCD;GT&;aM8pgxM?^5xN71R+%+74 zt!Gni8x8=jn|KHJ4F_QB;glPP1F-dS%ALaj*m^qU*5Lr)+KIPt?{EMTk6pxLTc4*~ zJsg0o-y@zYr*G@~lRkgI0Cx}I5AGu1 z0Bn7t-c`T>*!o4i%YXy0^^JPh0S92~AN4K-4nT5$y(1C4q<1E^ep2sJ-~eoWrQWr` z0oeLWy^DbZu=SaGR|5xN>o@f-2M)m2cY^oy&d1h&f(P|Z$kvDIT@f6Btsm99Bsc(D zU#fRaZ~(UcRPUnT03`Q!fls-sf&;MitKeC^)3Wugde;R9VC!G?E({L9*2n5y861GE zpVhlGH~?E;t9Na10Ji=XJWf5X-pzr}xvPT%u=Tromj?%6>wERC4-UZA|LR>J9DuD4 z*1JOT1zSJ-{4P=M6m5Mmxxd~y+WKR?izFYh^~riy2?t>7m-Q|a4#3to>s==tfUSSl zyHGd)TOX}=rEmbYep>HR;Q(xXwcfSD0oeL$y^Dndu=Uw`R|^MV>$mkT7Y@MIca!hw zov*F`*1KRh09zlfcg1i3wtigilHmYseYxH>!vWa(bMjHWleYEg> z^)4R{z}ENcT|XRvt^e0r05||@|KSIy6@UYvb^!i>S^_u#pH36C25#0Z{u7zeBAD900W+@ITaozyVPE4?je$2poXq z{#rvKXUTyBp!OeriCPml0BTR*pQuHF1EBUFeu`QZH~?x_;IF7b0INSGwyZTh zJ{>A*ec%A7{el0Z76=Z2+J86z@fBJ#MC}m#A+Q-sHK7f5Z|gbR^n?N zH~?y|;9sf5f&-xTAAXivEjR#bx8QH7<$?pC_8)$iS}!;NYQNxrsRe@rp!Oerm|8J7 z0BXnJk0q8kZ~)Z)E5H1_-%M-I;Gd~Qg9D&84St$hH8=oj*WjR8w3byk0Kv8n_gmDu!U0hG%KaC$uy6p>{&PP@tt=b>wX@ux36^%?0I2UKyrVF`$}q;;Q%C;(VAwT zj+x~C4)>kZ{=)%K3(b9~?T^-4Y3@s@{f7gfmYVxipU#=&T3U1M(>s$~Olz_w_jkCT zm0Zn%1E6-B`&(+c;Q%D}cevlB)*BAMH=l%Ba5wc%y zj5|maqz>jE=B^}DS*8`};l8b!ZY|t9RoAV$+pXGeZ@62D`qcVDPh(yaC92Vdvt!Py z&fAfgG}U@rA2Uex-e$&B6XmLz#YV>5Ro%CaF}qaz?Y$Vc>c16;X(>uqYl`2D&L^r@ z!%G~DKCN1CY0>jl4{ls^Z&Aj|c&kHnIZ?@qE9oD7UA5sJMXgnRxD!#sRU>uhbVFlC_g^(fa=FJk4#Vvx%`nW zMYU^Hg|iWPMZs%`|ECd$RZlJ`Vv1_Y`A4)Cm9I4wf1a3E6u*X4T08Nu>dSpHagu7x zRh{@j6?EoqPRJ<=VFRkJny^px=7J|gtL9wk35`TWOlGBy|68@^lE-gV{kc}-N2mtf zvvE~Kb!>8tt>dn%7G21=C8|ePYFrOdCfi;sGrWkXl#Qqz9ezx;>8gjv)j^*wYiuJ? zGMoSY)UkI}r>^eUHL6v2WlWIj)g_I2U6jv8)~_?>nCjMLjgC?6y13D`MICK=!%Cxn zYWP^x(lWyqs*c^ruy&%Lwz6^2u&1hLw{_G;)wJt8s=uhL?FzU%val$wg}9PO8W;L@ z)klsHCALG((GjIZm2FJZfg_Ho*4@+L<5ll&{&0U$Zi{GMefVkBz56OOQnl}ThQ1@} zZV?~+G3=CT;KdG`pgMTPhLsluxbP2Gesc6f<_p#RWRz;+eKoYWsKgCz-FfI<)yBIL zGC=k5LPPS1l3b6#zlW?sWoz2G!BqG_Z{**rj%=HSmV&>1_#)RZYEG!G5B0H}rp-25eVt zz3KxxsJ`C1{y(e6Ud8?~UC`M}4|+os^7?lz8MI#Y_EP#a73I97Zu$G2Q{BDzzC%=d z?@^yes=qg)&otHG%kJ$bs(XWacI&-CwfK(qYAjPo;^hAxRZYGP@)LCV{CZ}qHs7=! zBUGR7QTIox(Kn=fyz2CwlW#(+uW7dw)$3a?Pl9IO8(q^?w=bqkMNtF{k*8j#`h6Wb zR~Mzgk@8lXRL9Tnf3-wGFihThi|YB^kd;8wuT7^-s_VBwR;r(@SfP$`u_7xtszXIl zA{;2Inyxy3wc3{yg~IN#>M5%CcUyJ>&A)bS<5c%=t?X0}*|9u;3(O7=0_cslYk~*`45YUN@Ad#l33LSJS8UweZY4<=&2fkkuAPboxsy_ z($EU@Z$4l30>?Lds+xhvDQbev;}92GzTw znuBZV)>YlXyJD$m4>o!~OZ5li>Qq+^!ee6D=nxjEovB)cJ!+MbNi@yG3xud9;dSv0 z=n__`@l3S|N4(cc^$E9DPgae>zs0klQ`qR;(xPzLRJ=~G>J{!2PlRS+&Z;+6xA221 zRaLuiQsqxnzwoelvLWKp@>cp;bqrfq^j9szDenZSp5bBfglHP(^*^h+hAk`P7sbtr z;x(JAzTpA!q-Y%GD8E5<4qfGbRIS6vvPGhp@wH1lF`9?>#WSafhptsRU9}H~`<+nz z!?mRzsRrV8@$7Np;meimpjwE%-x?Rqe6aa%rl}_4X^9NzBIYY`Q=-M==$6F`hL<1;^oD9E zx?iiVI*L0Bwoom_+Y8 zM17+FqJRH&qse&Y*)un~jITcXN3|K7K7FYAjN||LOEnt5c=EgIG~Rf8L$wxtG)q))QbDHWwuJ~!3YC`^a zqeC>hkfm<;t2Sh}>yM()hn$mrA_|Sjlh@K!Co)jmbUdtE$fA({FE1Kx@+Zc9rT)#+?gR&B;S&ORMhWD`&q` z?a6j$l2w0l_BX9mgYx|8XXDVJEOmOTYEce26{32St523vP0Bw`WU4M@-4oHOO&Oh8 zUG*ss9nTtzMrFa{Q&p$3`?0#JRhfSD${1$l{dOctH7n~LsiV4;v4^upqg{F8>p0b~ zeCz8O_hwuh=lX1DEs z4?!n$>$W)6$}GGszv^X<+?p~N&CHWqN~&(=dt1^~J9F0NimIP^XVW^>(Coaay6R}| z*tkixG)r!*rFxn%Uu;oL&Fs%>sjg<==bKbpbMuDks;~LxhIOj38N0rs>TLeHE?u=Y zyR0jzdYfi#ifV3FTbo~XHy5ml?~C?ko;8p9puahG^$6AA%wCn<8y(KhtGcNc=T|F_ z_G0c>y_JnslXLBg4XVrOx57`gIcI-1P4zkReDWbExxlpx5FUXr7Kyss*nr6nfkRNc~VCw-vW zrSm3DQvK3ylMYux!}QHbc~!?WE3vg|nWiUBQ9aX-6A$~NY5HzrUez_dm(WtRO*0Y_ zRNr(;!h!N=oOVvgp*pAK5?rcv`bT`E>YZl9?<#}l>CE{1rO`bNim#>Gr?umUtNv-8 z__d|bK+TG~UJ@PD&2i;QqJ=s&uD9x;2FJ};P1GiFr%RxVS|To=YNP%Y+fwyWzln9L zM(U>6U9Y2)njCw#7+R@evDH*BwM*Fs|G&mvJ~toQFro-?A-IQ-emo>x_yHLs_s>a!N`j8~1;qMk2A)v?W!lAar) z@aTE`w#V-=vrOOhbXLvQ`ko}!ZEfK>Ac~NE|NhAHNYo+cJ?QVLr5diIJRz#%8tX|H z1<5A&=6Wv3RMN43t@adFP1n7i)~f4z#^X_K*Izxm?x63QGxkqWqMUKtFSd&6yw;Bm zR;|}Av5QpiH7xd=C|8EvN{%h4y04pJTdDTzH?bbofBh?Vwy1sA$aYM}bE^CnGHjoEJ}?GaVb zKIcnJekux~OTO(n*-^dOw8?Sj(44(C`H-lH4mn$S$}6fpJ90`p)t}upWwvV2zBKi` zsE$rJ-EL|r)uK(EIzaVkuTNbq%A|oO>m>alDy6ee#3j{LZQ3(Q(V|{jKGT2NAyG0N zdVJipf~r${Y+85Ksx3P`UG-|ir~f9(r^!b$r`J{8TK^fbs$CmBqQoa{;*Tg+V z=GIgV+?ctOccX)QYwl%HfKB?c*SvbFhkI<^EY-wqJpUI_iJiZ5!~7PijaxQ#iR$B~ zq&^ZQ+11-$S

    &a-$b)6@}RW+wLtWta`bj3rDJE?u~^fMTItIOVFq9sdnzgPiLuq zZr4S3M5%V!rZbB=tB!8R#XCg7He}<;#U)iww|!cSYU-X$%NCW}`JZ=O5~$j`XO?W< zfWB_mrEjXn?!~3C>-|I-Hz@sAQOI4o?nZhS)!PkSW<)tReC@qu)l_#kYWV`y-p%t_ z9@XES{n=R6;PqRPEvmbVR;^vpS+#iUt^7)+j7H1h{L2zbJ~psq)laRlj%hhBKlR zoGfqEQFVN?KR+o7!ZYQq+pC^$Nm&UreRpi^sJgzLWu?&ey|byS>if>xd{LB$7t5*! zsm|}oEjL7=c#W)jsOtR|mYqQJck8xj)&1=zJB9Y|qwOiF=>IO+QC2m8Tgc9$1N_U* z#;OH8Yu7QEt~^IhK`+$=zWn7aIUU>Ol*Fhua7{Tm=mUShXO(IMC+uykI>9yMq@fj@ zl`&NHf~R~mmb(K3oYSJ2ivKh za89uVG=;Z*m8`nLgT+$N7Jf@C2YulaUq`FPaO`1!)fuiUmWI~wZ%4vaZ#eyES=Aiw ze(cyZbcYLyrJ_B2=(xY?4@YO7Q4Qj{V%g{r|8b&@Y7wtKd0i&Wdc_N*swQzM@eJq^ zpFjPQY7@`?W|!&{w>vXZHHu#m&w@_zp|jV-+ZgdWX{uN3h$lj``02MLRJVA~`EMto zT|Du-d8%LBKs?z3@n{b(ys0|IJ1=Ibmht%S(^b#7fp|hRjUQ&ctGdR!FWnQx?Tg|y zGgRL=Ks+fL$NygLtUAa0fBZjDcLMk6SiX}-?@RVAOUAwo z#>_J_#x}A`3yP90m9>QDzHCv5vP4nJQb?8|$@)9rr|bUw{;!w+FJCjy^ZDHOwVda1 z9OrQ?mRZNs|Mo&SXa6xy;nB=I{$QNUa*ywQVwcQ5KJ&?yGXHp+r{>HIx1^Mwb$K624zb(q(D z=(JZxp1thEVQ%y3+x~mxhzmE*Y)JV~A9(rcksVK6C^IAFMm@jDUq&uF;K^a0^A-m` zFmm8pR}6EVx7_YGBi*cr5A&TrILA#Rms~k6Gb!a#oqgEPM%LJH&djQmSM`a@e=u^= zefJJ?pMQSQX(K;g^V`Gx=acuGJo1B6cFD|3xmOQ9yWhx3w=J1jm^{LN@rCV14uAB; zVJ`F@>wJ0ShzEW-%!i(L;pIopziecf6aB*VpBQ;(hxIaRQ{L9th2Nh1(`V+*3{E** ztE~Ivi`w zleb-A<}hD+@as({k6d;AFlYMl^FBZM_*q6WD^y5nfzwUCTTxn?i@?0?66VUNp(dDZ(|_`74aJbnLRZuQH%TyV_B6IRS@ zRQYJHKX>pkW&ZyRbF62sz4kHd?sxtF^*-}k?(>mjrW`hLm}`CZ4v$ZqXUrh8SLLs* zxX2X~=RR+i%w(0zcIi(iOg!%ww+{2JkDh1kiH}d3KFqydZrt1x|NG)Pne8gyZJlw! zy3GCl%zTymw&}dzJ9?$x-TD9Xu&>f@{k=eKM?=C;(;R#<{`oF`R z?Qz?kKH<(W*9`Nv?|pN<31{AUz~}qi?Rk$14EJA4XSS|Rz;PGohS5P5$uzWnH6C)~A0W&q0p{M5E59d^klXAbkbN6%a3u*Lsz=_-AW_m6J- z+o5ZIewSgM_xJCaap*EHeLORU~=`zV}imK6=Qhf1W(d`QB^nv_npK zccsiKmRGp&AD292r*HpbnESoNHuoI7?FHW*=6~-qdf>q~EVxl-9?L!a^@l!s@bBJv zdzc5l_&V1d^ykffKFkF_c<(I_T6UgYhxy>=95(a7c~+V)GnM5kPT&9Z1MeBF!@Th2 zwp{+e>wk8@FgJYK62CoQvDp{NY-ah4BhTz{z_!1-YnUVcsqekL|CRSm80Lv@HTInS zr+j7c%y^dbxa9Ab-~a#S|NSsu{M*~yKK}1(PaNiqU-tX2jsNU#KbKk2@*;OHFYH$? zxo?;|{<|Md-S4bNj~wQY|L2{L?RU(cpU%u_xs%Uq{^M`#xYlondE~!3f0b{Xwf{lG zT=JuzynWx}o|`|jtL0a&z4(^GO_T_iG?&VE}dFh)Tbos8|9`ny(Zu&#ZFR|;P7fc@J zr~ltO7wqz2`9x-x%Pl?hiG_Aqcb=aN^VAo8?5v%)eg9gSaW3cdfamAl`Mb+KILueS z^5e(ubpFJ>hdJx3Z}Yz$|2y-4!@TwFu0CMLa>mKS-1WVed2)w&w_Z52)#a;>)@^op zd+Zg%9QJDu{q6RbueWAqamW<#zy06(Ty}rf-|6$&{VYGT&uRC&{LVhF-DmNc`rLM( z)o1SW+kF?`sn2ouU47?12gI}RO!{1R&&o5C?J9rPv-C{+oOjRKGw<`>y$kQ8&wcl< zyt4yZ{=0YSoyvffd+S|$=Y9T&wO~#3x$xGCHPh$ATT9lIwIx^ATC?W*ym)KTn(TAq ztyOEb&yTm3t?52T-deZj``iN&(3;hexEPnE^sHf8{|a0E8H2faqnO5`+1kRQ)J}I zm3G&-bKE`hrrkyEB$>GvM-H{S%AF-US3b47%$??LTOx9+-F5D~KG()w=uVWW>yC6+ zx-(_#%D;A(x>Mb)akf7oyOU+^%F%XLyR+Th^0nRN?sRv%+--NgJHO8n zQ46REWb(@CRx79()DH5y)e>q78NF%@wT7BQRt)u4Yb9~f7Y9h6foN=|1nn~@n++}lREv2TC@vFvCYpJi>b+E{;JW` zYHBvMn|yP%oSIGsu-x;k^`hqM^MllaYC^T4oOHFKno;d2KV2=Urj!vZS6!{C=9CpI zZ(S{_CRLltVOOiFS=Fxc+10XYS{cG}+ts>i-afZTEvzP%DJt}i=4y1cx|&_>E?-_PuclYq%bi#2tNHu9B)x#1Kqj%AdcA_4 zLGK{HUN51i&|Ap0*K6oG^d9o=^&)x_nZ@sHTe4Ttv&b$!>#1F`m(kPcZMOO1NcK8< zo<65ZFQg~ROyf0f$X-d$B-{9oryt5*N>8P?+GV?!ve(jc>Ah|{W3KGQ^kg!RuRY__ z*{kWa7-t4K3v)9w}_4!bGK|P_~aAcFivsctJ%0_-=*%Pvt)Kkhx zzUkg?XRoQ})O%jL>LuBW>PhvcSMPCM_NsbT*~#Z@eQWlzdRiIEgAd)Cy{?}3n8;F= z#ibY46YGulyYuhaE9;r{&NtuvZ1&Q6Y8lHD&VDI-Z9R95tmSE+el2@(J^90tx%`Ji z-pF2E&#rgh{=~Plm)FzFV4i>X_j-Ljzuq4Pu*i|;zU$xRH2UwG?tA|`{=ED~e}CVd z=6c7^lk4c`@375UZ~J}n9{v9Lx0&#k&m#xY=R0ZVpS|hx%7^s%FFN??H+&ztk-pzH zXDs}N@7w2aonE*6pXVWG()0P!J2PJQyyQ=Me%oz&>wi5@xs;youdn^zYo52fO3(j@ zF)P02eaNx&ezw1TpZ|DY@-4l;T@Sh7Rqykz$i4J_j~M&NE8cgX|21Rr`ChRe2z1O+_w%+^Pu{ozd_`Llf=hObU^!M{TZ@57i#|<^YjhR+K+NX?axDJ`_D7>t9()W_bc12@QnQ|chvrVE!qJKCKulIN7U7xcya`N=QIS=KmIv;1= zcgy3>OZltL&sX<&_pi=Vxvb9DJ=P!hSLf{-k=N?{U2NLKzc`QOxH_LdFy9T2Ij`lr zI=^3k_4P-c=W<`2@4s7V^+%oeeZJf7cTf29BXJ+diFH4mb@MO(;CxS$6tTM zeIi%Z{j&UTR)55OBX8FIv+iGydf0s=ht~bH({?xh(S0SK*8R2K>Tf^fK6@u}Yu#@l z=Y7b1*XPPTGbT8kxDVyrx*ylw_}34(FXi95KkxYC2O^dC;R$ka-LI?Px6%FXTY0(e z-~CrV;}7m*IlAuWl|TN+-@C8n>$<=dC9hch^}~HWd53yTjKTx;J>htl7pKybEUB2{@GdI}p*mM8-EA_nG={j&giZ?N0j`yTy?XMd?*kY7E1@o(t|l``K$F)&;0MNSDjh+ z`1(NyopzOeOI|k&;Lk6-bftbwj<^17>oHqisb7=tecDPd?y>i(zxcU+PVVcGw{I2`lx8N1}Q90!Ij^Ah3Z|*YnC;C!vNOZ{jP7p0CtEhdKkb0 zKimFWFaVkKFo3ydeg141fNXjgz)Cw#J{txgqaFru{>>jb8wMb&9tN<@3KyRR1CUt{ z1K8)XHP3xNYAvVE}#3=~G{y?MxVeOnVr>lm*T^0|p@5 z9tJS!Pph5*1CVhK19;$y`%i}f$hwCCOg!_z(_sKdN9H{YVBeGHIUNSD*Ncyx1_L2R)zt5_qIu=zyQAX#%8C$03MmJ_$e@eF=Jod(F9+-Ou4B&--KXnoepw9_C>8)>{1OwRq<%3Ux0c^CwMkm1lCj4TFlVAWZ zA3y6!Fn|Xxc0HReT~|9E2Jp4B7CasXu*FB- zI1UDI#-ATO4hFE~i=)TE0G8VHg5zKSeSYqhFMs_w7{HESSpPT}zzw&C8Z9t@$IhGY zI2gbKx4t?Z25{vU{xls1aNNw%=`euZ-}>Qn7{In$oH!i@aKx+oPlo~A`^1*hVE_j$ zvc_~6z`qDHQz|#{RodyH= z*vK8zU;tAexM~^&tsW5SDDKLPKuJ_y&eC$RC{B;Tp;N>UppMtOb z;H7s?fdQO%!%b80xj+BZ)l*;q>)(CJ6nt-=kG$;sXHS6vOu1^t6d1r^=T4o1FP`VY zBd5RsHrwH#Dfr|suei??7{GH|?>YtFywPvBn*sya@8r#=;G;J_Z-Xf?fY;vq@)Uga zzL$@i0t2|>lGUc*vu}B2#VIg=pPsth6nuA|%lxscJ~IUdaQ5o|Hw6ap-+33Bf-hg| z3-eEb0UUVgN2lP^Pu%arQ(yq!ob;h7`1VPEoofmVVCPeV;}1Um^QXLT3Jl<-KhHh| zU;pC?vrT~kY`n*;Q}FrEo&N2nxAOGJJ|3Ci@1MuHr0RB7-z~6@f_<1k@ zKOY9*_rU=Cei(qy0|W5+U;sWZ48Z4y0r);J0N)P=;QPV=`W$M{0|wyvzyLfi7=Y&o z1Moay0G=-l!1IOyc>XW|?*j(l{lEacFBpLL2LtdvVF2DQ48Z$_0rdIT)&mT{`hWpg zFE9Y>2L@n0!2ql;7=ZN#1F-%Q1Bmqq1F$|}0M;uE;ES<-VF1=M48Zz^0a))afIfHI zet-ekA20y>1qNXMzyRzg7=Zl+1F+v<0QMgYz zVE}#JxAOo7;Cz4qI4@uT&JP%X^8^Oqe1QQtZ(sn<9~gl12nOJMf&ny0XXkq0DaE5^AHB$e1riwFJS=APZ)sn6b9gYg#kEkVF1ow7=ZH_2H<>#0XVN= z0M2h1fb$#%;CzPxIPYNqeZIN-00!WGfC0EKU;yq97=Zf(2H<{y0l05q0PY_cfcppr z;C_MuxUXOU?k^aC`wRx)euDwH?_dCZuDbgW2H<{#0k|(=0Pas1fcq2%;C_VxxNl(q z?q3*y`xpk`eue?KuVDc0Zy13490uTihXJ_nVE}zDxOxBvpgw>Bs25-W>IWErdIAQZ zzJLL!H(&tj4;X-Y1O}i!fdQyjU;yeD7=U^P2B5xy0jPIi0DX?UdI$!fK7s+LmtX+u zCm4Ww3I?FQf&r+vU;yeb7=U^V2B1EJ0jSqt0O~gwfO-xFpuU3vsP|w1>OUBOdJqPn zK7;|N7hwSEM;L&55(c2YgaN2GVF2n+7=U^d2B1EL0jO7D0P0s5fO-}NpuU9xsCQui z>R%XudKdVFu3egFobKY#(~7hnMT2N-~U0tTSJfC1zrKZF737hwSUM;L&95(c2ZgaPO` zVF3D17=V5h2B1HM0q9p@0Qy%LfPNMRpudFy=yzcN`d=7;ei#OzKZXJ5mtg?{)x}p1pVAU3e$njd$c-d1v08cj#Sur{1l1>|J~3-n}(o zEm#xQhBacXSToj+HDoPWQ`VL>X02Is)}A$JEn1V-rZsA)!HEbQ}?HaH`k70wK2hcm=k;!JV2IAfeO&KzftGss!wOma3kqnuUFEN7Q9 z%vt74bGA9-oORATXP-0BS?El3Haa7nmCj6Or!&-9>P&UEI%A!+&Rl1&GuT<|Om;Rq zqn*{xY-hJK+*$5SceXp@o%POqXTLkZUEoe|H@G9*748gohdabw;!bh5xMSQk?i_cI zJIGz+PI5Q7quf>QEO(bX%w6VAbGNzU+;#3e__sUIUFc49H@YL;mF`S;r#sYL>P~gH zx?|n7dFRI6>kf7oyOZ6`?r3+lJKNpu4tJNk)7|avcz3-!AO5cfPz$ID)COtC|>=Jhh&h z5C5YER12yJ)rM+BwW69)?Wl%SOR6c=mTFA3rkYdjsRmVxs!7$RYE-qVnpN$phE>a| zY1OuBT(z#67yqRORtu|%)y8UMwX&L7?W~4YORK5X)@p3Ewwhb*tp-<%tI5^oYIL=_ znqBR#hF8n0>DBgXe6_xsAOEKZ&B;nFdNjS7o=xwjhttdH>GXDbJiVTt5C5wN)C=kf^@e&xy`r8`@2H2= zOX?~0mU>LRrk+#psRz}I>PhvcdQ`oto>lLvhttq0eO>&f-zdUUGk${e7(M&KidDI z|8G7*W1An5TqC|ly+OY&r-f&^2cP5@(|@?CJ&7tnq0NQ+q3zz$$8`RHfVlva_0)~%jRDv2TvAdX?}Wg z`S|k5_v7y;Cs0;nX?}xp3k&bWSLVnJ#Qfj>Z_SS}|E#~${2}va`I*hHGJluf+59u} zv-nJXo_+HL-rq4|{Nck>;aZ)$#b&!G9Z=CkpPny+j=JI}EB+~%|Oj6e3C?`}SO z@1Xer^U}&Z?LHT~`5V9YF5{gxzh$0Le4F##TLV0#{CoWO^rYfxWeqfc>|xGv^XvBe z()+9Vho=XbHNeZv=i`ZH4aB=ok2M}`)VP_5S!t;E1>RAK4`K$pR zf7U>sm)dd%(!0JW-yE-WP92YoO&sq}QZ1(C22x`%e$dKF2ctTeSxIT*>&m z)f$MOm0qJQuVk3JC_BL#h<9JD$Cl?(;;ac=zeS8_%Lz z1H6Fk51zu-0B>UZC!S@s2IARP`-|tYH4yJUJ)Bz()G$x2&qeF=&3KgC&n<6jT)gY_ z?v8g~+y3|OH?{vh%++dtf0%O>`=4jEcVDf6_WQf`dAxg{&%5_|y?dYEyZ3$g{rP@; z1AX6N{!n`!-o5AJ-DkE!dw#>5o%Vb)bHW;E&wrRh)83DF?|pgq-d|>fSOe|-4s%o5 z`>%bD2`^HArmdI!yM9JnPs6;9K6it6rq9sUV{PlxyU)+u)^C0n->I!{@7{X%?(-RV z7M@AlANj02v$lWoS$d{ze|h)$%-jCUcj2A1{W2 z&$B<)Oz)50`<%D)#qV^bZu(RJ9Xy>>0nR~jO@7}jNVCa9_?t`HpZSO1V z?67{ECDuUi*V_B8I(w{vb{`G>Oxt}m^cQuOIn$hN)_}9l8ff>Qcb{jXv)>wUR@yJl zerv#4YCkz!t$}vm4*eVBUF4bE?&q%eMeO|zd!NGIZ?N6>H&Fn-7A`@Lgp&}jK7M>W z_s$Pzqea5~XvU=17kn~Yl$H*srJcf!X;L^g%?MYg>EZk|KHQ%MU6dM4bwW`^U}^Wh5ia5#ru8}4HK$JXBN+8zHBPG;wZ z+u6#S&)l8oSJ~*ky{--SHU3;Yxb6+7H(pxXjD6xDo>(`8^W0xop5t)-RUi5M_z8=ZvVZpG=>h$NsX@#E1Vp>F7T_JmaXpJvjZy z7ydAQ!W{Q~>4;C?Gsoe4a1Om=>q9QP?TLe)xp|iZ`O+MB#Aq=yys^#ci;1h=Xd?!aO35za!`0-0DHSM^i zKKH}vpZ&}qkNxDL3m-f8!iP_LeZeQDKJkg&r~c-nyeRlh@RZ;iG1rvEXSe(3iYZY( z4!j!pG4Nd2JtkY9i0RkEV?uV}n42mYuqnB*> zqYuU;`<^lFe$UV5Ie)E~n!ov)G2b=2Z9dx!_KGp-ZiP1oOr^Y9u6%2&(n^3>@Po@ZZ7!MCl@~U{o(LnhIh4air6aLB+T2IsWmtI z=v#9Q=U-`9@o2QT$Al)ArWCJt+N!&!MwrGE&-m8X=ci_w<`VB&cA1eHY8ps9Y(LLP zlZY4I;eC@*V@@N8r~cUV>8W|A*~6QU{rQ(tgWu25{r+Fq_hjZqJW{7Ub?2mu? zIi7wVr=P3o=VSUgmwsNQpF8R2NBTLCex9SB%joAT`ZUN-|O>xoqeyD?{)9Je!bVB_j>YP7vAf;d!4p->mB#HX|)gibFX9W^~k-hxYq~w zI^SNe+v{%i&(=V%gYEUKy)L!am-aeQc!%!?H?anK{bjGC?DdenuCdoA_Bz8}FWBq; z;CI$Qufyy0biFPPzG)5gI<;PJ*6YT4{a3H!>h)N?uBz8Z^*Se5r8Us&j(Yu2uLJ7! zJiRWb*VptqnO^VG>sEUGNv|X6^&q{jqt|EjI*VQ}(d!<1{X(xp==B7>E}-Z4d!D}M z+k4(TUVof`v&_=-*gYTJ^U6Ix-1EFWU)%GpJ%8Hspgo`2^O8Nk*z<%v-`DeYJ^$A8 zXgwd+^IAPW)$>d}U)1wHJ%7{lFy4Sst20i}YF@(`_4W7*yD&j9@yi0JwDgtY&~Aq<6b>})#Fe- zp48()J-*Z9G(FzZ<0kR?i}xQjZ1&Qv9vif}Zio-GI#a)@XB+n2{;r?V_rZNX+xh~3 zKWog^rxdlWpP^=ko2b40g!b>leyIIeYWKX2GC^mV^q?q~Q}en$Iz!@4;Betw3& zPVMW>_I*3`pBhgcr&d#sskziuYA5xP8c3a^mQk;$Nz@%`3%^~Bpbl`?yU*R(?qzpx z?=R8cll^_y-&_6t)88ZgebArl@%{3A?$6o&yzI}t{`~6Cq5eGS&xQEw@d;;{rQfIh ze(U#5zyAAm+^@%eUBzF|_3?c8Wk2}g->%Vov)9}t{{5D_&snqiX|MUQ@YNo(<(q3Z zpY5?KHtyJE+?E% z__);`9x2yPoKJo@|L}2txNoGK_`yZwit`m8ch8+8<+blDEpNQYZE|$~Ir+wU0 z^N*BezjcNDcK+?-E_&Zcx$)tv<+>NS?svX2x%}mmzZ%#4-p6h9_sQjyh~sHK@Z-L4 z@8ojFdA}awpCdO+F311nZn^P%xLI_~#GCe1B4TWv96Zk*QZ?ksUW}QaSnPd1a9mnPlVknpEyN=OcsW!$0`i`jg7l zSARUQL_Pl_%T6le?pU&_v}Kl%8Jag*gZKls^w$CMxc z-=}4l@&6x;{`{Eo)72Lrv|NC}il-e@Hs4~&LCXsmeBgj%$|?ITBhyTdz~Czz9aDCj zzWfkpetPL+%5TpbGibR3gJ{`9;}h zMF!fI-(95=pyeG5{<+D-^8O{hJZL!xgRd?%v248Ny3W)* z>*t+yVp(vr^#?6CVX(%ZjxKxexzV8IDGctu^60Yqk(p{z982n}Bqsv8CZYN7kUc+FHxsER1xOE4aYH}O~XZ+=;a_Iv*4_co; zIQFWe%8pO%HfXsIgU6;HRgQmk&q2$B7<_NrqsnLI*hl7?oQOeP`lzzP$Mzev{D{E@ zZys5G^63L)u*sDeta;Co9<;oP!CB`WS)Lht*r4T547M15WVv|#3GhaE!(hUi zN0z&{K6=n{D+Y6X@W`^wZj)rS$+H;z_u&cUGplB1Tan$i`Hv@*4Q`w|X!#d|j~x>K zeXU~$Ef-@jb}*q_e*5%6%gY$tGuMRj_*ajY=_W^GaQlNtlw0mO0qzO+7%cvSBg$r* zoiu2<8-wTfIik#XV8)>3aST4S(h=o=ZN52ZIUR#*-Z;Fx^~fo*-{f};uDSK_veFKx z4IP@_hyHevv)po&~iWqOD=GDsgIupe}%sce*4&A<&<5& zHE6jZgNH6WtjzNFa|SI>WU&5Thn4wv`;N>wIU|E5mpQE5`?v4Pj*~w!IN;xhmL+#R zSB6}XCAa96hnB@2KX1_TN(Ns%(?%n zF(>zAFvoR=l$9U;;h^QA4DLMakW#j~NamcJl)F3jNi zlMgI^{LZz5mKQTP_A3XLf6SMec5-9}H@tN~nSSCg2Mre+>~!q`ca9^Sv4y!+^&<<|_BKV|>&uZKGscyet9GrzQd zd1#}X2QBYru=s1C4!`A=LCe7z{Q9!-;%9^7$!`OT%b4_a={V6zX8FZX}y zjzP=Q8LWBBer5Ml@06J*XJ_!OL-s2ZX8G-)TWNm;dk& zgO&$0SZVCO<*OfgV9;`c2Je4%pR(u3gM*eIG}!1{`;@nze`wHhg$A>KX`k}3?H?Yr zyrID|&+lD+bjKrumP0hS<($3CPgnXgz5-r3xNEJw%ZlHBbkK5(2J1YxSNZ&0nblWh z_KgWE{vRItSDAfsjs~Z$xmP*mFOLse{?TCPC%;}^SoiOPmWwpFV8++W?LU8F(DIT7 zTdnx@GVg*<4O))UVB*7jmb*uu9`b-6pR{Lr^B?~hM8;oZe{5YWk#UfsKM`7-L0&Cz$=56CpDP)$6d=+ z_q{r3Ia7m^j@Y%FHRiR!r{Bw;8l3ZqUCU#q|98-GsRp0Cc9(MMORo=FUe(~ETkKMP zyy+W*mSZ)T`r^*zGe3KC$b0Vn&7I2}A9{Pxa<2xrEwyvmVBdFS4a&nBeEasD$}7Kq zchGXO%HMa{sl0poET!dVl^?yaW4UgS8H94R%3sdju`K-jtfl2`l~X^zV_E6Dvz3;^ zRj$8thw}P5iM1!Ex&5v?l>KMUURrKfIsEnQ%NgIFqqID)GS}(bm)$pbUuijCW&S0% zFHijEeWm4pmGefwR_48M&eC$h%6VIUtvs{g`%B9UD+@fkT{-Zz_m`F+g0l!e!wyR`hW zGTScOlpnt^cX{W%T(k10m$ohspYx&8^3KX~)3z?x4CW~<2d%vM(XGqs|Cp!rec*aO z+Nym0lzB_bO)DQ>d8@MK7d~8Co?6-Z)-B8RfBtZ3IcsIX&9^L%O_{H(|6cxD`P$=K zluMTQNNKrjWx@ToD4)FNBcpC~Oqt}I(NE$e-C{?c;g z%2U7Dq&)uI{N?ob^5)9ITWnGmJY|8>a_GuKf8MzK=kp5=`Skhr*ti_}`vptOt&1$L zjmp^vf3mbZyYhiUHY!_xbfMC6?#i97Z&w8HYh(lW8u=PuwGenoyAJa^(%XSdcAW0-xn(_@2}kZ z!*$D?lQR=i4q&1XzjAhb4v_$3%@+)OJ$#FnK3E%usr|KFO{_xTB@`>#B$lGYn3an%FIbQ ziRGoa)+*P3b?MUb6U)uhOWF4ErAy0IET4LJP)*1&2r>%pD!&JvK)TP8fAwCS12tnvix$jHOd2*uTWZ!WI67qUo3wen;adk zzWn_&Uo6MmJEpYU$#VC%S1&)^WyR9+D9e{Ww0b%Cr4>udsVo~zS*_eTWu?;cE6d}r ztXh6P-^!)sT9!HXUbQTJ!OErOU6$+rv`YEH3STIZiCH2Cv%IFThUnAOG9` z&42S}{8@je6@-rhdGk=HQ<#)FH&HOArQ)Fo7XY^Tp=9br)-^F)|OwIg`zN_!t zc*=Yho=IeE<}>oFJhPSun$OZR{qMc+J!8+>GjI8!`7XSZ$l%O(W^FHQ#vK+za+ZWPIixu~+PwmdBcV$)2*e>@j=Ip8MSW@9jZ*(Vkpr^~H0K z+N<_#%X`heY)?lfXzp=)-JWm!ah?Uvgq9ndXN5DP<;mt*;!KIm&^%+DHO`!tKbvQf zGbu7e^NeyFs9p$caXSKZGyvy8ayL{;5dB?fy+OJ|CbCr3Dr%O< zQq3AhEu*GsInG(@sCk;sA!{KuQDm%UjigpmGp%~zdo`3=N=+4+t65{IwbWcKKRRnM zHCbe^W{sv+Q?s?a>8$0{bdkxLHJ(~e&DZPM)Picl$Y{+PQLU(EY2-s8Aw5xK z%w~_ISJE@JJoN0P^i+{Kn?06ZOV8Ev)3X=TleJv+?A7#adN-N0dO1B^WYT7jr`OZ- z>HYM8dOP7XWkzt!Xs$Nyk+VbMF zm(|m@9Qo{Z^}J0Nl)Z5F#B<-9J+fX|&wTQ^_hb*Pm)2A3t@YS?Z9R9(ug_jwPu_Cv zvsc%%M;31O@OpVYePrThkFVF)^EW;vu>hDrWaK7B04snQL{@HM2(Sd00&D@s0Be9b zM0Rds5U>cCL}chDMggmUSwxm@Vi>Rtm|OyI=$V0|z@*dGiK76=nuWzn+|BZL*g3}J^bL|7tB5w-|p zgf+q(VUI9KSR_m`GK3SOgjK>UBTG0jOjssNGctt}Je!U#u~3*OY!pTcD}|Xx z)^K8|uvD08WDY0B3TuVA-aKhqVz97Sm@I5o7BQ?AW(&K8;lgrZx{*no7%!|B<_r6U z0mFh}!jVy&7%{9EW*k|?i6O(1Val*&7&ELH<{a6@i9y4nVbZW^7&WXKW*u3^iDARC zVcL;toESH(8|K~XoMGWGao9MF999l9hn>UFVd*gS$UIJr9o7zWhrPq#Vev3|*gT9L zRu8j}Eab%SVfirq$V5(zAJz}^Z@g-90XTukNKTFbSAa8E?c6UVhk#4KDc}}x47diI z1MUF_fs4RN;3jYsxC)#_WGN?yfy=;YM5c0b9JmggN3ZL~h2TVRBRCRV3C<+4mXkxl zrQlQ|b2&K{Tno+x_kx4L#o%OcGdLPt4bBF4gTuk);B+FBIXNC&56-9QJ(CN<2}MS8 zazwZyoDuE_hlESQDdCoIOt>bT6YdEIg^R*T;ihm@xGJ30Y~PwaIV@ZjPHUYBvkY)t zxGtPmuVcrB;lyxbI5J!r&J1^kL&K#dr}oA_lViiR;oNX>>*~ zIXqk*P7k+-%@6B9d2@=I8odvjucmlGsT_aP;sd^)ek;; zY;vr)R-7yD6$gup#mPnnb#k=0TAVHJ7Ke+=#p&X9alE)*oNqrbfD6V6xMG|! z?ih!ROTH&KW!y538P|++#y#VpanU$w+%%3FSBche;& z7mgFhjpN91>#vF9$Mxg4E34b*kMDDn?<2$8_Y3a-Cf_%{f6isZ^SH_Li05;Y=M&HC zCeJIL-%T_C@jOR8PZ{B!Z#?f&&s%o5=O6E5)ccSr?)}938uh+pjeCFbK1aPz8RXt? zyzf!(yPpS%^)PBZ$Sk)$V!e!7FS5+7pIA?$){~5L8h}`Dqt=`3bL%hGoc>_ zW4(^%dX21f>o?Z(sP!yE-TDshf7E(!x^??u)P9h;Zhypn8MR+zvC{y=ej2r(WVG8~ zvEN4RH`(p>U+l+G`%$L5{Tcgp)P9ZqJ4yo(`+3xUmH|%#5c_@9e(&dB;yf629>|P$ zKE!!3>b#I8PXiF=$*A*0#=P?-&YMx^jqG{nPn<`i&Lf%ht8bs@)u{7IR=x8p&a+YH zS)6a9&bK)4MxA$Y{+YdS9*#N><9zI#k8xgh&dWGII~ssEPdn#noUfhpHO|}4c^l_% z=lqTHxN{!I`P@05D)hYA9e1dxSu*2fVi(Z_f_0q9SuO-XPx^j z?zhhU7WZA}zU$|V;y&!$hjBl4Gyrj5cJ9l#KRX(LxKBIxY22@!`!(*{&V3vAZ|DAv z`?zx-$Nk*7pX0vn+}Ck`cQgQTpLg!_xZgV(fZ+Z+_kGh@;r=`IK-32v4M5Zjoq8ea zhmHmy>WNN05%ooXoQpI`vD`Go5-S>YGk| z6ZKA~-f43lxc^Q)6!lR@0}%C6r(TNssiOgida6@TMSaz&ucF@S)LT)1bu<7`k9F#? zsLwj}S=4KtdM)a=js_s=xlTP7^<75;5cOWC-fQzFxc^Q)81-RC0}%CMr(TTuu~R=r zJ=v)zqrU9amr-waS#M67*3ke&J=&>9qdx6u0HR*))T>dyb~FG{&vxqBsBb&g7(o9QAWY0}%Cer=E`bx}yPzdb?9^NB!NYzoQ=S)ZI0 z(@#Wy(djRu-{|xk(SLOMkLX7_{YdmDo&F^Hl}^7B{Yys!5dBQ2pNamaqXCG1r_=95 z|C6&I(GPX{q3Dk~{ZaHwoqj3$r;Y|7`l(Jo75!DGzlwgV({Dxp)#<;YAM5mE(VulR z0MV~?`nBlaIvRlJ=Q{md^miQ%K=gZ^ey`0V;r=`QVDyI_4M6mZoqjR;$BqUd`pHf| z8U1BP0}%aYr{9eJv!elsezen%Mt|DT07Spq=~ttF?Pvg^pY8Os(cgCZ+u;5?{cf9! z(hqm~;pmS${c-fmoqjp`=Z*#-`sq$T9sPAj0}%aor{9kLyQ2Y!e!SCF&#W6@R^PV zAh`byUK99DM*|ReP6y8ke5a!U2)w6*_q2I6+)5O`My@9O73 z0}t!qVS$fz@Uh_jJ9t^(XB`bd;AtH^E%3FD1|Ycq4&D~{TSo&Bcw7gM3w*Al0SNBD zgVzOq*Ue%a9g1fJQ!GXvl3XaEB5?BJdK+-u;W z9XvGf(T)Znxc?4b8u)2P0}$MQ2Tu)rwbB3t_g~?yfxlK7fZ+ZsJT~yz`iDD{`>*iY zz;7!JK;XF*o*VdXr2z=Mx59h-dE3B)D?B*x;YtG#+<%1^2Yy^>00K|0@Z`XkD-A$! z{}tXG_;aNJ2t2yNqXVC=Gys8DS9o>c*Odk!@aziD4t%@P00j46;oWVn5*}XR;en6W zk;jtzukiA~&npc;;OP~f9{75NuLt*E;q8IHR~mr8<10Kq@cBvu5Zr%-*9U%IX#fJx zukif9_bUxR;QbZe-|M)852*Nn;0G!VKyd#RUl9C3r2z;&q2d#QU#K(y!8gb@KBeMQf?ugL0KxrNd`s{zl?EXAn2L`Hex}j@1ovO@HNoFh8i3$)Dn2Lp zok{}`d{4#q^z+og2UUDf@I#dbAh`dEFADys(f|aXRPjl{FI5_V;QlMVDfp*K0}y;v z#YY7{RcQc%ud4W};IAqTK=4@=pB4O8r2z=;zv8>hT$;TMKCI%yf*-3i0KxrNd|B{k zl?EXAw2Ds)ey!2~1ovO@ZNa})8i3&ADn2gwxk>{N+<(Q_1%Fp*0D}9k_`Klv>Q;Ls z_h0dSWcXvK#HKU)93RdW9oUmE;rr2z=; zzv5GaU#&ZCl-z&Cw+8=OX#j$ct@zmBXDbaraQ~GCAo$x#0}y;}#pedUTWJ7-@2&XW zHV=&tuK3{Khbw+Kxc`bT4*s~(00f_0@yWq2R~mre{wuyY_~%Lk5PWpSM+ZM$X#j%z zulVZVuPY5e@Yxlg9sG8s0SNBD;=9{iHtxUT!-F5MGyuWt-e^(lS z_-~a4ApUHn0f@g_X#nD9ReFN>*_8$$epjUdh~Hgl0OGS$dW86Fl?EU_Yo!5*&t7Q& z;=5FOhWKuk1|Ys`r2*)D3F28)dWd*7l?EW5Riy!lXIE(e;#pRDig>n_1|Xhwr2&X% zUugj1T~vCEcsG>>Al_A_0f={3X#nC~R(g(jx0MDU-gTt`==~64EmRtSSR0iFAl6Ey z0f@CzQv>kspwg4X+Nv}FvDPXLK&-t=0}yMm(xb%MtTX_zRx7+cs7enNXJe%Sh_kZN0L0l@X#nCZtuz2}wpJQ|IBP2nK%Bjm1|ZJjN{njaF?{^V*L8SqRyP?tm#9dKo0OIbbGyrjzRC=;x4W9baA&<8i2TKYwGP5+_KUD#9drz0OD@0Gyri| zR~mr0yDJSq+~t*?FYfkA0}yw8r2**YwxSlOGyqW>R2qP&6)Fut)DD#fAZm$9PZ+gD zr2&XqqtXCG?NMm}q86$2h*6tV8i1%(Dh)u?E|mr#YMDv{5VcLE0f<_s(mVFPB2f!f zddR4aDh)u?N|gp6YNtvA5VcgL0f^eF(f~xQRcQdC_Np`hQHxc2%&5&O4M5atl?EVc zw@L#LwOpm=jM}c!07R`X#k?u ztn{W)dsZ5Ns6{J1YSgBc1|VwHO0OEVYo!5*TDH=&Mr~VZ0HW5dGyuJiO4P!Y1|VwV zN&^tJa-{)?+PTsIL@izEX`{BTGyqX+R~mq*y(cX#k=(s5Ai4D^wbQ=p8BzK=cxoo;Z4oN&^tRMx_CW z-lNh0L@!e5k)t=MGyu`7R2qQjT`CPg^fHy6IeME)0}#DVr2*)DW1<(TGyu^XRT_Zk zl`0KD^iGuqAbP1vPaVBgr2&XutI_~O?^S64q8F?5*wLF+8i454D!q2}ZZ+<&D3 zh~BQ!07S1>X#jX}&;Ud)SZM&FH>@-O(JNLOfao174M6mgm7Y9$%SrO+6kKVXOkBs}T zGyu^%R~mrmr7I0U^wyOIAbRae0}#D;r2&Xuywc-GZ(eBtqF1l<`q8^r8i45KD-A&O z_LT-8di_cR(9dfI7EsLt1U67<00JwhGys7eR2qQ55-JTqU<;K7Ah3o?0}$9lr2z;m zqS62aHc@E+0;{Mr0D)ap8i2quDh)tj8tLsat+fsIrefWS&B4M1Qg zl?EWNlu82-*h-}V2&|>j00j0@X#fI?sWbqA%|zXv+<&D32<)cP00fp(X#fJ-sWbqA z^;8;w-j67-ph^P}*ifYb2&|~m00eeaX#fICsx$zBEmazTz?v!zKwwXm1|YDgN&^ts zRHXq3tg6xg1a?(v00PUZGys8ZRT_Z6x+)C-4;&hRz``mGKwx8)1|YDq8kiaGztR9K zdgY;&1|YDtN&^sBTcrUA?5)xO1Qu6m00NtFY_QS*1XfsS00KL#Gys7mRvLi77Ap-vV2zaqAh5@p^G9zSUTFXV zo2)bdfmK!-fWR&*4M1R-l?EWN%}N6hSZAdH;Q2!X5LjppOceKDX#fH%tuz3EomLuv zz)~v>Kwztt1|YE3N&^tsYo!4QEVj}B1U6e~00OJ6Gys9!RvLi7aw`o$V7rwDAh6y_ z1Hj9N1|YEDN&^tsaHRnVthmwu1a@3$00K*{Gys7uR~mr8nkx-JV9%8XAh7640}$AB zr2z=6y3zmyc3o)z0?V#60D)~+8i2sMD-A&Ja}`*4r2z5LkSr0SIiq(f|ZjUuggWyRS3=f#p{kfWY=E4M1T1l?EW@ z|8llExPWRNFt~wA0}xz6r2z=;pwa*Ymr!W{f?KFG0Kqj>8i3#)Dh)tz5tRlYxQR*w z5L`v20SNA*(f|aPQE32z+o&`E!F5y`fabG>`>!+r!HrZJfZ$3h4M1=wl?EWVlu82- z+)AYZ2(G2l00j3^X#j$YsWbq=&D7v%aQ~GCAh?@K0}xzJr2zh|5L{8E0SNA>(f|aPRA~T$TdFhw!8KJHfZ(1g4M1>Fl?EWVsY(M7Tveq3 z2=1!V00fs+X#j%Tsx$z>byXUG;J$cSjSDWU(f|ZER&zdfwaJwRAh@$i0}xzVr2$xd z`}lv~_$Tha(f|baR%rl&i>ovM!Oc|~fZ*yX4M1>rl?EWVyh;NQ++L*t7`b6`r2**u z(}D}EGyuU3RvLid3TtqNPiC;+;yb^2rj$Q00g&PX#j%jt~3DQQ?%&V5F}Qy}ANTL~;r{)8+`rF*`}g^9|2{A7-{;5u`#!jT z-w*fi`{Mq6f84+4f&2G-aQ~hc?%(sfsXb5Jzvqkl_q=ico+rPMf`x*Cdf8+k`_tD<}u$>3Ef9C`4-+6)icYfghohP_|=L_!Nd4v0R z{^0(dN2Be0!u>n1aR1IP+`sb-_wRhe{X6f5zKiWV9Bt<#?%#Qd`*(ig{+*||f9EUi z-+7Dscm8(mJjVSypK<@rYuvx{8~5)#$Nf9sasSTyuJ?Ov_W|zT{eb&-U*P`TAGm+_ zN!RWd+`sz<_wW9}{kxC4c0b|%-B-AO_ZRNpeTMsYzv2GfcSE1ab|2#Y-H*6`_a*M% z{fYZ`pW^=Aueg8rE$-j_i~DyUxxPSLG?%(~5`*)w?{@w4mfA@XY?tk3BdI0yY zKEVB}7jXaT2i(7U0{5@J!2PQ?aR2HL+`oDR_pd&|{i|1S|LPaqzj_AuufDMh*A`V0539>e{s&v5_hHQc}Y4fn5}!~Lu8 zaR2H(euL^i+`oDd_pd(0{i_#o|LRBFzj_k)ufD|nt2c4~>QCIidKCAsKE?g3S8@O9 zSKPmP7Wc2d#r>;yasTSyuGPc1fAul$U%ia`S3l$a)zi3t^)>Eay^Z@H+`oPl_pd+2{p(k8|N2+lzkU|?ufN6p>vy}>|Kk4j!(Ho- zasT>d+`s-A_phJE{p+uB|N3p*zy2HduOG+#>(6oj`gPpD{vG$PpU3^{?{WY7{h=RI z!vk>t@B!REya4wPKfwLN6LA0V1>8Tp0rwAo!2QD`aR2a$uHhB9fA|INAD)5xhi~Bi z;T^bt_y_JE9)kOakKq2{CAfe13GN@Bg8PTB;Qrw)xPSNy?jIh5`-jiq{^2#afA|gV zAD)BzhwtG2;XPf$e{lcsAlyHE2=@;!!u`XKaR2Zm+&_E?_YZHv{llMd|L`c>KYR-J z53j=g!>@4v@GRUvd<*vv?;835H#`jY4gf5iR6BXR%mN!&lY688_k#QnoFasTj5+&{c?=zHAoP~1O!6!#A=#r?xiasTkt zuHmb-;jOrT_$%%o9*g^j&*J{!wYY!yE$$zli~EP~;{M^i{A_vd;{M^mxPSOC?jK%^ z`-dOn{^7~EfA}))AKr}nhdxPN%}(C4|~;kbYJ zIPM=_j{Aq7U?jJve`^Q(| z{_$71e|#41AHRkB$9LiWD-A&7!*KujG2B1C4EK*e!~NsaaR2x<+&{hz_m6+W{o~_s z|M)rFKfVt4kH5qHjRJ{R|o-^Kmodu#8P-uPhLKYkeZk1xjk$rb>JMJIQ-?jL`T`^V?w{_*>`e|&%K{TG`a zApe^`)AR!Qcm0f}C&-`ecQn00{%)V4=@Ig?`HW4kke}UmXnKbHZoZ@M>N_|6Lp}@7 zr0FB_S$SqnKatPUGi~~ceAb?M(_iGf@J^aOBj1&G*7O_sF1^#H@4)@jd&ok_HPG}R zxi+kkrWeVzV+}PuNvdha?k#()>1}fF*@I1wlY7%1ZF-&DyY_I?^W@&P$D7`#HvLbY180}QbcQ-hovBS=-t=9#e|oRl^j~=w zxD%Q_Ebj_;hP%TZ()46`x42`P-YoAPcTm%#<=y0tYI?Q2yWC+-&z5(aJFe;7aQ}G+ zx(nTjO&^zcr90Ez=?-mry1ZN6u}yE6cdt9R>GASzc1Jh8Uf$jA@TTX>yWJh%^nQF) zvj%8-z^o0_2u&}TwSyX>=?Sy8P-8T`Vb&gMkfuk>+C+__R#CGw{bJTKYMQ2R#QoDd z4s#`%9x`hqHB!?{X6>YgYI@47t<+deZ<)218m#Ftvo=$sHN9rmZfdxu=gitpjo0*^ zS^KF0n;tZ4Lp5U4i)QVphEz+cDVx4DYfUw0)1Tu0vnFl&)T~w2tZG*^Y}2!5ZL7v@ zde_?LXf!=+*2Ze&rkBmySqB+OV)MGZidG?-q(56Sv-c*m;^y=BW>S6V= zdfKLM&t6y0+w||*3ujOKo<2T%Wj%A#&*T2Hr*8WC?6vjWO@E)gxSqV}^Rrjivp4;I z_VRlArtio7)B6womfJi)VgoROHZPFa0Suwd6C}0(V`%dRi9Ns|+B`yH6EKQ4uaMXU z45Q66;QkZifOWt;`dpYc50TgijHJy=Bz6KrY4a3`t-x5?yhUO!Fqk%vk=P83rp;?4 zb_2s{^BjrozHV;!_V=yvU8O*HB&m@)xQ)}}ziM7Gp+WbvoaWJ_y zpOaV}%&yJvB$fx$Yx6yc^}+nw{7+(mFu^t-lvp9mu+0x8mIza9^F@g@!W`TDQDTuW z$u^&qSS8G|%`YXE3Dbma!Z_Q!Q(~VmP*^BTw9Q8)Rtht1^HYhX!c^OQRbs6$SJ*2I zw#{QDHVdO|^ID1B!f@L>S7N&`-Zt-**e?vY&4VR23?pvyVu>BYklQ?2V#_dQSToGI z&7a}^6O)Eb!>HT5T4L8Q>^9Gq*fxy2&ASbAj@mq2V&gFKHZPahISjqc(a?CRcz{w5b z2yult!!|#hTp~`f%@-%vh;wZ7$H_(FB-?y)a+NsCHou%)CQh@>H{<@zJIicK4z$ff zCpU^CZS&H}o#Ig2JauxbIMz0Ao!l!9w#{QFH;bcf^V-SX;&9tMcXGQp-Zt-@+%FEe z&4VX5j3aLI;>jK3ka5X49~LM>d9T>u-iO)a@#oWHt(L? zHx9hb!zVY6BX9Ha$(`fSap^eqHea7y`z^t_t-)LGX%GDV=0}j)gbhLi5T7?S z3(dbEwG1=>&EFuk4m1G4{ig$#`6HxOf(D@ZC#06b^Q5hy0cd^;slA{9XnqW- z&3Ga-0P((3v(fw;Qp-UD(EJ@z>p=q$+<$67XhCQInm z2B7(Er1pjep!sp6HirhF`E{grhXx?_b832;zej3)XaM^ByXFUy+8`Q$<`0GfYIYT0N2XxrRxv~Dy2 zea>L>!%1zN`;k_T2B7)pq?V2bp!w^h){X|C`R}9_j|PA?&;3lRM*~2+=l-VUqXB6C zKB@Ji0qAp8XaQ*enmiZlStzbLhg zGyu)tD7B6>0L}j>wU9Ib%^yjr52V3fHqcr-2AdqJ4*x5{IpVAO9Mb_tKO!) zr2%MuT&c~a0cd_*sokXkXntO)?WF-|eqX8mr2%MuV5tqJ0cd_^`&sd1)trU9UR*8k8#>xXEgX#kpET56|h z0Ggkg{wg)r&2KHW*E9gpkEJHN`Lm@~n+Blyx22Yw2B7)7rPiAUp!vV07Mup4`NO4F zoCYAc|J0DvlG6Y*f4S6}(*QL8xzwW505pHP)T+|}H2=EPveN)Gf4kJW(*X22p|tS& zVcK{a09tt(faafqQvk^1^W+mVyW+&h$W+`X@n!h5vC1)<0|6Imq7(3{6BLR2p(uQhz7u{5WKMYhrTyU z6dHi$FPgJPGyu(iG-r`$0GdB(&MMIWH2>0^WugIS{-!zWL<7+0-kOD?0cifHIV(j2 zV0H?A8r;7OfSj$O0WfPt17P-w2EZ&9Jl1R$4S-oKcy04<%~>uQfadR-vtBd+ecrBF zFdBg751X@MGyu&%HfPCb0GhvS&YIBxH2+z6bfE!g{a11JL|!bJmRp zpwIa=3kMH38%G1s{Bm=4js_s`^qi?{{<`q?oVjcMyE%(T1JL|=b5@TAp!xUaEFTR( z^Y_hJKN^7M|C_UbGyu&XIA;ZE0GfX=J|Slco4;_*8qxqX|KXfPqycFD#5t=-0}%X0 z&M=x~#AldoqyaGNi0|lgjm<*R05pH(oRy>jX#UALOGyLJ{FQUok_MppFXt>K4M1@J zIiqP-lLo--CjO@RIpcS7#aYZg0IS%)#hKFv#c}#&EGm_U1s7(g2u^#gCblr2%OE**Qx~ z0}%XL&e(n_W^M6pW^ZW#g8R>zT(h|}0A_XZb!K;I0D}83_&l?{GyrCO@qNwzJ7Gs2ag}l8F91X_+qo;Gyu&{K4;5m0L+@>o6Vln05m`PoK2?zFsqKQ zHoHy((ERLkww(sRtUJED`QPU(JU+bnQ5^JT<0Pv1T4~cg(Pa?e~=u2X)6&irx{tNv{ti?hDz?*^wAl7Q3 zSK(bj0}yMu(6jKipaF=rUT6UN9Clt9GyuFY=wo896dC~D8T2!}G-v>LYtYy5+Mog8 zy+MD&i-QJ$HwS%A?A1a8z`KKfhnEKp0B;Za9$p_b0Db;@oCSp*h&KogK%5nYUWj)H z4M3bFg`SAF2n_(Q5qcxuBQyYU7NsXiaQ}q{fL93(0Phm|C0-^p0CBbz`X*i{GyuF$ z=%09@&;am8p^xH~LIc1%g?@^c3Jm~n6&ipzYYV+qoV|qxAkN}Kj}>Qgp#k94La)WU zg$5wb@7yM}&^mkkX7ZyWkHUN(JNn+Mxkx`8(;wLj%B@hdz&24-EkC9{N3AJ~RNledzmm{m=mPxv9K>XaINv z(FgJhq550V~ zi#|4L97!3gLF#2I$Vl)7}#psK9jnM$`9-}|zMMeX_ zn~Xl0R~Zce?=t%3=w%8G0BC6ck_Cq0ciPe=>(8EV>TJqc<-! z0MV|?mGyuFXX#jX*21bVaFM*kvpD8o|fu*IVCT~p|0A8Es zZFq0e0Px~8kHedj27p(mc^%%JGyuFj&GQ7dS7-oueVX^-{Z9kH3)DPNV1tDQfLEw_ zA>N@h0K7!a6Y&~-vz={hE0Pk4yW4vT(0C>xqFAJ=> z&;anBr2*hYO9Q~0mIi=VEe!zgTJvkXY-s?3`!D9(c-_(fwEWxj!leP=jcY!RS1t_z z?_Be9ymV;*c91qS1}C$ z?_%?dyo_l8g4-zO8+jem0L1)%dLZ*crU3|Uq?nK7l}rP`JK6jsFJ&5l;QrHNIk=WW z1HgOP{AF-4g$5wFne=E5uBMpR7#XKo*X&L}t(=-6Qr)dCqQJY8QO-%#9tJ=J3a94!}fS0v-R^HY$ z0KBeg0D}8U5A5Lni+R}K#!Ak|uJ)d1c5r8f27s6L_hO!Q_3hvD*ygou-j??^4M1>l z#XK%=ZW@5#{)>6t;O+_y055Ozyu7_>07h=e3;^7JdVmKPn4aLg!OaKr3a0_!9Zmxf z+JH$NR*YM}uLZnc=N4z9J(00j46%wO|jrvV7=znISs zuC~ws1ovOeZ}W1e0pRU!zB{;H835+L(*vFtJPkl_|HXWGaK(iNAh`cxemuDULIV)o za-jhT?!TBf5AM0p00j46%%cZ4U1$J;t4`1Q;QovG_29A#4FGR@^X7gIof1v@`AiVWy0D}83=Iw)fPY?c>$1kY?2ycG#`N7o} z8i1JJPY?g#@(T?>aQo@;&+DHC;N6i~W_fpHrTAyh_~)GX=eP0Co3p$#viz*?jO;S& z+aqVr`qs$p@y~0szB#hgY;TP0Fx&q|PMIwz{@MOJ^73r2jVwOsRSv(Fs4 zVfL3s{yqB(|Bt2ffTyzm|NmVX2_Y+@5)macD=TFrGc%ICclJ2vI_KCUvyk18nVHg% zO46`WiAY6+gj6z8|M&a*`#{t`LPxB}5NX0rB6K zTtaS3HsQJ@oygsiLOk1&K&)+{5t7Vg!k#&T$Yc&7+L;50U(DWw7>he`ip7aYVX-4x zS*(e97BfPK)sQe_)g$6qj}o_7)re_UC1S@`S;BCuBtdKyBO0~}5#w8T5Zr9sgf1H! z5y8epRI_a&-m|Tfx3VvhHQ5))XW6I8SJ}tO1MDN@%^YvY${f99Z;q$rB94dTUXDBD z4cnT?vfHZ3F59k>bG8+cpKiNAUfGsL-p?6Nw&NtoX`Er?2b})oMNW6JFqb{qg3F4W zz-3Hs;nF3~aA}Zta4V7xxet;FZc%bQw;*|pn~TiJ!$Q{P*+dTIStV8Qd?yX@Op&(m zejusx4v>6#yGbRy?W8{5JEV=<>q&Ck%SkTVi%2=!&yza0CzF=9Q%Dkgp(I;AA5tox z6RDNYnl#U6MB2@Nlw``UOrr5ik(&5LNT2!nNIW~(NV+@dNZ~tHqAPdIMZeoI9?dK; z7_BPM9qlXdD7skSR&=jGb@YFNrO`5i=cAnjlcKW)Nzso51EYTlx<&8ZX%lU^(OU>+TOx>bv`+{C0OlmF&J9)wjDQ z>OY~9C>f!wC`X~#s4Stds7FFxQ9p$2qJ;MtN15-@ii+JMA9Z7oXw<|Wz9?>C<|u99 z^~g}+`N(U+pCSi@Uqv#CbVMqO+>CS=sff%K$&c(5Ns0U|LWAVi_%9{h%QA8ihhY;6dR0C6nh%sE_OR2SFAFkQ|w~Il2~$t z=)TAZ%Y9xE@%wBdn)m5POzcyM;1-vNI3~^)5iHIWaYcM3{FV4r_(qAra9N4Ya7T%o z;h7TG!XHRn2%ndT4d1mtDBNhjQ#fhAY54X1n&Bh+4~8=z5DZs2z!L6xU^Oi7z;xKt z18>8AALs}ZmAnyVA$d70Rx%^3Ns=5kCg~H#anL4A33tsVRu zDlYXk)LLpNG(qY~XtPvP=x3?YP)_Nz&?C}Op#jn!p~ceXq21C)Lf51ZhDyln2(^}B z42_rh8PY8CF=Sk(D}+P#c8I2IS%{x(W=NqdDdf4VXUMXwMTn@}kq~n^$qwQnU~9S3Dk6s3;foTv0ISw<2SZh|>47 zrb@$S$x0n(tCi}`4l3oHWl*M_l~wjWYp-l^HdR^u>}_SSvy;jkXE{|?12t8~1ASDw z0xzmG2R>0L4qQ};58QRwKhWT?bzu16BY|ay#RFd+-WIricr`#mbu7SA^+iC8YEwX+ zYC*uTYD@s5ns>;Hu>tU_W?LpQ5?Ov(>&b?p1)qPFB#9ibB&E4RHi+jik z9rxlB;_gpQFuTv6_~yoI(CemQ(BS4_knNUX5aQNiVCDA7K-rDSkl#(l@Q>>$!}qRK z!#3AS!&29mhBVg|LuXeZBW+hbBT?4?BSzOeqbZj*qh~H(jH+DNj8j|`jD1|r7#q68 z8B4m<7;klXZ9MP1X58z%$E4o*xJia{fJvZpu8FC0n~99`gb9Z;i|L}1oN2$4jcKD3 z)ileg!ZgsS$JEs6m#K`Cz)21#t&`s!Jx}&Irk|{LY(AOpIC9e8aif`$<32MFI*`rj9Il#=+dnsdWIu0SYR_#!*sEBa zv3IagwU4vlx39KXIn!tH_RKGf<}>`3*=IB@1JAfxnw&|tlsr>s$$aLu<+R<3Wv88> zRhgZZRg9gxm4jWXmAYNM)egHiRx77htOic+w7zj#%R2M4yS3lx6zdbG>#W63zqV#L zy=*;hD{$(8t>&pBTbEN2wuz@KZEH@++4h}cxBYQy)`r*SnayFFGMh6tH2CKX{OK_K z4X@3t%@6pBKKRNS_>M&QP8awIn(&hZPL10x!%uznP3t3T@y0#CvSp2$9U zG8@hO;VGrV)2fH3)(21TyQ3C7Nr96x@KjCV=?216&Vr}i2v5Bqp8lc}izx@}1{v5D zrm#B#VV7jUZmEY|(+j(2-uX4`q#D>!aj>(_zz$P@oyKNd1-tGU?7k_NJlKf=up{+g zX9^iP!!D)4ZY_mf+XlP$J?!E?t}?KrnGBU-cU!?O4}smD4ZFSpc7HFNf^Tl~a3Y?- z$tZ>s5&|d108Wg^i4r(Ht#FFo!D;&KPKA?Y4JS+rP8x&051hIrIDOaP6t=@@{0OIV z-Gl8oADmJJIIU)IYW?B#rot(%fYbaKPW2}^-RqwDaMA755OAAbyS1@hnyvtznM8X6zfl0LY*eRGw z!7!cDVM%Ims z8HJ8W!<5vAY3U48lLXT<2c~EpOw(sDRmWhuuKDG|r1gV|dlV)wuZBHL;V_uS88DSA zVLCsADg6$n^`if0nA|Ne!Bb(9JHSMjgUQaQ76Vhh0H%EtO#K%y{l`EBRs+^S5nh5a zlz~EogHjlPV(dB`59(12D$)#U(gmtA4(hTR$f?2sY9j`!qYmn00V?DTYD5E7$^&(( z1C{CkwHgN1`hHeKi4jyx5Y$W#RP8vZn?0yp2&i2$s9q_kUo)uS3sA$4po&XDbPCL% zlDk1I4}ogxgL>M7iUxz4CV{FJgSs|?%65X<4uk401doCO*Mkz%K#|QsnMLI+K&3rF ztx2HTnV{ZfpyIbd&AUL=KZ3gd42cJ&w+6+RkU0qIe*`GN9B9A;s2~dHAPp#?6lkFd zsNo6F!w^u!SD=Z%p=&@ET|gK`KpK8P92!6#90z@XLdZZP89*hMflh7!rE~zTyaj5R z26|Zy^8}Jn0it0(a1iK56DY?NXvYbtCkW^#7AWWf(9kuYqMJZRoj^&0Kuc3VO)KG7 zfS`hbq>cemaf_<}UFid5*#K>M0d++JeI)~hT?87d1S-1?boLY|Z4hYf3sBoqLJ5pu`TK#aBR$pMW0cfg;x< zwSg$Ph53LkMS(Kqfi|^(I*oxo?SMkPfJVcBN@Iaevw%`dfL3dOT5kirb^yip1I>N_ zs{IOdyBt*mq#Fgqs}JPMw@Vx-SOI8Q3#ix#=-37**$rqp5U801^qd3~eI97K6sWoy z==v5=_9LL}ZlLZ#pzm>@@HwFImFRFFb6p^Go*jHZ>moqyQb6y@K=DU`=8b^rt%2^H zfbxBS_CtaCDM0_p-~!Hr8z=%-P!8^(9$dm5a0~6=8oI$f41kOH0B&LmT*Y^A7ptUD za2nd+I5>H@z5Sb=-72N&ZGZpI&6O&GWv0$ff! zxScd`Jr}_J6oCu63T~(xTu~FaqdVY|9)eqX3a+Ua+|wIyQ6u1{#=%uhgS%P)m$d|L zYn}WaoL4nCun2Hsy5PvT*>-?C69She25wCfT$?PoHzja!YT)LMf~(U5cV`GL&kWq2 zHMl-IaDPtV0^Pw4dV?zr0CyMyE-?b!A{ksG4cub_xX2W6lj-0pv%y{Fg3Bxbw^;(N z^9s1na&Vzl;6`h~l{SDoZ3dUx0&evlxYjmsuaCgRc7U6G3a<7AxZ56ZxqaYvUxDi# z0QWlxF8Cd|;rHN*KY%;_1TJ|T-0}pt<}cu$r@=*k1vmW-T=g8d>jiMxi{Q3@fb0GV z?t2Mb_-}CI%izjaz@4vxOJ4)G{(r7L3mm*XIC*sQYyaQfqsvFPkFFoxfA_zCL;<`! z;iUjCI(YT}{Y#X>%lGd(aro~af(c%4*Vl-v>#M}s^%X*MeVN$0{+k&7vqV(>`ALNR z`9Wy^StPdoSs*^H%@MV0--zh7uf*}SX@Ym{3o)@eK{Tz76O`3Ygwg5;LSXehF|+cH zXjvH~;#LL-vz1qb&`KXMzuZH#F25j>m!A^W%N>O1@+0Es?>6Gm?|VeX?-s)DcQdj7 zcLTAqR7-R&RS_4K$_eMCD}>Ba3Gwe&0nzmO?doDClr3A5Olv1i2k26qVy-3 z@cS7-sQwHgw)_kr27h=H*M7JY!9Sb`tsiy-`wwekbkU5cSu`Xf7xf6e#iInzq8jn} zyAsj(U6!DHmn4k7ixC3fg@~Dj9Yo6lHxa+UMwl-!5qlOk5#Q(6$!+sX_T^51WF$lc$X$OYf3$)4Y?k`=!dkr}>SAithX zBVV44CkM_FWR2M{GV82AdE~1*x$3JuIsB^?S@)|knft3Q`SXkhxp793Oqn@IHl7hB z3(g3VXQ#Qyccxj$NzK#!&Em(YO0;I{^bs->q|YU z;7d8l^Ggv)>C1T%SQP>XwrwIHR(iRpR^`@m@p#MP8=nXCX`7A6H=rd z6C$MP&wQko&upZG&vYcq&nwY;KhH(~93PKvA0Ld)8t;yF9DfuoJ$@_t-&l2Y&sb@6 z(b)NDpRuIq!(*iAEn|Vv?>@OjSAMdI4*z5nt@}wUn&*>3^yEkJ=;n`t(Xk&nqRl?i zM+<*kj#~WiHR|Dq4^f#P`lB2^bVNygxE=Lxv?i)&v?Qu{G%Lz?G&V|YG%Si`)GKP_ zy~8R3h%Gr}B|G_oFfYGgiAeB@K)^6;z3r^6kQdBZm& zJ%%eHm4@>pHxH*ozI{iEEPv-08TQUTQum!nB=0+|$S*^3k++6KA`^zVBdvz$BgKZ6 zB9;fgL_8fFjK~{&8sRZ`J3?u&GJHxZ zAQ6!=z!!0PfGOg@z)JY~o2l^bH-q8DZ#u*M-rNk=cyleB{mq5&kFR6H8(s&6(_TA; zpL}f^F8o?E{O7BK;T^98!*gD-guB054O4tI9k%(^+pwYjj z$zgLZeZn5Rv@=%!EOW`oOm+WB!eSbsC`@V*T_YH;W_dN;S(bp6@+gloX zzc(#3y*DbBYGG^^?QDX2=sgmnd|NfY3sfnlG$Ar z;@q7Xa;TdW!r1K@GSp=eQr&eVgw!P&V%)_SBGg3}^5exqaL0?`;M^CT!JaP~gAczb z4rYCk6#VgdaB$;u`{3B;`oUJu4+V=q-yOX6j5)aH*-}vHvyVYR&t3#+KWh%!{;V|U z>(k_*)~6vs8BgtloSz;KI`mX7X!BFSpy5u&pxVywXQ`dTXU#i1&Wd%`on3j7ceeWp z?QH22@3TQqEY9jYQ9sM~MC|Nr2M2uMb~P}&V?5BUqbpFkqdAbZqd4&6YEoqz7bhyFefEB!SeX83bG4D+9QVDEqLfsTLX14)0^2VDLt z57zv)J{a>GYkTH*tF6v2wJpcbp^fBssLk1rsZHMx{$IrWn(p)ZCEj26wYxv=D|7$3 zFT?$M-{ICA-}=^Q-?&yMUz=7vU#V6}U;0)~-*@*`eCqCv`o!LQ>|=AU(nsoEx)0sG zV4rt)Px;i{)$obCE8=5wm&r%^?wmLM-B;ejcUrs~?i6|_+@X4(zT@UCdq>}U^BpPg z(c7HfH*PO`CEp(La=87_OW}5z7t8G=ukjXNuiGuAUg<4|yj)xOyi{A(J-4-d@|?c) z*t6|cg=fyKR8OB<{+>r~nR)WvQt({3$>-U5bKRr(=0}f^o9!MaZeH`)b2G_frP;@$ zui4n6yjj+R+|2D^+5FpGviY4mU307Z@Qo7prW-W(dk zuD2SrUDF#xUELcPT{Rn~T(&nnb6Kdba(Pyt;&Q3p$0f4f(8a7?(q(`BRu{VZdFS_a zz0No5>YdZ;GMqi?0-ZJMOr81bWSoE0ayWO@E;^Of_B)Yl8=b6bvz%mV1D&?inmUbN zmvL&n&f%1E{kvnp^*%@a>-CPp*V7%>Yy2JG))+Z9)JQre*RVRe)XX}l*Sv7pUQ^|; zSe@k1Rqf$WUajjutrm5#t)_E0R6TCbUj4{^rmEDwql&OEsXAjHS*2=kUd3-ORkdWUv{^$xvXWSbXm}f=kki>&r7c@`!Cg5)?G@rOuOW2>2pcb zQvVXa<-SY5EEq2JSxl5xTeO$PSzIc0u%MKxSlE|xTd0-Jn+udaH(x8cYCcp#Hg74h zHqR}QGY>6cHMc1FVkTem(2TRBz-+NN#H_#A$gH7wpIJunMzet8k(0*7%_pUb(@$VXldP zVStHo;c*k`!aXMJg=@y&3tk)d7t|Ox7Q`867o0H;E>JMGC}1;IDEMN;ThL~-oS$bj zlpkPpCtuH~Fki@sl)qwVpa0TOGr!VsPd?RfQ~oK#iHkCZPcAYUR$TmKkbJSlz~^Fy zfzd?|1L=zz2HP(38vM+gKQWN^(}3$SE)af zOV#hrwbrlCmD117WzY}JeSiE^?v3NBxyi?Ovz$r2nw)!j89CW{ zK{=j!Rymq_hjV!JcIJH3-I&v^J9!~r_xXhY-P#K}x>*+lbVD!v(6PDjOh^4fiH`7v z5FN$~Cv;}d3+eQo|E=A8zFYg^`77Gw^Woag=Z&;=&x>duIKO&~<9zS2rR=g}!`YF? z9%P#wyOzE8SW5QV(SYo}qn6oaM-OL59TmzpIm(c|_vmcas#bqipVqCcGOePlNUfMG zV=d1t5iR4al_Q6;dX5NWT|TlgE9}TrrooZkOrayqnM<05na?$8nI)Q@nL(N+nR=QE znSz>vncp?&GCMTBX5?%1XZUH{&N!-3n!&4)nDJHJKch|EG9z1EJ;OtNZ-%NmYX-ae zuk_DqBk3(_kJD4tYSJCl&Zo<%MW-{Wxug%P8l=~$%BRPu3Z`4C(x*$PeoI?FJdpPC z@cp#1!{uq=hcnU)4o9TzI_#LXsG^_tL`5#`qKZJ8j|zR7rpnwoPL;uPlgbaz-BzwT zm#TdJoV_yXoUF3@IR<5ubAw7M=c<)N&XJY2o-dCErKIdS z6q>Rq@0jvf-Y_LcUMa;xUL-|Do-Kt%el2-aZZf%Eu0NS3cR$%&t}0nnE+=_emX`cn z)-SnG)+X6cRwr3gRxX)Cc31Ma40Cd`%yLq^%;zL)nU_ftGWV0#q^py)`XmqJu4oeh14EH4bJc zavY>4j!F6_Hc8qg#!8+@w2)Lu6qVeU`1=4);?o24iFpTpBzPVeOHeuRGJ*L(Tf)fx z+Jx)-ixNotQxlB#M1` zi@%9KCf*UxE#4eIv9Bz?dEbTj_^{#&wEV z#pQ||k8>AMiBl9g5XUI8Gj2ebJ?@(D#<)=7pRwA)ld;^wL$MQkUc}zm(;6GQr#{wv z&*fO*Jr`ns2qnfo5{in=67r386mp1_5i*PYPe>=WZ?{Tp$!^J5zumiI)pv8nvhHS# z9oe-SQ?qL>CTiDMjQ*~H7`|Q4Vy1Vt#U%Rkd5&b5Q|Y25Qt$G;D~v*gCVAJ#~Lks#{x}v$0Uts z$1v?Pe;=)h{|Sx8e~)I$-$2{VUrw9nE26dXWz$mml4!Pk1Wf{hqvh@1w9f5Lw4CkM zG?(qhG`a2Cw2j+UX??u1v=Ux%nlJBenkp|ZZ42*K+7J&tt%BzdHI(NERh#E4m6KtRjt>=D8CAgnb4Y?mscW}2*XSnLAEnF4U1g=u51y>$bm@9+2$eBoez)7K|aYj(> zI0LEsIlZVW+nlIRx7kv2wwY61wi!@mw`o&1Y*VN9awt-ZIHalG91>Jz4q@tM4gu-_ zI}i0LI~(;ZI}=rteIs=%`ya}Cwk1k6+X5wmZHA)D_L;)XHcA=aI!I~Q+D{?2c2f+u zc2ah1eMFgNy+^sldW#ar+DI{Dt)U39mQ&_gE>l`riYO^8d6ZKu=P6<=>6Bm0$&_~H zcuFQSm156KqDV4_Q`WWwQ=V-JpyY1xp}21GpvY};q5QYSfzrctno`JQP4Qx~peQk! zQW%(wD6co`Q!a1TrTA|?N>SUaNnzfsMj2vMp_DT!QbHKzDO!v&6m~`_$|%DDN)3ZJ zC6YmmqRX(C!p*RUGETpn(m=nHLeL9P4CwhO{Pf!?Q*=C(n{-^17`kl~Q#uaHE;=^K zw@s{+JDXT2iJO=ymYbL;BAYf-zHeltv~6UdoZCoGvE4{V*|%{MWog4E%Hs_iDOnpf zQ0(C)x#2&`8hq6M8N71fXgF@%_7r zau{Arf9WW1*Xb!&*BK~h*BL3A>zgTC*O@58f0!wie^@ACe^@Enf7mG7{%}w}u5F{# zu5nSK*LWz$*S1r5*Z3(Ds{)j!)twZ|>TZhB>K=-~>R!ssiWsG3MVu11a)4sCB1I8e zk)g~l%TrpH6)DNfDirHwHHzr6Cgtbvqm)O#btxIY^(l70jVSwnn^IPmEGV5z)|3lN zrzy@$4iuRs7s|h19+a+MK9u}l0Thp4!4!pG;S{=GBuf8JDy8&iJjL&4GDY=gI%Uhx z^OV6Kd6a8EiYUQ9E>pCAlvCJ$)KEqj8!0u5wd4npYSq^YYWUZBs_xeoD)-k1)Xy_dsf{x)sg#)^s`1PiRdD7jb$0p( z_0IGkYSJ`4&1!lpO>~-<_G@Z4t$j+ImNg|ybC^=4Nlj_f*1s6jy1rP`3cfheJimC; zl)i+}7{3s-H8z*n3$wZe_o)q zd|sm^d}fHT{LB%v_p?CE&vCJs_Ho&mtZ}s%$8o(F>2dRze`EGBJ!9T6MPs2cK4Y|) z!((YNTgEQNy!%uZQ~9YOCj3)tjP9prF+86JVkSS1#Wa7Mi;4ZX8e{g6F;@5^SM1`4 z-LVfpNXBM

    FT;pc5 zxXr_~xVP^z;b>ck+E#s92-Qt-BL*j?t#>H2@y$~Pqwk%%%ZF4;T+m85|fj9AY2PWfF2A1Ma z4=^Mg7~oAm zCj5LgmeBF)M?%gk`b76vJc)|0_9bq9rII+*e^d$}QLppPr5yiYVKyiYkvzt13PN1uJtY;R!F{odH5^xoVg z$KL8B+1~p}biFT=-t>GFQ9D)6nRl9;6YF$8xAKH^uKUUPbEQwJ&ILVr zcuwcZ;5oi0bLVC|=+oLd1k$oQE zZ6=ww+B`E;+h~~%ZH1YK+L|+&+Illb?@whm-QSp%cwZpP?*5@Hnfu0B4EH^=hFfE@ z>RXGl;#zNI*|hd&Nwv;q(YG>Wzq==tU3c$rcI-XNY@2%l*;4mXvgz(!%YJwFL3Z8U z;q17(OW8JeInGPpJ#e1>uI~BaJI?1D?vT$X+_`xE^quDOvUmE3bDm}M-aN@>tvtGBhrHn%q`amZ1$oIgZs$4P7|2t;@iUM8#fDm9 z>Xwr7>Y);9^;(H-wLs~iYPC}KYWvceDoSZb)uqyss`k>zs)wD_0oH1+I=?)41Ap&FN~vwfL)H*D9}? zUF*6kb#4AC%QeojsWOGK$7MEUm&!=+&n5WNWB8k?GR`s<_zEfbN;CM5F!;^__z7+B zlg6(JTxEoxydU1d1l}na-Z2l}xfQP9Q@J=?4Z{@)xH4n7!XUWPJh>1{1;g(o?F zy$7CZEj-;cc*?%;v<=~@OTyDW zc2p$ntV^)Np21FAsJDP!rvST;x4<2CVmj=|Td*@n8wz2Ul3=&m!>-kY-Ma^N@uvJ9 z*wIUkPhfXfz%EaQ-R=Xs-UxQTG@OEM7un%ND8tEcgcFhsC#4Ba%@xx==WMr{EN-!fD(Er*dQN!p%uIrO)8B*1)OFfYTcUr`QTk z^IU@EA?bP$Fq!FXZx_AE?|KA0ZOFhwrH zG$F%Oafa!l3sdF*OdF2#HZXbOU;@>_BzkxE8cd}Wm`(vOr7U4u9fqkT1k;Nln;s^a z6ihT5m~3${;p$=14Yzv2)H8fs0~q7P~! z2dW|f>O!A3+c5`fGYG2l5Y(p%ROmdY5eZbu9n{GLR7wTZN(5AE>$&01Wl*s(P_r&j zwVR-BrJ!=jpmrgkdiJ1x`k;dHpoY6Z6`4}kp8W)s`~YhC98|Lz)Uy;+GzHW&6jap_ z)YTAFRteNr1XPzTMF@w~K%fMBpalb<24$cJQJ@GepotAhbU+qzKp0Ly z8ks;G4}d)8US>hU&?%sz<3LABKuKaiOT0i$3<;-!pi+RO?gCNG40HfpH3Map0c~9X z>WTyU3IPgp0~)ggD$@ZvQv^yA16tb-)W#HV1q7D>BzFsl?#oaY&|ND~ULDY0DNtV~ z&>sybFc@gi6{ye(=10+XfzS1Gz#d{7bw*MXw?j;RR`!*1t?Y$Xm&SHEf>%&W2_mFZY&UQGm!7(#{r<= zXF$WPK*bF}$7Mjt7lD@3fSPGQ&!Irk-aym#K-K0z*LpzNYCzkvK;2?M-vU7496;j? zF$qBCEkNkgpC^IVhk@GrfZm?~#oq&(Zvd(<2f8l;%FhPcPXg*Efc`_k1$cuSZ~|9g z4er1gT!J>Z1yyhjvfv)X!A0x_H^B?8Vk@`{dRh`VjXU5tW~aY``xpZkG6ZhqCAgBO z;7%TZOKAbOQV*`B0^Ca}xR^X}Ga2A&62aY2z~w}M+X)2M;|1==30#mZxFK_JMF!xG zw815*gIiJr*CY+@NdjDyFt{lJa8*3uuGqk3F@f9KNZkX@%N!h7JUFoyaAY$JpTV7t zf=e3&x7H7?tsC51C%Cvr;O6dutGfm6t`S^b4Y<8>aDA7-{S|==%mX)g9$aBMxWi;{ ziSghTso)w(;2y)lMFxYL3;ZIWgFD^{E?EHF zGC#QH?cknyz(sR`o8AVlngiT58@Oy%aN8{4x|zX!Gl2`=3~rneTsZ@{b9!*;bl}$i z&$au4gD(Xqk8Yms|GRs1`RMl1_5Xve9}NB9ZOce_Blc2r09*{~8Pb67@Nf8(akb5}V%HZ?H*RCw2*DZOH!khxlv%cmvzs zKSa*ur42n6Ys9C|`!>EjyGpzjwcW@Yy+Q^I>(^L-;t2>zpn z5+a)hhkp_|UY47JXg`SQ%EV1(+>1oR)SXRX=NE`c(QlhR{hK2QmtAxjR^N!wOQv*j z1z(Bw_c3%2UQ82qd^hPdr@jzs=2LW=zfTaS)A;FmCdY~TP6K-H&QFB=e+2#J3m=FN ziVgI$M(>GAzj6BQzupnaSGgI^B@7bLL%Iwn;CC@XSR)xu2EHQvHES5IJnbVK&yF&v zv-A+huCOx-tHSSYywYMcvwlk4-w?vs>(D`HOO-R`SUe(%ZHE{u721f0@ywgI(A^`- z>(w^jYHcBOhx|7;IyV#f|6Shv=T`%fC;EEx`QTbY?o?PPIX1Oh??b*cNJ+52ouBH=ZhjX`xo=qXD zPCnc6V}Alc@3FRptDi>HMoBWKxR8mGbN0+O;}JwpQ6@8C6ha)TX=h$93m{&!{9=AR z?M)=Li?Pu0yA$qRr&!VzoQN~8QdmMX><1$JtTXX_Hrnz+#$c_*|05aXA?PmNOs$S`D(J! zMVD>XHCM@omO0!0SQL@{*q?6Wo4r7;>Rj2@;0M2#6t$nT<9$3CKHJS{sZ5aThtoJ+ zsbS zz&OuGK43)Jp}w2{%*Uf7u|QM)S&A}gZz+vmVyhI1VEBM`xhMw_gFB-GJ^@oGesVS-g9+$eK z%`$uiCVU@7w`3Fxh=|>aZc6PH5bLgvR*n5n@Vk9!v|*TxAnn8X==ZKpg6~fxMNb%K z3(}R5qU{bn7F?bQjMm`!C3qJ;Z9-k#yVF?BCVJ;{%bhom8%47eCG1?((u&scZrMpE zt`Pl5etPHJns{{73g52AyMoc~xAk|Kd2mEif}?i5+&~}QCQ-9XI&nFQe`I7=z}nZS z)I`?Z=WXHl_@vc$7gzL0UFi4Qoj%qPB@j@u+l%RTRKe!H-7w8 zk`u29*Pi+m8Q(P^tgQy0bYW%``O4Z6xq4Jl$A}`JV7O|x#McT3K+nem-7kNh5dhcMpePoe*;$EE@lgMqFEqe#qwIZ9fr}n0c z$VF1Mw~PAi6^VpThKq)Aaz_Tpg^OOFqmPUesu1P4wG>gtG$?w_=S#$suZ&{;Y=aTw zor+?R$!mEX0$DJ3Y}I?iZ+8^tM{x0kg4u(N5n(6;OQ_sMC7`x}ky zPgyt^z7oTHz@yf?zuR4gR*j$96NR*scav(5w1wkfBK$6G z%B;r0o;BUDtWLj!wKori1r!t=l(ZKP+v(AD@We0nu=A2@2e(H24ek0WE)_QOHMI4z zwN&Eqp-`uj2~s*aPeL14;d4Ildp_3+K1=m4mxd}G;*>7inilHNc|=-zTU03T$pGol zO&*~ZZ;GWO#>_*xOuMC3>yCsPcC1Oadmap3mXVO**tR2-HP>23tb#E#;b*+emIFUS z?DU&uT8lo0B;}3EXsvgJZ2G_)T+YWwG9+=8Ciih4Ur6j~y`1(dx{!p$QMqF8 zh2Z2d7Ww(_!@&v9RpeFNI)g*2Jmh1ZHU=Bha^$}Z&5xlCODXP zXxE{aMfSm#8HR_{ujvQdX+#}rEj$z~GFfrRgt|MpEOy|~su^?e5I>#51Fof@TNN@2 zSK2=Y9X@EUQ10*|=yY|eLf_ZsAkN))6!y552H8L#Tilf#B(cDyczjPtP~-_MMNv2V zAe~}=MWwvsL9tVXiZLy6LDCY>6`48(gEXCgEB3WB2GwVaC=J$rKO1`2RB2!0@Y%F? zWTgkj9cSkks+F$M*PYG&JE$~LnRoW=CI)3URodBvf3nJYt=?y!E!r!`9#5y93@nryci1zxMQg*#_=M+cuS0`h;~!JJCi!q2kr#{OliZa zf5T$}-aKSf8xQvmP@a`j3v@RN*w5;qR&(rdK)Fb&+C_HZfHK(@wZkvA1ng4$tdmX-J1k8 z^A_s-vI#xS!pa;!!NnlWY*UioO`8%;V#?Xi>h^O@S3iBfHP$7~5q;z@x z4qh}kvLk=px4t**2*=2{FaMv*N4Qv@`?~DxIU+7u@0+Nwa>QIU$Cq+UL@Q4v+E-i8 zSZh_x$+z!Fq!yV@&zE1OOiQd!(sw6MpVn$Jr|;{9RjoDo6`w;7_Z~giGwP$7U~)9q z^0Ch+t*E0aJ(WH?f0i8;IF#-)o8Na-BPG~JTXF4ZW#1_u;b(h~+0kqGkWEaEIf%pO zC%Pk#-Be}r$<`=4=A<#_tx?{4%uD8#w=v!7vA%6B-uEm;vvNlNXN%#*{jw2gpSLz5ic>15S>rl z54~=jD$$uTE%Q39`AmmIO7h|t_@Q$(&(~{mRzTPBimBJVMjhSTMTfkyeFJps6ZpK` z1oL(E9oIb%K5ExZmH6a2Y5Pq#a{RGp+zgN2_S6bbMn6qGACXi~mq|~(@EU*5T(fLF zEfF)%yykm)Jt+#FPArppyT|!F=d9R{t4XYTDC8*}7kB*VA=~YEd^(}sV{|F`IJNki zhaC5fWTv?r_8Odc5a{Br;U9A1ZKsZV`ljL& z8@GzPE2KU-ar79oyCl>6iA!GJ-25VW4R%p`-F|$~FlbL`aJ#AOVUR)2c56t;Fi3R` zaeM!)#o(^0m7Dy3pA7cUDZAB6Fd25-<##)AT*k1{`H$;g+f#C-bxJ1Xj$o*rN%;>YMJu9asb znl$Bdb*jxM@BA~DRoWLLBBRPhl!MLqLv)JE?ra6)wo^VXS(D}@t zT$5!tQ|Dcq+Du+o$~gP1PnbBr=Wy2i%3@lxVbSS)mz-%MPrsAXB^%QyfkvmRo>Ws7 z&MYU3y%naOtAS2_uX{{$`%RsuLw}hT705U}WDz(?vfyx$VhVH9()ShTQxm1?!n00vMq&JtpBX8VBv!Ng($G(UA%yb@0IyQedGP_03>iCc= z#7tUg)?r?v!0e{&3kN0nhi1kBRSvn*U(EgsO>&^$&1&A`mwFb9^&N;&V+Y=RwCe}0d zW10>Y-h`@s&Gk5opfP@X9oA}#mkKLqs_gqLlA_<9>A(8R;!;!dnU)cL%UvVcXRH`C zEg6;q&s2%HTH0+eIa4X0Y`O2Rnzkcztyo4E!ROoN1g(r5 z%IxUxX<5~C#n=@^xm#Vk<6w7NGSy1qq`IADf4!CK@D4j4&o@>|mMf=!FRobKcr8}dWX8ZwRNN4X^qSj>-vckr|%8aS$Ay_Kb^YuwRNKq!|6(; zWovhdaoepH0;d*49@yS+);wj#QDmFz;&LiyKEk%aD)Cfno2Bi#YR#!0s+?^wSKq1L zL+rNOMt_`oJUnaDcahiTM$j{xD&502SJ%sI^1qz1$&aA@-wXbXe~14LzXrb+zX!h; ze+K?6{F(T(@jdXp@ICRp@fz@2@S5=2@EY-2@tX14@gDGA@SgDA@E-AA@t*PCaSd=S za7}P+aE)-SaLsV-a1C)SaZPb;agA}Uam{h<@fqN=z-NNb2A>f=D|}}7?C=@lv&3hL z&laCCK5KmD`0Q~H;9kHzfqMh@2<{c!Gq`tf58+8D})k zYMj|PyK#o&EXSFSvmIwV&U&2rIQvlpPzz8KP#aJqP%BU~P&-gVP)kr#P+L%AP-{?g zPWELP@7PrP^(b0P`gmWP|Hx$P}@-BQ0q|hQ2S5=Q43KMQ5#VsQ7ch1Q9DsX zQA<%%QCm@CQEO3iQF~E?QHxQNQJYbtQL9n2QM*yYQOi-&QQJ}DQR`9jQTverkOhzl zkPVO#kQI;_kR6aAkR^~QkS&lgkTsAwkUfw=kVTM5kWG+LkX4XbkX?{rkY$i*kZq80 zkaduGkbRJWkcE(mkd2U$kd=^`ke!gBkfo5RkgbrhkhPGxkiC$>kj0S6kj;?Mkkydc zklm2skmZo+knNE1koA!Hko}MWkp+Euk>!!;k?oQ3k@b=Jk^RvFpcg<-fZhN- z0(u4X4Co!uL!g&HPl4V7JqCIW^c?6t(1V~CK~I9-1U(9R74$6VUC_gzmqAa1-UdAm zdL8sU=zY)wp%+3=gx&}}5_%={Oz54^L!p;KPletJJr;T`^jzq@(1W2DLr;d@3_Tip zHS}!g-O$6KmqSm7-VQw;dOh@f=>5yijOZQFL!y^NPl?_VJtlfh z^qlBD(SxEFMNf*}6g?_>RrIXrUD3m$mqkyD-WEMBdR_Fq=zY-xqZdX`jNTYMGJ0k7 z%;=rbL!*~QPmSIhJvMr6^xWvZ(SxHGM^BF496dUEb@c4$-O0JRz$^eW0n7$4BfzWxGXu;HFhjsB0W$^67BFMLtN}9z%pNdIlG0es=Bg3o=Gc(N2Fhj#E4Kp>&)-YqktPL|a%-%4A!z>On zIn3rTqrLW?_AukatPe9k%>FO~#4HdqLCgj*BgCu_GegV{F+;>G z5i>>17BOSQtPwLu%pNg=#4PfEnIvSBm{DR@iJ2v4mzZH@7nJ{Lv zj+r@T=a`{mmX4V^X6u--W7dwDJ7({g!DAMWnLK9mn9*ZakC{DY_n6^hmXDb}X8V}& zW7dzEKW6{f0bmz^od9+N*b!h?fSmz$2iPHCmw=rDb_>`sVAp`119lJCL0}hwodk9h z*im3tft>|*7uaE7mw}xIb{p7nVAp}22X-IWfnXPcod|X#*pXmYf}II=C)lB2mx7%N zb}QJiVAq133wAHq!C)7IoeXv}*wJ8DgPjd_H`w7|mxG-Sc01VdVAq444|YG;0bv(} zoe*|I*b!k@gq;y~N7x}@mxP@Xc1zeXVb_G66LwG7LH)0bf=&v%DeS1QtHRC-yDRLl zu*~&E5ptVyEE+2uuH>E4ZAh$*syEE&JDXa z?BKAA!%hynIqc}LtHaI?yF2Xgu*<_v54%0=_^|84&JVjk>;SO~#7+>qLF@>zE5yza zyF=^{u}j2G5xYg~7_n=_&Jnvu>>#m=#7+{sN$e=GtHjO{yG!gavCG6x6T409II-)* z&J(*&>_D*##ZDBvQS3;uE5*(fyHo5?u}j5H6}wgJSg~ux&K0{?>|n8r#ZDHxS?p-B ztHsV1yIbsVvCG9y7rR~Tc(Lon&KJ91?0~Tg#!eW!VeE*pE5^|*__6E9&L6vf{2hQT_qzY#{}v1{_=o>qUEcE_etr0Y!aw}}z8boJ`16cC`~Tw4 z|FgIBFTUT$G2g%V{u@dU|HbR^v}5{<*SB-W+jYF&eM48*@%qzq&#vSB*jj3?YnH| zT<^=1$JcQEA64_N;q$l}II)V)$5^Rp6`$9Of0R{xe!HIW{v%oJF~=Nn=>vx3h% zMzm$+f6sq0ZUy&4Mw{6R?vLVgLMymm?w+1s#{DyYpmiDd(~-Z)%ecSp^jRutY+>h4AkACC+Y!S`)jr-O0pWScVzwSf(f8&1cxUsT?`#UkSa|!qRP5%o^ zxc{wu8 ze#d#_WJ&ps^Xask(RZ9z`QZZJaefJ(n_0klw&7~a0?s$(*7yaScdrM{7jXW)TiUaL z^YA3^_j#O;$5h(pabC9ApPR?|*_>cIkMs0sqxd||SFaDh=kRv`WZ0g};ruN<0-v#f zdE6H2G>7x~Lap>1&g=ctf4|}UP7v+>hV#79t>7EZ_r^-kZ#eHW=M}%<{I^hI_=bAG z5c_%-^`WN!@+|6wu}I)7>c_8ejak%_iayp^)ED3VBVSQ(jFPIpqW+wm3IB?EL^0C+ ziu&}infoj1Rpjo^GpJt{X^k_eXA%D>GpKKKLB=zvcXz)E&Y=EHxy??a9!5{xnMQr2 zxF=1cUarkrO{0GP3=y41Jq_CUYYO$1$ZDTLy%iG8nnL|`XmyxEJw9eFHHG^8YH9ro z>NW4ht}m$HJQ@XGP|pXaJinm6yW}W+LA`I+W&DEr|L4z}N#p^Zn^z~15BP$DCXp9d z<+Ub}A6AyxCy^&UKm0I(d@-0-JAu6M&Ym=Z{P9EHU;=qWV(X3xQ%HGe&I~Pbl$B}=6g4@TDhid$@#*vS7{T;`VmkffW$C01f zqyCK{PcvPs{Dlf_QNUs z6Y|{c^SYmq@6=xKd_vxfWtjYk{FkTG{1JJONQwQ3e0b!I*+=BX31Q)n$d5r`iyx3D z7keLmK)&>n%>017IiBwD0r}JAx6}vZ(Vx!$M*qjBZ+b?NR~-zBN0DDoJoOz#o^?L1 zHi~@P(91H4ysKh6@*eq@aklzB^6+k2)O+OP6u}ekk(W*H^S?)a4tJRuL7v{serE*v zdh^4i5#()Z*r^fZ?+7{Z5#;gZpUcC@=k)iU4kNEuB<2kxzfakC3?t8X%PI{c-=AUM zJdC`5`N!LL|KtCW@^|P5oL+>zLx1qCP4^x81^qj`@6bPx?|d0TKau_5))4xO^sa;< z^c#_*Rzv7NY?s7_(2po{Ef1nU5m0(Mh<=5|DQ^({3tN`QAo>}}r%Hq9Z+z*P2GQ@l z)fsw={wFBC@-6xyozaN5=#OmV^xvXiYEI*Si~i}%!ps2rDLd=C1L&{rJV_ZqzZG@( z^Z@#=|Hsr@z*|*y?c0cipoD-R2$F(eP@>dX3o!^Or9+TVKthz1I{O?B-QC?C(s1^o zyO9zB0RsU+QF#!IcV2UkG1vS3e((3!M>uEiwdNdg-`ALP@y3_W(vMXs`_CErvsOEf zo}pj+x7MsP^lyc}?|g=S?i+KwFa2GS0-4Xy?`1pu-PiPgi+ivAntt#`iNvqz4=?}n z!PoSQW7Zb@n*K3O-#<>%Prh4o?`itW#xG1dO~3h0sLp!>8DF)J9~ouy7GsMPtb4AT-oac{ddjO)lblmH*RB2`Y`?Z z{zJEq)347i8$C|{eq-h6&mA(PXGVJu`|ce1Man3d<=b{ z*OOl!Lob-Oq53iOgC1>jA45<0JKvq7=nLhq1xL{v$}S&!6#e0!KCO?UM~tag<|z8a zgV)j?MX!j5LYac=H=#?S=5%iDld44~P9@4AK-oxl4 zL+ejIj9#*)U;D%8C-+uXIE?n>U6xgAN^_Q+pG4YM}7W6!hZCr z%$e%#N3ZJmSdsncS0n%aYae>nmnn|!L*IHm!<>EST}KOa-G~15_M7kSLl2wRF6Tb< zv0tX#-iu!L>ZxEa`q`)1#_vT>Thii_z36MdepPNSdRx_}Gwelw+uZZJJ?L@o{`A!z z^tlHu2Jb%IzlzY(kl4qUSjovrY=;xD@wp#|^ z$tK&;tFwMwd^`H})&r@wqi28n`ZwFqw-Z*c-iF@2y41jJ=-(Z8G}(q8zN1lzZRq1` z9;M!fUjEk7i(App<6ExXik{xF(BQ4;>zVI0+lt=ax(zwpXC3y{|5Y&=7kz;z+ZX3!7Cf^TiT6JwE_R7^0yb)t;etF@^{Pi_%{c;mRpaXbLxKP_4qqu2j2J!zvroZJHEpIskU$OSNK7-dVTg4 z{!oF}t9*rDbojsLzrsJNedhi;{G<&VkFCRBdTha>b@)vcX7*o)|Mcm+2J7&n#(nkb zI{c}vC(^9Lue$Nq<+b=%1&eQ5i=Wk{%jmWETW6EouEp3DDrep&AS&0T|kHhE<4HTY@uOVnM1zt-%^OKb4k)=f*b2LG)^D>JQR{J6HS zZ(NN(cOv`f)%bODA8)rB|L(iLE3L-Q8=o@QYW%$*+wZIJ`#O|9vI_riX7h!s@B^Dp z>c0wqaM?EvSK$|qeW~Os{KM=+)33r$^nSm-5`QuCr^zev8^``KX(j&Sfqq?9;zw@H zRedG?WT!m^SK?RR=>5+M{L2#FxfS@C)ibVLfxqe98nyzzGxM1?EAT(}ANE$@hqgQZ z>SbPzAN$gd zo6GQLvy|Jr48Jx{FnbyPZQT!gFT>B>a z$`btPcTaU)f?vJ#mD)@2ug6a+wgf->i419$;BRLfdv!5>_woYCi}Am|-#KM5e)x{g z-4^4Izg4u(V*K*1zrC~=|GdHew2Sf6?=8E&2!H*(8Nnj__IA^!FT#JXwWQ}F{P>i+ z>n_5dAAYO&BK-Pa@;|i*|GxMqHx}aO*WbKnA^!fy&(2+l-~Y*=ehXm$nx<^B5FX&Y z5w9p~cSl85dtfB`7k|HuLufXbDYE`R}OpLx&%7=RUbS}lM9$aK+P00S`P zOzs6R05vcFH6I3`^q*(v!vNIIwSGPfz~Y)?=feP08r^w53_!js@6Cq+crUK#d>DZJ zOViAU0hm_k`*|<`2UqT#2LsUfo!RqX0BYarI}Zk6?d&G=U;qZRDmxDb;ArXW^I!nR zX8mI>48Xa^%oL?z0OtL>dM*sWU+G58g#ox)u;W}9faW!-&xHZ#G2q3yFaWO}Ofwe- zU__oD=D+|e zpxCJkvta<4g?(oS790|ubz05;V4Yz7R#xa8V1U;vKCm6!no(B)|688867JN`Bu z2H;+%`qFaT{kygnTU;6jfa(_sKEj(so< z2H^AUX0q2X0CVndodyHYsnU#TFaVdP_L~L+@Mp>v(_jEL_o*}u2H@pX1*X9OG??-D zG#G&LZ~rhA2H^6eeN$lo-rl`rDhxo^X~U+%0DP9vaViWz#a^|h!T@~Nzr<7+faVjk zOoaj1zU_}GFaZDlc6JI3z>8(KOo0LLM@^ps15oXcep6ros($*>6c~WFeyuzO1|V+G z3sYbKD!lx}6c~Uvuicys15kg-(aA6Xz5B133Pc~TOFDR12C)Es);ZFP1}x}2m_Fq z*kd9LK#o;SCc*$bf76=?12Fydf)il?#*a@s5eDGN$8Jx60Z1KxVgd}n;0zlkzyM5K zF?9kAK&fW^C%^!-$=!Ma3_$T;s!V_Zn0V~v2`~UNcRW1-2B7-x`{Q8%W}m${9tL3E z!yV&c02&luG#&~22}2H@ zPZ$XUFm-pokuU%S8?+q>1JL+koslpA{+jaUXw~Iq&-W}e5(c2i`x!^V0F~Fhq1Ps81sdGla0BpQ8Yy=EI%hKIPzyMsD)?x$GaTp9hf%iKPg8?YfyU8#Z zfYuw{9R>rCoU-&V%K)^>I}8Tk&(lv1g8?|-@WD_RfIGi@KNJR_;-r&9Edx*|Iur(A zP@d&OVE~5yJ$Wb$!0}&_hQa_e`R((eFaWQlZ7~!Ephoc;Lty~6v@bUl2B7E0!b4#I zhCY*RC=9@FgB}|S1F$~*-61dlr{{b-1P0*!YKMlv0F+F%c?b+ZPcu6V15jw~_#rR= z73U`mfdSaH__HA}0Gpy84uJv4cjLVwFaZA+EI$MWp#B#x4uJtEVrGkB0D8WgdI$_a zl_S3oh5?w~=GtHwfbN-24u%0ZcO)1L1F(0-s=+V-mEva(h5@M2ZNy+0fZKig42A*7 zKk3uKFaURVH69ED&@g4S!7u>L>y;f01CVMx#AQ*rBr#41@vbK7H&!7=Q&269>Wo zZ0gu;APm5o-##7)12A@I!+|gW&0ecE5C$OIz48NL0JiQjC!-k#;Dbfa4}<~uc1Grb zFaXUKr5p$YaC+AtNz5m`eecI47=SgeT}Xlfcy8F?Bp85!_mY!f0DkMVCJ6?h)!*}y zU;r-6oR|ay(C~vHNiYCcbM{Gs0qF5Zrz9AFT-QEIf&n;ot!@$wz{LCSCcyx7$x}WF z2B2lbSCU`=IxNVS1OqTSRkkD;fa5*WCcyx_`tQR5FaRqi-x&Y{Q1k6;17HB2PIYzw z48Wta2M53aWJpdP00U5MHRbVU;xhddz1(Ra3lHGL>PcKpZ+ls2H=OD7ZYIs&ir;F5e6V@{JumO zfVp|MC&BBR)+!MOV9|(1i7)_9q^z9?18{iQJBcs=_X<}`gaPP()|?J!7=X{G7EOc! zIQ&_@L>Pe4jdLWz07M&POoRbw)HZb@48TXj|4x7bIJfKf1Q>wi47Uu?V?R%T0r=6JJ_iHv__9_BFaS&H zHZ?`$q%5a1*Gqr_7;?2n0t~>uz3(Kz0E|iY5?}y+Jn%*W48Vb(N+iGll*?5t0S2Jl zM+FmL01j=*od5%HyKwdd7=Ss8GbO+P+^CQ)0R~|A^^^%P0A*(X9kKJSo$p6r04~<~ zH39>WrOM3+48XNI-$!5oYIMFFfdP1b_W1}5z;D-2MPLAmS3DYl0Z6}Oe*^|#K#^S$ z7=RgDw?|+A>bKk!fdN?k+`0%1!1AA0L|_1_9bO!P0T{kxUIYf9%fXou7=TAVOo_k% zyp(-H1O^~wlhF|vfXLcm5g34lxd%mH0J=?2h`<2cdZk|k1|Y-Ny&^CG7e;oAzyQ=~ z+9d)5(6wU62n@hmCEG<{0CtpX6M+G^S^uL548ZPz%_1-WH4Zk4zyJ)$S3d#+&|&!d z5g35S)7Of?0MwjOJpuzzwQ`jR48Z+IZ<)Ur_e6t(l_D?z?U%(xU;s+aE+2sbSh4tx z2n@ityI+gI0POs|WCRAF*&D?pFaRq@y&Qo7SZ`+UVF149RU`rf@KgF1A}|11*A|Gt z06h3KUjznVLfPjdFaSU2%pHLN_+Q3c5g33V$FmX30KAqx0t3*yO|}ROz-LRcL|_1( zPw{jF24F~sOc5A>6*n_PU;sw+dny70P^8e45g34em(xXH0LH9%A_4=@d{o*948V;6 zX(BKHuZ}eH{DuK2xhz!#2H@9k9*@8PbjN2GSdTCOtWOvK)+-DE>lX%q z^$Y{R`i22uy~6;o{$T*v4=@1i4;TRU3k(4J2L^!s1OveSf&pN^!2q!TU;x;UFaYdN z7y$Mw3;_EV27vtx1Hk@<0bsww0I>gI0Eh=L0K^9v0OAD<0PzC`fOrA}KzxA#Al|?L z5Px6*h(|C0#3vX4;uQ=4@e2lkcm@MNe1icX-oXG=H1Q7xfOrT4KzxJ&AYQ@%5I9zhMB# z=P&@|cNhTjJq!T(9|nMW00w~i00w}10S18j0S1720tSHk0tSG30|tQl0|tP41O|Zm z1O|Y51qOin1qOh61_pro1_pq72L^!p2L^z82nK-q2nK+92?l`r2?l_A3I>4s3I>3B z3kHDt3kHCC3J69$0#69#~K6b69$6b68Lb-G~ys9#|KsApjSsBd8asCQuisDEJq zsE1(ysE=U)sFz^?sGnf~sHb57sIOrFsJCGNsJ~$VsK;RdsLx>lsMlctsNZ1#sOMn- zsPAC_sP|z2sQ+OA=m+K+27vwm27rD627vwn27rD727vwo27rD827vwp27rD927vwq z27rDA27vwr27rDB27vws27rDC27vwt27rDD27vwu27rDE27vwv27rDF27vww27rDG z27vwx27rDH27vwy27rDI27vwz27rDJ27vw!27rDK27vw#27rDL27vw$27rDM27vw% z27rDN27vw&27rDO27vw(27rDP27vw)27rDQ27vw*27rDR27vw+27rDS27vw-27rDT z27vw;27rDU27vw<27rDV27vw=27rFsG61Ikh5?`-hXJ5JhXJ5phXJ5}hXJ6UhXJ6! zhXJ79hXL4a`hUv+7(D<60DS-k0KEVP0Q~?4pt8{uECXQl1sDMI1{eVJ2N(eK2p9nL z2^awM3K#(N3m5?O3>X0P4Hy9Q4j2IR4;TRS5EuaT5f}jU5*PsV6Bq#W6c_;X6&L{Y z78n5Z7Z?Ea7#INb85jWc8W;fd8yEoe92fxf9T))g9vA@h9~c1iAQ%AjAs7JkA{YSl zBNzbmBp3knB^UtoCKv$pCl~GJq-o`eGLWxy$uEc{S5{HJq`u{eGUcyy$%Kd{SF2IJr4!| zeGdizy$=Qe{SO8JJrD)}eGmo!y$}Wf{SXEKJrM=~eGvu#y%7cg{SgKLJrV{0eG&!$ zy%Gih{SpQMJrf21eG>)%y%Poi{SyWNJro82eG~=&y%Yuj{S*cOJrxE3eH8`(y%h!k z{S^iPJr)K4eHI1)y%q)l{T2oQJr@Q5eHR7*y%z=m{TBuRJs1W6eHaD+y%+`n{TK!S zJsAc7eHjJ-y%`1o{TT)TJsJi8eHsP;z51$Q0MM^t0MN5x0MNH#0MNT(0MNf-0MNr> z0MN%_0MN@}0MO520MOH60MOTA0MOfE0MOrI0MO%M0MO@Q0MP4U0MPGY0MPSc0MPeg z0MPqk0MP$o0Pq7~0PqK30PqW70PqiB0PquF0Pq)J0Pq`N0Pr7R0PrJV0PrVZ0Prhd z0Prth0Pr(l0Pr_p0Ps6t0PsIx0PsU#0Psg(0Pss-0Ps&>0Ps^_0Pt5}0PtI20PtU6 z0PtgA0PtsE0Pt&I0Pt^M0Pu5Q0PuHU0PuTY0Pufc0Purg0Pu%k0Pu@o0Pv4s0PvGw z0PvS!0Pve&0Pvq+0Pv$=0Pv?^0Pw3|0PwG10PwS50Pwe90PwqD0Pw$H0Pw?L0Px3P z0PxFT0PxRX0Pxdb0Pxpf0Px#j0Px>n0Py2r0PyEv0PyQz0Pyc%0Pyo*0Py!<0Py=@ z0Pz1{0Pq800PqK40PqW80PqiC0PquG0Pq)K0Pq`O0Pr7S0PrJW0PrVa0Prhe0Prti z0Pr(m0Pr_q0Ps6u0PsIy0PsU$0Psg)0Pss;0Ps&?0Ps^`0Pt5~0PtI30PtU70PtgB z0PtsF0Pt&J0Pt^N0Pu5R0PuHV0PuTZ0Pufd0Purh0Pu%l0Pu@p0Pv4t0PvGx0PvS# z0Pve(0Pvq-0Pv$>0Pv?_0Pw3}0PwG20PwS60PweA0PwqE0Pw$I0Pw?M0Px3Q0PxFU z0PxRY0Pxdc0Pxpg0Px#k0Px>o0Py2s0PyEw0PyQ!0Pyc&0Pyo+0Py!=0Py=^0Pz3$ zKmM8jjsM1<;m`7S_`CcJ`?Ji?=E_~dxpKk9%3)Cr`TKUG4>jJ zj=jeoWG}KO*_-T9_9}apy~`eEFSDoF+w5`nI(weIPYfUy5EFF$<5?way2=d+)WNA zmy^@U?c{iJJvpD;Zy5kn3s4hK8&D%qD^N2~J5WPVOHfl#TTo+AYfy7gdr*T=i%^qL zn^2=rt5CC0yHLYW%TUu$+fd_B>rnGh`%nW>3sDnM8&M-sD^W91J5fVXOIZfM)K=73 z)LPVB)LztJ)MC_R)MnIZ)N0gh)Na&p)N<5x)OOT()Oyr>)PB@})PmH6)P~fE)QZ%M z)Q;4U)RNSc)Rxqk)SA?s)SlF!)S}d+)TY#^)T-31)UMR9)UwpH)V9>P)VkEX)V|cf z)WX!n)W+1v)XLP%)Xvn<)Y8<{)YjD4)Y{bC)ZWzK)Z*0S)aKOa)aumi)b7;q)biBy z)b`Z))cVx?)c*7U^aAt*^ak_@^a}J0^bYh8^b+(G^cM6O^cwUW^d9se^dj^m^d|Hu z^eXf$^e*%;^fL4`^fvT3^g8rB^gi@J^g{GR^hWeZ^h)$h^iK3p^iuRx^j0tc^jh>> z^j`E}^kVd6^k(#E^lJ2M^ltQU^m6oc^mg=k^m_Ds^nUb!^n&z+^oI0^^osP1^p5n9 z^pf8N^zQWV^z!ud^!D`l z^!hLW^!{i7XaQ&fXai^jXa#5nXa{HrXbETvXbWfzXbor%Xb&&|Xc1@;Xgz2?Xg_E`XhCQ~XhUd3Xhmp7Xh&#BXh~>F zXiI2JXiaENXisQRXi;cVXj5oZXjN!dXjf=hXjy1lXj^DpXkBPtXkTbxXkln#Xk%z( zXk}<-XlH0>XlZC_XlrO}Xl-b2Xm4n6XmMzAXmeE7~g>ELtp@ zEZQs@Em|#_E!r&_E?O>{F4`^{FIq2}FWN5}Fj_F0FxoI0Fp6Guks6G+H#8G}<&8HCi>AHQF^AHd;2CHrh5CH(EEEH`+HEI9fQGINCTGIa)cI zIodfII$AoKI@&rKJ6b!MJK8%MJX$=OJlZ@OJz71QJ=#4QK3YDSKH5GSKUzPUKiWSY z0A2u|0Nwx|0bT)~0p0-~0$u{10^R~116~831KtB31YQK51l|N51zrW71>OZ723`i9 z2Hpl92VMuB2i^xB2wn)D2;K-D30?`F3El}F3SJ7H3f>AH3tkJJ3*HMJ3|;mP66;nCsM;o0Hc;o;%s;pyS+;ql@1;rZeH;Q`_W z;tApn;t}E%;u+!{;vwQC;wj=S;xXbi;yL0y;z8m?;z{C7;!)yN;#uNd;$h-t;%VY- z;&I}2;(6kI;(_9Y;)&vo;*sK&;+f)|;-TWD;;G`T;<4hj;<@6z;=$s@;>qI8;?d&O z;@RTe;^E@u;_2e;;_>43;`!qJ;sN6Y;|b#p;}PQ(;~C=}<00cE<0<1U<1ynk<2mC! z<3Zy^<4NO9<5A;P<5}Zf<6+}v<7wk<<8kA4<9XwK$-<=N0#^V2OUr6ttj8mA5bZ~cQEMdZ(Lr$ zd$B@ae_rO|-q96({NtS~c+qTq{9SvicqzN~_8)tuo;P#*zhG z+si+4yqC9kcu#*vzeF$X)*k-&QA50am%IA~rj7EReAvw|IcI`*>B(;XpgGgLD%raF zKTMnBeUSAFKg;Mv-V^CQ_rLDD!t46yXa3#R>%3X#JNw1n-t3KE*U7J*C+amH(9wV9 z?r!g?_d57>w;c2qr~A}D)aSTYF=*$%`T7~}e22DvU$Fce{=oyK z{NGcRvH!D|z-Qqz@!9x{d{#a)pPlc( zci}tn-T01tSH3gfooB$a;F<7jct$)co*B=MXUMbUneuFT#yo4DInSPVz`Nj`@NRfV zyer-r?~ZrKyX2knZh6PNYu-8Uo;AQ)U`?<#SRb=Ev{a$GdzU@TUS?0Tx7p+Db@n`apBP~NeLMed{`+?RyZQ6U z{CV^DlllAR=Oy#=%+F8e=bPV`%yEd7e?8r+L0np09b{QJ%MX z{!yO4c^^^Uhj~9y-j8`-QQnt%e^K6_d7n|S2o)3GU=f&RV`LXwTp6q>|FMFTo&EDtvv-f!)?0w!3d!P5k-skNn^);oKj_0QgCKd|@NAMAbh3wxja!`^2_u?0xndd!PNs-e*6u_t~H9 zefBGRpZ&|;XFs#|+28Da_B(su{-4AH```F85-;rEv1^MpCi%v$J=UP)BfBQ0aAb1SVRnv`ozX6 zVt~{yHkJ_sq`tASju;^IkBx=I0I82`tRx0V{bXY)F+l1o8*7OHQh(W4Obj44^L~ic z!~m(^Y%C`RNPTBxJuyJ)Kbs4P0pteO2f2b6AoZioCBy)!FKw>QkGm zhyhZ++FV8qkowlV1EfB-xsn(l^|Q^T!~m(UZLTE-Nd0YdF)={ubDOJ) z0aCx)Tuuy-`rhVxVt~~D!~u zn-HIA( zBEBkHN~$5%-#qpn}8yx>AeXIE4PnC^-E@Qg* z<(ba(FZcA!{s*$O=wClup8nUKIoq#Oj$!>CJX@|`Vy^3bpUge9@Ay1L`{vBMx6kZ+ zANDC&;BN0l1^e}W@rBgAmlPiMW#JdoeL25qQm?!(J?uH<<&Hg{e)U3+!NuR~@uVCO&i*7Z`Z0Nf6^|W0Jm9789h;p+&zgPZRmj)FJcG(=);c>CvYh3y`q2`S?L9M&3AJx9s zs`UH6wQT>v?T@C{z24$by>rd~tiS)mJPp@3tK4X2(>9G0nT*Zfeu>n*0&z5P-94}NP|`u%&Y9@W0vI;eG{O+w8}ANw_qfAXk$a@+OQ7PV_% zbwvBzRXTlo^quM*dcR%Be5$`X9((gpr>>PIbEy0=fxyhY7Z9%`QU^}dO@%9*D>%)EuO{jNQe$Gnvm=IzWhZ|O|` z<(bl%w^r7?y;kNe4mNLdv3aYz%-cP0-ty1pZQnO<{U7u8|BLVR??3Su|Gpnz?a|Ni zoBui=U--eU_=)!y$EW&paD2DlTg89>TiN(}znU{j@0{uX#xFDbFT2&Ef1aCp`j5MD zwqM$xhV|?BLph^jU+>%T+R(l~epj^bM_2at`S#L>eHwpzxA(bk`t@#jA$9Ky=Z1aR z>}R{$`J{M;CU_ex; z{Vy`?o%Q+B-PgKQ*;TO1jU6pM8xc(ETrzs7(>L4y>Ns#)p^l}tR_}0qbEi)yZ5q-3 zy^V|7rP`3(cE?x8Kk2{j(#Mt7-e{9*&E3{VR^4kgY2|M%+pM_#QJLk}TclrhuKBek z`#(%xyuR7=MKhcBTbS6S)q*yS-c8=*mtpd{$YL=Ml*Qh+@QT4`?*H`O0seRRP6LVMDFyZJs7svO0JI(kP-YPTh z*qiOgcC9pLOb-9s(VOG)jBZe|<*0k*myH}z?!kycWvh?a`ud#VHOo92cDZzuVVz4w zhdwG%c~T6B_`(Tp7`L|qKTbyTuZq2%$$V!*;*wW$Wkn!+|&0X%QNkd zJeP51WcX9PB9GEHihPLf}Z*Eb&Z*E#GW^Q9`Wo~SpV{Uc5W^R5hYHo+^Zf=m> zXKtCzZEm9NVQ#BEYi_hHZ*IMvXKu#LY;Mm@G&k%%9N6$e_dyrV-5=EKY#(#uZ)$TZ z@OX1`aA9-1aMavD+{D~c{AgJIBXi7c$JIx?bMV24i~EZx+ zH$AsEw?UUNH%6y1w@P#GJ$Ku4e?529a}Pat&2yhTcgAxsJa@lmFgJX2hdcMQa~C`J zt#hY3_oj0h9hbJsQZS#xLg4RbFwcTaP_G0CCq)n+zHIRzufK1{k`1L%RRi@wab0F+?mV0xZHiq{kGg; z%RRN+MazA&+$qbwvD^)-_rK~ru6iG<-m9wjqv}1UdS9vDJF54Gat0`Khb;emJ<0qjXGk)~s`o+ay^eZ6qu#Tq_a*ARhn!u={IcFdsP_r# zy?}bZpWf5w?%R`l^Ys2Z&ah*S{vC4`9rO5lubkcwr}w<+eQlh%#<>T2f12KdruUiY zy<~d77-xiWPKDn0#hG24o1yn_={;I{AC}&0#o1JxPr?~foO7c0Md`gyE9Cwry@yHf zQ__2p^nN3~r%3M`;>;k~|MkI{Qz^gb88 zmqqVa(R)(#z7xH-MDHKbdqng;5WUw!@8{5aHuSy>&b;86>-`ma4~5<*q4z@Q{SJCh z1Mil1toJ79{ReuFf!;@;_X=<}0BcCk`PcLM_1t|uKVQ$m*YoW4TzWlUUeAfw^WOE` zcGf<7K+jQUZ?H$0X=cyp`Q&=exSkiT=YBK0%N}F~mp!THY3sSzedT;>J*PU5^QM^@ zWzU=b&z}FR=Q!(m%zCae{unVp&pFofiuK%KJwI5_0oL<;@kNONdcH0`E#F7ayVY}R z@t^trdXB7~2dn40;?ENU^qf^aFICSy)$>dB98!1+Vt}3t3g5x|({noEO^5+{Zl<1p zspnYgd6astq@E9{=RE3pje72)o}Z}aAnJLBdM=@!FR14P>Un>9ZXf&|F+k7J)AR83 zTsu9VPS2Us^WyZ}H~39r030YWK+jWyOJ%>px3YiroH9LcOwSF|^S|^QFFlV-&(+fN zvGklPJ+Dg7oznB8^c*NX&q>c^f~_P5=s8Jx-jSYLq~{O85E29QJRm*SN6+Wcb9VH+ z96k3&&#%#QX!JZ8Jr_pLchPfN^t=^4HwE^I7@+5v=y@bCMZ^F-A4Jdj(DOR<+zmZH zL(jp`^DOjS3O!#!&xz3U9`xJ>J%2&ZQPA@c^jrfypFqzUfE6GH;Q12+bbepw@O7SE z=i+s~9gmtAp!4QBH*U7SsQ^=?&^d0M$JV)OosZTzXPsBpxnrFl=JOB(be>n|a&^8| z=VW!>Rp(Z9{#55kbskjbI(0r%=PY$zQs*9Zeo^NTb)Hb?0(HJm=k(mXoy^VY{F~0P z={%awmFaw#&Uxv)md;)2{FKf?={%FpCFy*T&I#$fkIwDr{Eg1h=sb+hwXlDP0Xk=* z^CCL;q4OI$hoSQnIv1hy4LYZw^9DLMp!~mb{L14iSFe1$a_-8jD|fE^xN_jib1Rpv ze6@1Y$~!B!to*TZ#L5FJ*QF|DR-y*oN{o=vniLRe3^1$%6lodrTmq0RLVms*Q9)saz@GvDfgrNj&eB4 z(dY?E95hvIr96&zu@x( zd>-@Ptfp%IY{2J5+vhWwpB3`ek}z`d)fl?O(MI)qYa@LhbLgPt$%&`zGyww2#q# zMEeTu546tLdR^;o)()RR>tL;CwJz2AQtL#m_q1-)`b+C5t%tO((fUN|46PS5@0(w5 zo?wa;nuj%?YF^a*rg=*9jphxF{~E_N9&23H_^5GCmS@59_dn_TiC3$0jA_FQcz@#;UZ3?bwhfQq>W}@s%)iALH@t&mg9dsz z3R&L8!&68*akw|RrsZB>4g5-<0BKuj?N%<_@pt%L#Y9%!#dt zal}PGZQeh;duc3(0~_MMGUqQtSGT|`vb@;39RGRI`!OaDFKKP%l>Yvf&G43BO#Gxj zQu%fEG{JL%J@H?ko7VsIdCTj-r1&eVruPeXX^2M!tKy%y`IJ9?OMPOkPs~jkoXOw) zFvjrVZLN7ei@&e*2Y6jDFMhc-+5FXQ>fnLF!uV+`=J3aitc5q`y`JUmz)KXFGf|GDiR-X4sP-#*(b{^N5h;`zb;_zPPW z_ZRdnj~8fpz&uMz`q@7yi%00=6>k5jwBIq`>n{KE&-`!VBicX9-w{92{w#i`_=@&- z@jJy|w4a5~BtE14tbAti8|`=DJBjaTzboHa@}7MbJQMLD?X%*Ui63d7CC^lRN&BpM z=HgGY1bNS zPW(-~7FmEhekSWnECddlVka)S7{Hdl}{#Lu<4gq$M2uFW;%9PxK; zE+Qw1&ueoPIZOOro6E>);``cMN6wQv&gMdLqWHizSCTVfHDNZ$rQ}rcg>9}S=ZZgU zb1^wteBwBAH91@SVw=m!>Eat#B-fMk$^BFS^6%T!S0?wHKW|x5{AT%iaAnqqCik1) z=lp4Mzxh1Qx0cUqSyTLMa=-aL&gUlgo9}CT2I^RHzj+?c7bo|d=Ve(`{Bm-?d7jQk zC-&Zj5$oA>SNX>z|=56;&o_nY++RllFyZ`PCJ z0LcAjy*WOB+;7&S;|9q6X1zw0Cm{Em_3StUa=%&cuC6EdoBiOp1aiOGFOF9r_nZCX zI0kaR*>8?-AorX7=(q=RzuB)*di$F-3AO}=ov z3%TFq6UV`j`%S)adet$NiA|O}>T~v^)^G-{kW^IU&jSuK$#Jz;Q)VFF4*v z>IugoNxk9tB&kOnwG&|IM;$jN^{V5^q@H!0nbf;Z7m#|` zacNR7J6=udX~(fiz3uomsmC4nCiS}G;iR5-oSfAAPM?r|z;SibFF4*#`U%J3Nx$Lv zJn2UqwG(+LM;$jQ{i@?BrJr@2rS!W_HBk-SDgCTAyp3t@X0jy;{F&9jf)D)`eQ%X`QC^ zmex&L|0rjtx|(u(^7mbyR~=5dLiznJ4{APB?osoLa+DhHmCIE9PdQI{J}$1QUMSDg z#S7(HRbNz2R&__^Zsq;Cb*eh0a>4rk_h+hBVeNmhnvhzs@!{+h%l#ATLGQiar(*R7 zwkEW-Wc!<|D_;LK)Q9>MyH+vvPqCVlTCwEl+LVSHv5s2PvEUoh_4VOulWTJ=n) zigB~HhWb&)A@$>~FS0eHt!>NB=^VFq%>UDqE)Ix$qF1a2rnX$)W=!1A%|diM?Dw6*iru1n*p=sea)&xrpRswpj#olGYsB6cykWC#O>29RR1aSA%6}N@ zTVKCe%Ip1XsB_(JSk|j~GSs`gfu6T+u&sG*ud`*%+urgDq5f6-o9f;hzt|es_C~)w z_P*D6MyQ94F4EA;TrJeaa=rJV*ZlWz9&SL#*4|swL!E5v@b=!0N}*o1Zpmlf+3U7u zw!K=D-QB%GNuhqW;9?)|WP$&uqdkato1&qf)+J?skzViYq2Bg#?lE4UMWOCiChvGJ&ugLnb}HW_uT>E0aR26;>b+Mr)ZjroLa$4`P_N7TVSQ#9Pl1Z4fViP z#SVKT9@(D2Y6&-=Jmy_!66%A+Zk_PH-(-6Pt39+maN1jyCDaS2&Ohsw>k#UOTl!w` z2Jei`<`TJdtass^~DdT{p78v z9qNn;pWO6TObPYI)+K)N`dqO+ht*mh{qL@qt5B#vzLk8>8}>=4LzapB=^bAbn+Zm< zIZ)|=_w)C*C$U=2|NedGUCbBiliRlb<1K2^+-g4bDrw56@N13>^~$ajAM;P{w>^v1 zie}$U>A&_UHd{=t7+N)z|K-b}j`{MO)c%~Np`JPDej0z}kWkkg_udo!+^=G@$Y@lx zW~cMxzqLJ%)vh-Emfo-Wc&K+Cto)S!Z;?>oeEGCrZISJXtd=%ycNTxwj@Ya-8e5B}viWaZusxF1-Zs^J#$R$bHUo_&H+yP! zKS!!iH_dW6hd(rXsGnxapVR-RaHyk>ZaV9$7WB)td50d%YLmIj7V_U{ z9qO@%JG|h(|52#RUY}XmAKEn3XImaC;$N*7>a=hE^P=CZMyS_DiWT$!elyf~Ag->bQ-Uyy9QT5$d`BJNBwyG)<`M{`h-wf5pAnEI2)0fgC0Mk1yFC z&uX{J%9ir$?~Bcd)ARLiRN9YU8Pj;_{YLkA&Hrg!Y<8R)gn#CLQyrK;%imEwn4iVZ zls?k_E`F!#!+aJ#lk}bTv+|i$FXp@Ooup5--<9vIbsx`yXCi&AeO5d()suOaJX7g| z?X%{YtG>*;;GIa{Y~K~{O!a2oCGS-FZ2PWx=UQ*F7FZL~m)o_%no&KPwZxi|KHjc1 z)|~3otVPzO^!;|NvSwAUW-YU(MJKRpoi(p@E_;DJA-aOyE9@E7v)N1RDbXS9USrRx zzRg}_Pl|3~_p05qu{j;Pm)X;zbJ)Gkp4a-CSU^k=UBt!;VutGB#1dkP=qNVU5OY)? zCl(QtM0c^VikKyHKsJ^U(?qASv5uIhbv?0=m?*lAjg`bq)zgWk#8lPQiM7OB)z^u| z#AMNpY^)|`tKLp5C#H+eWMe%sU;7Di0Xac*DVrL*Z3QB#QyYHKZOF7+3v#i+?dH?_4I zHJkbk)N<5xqO;mskD5>WMQTB6LeXVytw_zNegw57HKpjdw$`NPRDXh6l$um@Ut6nE zv#MWVYgtp%icV~6U20zKQ>lfiiA7howK6rc`We*H)YPIw+gh8NTm21cacXkWt!=GN z&8~h2wLCSw=-jr}r{>rGm|lRMKy-22E6_8jA3`rdPa!(G?KS8*)E}W2p(hdD-S#T< zEb5og%h1z^PH%f1dLHe|>4oTtMAx^y56z8fp_itoR$qr+o1R;uc^=8?Bgyk}ev&-TWc8Kgc{_iJ-ru~BWc8WkeL260-ru~>Wc8ioeLMe& z-ruYT=R?VQaefrNzgbVo>PyLbbN&>)zgdq_^{HgNI=_nE->m1T`c|^uoqt8|Z}vk} zeJt58&d;LvH~T57zLxAa=Wo&boBbG7pG)?u^SkK%&3=xm?MnaPowuY z@ieNwn#5b@uhILPcpO!qP2#ol+vxpGJddjHCh^|+Z}k2qA4JuMlYHU)IC_7RPonC} zNxpIZ9KFBEM^W|ZBwsndj^5wov#9!ZlJA^1JTkE-t{`QG_|^!}zEh^h}L^@8&Q>HSST5mjGM>J8@)()*iw zB&t54)GN*}r1v-VOjLbCsdt=iO7Cy#p{V+ZQZG3_k>20bQ&II5rQUM>BE7$<$D-;p zO1A-Z#aLH-rw{if%>GM>?>PUI-rw{?f%>S@FF8Mz-rw|7f%>Y_Z#jRJ-rw|Nf%>e{uQ|V!-rw|df%>k} z?>YaK-rw|tf%>r0FFHS#-rw|-f%>x2Z#sXL-rw}2f%>%4uR6b$-rw}If%>-6?>hgM z-rw}Yf%>@8FFQY%-rw}of%>}AZ##dN-rw}&f%?4CuRFh2`uRY8U+MRq|0{YxpgyqZ z1>LZI@;{0UMQv&ssMQ?Hb zvgk2^`plx&IKNr+oIrhN(R-Z#EP7C&KD6jX&W{#7DNtWp^d{#|iyjrIPc3?t^Q%SA z3e>k2z03JLqK5_QV~bwq{A|(F0`;{;Z*%^(=y8Gi+@jYxzgzUYKz(n~`<(wRdSIYF zxaft>4;MW#P+wg1M(2-<9vP@lE_$W&%SF!&)HfHs)A{G3hX(4Si(cydbkS1-_0>gh zb^f~Ov4Q&RqSrdVUG&^QeRt7&ou4LpaG*ZC=*7;D7d<&pUtaWP=g*5C9jH$)dbRWG zMb8e@w->$J`S+rS2kPUCUhe#S(bEI<^+j)Y{=Vq(f%^QS*E_#o^!z}5f6@D$|1W+( zpd5hs1&#+0KOs;qK>P;B2Z$dLC?_C(h2sUp&j^$o5WmCm1LB7S$`OcP;&=k_Qv&4* z#BXtYf%q|jat7kpINm_~oItq)@p~M9AbwDw9D?{ojzDCZ!4o#P$E&kK}$5Wmmy z58?*~%0bZko1Ve(5aK5W%0-CZ==ccnBLn3m#IJO`g!q|(auecrI$v7+&_Fo~@k<>~ zA%1G0T!r|pj;|0uHc-w&{94Cbh@TrMcOibS<1fSy4wSd_f!2&bvV`2R2Nfy zOLZ#Mn^ZSa{YTH0avY4DL!~^7{Jdo4V&wNZ{XjWc`FyS~S6)WGkL!1pOI3bGo`>rP z<$1aOOwSEdu121>>tE!3xPC(3m#gpPeY$#Exk%-2^jtONaP%BD<#F`fHd$Y;?ovKS z&xKP?N7k#WFZA3w<#zO(I^}otTs!4>WWTulr03=-*Q4j`Dc_^#^67bfdXAs+KC+)( zywP(4mH$!BOL;Ekwse2!I@k58>rU5?{JYZ=w6E0XtItWluYPX*{aS!%X(j4Ds*v^naY-qEDPFPM-yxrrqC~5TJO8p8rPV&mmK#=a#r=?1%H3ps z#RvCd8Y$Z4^xoSmF1{1;ON*wRskr&)n5K%B`O4Ni6<_*39oZl9PJb7EJ+4>~(|FN7$F8p&cXNaJd2+t<>Nji0 zWmsV~P^%5sIMy_7?A(xtYSpA&T(3zn4H<3p=O4Po?HU&HQ5`o&;yU#=e3Wof6aE<# z*XQ$)m-@8w$hh0BLvHG)LF40s`XN7+{_xbeKi;((s@1lSXPgr^@{N$ED)GUhxWPqY z8aUeOOA}YbeV;w#tG1n67q=jFJQ}Oj&M)QM61V^NkhdCXj!~^~HKwtnz3!W_H}17# zA%8XK(&4!HtyY7z+Wdh$r{Z2&6!KU@KRh27H#Vl>qs{J_aXD^npODY$aq;`OAs<_f zHm3dOycM^zR>*6;+VHoy=5NG20<_zgC;Tt2dESuU8h7HKxLs-bqv2X_;ng%Ly&=DZ zJlC#*sl9clV;%(BZt6Fm@G5Ny`L5qTe9|j1%WAyVyBOX(qc<=y1tg#6gS86~_QidqfXdOLg8 zm-c>66Y^wrj=b*Gy&m&`(3U%1FX!b8LcZ*ohZViL)2zm9y`yTGD|t7&g}hnX!f$y$ z)rxscXwNk(yz5ncG33vlty9g*_*fq_XzNY2ZBxT5e<9@2%J!=59bOaju+XN54*$U0 zIXL9g8qKQjv-^~lh!mz-|yjlC4|Yt6oI=?z$G zHEipx4f>;v_ia+hvlU3y&YRXS=E0$D7th+k3yOw(+w%OKz3Pvw#%;a33B^D6DjW%U zw;L6^dE;lqJU+DVMb&zGA9M`)x5M>&dp#>y4cvNz4O;f|Ql$@hxB{<7y#JjuJe+WG z)wd;h?=KAbxB`_1cv-)&8oBizm+eXNDtaL=cctne??}3y)}ur_-+5%Px997SpQ}@6 zs8?uq$k7cuJ+h{Z|9PVuUJ z67z7;=8t_h)hkjg1VTs6=Mtr-bS1Fuf4QC$L<(` z(fH@~8L!4f>v33iBWsg$-s5kEyyN_R=e=ULV~hvh$I4RQcsnPB{A0;k7rjH3LJsoP zbeFt$ZrYhD%Z$wHdf6*6KE{yXjf}i>#T!*2jN+6`jFRLSo@)u<%1X_gm+V5)gv$Au04y`GDNAK`p0WKBE}Tq~-GE=Rpr}op0v7V4+sjmH*+Rt7jlJ)Qq$mXIS&_eVOv^`ej` zjhmU?-(N1qfZ;9We)ma#@sZdaI51)h?>y*}jcr_Md$} zc+)~tT@tRctR zsChR3@!28InkwZpeuZLnEQ5!)Rd3-l{vYc@zO_o#?EXuB$hls*nce^XfSnPvOy9F3 zbNIPGh%tV6Uw^*(tbgX4*xf*A3SCb;>t}9lJuu4#PWU{h;ic?Mp=Ac^XUXM1@kNXw z#2eeZE|f%V`loB3Xyf_~vbA&-0K zW}Su-FZea`hP-al`-S}*Gh&P=-d(Yq zh5aXUh5T;2#3KHtN!G)&Y-y!jFZ#E$ggoz>wJ-WhN5vRayuHm;i~7H&3;EuLSBm;O zlB~yP+0{|q&G`)f*%?jCv^IV6CI7!(F~$||FPQU^-}zqbZYMOSEoENz+jg)Xpk-sL z9eUZnecjGcz_{esxvF4PIW-YQNm6K+zvSyW+W-YU(#izDwoi(pICwqZCp&T`Pg*~G@ zHG7FYB|f;_YwS7YtJ#a}N#(5BtL$0jt=Y@$Y4O?ZUT4p%zDg`0CMbtZtRQA6k4-Eg zrihPkV+}D!`D|hlF-bXXVihqMnmyy$i)3CXYoToZAxsaTw967m?oT)rHxs;qL9Ei=eeMRKEXu1>%TUt@Cu3_JY97_?sfDPClw+q>qGnQ_omz^TN;n)_Yf*D4-%c$? zO(xuqt<|X6ly|3=qoxzi$JTn(eCiia3sMs*2T!d?&8R#)wInsAa74D&q~=sUo?4We zR5^KSRccn{<*8+3P(~HoP zD5p=aLeHYSKD`V*jc{VN*P-W8Uxr?Yo=7=vnlUSFGo)&oSW_S==szSq8Fqm)HwipMS4b^2cVavrxcFP_L}sZIv+qUN>8eD z0`#i%tU511FH27=oSyA<>3P+Mq8GktdSaa;pjW16)_DSYX?kkm0Bx^L&#m(X^y2j7 z!VTJ9ot|Ci4d~_R>4h`2y*@p^`Uz+OXaYKifL4HJpz{c531|w!FMibUK5VT@6W1R;ryD6?hgpuY#9>ry-oY^*Zo8)HlZq!4uIr7Q7NX6P;(lOTkkS4&Qn$crH5Mf)|4) zqjN5JHF!2U?}C?urz4!d^?LAp)UU@2!V}Ut7`!4pBb|rAOTtro|(?m;H6D7o?6)^F^>(e4bM&I zYw+Umn=WX!v@bqNP!g_spe#$4{1>ybwtLE}pK;xmd3k&sTX2ykI$T&# zyZIvH#amBa=8W*_@$7Zp2rnN`U+0eS`tkggACQ0Fs&h#4=iNM#{Jd>CmxT9kexI99 z!uvO$XS>cR$>(+RO7eZS>)eujUpK!b&ttpJG0F3C^GtaE=6NQ|^G%lL?dF^C{>}SH z);TA6UvAz>-eUH@_wE zFj?ogBwo6CE{Ug6o$Hc#>*l-g{!KiN>YSIvYd7yD@jR+?UlQ-#{1@K8$p=xL1CxB= z=D{SNM0GAq@{OAh!}~Y+D5`T}lCRvnnB=pl&W%aFbMs?(|0W+sb&gE(rJE;{d>Ylc zGRe1Yz6|f*kszi0T}g)C+DNP3noL&ZSAc;pWru z{!Kj+)j2h(SKPds)H6|?Ta$Xn&9CA8n|dg!b8J#Cxp_9Jr=mL7CiRw^Z^QdH^;lHr z+@xM}^KMelMRo2?>OD9AhWBsk!Klu`NxkUi;iR67>Rg=En{GZ1@88s;QJs^MdezO# zNj)3YxjCtK9j7Pta8&2$q+WLObW%@8b*@h8Z8u+s_iyU)sLt6*z3%4iq@IuJ+?~|> zZvGDM-}D1fox_uU!Oi1IKM~crJn1*wd>-Dv=|`eErzic2o7aV{&nNvks!i|U-8^lNV3Px`s2&izTh=XglGf71^}bq-Ma zMK=#9{bW?<0;S({^MQE(rXP*!oS^ipZeCFO*{IG9O1~Rb4ioR+^utk|Bb0vG%@ayL z9o4x)>9^f{A>O~~$D=xDDE+#dHk-)@89SFQJq5+y}->Q;{6*vAu9Sp zRP+WnpNRKw^oXd=DT-d<<`qTHi0a&;=pAl;5%1sVAyJ)U6urdFGm4%P)wxE|Tikpj z-oMdfqB`d&dX1ZR6g?-ZbC06;INlZS-{?V6or4s;$jw8Fo)p!&NYR_zd?en#(W9a| zCnhL^i|U-E=yh)1 zQuMs2&RvS$=lEW{f1?LRbq*8n-{^&I9ux21=!sFC%M`uQ&1d5M8$B|rbDE-8x_M2} zGow1UDSD@y-^BYjdT3Pi(WvO9Zk|*0)TqvNir(txJMsRF9vkSKr|7kA-c$74K<7S1 z?{)K^c>hKZ4s;Gw^kO#;iuZ5y_MQ?WVp?LpBj}CNBRP<^$FDiO=pmU?5cf0vf zynmyI2RcV8dbyh?6+J!Bxl+;F-FzwDztQ6Zoii1^-p!keo*(Gksp$QIa>983#t#T| z4psaDH;;<Yir?ktXYu}x9~S5wt@vebo>u&{K<8@3Z*%jt zc>l(a3v|v_{5m&pD}G*}bGPF6IX)ln-}r%n&f$t*=;m?7PYiS}SNujdpNscz{K!D( zbj7c9^Sa_^20FJZey5w?#rrpYXrObv;+ML4Uhz`{o$D39)y?*f*g{*50T=p3;4#cm#0{NzCVBtor4x$#LYtsPZH={wD2ZwK3aH` zK!h5;-Z{fiLodXwM%*}%f zPZsE0xbS9fK3sUTKr0;pN;sx$ty>&Xo&q=jO|W z#|w1MTzEYjZ;Q<4kLl<7q&7%uX80cKO@P=+aU3kPm=hTH)bo1)M zGX^@hF1(|gUl$%S&^dPDCEYx`@RWhhwF__Q=G%qG40O(2cuhC&E<9(TbML}?y7_nE zK?9wG7hcrO!wXLu=v=(;rfxo7c+^1WxIV+bk1IQT{mwpJa3?L_rm+S`8eT$1D(ScUf9j!3r`&AT)yzeZa!al zNozPjTtK=|w_ z<2OL~?rHx4HXlA^{0InN-ti|OeEO8}DW&9Gzd;`Znfy_rp89xOwU%~NLAoCeg#&3blcX0d{$b5*D z@nazKB^-YSGM^%4{2Iu73&+2K%*RL>KL;{j!|`_@^Epz+?}5zsaQq+0e2|p!gCO%o z9DfKhpCo1cBFKCb$3KG1M@bn!2{K>B@s}X;SyIMtg3Nbu{3pnKn3VCOz;FL}XXf}* zkohzz<5xlE+c^FeWIj&H_*szoI*z{una`6leivlEk2Akj<^!dS9|oB( zmqF$mIsO@BK2pl~X^{C!j=u((&y+HL8)UwdW!9DfrspD$(nPRM*e$Nz-P2TU116f$4X@kb%^2~)-|h0Hf}{8Pw$#FX(< zA@da-e-$#HF=hN#$b3h~e}&A4Oc_5GGGEg1XCd<`Q^v1_%(ry>TkzXIzR9GFp9`6< z>G->l`J5@^_d@1-I{q(YK4{AL!I1f)jz0{UPnt4*F=W1};~zujqo$0X44JR$_{)&_ ztSRF+L*~0W{xf7gY|8l2komG{e;W3D+LZCDA@gk={~9tMH)Z^6$b4PL--gWRO&Px% zGT+znzajI1Q^pU6%ole2amak)l<~_U^Nk(<95Np{W&Cu=d}YU9hs3nKH)9seLQA3bIKgvfk#$6tudXHOZwAu`|H@gE}d;Zw$sh|HIF z{E6_}KfbA_j9(F%Z}0dQk@@&3<7Y(X>pT8NWIlh&_#Kh?{*M2Va|;%0E`jkwV%7~Y z^W*y_AFH_*#xKdhE!S)Ahgq+t>drrEE{gF}a_Zwbnj2&MmE3Y|x#sE^za@`%?xwjz z#_xeOY^CNh89yc)FKO4@D&x=Op0A&%xn9PvN%cV9~86Bs_}=i|9LNIuBq{ha>pa@Xzr`=kMhV% zpJ*&JvtrgMHU3u2x}?VMidl!$_?IyAILv$uGq1wTk1+Eb%zOni@4(C-F!KNmpWpEE z4Zq&-obMBI zJ~`hDbx(J@z!~NA>*<0K0(H7=lNd7 zbLV+m#(U@aSFQ)n^Qc@eoaaNio;c5Ia=me$pX7SvJkQAW%6Yz!>zQ-EFV{Qg{#&kx z&i$}lFP-~Sxt==ri*mhn?%(8k?A%Yu_1d|=k?Xm0zaiIq=lXB16X1-TSdd~L?<0s1aIgQS< zKI&e9rGGPmeDUJR-2X!a`{PRXz<%(22DI?#DaFgN?~4R(g4+Ky|CEoo4?&^8ukbg# z0Y;X;6WI?;DPZdUAd~6Q`;o(-4JNJF02Dcaz*YX?$Y$<+Ay{0U{{{kc`;gPXkBb?u z^2XuM1nlJxV8^ebk-!gg_Jdroo^f6oJ{rNk3RO^wDhpf_{78!d<$oRp3|#Byq5f+b z`SoSDLN_E33Une2HF-EfgWUJ`!ZtK~L<{tVJ0sfC(A3DEn8sxRC~Atik2H!BN2*Y* zq!=i80oe@I=GhsD6fDqUi7n zNT@&Z4TuGYv5@PExX*+dna%YkA;dI}U11EgYeP3j0_a*riEb6TWvCobl;}~RTTM?W zN~~9*+eC^KGFyf2rv zT}_-ew9;qM;zg zgkF=*)}l%*wlxnOrvI=WhOOlvhNE4opbAno{6TcYiGk2+Uxc+2JDl-0`6N>+#;k|d z`0`HGMF_;+qkfIA#Fitm5DUDW4~bfJ-*yGw0>@ES2k?FPll4Z*h`ex8T$pX5+1+a z==Y8_^Y{(El6Up-OJlzUhK@D%%VHZ@t;hLtSUITX*b~%m@`W$a_6Ns!UWI<>E9R-> zuXxB8JCzAs;Ty_x#9#5KFV?|;t9|*~aD>0&`Cx1=i}X`p;d~_RuXrgKo5wh>_vPjx zEq}$If~bF<3U(tsgu`8pq(y0@e%5v1$1o_do{^tKO>*{p$aQ90E?I&yT@Ba6mX8m4rGl@u%w3s zV!uNCp`9)1ArYj=f`AXdZzo$M>5v9BT$ z`#Ia-6km*&317vy*kmSss&9zhPxp?!&G=69P3h6`EsI?V44v*9d6v%V!Lj8m&@#_nWc&$e^muei*L zeVfgFjva-+;tDIao@t(I0)Aq}e#VpOTPENp9KuqZX9DiDVs$*^d=v0XD|QI`?*;bx zi0*2sJYK1pD_y4}Y?+zTa@dylH*!pk*b=(f7d{37v7hr?yVO@kfz4OIbN_q3(lfQZ zLFI8&r=X)6t?~v?W}ZkQkK7VE-sevtpp2tV=t5r}8@KFN2nl`Pm&a7?^dC0|m8$T^ zXc;RMV9+Rw!+`GH=wQ!bKNR3S#VBhV!{xLIvSI@tA|#J}uneNkfKQFSjwPt_$2js? z*63py!&Lw1Nm}#;0vp*oB7rqXa?Dm77qmtrOW_lJpT~iJWN_p9Y)Yi3p2S@Xt9`@f8fYfWj%Xx!5Y&6+-YT{K?w{ z9nXNB2C%cuuY$KhD1Qqnkz6vM@2l`+|-f(vOf9Z}`X7{zcgIU2imek~PT zOPiO`M{{-^MTOXW&#^(7&Z13>HoK3aLTv7JY{Dvd18ugT5_0B`qC#w5b8LpF;8V2u zJ+r)U6cu8VgO;=NgUZ=To7Jf2oW-N4fX(G7!4&N3%89AqDD0OXie}B(uax0pvcEBz zs)F-qayeUJMJdC@q{o;fRIrIABbb>3OBpUE7aEh43Z6ofDKz<7DZ|C&cI@i>ZbbcE zO`FeYb9gBgV)F-Mv(2Z1kJ4rfGu%{4h1gg)7432dRd5S!PGtSHmQo=$;~kqk6)b^J zKA&}SL@5bnO`c=_ zTUW|(F}cy0p#FY9lRX&AF{KO_lc$Xd>hFGtESC+=sY=RmQo=$Nyi5Dw~{u$U>%=bN`=^*;n<-5 zHqd5o3=KKwl~Q3@1&(RyrIl(by)DUT}ViX_yS>6Pm^NC@=zJW#pK7>)$MgF`ujz+>1SDf zT}Fl2{My*0U~?yJE?|a#Q$~f@d|+(C7%yI;%@r*7Gi6kW&9FjA>%{^U3_vKqhWUBE zj0&;Y)!3wlsNh7}G|=XcWmJew19o+PN3$=biH})+tBm1dveB5J)w^g?&NKAAGKQno zA7kD=bXV04=7260yo?9@l8wK$jNuaJlg8wI6}*oom$OHFQO0mF`3rV+ZN7+_dL6>( z9M+W2Dx*e>Mim(&48M60M)%VwY?VXem(d3? zFT*SuR!2Y1L2I}X^(cG3iE-Ol6+DqK-pn&$q*Y1{VjRi-Q)WaxvOMTM<`y2~V?B|)6|G-v!8B^z}-~tGvuVN!jLwXR9ne$%y+$2N{tvL9V67oN*X=Pk!LTflp54W zAtT<~w2tlt7eQm{<8&T!FI#=7RZ0co<@NYZV}ttm32i1b+I_83D#YfG*mde-GmW05 z(Q>Pl8Zio$7$elj$23A40fW|j`LN~sZ}WsVW*V;+sJVp|_% zl~N-{{f-gpqlHH2u*V&0l~RNHn89{!$mro$L!;{hhg`%%mav{%tWqi@-bYUn})%Ah9&)`cmdWvRmr)SH=y#c;qpVVDV8q_Io7-p? z8lAyr?6*p(v8)OXUb%}3gQ#!3Quu(@D|VgYI(cV&?gYbbW@6t#0PZY9O@9C1CxdmZr-id!A=Zi>sw z&9N_2eA5y6IwMz&GumA!#wHkXKZ=#R81X2IOKOdH0mXJlyp`f5j`%FahaB;56bq)A zW6N=SkbANtE~0qobfZ0j;s-N~cs9lGu14Gmm%QAPdD24T7Em1Hh-)bB;)rKboaKnu zQQX%Ne?xJ-BYr~hhmJTB7nR(3bta)bC|)$*h>a8r>Wz3Z#o>;49>uYacr(RGj`%x@ zGad1Biu*X?P8j@iyBu*5#XB5v6~#jqm~<~?<=ni`bd_r;KJ19MQGDMKAD}pWkuiRX z;_Z(3GR3?1GTJQ^?^|rdzfpW>Un90K8?US~VlTxH4>RIL6hp11$$ms}M5hrSr8s5X zNa@edQQZ9)Bfd?s_xNF={gmP@ju^pEpZmEZ#wc#vXpARN44h!Z85A2%H{#bQHlAg~ zHi|7jG2%BVe(TOLlJ0*|{Fx*Emf}N>_*aVi++~d87=3fU<%kO@o}V(>BPd>cj}eci zcV136~$qjhe{ESp*Zq4MtcUu zQO_Fjrxd5WV5y(P#upUl`3uSl3UN*F zjZ=AfdqBjipW(`1Feh)fyj}Aaqa=7it~D5!gA)`(LPHS3op3QM=VEw@$RR=dkery6 zmuJUdu`Z$+5$0Le;$nv9?}X^4Vi=7UXV~MVO*#X!F`5ryf_O_`Z21e^5f{NQVsc8u zq1qytPP%xQ+8OyP8D{OAZznn|sLL?iu|%Gk8N3$PiRvOSu2Ls8u^1t_6mg^!Qp7U% z@pz(Pii~&kbXUCd@>yGB0w~8Gd8|X^RE{4z5q6_6Ro55L|11bxuLBu(b%)5SM{xLYiVgu)^{aa z6E)Sf(-TKct5J#d$WliWs;99psS-WeW7Da)k7q#QsG1q5*S0mCjqQo1{#MoBNg>%1 z=eKgVHB(dgLe|>bb_^0}ZEr+&vXnm2+O{FtlCblhKrGX06MgQQ)79pVxu>Y@yiGp6rz3*UxEK)tl_;ZD?+9>}c$%u4!oP>N#>+ zL;b!7EIuGH!^VaM2P|t?*3)%FvbnFfVXyl7jG`jPcD3}iboFP}0<+oLjc(8f?Ce$O zJzYn(CDGR!+u104qF<=Qo^5MbeThV0M`C?TX~)&qNzBx{kI^m1yhe?(az^y8C)mqBFUnuhsN8c3$>UWU^)^ z6X-dY@ogJ2;z9OxJYB7=y~)h_Wh zhx(mevumxpycuV;KB2ddgVmhuNcOBrb~YcKq2|%-d-Jnn0`d zCY$Z%J6d-dTuRW0oh{x3bdlZVs+}R#z*aV8u?xm?rKhiJeRHpzA6Yt$oU-0FLaZ4n z>)NA{t9*9h5{Y$nw;Mj!bAdK?3 zAXJ-%=1J=A#CpiY0F4VI&TV%;(WArq=C$ZmT}{2|K`X;Zch^L7dsi=p`9yC^8?L!+ znepiUhVr;N0{XCYIDL^;i8YNK9gX_Rf<0WV&G^BA(VZubbM`shgkFJB6_@Sywq6WM z9UL(eiB(H+EKtUP-gRv)3hkxO9Q(la&AL)e_3#!B_GVx)L-Typ6M~!3`#M1qkq8s( zaIHX7I~NsHnQL&cD}y6yTWh4&7FXXfBJ zN#_~&Q+CbcI);vxrQTU3OZTteC$UncN8VHwwCW z*|LM@O5gtU;(X!#g}YMhZsYC}9MqX6Pd&5~I&2gAQ+rnv?or&=G&al8Nqy2t=V(hN zamSr`>9MN=XG3Fq`cl>3+25PQtwU#WJ+9&F`fwJa2Q+Trr7O`sb9$q`qPa7LfqlF4 zT91hKolaBxk^0668P`|rz7E8LGccph*_>G}qMiC|T#x$0q4=vW?unM(uEbhgmvv{> zQ8A+#_h@>=aP`)VOPA}0RNuO-N%o;alk8|{&X$%Pw3QwwdYKfe9pk!l@|lxm@MdNf z+|{P5h=CYNbX-{uhLPYSEpjv!k&cI%J1ARJe_v6Q9V-{!0DOjQj5R zd^|WWln3WHZn&G1y}fvPiqEdhc!r+zRqqni{MmReYvhx+vZ}Bftha9%_MNUm(eS=G zzTD8zK#4WXiup^e5!Ohn%o=5l@s;z@KVx$T1k?xH+)6*6K3$t%UND#-KOZ+;n;%b_ zc;n>SGG9gDqmf6Chfde#$J1u!@qGGBZ+;c_=)QNks7H_2r>@PfiamO~>~d{>yoAcEKfaVoZ+>Vq^_h}i4fp7W zrw_)SU&TE7m`7jg(U*GkBRu*M9{os<9;AKO=2vANeVI$k{EhPHM|t$4J$n5q(6RBW zF&_OGN5>t%8tc)I_2}asecYqp$)n%Nqc8X9%RTxEkG{gAALr4J^XSKW^y5AH2_F3f zkA7#5erJzCw;f=*hxQ zZ+;n8zy zPI~jJc^>_|v=V!MRp-&ydGzx=`uQIHo*w<49(}z>U+>W`@aPwK^b0-ug&zGPkA9Iy zzn4e9mq)+1N58j6zu2Q+?9ngr=$Cl(`*`&Gc=Ss>`lTNIz8?L)9{qkE{eB+({vQ4Q z9{nnkA9U$f1pQyphtg@M}LqPYaacf9{r&neS=3&+Fp9|tHaU)_WUa0kym@Nhf;4T^9- ze2S6d)bFA$HgX;19Q9)(>+~n9JB^H6(<0n&KVoDbS!YmP+zUiG_o%L z5cM4+>-4JB)kdzPeN^3SWS!nrb-$5yehbtSM%L+7sy`Z8=Qm%yYh)eY4E0%tT&u!3 zPHzKDZ>B2Akf*7gGUVxMa)w-^W*E7S$A3-jW8^sHgH)rDb$(YV&db!BF3+LrEFx_+UOBy5zf|g zL|(1sVd_eeCu(`9xa8BYevSSW)bdBJ~J{Nor`cb7X%RzH=Uoo zRJq6lIzM};nIhi*8J1-)-;>i3=q-)5nb!Wl; zu;9c1SjUmVh z%g696ybSr^=g!`CC%Wz^ZVTN*+yU$wZkc_;EweMYWzVUM=67q|-PmSY3>n;=~|Fn)ScA1g@KC`c1dkRxUGO5os|0TrykGEX!A}GOxTj+J#e(I6HG-=J zI|PptJWudfg1-~|L@nZh2<|7C5bPE_LGV1m z8F*GJn-BiJF> zCwP(|C!I0g9|=A#NDmPVABN9z#My#}3T_nqp&+OG)9xKXx@4kUE4WHDGjH zuLy>twmeyIf59HX3k7czd`@tiUi0JYVn@!QTshAy|$Jg)W!ifr3fFKEaCx zuNM5Z;PZm-2!1A*Gt`c^RB&g(nSzH39wB(P;EjUM2!1ZO6Fy@ypNj;K6g)=o`+~m^ zd_yoFpEr42jo^WT#|oY)c%9&H1pgv93KviwKVR?=BK%^lAr7-tKe5D8CliY;bv|*Z zrG7vxvebVO3oUgIafqcJCl*-h1!B}v?-KJZ^*J#QPB!p4)rX7TNMeqqCJ`f+noSH_ zYA<5QQU?-)mP!%>mg*z=Ep-ynXQ}gucoBCwQCaE+;x?sHL|j}SBYvUOABdmBH3adm zO8u4i877C|v#sw_+&2)n!qE@$FG|fKeu8!&eyr3g;zvrg5I+RVo%m;^P9%Py)VGLR zl)8-gzEal{-@|xMd{?Po6aS>t^Tc;>o)h0z>NDb7m`;dy6uvhx?SuG+Qacl0S868l zHJmTRSCv{xd<8ss;>%#z6aT2x3B;G+;fna8Qk#f)fq5PA4@%ud#LdT}#OL5MhWM;f zZxes7)ThMXVJZ!7pnT6@J__--aEL~HTB#Ytr<7Vid{U_ch`&*)iTH$4M-ewGH9&k^ zsdI>rDfNBgua){K@li}=B|f6mBgBW5dY1SrrQRYwq|{d8gP7Yh68HeFFU0$m8c+Ns zT=Ed_Q>vc$3*5I6@5QSP;yp@r6H{g`okJzW&4T(1jw0Py!O+C}8q%7Kuy3MA?v&9b5#$t-{^rrS^Y2k*oFi_X=e+i)22Blz4VIes9Ct-I zSiv&Sb@u^-B$7Fbm=}Wco%(b__*&6aayrme^Coc5?acHmN$;`xZKMgzc<;Pj;8Cum z9ZS-cjb+A51Ts_yQ|K2wgDVG%(sjmWBqeW*vPMYVVDY6-$BgLgcT!nnv+3E{R2d!1 z9UT>eme*Del0Wx&krAW3HOra}>IR9=HL|#)lQ(JEVv`qE*;E-LxjQ=hm7A-pY_A+7 zf9_MmeGtM2tw60CBtF-;=8jHYCT1&?ytB)uvZnwI)~RjnApJA_qJGeb2Wx75=pgN; zb%Qp8)(%#qTB)li*Z0cWQlc;6Cv8f4jl5qAq+D4F~*I;t07_@VGuk7P)PE~Ox zDW;sNs`)GSt!nJU^rEKzK2B!+d$%$e;+2_x&&Xq@^N(x8>ny$Pguk@IYbd>W?Wp6n zGk$nw@uhZCV8dff{5n1(ARMou^j43*8FsXZYnA?E><)#LVONd-W<)k)*8@4jZWja$ zh!Mcpor(PnyK7uZ*Y4$ByXz28ho5XFzS|*Z#D`}ke8P4%V~0nIOgp|X)giX2vBRU2 z#}2U@C3I#NkARtWbaz>YK-r8P9%(b}_Jm!Q{E_34QH~X`(;;?*CO-OB%CrMRy1=BG z&L6$ky6qO=#pq=Wkj=zLE{NOi)kZ%UDe2AFkrU#!%Wv{){(!MGcDH)$9^L3y@IjUdp)CCGvW)p zhJY;N%iUhPcagtzF`W8)#$$If>~sQRYs$ODYxiDuyF47=F7L_j!!FDDOD|p-c5o-= zWD04Ubocby`4Lc;E{L%^+-p~l0JOQ;j2*c*8R;%WK-^fR)4kAZmqb98dcMJH*MWe6 z?c;mYYxgb!vgGeouig6y$dbP=ymmwI0V7NP;P)i6yfFl1$zPS%?mOA->b!O_eDJ8- zzPzivb_c;OOS(sR?VibQcbwPmAPg>9(*2g#?mMu{lI~SryI4e#4{0`3uiozP*qsg! zm*iEN&FpUW*qv38J-*jGcIQq;qHz;jy8rQel)ImvyASN}t-)+2-7-{HhTTE1!#hQ@ z8N1nDyDr!nC5+APGOt~4L=7+j*^FJg$F7jxGI0u<&DfppwcCLBj1kb-(IsL=IbfG< z-2J)7?jG2!&Jy3#9=rI_$X{LB(4_mG*Nz{;veaK5x{*77@h4#C%AkpFqSwyChcK9$ z&Dhm>?Q&q3rT!YccKNVFp3P?B+u*eu3cD=rc8=GsI45iUUE{GEfZaVNQJ_ipeve&U z3DO-%8ydS8ymlABE=&FW)ob@l*sb0^zEaewyFKd0kg!4?FyKvUF!bo~lODtq3D?pXo9i*LmVQ`PE$Y2NMbO zX7?VCUE}My?%~C;yVH~IpGxy|I!t#pekNTyn>TSISRIY{>RtWM=;(r;`{oq8^UYi} z8sD1DMjd}#4Zv;p`;T+gI%6a@)V~iq3{Txgwf`r%m`RY{Xv2-@%8oi6cHQ`9y9VL- zETqd(2t;)5;ZAK0=c!+~&Px*?4$ZLp2=zjj`erkBQ>WL)-CNC!nYGn3s;hUM9gkOQ zh5fgtx_ai!neli{%}lsY;kG(=#MmtQO}Om;`{AP0~Wpe%CM&?H5y(Z*8eh zynSB5PMcrcy7nIRL7~53(fUOPYz;IVur+__w5_2_r)@1bEBJPPFz|MMVBy<2!3A$e z0@l3#)zeq|VIBG)5_;na^-e*d_0D6~&@Fyn{^lD#^;PE$SaZVI3svtkVC^z0b;GB* z)!!Jn>&-1EDSTbqwrwrOB)fhC))&ZRK3C8=4f!(-ZSsxvq&UuD6(rKL{l7%x`Dc~Z zLyh&M_QF9vU$__s{zDMtch->NnneEdc*OoA*w|PzY6c{%C)JM_u%6TkB${4NYAz3+ z&7gSkEbfyl9^5gTZ3RIW0Fq%kU9AmD=pJ4fjhY=JEY{uVEKMt_`bCHvfEG6{- zgYBiH!n}HPmC)7se07ndSDyHBF~e0ZE1?p5d9=q=>`3T` zIjbN?@kLyPt_+`oU|)rbeoXP2AihUK#8OgkGQw;9Jk&p%``4GTvlaw`fqsOc62k}` z!hJs%!-)*nl~afhx~eoXHS!@8(HHP1Qd7)*q`{@6BDIoYAew`ML~8Tw3`C+oLOn!k zOKdSedOQ!UEwe?vlvHF|-lsaE5>(VTv6p)S{^X$Pb=h#O+XXR>i_D7fNjZ8iBiJ>^ zjzC36QJf=UAj)?)k=;a$MDtmKxgzFA%b1tlMJ$Z|n&KWJmPB9SvGYVMjXunn>qHzC z{g6@37ZFQI@yR=4MV3VV#9VDf79;!Qa-X%{LUCyhMJ_xNoq$Gb!9WWHEG2b4vl{7-kOmh$34bE%iZmq-2~A}-*PDdUJnVIa z>yZ4~$jy;F9Lc4mBDV~c1Gtn_TUmFZ*aqV*J? zD&o2|z6yIOsmL=D)q-dlYw}q+c4_otw$gLCU^u{dS@fsOLuhJ%S~AwSZ?ZmXeBgF`?I_vvDb@Q=sRe!}K5amSJ7|!*H|<2d*Jh4bR7s69bXe zz6fh4*35XZloajIbz%ut29}c2WW0(%jORY&5?hYME@#46O3Ie=V^1NG2$qtvk1ve< zh%%OvdH@$DE+xeYCJ`(pW$UYBTabqcmXdm2>!-(7GCeFMW$S0h9;1wgw zrKDInTuSP5);gAwx?I~I9OHQv!BSE@mGn|lQyC$alHxg{my#OJ04yaH!mW^AO6u2) z5=%*O5eYw+lKKJTz*15}wFQ=v3I=#8*o{Ol{H{jQA~Of0LL`T^cG|;KZ2#CPJ=~E zkKI^GiUNDYe$Ym+loS)g6(YtJ=^|K4N_qrRWWj?0MqgTocncy}O6oU^Y9n$P!BSEb z7}fba6iZ3jawv8UqjoJNmAeFKybNQ>_K3}q0bh6mnkKfGQDG@5Ud(Mf-%z_9 z1F<$12un%Pm`h2$#x}rGQoKxXDJhN{5iBKTmtybODU1(GNgc1_TNaxPj9@9L^L19S zq!^BiU@0m4gj*YXndxCEDO>K2Vg8$nU@0kE-ViII9!p8hMEV@jW32HAmXcbe1F)3T z_h^Boq?iM}l+@9*z*16-LN6s1XCASXlpTPjq+VsAu#}V?fTg7HMps3!l$0HSrKH|s zHnEhH9e|~zA}lwSlCo35Qc}77h=jS)bvnY9nJF!YZTUbWb1A6^mXbOF0kIk;kENt2 zu+F*2Sp-W-eM`$5;LaV{p`fE0t#a8oJds2mxg~<7q#i&(8AqK6mXc!QmVLxLVks%6 zYN!8Ob5JSP(t@cK3@~Vv#bH4AZgjAhu^$ZZL?31GKMc_mQ3u8@yk(4 z6~|9man5%|yrh8VU@58nU}afhkOq|xOG%v%oA5Zqef3R6q`N;QyNX?p6bREpbAux_#c{g)9yXb0!t%AIeVShv7)~-XZ#s0nc z-GyJpUbNdyhkXQ@L&do6#huEUTgdnZkX$={LhD}=5Szz<=y2rFS$M?vP2 z9|)U&V)hSBZ>$Q$t+&jQvWQ^*7U z92VrlJrkB7@Y~Q{fZqhJpKv>NZpCkBT218gB~Lkx&0sE zrw`9#tKdiCqJ8*yNEP^D+oc8B@_ho&PyQrgn!KFiU#xsBT#kJCwp#hj^Avco1TWLd zp@5FXx_A2uUll5{R#=7TGQPjdW4Lh@9x|@N!bJcd_U^YV@B^qupItf5w2=sSCAKjh^>ms53L=+-^agzzG6 ztQQwc7+i^`eX2{?_|aBP@e1p3*v5!rY3s{)_;x<(Ef*dL`8u0Kn#Z>ePjngrB` z)-sMkX0v$ifv0R)BrRhbj-REL6L?;M=uB9EpI@yDY~s#-b~s_B-d#>O96!H0%D0I- zEw&KY#GOuC2)WZmkUh7_QY(0iZ!)*SF+#O*W3HG1yl_xT>)`;;P2(d?#O)PIe9= z@*yIC-hA%RJ`+l}VG2{bwJj@KZvl7caV9kAgbqQGLPY}u$Bpdm4%Lm{$w}HCw^;^D zUxM_ZmLANR#-PVp7RP(`sF3>eD;z`3=Ku18={m@6Tvwv$KyQq}Z04g7gT8X;v&K%` zsSb$D9)BzaQ!^X8l?h|_a&PYAdA0GY3M8@JN&*=!ArI*9?uIwQMdDQ$#GwrD_x~L$ z1N>*zfh=n=*uDoq2u$>KkwaJ2j2_KN%4Q`1wB&Z{4WNzb=o0Q&?S%v2=#uLVV0>`a z8^As+?DYn47iQKQK(MSZz~K$kM}oRD`ggU0ImJPLaWH2XptK}th5S7T^A}WA1@rww z;@CZENiZ0iQCwU+yf~O2vMQ(YAA+U_e8Dojb+dy0;UxhJI{&lB@z|a!X#D=0{PB2b zr;r6zFy#N^ahA5f$hI#IRaM!FcX>?6f4DU_=nwfPRQYo#TU9t{d~j^Y3J&3J1#LE1 zaZl(F1V@8o#|MYZ)kaomm@kMi+wl%-uWFFFU_q9(2?kwmz`MGD_TdcnB^;01O9T9O zIR0lN)60KWxBi2B@~5|CJ8O>je)KHu`q%BOe@D*v5d$VZBW3zp&G5dT_LiODkaloy z`w825zS9!6qkKA$rB{60IlIeYJ-dGTbbyD~9r&IXC$L^O^2X)+|4&}t|Hbax9T)A| z#kKfk-`?@MJqqpEp?cyU@SToQ?8sgE-{m1)_ZZtFdJ_l61N538#)&yjry7Mnboz{* z<@G{t9F8Y!KjX%=c-otIH|hP|2lO=C&a!cyC~eBIdqZuatub@q81H3PdtXj>Z;bZv zJ#8G1e^saAwiD!k)PZ;TE#!WYR-Cz#6#UC{NR}bo1TYHAj9K4LT>wnhAweeyNkNp1^9aiHF1ioNy+h!@> zaRvEN6?ffb@+Nc7f>9@jPYInGJS}j#{|w*RxKmN{r{Rw{x#nxC;H-s}`~ENcw;qao zq&M5&weuw6y78tB{aw2^`mc6x^jGcP=zrS1(Vw(?qkm}kMt{%ljsBb68~r`IH~MET zMF8uTbv~5&&AcdL)EL)C|5Ta5e5S!|Ki)VpM?PeOF%yRgjvzugo(QhN6bWY&(r&ik zBEfwHR|u{aObYf29wT^y;5mX92wo=m6TzPgrUai5#PnL7k5>fW7sP$4T^_+%f{O$X z6l@aYs`f0;iGu8?l)o!@o8W_j?lLgNg{4c?K1RocCK~Pg<5g$KSF<$zqBQ6vqIe>CfuwU>L!3zbi6uepRe!-^& zUlaUTFo=%Mc!vp&7vvjroxUJneNm?WI3mAa6UlibUMx5lr#$7wf~2leUL&|(@B+af z2;M083&D2a5AizHn8FoE5VB>V;<%6&5tw>^ zIU?*{75PoU4~d9ptLOu;VR<5gMS{ZwM-uU?5SdGF(taut`QJluA3+SeI)0qi8WF6K zS2CtMPH>{&R6%_mfu0|QXh-G}akXHJ;E{q|g1pYr?l{4d1Wyw@Tkt%=?+WsDAdkCR z@F#-z3f?dHsNiP7j|8_0!fl3*2ktdAl8nT7;l@Mb2tjg~7(PL87r_~Vy9(9`E)d*T zaJk^Yf(?QLf+q`pL+~8Iiv%wfyi)MTg8X{NeBB~=m*BmE4+}mf__QDyIXv!V!Pf=f z7u56x==o8OcKZ4Vir{hl;6_x~$c&-VbdQF`{r-O3o8<(*& zJ2X9E)XW!6hYUVvG;Pz0b!aiM^eavxEkiw^Yw7w2{EyEeWxI1@J8{f08{3`RLj0IN zvvE9WXD5)&=;lMlB~#T&_{6dJ_>9PTpN;OJpD@^mmg8rR!LBOBJ@>Kbt7bF0W(1gh z>dr@>;XR+(j4puyce>riD}((AfPMC-gdmna$YUfdKBCZ7p~; z>@#LF{e|vx-1)oBRez`=Cw~uNAI;fqj=$6spGk}8>KraIj0S%Y!2Yip;+xqUe|yA)|+%iv~j zxtYxDs?A_!2dsC_&M(=Tb6m;R=-icHXP0aZw%5NMt_W_~xNvfP{oA4X`C9|KH7*Rm z_HE6_CKr3i=5s&wSD&>N)iWmt`(f-`)#PKJ`)MBbebrm;I&0BeZ>ZE4yhqYm2v{GZ z!1=4udKV&qgR*<`MWOIdip@Zv-wJ((6WMP?jwjfBY`-rYMW^z)_}KnHP(Lf3MJt<+ z?GJ=WlJrM{9jJPLBzy=G6+Sj}{H8~DUn)>CbQ1Rugt73k>AuVGvHdn5+qXR*y9)_@K1_Z! zd~9De_cQs}sJLyYbj`>1ZGztLvEM>^4j-G3-GlP6{V0fwk9|3E?c!sf!bAT-J~k;( z4j=n=Mv&%XPo|jWV;56Q^RWXg!JvHX2br}rANvCo(Z$F91*1yyu{qmza6a~*S?Dw$ z`*4abJ~p3o-F$5NLH`H%*t)*ceC#Kfvos(3dFJ~o^Ra)-tQtP{u`Fbok4+by8GLN^ zy27s``G1~|&1n;VHy`_tEMl6EeFDWn`Pi2**J(cXLMHST`Pl!(sM36FQhWyIV-I6Z zruo>Hv6a$%Y&|a_&BvZZ<1`H8_}JYnkc*G~BHO^l$L35EHy`_C#s%eKRfGeC$6mn{GZfsbv2uK6V|Gck!{WW}SUC zJ~l@khmZXp^EfCU`y815tN7T{S%Nel`z9vr@UcO=8xKA1$GB?A7|u!vTD(Ve_}EXt zeq;PcsB{&_Pg(JA;Q;WlpF)s}j~&PHzEiBBe5whLK|DL)W1oOS4IldmMvBe454W=A zXCpP?V^2U}9KZ4-5ScZ*keuKq$SWB38Dp^d*qb3gj9lQ(!G3^ z^3C$)QJBoNoP4u=d1;dL9N*tTk`}gep3QFcr#aIB*^MB({~<}+oL~#j=Ocv>4gxU6 zG9h>iA9&O-YiCVo9xc>m9X>CAE*|^G1VAp{BQFm;;&gOlCxYTU3hzVWdIv4J)BhMr z8h!3dDAL>0p)prO)32qxe+N67eV6QLqVB-z>wF*R+4g`8el(#KKbs%TJstuD{+dlw zq|-!cn+(U|aBQ;!cY#_&24~<(n(d zwkKo|lnExMD_lo#(9s)Da-5Tv{^1X|5Prg%<}SwqOC8P(GCE;Lb9brMtRU=%pJqpM zhuK8pCbwiqr!#vvlzJPCC~Z<)#)SFvtG>QXE@6XPI8F<*VP>h71m+V*bZ<)6=(2Q; zf-1cX2Fw~fLPcCP3aWHEleE#BrE|b`@~OUF3DmuW8Ithz>2^HGnD7GQGC4MFa-cB@ zxD7U%(4Z4K5#yL zo5TM^tfP=MpUz&uWKwr{BQQ<=s_5pugdZFKWyiT8)na()Uc+rKi;R8 zxW`Mqcv6=Vtj4C_3I+K-LrM_WyRc%#GLtAHadw)w({WoyH zGnp*2{+G$l!-r{}b3eJtd2zCf4+p!sSksf=aOlisA^-WHCI_p6WiVNy|Juanci|Ob zs^K+XXw#Q_ZTfQ2+zk5i7(-vKanqO6p*DSajL?^Bz`h=aJRKVM!E^urAct9)jI%aO zCz0{rk`gZJwRLs&#w%M}yDOW! zI{SJWoBMVL16(D#XY{InckXh==Mhj#F`1&hjXc+m{&uomS1s-8Tmx)v!LZtq=v~*= z!ZKxJGB>v;8$0{Ejd5aKvZohS<`}gH9^Sf<&OWz_h?B9{E%;#D@>9Kyd<12H}09`qA5Vao($<4tF z0?kEcnaN4!w|%1KD&w`lc*-!^MZ)<&M*Td&MS}YZt`J-;m=xrb7LU_hW#9=SpCfpI z;AMh85!75|*r!B(LQr#+5&nwE?+a?KGQx{cAxuwmm4TY83_MW6HCGw3<|+d6ZS#y;k?<=zADnsrNS#y;ke^X@5Rfep&%0SIk25PP{P;-@mnyU=dTxFo< zDg!lF8K}9+K+RPKYOXR+bCrP=xpsavR~d4>$eODRS#yCQPdWZ4^ zK|Q`ht`V7^Sg6u*xPf0Rp{ zlH>0a^m2)xk?`jPzl=-#x!CdjAM>SMVF9Be^Mez^^-DdV;S|r2@I3_=3G%}e?GF=7 z3bqOIBNX+=3-YrQWxDqv>gyYDv&foTjQJb<{zU!Tf*78${$je{LezTGuQB{-+4S#H zk@c%i#8V^j@Lq|Wd!zs7IKi{rEZ_f&lwehc`aqY^p9laMJWI-`HofhHzqI39aBkCW zaQ;%qjb9Mi7GGvJ1vcJv+Yx3qbJx890VZzhE~Cswmd)tuAY-^xL~gUkDD@`Vo%gc< zeA%({wG3#E!LGU-arK!(x^zvhecBBJCpc~j<cn?4_RTTaRjUx+MDECDbOVsx@ohzX)d*vJtVWZ+ zZ)4vagI)D?#P?d3dN~g|cYG7k;4CNO!)fKj_XF%RKBmR32?n?FB$kaj{(dTG>_*^( z&Bh7lbAUU4=fch$1C>sfcnf~+{8b}=g$QH*P$VaR4`Lt9*$vR!J&4cUr%hT!S2d`Q zU>8T=aD*4($NFRZOw-jpR0;ZDIl|0l;^Q%HyE^2L&oX8+c2j3oYlg4+^QD~N>Y7=# z+W5;k!Jk*?)G|21-8X$ZGIjH&cPAaAS;6qYJY&(ycLT?4eeaE9tlihVciJ&z0M{dA z<-1`WN-xa}uZO(y-H;Bm-G_fVCIw-8C&P0Oxt|1cs83NP3o%yKe zKMb+?rxY)Q#y=mi`KwF#DH8qz>2%IdQbnMA#El3F25!UO&>R?9+KF;-N&yr0Hy|X~ zqxZwVfqe-6oClzY1cF!j`8=D$2{^&4^M8xL9A1EfKQ3mt?ZI;x_VQ>?{&4VzIlDuS za+&$ymEofi3@43IlHG#W1Ygl2{5k&^c?(|a=b`?s_!GRo>?-K!&-pNjsH`J##1QWL zZ^T}BxUP^w-Yt}dr$%_U5j}&7nqqzDVf%9q*Gh_kXpG9*JUauC=$~;wxVFR=^P`1m zv2bmfEoy(x;c0n)WXcuv=iHCITsrUk06$$eoMhEVdt7)H_+dz!Q^Uf$=9uzzGqpJ) z2BPz+-A%+ubO7T{c&>=~(NQRTcy|#CqwgWU@E#(TM29hJ^F%C-euKt!B94mg#i-_s z7*|7=A*F~FUJ`kVxq6oA?vu-X);elbg_q_~^wXd770l&+x?qrf+N*VVxyUEOA?qp} zPtuJpGWTdvKA*s8`*G=It{;Cz%!WsoL{8& zHR){h=ghX|p~Lha_LgA>@ejk%E~B9uLe=oGDE!1gc(pIW+KIKWF5u7E?kg&GDh>*R zKisd25Qy!^guoxRW%!=7a3v@7}ZIX!5_BeP>d5^!r%|@funHBt6c6p3}eamh|OX6b1pzN z#yIID41dl8+Em5P;i2FU+wB;LUC&&CKTKo#b6$a32!lV&%LM&77f}y?&UPvGj@{2v zfIr-$<69P6OMCcpK2~S-;MivB!5_9yxV5nk>cJnjUANob zo^#m;bMY*sGXS3NGA0ZDFh@T4bN(Gg@P|va2!GDx!sCAI3RV#(3)%jh!BY?M<>c6p z5wtPR_cSX05wjKNIY>Xzhyc#ID`vt9{+uVkE(b20PlI;IQ3wm~jw0q;YS+G!4~5Jd!t!?*){%cc z_OHP2GW;sE-{!7D9?Qpt`|%t1GX7ZI+K!_NFZl>4vc?w_=lKiD3jX7iIBz!)M#-0r zx%skmh+J9>R%~8gnh`rfJSfWn|7(0(wErM3i6h9YCQQ3r64Pt2JB&R*Kd&0<>or>b zdOndok>TF06#?M75@_Oe60CjRivL}{J_F~KrtS7F;bi7#aPkO38~ z!6-SMA}z@#X*wqOpKv%kWJv~NQ^!yhEUXIVOwtiEDq(MW)6Ax-kn}W{(-**bn`r6n zO00!D)%GN6OFN}B&Q+5g$(}XI&gP@x>KBB$zn_t18pX>tTi@KP*=N0Imd3uMs-M%a zsuxtVhUWIhj>ewqnugY{o+GC<)bD%1;sX*hY;0I?z_NyAJzYnDuGibJSAD(h;&OX$ zkPg#LT)DP4wd(R1FOlMeQFGaZ6DRI>JDQNK_05tihaZ{tDNBEvy=`kclP&S)wT<9a z^=p5SwhK|mo2|_{>*`D-H?;L7w4+DRK)a4?L(L|7*R=O1)8094myGaWYCJO1Z?fUv z8M2;ng$ZxFO>Ca#b$vQraZ*brtj@TpPXzR|Cp%3!#MvY`SRgYd((ZRz5-_uPIr3sxc4CS&cWOgEKi=Cw^W1CNn`y{EH^ zoY>{fv~F!T)(EBxa#DNZfV5%CX~Ilt|m6! zqQy%WW^yrmGlFb?$d21#R~Ntliayqf21IQ%vf|+_SGb99kw^{tDy82Zzi3)G)=P02@&|h~)lY5}mENk5#Sk($+`<(bhR^&=ORRkA<_G(}Op5DCB6>PWO>NDz_(V8|N;dW;C&drNgp$hHl}%{f z=C$#j1**Qp)+=uysiv(8+9wN9# zuv4&K@Fc<01uqc%f#8n>Zx_^@O{DjT$b50Z^ffmJ_^HU6ivzg|6+`_Vf=dKf3mzf3 zPVgkb%LK0%yjzeTofsb+Dr+p@qYvcKf>Q){6I>#wIW4eTEAo0lelq0o7Ybe>c$45S z1^L~ab{`7*aGOoJNH8wQ*NY5q5Ij;)f1yP9Z6ZG?_?qBHf_`*&9?y43#GM4`w1{%M z;IV=i3tlaFtKb8IPYb>(s3*xIo=Q9%FuvUd_Z2)$utV_cg5MPUp5RXf?-KmA;2#9v z75qX_yLm!-qeFJOm4bZV#(eB2m=Nq1JV9_AUJ%l*MsS|s{(=d?;{?wXyhM;|yYu*` z1z!{VSTG2}1NFlM#|zF7Tqw9oFe%tCc&gxc1g{pnUGQPS=LG*G_=VtNybERehX``1 zc*f?V>P@ihzf2%aqXeZi}UXuE3!xwstt zo8ClZenh@c@F59*Qsid@pO^4AM1Du`uY%hI1LQU$-XTPU6$@fG$>47Q9}Nv;wB1$4B6E zBEKy7y5ReQ9}0dh$O{UO&k>9Y4i_9LxRW3qYS3Pfx4>GFcN3f^=;bo@O89!g;{`Q$ z9`T$Zvf(^_TjWawuN3^T;0=N|3Em}mui!(1{Dz|IM^JwTM0z;g@nYZR-%!tuh~Z1) zbdJA}dC%}K^8;#Mi(Sq=|4-8X{;ha_ycaSX+m72__@TL-?N#iJz%hC5X! zirQKkmq8bls5M@x57Y_iM(7A$=}7;H^(rN7$W-{&Kt8C-GvBn#}}!v%gOv$KMTt#%|My?7Y9b#15dhQrtkBV;I14aJwBpcm4{Ize0pDe{SC2!;t+h-rwGc zkK@1DOnHf}YEZ{9T?CT%XX0c0OcU`r+fUH{COcBPZi^7+wu>Ww&t|ckI{P2w{ngY~ zPmgo^a^7EHqE0Y__gDGWmU?&t&H47C(-)O(esOE}Jr;Osyd?2tfp03m_uvcN-IBh`1kx#c8I>)N($GCHJP*I0@SJNbV_O|hf%g6-bG z<@2L2fu436&TaprF!RqUt%nJCeaE9KfY&!12L3}3}mF#-bBB`u6O5;&AGufd;S`3Ux` zU|=);hBn{;%Rdh}5g(!c2N>K_zzl^ChIV@&p^K3f<0JGI#OU}4WpA%UZnpCgT7W>8 zkI*kDrhSC^w=lwM{XEoP$Nfwnp{T?m2-QA9{g-3U_z30QhvOskS2%i5AEEguh|5Rl zHORHgM=0+O{!t&Hm59;t5&9EGkoFNeielPF=--e{myggAmLTmTbOrOWd(J5^@>LW@ zH&aae2z`ae&J%5E^k&AK_7Tb{Z-e^?{VNNd_7S>m*<{WX8 zgQU}ez0c9fb#sE_w+^YDYef!=aB=yluJ5#u&|flVX&<4FG2dU=N9c{rs__v@UZcxL zXf3n3K4jNd0R5P~u84)U&%-45FEJ!AEBH8>h=+OH`8_b z2)%*{yL^PESO{?Z>@H9kyPUGiN9ZB{kG(H}udAxozhln5Nlu$INpCumHfd=~ha?>- z1qvN3wIefHNYgeQphIXnQ41|lKp7MnMC54@Eh4kZs30h#Ww6L7AOgZ;Y%Kx`_<;ZS zt^MtrlNJQ!y(j!1=a+N8z1CiP?S1yy=j06EUWfMJ___Sr-0R$|NQ_WE#E8ZSeS~r( zMkpWpL}P?bqW?&Y&{uIxL}P@0ljS2ZLQ||S5+igy@gMv z$8Q-bOjM_Gi?~6N7@;q6A4Fn=E@jo=_?=|sC*?Rn_aDUw<-@mVj8IMx{zoxF%b5?3 z-w0gUk+q#;kAntQGSL*^_+3Z~aQxT;NQ}_S z*=PS+j8L9+@-agH#x{OvjL@@T`rj2Jl#eVTF+y)<#rYVa;P~02j!bG4s_c0S_K)NE zg|&AJyv0YA^1;|4kS9<#oOUi!C?|Mq z!3y>QbS_e8Ih%wv8Yz??qB)(qMN8{q@x42;DFqlnDXe`KEv<*HoVvc8tsft2`F*Ea zy2A8dwRAU2pJC}uiWR3R zmS!P1M9FDIR*DbR`9Ye2R9cC7kQfdD%b-7V>mH7GkF)w@KlmGb7K$exi5F8Cg7>1a z#AER+v(e`avHCf~aX;KscQ*cFx{bg1*>t zOLo^D@w&48<2USER2uITKeXtuqC<=U+Ak7ww0{v;vYbLRU|6iKOmxcK@&yknaK$ia zi{c02lrkt9kaWMYDswnko1l=SL)0pX9Nl&xkZ{QZVk1_hd3>~6CPD)Fl0cIk$(OMp z$YiqF!YC2aj?mal!YHiCSW9y&6B1TLg*8!OT`Q}Zf;ApHl;8-8Yf`ODG-FN1)?`|l zSnGtHiJLk>#P(}Dx>!8n>qJP;J~(BzEeSTk zwI*+#iu-o$WNuW`0Vsk%son{V-MN*6&Mn+Eeqnx3tbV+BJuzx$Q)6P)aP?1;McY#t zKc|lV?}ql|cjlMz1MZG08liMzPwqq<#Suy(8~90s7xE-UCYej+iKEcMVqVjH=y6fv ziK9?|AXRjCFhR>e7DWin67WPj3{J53(wIU#8Deo2 zNu7xN***DHM*gfQ?^W(2d%m_VZW*U21J4Kx3zBcGi`Vq5N6}@2(_yk#RV{2lBmGNa zvM=}7b@B4@@?^(&Sy^WiRFhvCOp5`Bwj-K$WLE!l&!LW=8l{+iL{?8!%w{`^X&Psk zJTX&r%k~V(c7!>{5{mHs^2|Bx46v<4>GbSLP}>~AP7Je8V{B04l37qte2blAxQ`tg z6dPAJf+aj5H&4QBW2Uz6pLXQP29X3Eq0JEnJ?~8vSx+R5FnvkKLS#%wfpcWUHWHzu z=D-!}ouMANN^^92%jk{`0Xy^P{qjN$N&b8#@vMg#2y{ z-H#E(Ge2-}YPMtLLxYThSX{^0pkVVFX%GQQ?LhFP-6_+@eX-%dJk{6Hhs7-B=>tU- zTeNv*-SE#thUQP6?TEDh#*m?(M+^N>PHI);f|S>z`*!HQF*vE<5Uo6 zcfxH;%HBI~$SZKU6j?rvywpmxkGDwd^EO^;^qdu8rRLRm>;(Hy!b#_;Vp%I9vG#gr1Z7C&|XKf*;0LVLhe7k-~|> zgN1X1YlOyyLbP#X#Sw*UaYTVzrMEbu zkS&fVZ~|^l=q#+^~Eo>_kL6dPwditP>6w zP7v-V{1Or6<_nh#j}v~Ki1wZ>JWu!|BI>_Pc(wG`2yd4DSHgRxe}GsVi~T|RXN3PL z{huYjF8n(Y?dyOtL@sO(4nsqz4NHVI!hXUb!l6RG_F(xh3+D*u3zrG)JP*5dk~avy zCOkvPdD8Uv9pU$dn}k;ie=7Wi(Ebmg9ACMx{NuuBgwG3K6>b;W>loNq^85|lMOZBy zAoSc?`@aD@&#krpACM=@Zl;j$4(aa*q5WTh%-5mRlQu%M|1-dKlKCo#`U{0W5;6o1 z^*>TeTn7Tzy>SonM4v%>!r+6x<$e_b+PJJFy09|Q6w5#?Qk_Wum$4*P!w z{qEA+TnoqyJw*G1h_K_!A<8!Q0*KS6>HYYEX!(Bpp@_+T9P&Db;}Sy zWuo%XN)5UFB|faaX;%u3>#I&<)it(xAwOR+wp(F{Vm>p?Z7R$ z>G4-iFGx>Zyzt?-Vo(3zr{iAkFmBA)=`RnRJO1UK!3JiFrQ={x8Q5zDav5Yhf%k@PD6$3W3@1TW}@{#1pg7D)4{Vpae6) z|7AL8MlSik--eJ$6MV^SB%J3<=8Y{7TIF4oakysV$gd-m@J~NXuDfCiU zhP?{@FVpOGqajYoQY2d}G~(zq+c3z9@I0E&l)MrA-;+=o$;!6L;QxLbwHg0+HogCa zO*x_y)AYWTVncyzXexY}Eosa;>TD*ohRx~8&Qgp|Ixbv=AFiq)omvM0F+MkQcY*(V zDa7zW{DA+aHGJ zO{@v|j|KeSP62cKh2P~i-IE<;qKomFxxds^> zHk?cGq0(_C=J~(Q)%cJP9l-x}ZJrX|#J%)H;Wpde8R6Y*bxsTI{q(vCwDac zBF3ll6w6)3&OnUMO|}WC9B**Q|8;UE_bXNm{;!jZb1$M2@_$|Vk{oXg$p3vR%Z8Tc zR?!~(UzcB-E20ekF9Y*2#^(=NA7XsE{871{>;>?D3vl(q7@t}CLyS*%DjAzQiZb}W z&VGE37aipPy8KDG-%|$vx7f;0$#rKpg8%F6XXNZl?co2ia~R_@$9(XA?Eypep*bE` z0S0*>+AB5oe|zpe*Ux%0UFi1Dcrff~8t z=@i{p&V^s&|GrFDt=!q*|5Bi3MZ zHGea5y8|jeMTDG=lHEp8O}zfOS|pYPKG{9mU) zjL+Sv0RPu15aaVuj$iP9T`lDQo&hIpmGvq3zm(Z1lfnO`ywuB{|9d_ZxdT}}_`ej` z=f7c}f&cqslM&;SXLSnZ3Nb#pb9f+0?z%mL7@to;(T!&v@_)H=yLDtwfd9){UH#j9 zA;kE+8m8d?Qq?`q(}0a`3^0bwO{aLEcaQVn^T$FB(&70G_VR7C?+o zp7{{tlaUI@|7GO&cs!X(?T#(P^%$SN_Iwn|bez|YaSd&4uyz`WT=r@jwWI>n51 z>KFLs6$!kI;3b?3k7)8}T=n+83iW^t{Ck-7g|-T7@6*`$Q6=|5HwW_m)J>z^?wxK! zdJERgSgYsIZV%HH!}Whb=gGkI_ciD^BioaKZ-wqX+F|u%VCt%mr0=mEnJz=$^HQuY zC)C8pR#3O=YBaP2&QT6O(~BO$qrZNqLfMa&Son>BD%BZ@R3(1mGl~jX zfTa#WKA-CJXNHyHJBwvjYBzSuXy~(}SnA01z=K(AKm42w16(J?`ZH(HTxhTiUW1>+ zh(xz|@@Qy=G|wCvON>kuQK;o4sl=#65jUdF2*aZjSqj)M?A&@rtv8Y}mB~#k!?|iC z8B=g&Kr&Vth9&qAl5yu)GS5(jtD0C*(Ow9(img`?x5Vj=(2}BCPzLKUs31@=Q9}`5 z+X9b*uu3XyR-sA7UoDKs_ba2ms8?*iGJbxlSdmF(A4csN%CrM3#1QQZd+fn{U{l$b z!ah%-rG2M7byyZ<6|r5>%<_u(uEnnIinRIqoMh~Rt77m*x}E9hR|> z!9^y_!RolkOtABugBp!bD3NpO&tYu~qR_ zCU~&`A<@djY$qgJ+v=SO)eg&e$cUaw@GadxQiA7FTe!VwVBA)<6o)=8DwfCU`?NCY zPI5&swj`{Uu}Fia?Nk^H8P>-& zLL81Ke4D^Co{aNJ+mc`tU2F3`QgPqz9nAwX?TI20@7d5-3G)t7@7-aTu)4T2+`{4J z7q*HkAL6k}zeIJuDXhaUwMh8E7}YaB>Yw)=N%y(4_}@E(*k`uaIAH!EsY{fv{g%#M zymDSs>~o^?zlG?`uiIi*{rh;%*$PK&&VonmsLtdz7n9Lkl3X|j{NQ9+mGPHPcKqc% z^Tg)YMQlFFWt4%~TwIWRXI*@cbak?bPF4;EOS)w6z@a2JCm&8$4TeoNdAbz@m-*b} z7|(Y8+q!sJvM^pzUQq$#ZitNl8g=LLGM|6rI+QF(?r*_%>&NWGfle3f&HOcSV`8Vt zeTJ$dbYZ$Pz`JllFNHy2u8@u4ZE|jifkw(J! z+B}aPgC4i>>&Y8#aB-gJW0J?>MGQ;(KTMkb$1LauPI};h^hxQ^pOc_*F3O*s8a^!~ z=%YvSB$g41ppI#1hDX*>bOUgJm3nOwqiNvRo z1D!*=c*n;6-iZUvE6trL&?8~$Zm#i6llzbyIramQ+yi14A~O3B5l?P_^nAj_{Jn*| z=cLTLS0bZW5qZ-^WV?t*3)c%z78)lG`4>pOPE?go!R(OW+yF$_= zSng)weZoHow+i1CepGzksd(x_e}@Z~2#*u;ohS1z6#hhbAYa))-zcz|KM2lAsWVju2rTG?) z`iVlmaijcY;T$6DY_1UWE2ZZvHrkyk{HE-18vaCF>niQv8eu=-K%rglpk8tqSpQhz zc;O7;fxT;gswD`QS zknu0i#sRa|?1DG57=*lT#_-5~#m*>x@ziaUhq6#{{_&lC(qyENX;G=5uhkqY=e;bkZWsr*kFaiHg6mm&`IiSUHj z&!j&mAE5E{F7x05v7f)hoJ{&Jlrq5yfVSAr{Fjq_8LFgWKa<9otSvv(j8nW*Ox}r~ zRPQc7g({umJ#|42M)4$X8`A?j%w*|#(4?1JI=CP91>k#cKt?8&zBrjibF#NWo4%y@ z5h$~~!A<`dL31G3SG_BcDxy94-svA?_k77+UlUY#iTvB~pcp@bem0+cq5J zyrQWIMuN|Wx}SmHV0V4)J{GQFQ$|Zng_S54>>)7|Zon1>VLdCE?5P2fCqa zOLkmn$=tqUc#DhQrXIIILqE}(k;C@x)_};;9wE>Rr9c)p(V?y481P_)b`N*JpY&e9j9x5#} z(eb^5N9AgKxSYn1tL&8UOo~qw{t{b~sGbq>UqE{J2v9 zzPB4Iu^f-<0DSM2wh5^mCs;x*cXB58s>|=`k!t&3zJp?_G;7OIAOf&h@4Od~Xs|lhwxe=Aqzr z()DO?WG9)(#$hM%1~Z-dHVn$+o1x(VjhIs9_vdY9#Bv>bbWp;|7>!3DmzJz;~Z<0*sh?c{>o4=L{$@0pL`)a))>0`R>% zpc`}V&=h>{4X6NTp4^Yw$KZRr{g}#K##VywO=I%C_eU=T;Cu7m1o_^iu?FCKyRDd% zyM$W-zV~wTHzT)@_TYPe1-0XN%l(Y`;Cs6RZeflO9|Q2co!p!o&3y2^oxCPD9DNvo z@7>e(Ir!d;pb>!YJ=hfBdov_O0KPX{kgUEip5t8V0DNz{FuwQikQ0FK?G)g9^GQMg zzPD3=@4Xu>!1s0v@V!Y%3c&Yv3h=$Z%yxnA?P|f9zwmH4VXLf9!S|-jMwtx0H|4#& zOul!3c+ZQV$nmN+0NjdC?bLVy&&b|cSo3*<7f9VT>@6Agg@V%+(9_MMmMmGl7W~9?89_ZcU+oD06ME#w$1#J!R=0K9Cn-vjWydFBJ(n^8al@VzTdM7-w#*Z_Qg<9K$_FOliuJ!4)$ z!5nzmeCI=qAX#Ang4t zS`=T=>1?F`jP(_))jz>ce3j{H&=5WjbHwh|CG>YQWKQFUQE9wShcXb2yLC9IpftXJ zyacUGw6Twq?Rm+claaxeB_X$qn9~xwig+!tn~2n+)^;cTnWcJ&>udVGi^<^bnTjVn z>{UcwcU#2eUHXCF-5pniRhGcbORvH4y^B3VeAi;e7#>@2-o9|q`xC@F<_NI+A`*Bp z++uf|d~7k1Ba!+Ymo-p;u}h%IPGN-|%@MyoCN3TDK^wTb1g;iXn2EtoSkcPFUQSrk z%EUw`ENo@sOHNqa%36=Z3SWfpnEvQgD-*nJ0y#L-%EX;c*g4AZI%I%iOYqHa3oML7 ziA&ra8-|voK0@quTXQg>H_c-Q5td?2##Y9yk@PRZFOz3tMXiKyV+G+iZf(BW=?QE# zOCZv)-+*YO;UvnVK_A$!GuV;=Sd+08Yg?Ic{kmeg^{ea36)PfLxnfnMD`&KIC0M|1 zT?rPjZ%Mo0!`)Eo@{4~>it>w8KFTlB`6#~_Ek4RG)Qa+p|GN>6Z2^W49#*7ncqQM! ze|-!3o3r@7t4UGKR#l~I`lPdsV2<`lmoUg~BNdnpn=Tk)ikcH#$X!YEKS;80yeo~f z+Od7yUb?IvoGw9Z;R)$#I35hg(dfOZ^TV>LRbM1}@4S{}4GX~+;@9Jijg*f^8zD%} zYg_@=>FT-Q;w_njZUqgGVvETwQv8d=(>69<`)IeGTdQEUJ~;54#Yc@JYcE1<@|Frf zyaQ#>hr9)^&f@L1)kpRpgAq5)t8xTHqe6)f$YK`Px1phBeypKAwb#>P8(QoG^5)XG zg!30SF2D!o^K>kRnQo&Ax2#$Owl227I@$#c_T;a*t5(>z*L~359mDXVlhNBpH7ss4 zj^do;YNrFsvy1a_iOF1y z?XZ(p&s{jj#ag9zkQQSN*b=nO1#fL{J%15L*-}T=M70g`S1z5a5U%Yl^E^*Bu5odL zbxphY$KoG1IR2-C!>-1rl3&Mz9o@m5fpD@$o<=`lj~>(1xV(K>Sq44E{$=J8gq&?q zTv_b(d5f^~7Qvh2<+)FwMuO|M3vHcmz8gtPn^wmf7AkIa%fe;LS5(>fur|zVJO&lE z*fzPoXmIhH+al{CyPe8Ki590X%ACc{MPS`UOEIpn(T(iiw#dC`RCCkZMe`Rm&GUzg zeYdrFyp5s8H5NSD&U;1=gcF6Yw!`bFSe`%mu?f!pl-#grN%P9(O%2T}mSacY80K!l z;9I&Z79soc;Ba(X7kk=K6ctmtjV0-V)*duv+0q5z@;0r&>8Od$&|DGlS2ZnfS;XD9 zVDYj!7%!39=Ws9_uxKrNM%Ig(njo!Qy0QfwL$V~s$UGcB+&imn@7Q52`?ko(dCuhG z5yKj7O#WYqd!46SN6D!%+u1|wxog>VF0`{7X)6{jX>v!cNZHGWjUwkeO6Im;+IHZv z&;LynRC~AhVH{LmDelvucw_RU#L4l*+&k~My+drDp-?t9HO^TSi}&Xx!N>`Nrp5}w zU}_d|A3CMV;}!8-vNGN!-ZkD0-}vd7-~+byOH`4Hz4m@I*Dj_bilnY*y()?8)##GM zl`gNb+m;lbg&@{rUeR_XOx356gW47CVxO?TcjTb@Gs;dhRLl71d8m9?L7ozKBXN|F zcOsOh3J(+>CR`v~DqJZ%QTSEiIl_yCKN8+3*bPR<(0(uB zWZ`V#k-}BN6NMKFuM+-J$N(Ai_r9H`w52% zM+)sci~M~h+bd1To^N@u^j{J-3Hg?vew&3WgvSc`)Smf#rAItnc%JYAAs>J<|5w7h zg?Kq)`iF(T7a9))_Wvn)$5^#|l|+BMj35R=KG~;SF02$<$RX(MnHUhK54?16+$8g( ze)QvMnD;|{$Nwh2qWj|=h6~+d+bO1ZIV2H#H!0O8&8S8QuMvu9z4LmZ z4X|UqtdHA4KPHt69Xz_VGS4I8(u-c7l`s1n6`#S|`Uk1t8a`?kve(`xH zLKF3OO~fD1v)n9|)uOByi!uXd`tH!^SI3R@*FMxyCp_DOaOSk;T+vuRt(_c=`Et*{jDP9{NKSus)6@u)%IQ>y zHG3fP5Nq}oNQuKxDmAt8Z~$V>&P7gQ7WAp zB*Fi|X~mlDi=yd)WqePZc$50t@_7KnGpnQLJ@He}y9-BBI<*DA2-ScAljwqB9t`Zj zMkMaUPq5t5!7j+nfNyv@beU9eak2-h&+dk%1eX+VgEGsowZV_esCN+s2O(vjktW|T z_(7I5q_87?f=&A1do1LC+2GRj-%-Zm%l?%PFH5p$qBql5b^9gq$TwUG9Xjq6bb3do z6DJ}++u1s>J2`vqLhkBP0AZezJ9COoOPv__Eo0)tCw&L^HGXMJHK}neb>6%bi#p zu4d8tZca45VRmTI+vcbo9d!m$g}l;W^e@{soVebAi<<06#H>Tzo0z$K);WlU)=Q%$ zrb4{mh-LSXmIrA!8wIz+*FBUS59>Hr3h*Po@jc=I5PR~xW4Ku#sfs|)T-U!0b5>&=l zdA7;m8%{xOXU4OK8&%fz_Ys{)o27SNVPzW%ToLN+Wrrzbm0d_y`e zJOYKess_-XAb@Xp44RtBuFRYTFRWErYon7uYrgp%YN zX0Pj{0^}QJulFN?e8cPwk}~1`Y*!oK@DWzko^P1_MJc0uCaO!q{b+oX%2tLCQoPN2 ziG0Hrig)z56wM>wZ~}MDT|FK)u_j!@R&Ng9F|l7bk`>*Pt>A55wc{IR?^i{RZvs+Z}nD9U7>cP@(R(5PyMe(81-Ar_R!|bDSH9mZv&3Ig8r-Wy5FFjFcm-pZs zu4e92od%%O$TxhO;$X@ zICldo$%1d_%9rFgDL4zh;hp#|O1|Mx+JkTC@@sQ(7EVmcy1K-f)k1~E@ z7JNezipV$QL!&JChVE1{Hn$J`gKy~U$LH?G(9MEx=<+A!TIdgaLl?hxO70$ZBlw2S zenxI0>j&SEokPAMAA)4TH?*5*@XUBzWx+Qz272|~iCh^Sf^TT=(W~!Gp=NY2WFZ^+8X)$A@?vfvx`#ZbtR`i{7tmHh8VS68qo_=avjrgC$*LEszG zn0!M<=FEa`Xh9;uH=Mz$!8deUF)25P{=hdp&iu_VCSMkO!?UfahvuH*UIyRL9dHYC zKWBa58#=i;*8}CU;2S!5P3{TS2fpD5)Xy_|j#rlmL0U4=6yO^!pa<{`*#hGm9zzT8 z4e7%8hKx3z1>evqz>baTa_-rvTrOpXbVgZ|D@@8{Wref^X;);2U;kJHR(|wUBSP z5>D7E>r?OzDYH=~gKtRrU@wzzm<8YPcqnr9tR8$r3heW<*=OJze$!;|4S80lV6MP7 ziHBac8-W&@hy=i#}V(G1wcTH2}OoPC3njZ%7Z|8*XI9;2R>`B1FWO%^@GxW1UcC z&y%5a@ns9aH{>MjUA_ zK^JU8Nrsedg(jV%DxD&6FrB&pzrErNbL~UQ^4^Y1oRg1xAAyqbktKYX))&euti4Cm zdQ>SNtj&YWf0Vt8X}5c)%aDEsD=)vQOKG=<>G*Ix#Hx_87U-57-Ser#TS-KWWlMa- z*gmYg1U};YDQ9AGAtz|}tw4s46uYa>?AIGw&Qs;RDxRc_fXG5A{_yfUKCR@JEWJN6 zIDhpZtbHdySc1e+EYzQ6Xo@=>grzOvm#YTQd;ra2yD@tNv#`eEGfK?W2`IS%tFws> zw9o?;iSBW3OR^S423ZW*&WR!lgDq@qWg^RL^!+7(A>Fa>lJ6#WiL>jHgO)YdQ5;MO zLOq2s6j192@-y3$GLvm|&CmInVqkt+_?cvV_WlG6%|1Qib!GdS_5orC zw~q)rWXB>lUUA9+dO9gjD@gN*++nffJZ8a4n~~*6q)f3$`*^UKOgi0;ORBR(Y^FaI zfc4ni%1U^!LRitt#Aqk1YaNfoWUSzf5)L&zIHOF=cS5F>iKR{`Zf$D_@0@p7CP4<3 zli-`af20J@jJDuJs51x7&q}%{y<(DL*SYgu>9uvqNWE;dEeSg%*CHLa=a!~)@nBgeBDVIyIk#;|P|G!9p2~P-A~uTu%xr1XMoi;r z?s%?=*rdEE&+Z(R9A3 zqrBod;h?3go`V$0eO{RBAUKN1GT3*&UowJavJ(HW)%unw!WJtPf2wbcfoDP$PjJ-O1+vp7+^~^4DOLrU*eX&jB>5pC_z38X_1{&^oS^qrrg;B_i#oIEbs~ z1G@KdjwMObUW8v~q(m?%$)h93D^C|~Bigp_n07Qy&vSJAJI8tSG(9nYJtH>4MRQzWJ||s1;?8FV-c|%mWb$^XRWqT(1+HE zyeZDKZB4tw)${EgYg+{C{HZK5d%%&3MZFfAJ?}}J-#nkVJ&V`zdmSM<%Di2Y-$CtO z*r5*`?|w&4e3V>j9RrrHxbf`eCeQPCjAyr7@=fF(`FBTWby1~#lyCf(Hj;CmcKq)Q z)%p*4vb+@C=Q9|qHGeIQ#HW!L%exCc;bH%_@nRzs zLqP08#GOqaB8&z|KT2pkFW60#JXOe>N0y&0Y!dQi67_3^#|yt9JV$t;@N(hLg|`SF z5E>sA{{AHS&qBVMWId%q<7+{lDA{;fkol;ac58$u2)`~go)z->YKC@q2_F#_@+Jy; zi$e$OD|xtZyzl_w9HGUVgZ&1{-w<+UJ^fuFyh(Vk@JZpj!XjMO)4r>)zi^arfpCTJ zL?Iu3v)mTpABFD<`9zfY-Gl>#y9*}?`4pITXA2n!fby+E&Pu2JlyIx?zl8iuB=aW- z4-z&BR|-!Oo-5>gB9^;Wc!%&|;q$^bg=yTo(7r<0N66{=R=@Bd;e6q0;a7#{3&-%) z2K?VErR(6doU~ih43rFQ-%K_ zyh(UF5&P13ufTgLqYaNJ-{Q1FeqQ>QrGHcM+rsyx&*GfM@}aO3k^L^Ym#|JaTsU4h zNjQ^;_E?-&pv7qgTAWt+w>Yi97TK*9ZczD+!f!}_j_}(;i`$Cwm&@*2;f=!EWOtYF zS>X#rtgjPM-r}_alQ@TSJ4Xs}y0rG=a5RM4uteBbI6zn@94@r;Kel(ATz0)CE&-8JBX(D;}WMSll}Otlx&YgQT|~0 z;WZHX?>_%ujDzYgnm&(%ivHw+VPVUz_~pL9Wr8ikgdV)zKq#2ze&s^D6_#>8+^<~5 zWA$YyUxKxfJ6Vg*8w(kyuNaZbg+1{D=e$nE?zacxY}X8|z6_H5a%AjEj19l|yg5+# zH1nPW**logx+og4%k)D`NiAu`kraOyahX7hB|Hs zm+P=b+t(cFKWtLIeRm;^&1(kO(hnSy=vei25hJ@jHVbxDP2!&2Qzh6D=<<$5o zFPDwGdf$PwkD8r+Et7s8oZ`FUj#KOZ<1%QC zYs{I9;2N`N;s83os@o$lCD-^2=+L1gYjk8faSc-78ndHHxCP`IbB0g&GIGH+W*T*f zYwT)Fh3}yTaE+aq3Hb?*Y<;;Ci$juOz%_QF=NgxqBXW&5A-j+^oH1nEhPv@$-nhos zvF`imVE3$Z5DUrd&yJRuvf!NH8vDw7aSO&sEDrZ(TlSP#68@UvUJ}d0?bt+cja}Kw zkoWH38auIj*n!6TNQ`ogNg)gWjwXU@%rtx5h-Xu>6q8`4g@duv!8PWFK~97hQl2T9 zT;r3FQx0p}WN?j1gg377YR! zKU`G;2OKKQ$k*YgKNCaws%H&5gYkbr+r~Wu5mq$pDjKHMiH(t zk6?0*82}SpW9N!oW2RWtKKx$6(Nb{=f2hZPnTo8A%xSjL@IwZ1_Ol0G* zlg>e#(y6;)P#))YbAU!nsq*{tbu(f)4%;>(l&^%sxW*iXb})-;e1Mm6QvV*i5nSV| zu`!i5qH)GGZiPk8&L!X)Q@}Bvo5>yn*Vy$SSiRhSaE&!0P$M@youd271L4=W#xK*= zCEWSo8dIRFD_Im=V<#6l!Z5hT2V*;M$j1tqcn8L6w&NNz1g7J>gKNzHesuL1TLrGM z+mET-Ms5(e#xy3^_;Kz>aE)zZDY(X*$WN}Z+looKE7>$~jZZayZCvBatf`0QI?^6o zV|TzU%<(}WxyDXz;~G18O|F3X;2KXu{XC=RxyDDB0$k$@X#uV=TaaXIQ_nS~3*#CO zXPw|0I|aDL+qqHT8aoBJ#+zvYuCY^qYy2Kg;^Z1T1-Qo5+-`719Eq)5SBfosg2!vjgO;~GB& zMK_*x$TjB9?e-Ge2(B?}b@gxag}^nw5vJf8QzcF@&s!K^3>BPC@jyp>6C7IpSg1id zog%TnkYjK(64n54jd$l3fNM+-;2IkN9bDr{CW31`0QtBcV>E-Fw?Ns(H9iYocDWY~ zU0-z*wlY?QH5RYhgaYvUI#lEu&xaMb#{E&AT;o>Qbo@SaL3i3A+UaG`1iQjBiO1JN zNT-;ePLWHTPW=qOz2YTo&In$@wcXst2ji-@_gXXn#AD9R?~BYTti4-kJ*xEg(9MIq zKXqMbw|l4Ckp2T!-YHa1rrjQ<>ju|Zte$vGf83IDsUz`t?~b=Z)sdG^SfQ$mfs9NY zUqtkFx_ao!sbjq8DOjtAv)X;k?j*=3Qa9Rk6}02ahaY3@!)@VRWSl>|4T{ewd>>B~ z`|g8`-^1cjth@Tme$$|3z>e3jf|Pt8L>7W$lsuql2n_qa1Z4($p#W>&Cn5Aif>)-o z{;jgl^5G5an`r-2C^@N!GbIKvqu(vi@W0&}7K-&@De9B_!Chl4esIwbe93RX<_xU6 z`b;a$|1}p`>Hc$2dLRlVYFToA`afCnI4EyK{`FY<9u0waA%DO+fL8rZgXV2Wf5QqE zDqW01BFUe`#l_P}Z`h9Oapbysg?Zl*yq1uK?;n>iTCzveDT&VtuG|C&Oc zf6Z(R!TSJ1zKXJmzanx_@_d-ouB7<4c(DmLVUQ%=iWk$~6@Dk4RbdXofp20rB{v~b z_HA&Om7Idsi6=9dlSL zB(cIA*F~cnW9aW#2ag9VJj;DFK^!NP7+A=JW~~2+ARfm72THD6ki_Cj&m{1~fdIY! z{DAv+303SX z^b>*W4i?b3CGHJi>vc&hu|xmI;#BOQOyv9GAN5%x&h8$C6}`|Q+6$?VRX%BD?NXp^ zJhUlybejGkb2i*Aquk{aq_%5JrhOOt9;J?p*ZVGYS~mu`RU@!+%c9GQh`<}m&*ug# zox6DDyrx+#$F#&gS?KP?i{{J%|9;lLb8Y}$Fnr4922_-lrIVF5JK$)t^*bUIcDi7u z%?`L@$JqhbX?DP+dA@&omxAQ?O)AG!f#efw;$ZvZN;Y0F#3ln^8o=d8yD0^~?Z7Do z<$3*;tPe8;(gnSQy~`@n#RX-9(%Idht*=BQx+TwKBRZF-;>b!qw=Ry{SMxI3M*D9#`(6cuQ3Tchbseio9&BN`2mepaLiox0|1YK?v zO0|!m?L$$M$nQe$DzI~&DhyukC?8?g0&=^!*&lyq0vuT2Z$Cr9M~?oVny7$TwJSk9 z{(QOuW@xNHQ0A7ZLGwv(9~6=2HxHV-Z0U;SjdNG*iTNF|1{VwXfI|=5w{8TYG4Bvs z{{NqO3w|a-eo+25&Pl*gRu{uhy_*-qaOVHq?1Y(h!(A+QD@H=Rg-&n45x1tkVG%w7 zV6pK34Ko(nyJOgN zV1uvyoCchdc+-YkC){tcHRQUM3dv!j{Bh?r@ZOmAd{R$5Oh`@`<;B9Ih3kbU3(pW< zAiPj`x$p+z?ZV#)`4)iwUlRUV_;+D|hb+uzG&W*?;dJ2v>zheOE^_HOL&xUt?+9?em9)ueK7l4B>hqzwS%>3xq!rz9{7LdgfQ89M%Yj3ilPx6wVfs=)!WB34bGeO!$J3udHd8 z=4&HhxsbsTDIYFeB0N@jhVZ+>D}*--?-Tw(xK;SB&|-bVzs33nTC8uN#rg(L#Q|aU z3zrBj;0yAEW z!-W%s2ML>mD}^Ts&lPSGUMIXu_?Yk|;XA@2ynkf9-GzgM#|ZgVN9NmSTY(Qq{M7s^blZB@X&lX-JwAkLT|CQutgf9`XZ?_6xBcd&TSAGGW zNKq~nS`2Ua=_fXcPGMrKk26m890ghFH3F^9!W&GWx^KWiON4kc)Ijw3eT7RyTVJPzk-N*ZkGO6 z!p*|_g%1*8_oU>fg|86Np6$Xng!}?Gw>u>ag{8vIM3n0)td@RP;SeI$xx(eb^}-8< zw+inU;@^|`#c9wG%`xO7N!Hg_I6zn@G`tx&2Y_25a0n*nAZSExWq$|+g z&+Rx|a-*3Y5q2LigGKX6Fd{SBbqdA3T zN7)U8&5rf*e%CJ;Hnxn%ulG&GC0O6W{|3MKys=Q=-&2gprK%ca9*jfYpJ7Ah^|C$|A@Y7M>hF0N zR6*w#pSJ{xsK42R-Rn2{!=+l@-$tZ;86;!r&hAAs(_DPs2Bf3@n&Gb*I{M@PQr|xQ zKl5dfj2#Yt*Z7?n$>aaOsK2M-kK0Fo=*qmmi;$*29;aMNyT)SMcoNXUJg!#=z1{m& zA8#(tnqFz853?*GYD4?_F52dF%>XE`h)3m}c9!5F^7Q_9X18phWll z!?`^F)f?w>I?&?%VHo9)4Q9QC_VM1_FWzoQUEQdv$Wk|aM1Ae>+S=VeY%Wjj&`}?E zF3-I+R$IHdJk8g9E3^9+gsivk1DqUd-8y(}?CISmmc5;t6>K~6OK)v^VeN_gF4%U; z+T?4g^!Tl*wPkN7??ujL=I|Q<%p1QofIgAeJ6!>E@f~#OwOcU%r=YZQB4+?qZ#fe) zfLgbfu7$_Z^cWw_vcK9ITU&v=cx_%k!0F>_v(P8z&I}HhGo!A|W(m7_KS8}}OojLgMJ%Wb$Y|U_eK#lCyq{ob5uIZe0Xk|WQiY4~!>dBuHk>3g*zlTQWQMbU!lCmWSl$2761a3^$^ug0T|2 zhx^jiJ`yqSrypv{#DmEhK9352%6h+8$TWK$ZHxs|vJ}Y@56@yNr`d)+1VY!)*4GZS< zWM^sK4;>dyL^fB|kWNj3fO$V(2V{bk86FTJr-ucrO6`&p74hFlu-aFI-NS3Jk}F`j zFt|4JIyQ>)euC>dsQ~Bw1lRkKz-VYyp1?|5v5d5OleJG(M zyo5F1q_UOa2$sFgdWrLX-lBL%kF&5#IPYf*wlBD=$IT|zg#5ZkusM9z#C{MQ+|t@LO$woA(oJQN3frkQF^xn#AQsqIzsNfUX`YEi=*0`w1SEtMOqA zjUQLpDdA}ppD6sLZSRb*54Y&4PMxsXocHrla%sw#_v7+M<@j(lz`P%Z80Wm7O{^dDe%z^KY>qd70p|TU`|-I|>~YNd zaru*S9KiwR{kU%!Ovw#qdCdE9_A_z}5*}dQ4?BnReiqXn^M3519p?S;xC$`uhli5Q z`yrVP z-p>Y9fKyy<4Q0&xar-fq<4b`6^L}W|c|Uwe9bn#%Jv_j?pO?5#Fz?50#iZOXxfPiA zv)ug6$jzlazA^9>)Q;mV_Z#M8-j6%r7UmW*AM<{k+-%=02=I*oC$Guvjy?=9@298j zbIkiWoejb_1_qk~^L{w#B*45Mw!r57{E$t;HwNg!=KVZ@oB;EFoC5QH&ZY(C{Wt~Y z{p>~y%=>W)%=;Nl1?K%Y1?K%6&30qnkE@0Aeh!Bdw#xbx^L{9^Q6^*F59PhQ%y~Zn zzA>-}iriLi0_OctV4s8591Ae-#~yT7W8M$X>J-cs=KX9yYj_|@?z%m|HwLbRq8raT z0p|U1=XR@QUt-=5YjySi(ig(KA6^P!-VasX<2()6=*9rsjC4B116|)9;5I_TDTM9| z1ce-fg}7I;24H^9I97{!KRokc-p_p$G4H3+M9ljciw(fMpLOh_n~>?|{bcZs0X~f1 z0#=y!a|Z0PnD=uEayuRkT`&rpm_0vU+7CiH zb)5a4h~HlE>FCt>ac+{&7T9x%_vZAp`1+DFVNwqTZ;^W!!E1a&1wT!|+vC~PJx$&5 z_A!I^AoI~+^-u5e z2AfSjwwTC~Nd3-B2~;Ay^TszBYgyOI1WUNd2T1sZQw?Aa);v>Km_ciVn6CtIMI8F( zRwg*mA*^U+VqYh$X=P%v6Bf2I!N)8xTim)9i49oci|`*!}b9C5RCY?u53Bhy3+Mt%W;w3YgylV1gzO` zlxXY785^K+9oZa@bYycP-$u-ENah>a9p*SwVPVg>g*_QvqVn4?PR45R`%gxO|70xb z_Uvc`XEyfrlE%3U7cFi2gbeHt_Wjvqb~|pCkG3BP=xI^69n*WKK=0V0ZGqk~auw(u zseGV!r1OE^F<5+{cc>NU9sfc}tdoTQm-z1+OWWv59v=ta8JzC2oRPX$LrP{r>aICz z4Cv5R=@JHIZ%o%9^7>>bhM1z}gfzb0mzU;$kW@z+H6q9(n0v>`$t+pbAbT@nJ6+Zc zPL~W$XD66rs?FR2!8-%h`9WDVs;`bA-4iJs$qkYC#0a#!7PMR+raVH=b+MOM&t1M^ z*^)WvRD^BbnSwfQ^sIwgnwGcBn!C7hN#pX`x>@s=EkA1LtZ`Eh*zbUb;SOhwKVZhJ z8OxU)3Fd3dtS^ik=LncPM^(;8aaN3TA1vNSTaK{k7&qP#py$uS+=C?zicG&`4%)kV zu5YgoiEee}`J3&+9$Wa}hB=Kb*gTpWo7z!2+lRUL>GKRVWW`Dr$LgT?fZ)2e<9=;2T z&1xIwuUtAe_5mTK8(a|ZS{LZMadE?(m7qJfi-GS6>1>O&B`SPaXIv4DJgKZnLesc^E9g zSYzb%HKe|-z`=P`!{SDEn!Y@+LvV2y^!%VH%a$&P`9pj`(+Zr7ni?$Zw?C{_;j9B1 z{Rf4Gk3^{V)-Ei3y9pRB_`UnWLVlV>G|qZH%z8sU)ObEt{Qs5jB`me$Qt|U`+`Er; zaQ7~1naBOOL#+L|ibH$Ysm>SB)B6Ke(=n%DVcx zp;i5sH!W_$8N7ehmoW)#(5OLk@DFY7!m8y>s}^yTRMn3dSvzvr;qLw7hjE*Efw)hH z;*H6Z5+}zK^X|Ok_71UqhC0P2(~k5|NV$;x<_ zcvnOxK-`Z6!lH~{rbd?}E^y1D3dp?r=TiW;v|RvG z{xrsK?}B!*PuSl(#BcYfSg@UI=I!*K1@^ogBj<|`_{o{zyGtV9^%Ciu@!R_l@it?C z^rM7(3nvPv3J(+>CR`v~DqJZ%QTSEiIl_yCKN8+3yhV7A&^XU%=T^yY3ynJky>X_1 ze0Iz2nJk)>|s95>6M+5*{UFI3(KNAiPWXyzmWS62qN#orJxFwL(7G zW&T%$=L`7`l=|z1{G>1ChlS4x84`{9LBc(SQ-y~Mmk5s)o+13M@CxD0!uy1O5N;K| zD-1EvS#J;FAmN_EX~G6!v+#If4IVhMe4TJ_;dEhxaGmf};dg|W3Lh3eFMLy&24R8z zD};T7!-W%s2ML>mD}^Tu&l6rEyivGW_=NCP;k&~9a1LPohY8OS@=LPR-y$q3baGeW zZbFOW4!e<(jq?n7hU9~VvxIYn%Y_?--xFR;#J;;!$nZ%Ctj2w2dnDf`wD|7OGtv?5 z9u+=Gg#HD|uL!qGZ`^34-u0oF?%A>32A zk8rYZns9}1jc~p2MB(YeGll01zbm|0c&YGbLeELPRr2jZJ8z<$zm@!$@JZqG!k2{a z2^r6n+nE*eeJEu=CgiD-4;6Y&>Rid5liDnKh43rF^}N^h?bA$tz$i_&`z>YI|^6Ef6>ZNJcnA1Gfgxl+jI`?TvL zts1KM*b7kFTM!E2qArdyvZVpClf+yTAIZvl#I{3EhC*@u}c3@>;({ z2lE(DhMg}%7wh4VfuRU)V|v=ezix}2`b(_Kw#UA3Ab5-mwta2wo7-+(``WgW zcOJUs>TQ$OUcGJM+SS{3U7Oo>X5ssPd++_9yz=z=%3Dr(`I+VkZpel>O4%`d+74cp>kzs2j{sJv?93m6g85j@tvpo*7a&=)_4 z5q%1BMnwiFlZjNS1jj%kUhodit%-Q%I6@+AAD~JEye~)|2D{|c%0taO%}-J#Plr`< zdY7Y26%3(7232xFCEo%jGU?M$Um_DsgKyD66RBVf9UTng)WEVSOuvbrRBd?!)4!qV zsIuiqCo(A#&67*;lkVN+0jSa`-pUp%L*aOG1X@)vumc;Eyp!tXmJX&PHvl#CZ0Itn zf{T+i@R>aXO)0pfm~~~ZfX9L#mr)-p9EqP{NEOkZ)X;(-WO?BgX7E$6DX@!6u=^Nd zwcygUUE^WWN0Q9Zg3FRDnj{ae;HqwSzyqnFWKf_JdqCTf>Eu;NWjb3&m5|p`nHiGd z1fK8>{AB9NY%-6dhGyzjV=7EyLo)S6t^t|w`=~HeU+%=>a4n10cXOgqLo-8*xVu3# zLr0y1?82|&rvxh7HY97{u_iMzLmpZ903Ga}_1jlPakNClqen9{dq~WLoQ{(jBe6K- ztd`845=+9nDDEY(Jp2>O?ky2v$mw~k#O@*Qk~8~AtcrEQ1stfMnaLU6wugV=Mt`x; zZsF1EM^K!SrD)X9D(v*kG}|zvh8|6MrsR#_cCA2VNi^0r8Pw2qsO`*n=I{(}`dxn? z(a9bF!26%svW5cJ1*!0Uwxlt85G=u(3aw#tda|=b4W;A4Cj4+!4e1mgAAlPAV>UIj zGIKt}kUyDKr38?LLdL?)to9XQ_i)seEJyVVGuLKF$RRZ}b6qDDAT=~|y&nmrhGuS% z(h#HxNS(S?N1{GxP;)$BsTXKqs2%J4yM;%(MTJ|ukRjvh8C8PrgQ zIL+ME<4LqOQC$qM6CE`)bH6Hb)X>atwE>PAn%Say$Ap*D z)q|zIt?by4PZTl_mDZc+sG*rhhf!IFLSd%4gHhl56d0N`alhJ`J-}=QwBBkP0JsX6YUtms{FL0^*{h(2I{O*9RjeP>P8p=b-sG$?+5Y$i}BSsA!NCl{&A)XKzHS{jJ1T~b8gNz!= zx&IkZL%W!Tg@os!;C9j@=#a=xGLenLPU7>&bc$rr^7u>8aDYZksq*`itWoEW!?w)` z<^LahUjiRhb$|a}W+s^|1Azo4K*WKBO(C*_7B#E_f*^uLMMHo9LG}biMMcHkT5VBV zYmF;fYpZps+G@3Rt4l3fwYAmOy0orT>r!iL{h#x_=gzzYT{-jQV8p`3SxE7r&NrD=BCUT_h-VJIf4P4`C z`p-^+8tO(co~9x(32LZj1X|>QC*rKWVif9amjpHR308FkPkwFKkp`>!4vT^s>g@dV zWvm+1(DCSC6dO}`DcOK(u^7oRUhMGeksoZsG;958`MzV)oEB&poa3~ z@IsQ^^|d6Zp}#;xH{NxUpoa3~cH6=}f*Q(JUHeb@LZF78hOD55GO9Awzv=9sKd7KmiC9?-9_)Nh~$*JlLOI*Sx#X(KfZ=NysiDWeKzWg zpUP(Aui$_m_b}T}+u!B0{T*58QpMHw8Ug`7-o+l?-Tq~ttqcd(0ejGwjZ&9otitfc z_SUCCNZOgnLBA`JmUm%Z_mHC-+i7i(*OFIAHZ3ab5cXfPBj!kA~!1 zc5w^#Fxa2)SM1gZ8+4n9%rK&qX1*?S{j^gs52i7h893J&Yg-t&-x=##7>HX-GYLi3 z5{S?|oC=FSh`?^g@Gq+MpFM?<%yt<@iS_wyD>0M6S%S7#wxEGexD7}CiP-akv!)TJ zU{3~b?bGkAY5jV((ArO_OMvSXCa%Yx%Sr2G?5yWP;I#@9Z@`|*N$bZ-<=4`43KL(z zj-1o_p#wczX#GX0)i})Eu(N(5|4ho&No%}P`M3Rgg^3%m=W^1b=#KSV3%o~R;{Dij zIcf1_0dt}g+V~}S2=@G7`q$(8@_mrsPCN616Zzh$Od{C_c*Md)WnXy3?jL(8Hd+3#&w)Seq`BSRJ5gzPcA`C) z+{o5FKlXeKr0`CO{`qCI;XXSRI}f=N`2#?b&mf3J>I>|PrSb^%m))OpLXleclG`1=|hdCwdbue>!CycOZsaUIDi z7mqp10H&|tI!|KvG;uQ59f{KMW#PqHGWEciU5QKcRQ=C=uS#fZc!c z_L*aVE+fG=$^;hI+N%k&Omib-Z-YSIitt@0qO+sqI?}U03lao)wtP;eFn?*|%DPp< zhv?p6l)>oDge2nOL%pYT_}UIEGw8=4q8?%V>l|;|v6Q!>;)|*Lzry)7p6+MtYaFL! z{-JgjjLq-3?xG6ki1_Y~4oY_`*+Ope*!AR;8aeX4Bbe7Y%6Rs&b*hUt>J>-%&a&b^ z^m$+xegQ>i626vHdyW_$rRirG(GmK&=l$o@2fX@iKH5=vje^t-UdZ6Y5zxl1UdCV zD=mN%3pn{il)1kwcZMX^X)Qfy%}e)c32AIviG!RXVp{^1h0B|dSlIx@Mk`s5Q^eFo zY4fJ73O+;M;k-&r3Xzp1n1t!`A=L9dL6lEFF7jN?$MP}l`kqjAGyfedb?M5c1w@d7sO3Wxp>{pz(r6_+!{(kw>^Y?AncMRTKd?9)F<&k6KTaz?x z_nQU*JXc1x7=9o{w-|oJMYou-T5>V5fJdF%V$Ky$HX;`AFVNh!wGVN;1Bz@hW6s zZY9%C5k4g32z?SRe}Cq02kxeDH{odEM4{*O^9>X8&lN5gHVKat@<%fB@x2J~Tf!@Z z*9(6tX$EC!2`9_`CQ^;57v}=WQLPq;^;rYUwg``3-{c+** z!Z(E^bufK*;S}K<;Zor`Avre8e}V97;jO|4g-;4!5&lzHf(g&^mBRkQQNk%g`h8-) zWkT~`4%_^f120niSp0LueA9)82$u_w5q?Yf9pNp)`-E=_v5^Ir}$|K&jQUk)_?<-o=G^NjsjE4*HKhw%5por+w( zU4@>@KTY;L;bP%(VYBck;c3G2gqI18vyXl}KpW@smqO3oe@gjYAYy+-X#UJm?w_)G zi)VU*i1FWey9sPu0L zFH!sz!tV-ytn}N3_bL7%;UmIll>R5-Yl=5N=IB?5-Hu;aLd5ZMWB+kk8Y0?|-%*UO z5ZWt5*wwQ83I_^@3a1G9y~Ofg7TWg#?0K>m3Reo7h5Wyg<<1sh^51o~XD_UQ_G%jVRmGnt{FczZpOC&uHvh9_`Ckd`PiEM^m;Gnq%R;g@ znExGN$nO`}31NxQcoB&2BHJ`a--x#Ia_aSV0JYqZE53_wg!ZvLi z@S94%SV;C6^ItEt^*vzUF5A8*VLu@Im%^une-yqbq#G;N_m+@ONoW`Fdk|PGEEA@M zI|{3WgM`C`y9-APCkdwt4-(c17YR*!hjyD}A1*vmc&hMhAsw!Y zvLTWT{e7nG{UxLHYN5Z+^p`zSI7&EF=dGMJ9@Bk&pGX4(1#?X^RPr@#-#h%*yYv3s zbT9*PK5$FP{t_FCaP+St&IfKhuXvOQYO!-GuX42P&ImIPcg~r;v9mtEjl_BH!%3vg zr|kthTHh4Zm&BxGeVm)VK7KFxG6)8B_%2+9I{oI;8WG{cOxui!-RL_XNoznj+V0GL zcs4{nw##_m?%GHh1cO~6Fv&2W&9~JIJ6hjm1Kc&m`ta4Bt?zV%eHjFU15n>Y2DJIK zlVL~ey8-phMI7r(VfX!`R?wG0Ft`}??X`{LrM56yUwMr?Pppr>mVJHSL74S%K5%=X z3;bX4L}+6g_Zx&h-}#ws>t%kbd;r@@d$jg*?z_t8fN1|J(LbCzJ6`@;_x*baVchyw z0&H81`Z!np#=dbQMy5w_0rJ%%lJ6n#^V;fT{cIEUWw$4Lww4+A`r7Jc`lEk*M)8}^ zx67bmBQlZgqxCXFhYqy-AFY?U!wq&;FH?b|dF_Vtl1n%L;nhQyIE73yvBv~xLY6=y zav;?)eYR{mvUKQ;S$)iFTN;jhZOa6xMNU34IqW@n>V`^Yx7Zu)W4+!f9W@jFzgc42 z`CI31hurxeJ9i0kC!iSFl-24yc>Cd7PC`HKIWpX%bL@HpR{>1 z)GvQ{wby}*wp_l1iWjI~mQe2l9ng|TZ|Cv6wq-BWwF!R5qjeRp-x+18!?`@$uH|2X z{7WqVPSN~(uP;M>YJDz05N#aDHmI(daO8+By^g$X%e@$_QX8$)*S|(j<#buF*I3-w z++2%?^chf6j|+xOf{Xm@5JIoQ=TW#K=c{SRRvyMTG87lH0P)8#4f94+?2EjRu-Nx= zUcqxrp@b!GYQ>?1cwzxAh4_3HoYv(Siz>*cl}wz(8j=NT(S-CW@k7{LrffX&#Rni) ztbZBxD)A1CA6UMc<&*Kjta1;2w9>0gK!Gq$6%AaOv-P-%Syo%P07NTuW&U*}m@9KK zJPNtK30#?*Uga3n2v_Ee4~q7{$54cfx+z!YB>JRw!UtTLb8dr#n##uj!j-u_&qJ>g z=K~L1nX_n|4`*;?emAm4^ePpIHN8swDum$5oTF0uCw$PA`MYd`f(f`XXBcgCfIla= zGIuS;Q;(vXaAoeyq;tbPxZIf~smoY&a5raqSLQt3AEH-z3pLV}x#?9%!hkDtS3!^( zLvuHo@l;ouUy_+j?Z6`#C9@>ek6qhcW@+jhH208Mp4x&#ge!Abb47}>XSgzVW@Uo zbJMHXc<1ygFR^EJ`K~MR)D!G?YrP6wnSWfp%6fE-uFOeJPHp6P<@73iWPmGkH3UvB zXI<$9Xr8Xjy

    b%vsoGg1ItRez`JtmeZ@imAPGz(5w8CP5nrw)2qOh`7*1>=~dv$ z+?B0J{ho)I)2nbs!j-w#t4!dj$>~+-!yB&5yQyRIdV8=B}ZvD|2@MSy$$+ z-BGFUu&SJ1rJQDKy$W2JyQ;>e{={zlR(+n5;ww|QGWU9wwM@)buy~=%TH=Q$&jq$~5S^eXJcw)85D$4UA)dKG1L zdKDVm)~oP3jOtZrNA)V-;V^o=%E>qYb7gLN6}y*2^eQ{@@Ss;=V|h?8&F1lckX~gW z>NQv9rdOd@iLT7OUga_tjp$X5V%5;A%(kjaf+7Z5=~d{;d;m^Ox+|-S=v6kcXhg5_ zRUS}8uW~KVK}4^@_XTui?v7$&dVkgjy~-KZw9~85mATie@cjl|ne!_%uWE7ndbZa_ zuR>SmE`4qKNw(KkuR>Sml!j0im|o5rpjTlJOs}#50lG406{c6=yArxGcM;I5yv2ix z>Q(Mwj;LORaxJB4?Mui{#H@YCp3=*pZDl{DSN)0H_5+`Q8lam+rEUWKmA zO|Qbc4qcg>UgdW7@dNcLOE4@SPp`sb#AWj#dX>F-1UbFRiEKEkSD}oi`&ZDnL^uL< z(TBO|RW3osV>8!bw1W)xAk2{Z3IWWEh@ua3=~e6z>@?|B{(?e<5U*@Pfr639PhaN! zU~EIL!rx2bH}mo7__oBbXB}z?&o`|KkBz_mdzuF2Tc%ZMfX#2mp6!|Mf{xcA{1@ym zW3Mvz>=#-bdqthL)2g(XR^>L>-(?)NDwmj6WdY_6*W>Ah;sMtatqL#_;q?_f04`BM z#b_1(;8NVnusHxhuL^uzpDl5dm7wSKLhP=Di_5_7jy>qb<9R+?;>T8^7AbrRb|qXK zh2i^I3I0k?<4NE3>UJw}5mGM9mT+;mz`mX(dN0O@%l${o-3^CBji{^N#c>_raoDka zq@E=wV2QVuwrtn4P^<%)2E`p+rQMO)Oht_kD74L60h&+Q$lG;ZT@*${A zqYc;LYC*V^xWR>$D+f;_2t^5jS+;WRj#RfrbrAfk2=3Sk{929$Yu2_fFxeR^%?0^d zXRK~vfEOgPHMcPEh%*jrc^ZN4Xccu4_>T%)yXUnqz~7|i=beEgosqwl+Tl6W00-;@ z-~F6xcXyHC0Fa7YL<{m#i@0}pNAqREJ(h8Q!sFOY6!J6ztY2>58SH2^%^+m3o7?xE z2uyeJgc;c7_MJf#h=&Eq`Thj1cOaO62#BYkevNDYQDf)M#Lf{zr?l~+;=5va z@b^)9b_zJyc9>Mo{B7Xhg2>ge7HOBXE#%L_2Nl|c0uQw<5#jB@*McN;0_yS&#J9KNuGNgHqIK3d}^D+_8I*IXxp4i`w4*(ZbGy=j!GN`JI8yp-+0UO8!txg{yyyEdD8uf=dAD>FEoF#@x=R$ zBOcxFf&GY21aerocf`(7<#BT7TPhAMkHQ}b$2Yn~`}+tU!#js~ti(s~y5@_Szvte~d*UF32j03Olt?4n?Iy zP{2%zNPj4}IXh8-vdR1oHHnHIHTjdFAZovrM2HJZ9N;r1Dt4)<$%jnm(`GDVO{P=| ztX(F_htK67+cGF3Nw+zi4|wI z5&@ZBiVC4M+b9}2!VfIls%Yy`VHqxd@gElUIM?V6WXgYWG(N5A1z0US$E~L%##X;r zHE5X8`#-t#2mb*L8qTu+K?#tFE2!+*uIXupuluIVfQ1WJ4w%1UdGqS}`OUjSk`UDW zf3NAuPQ0wT=idnf&qlFWMGlid2SMybs&y<~fx&2-xMLOg(odKV~tvC#B3h+ivvo$z=f%AHO` z`niffU)ZAft7Ly)cmomTZd3Zt75|{{VZ}cw`)Q%+Zcy$oN`F`J{}RTK#(uOTVq7{3 zD~Q;4AR?X4znI=%I7spQKZ)_RLfp<<@#+z6cB!yJXfFnFKKcJ7&nvmD#4ic=6gCJO zh4%Ix`S@;``HvPJCp=AfrtmzWeZL_8WwNgn{y=!6@K)g+!uy235c1_M+x@MO{{z#0 zL-?-nU&3m9M>8F7mks?IBO_$*A>@ll=9?t+YmMwLoA2P6PXD09MxniVhs}4xj6Yg< zobVLk8N#+Y9sWPfaz7RRT=<~yG2s)!XM}$elC{F}ZwUV>>lQuD_kI4DkMLQ>Bk6<7n*Js@n_1uM7T-#eIYp& zEPsdaE+P2_jHkb1BDn^{zX-`LpiSxnF(a%N)(Xc7$s=ICgM{Q{(OxCINO+l$ECQzA zCj6D~*TPqYuM5d7V1BZrh-Bvy;lt37Ts+z&dJ@SyAkGjj5H1#ygu?W*g_jDi5Z*4l zQ<%@|I>|qMTseT1NB0boWa#gEZSQv(rB@5v-v9V#2>Zjo$%qq$Q-srn_S}v1*|O&d z7YmmP+ukqNDt?`Cy>Nr@6yX`dvxFOk7YQ#DekMAnZD^eE67s)(v7c@jBis%H&KYj} zj*D)%h1k{upUj6#&bGGsn8vLScFwPl%GV!x+O`}06N__|+g{jx-L!9pu~!L0Zu4nl zVSkv3mP zJ?v<^Pxix~x9B|EWqUjhVl#GM2EpKEWXLd}&8P8Nh}L&&jk}InA0A<{^_`5cFN0uE z+}XK_WSE;zI|1QneGj5OCbB*bqwn80T{J%3_G8q?`>x-7edi#eReig-<70hz1k2WU zIl?S65IeWC@j~DlKgnP-jr+AipRcyZwzW&tBr(6=ZbrW79Q5<$7G#L_?@{!x6mjfd zN9_K1??)Jiw-R96D{boYZ4o2WBgpi`F(DGeldX^Sv(3nG1=Fjbdq$k!e0?1d5zY4; z`p4%qzxjN-3>xvtv`a$=j~JZc_R-oU4cu1Rr4^e?c9{0k$t8byb@7t;%kcVuwQszB zX_oX$AFf8~c3td^f><1D=gh*&J|C@K^7&)PpZ5v!=OI6pL^%ah!&6i+#fMTsR62}0 zDqnYE)TS{l57&?L3Z{Kb!PN5VE(b2!a$+k56LnftBvF;sR>9nR7}w}PCU|Uo?Hv3ucVfVN~~=k z%MD|WeRJ1q&igaw%h-c(0lT>w52+n5xeBv~H-;|eHk;kWoPu>5cUG*E}Il_mIq2I@sb zCF1-Eli!R2VXPLtf(D8mvNd}Wt1VnG6RG)Fvxi(A(?F3sQMd-(f(9zZ@KvZ08YspG zMU(L{1)*Z*mj;SIP*R=n0S(kQ5KT2sKMX81P+buVhIPzth8YqG(UrYn#T8yWXI1p%{oS96K(^@dN z+?gdQBeM_g=1i}FvQ-hQxMt7QXt(Ghe9)}m9cA~s~|`XKwfB| zoEc9gXnsj%GF8hX7$vhLMI{_GP-;AN7tK9nx;1;CfpV!8sV%IkR%T_Y4>OOJnTcqi zNT*Mk$Z78)hB@lx^!)J{0*&_MCPVCSWdqP?$dYM{IX1WH{k;sD290$L)gv3eM2}soOPuqqj_qe_UTxFHRM%IPx03nG*FX}iEH-sW#(r})?+OF znmy1!*((OD+0(>^p4Vif28tbG(N6Zk+0yAuelQ;Ag*T7(OzK>Wl1>A~(XlmqsDW|^ z6r{h-!GH$pYC8nCW)C$`&Q7K;XT#7yIlCnN4jQ2b%9Sro|CTn^?0Fs!4Aej!$o$Yi zx%7eQzwof2fpTl=3{9WH_Mm}s=_Av590h2gxF|- znbbhJ^oi-)XhQ=9MJ0}T`h2g7V@`cMOPhxK=Mn%5OIP`s3E z&7S$J5E>|6BerJGWJW*()e9}ynmu$cMGe#<3|Xw|=|uXQtOFXTL6!sFrV?>p3hpFr z!GJ_gl9}urGSP2KBK}KcC^zTWoS>1cA(H+1eAhCu9H(tA6Uy(12)p}p7TU#(+s9<& zJkZs!rg^hX#rUtGbs(p@DLCe)>BcIcT5`M(=FR9tJ}EoKUyBY^DZkJWfq| zDyxD9ir;3e>QNSj2Fjhsc=|{l5HwKCjD^Y4&+!~U17*Hvux5{G#dD(iy= z>TIhor-8c8x;i^u!>&RD^1yS>3aLIcHCUHfnOLRhnB zBeFsR#VD=K!}}H{7+2*<#5p}HLtcFTTHw;*i8uv^MVy195wH$GvNW7W01Xstz?wZj zV8hTrarwhA#DmzbXsi2=VI{(`XoDK4uc7#k^h|ebhAR0WgFOf{=2Ho8;*mfN)I#LK znmxTxzVO7*R>>)7kH!iih$08Jpo)gqKyksGMEqj={5d{*gn2lM@G_@?x&c|ag+1vo zFTA`H|6d^)cO>?nE7;dfrN2Pj@vxULjvD&#ijMaq%y-&7u~(UZ{yP@80QOAmP6KsS zIqRcOC;ELd4b=C_*rOk#4|Flu3)KYQ#D5W0HEioAwocozXyRz>Rb0kUaT^i*8g{3F zdLUckXI6sV{eFnum2h#tfc=1#;N|dMw!}SFg7bjFF;~LHrO|~B*n?gZ@v#ej0k~e> zZzaw{%Ga^G5-yH!1$hSxdh?Ol<$lF-{}^ZIM(i%Pi+ct3bJ($cqz0FD6DO5Z(J-S^MEN2}h-7xkC}fX_cu>UMZXjyP zAUFj(ggonPVHLhBhH$j-LO;sL*$o7P6kD5j7yz18@R-U_aQFFp36yVwM(6L z3h;av-iLT0_FPU{m$=kvHv_p-zU0HEUCBzT7<&))Xl!K*V>p-{gEi~gN~;+Eq)XdM zcJ&V9F>GjWDv=^9*E0&GXjQt@X@h~|TzCp`B6j4QO8HIC7Fzqb)T#W+Jj{hB6OY91 z>YR+6w2pD9(|G>AhQ0N%FovgdTgSrqD_z=F$AUxAHU)SX_Ew4_e=<$Pp#m|=yYsDY2VaPlD4D1*q-rtXR!BYUdBepuFc;3UaXGcWyLUAWm z!ZSNWf0-b~T_)KBTa5g?G;jt@WQJ>~wQLX9R5r7}hFk-CbD!Z=BhFc5~|cjrS<-oU5GIe)Ds}qyLuNh_*PP{Kg^S&aWGeCkKN2Wb7PN z9+5vPj%;*`_M3mw$DHfaPqxn0c6HhpLY+3^a}uXr@uA|heG`?7Af$@w(x^W>JCSy} zv_yKBn*7-xqBe`M^6}uCUHs;Ma?L6zfJT~X?Y}_9_DM7%yiwHU z7QFgUwOea(-v|g>;8EDrhpU@cU`Z#4Ot7{Pq)ms_FJ03RY+uo8xkg0m3}Nalvo*o6 z2vFU^HOn#bSdNWD=SR*h%``CJ(okQV6|Fu~^;`Br`kZBOez7;d23%u91E#L6*3{g% ztf6k+8VDQLEML>quz(Z&@SqN>M=fo@l61@J*V-a-ONS4wciFHSm95jnt4B*#{f`Ra zR*m3Ia{KC414j(yzd$9}qw7~yN1nI&xE4`C&yH{07uxT|oY@XJE;4~=}}6EMGV;(<5IHf}rYf5|58 zi1~IF?k1choGn}=yi|CdaI^3a!Y#u0ge7Lc!YhO~3lHM|)2Mf`@G#*?!gGb! z3x6tnSolX_Nz&C*DeNyCC7dFhBU~z6Cp<%Vf$(bKZNi6ye-OSV4Dq)v``=MmB^)YT zFFZ^5fbciMw}oShTs`{==Lr`H>B^GrtQVdnJVW?(;U&UrgtrQRCw!KObNgrE%S7y- z)f!R*@SVkedX1Z3OKJ+^(T-`{fOWFx3r*vOFG*WV3gx}F&DN4a{u5R2S<3I%lroJQ z%3Z2-uWh?d`EFAD&t%^tG>sd|J*IT8ZF^4XFDm{`+3yHVJWV9wyvXSSuVSoGRQ`=+~w?MD`-#p+fuqMg51#Ch5YCOL(u)uTAxY?5Bj! z3;o(uugmspQ^olG$>SBa7nTW0TVuLkn`(gUK|=ffM*8lu#|ydq0m~gE^lMVBl1<(* z)4w7-TWBY>+NVoKOexTBD) zT&CM|1#oxSeyyqlWFIUf?}hnK5R&sko68{($#NmyDkQ^&_QOJQT4?`G_%9*jxRc*P zwC50DTdmw7N}nersPAK;89`-OO~kUTZo&kK$Hj&O|655Ov6AK_lYy@d_J zMj?4}EcX>5IW@Fz7v3YhU-+=_F(LUj%>SA&pU)q#i-Z|rwQ#C%Um=QtG0%UhTseT1 z$FLeA$6CO5l$D*6wVgT5zZAZ5Uvz93)c$yR~6e^ zFWewJMR+4 z^Jyz!N9%iKkh`u~A07#_^__&UFN0w4JnFld0c}3*c-YbU{>l1~$oe>pzJI)id>I6T zZ{s2n#%nHGU&#=6oU9K+nXT_Kgjr@Fc5c^J;`@L%Ds4>TevQ!QTUv$Z0OcY0 ze77p>lb%Dqk=_9Mu5t{b{VPZRaO$?w{@sT-d`+$d*j8EHT1&`wxe;;u$Zpe-kMAw` zeySsOw#)k2ChE&>>oNcOWi3|^%?{Y3`Kr-BKCk-Cw`>1~G%j6Qw`$0sniacbK5E^v zU55`JnX&DowSV!R)>BD;NIx7@heIzPGxo)JFcyzi zF~q-(b-)rGxCU7M=5V*<+}P%Dr-^ebZa-!2Kq%JwPY6dvbN}t(KmXZ&8(MSma5S!q zl3!xP4)I4DL8#D*aq!Si*<)8;Vk(9S0<;Af{n&me1OeK<$PWS9bmWWO$IR2ZEU>78 zFCiBMXz$TV7Mugf3DDB4p&x34&}=+XVtfvQ&}_D4jz7laEARoK*>#9Y#5srZ^N}fx z(QN{RW^6dt7cmf;F%0E`6Pm4uVM4P6x>I;DVj(np9Fc|941cGL@j(%1H#KF&>k*L9 zYh#iw_9RHX)5dvx8w`utuOndxm3Y zAOxY=0;HGn7XTOA;u2J;`Ais8#xUB@Vq31ocTmEB~xXyzMV zf%^l5X1?(kPyvKyYCOfKe+bQ-S)OXguI(waBE@%V5SqEv%G7XHHCkpS=r|ZHB||K> z^(cFFE8E?>h+&R8`beP}O%s|O!(Q%V2WCRExy-(=>%*< zbFlAEJ!59y)O4P>2MXUaGb=Q64P}L9?f|kvGuP))sWjXDRfiZKi>qo=eOc9`9m>qi z3e8+q<5EX6^KaGXDXDX4{;udJcD&P5{Az*Fj4PB;X!b+)`I!lurqIl#k4*oV=@6PdZt0`a-()(3X6{x}n@-Y((9Go@mtMjVhtSNWPfT}U zc?iv(wDMEZd=RJ5%;le+=8F$5w#C7r&}>iUhtTX)%Rf8K>xx1%UP>l3JDd>^n(-Pj zp&4H-P-wOVB}`~GkyS!yHV{K*LbCykfY9t+%V9z@UJC9c-GmNDPLi4I98MBn;w0i+ z&a6DVA2FPuk*tjJ=krd>#B!XrxlAbk0wV10&sk^}Gj1QeE~~ta-Yw^0LukfJwSw#P zn9z(*n`yguLuf_=*LZqA9xsGuZUp1$#ViV;nPvo9N)N34pvZVJt4 zuqytVr_jvV`RS8sLuh7i_o}ei76bPqv%2ksX6-PH>3=dSgl6lJgH<)shS1EN$9Vb- z_7XxfW~R_=G)93!Gk#6vL1^{{&k2NP?kFav`C^1Zv(;AL^z@gRAB$}rWnG<}zJTcv znz;*Zae5BZAvAOL$~0f#P-y1twdoNULki8h+c}5OY&|;!p;?VZKxoES78IJX2eGP) z!u0pqB?!$}g$d1`M+${zE&@WcZ!-skW-bCkGma01W-bCkGrs?%(9A_ZXf}@hg3!#h zLZR8gsD!<;F@?~KHalfDgl4q&@U|D4H6kMYM;-!%W;8hF)FDx5c7)jwn(?Mc!>WSN zY(09z3rV&UntdM;-FVlb(2OUyTMfq&LNm7N+W(0!1fkgjh=kCLQI#QY12(%c!R|*m z5$AhEG^w=4yPR-tMT6db8ok1-%(H(OhQhWTYnI zs}R{E+?n|Y=CiDMA|i%8`THjvRLCsh^s3*ZTsXM+7+4dLz;A%6yU}Jiq~z-e^P!NB zht+rCBOGRN?;!Xbc0_atd$lVojlWr24}Qdi&PcwiZ!VeXXhUmC#IrX7;20QCyC<} zPn@lIfHu?HTVdxpOug!;Uz*a*aZoki?&)51EZXgY+<0*86_=jU;=g&CQPyT zre@PcO?Sq+h#&$nw(+Y7Iw1mUpd4$4)y2+6L`t|eVA_Xz>dZKzB0?qC{aNfjtCUcQ z!J*huA7MCl6Ds+mLA*Z}DwA@DGK+`8i!lsl5~f?p<}iC8m5AWbyWim!$X?&h%3bfY z`OiWuu>Uo-6VEev$B=1QHm_m9f`$ciMrH;N95iyks-Xjx)h}7Gdd||ud2<%cpFang z1}tB(yy5dCp8NM8pU;vgL$G8>S-KpnaKzSziNd~I?BtxXvNDjGQ#&I(JwF@;2KV3y zf4dj>*r`OS7gDQ8%|^LIel)UuB4q^eL8!GH>y;crrnWNlMsOFTmjMSMS7B^TO$Ij! zkfawht*BdEzkC7QzdIIeonr?26)SR7+vxivtRhq2Tp!dOJ|A?@W%E286r5VKJ+pS~ zZgXZeHLPx$Gk7x*EOtdY_6+cy{HK!%M~jQ zZDgjVMdT1?YXc*;p6QKEb@SI^q~OmU>tJRNq3N(j&@?>{bAkNtgRyDtdaftdNombg z#({v+>4$saa@U82%h6C>ZsiglNraN?UFnZ$Tx7$zsD9b9dYtA(%MrrbBn|cG%Ib!u zHA|c8;CY{%&^F_K`25B5>=0J0!D$e$bQ>pVVI!td-SWm2^UxtQ;7G$wi&v~}&a|#F zOB`l5>X$lNYJJoE9F^5|2;D*BLEV&TWB0C`861uSAYqeiV;&)fcra$+>PDk+<2)VF zP`}!p1V5(aeB-R~By#zRI@dBHnie$Tlr*9?x9ov=i$|qc-DqiJ6QU2FADP=|c*tNh zojnXUPmE~0xUOOK>g6i}cc3=LZ0-o-PS-WrDRpB~H(}D0@!9onjGy1sD#|StlO?K0 zPIlvR(61Yp<5an6jw6`Aw4r|anw6yeHmz)!-?*@`VS!&|r*Zkh6~W4JJPyzQwPl+E zy!~anSY-iKVfwD|m(HP)wQt-S42{cHu36nsx3YOPh6NWL%ef;JL0s3Pqaxb~+Z^{} zRksXN%Cqj9nlY6Rty@~pE{SoUBi`08U~gtkS+RUkP`9X|8Ml`PwuMMFav1I-SkDEi zOIOUpjEQt^9;d^8jYl>FA45ryyYq`JZHx2ZY%kzNgwuAooi@9g)p%XD?d8krm!dJ8 z1J9-YUl9#N*939n)Y!Cur_yF)?y{Y~bOrC3tA~!{G>>WpY|$N?Bpl!XH~QT&eK~wH zSFBjtl)*PcW;7lj#_RDRgRg}74NXleRySov4ruix(JwQyW^m0Qd%PGlc+ikc-_;Gc z6q*|PWe&mv#(d^u}itwY|{g;@BH|hL; zi^%^2iCu``x%DFAgz~2WeL__@L*Ldsqle}eEL;Wfga2>&X4U)T=6 zNLbD|S3u)f0qqYh;AEvAAY3fun^2ZJS$K}{GT{wEzHMhd<46JDke!ELbd2XKT4F{x zO*lt*sPH(Uag&kXI7-0h75}C%hAGbaItqIT`D&Z-ONB=X=?9GQR|;UM##_Sd2F-%-2;&$5gZj3r7ei3#SYB7tRsR z7p@i>cNz7ZNgL;kE~<#<64CYr%6FCUM#bME{E6c4lTBYzEcb}wpOXDYA#M{^Kc=N2 zzpL0D@At$Cp}nDiT`jw>aH4REa6jRfg@*{|2@e&n5Uv%j6P_qMRd|-r?uTgq+p;ef z-YmRTc&G4Q;lskmgzpIdDJFyF31zAL9aPRRdn zX!AdQ;!NQ|!aCtXq1}Ix50_bxhik!)KTIp{&(A>K_mHog@pvKY&(EjifaweIzn=j1 zMe_YVn9@{*<@?8`7~ z6P``}8Hw=0`ZoDi;NEhSPmH8dhZk*k!H%Q?xOQ=C%(lBSQU<}`CCtGL1KNDmOJPUr zdo$zaG>?Oa&2eG9Ct&ww5DbdiyL=3D^J&K-9IY?jBUc~qS-!q=B4rQ^x}v_@an1P6 z*LOA|qV<)dKK6(G!y#qsyBJ}X8HkH@f)}Yarg6Vo==06Mg?X6r5PUv9zcK8$ zpCg|y!#F=*ZbUfRzserDTqbzAa*87=r#?f*^xPzUk(( zF54}|&NfkBcAJ9vm&sbW`dB8KuYV7>(7Mmc_PFI9vaw8Fl>ap>lNo3{FZVfU;K1R- zhi5W_1`QfI)Z#yy|Ml}e)8$f*QaBI~}8$gt1}hNq+x!>_qH+Mz6MT!9GYWfb;P)5SNVSZ;I`J zIt%##oquJ?7DN_ajT-a6Q^t750w6h|nEA;G%fGacRFTwP_{hJ!;6y~@kKWXd7`gnb z68|t0oG?CF=YKcGqOp0b{F-h*K^i$>YY-;_U3-ROcOpI6*#@Vy91#`CU6TCsJw@h5 za!?t=XoH-v(t_&bh$L4#N|BtF+_lhE5Ttm_$=zheQzK}8NoF!do>X#_%#zeZ z_GNdOr78YONbVuCJVl>o$vtIOq~4@iE3-1S12d17nF%_M!l)&~P%};-n|{u>&(s7@zNx`^w$`QpYkh_D|%tLk1^|KXlFtlLsfM`gG%c zNJmqEqIN29l6CoR2;wO|OeO0J9W^PLvX0H`&cPBVj1?Chf{M7S1yEFAfD?8lyP8~+ z{2CjgrX+b-2ZnhVf+yUSLx{lIb{M$sc!EXf2nfcoR?Fs-rOb}63o!ZD=-=CrbXF4B0oDDrt*oi-NsvIXQ`H&iNoUr6CbpVbNmfWm% zN2R{Ys(#g>o0Y9ijiUKzhn>xIoUr7tRn@puIY;uhDmx|h2>blIqQ~ucr>8ctlfUn1 zD>%vdc=DN&dSoIe>^vUPbL}{r^Wc1ZF&lbblZ~7(o@*BEWFMR@oycYA#CV*SVMuDv zq|OPH>>E$c%}a80(r2+=aKe}mXEc2(2Lqh2uh=2P(|=<+IAP9Crq5@?a6azrlJvjO zND`bdSH3j;G;MIg?!h+}IbqY7ADl3kJ}~_v`j7-C%yG7crjKEJ;DovKkwzm*f)hs4 z2c3`iW_{pPtDIAQm&N^rs^ zV#s22KK?D%0Zv#)%VC@_UJC9c(YJWyB$>(1;Uuj?pAzwFk)b?%1~HtVk*tjJ=ks@# ziRCzLbD2;+K!kC?I1BA!7ANdW-p2O`DXK|u!oGonskjE6D@j&`$&-=8Sa(Tq!f0?t z?1j`MIALrI%TuIR@%X_B(~LliJn%%E)mI#WdfO%U43m$rsh{aQA|u9!}`DpJI3mpp5~8(BsgJTx311kS2I62VeW!k zoc0Ztg--X*~aa}nT#J;5B{gt-WC!l*G!f)nNUjf)mD8UHgywLg0i^?gma6qs0B07n^Q2H+#i+{prXn~H=&aKiRME^xv|GZt>gN#rWn z0rlj8Al3pS5kD0e8Vg*L)poWa6tR=nE^Hkg(!aNaus26(5hlXzYEM!-}th zwG2D9oz6h_^WKJ|m)Mi2cxRH|^Zpi=n8Ab3dnYVmpZkMx5ahiZ+5uqTI0oB!ZlrEhA3}KwFM;hZ}?9+!go%th>AxUgdlyHwqpDwa&9+Q@}r-ugy#W4s{kL-9KL>^&D%b2VVL-c z+A5JX&$8q0sf|P6H-GHi5y3ujr2S~KRlhNx&%=DaM?Rext(V02PsL|+)Qd^W=PzBe zpdr}qR`)-}ZfyNt&-jdd)3>a?d2!8RPNBL54GZhZ?P@+^WkVCJLZ%fWM`-`4!ted|Jtzt+X??c*O@2WPkc9s?5oYh!cCtLznR8O?$_ zd6zXCi`^Q_aG7j9r z09>*`!&$-;QnN%w;~#E=gxHEjSSNa&V|O{Koj)t0k&0|7_G^ysYGg3dL@nURd^r-{ zc2}|s!KyS)S6kLEcwaf*qL_kYU;b~pl8yfD64ZIBXqJy^6WDWA#d7t8R#8=Rw9=LP zVsUUQL6WJ_Uh8l{tsPv~2#T?>lO6Zhv9n2?1#fq2!lawgq{?P*QJ;l7Sy4-IH5)DP zP}kKgW0rmPTy4h@7M(ZC7mbk79d%ViU-6=|HEB}iZZEAEqmE1JXtz-s=dv7+Q*3SA z)*__T)^tVVHG;_~k~PN_JapHxW72Mm*Sy`6>^6Cp89ruevdrf{>+{J)```FR7D z;0FNfF~4rWon-GS{th8sv(VtdKd0Rw z~|+&y>ONAYT+%yUkj^>T)Dx*u|m(aoF;poaItW?uvvJN@HF9h z!tV;NC*oY*B;-PxjXlx&aRB*Y4#yzJjD%OP}gwd40oP&0qUvSkhUZ563#;p+Nj$TWJ!)SCL{=GBe!)-f>>;J`7Q|zKaoN8D6K{3X$OlyeVj78uzP(KHrZp zAxZ!8o6pyl!#faPY`pgU=I6_eh=}&@>B#tXM4CSz_aKbJ<7u&NL7V#6E;nN2vHeBOXI!^_2qIW@Na6n=$_~i1VATk7c6yUPJ##67!qSmwTBsf)w7I562JW@D3R^ zIK%CuIlL?TT5DMjZx=i*ymrH#*Cq14ciq^Rg8A|I&ST?m9ve?h82eH@+?edNd4Biu zohzR>w4m$5k0%o^-&3&j1h9HLB!{$&dH3NPUY^jt^X=o`8D9Eka9Pl692vgx&EbT; z6JERZ{lER|_SeAfy)3Bdvh#$o@5H-ZKjt3~zw+nc_IvppW8H{{0}v>A2uIFI==$b| z1DWXeFV-(T3{f%sS%5hd3zPhr5X(!@n{+I%pd68Td~y-LHx^Hvij+JqWiEbiEMCB$ zAhBfP2N?cX5@cJPym*4Is*q-18x@Qy@7NC&<&ncFes5lT#yfs*EE%7}niu1vHNW>T z6bSRipeN$@<~@yiJim8;q;AdcJsMr{{N77ZW0v2`?vSKwRF^2fw;v)S{N7#|xd^{E zkBT|*d-M29unoT#12+P(#_!F03?a|&eGBbn`MpL=`XGMq-_b&Z-+P{!S$^-?=-wyg z_u}9B9KZK&R*>WO8lgAG@8!c>gx@=gN08(9?#I65_`SE$%<+5Q!y!iaz4T`v;rI4u z<_N#HJ#%OIy(E}N_`MA@BmCa}IO$P-@6ohBjNf}WTFdc!ZM<{*UXt1({N5MXlN`U- zI`;ATz1Omr$1BJ0P{9eww(o-=opMu}Z_dpST@4Ia31Nps^m^sJqeU)a8 z-+LU*9KUxZPfd>Bdog>RIg&Yk@70_?IezcA*~uKg zmmIVRzjrNy7Yxzr|6H@Oyv5^a#KA3N{?!_r^KZBK+PT z@t`97Ui!+5@_UWv9^v;I?=r&gE#N3b_`SwWkMMgBV*L?*Z#nxL;rG(VWR&0gI_rz@ zd#Uh<@_S!ldW7H0>#7yMw~iG?`Mnbu5#{$9)ilcQ{Tl1|eEGe+4x{{D+EIS*xg18% z@4X3QlH>Q{G#@x&wi z-p5%q!tW(FI?C^*a68KHy@X9i_`RpIYY~3$&Yb5FelHi#it>A(WqT2RFP_a>@q5A1 zY0dBD(`YMx?}f|}<@fS^M=O5sbha7g_m=bGit>A3W{xPow+kbp{NB+#?$3zdJB4E! z;rCv{G5d74}xgDpX1-tat7cey0h&MWsF5#)`?E2hz($CWoSub9-` z0Y=^3EiX#lt-;$j98xh30Xeqqzp}N{%2>{wWn4l0YQ)0M#bCMOIkgO=*HQRATA*U0 zZYI;t#Up$sl5JWjZmhXbMB8CFsf_W(J%UMPyP)SKatW#Ysc3$3Y1^?uJOKAbemv`B zJxVHn2jnMH)aqycj#+lDa+Gxn`kw@+kar_&-Ttk)yaQTud24Ed zJxfNFoLt+^x!dG)$Hr;z*}c3l5iTY2LSQ^`j^c@jD4xhGocRH5Hol$;gXsiTK!2Ch zTNq*yB;Yf*<>#Z8?1t-wTUYFGvPp24w6R$yz)a$$$B^nZLC+Ri6R{Whn5uZoWZ3LK zIH&~v(nWi0n!QIXJHEgL35zYbAAx%;Xj<38fa~af2({VvfekJ(fmJzIo_;it;IrFd zB$LRS+jumU*yYNTL3eO7c_`eAg4My`UWWyPsw=aHSDcN@^t9t++hQRz=#Fs)fybFo z=b}Tp+HkX9=o4YC1!od?-0A{Ctv2?Mhk&6c@C0@@)^YOv+Ul+=gNfBWpkoC6cx5oM z+VPN?hi&f|tO7gP@~vV%oN{JdmCeY`Eys?!@o8I#Rq4Z!V=xrEoT_ph5X_yO56BMw z@NaNo*toHbw|zlxBgwW{7|)M={Kj~8+`Npd0@ryJyq;uWzMpaEprC7R(t=e zHE60Rlc~XbRM3j+bF|`ZwBww!=EXo3&XVi?&-uTi0*+Wa)R=(q8`=!=Aia9l!>?j1 zuc4pPC+la)2FBafkwyacq+sud@}ud%pCb+U<5ItQ;cTZ2H^c2>Q)a-zg)0ZlU$MM- zb^ZM2-NCf}KcNgq{uQB9SjZV{cA4W?=XX_JDI-2#L1-u8ytOaf9HpFp0Mt46zd47n z&Yh|EQtD~s&XsQ)Psrv8cUi--rUrUD%{ppzWpX@JU8w$Ia4t1-?o1u+arPd;KSwUcBLEQ zC&o_7J2_lZbniW+505Dxt_Wt0^&;X;%1(+ODI|}B`T3)RI913WZnWnL8-z{5BZbEa zzbf1)yhwPp@JGV!JYzSm+j+)r9Jcd}-8lTO^Ncs+B@Fq(j|!h4;{NlT>=%TuD*heW z{}hI}$1#5i5%rV`J1IURyIMGai1+D(iP*;|eu8kCa6jQ}BKCUObpFA1mJ(6VaYVHL zZQ&ilyM(y?Sw4P4F+Xm_hP>y~t`OP_BiPll`wID@i23-6i#SSHE9Cb9lM zF~Hg|Wo_$&Po6KFTHAOpif%q1?^O)*+;d~Tl@@Xz{wba3kWb*XE;?w&!!YabjGcM7 z)8@0OuNy(I9?yG+DX=4x(t#2Lbqr*kk$G-Ub_-yOTAQ-H`xGZdj@fS^J%xZwcY@-U2ZpH zkM?gvWc>IG&G+v3=?!NjOE(8t zJHF?HaJSg2@uJwPG3LJ|Hi|?%kk09o5OzVky>&4dgMF! zo%r4>_j-`eWLAAV?1$^Gqy{5&NaO&0Ft?7p$t&{`<1sAoAG`pi+pHZw8)e`#*p}M( zu(jjgM-5mnehRZETdfy=KB5xwi}0Dx<#n^`#g9i!tSfqm_2L=Mt{2}7!`6#`6#>6q z{7)FJM*py0JmZ~rNRnNPnP2P0_rfVmy@pn>Ui>md!{J}*Xf|o=+sHB}^DpW=|*C_2ONN@zn3o0@jOn zW_G=JXO^T$_QQJd&h+cW-^Z4#=o^>>nWBC1K}D1u8`}2k#V^MI`1Rsl1wrZ{*0)=s zGqdZ(J2RQ8$90eO;++Y9w5R~<#XGaquNUvk^3>a`YEPwBq`1xr){A$km2R!@(K0iU z_2Q}N_3Oo(z89m85eu+hJk1z9Nv2L@)%)0i!Oly~#nEBCcphl1Y6F~m?v4;e!FI^e z_2Mhg3pd_}bYz(4bQ614m+yL(T`!*B5pbL7*Nf+1$u}@7E~-H?ceRj+4}}5Wz~&qk z>&4Siv|lftVK#(2G1rS%LpVLWSC+0tD%Xqu9S%zC#jAkUi&uWF7w@c(xn8_m^gg>@ zyepesFP@_mSug%boL%|`z6-~P_2Mr#vpSXJVBep*-^{+LF`NSr6h3cecD;DlPe2Ij=UdhxC*`UYl*MLXFC$Dz}n{9ruJO9J=1_Dt&hEGlyA#dCDh zJvkQO4!fFi>%|{jz=m?`#XCE8tw*0* zFW%+PtryS1p>JRcA-G<=37_E`_;n5}d;{}RYPDWGuaQ>k#nX9dtM%e5Fk~_M2Bu_# z>%~7~Im|aOF9mm!S}^L7lVm14hm%CEW+J{G8Op=!5W@)?$;v2yKIxO%)yHX@%Y^cq z5n;Z8IScJ#mT%x<^iOxpf`vS6aED21tN>xgtrt&Kd)n^Z;0~L_9Ufu#_#x2 zp39=}4Xhb~7J1-_IIGXC7k>$>dWl)V9j1ZXMS1}z8@R*H&QG67yX|`Ml+3H!ZoT-o z@er3L-<0dc^V^J7Q4YZM;@x@7trySC^bI@&2ha85O*k7_FWw!+MDu~o_2L&=ebduq z{d2we`PS9h>5c31r37>4V`yH*~AZ{YE$p1ra$g>PWm z?3CH?4NSYYxBYtY`ywK{UOWwsd1oFYxWncwpbEZ$c~hieRlzqfPYy36*>1gf-U+(# zu2TTtz&yF#I&&=H8^g)KabD7IyBhvaYSu%z4&}o!1dz0 zBNu!FcgF!0elzS)3NsNu0G~a=4Eh!}gb7qKH^`-1V9$ysXdf1Tr8Fv44T$;Bl2xNdXp z{Nuii-!pE(_z5l?Cr(s6KpR}Xa)T9dU2E@p!5_t22K)OD^w8!OKG5;^H;lC{40LtI zx)ug{Vuur2LSGlZvW0;fi=R#yZt*MQEewouhFfQTj5A7FfUP#pdT=5M>^fPe`(`uY z0^#PEvsvf0xI}ObuL7O4g+U$yJkApEE(F0D1pLg!ajXuli>#d`Kptg~pWFcdr7 z@`l+SBc2^+f4P=Cz&88}_dg#Mle@5e1pDu|ALg;%9{9}rWL(JYu2lb1u2fsIPILcp z^TmddA-8g+inEz>rHZ*JSE>kQU8y3Rb)|~Q>0PNJTCP;_-4P*K;;SP#!B(i zKrz%(@LbfLo>bdnc9D0m7-Q{gJdcs?P;-R`IjUltNWYH!o?J&h&uEMhw|w%F*=mjW z=nEh$5WTEn^`eI5^N-lRM*Q|Q;*EHgb=zp9y8n;Yh|eCV^Ah>rw>JD|u`2w>q{+H_ zs&j)%BIbX5srW28+j%}+vwTfc!-DN=!Gp3(=dlCe`1k`Uysg%PH_rBu!L2E*|6QxX zyC=pd=di**wE_7MH@aPXLpTpiLxzXoqrRbjUSkmULohL7{D7%JeyU(0AcQ-uc!=Ls8yhYQyUPZNGs zc(L#b;q}7Xg^vmUD5UEHwrgt|1I_;&aIoTStzy_SWOFei=08+;its$)CZVmWgM5FM z{kG8jz9F8fbJk=2-hk%c4LDly=GP5&oowTAz&={G@i$;!Ap2_JFNDUwK>ACvjduY% ziK)tV`C64YPPm`2QFxK?8sRU5PYNlLXL&jhAr@ka6Dx!>h4Y2S3C|MpXCd={Uq~-7 zwE1#{$QL+7$aW1)@C|#I?D4``!Uo|Q;fca?gqI6%6y7a-O!&O;EnxzW{noy)mvFdn zFX3!qqp*apC(+L?!al+g!o7qGgsX+e3%@43P52ApQ^J4OKk4$M>))}$vxFB5uM^%W zd{p?na1dVJ@%Tmy*9lJ*ULkx#n8z1s$X_P(Yr^j++xsb{iktcN5RMb>Ej&=@{gfU? z8|R8kgb|M+qRkD;_jTcgioZm7h2pRKf9!n;d{ou-|9kUhGBe2xBqT6lbs+3QNWv;b z2wOx!*)3W$gpiORkdP2SN+qbcFQ{nMYJ=8YTbH_^b*s45TE)85rHj?tsuYS_)!P32 zf4}FRJM+S#Xcuk&yiZ=f_nf=mci%Gaeb2cn->E46OHu!$DnFr!%Y>AVX(`B87_5)i zcOvggM0xoDELC}e;$+3Cit;@g>E^0jrC6)jptwTuJBsTR&rm!^@j}H*6t7ggMv)u| zwok5uz{gd7Qt??u@!O1ezP)66-T;Z2ylw&8D7IJZsF+mjsmM<&OfR3sfV=YT4$=6@ zinA2wD3&W$D&n;IO#hVs27i&fz4<&h?)MjoLmabuvsX)Wg!jzQR8Z}tI>(~NYim*c>G5bLq~vO7P)6KN7UyVLYtZL$TNaG;|k(O+(zdSS0?K`2Lc#w>4^=h)_xg$ec$Jb1r z=l1XNz)3Y{&b#l;onHMRg=Moo%3d=b`>c;*z!)$Bi~xf`thGDZmig8*&;99r-gBi3 zLAMkqckES2b9{qngW!LKaI8ReItF8o_2Z8h2v;J#w+vGuaCrW7BnB6Z{BBRU2U9yP z5LI|2Qepl04=F{${Na#ZKR$;g%tmS6fZU0Q@#tS4yfC%`ys+mOeGUEvdvxU2{!nl; z{%6R_qFxcQg$A@?#U3Aj!3$$J{3E2#z?$*R5QG=TwnsNX8@evWIT9s_8@w>;4Ksju z*(|14UKr^j@%}9H>hSSU<701pBgGp+uZsv?7>OR>g)yu59R7uF?tBg6$O}6LA_j}k z;%yoB=%Wd|umy0dECRz>i_ z2B3ivH+)!xM>~Eer10cShB@kJBY9ym5y%U>jIBIEI_8lVb~KYuSDC!9*--oenWf9% zg>^;c8{F_Q5l$B~-p96Mn5DnWmX&ANKGWHFxFTxkNs%}k7M|aYgQdJM7Mw|6dEB)I z&{QCR7j`xv0$$i^U_8ORD{>fSMIG6Vm9`=r9$u%jZ$d12Veg?+$_vvB$_vwmDKE@O zkvRR)h3}3IM-f~zehL~DzDGr~W_^Lvv;d^yX<;O=d?-m&)^1^t_4nNZM zd>j(;!nUxe$GYApV$b+E4)zoA*F@|ar@K1v!u}y*iWg=oO7X%>2U5H+)8n%>1*LI17XvRWSHu)A%oH^tzLJSw);3Rx)Al3$N+v0t6N55^?4wH<$ushi1 z*J6hv5!Z~r9b*b!7|&qx!e~bUUYKbHd0`AOYkT>}+0y=-{6{^G3l}nO%cu?sbl&j7 zI64Wsw_i{-0=%#v z;f_aM*gK2|FU-UjC4NU4yfDMt8j|Qm89pUV{D{P#D1#S9))jeS7qfo&lr)!;(nNqV zd`g=16B7Kv90o7U#7{~b%=}n0-mFPKCBYXWVfd6Z>8B-5W&5#aJO_uou;Z8>yfFFU z30@e_EAqm4DhV%a1q*;rNuDFZ3!`iNFnmgKReRxujboAUDOrRe6JA&!D!>clGS*&! z@WOa1n1gf|8tgkrBC>HfNL*YX6ucM-^4uq&;RN+1rOF=9Es}`&IBnC3kpE36gcrtH zC?~V>!V0X6)?LbOf)~~d%uirm#KKrJz78o8a_t5$i~`Q_#0>Tqyf8C@LBp5=FHC0y zYGlVlK^C8n$6KdO7;DDg!=id}a)B2{fkl0rGI(J|&PZHMc~@T86G*JhHoUMl7{{o-4qn(= zHVA9R7m5PBu-n*T@WR*v;e}ntCSlEZ79qT_-ytRppOQuaUf6e;0zM^;0=%#hOaY&g zMgd;fAymMpq)~tuR?l{U7iMZ9FYFi;!dA(cf)_@ajS?BWFv_E?Y`nd`Cq(lVS+sYO(@6{UDuLlAE9|)^dwzV@lP56Uf3j73tkvY056Pd zz>^o2FCuth^7=9oY~~O>fXFm2Y(7dkfU6pIqg-B2$qO5XROE#r zT@=g2pNiPF%b*Jd&40d5>hAJ~l=UddA2i(D9(3mI7U$5L*yeA-2co0}+=vh(b)`U~#-sgNEyvqfQ7JG!322 zhR)L%(9jsH#*Q)xHQ2#cTkG@CIAbYv98{K7T$mbPveMWhGrY42-^cDcM-nz+_nZ}L zTNp5nJ`y3>y5K)9FW5Lc%*G`C%`eNt&3+DBa(P|d;>ILit|Y6L%&)>a*$d{5NR|{8 zj~KXY$iO8Pi|QKYF0TD*JoxQ_!ZU z&6Y!)mf_9;Q?0ZWPpvJOZE+?pFg!H|dm&G2ZCY6x;t3nzNDa9#$_ejos;`^L1xyp@&9 z>z2&N7||Ie*ndJ3`mblnsmHp;sw()_#Ow7Y`U*5FRi{^^M(lB|*R!w2dh=vSRW&p$ zt#fnjy3<9!AaLx{Bok!NxkcrlMg16cr7XH3#FWy<&LPz$FJ(*Cz)qT(GjDp?Y9Ra^Td# z;I}QU8;EuDYAcazacxCo?b3zxQ`xjs2ycGk+ZQ9k$q8aSIR3ZM-^60V&wuOddjjMG z;J7yVCugh=of16NJ1ua!`|Zr1J#IYjeNFxCW&7Iif4HUk>&%DaSf}`KzH6}Z;jHFg z&W9^Qz2w8pQanm=p(1~IFuqCgB*oJdH!5DKc&*~yiVrA?TLF|K{14!E)qkvb0Dd>I zo1v zjp^Gdc2_J?T&&19t4w!^B8?m=-=+AdBA42so@TbhZg`PJFM(@j%6QgNrOmpje~0Oi`|bi08W&raMvbOvQ5*`3{Tmmn!~1@mj@O6mM6&Pw}UUk1IZ@ z_?F^!#rG9IQv6iW<8==8#uT#^Esw6N%ECWJy8bHj%`x+hSCs26Mc)8*giZ?0VqIj3$PZS?kd|dHq#b*_Nt7!e#y{+;N#SaueR^;0)wkxO@ zS0wR*dR!*{gM7c#?R!7p597`ahe@_R_>W5(p3TfQMA3pxHvkHTdEB@$9iN%(#_IsL z@z`x1%CBOlFHXDJxG_-RGUb$N#ATh)4$O=8kOA^qlC~UJhi`o7%ddeJ`XWQy<0j z%gW-R`^5Jv8BsJM$?fy`ev=BN!d860^0&{Am2Gw3iFiA2cixF)bSb+PyuMB2!2Syj zE*tQGTi_J5-x+QT?q5N{k7MtAIyiV>@}*7hL_)DLr{IIP0t?;2mreY`n}LNNJu~&~ zCu3YCdftSJ39+rWeC!luHM=9j2nC8JH&fMVngoQnQ!kUpmWf&2F! zE(D;ntps>ma1gxV`QwoQJit-N1V3fTCX!*gAA@W2rbcdraewo zyUz3^#O}V%bSau**O@*ZC8pMy=GjMP{ch__w}H~P&NRKn`qr8DNXpT5ragW#-({U? z3}Obfvd*-3F+z5o=~qx+YMp7`@*{g&XZmS0)3?s_5)o7DOrOB4C7su!xIlq$0waU7 zrB%Zo^PG$*O_-r)HE$W&gUK9I@9m6sJ*T;y$wgtx6br8Df-r#?udi#UuSwH z<|1AAR^A3D(9Ff6gsj)=TW6X^ zgc095(=;0NuQSabNfF;V(=@L1uQUBRPI>=2)2A^%IDsSz1q!AlxKylvo#{HxW^e-Q zWL#$@9%8(2ooSv|t=5??WP$#5rrT5DUuXJ37U^GSnl$9Ec%5mUhyHb@Df`!%=5M~# zI@8yq1L<|9BV=UZo*yy3mBGhK>u)9XyHrCIsV*pMdZxiGMRf6+SAG|2O>GkrbB?8~h)&8tpoo#}fxR^S94$*1+qCe%U(u-weS z3EY5M{#ENt_hJvy>r6MZ;?z3R-~@I+Jf6q;qRMVJqltzSm|AE0a-?6I+=M}QlGq(L zc?L5$U4I3YZ=LA~wP(1w|T-aA-9=@VsqQzQMSiq zQ8mxLpLVE6&QoSM{ewU7{>!; z)$6~xQ3@!WV>{rFOz=D$Jy7YH%rBVCCjE<=en0b)%WMA^GcUQQb&pm)`u5Jf{BlcT z@3xLMCTF25t60OIVV_u17Ci6YdiCoATd#gSz@OpJTrMdi8)i1HKi`pWy(>&Oo488# z#Eq&a@(RQBzD<~*E-wo55C6GI0&}&PHV4Adj5iBWFF+7n&_D|Vi;WO$VPLrtGFn*e z3D}hw+AP7DgtM^2@nEop0k#Of1_^wbj?{#!uuJ(2{KyEw76$G#LPiVFZl<}P(fsM@ z=1*rYO!Jrdn-3;wy7|le&7aO*oQNHSRl)}BAgl&k7%@FXM%+J*oC~xz#{BOLg2_LdDRXg$*ZfNHdA0O;WX@6y_{giu*q%N z2!Xrn%q6gg+6o3YVMi5&E3r$}4BUVndIASkt7hQ zR&)aPX6$ye@nul35zW}yExXxx=H<>f+c`GWZj7^KupFj21-tDGf~n2lzH4w^d?~-2 zt(ms_y>$MkymYpH$t|2_zV=pcngNgj7F1PNG%a54cfpzV(iu#7=|m`%1mTpIPCO4= zFP%_pxfz%|u$T^^e9RZiX^v*NTpN7Vs8BSr2IS(wSYo`3w~?!lx6jMX16R3ohSw2N zhrHDC;*ZF(<6XQ9Osb5+jMfP!+eOPC=c485WylK)Nnch5v>`i3NvZbnqJ7$QQc|G{ z=*$zm=y^;r*5AnPts2?g*1bz3yJvXaU96fO^&VW4OmZFd3|N2{w(eh{Symm*CSiLe zo9@M1`yLhcwy%|YZTsLfVY?v1O$O-dH|4SK-@cqWR!skwFQA@c3R@m%_0mQM?9sa8 zYQZQUSG!QWW0r#ux^h7UoToNaHDV4sX+|ldYU-LAoMpvB#oL}?o+{~hUIlDD;t$2 z%q8o~(Zy9IvXp(fDfEydW+%rN4^NILEGaA&Q;Xt~;=#$jSQD+PqOq!9@>>flD+i7k zI3InitVuRht*C9p3gpR>VZ*tsFleFw9gNcYp%`Qg28IL!qeFr*0=HZRA8}a5v$1wz zImxRWNf}6+$BU1G;qIqaMPJ!ayS&Oj=Nd8X zF|OcclLCy{i>2h}W3l+fb@MA0m;28!nb%bnIM?hcVcdzr5p)HXJGbYM@h-|KzY^!X zF%`faYn7Z+i-!%VFsIsH*F@h}!alzGR_?(D0p*S-NquQ;-TX#pCC+hN4)EW&?erPD z)K6$cGQ(wOJ9z;}T^e-erLRZ}tCnMYs>o<}$}1L-4c{o2jD?Gva80u#vZAVi=OSZG z1lZTh>y9g5T*1ng%;(u}C#{Sd@>VacXjs_j@E}wzNSd1ErtCDW`QC6^CGI3E<^LK;-%Hl{qYDPW3hBe#bWftDR1I%IERcM zKQh^um#|r4I96TPkQ@u+v59ItmYmj5S6S8ASl7^)95Jw!9a+CGd&R?Rc|54>jnmBs z;Ii~O>P@ND(~oH5Jp9O`kL~wy+J?`0sm*J}lHm^qvO?0^?rW^)Ie1xwA6n*@_%57o zIZaz}x^Ye76J{V{jvG0cZ@o+`qHX{E#m8%pR6;~^+ zQxxtZ((`vV>)oVylj1#!4=6sPXgS@ltNa&5JT*%>^nt?ihAWmS9;rBAah2kUisvYP zPjR#2V~Q^*X5!JD{~GCL zJpWl=r*w?O<1$fkwqms+c@2y|P4N=NQT##({h^AoP!;5bDz8-Bs3@yVA)adwG2cUq z|E#amB{+9k-v8Pf>6hV675gQ=OM&-O#&6_@6s-?aSsNYkuTYPVa=%lQwb7yfi^}gQ z%G&7Adw4<3^kGF=8y)(D%AFNuO?1@Tk23ayRDZCdtc{NFWR>mO=tomVzH%b=I*o5s zT%*{mxSojp9F@;klr_^)&XpQ}o9gdW{E6yiEp_zgan(OdL_TsxS?(WH|EA(QiXSNc zjfmaD4P3@Wu`Lnf(oOL|#VLy4Qp9Cf>chJWL8t|@74sGM#)&V|_#ukND$ZA|Ra~OD zTyd4+I>q&h=O~`9_&r6wZ{@gLqj-bjt%~GiGX8$WhZKLN_zT776kk;Qz2X~+I~3nl zwA}aZyl6 zKde)pqKMnHq_@`}h!T%zLEJV4cfC&KsXnRLQ?ak&0L5LeSEZ_-pg2i!isCfIS&DNM z=PK4HE>^5p-1R!QM)l2#Co67H+^A^JE9nn@R@m#WQ`mU?lI0cif%rWvSYt!5dtUAo z%FBns`HhWEAr*zKexB~PA;I`^!(~mjKKReMglR0>5Jd|%9p??hoR{2~ZnK2UKh8^T zdxP3LklPhF;WpcY4ViUuze&-iJL-Uavmx1vbfb{hZmgHv9oYTt zn}_z<@#EV9+rCE;M)&Fgvc-~S4yu?M3%1cWJ)BacOG4QJdcGTAc`ToG`i9Gy*B$Ag zvm3I=#ytLX^=RJ<8b`3{(pQ<`G$BbA4;@xgG_S5^gQ{;bGu~? z82HlEw}07Y>f2An+-WW&d9(d2sCmTZ8P$(i-=B)#r?&SUxUvLL)k2alVG{oZjOKl7?u zmDrq-R89{e=A>1L^T5Y^c9*^dv7jvGISs3?fMS{`)BggzyL$Z+L!t8AjMs3X@Z3l> zArLBMTp%oqgZS)9ykKZ5Vgk#VYHCMLATJoES57Y?KB>J3j65(gf+4;YMI5JTAfKwd zcKsM0jl^nK5@<_(QQiU;6A5-@$-K37#Zffme~<+La7P?Cy3YeBiNm zCABCqWmm%H?9r~IADZH`E1}7T&#ol!8VkJ9W7Ytlu6D62!NAcLL+nZdmm_5DN4DF#B%3`L zrKTdWcplr5wktV_;%JS{i~j>%^x2j0H-OKsWIK!6t6j;Q4^u7tMte!G%m zDSwt-$p|zpZC4`Wowh6a4O^DBD|wUc{?c|O=dr2Qu7uCaKD&|*Y^L9?gtIRDbX5P( z+m$@Ts`k~cWIMaKC36XCrmyLg8ig_H8$8W+Lc_xqSAIH{V6_| zLq>m~!1$Vu{3@p!6$A<<#Q(u&r0q&*pY5|Nsbp;0t|W)Up0+DFnLSF|l^n^6zLZ_b z4wU;Db|sY@44+-ei>%jYS8^dM_Su!Z$WHj|O75ZTvnx56>3w!3zht+3b|rIIpU!(oahq%ldtG zCG-I7w=3a!)yl49FbnkCm2{%QZ&yM>dMmqM14@2wVUf#)M;5C#ZHUd6@OV*Ys@E6DX)pbVW-e@HK7ZRS7y1|7^RG zwJgDJS8@T1@Y|L2WE=fHG zO|QcN2*B6$VeD!*L`@(0$t;t$%`mB<=*@IKvw zT%jOMO{`tXDwd;mB~KvC&AkwhvONw%ZEkTk?Miqa@aetB3^d9u$)@eYAXJ@$y~jtW zTi&X*_mp{TAV0U|0a=9Zw>rfBp2~ zPGEQ-i^74oqbY$Afh-zt3=s2;6|;*Yuk8YCvH!4BIDSA0{SY=l4y17{h*6U&H;As`3gG6~KiaEI~4nidAGF?zyH z5}ZaLZC}b~;6WnhoSyFFGJhvw&XMlq zGJhwhvy+>!!@7aM-E*4Ov@pQlK~FH9oSyC^%1?I^9g3gMkyVBME_ntQH-1ylK(FUY;+h zW)e8$+DZQR8a?4b>{=s(k78$yL>`S+HYD&1;s(l~ zJq)`w*QiFAyOr5EPH-zDC|fA(1Z-MZ6EO*QpV>w@7I1e-v8i>6fXg(j{Rr&Vl*8t+ zGK<~hi$_ql%vk7i%I|`7Jno!Cc6-7GfMwWO`_b6>3E9?c`wW$AwuSyQOlw=F$prl6 zH)FPX;#?`y_t|X>2TK(Pif@{~Dzl9w%{G!S+xRmr zCB!1)Ib)D9sFg*;AZrnEDy=bS`QW|aReL=O4>Q&d>(!b=Gq*P7NZEWy=CmmXW@y?z zV_(c6)aoN;%29}xdlj^vFcv4D+jQeXpB5RhQM-HD-UltVxj^RWU%1VWcl$U=gw{f{djKW;tDv1E-Ic2?(K1d=Z-&o=AkpohZ>waVdk{C zpx`d5s$AYU7i8VESNAVztAW?=Bg8}l1a&dlux`RX-&o_n!$_lizgY%I>i@j zS=v-@N&Dp~&c0eg+1YITo6iTi{kWO36h@8uvlq*b)TIC7RvBDOA!U#OOM!o<1;%GS z9}MzcTyUHEGS(W>k5(26|KkQ2%Z77){Hv@mzPRCqu^H2w158Q2MphVx>##RF3_j3K z@cY(3#|=z1CK!)Dg}ASy9R}zqzAgRmPvzIqw|+aci$7vH*1OnY@Hw=V83vs%W?=s! zb{PGcK5ka#BaTs-KY%D7t~f(+o??|^qauIaGW|Nma}_r#Zc@BS@gBto6rWMtZ--&V zksrl4p8XU@C@xeKz9r)M+L`GtQQWG?C1|Oq&m>|DQ=QmZvA?459-$ZBBk*L^(*q>a z->UeaB7Im=|69fFihoz+5}}Nrs5o1(O0h|Cz2b$6S1aD3_=w{3if<@>pcukLXFcr| zdnpc8oT$jRm`uknXT<$>7-k%9;wLDK$K8s*QY^?cdh1(%yvo+M{#2FcE7mA3Ra~z4 zZN)Pb|JUp=j>88C+BaBxj8!UIdyI9Iv7e!OYmadeWsJMnUjW6v0?3WLW1L2NOz{ZC zxr*}?7bt;sirpae{AkI1)rw*#2)RjR zYtPWE@&?6?idQRI`-NTY79P;}Es9SlKBf38MQgwCn#$IG;T@GfP!u~vw9n=J3K&t0 zDJB#iJ=q>3*gt_iM<{smu?hGyi188Hz_L;&v(JX4~^n5z&$_q8L-O>GD+G^?KD;^#c@(6o)8| zP#mRLsyIP$n&K?QK{{`wK75b1_5Cw;3B#TLdb0$lGsXv(4*4Ab5c>e4-7svjb;p0E z!!(nP$HBibj$0q>Jl3C=j>mP^dU+498|MwTaoBCyqJZ!Z+!O6)<3>Y)+pANm5f3ME zufcq64;di$Nw$mkKbr?Z=O37mr`t~Y;^z6n2s)?WhhUX$lrL^B!v1>K^xm^wLY*%U zg3dND5t0n(X4`ZeWPf?F0}bz;{lKG9svjpJZ1W)KWMN{@V?Z|>cLHR8d0kN62IyEG zx}GX;Bf>Thg3fU$?__%reR0g|FYhLl$8lwOIIU9UZ9HO`x-8X*xZOlW+_CA6g-Kz)4HVx$su>#Q6Mf6P% z=VYWyLfHZO&$3InDhWmt(%8+Gx2s*k!)V|0HWARKOTCw?9$d07Yg-&NV(74>Y@ctJ z@L&(Au$5iH&fC8m>AKZr<8RjBOq3d(0cQQGfNmkEddJo*r&<~=$(C9dC!=bCgOP~%E zIPp4)H-vsJV$ku=_;oPBH5KJz5(+C~Et6ILjNUVld8yxx(L2F%qAN z>p^&wim`Z@O*>e{>^Ln}!=qKqi@(XD#;BMdr-S8isfu0VomkXZ6_ZXou`+POhehbe zB7QyVot()qM;&c+!c(FYJ$N9GuVm3jNXH-t;)gT&bd^sIIGLPuG_;j2AKt?S4M8Zvx`M`K4^RCEYm=*Ez9bRcGLP?x;*`)Z^gzt#Ff==a>*E``m+i8ZJ z@&+e-mz@bYqB9UYD$Km?A{96EfDifwYr=T|%7pX3aanzQ5AvF3X< zZ+@JnD&Z|MO630kh2kS!SL2Wb3X<{HS=3`)uNJXqyblNaiTD#D_KgqWf%|#%4G{O zYu+jG6Dhuud5!dUTD%u~^xJlSL*oJkv*ORQ&9B9Zk%((bw4mSNKeXW)94MF@=Wmqo z8#>t*fGf^p&8+R^A7@MZG5kk8j!OvFyS9w#Kyq;3V0d02!qG{Lg&3Y6&_+24l8D3L z{vU$}^gux{!38@Z=NUPY*lOat89A1CknIBZ-^{h_L?`wF-2aPk2MiSCC20H{2KV2@ z7bTvc4DP?Y%qbX>;FJx6`)}e$B*>}_Hv}^8m;9p=XR>~9|IMYOH1PrJ2lwBkpOD~! zlwolHP5h)p5%Yul|FGnrlIX?!;QpKR(-NzhAKZTq4u&~#B-3L}iDi<0PJ-uE_y>Vp zw#zGcJdmhm0pR}g9PtXC3?!yd0q#Hj;CltX4kd=NNUSN5k0J94UJWHWQ33A%Ym(y6 zA&fsy1#^&E&|u#|5|NEVB66)m!Db}Lb4iQh1ob7Q${x=fB@y#++NKjB|5hmE>d#py zCo?V|JTJ4*KD}aw*Rz}8{?`EW-$mnM;Q}{8Pc8|$c7yvbZe76mp2+@UO$jrC!Ngi- z1@~WP1Zrf*LqQgw&*z&q;W2LHN){F6Fe$kIyqmG8`IN!^H^(uUIDxG^Igri7fr3b)7djsX_g|bc zU`>fvc}&3lH@%pYxQ@L5_rF@oo0j+n)1MaTR4GlJlOW4Je0rdRIpJy&rHlvn-^lfe zk&FlT-^i;HG}Q@XO^FOS=2%mrfeku4kljHPr@09d$;06OvjtwkCO1LrHD!~0W3UL4F>>v#8zp3R(*U6lS zLf9%9(~d@FqeKoHndTKDC!CHu!iiw1-J z(E+R}(TFm;U5ZGvrUYzEGWhcNfXAU)o8)^rC%Fax+~g(rk8(dk1QrY_=!R6T8_q_D zqL;Wi*$~?vg@2)-`CpB2clQ`XyVYhHiFqi1o7*EF6U1HEei@RKLNNe)j}Ooux2FAZ z&^-nDVe0NjU2bhVz6DL7CAruOZiV0;7o(1E4@aq956bImIWq)=?>_NbY0?@K@!Nq zgeY{!#H@`%pIDCD&MnRO?l=_CV;|Q#;L(a^nid9zVFx>wFwW@fTNs!m`e}q|qOT9OFmR+1 zA}tK?Ed|))u@<0iySHX~y141-;^3k`UEDH%am)P0nNrIDpcND5Vc!Gc+U41TohUm* z`BAR4Wt?w1IN#*p6k!KXoKS)t{PDFd46v!t6Ihutn;D!UF*68!*CWhk24)#Ofg_^K zW;-}!HbX007yJ)Mh>bDZJR8`9EDtA6cVzj3+}!wW=8GGhkMx^?sS`^1RDTO5c3y5G z53b7L)jSmKOM2^ZX+PkDJ}+2Il53NjEF{gfZT0RnR~A@cn6L~gsn(}WD-9zSPSXQi zAEVsoA{UNxc=IZV@ z&FT|}x;}rpoJ^K+2tVN~YC+$%E|3@0HNok%(C@^ha9wpZU5tZs+1g!rYre1b8w{kg z^0cdBvnx%#gZiz;_?|G`d+Ue&MABPWhCn<0qHT zvM!zXk=SU?arN?Sy&Ma}+8o*A>CjrbVUGe`wbK>6I@~Td&4i+HK`jnqEqadwgppN( zb2U!=#kF+ryt0y>%=K(YaUzXFXYqz@38ZE;%;2IL<1AkNNsHTR>wDhMNLAPLsxoI~ z%CCHy1`dDoU~-DndCY(c9*ng6aWtyFs?w6i7s3s> z-|e4X0!|Dx$WJAm+y9TJ7HzL zE^fC#4?gL(+WZPQfBMuP>G7f1w|V*qYE>Q|LVTNtM-Dz9r?>RODs^8+ZYq9|NiXLC zTXR#*HQG;3h2{%$QwN}2a;12vhpR&kReSHonwUnq*tPRPP(0rHy_JL$zqgbmL<7-mn>!{dAak%0kiVGAQ6i-wSTSivOn=;Pnmp`6iawS&?^I%5q%= zT27~2Pa*TOHRCH3YZMnN@(ncOS1L9uo~(GL;<<{KDt=$_YDIo#W;wSh3QYm>eJcM{ z5g!I59Y5zWJx=S-Rku9PJUt^pMx1xHRtOQ+GMuXK%BGAl?Qmd|?Ega$NIXwUNHKV-WV& z```iaS&MY6m-Vq9#Cq($?9Q0Bj+2DWZZ>W)6#nvV>Aq*~+DS-f^RSF^l;?kzwQ*~A zDepmFdAugt_VIdT^C0Ndp}ehl7O|U+I}Zwf`?jJy_K*GLGrleF3WS-b2s^hi?Xa#Z zPg30&$NeTno9=pCn0XDgn@x8&6b#!f*|9a(jP-K61G~R{FLqClADWPA-=hfQk%)&y zwpqKBXX_&RhQT=v>5@=(fSx=w*2{5cohUE0U5ELXOiAgsGmk&ro89;BQ+Gv0L;147 z#rx({w|IC_QIgx|bJw2iCk;z+*E-^E==K}<)<;v%D{Fk|w6c@SobFDt{Oya|1k2)O z1GmP&P+M6x^R3|gVePK!IQ8uwJtl7ZW7DIbWVm_T0+|!Hz4q;gJ_)!pKZ*>P307OX zcAd5bf>Yn_-Fx!3*P8OSWgx{LC51bNd1jRzQ%26)3(v&1wds-%##`sDzy8Q6>fG)R z`4hLj-sFzl@`>l>Ko?Bw`coH%E+RTgOdEOU)8Qk_oPtk3{J&2N$}-B%DDyrEy?50o z@TI$Lyc_u>{H}>B>a=K^>pqxO`u5n;pM8Y8$(tXY>lEb96MR7IM`TEX?#DQ`u^u?8 zr}_?_4T2gs0r4QpkwXC5+$h9=Y!}4D2CwWiTxdYH6Em(rI02=16cZetUrh*xu0*-s zMNBodqV@ZFcb;Jh{X z2Oi!NP=P#w{~5<4v+MDTKX`bo+k2Fe4H6F1dn9>y@@rKYRB7%pzTErvk@&1kB1km9t_mk2xYFrKU#T6-%$5plt>;PSCoj~#R3kBngX0Se|dt3 zXT)Hf4^-gc88H&)?=|r7j2Mg4A24`$M$C>2`D3(-dGXhocZ`bp@kd#5sfzg0%DiJ$ z1P>2aVkbf#-k;g3zq8YmGa2TnFQMr3!As|@;Nh`j9(j1*ro2ZVygZ!X;hl-vgoif? zJuu^)_QCr+TUMT7`^<+>@bHd6N>EhdY#4ZW94zJG{T;!~V-d|=2K4|8HQA@&;r$p* zB@gd>i1ADD4?H}E*^R+$=1N-;@=Qe8*?h<(508#Vm4~Mpl!vDcQy!j?BJmk)*WJ-6 z0P^sjXI1y8nBw6Xf4152Lz(zqoyGa_XDOzA@HSFR`{1ReCU|(yqqTv8o^f)Yz{8`9 z(?CJr_%~TmYahJe;hBn3JUr8Z6c5j|c~tyP7M1qF%b%^_;nDl4^}!1so+)ZVyeAL( z%i88C@r^u6uVlU;{hb!SlZ{OK;2pulX&=0c*rT)$-bPmRhE6u}@Yo>n?3#A(T8Hx6 zQ;*{^6s5IgR0ncK3=i)Hgc6l37d$-EAt%8X6y)I<539ih&wcXnj2uZ^&5C_Kc!ie- z9-hgcow$mf^7-IBn(4vAGx0@<_t`C<4_?kV^6*Ujh{P+D!Nc2uJ9D65RAM{p_xa!* z$@0O&GwCNJUd7ZU56@g`CM7m8zt0D6ChG$a&!nH0Xr}D*!5g9s9^MsF-<$-`EAsGo zS_u#DKo;ot!P|}szYpGLSOj=@bVcithbMHOJ^A2eBlhHjmwFr|`jP!SAH16M6%4C6 z=zI3TI}rtP7Rt#C9v)@!!OP1Bn#)T$d3YD2Gx_(R1H!{Q6*&@e?e_WLrDu5Z@XQDX z6LeWk9-ht!wAkl^m+$q2hxbbsbrKIgcz6_Wxk%i=tl;4pIV15S77ZTWOf*S&cnrLj zZnoj!k*<|EoJE0$$M&gU$5&;N=`5 z56{#>9v%-hTP0HgJUq&5l*r)WQ9jbjmWQ_vio}5|%jbjlha9s#`rzeJ0S}MB6G@8h z>KGp0qfm6_Rfjx09^B6KMNS?bYc=)1U^9V-w-HJA%?B_0i0K!@@5)f{Zzv*@Q@jU6 zo%UUYa-R0VyM+~}eDH#YmyI6cdF&um+3i6bpO8BmMUscN8l@cYD$=h_ZpNTHN$ifB zT+a+n*EgUd5AO)10uOH>vPR)?_X4CbK6oEQy68qX_eN-1`{139GTnnS5RbRJ{D;l$ zaXGc4bNKpf1Qbc^J@~HI9n-D_;TN&<6;hAOkk2j6p-*1ET6eJ*OhfJNI7wFqxd?mD z#-=5XJH9QQ-M$O?*GxxVy*oj4G*P_`d%@YF>&A2>em_fH7VDiT=|YI6xoJ;)#dOQ0 zYrH|s#*Q>OZm%}EaBc*jFO-pBs=3lAm+OPhgln&NM;~3C<-9!|s7t)WX0xBdijp z-vT47XA!)sgVIltD0Fc^b7i4R_07ePfNY>;FPt_;LgMo-{SC=bw%ik}C_ z^Ba^+l){D@L=YRBk?DM&?~Y`n+#h>}GwXuj>o5U}=-_-1?1#T@A0pW*r`xV6ammHNm~Br(V!AZ#g5dNEf(*0L49Ccy*+fnX z6m82!*yS0;VTD&%LYV|-5T;>2pD%M1+P zV4?^&nW!M67{1d);lFHM@ZU5lsG9Wc%PM#}+3j3RAN+Eie%(_s~PM8?q^;o0vHf#Hvo#Fyj-YqL+uWQFbGi@Zb^RxyNfnb zgoGu9p?3WwmPx(EZm6A?N6P3Rh^}x)QFqj<5!Pv!*3MN?9#W1*%Dkkv5+(J4Sk#^c zEoV$G)|hJ9J|qdX>&6mTHLy73bqEbb(90-pAIiz_R=c76!$Ub;L;1y_?CMb0Z-oYq z3dKf++(Ag~{bX%nsEuSCM2_vl4sOFFw^~w|GDBOFIa~4f44KJCO-vE`gtuqer^bOF zICjt)mXx8tk-YhJbJgmnvKm(3f7C~-Wk044f)aU^?pi;is!>RSX__&{bl4DbSVZHN@#%c;|+4 zoMyS2#Azm{pGBLZFyiN7x>sr1Xlq*W?ssN!nVP;qkkF`-nWgjwD;EQqxUGoA%3m&5 z_ObGc(_CO-Sf@tk-|QFGGPvQCeAUVYID{#dYl@bR4|saAA(rG{Xir+uzPgGg_{XwQ3In!@ed`$5L#Z3HOWW4y_1B$;r;84|1P@JhaUs3$;Azib| z=PI@+{!meTnjqbiD*sxMFDzMa7Jh;fJ1O>49HF@1Kdc#_5GFduX;&`pP}NUVoUORu zKdc!qdK}=meO>*-K8cslY~QblXzMGA2p<1DE3i2 zP_c-Jbl*^UjN$~Ze4VhnTDu7wM&H~#hlIcR3{2yX>MY*m+K1^kPZ)E&YiVGAiH&{NY zBEC`es})aBJXO(hgD+C~QpGD2EjRc_DqC*w-6~sd@Z&05ZZJPsv3-A4%;5DLvfNLA z9aQe5DEAfU`>Q-main6I;$ezMDjuy^t++^Wh2m<(Qxwloyh!m<#a;cq@6LowAA<1TvD?l5I^Z)cZUIiIMl>H_K38>s%rxBjEvO7T%d;Cl zLO0|3Z8sY?4hnyH8&Dqkmn@I-$d<=zwatT|a|=-h|$ zn9goC?nEg3kyX4`ia!py_@ zz-=B9+{*)@8{@d&tZ379>AGjW_r019AlpWy>gz9m8QS*!3}JMy z9w6J3D35d1ZnnQfTyE1_H_TZm6VTu%os`FMXPv&`a!N7(#z1E`TORZH)9pn2Ub2aR zHeKp!R6KOw_}+s{h7U_}`+UCl`-7yy-T2-+$95Vmx!R#mBJYL~J{e4Ha<@lxdN8-B`Mx)It^+Guu)b_r+48cd z{`5;sT5~*t?m`4&9QcQ^C#6s6f8b_ciNORn`(unZxY>N_@`540BLzkKD9lArj(>wo zL~u4HMR0h2ITC=b{RSkgy~(xIgBL*+JUm|>*n**tnQj|%Ozn6U69>Z=P})qr(zW?a z5UlOkj~P!x{h?&;OomB?3k}F!!tg}ui}IQorZd&h2qE|cN%abi%4>lh+@Xh9>Qnfa z(W4{ZM1+Ez92rj`ksG`atqTum!-fStsKX5s4hyF?#pMoP;~kF3=-n8B@O80n4Cf+$ z`1)Mxoy;ltcML*8Ya*9B{DUZ&NO79WhOZ8fMm*`bv}O(85F&32oH!?VJen20(PP%2 zaJ6sl%!f&Gx#i)^jVwczZ5a-7m6K=(8L(^?kRKfs;pf{p-G@hubLCU6;c`byw8mh( z9Ls@LosB45?&#pGekjjyx%mK?c`N=M1eNp+7sqB4(K9+c zLhtzT80$VLYWqj4wdhC{gYhFMenZ7bd*vN|Yj*fAO`9K0-PM zIS}7UdAiEyXc zo*;Ec;%r!Sem4%5a=BS><~jJsU26yhH$niHn;!5Y(Wb~l5aW655_OI;~NE+Ta2B-k)@3Xsn66HKp;BwPjA-UWKvpjIQ&84I?aWQ3ZxlMZb zRAqi}xlR0}L?`A4m%FFrpOPRGISMYfNk1(?k*gucF{` z^HdTp_a&?VTyCBt;#0Mm3UIlHp$74(+M8VhmwOeCx^TJqLnjI@_c%!*K2>=tn1l2w zQu_{)h-@4V(oJYnDEKN8TOmk*wo z$5|N{_-9d86kP7d(V6_Vs4*6WPu07SA|cmqaJebq98cWD-hj((MlhIofc*!TTW17n zWXD567N5TX<+g#t+6Z5QCtl>pfXhvRMfK$1g3E2>jD*K{aJj3|I^l9N&<=^U*&Vk= zn*(7|eiK(RsgKKDNEuvia~y*Sz95K#%gw~(a&y3=;Bxaefpb3bHd_rYx9P>C#BZ73 z$K|d>%~5c?kIe!-U>xx9b%&3 za#P^p3t()b;Bx;|WcXC&Rh@zqrCe^FNGf;Q8HG>Pze3TOSDh%h+&s9Q593IH%gtI% z{TVn@BonyYZy_nT+*H9Y4F1dP#sq7Ja45(Vy^G6}&z=jTMBg9(GdTxmARuLdb4{Ll z6kKjz`QTGEpCY*2^F#!fyBZ2SkDY@myYW?a$eqY0fy;dZN;!ZW?X}4g45^dkFA_IN zLkE;w3sok#+$SIvxZHE7J;N}!+ujXbcr|hc!0x^axx(!^2SMz98bT<@_)w5e4Z6Ee zVgTKdyaPDSb^M3T?TP2$9`Bo>;>miH?HlA z(9r?=JnTa19xr{|32_IL)u0_9dNV71(tFr@vk%><=f5Nab7RpM);k%Fh(1Ws3wvK1 z*>3{0W1$&?9l7T~WTqhh^~CNTlQ$i?`>$v2Rrp6&*t4+rInF2awaE|s3AEaZ0nE;S zB@9%=&b6&L4%zvdtgnrfR;-8SB<$J>W(xA(FzoL9yx%c5TfrA(7h{*!+>XF)6xbRo z^tIWvH3QhIX)Ff2W40XroO#cdV}*fCu4Ood(=pIe2|SPI0c93G~gvq~X&}zaeQQ3=xablmn^4^(j@%>m>JhJ8O32DG3if}n9(j!)!kNWsj|~;#hG482 zcm+o|pZe71@*HsSLc(lT-vI%b5fJ1$>CCkkLy)nP(DJN>H{M_i1H6<#SR>AS%OI%N z;3*QEOE_ARtO>L*z)P~{z?Ol51|wt$d;3ZVsF%Rzx@xmt}K zz>zo%d&p^`9Rq_$Vn_XiIoL61u8c^v(Gxf(YRAAJhlh3yn}DXB$08&fF2#t#6<0R4 zBH$FY5JzH%d+AbuIUKVHrpL2vkC_-+*<5jT!I-48-1%_yhyBcd7z?aI>#eZ>YzCZE zo)D^FHD-iZ46F8ADe&Gn47)WGC`FhJvGOd0=lf)a>wPlA?7vNKTkfv|(Pndb^I~ck z(x^&CCkdg%s0n5~QYqX38=b_S;k+C3z23)QQp?>}V9=$4{qiZ@zyK&%`0iy;tFE%0EzxA^QgkqHN|Q=0I?0QHafmpv~henx}!8K0(ROf1G1> zvjy2wY!Nn|=ue-6VmxOOiu@ek*}L;Faa|mQzeAT+E^b;-r4kh5>l&(3+Wl4(|0yd9 z$Nv>T>?WvCPuMuVl}j3H8_O3~R;m|m_|2{W**oP;8xw)FN4)Yz0z9RWZ)!rRB+w#- zak!muQd0wi zMN-21ri6?ntSxNX^;*b#tqO^H&C6VGS)rHB`UmEEc`VVJOJfJG@1D#oilr%!w<-l~ zym^^qY;?W2SZlBpv`&pLfd7_!te}AA88GQJ<{ACOJY(SDp?(L31{R2IMluvjhTQH* z>fPAdHsd+`JZ|eH!09zJF4lnHuH&#Y@|sH_?^bN5R?nu?7tPw;tcIpX_h z+flm|&;Nek()m)U7THKS@UhR(9$p+e{0SIZBK zLh&%>uWFFSO~#PkvRj~IS%2!w=B59j6R{i>4k z+6puRzbTuloc~{(Ig114T|M*vrz}EzcLfZ5+JX94U>%a0&i@)ak@B=P6Hc&y#_D5w z@la>qOg~aHTI`|3bA9TfXS|$?sYBW=x4Q6#+x3+xm;GPJ;A3$^)xz?o{e~ab<$t-~ zHM%;J$8BSeKJ|@dAZ{^u@Tpvd3lBWzbESofr3=&#zIDNmYpn66kJAFygK(3-q+&4+ zrGxblVJ!0%8Ggj@IOVtd;KRS&_z*w7P5#Ll>qDmmPxVgQZ|}h$GHvbf2>v_mJvjcY z?LFiX=nL6<;IiYaMmea5*j}+C5kGo+5s_$s>IWlANOykGI>if<}@sF=Z@xTsh7xWGeH79K9-DwUTjo}_rb z;uVUwC_bS0wBm0R#kU^Hqc=O&7sD$bqVQ^g-%$B5#iJB!6uEpX(_f|dW5u5-l0?S% zwu)TjkMbzR$%;oS^1~A2S1I1ENH0Xx|6XyY;-`vj@MDkhT@?o?Rx36sl2yQT7b@~o z5#>7+A5nZ>@eRcf6hoNsOwW&H#9oR+6(=h4MJ(g_-H+I$xL)xh#cLHeEB;JzF+am1 z-|>p{GDi8kiq|SWtSH{W5dWIW?<#i1xygJ36%STCT=5viC5qosJX`T{#UCo(r}&iO z?-X|`y7;8Y`r0WLC=OAasCb?tJzp_B*M%g$r5MgM@=V3~ij9hNHO2I670*|^SW$ee zBmOFtZ&bWT(b{>ur1E=;pAd1Z#hwFb?K$GOhOxeUBHGwRvAgOAs4Vszh##u@Qq_w+ z2lR)kewOORo&)+Cl@}{6({$faJWcgyDW0eL%T(T^c(dY<6*m*n?ky@mrnr@e{ynew zlHyw$zg_WN)&EuTQ`LL8mUA515K&I9VnT6%#uq6bq1BtRteH zM#WXCU!%BQ^`|RtRQ)B2mn;5I<8M{GNAZ5e#}t3AxRr?ZJ*W5w#kYtUgAa&k*T;$+ zW6BwdZ54AB^NGmUi->)M;!%nhDB|`b_2RN7h~fpa6-OwJQXH>%h~g27GZc?fr0;I_ zr&@85Vx!_p#S;`yR6JerY{iQdFID`3;Bm@%M^vDE?V-r{af- zpD6MhKl_oVXnp$2eHr@Rs_(DJ@Bd6cQ<3CP%3`MptW|l5;&R1Rit7~DE0W*C{PaUg z6njpf&~Siqp9hl4#P}a8(!nm}hZG-GB-@kvUn-KDK>06<@;m_f6P4-Yi1G4#0F0}g zqsWD78Q(>bTn5V4o`gIG$_I;l8!)mZ+1H*B{2RUia|bqK#nNNa}MNOm2o?lcG&Y5qNKOyH*T9E?|Po+ zsXnRLQ}LTRjuMYAg!!ufC+&jpXusbs2tz3wPBq#3;6INK4z+AU6fM|vMNlxzW6h1} zu9J}Y$79WH0CwCWoKo!EnhQX(0CvF6G~8KV8FpJXf)0P9yny?I-E7=ADE#GZKzY+J z=UE=xV$0*bz~({FxefD%Ycbi)#w~!th8cG@e$4e?A-dVPd650}zS? zeH=#HK7Q=Ac@T6yMS1P_(BF-S^OxrgGRKMKwZ(4By9!~JXWNw53BQMNJnY6e?l&vi zbiKOon_bXlNN4k~Oxslcw)M9!g7#%Y$M)rFI?k(~VaH*r2gvp$%Ja`@wv8LnH$5;3 zFn&;eu3Zr3-xw*u{IlilY8RA`_Pw-+boSjZS9hx$luQ;69ad5_w5aHy!O3J%lAHNo zTvRk{7z~1nOG<_f5&h@e1qsOwU;9jd`{KHpaNK^S@1ETp-m#%m{q62fFXQycM>`fC z=IlJH*}<9(zuP`(br-A&F>8D9=)CRTqFLJmi}JR+t5@#0dbNA-${nYy4!)BeT)E>K zXiigW_M+Y@m{tK9<`?()Ee+XIsF)E!qH?esfxE9;24zuR88 zI(K_;(M;5kixe}ryGIY(F>%p~9gi&Py(42$^^R*64cpOY(aIeYSFhM{%A$oku3bG8 zajci|?m=8%V#SU=t6zC0IpMdrHg?;9`iCQRpB-VT@61~_pcT}(2U=Zt>ju;X-O;^v zgpOXhWBuy8b~vkt?09T-{k@OvICarO+nq)Ahj7)1`a{^>8~^mX?ZMU0;J>%pDSUHl zsO-!?iAlCIlD`M!Sn7Hb?Q!!v(RXld5M)!DVZc1;X{3O8(iB1^ z@<>+2suAVL3Nxfvm>?3O(GBdLW}^&UH$vB>@OB~{mW-Im2qb0zL@JIrR4dk@+NX_HoM&6dYPH3oRco=O&b1b`b)?pLZ2#Zy+TW90 zP%A$BUZ4M;=aZA~UTg2Y_HgEN*Y~U-OvLX@M3{)DY4DmbtA>X#eM6UXkwyra-O!$fRF9~CA-6%-~y9aETyU|aAO0AV6V0T?FYPBwL? z#I`UI#+@&13lrh$7AGHN-Ay)2q!z89cz?I!FpD8ji~4Z0KG^MA6U&l}dxS6%kD1sv zIgt%LoOs1|cKE*AacvGJdCc>E-mwb@j zcv?r^lq5g-jW7|{*?4Cp4`%Lj`97wU)S^F7+?q2Sg+irslQkUCi@7|4Ni7=1hF;Rn zMrsi|#HvO1k9$i|CI3;6?UIA6j?C)(4F0(=5$t=4&)y6Z;RfWT4&`KkT4Zq+K`pw2 z`Jfg#Ii6}@!=M&9IVZ(KJPXt!S3fUxEoD%PF2cp0)FQrnWS9t-U!J-L%`;5IPb_~( zY6jZ_waDcUPu)uy)S~+>e?;nKwhwBNJC#(VCeuEsMXr2%mQ6~s z$7uw$$d#Xw8prlQE#l;mT687zK`mNs<>#h&Tro@p52fwGMDQ3fY7w6X87AV7sA1Hi z3uzM6q8`}lMlG5~8=w~PJz==?^(f|_hl1Nkmt#UQHj;_#918LIKN>k11qyx6J9p5G zqErRj^JXi=dfaW>3!(lKP}m3ixfj~OjME2?%ltq_@78k~K`r8=XffY6TbPK$Q6gpM zZcvLT;22MlXn(Ahl=#n+CPWjbcJ-4()+jwA}2qhlyBfU2P8&;SRVZshijys6|e0NP({I zF-(M$SEue~d!QC2ZJTF=iRfkuP>X740n{S)AY6K}pJIYxB4}c}FcD4xYLP|k0JX>| zKrOn4qX4zYDL^d>!bCU)s6{^e0cw$JYtB3~CWiiWJNgs72g3Jdh;2FcCZxbm3WtVIsJ3yIjmZf?C8@ zUHjJsl|U`3LMxyaQPtJwX~6bw>|l2w9gXln@9Oj53yy^sOixNvHuu2~k+2Sc0#wEk zfLg>eAE-r)>%}k;StjB}jDfq7y~hbCxGsGWhUcZRdVcy0Sc1Wa zpkjOoQl7vm>I7}#0>4u~l<9adbkT_WUyF24e;Bg;wK4qnJf4!d_$3uE?tiD~NEG3< zj&Dm#-iKZPnEd0BUX67r*3ylvy{_m8l=Ekmy}???S&4rj_ere1EEvS`1#FV<+CD;s zviZpHPcYp|==klMGQP0$Pc$9heLYHDBj@16U0F99jlV_ROYFr-*0Yb0d=x7b-$sML zW%C=#4fz3o!zlSYX2^Cr>;$BRkda{&5OF+uiGh)+<1XQTNe7{VZv^e@RNi-Th`q6r zXhGx-k2H(yu<%&}^aes2g(BYD{)|?pSmkrWHUtLpt>#QZ3D%IeVLCCeGSjTEaquDt zgR#>5%vPp`Vr3N~n{qj*ZwnM$d>|dj!xpWcUj3%Q^B>XPS+RNXADHaTT4)czUp##8 z0D?Wgc`bhHEC>f;jjhfpH<;$6z;G}(G4K1+Nzn-ACnyRl zw%~NYSNm;CZ=_=0k8omgli>QlVS3R2Y_BE$9-=Kw?^n{cVcN>0>Hb)`J=i|CN01jZ zV1_9mkIN}ogECBCiKXvIT#Cu(OD$xyp!}RnQw1Fb#FA_mMY)uNLg=yw#(O#gA zNO>V}BUY51LS#R(y`~0^c~ZZw7Hxt3fv!2wQRcfa_M3Pw*0}fXG*^SteOPIc$cJj= zPIkF`{@m(vrxE#5AsesC0^5||Q$CSnLVhI3rySQfk!?%Nc5oPFUN@!~`cSYda8dfE)uR<~dt2p02DXuyj46*d1` z)Q|0nIBi4_zV`jk1km^=Zi+2{Ml@XD0%$O9#t4uw5J_VNgJtB8NJk684Yd|HgG`As zGC20wV~^dDX0VH7FD6hS!H5+W{sK6de2NxhWpoT!8B+VZl_52V1&$&g!VEfHM-Wgt zyNoK(Bg#|8JBen8XU#>yaQVP!PRt)PXb^*Du&o@#?I`R&D4NaAloyzsZ4o>Qq8vj` zc{Ec@gqsJZVJ(NXtpi8;>2Oz$s+^XAldWEMTLFa5V1SSyGZE_;Ei8?GVLlsGCI(Uj z$)6l8=n+MWz6IOZxGvomY$F`r9f3(u#zqP(2#+_uO?R8If>?MiW;NV*V6-TF=s>*O z`=1QT;X-lL&PF7-Z&ExCi^}1GiIBaq9Fga$>XtXOG}cr#G}Ap8AAzjRJkb6l9F4Z1 z9L^hkQT0*ic~@!X92rW-OnL!GZTL84G@`&5&p>cLzCd2bsNTUp~vxC^W7EyUV%Xj$`4D zG;l1+7HxO&McEiu`irtR{JyjCCV+53F?kmvGJ6r>w9;StJ%xNOWWCYC3Bu{ZIYK@F zvRs|8L3oVt1mRi2^MqFluNU4ad_efDkPmsZpNp{*y9oyf`Ryg@%?}fJu;dzHqwq}O zkA&9=|18`l{8Y$~T+%MTK}qBnABpz4GoXDU0BHVlz*^<=y)Db(cVEM^g_jC{BHSX} zD*U?;JB-!qC>$l6EIdTmAiP3&t8j~uPpa(4TSES}KsirH4+hGI3YQ8`5&l5P&z-Rx zfA}ZfC;YvTA62BjtI&86kVi;1FAT`@Brg-L6`n4XN9i|KN03&N4NHc z{e>fi{27b+{AGg3-$024IIM|j;XvUi;WQyXc*b(ZlK`G7`2yj6!Y#rVh3^O>aaX@k zSSB1I94DM3TqJA}t{475c%|?T;X}e_gs%&SW5kb!nq|knzut@r}4!)jF2w0*JO5fczhay`t8=`? zLVL3WxlD3jA%8VuxiP|t!l}Z8gog@O3)c!y5S}bNQ+T%UBH<;%D}~nzZx!147XA38 ze9)B7!#fYWRXPD8fz!GCN9-agtgL>NF&j`#UYbGvb2xy)ZUxZSvn!5Y+|yc)tN zTmyq8$m8`4w-8>1GHy)cyKvYq_?!W--&NSJX;_0gNP4&8!kLGCBUpmG`A`ID<~@LG zb{-9B3G(Ja&TKc{+m&OxY>(q0)?*FoAn830hxIfQT7tYIAZOYu-reofw1?Y;Hhae- z9n?Y6dk^+9pXh=-KL2Fe>ziSZ_Y6V*&Oth;gQOS3f%4a2BWC1nKswXjaMz{bdh%5Zq#K#7dIUxmW}`YpTqW1{E^bi(<;Ls zN8gTBZbSqU|FyAx{Nt>*yi&#@8M^Dz*L?rI4wbKtu9#SP_sbtlhxQ)&{Ud$mB^_{0 zu(^o%pI`&z@L`ZQwmUBH%eVW-c=UK|L;2;y)4vmTY&f+W2R{@&68jiD{mY;X9}E+r zsl~N~Nc33bgqvX;UjIj#Dyu7`uwA?re8fdJ36G_|f59Or6@Hih$_wdc7``0+3lA?i z7HRmN(MvSUPYQqp@DNnd$Y%VH@mu(Qcq%#o5&+u{KfugJOJ|KhE=d6N=QI)k-(@6t zV-&qIXB(7>AHpI?0MvWgfkO;3`hVUnjw+^&Oj>rIQ&as)7#k4b|*{?NdUZi zO01am! zj>=rs0{9jXKmxcIT_p+N`w)}#iv$UPX*N{BZmtR%!sg*#m$wAXlLXKKHAMnY1(5*M zF_8d*Z83|}dq-jlfFyt?+0>m9+eiSl)^ZyOz|}2I{+@L=*({L+&_wb6ZdapwBmwa5 z86eWxx~ zw<2k-#alYHBME>VV$~x1$GxSfp8u%FcG(MA9hud+8)`Zd0B0w) zkaj@=a0BvEe2^ju;0zl=B*kN&BmgJJQ}jM33BbuYDL(L$1mNoDrARm@3E%--SxEv| z%<>=sxcu^zPZ=Zt`=AEmi&V2ckN{l%@YHjZK?2xj^+%-MVEZ5exKl|*Y9HDM3BZ*f zmwExaZWiK;xcmvJOIaTzfOo9^l+??dRgeH&`5CFhIjtZ8aB@fjc!BvK0oaE=O6R6{ zT#*F8L&-=0d@{{Kd=VZaMgl0J0we$iKrj-(b2JGOzywTLxb*pG>QveQ2_WA};FV)E z!b8Drq~Br!GB%Ql>>LWMMW3RP8&ROp-wF+P(2Sx~1>5r(E5v%-ZQBc>K7Vnrvp@Gj zJD73$7>|F-~{6u~+2}(u+;8$EycJ2lVz&_~$*Kh7RBmuY?jHKpp{2&2n zk3fqYI57z@05^&WDSqIF zB!GU_bUO*)Z0qXW)Q6~-h4>=wfLoG!o9%%F;N*4^fRk6JK45zw0Sra^Jfo+0XPkxj zB9*2931A&9fCRuE7zu!vO_Bg;!bkulo@61uh*N+B@B{}15`a^H1n_H?013b;KmvG~ z-9&s5rvM3{7yAJcfNKR8g6tL;VXtgXK?0!6PMHi60ObP%IUoTX2SsXkHV+a21#Z4O zIcFdN*vD~7K?2}Ok%F00d=VZ_i6*=M2Fj>E3SA->U=6JF_&Lh2OaBa`^wL;8Kg~lFc3*~yT!3jP z1ug)O?gXNVoQ*Oa`KmgL?*$VGDRK=o(Fj%1$a(nR(|;2=K0YjqjJD{U{<*l7Ejb#k z`J+1V74{5d4#!&3g}VLnTakVX>#NkAO$!yBu0**#k?e=HbRb7G#>(-s!fon8ij3{} zUnn;WyGc*1rNhv1f1K&KhrdtV2GezCxm}Sg##)-ocE?*ezJlZHI14ROX~Vl7;t#R* zdI$Zn&iD3bhTrya1@Ghg15uZ2B8;!?d`lrH_~udw&Kr~SwZluCdc2Q);M_4e3=7fw zwBr$KA^WT`*w^|D^!Cdck#llIZV(OvI};Zij5x+z$c8svx-XGC8}-CbqzAMue#jQc z+Xr*t^FEw*2_=@CM;MCLJc^kZq)?WBPf7@0%XM z9GJM=3Gr4YZgoOVYtZEk-(h66EqO@68K1y``rh1NypE^PUVUa;o$V5CT(bzyz`=yK zvBE5Y7HDf$MptG*xBcSdw81$Jg-|gE$vmv0J22VV#MR#5Uad^JRu3oCVny@^!V0Vw z{ejcO-<_hEIZz9j;S&g1{7QC2=9Z#JJ`2ro;_t#@UgXXGfT3qd|Cyf7wOu6fhmwM%wR-f1FnESqPPu zoJE*|H3sfOYNHgZHZc87KUEaZ_qe_yvfTpzsSvG5kUw1~o{e zOW+#bG2DoV3yE-U8p#H8#;1?^^k_U*9A3j@30%nwqj5n0XukQt7ZyNO5Y3;6+&z#L z^9S#SWKYw^%TaLfz-WFy%Vp8%NL^`brCD3mNr z(;+{<55)2!8fs>am1yhPP85mecc%q54ID%&z+Om(V}pvKoh(d3@ziLiZqee>Xs6xz zKW|dB$Dz?ZMnuEus6R3q9)N1$yS5LRaG!^ZH_q#AU;p08kO$wSXa`>sKvQxhfQ1 zUDsUhEw8CwF}-&7kuB8-Y2p1FUFn<5fzs~*e}@HJeVjBm8l zJ;r3wO}?t@JqGWXHlKCD|7t$y7E~P4L6d7#eQqW0@jkdN;H$ zVf&>&Q^p&&j3sPeUTjzVZ^l00cA;PXe(lXWpOB2JBbcY~)32(kuBl#7SG8TF58K?uC5h!ow4$DuTegCe>!UlDks^k)li65cEPtGg!c>oAbd&qt}u!no%M@^y@Y!S#|sY-)(Te%`FlL;UmzU8 zpNSw(6doj8EL2I0NJ z$AnvjZwn*%^~B~!SS>tKc&(5hVq&=`gr#_qOWFMVfnz1}Q%clN7cLMk5v~w63y&6_ zCcIF1tMKPUY|CE?A0VO+=Fg9Io{{_~q51Vg|2N4NKLO>LJVtl|5#u|b2s;)x0my}V94>}- zo`#$!xmeg$SSIW%oFSYe40r)ml52%ag-ya$!efOe3eOOpCFH9*_U}UBWx}h3Hwu3$ zyj%DS;X}elg?2uNJ$e(-?pwn5gr5rerkeToO%tGf>jg+}AL@4%@&_`?cK!#Bk~~H@ zQ8-mNM>tn#*9X+AmCPU4Xzxtn4~51HgZ?VX*9m_rwCe}*?~%MoNKYNw+bn!W_$T3C zgs%$U7QQe1hmfyjX=lgp?em8}>h~2+7ETu)Dy$M7A*>f3EnFx3uF$Smu=`($(+3MStu4HF#wEn7FbO|CrQP=H44GxPvb{>Ifo&wsZ}~D@7lI|o z8v{kAz2>y%U5tH-_Sl!e9)ITx>LBU;0T+=yaGV88khchmAkDl8_!fK8h?XF4KIF`H z3wz_2DNGXEr9Nnv*OH(PlHRZa&r36*CCH`4g?^_!R2dZFsN!(-=m=JMsf^Cu3n20!CF|K|RkD`!7d_3Bx<$;#QAvnt=Ioc^X4 z$C~iU_Fgika&qM_KK?~%iM-ZxTzuF;A4Iwan!En)=WM8?{({PvAM;*&)GK;3 z9M0c-~KtZf@)4{rJxPyV$AS_KNs?p3Hd^ zGkPw@o3=5x|HEhMW7v3bfS&{YvMwMYiByR->h}=+_m8-#ibucqHrcFz@vezr&uJb!AR>ru(2o)>Q@6 zVOEWp zo8ApwwxKBf<}YIzKYkjT?8tOv7|JF(+l1xuN>QBHBVG!7Nq!a}F{prPv_Zf5#9*}; zNj9OIiNPIQ2ja;tCKfs|C&>s;iNRf*XnymFJv;O>L-d=cvwHST_{T30*w}Cop92$R ziD7Ym6*kGxOo_eq(RD95lJ@qI7)jETF0rq~c#@xUPK=P4lib7sjg**|9LBDVl319G zuUE zCyDBW-9whflk8YxL3d7;{N`ym`+NAuRV_p#=Rknpd zv8g*HI=}hE&pMrFE$1ZbG{ikobf=r?~H#rwNGjqcHJ{#BZKuv?TbCrZnb zxxmCj$=yusn|ux?6AvfGo9O)J6OXDP=Qp4Dtp?!y<`bLM?ucYBn)-dG$yT=_c`N5* zOQ%Ckbbj-RCuC||k}rP}Ppj^f7N`3op+%{j|*=O$Nk zL@(y@2&UisRyOpKb~gIWb6c}&k^SS|Qp6*vh4lz`v--8O_s>JjF{Z{ErAR3Qfpzj-I;qy}+UgWtTXpO=bKhTr^qxT?}` zo;MB&_|3cg^3+1g@SCTzYY2Yx{9bbce)BGWcxo9p75wJ;b?Q**h*T~Hk$~U4JC#(V z>L|l+-jyGh;)}rq{N`Q$gj65ahu?ge)t{0&g3}1Uc~^c$>Ti_cH_yqT-#kfE3HZ(P z+uPtLq5PqJB0GnTbS?T6jXaM6g?>KL+(9#nQWb2^4#;x$xZAcDLj7_m z?Cj6I&<w!Pnm`$T^KLsvQvC2i0)F!>OuzZ*>^1!6 zd6}T!Jikt!fZx0u#e~!ctPj6=Ud?gzrFa9GI3={}CL8tK)OT1Oe)H~tTaw}n)dc+J zo!pS>&GPtozLQs{j%IuCo3BOtJfo-BPy&AQD@_5v`8-;H-#jzI{CNJ!ECIiHnlQil zOW7v;=A8n5^V4`R!EfFv;5R>&69~U~r-0u)X)X!)%{vAB=6}Kx@SAt7&~N@Sm}jqS zPT@CCnVm8je)E*q2QvNU6BmTCZh|5;3pok+%~Rl(xA&GXC$zxh`<P?P<2E|ue;-}}+$XY${t(;;m&Dn{ zeLKB|Vmx+-V=cJ~t@xf^bx!mZ z9Un$HQc3>FawG)!qfIvjI(~bjlrMDr(cM{&zwOjhcOi9SIz9;<--lg_)tu)NE-b!NE!nM z`T;wG^PV=dcqk8)+?snRRD^aNkgIH4N*t7e1>2XPU}pzwTPuIhouPqTivt1Fk2H}7 zGie~i2c!oCi;p2<-JSxHMlQG)1fHqDR3Px)1x$rVD-%3tKv>(##4M~RM3`&I8H8G_ z_&|K9m5F92L|U0R#tE_3pi^H!^hl!|7#Rc(1z(j9M&yVd?bT-@`*W5wbnv4mI0FX~ zZZhpm0xdYAN4u?A(Ak2i;leP0G-FeR(+mXslmOPnkz{r-na1jShZDwGavos{*08s> zJ+4L6Yaz4aKLXqe7D4ree;`NV+|uoG*;D91moHPTsrmervq<%ir(Uh4hN|y|zNW7ZggP zm+y~yf0+B<{e4tu0mtHV>hQYEdCcr(Cbc7tyxp+Iyt!vb4n8}=G%sZ_Z`Rq7*=O4m zKl>i!2jd9jU@)0BQ9M}uc}T6sioJnwj3sB|zb%}-5~PM>#STYc14!b(mMekRW6juC zIq@z&<`02;erCqLWOBOh*SnP!FT&dAGnL=yNQ+#L8`#xn!1q4O=nnzA);4oSVdMYC9@+R{zULQ|s`;pfnkMM5Kk;isa0!Nh6V|f&g-5tlTM=kc0u`Z;f$msS6BJf6crwJ} zoyYf6*sVsklVFO9#DZxd3ntvbf+8f+77St__%ACaO(4^wYdR8&b`5_R0!O5%uqR?K zL`WP7ANw6Y5{~u=e~^oe!p=q0gN%! zeC&~a_(+gl!nq*flsKkM&w_9vEr;iktrG70c{~}?S{U!bv1HVZQYzcYGU)tH7t6PC z1Z0^~l4U^sCRwI)G|%^={j9YCb|4cn7t z9>ZgP$MB`=2A05sfSj4xQ>TocG7jFL^1$Co@=Vy>VKZnbYcy7`STtlfu%?Me*AY05RxD22zm^psXRN4Mlty8%s=8@mbKUZq zDt@@Ws;a4S;*{}VLM&>^JdTm!^ug9@sBfxU?N!y+);85N>y-N?pUF3$4LcOfUf%|h?Up?e16QQHT#uwPuwMR?F&Ulie@s;VWh*jQ6- zr=rz^tLmyT4#(lyf7$`*v4e)ChYuV)aFB)Y88mp%p6R~uGN}P!q+j|_oS+5_AFu$^ zxNu3jv1VmmQ(gUv^x&bx%7+a(EInZP!iJWS3+o%6^JZO54MZemI9T!j-$Ua0mX-6LXXWJJ#wjx%2H*Av3-8;<=B7`Kp9JrUlcT3ZP7R+% zKF;jyM@7fU_2^^#Egy%TR_)7Y<6Pj)QpOUtuY9&E!eF%Iw~OY#RI-D-CuBa+bDR8Y zK8{^_zY-q@=cny1wx^*D@^SdIOyqO;zmtzM0ru!eK3zCRxIkDZTp?U5JWhC~@EqaA zLO!U|?(M?+gqwxW3SSleO~@xu*2@wW2zvQ`Bh7{ z_r5TO#}~@>-E`pok`ENt2%Ci`2<`jmD1V9M8-?c2488d=1OF(!ecur>zZS>#a`0G2 z93b3RXnxGlA1rx^@CU+;LVjVB_32SWRr*+k4&M`3}mRQdc3jOF@EUoPBR`jNs3(oYr6 z6jm$0Mz})QC_GxYPIw{_{W(Q=zVIU9CBmDC=+`a6JEi}*@ImPx7CtWhGr~U!|EB!6 zg`WsX&!v6*5NU`X7!C7@=wD}HiEu9>)(OHo;ibaYg>MRRW;HuF{TZTJ!#rWJ(B9Re zy)wytg;RtxgmklGzYY~H5Y`Iog-t@c{-XS`l1~|e-J(|d{OwikY8)0 zUHgnEFyL1e@%j#V7hzghCfr>}o(0R%vy>RbZK2-?+64LpEav$M9;b0*hQJ6nbI72u`NM97@*9mvzSqqnIHs$A&we7Ye0M3(JHDY2GbA7uPxIza~!$j}ZgO z-da?%pk*<>b5dLHDP6r_0p6@-=Hfj@rdW;FZ;SDDn2h?L)hy$0FtUi(X5PSs^~;yz z7lF)LwfNx&g+|YsI}a@b{T*|8k+ zxb(rw?ek^j%28&=c7Fw3uy9**>5mnc8m|H?mm9HBx&6rZVHvJ$uM%s}2PBR2^&ze& z!4l++fg;o1uV9a^pR~vQF0ki*pbct!-n-auo(?7h>cHNjj5JIC7SE4w(1@0x+0-Gu^aCbR^3yk>1@4-?Ach4ye8(`Iiy(m@?0y=PH?a~~{0 z-tkam+M9tw70}Thr!nZ?`A7$Kko0m=;B^NZJ0tHLq%-YpfIV&}+Utllu(uIu+6(&h z@viWI!S)Ci=5f727?kT>vU5DG3sG)dU<}B1x!jI5vw!Eqa2|B*Ujf#jf4@c=!)pN8 z@;vNi?)$-95JM_MC@kGMp4Or==gJXO4eVhzYCDFQcP0AwR8R;Ql(QEZ_)(JKLwAm+ zHKcran#-5-v{s`{EIaVDzVlT1Ed$;NeYf?E(QD3#pK#-w+xDN-ce96RB>gLAzY$qe z@J9HM*>8jnDR{$Qx_H|aOIK~%xMt|Klh@R2iz0o}nw8s5UfOHhWouU1+Iwm5ZLu}} zh*jIxPa3wZ_Zmhuc?SHgXkI7qx4LZJ{D!xNR{VXNw_RZ+Izi_<-R^-d3%Zc$+BDlX z?E1mB#cOWc<}Dqz?SZBD!N!Bz)*o{6wpe!Uw#%2+Zo6!0`L^2ZTejVs{r7EoALTrA z%eD$j-L&oA({i^Q|Au#3_{O_m4}G`%ZpJvtOgHTBf1j){|A(*rl@nyo2TXVozaBe5 z&cR6j1}jfgnG2kCtFhrg?>YhJ8nBS~0sc@ZNhxsBU-q|K0uO}46@jc?aX-x7?Ek3BgZXg{sD?V5)MvQb4AKbxpAa4Ap z_~1e(<|MbGetd8jCmJ;?zGnwx{FjoNwFueS{NTXzSZ!=LFZ>h(FN+V0^M)|FC)?gT z5sZ&F&GCICMv~(w?kh2#JO^WmkC2#?e3kbG}>Dd zza_pEg-Okd-<-b5a+1|->Q0G{nic<9r;+GIs5CEm z3Jc$*y2VL8YQ;C%ERmYUC%X9k-Ht=|LZD`mk{N%n8$+3pnnlV>{GsGyCiYFf0F&{D z6R(@-s9Etx)sUlR#eb^-IBHgWv)UbztfZ;mcOnNRR9caI02trWi8s}uQb)~-KOs}& zlGkvfKdrh`lJu&NKa+hO`buinNajA5?*kap*k5xtnpBbd~zf3TsK zw6l?##VKXgBKya^rHH(QBI>bSa*)-LS)I>B&AyTN{7{^;lj8kC9MmkgNxT%l$q)xM zYmp5hl8V3x z)l5kBXMIq!9=7^ZQfF}*LCtdIXQV!)3~Cl9htw>F!HR>Lwc5(hP4T#jgPO%d$*5Vk zu>nxCc#Ie|>qk_8n)OH2FlyEe4hht(9+;XiLz)bx4N$ZAK2g*x9tv(FU5?Tj8_7g= z4jXAU`V@^Yf?T1`J(xRaMp3GQ?a2er+2d~8UI_J{fWprH+zahs#_5B{Wqu&zI`UUe zBdA&R7)dw7OM3)bF;pbDJsiE9Bpk_Hamg<9sr>p9 zrXFEYP_uY7qp7)+LCtd8F_QWX2Lx&s3zM4F!d`=##mfY#S)Z`ipk}#IOfZUJ9Mr7k zW^YDnUtk>6tfkh~xvAq>9@H#%z%5DfU3whUEGIXl2CzJ+Sx#P^x`ge4nw7L|4r*2f z3xJx{%@m+!?Me%vX0ZoG&ANvrK+U2Fqh?*nHbKpD3Q)87gG(ILET;f9YZfOE)GVg} zHS0)L0X54hK+XC+OMsf?T6qN2tSKD8z zHH!l0d?Ys~s98%)1~rRkbqZz*)GTfs9!QdReKQVf7S9A-c-D!7n#GOVaiFF)}8gcR`{A>pNb^Ob*W+g>v#!UXn44pItVgx)^uRYOytO^jFnV;4ZrG-4 zysT-ocdQ>h81=I32fPdXPW@1>)dJ~%Wr{o`x^xh~u2x}=F68)(~H>2FqkohTtvd36=x|Mqn@=vh#YHC^T z`7;XG_%c)>HLz?W?aeeDUuccP+N*Ab=g%_LW{CU_P}#ls=O17?e*Z3wwTvuL|9}#j z`yOPn{>yg3KmUNf)bXT9K2mRvWi$F~i+@G9&%02}LI1eH`n&?+A|!r*wQml(8O~wB zey5{q=&8;42`k`k!cjTbKWx@o)9@fMPKlj^6E99bl6WBlz ze^dvuufTT_C8lJczh6$k&+3yyo=!#V2QK(ZsmM0qK}`&}JY`_qTzz~)?eM2h~4W^$#IMMVCkya*n6AG?S+=5wL z>4cotpvM`M3uLt|FCzuo0fFOh5B@@WDl!Nhq|0clmXUB4W@TD%Azz$@S%HO+cNT|Y z3k-4z8M@#vp$HUtSTlmZxH&t3Fc&MRH-!0E!(Ov*ld%E=G z8s0|&eNhm|ze5|lHoyhG?+r(p(=D@zMGzYX%X^wm@G5!L>*jP|Gfi}pDU z!4ia03Y9=J6f4@APIU9z)Id}pCJ{MTC^MO;K1^vw+HKJd(~;a^xgGL-SmWNi)B3$T zrC*m;O1x&mP6d(uZ_f=z(XI*Ru3du)+bwrN`W04KoJy3%iT&Q4j`lJvN|Rwxn!p@3 zk(R(_p7-w5e)#JSTkL-KR<`g6)?yF47+VmumtZdY!2SfSGaaLs+)gyY{vx6gQf)*dq}zx_ zxa$pwMo^1r6vK|wPBi+BC#F$RG+b;%BSzU7SO{KBc!?h^*bf13iolWyFG)uW5KbrD zIf%4Fc2POv-gF*3I9eQT1_7wNJ=9Jy*f)tiqWKI$vj;-&e6Ac`HZWY2R-q!+_*b!Y z%A>nlk)sA83XodbA-<0F=qr>8I&5QSaG$*=fipDKg83MCXx~_Fv=bu=6%UE#A?(j! zFr<3M!Z-KFBy_f7S+Q`ZxzUcXNzvqpXjW_xNLQG-2WA`h>hg7yqPZ~35JJ#Cg}DaJ zC_@_~X{%#+!+`Wa+zNb2Tps)qTs3v{oC#IaMo*iF3lbddGedtgk~%|2d{B2tjM>in z{mTf6du0CDga9bZ7Sx)XJz|_xFNOntO=IJVdatbqvkw?McKqzw43y$RserRn4d;Et zO=+iTjNND60ZlcHP4gBms|JCje9*kw`o<&noHusr?1{6h_HsCH-0T_iW;E6>1w*81 z-u`39+74dd0#E%~Fm_0&sa=5%EUd3Tq7JNquR=s}W2$a$LH+Fl{TRK)IsRMp7d-oA zvYpz8Iq{J3RZ}O<#;lK>;D|dQJA8eb(!ZuAeGb>CVLB$Hty^=(&z@6NIeOxh17?Bu z#1W8wIGh|AUmGw%MC9e%k&xh{n&FHGS6qvqYnX;Eb(k zX~0fnoSdqaI8H&(YCE8D+_m}9pQjr`0j4mSRx`WEo>j9kex_6j3rI!2eBF1;$$Zm3yUS6f%J z$T7caoLg1Kbq8JG#RfYY$kq#2gG$y^Q-g~N&$l{}1y#`o@{X{8TpZjYT%XYF^8Y*u z2{%_cSTlJ@Gav^G@7TxY=A0Nl3GAaWxrNag(df*`xZHGTMRsoCnAnWi%-o#O9mck& zbG`fSf0WcEtK!Og-w2*kJ_eoF_B@9h(2V8(VjQ6&^pD-;HX<*nXGVYXn9kT&U7Vn@ zMVUI!9dq`imW@|^ywRpFHTQ>5uKT7lk?jz7AtJLEG3or_sNYlh_6h*7-ymkNI(+#=j6{JRj3(N?dcaFlSe@DO2x@CxCr!Y#rVgl`Fb90KgG#U=pukbJ0c zsqhrx4}_NsZxNbrE$Z|4I@(L(F^||)XdEKQBP34|&J!*Zt`+ikY}UU}c&+d*;UmIl zg|7=g5$0e=xAukog(HR2gjK=@VF7;PVZF3)pm3CMnvfq&WI5v$0Z)~Df$%=z7U7G+ zcZ89+t6wNA6AlrM6V4GX61E7}3x6QIQh0~(A>lK^*M-Az?6cn!geM3$2(K4@Bur$x z^1BLq2nP%Ky*An#B^)Q5EUXjO3tNO1^9S{glYFx94BzWF3} z5(XR@ep8gPp7t7q zYlX)OPZ6FjJV$uG@Jive!k-Fn7d|4~EPPUEvGmaHi;`a!zA1c1Xk1>Dv+FM~&g&-7 zxV^wa$;HC7uuNDk93rI40qf5dE)p6C7<#*Y1DmB^D?CTQZj?nHOpto3oz=6`!rIzI@gcdsx@)XI&Rfc@H zh4Y|a@66B46BGcZ9u*VOs(;oM;z#f0r4eB829g63| z^*BEUOOUq+iXhFrKV$#;HTKzH3G(Jck=gD!{lK$AIkroE&~6jbK^-K$tMQPUWKWg9){j#?|h_#I!JnN z!QTBiPX z=ld77OZ#jyW4gRK*#G)K7c7Cj9l1#tqJK{Xg@8dhz6xnv-o%LTJI75LG^D&d&E?Cv zNf)~vCF;i87w<`mJw%Sm8Su)R`zI@7l^ZHYkdqWyT|=~axbWOOKt4TUzJ`m24Hz~&|5^Swk) zXUy)&850#G!Rg`m?c1Y2C2_c;bvl=W9%Rq3JUoq9 z#P7=_E<&e3ETXqV;595$4zQQxaROoy(`bV+ zpFk{fEk-QJ6Np7lj9Z)~5R06clRN>2K`e4&KrHHHhDa>B4B6Qi;9pOuY-~8_Mqp}4 zEV>oCZgX3J{B&*flwxg-1(FXAp}bXd@ZLRt2$$Y0mme^cchggkJ+=TnCn?2`6&Bcov5|kHewMcOT;1? z&R&UsT-8D}!h3WOi|%4qK`go&V)9S;2VxP^Y-j|#xhiM~n}>T{9v|*VEP|V7KrB)P z5sTC@5sRD@Px5*UV$pa2SO&>mIiGh*Y$FyKDZex?Igy3$(mqw3{5{1@HcKQH@e&JS z(J#?G5{vkD55%H3Oe{+>#0Q8)^g<7n_Dx>JF+H3ZU}77w$TiePEOG;ABNn+nk4TaQ z2x8HmR<|N)9Fr}b#+ukhEOMsCB?oXOpH`ozB>8R@#3CLzBo_UeoqR5T3<{B0G@6CC z<{X7WBo-~@h+fR)5lmvyTDJR=b~X}=*dbOevVYuLicaP~>aks>BC8{_I`4v-j#$Lm zNiC#Z5R2S^yc9ojKw{BlHiSruFC0iLa&kO%JsSqG$jLdW_s|H5MXr8c>Uzo`7Cncn zAc;kc@kC;g%P&uT%3*<6^p52ZN%29B#3GkJJeB4wfLO$kFO2!bt00L*?o?8dno1eO zB3FJ~suSyjSmg32SPUr=i(E{pDX9Xs2V#*cKO=Q2We|%vIV2YGqfjIkSrBljZ}bGL~el*i=L(l5R2wx%EBZT@nMa`B8H(6v51F)+em-K zgk)?a6WKXzB);^BMt+3?h5kp-a0ksON>#8u-?l=m$KAHQ5b760VP}8tg?2FG^ugnD zb|B+Aatfyr#3D|A@g{W6h()a^k+O3Mh(#1|jHl*vcpw(J8H}VZ<@iA?(jI{pIdIUT z@V}Us4I>u4N>itEb4^mjl!;yI*_J7 zEaKISrna)`388$q9V4j~91w^_EKFk2``iW~7V$DcViCg=kyzwLF(LJR+5@qupV^y{ z+8sz@(KXi9xsI>~Vv#%GmRPJX5{sPNkRn%v#3CoJPH_X1STqgo^Nj97GlE!jxG6v^ zx|$_GEMgDBjQPYH0}_j9!iYsY;gVS76d)Gy3vVPAIR%JCWG<6fJB5Q`|U2;_iRbO98pQOF^&hyv&QR?ZoSMOT>& zVi8Y@6wDNeMcg<%kR&@|(Q{CA;aP{oB5vF+G0p^tMQqizzb&W)V$nq?3StpeU45Pg zZ12Vn#&`G82oH3{g5nsVVR$ze5h|Pe;64zo1Kr(G@{4Lw3NfGTZ3-eh zkyzA`ulBR-JtV?B-3CoGLRB0l6&eXy1u%n^;Ya;HKz=8&<3#^i58o!v2M{H%{c zHL*YZN=`Sdz1Vg$%Gkd(Kz~*EJJ9vM6#u+Fr%`hQl6`|XL;dbR3!xu{y8E;fX5MbA zy-;f?@e|12?!Lbez2+JUe;d)~+lW425Xh%DNjuoVwu{r#HzQ8ZPSJP1h_AyJ5#-Pi z*SmC@$laNGA`idqxi#3;LpUw?7HKEs*dr)puM@#-F%RL7&XWJ?~c$fCAP79 zqilNnyhbbN{&z32k}S0w*3R3PWZt_WSYqA~tR>s$H#f)Fra-nhgPg6PhfFWekb|LT zjtbds3E8-@a|h${y+fER!3w4Y!EKPkc{euSX$iHKoQ?msbj5!+g%N4oUeP8X!M!9{ z>;~E^MU~Lk4B_%EX<|SP;swmJ=mhf=Zsu!-gTYJ2&xWvZZdk#)$NvmzVn4^3h=x-L zSpup=c;!Hl17hLqG~N7H`e`s3kj@XUo@9YVa?-{X0AHf8pb*I-V+0h(!fRk?$iTS} z2Qm1`3e<#|&U3>FWW;<@Ey`3C+zXcP9h6-~EMhFyick;k=8W)%^;URn#-oa;x z1n~OQC-)tt;D4V%@HvjbUxie#J(IvWHSfS5FlW{O3{ha=vbu&U3q(@Sck^Eqq$K0@ zy>so}Az;ZD@&+=(I{d#Em1L(#H0@`me{&EMct^w6p6=C*umLA&#<4)0koqP#URO0O zszdy#Iyy!(5S3T8xO(~WYU2YT<$UhV@!o=VEI_~*xLd=$ds&@%gd^S#j2tip0e66k z)6ulD4(`{h7Fr}0*sX46C4?eFk)0qA*sGz9Nb-I`u~>) zcbh=oe8Ss*$2cVGGQyCI;VX`B7}GU!ZS4e^)2MZNYFC zA~tj{A`11Fo{yd^H(JOCPRi4Te9)x4K)6`gB3vUpMR6Efv~# zyCIL3JVUrnXug8T|1Zfm3C-6J`u8Ol;rWzy%Y^owZpdRK&lJuVUMRHhZKE82m}7l@ z1Bv)o;d{a;-n~*^D4ZrdOlZDy$p4PyGlb?N2mN)D?-u?>_($Oz!cT?f)qr~4u;a7c z0Yc*dK%Of3FyV6HF+zUii}fxR-XxsEpFW_k7S;>b3C|Q>E4)+qknm|?6vra%6bX9? z_Y#g59w4j{8V3ONPLh1C@G{}8!Uu&<3SSX^Bg`u5~A@h7seX-D996>IV+*ioAd@RQ|eMI``5DybB5-t%QDYWx3 z${i#5c;R=2X9~{~{!naSI~8-=$Ceo>Z2yYSIA^fxOC82T9Q14yIKCc&$qrxDL#O{*qdW8I;l1B>d`UL$1$y0>0g$D_7 zn*EpY7`F3a&TT(l{`)@6!R^zxKFpYUTd?cd(g*)>xxg<9ZsD8v%q1vS4kgpvc3fC) zgQeU*p6j^qo)V{6uL3KVEqJ4z2keZMWw^4vO00oxB)$8v-h=aKumpKypvbiMBJ7=l zeT??lm%tv+l|daOy%TWKZN&Z@EJ5BPD1tQe7>9xWV8IgP&4(hh-DPE-mqt0ZOMTET z9jt;nNP36nqZ|`jg1majnf6Y{#0T@jVF&isBOTPCiKAhU<$@*1J06NmdlzQd<0UAt zcRtcV9oqOV?2*e7EJ5BmP-NP>7WTNEINpv}1A7~hW}R}ZTrS1K#r?rf0hxJRZx9CM zmf&Ky61rds%H0J8)4}pQ%8d&IAlv1_XNJuF{WN2|c=T!O->;Fz@EQQNl)*nGbDs{{ zB4+F!-dvQcfRaAUd~Ra9oOiaFFAxlD)9V+kp_`cHS zCGnv|f4{uST`J#tEcdlv<#vVFa^B{jf9R#@w|u;x4Zr1|e;7&^-}CbiBjwc4cliW= zLEyXG0lv!>{VKh;J9_Y09_`)S?zQaQa|d=vH`ft=CK5T<;{ZMvedUc%<^sQE&EqAnTeitA_c+m~}&!Z752A=F3>dkMk429hnZl zfmEWi&0F3lC{&!-BhDWzlk}ZQ3@Wf6FP%SgVz63_B)ejmiNPIQ2jWRm#uI}JotTrn z28I)ZyExJOnG<_<=m&f7j>JUWjqL23@NaLZY-~6HN5W!RVp#l9w$0n9#NG*K0OO;$ zkHko_2gQ9Q#*_0of)NsPlFQhakrMNg&r=*Fu`o%}XJS8z#mNsSR!Hoc+@FO2bw4b1$R>1&#pDVhGv7ooBKC~ZTA zKQjq%8~ns!@zu0$^L=92}yv`rjIJ_}4#C!AYtJjsqF7If!i$)A~qv%iOb zT-5^HDvW#AoR>U^h3`_`;^dzx zZn9aTKl5=E@9*|Bx)*{!^Vu}@V7F)%#j@mI*z1QZUIP7@FX5OTPK>u)=g*vYR1G-j^UW&xx1pJxb!xfSK%$Kk{{Fz;Td1_zE@Mm`Z#zRt9vOV}S zyZqs)k_cq@Gt*m`{>-_w2Y+UFDyc}dP=-IVD?ctZob}<)?D8krXZ#cJXD+k)Q&N1% zlz>08D?cN3K4thbb8_g<+>tW;neC+p{F!-NCE(A@L&^M^PhbP^XXY_t{>)3MfIst4 zv|#?s#T*j+nHkS3On>HkXaoMtW2^)|Nr9jvXvS@%f1-58Mlz9|Lm@s;MkCLoKq0>V z4EGlp%qU7#usu5<%h}^@+g=Fu`E_zT`*Sa}gBhof@o0eGs?ZrTi_feH_%r_sgDLjW zVom~q5^h6@l$}f9&rE@PL_KE+{>*L$BPqTP`{>_g8s~RvT67;yHQL?ZD#!pe`enNCE(Az$woal zHI3!r&+HDkB`Ll%Ou(Pn$qlLAEDwKXC$CPGaVYR-u0{Li&pe6+;Lp6$6!2$$nI--| z_Pzu@s_Jb2-nlcmGf5@{5||*{urCrw0sIk-K1_5}FMtku*{+OlK< zpZP^31)rHJ_3;~o|MaDx*HKcV}>fW$>@Fqnf?`=K|BIJWw`v=i-GysK6Hb#@QD8jl6-`Hh>aXt z04+aes1t@$AWms4PC ztT4o8)7I?0o<&@b6vHh)yl}q|=Eu`+PnX^94MN(H&CXWVQGBf(~ILeIG|Mq}!5 ztP2rxyr=y>E-CKbWk^<3-%w0d$^FnkD4|d)LPcdIh1pD7JOiT`^`7-(?4FXfFxmH> z^K)22$=WekK;U^lhv}S=wY80o_ktg(MwFAug4k?1wOnVE>t>_b+(WrvhPB=;uv`Jg zb^u<-Pt5XgIf!&Zkn1*NGbqdl*0;fq7FiOJgw%rUQV$5&PX4%3o9^v7fBIGw;->p!!@|` zySjt3P2F9;VXbGmi!wM2>GdYKgoRmgg8IS1H7BxMMq{#of8znl{ntasfvEy+z;?>0Q^16qwrw}e6 z@?@r-c(UpNb`y$sM{Yb{m4U2IkV~WC#>*wf0n?pEqnUz%vjnh$+?lfFVurehcWJ9}%P(GwP9_az7T?-ba1Zwz>bwT z(i4Y=sTb2UiOGU6dc8>`p_gp4rqjxLahfw z-&6DPN_`L1{K{2LaP7OIvU0>qTsNHEmN&pWGW6AEB#5MzH$W)0yaB?g7C+%A>TE>Z+?agt~^}#|8>0^_9A_}ld&MCm*1`H92@a&gDW{s)Exb6#7COrvmBFS zltje5HyT`;2%t=?D*$GHHKH@T-V^q~{4e?f=06u<0P}z1?#%yO*TupF-h@bQG6M&l zkq4STkMf=kX`=svS!I*Trlv{1t@RC6pbyvAl~=XaG?$A{XmEf#t~5|nN3YyU|95Bl*EUwIC~rai^QSE^?fYNg{eO7_ z6uJMFm$M(tIwvctn$ba3T#Lc^63YjCVpd{?e3<|GGwQH0RJa`9s7V$ z$WNZ@c*RMI`~yz?EX5-fSugb~6or=xd7a9qE1sixiQ;vNTNNKr+^+ar#T|-oDe|v8 z>$CO&;=&CwDFM{WTYTUol~*Y89XjJrRXktu8pWFxf37G#mXZEXDu19T{7vY^_c8Fm zkSX^N#VW;S#Zwf|SG+>;M#Xy+pHTdr;-3}8XEEx@#@`vXzff^M#e)?23Y_sP6)#e} zQjwp8882iTAf}(lofHcd#m6t=4_2A3b(pV4u~qRF#rqY1ulTm&XNo!aE6o)HT zE4C<-OTl#CRotw2tKv4rrxjmU{EH%8%`tyh#es_ZC{9ycq*$fcqPR)%LdB~Uxe7PS zeMGSqfBz`US^>b*RK7^@YDHNy0P(+3`BlYt6?;WZIfaV*E6!3pQgM~y@rvgtUZ!}x z;@ygmE55AwwxWwqUu<_5#r}$;6{jhFTk#6T-zvVL=x3U87ARW#fF_l#eZU5l=~9UG zUaa^7#VZxJDBh_kYXKnr^D2uy0OU_7W2`?@^zbT+{C@HIkN5(Wdn$_0f9Qv+T%;(z z|Di8cd8(rL{)c{{%8M1n9su=-Jpk}H)o)M~pZ~~ruF4lEiqC(9ub_r{WE;;pK` zSLFv3A1C5CpHvi||B(Nv@oy@=t?}jZ5?z_OG$^#UIdIr^4N{GeHSBa^C0Myp**_fw406l z4iv%il7(iRSRVf^+w!hNn0Z(iw})}^dKeG8F^>BUiZW*aJ=ne>XrJxBJjB`dJ%TU}uK^(2iODZ#H*yQom7?JZf{go}2!vl}T%CX15X%x`f~(U>t~lF8zdqOpj=_Qk&MOZS$h zw6hy2y0vg;=&W<1r`-7R&Jl+v>HFRrK7GN?@X>iYy>$zAhSufnbdRpyb=A>>clqnq z?AmuJiW#aMy};PXA52uFkx5*S(qV?8^N(`^8&#l}hNQUH6{p zKXvj>=S=U$yZ;!W5|BN*-iNRI??Dv_Uyk35XHbgk{Rp+d*ZnkTyx&pXC}ID8#M0M& zGj!tXekTGk-Z0_o{^tyXenVgP)H|6xYd*!E#q{dyejr*AABG?Jx?cq~2%qt(=n43` ze@sN!hD<@T;Om}Qy~|km4L!bvFl|HR;mnQJLfeU9@9zjjyGbYHzKcZkb$>tWC`6&~ zb;4fbh_)d|B9u7~KhI;AW5Y>C z!Z&^0*P+^YF6-VmW(siPlaVeuUd3>{E5-d(jK)a-gs*#B`L}WK@O7`18-L>yRm_in zj6;O4dlOqA1{v^mZ^WK)E~5xv_eM+xeBIy0R&nt`__}A9z5Xcspe#m_Oyc-CjGiqA z200XeiSj&^H-g-~Kid6Eq?SX5ZO9)`oA|mfz!8}KKB^1DEPV(P!q>fNN;v*H+g%as zEwL$I_v|dS4Pn8Ve5B*9HAKRrA;2~ymra4M`(+U0f5H!Z-80OJ_&Nl>?zJKe4`*F2 z&3owU{zbHrwjt5mx@ZRVb+75w*S(RV@nvl09kHJA$%Z(uX{4rX&Z7gkLj`4>msIn z-J6P1zV6Kdq}jXt7wkz}G#`VA_T}!-`(l$wu1{Hi%if$`AXY z>jC_s9^(>0X`L9=tqD1euY2}Rq6X3Qb#D&HNj$*LfNjW;I560XC7xzHY(tD3O+)7SlV50JU z7|Nl7ZOG3henNuwSoC#oE+wUj<0->7#H62^7{&as4KeXE61ynFHbfj*^e;=aup40; zV$#n|{EjkgL)baA4QZeZ+mO{#-{J(%EBd9m$WC*E2hu?x%73<_rV1TBotrwhayEnuHCQ= zp@4HdA!}X0HpKK`IB^}1AGRSnBTyp`98SpbThM}X#n=50Srm=1=z=m>+J-#Fs$m;qj$($`IMLUAwUjqE!3Q$>y04U`E>4s)J#0hF3AZxA6=>+| z-pCD!LZ*jph>=?pn^+%gLo#H{;p@JX31A!2O%$*V`8!j zL|^xGbkpZxq}!0pKxQY2-EouhUdZW1cS-bhPYX8J?Q61yT3zn~D3T3K+ou6(HuM>X zE;^ylp{VEhKE0q`-zSVhkLyFnAL|@&`_X_C-N<3c=Z~XsiQ73BLZ{2|6A7E&>k;nf zZbh`)U<^qfW);}nQ}IySpI(>T)m^tD8S7qxy?-@zja`mIm@nzxr;c7o+@`KKBi%#< z`4Vmbzo57+lI~2%e9<;g3`y4HvGTr{f}ODs1hvRrE2_;9&%r*3b)S!NWpl6f26N@w z198B#SQ>l@g!2$M6Z?>Rk>;mRfDS$z4GTTrt*^_z@~9k!vO_O)i?hDH|AGdDUhLM1 zjfDM#I|9SPJyz%DIG~gd%*o60a(d(}%INIQclmGTeqt7lIZOo8^%;V6J>!`9 z62OSUwQt8n{YJP4WLqPR!P&G8D9yNNvQ*Sx3I16$22oRi0a|%bH&B`XL0#GwVNr&$ zMCf3L09ykr-Al8BFXcSHy{*CU&$AZ5{Kuck9I* zsG*Gk{$)i;gq5Oi2)8lNYJ_MT0~?Kyog#`uPHopB1d9Oz55brcFm#WJAUvFkKw!7c zlrTS7!u+;$3G;0UA?Mr6ZDw4jxJl2TdLlbXUIj*+)lSL4wkX7IOyevfOqJk5g8T`0 znqBFEL!e*|7!)wLOp+}iRAU!|0(Qt6qbIOSB2JT2JR;RQG$(*oHeBIS8z%<0ZrC#% zE}dk;9ITLY-obXz5T3=s<4_?yn<%dbob%=oIaEwfWIr){8<1VYFu-myU!*Ur23@ch z!o#p5?JT0HzX>K|%HF^XO4r}i%KB$W`lj_nQ-4z}ZzfAcf8HEot%Mr{d9y+JbBODW zK1@7O!spE)Zj^8XhsJIgJOY4$WHBqmi5no?@> zGHf$5jFhtV#IG4585z+%Y@+1%Z2aARn<`zO$)e=?E>pZjCLs-LYc_(`sXTMY_StAQXvuKOKIMIQjq80va^* z&G2p*jx^omc>D~n^J29Aph$c|#Lp-e!vxp6a{;p=^3malLG6Ac%fQ>F7eOPBXBlj9;>-sj9JQNo8%ts*1*<;w9DfjmL~yGG*3+nG4GIF}P&vg1Jk; z@I1Pzvbkx=fm5c)6svCmxwyKazKOK`>N+}FudhF*2A(YvuxU{o(4)4QmY7N%R}V<_8w?5-&6+lQq3t=ls({S9RVa2(%LjaE z`nRN-3NRI{$iSzg})YaF?d@giQgtOa$q)U`BKEf+&9 z3QY}Fl{M8h(3l!=ovN;_y3i@)(BuPjV6-#r{`K3$pQq^LgtJ@DX}aPWDD`6D$fQ z=j2D`Mk4dVlXH@x1(`YdlQZUK%*)B1^zUI`&;`fx0CuzC2`{jD!YoNEJo%d%l<}4_ zuzAAZNGm*HU<73{DAL>i#NGh34f*56F`#`x-*j=pQ;_SQ-j$7g!GQFN1H2@f^T**| zp-j9^;gc*mog8m+tjJ#=vL0f0A|eM8@pfpq>PIQ^-zU>eQkWDMI9E|PfQT2L&cNeUf41VKiq|RrO7TU-9g1|w z!+N6l8$%qcC>%b>3skOAyj<}H#a}7@R`E^6j}>D$1z0ZKauOFRRw|yPc%EXLB54>* zf4AZ<6*KVviTbXJ0~PmCoTj))u}ZN;k)LFk|GSEt6>nACruekt>xzF-j9`LG{fYw> z$0#1CxLC19F&iHtn2+CviGvl#Djuk~T(ME{WX1Cp?^gVk;_no9Dt@XMkD7XVDHba3 zuQ*HbNX0tE4T|R}UZHri;{A$GDZZ{)jB}pHHA!*3qO2hR{naYJrx?mK>GKr#QtYEx zqR2PbEO(;fRK}5uyJ`JZwBss8S%U!bohsvUC+To{3CeXF`Epe*P?T3>&<{{~h+>iAXvGPN zrHV5Y%M|79Aj)Z0nV+KA&JBvEE1s?RT}810L%JWTe3jz$iZ?0p^&ZP3_ldYo@e#$} zC_bb3vf^use^ca5k@@950L)UER3YlSD<%~!r=6eB7*B=~ai$`D^HSzVKjIOJ%M_~> z`MHhp-%{+zS-(>Cmb-p~%9gu+m&*4l%C||BXF2Q7s9x?v(7&d#+>ap3+BU#m`y=vwsfDDxexIA8G)#ifeEkw>~?RIXQCqqt6yA5&Q#87ag|73Dq+`5Ki;&|o}nNBFp% zKEEM~-k$%661n4bAYb(zuLna^KU`6sS5S|n$K$C@|MfWbe9-)cV~;MD4X31RgYnDp z!qCdbYjAM0>3EH1m}Ae4=^mDl`Qg}e;~3)h?37~XHZ^I=?}jkbaA$qfvD>l{6e_{} zxS!a~#!ZGISYBBYpFc4-SRUJA%bSm|&4ZwG4<;XNS?p%xmP28~jGKn}b(cN(K-^M< zgZ2JxpyRxabgY+pTW=G>!SeXoItiWKY+OAQ!Sen*)SN#okB4o`I~8G@2SKMV${WXk zZZ_^@$ieddhVte@$MW!(C{^CY2-`deI)|Y=p8s~Uao>R=SYFw%^thpmQsrHVF!OLe zaC-t3_QCU_-5AIH21T207dR?wY$Ahc)U2I zRQn!57>CyYknI|j7o5|qlN&KGJ)GYnT`830*z^B4>t*?@Gtga5&m^9^p|hJUuOr8P zIokJm9Q%g)wN;H=#TG34;(f-H6zx+~wD0F}?2C&Th3$(u_8*#tr8xElI2x?YFlW<^ zXGKHjdlxir{{hxg0LwnR&-5j4gcoo6B(i1Bj_>Vr`X|vdrtLUu+RlP0)938CVAQYP zaL!orMriq*9b3jv*>T2{gWmL`M|5{Do3mr{z8gOYPdoLKj4enrZRVTNDDsc_-5bvL zrtdgw`juJl6(G;pMboG5ICJWOhCdK=a`|H+fQ71;wR3u%dr~7rqUiPzjzYzgua)z z^w6b|8?iFPxlaE+(;xq%b5ALsPi3IOZg*TWvU$arXGbo8;N?d#kl^Kud3z{Ar>@}T zS0lG~5T-(CRsr*Yqt9nB??EP>(|x(9d_Jyt@~pU`Kwcq4BOfy+>Yols^Y!_++#{{j z8=f}}F&>@Ndqw$+877a-8<%&CWDGycqNRPkVo_R zNTY;(KE`B#$A2~=qT$F@UN1Bg?#Pkin(SRr#`-e+<2>pObF&bkET$)qKk}p4BFJ%% zWp4I2K@DbQi!1&>eD9&RTb&$vJmuQV);ez`mS*8Ke_^*-3FUdDzcAOUfen}4_3Xk6( zmGzMnL>~V+2xXpxpBN5SjtwVrCxi$1W5EqX-S42a{=PALe3Mw-cooC(Bx~DG#i%&t z_a~^B9e)=E`1`Av8|M?DKT*Z}_f-QWbl~xm2J(Nk#DZN1~>v>mL;T zGh1~B>peJ=VfH%O==fzZiXM6VTvEiJEe8fU6hD&5=c!B{|0*c{hSYM%;PKP&@;ui+ zGCBjTF#Ua07lv8-R<^7>!*oG7ejf{~h>`ONiffz=^OyBzXDN@L1!o?GXzp4=B+Tba z@c8+78TDJD=L6$=G4Gnr46`EKg&lvbtq8+Y1Vt{Hdn^50qgfF={DQ~t-_}JlkjL-e zZf62{{Qg#zqVYpmcACdelUBbykKg}U=W3}rH~tgWe3#}ei0{w5_e(F4$Nw3{ZM{gV z4}r)3Ad7ma*V7^ni1%P;KN|m7#36Co?D&txy5cq$>Th`b{^MGa;qm)V=m8iWzrS7U zoe<}`bN-W^dr02W_yH{Hsm^D_&O$jLGzZy&!_le<})}FuJN!pkLaZ? z!_aBu@o#0DU(K#SqEP?Eadx2pha8^4XS@#7NPD1*npOY%=h ze4hsj9>2MilqMpS!Q(gSrzXx|kAuf=;%6j!Fh6+w?@Ru&1pjpU;PIREa})gY?1RV8 z&LNL~Cewq*FODg&#skkQA3T1ZO2Xskze^uHex4)3<6lArc>HuiFFbw{p?&c9XQ0c3 z$3Kh;@c6q(3gPkdR4{||1R5L|BoWy-4AOe!i-gHo&v##ih7&Z9lqx%(bcAopK#e?bEMtM+f&#QL$Hy8EzhP0IGAVfc6j&7B?E2vG8#yC!0_Bc8{#TJ$ zo85i8e`3fd-8=CVlY+<3yBUjGN*O$UGmhcJx7bSX_?ehIe!g7w!QT^D^>X5@t+{&%}vxXJ$U>VNK+RlXdmZ;$8S!!m5JjR4<5gf8xjK<4<5gfTV<^f zA3XjssGnE##K~+Bc>L2v0Ukfsbn?ODXA6YKzlBW#kDo;dkN;J~_~7vy1$g}5V+!#2 zjRHLWVx|C(-zdQ2FQo!Jexm@7pBH%_JbqIPdHgLXgsqZ31&^OH8znM${FD!|GI{(y z)_6Dxio|O?1n~GNu+RBo-3O2V+aiO<&x;ZTDGEG(4h~NwmG^qv#~Ke0LeYa)9UnY? z4sMTW>`UMR(H@6=x@7(=5UxOrvLopS5zq?QgmULj1Z()CfI)0PEk`6zSqR^FS zTL0S-fh8T7j#ux4vD+mbSmgj@$-%BmI% z=dj>0CHBC9@4p8QJbCe{r3;iR&lw?AY%{O^oZ|;zjyi8+hkhLKeG?u)ls`Yv zBdD9<5%Vlj=DF&5GXP_pFax{itZ!~(V5t#W+Zf;l7%}VH7&s5R>ntH$Z1fFn4E#X! za|v5T5AHbwd{yr`4be6Ro-#sqn{8#lu{ol2yA%i#I)Uj72|b;If4e$tJ0OEcOkg^2 z%jc%k&$o$jNkKAp0(PS8Ha3btfNajo1331C(Z4ZG*8-XI+K$BmxA?qCk^&Kdj@cJj{I?7w11)dVw=-(HBIY`BW0Hn}=5rECTG z4LYKyT!cNtfhYSzF9^>-xJ=|l7lapI5MGLKgUE=7%&|Q&AoFN>WHvv;*9BxA+k*j_ z$Mi}-<^gfH`FUVGnqV6t%BDkMMc`8G%dxx8Ap|xqxd;#}(P~z@b(iIIc6~8}5-6u3qE!ND2o%oG#Q`jiY!_r=#G17YvW|9uX-h zj`ZF;5*rce-9H(L&WZGH#}ki%OWiw}j1-LCJJK73aFD$XfxLHyTf8?Ey$}u9*Jw?0 zmX@NAj}V{r-3|))h##ob^uCb-7C!=x>`}e^YPPj5z07}^bVxSpzb_8V^6U(h=Z-`V z96TWz!txkyJLaG;@6^S(^>&_S4y%vmwUy#E8$$?cK#7@zXfo)y@E*Ic`- zS{k{m_LwQ+K^lzCF{8;443PS49;LN+aM*20&gmM-3T;PH6#8HJGI#<;xuAHitZ!*l zUTAyI`j%F%q(~`}r5O%lfP&b(oFsAEu%uQMuc@Q>}3zX?nb6 zR~mkMz*n^Kr=9XfZn=$?`M#oJ)v5|%?jr|>4KA-_Y{!bl_VYb#)t#!&RlQ~T{mI-8h^_MrvF`B+n-ah#BJdb1s zHyJ9ws@hRjgRbd8bG4j&!+S*!rTE!s)Sg+ft14R8F2|S{0kF?(@#bf`cF2a+At125>_OAr%ysEWu)o94gD_d4A16D&{-LPhKVN*ll^5QYn z)Yext7gj8**?(n4<8mk}8Y@@sj~m>Yu~mhu_O5P77Oq&nwxY4Ruq0VHXH>GVx~{$u z9a~e0T(vb7O*M5Zpyc`l&0ysh!iIy`1ReeA2j%L9!pi!(=EjQ3=KV3*_5Qs87r4r* zkqa;tG2d${o2F|~O(S`m4c^h)$?b{R7zT8+Vf~xSar#`YtgYwOv~lz}2h+q{vRAcZ zjW_H=I~$&x9H;+38W@8WXuZP>`Q6L{rC+7^<7~2#*)juuc^vD_EGrhCG#h#Qi zF4U5lGhp(+Cil8?;246B-&A|}ixk{EzBvtSyK}Gc>Ljq?qgp^>c{v^A+zvAT@1?ih zx!C!_iQ#`P_BXlKyFFG8Fyq zUU8D*bj5{=hbgX5tW{j6c#`6|ir-PZT=6=^I~DIy{I%kqoPBc`9GxJa=|u|;u{;&&A{ zE8eQOP4Q{P*A@Sw7{NqmJzW(CD(<5=O>vQ8wc=XE(-kjKoPg7v<;_$S$3>7=sJvG3 zJBmM4yjk%ViaQmBSB?C_s|E_M8YsMKpzx}J!m9=fuNt@t=PuiEyy7{EKTy0u@m|GW zE554uo?;kpz@>i_D-`Kjhk9|H1-wJ$XBGS7vc`DfQv;`{OjkD4&rw{axKgoBu~||0 z)JT7(%9kqMrucIr#_|`6T;`Z|Al5hgvns!+_zDr_y{YnBitnple6}OM_1PZ9HIC`? zh|nh#2P^KaI9_q0A}%-5E=*@ZTp|T|^=5ndvWqCMaexC<9->&JI9l;=#iJCf6l)Y4 z71t6-Xi~dDu1l_ zcSYgOAU>PdO<-Tefr`TwixkBj5z}4R|r1Gtb9r?}T1QO|frSVTGKBw4`-~5*9<&!ec#Yz9idz-$QhZqPmx}z_!+Jkfba{V( zY{S*7YJ3F`s`U6u?`VY{K_edGtCR<CHKI;rj4<{er)c43@9^GMwLi zi%XK+zL@j-@Gz;ZBj@7$Q>IVD?pg%0$t3uZ?STM-V=K?$ZuAbE!`?&;UU+Q56r>1+BKJW8-*yHj zmDd7QcviuYj0s1cMvV6ma)jq}=K#a+bv^Tchxu0&oI+JJ@)m}{<5F1Rn(mza;NG5u z-cNIH4}#KL0aYZKHCD_rC<eXt4qg0B7O-#39v>+xvGFQ~JJ7WA+}M#(vg=HLAJv6nmQEsCtUSYX zL0BA5$0}kcNNhCDhQ*fkW@jlUmj!2j3qRbohDew;T;SyXf%7ib68#0lIREd*)^ui= z6)k5o*V>9OJVhuwmvduf?A9m;nw;F&ZCx}2Ik~ah?MxsiH?~!!XuOW?x+69PK;PQq z*!g#=XnbqOe%ARysW~@Z#l&}M-hw#)SH$j@ULq&=T#DOzy@2MClY29ZdZ<^#r#K)^ z@58Z29KD z=OaWkoZQ&6TGZ6|EDrh$nztV9&$BbY$rZzH_}1nhH^})$jwa~T8**A}f0@kI%~NQr@yOCnteoZQD*A2_)teq4etielj8(ray~|Aa(OmIqF*xs;S9)=~y1 z*QB4CAd5T(POgcck?@!woZJDDzbr9|-3U&uNk2Dn6J>C6**WCo(%o(hoZMeadlx5o zUct~IkEfDwa(~PUz{%w~BAndwr~oH-3~CTgZit5jPHrnkT{yXXc@+aEce11qPA*Rc zGf1BybzqQ0WaBVM*P%_3@GD4=56`1`iG~6LNvX2qNhiXlJWktmBA$X!h%ar2q*WuOaV?Vix5uk_gE)5xkdp_?lhiU;N%(w zIJxvZ9|I@XD8R|BWEOC8jRKt9lbHgXTvN+0!O7i>;@K+cQ*d%Avr!_0lS}zjE0dEO z11I+;C=yE%69Xrg0*8+aKE%Muy-#Fta(Pv!AVqAvtE=&;pF#Kk6 z4$enF$^v(GA&&r@TweLW$^C#m4o>b;5y8owhIl-W9gQk`zXPS=SzidAleE;Y_?$sB8j$!#d!P~gxy`3UCHv; znv;-y1NI>{Qd&d1j!Uq^b2nSVOdfxRVRsj0NlR`-{7c*Rv2QlXiJ>o z6-W|#+U@B|cfEw73m?Pagr0G;DU4WCQR{@Bb7PFgVAEH}aD*K1X_!O2$iN~T)5!XU zVya3wq7X_bl!{PMSxI3w(-y73s7AeK{TMr+lk+_)xZC0M1Y*g82M zl7(r*XOE$y)5>8C<9zA`r{(kAt&_9T`7y~yz_Qf1ULTx2GcTFNA`9C)Egzv2arNgu z60u~At5}pk30YZb_wB`C$p_*~Tz4kQlnrMbF3E;dUTebqhhsMvEjL{8P>4Znaxrt} z+A9`F;JnDlWx-h=Zew5^cIXKcB{-LG5Oz?&Lv0K!G(xzIfuoF&(N>KBTM?k-Legyl z5PWa~(-}T^ItSk%$d+M1nvM+Myc-2>o_K4SawBezV=-X_b}+aJCD=XZ1hR6z+M?(H~x><{nQa0S}O>e5qii0d@%DnJqIEM&Ro8e(1FT5ZO zayDDWM%j3VS&fx#mBBI*Z8mo@klhSIxvDViuH0MtiF(l>0Lz4Hb(_Ksu~8h}4Cmc0 zffvM>6V!4KBoDh(1djotZ0VRla?fQ_R=Zp2F5ASIU~*9edj#>ac`lPOCXl=*MBHJp zaf+LbQ!BUyWq$MUoP&@h^p&aH?Fq(4!ta#&#;TE)cKi+9yRZuEu_gZ`r{7Au!E4?< zxc#nN)da_za7aGFP`Z~_Rabxxn4)%L#-!QbcyLhmH$tf-2&dTJ8EN)6)XMk9vov`z zw1UONnqZuOca3-j;sv~szPNKhx9;RMPXI02>oNj(-y7e~X!w$~8#bsk68JygG50)NYTA3}{ybmYso5!Y{^LDx zD?J`(nDxV5+gP=tyk!p-57rXJm^`R;0*>EM=>G|Rxxewq{lDyy8?T`8m=WZJ^ZD0q ze9oPmQ?M~(Q{>d}Y2N8zgFBN(L0Q2^GRGZ?U}WsH!dXs6+@BQ-WoC2<=eu3qgje8p zclUC8;4Mw>P(S@2WlQDbc6tjt?|hb)_$(carEH$YZ5j`n;O5~uo!{}(Tl%@3x_@O3 zIQzFF2V8Dl?K$AMbnw3p{$b#+D94K&NFFn>tKt`N!1))A>8C5sQk<{2RIy62NwHP& zRK>FtFHyW&@jAt=iVrAmSNyHw4n^T4qCNa?%XW#6RbZaVeH8amoTNw&0MoBgJXP_0 z#cLG#t%d1+uK1WDy;xEIfno;#xj`PUc%UN52-H_8HY=W@c)sElihPyH^!F$}q4+z+ zKP&!CF&opE>BT1~P#l*54^sVMiYpZ_QoK^}r;3j#^6x6k>!e7>VwCC2i+Hdioxf17 zQRItl%C{)qulRdKx{hHyzseJH@K=S{OL4ejwPK6nCdKb6ZdSZiahu}PimxmFMKOX2 z&w9Qr7raW-wyioCK#jT2uDAw}R6Y4ouQJmsHzDVV(6(3L(&o+pERpoaTzb+U2 zGMw9N$MuSLD?YCHvf|r{E}Q&C7ART{c$3O> zlfrs7D4wr)vEmODuTM^!OKM4N=$jriUw_fr&(H}oYc zk5Sx@2>ndOg{ohyxKgoJ@i@f|iW`Z@f3C_GC|*j$T)aY&E0|KgRpaka{JH9Xq4=2U zpHO^3^)D;Frud%5f1t<jR3fEB1kodTvaQ%ZebP1GneL(SH#Wxk@K8JWR&Y14+ig?E(a!fH-F<-HlVqe9M9DMouiSqW-_^FCB6z3=| zP&`7hT#?@+*`5;=#g+=P+(&^wP`%~i|3qcEuOeRVtH58V{&B_MDDvYb%YR#uA2uob ziliA*?xM&~nv@4Cjv(UN%8#1VPg3N^OUiP82J(|7;pa%|+Z5$~ z4fz(8`N5I#Bxn(Fdysr~K0*||ov(*!x_s(${y`jeJn4PIVP{XL|04`W7`MFCQ~zj2 z1~yDD*@oknVU8O&rmK~Z`Qf;6n~L4$p?o>^WqLiLY~xB1#%0tYa+{IFIuIzF&)b+D za@}IP=3=*b5R|#_Ys?M1*|=p;*f8Us#KhvWq1|j8KehzxEkFlcj&!V-_3=1}tFhZW z2s$_7%UqHH-E7<{$iecq4o!2gaZ65>w-I5Rhed2hd7S%pvvDUv5iIZFKzY1|+xGFg zY4afHyn^zMz_Y5|Y#gt%!SbF%c|1NIFHWmec|Sy$d5W-e+b`ibJMCaYW*qnH6>U0_ z64pRxH=B;vZHDc3InvoY)bTjD@j4%D-z$OR?SeRaybmFa!)pM@wjJdK=c=uX7#MaZ z+{gJ+9QFZ8e1$ee%dahu{{sWv>b#Bik$Yk{n=Zg%9}5b5@(cY|m+UikOp@CdbJ&*_ zN^R{p>}N&azGcvM=gm`mXVBaa!$-{7vCn{!A8&kbN}WJfUy zr=bnO0c4Xxm52xrP3(iP=Vrt(UpzN@4$j{YDVN}{&tXg`Lf3#^$fsMh5T78xU$0?I zIC3>&Lf=OY@YngQ;Dvp%&b(-ZPH?@bUxgl4o;uWl-%@lphJgtgSHdHp`RcGZaOM!WBWA}*#sxRsh?bk)SqdUIeKVpnxk5@`sN~pC z_c(M7x#_pDZkmIGn{Enl;zKBoS1}wXg&y2=TRGj!f}3tDuVq{IS1~vKBE^X+=Epfm z;HI0z1#uF>z)d$|Ps632q+-(P(g~@Bn;u3TaTlWsZaTy4^+vQ9+;oa$GR7w`dbS)G zT-%SUQCWN_2Dc$RR}m$G!}@1wdf%+grJbQYY+Wd^uw4RBuz0o?ShoOj@+UkfpQF@C^JXP6aDV>8#ohqid>4spR8=uL-7sXF9dG-863xldhrHAZu(7Z^`r4FKE)yNWvuA2SfPk1Zn~)`#Z5N{ zkm9DBHcyB@&7z*{JWBGG#t)*sHyRx9P}5o&1LcHI7%;O?vmr38~+&_ z`BIn3NJMV>{!IL8_OVDrf6+(ti2jhnGnm|TzV84x-86&TbcUFKc@gcCn!JhuMTw7iSm34`f6k*5HSBzF(@p%i#A}qnO(!*#-1K)@ zKe*}UQc{}W9~*MhP5P;c9hk-BrknT~i61aOxao%bUM7Bg$xS!u=O*}~irjQ|4!P-> zl)+6GBYOCY=6OYKI!`6xrcY#n;HL8&5pFuoXUR<`ZC1GH&#(w^)0d*lgqwaN%K$f> zbXl*zaMO7zm_ed7Ltv0ZWaBVM-$9!q;fIkR-{lR16Eu*NDm$Ld#pyCo?V|JTDhm85i{n*^S_)--v@LxCf0BZh9M1B;;BGZaM{=;|Uu6kehCLFq~Mz z;|DigX9Q~Gfk(nDzMu@{3O9WRi~24HztrtQfkj=ztl*{_IV15?77cFtA!wa&(;4^} ziM82=n?4a!DN)X%z)k1fj77b~tl*}baSSKc^MJrjXJT^G-{Tm7o6g$=x#`ETYH-ud zQNUj`%L6z4Oet?}Vs9Y1>06|!ixV-X2RGfEa4Qq!?~|Ku10e z{s2>en{E`~rhmxk4{o|qfSW#x#|>_}spXg8rk{gC*edB$aMLNXQ6htzPPxv?mYaSF z6p8&=J-F!<*yq1wpMjhHW0Ap4=S7i%6a{WN2Ztw;%7&Z%5)?gn)gd>XgWDs-o&YzU zwVL{O*-YT3UxlRLrc3f=ZnuiuOt12u9v4fZQ97JZq(IMx;tgc8n z_-g zos+R^sHe-p@s>b4vSHp>P%%SU6pDl~Ul58h8dLCBfD!!c;%x(C{(k5@c9LPtZ}W?( zF^u_b{sAhCV&Yj8iWg!wcn|s66r2%n;gG$}wj2(rDQB}O$E3bmQE*2F9iuMxr;#G8dkCukX+k%!b1Fj&53 zQyO$M;R*>FrI11$Q&-_yXeLR})Mxc|X6B8=Y|hSWmp&d$PuJo(tPl@dgODCGT8Qu@ zS!?;Q$Vj{GX8JBEs=TJi>*@?fGxNK;BzCjzt`RBg8&W+6Qazmy+5;(`UG>GJ`c%e6 z8EG#5-dXME1M^&k_ZR-%WMQwWd7f-JpLd1Wd7%M zL*_mi-W4L{M-my{i>)r)wd0}8%@}FP|65iYbAjzS%#@$f|3vjWJLu0<{hvGN+g8Is zA;YT_8-czf_TUfxA7CTUmpw5&O^^5^(>S)Sf9h{REZ(KdA z|8SCpg^ddwC#-*@5SQ*>*9yQoDE}uK0|?=nMgWHSEH156^#9Lg^W)!3OO^8<;?la@ zc#>YQc;V#YF}p8N09%!`7yW<>bLmR>qA#Z#Z3n5a%)#19yUan#TYdTbIrHgv9A+ZdAEHjYyHE*1!Tc7CmtTjspbXa@AINK-N z-WaER84mwfF%jXFUgnwc>AeTefAEW`;r*x1FuK_PYW)8Njg=;c^h+wL-c;Ke=^wh6Q7+?tz;}<{W_&v2Q z!|p}^@KT>_XXW#6PyQF{F&K}TRRQ*}OvCE2oaNPZ&Br!W$%+o}wr|%}FpDLW*U72| z?R@Tk?kWV;wG}IxaIuDoU}Y=JiOd27G^)~TS6~?rS$@EnAB}AtE!IakpI~r?5nNSK zi@}Abf7bmk<13!e+;-!0@Z_A_jp0q+siD){6`2n`xb1-)XA<6W{7c#g@EJe7rT-65 z_pfLlfHwp9(_{W`bhHoPb*sI3z}T;B8!!xIhwv(HoZS9M z4T`5Ko}>7E#mg11Q{1ZffZ}fy$yZ^0Zz#T{_=%#A&S1Q7B7s9y7LFt2qg1X_6mBE* z=c)WX#j6y5s>tv4ESF!$iMtg0;g2Kbk%|))XDRZ1Gvkj@T&H-3qWJSg{M9PouDDI{ zDaAi1zON{YRU%)1{I_KJe78%Sq&QcRD|l0Xw&M2{Z&Lh|;s=UdG3A+lfZ`~{$%^w7 zmnvSWxJB_1#pe|Ns7U{cEH}c>8NhtS*@{Ohu2MW+Q3yClf0@eHE8ea6E5+X_?o|9# zF^)HLtdHN2h=q##E6!3pQgM|c-B~gHxr&!7^7B9S3;C%JSfN<2xIyt;#p@LBRD4wN z1;q$nsj!@`iUSq*QJki@NU=(>MRAkjcNI4)-lq7F;&X~`D1NM%h3{glzo%lM;<1Wn zC_bP_?@>(umg0VRy+rvS#Um80ZNLhZt!==GDxa!&w&DefKUBO$@jk`hE51R**zQ!M zMcWAn*d;q#)~Zg@;7Sy8pRD7e~O~m0wCW7 z8ZR~hkgwMGEsD1&ZdJTbahu|!MC5y1@mbZssQ6#1e^c=-#ZNT;GsP&zPWnl)t73OW z`etH1{S-$Mu~#Zyrnp7%F~#QD)vwm+db4XNabOQqZF;}!bFuPD;}gcTan+T*nLp zi3?08?mK~WPe}Pv#UCkNt$2f?JP#lpKYBC0T~B}?yeYq=$dBEW-&2$i-H@Zae*^hR zo7hWn01@{De$=LZtRg>PQ!Z2FH*CtX?hKG0tSKL>C^ig`&r_M7uNl8tk)Nq4->JwC z)Re^r5%`MA^1K0=-=Z1+ks?1lQ_fN3M`p_M90KI0Wy<3eal8C)Z6k0SlJxfc=y+Zv zHQt^dMJkV0T&(TlJNSQ?ZN=Dsd(#T12l@k3ubqtp#MFjvldUg)nGVAx8~Zi5F^=0{ z>>R5vN;e#7I@Y@cI=k_D$ZZOCTQ+50kNEZ7ZZ?kpH*kA#N;Ts0zMzNVJR#>F(@Z{p zvRx#8+B^t47oe;c>_G)*Bsa2p6oE_3=1}4cLSA-hzpk zgwAd@t`>@5dAaDQT8w)a8o7|sTOY{QdZ&bDGH(k0RGZpeix zA@#C+))|-{&WU}I4m!Ibi)_pjOm{lk_l(97Y`XND!s<~aUuJ!PqS52VCAodEZN<2O zQeivWilST2iN3rud3bWW^G>ceeENc&;iL0*dg~VK46V!C=^kCZ>#Cy%@AB8J*|quT z6}zrpH+I*cb%Sdbi;xG^hJwrVIOpjEP2eP>T8|1JdgO@Yd_Sj}pA1{4z-peu%0| z@DuLW{d-VF!k6PWVM=g=f{wk+c)0#|OI*#~-g^IL-$^e?JwY@s+rC_!Csjj=zcm{QXtTjo(di zqKf%(SwG}lS&z1ud8;V&>K2PP1AVG7|{Sv9=kYPjdCc@{r{*loFw8HfFQC%2j>6f!*dRQJSF8hQhzCi)Nq=g@3!93ACZ`x2hD4PiMRCh>b-Nw4pcv zjq>kQ(b!P`0H=$wGKl<8wx&k`VaNmEaCuJ zq`-eP{-}sU;xjpLkHuaW(b!PFvYnzt;@{{;SvnODj2&W-cx>A%$FV{{sAD6V0fU(F^9m^Kva zaNPbMa(D*QhTN^GVK8wyzf5dQs1H1%OaVdBRnu4g=KD1I*aCnU~dJZvb;rKB|R z7uF9O3X^_nqLMuh8wwLYBf$kMeb`XQ3#0yJiGj=y8w!(tZh|jdeb`X2b7(_R%=ECK zSS|G}PVl_)VMD=FNo*);sDKRx&k?bqD5C;46we@s*ig`B&4&#IjTgNBuS61iQ2`r@ zS0#nmQ1DbRgVcrw2L?$*HV%VC1B6KUL?p;}Z-#~wG?0`kJDyu45%Y1{rV}AQO@GC| zKWCww%(#5;yv#!T^or>(um>vu# z4rf-_Q0R<6jXZFW+woh#XQ3P){{4T*qF!cF*icYlQNuaeU_)W#jKpb_VM8$yxx|Ko zft!(7o85i8e`3i0D;}&8zhhF^Q1EWXqQ+5%4TTxUaN-1x3T!Btm^KvSaqvEDD0rI? z|Na~k*ie|Gn2|VzO@j?ZwUjqEF_-CKLs2PBU7Yw9<6%Q#PPml`QY?MgP#C!(!582@ zY$%M}nkc{t=EH^}L&h976pd^UY$&>k0yY#}M#zT^1zR9C6yIl)U_-$o#D?NGi1A@V zVHB{TIFl)0LtzxKq1c-#U_)UPu%Q@F1#Bpc0yY%9KKihsFtyNzVj2oztE5k1LqVC1 z5*aoWlm}UvHWWVm`_F?S@gxrcHWU=t=bdZhl(35zo5?x&E&|d3*gAOZbJ$Su$_E>Yn<>JEf`8q>J;gH`ng##oVM9SXD%emA#N>!w;&#r3*y%9*M8f8m zHWqzd8uPmK87#&*n?Kmxeg)`Vx1sB5Bq@ag5A06AZ7A1W-Q_rhAIAOw_Wt}E={9yf z2I*iQaT8Q-v!vi7+8fx7eMCzhtE5kijo8ILVvVRWk^fz(`y2P}_+0sK%tXfoY3Im2 zgU$n*yghH)%Xl5vB1s+i)omf9VXGV_8JtjR;g?!gTDO)9gwkS-w)d8RV-a z)Jj;2T`1mca|3qh32ZfU6pu(902$xV%7zP2Y70py7rz+}mw+=ZVsD0=^A0AmGZCI; zI~C#C>{GT8;Wk_v#HgNBhsv& zj5MqZ;o3uhhfDapImBuSHwYfBdg2f^t5( z({uRD_tjmTe?3ZYdnz!vfVC~48n3FTTv=0B^)>0ndoKImm&RF`{XI}Brw0Y806;G5yg?%-iRv7i*(B9y2mgW#;e_= z*NI-qkvhYx6TWe`J^Li@1O{}>TQ}nK+>(E(cvDr%OF6!Vz(0A=18!3d*kdUd+EuHn z8dp@+RUT^zejV72Yb%>T!G!l=X|E;LT@^UM>gz6DKF zGUgse$xvL4b7eNguygl7R4lK+V%IgzMeTgrxA($s>DnZcI_2t)T0J&%xY1n8Ph8tr z)68+eV2O8WX_@WVI;^T)?KI4ngEWaqcGVU@(X_knbkd7bJWGg*Y4YJF;(12ueDwna$FHC4;)nNU+#U5{C$d|AU7RRSj_ZVS20rWXTqr>Y8_ z8l>u0<8&jV)T|p2pkI?GZK%)eUS4xCS&u2Ntzdtt*ZC9=^(&B=&6T~pVmYRzB~`De zYF>`%!bU(@y&P6GtIF5l(o(}=+?`+?AU@mFhG5)|^lF^@W0Z{bft39>+^rkehG#{>ZrM|FL%_@Ksdj z`=7aUZ*miILm+`0RxgB2C77^A1!P|o1X+|S5<^HN3P~hkEy|+cQWxrOYmH0Qx>T*T zR{goPYHM9utV?aR)}<~jVzpW;TI>IL-t(S2CqO{0R{S^f$=v6>=bSm)ESWp=z3<`a z@fFd)Iry*Ml8&{#cbS6gB38t3Iy!yy_O!4^^{psB^nQ)mf^Qs_Rtg z_K5kKRBuwfNA)q)4157#KDZQdDWsu!qUt@;zyhg6?deO2`z zsxf@!kor~m)R6X2)rqQeRBKdo_(&T0I;r+m9i}=_b%E*<)%B|9s@|jexauEOx2k@u zn!wj@)+c_#p~Y&CP@SrJv}&#D8r4mzSE$~q`hef+Ms$m73(=vl=B_6#g90`S7|)m z;V|E=sz25Ehg3If{8OrbR((VDpQ^$TBg}>Ez+u~rP2+y)iYGjR=q$~o`oadm1zE$-u)q7Qcq56pGZ&jaBwan(rYV(0T>&sQ`sM=Xoe)EC! zK57q8mFqp?4^VrgDjg89yn|J@_e(ub<1N#9oZ18gxZN_#ekdaf!iTX?Br z9$s>LE>wFw57vCVuZgq`k7sW{!^*{t74xC^)*-skhVZSj(HnrT3l-jg`3();07eXG zemC3dk6MOW?!6f5ixs;8_lRcU16+5(;U-Ied@{`a#)bKK?`9Y7H!i%s*llRvPrD66 zX0d6bVB%8kQMnw03soHZpZ9S*99SOPH65$n20`yqV)1JV+-<3Pb zHxFrUy$gGwjmXD(S)Z-<1ccr48gOAvA|)E~_X{`QF=!wE zC)vg3lZVDNwdMFFGTl+{-XC@8z_P(9F1u$YXZ4fXnlY2be|dZCDHHs6J{ej5*URE_ zKZqVOZnM|Bpk%)Z)Bbu|*7OhZ7Tq@H;rj+pnEpY|qKEIR>uRkyteasydtV=FJP@nA5$7oN!367Smm?ZE4>`S}mL=~s`r`@a4Y+IIHK60oDw zZyfXBeQi7UpWye4!H(x$f%N4QawZfUv)3{Ayz%zQ6DPa~zt)H2Ts8Y5>Jzrg>4v>| zz8yJ7!BYMKCq1yid6Y;@?&2ev{GnV>j*OA1g@;k1G2Yh)iO+4?5!T2V=>K z1Ky5+v1B;2A5zI!u7x3tCEgHtS%XkL7|Ul6nY9rmg0W=0p=vrH)Q0($u_StxU?dnz zJO&{+k>EErFqW@~3C5BHBp6HP3ie_6<}TMDjf^GvMhq6eTeW34_!iQ^SaLw}-oOVL z%jb|FE}X$wGK@Nuu{1SC6VIcWU@VOpPplHNz?eCS6R`~#OJiEb@+B#VjO9{i!r-kg?={{RDr80>;u5;3bM^9-wA4(T3)MYQ_`)#ui{KZROk8p%H54B`#;v zMygqmcpF{JJV?#L1YPoiu{7IuO+3eKN2>|O5_b=VvE=Vm6TijY17pcBM|~{KDOofF z`l;qWI53v%80<)b-?PA28k>yeY^3mqC(>mwmQ&C)VJu5ftr_om?HOk2kFsUu8Kz~? z#B*$SMV7%6jh|{TmK-c)ELm{&1Z>PzYXI^E1B~VAXet>?Qhtf0_yA+cFe@TG0>)A+ z!tUX|)rDo%&8jPjcwlMJ`yZC^N z5*bTIgRwjp%_C#kk^AwN-R=>yS7J3={Yc_vG5aM*P=m4jSj;qIX(~!HmZk$~#?sU~ zJaHb2da_->uct+$67+lz#xh^bG-GLs8kcyB&G>`1c}jx6s{&(rFWMR@nx0t8)EC;f z$8eLe$vWDe?u{0g>l813Hz*sJoE<}@$G98SivE#}0>>(ISW9KCK1%iyF**-7% z1KMCLZ^C~%GM04VO2*Qpmn0uS^<*p!135U!BaV!vNiR#%DJ&UFLR9oq{UPfIV`(lW zqmmO@J{U`re_Zkz9J*vIP5LD9M@+_2Cg=iV`4mSLjHSsxJ$X3m2V=>>A!A95ij1Xv zp@*Mpo>ycnc`6BG*@F!NW65(w7)w4v>CBKD}u{052EU#b=FqS3)j3u9YlCd-q zU@YHe4ltIc7BZGcqY$=A#uSVtZ8l15FqX7OTH7*~HHb)-v3f9;G&tsGaLmA1$`9a+ zz*zF4NJEMOW4RVR;)$fTVJvS#L>FFl$XIgccKId83XCOdHTBiMbDxq;X1engS69Ex0EEdPmoS?Boq zry@^VLX)wm`8)~X9{w;^H!uU6ng>!;e7#L}c6-^9GF~(|v9p}No#*_snzP^cp<0O7A zWtGIQjy5rHhB4wz4DcyN;H}PSx(op}8Fk}xyM@n`0ZLMsFTf;!&IbHWW)~mlmt9Sq z-xJy&EBv!k*crfs_0$7QG-afTZlsPg(G>O+xmQpRm*`oPc_w-_m3>8)MYT}V(AgCB z3~k1zS=cJmHv4H*v^ZJb(scdos{AmNR(gvB-L` zWF5}*J|J5&f}{N5s4&>u1y_r9tSnDzAH^+}_$h3?^E@oKm&t@ssap;`2KPg+B`(P5 z5o?1Y{T}Gz&1(ika1rv;tk@UrL${`OK@}KOdh#?Fl)>YOY&HT^BT!kfz^k8ZvNhv2 zKPMHNMlUUpC)lUuPc7U@8f)jibOnu6j@7__3ORBU9KX$}KSNBW$=@^{8ZxtK2vS(b ziiXM%{3=(T(eQN!ceEIu!n=yNrjbksEoOUK{pA*82pT~*Hl&KHtLuv^>uMX9R8%&O zz`%LNU+(s_HIBUy6?HhxPw6Iik8+TkrdrKm6VjM2HH+hjW2n6x_|8*;X1FefciJol`n+9*G0sQ4Ro!bdioNeM_Y&yH{*2;$!id3 zm$7vSUd88|GsMlAQA<24_1+BEH)!+D81r5E!NsmUykb#vvQ@5lyMU=JZvLs=;qtP* z=Xk))!JVheyr!HxQQnA-$?bYd=7x-ou~Va`1*b>O=Kb)V$i238+U?$4GkQaX#GRQaut`9`ZwP~|r? z#`B>P^;lJYZKb_b^<>r4RQc_R>1;psTGcyMg>OatqiPGU1$(R7+f?_$AaMHus={Bv zK3MHzRO$YL`If1kta`cX&8ospA>ZHC{zO%HD8!4;I%xlhDepj4;hPZu4Ye1lE?4E# zIM#oG>i1P|Q+-hNRaLsCVEzccz){<&rc|e?a#BgAAFsMj^$yivs?zZe^U)U&HNf{r zYJ1flswJv?aLDv;s$Qb{1J$3Z{zCO>RX!%?cHQwXl3J`fLUpR@(W;A8PgFfi^?Ry6 zRJ}*_an(PnZdLtQHGu=2_41*q)UP^1^-xt#i^=qQ)pe@9@PL`|rK$(1PE##cU9EbC z>UUJHSAAObRn>o}#&8a@{0^$URfnjKSDmd|rMgsgqv}PfKTy3>^%2$QRNqwnSamX< zqO<;QsGhHSh3b8(ZL&>1;aib^U$upAg*{Ad>-%=P+J~#oRjpKAqWW#sOQ_gq-&5se zisbKa(Dd8YzDxB!jekV#U#oJ4NA}11$o-qzA8Pu)RdaD|WBKh>lT>WiQ|&&g`)d49 zwGU7|NaGJy`%qO}hMMt(a(zX=@-)6ob-3zS)rqQys`4=q$3uQ602Mj~x=`a6smk>f z@hjC{t9pv+S*qVwy;${9)vHynQ@vI7c2&9VqWlNcepdB))mKzsSAARcJypJ;U_a!= z3$&No{Zz?JF@3P=fvSA3$auc~r5>U>L-lagd8+eO2~aTqVpXCEv{$OGQ{A9?rs^iu zpQ%2iiWh3K{btqQsmkkTl>3U>@;eCFZ>cT+FJNy|`(xD@uj7c%QYB+ZyFj&z>RzgS zRrgi3T4?_;$i|6d`#vnt=#)9$U>UscE$ z#Pf|7(*?j_tgYHWy*H-UUVQPmFx5m-Vq9)H6msy1exW+iei^-bH!LXBV4x5+dC4W;x~Yf1qt2@AK_8EF-`d7a~Y@ zv1ywS;g+`m<*|QkABHGh-sK2$n-Z*CW+B5RJV|w78rK_CZN9BIAo)JXE;ipCh+x<* z3%WKxR_*a}8#1`$+oD&6PIj@?35>t3s3xTj^T;#-qxHazI$7w8Bcuo zwrI!`uWgAZ?tq<=GaLhUqceCm*qkR0 zJF~_@=(F`1?wY&QO#5s#Y;InH{{S7H_yd|DPyB6~Ax}JkyQW2+nD>tV6`q*CKyY|s zKAUoQVu9U4p1313hdl9V?9rFN6R%^r4o|$CgW>SRuP}WVJn@_Cgu@g6n)YYli5Iax zhbJaY=kmnuS)Ria^NXR&6aNdBFPA44;?m)XU*fLc1y3wLZg6;Fo>$FyVtUkX#uE=< z#4dT_^(N3B;fc%H|CV^-D(s$?dEy(m=}vg!gK?0F&sGLL zA5Y9T5iUwQdm7d zCGQoyZltyyp12s*WS!9>Ph5^-cFq$Y&y?+WV*dDLd!CrT+6Z~#i`bOU%o7j5dAvPO zypnZo#}j{(rML3L`5nBz_~u(cx_5Fu`Q8pOZ!+X-?DUnr==t^FiC4Ki@oJYRKB)zs zcts05am3|`qiH-8JaI;v$^38e#4GsxVn-r(6(38D<9XK%!(BZEQHM*k%M+h84^a!S zf+t>93q4!1d`Ud9GqnU!lomQNM{>0C#Mo^mO&AMVa9zh<=O>>!b;sJu z6W6x-xHY7*dj9oV;)(IhuazhM|A#03^thqy`0_>btBw0z<4RVEo=ziMspI;kBdY6{4K8k|FJ4eOG*!GaUc7I0eX97_1SZJ{r)EX6GulTB{0@FHDD*q|o&7F;SHF9t zr`$&4<~hB%5mE1*Ptpkp;1{m03EO>h%XB{Q36}t`#Qy)`iRIqG<%vs&psT{g-~~P3 z^^>FH`)4ZO*Hb%D+qBFRmubEUs#8^GseVKCSXF*)Ww}dLPgdn?4#tx+pkAqZt?Hes z!nGm&QMFrnVl!ST9J(C0R-V|5Ln}{g#-WubHsjFB6Js3kB7iT*sTZqWs(Q8Rb*i_j zw(`Vgyjpo;GY+jhu^ET2fG5WNS}RYC%aSbiP9AtBtJ@_Xcy^;Qj%gXpyVj09^3vl)Z@ytU}k#fXHBe@JGTu3Qs zzc<6=9F-#u;?aDTwiiB{bHquM??>9Zt zI-mvOqR;h9Oft{mi2qD8^h+FhmIWHW#F4%XH|K~kK=0$Ri*Uq|(~xdC;ula~nj?N3 zg|^5M--~8C9PwN+(;V?CZu%KH;@_i)G)H_33kW&l6wQz$78W?Nf~?>T;n+t76U5`RS7@k=}t2f;4=5)VL2LylO+ zJLHHTX3Ijq#80r@pW83-8Z<5KmzclLa{LlU*-Y0jF^{^uC8+*$aKtm%%#b7IPp4bv zh$l01=$H5znjuHbpW`?jabND%kRx8sR)>CxhqI#3>6iFy78Uv>-iv07eu+1;8KGa| z3%Hj;zr^#I8gj%h&>u|*6v|Wz)XH0iE;uBf1 zb%@k@L^4|K;b@mSX9aK!i0cKi~*&H5dVcpS@j{1VIj^p0QR z72Mw8h;QdGIvg>75bydW{t?q1j+p0FGmf}B3v~Sw#~9&q#QcqXGrz<~u#B&kBj$PN z`X#3A`Xye&VYD3aMsy(bODxwCha;xbcb6j`%Ko>+5f4YXAxC@^cfRA7cs)0DIN~WB zIrt_16dW-p%5wb@bK))6FEIgTmm?Nr)bUF^n^ij;aRtlUgU!s_{{jVKU)i62Ik!x6uaO|v%m?N3FXo%kib47n{wd@0Mp zV*C=1LIwVyJo+UbipUh!o^LU?@k{(NY~EKDeGk?8L-N!wF<-uf9C0DXt1Op3hzr>| ztm>DzBjfmMmCLa9dY^R}zr?5Gs9A}%*P#+8eu+6l!v~DxD<9>Ed2`th>#qG0H+M!H zgl>vk{SvF^;Qt-J#5}y=qqq=amKOaIlbdYjm3SU0N^-Vwc#vJ{^(^w!D6x%+q?R$nb(pX_Vk> z%1I`ca*BzinEuS7nBZXu$r8b*GweRQ(pln;pmfI?!>%6KTXui7ns7|aAS=YNM_Gnd z91}BOYMxHv@t}^0?V&-(#E6w8^hV5@$o_JVoQoB{h{NWx+p?gkNb)~5EzHuy`>)Q|##m8x1iziPpPss(e)QUgm$%Zg7J z49@Pjx+QZl?fBedD=X(BQ*muwZPi!pad_CC4+sxS(c>`P`v$oPiqGFt^)38`dmJ7R zWWg13hEJctJNG7xgfGG4FsIf0@|_Lu@#rtez%n6z;hDA7({N>Faar+vu*{VUQ%kCr z)il7HZ))JsVI{)`9}RG~5^Qf}-4aYrTD*8L?8b#l7tbf*+sgdb)YgCkhvQUwr9QS| z@#2bdx_d>)3;j@)Mg`=Cs6r)8=KsZLOxsya)xl?OKC)#_i^j6L(Q+EuleYCqNeR0pXZpgK}@yy|4t>8i6- zk5VmHtyVowm2Y&|p0iZXSG`#ED%ERMZ&kfr^&ZuqsXn6mYt^S!f3Nyy)i+f6_K5Y1 zpM2={{)0Q6TtLBeXMLz#|Z!g>@8GE|0+%>&|=u z^WN1hZ=W38KjXNti%l!vF5hq*FEu#M>|*mBg$TFaUPVB#kZ*f-mv1)gHZ0?6+`y+8 z(8Z=52iq<0wm#-~W_fsVn`VL6A#Arn(0d5wyY+pvhI zQ6A@@w~I|X2N7<0Pocax;@CcZhvI&t&6gtFrUWaO9>{P$Pf%T$#`Stto9`zr_yYc^ z=7Y%6ziU`FBkb|Q|8;Kro_G4o*Fm;@4Ni}D6r18VzAbq)`26Y`}H*%9#= zA}NpK&N`jp@@~QLhpg$vmd9<}d~c$CPo;B(_1YhYR}UKaDSZK#mKpEByJvUb+zGo2 zYIpeCKgpa>{?|)$|M{lB>X^-5uY!`^6Q=$3?2Npv(N*ug^~+W7yp{Li!}q=Y*2GnL zTLX!C_`a&HZfrzjuWlCWYwW8M8+|7leNam2J>i-$-aC2Tub;@=lAG-McHs5ce9=~K z)opLRE_IEQT#3$pSqH?MQdpbW8u9(I5Fgntf7OJaql|9HynWBo2~WLVhTplG{TKE5 ze>`U<{t=wv47d%#fAC{SiuiHPxelMfr8rdJGx$%mqOno1g8dkt)`>6hBGJr0F+)7o zfZYk7!MvFXeFhIlmf!<^loZHqUObx15<24peD8OV5{q7r&kUIzJBZ`d0N*>FTl|WN zOC+563G$QgZA4r=8oMUoJz3U4s1khdy$n|(2l!sbo0;c7MxYJzE8p824NJ7a2l(E_ zh>jF_3C@rJzE^&5TNL%gTQc}wZW`>v!f)9TNwJTrY zWe#d1w`)ZO7%1KtW^;h)4p{nzy6Je3d~YpUmiRFX*gwnmk9VfvdyN@Q@I5^I1RFD+ z;C%`BUSsAYVr<$7HS-cD(j2K~LE<%Z5qz)7T$s3%-?BI;}Vau z8Gq1irz9@sUV1M38tL!!#L-NBq5X%DNYShWnRW2JrN|U1nv0ff$`WcG3>;)OzQY7LWb|<=p=b_L%!D>D_-(w4hH-L zAB~&mNKrKTGp2*@HFiAN$cn-D8apRR50>P6&Gvc8AJ7Khdm;V{Mv4lOdow@yUXxyu zyqgC)_}&{OeQjU3w(#w)RrwzXMUP&LGe4F)y?=_c_QAtibL%!GKAD4Uvhc5jD zoAgP^Q@K6(-Uns-DM{gX!S|Z{)03T8|LRDVOk`6uD|sV_8GP>vl7CK8JcVBs$>*sQ z6g?bC_F#eFdwGroMUO?2aYlgeeFj?uMbF2Qm$1kmM)C?VWI@r3vE&Sv3BLDb$?;|k zO4QhXDG z?==xO`pIY5De%1};x<3|L-qoEuZg(ZPd>+H!cVY?c+gM&i#fpenp*I)=Irq(gsqY> z?PP2=O6*Ky_px@;>-2W!C6Ua-5Roin_27GHaLiY8%)s|nh`qwg=2e}B6xGek=FZ`X zq;}`GGf#>Hyb^TbRfl{pcW#&ObF9GkvQ|_7HFl#yFQXE*fbV5gSD%*wIl6Ix-HLE5 z$`ie-&y&xd3(rgZBlyhbG5B``qygY?`?Ck&dwJ#a{cgvxV(`5nw_rx1(R`#w;!z(} zc0Ub~F@J9~iF_|7Oxuf77_3P(p_g6?tLLXq=LTN4#}Gxnw>xtAer6}cW?ka9%Y)hW z8~BJt&1W^jJ^Vq)?O&ULOlATbsy_sGqdgB~yMEAt9BvsRQ&@}s&fM3v7k9mf;W&YH zeTUigg7XC!ySBw*~_eYYC_X-7A(GzCz{C0lt-265{ZkOEI8SVTTeje(MgeY&& z9P(`?d;cfMUK|5B8%~tBiqD#G0go100{CMx3rzgjk&7nfLBUs2_{A7VB!$n$fm${; zF)-a2E1DRnHpXg!GkMv>#+3CYzP^cp(!CZ+Wzdfjf*5Z(`svW8^eFg#eq3 zy76fjw$QF#3b6yRM!ZdjQrRppwe{3V8c$^l5#LCir}0#_8u2TrY#_@y6UsI)3^9ut z7d}Epf_yryU}PTF6jp3CjoMPHOba(n+f@rqYd1~XRcqy+Eb1cjdcM|6z0`ycrQWFV z)Y~+k`iRC;ZBL&<*c>05rXeUx1Vf)5YZ(FdvMW|_*c`5nSYzI54@@qDtP{JPav4@( zav5Nqh^KG|E0fEhX-R2Q*pd=ww{s84g3CSz)-G%Saa|4}yAN=hjbRxG+M?iBI_%TV zy#Ct0uqYN;E87dy%u)ldadi^|EE`5N-7s!|I9W_v7{tX|7Y?Jlxc2e5U&4BM_+*Z^hk$pQ5&24+ zk;yp|5f!vS+cSa{K5NGq5M2&3_KUTF`aRJ5o7SXom2Sm;0p9JL_Z45Yg9ch681SW6 zUbDD<>5{7Q`o<+*d2Q8-#_CpYzyE{euk$JcN6+%gg*Y(k<~MloyIV(~x4dCN4dCA| zfdc;W&|jPbt;8=JcMD3rsIKyO?9FA3^Osh8Y0trx@L7$WyA+hPxhx!8)d;WCRpt0) zgI8X$U;+0$xA@fHula9Te(a*9JZcp8URJe)tUU`e3Gjd2Sa*E+q6$I8=Qq|Zue9hl z8VYB;+O-eFW-lROL(izxIK~gZI5K zwG$OjlzLNh%b0uErlH*X z)P7p^CDlxHn(gYS+DCPu>Lk?}s`FHjSH-I?+5RHcYgGTB$~U1bU)V0F%n1)I;1?>W ze6fNKR9ohDhb=4?RM;zMou;3tdZy~7syC|2-0R5CXSgi?uc~~%N}DelsKZppsm@d- zgTnO7Rc}^(T=jX?Evg@?X5kR$c7>|5RQdXt@#|DKsWz$Jq|4@zL0GIkzd#esrov6x3{>)dSn!`u^ zusf;tRUM`}QFVdp64mvp=c?YL`nc*JRkx~steU_%$ojge7ORd>ovM1YYOU%T)lI5b zsNSmjfa+7Kud0^fK{)Fht-4zEbk%EB-&KudoBa8zomKZz9jIESI#P9<>LIE}s;*RB zN5#I{ph|BR5!88}reCJ^m8#cj{7+OLP<=x6c`CMlQT1)r_f)r0(eEg(Y0MW_O;8bE zsCHM?9va_Y?Gja7cA7DRxHO8*XFKdqnd)%Wv8oeQ`GAl4W~j<_5;kACGJc`zB2_-z zXZ%XlwW_D6o~8P2)r(axRlQpEI@McMZ&#J;D$0LA?Uz+wQ+-SI@2VfF{#%tVFxb9q zRXU2JE!SgcceQ(}?xQ+Db*QRkf%$%d+t;gFmUp$iwz@sy?R57oKd#v#QUlTK4x1wcl2KPxW7_e0s?3d@t4h zswJv?H^XucS3O#_LUoa9z3Ot+Z>pZ6dYbAvs^_U*rh297^{O|iTGsb2wfSC%?fISR zpHyE_mH$^re@pFusLKB@#N*~kwvVa`e}ed)YLhNv`GiiWLsa)y9iuuyReawgpZx!W z;xfKV##jDNBVPgYp5V zA#aak)h;&e7)01G(~iV3Q)xTpq|HUxt#^2lxd&st90&G;N(jj6FOy1dH~W_cx8xy(g|Z`qvuld;Chp?i1^$=Oe@4CmTt&8d$9^QkAJV0y9TaT_;Z0owO;I#<|7c{o;8QCoh(pi+Xqr9*}eEE!T#vVTb`g+DCj zv$UjS=ukN4EiD;ZQYP`c=X_7=EfvO0fBWG(Um<+-elV^4uitKS#)OR%I!+k78T@VV z{Df(5dvUB;Gyf7jV&-2WV+yxmdfY9qo{+aCGd_CD>njVlL}C9Kb_DjzEAM{C&k3;Q zYft2EY16&)+dw&j!Kl#xdZ)Q~4GQ%q~GNFuP|X zf3OONN@Qvww*$XB75M_;#in&yAW@lB%ylor#}>-h)_6?re&U&@A<|)anUB|mpnv{& zqy%G7vh~}00*>{dET5+{n37E9dII^u_&$OtfLZv=5aJ^kiA43`8<6|6K79G}88W_S zBC9aI-O$#oM-dCg_bo(b@drR)d>L=3u407RFuyXs`~_8F5X-zea|5CQ?j*iP^ZM9F zVuJDIH$^bM+%(`XpTPLC^JIL|~vd~%S8&2qRVUzLY zT}yjTlQi^{0q6I%V2!>MN5V8rL!h8-t*cs%+lXrH_9_iyQ2yIzzvM=p^_R;uwh_) zIatd0vf%7_Nam_F#G=IF!1#U_LdN%8C}4VQyR03=H7*ybA^6`?Q$75{GcGA4z;DX1_!gcif{{9Wt3Y&G?#%(u}X^K$`J2Z62N|U`0>1 z>mu8ZN{nDpPqo`u%rxU`iW-+##ms-uHcv@>!d5+({S0~%DVmCv3T&(Uu%zC44;_`b%}SM^{c)| z=p?H+7GQjt4|_COg^kGgo+Vv~CTFuEFuul)C;w>DyBj+v`3l?ASSIP9d=*e({m1sMwbml4AQ)XB;yyFZ_kOx%u#ZI}t$dx#LGmq($T%*yy4 zXl=Hi-2~%%F|@E4jT6TAROCp?wHu5t4IUAER7u8{m67_slAD6@)guBmvg5HRi!bE& zC}Dhm%c6>TaDnlq!JuvyV0=w4CM6$bFTnWnh8SmGlAdG9_?{0o@#3AZr0lIdW4ja{D1Ufbr$iXfnPg0*r4dbAa(R5ny~rF#?RQi2&n!659>N*VKZ? z7}-lv2wNp%3dWZ<8znXvU)qOT+cLiE5RuGhSzvr=aLmWDk6?ViEjAcmUKD9aQDA(z zb9f@DZ5ZEQAfgMeI%IsgbGwY?Sc36ot)~8G>_%XGA4Vh?Uq*HHc^QzS8wVJX`B;=E zdRLz(pFJ0H5ROGZL~1sV!JaUs0bp?tW3^y>dF2D+E5Dln<69yo7+>=0xF0(iWp;lU zc|*o`6-wEQZg1D579rJ3J;`RJ$X}t{K`4NX@1e*A#+N?gv(EAJ&qHckKEll8cZ;m^ z{d|6(iA5O|i(ZJ&9)3I4U1osaE0M~@@5%QB{{HQ5LYAS3NMY^yCQ9`WXwNDi#rhEA zI-|kAt21XiVwfNaR6o&83q|7q$^-T;MDe?0t$4UH2(Iy5~86)1rz(!-_G+m4U&k@v( z&+Qhr2L5U(%;$SYhS_)WEzo425oSL;%s#^@TDp&ZQ)R_v1<7XfqbL)kwz-spu?F7i zHBAh#e}F$JbFjwHDe$QbR!hoE%0jFdvNcT%EHm*G_B-Y^c%=i$!mU$? zy6!}$5;1M`2M~x2@^(a1vyein6uDNR3Jan(iuAU!q7ovD&bjl!Qe8lylQdPl4GlCD_45ufT=2W@NT)hvO&CEHYoEn_JFyw z8-Pg7tz1;GxME33>D=nNCC3k%J9g^K$urA`7@a$A=JdJKm((3sRoU1ucjDNwj_1wh zER?0L>gyV6R(SZSYqd1e&i#&g&Krjg76#O?RuWWFYeijs6*#TM^U=VN$s$hLP*v&F zNa(5=nzfXaSowVM{^`)C4T!9(Ew5Tp(^xJ%S9xV!-SIU-6bcF^?n4d2wWtETS9wiC zdF2X>nK~P_oe__rY5$iC>XyzYB&Ix@ne%?}d=4uH*P>+T#iFWOYbj6$une_0$Q!%C zY2N|JaU@W$z;9z}j+JIL_jX#oq^bf?+>)vW_%+3^=RX}67oK(7?J0nk^F8r0%6jXT zqJDGH|BX*dvk81NEw27RkoR4)6bqM@>}W^t7AGVm_uM#!D{Z0fjD@V)HHH`;TTw1MO?71y1JpN(X`O+2ty9n&yaC3 znaN&Sm#Qv5ip^1ppvbPH*yWXu16VXfc*OJo82+!eYPnawkZ@vcopxOIk+f|=1+(` znyLkwik#JTD4}A-@&!1!45o;e1#&!9Rgt2stXqmxrreBe$Xhm4RRPO%8SHADw%pEi zQUOh(tc10B?ix_j_|@gG^N@9D%JO9u!d|9{NJDX|1KwtQr#-jQc;>N->gMBcahfxq z$HGir!5)Mf9<1o&WdlLK)NsWf@{PF5LKZSoD zl~oN5bxRsjWyQ_h=#TeoG6N05{U^63Cm@FeZ?mhx}>y&j$c%d3i-u#r&G`MGI<{Ew0<{)IA&9Ww+y32He== ziws{dkjp}pDBmm7{;XW;1l^8bVYvM_RF73%q{^>hOkbyJdDQdOzFhT2)w@)MpTc%e zsQo+DS5*I|8pGg7e^iI5PEh4L5T?&p748W(eKIhfpfvTns=_b9<^vwaKckw>FGjGF zs(n<4sE$*esXAZv1l6^w!U>_ACbfU4dbjFhs?V!_tl9?OQdvKrS5fy?EmJ*KwNdqC z)k{=2tNuy#W7Qm-5-hKa>OQLbt4>nolV;{SPnE7dXy32;8&%Gf$oQ?Q|56=_r*w=T zuR2?`N_DB~2Gt8xuU7qu>O-netG=rG57n0V)FC(lq<+=es@1BThLY*0sa~QwoR6;& zKUq~Ab-+GW?d7WHt6r&ktLo2Hx2k?#K6Nq9UAE&y)w5LjaDwqStKP5rgzC$x@2W=e zRG0ZXs8*=blLX_%RSfh_wST8tgl9HPw_NI2wduNn@zYf2t1eWnRc%!Lrs^50m#W^b zdM_3G^5?3*prQ?rY5MQfeoj@mRMfvk?Z2rCpNjZT)DCdzPV=dV&sRIC+E;a7Ra{=A z9XNbN<+_P>@tVx`@lg-;0M*f|<5l^fj_G_7M%^8c+MxLah(P|eYM-L|EmgUGBAt(Z zSnj2&SF2v9daLT~s*kGvM)euhKd8Q>`l{-Os{dA%>n!Ta;`I=kr^@%WwE3W%%J;_9 zajKJ4r>V|VovV6`>anWw`vGjfOl`j6WqIpVH>k>W8}TF+n0|@s_f+{Vi19b7-li(o zcf|7{KGR=PeMj{lsy?r~NRO$uQ|+MIL$$YRsjB=xz;>h69u|G%kIy;&Qs%d?m=kZQOdl58E!hws7f>6_+?~6jm-b;@K_B z?}(LoxYC}8)wTga;W(7PHJ)f5A|*tB}sZh4Kp%=MS$ zvD>!1QxUe?Am}}W^6-~lY}(0)amzc!DG&b=(&b%(u-%4*JdMKWyU;E+?E*x&<(-f6 z?0##DG~2$b5#}}}Sh+ljuK^d@g90|wxZa{_^VM|TIjeb(=7Y%cBJ!141Il{2+=_|ci+A{e{KE5$_cN7vwR*0uNlXv|8I0M=RJ%958{;V zxhgozcW~YU5nKuh9zwQYSm9Wtg1M~4aD%zztnUH8eFaksk7i0VwjL?L$=qUEC+<}E zOx>5o#AC})0(_?OM|%!u$&JexmC7H+@C;;*_Rl|z;eX>2in8g7^9ay#o3WjWy#e ztFeI}6r&{>{d3uf;1~GFSR&!fLy(%8<}5R=3A&-KEdJmiLpjS!QDR1moMpyUS+lW4 zA{QSSA!qqMO^37m3ky`vlD}%m*nzW*Bi3-1-$5weQ3faPIW)B}uAJo)C^X)Tvy2b4 zpiY8LVdEiZNn$1*a+W7?(`KAyd{CR+aF!_yO|Q6emb^uYhn!_snjvS&8?kuESti(n zkh3Hj8xJ{4PP85mIm=hLZOB>P!;(YJvKKQuoFy+^aX)@=TsX_Wpo#I2vpkZf!&xS= z)8h_jxsdj*ILm6(w#knl9VZZ$kns*VOW-wLJmf5Y&6b3mr8Ml*bC#F0sd42jPvLll zoMnp5+<~*?P3OXR$XUj3Z|`uH@t@iwft+Rh4z-Lg)%cxRW6@grQoWB=-KD1Sr5gXg zc9yf8%sz#j<&!i+&a#1K$XS+i*MyuU;o5k}S&~1EH|H$lzt)NjXBq#EcEE6!@y*)i z;fbqQRLEHlrrDgcjQ>uH8kZnq6Aw8{-fPE0&hkPwGUP0KGjqsU9>*SqoaHgB=yP$F zAEVrU(fBcuxNw%0EZ5;IkKtfAoaMbtcR0&)SuuR6TF#OWc;XIcc^z$sv*Zt1;|^!} z61(MamgLpq4rlor+74&AmGwKECBF#89nSJq{0E3ToaGtZ-r+3&$x(GU%f+nU;VfTe zy2DxWyo$S=WeE#(Im;v?T+Z@d7U^=9-(neiHfKq)EN(f=Ytez6c#$6$&Qh)=4re)z z-E%lgUU1?qah9V{Zf^V_KQ5eQJ$JstS)R{L9nSK*EE>L455`UwU#bic#ZykM)8_cv zNG8$A9#lSa+beir(DkR7Upm{Oa7iQ z?sArV;28hUILkPEsS0OV%IY1?@;e-}&%{~A;Y(FGOI~&2mb3gL+t?y!xem2_QJiIO z_8{aeuVTe6XW0?yxF73-D!cy>O*EWk7JR7+XL&#JuSpRs_EK0qKSfL%oaOHkl@)T9 zamJqEa+aM@SOnxHA<5>Pz_FYXs^5U&*weW4#G$Z-=ksqoVOxd*kh>KU$E>^I>kn+K2Vw+o$LAgWom$ zDcLI!*Y{q0@CNEuto>}_-j5=dKZoIc1#o_DjqghGWy|xYXUkTvAdOFf_GK2?;$v7J z$rfJ!H=vQH{jNUA&*1kcpm+tk7J0_cp)mk&X1&O>eioB4VB|aKcLs(wi^HBK6-v_8r9yk}gcR-5%`eTL;omW)O*_B6Kc~$%+8oh_mGq5yrItGF z*9J6kdmL?h4-O;uNpCni!)%7*w2jY~7ySnSyERB{-<-+$DJc*?Jg|}62LrS%0CQ=| zf=zKDFm7ZIH{m?$ks43s>5V)*zwF}kd=Q9LW8^IKrrT4^_hvDBKdjhkyznSG$L5*!N!O-*=ij!6;}x^F*y@`Kw1*O*HK1#CwK#U(^-nS9C<kQ7!p z4yBleEcFGe9f$~S0eY0d1F)i9l;K#>USAqB#l%ylV&r9U_a*XStFm!~6ShcyUQD5so)k$E&XI zcSZ!u**<$To#K1x((znIJHml9i@mhdV(IO%vQS$v3wIYce@~3f=VeF@bv3!Ra?#QS zRbJ%*bL*GX9lNAraf*mkL#p43vY~s=J+^jfs&V&pCLS0S*Vffm74yCLTyQ@ubME4b z%7rzxUryN#D;xg9He(L$xu9X@HgCI-Gqwl+VGYeo)=|Nmh$R4#1Sr7MHDO34rlN7- zfQ39d$`@2sSCEWrTv=b$fH>@Al5HSZVBo+ZPGmyqEQm!8Y>0TA#sW{7EQ?LKyb9sO zj>%~h7={!+Q47WEDe%#T0f0jjDFB*FhXdgZa#PVrtZQ(30QaCB3VIY|_)!w0!P~2S zBmfURD_~4k@a}4Yp!+FNS|VF*Fk9s_Lq_oaYCl*p0BEY&@LR#bwy^hB`*6%E%xO!+ z>ApoMy~q%!5)!m@-&hXf*wCW3T5~ChSc0bhezDxW3~M?)_2s%Ubx<-xnpsSa_!<$% zX7J?aBvjK-qlMapy|e_VB`iZ$OsT{Wk7LrpI?U{HLg^6U_Y6j-@E}uL@L`Gru5>83 zuuN{6*bL{ZPs4@C3{ug>Bg>T&G%TB81}!b8Sglf!Y2?v?e%UVKvWA%y3NGXc4YIdA ztI9DiM<-VdEUy9lsu17*3KJ(J+xAp+Ga%F9AZ0w$_$!Z77gbK9uW6unPw-}%J{&`e z)ErJB5gAgdpMfcstFRnq1|oEDO^eA&>SyCoUT|ezH5H4th%+vc z23E#DYXRib2(O_3UlD#PjABdtDQ`E&=H{Ie-4JYyoa!&k{^c(odN9`;gYV*dq`y<% zLWfIuo6WdA(cdY*Ch~h0$9X&6R4z=`;i=v*3QzE#aHV`$M1E|7>QvPks>i5SsWzyt zQeCHdj_UcUm#f~WdY5V|S8B$)l`A#l(8`sXarj^5N;l(~3a>wwC;by`ytnzY#{XTF zz!CGcp(4Gl>RzfvssmMrsvbneSKx7~lT_zu`drltjjvLz)%Yc`G1PGM~Wiej}e;zo8p6{%qBARllps_Yo}j=c>O@mEQ*-{%N(JSA9|Sb=57Z z@2P&E8sMKD%gt0JWI~%yVyRtJ_fqYnN|!WDAE-K1b$ibBD2*>ytyVow^#oNq4Pkk7 zSwmf`$~PahFIH_*y-JnuJeY2|*86DVMI_&PF#flye9J-mb=9}1$j5gbjQ8;*hANMT z5pRzN43os$<0Y>4_Qy?u#-~*6ar1?6soOEB_!`s7q+*=8VE4(=7oXfWd^*i#u#xnq z&DS3>40AtoVZLJ+(1rV%%UG;-8`|e%eG%6XyV$gY5P{2~H%b$Z!TaS~a2)Y>MG$#d z&vs42YPUhqYs3L`3643t*t7~n*f7&LfpXqX@{uxg>&+|jycF`WUe?EcQ0uX}<#hve zm_nRgY}z73xaF1fHs=7#!@q!Zc_$-mw?WVwf$~Zi(8Z>$f$f$z3gwML9LwXmW7~HD z!gd=3y~QZ6Pr#5_Y}&VBy5+4!dF&s{<0}GN-W3RQ8{4MyaAIC(cebW6{l@L`4F}7~ zYqMRLhbtLUs$FhFKHjt2#U3v|L4?~r`oQEhgze)i1lvAdx6wWB7FpgzdG4`l>!Lcl z-AmygQVNkB5sx8~@>o9WbcV|th2t-UIJ?;LxQ(0dVzloWn+a<3g^w(T5jFi3enAKA zKQzT<_pIsjy`;istm(Jn^|$re>}@$Y!z-HpLG+NZAD;5=xOX#qcN>S#vHOm@WlXT8 zSLHiTfHL(Gn=jnvjq=NiK$-geF5KpiD!lJPIDjrnQ>OKI=hxRy%m8J24gcRuby5E> z=v+<(dVi|ZVH=DLz^)1QP7Xmt;AcD)qr~S>A~DWV5JWOxhZS)c(;ymKf|LlkPi0Jl zXl5?0cx)3Y3gVfEpi*T_kv1HqNB)hEXhHkE86JYn%9uv}!Fa=%2Jz@9mOKR?%^B0l z*ual;z@e;+X@rN8WlRSkbw|du7)`N^>6s`o&6u(|#b}`5I`rjf8Pm3ibQsf@Xoiew zWE%@KjA^77!_65}4BWdIbYV;*w;_F}jOimNv_;1BWi-=aOxKE;_T{;pn|?;dG{DfL z8PgxKfRHgIiR&kg^a0;cgUDN#Fl+gjOod2nq^Ec;~ozg(>R;yGNwH0^6F6i zf6kbapg_eUHru8PjvQmqNyLBU3}h zG|pjfkujabiar-(`Xb8R1!H;$2V)nEDScyI@R-4(^&UJ%J_ck}=I;8(qe9GdtxnrjIa(%a}gRX1a`NZ?@wL zVodqP-(^hC;h23s#*|l`G-LWW+t?yw%ITE8D8`hJG91Q~zw8eg(;ym6A|3Z*xu~-H zCNweT^BytHnBIc?Yf^V((7hB^&rh9<4ZxW4hd2&n`XM%rZ1CHkhdjoY=f~J`=ZtA5 zq*%su4hzNNFU75F&&5pHKac)ACn1twL5kWkF3p&J2etbL=8?bzW12#(4r6)?^1F=b z!N@!ktHYS`3Co38`>;NKMf3T=?-*cA`<{kK-aOrawVzGc`vS!BhXlN*z_QOOj8&vV zL}}5hkh*XEVZ*#g$4DC*{e>1SjC=}Ow4*~7VmI`{gU69=0({epY7k%kVr>yiurDJY zxrd`wnYx(*fAOT>hHf{(ClWWzQpcQvE8=Ud?@!KWe48HLvjj|dKmPZK3)iZ`9Y z6^Q5RCItUk0&#E3inl{Tr8<73flyrL@vKRJ zPzKpb#W4G83cybW`Jh25)S(EXiKhN>CZ56;WC|);+BMxAlAv}NP%^T}!b=|)R?3AH z6Yr!Fmqb=dN`kW~W-NpdJyc?6+G3kwp)!CbFVki5Ia{P8Y>#$&4hfph-W8cmySRVN z!ohSG*XDP<&pVxcE4ulWqnpF_9CDMsK6fNHe`OfV{nF&-Evrdm65`x1)=B(xBG|(X z0>oVD_eHFD_*^Da#OJ1Vn4msu2PQKsqpbj$b9MkSJG($;R&aDHkl9F2bY;R}S}xN% zHrzdt`E?;NTiHu``*fXQ{&(5S&pyW`Y093I(^1`b_#Rm678XM?#l%* zt>@WR<`OvgPUe_DVHmG`X}7B4Q`x$|H9l>>T=3E$;=@)97D9YaqA+>0=`xrp=f;uu zjbn0iP6;+dHu}}sX#jKdAS8${O3&v@p4hPQ#Z$eEMCR12NOng1Xo26sPX>j4C%?1b z1wX0m9_gvy9m2xhh^Y6@Ct(WjPu*17_Ribn3J~Ki0p1eg^|7;r_ri?a6ZuQND`hV^ z#@q3iyfik$FX^lW4;=7AVEyg^&WG|f*VBwct6xtu4qudC&##KVoP}#5IZn%A9!(q1j4g+GoTgh2a~W-1 zAGt6e|C3Ppf0D{4UDQHVdHw>sm)d-q!}Lk2Q&jmdiSd@7JVxyWs>iFg#7~~A=|nqN z&L-9KRllcth3d~$f1&z>>eH&vtG=kZMfGp0@2h^Ox;uW-a+5{)r^fc}tGb^mAH*~M zP}Rd#k5sKtty1OOVa#8zN+N>xH&xfGZdA40NL9E=@Q!?n&-h1G<^L+; z?S4gfCEf1#FL=Il`8ma~uRqr40q2tY7mgp7!A8=b_KvLwVldR{JGSlfF^x-Kthl|| zZNC1X(JIqwrrFpG~$G=$MM1YDu|r_Y?pbA ztC=7}aY0yZI|GCc|nA?!Lct;0;E;6e2q!epg)M zEF6E`k;g8!yzRM0ydK>3eCO4J27VeJn)?qMI2cePmfdrW!+T1rnsJRKx1AOL)7Gx5 z3T3AA{u5?yjUJi5H8^hO*2r=BTm4nb-@1C0KYaOH8&`2Y^W|?{gP2oSZGlJ4SRPo% zpzY>OTfJ5OfsD;U*k9%E%W&8GHf@ba-psf1I^Xfu#8oAC|MIOG@oJAq4ScP8lwrGyqK5VnDN9r$b@;xjhU0+T%ef)yBO2X zOa3b*!(CA0?flA8jvfVfSS=n9yY_g33Hmw3yyPZx%4^SC9GRD# zb2uc}T+B<(Fh?D2^e`_u&4BZg(^nSeC1=NAM-o$+{V=sp!NkHm=r{?4bQ$xK6S0zc z$qNxM<2|oE!z_I>TUMT7ni5UC#KJ1Fx=U(2!G>X8at@ZxOU{C`dE9Z;8e-AGFfcFq z$q>#}T(F^TAMB_Lw`Lk^E%Q>aU6e*gMxE}q+ zyyQHCIWPGOOnp@kHqJ}V26594^1-8}!$JIDJoZZr*Soe%>KMm|nU|cSlbi^X^OBnm zc}cp|<-Fua<0hB0P)}t=@Rw=qc#{96V0Slmj+x&XETh>zFNyz`GB5ds`0vPh$zNx? z!7`fklH}90!7|E(5}22~h&EV8lU|nmBW?K0yjQj#p8P-72Y;F7QZg#pn>JWRlYd;Y zf+G%=(WFmG9?0#%GCnBVPcieVgJm@Nrzfvx|G+YGa5yhH`FGAsE)!i8%}MgS;=JTM zm1JIW{u+hzlJgvqdC6BZ0xTmZPL_Gehp{nU|cim?Y)e4VF=+G{J1toO*!slA95XCh3th6aF&wh(L|( zcr41|3wiG&^O9f5qDW$KUUC|^TqNhx2Fqydj3n{h9p)wHqZDnnnV0;1-1sG*XI8L` z{BOph7SaaGX!c_?c@tX+f0@k8dCAMrdCp7D>n`Ud=Z}RrFS+T(q~wp;3$TpUQr`6B zq0A3|nU&JiImvsO4wliJa0`<&nGTlG*!4-yXq^dvnZ{m`?1eGpyyO|O&oM9gm8=l{ zGCN8H<|QXc$9c)wf}rSfKgsWuoR^$M$h_pgMGEI7HxZbZ{4VAI%V;7nFZsUA0hZB3 zU|#YA7y*{iL||TW`V;27IWLMdWK+yb&Yi;(No_MPIj;m=c-7&&{f(hQJ&~seV%;wTzFpMAHiofkHNnqAPwOB;j9+^ zGI{00yyTpnC=>oN`Be>|QZzaQ9e}^gt59b5%aLgOWrCT_-~={%(dp`%)Lf)`sR!`k zr!K)K%58%JI4^m3BsRU@M}yCe!*TQah&j&<$9v%A`^~Nc{nmYTx4!?9BD4amxp8ka+F?JWnOXy z_A$naCI$u=V|CiKBC;)N8jjd8Sg|?fP{~vuZDN4m8vxtIW$y0z#>i=c%7RmYi*Jr; zs00}6czHA}n@#D%%-$@Dq4?mwk+qM)s$L!$oP-qw9%TwvG}2Eu2JvhYn?kk^A`4DK z894LkBg4B)n#MX=e#F}}jk;RH5Lvq7Ga@1F3Bt_dF0M^1{quTBZ1sz1d^&#lei55P zjiDLeuG-+T`cBjfu0a4UeL0!+er-hs5&tisfLs@BJcCoVPnp zqMZiB98Y?C;`G_#!>mduxUbiw*`J=QGRLijTkIs;>hTb4*nfYXZ6a4*+Ao`-p}vlj zXA7=o2lfk|G&?;!2H5*rO_ojHa$npu*?Z*V*f^}Lg!A8H+rLU@ng#k z{!%(7+!L8N-q40iROXysk&Xy&Vi~n3GID%Z#_tFm>*kD{`6mZRu9q_nHcwK+$>D)P z4z{6Bb-p*F@;xI}I5{Ntrkya~(iu;rk;>;U)X}Q^T0wiN>QSoll>+fKYA;u1Tbch1 z)pJy@P`y_5$Etjh#r#jJzNDIojx)ZaY9Cep9F_5$W{5gNb)M?+s;8-5qf@@x>R+8>IJG-tNujwA=RfL%4IRBu&%K=morS5-@K&a=MJs;gB`SG`vCUDXJlurYtW zYG>8GRAv5ar1R&k%r{bXoa!N}N2;z=T}Q>f+Ms$m73(=vl=B_6FH^lrPM=dsPa7~+mox> zLA8@A33R5*brj0?i?ro+9F$L6X&<6`gsS!HSE=@~syMCipgA0Gn6f=C6Qa%h;k6C- z$7hi%mNS5xA6iqcq_`yeEAFh44NDhf$hmnuf65hFLFegJTB&^Xy{NDiC4A zO#1=uO~^dj#RiW?gj?^8dwJqRlJ#;N*bget*Z;@fmB2?;UGMj1=FLo&84{8(14&>= z!YT<#2q7w9fDm@s6%`q>LLej|3!4bIFIB6>x)*F0Ypq)A+SVPlR?rlx zR*_o&-*@kMGcO3ZbhH2F{qp9!=iYPAUEh-TzIU#j2SKAB=3s;Y+3d7N$WD91`s+DO zdu+CC?-YdXJO~;`z#h*v_GYJTM1<4cXoo$XqilOTKiGL_VfJ42J1GS>j+{gG#&&SK z1G}?+^ZLj84^@cO?-7JCM>#BN8x4ETxymxR5gpxNv_P*Ak-QhS?Xllkrak8oG_J(_ z%Vj_|+upvsvD*Fz@rPHnCJNX5U(O$1QE^#GgxeSM#^w!HmFmJ9%YSFrgi|Zc-Jgw( z?%3jA2#>V#fk^XA zziZo{v#uX+?e=Q;b)Bo4nJX)fc|>GM;+rV`J8J;~&~Ktg=TRvn&AF zGwYV|_ipRaXIP~<*n;d&xeDp4E0ZhJ7x!Cy-=B7!GO6-4tlxYTj#WJt9+UUU$(`u& z3+*0uAoyjkOmeaLt-v z99**nC@9V~8x0lrc$yiOHj!Z$lEFJ$z^r~x1+C4(4|r#{AC;k#}}H;?P-~z&#jtbM;;D&e$O- zf5H!WXD=cl@B)6oJ7XAS2=7dn=n4E8)dcTMi~hj5N=(;ca^O^EEzZ=U%{zNt86xkj z1EEAN%DEf6Y8%QV3vj{^Y02R`Sl+S;9M`;lxU0<}M|G1_J@SGx`=H?`$2!z1a9zy) z4{YTqy_iVKD0yd!m-0%_o=_t1EQ8A1lczw5yfa>bz&qm+Ox_uNEP{8Yt3lowL(H0? zemGk)crTp6c#KOnl6o+y*L(QUyfgMrsDXCDJJXho&;oV_cxN4|37!!7sN|h#*&jNY z1%r2{<>b&4D8vWena-aQx|K3~==~5^I`Ym&Q6IcBon9FFEs7`aO!LA@LNiz%cxO7j zEc7eN;GL0J;>sNz`h?|!ccxDz;RNrD#}#>JJd_mgY%mRicgABx@y>cM0=%I0i|HtQ-cZ7HzXUmp~!id<-$1 zpbk|=+2i@3Qer+%+qe?){|OO_cg9($4rbw<<=Qf8cNV)5yt7ScO!#6nK=IC+p%GH& zZt%`1;1~~;uzBE}=^pfi%GrMK&SXZQL^j;=(0sTOb`|gJ9-3N=s*ra^fu_!3R`AZW z>jns*jNH-?7N6nJNwpg~jgX-D3f9!F1zemluKqcVAC zzvdW#cgD*Ed1p};4c?h<#pIA89D{e(s_f0uj4trbPEb`{5Tc`4^3L=Dw>0!1%LDIB z%Ppa7C^!4j3yNCtT*cj z-kFX7@9bqZ3cNEN0p8h-)Bx{HM}T*>oz(>IOhUccx1r@9cOOVXai3f_Fxl zl~OWzXOzd|O<@uWyWnF8-@6I#RrNo37C`ynDS zdDbECjDwr`2i6h1GnT5$zu(RT-q}i&0v~#e5`G!aTbN*EmVv>EN@bay2;0ZP2P&Q< z&qU6_MEw7wDnQ;DTL9h}Er54+B?|`cEUZNE&hn6s`>|dqvhVj08Rwl#1l{Xm6i z&c$77&Po(u7N_!QQyC&7*mDLmZiMp3_dCc>W6!+-dCij4Q&`-bT>i6Wj!dTob8a5* z)XY(;SUxpzV;|7m(T=zfEAey4ywc=h@ma$xQ+6-LtT_XF-bR*H)@L&elH}&Xo_7qb zAFlMKLgwL)_E4pJ<>YQ(cwJXh=A=;nE88CGu7-?omP+7{8(tyw#*}yv68|p-9gWae z1s4){-UJz~eJcaJ9za+VTmKir`mNIuy9hfn6Kb_m%T@-KsrZG2bt-k=#P2@ad5}$GHi3F>V}t3)!2i$e&BXC#?>f%R0rJ5Emh&aBF)pK} zg?N~bCXCh5?ZgTlO<)6|y@q&{ik?SUq@&jp*;c4DHUV`-=M&g6)EU2eW36=E>|c!% zuLmKID#kp*0jgZAH3$c&eYw^kumxx~!PyZ0?~7Oq@_klI|(j*S3<@j11i779zTTgC=1FwGzf!`vaP!Hzk#aVrD5)L8`1 z5)1V#Du_)OG7;lNvl(i$Fbpi6TVL$-6v#69zyV7?$Lqbw&g}Fh7#|+H%1ou5IV%5r z0?Tq69qSc8leQsvVs&wv<8g=TVDqS7{;;c@n^Wf9_t$kR*v)nPPjVgQncshg>Nrv{ z9kC#EFGY3iFs-0FslW;ivJwg{pL=xy)@LrxP>V%pTFIL42oJaxS7Ro>(GT=_bJGwA zTFD~|5LrNhu{jLDL14-LW1%`#sg7p)K(!w9apq_)2t8!<=bR6ADJ(^mUJk~jyVc|} z)VZIp5OioaPb(o*mP%PVZ-}C1rYX*Q&;7bw~X^T)W2Vdgbpbs+J3d8^GGSHSm=N9-ijs z>~{(2mML28o3)bkimEk7RW;JlTXP2-eRVr7tXtL420m7#xO7zEsFLF&`73H#I>yvA zx8luV{)!UF?MpjWR0Hb~U*EE-B)_dCzqY89F^$bt?fF&J4P%y8wbmk{s~()zqBd*52AsgItXbRc#GTOUMK3Xi}UoCpV1L zU#I*zuGs(cMWdBJL49KVa$X6)9KAPos@|^?!{|S_YIGNWh4{Zu&H&wx3!~kOMK^*t zZ$$r-i$y2n&eO@oj5zK@c_TVLn02b}H1Fxw8J;uUXSvSf{qQ%Dli9;jZ|BW5qrZt9 zO#U~)zGNTAIhe6Ck?p5YPIkh-^b7wI9EMcnBhQlW>xsRIc-}OCh(YE5iHsj1$o~o{ zj}xpEBY!P^BN5`0ULkEf~6Cw9bC!HD2Y!G(g$1y2&ZOYl*_w*)^BbmRX=+U+UWU$9WH zQSbyozIvwqje>UyJ|f7aikSYUU|&3pq|AqsM6M}DoFT~9G?Z5eo+x;(ARpE;{Re{g z2|gkCvfz7yp9%)NIv-!MGe4b$5XT7e^K;5kL2^+jpCp)v2h5a<1dkA$DHs)8FL<`# zWr8;eJ}3B=;D>@1jzQYb5F8*lQgEW+e8D=w4#Cp}FBZH}@NU7!1YZ<^~^-?*v~Gd_(YU!CitM2->{PY@Rn^ zN4{^#t#xaM9}tgSSs=uLB;!rKAjsd-*mybf=3H3608<%5L_YHF1SXJZ;oj1a>1(w zuNVBW;2na>&l2<>5Sh-lm|uNY03-p1GQI2&-w=FT@XvzkdWUrNmI@f;bqd%^u#aGW z!2yE91Qjy|`h26se2S6*JWAwa1*-(>1e*j~1y2y%D2U5~TBqASo*^pxxXdZE$0wa~ z5HH9j{%i7y<$mqIo=*IY@Cz@ZrsLW#~~Wqc%C~J=X86s)5anKmkpy_5|Z)g zo{RJHz8Rn%!{gFw@H}qkLC`41g`g+qw!PVDixFXmnO1>0^KHyEd$ZFPBEng2Z7$aT zh91jhd29!<8M~baLE{f_G)2|?PLAWMKOCdODM=gaL#b=I%Z(O&*9X1DiYgwebfWeh);>|@XF z3!-Cs7>`3Qg2-No=l^E3mx7&TI=ahv7rYd{J+e339`iW$)}wyU*-AiLFZKwmXyku@ zPds{$OYw;lg-=|#$1i;1!aZIGpSW<3$H6Bq+~e9WpV+VX#J^0|eByiebmbG@yT{dq zPkiqlPn=J@=|FtqPtZ~DsGwgEI{HrqyYh+M>KnIF;R#3sx405RCfs81iRVMwhfmBE zcEKm!fMEikn9h#&y9Z4f0()}@iVtnFUS{sg^u6$yye%h5!{3~R$`NZi+{XCzT z7f72=yapD(m`@x=wH$n6-sw2`#Jg!w_{8HF{v4k;1+kh>d^JKgpZFD2HO43A?bQMK z#Pkm3;1ly-Q~0q|cfh&H0e(^WRr$np6cytW^Iv}WvDEgA0KY_X@QL{%-N7f$U<=}W z;y$cPoKO56ig7;iAJIeypZHOlit~y8MpIvwPpn*m{Udzhv8Y;{PptYo&L@7JHH-6! zf6IFRbNIxH5%@)X;!P<2>+^{xptded1U~8jpID1u#3z29O^ox2c^P%^iMiDJf%(L| zr~J3@iC<$i;(X$3I7)FoaVt~feBw@uaXxW9Tl6pB6Z0QaC!d&(4V`@ApELa+eB$4- z5e`1_Pbhx{KJoD^&%q~tfwF^7yo=>K_{97N(#a=&9ami^pICk3;NTPUf!4wJ#6M@c zgHO!kstcdEj1_Y7iTg3)pnPI}mhuhf6Q9d&+&`aKol6{i;sCBYPCoH0w*NqUVm_xm zFrWAeX59~;cq#@NhrE%t&+@(+pLji| zwv$ghgk?JU#ILhaPChXo19#yQ|Ao`v$tO-_J^o32;=@_|zkpACH|zLs;S+ON3 z^w}h^ia34 z-W%g&{=4|ZYxw-)^NieeV-a0}y(b;#Ez+^OVZJh)=Al zT&zl%M>s(3%e4mK01a87G`ji37`DQ#=nJ*s+>KG^FP}Q`Nl-VRxT((gS8$cv*0%kF zb{iZ1GYgaN&vz={EZ~`6H=h{n;Qt{$@qZDE7}FCTV81e#7=-DfQo4?9t!kHl{r#RWsXj|o!=@V@)k~(a2yjz;v8o(-!JpL6XRT~*cCQD;m#a(-k&(Wr=Wr5q_P zEGjE1E*cRT+*;RIhZVPnM2=fhQ|Rdi@i$te{Ny) zfBH)2vB~(g*F69KN*7k%hNIxC%5mA{kgRT8J^>#NM4K9#tJ{p#=tUmTwQbGOr8ub7 z8uBXVm*-=vOC6VA@ABb=_Tn4uKmqzAizRjKAjQ{3ahf!``NUP-d}7>C-0!{uMiC&v9+H=mgO%uPK% z2ZA1{_@#VR%dJF1?AO-geJjHpH*VCsR)zGBN5bQQb{SFv&Mh+ks8zc!EfbW}Cwm-tln zSDZ(j#A-YJ5_8t2oQmSV29KD&`{9>(0)RZ?Z7k}5JmPs&j{7Bkono9vypCerFY!VS zP24Z>YSudLmzdwEeO(^$c{COGOWcp*0sRtN9P~Jkn9e30JmQO4$vBTVjmmKz@k+KR z&Lf`2g1(kt;x}N|;g@(B?K=DtFJ@;r{1QLTbO(?4L>BDuOZ*%g;ouS9N!h_8E~dW2 zFY%*nmcuXce3s|n5x-B_!6W8ECQcqPKR|Wzi20$ulSh0u^E-INJK3uazr=G{zQZr^ zADQmp5%aj}!XxGvja_)eAx1cP#MjcK(=YKkwDF(yOU&cY>6e(Y(=YJ_>_(eMd@dRg z_e-qKB@P~OF`MV`OFWtFKM;?YZlmKo;^R2@4!^_~GOL3}d=gE=FEQ!EU%(^gLQYP< z#J4c3!!Pk_HptZE)OPZS`?HQt9`Rdjl#@sNBWgJP5_6rfEn9vvTPc#Vkn?zr>pm73UH26Mu75kUog{i5OSF5WmE|7{|}5 zwqVaY1eFvX@mZKPYq95@!m>1v`0tQEW?U_;Yrn)i_YG$259*h=mxFVP?#wfilEx;v z@wKQ&g7|>c>Va5#_4TGfdvr3!L9$tgs(63MOiI$sRTF9nfi6Z9O>;^b|SkWE5l2%o5mu- z8tlr)FavyV3Bk3MfeW?Zja5q7?+v#vy9cEBlZ9{ECQv)VbTRQ?qbV=2U6;;u;h9yl1IcVdUb4IipWNaf^ z-&$AK*w6-f1<2(vGJkq=(-L5PExz&q34B!p7~iXF6tmeTHrF?Ry81;|z2WgA6(?W# z&<6dxsiVa<9bHw|N?+27NZwAaDoe*f(9l+k>Qs{#JGWsSsu=e(>^xRhAgiJ|*EV-l zlSw;$=7ed{d8lh^LpwxRg#U7*Z7G~nN7&$&Z>q!Le+q;6zlRdMaui3pzNvj}OC4Ox zD_`;U7~+crCN`1W9PMc8XsfGLXEzFMEp;^w^$m!@)TnB#!?y_a%`nthwWO^WUnaCg zYt~f3UR@m~EWeqM?-Xox*hSiMb#N$JbkmA&ATOA=rS`_#&+)-Un&!m^( zZ=#Q3JehE8@!M%eeiMBRr=niGcW3{0h>?J`=Q&vuXs`3+sOPU-K`_r}yOL@&OrfoZv)3KFVYKEWt&Be9pu8 z7C}CeqI|O8>4JQu#P~}DuNAye@K(W}2;M9BfZ(qLpAg(G_(#F_1W9pVIqFRUkc(JT z&J`RaNCz#9=faP~!vx0)a(z<9EC27n*&@#uE=LsGs7!|A+TqejjI;`Khf)@&2B6yA94T84`{#5Wj!Ji90 zCitY_bArDYd{gjGf_!_V`U#I6iHU-?|6uy-V?38$CGyP@u|#mRV7cHV!D)i?1i5T7 z^LaT>an4PV`3g|+yqjZsk<=%hGH&?768{hQ10MC?PTz&=RdpZ9zT;M+A@++dQ(J%h zV%pa;gB8TZe2BOPf`M;Jk4H0Dc#-6%&IeZo7-&C3M^3wjxdXFsqVM84T@mU|s; z;3J5$H#=<^BAoVaAE@Uu?ct4N%-%@|+j$T)9)>;6dwa9fPDF&$-a`(1XnM@vW`ylL zwDBD5P2W#@zl}7fy=P&M?PLA;Ka|~Gz7(OoLhRi7L*YVuupu*z`%Qwj-W><<1$?LI z0n|1uD{h++_I%;B&RM^g9PQ=nAiI7KA&lm=0Mxb+_MCIt?hB%0dKl+JFM`Nkh({MG zd+c|X>F6%wN0@(5jcv9)=5gx1i~2nq(~6IQ{otv7L~$2izz5;(mT5Nc7jt*t8Mu`Y?du1l;bv2UqZ&u)*WLRlG5dHr}}cZ%`kZ+$z1p{!kQqyJME zzh|twz4L8V)+$oL zynZJqU#(Kcb1?_v+MefUN_+SBqJJ?KCw`#E8+e2ekdBZ>s-Z)@mC@5By$+ z+3STArzcQ!=Wa3s{GJv3UN#J}D=-z4z&BguQ(Z>l7^FN7ZPny{M$fsZn&S6{QLOIo zMLij&^`}|0s8`p_6ZkFbU6s&RrTPP`n6J7oJIkF5x6GD@h7${r%w0;bJiPZxGgDTf zYUKA;Lkz6P5BR+dv!K7S+Nda2LN8+sN zC#XY}QTBM=tdy9K(>AVz{7)ewk;frtp*omx`k zjDz2+Wp8LDO@rS%7PV9SUIuQ1vQ)eGQ@%|u-(PW48OoxmlU-q6&1mWhW(B`jkE18l z%m#tqOJ!HCKeUZw0Ddno6RzC6P?WU>zgM?na%chVf!|xN?9B=t0`#5f>Qketx*)`b zZpiP|2i(%o_gNnJy;^Pw;hxU$ean{DgcOe){9dmb^G#-mJ?=Z#mC{Q^oN0z?X#xCR z*1(;6r5RdJ4e)zu(w%#)8R9>`TpFQcCt|d7v$ajNZF^m%4nj5fNhFlHW^#eZHQ3 z27YgqlGhlCJgZYsrm~Gh4h|0_k^AiOZE(4HCdlMjhx}d+Zl+o&0Q_E-s>{FL&J;Gh zH7EuAUPfh^JPoMXjR|%e!j^{zdX~w9&psAjQt^-BH<5GjF9@g#fQQS+PxKSaGoNW@ zU&u)TelM6?5M3TmAEd)i@ZTW!Jq16OIRsTAzn2T9_4_gOH%9mslM%sgm=U!em61&! z_T=~Wg_ddh_+LQ6rDkdh#2&}s$MWdkdW8F%Zno%VFO>8Lr$lok?nZO!Sg%_$$ipo| zWCVNed$4W(pyvrxnw`s!K+GRzEQf|UC%1!ltQ zuy!+p^S!C&95V%Na>c2wh%5Q~4F(H3D}afk0+<#33(O;uZ5O|Tl2gr|X1Vv`@yaSr zKrc6b?cA*HH^breKd?N3NN~1Jz2`@cfwvtD&y#`7;kzTXm5|S>(K4 zDCH8b(BUJAw@5tkc8MoGCh2%elp>Q+?O)z;S4E-X{dJM&kTjO)DWSEyHs6%CJJ--j?ZJQD6n#$q_5Toe;5n?$rgB+gqHGZY6llOwfAQ7LeB4 zW3=T9_wEgDue;GiM3Lp|W%<29D|wPTakS+hj<_jlmM;U5J*?#X2?vYvgCLwd#qy6q zrhyqK=u3J3osq`U*P2$!1mw$OwpNpzV`2(t6FOjQPoC6d3Sc6C*2eSUEyf98ltetlDOep`EMLk)5@ zHdM7WG%Z17eMb{KDK|Ie!v!+24RLU%TIH1MTk>m~o7!8eYTCzuwrE6KMuN@w|Jeud zKY_r@Sqx0RG zF7G*cYdRsAeyVkv=XCcOWcwQ5NWL%Mhs3w|tv2JniG1Ils2BT^{o94_t4}Wu!Y?AA zi&!UNO!4;4`TV+AZ0 zS*`63S#hy|ihBiYmh=+^&k?*r@D@R}_B!-m6q&vnSk4|nKmMJgJW8-aaIPRZC``Xn z@K(Vm1YZ)|Dfo#XUwbnj9TE}gXo^@P$QQDd&llV(_(Q?_1RodV0%X+B5F8*lQgEW+ ze8D=w4#Cp|zbkm1;2nYw3qB|Kmf(ki7ACkVUvPk6so*3*KJuqtgJ3cr^+WD0I7o1m z;3UCX!B)YO1-~PBpWqXMFAKgW_^DvPugl98%oiLZI79Gw!6w0tg69ifC3u_QgM!Zr zz9m?M2jOhrIKlOTX9?aQ_`V=N?5BR3U?0JLg2jS#hd{ltf)#?(1dkP5D|iwSV|AJ! zy;-o$ zhlyM$h|^9N&LFRKYzLq15X%Hd3r-N6B*+JR)SDxy&XbV&%9Zg;1setVaG&vO1vd$v zDtNBo1%j6dULkm$;P(Y@6a1;5IgUUlAvtlqr<)mn|fD@5-~!5al{5xiaS zF2M%`9}>jNF;&h}f;RW}C6R6J@1I28CHR5h-vs&ekoENoCJU!>(y%6j3g5axy zZwRXE71BFJ{!ma|zYvd`CzanLsQ4#{&k=d3AW0`IXQUv#3Q`^~NPY%o<@+9}u75zB z#t+KzRo7|grBg46agcfZ^*O%0pX&C}i*8gKroY+-;TM-24!7D$1Z}YOh9QDsjvF`X z@gCORa66&4@%Xj#Fd`YkXq=Pn%}yJO2%O%Ha!K&?#W@+{4SFeF1L%k5tQXJ2b{+(c z$vBbs#9XyEJ8dx{>@d@g#hj_J8|6q_h_JKV(Yg8_jODUCwu49#lGEOOAbds;XK!}e zazr@oIeDtMl*R0wjIf=DHeQB3UW@F_PTPP8r#98fMq;LWJ!+2paFfUh{t1 zdp^>f_WlNYY#;5Ri(>Y!M40vpv2$Apg>Tt|4Vh`&Zx*!m-pa`@B4j=#*e6c4cy;% z*KWvq;vM6xc^?mIN!WZDV%|7`Io3`yukc^gXJ@j1+D?z>#=Y*d+k?K5}$>4b_MM|%8wlm9kp z$5B3W%c~zReBHA*>G2!)dM4IYEZOPx8NDa&^!Xm@@%K>0j!Dq;{uSx=DQ1*mj-901BGa883Td6e(x!p5+U!bCVZ{q~%8H{-MlJK>R@>>`A5cLVF=82?D zN0jF{X3Iy|QYI>i-t*q$}n z#&6AhAF4e(Ue8U`G5tTmiPvJ-^Bbi5d#Mgf=>fB0|8PG)I}3KAx&ERwhEWDd+WulG z(WBf2`iqlv1^mIsP-}m2x)zgzvoKWt;!G_nlD2bsRh91BIE8m>1w2qGq0KqlJ+Ll^nBBQy#GX6SN*-HC&RQ( z=aK%XSNEYO_#yK8s}fF8ss5mbT8K4&rM7!+(#6nxyUjS?cAgm!`ZK5 zbV1S%HgZ@W%}zw+LD&p#V&^^<7_P*@!AiF2*9lXVs7c!XC#4`w()RyG8lXwq{->ne z(ZP#p>Y3D8DsOr4L-xnBsf(4UN!tDw#8gG_K2E1UNZ#qeU!f`f7ZXXfbLGwo?qMZg z=@~_*fju1LBMJZZfH?olF3GrHpiM-Gt>|JA>&&9FdpNw z3`rJ~dUc?RgFXJmEi*D@U>ZL&T=h7a+$@`I$!LrIaeUt|FwY4aFSB<)`?0wnFjkyDYhchDqA z+9#rDMbdtlHbByzq%=U%_Ih|I=t1&8%P~kwWaXgrW7Ns(A?rHb3?a-3>QH5rJ)S8@ z()KuQ<4VXs5)ta`&snGrW}H4IqJS1#M(s$K_JgF&2fE=a(ST%su8HFbGeVt9K+>jw zV?4xXUVf0Ybq{(%0}$^ANn2(FN@T;m9-0rkU@z!D!u0bZ9IEBumzzB)(A2M(6(nsf zdqb<)b0BFiN9{<`PGTSgWvO=Wr~Dvk^CBDC%XtHmHm_zh<);jiwjM`M=x{a&ByB2_ zq&BIyT7dpXK?p#uTStJT{TH?ZByAl5k~W>d`$5vy5g=(l!Q%%cZCwhU zLnYk=^Q@KX)81NUrIhT`^0#c6ByB%P+CN1^=uIAbAZb%zpP$D*14;W4C9g4(cvh#N zOl2EM92_1`rRwsN5Ti1M@kItoF})r}Wtlt; zsM(DP7DCwT;enoI^5Cfo=IDV5j2aiTT*#b%XcWePj+C1}tr0qqLA0+KMC4!{= zeWc@l>}}Mp@AViT%N&a;C4i)TD^&X(f}f3%7hu$gl;g*Y+<+Ft?qD<{0VHkZ71{J( zPBUklX*Wa1x}SwSf*;qn&9q-K<|)S9f)k_bLNo0(#Ngxr0j%y0q*z>F&g-F4(t}9k zGvxm4$KqeDRGwE+oJRCvQ#(su%2vrtikQ0YwFF@du#&po87pXIeZ5ors1kp*sAZR;2!}^Rmze6V^j>}?#=#<2CdKeZ?7)B1y zc8L?Sm>@a}Vmj!YNz^$Ty`4BEiwV$q87(*gLDhdD!&*+2KVm8-9vNo5sBE!Sh8xy- zRQWB2K5nO9F2)bg&8j@Z`vx`4C`5{@XM&gW5bLW6<#4#yEmf$ zKBCS7wrNqA38FL1*7?k3SfF+rIh=Wk)nO)x&a9XYz6#>~LC(qSzxpr}M5jHblVn&m z)LG8HSr%r3=v)%hLFb%7ow4kkrZ5wr^J|p+GX(AayO}CKW#_bp880fY*edA1C#k}( zD-u_Q880d(9`PtE=)c`mX`+>NVaAI}o~?rZOGh||cc_UQ!i*P{$q2^!ZxnU@z`1pD zma)HyxO1kpJ^ri1?5NS!M%7>Q?xnIJm1$8^wt*HGss_VIaPCWy}O zVmj!*N2zly$MZX3CYWYUG5g^nIaG57vmTepQJKTrgv2d!0Om|WpCn!_$6C&FI3yCU zm!m3YGtNMXH_7pn^Co-chjOIk@GV#3ZT2zoAZoZALmjP(lLI61mzj(gm5&ir z<8>$I``grchi!QxlL?}el_EOZppyh4XFSK^=}abwPPwgv|5B~t)S1IZy^zTS(W$j{ zUJV-7Tg!pz_nlq!nVq2-mjGty$-)0Plks9R2haCZv41wKo(Sjk=ZyF? zlkuWbiJPuJ!-R<0!0YMvWk zK#Cf)&v5uN%L&X!7zNXGzTW6zT?WE50toNa2mh&;5+0n zQ$%TEObNqZLZumO<5)Ay6j53hQ^E{ChDyh=xbbF~DWdf4m=cD61C@?uy(gGqrijw* zF(vfJHB=(=BXN=$W(r29k+Wd3JvwR@yp0sQKVD##ogDS)W|#@E%jWnIJla2*&!OAB5~gR&cf%W{N1yk13%)DyW1p#%0?KGewlv#gxz=4OHUyXo*Le zVWx=E)|e9d<2))Iii##4ZHAd5N)N@9&>ugc(wm%d$C+WKpg+FPj$YVhhJS<<)gQ?6 zHnW_~X4INtCWzfkyx*{Ok`T_mkJEgq8D;`>cn?^Ppz06YkXpm3w4O>U%q*sep*pA1 zJSw$u#;!EOOo0+-t3?s`2+_oJt%kgaalDZ?OI6&dkT+o;zy+AhGL`pM$k#FM1N5JHX!4y1 z_d{`+*azIA;?fz%#}(tT53DaT%)?Yx+%_4jRa7ye0<6gc5cz6;U@f&$8TBc|k5m-3 zG8n~|xcqNoP(_nr9Ut(u(93su+iGu|L-qS6`D=at~W$xVE}fLD2r9 zFC*iNoOrr^Bx&ijN4)mZCq8@W6MxsGPZGK=eUj*0$^=KHz4S@4z4S?->(VE1?jQf` zkKCOedg+t@wKY#v_h2}4dJ)dU=|(N{;5JTtN(B_%1PRRG+?pWZLplOgJjVOx ztgTK3hRbj)VF3{WmGB+hz8ZY7VH$G?wwXCGGd#@nhR#qQ#UY=WqGmcfSKxL}s|g2~>jt&~ny6`V_; zr34m$UO}pDH~|gwqHhpo8#h(w*pfmMS34sXuOybu-D@n^>^Ww$hha{T6yrnxkX6P< zqdpqqk9;&FFKa7f*JIB{`g$Yhqr#7dv>E*E+eM8kXJhXhS4-w~XJ0+)u(e-cjw(OG zo)b4GrAh}mYDhf}LT+5wF8cGzRD2qH9+c6YS!~IHwW;}%n6|Yy=+=MUG!?mfjd`0r z^EZ3`jxcwp?7~>4p=eg$F7`vukQ_DM9CNQRYqMweW)H)wuwy_Bc6fY17|SWq4@Zj^ zwNOJMmFl8MrF*dt*pH$;lN@%b%H3WH*|@dvZ` z*rj{np3i+oyx(4dTa;ETHqp=&t!ZwHt{hQRpg!$o>rg;UvOpCTxVJ(R^=yLjj zzQ9i!Fqum6MQa+j49iqsx@MK)6W9J38I~6xxn|_z3*e@RmElf}49~aH-D?W)Rcu0m zl~Iswc?+#RB@ow+w)zYLB8?x%rr@(-L{7E*BdtCW1|zhXmY!zy@unA8{sJp&n&n5z zA&4(bOT#C&sa8*Sdx3ShJ6K>96yRIqRv?ALBb3KawY-_u_yJbNRBJqH6S4XuvcUe0 zSc4;$KgSx}*Xkd!`t>WY5(_N+qNM)At-%PmdqmtVtllwc)?k!|lzw9@|I}&y5I08G zpx_4#xzx;q`6k%rF9xB3j1F7ft71^P>W6pXbF zM>nH6`Buho^*fC*1!!qMtN#)P*aK6o!Bg34f4<7xrFDqukhYDn+g5Mo<+4G#S?X7} z>5f>NtlWHSSpNm6b+Y@>6VSlnqrtf~P0rtXd=%Q;+BSPcQFLTcF{k$UhW0sitETWf z<$0W9Ma5ykF3 zeRV@^ZDZYp=DPZ5QDJcj4<~+^+TOgP+Frq>71o@3G#_1AG!n-XR*R`>jB*8zF5g@` zwQ1GZ_ap56v@%-XumRJS(PHAyok9JX+N837=0-&CBquZ`;C26DD-&m=VR&E$vvNq*YhD-*v2(_I_!>gcAOqS z78qMd%9*T&0OQNLqMjY7k@{9z|DuuY`Y;Hlv=OSsTvTAZ0q+Sc;j>860H?>6%29 z38xY&Dq6C@5eBefO_y;+R%HiYb+^^+JLKwMavD@KR<+7*C3?B6=+I*O(EZ$5K%D@( zl&Ea5v+GvWwJxb^s=+LA9K<|_INOc_RDm^(4K2}?r6Z#4&8k|C3ds3o4wlSmQRU(A z;Q*nJI0Ntij|t+O<~{SRfjmMR6J5Ti9QMJmg;8nh{S49_!3@@ z!ULZeSj&B^c9B)TP|4AH-SlX5RaIk$^H@XsCLK9HGNEWxq^zL0ph!6{DJm`+5gFWC zhoz_5>V`y)TT)Y#UzT5u30ku>(ptBwfh$l&ic3cojw(4G?gDDyQJ@A3M%As!Ur_@2 zo4c@>v)efFapXIr)HK(peGUeO#6I({z}3e-KPtZ&6O0--OOOLy%>rBkqI7|v&ZZnm zJ1@?&xXKjT~Xw@kk;vG$qM7SD|Oc>f9uqT$4>jw+pTf2*TKdAU<3A^UPL z4&8+YeF-lL`#E6tJ;CTs;&H5(OWRKtx%lE5>1?h(q1E%$8jQ>SE+bNtc%A73LUoWj9XZ`QIIF5hhMgu$yT#7yEpr>1j;d<3*LsVO29@AlA0 zYTQOS-M4VG*4E)rYnjm8rmAl*ve!^oSLZB)2bS(FwbWVsny8mVqbHcvxZPOQjzbv- zY1JBDBcqL_B~|Lu>8u>C9jbPiAkKfUK0hb)OFw5es~mhid}yUVs$Aw2K_#M(G}R2@OOifzi)ezNk$6mDhOo0mr$tJLC()sFM% zelpkxD-X>5B&*`oTtL<9o78PSXJ=h)M4!CX|FuT!K;ULpt6* zrX9BooYeL@eX+9`4-2fy`1M!p+fVcC69i5l_IiHKs;VC6x#hofkw3msaQgfh#%Bt$ z@wwIbVBV<-r}UQ-#o_d&*BoFl{r%>tEV0@6*nKW zI5sz)wcvHOWAmtQz4+QuZ+PnB*xYy)=-k}uYq)rfo0JU4=Ee&R=Z5b*oFZxiPK{%8 ztFO%B5$=6z=T@tPJJU0a-VoVp_CI}suwU&hg#k=c=Lr+fqu?hbPn~0&@$qAh*8u(M z)rHPsi}@`*$DZHPf*PU_ubvgMd>0Z25Yar&3F>jEiQ@$M8iMi+LG?{MhbFD#fRsJ>N4JYQ)uy;1N4 z!EXs(EcgS#I|Y?na^!nTWPU3|JAV^Q!gx_WLU6j^ae~VP*9x8~c(LI1f_Df$B>1f0 zcER0(CZ;~iOBE~@EEiPYSR;Lr$SVY|5d6O2U4l;vS~x^#H(jt;aGc;Q!Kh%9;E95F z3;t5@kAifWPrDvG>?EcM<_H!EE*D%Uc(&kWf;S1?Blwu0TG9h{cZmFnU?L_w%j+XJ zRPZptse;D}E)yhkl=;pUyj+m%2*%$h_@v-Ua5xyhLGT>GD+F&5Bq^VIq&XAc7Q~m4 zO3nd=h4ICL;|1pkRtvTYo-Fts!K(#t6a0nXGlFjlekkb0xq#(`1o;Ub0jo|kMeY3(p)8g+ zRPac_R>6w|?-6`O@Lj=A1pTf9F1S+gBEjnfZx?(}@K1st31;=w_6`v|OmK?e0>LGMs{~II zyh-qG!IuT;jhpoxC^${9Mew_V_Xz$<@IAp)(8ZX)RPZ>#O@h}6J|_5k!A}LbR+j2t z!R3PI3tlOBBN6AWTLgbZ#9Y5e(jON2SAtJU{O?76S#Z0=zbEo;!M{qp39=OJT7rp0 zv@b*C-hzE4eu&8Vf};h?1!oG*6|5Gl7wiyRD|oTs<$_ldQU1*$-zs<)5&dx=5y#*Y z68~Gl7bX2Q!8ZkWN%{wZdx@~mjrMRkQV5d@F`X5L1=YJ>=nW8gh#+Zq%s)m%}$W#Ul5 z0zq{@g!ri;~)nZC(1PhJ1v>=K6a0?g7Qw3p?-Jyfs?7ho z;9G(zh+}-ZU_=n?JQdHcnV4Q8$n_p6FBBw~lkzG-+2<8dSknvIJxHj77gRkUk2oLrP@JPD7V4r{1x_u6zm-U9jT5W^y%Q3<TY>^}UJ9BAwo4 zEw|s%`M@&0!sw4XE0^8Z`N*+9>h$-ytMlPwk&;;2IZ>q!>>PCL-#Q;&7wSC!um|7w zyWP7td0abB@jmpv-}C%?#$gv>^-$N&Q?2hJ{M>tHpC5PDEGzAtG<9X?gU6P3dWZUu zucPz2#JtXdQ;Rz%4Q=b}KXp`R&AN{}m#k~+bPw$SmUJ$jn%8;#v8y|MiLISi4Xy1Q zG&QGl;Lx1T>!;Rro^PIKMJ&c(-ebpGPl0jSTY&Wd#%o!0`bb#r?xgpOWs|q}S?)GMH9JL1u9dEk$S-{W#UPaMb|^&lbUkB6V0 zdnRH6xnll!=0REc<8j6O@tg)NIQgN+4EWvI$VU-=-=9#D=YAF^?sw>Z)Gh9Ju1D28 z{FcbA-S6PD?l6nuV*{*(`aF`o9^Rw+c0Ju97U~9O%_%6RQq;ZTHU|p0wVNHRh58xG zP>YTgr7?^$WGz%(q9@4j;IS5}7X85=q1L|QbS)+a`Nb2~Le-+Z7OHYfjI~hV`voSG z&c#m#nxWc;vag0ku7yhPj=`BY4`D4-ZNLc96C~C`)uJa@LGf@A{lP_O3)Vul3-7_Y zj1e&nqgSAjUX03){RIwH+!|e69 z*ay=SDAFlI@KPopnaGAgb_ECFJdL$bwR|f4WUNIBog=Fz!_7`Ts;1ULorg%>--~)O zOzTTnv#3{BMZ4L-TBygWRPAO5YoW5U#LW&3CoRJdcPRmWGa$gt4j&V7Ez~U#gI9CJ zSEVw{f^K28SK9?)cqVcxBqNn;p@uNEWGz(5AZwvY#bhm1EonD9SPON5nwZJK-7KoB zn;qZJQd?EY+RYBuLe+V-n;oo$%3iYF>|ia_pJH_BW@iq^@zLzpm6#Wt#?E~#0B>nX z9UP=L6Rd^WUx~4`P<27EwNP~fVr!x5az_WNY3iBOK`L)~@B#M6v#Fz$7+VWfo2m%X z`7hQ&)p@4}&qY(P7V37@-dVv{S;<#=mZH<>W{2NO`?e>qP%YAKc6@IJc?8qV4nBx7 zuokK|MK?PPF>8kUVLxQ>d3^@sF)rhfWHG5%IjX4FLS^qLH#=MlRa-Jb4eSiK*|}6T zLA%-ETBus~hi0>2xY^Nia;Tb94Q_UH{*(}}##{^aX|#rJcAjC6z|D?MFAVY99Il1> zCzW0jDrI?av!m0?LO~uyaI^D?N*^7fzcsFfs!t{5p(iQB&5qWu2>E#c!_AIPpB%c8 z_TXlRtHrx=r-x>;8{uY0>(2^(Oc`!=)XNOG+2NXpKDgQWfhuo7h{qMzLgk^P-0Ymh z0^nwc$B1&Xvy>5Vv(pnfm7ASAaDZ?v)Oje{&9zW(rVY5+;Yx|_T;*nmhk_m?y6tfc zk`h@t3=*CGdOi0-A>Hg`3=BF{8D)>>+e(S~IBnxf$WIsF%B>D(p*onw&CVoS#_>#N zW?T#PT3~oN8lcuf-3*P8I(Ng(4h0nX0DdK^6=_)jpn7AlqLW@iLz4L3WyOmHn!I$+^isJa!CLnB!=xY^mP>}fYUTnlxp zs_KH!M2<4t?C1k-Y3MbU2RA!f)^2vV7OIxlgrY1DZg$3_{Fs{^u7%2T4^OipE?~*E zP+5bRn;ou&N)yV>PAkiVn;jhiH#;}*V1k<+9RW8xFR~SIv!f&6W~YQ%;ATfhz|9W7 zGv`{Ux)i$EISJ-jE7hlPvqPDcQZn4^P_DLRdo9#+5fQqPeF`@_6xip-u+QLT=X*+q zn;o7MDJWBLv%|sRfh4kC3-xJ4Wb&-TwNN>@nd8}4aI?cwb@|)vOmMSPj#A)ehf!H3 zPXlUpV}kMhiPyseJe20Pb+O`~cTN<(Us3J--VJTnkk# zI&b1e>^4-ZFFnj?|2kX*m2Y4A(Fxeb$OEuuM9T4FM!3!#42IFYTm*G46im|}g?%_L zOuGy^)_I8YUxA+l_}96UF;_CCjXH3tGlVg>A;#@bI#dPp7{2!^)7vlk!I!q9qOpKqlgU(5WkaHw@8!mO2 z03EhqEP|?Y;Qyk4Dvx6pz@-l3MWxDC8E#m!sq$Tp!kjSUMdegmC2CmhR0**EjtVng zRBo_Uwi(vNREbdK*f8To<<|(R`ff!3-9w#mY}2AJ6GZ3Fwhmpwyh0tiii1lXCWuZN zjuG8%xP&41Am?QEUwxPfqBAO{1K%J6sWY5?vnsoji6OC5cz?3qSJ(+>OTzo zBC6EW%sZKk7nKWa6^!~xR5_1FO=l+KG3t|8xA&c0^$R;gGcEzlz-Rw(sl#}&`IfEn zXTy4qD(|uvKFwsjs3hRYmFmq`(NiBIKKo>r1eZEY5v78d5>CI_5VAX|1eZEY5v94d z5?$(yr_wGq5-xR^f-B`7b_-nU=zht*nstFo9erBOPUj?tOC85qmM^XK8L6LPT}X>` zlS-F5Oo2t)rH&TWndSG+Jila~CiWv->M#X)_~wHybwpHdMBq|KA0*j7U;%KcqmLl% z-~=vp^kEWnsiTjfm`fdf@yOoG{)bB)$MuG<$#n~kFs!2>WM4)lxYS_^YV$Kz4lZ@1 z)jT&|h7>hdKEvV9EW?=vE_IlIzNXIow$4Vw`XO~5VZGr}hY6zd27zF7MAwUS zslyaes*Wk4KW0;@A1X?hI!qCzGh#~Uk5yD6v578qn1cSelpPJ1I*u8B4^mWrAj?h6 zGM4=empV)kyRSHOo}|v1JlNn;hY8T(J)j#@1l1q72etk}rAbtROC6?&p}|h25QOYw zIAh^bhbd6vY@Fd#8cn4qIgD_r!xXyIc^0iQr;;Ryhid8Y>JcDsN&_(9lG@7EH&1ZFQ7ZX=n1lTa8_o z&sgR8tEa2t1X~ejCNCB5#}3=mh%|^XnK0zTN{orEY58$|ifeK@|V4xAo5arXUi+7SHZWNl?S%N%GxR))&U`*J!=ACl8GOV)=| z;ADiluV5c)*Y8W@p+5Tzj#Q?z47&z7TN&G_Qzl8uy{uc#R>uAnJNui+K0*F{w2%v7v#;qerQ1bHKEKRa zs6IMgh!3b6J8JPU-#_1R%s#GZx_qFb7qZ2Oe$GXT%jqHo!_1HQ;NAqGn2QvIV=hu~ z;;~(%AX;3c;2$XxtPbul#f!-lcbM{j?0pG*71jOy%$qlFN%BGhffr=)LD&QmlCX-P zK@bs8*+i{q2qA$eSxCa7)r#U?TdiwdT9>M|XsdPCy0osXOU1uiU0b&<|jt^k)i&O3TUxFBc+#@DD&}GG0gAcbrLy|B6eYj*PALT3#1LI zjTBLSg*qzl${DBZ^F_I|5{EA2+V|&6TLQ15Mx3moDFd(!N)A#~Lvd=xyB}wd= zNi6c(q;L<-oM$SpFpWcArpWh;pbg{t`Qv=IJQa%Lt~&VbEk4WSw}99k9lyQ(j8Agq zV^)n|sMBo|2iYbL0-YSFlZot1&5}9_+O*Zx9YSfAg`yeL)L63wKZu>` zWmJZ7p#3*CHHa!=b41(~Vu7g%t&OSO8W+?-LUdsYDuK0iZEcWtOpPh6EUy?-x^zTo zW6icp74KI3mtsDyajb8+;(m%pD4wi%wc=xn>lJ(Buh&aaS5Q^naP&`ZV62+^C$ak&cor?D= zK0rkIC)9pg@vj>Hs@iWVeyr$rGxZiI7Ack}4pbbaI973g#RC;Z_XF)Ws=ZWkIT7(k zseP;>F4waCxEyTqJN;sfmsf`vr*gGND2`LCQhZ495yhtzpE z?3CL56v_HwzHy3sC|cbDQhu1u4DUX-|0QS`=O%Y6n=?k|A1Y5H@DFDQ1@rf;wscCl$cMMSW^V^AOW6So(qVY>cTXx*DBh4D~4^IKEvC{XUnikyK8PmIM~0F1KW#BdAfhRK49}&0J5Y|S@77m z+e-`_9?l%(t3o6Wo6YJooPpzSl&M<&+xiM&1%}l*AN}Js$u2hEu*%^hQh{Yl`V3=6 z4zD!Xx2(_baxZBut#K8PN4UKs>Yr*nl?`G0+lVIC?SSsU^@3BStNO zHxP)Q!Q7YU-Og~5;a_!OypzMD=wqz8%h{gwkiE^52{0GDg zJKkdS6j}l->OF+~&=UAD!uer8yc;(bS^_B1iDB>82ti9=KcpAXBYZKm1o#5t}P)mSM9THEYH_#F=6*!4Dc4e%Z;Y1w8pe0}%r;~MP3E0M;K?Tqf(8d##hk%xV zF^durc5N3mixX419aU=fOq8*z32LUC&Xj14xzG}zMpoh$wmU6H^s+GO=p(fRX!6U` z1fMHFOMn{&JCrzx*=MQ^EdhL1fQt!o%O*oh;AMnGOQ0CNFynntXNI{?sg?yT0n_hr z;!ajp6Ynjlu>?B?EddUeXbJdXR-99YWUktRA07b%S_1s4npy%2fC-Ofmlrb3hVbi= zS_0Y-b`Oub0zQnPmH;1$sFr{hP%Qz?uUZ1eiY4}C-8aWaql!>TUZM(}f|h_W^9!pN z)H~1;7$q$iBsdX6OTd&ZPK;sMyJVE0C6IWJ<~_Yc<+LP~xRF)e*GnF1l=MrC;b7mN zxF0(VS^|kF+;I=YUlB8{C14s#YYCVQNNWk0cE=@nnm|k7H7Q$_;MarD5}>E(P)S-# zz*IFU!S9}-C1A=&T0aKHc ztVbbg2^`1=HYMR?Z#D!i0b|FKPnh)H#?DJpaF<#FrhGvX_YqJXnU*t&2+zl-O8aT(3lexXn5-=kePVy%awFLBtK#SaPKg{Zj z@mRuW30%yo{?4q>5}?7Vj^n`wEdgUkl9$tlmcY&^g;O5iMIk`J0qwTY5_lgsV#$9q zE3^c7HDgs2=%bc^*^lAmk?bY31elpx0y|>ksU^V61hoYI&V2$c0kaiTlE<)X&=RPZ z`er2eW`1Z1$OF!j{gQluOf3O(!YxkDVLG$~jNOvVXF9Y5jJ+~B3}Z+w0SXRd26vPE zgq&Ie-6R590@t(0&=Oz|L`&dGb_rSntU|N|cnzkOfQf*Xz{5n2K@Vz0#a&1j5H1+t^>jH6$kB}h>>7mqFi-TJE>AvtE<7vo_v3#KkHL2lkPhI}e}1|}EdkDa z_}c4Hn$QveiytQBrar+ILQ;TlMS9O(238tX3EK78?Ry24UZm# zp2usVem&y)x&u(RTN>eZP-Ddj9pSj!=i=sgw&Rv<$B;V%L(2-b{E1YybMSD+ZMbh8 zgh#A{@MyM!@L0Bk@OaSSH#%k=gy&iZ;d$8(!V|&#{7fm|I0)}#{FDE$`3c8pr2T4h zH2QABIe5<5yULeXCF+D*e2MeOX;?^#a$P$K$z|f+_5bE;g}`SC zW%$6L2%jBH3(*U9mTw~QYLj+dm~q6XZk;;#_=0!4EVpVCznG^$P-=!U0 zBC|L^G7dPUDYjx<_ynBwv@gULylIb1ZOa?rr_(x`vVMf%%u2j7snf-coCtCQGmh)5 z4GiVYaAd7E&&q)y4oO<&c$YPP#eb?zyRr#+sjGcEO-RllTWQ5#%it!Qna!_%}s zG3l8dNK&4#3z;Zx)@sCOA0pD8^r|t&;6fSypVjsF-e*YzeN<(6h{cW+=UZw2QO3`d zI38Q9-dQtV)l6T6L|kpWY>6+hYU6*?eo;XJmi6kH`N#sk!IY;JbWMo&0_uuVk9ibL zyUs(WTHx8Tz5&i<^^B0$2x(Vn#vPVAF$3po;nw+E%{t66MOjy=)^V9Som3WC(6^iQ z1FLRp=}^(0Hw{fVKbmUmGT&h|%IRQ7xVn)}U3CbuoQ7H7TjJZSx_Y1K%}tBoSuW`H z%+3PVjoBvs>hr!WOMIF63mQGrm=2--%~h6ke8gjaHqmGR=}pJDB@lakSYaQ<8PM z$5YC9TQmn<#x0*ZtE5w99P7b(xMd{fCpi~+a(qJ!Lp~e}`X8fh7v6$>8~uyniFshb zkBGnmnUjFU+d=%=3M?D@7volD7CeN`7zlX|UYG|KFY8SY)A{Blv(TRy--q&N3~MG| zFnziQZ*jm7w6j1u8u{_76F>Hp3y7{1(gt#yiNXa$#rOOm#5 z0D*j#O#2W;dFK!NY_%^_d|L4zitj7RJAC99Ulc&$00M;r2ow$=P&j}<;Q#`g`QsWW z96%r+<8~oTSEPz3R9fu!Z{v{Efy72N1S!0D*ixz;ay``zwxA+)Z&G#X7}h zipMIRsd%a4^@{f>KCbwR;(Lld4sdB-vA^Od#oZP6Q*2PA_$bSDR~)D)inxfUKqJ!^ zDz+*ft$3Q^ZHf;mKBxGG;>U^!KB7Z?y%b9o$1Cosc%WjF;*pA{Dqf^0zQ9o5U1~q3 z_=;i$9tg2L3Vag}S3FVimx}8Y`TLmpx+rd^NPQv3S1R&HH*Mhr0w<|GP4Rn*KUaKR zaf2e~7;;4-7I}VSj0%W|=R(BcCTO`aMYIz*ZZ-aMaYNF6JF;%Nf*g&_Gef>5RFH3q z2Qn06j%iV@B>;K1j$NN#xUaZO!ODDgsX|}?_Oo4V+9X8auyd+3p$a?oLR7+c`aA?! z9}Z)O*BDy{L8l&dah|q|4b~&VhMBe}j*}Dvy4bV@u!HUX4bOvk+_7D@XWPZiQ&xSA zsE_&VV(VLmh+uth2kOJ&p04kQ2-`BO;|SC@4fDKRY})aN2-ZiPF!qc6<9OTtosBTd z@cjmtKjM~QDdsi1FpcZQiZ~a;_AiG1+3_RV z{@sc&E;lUzS=OSy5!L{*O)kX1FgW2P>O&;Ybz2{iZKA&PQiS7WaN5e$$9tP#zGC$6 z!A;~FRyp!>`O6qHs=Rz_`51%1wZYPXkFk3G>Z4kAAA{r9Y;V}5&~M%?-OJTjV_+ZsE~g=qCz3Ora{V~7;^A34rEH$pTvCO=zOGrm+=}SJMuEd zvD8aQfddG>WcF&=z|bxvTi~5QCt7^z2aX2cy!qjq@ISH>nsL3IkqC|k8}sHN1{@8B zqkLmRj>ak&!qM>2k2nRk!O?gEk#Q0l!O>v6c`MfypkJ3a5Pxd>xH8o9F5D6Mveyg5gaU(=)|zM1|e`X79zcX3@&mso?#m& zGNGai!)QY}8m7f?g7-w=Xc#k=_z;=E(J*FS;uA^jVNA=>ctI*6M`Ia6ISu&t4p!MV zv^^SalcRAQ&~h|P1x})c^^J`iGn^o}D8A}|AEd)oyn0bl5*m!U>j9HL)8})&s zVa%e0hl2?m4PzE3e!|REYW7S_W>pi^1VXI zXD|1X4TBv@%whJKYLla}4$nDIWSGsCR?pX^z6#B?;ASjWn0 z;)W^^OR!_$XmGHUqrr-ECZiBnZ2_;0VSuA?9)KJT%KRpBS$26L!)%DtB{&+|5Oz;F z4~1KhN{+@lY?N{|w19FnG{15*j1@~zy%HRaiKv1cjaGCD91UZpIU0LO%V~~=DO;Q< zW7)f8l*rK#F9G-TIt{x7{vHzlVpaEvJ|o`OCdhmON8?3F9h8{Q9rr-|V=>bl4bxDX zqhU56&CxLJj!W=d14qN-?Pp0Ky((0a z=4f=rK}L>-(1l*i+XI=%(YO=a4UPuSU~)9bF$PD&bb}lXhFG+#{NvHmm7JHZjK_ZI zg``eQ>XyRB8;%A?C%KSg0gi^L$w|_AAvqe$WD~+k{_rA4!`QK8%-Fq+otJ!x{Q^hB zl+SQ9euJwC{XIa)TsRsgy*&8_ZE!RUhhju>IBjq=O!}DQd$hsP;7iz0$+)D@q`=WI zQ%O~_lL9#VD z8gj#qck?{2$kE`bBpeO?q9jLy=ZJ7Lgbe_W2Ic34qcMtAf}>H6Arp>94@Q8aL9u$} zXz)}pJLyJrIIxq%WaqGx7NVRV{wXpPx%VT62WTKGqwM~?OER$>58F&8l>a9pgpW>Qks~Q{H#izJaE>Qeasa^5Fe4aFUd*E4Xy_4v z7P;YmnAK-E8n>{jQXX93XwYC)t7(IyVeClqQrh5XOvQExM}vX;ky*QKI2!pF#^gK9 z3XaAq$?7Cep$(3P*^lAmZ`n(5G?h+;tNSINU^+M&=7d|ET*CUm(J*#Pav!FHqhaio$)OlSax{9&J_kqRQZ@*V zMwvu_qj3#;42}kSARLY7c$k2r!78#i8YTi94So?pj)sW{a5PLrfTLj|z|r^t`vs1M zX@wk(15pWkC1VPX25ojqY;ZJa?`&<$(P%(KvIpw|M}r1;AKvr|N8?bj!O`HPNJFXu zM}s?uCz9HRqwyO=^x&*Rjs|ybkDWP|;ApT_)Bf$YP==$yDCJ^s-ogP!76#Z(=x$H< zO@!^a@NbDHAu5N*U`~#909=Y0Y!)01)&P#iTAJW!6pIOthJ1<<3t!J6x&w(Bj>ZDi zvi(blIx@D3nVry3IT#-y@@Bj$ZO85$KM@%j_f%s0l+82`V*(7tZ@Ob z9`W@p%SV*9wUjQb7{!<+%{A?%5I`Oe&dWkX)U?(v9*?7U`RKaR#v%1BsnSIYSJbrD zmsX}q_a2@qt#4{B1gPL0d|66S_^$M9L)4c>H37><86RG@a;9T4p!gF5)GcCzB0inA2wD=t!O zQsjFrmRqfOg5nv97c2f!@n%KK-FQIlCl%jNT(7u2b~Eeevr&1MtTDt@Y%k6)Xtzn9`r#hnzVD(H`6;S@}pMT<%&xbzpr?XBEL9dz8e+q zReW6WWyRijc))z6isKdcR6J0zQSk`HA1VG!@z;vCDL$n5oZ=gbA1l&BA=~9!9cf>2 zyy9Mp)ru{OM=AEh!xfgRP~1gvZ^dfG!xc|bJXdjz;^T_1D88rYlB5ZI%I$mw{x6P{Sxor8RAi|fUTe4ojs z7Tk*ECMf@HzN=sb`}ZvJr2_fv{=EWm!SS0O*j|p09lws8j{l&(;IU=fBH}WbUdp$U z(?Jf<;B=`>-#cSXbs$3Gx|BCYRQKOJ^%|N$Pj(})s zc$bTJJJHhce$|EX=1tuz2;?$9c^cj?;tA~DL>Jb1X|x8>cwvy}OLL8Xt(ajad?vQZ zyTW79Fts$it9tMNB~POiCU_e2QKA#W;WH8PyLF$Abfcx=4~t!aghV?ND!MR?HptWP zE49UN;uEysSLW78i$+VsuPicVUgBRYTG_*x!qf1F=l)hIB2R-~2E(bPx?E4efh&d=RmdC&Yar%i2l^C9e|7UH; z@HG5~bps4f!(XfI8Z8a~(ZWZiY*ix0svawRNle4j@SoJGjFyJ~w3anm8vZjmRI0H& z4gdMhFQRi+OT&LLuRC@Yc^Z7N?!TPRGuUcr_^;@}MxF-uHH&tYe>_^c4&*<^W52wC zq)trg7Qw$kVSj!o#?eVq7{>=sgZZ#WMN7j6Ph&UUJgb%l>>^_uEe+Vcjh&bL6Z-|8 zhAD4&8vend*bjJ93!Vml1o_a?FzMyVM`?qnAveLQrQw68VbaGWpJ6(98vK-=JPi`? zeeg8QRARI=eDE|({z;;7;De`O(v6me51xk6>M&XwK6n}?ztPh0!PDU2kf%YBJRdv_ zxj6?<<7Ku7o(4~)w3dbso(9j6w3dbso(5ker?oVE@HF^oiC6MBKgrSe!PDT2W#wt` zR4_Z~c#L{rCyB|Gqfky} z8JPkb} z&>}b753_p1)9`n3WBiepOz_|WPeXpOp{gd@;At2;l021mM=cHhtkZ6HU+b?5MW4qF zSMphA1y6%lGajdh(FRY$>_?-e;e)5a%;aedL2rEUGCPK9|eDE|(gz_|eXla-Te(w9Q}8rsvr}S&r$IX(N2=K5Y53=aphbl-e~fz`JPjHg z^L%b2v^3-gZ3%c9oYiSaQSdYtW7BvdslDCX{trSPXM!G_b$swNxO02tb1cErV5_G6 zAKOA1o(7|Ox|{~&=*9tdF2a78C%S5E)Sx(GNcl2K8#z1%pN1(N08fLDR($X@IP-z0 z@jIH}Y5Y^n4q6%{of@7-1X>#W(Y^hj5w%Gz4U$PC;AupV3p|Z(Xf}F|TlgWG?%pq2 zAI-fB38ZF37e~8JKp4YEYDTodnxdrt%@&q-u4XY6-b`+^!3kXga8y^NA9svxpO0SkM=q-iH|&ID8~G7O1r zvK8M}UPKo8K?oWm`eWKziisvc*Qt>v$KPkSY_=#dZZ+ubTc8cYS zV-+VW&Q@$uJW}z;igzkLtoXd*8;bu?%*9=sw5Pa(qI^$}evmlL^nDfU6x$W?$XL?P zP`qC8F2(<+C_W`n55GucecR*4k~maxCq;STfp|XrVfxvM*DKzw$j5t3e^K!rMZSn) zJYQ%Krztilu2kf6aHgN7$S-+lU#G}N@U%ZxOyH3O?OuwdisKdcR6J0zQSk`HA1VG! z@z;vCDL$n5oZ=gbA1hk!LvK6*U_XW_Rw;__D#ZU=ZI_RiV0Tj7UU8V>bj9x}9;|qn z;-!k$E8e5{Ww{S?@j!_ETBNvAQG8b+{#>=MP`p*~A;s=^^1<>uC@xf_vMS?GQG7=6 zRmG1Kt$sxmlQi>N4n#`r0g6Kvhb!)?c%0&6iZ3d@O2oc;QxUsiv)qQ?@%%&nBId(8 zVZ7E9`^)N8a5mh=Z7}c7F(t?neE-Y{481HvHOzg*h52wuq!*m}vP{8$TZR!;So85L z%Pux;5+ZPzNjlTc$2)C4dFDHO?CSJ8@;M0GG6*_*p{}jrHjLa#Zo|-?hO@wSaoVKY z?Z|D|XDhi4;{x^J@J`qFLxh9dQHT2e9Eh;NTm`9k~q)(Z2^bk#AV#j-x*hx1plEvcixXw(LKoUq5Lu z&21=#H*x)~z8gOHm<>n28=8O2hGW(pyJ7XZ19tuWzuXb=o6B!)+1+{> zk?YE58KF=_EX&VGYpOIy3 zE!)pXEaPWn1%ajs^UTkV_E@_!&8o=>b0@RJ@4={EQsJ5fAto>CEy0 zKO+=Hj0OCRP-HO{@H0}y`~g2BJg;IwKO>765%e=cN`5TpXN2Df#K4Wn@-q_qcKaD= z=4M+zBmBZYF9vRe_!*J8B;aRcBDXi-XN0njvCaA!iGdq&F@Cfqd-31`H-ZLVuAe|V z;Ae!dqhlSp5p+eN?h?AMje#2>en#GB)_|XpGiZYwu?q&DjE%$D%YdJeU3pvt{EWQB zofPmhLSlX_;Ae#5i?M*8k$bt70Y4)LGCkmDgv7B}z|TkpuMI&zBQ5L@xDnlOB9MZX zpr4Unu}dBOjKqR|Mt;g19sP{NI{F!j1^tZd#(sS{KO-@4Bj{Qr`64$V;AdnI zxAAlN8Hs@#!I_{3XPub!Gct%{`G4YPq>9aE{EYBxl338sNFGKDT-Bp6&b{wOqTxow zt)CHcD2_}WfYc5e78JpVXZ(yLkuN9hXCx=!XCx=v&qz+TpOKt^pOH~$B`4d@NKUq& zk(_KlBRQM%Gcun&O8XhP4m;8v9^rO4d}7JPoq*e6k|RcJ$B;XtUn|lfZb4@$?#%wX z>)kScb-6p`*5ZfafLg>2n2Ub{QK4x44r+ll8O9{6cr?ON_%r|b0|rHZgQA03ltR4w zV;#&YS`gsZTmzY%Ii;#&5m=2?tLlt^%YXP86fGQAuMwjWYQNXktu86m1r|{qwuzdig!__lXp`v)lsKqfC>0)RfIM31>Jc z+ejzhI?_qxvmChegGZPAvAH{?J-YPo)0A)Qwu%8LXhyyg9Sg!FzP9GuX2>jQ@D~}g9$gg0S41ZIOIvfAx|P4@;&dAf>dN$#0|TCuJ>NEi@5D0 z-f;yfIPEDKCh>8``(C7kY2NArge3_X6PaAO-iOE)_X<%mQsGA;uI~=;{m2lsv?rdO zY;*my3?!&6yZ-qqnNcFnFuNV@XePsrjkAp?RaY(EMKCVn{{`-M7H{6~PllUg&S1E2 z`7d$=w599Gu#TG#fhss#3HXHiiaiE>Ztj$NMG`tl7$oymt@~Tqywhzd=zzO+y zz;vuTGv}VW^PLH~y9o?O!ncfTRTSvAdBd5B_`lbi>6~dCAy2&fWTHH<5b)}ex6m@i zS^6`9d$R!b%Eo5<4Z{0hzN;jk0k32QyA$y%s6P?EJ%(yLcNz1IRh*zWS&{F^na;-* z#082CiYpWkS3F7a6vc}af2nw_qG->cK7PB*dS6hCV&iFdQ{=l0+LempHwgADwfWsF z(+^P;zd^9iR{JtV@f(DAzTap5_Z7*Or_I-eL_Q)XRw|0$AlQ_zX1w?f0*c=tp!f{} z^0P&zi{Bt1-$~FGzd=Cp8w3=;K|t{v1dQ>a8&LcP0Vk}airpI ziu)+mDK1kyR`E>5OBJtIyhrhI#a9&HQxv~JY#+ZEqLdgMgwv0~EhOK=B&{6u&`0@f!sE9-eZre(@Uw z6u&{h4H_?+GuU_5Z;)s%pig`f!*Z2Gq>oaZt~f(+e zd?^NWv1vSag7p=Yn5Vt057TD4zT*+LWe{}EMSb{7FE(v8VuJOh z0`+kiZU4?e*p^`>Yf#x!n;4ffkru449QASg*gu?F>H023nDv!o<+8d9?tgfq>cTXx zS1a0lo$$nYx#l6*eB|OYY?l*|Z&Sz1&Bze!--jN?T1^s(^6ZwV>ulSt&z>(!6giyF; ze&Ce;(qIRE;MMC3Qdh6fpK<1f&hK8mzH`-S8;afytvX{v(Yn(&bOlTBylW=D8lE_D zzGVuohW{(W6TBSk6)5DTePG>!DEPp- zm65;3u!1vqAPPc5iEo>|6yx{q-Xc-a(_w)>_-|Sr{bBL8+j|`;VfBY~7HS5Ua3-QW zvfIMtMGK{1cvp7gQ{)G)kVk|cUW@;cCS-EGrAP#?ke%>&3k+T%!_g?>$tye=Ml1|o zVK4MA&YN}c3VCgclUo5^A>)ne2IUlTnV*_V;1$wkPNJT5UK%|X(cpR{*3w+#e(~Zw(ZMTZSlDET zfGVghh7`95;|X|$+IXUb=FVys zC3f*)?xJRKg5Q~dS7Fh?DIbiga5>CrdV zU)amNWW!*G5*M@ZOtq=G)QE`xAh&EXG?xxS*n-|1EY)0M#W}2ztF{1FJuslTL;)xA3dzDv6tQ2+3mIlZI0M1zvJGMP zlp~^m{*TBj%*A+7a|ygcEug$Y?U?ckjTK9r$GS7Vu`WfYz$=`H8bc+_0qD@ zTmrAqlr2t-X4$)Bl&HD%J(j(v*Bb1S5Hy#B1ax1o$HnZIAT=1g!VO{$N}R+U_dvXB zl$nj@5_pBCp){}1Y(SbaoHhVj9gQ@Cr>;lM=%3d|LZF zJ@GorK9lo=Y@qRt1zsUuAfp>|68YFr@Cs{?iJD9A(R?|dXD~IFifF!~2OBk)*dZ3} zD*t%2bZzE8#$&&XL{cXvb(@WiH@rfQPV%Q53-Ah=4|_DZ28GBg{E=)zIJuf530|SG zV@V3$!tQPCyks|)2d~hSH=0Z272b=hA$f(QEt6Mh(#w-6+Tax$-&G@$92@cqP5PMR zAf|&?_@?ASSIb=E<<@_+Gq$2l4#P9$OWM!1y zpU+4pmg8ZY$%OJ$KoZR*9))r;tLD;9*2Z;&(pKaZ{uEfe2RbLb!sC%6DRVb?g*13X zT*2)HuaJ$A!S^_ef>)?V1X|>V`(ajZG?&OL{C})!K6hr7+nENd5^5cIg~pB~UtoGi z-&ijqvv%9?3I||UCQH#r@(Ou1V^tKfBCpWw$FOK+kypsf)Li;L28g^uUM8ryG>uyU zUZL5FDalW`72p;AKE2P0OujV#_SNIdLp}E9Kk%m+S%_Z&}o=9qM_cnQj_adSPXC3kixpR9^ zRgAnswrbjc!WPPCE-^}dU~%5U0Y>jvkoH1%d%8UN?75JKupg!)x*Q&ZePK!mpt*Dm zn+30sH9&JIj~f79VY!&lTv~|@0I%>l)YHDMjd?94gnTErfUz-p{`8q2EW-Z z-AKL@t5(IQC@%l;v5{MqI}TZ-SA1MUTA);Aje$0&^on=MuVV#$i@lNuPyCm{imId< zkK=$EdF5tuE`rzV$??&2P5^7SU<_Z0c4||IxM}S+{y^EV0Fuxu8 zR-cnG}){dRm z(%QVJwWcvu->{^vEj8#n>~PLJinspezBPPAKexZ3A0CsK8YC8e(5ke=V-jVV__&97 za1Eu5_i5f|(GvfITyfMF@w%q6X^Ff17tj((k*OF3l1%+Vcr|RSUfJAI*F=(5YkTvG zTJT6g{xcLBczJTZ2FG`wlS3v4o$ZxznU{9JmmzSGY)6+;^`I@bIn|)c)~>8kR%~Wl z+m<&#Zfn7kL)sb+t8!&Ea98n>LsH_)Cm7}_r3N>O~k93 zF=dry72=w;qOxLmYEWz4lDe93Et^1C$8Pjr-9cYbT6`%2& zA~E9EXO=cx%HB2tc_*nH#<|L2oV1O@$UA8MWXLQV>&3}qhIEF_aTqzqo8T~ZbfIVO z^1d{OQGQ9`tV&ibpA0?&2A0U#NJc;w_4IC_bXd2P16f zCB?TCA<8T9g^GNS!hDkz=PE8xT&Z}p;*S;i?uO-VQoK*`3B?@z0%Cenae(4T#Yu{@ z6&ENjRa~WbiXuf;Sl_P|Z&iFyk-xZ@{;^^%o`})jPH_jtF^Y>6+Z9(Uo};){@vn*> zE9T(`AnWBDHzM765O-9ZqR0o4j6YrRw~D`4d|2^$Mf%8K{{JYB!UIRzyD9FYSf{v5 z@mR$(6)#o1Uhy8q#}!{ud{6PSxQrwD+=}fh?xR?*NPQNjpP+b-;y6A|NBka&R4$;s zNO6VY8HyJxUZZ%Y;v0%zl*`x%vIyHfLh(n6KUcg;@%M_4D88t;PBDz9%&e!YVvXWb zMRE0k^qbXwQn3V&N?6Wv7$>SN{__yOx7rI77b`X?wkv*L@g&8w6(3aGF4wd(NU@xV zeLF&N3=w^zo*4TxU*qc(8x#*EBHs~;$0?qqcnT5qp00Sl#$Tv-g~ng4c%95ac0`3YD*)H4Tb`W{)*fIz@ui|7)F`$c0f`otdwFMV>$?n>| z%LcrYxy9~m*i7SkwW7^;-F92Yp&SbGFOM0!uw5=UV-5Ci9{R^|VgGn%Z~J#Y!nplv z0mw4HLw$BEh=E~n&Op8tBDch$ybj0TAg!BV>%*|J-Sn~q{d+oXW%3OhKKyfWD94N% zGbSa=mN}HGdP{?84rMot&e}I(2d{l2a@eVFL=XG@8=-?ozj^#&qu#vi;CJ3!blB)O z2OPHI&3g}9^@f8q_b~V7mbBU;LU+jhfm9iGt8lXAb;cIX3v84PW;m3>W(xU7BO`c| zbr@l9HFixXt+lu(1`Jw@~Q81d(TBM+1G)rqSx<#!; z5)S)CRcrAzj6VEmH3C3BNYG(fG^4dhPGmHrwYU=JdNf;WF`BKl7|m!cCfK!%*5b(+ zsc1%PaTit<&{{N{$f#;9k~R^|)>@1Pv=%R8F9TYO2QvGXwHBkQwJ77A(OP_oJ$lvnOjMk#Zve{aT(TvvOE*$KP)*_j|(QK{7Xtvg3 zG+S#in$cP$Co-DRS{%r#vb7eY8Lh>`m^q`hcoEHv*5W8`QATT#zB8j4t;O58OEX%F zw=wk#X)W^C`=D@izG^L!haC-QE!MG90j{mc*aR|2}ptZ;k zA)^7U#edT7ptTqcXf3|Y^nlhPz4b-|T8rekMFU!kZ5;7{*5YKA4`?lpVE%yC;yLVp zKx>f?L82YB7NbF}Mc#EqgIbFRFe0e6NGg6bsI^E=Wc1suwfGBew$)ms55>Hw)moIf zB%rl8hua&_TKpM{ewNl^33h*e)M_pE<-r9`q&(>WsqRO#16qsJ>WywzYcaY?wHC=( ziw3k7&!HXATKo}v8PHms%HtxSwMcqlG@!M3FSjC~wK$*o16qrZFg>8PSjY5$)*>Bv zMgv-ld}tL7YAqhc4h6LqZ)J~zT8p=^OF^y0XL;@fwHANH96_zcam*3aTAap+pw{A{ z?AMpmT8sv@7NY^JMeqM>AVkyV+Gqo1)#3s3Z_%hrctG~$&C=B-5 zHHh)UcVSF=x@1gtL{U;!P}*+C#CmHSM4Zt*8Y7s&RoOK&_~46T3|#CXSuAPa8-N z^JN`#+(k_YIn}LoHQ<>TC8uieWI#4?It)ED+!o03+`J6K zT)Vs-@?>U5WoIO9)2VK1XkGx)3L2=cU)EIXv@LFKZBJ$A1U+VDLwmX8Y62TZG~;U8 zYTFwcKevF~SE?8H`M7pw0;sOX$-AVX4P&#SHgHN<9#MMJjZ4?2x)o0KV&xv0!7)cT zNGpd5%cr_c#>0$b_2fOK??$?zQ2OLJZ_A3p&P$7KedW?|o1|7%TmBQgac-JfwGoL; zCX_Eqx7tRtg1nq~yezF*&@g^+P3uBL)U?(v9*==uKDw^7aY%hjs&vu96*aB(rIo4D zy@#ht>zkTO+uB^^P~Syr|5EW7xGz6#X}#=)VDDxK(BQqW=b*q_*h4!4~~D;Ds75`fsowQd{)j zV2l16Q1st`qW=aI{WqZKzX3)64Ji6=K+%5#ivAl=^xuG@{{|HOH(&%09@x*Wiv1Nw zD(E;V!NXM1{D1_ zpyU>E(FHVtLt>^V^5%9vRbh#FA z%(w*K=hMbe$|ncxZbf~}XBV5+j)-7=CkN`|GfP_^uYtA<>v$0LQR2fc zHtje>1nWB=^|4>W{ zmnpdENLd5O?clNoYp{Qp1h$vsW4HHr2;*|p0+3}f>I)u&wk={{7{o8@*7)PR635FR zt(#!$>&O+k4*h#z6Z!Z%sA&9Id(YTWS39pwh<2O2$J+4ZzkYb-s_ZK5xU&kDl7lW5YQchOD3PVfeg~k8;*e{Ajy%-m5Wh z;;Y>!x?`(Q;-yD+m>eppoSd5c=?9;DI%e_?lPh5}9DeN{KQ;O4_0IgO*N3XEULS_q zSEPKovk)Ki9^gb)OGVpCc7sLU;EqlRvkHbZSGUR<^gMa0G;Ms##V2?w(;hc z+fqA(*A_ojwL|gRRXe=@$b!Y?GRjWrJ8R1)U%dFD6L0%xOBKfl<&OM&I{nRm6zuTV zN8A#d|EYhlot(9uq@Bpxq_opX+Ib+5@1B3Ky#loNZ?t!Ny1tuH-Z}DywEbJue^sE| zum0iOaXiika~_4=gAmC3D`rtn66rHTPXh3X%5bgqx?!>i4=Lsx4r#ITVR?Mn8XjG| zH={y6MYlYDRuJB?`vQrIPGG_P5f1NJyo^y{e>QVn%ewaNeu6|rNnrs0Xdr5XR@?Ec zA5HZ z9D(3^)VKSmNREW@2p6w7QNZ<%KsTd9^Vvi1-}o18m2j*TsWFh2ElXPrR~+F-6ENK0LP! z^+6U219c~ob8o=Eoe?G5hAZ1%sIgysbnH>K&FgD?$GF|TsWiu`8O|R{b0;-p`E-XH zAE#zsKJU}wC9ikF*iOn)(36m z55QiHPs?GLqfY;X@#%4z9%O&==P-G%9BvrwQ2tG{XQ~Y$x7>@7Qi0sE$q;fIhOV9J z#t)1g!P;fK59-V?YcF8Wsv~9y!ukI}PvSN4)sh;^XUF0TdULQu$So3P#kr^BA6IQ5 z66QxN5OQ0~<1W4|b|1|Aaoot|g$%Qy1KG_Lwjt~u9(4s*ps$PL*T<^RM+&*cZ|JNA zDC8Eu(H;pDa*N-jRxF<%HN|g^%L!bPm%oZl-J+%ua*O}2@H}a`Ab$^LzE#U&UvSsl zmBUejkX!!IOueVqU(xkYNh+V74deIq%0X`->XiR1dwqXmn3#j|KR}i72jWx3G(v9i zKWjrq$SwY`Zh#STi?7vo$K|hMRgV_Vkg`?z$IyJNaK4yE$SwY)Ry8S~w6^%uT6TK= zQ|$9IIl0p38TmhDC!gQ}{%mG`G4Cu%-7o)8Zqdv6JcA+RmVY%HdPNU53b}D# zvuIcO$8qR-3I8!3`{iIH`Aq6I79|ITpc zY022Jf>RX$%OJF5h1fbk3u<_F@5m7Y_T@ZXHq}nAT9Bs zOYxIvF)t3%(yhpml(__?B^o%#lXSrw2WiQSU^w|NZa+v%dPJZ_Zg?cj>WiCDZ+;x4 zr6_LulfOq)9Hb>0tcw25;~*^=JCb~WRfDv&0KEfI!^veJiOkyV?rY;9EggVelRSx4 zfwXjqWOb77vnWVQWRYOJ*ykB=2Q?AT9AG zBUCaYIRqF7Y3YxM=W#$4%Q#3&=7d|E^q3!{C1bZFdoe#qOU7QA6y6F*ONXF+k3w#| zKY-R(!S^KsLT}S2O{Lg8;&?gORPeK+)iSfAT5~)2)XgmK^&wd69FN&rQ8aT zmP`bM-1tx}4$_i|fRNk2nFFLH(+Y&#a@U}G_DaUIyRq3Rv7^TRp|vUG76)nR21F#Q zIi?^j(ctcTm16+X5~bNfB`cj=&gwLzs$NbmcMeY^wYPga4${&`i0HvtCl1mQcW#e- zjs!?cY}K@%i!((E6+6*KkkyTZ8P(I}G$2Pe4zMJ`kuXp6o-R*5doE0n_+j{;%VTg~ z1f(vIi)M2RKw9F=2O&2;qKkvHR3|2c+$JF%LT)p1kzvw+jFWWFgaUv-$I! z7*$%m+hhJ)$N)7gHncnb_i_0g+I>BOt~nxxMs)YYuiU?#3z0Y%Ye`e3oL zH5vPS5M2T6cQIxbV!ATspRoRpwO?2KbKjS8{Fe74#(m69e7_s>@pFX&to^8A z>Av5SaYJD9``(h4iH`e00k@jW#GNH-Hn#i20*)AUZGUg#mN@Qui5rEQ`7J>I{`eg; z0K=5C3jf@go0E$NB?ERtECo}~!a86K3_g;+66-)_8#D_scf-09E4pxTHw--jA^u}! zaOamlmGxYY6y9Y%iFL3|9dsvR*CFN|Dc*lAOqL2?$f8j<=O`9^39nF5JX{%tfX9D)YvU%|oGJMznuFReK&GEz9q=)-U5CIm zSO?pzgObSdC&b)`6?L&ctit2Jow2%|+@5E!F7AZqk?C2i(x-I@yn}VH%_{whMKDNM zQCA&?gjIz2Z&$3SEAltibre#1AyW^m1KMF!B2bQXu+2K?$B3Pd7?NjE*N*5stMK@5 zGFEtoO$^1I_<;S9QiDv@SO-jpu^fSRtb=XVLG_6JA!1I%in`iiPDa4vzo}T=E^cBa z>pBA|7b4Tou?{#M#`OsB=k4Ihnsv}ch`k>%f5eL2&TV8B-aqlr?e0cyWj)+J-W_sE zlwE%ZAhXG~ZHJg*tT=D#@ozpx_XQLk>dpwY)e?Y{noiN`l1=1Mt`*At#fCYrZDy0h4a%r zF*Eh;h>p7ByW+f(sqZA2`Yu4^nOM!#_d}V%UWffM<7DbPS*E@bxMU5$%BkbnId zFS(rhPLnC@Iap6I22*L!yIqCSV_QP1^q~nL#uV5X>TynyF42z#-<92uBneXCG6Il%>zRq}lT!1xu z;v32stmr^`;!DADFUdWWB{}c$Bkf(V4rGE%VEjCLPNozmFmDV?{WA9|TZ*4(AIwrr zkWxp%GR{0?V_7ObgQYIdeb;X6*~oJyR@vBJBX9-Qfy^Zvdl#%fV8zC6JnOB=9gpYa zGU@#Vd7i*3linK$yoNP<(&MWnBM3ii<4NzzUMH|B&Uuig<=7nb{0)x3`&3O|L zvkO-AYU4TY%IKr4ic`W|$6 zd47s@z@0FzLg3d}Gc(?^h`k#zcVb0VpP=!{2xMlwtMeOJRd3{b3VEKyI-n57n+Uv) zH8bH2L9B;KTZAK>vh;+v81=a~M6YBu+_+-o>4sG{Zbt-0V;#s`GT+UHH504OcTE_~ zM^JRL^Bpt2ubDn`zGJ3Nn40XInVIjHvUT$vUunBD%zXC*y4Z@2y4=!oOc*o!&=b{z zh+2cSoHt^#WCA=N^Yv+1`_5wV*@ai2%uU-5R%dCa&@^tsq#dGn}{m-urG3*E=71N4$*9_C9d) z#CQSst=@-j9`6K4F0WbQcpKa}4ct%jwr|vw5HdXO_H-HPak4QLJYgy@W&WaNM*WL* z-)nR8_%*rjb8}gn$^9pro09sWPw^4a-_V}Ndxg=W1^j8Wk})u#1^j8WipH4b=qaAU z%8qbGjm9>GKCnf3Yha3g5G?vZu;}`z7UkVp=r&uFr>iM?Td?SD!J>EAqH%0q=z3d} zQ<*7xeX!{D!J;?XqEm5g4!s4Hq+xkvKJ4_w;(0#Tj z4-ixIzDQu0?u!J5=}%g8N7ua=?Q(VdCtw|kZRhH4PwQY@^0~T0;Pm~Aiz^Rs_=!WL zlargvK(q@c9_mcTx*=ediE+_L8X4kTqg$M#y2UVAD%W-Q=;9)f*9X-N!@-_V*<#HP z$MjO0hie5O(6 z?viH*Vqjh&Zm6rQmU3U{7<0g7%T*b<1Y*YN(a^YlDsUXk*T0urfmbLu?V7t!WWU_~ z{e4ATdVud#bjfHe?}HO|(1=Xb4(USdN2b`|TpUiFal#Hc@n{#p3fZ$mPdeIlLODO# z6+5rgB%HZxUIq4fS-Ku+Jl8ZnEFG)0YdrMmH`=6%Kz%%lDs97#Gdw8xoRZBNp#vqF z*_f7ejMN+zEU-rxQv?%^G^%;VWNSq4ScY4zae2pA<=Y*A)0hiRT|78BBK?LP;eNPZ zb}lsWgNT=ya6jS=COn9Ei^dc0HevkV)Uq8SU1tVir3B{?SYOz|FNO;kx zKwzV#Ct_S@Cc)M)Q);-(BoJ&3GcSPg8B1@(L#>)%IyE=gsab(e&0?pxm98_FaGL~Y z5o|-V(hY?X>$tco$--NczE~klO_(FWS%m$tdQPi*K`R1mIpmZ}o2H?CG7ZhN4Mi|m z_*s>13e%=8Y-TxDG(+IH*vt%XeU&&Tq%$W0Lm*lZSp&8l|7GE(vA-u{MV1iJWZ`DX z!j3V^kFg?4m}s)hLP(Y{{xi#|Sdk?{G+AaNBufl$j|L!AhBf3Y732?j*Wue@S)$0o zi=o~qq<)K0Ppw4kQGG$nKLI7k5#xAvy=mhg|4IC4p^b@*>^X|#Gj%JpS-2;KW z9*$)qXWFdMbR-WvyLiz|b2DsYBpt~E&@OT5nK>*oTM>-S_^ zQb(X)naK2s?zqfla;7)SlSp%lW{OL$4(F}oGNMDImp*3`PMcG>YSrP}@tp3HKB7D+ z#X}WaL(e4X#otm<<_u%qcHvx!QNX2vz%!i}?QIuMxe}eEL$d9{>Fgy3N#<;a$ryV< zF_)Cyj52p)eI>Z&;RzFq|C?BNPlEe%g6a8O z!afo^gD@8>H)7@m44JwZ+UmuO*ep9@=JL%!Gl%*tf^B4$G;$DPFijIUM5Y8oO(ub` zJe|PMStfz-^K=43zcC4f8`233-EI;H94^xaLw`02geTGo2yFFYws&@LduLxzhT;>k z;x_?dE><=BoOTO&c1-5B_@He9IGk8&>1FyV7GVn1q@wl5(qb7H6<9j%Onu& z_RhY5p$AO@;R&p!1Ol5}@(^pbZ)RqTX3j;d*@l_ybsJV3Qp*A7nP8@8Gc$de$<`k= z8Sr10q4>{pmi@5H-5RjSUfQKM0)4R#(A5sQO}FtxrrCv^w`--1><~995I+@RuJ)OV zP5P$WXFu$?SPYKO+jy|;IedMwc|DmqkPB#o7DwY`{S>^-F{%gnKe4&BZrC18wM&*Q ztkYO)eL44B_>iTvsky1Hv<_de&ucI(%-be8vx!l`d-mX0Keaf&oDL4em_c=6JTOW+ zs?UTG2h|U#N|Y_eqbI9AgHT$12H~{&Oaw0y>*{P~trrIqSaMcx=42NhzPfbjQq;xw zxq9CB}c{zIe=sGqsgh5`jYw@n;)L_-{Gnppb<_t|5KM74eW;ve6;;7$}%By%qYA65s9R7mi1{zEsYNc-?Ri zdtII|GFpi94oUg3h?n0UNnyY+nv&up=tjo-ekpP+DU%#%mN~Fnma@o5m|}YiVLoTA zh_^DULYp10mN!{GBm!O?G_RVQswu2gUDHaZepzZn)vZ+VqU@9EEv03NM13eNsHF}8 zGhWb)YR`g(_E~lRpS|;dkE6QU{>-jctHvVRvR6hnUR!d-mL)fAhvMFiJJm$UmShWD zWJ|^+6k|&00Yhj3Oz0tm&=N`r5PB%V5JCt6LJKvR5_(AZp6A?Wc4yZDLf*XXdzqg` z|2g-bd+wb(_s-7F&YZ)DV~vv#F);0qDDWSJXozqM^&fNn#m_8ym`Z>At*&oqUN>yf z`XOkHRjrVPir&_=0{ggl<;p{v;dLtTZk36Z=3H8NnK*FFTDo%0YQ-_EL)kTO0cQSe z%@P#JJ8K+qppJLgan&r`|PHvlANH;dCc7(Zea^9SR zBPj=G@VnF6*yiC06-Io^IA3cSzp@b?dAKhOH)$KrYZNZ3(D)S%-ePDpWqPrBMJSM9 z9rwtNo<*+=oVC#j7&~_zx*D$C&Pz4r`BRPUvizk z++1~~y`1I70}VW!aWK1a3@2x8ZH=p&maWek&h3nL1?F72_z)W(aKDBFOQ&iaG$Wa| zc-hKU42!zfhGtymH6x{N-pmDKC+NBlQ3kV|yk*8G=Q`dep8*GMb&C)Q5U~)`&dV&^ zVKZ{w3=hH?1_RT@0?qOIXD;7b#@WeXe*Gf)f8&`$BYQET4X#+zg0!57g?00$D5`44 zuUWbyZ1*|9n_C;;RIOzWqOoKKXvTLM&K0#V4aMaMtZ4g)^M|!z#;ozv>*ia3xu&dL z-Q0$@xufEGYu*I8remML))22{-s;894wKZS`+8P3JUd!30eK>|Ikw%wwdOk)i5N@t zoY!8+N3?oYcK-w-^Iubd62AgMd=`r{_E1GLd_Wr(0LQ~ zRpVUYtVo$IhNg3U7mjneJQL`$&V{qZ2L;Yvhtw^rr_a6Ri$ZaD-NzJ$_mVbD8s{4l zV|;~uAo7?sHl$p8>?=>Z&I!}*=FG#Sh7`LR#t|tKpMm%U<(UHKXimnkcQpHm;DKmu zXy*{r53)Wp;d^f2Dj?P&vqZB4ZP!$K)LwJr1=lE&7dBGOn2EL-Fr_m|wS2 zG%2&>nGcma(+T)4A6laLZ8=*%KSv*5=0i&qURkpB`7BmuiMq%5(+N@Y-jWt^KMBuR zhnA>^XNE(|_AxX&g>rd6s&kHvM@U0U)S~TV5~A?-)&(Me%HueoAGtx9Y}=PfS^4?) z%uArceLYV390wh-|7Qf5p!G%0Srb0#sv0tvOPPyKp2(@&?ioI9B%>d`NNu-Vu0r71 z#cIhpxwr>j_+r!ww41zAycOIT@*>JRDIc_a(DK1C%tv=0B({(!cMggCYss$eHwAL5 z()pXf&UhG(BPoK($+;fEVdW1qB#$VGB3=ZEy~&PvvRmo3;-2CJk#<>b9}(v+lMfcx ziHD0PiJQf9#Vf?C#hXQr7ux@w_=5Ph_`b-;=c!jBS`0eKRgy=GlSKNmr~Y@ulSK2= zhxDIFzDeXO*VJbS8S*XhGm&r7Gks5ShIoK@u()14UOZd8T>P1MkNAZ6qWG@p;}#+7 z>mUvh$B45;##^G^a`AleN8-&QUyP()45uctOdKMP6=#ceBEzOo|8VgZ@d5D_@dGgr z_b92~NyNjxCi5LdrXM115c#Gd)6WyH5^ohB6rUE~5I+@*FyL8!Cvku{TAU{CFCHvz z5Kk0;AYLv0Qv8j$3b$5S&k^Fu;`!p$;;+Tui?50wiM?HiN6(J7C#X4@fsTION#x(QQ|c5ERoSDsQ-evO)M#L>HCUH#C774;xVGdFom59 zBwr%_NW50OLwrm$e|{)egb#kU!(yL;10;V-oG&gUv9AY-4J1D9Rw&mr{E@~ zpCY}}#j}+DL&=wkH;6Zh_lXaRe-NJ)|02F4S}ar48^sBk?c$4aWEZhY>?e*8M~hR$ z86tlNX1^?ye300vbcO z`22WL>92@yi+>eACZXr!QiSDWVkrqbeCdtsD)PNI>Q#$FmA*3r#pc2+2Tt>o{B$C0S_B<0hWAN4O1FH`z8lCKwkNunIzd1HOQRXX2oWBKRBm&Mmf z=)EWTL(#`)GwtMyMPdaBJ3YjH;y|&MM7iPO9!ei4&Q$tbac^;n@(&T)#C77~B3mw^3Z7^wr|wO5a4{xSpZ(v&D_JK;T7n_v6QgW+!1c~~OR{j}EKU+Ls>6c0Vk$5ACaF6B}Z`(Gw@7ki3*Nazg^hbnznah%d8i_^se zlwT(<6_<&tNZ4H?9-;J2;wehsES@D^uKcUS8^oK$+ep~GQ~b5k9}%BY`m^E-;=9WK zK>UXoDRcc3Ct92={uH-%lJU?xy@P;#6^_IG2Roy~R4EFBVrQy_LjqJzDAC z6;Bh-6wf80cd_Kl#h;L<=W+2Pu@qlCnZ759eV$C>+Gx5si^TX?BsPg_#P#A4B+8#4 z`4n-p(l3zwL-D8L4dTrt>U~&zQT$Nc5jQZH-%s34oGmtysDF*PNxVe-xkw+l)O%U{ zTpWn+^h_TuE)my=7mL@5&x&t~<+umH@_od4;$m@$xJq0j9w{Cz;_I}1-r(z+5tnI3 zoW_k%GxEJUelAss{lpq^n8|ST(tWNuv^6M`5?VWlAXmKB3*bgeSlak4i`s>V?^h>%Jb-m ziRG4xE5%lkp;DQDg!o<2?pGlF49Rxi0x~_RQQv$if{dI<+3sh6^zuacQSnL9;t?SI z70GXi?}{IYcE1C9e8`V>=pu^jCRU04MEZ+jzTFoACrh3#(s>l~7m0SC1o8^WM~TOZ z3~x#O(?$A~qI{*u;LwzB6zOG(@WsW_?q|^k^ZKbZ}(R~`kJELMWml8%7aBZ znW8*jJV2}yo5X{~RpJ`)2yv5mf_RE}rg)CHMZ830lxo(0jcE6AAU`ho58|`p%Obs3MvHcz2=YY9bQ;KfyKe+C9wX%g#RhSyxKeBt zH;6}w^u)#T=Zh8}0`m2e>57Z_cK->a$1TdwigX)6=PUHN#q^Ivy4RvyBGS1Q<(?w_ zXi+wg4IsT}QJx{vVHV{@B7J62UMJdpEXb!yreiGTUn0^s7G*lECFvE5d_<)4E6Oj5 z^nXS9Be8(@p&*xtbZ|wvr$`@Hlt+lWljsL}xnlZkv0iKx>CcM!c0UZHCo9U|6E6}k z73s5z`L~D2yrR{Fg-frlL$wnj{04vR(90MVTH)Njibzb;9oAL~*J(M_eEt zDAtS3;&O3~xL!O;JXWNCDb{z1c$IjK_%rbq@ow>c@i*e*B7IZQ9-rqW?S3ElH_0*V zBhw4TQn5^=A1mgM6!#Rzi_^rt#C^qu;$m@$XmLJZ&+a3F>y>`ENH1Be&*FZ7S4zHG zyg|H4yi>eKd|2En{$Bi}_@elVNEckJuRz>U>?HOOE5!j~wK!a~`a z7wOE4`Rl}u;xQsUdolk9;w7TRFF`upd@=ua(Y$IxX7pXA)9Dv!_esImCBG%|CpzZm ziFW@Ka;aoG1Y>@0kz{iLzJ--)k^Z;F2xectzk zp55mK?LIHqo#{C54OD)OI98k}?k(;wE)(s(F65J<09Se=l?fxy~ z`z6zN8S|eJ>AsBeyCU02IbTeQ6(W6l=t+#} z`-pVb#qWiOibsf>M7v*#e7j!?o~88jM0)mO`K{vb#XpKKim!-oiSLRZi=T<`Uu5=* z#15j}7ezhYB&Wo_;x6J4(e95ze|O1a#VO(pah|x3_-%2K*eos=+eCW2?n2-Q(~34i#S*uCGIXx5T}T9#l6J?#d^{1+oFEEZwnr(^bO)M;_>45 z#52ST#2<=RidTztcE|mDT>OLhtoX9{n)tT(SMgKvA0i!N(q5rhDwc^AVh<6Qxpv+_ zciVX*xPOwO3_DzSKEc-zBQA%GINch9a=2Y)a!RZc`-ua^k)qvqf!#5ZCy2Af`QpCf zLUF0MOl%R`#Em2xd5n0xc(Qn!c&2!fc&T`$c(r)5c$;{qc#pVMd_sImd`5gt{EPUG z_`b-8j;w#h0^P^3=R~j{jQ7OjP$urf@Biqx2lL#1+V>6S(;ohnlgOVh+4>K5&Xjx( z$>Unxx_)_E{UQ*LH5!)&TL_cf=2hFnq}7XB@uJ@9#%0w^tZwJ|BR;S6r3&HakJ?d8 zmv3lXv}Oq&+}Sry9fJ|B%3Q73fYJ9(#5P$cp7f8Hdc4p7>8a z+`_PBm>7V0T>4_gA^S?b8tCNK%W)Yj7$UX|#D84Y+gxM9ofADT1>$imo7dE1eRHse z?R^ZnJ$o~e9=7*<$R5upfxQhm_HKjmr;rvbLHiCxLf9U?d0amg1HD(qy0_A$W;)c1;~yC;3&-KUR3L!CxQaq4 z+`e^aA8oUJ_*o*|KAu}~*jtcfOWFABIULkQV#uYJDbVBdcAWo#y;5wmPS{H?<(MCr zr=?8W+2>)sE73ka4;U=LX8NqVYH0006OXTU)DVX1!*Wp3krQW3^8LUP>+YA;cUv(x zuxuBP?<7RyJ1Sau#`J>t=KM1@Z1vv6H?eo~ioME`ck_z!hCGKjapz7d*!=vY-%i^1 z7k`_JXY=;k_XLyeS_KZJGY@(1ZM;=Z(AZvG|3ZE&5-7#s6dU zzru5Z_B81?TS$oD`l9d`1#cOEOYsDIrMfzXwRpI3Mew=G?9 z{}}V{1nZ|b`YE88>jzL`i|xl`n<>nFLM^UuBWZ^cWZXR{~RH(uXc z-}H(e`debjk~iV?7d_{n`zuH_lXiO7o3?4vbo33j#!Pul=e`I~T3D2d|Vk1QekA7Tn_ z&Br|d6)wsm>6n5RemN5R780ZO)7Yr4_^|LIkvMNWN0)JXW;xCWc!N1Mhgx(B8=2Mh zFiVQ(Q7cB1OUl2;q=J}5t}ci-VXkLl3eG}al)tq^6;rU1wyMgeAw9<5Afr{ZG_ccw z+)koww5E(F!YBiJM@M!#8rz6rvm=W!m`7e#Ou>;T>_1iYdrnA7Wn^Q!u8Og8a=gmWe620WFJ#VhY}Y^Lc>>EF@R^0;COE{4%~R!qToCZ^z1Xl6VUQ*fDy>6n6>VK|-@Q!xIO zF$F(?iK@6_3XWmjnV5njX)hB~FhwyFQ}A@`OFR=(@H6gECZ^zKHZ2oV&;mbZVhYY; zMVXj_FR<)(F$Lp_DaaTe@k~s?ffPeA1wW)5iYdsz;PEeuDac=_PV?i6DQNwji7CjR zS>u_Qg74ta#Is`x#{c=4f~(QAg1BM|4&qK`VhVoFW^Wf$@I>_S(s(AOU_2|PU_2|P zU_293u#wHYrEole0AmTp&x+qF(Zv*uXJQKS8*DriQ}6?dnV5onP9UC%DL9bFF%whp z5O!`Rrl3X6%#JA-&yFb=&yFb=&%_kmL{piVf}JR4#}tfbVhZwU^>`+xAS0f}Gcg4j zb0?mODfkbHnV5nnbB{7H1@~k{|58lBXK={+<;4$DOhJBIh=*bdM%e42n1atUKNM4t zPrgG=#}wR;LoF0j@K4;SP)tF_(u{{<3f{>P6N)ML0w-W7rr#X~U#_hkK{n1T;6KNM4t^C}*WDR?6*2*(s;RLgicrr>Eb z8ICEqgf{+X#}woPBM1rLVhS?&ZAm#{4965~=Hv>;6kNo;2*(s$!6M<9f_%~;{vV4e7!P6!&Sam4 zVhZxt^Z3__DHso83i7NI4`K@5!oK>#n1TnPmVZ}F!Li(fOiV#Wk%)(53JyU&uE%1i za_1w_L>E)AAc!e=KJ<@F%}1AdDXgBKvInfZ?mtCRK_;dkAI~U61i=TO<6;U<#gQvK z)9>^=QnF(T-i?&5rG>v%Ou;^|RQOOq8Lu80Q}B2+rSRcQOu@CxeXka0;$x3PWu@WJ*7S$S$kIEl~gA zLIw*gfzf=dmFtfIns zzRDua-fc+Z&h42_<8Ie_z0XGm#~|NhamvcL5g81^v@D(B^}a`G8#8GG*hmdxw8<6r zcJcjFv8P=9-aA0zW1?IUi3iedD8u!eNIc&};^`fPu3;RTKB1U7eM2#BFqztkg3~{w z!O{Z)Q;5X#&qS!f9L0U)!+GZgUNdo5!aMu{+u%o^Wq>;c8Qj=e86;2N^gP`DG62c) z9?UZn`~(v;9QD>8wuKw~f&vwSw&;&_b~>Iw*s8NNhhRA>&M^x`W?>EySooq4HTbCn zm05Tiw|A${$h2WD+u-)?^ckUjn-R1Erzz~KTi6W7(ja-+0!O#}B;@WfnO0rbWCB&N z=xD6BV~uWN_q+Ye%(mT%s5?*l1^J3mA55a1<*$XRbCA2S7Nd8od zWJ3EgCA2S7psfX;iQYk2-S0Kuegm7l(Gl}jd$mBk z7j)4&EOOIXTo7pCZYDNg!Ri_@o7jdmhM!tcgqyC&Y;2_$ z?kvYQ8J;Or#Z1|1WjORWQ%H8UWrTXYibJ7~Q%YOT-l&0y&Lr4I%oKtK-HhN?C#=vR zXzYupiZeEc2rSIm!mWf^m_q~>zG$jcSu5reEE(}mpOI<9T(-fD@6%_5cCOv2!e($z zkPn;Hc`pLoKPJzm9}L6XPgd>7XARH4A~Uw^8&X+Mw9zDyx`O^VS-XkVs;_9bVk z%tzs~u;Ku4sJxF=Q-zx}mpxT%nzSLy9nSq(h$|{2KE$fw&rMf8H2lXQ@gl6gMHIpY zm%XrV#R_lJ6uF>YGy4vx!Ou-+FK6%vBVN1UW}ppzZn`3~v6WsT*y7+P=eq50+{&kW zC%jPt;TyN|c1oISZq|Qe9Ws}A5-ZPDnQ(4M_{wDfG%#0)YOFNyja&J^;r+khR-UI= zE3I$9CFBIxc|%AL&Szk96D!-~%C&@-d<^?yCcj z>2QY*r|Iw?Opocy;r@C({0R4r6*Z;cAb5w}Y6jwGW%wpuQytsYwvw@)WOZx@qJPZ1 zd`EXkIXT)I`28O265wdv%2l~ysaQW2>*+EpT-)%knUKYFn1a#P+ZXmO6* zemk7|bUOmJH}0RSw=!+X+LdoRp(aG(;F%82cQX&?Df(@$4Y@eSRXF@^r=99QKquUA zs!y-_xdWsvR+Mrh#JVK9CiMm5!Tw+c7QEC`kmP#D<5)PJcHdhB}@8?m+j= zI{L$0Vst|)>-cvM`hbl~dz)9HwJ1NytRCrqyQjCT$1TH#{vOP*Ez7W`+gP$K(;MtY z(8T|u5mcSZKj6Q41a)vDs5vu&j z4DaLrogT^qzvS(X(ezsqY;3OM@^;*nXJ!H(3U(vXIWBK)Ua@!mvW&m-w5xJ+k#2+f z>o_fMUAl60TZ;2|@yb>j&UROx?rqnK*1$)3-M_~b`TuO+;+Y^1|BGCTf8#&=bKi>` zmMGc5ehLh}kn_uUyZ*z+CT2%An*Z==U*lpd)^_SQKP}%s(0{^Ld=yf^`pBDLx7-jx0L*L;Gp>i2hBG) zXuiQg^9>HZ$lI8p`348gcNJ*9!NDQ8xyAf3qWK1gY`(!k^9>G~Z*b6jgM;Q995kO& zp!o&|%{Mq`zQIBB`2?DeC(wL@gXS9?G~eK$`348gHxu{@?!U2J<{KO|-{4>;+=63z zFVTF1LpI;w;0C3ePbJ9bN#+xtEO)E;p!l@-hWM#igaJ?eox}m+XmOgjzj&}{zK~Gv zM9JnG9J2Wa2hBG)Xg-fX^9>G~Z*b6jgM;Q995mnHp!o&|%{Mq`zQIBB6$JJwaP1u; zjuYpKi$wG31N}{sH;WgG*Nbe1n7L z8yqyBH=y|j2hFz)xNnhbzxf7-yiT(D28V3E!9nv44w`Rp(0tT@<{KO|-{7G61_#Xt z4QRf>LGuj`ns0E>e1n7L8yqy>;Gp>i#}5JK8yqy>;CPYLe1jw3e1k(i9FI%U_s1p@ z>E;_8viSxF&1VeK%~uR$^9>G~j~LK=#DMq8&acI%#AihF6$8DuCI3U@IhpmxNz`M$ zV<4OF7_dU=eWW))93}29nvZbk&z8J^#D0HAyjc8&_#%n=-XJk&wu$eNu=APnoT;`8Fm;_D>p`@7f)pV5@fw+lE%@_wTEVnO;*lFubk{{^D?T!Cyp zSHPbs{T2})t2S2~#XZDv;xutDajCdWY!%mvM~Ium zlf>_dXNl*DH;Q&0f$@Kb$ zzC+|g_>`X%Ul9K++VwED`GO(!@ROghP%IP6#l9pyKXws^io1$@qmKFG#p&WKkq^={ z|5)*4k+01${cO>$t07-3`Ev0m;&tLL#5=_M#0SO4#NUa0^@#O6FTN_iDZVH26MuR!G%gcNL(WFEmhXDT0B(T zC>|s74Fu}lB;GFGB|a=}747>5^#3UN&*JN%`7A{~eU#AdKg0;XKR`C0rQi;d`Mw_0 zE5u%6AF)O>pQh0JmSpp33VEvJnc{rWe3~MEk>n?n2-Q(~34i#S-c?^oE~UGfBRia1x? zTQuLM*f!s$Am1%v{ofT&6*r6LiWi8NidTw16>kvD*D1Em*C}|f(tj;(6`v3>UCalT zT@T`X5?l|am<}B-JkQ|tYDBlW&sWjPL9dK5NLLBex6cQRz2N*{`5k2+`SYm{d0*K% zQ}Q{o^Y8P?g}Z_6xZ29xM-1QgYe$hc04@0&pIo?vw52cpa~$AO!}HmB)OkM+&L8n(x`$$4KeSOR-9kr1}GEM$*u z3G8jacG%uVjNPXKW74B|DAusOlVNWR(%3$>E3kJuwnNSF_C*KL*JZE-d8Z&DZ0}*% z>jy)$hubV^dlz6kD1%L}D{j0Wf;I+AkoQw01l!Cz1~-9UVg*`)ydOgj*Zclx&r6{~ z){C#c>3VO+c2EYJ-jW^}e^r!&yj!sywpTV0_K-$<-0h%W_}wfhgH7*j*h_IkOOVI! za$$SJV2@*n_Bvnn_zD*oNIz5$omr#!uA?qkLNeq<8K&&y|=N=GOUYB z3N9{W73cQx7as*Yu$A;31yR@se<)Age4 z3k_eZ-gMcG3ue8);-4rR^z9h+)5hK-zp`(y`@lQ0$JXLMfGfLhz3zjJbshPCa~d zPlAyfQiX3SyGQ94?1p<}QM=E+Yx#I+L?W^4ah8l)SdO%Bs#|czjD8!2GQO#9gH|Lj z{t0gd7sQ6*j2+w>_rzMDVplEE4OFTvV2f&VM15d?tD6kv6F$XDc*CYuc?!vT9^l4Q~Xh~=wh7F;A`ryNG$4) zCc@Vg)4gJz_UKBXg!+g#T>xKG`$JAJ&I)`@9gAc*H%L5#?t`x>o&qDdjS$Vlc?7BjUd`-Es-4eT@rCE-7wqb9$v>yXsP*{ znu$c$-{0=YZ5~tJ{(!G3*Oa`(BDTA}&~A2B79`j(_?lv8MJtc@(Wx|Cycqwus)qbL zy7B4cmtKUX(%0145EBRTh#%U4+pLJOFX3xS6~PimUFlWGrLU<{G^0aZiw9p*D$t>B zwFh5Q((h2W)`PDpClw@kb2j8_>M~Zfov*1wtme{0XDZ*OvgL^-+{L?#*h`VhZizoL z_ulS5T?tOC0^nfc&O0gom39&P`7502VYaJq8fP;AJJuz%GrrZ=04YPFgh(#IY03d#TQGOY>)O$Ji|SDIl&nmsa%-g4;b-3Yp^xI zcQQMXMLXL+_Cx13{$o0h%V=c9nAPPn3`FN^ioKIOnRel8ih4Mr$?oiR_?p^myO5V0 z&yIz!DJK^sE4ah(HRa@z$HRbeYCx>z3!PgW!2i=@Jj`{F4Wxt$O?wjPiqOU1VrD){? zktA;c(bp8`NVM|dNYdQE!PitVG^3Tz#F7lmKwnccp&6}wK9+o+HsEV2X&Qftq5nA* z+(CK*4GtY76WKT@9fdaK=P`ayng1$MI6yJd1k)UsEpOHb2RuPhV3m;T}Kvb5uuPQ?8bWeXn=}%(GS2r(K=QMwuLU@&SRI z^t!%7UsJ~+A<17$=xd4s`@E8KAHJsSX@kmjUNO(=6wFk2ub2mi6G`$;@6gxOLrAFL zS%UoKZXi?SUp`(ya;k~ELvFjOhFm1K6&gIRiyCQ zf-c3##C2ZsKIT7H(7A)j1<8YOfC~Q<=);EFUAKmDwm>6 zQSS<7_R{z#Qa(3+zD-Iy+w1P+&}?CHh$m`3Gv^i0v9ZcLX-ZJ=_b z7vlw2C7l8l)pldLROSaNpL?+hRCyhyiiUS%x>VL-)3q0Gm@T0Wf9)w6)r}d_IX|s~ zeL9IcXK|l)@5T)2+?m#iV9=W#Z9VmD?;rvOLFwFjN^ z5p}k5&!=`{26Xu8vkNw@bCO<+&wx~xa<}#>XS!7O3RDJru|24gVvFaNGhHgH0+l*1 zR!@~@F_???E@!$_&J0xU@M6bMC7U_JL8Pa(s(D^*# z#rP0NC7<9aT2#&q>3Eo=Zogw*>}~2?gF#f(RL%_PRHb!_y;vs*mDjOv4lZYgbm*VT z*+J**N}U??Ska1dW)1|`rLh1f{l{&LI{x+2}LpqEpTzqV+Yy6=!D(JcI78Dc1s1*(QK;h5vbsJRa0dE z_w4oxrc0$hP}$Xs&7n#j560aUOqa?rfy$#^tc@zX<5=`S1=FQ+B{r>}aR!Z@O`XTN zFOO6(Lpl!!I(IpvX!=~S6aGp|=LT`ETeDmdyZsPcPG ziER~3$5B6;ZToAut9}|3Sn0*Ku)y&=_#am=T{a&NRNnStcbN)D#NR8JE|m|l>Glvk z^=Am(Z)Z&rzk)eZV#pt-gwrqMymueK?u`2t%#qTVK15SfFJ0kMhfzA)T$*bamsP-9e>kJhHp{<;;;1gRwg$ z9R8Q7bO!fv55Jr_Qrf93P{If=gwTB;s~hK+Ge=5$rj>B`tEp7RT^;Y2Ge=4dX(jZ> zJSy=CnWD*lIdjk-{Gq*QN^o>+6r7Empg$Osy*s};7R~U>nE|`}JpM(XgZ}t2b#9{0 zOuw8N(s>@6>Hc_>O8c?yIes~Fq!hy)|8#%6PbC~-&FodQm_rG7axpu=mxcd%&<#GT&QpQv;-=fZNo8*^l+GhVJp zE9F7xejrEeD!-gLP~vDD9aid3r4x7<*ZAek@%<|Q1~k#{=9l=qe&@0jYvge6kI3&0 z_mkcI6gTl_OCMfc`#bw3yt=*_>*ZJr)}XAP@{=z>t#4m+jNj8QJrlxY4B5e0`;CAa zd=ucm*Kc%adymXEuH<>0jc+?BSZ3|{2wR<5z1QDoFh>8=Ogri8@l}}icgIgl1JKe> zCsC8n{dK~+3oqCG&nlQpuiy)?!Zt77`}+%7>vP$*HbB8YLAIVVTh}0o?>{(O&zmjY zL*}!3u)=VR{@vMDcEB$BkIKs3W@RjrMqzbU?lmh%LjDd`SotwK^ondN7a_~>fzOjfXB?G%>pPTg9V_r{av7ryLxPSRaom2xnPr zS@BNL+zqGb0u_n5B85r6xY${stH`1qvJ4jc{?txPFX;($gE8=S=#-_O2?U9CGMo1l!)(Cnew;^@o+a$9opEJAXM2D%J_-w?CHJEe-AT5*|xCBb7}e-TZ66Nh#!` zW`g!z&D;u&T$XRYNh#!PR~l*Q<(np}94zc`E&(|vxbQr~<%<~T zFLi3^|3P}d|A@Vkd|a}56VT*uye6(()|$dA|Eb31iy9jm8XFdlObw~29XV*#utCe~ z4_>)?;j-pM3zsZjybwx*R;*mn_}}O?aW%aTG}X7ZA^dMMwuTO={x9^ONXH0^S1w<^ zazz~iAunretzK%6@5ZKhF&q7O+z0*?%VIG&_>1QE>J*z|jupE^i&H&gr4_L*yl7>M5%YV-Iz`)3@Y+{W9f{*RcBZOF`4#v- zx2~zdZk>RNv+A1qrTbO$_4ccP`<1Ti@~^6EXjUKA)PAi#w7RAR`*l}tUDI;*>)%+{ zv;T#4ee$1QSNeGUC3hTt`PleZ#ysv>y6JUc1mh46Dd~^0_5pacjLu5MilTknFp2tN z!sPqWX8147k9J8psm`R7qy;7okkp!rE~$R<<;*@b+nJUb3{UwQfia{NC}bVdpJM z*(a~|tPQIfHNvaIDW-89&T#dsm$Z6g=gzE~Id=Y(y1mBkHFd8^UfbH{hK6O0<5xB| z)z#Jv8D@T1>eiz9%NN0aS$$h0ob93Ju%1=U5bAZU%}Z9)FRNR$rYYM$VOX11Jv?^R z)Y`lO#+sJZqZ#e=NL^F&y2ge&Yjb)(;W{kq6ph}2Td<)+;1Dm=&(_J|I<1e`myN4e zuUHvYol`s9wA1}CZ^8KS6X(sdu3gNJgtQAcd?IA+b}jl+PSNOqu)cxf>Sc{9)KB9_ zFI>>txVm-W;$`*A>sQy*E^J!4`jDXu$IqNMbza?Y$AuH-&0aWr^~!@A7q_)8oIHMf zRu$MW*RO32E7!E;WTEfc@wAxkDvYR{zCs(9@xYG5IP~hqH7_yGi1Z`4wxND~;6yR2 z7I$c=PPL^g@n~JRU(*MNBV$b~v=*;i12=8(mRGO;c5K=?ydy9OXmdF|;x#XCS+lya zuBB~tW=S(jyUFJ1ys)RP20`)ef`44$t_g3|GNZQpxs8jPTdYBIcz)mkZ*5$hI|1zoS!Rwy z%bZqPXNJ>;3?Jb-ctsm5$b)om-`22#_poiV6W4BMJxHA}Ycqf%&0xKR~& z*38T-?B(RW7No}4?wT^+-*&xQJEV4Ks^99yWsUW%jr~&x;EH$9$U%!RXcsR{t!_ND zxwU!aiqw!1yVmSF?7-BZ<%?U^?7kQ-4;$AFT0RVN+tM}57lBPkZ)!Po*r3*yK@GJd zn8JxRsD4rN?n~=eHz1*Y_2Q+wV^?%tf8qvO)FLo zYHeHHycngHHP^#Y;}Rq`ty!_S4Q&{NgG06=jm{Ipa#PEo#Vc2|t;R>$?ijjWUCZ#+ ztZw3zz?mXFG-gcPYcf7qCeEEZYi^dJO$(k={=GgrLsQ;Hz&xJbf-%7{o_69HKG=31 zTDy2DPC_dewZhf8&XJi(fHPS3JO~$eLwE7Am96+Jt7~m&hKJAQ>`85d6uTQ5J(vt` z4u1`opy671-gN_i5k?et3?AB-HMioVvV6@l{I6RuW95n^pw2t3hc-8OIMy~3UBR`B zF*`D!=}pbc8Z*0$-pbkM7I(qo&Mo$#YbU*+yT;-iiRuFHqF?SjH22!a`ml*7|KJd! zdot$)=Th`brtgTX(dA|_SaU;L>dKq`C)-Fz?bT`eL zy4U0dGse#SlD)NS*4DrYYq-Ph2!zKmcb^Ua7ag^RZ1XePbu%3G)-P*oUfyVzp=sx> zD;n2&b&C&e!}S?vN&ULD4Y*ucHey)4sf8QG!OvEO(`-=L)lS`_Wrx_6D^&O?j*m3h zfpg$2eGZd$t~OTKIc6<-6h-mhE{^INT36OB#i7H&uXCo@(5#E-#W=l(X9rJb?Tj~f zZM~f%*mg8EGVScw%Bt#?EL+3+b;dXp7q0jqXs;3#WfQjRA|~QAXtvs^m6y!;^l4jp zNZm5rY2gJkKcc_-6PnYx9eb>9k$scGg~^gOoW$+u^NhH{zTWT)Nn=CGx)0^uh__jl zeM-mmdn1N>$M~qGl`a*^)lk6%`edub4qrPcH+xnKq%xBJ6 zeu2VwBAp1n*hy}BPpl2u)nLH4w&1F(sTp6MTyNkjOw-Etx-U3A;pFAMhqZG=@#%$+ z#@4#U>*~?G#>R$!%8R+pm#l{2W||G|`elurHn4OE$3g?Xk>TQgdHpi9)x(QD7>dEQ zC?3lgKYnzoA1|opujIW%e1S@h#r?#Ix}TWBH>bsot*!WOof(*lbfA#tcH-+(= zu=hEZz(;R+`bM$4{DE`$q;%>7bz5E^GGYca{`5p7h{LX$dTJCrCck(OnP|nT~d!aEf zVdM{d!II~_`+2ZUMsc@4yda24SVVsIkEl`H`rj!_BhQ|y;?F^D$^0}xnZAFs_49M| zagRQ2`y2)U7l^fG)EuLqlT6!y#HqFcQpM>e|8LMvpr=w`emj+Bdt}I-r`0y{TP-@ zj%Ljg=6B7}=bQ4GC2H2ga*vFFt*F;CN3P6~d*#Tz^&69$zx16vI;6qgnVloo<;bm& zIchm~=v(=eocv32m5vTmLf{UgzVw zChO85TeJ^DTotEl-0m)BJ0^2(Hs*+C5*Kf2ll+pIwIj^hu9-PEI(WqrZns(G2Y%Wt zF0j7ZEK7vV3b@D zjMB#{eZ0~qD1D;ZGg z#P5k`iWiC3iFb(ih);^oh_8w7i;UaKdb)_aiPOac#3iEnKZX8xCG#PDmcK~+rHJ=Y zE#3T^B7aAmH>uZ6+(jHMntxK{?<<+F`BVQ;@mTRp@lx@6@mJzw;tOIV>g<$?Jw)># z3j4cD=G*41Z@qZDc%k?^@ntcR=kz;>DRHo9{x@N7rsNaEbHtyE_li%5FNu8KnCmpJ<&1=Yh2o{+RigQ8NBN&iHlH?-?~?p$@k#MD(fqkXuNR(BW;=(7= zZD@CZxRXviv0RVDVJ(eDNyrX7N7p3Gqeo9q}Jx&r)Z9g1AIH zQM^WcT>Mbnse>!GhgdHjBW@OdCO##8CicWvGTSe4f!H9nisy(|h!2Z@6yFd(5eqsw zyGgN+I9%LcY!*)uuM?jX|0br&oV|(S!Qy)H0`XVkD`GJ|khy;~;sSAlc!Ky7@iFm3 zv7(DBKSrD_9!Pe_<-WLAs zl8+HjQu^5>#@G+UEy}-M{JHoG5_ayB{Gj-l(w`+U2VW5Xto)C~&qTl6*(o8h-=$(w z>6IkTJ$=Ppl)r~KPMl1lJ#!`REgq=!W^yN-kHuBWKSn%WJcWdvb0nWHUZV7$lK2d{ zLA*)%4~oALe@nv7bCO>aUsw7EBtEM@5&y3I5?p{7eY|A8qsV#=6dS~)B41DBdFcr8 zIFT<}Gu`44fEI@UC^n0$#5E${7N!2_;yL2^B0bYE z-@f00*Gc}F$Tv%w|ETz+Xy5yg&R0wMIr5J9vG|#om+$fm#FSViT08>i4wgJh++Ca? zP7(Q@D(hP$HjB$ez>B2tIZi?kA8XcrB-wH9M`HZdkeC-ENzB(VB+esKNc8(`66ZB8 zw1dNI#4ejXe7!JQJs3YQVfL*)*zZOeOp&OkO0@c+JdiSI?cjNiGHC7L@uv)qA<>Qr z;yj*5(4N~#G-d$j8S1yVBB;;qC!juy;|BXrb6mpiB$T1O>q*!{mKW)({z00x1G2RP zcI|T+vh@S(FO|N14x^r9Bp*+rzKbMZO2W8(&Z7LClu`dv%D2x|wBvorACv6o>eltk z+v*pA_(9&dG}yx9B5hu^J(N+ssI@i6jl11y-0rS;wg-39+3q%XJ38Cnw{Ayi`@7KX zD7AA>xgD)`ZVa#e)ZvoC?yCYee#v0LG_j>8 z{!Ofv9~m252v+s`*{5x zZXdkfw%b15_YUvx#*n?zkiB6!_U?h)-tn!;v3E|$9&VAO+sF7~_)Cv_IyvN+36?x< zEXc8UE$nd|aQu~Fr5=wneLm7&upESmGXUT9f+fg1G{@d+utygtw8!s+fj#;m4$9ER ziI}Jt1(OkSkatdw-hiEP&B}qSCD1z)8{vMwb{4)PLyz^cnL)k$J`8AG6>c=>_Gx z;WxB!gIO<^zd$d1JX+AcV1Fx-AGGi9(8D>m#R}nHH%#*IxJR}vWN3JJv!Tapah{I{ zV5PlMtgJIQhhq~D2O;)ms9<0Zmn7MG`@)Y%J9>kMjvUGe1i|uEF$-#U9Wi8>DSvg$ zf{VtmfnGXhK?R;#DZTNrx4aFfzvXYpJAO>_uG``p)^59E!_T*Q)7EbL?!jxf-M_)# ztO+vi})xMK;WSD{}B}--=F~!@ReAl$^N# zuG?Z8nzmgwdf2ur_HWwOd;hiDUf!_lwo0TOdvKp^G3Zo8$w@mi#aBY4JwYWB4ZWh?)jFq6B&)o2mSMaUk z32g5dw|338$zRag#W}5=^fg;M==FET#!g&b5ZjnHsmrA9lcrzy`A7fwe88mINvTPG zssdI#eYJnAodVO zH^K$bJ#Qvl06!U{KR`~j+=UC+idG?9z#OE{b)_uA+%MHcN?=Gz(0fwcoIqZ zdC%Z~{12$YkKTwTAY4ELi#?8i2p7QZg8PumZ~@#~3m4EIHjBQ8T4Pt1e2T=PzR*Cp z0H%Az@lVwn?568vOBxBw>x;R5*9C7h3=qs~Qk@hSM%nMdCp`O=GFg5d(LLRzATb&o1^ z2H?@2_C`z0OYnjK;R1rn7jO@DlUS0t6g!V_0jfMPmQCA3Vp-yC>>|PixZLst{c#~& zfD^kV7%~yz0-TugI`S-U;Q~Hpt6FeW5iWq+?Da=zc}5{c3m3rOQ4ubHJ7(bm-ljZ9 zGQ$O|M@|76YrBka0nej03l}gSiLSrD-I3e0-is}(%Xdx5OFYeX*B9EoD1-}O!w@cj zouzOAG+cZz{&7_e`FSl65H5f}5i?u>e9!=7ym_v)o4JZvNSQ3 z%C~70mnZ&2@$Mq_62k=?N%7w9KS%Q-2p8}Nn!3OH3no@27+etH0_fQ`QrRzY3HRxt z!k#9k!v(mC(%}N!4y3~cxHj*W7(i3M?aCa9+PZ{9?*f|Uruz@nd1^mS7+c(L1#c%3#elP z!Uc3h4Hhn7BzFnn0_LM@q6`<%g*Fi`U}w{?Z~>eO?jZdU+M$DFA{&Q;#4j=VdAC8K z%-_Zo7!0X0DL9@y{>~nUZAJ;@OORk^e~v<%%s73FN7>1NjQM;PyAk06cwf1^CyZIR z0J_so+PNFy0w~~Ql4QtJh6`{#n3w!M_aET`G$K$VcRW9j=F6wRu7wMDj;20>VTKE! zKvVCqD8dCeIX{_TKEegqhi_$xSImuVP*$^DxPT!zG|69472yJS#;2( zeS`~e6K-j8CiM|6z{xF1eraI104J|YevkDbT);TgZ{Y%X#m{g7b1ebk0(@FPxB#}m z!UeEuh6|tx3m3p21sE>CB_LeDAWklX3vdYt7toob6X60}0>T9hVG)E2a0v((@B?Zf zT!5;D6>%}BU}LGMS&cI3pfP{$+5^`xBv?5a}G6z3$P%Ua5`Mf zlOhE(g>V5pIGjk5UATb9kx;?24#NfT;8rYUUm;uoYjyR%7!*Rd0EU7^xBw<~^LZMu z(TxGN4ciC{fJSxmIr)OQP>yXl&By;@j=^edSOX9)U^w>x;R1N(gLBhrR*Y}~ynFBa zxDfjZnzeIZ{EPWKUIm*X`4%T&Iuwpf#nG2u3ajU*E`TK%T!W-coPYwp$Ux`){h?zn z|MT1G?SC8RyEm@Sj)=yGPM3T==sR+I^3$f(w6Ft~B`=Ww`Kn^}vPyYpe(^ z{EJXJMiV{#8=>R(^78@bI*;@ZD8Zvba7b;pZP-+d5o#aj6m z4fJ-2eXz|Z4J$uH%ltlm@p;hTErOG=R{#Mz$3pD79pHaE`__HHz z_&+E5SAR|)e{KXHetr8u!9NPuE)~#%2J&V*mAQTVd48?en@5leqfKE>WG&R@M%Lgz zv-|O^;*Vy{t;!Y^tTWnv7~XHf21Xqpz-`lK5*Sw z)UeTNSO=NEz99`YY_uA#g3L?af$PRmuRCkyFB1Iq3~AKs#k9{Lf6BDB+Ik!Wvqxvk zrC5=+2x(?-4CFnSwi+pBZEr~PnbL}s6m6}5bTCuekW$GM{^oTiQ`R7*4^!@fbURiY z4L*?8-{&y#d$^;)NyRU4HW+v`Qg$@xF_lrZc{F-j&+|7b{$AydMlVY{7&3pO;?bzG zqwyr9$C+YBqqptbXOKU1Y3PIAwr|y#to^XMqtT}`kH#X%`(w4E(bu~EVu)mKgnR+h>}U)y zd-p^Bl}p3X7-05x!1*$cbzn=4=kH=_6CsYbq*^2;+1Cd`+|QDRAgO{$--XD4#{*l2 zBB=+H_`D;}>|V9+^PUmc!WRqRvF00hv^dxOFK|bj_Sp)Tv3*O-yKLb1wU_+9hMmb) zA}!a!Y*jlBW_!cIEXF{sxdiTW;wHQVS#&yG&GvN}@I34C=!q7JCU576Hmf-U)Ex7U zE0?pos5#-ZfoM+Jf3Wlhwd1a~y4s_U-S3V`1bc*W%mrsOe5N06?B%x0$v#RaM=PD= zCkXYwY{Bz|xF0*4pef&*PxN-F1dTfHkK7vUG6>cHbz*myO0dpsXOT$AT3n5Dh`{!o zEg9Q$GPd{0*v@fGn`JOZaQ5eB_Gs_S9?c2w(Oj!_0E+wGT*B?q-kDnGhWBXhmYj-A zbhXV3@69~3JJ9UTBZ5Ae*RBPc!4-hLvhkmPBqFGZV}iWOZRe4^W@vA$@JB4Pil9pS zht_r693oJfliAn2JRfIYT)D*zRoFy_6aBD8@hQKB8~hmwLV-B|rYQ*P%s25O2s_}> zuerFq>bA=3HL}|lCY=@}BZ)b~x@GD_X;yGDR*X^NOsr9_%}?vFF?(TMjWyz(Hj|{u zh}W_XNH4h5vQXX7nZdgn(m5=x5XHp|Ub=G+WuUKE@d&I@ucg2|8@rupS(m9gg6{WO zWFS`Gn?pFQRRy-ouC=Q&MIx>bp=a^!!v%RAS%6<&hgP8@won>^HQ!t1wL<1Le<3Mw za%F+}VP<8SGL&46tp%Az+87BAQv}7QL5&@co|qOK0HmjT3p<5{C1{X+%KkmrZOpjb9ghL6?(cN=BApH+y9Nt2F2@RsQ-d^eZ>&vNkv^Sd$r7~Z!@T~j1^5>p4{Wb& z(3~y4?Tu0=2dUf(YV%kZcpuE@|G~8WJ8z*R%^BFVg~y$mtlMc$hbARyPRFJ#dH7Gw z)mWi9)7hjX&6(ItFKj_DN3V6;dF1s<2eOvX9HmP8b94-HFw%%XDKtk53%_WNa_ra~ z<%a!mz&Xl|F)nA_7H%xXnlne4bXJi3#dCBsR4_-0^RQ;k(HL^vh+^%Snf8^A1CFDM zWCh_Fn-4jwMBcuTIp9!Y2B{Ly!nt@u%g5)(sf99Qf7C$tK%S7VlUE_$V^cV*if7DW<%y6Lk;N(i!T&d0xe8a z4>Q#M_1dx!Im@s@e>zF~C7#V;o6VVtT!0*Br5_0Wy-4;2EauT7|Ml9!o=^)y(>;`$ zHQkxcdNY%llFFwiF{e8X_zj4p}ztcVQf3as~4;N+f5zD)2v4UuMsy0@bA8o4c1dp+B zx4cuVb97w_Nj*DZiRE>U734=t{as?6hQ}(Z2gkZb52=pjW`4qz9U7}->L8c83%3Wmq}o_N%W+9vLfd)V z9va(`h;B#)`{EMN6}IpBZV#wqEnpW>I2ul?@m?@I5T_5xC!RYd#i_wOCToIYQXVU# z`HJWcJTTF=YCAGzu?ifmPJ^c7n5^S5>D38tuH7LB4n+-o0K?mFbqY%?p5HrGoL@F* z2zot#Fb-}p+n8UI-cSO1(|WQny1qJAJkV4+b?SnucZhW#7ONZ-D;zK|RyjP@chKNi z7pz6mrPZ+=qe)gVIJTp#ViX{!VH2Ek_elLe_PzwZs_I(*oO|xMxw#n#L&yaJhJ-;P znFEA~$`B$%lu^`3jUfpn5kg49l&YX2C|V0*9dH20TD5Aewbl;K6As1Jw$`C_ssor) zX|?s)zWV>Zwb!}#20=T#zTbPl|2uH2D8BYfI`p!?zZrvON@C?LmoYm4Wv2RI|eK zb`Y|+`c80Z`ZRQPox%6=>3_+|<4cnW`ft+Ls46Z&)mhiEHy>Drg z^7+B6eKy)Bfvz>yIg*FZ!g?^qRYM>6Ir3DW==A?5Zqxr_dQzbyjZu)+A$Om1l%t`7 zq-dX`5#>-PKl0N0<;&}3Mj~X01!L5Vrkkz0gEE1(AhsF|+Zb~PqXdN$pJxH>MfF)& zScL!cLHyj%RI~sDlbzsTTVAbvv7JSq8={5edHXwfKxOb5YR?$grkQtO9bDejkvN>C zu0AW?A($|IlFQx>^&;;+2(Kl$3Vou=f0l&OknF{0`l_~7onXl`lU%y>i>W7Lgp#bi zQb`_UHR(ki`FB%B8ZXSU_c>a~c9Mak`gLDK0O_+iVkjPpxAE_0VDwoQo55|I(~DR! z#)bHIG9Vt3<`hsiz>NC8g@iB_pJWcjLCDWHQ__PQ?Z8Rgk-8VV8b1@6xCIhd z4B0>UHS5&$=*H0b?xx^o=Yqf`_Uy>>Pd)hrNe8E<)cC>wiTr>3{y2WbKMPWa-D%~^ z;dnfLO-wk*2iQBk`4Yr8A^%_EL4Lo)!?Ez2Wx|1nFB2q|j~}TM4#(ot(DB2u`o{%? zoCCZezh2_uSXt7i{FZ@zO}@I(K+5djeyHzwmD#7{qniQrj|>KSFNEep6R6D&xKlV_ zrTttY$wuz$c#R|o0MSf+#bn_HXS6r&NOtD+>9K{P1<(n9!zgp#QD&DX7gyJ)buPMHz z_ju85@<4t=0Xa{x zRB?*p9K|}tHpR0PFIK!-@peUdzZ&^IrSeOP?#$A$c`$}cFsp}1d>4}Y`**U@iN7m6=x)w zd{0ztQ0!DZPjQ#xor*tEd|vTC6uBKX{T!q?Mv>1YP(M@g6vY5td-4J6cirmLLn?5>WV-fWo%~6uu>( z@GSv1Xu7W}{#fxj#n%*j6#u4}iKU+9j#M0{Sgm-9;$k9vU82}Z#AV@Z#d8(6DSksy z_?D3WEh=*>X{Ni22>lOLeo*l-)$dXHMa5qeQU0fj*;sHXAF0?vM1CuY7z?Wu*AY?P z#fn=MuT#81@tZ`XzenZ!6dzN3O7SJdR~0`{{7~^@BJ$xSljQ~#`zvCfU(t_J%vY>b zJX-Mt#d(U06_+TkR_s>XqIikob&5AA-mQ4A;v-m3V7;%>zk6n~-kTgA5&_bPgdA1m^4de(zChs2;FpV*|FuUMkU z2WY9Eq&QjeSViH-K|J4MrQIotrzJ%1?0o= zwBxs=M7hrb^6^lvn==&UehcyfmC0Ak_|p~n>?q~6it826Q{ctzpQge-hFKt8X^czLG? zxLD;SihOpJ@n%ugIrqng5xJ8x=25l>1S{U#2pjw59!> ziuWl#p!kTQ@Y%qQPvO#D_-lags4VxdkoiO|kWb@MjwMeSf$A4a%o?y z$ft5CcPMU9+^EQBbQv$aG(h2_0p6+lM-=&zBJEyOd`XcH?DBf&^U-{y@+XS?AjtTj zBA@1^oUNFr$Y=Gb_xWe!z8SL5KQl|?`J6B9+7wqQu2Vc$ag*ZL6}Ky1qqs})yNcge z@)4BDITXdTk#~tQx*AKH0@U@o~3w>qI?cP{MS_GGt;!cS@GM7-%;fA z(~N&cQ9hqQenaK=6?+uaE=JOBn2$5I_d_%o{t11-b0pCL% zib#iFLj50y4w_yL-1^8d8h_c}=t?=*SBZyjHx^2UIhJ_P?p_I*KO8$err=Dpdk^v* zjL^fktA(6s$9ulXz7f#3TZk}+=wzHcHWrw1%P~e@Xh;87<79sR@gjt6xc~PLKdu9c z#QbhTekUUX=Er>e{LV$#PlKSHOs|xvj;&)a;++zqQ<~IxZF)yBI%2<9cB1|8+R`8gV zhxcBvR`>_wc=9t%qTQ-|)8_};eV}%}{sY+Y*)ad`U40LVME@ES>YIr;zrOs8gt^h~ zr*A&OjD26GPdtbT!^64;c3Ytw1ihbM2Er`UpKAzOV=?|tWIzu;Kekb#-DU7E*^fk= zA1o>_HWVj(<^;!=a-vjBEG`zyFXu!VP%TcyI8mbbZ2_DevkQ7MF8apZ&%K{f>Qo2I zcJ}<>fqq*rs_wu2!s^+3UkUZQy3gga_f|(|?|mZO*%x+a@7)w}_oW9X*thJ9IKh4C z);(2~LjzY>`yO>>@7?>yPeKsj{MZcY)ebu4#{Xu(TRb|x#`%hNz z3ion*XaDPF?|mjR`$H@B#U88mS3TC?fj#zZzv!`Q=k?e-wn9gSmF+!NN=y-4ZGF zc2#zH@1QPATUU9T;os|sdlDQh8@pF}Z`Hn9)#+Vd`Ns53J=T`71%3d#wD&&=%*Rz7L~4pM-X9)kd_?NmY-cO&3(nuR7*WRd@Bd zI_ZeXfB616p{t#%`d#T>7u@0O52psM4wr=Yhr?5%;qj?u!Ro52N2AHx&KZ=xKb#&e zO}Q*-Td>-$4sN&hr#f9#vp=-M=SJ(R-0jCzM=pD~I(+F%)uCH+9>fDhKE8XaF{QqL=pAdjmT# zCc1ytW51lb1B^W{L$^C^hjZ0)Jr1;1clwU!z@5X;9$14PXZNc;)&m$rw_T1CV+iqf zw^Oyf$Nu!S_k*indq1?`wfDpJYwt($o~^cD|6_36G275`7+tk{daO@b+Ba}6L`!Ai z#7N0UPUzM1x0HGz^j;B0+vb|JUU2YAZ$xXUSDjzt-O@_dpb*;iMHyZ84tNlOH~HT{ z=_tDu-qm(`k5`s?D=@Ma*RJ)R{ItTWs;TfccNcp%Z&~N%=9hY-cXVJ>6nmlkRo;p% zE4@aHs-oIbFFd%z+x%&%HzU8D z^L9lhdZE^_-o_ony^S@?yrjXoU{%WX!ueyp@RqgkvBXOr-0I!1rO>-+N0)bcgfpoK z>_tbQT|2zth`R}GabbRu=hjwuLD-Glk&hYP=G}nuo!TeRH%Gv)F7M6!VsCn+)pKf^ zyl-wP@ItkPo>RHp8{Iw9+l0DbSX1szt6YnG$72RPR`u5ON3n8Xw6`v-O6su(V@^co zS8YJQK7_iRRP{)YHTYcg(wr)+8k|v)c~zJzH78b`gZ{_t*~0lUw`u`q%HBIut`3)_ zY>(h?WP39HCT|bpZ+LqW{w8e?;csZWi@)ynApQoo_qjTGzny&C^z|Q|b!W!auUJ># z^Xux2?XP_@>Fx!;%e?!?A7oqv-lMNu5B`$hsmih(w8`6?$}c6(5=HMn;5_0hvH?5v z7H-AC)U%WjaQWkzvx+ej2hBwi@ErY#F+rDPKaOzG&K`6IV}ePf;{nf61Fl5iIjTac z19*=5FwKYo(_!xH z*&*Sia>SC>Xft%-pnHpxiXxMXkQHc+`15Kqf71i45%pGN0{)QLDTVgfDKG5am`o?r z{stMeMjHTl2R@C2YM?ce??Ll|mcuWQKx@RL4u7Nst4K`C`Z*?hg4v_@ZpXK8mK0<=aZ11pWM*Mru`h{3dvEQm*{ z7*6{XDL`vvVpG%pzzQ9uVn*5z=-SaL4oLeo(;lN@G>u=ag4W2S%}(PtZJ;$WVon0B z(JS=o6}SjmBZk@Pvnb9=rs(8tu+x&!>7X@Y#UKaLxSb4Wjf@OhqsSt}@ViN=GH8ts zgKI)-Gy%n$_CBp2!_56jdR7-Qt_0H_qu=$(^3`NsIE}ZgpfzG+39XSEWX6%>k(j5J z;0EVI0IkubaFw)1WFtrul9$ze8D>HK=;j)~AaoB$T}CsCC#@0RgjZT4O`xX_0R z87Z7LkAD3i88_?5J2maQCrNLhBCS`s_`W%YShno!HU5_ufH2J+^lT}3B<({B)r zz_*i@N#i$D=b$YEc_*ix&KkX)&KV3^qqKP}=yy8UNNYrgm^4%VaI|Ee#y`}fU-k$+}S|gJ_ zBkMZKpf!^3TR>|>UIEe?nfT(YpQCuv8a;!X{XkxM)>M`US|bx*k@W-0pf!3;;wNRj z#qvRGWR{Z2S(VHmv_{6hDvP}Jq%|_}GqU(SI%$pM_ioS{^{`bzYh>)_WYw{J&>FFE zNNYrf57HWKmGVx`;=CfQ5vP*S8j;YRv__mGLTePH0<=aSBZbf!-OVgPYeX6$p*6aM zd4Sf)j!=Pba@`=Og6X86pg|HkNklpaBmVZ|26w_>fX(HU12n;uD!)H>i_r#XIBera zNKZyIS^YT*Win&=;JhRSm#&ye8`zAXHQJ2IM6W^xgw|*^EV5+n2CWeVj)($Q541)s zjN~hPVuiFuIwDXaEA9rFeY6z$3a!z@%!=gZq&1?zthk97X^o5=%K93!2CdOt$vV}F zFz^D5)onv-l!=DU8q2IeYqVKRt*rZ*6tqUBAA?z^vO=IWqA_WWUSJ=9)<}NG0<95g zsz__JLDJ7K^je@bS|@Ux*63Vu_2eu*w?kSZGvS)E9%p%=H8OIX*2u_fv;LFif!1iG zjEW6*7C*F;)@Yn4Kx@Qb3P@{24}{ie1uZ~p#4Lo?D4jln*2pM8YxFZ#3baN>0a_#e z3Pf5XqX4bZujnRdjf?`cM(@)Cv__^B^kt+Gnb0d~(?Le2Qz9oBncupK?9&>xLy>g^ ziwCU{1$N)X>;upmZ4h~_72%>tL6Q!&BJ3PaB$W-V(f6Pj!c~W~M(o@nud}T{Ys6Ab z`H%aFqE@IArQnqesuh8@UU}hs4eVs9!ySxVm{8?mB`mF zO69NJU&XnGx^E$KyEyYg*zJOR4Rzf1&MpzVCm=tBGq0r{93^FGeAV+4oV>$<4kRUI z{iur~8{rsgsRv6*Sr&Et)w&2L?8>3brmhAuS;?Rq2i;`l@B#Rlu|Awk7z;W zLp1=Cw3h_BhF(?~d_D>AW@+IbKx5AoBO?aJgb2RnJ0vOjK~aVlY+w@id4tuLD)67)I3` zh_gh6s#N4sMKYmwQK3o|qo~>fag(S}wTgVI?tpk3RbB9FqWHz%I3E%f{F*3!@jCJc zsybm+DOM+7NX)>Q*9ogivDyW3hp6CvrFhTZ5&4^9UMIY-6z`{E@E?scuM^%^iubD_ zE)x~JuN3b|`9p5PyiRyuDc)ybmhrNa*9q?{#rq8qc|jP_4!@2RzecpfpCiSe5#+}? zQv4Xvj`EL`^79&2z+#dZ^KrY|m}SEXm`>`?7U5d)Q=>zgNm1(FgZz%s!RbjusrwA_ ze;OUUo+Msp;`{3UIFTRRo-~?vM?mJ!Xwbp$Nn@#-0+~Ol<#lqH9wol;C$tld4!#^E zzAT4KdLh`sm!rg&^C0tQH0a>VQQ`|9=exq_;LB0s%UzK9GaBsR%TeMBw^e-9=-|sy z;>#}kH3epUM!_DR z1%&V?A^*Oxk8#n^zF&+INImGEX^n=P12XN=sith)3Nx?&RpddaOagfjR_=rF^5h+a zmxt6rvG&1ONEEZtTykImz{SY$@nFC(Jc7u0$2#k639QC!hj72m0NFbwh5=rRm;~0n z4*Xn!@6P8CXyRDgwyy7G0KwSI^=(M`kih1k*2ZX_Z-k64{#-^F8?d&m`2<=rtNA+< z(p->`#a++Gpm;weJC zBF4ufl6plDQ2`fUY1Q!x?G;B=h5azy2 zvOEO_deCFmmU*OE{CRCEM3OO70~eZbHIZj3ewYMj!YV_YK+UG4{U0P^Gx`7BE5(h ziinTrfzE;Q785_2NUsLO<2&ij$8*Qzg7^UiT!|C8P9@3%S>OtxM-|4S<9&~y!tCnh z$z*!6$&^&Xy!cHE@|wZC-ZSBuetI{;nQkZ6q>AZlP5S9XdK$4}4({ZJ&gx$*ALhr_ zSZvZA$8vc;gL04c%L-W3ZZ#fM`C1rB%F9j4SPIcfSgc7Li++wyDlS`+o5`_*gF|USs5#u^SVuHDCRlXQ*i41o z*cufkzl-Ijux}UQg#S~BmzwbLM7F}gMr5|sg5@IB9N$OWCW(h(Q|hrqmYO(!d$qUBLX)e^aA~vboe8}#E$&ZH@@9VVd1rh#ImFv2PR7E~ z!16J#CG`^H*$G5`G>L%kh!b-Tn3yOVZ{rI{FK?%?jZ9hbZtdmm6e$jWQc}WF9>*41 z^~89}cPE3vB=lgjC6SWI` zt(&Ng{fr(;)bit}97%~<{_-G4I8hs0=93e(wZ3g6Q5(C;q$Fx%*RRw>?N|I9EQ=RF zwgl>Sny<}9fCG^C2mZm!QR0y({~UABF}rTsf5B$iSn|JJ)soi}@~VS-fazL&KupzE>2M7MA!m_!mp)owK%zWqM+!X(RJWrMwH- zQQz3IwxZ6wREaLDYiwFlziL@mUDvwyrq04n&M={v3AA{-9|@ty zkm+b@YE$Fo^FOqIBV#A#1T$OR&NGW-k160m=C*e6eN)0|^+z#cNCknAQ- zMxmQDpg-wMKr?b&$PVQ8b0g;}$x5@~Z4r8z1BhM@6y03>kZ6a*wA7VYr@PQ-3yoab zOBzf2Qa6ntVPSO17g0%MicBn6OTaLyR?IY;l9OCWD8g>p03p9AGUb%Gqo|6NnkX^3 zk!hli7MgNE4MU|95%4RKB2o!s#7%X|S!RsaB&I2gSvh@;zTH5Yf%-zfW;8so3FA7g z_h4$Aev(!y=q&A>f!ZlOPa@w>Jg>haq}gQB)YMTzhwxRcofPSma+-qDh9F^aG~th% zBNkm^A(TNv0~8No2#Uo@1DOIc4kQ;D7RK6?TxN32Heh}^N5E~7z`R8TOyz)3C4A6rmRa0IMDa}+-`hogZR zZrVm|_F1O0WK4ZY>$xMPqh#sORYCZmicLhJD-v9xnT!Onf3iV{BoTW#i0Kelqc;Lat^mOlf{xk8baov zGfWiXqH~&r%cQEh5RMX+(`vv>Oy?^`GRvYf+(@SzILtt!fguK#7#L)r#Xz=zOz<)O zf^w4R5}NXWmi>E0Z4qa%w6pJiuH-I#tE^-WmSgD>Gn}-xrX8F?g|1MSp}yLBBaG)- z9j%;cQok9RjESk7W8zHfnwF8Ulvbj-FOn2xrU>a7W zQ&}g040==esm84_h3+uv-YUOJrG6zFjD=sEB$L%Vb_uQ$i!bRM<4MTDZ!#F+=5k=1 zmUfqHWrV4ZSdeHq-1jTTpEO2+l_`z!2fwhX&A&YjJ@}G(|H~%-U3ED`Ik7f8SVa!( zivwgCn*P<6*O;VGc$J%Sn447OMnNtYs&S(s8+V*XPx|knnfpINxu&|stAw=apCFV= zq>m%{6S$wcme+MQk+Tbdb&d7wtU7%7;U7>~wQ(Qt|Koxi2g<%R4V}W2)`^dG^<7PD zm1RwBDl|0LcbFDjE-l#Evb1gqDAH(!RBIaiL`b=|rK=d!h5SHB%C`g>xPJrv+dshi z_OFw+{Ua=GaVj=`#MO_}i&u4ZHFYdmwvHdHt@imH4f+B6i|OY+|A|~Y0jVCE_uoeE z_Fqrx*0rXkk(2WH6^$)RTADDT8ar3iHP^Q_F2i^u&DxzysIr3#w4wWUPC1p8>cQh?)s_$$XlXEJ*m@23!SPX8& zhUT1(rqwN-Ei2k`O22Z3i(j=T^0;k)>>vC-aBBL9jmhVSHzjQjUEp3A+~QmW zR<^0>jqaR5?%b$5FUy@j&|Q$}o;bi=*xx;=pL=p&_mm8`wvT&iy1OXN{Yt8PT8dj2 znUa3L?c5hgZ=4!BEmRj;6#7c2Hgsy}^kNBU+@0R5^ zieL~sHycg^qYmP&CG!QfFB>#}$^VvkIDAPv;rMcXH}+EeaPY%V;^D|oz;TTuENF>x z-?)Gf`P}fzAHU3%pCrlO7AI2c_2nTL*+w)<+(8#X^L}IizoOAY@}{vQBHu?N4kD)E z2Y4df9;^B?#Y)8~iu~1!>G<_KkzaumPgiVHT%~xX;ugiPD_*VmEyX((A5wfm@n?#^ zQRGu!ERT&t9Hlr;ak}DM#ifcX70*(XA3Kr$n=13C6Xy50;(sWH@Kr4JnTjJ6%M_<7 z&Q&~JafRa9ikB!}qjR zAh6r0@@0xQDc-C2nBt3yZ!3PJ7{nLcERQ?B5l1MND^@91 zu9)9LiZ3X>srX05Abv}v-5kZ!6|YvjRq+W$?x#un;fke-6BKI{=O`{zT%_2b*rB*h z@hT$v>{`X^iFl6cn;OrZEGgfo_(Rn{q4I9UpQ`?4m4Bo7mg+r~|Deb`d4?1RDh^i6 zS1eRKT5+l(w;g2qg^I%4hOqFq0lQT%{A~z-O=aP4L%2uf{fbe4oUM48;$lVNZG)ZgwgES){sP4-6t7miP4P~}A1gkrxJU6t#kUmSRs56U zr;2#KPW;4kbAs85If_M!Wr|Z3s})aFJVmitahc**71t~NQ1L;9{{XT z`2{Zps@J`D8ccs}%WIH{~BGKBoAT;!hQYcNKOotNa_q-zf_37~(%v zS$M}F^RaH`pR71cF;{VnB6obIUAba~A|Lpse!gO@qC5%&eUr*9irkl$_QEp;Q;gs)Gyif4~#YYr{XAE{Psr;(q+ls;ii}(=lGk_7reu@JXhbiVN@N zI8RY{#Snj*%592r-vhnyivjsw6!Vcsz<}4Ne3Rm>igzpCtN5(q9>tdwUsZft@jb;4 z73EIE?~5-fFy80= z;tL9t<^C4PmlG&Eyx#=!#RQ_y^Tn4EC>JU6g#^me6%XX|TCRGZ*NZP9(0;QbUqGOI zt)koqL;kMHeDQ$sPb>1J1IoWuM6(Nzm4E$&DDfEXf)jN;8$cOG{`K`A=c_v8H z09h`NhjAwQmy=N6eu(q^<9AXR%k2O;$}yl5$2803K};APRx^wyLy6%aJ325wwmZx8 z=LUk-tr&m2PxlW$KYn+YXjcsX-t>)tz8zN_f6s-&6-9AAsPQ>D#W_68-;(0u@#CQ@ zD=Vp}5dD|)L1mvM1;+TGhT;?&jHh7unXni^Fw$!R!6u z-5V~pGRm#}8BS4mmT>j^&K^f(Vp>j~WE^w_t7b7xC+PjE-5$JtTc6WB7rTMRa)cgO)#Gq1;K z?T2zZy+e7Owd1@u!1wcd_dNK%)Z1LS1bjdv!Bw-=yBQobNwrJ7n_EYL z|7Mgo5_XTnpFA)-J<&SB8`Ygr)-ZiK(uMYCgr=k3f&CeQAlfL1u#5H!?#~FW|7g)& z-OU%@GrT&G_t~HS_Sug=2wyb3y1RKYWU$3df$l-W*A=wrr);w?nA#lKIx~Ec zftg4S0xZ!&|}L)B0o-+(b23KyP2MhO9l+tT*|526|g} zSA7zGW|f!M`b*e@H7h@O**LGEwhMe!zx12-r`l*k_m=&ssW80o-f)%|mnT@D7QBfXZ&3Etu013P^O>o{1>z-^sg?v{z3yQABC7~$(H^Sv#* zTfC$PTD{G;jqxHo8obTB8@w%*hkILYYxXv8>Gbx3`RKwelf1FWbN6lF5ChlPGw^)| zn2}zuu~6=0^!&pp_Z-ZiQ!v8Ed+%d}K3;PQMtQkcUo#$~e5u#4Wr;Ux#|STP$0&@3 z5#Fd8%plB`TUr~v8(~w0wrcFIz)V}`jRBL?>FDjJYS(xhx-q&jd+b)QCUtM@34p=s z9F+e^_sKn>+LL=+@S-iQT;sjbz0@0(ztp>>2D1dS=w{58QLUrBk=+fzJZ~gyo?gx_*DyPTrr9?CuY{H|-Ax z!~3Hgsev2!hn@8w{q@eItE?-ZvFv@=F=e0K*V-1mYEV^hn}fg3wh;b?wz*dwRyC+9 zaJ9S5+4qPO*dDyfy%PLjHJDSap{uXxu_}MwBeM$pa&{$VQ9k;*+u8BsPex2Ghv%K% zO&IN)FiYO9B%@oGx1{x)9;=ok0`m#2aX#Wl0Y|{*-5PLA)q=fjFc{AA%f0ikPE1AX zE=4O3uNi?6(*$0yk=}6Rb3^_(uc{VYR{5xP?JDodTI=fZ-ZU_m*)?P@3tYX*djxBb zi?!(d+EHGxwaMFvwTgUTH=}26>>dw}GO)w7f+?;RBM+yAUJP`D{jM9mi(bD)dVsw_ zTd>r1Z$|B&?6JDRmo{g3b!&4_R;1$UcsP7zYxD4Gqi=1tuVgq4%vKRHTg}$BYKom7 zs?MrTt-i9_y)aRYypHBE)j8E%`R?Cu_38V9 zT{LhH@;WD{VCJ52zn)ysvu8uW{uhQ<7sqUR_T1C_oeNDGyXd_alDw_8pMXj2`<~VP zq&K?ND)`NwAjXE3XO~?&)kdgqPq2G#kHdOnB)-#aL!JWJdx0gvpY;#ydGOtgf@k*p z=-q3-V}s$&%AJqdW0&qnzTcRN>rXd0@|=%exbj`!lW)Fj9dX;9AG~`KzOXa*2tj+j zi|-L8;*RJU|4N>4aR-;zT`&Zf*Ae*2(n-a4m4PFo(_jH!uV*1Sxkwq95M4-B!0o|Z zg(GY}69=`3D(N^TBppKF_$cow!S^*1_l3^;%xm@_-WG!I>q1Il_cDH<3n%5{h9l1R z#k&oMKan`m{u3DH{fLv(zlPx-vcwSszJjpJulbyB(W|ljd7tDo!*>vaorf^^C@!Vx zcku_rU?DgZ3X)+W>BmT5J9ooP5QEV}XDpI|7>wcY4TvQ%*zFLKNesrl1tOX72E<_b z3}1oTfEbK=D}_zdf>0{$9V?B*VA~+4f0KFMoOBb^VEagKMXQ4tYyzS{`(iogq8UL9 z#-z@F;;s|KV4uRYPcRhx4sGo4-PAJdyoSO-491qrI04y`7_11GPVNE_gE5RU`qrHR zt}iVyn4X7V~r0 zkRyq~US`=>vh0b;CIc&-I{<(f%!tACO%#t*F`WKA)CI&~CN?$wLi7oU!Hk%Z{vEn@ zw2A}L7c%WJDn`?<4?>)*Vs`ptXgCmqnY17Vy9likwv%eYhoeU6dFWLTgE7oj{|?(= zRx(8rgQag}^a&AGjKpB+<@i7VVlX3b3|J}OLQDm$rOF@%dkLNjG1x}tF716L2xSV9aI3NquA9r(jjO9%ybK>#rrx5Oba7=KDl zC;xfU>b~-`Dhj%hZm;nRLibFQp#Vz~gB^>ZrNm&GK#9TBF(n2wQaC*sRRl4ZOyIoK z^ge9Q2ULs^gWZ65s8npB&m3 z&Ij^Fq@T>j-JLdG#KY68Sf^)_=ZY931~Uc4h`~$+V#Hvk+)3&Dodd*RCrR4L=})pf zUhKP6#27J{$*L;7j-CFp`aCQBX;dZYl}JDFc}_ZiA_Otm5;PhZtI|7Z{ATL45_@v` zovhK@>72nJ221bDa(}0Tjl^Jdh)FZ$58EO0cK)Fr{j!p?oKXWOz(qq0#@5OD3iDkY z@Rx%u66BK@>}jb&FpEF@lNij%;jGhGFo?m7oSJoe5Hg6tOoL=(@e5rNgYlsYQ2AxO z%oYJLn29gW3R4C#SXAQ6vyNkVAO6_I9(3^o-d2r(G(VH-C>`bkj8>d#RqlNrm$ zG!(GLmocCDx;BZyUIa#`q5?t;_9!f}WGw+P7zHdQSy!`#Kn!MDFqkz2dJ==_h(L*~ zcqqv1qhaJH#9-;@$E-;lER*ei6qwcXObTK!BZsmEvE@Jv)&lRq1!$!(Fbu}(wjl;v zj4sJ~j^hTzV7H5@mBk-yNepKCF_<-l6#_9BjY$mlG5Y|-V7yFV&S#y^qCpI1YB3{g zDqRCH7{8POEnn7;fJqkw29t>fM0{B{vX?;&W+q&7*7sQ+h{259o^>bfFY@KJSx2yy zKn&J_^0}gC{gMVC20K?2AO_=W<0J;72SNp~y5Ux5T24m+A39_v~ z48~GT`TbxciK150@hHU(1*yumxeUnY#sC|Ja45)$o^5mT`Ey~0=tWDl$rc$c))I`+2*Uz8p*GP2Yw1;((>_#h2-CaGs&3GasC%L zpZr_jKGh1Jh3-y%J?!#H50_b{u!JrIhTo3BXL#DL0YWaHe2R=5!U)?=p)Xe;C=GX* zlF>k%`%iP#gAJtWFbXb1dt0R5l~jW?9T8$#PGn z&F|3&ktx}XP#f;yXY%P|x$9|DMwh2&GeT|djoF}aZlujt)_i6*BVfb*5c!?2R4dDJ zpQOpzP)1IOQm-a_JVZ>2EO#$WUcj)5%!^X5CPOhK#iY)1`SeKc8JOacg;DC&WU_Da zpyd|R(PGmX~SQ}BBwS|rz1+enpFBGXuo`#kU1l=I!e8oe8o3G`*A7BZDTIoQR>xXgKvWNYp2O} znw%Y_UQKR7FxGzCY4bG4*11tesLfNp4cqVgwD}%wHbohsHXp=n(0;Gb<}_3|vL(t0 zwaMtCWqpSB`;0aZvyCr_GD2<2V>W2NJP5hpVt-y5WrS_#&g4|RT&HR-e`SyC&{>&V z#hG)RPQY9~*%P@z=UVO>47|uKI;(O&z~U0QP3KQ8fAf#rsWT;aCdbA-{+!^N@+69u z{_2nF)1}Lp*$;+L54UNu*Ed0by-brStl3Y7P_HIw_z6IAnP9p9Ns|ZJrH>AwUQLR9 zlb>2{4#K(l%;l*e)T_w?1f{=l=kHFV&3ulp=Y}vsZPxlW55i_CZQiECKO4dbwYkQ( zNy2(@5p6zVy?-@?5o+_0Z}Z!9d^)BLpGu6pI)o8w^R{pEU?0oTyepF^lulN%6}*8DA6Y8!;1r?8}eJ%ll8^kmEkmz4Wx^f--@ z>>-R%qYr$e2hpCd(5RLDl4=iO3@*tT9JqaLZI_`}(U(kHm(`)eImie4qO7t<aTrk-hDrx%CWQN|z*w|R@?#KcZ|F~ZhK zGISt~N7_1rhVJKTJI2;&GISzqkZ zBh=Y*GROB(c9bz{bbZVS-M^JaB$tgGZATfSMo+|yFv7n_qkGv8Q|%~Y z)M#JK2;KiOjZUK9)9ff?)F@+s6>pEvX!I#po@4DOW6&P090fD{-jPu-4KaRulp#EH zKYM+a9c2Xa<@I=}Z-e$Yi8iM)+vDvhBh=<%1Y_;-RT@R;;9NV(7&ZD%%n0qVi$>^U zT(<2fW7O!EF(b6c<1`w~;uhLb#;DO>Vn%3>y)=4*eSMN0WsDl-;0NK@_~-*+D0kC~ zoN7lIgZ2opUl;Wn;qwtA?SUaRjY+y$jYd1l2+em*g3VIe@Zr%&vmIpwY?wgX-k%?a0mZx9 z(K!&Hl#-`G!B-y+=X)VXXXAOMfgl^T=LEX&cWz)6{?4~cti#D`)Qxv=KGf*d65WM_ zZHSqLghABJB((D1gKoIWF-v?*I1N)X&&GtX>~XefraRDPcfkR>5xKLO#@XW;9DuQw zj#HXxoIRb*#Np15#jN}UyDw`x0LfEvj^=aac7@%ScJrW^MdiarIf%-0pjc1klSVn5 z%4?wD4xXdA4LFjIp^}fzy-4L6G$E8FR33q4Z#d4;gK)b6bfi-S+2_+a?C)&AG z-T=krRFa#v($vzzSowqKkoZWWTL;}4I7gAKc9PNYiLTeF>mpOE-KQ0;y8uJ#Xq=s4gjzcWBRQ?Ex`>5odHI&1t`~ZsgsQk=W=2JNUmtTI#Flu?RWgla* zTmX5N=)g65jNPAhyC7dFI@ItOJ4-Tz%)6mc%TdE)>><=upg?}SkeOnqzl*w^3-L^x zN4$m(w%itb5i?>n{tK959jOV=$}4IVsDeV-?tZ zXTyHf%&T1(eBVaJB%{Ll(95*?GgSL=7LxDyQJGbI5}r@R7hzUC-iLMMUg6i`ES5?2 zL>~@dKDW+i*o$ROJrSkuJ;-lUcPu;Y37Ju#(X~Q2i;ovwKJ6MIFTz>G(fg!icQ3?y zsOnl{*-vG1j6VaBciKfHl72dk!|xM_yt6Li(0zIURkz~4@=}~d9Jx;qq3RCYc$(S2^o(Q*<;*3Eh97s>rOUK=rC-bE@bmnL7q$ScjiUWjpr6B`_7|;TNMb*r5f|ss2zYwZ^iS zw5#WXBnJHEb`rAUY3HOt%0OT7v`2vw?w==9Hl)Vr7sIKXPV3F74B9$jXci7;awPXLoXY>dkts{_V6o2y2{IY0r9F;G<*Pn!h=0# z3&?2$k!@4aE%|-~*1g1Z*;s(bnz(OFO)Y^-1u=Jf^Fq_zLUmVar>+&LYl*sIEh14@ zQfRR~Hcw9X8wk^d2bMnEs2PT6-T)!YCv^{TjE5e?&x9EgTu7)jS_1E*Y-=ImZKEaZ zHCh78Ko0nOh@%{Oa10Yn5eo<>8!f>Uv4HTV(GpA%3*tr0h4LUrKj>_09^oOJo4+%j-TZi7SX;GKPV|+yJws{? zA4Oa?5xN*BNui0C;6(O>J8(Ky=lY!t++*|)0az276Q9S4$`M||=~x}>cQWugPUwBV zXbz1YER*?xW%GDnCnVMIjNb9^{j#kEbn7yljR(yCB zrl<)3H_scQSCB z=ob(Q(V#-4&H!H)a;&r0?qooPGerpCcAOmNfM%RxGzU)dl-6Q^@3=q+?__|UCy}8& zlo#IVS0l+f%P3HCuLB=9tPMEfI32vk1PR&{HzhX3O|hoH>WiZqXAVb)bs|BN+>w~% zj#!eAn9~L;h9t+IBn>d9mvN#W2!~6i3kaI&uEb1t#WLlfFb8w^0HM7CEF!Rl zG3p7L*~Y}o;_T(Pqe@FlPe*EIW_oD#nLFb>bY?iAht3R&zz0jbJE`CZQbn)n zMT>YdA{$KEzWw?kV4h89zw6*;d00RRTGnN;vM@$WIbA3RLU<4A28i8CI=bii8mZW~Qu(R|%6Ne(2@EEN}Nf-_P0} z{J3V!$0v-*{&*(%@wW%JhyQ@A|AaFHMr_Eb40Gs2MBaKVZ78SX9AJTz`{U!rB1zF!Qt z;Z(n7(J#s!2{!zyF^Usu7@x}U2%Ja*dFydZL-}x=Vf2X6_yyx*4nAb0@DqQ+!DT%I4+BFOOlKTHb7y=j+mq572F`hCWC=H{r|ZrQdqO_8_&t#A#9( zd+MphsEz2h2l>SlM=N|n{Pt9a`SK@xg1l9HqI^0|X#>&t6&{O# zlY+ZzsRy4|!0pa)#7`x>wwd|ygnklkgwXI9)Mgy0fbag@_rwk(%AgsbiV&M>+5x@n_* zsj;6$8!in@>*q=m+aNUT{ReO&u7+utH^P&N^6Ij+bvo0l=g0c#i?C|oTUoJx9=2iY z<5`@)!*){oo5`hybzXoIu`+Xp?WCl6#cEiLB6%OeGIyK2W^)z}+eu0Dn#sIOpJM7u zNtBv#!r$4xUnL0Oi&4po;|wLMHKliO(wcd(KTRx4qNIMs+OZVP7S+5sHccIAO-cQl z#k@G)OdZ(*lp1lOq!WC5=OsFu~5Z2j@8DZ^C25vIKnL8P%m7?bpxRZ+{huR$Y{gk)PgK^?^im*w{V;}5z z%SrV`qMk$8g_9MC?=-}@LL*bllL)Hcy75Q_yGL4_BsS8WQ9geR=b)<^CVd8Bq zfEEE<-T?VI zkPohv)KixYA7vF+9cA9KhOF(Ww1J5n`1s^FT$*BojcS(36aH4wUtfm5khe~UF6`^z zuj;l=hF<*LgS7BBLBDm1@k?V^6Xe1ae$3k@jbBHNq4qtT>AaTm>Y{q;Vs%uVU&mOz zQ6}qLaX?#8o`h4bXuQ9OwT2tw=rxC5KeWN|ej9Wl3T*&cuCQUsYjL6tRJV01^P}!5 zoM?jt{nlyQgVa7NDNG);r=B{_Nby~DP{|SNBT7k0;V^(D@Pv0W>76gbJIHdM74~)T zPIYq6BHlfOwD2xL&pQ=rAHylF&3iMwr=c##_fB<`VjO3gTt z^9ybze{&!VWt};AA33KS^VcePh6 zU%sNPuB#rLz})?X%VvD9mPc*db^2q6mcBJ^pCZ@61`BRxsK4tv$vJKxXLX^du!&3m z%*_6oA-ix=P7S!)UEC2nVBGE_nB}Gri`;$$Y>%R{C{2tQI&FT+B4ZJXCZsD)NX3Fp z8NQ``2$>|{4oT7z{%}7B6}6myD7Eb6;)L)OGwZ~y3|J?T_@~&!n>||+3`|i@*Wc^; zfi)|3)0usUyFxhJCBY$UJqnQ8nN28Sj=0H;Bcr`jpav^r1ykGK4HH5RUVs5QvTK3^ z??mcjz)0K+!NHyu1headGe+}_Bq~v3Q%7m@vBq7^xX3tEqUjn<{t3M(mC*fkoOt(s zN%zquNg3}_?(31z*Ago_F_GR9UHnfx?EvE?IOBD2F|T-ZLK1DgbQ+A~AMD>j5Pzj# zxM7DQO{Z-pU8bEOk(f@B^4set>Dbt9uQ)naNw z&abRVp~BEHn9%)Qbf$eA{uc5&YscsO_X4QD%=weuoFX^V8IXfrna;>@`wn;A(D45K zUA#8w_JymV;cj092RTC!S?CTLH>T9>o9{Hh4@9Mfu+fFv*I82N4tIv<6d-uI#9)V( z0lG`efB{%eoG2<<=ne(hKX*(?aniAsh|^hvq7fPjO#$St95=J1WSl#cqa(?|a87pe zpmW*_LGACHQHWp$ox&jQ-#-%tWTF`UgOg6W?I!0V>ve@WlEXMRrECa{OIUt4$}fi+ zbCZP^m@-l@b`e@bWu&lR`0#vI3;DW3L(XdCNAFVd-Q*E&N;aY}#zO;Lx7bY{YZS$( zC$_aItSQ7HTirOJJTn8(YTW$CkwH`L=1JJ7@{NVr0K+L!JF}FI(OimjW$iC}OmT7= z1*af)k>Pw+O{ZV7j7k~817!0G%>88Bq%Sgw3XLQ_v5`$q5mmDxxaox~;M`NoFME^W6W+VXKOn1J^S|lU8Vqi;RUz zg|1v4=&4BvPo*L0sY&QxYRZ_6*`>tc5RiD|ewnByF88oR%NHUpSSrlGS$Hd~VT1s0e! zp;W6X+q9r+vQRkKgU58*j4!RzBe*lA2eM6=S*YTRmsXWqy~Hlt3Du#xK`caWG->LxJf*}13ZXF9L)G%&q{}-89`sve|q_m+b(Vzg--LwAEhF5v2nJe z8%$@ti3cT2^P25-aF?SpH-$RzvMTk2h0L{hLJ`gFQ4Ld_%RftEW#KCHM=N}txpLsT zk>d_39On)vjNw&ecqu|yTrufgCzscR<9OA8L%3#TQjKc?7iKJaa=k!Y|4cVUmb1(v zUN15WxhM?f#LG16Hx`2A62xImDPU&2?AUG?xs{B?{6bVp0WWoJEO`La;(BM6bSKj; zFjsD>~>U!_QcM2n0?L={7o+9l|!z6C<^(*S}sDo-tk`oB9}BjkCYeT<;ZR&%&vlp9(X$`K1E&6YSfbd>AVY7qCX$SqO>yW<&3snPDwHES*QQIk6( z-21ark2Y(7UX2ROr79-*14+k2Y+#vtt8~{MEk3a@XYC{wmpUm{oa7IctSw_rak-}O zv1YL5`Wey_SW31>gs{J%*6?sv3cnoMcEgI!x+V1uUDzC9Zdpm)xRTNX8SNLZE0>Ks z@QG+@OV_-n)ic`~o7OJihoX|w3R)kiE-S^p7E2oO337Se+7<0hZPrOmElZobI_pY{ z%MY5Oym;bxs}7&FxQ|MmY)8RuGq6Jjch0CQDK0IqTUl1Z{aU(KEMM&JyV8N&6786M z-O7@2+?--*Tm3TGQm5DU6^Yi&)v8;zc!}&}fxTPmu?xmQs#CY5Wo=Vqo$(Pn=ya8p zVy}yYhLcuH%(-L9lCCf*&zjSWfm>U zd)2N4O|*Qm?o-pzRF9o}un$dqyP9d0i%#rp>gZh5u&jQ0eMfQ0BJ6~5M%kii$IqWR zziyntMOE|XEW(ButxXMGor|z_Mz11JGt+!s*w~}%fGF$~(vH!BZ9bN?Ve6cR6)VnY zX~G7l^~=~vQ!#w3x~VNo%?2&lc4&=kn$ywLi5*m}*iI&i?PU6k>9|c%^NLj+y^53; zhd(S5#jV25FW6wGUjIrj9HhI(qf?pP@|HI2ceK2HRYy}@dl$A{;kHLh{GrIf&fyDh zOUAPR?DNrx;Z$e*1u=+@SsKc)mEC9LPp=VGSKryt)w28`+czbQ5Wlp<%8$p8=1{F; z(-Wbda$BeUd{)xKMai&eW)?m|}QaA@FGXSq;`zwD%lB#oB$%an;Hc$r{R=Nt%^8VYIzz$Re%gZ5mHLqH}7`O!b zCGD%r3p(2i8cW7g!?{y{-Jy@dzE+J;)OR#AABC!}p3qdV{D>v(IR#4_*VK0`DJab; zm|d1ru%vB8L1$M-O9N6ZYpL&SX^5{+eGe}0FrUM3ujs8_;(z-Twl;6m2OWol{t^5yk%(LxBjN~57;n_b~r zG7Fc`#4Ncmnn}MHdlg|l#&%81S~{_cE$3R>f+W?rnqd;1I170Jb@k|6-O`ASp4w#2 znH<(M$OdTsC6zmmTkVN6zmAtYS)cr+ehQYezkdra^TqAowGY`rrkynKV!7|YrL9S- z<#(ySu*h1`(%FaxI7klu#2w$O3C%p^9YA8g_=6-tCs&EO=7V3#Ini6%R?o89k8i>C zoPXv1>A*W8EJ$DAni)iL&05iBdSCa|`h2Hzg3Ovd?YO!HG9Jx!V@*d3_O6TfD~-&a zbg|((g)3})d$#tH&i1mpV#}bp6FKNkMY3I6Y%CtSd1c9t?aBr_!*pu$T)eJS?raj9 zRVHI%{ZJK7lRB;?7_pdvi!m{ltyqlvxWvmi+i6`BcIIoJwqhCD9DlK^9RA{-34gJ` z`=h<3sj2C}?loRy@ z=(b#c;CG@<2A8>CT)gZIxxGZyjIr8C_Z;AFCM$*Q;?=0G60a^o}kQ9IAj_2>* zJuYFE@QQ3Icc_~tb1(e4P38{W-?B<}%64x{c~y%w`f5y5Tot}xxYL`&+DmI07ds`d zgOtj9UtEg1R-93{tX>wn#R(fQ9wdQ3>p8;@63ybws)Dt3X%`lI84^vjtwRL%dqX`i z@;I))V1qn=DdjE8L3Ybatfu)8gIVa`da&0~T*6HdhrhqSUTm@DhndgqwAWrzuk)9P zWdFdF(S#cV4PHKgC@TaZgNk7lz%Fk^+x?ZWq32_47|X`NZRorJILK{H*zV^&$2IoaN5x z@6PS#&g<*W&u|y?aZgNl7pA!M!nouKe9Tegv)kpT#BqzMdFM+5Cd<+XyqIF903d&kEgUNQ0E z1LFDMNc?c{s7B)9kjp3G00Cu!#PaZvK*E8is}m%~^P$f8;Rs85qRhtvM{*7<2h#fq5ichvp@Uc(Tt@)|B$xfq7@?+Z?LfWU`*5d0!;Nm zFY}+XkA3G8%lKeRBRKEjXavvfT>~5jl-K)#o8UY3mn!l(Z^n;@QpM{O?^XPX;%>!XDSo8r@TnK1@26O;DEkyazgT55B++hz;@1_gQ~b8#j}&Ep zMA*Ng^81RPD2Dm`5#pnY6BUnDl>HJB-=uPv;*E-TE6To!u=|C|sTfbpcZlLdMR`aW zdeV6?eu?5L#f^#&DgIQkNAa(UDR{<-=?5#0QIvgjpeJ1b}4Vu|7u#kq?0iYpb*QQW3@gW`7;A5;8=;##~3#q!Qq+^%?|;&&DI zDE>y#Q~aCa7%a2QhqTDVnTn?3q%5YL?1u=vQRQzb-mUnc;tPszDfUe< z>4z(pC{9r%#{%>3R=ig6A;q^8Ls$rDm#=t&Vu#}8iVrBhrpU`0(~;hnDEs#TTUEY9 z@gBurDt@Xs6!$MoH(9Ykag*Y0iq9+lL2)3~W~QrDoT0c-ksJby?@-*Jc!}aQinl2~ zr}&{_f2{dTKVGp`@odE#6rWJstC)r~OjoRUv|_#DM#WndpHuvUqTSD=&rm!}u}YEe z>N5YeiklTLSG-yAUd2Zhf2R0`VhFbv%qLTEqT*K+&sF@U;sNW35S&EAkPgh)_*r~Xdi2OFHe1YQERDYGq*DBti`a4y=NAdfre^lis z6`xi8ODeyr_=f6xRNk-nC)Ed{rapMSQ0kRJgr8X|4^bSeSgbfjak}C{#ahKy#WuyW z70*??RPl1fTNH0od_eIhiq9+lOz|zncNITT{Hvmk8%Ne7jfnp0t2j{gxhjuRJVNyo zR6bI1vg&84JV)_##YV+0#kGnTC|<01jp8oFyA;2xcs~*TKB4%c;+sT_KL^iL6LS@( zDV|B>xFX^n;{wHtiKzEZ#TymxQM^y_F~z48pCcl_msEaL@eS2~pz?=`AFJNNCS)ux zsF+MdJ_A&aDvnk>La|cuXvO0d=PI7A*r?d4xJGf4;uggniq|RLsd$g#!-|h9zNq+; z;=79b6hBq`n__CVsb_{_CK2sks5pg)dQVrJtvFv19}8rC!EL7?F5iNsyn`EsE`mU5eWjzoB@I;x5H+D&DSmkK%obKUREL@hQb; z6@RYyE5#2LKT`aQBEMANdQ9$pqI_-w4p2F&$ZsbYKT46rYLurb%6_wuPf+<}#sA0N zm%wLHU475;tVwtb5J*^k*a8{|At0b4h7h74%C3l%kc5N;LxM?IR21q~cSS5Ju}YP; z)|KK?+Pd#nty=dTZL1Z!h)Yey<@^87J@d>Y1fg&H{l548eeWc9{`a1H&bjN{J9lQD zd*&;O{aM6|{aN5CN?)$XABR!jg^Jvgjo~{Kv8|_sf1~)Y;^T^9j~4u5j}|EQXo2r& z{0E9V6n80puK0~2K6#OJ#4au5J877^!7)Dr6uA)`!$&C|r#MsbB*ijC+W#Pbo#JxE zQx(rrqvv7Hz>-wAN+S~_iLr)3|O&d_s|X z4Kh4bairoHMQ%ID_~RA7rzp=2K(E#CQpFXDVow+G@;m`}uF~as0>VGl@NJ5}P~4_? zui|5hG#S8r{9f@D#kUpTQ{>Jp;%IHDCQ`N-Cg(xXn3%q*x!X;?C%06D1DNm z*x!YpyNpvWcUB~xp-2-E44 zv4+1;+^rbm^9}gKvz)G#fbk^Yk6Yl_?ulysU?Ahs%grO3TO zNzYMCDh^Z}s#u^nR*{?VQI7kF66Y#bD=tx#=VXXqq2Y5B&sXH0qm zR(xLZCB?reeysS7BG*3Di@g^Gv8SS7Z^fh{_cA5lIK?T7$0;7KI8U)gu}<+U#q$&| zQCz2Zwc@pk+)I?}lV2$QO7T9$#}uDZd_nPL#kUpTQ{+aZ)VEvF;d4NQBZ{3AX%~ug z?ovt|qc~oXW^YKJtVjz93?HvJPf?yjg1%V8G?PHSX2mlUzpr?{;>C*G6P5fwQM^@g ziz4?&W&9J0@_ZBF-)oqAr8536ik~Wep~!tx8Q(=QsW?!vK#}GV$XBdbswmG#L9fy9 z3dPeD&r`fm@oGhRZVEYW$V$E26uBEK!_O(cqDZ3$q;qRl;#Z0>J}*T$L$SAFQgM{x zSjFQMXDU`JE>S#9QJ&92FZX?={#zBdDc-C2jN=c;!TR&pqKFvD*jIK_ln%Dm+?CkTNS@j zty4w0GPa{fZ2C6r zfX=?eV<;S(x(JTP)$>h1#3NPVAs^G50TG*gI~M++zMG&g2^#e=FP^?e z_=Eb^BJyL19 zD0+Oa%*Fk+$E0!O<1<{McT7DI_ZeOQ==H1J@CWnvJo4w27q6vK`OAPZTx-ib6-Uo& zdkuSO5d+=BS`EHUAoc!C@2^`8nnWZBgPa8ePP;~NmEPxz0g>1L)zBe@se8D zj739GmY&wIk3ODu*_Q8@W~`eW>vTnIePo^W@pEgfoezb>yFzJiS|^lF`xr(q*I!<0 z?FyyeTsp6He8GvW`ua$VlUMY~ zV{4x*?O8f27TftqT5Nqr%bmMF`82*hz2!|SZGESf=z42FX#K>}v|XW$=Sw%1MqA<= z53E^G6KeStY?9Ay9ho_=btEpS;+&b8MLn@&w3KE_>&WC&yRAv~59fp9B!u4n$eMJ+ zPCN1V?gYx>NLk!#OOSW32GUBNLfp{OwYwuW?rH}e1F2y>osCBW7wxn|k&WGUS(7MX zA33#kWKq|W2VRJ7OuHu3l2#JEBDT>Uxv@C3{`MErwRAC*?)lQ=UXQHrS$f%r87*CZ zb-)(bC%-Jx5?dcfyYwi{DSf-OVC|IBlS&izG<@2Yk#lkBd8IR3$8Va|8p^PCrr8r) zL%nCUj=y|H&8D4cmc28c_T!y#`{CBmrsCG|)q!`)_eQ(GEJxk;3(^{feylKVI|02@!2C(NP zW~1jtTKd$y*cy5;)Pf$DIUBv={G1~6@R8PqJr}f&yd1qO6L~I03*i>wvEBGwv!Auj zzH06643;IvIBW2>omT9z-Ol30JM9Sir2Wip$7cV`*<~HQuB3FA6~Pr$JZ(pWMfQvUF3==dfj^Tx-BnyWs9S1vrCVC-C4ixLl=Fn zlk_>KCB8nUeXbb2E@SQgn?9Gy4SLw~rH=GD=FM%1gTgTT+_JkvrE6DJ)ZBPMr&4=J zzw?Kb#-IQ8i*LRiQhH;}`xo>(|GqyjD?<1I(mn(KJzRs!Fd4G>o-2blKp%OdbO0SY zau@D#+_kvzcJgv?)zEzWSdbhi90k#p&nFMAC4BlsmTT+3>?g>=P7w5vNf99-L|;A#7A*MGu0o?S71N zcxZyTb-7hrxKaGEuaU_}m7TpA5%Ey?r!Mz}P2=0A@J$&5=pO@)@Xx!FZl$woD&Wf? zKfaZYg>QseS-g%|f>Zb>(I0{Az}`APBMsjiE&vtAU@iAjWGj4&OHua`D!-%Gr(iuG z6bao-9y`VlKEw38s3F146>1PD3N;jtmmml%grbVOJBkw$0yCO2BBDTWePA)C>{ zbd!Ntg71Bzg;^$;k@!9IL<@VFU}opCRaSIlI(PGd>2FjN-_oYvgVT7Bq-?m;-Ubx| zqhn$(f|lrkQ}ocdSH4x$cbEo4iG>UvuEAJ>FAt;RG?DDgPDmL%-VPjW+f(3 z_DBupBv`s=kp_DwuA%G%4JNHFToc6X=#*GLq>;E4tr|Thjegd89|ot!8FXRVIq?R= z$EC4g2s?>9+;~T4X!smh+r9xYBfu?1KG5nyi%6H-(eK61pmwS61zqT;_A$&^S;SO9 zD8aUkmdDSQ*jR!Yi&peyWw`_J6?h~>#p$$IN~bAALf0VB)y}L$)?(4+u_q8r^kE@a zbf%vP{ejtD=_LeB>~)#HMS3;SyJJPDzRqRKtmr*mRG@QNqZR$7*AqIIt+b-sG!#qx zg!%ead?EmryAynm8U3{e6P?Q{s;%g6I=4v5nTc!3e6PypBxsQ>`bZjU$r;c)@iJo{ z>+>$M=L|?D{zz3%^hrad!fJqI_@Rpx{hcOMfFKI+ zoEBg#f+)fBn(nwn6IH#~dAi6JCB9&NywrK21SfXJ76n%HRaI4z_&K}N8!9_B(aJo( znU*ejo}L)N*mt^=0boTw@eYIUXKawzxrt|3qCX}sl;HdXU#3O>q@8UMzO7(eQ?#3$ zSP$Jc^F%t@WeK9fjOzX%vN$9ZUFgJEJK0<*MJpW56il_VG8Q}O4@(h3*-0otILm}% z*%eH9vD4RtGqMZW)oPuX>1&zTz6IeWPHZ=(P+YOutn=tnPk%x7X4X)>)4em_q6`?7 z{UOs^=EaZAZe~+8I%xwWeq8o6roY_Lp`<9AzgCE@@c2uziz&a-i$6M>Z_lHvoUDUH zeron*tj5zl{^{8TOndPFG$^?tmwqYwV)?$Mi^jKh(FJK(KwHeb9(Z*wyFV$vP3J)E6Oop(5CM+wJY!l-{<3Z{|x zx-`&864XZe1@aUL{R!%_>}>eiK?AHLdF`2rD5Hj7@(?QtlSA+IFh}9HCJqRk;!^MhLuiFHkdWr zJ)V!Qb)qMsD`kI8*0Y?P&ETM_3m87z>0;V3lzkrybdHlrW*RZCWv~xvae@)7dx3JBYhVmdiL35xWvgkT?psf+58mNXHrv_! zVkLUHN4V9_F6PCw&LiAqXY-qn=oKE}UOW3JimdktkJ{P%dLw$JxgOD7Z7ZEKHFG6( z+QWpIDG5hS_#!WyZT0v#dW{q1OWf>BSf|%Iz2uE9>U;_7>_<+HywM%7%1Y;`&VZ=u zW2Likcp+)H=f}}A9d|bfy*TPbf9RyMaeML0jOcYvI#V_2r{hWyp&Tn(f>i8Ch@{>& zhXLu`=wR9KM?#!+d)vJDylY{C(1+uk&OUeoJfh37`h1@y$ak|j^1;gKcqTmD?NcQ| z>~G(Qc-)VDgxvLAhEv!+2w94q-Fz_~Mt@U7rL`_MM6)@`4LchWX6w+rSrvZc6VrsPmg8s z?ved^B*QaeU2l=FlYJjBKGO@k+58G3J}cHmeyuPdl)aezvt!*pf^zoz43r{1$J3XQ zJ%{|qd*Or?<5Q;i39&Fuvxb?4e)fH=j@Kh78s45G<2>wVGw_LO4rAWvOw+e3K`evo z&m7xtc6kZ@G>A~Fe^*G^Z*^v-3K2e-H0H#9y9*0ek1+Qa9)O=NZtt`il-m*7NXimW zGD#T=6}-(Ga55-eNx2lEGf9CtzwO;g;j^62NU4Wq!1qMa*&wZi8&D6+fbVrC*T)FH zL{e=zNZm-H74_TT2Hg2QRB6DeBqc~%hSJW18`zn}e!mN8<4_9D83Q+i z*M7ezX)Op}0yk(GY!?1Ov<;#)$3KV`ROrn}-9FJ&=n~}jpJ28Nu*NYJI!`LJ9xXE$ z&Q$10QlbAq_!H8kLg!0`_Q55?Z%Ryseord265&~Jtk8v04}V7J_oSdg7fOYmiL0v_ zjupC4DwLPzqoklh7fOZBMrn?Q8?Y3V9-C29&mqK)Dpg!As=q~$y+x|HT&kGg9Mr%` z6_-mD7oorKRlihmg;dJZ2tGg(tGGfcXC$7|9tdZuxI(Jkv4p z;!3}YE4?cIl+96WsyH9{z7otfUk&HN(&oe=^t}Z444kR-5~=iTbpLd?!F-C!E`BZ; zhQQkHav1v@0-Ajb2rY)_!ft?d@K8`!qpY}sR|4{En_mvn*?E!wH3>Nx&!M|_wcSK| z*jP@aWx{N=Ln+1(X@@dLIMRKN9%{G}92DrOb}u#9D=3fgzMDNbgKT|*#uAM^$G#z? zJwBagHGS;|4zb(>KiEi$2hG;+JM1X-R}+sx`-lTNu%kGz13QX?f_&(G9hhVs>=}Dx z35Eo$KpqsZ^vF0`g|uic61{AH%rjzCu^bq$BR-756sG826VKxaFoHN8P(55zl@ zz&sgSBlK0kK{bIHwSDUrNLLPAydcjYn4+w^YmJF%dp230Nnk!4Yh55eGnpTXlN^u} zvxaCbkWebZ8*t3ttm~=86l|6+0Tp~JVN(#Z2W*x2b+w=iB>4F|%=v9wLl37u=%p4G zon{t^SyIwD1Wtt!yslUdV;?2(vrb?{ZvlXHLJ6X&rUhO#1?@E=R*#Q?Y#7E8e+nmA zq332eWQD-&2;FM{33yr@l+D*^Dny=FSnIZ|p-1b4z*=Q$RCGKX5+KZnLq$&|nw-xd zEP?|Ep&kyYZb`Ky!j@-4@o4y;go}|Oawckqq3v*K)|o=1228$E|g_>{RiWS@b`wpI7285MA6SOB8n-Q%yPLY2PhpJOq6dGAw%F& zF=92M0()Oi|4ncQAbh4Za^Sj>NdL%)+}_uZMwUt?chd>H^UZ+7$bqL@{UfJBl9V&y zx}>O#MK6r>zWyuFW5`RyI>jO{{Yf~~K4BnSRFZ>{#-Rv|gY$UlHw8@fEk@#S91L6u zsAkn;3?Y~cv{CQ_gwe%jM<{L@J2lP--K#JOP@{L?PSwS=fn7>@X>NyudJc9brTKxB zLca3(UQY@$(E%ZJki2eCBFAW4lF4bO0dm@3^ zFmoM!^WZSS5tuim0(EVUz+6WTT=>)5#B0E0cP4>pb58T~Fq3&u>EKjnWHAJJM-m=f zpLn2WCvDks~m3 z;_h3%BH(b~SN(zzw57qxa7fSPaGEeHmF&a}slz#hTsUtQIU1kHC`eZ+?d9# zM%T7A^q6{{NnlelA56kr^fL*j95V>>;gBIhHJm8-@_=w^PA!7}UO3FD+svHG5Sv$~ zLeMxpde!R9sb1X%=2S0He@^w%4l06P@37f~xZy=MPavER2MeTjY6dXVzCZUeQ>>qk zDr$=eqX-?G$pYbs`lO+~yP zE`n>96Egh|!s&!eFI&}%Zr8HrCTfP)agikJn|Cdq0R5&MsVO*ytjW()EKbA`n9cI9 zD^}!Ja9-Ae+2o}gm#dg&ol;kFx?agbWKQTP&#cgSer6+%tK67{O0_3aOC6=~T?~hQ z-V>=+z+s%_OwYvDLyuEyj_|IKg- znNc}CkH{r`91>-1U_kf`fKrJF=VSVFB+(g!-f*e;n3MA;IB!0t-(+wGf%OB8(3d)7 za)wG+*+e?L8gL~LOzI~R*d-j?V-R@}qASmi_zqeN@$cc;gKNyU{;%b-|7n)XWWzOVQay4+ekD2yb~vr7F2_E-WzDB9 z6T4z)c(W03GmMO3rsDpf#+PCN6Vnw%h#U~cXbS@|4O2{wpu!l=hq)%0)quf;P~_N%jp9V+ zbq%K>9E}{)Eu0bQiOOW=iR)=S{wQ3)z@a9FMunhZB0-f7l18$7si<(X9`S6_J4tyWCZi-qisXEN*s`z- zjbv|A2h&XmwIn=+h6lAkvn)31jfRM5v#U4IajV#A9n+JXd_&YwvRx?0Jur!ubLXM6 zN8DUoAQ5+-orDdLKHc1dY_Y_J#!TXx=}o>xDwYa_nWQgVQdMXT! zNM{3C`jFQ}3sU4Z+@=(6Bw?L8pk#aS(kJCf=(H~%nrgfyF+aRsX zRbDUhM?&c-#;~J|S`s5Zu{I^$O?(ARRD0MMlZ8R1ufW!!7nb4eU_&0J1=+{&Cgl|S zQxP5Lm{7hq+Euq5?O@<18*#@*4&{&+jg045$3btoTs3K9!-+zFs7u2o(HVTeZtx`J z`gJ2>o~)~kJ-miE#34bBX(*sppR}GC*kGoK*FCKJ@SJ5BA*WZ9#1)#*!OAIxiimNi z@f13oC$XRz-Q$vt&0>JOt9&Irmm$L%Gf)B+i$`pYP_0HYKKsX?hhiq{j`f@9QN znYO_#^(39i3?T)75?X{b`)4keFYHub>EKIoSV(E6L4zt-Poc>JSX;49 z89kC)tBVB$F|Jfwk1f?}>#+&D7`55Mj*Vw?=Km)%Gq@Q3llEhHp#%*A@aiK?S9SOW zYI9X%b=|4Pcm-_iRGuttktjtduNg0WXj@SFz^hE{I2Cfy2d9v9|Ge zN)|Y1TcT||pPTuIE5Ei6hSU52e6Gb>@sIz!Er~2&Iead1+Y^Xqi1IXj+&#u3}wt^Ksg($MAupPkbN1p8fI zd_u`u|F7757(uztmUX0Jsp2t;d;!jQzAquxDW0OZM)4fQD-^F${F&mdirW;QQsnQ0 zsP{d^zbk&G7(qiYK0`4_aiHR1iu}Yw@~3#Z;zf#ADc+{|OT|YNpI7{=;#Z3Nxghl( zsmRwd49gy%K#na8%U++r^EG^x;!hRtR(w?PCB^p@cPZLVuWw<-Qk5zik)Zqr-b=i zD$-9@JWY|m_91x3c=SuX7m&)7AwwFtWa!J zJWKHk#Tyj2Dn6|EqT(MFKUa+4gAV39TXBfup^8%!Hz@v8@jb=ADP~}}rk=TqixpQX z{-i$B-ONsdW_-f_5QNuq| zyjAJH)bMW>+3l%RTBA**Ie4XNrO21vhvR5DUKd1CpiMYnzRD4(YKGOKl zG~BBAwbEnI!F=M@ORzH$>C0Yy@XKC(z(GncAi|AOELId78}QH8@La`eMX|jB|0)fy zR=iMAY;wT=BMtvpaf{+zijOEhp(wUH;D1BIA1VG-@e?A-^RuH%IwSR9v9^wHjWk*hqw&*bD()tKr*;(7#m?)1~x#499|K z7D3*x@Ot2{EQq}o2Pqz;I70Cd#qo;8ic=JiQ(UQtZDvI8S&HW=UZS{8@oGhW>%n~7 zsQ5F*+ZDGe{z{R*x+4Fhiccy&r}(1c8;b8J{#o%aik~Wep~$a0sFz=361yq(P%KpB zSEP*RkLrmN6elYlt2kS6u427nqvENGXDI$aQSMKmmme!q|5n9cDe~8pq(81GpP?Z9 zf`(sKd|UB7#Xl?lMUfxyP>9D->H4uUC}&Cdl8c;jN1IDBh>|km6H{&nn9O735#j@VknC zP{cw&@)uIV3^e_BWVpDBK=X!Cvy^q8X9_(E9j`+$4f<2+CKhbwYJ3F;|QJVtSv z;(W!0iv0B>`A=4CQe3IX-)S=bEX4~HFHzj6c%34DCrEy|?*u-i;l~u8ReVA5b;Y+8 z`J+P0dwZQnc;AR{nj(K#$Z$8seu{$>hbk5*dV8N2Y4|9`V-)#|Me1u-JY8{(;zf%5 z6+HPiE8e7dhvJ=zk10N-C^pX^_a_bSQv6)e+v}VQLF(_M*jbU=T#(*Rk-w&7xJdCR z#bXp_DW0IXP;rss$%+k%s}xr&%6&ETU$5bxD&DNlA;YD0`zLev5|hQv8kL1B#C;{#NlN#n%+yRs4e@ zf6vPNeyM14oq%vyk-u$axS!$>#i5F$6vrwasW?%Qzk{XxV#RtzSutIf^GL@^{%xSJtDz%QU=RQTB!h{W=ZH z-tY+Dtl?iM-mQ3_;zNqhD!!ojmg06r*)tycWY2iu7fRo)$Y+JjpV&qOcG7TX#XgGt z6#1ia@|P%1Rh+IUd&eVwzJ_I;ig1mFWu1!f=^DOR@p8qh6|Ys?tay_mf5Fc5Wt|Fq zMZ<3>zNh#n#a)V@D}JTO%}J?8)~Ucu4fE&lq>oV?uPEzM&}A=q;7p~5vOa~JtWSaM_mtnJeD^Byr}@mEw|D#>HT-AAzbk&K=ic=M*E1sZul4AQksO@PeouMs62Nus)ry-GH!I$% zD0|9-Z<~hiRpgcelz&a}UBy2r?oj-jVyog;irjvH^1T%ME9NQ=Qyif@^Sh zDH@)kI7bn;A^*`mun*^*!RJYIwS?bI;N6`9$#lOM76a z_P_4%orb?X_8!r}m$tI?bV^gZ*CxS@ssAT#hb{ZzVreb!UjS|1J2H%BlcOKbhv4^Q;I)1?sBOJ? zak4uQ;)}?H|~BhTxRGm*Dqg;I+Piz9c<*cyZ4o9L(RX(8u>=3Q8&u;Pcpm%Ozk1Zz zg3(4`-}_ge^GnIp9{X2cwB@2w?kF5{qS#S*``V4A$MiiZX6=f_rtSECeEG514LXKh zk`r#}v>g{_WR~`>IkDBvjMS8TdYm)i)8nGy9g9K_Yz^-yx3AdRf8wDNfB$9Y&#w5g z->x1Db9aY!mF~{^9i59Ox4OxBH49qZqJ<^JpB@*1ynPSkDx3>&UKGlhSUAzH z`Tdt!|G47IfuGD<*l%~_vkAMqi*#1;agdIUyn52YlKWqnwquIhvNf_kiXC=~KDlh| zyR8L3?ooP7tY>Li&PkKP>!IfHiH$gbZgr_Ww;d zEjcxIOLJ+Dnz^m+^cTMD_Q|?02O-bN-OjF}-CaI$cBDDX_0dQ-zSFh8ncJ!6XZ&69{j&8*_PWo~>_IP$*e$8nKZR}d&thZZ2BW>)c%iXrGoAlU= z5!v-PvObJ_hhC2|pYa~0H+&dvX^BO#H+A@$Sj(K8Y1VDrqM%>TnvduH{>x0%W#%V6 z7shtF)@Re5n!kXS_0<($W_@yK$wk=9*-cJrbsvoFwA>F~OP3vnf3wRv;GfS&Tf*zF z#%|s(LA$AuX**h6rt&oQ>E+ih+)w&~EoD1qBrYn&&e4vw-un1=Yx|Zac6~ci+CM&R z$E9hDj*ahpB#xbzV{HHPr2XgZXZx3;{c}_8KSkOfwY{J1KLPFEFV+4mX>8;*(*Bmz z;iKKJ;Vwf*0ik+#!D``axp+TUJpq5UoF zaUI)b$F4^Ehg#ll&Dzc#*G=A?*IC1xJ}g7-GoMFJ`-Mhgzwx0txC%_WJ0mWdgq_ES zPHc@Gv+K3Ev@hH4U)`7aw?n+~EM(8dz?ShPMk91GixYbAz`o3VFkZWFV!{oj_GLaD zbF=#c47Q;$=$=sJgt?`j`xA^?p+kFA2q{`X!4u&R9hUYs2^qk?%+1u0+LxKLx65bPVcnN`7NWz+t`kY`30>iVS;xa4euRYa&=elpwU+)& zG8SZU?8QESd|c~x!70*aU*FY{BV#;ESgd^MHtu`lytP{TJvi_6F5@$OP{ zng2jmbK<%$^C3_gZ?i9R+~1e^6J#^)@5_9i1XKGmZ-U}@n|+z%``nkgE2?H-T=!+} z!nFN;na5C{zb`Z2fW`fNnd?xNxW6y+*DR2~FY~R;n!hjeHz;D<-*(nXhE{yY^+~lljZ-xbDj=_3iJ=d@yt7 z@5}rV^X>1;%#6kNe_!T1*ze-HFLMD4>F>)tmD${5U*@Y($2D<(U*>q5eVOBJ_GOOy z`!dgDzJ3*#3mE${H#4bUYtZb=9QXHSo=j$cU*^9t=nF zeVKE}?C;BbDof<=%ghgT;{T<6nGb^GkWhS~?#ocGRGB>eW1N$=bjZ-|ZFEg*JcyM3l%a}lLU*;7g1ovfrmMVk$ zGJl^s{(JAs%zaGa-oDKDpa2wl`!ZLt0)zW9^F@6;xG(eH$?@;)%N+OiWuD49 z4eZPOBJ1p5+Lt-*?aRzjC+_Xb{37dWulq97Zt{O>U*;l~z~7ho8YUdvmw5!@aX&^A z(0ys2+U(1m=IzUT5BS$4Pe7GgNjS?+%7?X9pF2QG^Y>+@RSf4syDL|)W?yD`L5-c7 z`9LJNFLRGfr$;P(5guV=i=Fmfv8+eH;$TPSQs{Jgdpj^Y*-J?8RQAREs?W9(zH^^b+Qk+bg0d@zb>UxMFDBVM*t zBijA&@TC6|MqO&lp0@mm`cSz3%(;D;-DNuhd{n`l_Rm0HwJ*12E8!bJxRylb$zEr7 zVHx=?)3a~`u$S-;jW9n?;>j+qDEkw_?+Oh&G;grGlP?FEO27@M#TLyQ?4G1?SGc)CtGDc{>;t&d^2G>W zNZM@6zS=(Ed64cv@J5ob&+pZC7m~OK-9Jg1Nm4hGrh-J%00W1EZeL?W*MV>mi8M(M zVs~;r48pHTtYVd3WA`R80fq?NpwDu#Gc_`Y?P*X1`zLm%v3RbQ8y$>ii-<3V8_bv? zS)iPVkaS8TR|L7R*{bjsJHE`5<2TNAl&kUN&PM3_aGD-hDz>$j>D^(+H+gbbgJT2b z7;_NQ!*{9)EYRi(KhN{&yVH*I^TFJFL~RBC7P#Dg2+-;bKV-@CSce=A>RX_^0S9H1 z5u^%N&I{qQ@3#B%Tf*F0MC}3>hq2uG2ym&yudnkcK-M8EK%~h4>d=+Bj*bE zpe+0YDtjGK{K6$4F83J(Cc!fiE{_6a9r6LF^FWyk2W8(wX-RkFTn(SS&CcN4nA|fE z#pU8sxZGt3oCD8UaCsCU>yQgUh}|Yw_;de!vb_QxS{!S8(ivlOiS}n9Jb?lTC^@ z1fg6wZFR1yBNpd>`zbrVflAoRCWC`t$qZ(Uwz~96@+V|VPy1Or{g|Lb0a=s2e`$fC|)l|mbMN=~G!Ab9Gh36k|c@!Y4 z^e*0`@=X+!vD!&@C^-Fl}hRdS>S*3S90}4N|(cVS6E8C*kZ`x z8rMZ-Yr)0uZt}cXkv|g@eszPIpgg7UV=SEcQyRO~?zGyI=eIZODDTCJJioZP#mKYw zQOcEbCgs1hJ3U2tj&1w~=Rr8>eXqjvGF%=7$SS>$pXKa;LuT0fNO$F&MP*;vx!v(T zM|z))C-VGQM|xj(1hU}rC_q-}eR-f91P5j8eWW{b?rxODE2)f4Qv@!4sUuCpPjY6# z8a5|kvCG34Cf`isN1~W!lzaF7F zUyh$cyK+-tC!9`OJ-M^N@qNnic0uI$-A;?h$(TjCxLBeX4WFIqbo!REG9!X(3!Iq| z;du-$j{;;hGa@Mbut$3h>8`{cMrB=`+^O9lFEb*zXc@uGh`8Si!R1katY$_8r3ak$ z8qyt!9dDGyuc0zlDZl;6hm$Iu1kXgcJPMFis+B)KnG2`AhIB__i>a)ellcLa$&3iD zrEq3Ogoj@S16Ta>TJ?1C%&&-Uy$4 zh?BmJiey#<*HLhJg@v#SWYn2 zTL@19+~D)Q>Ya?xQE)I<%>nFIQNr^UIQs}EDoPfBV?La;Q4>7;#wgEYlXf~El=I+l z46{F_@Clp)%xC^Bh_H*HKVQ};b7hIb-?h94moH0{6J>=m0C#T(!sW{fWu7chCL_#m zfbwO5a+0i1)*-wGZaCH_Wf|L%Ob%{dB5=d8JSjVXl#3Ah0V!CWl!^Ac5W1NZEKbT~ z1rx%}fde<3#$y(WqJt1TP)JysEX<^)a}iug5?3Y*vq<_H!M_R#3zPCV*Cnelfu068 z9P5&bI9CimMrb`LSe8^|kizd{{y_>>B^9!CnFq>LxB^*}REpdK2;V`PtVt>}DOteb z8m>T=B$cvExd`F2;YRSv7=>I(gA;=n-|4Hh<*SLUcDe*LFgqo6&nXnSl+$c z%j5h#vWV>j!$%a$@x=If55II!v6=AL@@n2bH9p)E>jtK-aDxjFtv9BHyliF*JI}H( zIU{~LMR?T=2m3HMxoS$_;dGKWTRG*bIT4f-;IMf+XKZS~1b{P_8TOj~Pf!l^H(-pj9d-M1~}+qf2RgV&I?3WxGStmOP9Y5Ot-*Emwyi`X$|wa|L|%Ss7*2^(kWh0;U~sxgQ{4V>sr_lSh7X4#A(*9n>s1=;{w9 z(p`UDb9Tlp)K!d_JTM&umwN~TMevM=^OrT#K%E21EI2e3%UCVCj>g%(ApCc)d`rMk z11IIX2%Zbz29rz5_7j9|gwy7}0-lI0+U)i5zP%yF&h%%G0<52toe?q?XJDx2FU?U&>{LvpyPP+`XSc+k zrzksBKQJ8#C!K0EJfq<9$iD$jI@K|tOooFlb}G_ce?{}7{=M~yZ3ojkaMGzhhv!qcJo1xMI#n7bffyWgu~U(b=>}&mE$km> zSbZVRPIVxd`oKx28U;@wT%N}{gq>@OhnoQM^2pmQ+FxpEG{XFt^G z*PiGHVEQ9m9$6SE;=4ilr!P*rE3vYAd8E@nJ@L#O^jf$)vM^G_4+doj94dvKj`YCd z<*`na4n)S;>5c@`5pdG!X2UZR&R@vzxk@c4i{YS)osR30z(VGU+;!B&k?c$`t%j3M zw;rB#aQ-@mo$e-3ehLR&>~vg~ICAa+pZ!GqZR%p9+y|!Lz)7S09-imnWEn$FX_yZ| z`4b#;vD1<6$hkXp{WkNUB*fY2z5>&iaMI~IW0E-lE|2`=lunlm%0M{iVy7eB^;a=Z zXD+8McDlpCbSRv3y6Ny72j?$h*y*Z3sf5!`*Hd)8hM@gI{8!Y&@|^~TRd7kBT|}uCqf_jVqC45X18DOG`OFN zalZV9VyWKJ6O@{`ldd!U>E2NHV= z>8`(kc{}$3>SAxH2U8uKnfKuNKAgXPk$Df44RBDy-ZC1x9Dn`tc09d5#95oSf$0`F zsm+Jsc@WNDzVI=^tDw9L2VLwfhlwtpxs-tAz7wd6z2z@p+5uiIgJI{>0G_krnAIJv=Rr1Y9ML3!O5 zC*2j%O%(q&Uge2@45q(PoGgqK@wDC;VBoMmVDBM4us*Qu_*TlZ`y2?aK5)`~M!{1E z=dTYq*h~iHC^%hgY!+oa-vnp7cK>gwjEjv0;F=F7i;X6DPJzqwSY@$sJ}BqGK^glG zRXB3K*(eK79SC`LpdW#&1x_k>D?D4^@+d%7spKa>c??dKk?u&WEIPt=_!>{yTi|*F zPL%C}=kIWN6dlFs3q;agIp0fVnRfp>sf=y54P5uYNt-5etlCqvaC{CYRh)sjFb!@n*`#{=A#@;|E)X9TB|JYvMP2N$C>afoQE;N< z7%ieP6yU2(Wb<%0g^w9TN zxR{g9_10l4uveXv=E#D~I{c61d))4AGtT8uWkjE_MbvQP89k$|!)b`v{T8;Aw{ylP} zU)Eg_&F}-LRQCx_lpWrPJ`o92(-V8?c-#IR zYMkzWZFS-|=l|nub;2Cz;Ec`~dWs@f6^jMX{%WgJEQ>mkUlyZt3{V@KL7Hc)Ge{fM z2evh5+S`i5b0TxoPYjhtd2MULb@<|8Lk1;wW%k22ldFeI@7&1Fx z!0`7SW=HY*(@nr;Y0&KG@Sr(S%~U}LW=BV)Qj?;jo1zq^sG3QokL8PMp(nA7P zNk_M{N;<~3N;)?u(=5W{aK_RaeZ1>{_|fpn5kedYdf@S}|0Y&j4ZE=q!W{_W}^)AcvO&Bx_&KJWve+Ypz!&$nx-tg&eU8jnb1kP-=-SE>DDF z5Fr?m1#iInH=)iXPy;G+Y6qHJNV*}4GDVh{vR>&~7CO>FmLuIN0#1bsTg}#p+*AZ# znRS9X{&_66HT!swm%zc$)ds+I#>+Ki798?j2;hPWHi$L?cqa~Cu<6ka!6@8Zgcrg= zgo-wccQzj@Py?h1ruL7&7G72|`a9Uz8n?C^??FF-m4QU^iLVBi(9nodXw!^{t{o*E9PRVkIKj6M|e1YizOV3BzP7 zV!##!=;I{ z9I*h=uZl2*=pv|5*yQwcYO}dm(`YW7<*)-pzkzLX8P1gAzy~oBTp_S| zJHhT*=e28B_hgUhm#SOC&h&T_Z`VnCc+hBH+qt`K+~r`nvuLa@y# zu@$a;3x)S3YTMsHj3X1w;@!IjeskC)(FI!8m2WLMI0r6$%O=4PQ^mj{4n&T=G%wn= z%aBSJuqx-`;evT?yBA_gF<1T`r(ZupG!w=guKHP~A=xeRBjM8Qu{0wp4snQ#K)B+uWJ5oFG08*2+UkTVqkP&GVM6oZXq}t03}9@e<1OBu*1^!^Wu340Wb|D ze&t1gX^&$RC>WFpMrPe~;veBaCQzIUxb~uHA~}OV7A)D?b1-c5&kX3FP5tkS#7u(f zpWTtPWrIPE9GuZN2=~L8)f;^e!Xbjt2xczih^yd0CY+~arb`Dh;Vn2dpB*UX(aS!rvolFUc$9-WG0%1obe>Q@`TKq!8|Zwa`+kW z7e7q(6}T_q$V0po{Ot_eO6IH;h&U4t28yRfMhv>1Wo8zZ8fC+bBSuwA=tiymnHu$-7K7`4QWi4kCo(=Q_IGB z{qCa1Q5rjf>j%4{xv^NAMh@0K)1zY|UfQUfqt)y((+%d~ErbJBotcmJZ5@y{Mdz+0 zoa^AdNvJco0`4_lNa^7% ze$B{aR!K9cbrT$jya}T^%+v%^`^RsB_jaL9zYFj?@un_jZxu;2Ul^@0$~FMZLiYF! zMD-N0nVk2FjdwGE3Xw3M>lnTBS&62z9uEa_ND|>Nsv8F`S5_ex61W*)=1n3qcwfqP z!=OgE7EUZTv(es%qupmB6Oagc=un4VqC$rrIlPjYZ;IA}rt9fV@G?KC8@RYM@Yv9nlTm<~ocv)F};Xq|&afS}erMAt%mbDPL*|uyF3^7%6 z;kZvsUHh>B(Qn2uI~rZYI4q~U?sl|x4-y07Y)QRP;giGs zB!a6d?DuF#s=5!DV?^Aao1A0&*>A}ls426uVYhq zlPE}KDo9KpJ6!t~3X87q z5VdXIB5#c+klvA_M(fZ$r)Uy!8M>cItF zfS6LuZvectyI(&YuHF6Lr1*nGaP6MbiC^77XBW6YhYb=_Wes)2>B!3^j@W_D6(ssM z!Lm#@oT=0UpJVxb(+w=>1L7RRb<#u2$lYqoESu;}8PuoqFw<{Xp{ z7pNGsA~!_80iz_)MX>Y^K5U7kVgg-19$3|Q zDaHIfu6eO)?tjeaAw+Xi?^n0~jgwzrmQ60hnbK(s;ZaGwLt?76LLG5B7Db;F@%dhf zd}8|w2zA6xF)sc1aDzC|_%n$^lupc7I$)0@0t(uNKrz&$C(S1Y)35jB16AB!N2bWl zAQ%;M2>9rSiV4(V-b&M#XCes9SYR9)iXh8j9@&UT)-Lq1_IXgmJ4V4ncNiRR%)NuO z(Qu>%>7L zxUqa`vbwgeswp{S)!5Mo&0k!emQADb*J7%_I(DWirh zEnm{mI3JP2>Kp2-hEQ3LVx;2gWZ)9FkwjhNQX5rRB{v`86EbDwj6Fz$|izAf5=8Evl+6UtZT- z)_m%+swU7vpo!_`W(4pJB~AMpUy21(a6k}r4BCxVRrSiO$>8xTHl(q_NDjU0O+2f! z$Aw+Db24nZ4au+@8POF-w=B4bJvZFdO`D786?5@G2*&IqQ$tR;H+}A_jvdCYTS9I( zp0aqF%2NdE8)bGk!*r7unU#`!VNXdB4@&;rNOlbmHadAO40k0QY-k!vn$W@FevC_M z%KcM`J-Z)?-R31GIwD^7`-j}{fz;}LlA&dle9CD!BZ4`;sL4+8Ke=~)C)`UU-CwUz zo!uEW6_E6+?jNgtb$2HAo%~a$`21h(2miU?*Sxr2dv#>8f=moBdHi~{)ueGr2yqQ~)+G(9EKDcDaSXPVUgt*P}wvL0-jRvRMxS&?=_r1WyVEP6-&gnOaZhL`pjuz@j{T5)x{ajQXI|QSAMiSu z`}07bxq0vW``c%(Jj3q;KirQ#@L{0Oyt5ztn*)939j{{A_nB+Y*rU(<(ee5WE7yH* zbu!`}IWC-qE6t4@8?n*sZvS!NaKv3Wu4_2P3ovpbhM#b(BAjtUI2tKH>-TmqWs=>p z3goJbM%=%iVRvJ=h{mit7--zdWdG(v$?>#E?57eDEw4J>te?h9ZDSvCA zuD_${Qki-&(9~=Hji%P*?++xuv(tAB56Zu;(eD~}eOFT}|FeOnzT2ygR8#8}{1}>A z`14a&=WkL??X`wpS7zi)Rq@~L{NSj-+TEjyFFw<6lE2zoM!yODD_HYo6T)NWbCCaoy1K?5~T}ZMckFiJ!8;G-Bot}6eohUl7ExC&c!9) zjkmR!KEigyWdpmN$MKGrecH`{E{SL`5#M#&+fOe%e;nH5u6Ldkr`>?pYY#bp{L%}d zOyvIkTi)z_CxxGK;X3VVZkju|;k`Fab(m6+d5;_3hnD--)fIc^Pj#Pt-0B@{o z$Y=4r_Ne{sAyfPg^5gwz@HYb;ik2U^w(T$U%GQA2aso9>cxf!Afvl&N;qRl>IU~jq#C%t?eE>*o*2Bl#ZLQe zns53Z&F9asdSjHwf|*tOaeHv@aoaV_ujbG9-e{@2sPk9&{7>(lf1i!4c?~pL>vuJp zvY!)}!|vM;{zv^rZr{YYtk;NpTKjw2QKb9#c?qfhwr%k1HT%As#axzZg>4vS+C4k* zuT(ABBjEQgws-eluc>ypF3=8l@16fU+rclT8~0Oxe?RJVW1t;=wjca&`0d~>*-J~{ z)iY~;ueY*2Wq9=OWUD*6k>zdd+;DeyJX#1hwB~M>&$i6%Z^VsPw{6RHd$x^#iO4N; z#N82S%ggrU_b))@|4X1P@7a6Xr1JDcpe@hYJAbMz+ugF_-d>(tMchGqj8`W~rLmzk zZzKFsZ*rT4V6{Y2(;ijX?pixJ4!>Uu-d#P)xiky6Rhh|f1f!fi6c7#<;7jcWQnlA5VyEyR58w5gx}bEnC&Ftg7BBYp5@)T2g{;!TBY#rq7?=*s!FkvbkygQ4=RxD;sN@tIAFpamcDdc|hB+ z9I00?YiMFFs_T)d%7%uMYmvv|+QpLTvgV~_D;JfYio#Vj;SsO3Je6xk)if+`w4jgj zkX?>)R@XI@GlbZswWzS#rOTE#R+TMlZnVnkt5!8vThK6KG$k6#>ldNQRI{c~b}}9p z*Dp@Wscj9GH&r&*F0GQfEh}p(oji3CnqU#@lG!p!%M96THWaRQ6`HNOx~ZyJ9%G}P z8>ODnO31o}Z3&j6#8peH8W&g9SDq?Ndssar=dy_nRn?|wO;we~bE;GhUMrxa^^2@Z zaDascl@@GlZdh5_Z;0{st!t?gh%Vc z#ty4M1y$B0k=xp)+J^dM;pj01V@7>1Ic#a=vgJoqHZ;QW;;^No5N@tnzO({Z4SMym z6{ChVEgQCI#As639K-PHgDyQ`-b{qC^)eRv_<93<-u_EvSF1C_05gt zmCZ+>zOAxlhp=g8%$id?Vl=OnCe#LcwO1QUEBp>!iQJhAT`Cod3#W`}O220vdP2C+ zaQPMRD#A+z>31tDYf$+O6;0AP$C6fA*U*GEEo)j-yQsFlmi=+ov2!Mr=xYh9Y;pP0 zrR8$1!WZap?DW;u%~Nry@8i|gaJ~|$1TVVrqS{r3>`Qo8QdWT$MDFlHqpr4zoq$(O zE%?k;T{dSbdN=Z;!%EYNT3p;KE2V0@Lh?12wX9eMgxTe&Ch&V5yn|#BTZx`izkHde zw~XTmnhD`qM^7jzVg2iPB2|Wqv$kmwvbSso`gJ1)7;jXl(a{J)!w5+8Dux=l7#B4x zm#j>kHu0FU*;3i&l9OSjQR504HdYAgX0Ucduo;RB(2`sswz|-x=MMSKXfdwU*1%O zT9;8n`b&M)N_3hP&FGM*sPa`ZsML)fRc^+bin^0!=ssoS2(3QRsUua}L8@MQ;!2bO ztT@XM-@LMR5eJWB8y3}8*H*Es&(LOB)YMQ`gMm;QnSEL^(q{V5i$iLS72=PsPZ zCsk}SRPQ2|sfnVf9FA#TC-ZwllZn6u-rR6G&Uv24r}w8`Jn&mV9vLj z8F1g?z-{E}1dLbn`w{Qpd-vkRz;oi~#?FiWAaZ{Ag3yKTMb4%6gv4~`PicvP#p&{0 zipS6Q^Lybx+IclGke{@82fsm?kjOkIbgp|IG|ou--Q$lvny{b|^pQA~^PRb69|UiB z%%ow*Vt3r=v2iCY(j}B-ceAtI9J`0z)9!^`eEK^5k#gH3NC;WGz7585Pk`WoRYov~ z*UEUY95}GSpe0)lrf4DV6(>8k8xmeR2M!nSo!j!`Q%S`011fXi4RqkZ_UrBVBY{|c z-w1zLSC8kx5Vci``6N1DmaZi#i_8c^5>XJ#LSJ<9r8NMX3Fa zmz0P*YVvEUv>Z#my6THYV$C}Vb6q&7md*?VyD4%LK?lS^#4h-bNa-UKk5nvCoTZ*z!sil-~m$`k1{2SdC~QOxon{D_91SNy9Y`v>{c`GpSf$p6FMd%#Cg?eG6H zTe6$Nl7xf}Bq4zfQiKpfN01;zK$?Jxh(sWvNr@1osDQ#n#IAU4DA*e|E*7j;u~!tY z6%`T10tl9CzxdZGoEEao; zL&Z{&Yr)X}3~{~qocO8uoyZke=wDBS8j=aO6;BrDi_68U#M{M(#23VO#V^F4#3T%O zme){hDRvbHh@-?QB3Bh*y5-{4;u`T$k;{Y7?-b0bAs2{TMvvi@;u`UJ@hx$?_`TQ! zmqMm17LO3Qq6O{a#F^q*;w9qs;#%=Zag(@B{7y{36JE?WDmE9phy%nwi#LlOiMzxU zT(X(ZNO7V#S6nDA5ib|H?g7)?Al@e4BR(#^CVne&odTxI5DUciVsCMTc(S-aJex!t zoGV^PLT&v@#owgxZ6a3?V0jNI{Ft~w_E#0&B)%>CHibVEzZZWNlW>E=a=DfOnJYFH zi^TR~Z?T^^QXDN#6)VI=;u7&v@pAEI@pf^&_^9|KiQ|4n;n&5tWdB&ZK6Pf&P@IGaSe(-eQ6>=%ib z$$k?FzdOXc#lMm$|0(fh@ip;H66xL*KbC#F__gdmh`)$+@Y&0J)5L~iBav$gFyCfk zk?ifo9h0CBK5oP^(Kg-;Ss zCQ;5Qia$&Cr6Sj5V7jYG_+6*)TE*WlJ}mo-B>Y}ec&p++6~C1ITZMlR{kUmlx?saY z{IO!GI9{AYBHyXvY}x0DOJrY8V!K-QRpPDU8u4Bd+d~RJCO%K1oL5O~TV&rRelGjh z3Ugf!wug;-bfyc5$zl$P_@CD%**l6oWj|6pN*t~Dlf-h_CyO&>KUF+a_Or!v z#g&R*E#4;HDXt}P9QTV{RfP55Aig5|8{*sI=ZfDc{$2b@+)E-~KR(0A6cYKSirKO^ z7MqG472j3tB_1gbB$3}x@p#!!6er0(U7RT{R{YuGMdAwaN)q{ABi=0g?c#m1KP+;& z6#8#eJQqvh@x3p8Bz{W5?+fu8*}oTk8BTnd#Mo*;BA;CG5V57ml~Cx{S>bNtktE6) zr1&wij}s@#UZHTMxR6A;KPjHep0NC@#8tB2s_+`|0TSsR6`v4aSNxmehvLWLXC%^b zwG;9?*?$xR_(Dv3k{A*5NYpDPwi1iP4kXfb5s#3)uXwcV$B8G1Qx#t!&J)iN&mxiU zQt?9BFBPwq{YLRtalPUn6`v7b5ML#c?|4YyW#1!mjT8DO;JFmG16Md9>xoe@ zhlF3g*h2Q!VrSV8CoztO$Ua;gEpkB<=3h?2Z@R)W#WP5hvsgS^yh8CS#p`6hNxVyT zu4%&jAC-NB_^in1Zy3K>{7Cjs#9gv~E&eLIAHTh@ULi4yL_RrUQ?Z3uNW!0MnUIIc z-a{N9`%rO&Sg!cV;!N>W@iY?oaeWhVne69@T;YWFYe=;3U9ztg9~K`MpCaM+vcg>M z#Iz5Ie71^Q-Gt$96#u=*#hd6K5EDuG)e-B<-cXE@xJDgH;yZmCv7O?%h6&^QDLha- zTK3TjpCp#cUZHTMI8XK^3NI7?EM6sYArsbrjrfrGnD~;&WlQMyq4=@*wfJ{2h#%bO zmnde5Ibut(Q0yj_h+Kw*>4%BOk!X)`3QrJEmi<(Pxef`_EtGw^!WW2_lW6a2Nc8ue zvfnG-FZ<&PZxCN0k&f$=Fx@uUKNEM#{&$6c5`*|{lIfC3q{}8zzdW%(_Vy(Fx{8O3 zgGsi7c!F3emXSy|NjydN+2SJEmx{~9s}z5&c#FtYM_ArHB=TJ+J}UbY;!Co>F1{&# zs(7wA!hF6FzZZWYk*|eiH^@X1es#nw*&B&X#A3yF6nluh#C|058z>$l`|)C#>|A+- ze$&MTia$%_VkE53h2jbl{#S_C$<8H8OgqVbKZ*W*M)nuPP2yYPW)gm%DEztjEs1h| zQal$SVg3=Z9*J}@5`HZd?xOha;t{eBBjGnv;Yo_0DspiV<~LvA1>!j*(p@NCD&C;@ zTSTrW!uqWf*ON&1sQ8TRFNlAW{XOwRkxPj%pKrupME+4hdyquFTwH`qm%YB&SoUV( zq2ghR?;&!@5au^fJeov)$B1KO=OQBXnJ!h9yleu~1g#YH62EftrGS1JBl@dnv%5xKYs^Ia!CF8kBs^Wr;- ze_z}x`==roBw;?^i2sm1kmuAZEM}4L%MqK3EyO|+$5AXECVLNYfb2uX5n`F*CyA$s zv&H!&@?9XFE&I9RpJiVut`_f6{5tVb@d@!668XL$Zj${iajWc~i95t!6mR7_?U5+f z5z|TJTVKqRJth{)-d^l1_EY>o@fh)VaSVxk$B8G)K0}-@`yvwK^CH<-h}VeMi8qt* zyIbMEh>wvd=PAX%A^Y3n`?7zk@E78DB+~t?_~gb2W4zQAGf0$|t8inn6^V4kVn?yB z;s=Ps#pA@$B+{KEPL_R|I9K)s;#uM)ivP2?O1we5l|;U4#QS7lFFqyv3*sx{2a4Y+ zekpz>eoG?XA4Ize!f2nMm`WnPzSvM~srW*%lX#d|LLyynaggjsi=$;9Cr%JgRs4K$ zv3Rz49*KM}60el~8u3=y?;_E!kIDX|_@el#_y!5T_Z9v~+(Dw8uf@NM2{G8wK1pI- z5`Oi>9NF{5LuGF(b`bk0zP~tF_F>`)vX_ceWUmk_#Xl+j9PtwI&*If2>bFX~RrWRF z1F}CVJ|VuY_&3E5#gE0$NaVXi{7&{C#Xx}*pCm@aJQD2}6I+QzVh0lWb`g(|y{~w* z?8k{Gh*K3`ARJ>O98^v42^@@K~d{Xvj#8+kCBz_?KHt{p@ zN5%gt`kFfRNf7IjsAoN~k?aLxbFqu!yNi9r0pbucXj#L>(XyW;o-F$*;%srL;+Kn; zikFKk$siP=#M@-QQ+!bN$4Hz{ugbnj+$?SpKOy0_OX07@U&$bT2R+1LNX#J7K3QU8 zv8mXSM7lz;lkA6yy-9rE97y6n&7tB5#ZMGZ7Ar{jpQi9aaS4g^SBQ6skCE_yS$tRg zP7F75;$tGkgy=s;JXgF@d`5gjw3|Erb;WMt0CA4^CvmO#r1*?z;lOgZK)C z=ZdF`i^a3WtHo8~&EoCiqv8|d3*sx{C*tSgZt+|3XK}BX<#UcNM~sQh#6q!H>>_p- z`-uI;G2%GU%qPO}PgnR6^|275XXrVL^Hn$^*lx4x#H>K#o}e6nFj^`)e7Gt z-XT6IJ|n&+{!QE>ZWF%}zY!z25O92_iw(qFu|RAtwh`Njy~Tdw@#2Z1nRkW!XDYl{ zJX^d%Tq&*<67U(o<4F>;#XPY{Y%lf^`-`K*G2#qymbgS* zCSECCBi<#h6*q{_if@aX#hv0FF_NJE5Sxpw#Qx$S@g%WKH1ol5{0kJmP`p&UQM^@L zFPeE`NN47Wfv?N{vAA9QLHtFm6LRXCCN>cd5j%;8iG#&q;&^eQI9EJfJYT$6yk5Ln zd_a6yd`a9Wek6V(a%^x*5Oc(QvAft)93hSrCyUd>1>#xarQ+q{o#MUXlj1YtTjG1- z4so|=bKV;E@nE50eX*f2%;&gGQxL7<}H1qP1?{x~V74H|H6<-uLi(AA!;&);K z=er@lBr#je6N^MMe-D0r6z(sM632)$#987JahYi5@gbjU6gKns5MHaWnYV}VvkIH} zdI)b;c&E5WH1qQipU(MgU~{pR*k2qZo+Oruv&DJha`6Ijm3V`=PJB>&UVK^nK-?;R zBYrQ2HQx-6Jed0Cij74xzYfRIQQ`jLAaRU1PMjsq5toT(ULEqenqgdPSBbZXW?mia ze^K}W(af)d-OR58Uy^;J__?@K{8lvc>EO>bC0JfSOcv{kW*!~l%{)4=Q1)Wc%$tLK zkisLxk>W{WnP}$G!GDIr7mJsPE5+5~?c!bHed2o2%$GxcPb>VAxKVst+$@@TbMW7; z@Ymws#VmY>V|(O?1!8ltjo41?DjqKO5&Mfri^qs&-W>8b^X9;bvYYvH2+vY@j%eo1 z!G58_my2c|9qj8Aeo%Z$d`^5rd|TWiZWF%}zYznRCx(2(Vhgdg*hTCv_7?|<$B4&^ zW#S~!%!5Pz=O}!cc%^ugc$;{SxK1?l;gJ5X3co16D!wazApR=a_%6@mGV|WRItpis z4aCM`Q?b3+Su7EIi^Ij^L^JOV`I~uf;OVk260Z|)63u)z_}!!M1LDKtlj1Yt%i?R| z+u~;NV{yC4XHR(C31S^FP0SL_JU95o6mBLKie{c0;=3r^T^uEj5zV|d_?dZaV1?|J z;%VYSajCdmyjZ+UH1pk%kD2cVn)z&?na>8kAU`v&4dK5j{EoOq+$Ng&ZSdQp@Q>oJ zVgi2iV0$HrX=0{WB(@iOh-O|J(hXL4m}us)!9G^usbYnAu6UvNXYnfWI`JlPjd+jv zg!r`hrueS-rTCS|2by?%0WniF^VDEB^U=U|viBDIiN}j4iqplJ;$rb^@d|OJc&B); z_@wxZ_?GydXy%onKD!mRId2N#pjcmQC>|=d5lh70;xXd!;uLYZc&=#Xg`u3A6uwO~ z^S)p=^S;3MW&cS0Ui?{1;XEezrHYNkrea62t9X=X=5ZmNnYRU&$v#`0CoUH+5Lbye zi0i}$#TUg_#Vz7C@jLNHkKZ0r#EXW9IX~ZszlV zX5J2Xo6?*4ItZKjI^cVWcYdf!IOpA`TD-i)G>@ah`aFc!79{ zc!PM0_@MZR__Fw#xK;dA{9gQ7OwqiKRI#zxRO~34c`fLdqZBstSr9H)c(OQ`#CPG- z#U-{viG$ zQu2Yv2|-rFR53%`_y4KpvbPe8#P(u|*jwx;n&;fvo(hi^PZG<-3b9h0E1oWz=i!mh zzW-aTQ2c5V{eGi(tL$sUdq|w8>qPT^8T`$2qsZ6H|3`cV#~a?VH12vU+>eA`g~F92 z&-=nz^QKjf9S1_!#c-0l2f3t5tI!DN6pouU%PORyaK9Q36n8jCv{&Mx5K>iDuKTDU zSthoueBA7bj&4h#vp;s+I7nG}V=2PoaUKgLmx<-5BXf7s{MIs+%XTOh2Wb_KpD}G3 z7LV|znt-)J;M8;2pu(}0(6SmgyAs*{(=Xg6SQw&4hk}XP^Ud=@_nB8?yweYVr{>ZPQLZ~kJaHSb@6E3a`Q3x#Wq$aHFrMG1o;29C zHV<>2?cqLOZdqHg@69jcekU*Hho7k8`F*W4Xg2eDaI$56iT}jh7xUxxtLXaOaEi0e z(Y}63aCYm!xSW~J*l_*W&U{ht#9O~ss2}rY{qPk&UcV^(&>zRq$;PU$w(Zrprn8QII&gU<0b z$FXEtsq60jZqdTF1JA11P+>3XeNvZ=Iq$$Squa&^XwB%c5uwr+ueCU8$Zk9Rub=yh zt^5;z2pm;$Bw`olzE%KxSoW{C=eH=_nDkCbi{g!oTGV~55#sU{w{3fBi-gy*nM)HV zm-n_0*}b>O$*Vr>sq%bvdp(2#3O%C71_?gsyBs0G|`#reU4I~6Ep^qK@30MCh_x*+N4b^XOI^t6YA=|7_ zn{X-^IRu%8+ScPf%1DEHXQ)^u1|k$b2^A+h6$nQvQ0q`}h7(MQ+<;~b6=yra)U?vM zR;XQaeUniJ8tQhGn|v+a4uQ!W8_F(4js>Ak;fGoFM>yd_T@u~n+X!2ztAc?D@7h9# zDHx9I#j%9CDTu<+C!y{NrbZrO)ecuMBXSJW_E0b@@&yYjQ7|XM|LsFP70kENS%I(} z8W2vz5k-DVLF`dU+-Ix*g>5h}kwJfKksX67DVq^JZ_%@Ib zV8+R(;fS6?)0H5tbfy)0z#R!`rE{#%g9?Qsc{s$-`b2Z0#!@0Dv8aa>jHH#0n_z_= zPFrkBPL0&3^CL=|73s`F+>pdp^2Kr@_cQkC+-K3dzF2-_54-i*+^Covt89#kzU14@Aq1isY}kpu3@03pQoRM?Mou^-`YjJ)vM=n6 zwbbb83{UZeKSq=LVj0ovSkY;2{zcKRc^*vn)&J4Nw~ta~DpcXdcaAP+ug~-)C8ITb zv2M{)mOtC4OG!!eMD%~?RM)?E^eUdfbKLlT(M+bF>&r+p=?6wr*o>#S{zIeBFnqc% z(R}-jjfjRAUgZm!SuC-UQJzZB{t7YTuv;gDhP zMYnN)dR%F8`;(KdocuU!tDKNN7Y1|n=O{EMGcF%IFGspzoX_vD8T0Ih_kmemZ~!Tx zm>s?m9#L~GX=n`a2%cG%i^aQ zv$~E+7yHtkehfq}-~lc1rPA3K3r9a?ANN?}JUo?kRJKNW4 zxyf&6^mQ<_%-8T9Q`M2tog7!^`06_++@$DTEN{6Ru82NG|8w2&+-MG4={#TRaFow0 zdUOXJ&iAE`H-=@9#bgc_I5qIcR@+g2ISXCrWZ{q9Xh-X@ju*LxHFmTMMos8q*Ralx z9?b^4#5Fu(M>n&Ym%4_h;DO>oE1dHY!_~Hu`AN-MnKo_Ugjp#Q4msgjZa8W+*d4mk z7rGXP=r26?R{F9TV4HKsN$471)?Fq%*GlG9odJ_ou9eKr;fbVh!`-0;KL5usWb>*M zy3Ci%&duh`s?fE*WR~ib|Bag{3quQ~*a-oea%^4(%;?4d+Y3uVfcF$RHcvkHTxfy) zgg_MU$sB_{uwyFVvvS|z5fu8Pyz<$0?k$K4wejZ;GC^M;a63mwIIsw{Yt#e%6SP~P zO5wA72~>H@dkSw0^E;x^t^5+a+4`CKn8N4#Vm#AryRnljajxy>B(nVT(c)Gf zb?6r6twjed$omB4oRPN*=F{^yukEzFJ8+$xZ-ptMn7GIe-V9^d4_o4LyWSn}3+|-l zc#NvV3+;N((XyA8dzj!#JB_p9f@z3O2=Ee@5ZC~h2C0dI!^yWJ9Q_6@kvKG*!MjiP zT~pLJ@#t_p*1;F^MR})@ILrH`SGI1@OjX*MHlJGl|?B{tJnc~r|K9ev^lDgzDLOv_wJ~*ax>BCveN!@c8A)mj-eL}c- zrcV%Uozydj5%Sp<_o-_IH_>MatK27t5%S?YIHx{n98QjlE#;B-&tU|7*zJd6*ECMl z3T9(J#z~M#gR^Lt%V5`~jTJncE@`asuq@i;a*FFxY6ZvAWfcZ((y>{z%Y~O;Q_$m9 za0y+Wqsyo)+U4>fc1?X3qWw6DE_Mr#X-pO)JAj`=D_;(dR{+kxA3D7y+N3&{Uio z=eFMobXh}}nOU^U$;%*uA|GtxJo3=&!Sx}Z@4aKzo+Q3 zg)R%SXqOB1>upSrCE%SPf6Sd?Z?S;u?}d& zq~%$RkWX3M2kl3Jx!7B5;|sDFA)jS&AG9AQ$HjhPe_oQs2-}X8a#a6Wr)q2x>v5IN z%Gg}i{92uWu`MkBdYx;r=@`mMH|wm5?ZtH_>2{qzF+N+6beGPQSXYjXweC5=Yf3hL z$T9s@4~LKa7|+3^_1Uze+H^VGbwPg>(xoMj?6GXx0|}DuzQS;lq7A)rd=*e zT$fj^U?p8Jna4_cE}M3_+=^Y(7Y|^(UrwKC96T>)GeSNuxjv7>=VAK1#|pom%?SBW zFV5r>!u5h;axq^0lHST@gnTm6-i!3--%?YP(g zcK#39v@6foU6-${Ag9;G9^#1jHJf(1{2jZd_8+39K0zRNC`cDn0?%Wo0_ zxsT8(WM?x*P9?6><7m$|bXvlGNwKpTgS&u3IB?T!wM%XV>yl~fvYLA`2YG!rXs)uC zxH<04vx1a~%RPh5*3iyk400^t_{nyI=F0MnH_d%aQ-|%CXJ;`6X>MjK<;Q~qSc?K% zCrNG#R=KIIGboqON+h+gb(-W3;Ssd7bq?hYVLunzI#F`ZXU=VG@8``33}4f_dwWPJGszP?IXl}~j6hq{=ML9rp%uKEKBHLg zE_N0pwM?JUN~sbPkj6GnI<0=dt! zAC9oI7$c`1aVK$k7;|}`VN}oY?79-@d1-tR~c$H2ASoYC&7GvbZ$##wt z+T&X~p^x#gZD%n?PA%h3XpaU6(w`*n1+5q=9|OnV^7+u#h!qlk2hJ2A#L%mYrrdjnqr_N3tWwB&6BH z>{Q%G`3kJ$c5t|j1NOd7O-zg7 zvKdpZrjMLl3kvNXDQ>&*Xw&R;yCmWABTO}#20cyXOL*W2^f`WIasB((^Wl)2RWmqF z&AlZlAqEjfjM>gG?Ck6Z$gZ-JOJpaP%1(03`;6*6c7ErpJ^XEJD8V8E);IRhRools zL=c1H5!{>PL=aQr5!{>aL=gP{z{!exi?E>#g4J~*xOWLQL=Y?D5!_pi4H3lk*qjvH zy9*m4h&7&RgM?2 z8XLVxwy?aodn-27o?wI1i)3@li@Wz@gBQWprZI5()K*zj~ke*(ZN?yolAJxwUKJl|p);eB<`ov$oPyFnY zzdBw7`+_Bs-(pkkv1eXBcgN6a+@e)(RBFguz7^UA@ylV3m< z$0r`Z4%4_VKK1Um`XY(X{uv);_?I1@(8%4gYgoF?8sBwv#mpHKF-s_)ORdeyZ$7tk z#}=a}PM@7$X;yy1{HXkLt@<>&vst3A^(pPKc;1v5Ge;w`_4FCj%Ug4Gq|sRVZ|dx_ z^3l`Aj-SM-N&gdh&zd*u59W&{EJtHe!F}p(79ezw;18Ct-&WBgdi|X?`t5>4T$`^H ztEv@_XTOz}l}{Lp3+a$$v&I2^cW7ygGw0Nu^y(VV@w3#{-!LfA2G%pzot%e1kT zldy-6an5#AC_#0=oH4BAiMev%PL%*+f1AI}J8CS(K~igZ@s))<4oLz1*&{9x|*KY|to}S>$H;FxUI`KaC9i{sG4AISWfP|HkiT zZam9oiPN%bev8`%f<`pKI1YY+KxUf97^r z56)fZ&RL`Nxbn#pCsocWEiS_1qU?L`{KTsD?Ao>6Uv}+_x?ruuYOB0r8e!?6o+J8| z4(>U)|KPqB7xTkWM_~!T{j64t^(&{cH;%yQImptr-mIMdpnH57TW_>!Q4Sq0!8@C)n0gnt zHEXJxrruAVbVSeXZ}HozcI`i^PwAlk!!e|K^>f$6)tKe*=Qyw71MD|zk9w}77zNc< z*R5Js*HeZ$HGcOpyWY{Fih3KZBhCc&+;0}+^*Z6`Keg%?UQS@uxV2|d5+pSV=i2h$%!r0qv9OD>`@nJBq&)_5R$nXb}(i7KSG}QqYQm$G)c|RxF zz852>1^F@HEVI0yB<^|HvD&b4PD6hDds`NlGt=81o4L@$hhfiQM;pHwE3{&gj{b4Sk^k;1jG9eKJu7>J%=6SNX)Hbd^KrL+c>RTJ!j{x?q6JS+LJei zm9C@s_VPzoq4rh}A5Z)LRCI0y54c{nHxCX5)2h`MYyKzKul{G3t#&V17<~u2uQxZl zzgfxpz^9D4!#db9*9T6@DtOz#oNhE?-E6Zm_I{Fb?ev4Lm%Z=l*Wr$zVmPorwj%d_4$r-6;F{vD z*X^yUbMMATE#i$V_W6S5{3L+7{a;w!I|aWic-QvMN7#Mw*Q}nAz!Lj}B+L})nOyGR zKXUDD{yJCn3Rrmvyc9Q7{bENG*V6XBe!F%y{?YTi{{3rbr+ac|eKM^ku<++WwmH|z zKFs5hiv6Mcgn8!fcU&w7eG~(Oh zW^s$SP5eyUA?_C0;yyGh#~atq##9PJ{IP1tXQX_HY)az)uU4|R6?=%i#bM%cV!6m) zx0yfxI3*W~OU3iWtHssg8u3B#d6Bb`n2$MLaF@dDC)(L*WQxdD<{2&&M~LG^&T?lw zrluKQCax0i5Y4mA@cWy>=9y)Lzfss|;3C|fzb}Km#9`uCu|ixZULam0nrDBJ{t<;= z5IJ9!`F<|`C^p0onzS3uS+JABeML^YX8aP-XvQMETH*V}o#HQIL!6>a*Fx+p9w{Cx zmW$Vk_lU2E?~6OcpGBj&iu@bk_g0oOTpTCP6weYb5w925icgBKi(AF7MIQz_^G_F> zh{YoRab^54ahy0)Tr92-ZxZhpkHN-FBZ=hFBUHoSBk5}+r_)Y`^5F)2Ju<(74da(v$#dvE`BL~C;lj! z`xewU!21c%tUUmxE8IZL75Usb{SFn2#g1Z$*jqeG@{8{7_Lmp2*afmovJV7iKr-;+V+2TBr zkN7gbKZzHKD?~oY%lK8IS!)1cv(^A;?khp+bI|Vz@oDj8(X2s$_{|D$5x0w9ie?Q0 z_j^cSW+{d}s z6A{s-96q7W^6+uutc~OP{T?l#1FHDA|0jAybtX@rFvAtz`LB`k;nJk$dq3NgFMhsw zUuZ`2YK(VW%J5r(^V-*saeOtyhHk0RkDq5u<1P1FgxweWk*`+RaLa9#VB;$b1rG)B zvC8=@W@CB7vAK1?uF)2IjZS*GaYGRH<~IrXEkXu#WnGvj^DD*XropcDW7PSM%YDAw zxKlj)w0CQW@91vjJ#o{p?=AN;e1H$d_++`XyX7vzzMD68Eo$E7b4M>Xj-T`1{5l`u zoD0kkx9su!F2%l^2D{b(=uipTT23Hxpu<}nKSz2FWCPuz9b z_vSYe`LSJDKioRU^Sc-O%#Y)NuYwq^HMrk$UyS4Si0JyA({}&bJI~7xa9+jL$F$ou zPb1b_zmq)2i(A)t{ocer4zI$=40-L7AM3^!=`(xI+a&l6g%QIBzo$9*vE5mwr@5>L z+c{$mX7h6MOGC)(SAqI{Dj&l2Ytx~qtw(w%zgBzae^z^ECeGQEchHNJq1g8Y?HxXQ z>i?c!#^c&Me9G5fjKN=}y^{e4|EcI-UtD|VFeYq{Oslka%z7Y!P$j>Dhl56iARNj= zsw(ZB_fQ3Y`w-rwz4ILgp{u=f3#wU7duIh}64&10PaXbMc&o0xvmQ>ie>JM(YVSml zr>nhlK4O2Xz0(LaaJ6@?!m-t?y~F!UkM_=qXjZTG&UiGJtG$!J%zvZ3!^L?V?VX*7 zceQtlkZoLh=M$Xl2h`q);6OauJ5x|=kM_<{XyxCly~9V;>oGy)zDd;?dq&$EsCn?-+rXD(#)ySWuPr&Y#h6UhSPq43H}AoqFh1kM_=; zYy*$>4xj$_YVSmFAwH<~&QqvqmG+Kl?<(yb-r{+*cc@(C(cWRjeuwr>AADhsYwx_m z9SB53x#nhbkr>?VWqrtq0WJ z8Np-v_h|3%k@Ev<@9>vEkM_=U9O+fsJ1aQYsn^QI+=29v1X3Y40>c zN{{x=vCP+_y>kH@!=t_PJ>w6ez4I3iHIMerVGMh;clea8S9>R!VUPCC2`tZ}z0;p( zkw<&y2zIPTdnd?7^JwoJ&lA|Az4He1^JwpIS>0bBS$+B?6Z zyAG_q^8u53w09u4WBrrbJ9l#2c(ix8!jo5fry~!@qrJliAHCW;Mquk8+B^K!&8xk$ zhP~|3-g$!Md9-(Kp}$9ar#@TBtG)9o9lY8*^_hcLdxwAgRny*ion?BpcYff>AP4zD_K?VYdKH~%ZzJN$3cqrJoB*s5vooR4^D z?_7!6H5!Kg*++ZlG59ac{|=+p)!s1+Us}1t(GLgK-l;&xT6sUfXJOtc=%598&!L<% z^3He3;+YfI z-uaQ`$F+CP#D$_td*?A+C9AY|K4z=LwRgChWewUp*D|v|ti8i2G5-ebomLz?HE8eL z%Ok8odxsKZHEHimXS>y)y)&A9dT{NX>zK{KwRigQk`mY6;mVygXzwJl^AE1Qvxy_3 z2JM~kEU6~#omc5pllBhv7(LoMi5$39+B@g4E>+q)Ejh?*(%$LDW~|Hmd?&S7@bCYhj-I< z|LWR1-RL*4R(q#bd#6@=XAfnYOVH8t@e(iLR720!xN)c zdj}Tbf;WRoXkB#I<*BakO^|_EEqwzDH5TrbCtXPWyedcZ`!) zd#9h#-g#+X?H%KHgAuiPpV~VGUhSRX`zyH@OYRPRoT>ZhmHUhTi-~{ve@A;~-)Cc;=aXyYb^4Xo%Ip09C$ID0tdSFckhDq} z%REtDE1lyAM|q#Vt(DH1I%8~QYseIKpEP!6Sv~{|XO5rL9Yg5UPUWqq9Xg>RzxBkj zIb&x|XkDD&dPuwc))S`BXbrK0$>Wh~>g2Id=$HuOgxS-_S5BTWy)`t9$XT#a8N(Z% zP|(D=rF6A)qax=BkIe$bt z=Uiqwc0yQJJf3LIPGvC?H$e>nzCURL8cO zSNrAjmtMvmggg~q&8-GjmX*5h-tQJI>@o1HiVYR^qTVO<+1TVASY{lxF%7h49K8{t z(hjc;**#%c$D@2>hwQe~|N6PF*vdcghrm%4N5W^}A&8witjNTM75mlp{1)9e)_JF- zMemJ^T4chbVpwzIkuQ%Awx_m8g#FZEF(=<9PQI^iAF_LIk(2w7-P4EVn%GpO+JM+8 z!x|V{K(_U;O&XSIY(ClUhOKf~nz1dC?Ize}4y$8qC9++;-FnY6=#uG$v}UBTSK!6#6tZ@-#7xro`HX3zT=q}4Qg9%N18nmy|n{WrW- z*X(&8PPTsys%jWzGL>nmxzivB4E=jFdp>2i zR%!Me&c=PAPL!v0ta)Sy`{G~J>>0f}x zc%rY-?dA|uqANMnJeoZP40|+to?%6&`E<}lQ7nyKO|xe%%kyaVOkl774$U4a;d?cE z_Aoz>W=~5t<7saBL!;Xm_GtDrVA!MC!}F?|X3q;Oz^mDFFAcZ)Qex;Ye{6FwdMi$l zYMMP~uqXeEG<(M20ID>5%(cX$*>gKv$fMa)hb{ciY4$YXU@5WFzcPcxivG-`9?hN( zY`G)s^l|2znPMe#XD^&muAs$gurajA7vdw=(e)fR9?c#q(;rN;=Lhz|pL|iHyc{bq zN+uzXW>0fg?QCDG<)-MN(S0?0E@LlyG^Yuoc8xFVE=2lbbFJjNaRp<*WSwgzv)3N03OC#xTHy143_~`rI&saO z5Zmg2nmz4Mik%Sn2FY^lWOQTZk+?;HG|XOD5(25XAI!0N@@4WEVQGQ=gg_MU$s;j# zdSFN6CwCvsp7n^@pJvZZs9mEn^v^z;J#WH)VSYLqeIL!93Ycor?8!uR7v_yZ2UXYX z8H`L%%Nvfaty!~Y4qB>4&7MYZN(gK~B^zWUo)u1h2;nGK>PTGTD(hHL8#PY+ldIGt z<({Q(*dLvQR!=-TTt9}yzE~i71pSwVGbzDCB7#0 zh7av>X@qVvE>T6rUIrK@zI85r2!wC7TiTmJ~uBJ~L9#i)mM#yJl+$UrOAE(b}Xas2ZFhV}x z#(nBq!H?v0l8!-sacoawrhTESE3awOaD*eu%Ra--|=xD{MMmkPR!%A#E^&tccp zcOlyE0s1WFF^$P$gnV|mK6`yu@ICtQUsh=NFhV}57-`ON2d&^<`bfiv5%Ost_er*b zF$7}L@L_~}M#g>6I7iawuQ)@Y;ll{{Q2OdL?7HoDGF`5t%gij=<#Mg-g7&+BF4FL! zT`o_!E@;1d=^_mu+U2s%bwT^RK^JNG&@PuS1eW9N_dR_c;@CPXixKi^<@&JwvJr^g zOrND$jF8XJxDVQ|2Yp7N5uxG32>DdTeb9d6=_3svM#$%ixDVRzZ2G*({=6iM5w;zZ zhL3Zq#!^|2t8$#PGM3LX=USbBu^92Y?eC)^WVP@;IX-Bo`GT3!Ne;rPjmOT3&%cfl}r?@Vi ztl(I>NW+JAxvX$qUbTWt=t6brr023}m&=3LHU0Gf#``Vw>CeIQayBF6v)T1|96m47 z$6{Z+p3MmPa8Wap55C$5zoJhn59+OKM#!hY_4zPj1?wRYJD2UYIhzsk>F4@9UKjKG z=pzjuM#$%6?3(sNx1T^4Bcb$pHtlk`z;!{dFQ5z8NP>nB?dbKctlKx)o~C--O)vw$ z9WcSy911^V)2=+Xx-MT?!Pn{XAzR_sY})0L0J&|`3Lm1SzJon?HcNtr4`bwXXxs^x z--Za}encl|_%KFJLtQ5#0_&Dv7dl~Bj4Ik&Snp=;992!2J ztL*h|j(hX0;Kj`Gc(y(?d>DfqT@4>6Xs#@8dec13H2g1|8a|9cn!!9ppy8vS5jTN` zk8_gb23cij_&6V7xgYat+rrjqlIv>tIOkCA5RT14TPI3x2j&b7AJ6Aa8HTTE-Mu}m z;BW+T-(V*}!-p}b%`#T5ef+3-ZM+;YW~}VR>CYrwM1mSVj6hq{=V8}pA$~)mPe;}p z8a|AW&lc=DWuwzxrIXE0gN6@dgo%({)071Q5tYALC=&&SH$5 zy2hQ*9xdqPYWOflPNi`tw8vmNZDU_U!-p|)S`v3cd(5KKCXP60_%H_Tv4;%}4Ij@4 ze*iJ2J&@!UCYj52F0->3p?u%-_`FD;(|EE$!-o;@;XNQ17clLCFMz?X=+u=?(C}f5 zGHU8|%0M7@Cr27Id>8{Kj>Z9Ar!I8LXSJc>!x-BxuunoFyLXj_Pb+*^;>&&)4o!zc z-=_)pxGd99Y=`i!+V1OW`0$?EKGNv*RM+t7S6#!WDN`M_uZ9nA(=9vAZW^hV?2lwe zj!8(fhuNuUXJ3JpoP0Qp_zG9w@<+NRAC}xDxj)W=fMQT^@DPiZgu3wMPN*I{yWva< zD@o8vk{Gp4s_1&P8b1FU8b16##b=!nAWNKm!UK?$FGdYiePn}thjfN6G5zvM{w^c zCxUn;9>Kl0oe1LHcm(%$I1$9Icm(%QG7BfzPEO&p|FKsqB)6?$L|1G+tHMW?U<*3R zHQXJ54PL}ZZ1f^WVUrhkr(%N_F&`VfNVciGxVr=!ya+Ziz1*gj7u))J$BSUI(#vgL zd9i)(cf1I;F}>WjmKPiQ1;>kEgVW1xczL}G^9PO>u|r-Y+g@JW{Tdr;Pk<&bl3gM% z#{98YA(BHYhv71(Gdd3M80I9I2l zRoFGJ9K1XE1!Qr2;sNY1jr*zxH^0>vNqqLt_%Or2^^C=4*YND9HNNZUikUMe&Kx@} zf5POc<+Jje&;1>GIC$u=_4FCj%UhS@!SvCSr;ndHyR3Zlw6WtSO`cxP@J`>s%|7U6VJXcM_Cyg3Da|&a@%osF$=6E%HVwuqJc_Jg2kx)OF*(#XPB-p?| zKR=jR91JED)uWitcpFMO{_m{(pq)@J==Wdgi1`$DJ6NJejKa-RNaXh)WdwVkupsP{ zkpQ)z*1?R%!3Md(%p#Q0#+0$fxW8fCA6{tu-=VDX?O3|Cgj+{Q{2Zvzm8Q^bt`g9J+-@{(n;{5P9~S|y zEJ3@rrPLPL-&4ZHo%d&MS8SD*PAJ3KGOcv(jEeH<)^X+L$$sat{{3WBD+n}fQ0bta zBWeYKIG#%JICkaiSr|m)XUv{nX-%MhiSypBxU_PAL#|_ccvns7f3@(a62}S*6p<=T=T|hvm^2;cYRL|Czj(t$&I9aTEQj9;Xwv`Xj9oLpIMLEp=0A{bel z(y^80IA7w!y(b#jd?;5Ru~JOIsI~sz6AHrD)^YQ20uRKkZRz+^E2omv#?GBnhMSiE zI?gCYcF258Xg-GkLlLt7khzj^(db)_=4%P=LSV znOD^>feiZNtI<2LehdGWd0u|=R8^J1Z}E?~s+XTrGCVK8S?RpW;O9IH&&zM&?=#QK zZ&nJgGWe}bs|kXvF55gE{~{b#6>ZjWAGl9=KOac(Td0F*1M$={Ey19Mm-F+4vBwm4I7Y%Y)YbOTgl#5 z>>>6Rhl$6D<>C}^uDDR-&*v=feDP{=wYWxnP<&pj)dh0etyUMvX@^=}Ag3Lc<8sOK zsa6-rX@>*p0&&Ja+lec2lcU5b;(T$rc$LWKDd_*O_<_h-P_!3_M~YL#3&geJo8nJm zBV1dVzNc6wo-N)kz9N1t)<+tq>ne^B&lGPIpB29lBbfHdbj9Ma;(YO1agF$p_?-Br zxJ~?8Ay$$}mUXsxu6PlNe6AI5ll@L{ zt?Z8~{Dk<7?5`>OHxVD}rd-|)vV5Eth8PxxS)%y|8Sw=QHy4Y<_F^}&L^SsuNXLKf zng3$(Z1H08GI6E2TD)DnOT159FK!T@6<-lw7dMMr#O>mj;&Nf>E-NM- zq79GHd4`V@%ZJZy_xfrT&YCx^a_l&;a;C#c?jC-6t+WccsDf2EZq_VE{D;QE1N~=E zs}IC>=L?rN^J<27{-WVduj1#G_vQNW^NjoKN51IC-yhr;`;o6!*zon;D#6CrIyepm z@v(|uDx8hw4aeq5Zk>d{M|9H5jT?fnH@`p!%UXsE=*qeeF!W)-TYjs{L>a8?WD+*vD9|aPxa(pZr)RU!-SvSmAc)Ul^mXr(%OlE9HZoR@ZA$a?+O}f9Kq;eard| zMc%B}rk&P+OHEz2p)P&qk4Ie!b~Wo-uq$E8_+7WmKXuoQQ#$Pm&Y!(&@hH}zeedgz zKpm#APR)C7*lCU0fW4Nz5AFT8w^R1mDO>uy(mS*#9D4e-zI}&$aa1yEb?(o;cfPaM zZr^jSb+y&x(w)93m!btWnbQ3zHDQ#mxYMq_^E>Uj8KF<-Uwj1fUA)sbe=$nhu+u-^ zzbDnd^=kAAlMLhJGWopvu*yD$C!x!pIQ-IxCJ?f&*}+r8~y*zTL+?d~7Nw(qp- z5cKQ>^z1EY^-ty>vdfy%Y?n2E!mdRag^T9lBz6!f311n8zyZ%r}45!KdUH# z-{XUE@pG;d0s9o}r0@#^zhv$E@&y8e5aqKIuEOV%{~UZ)KspLn0hq##VDkBbeB|5z z2)(*AIFT{F(4CA41P@_MEA9_zFo!XLkWmy52lwFW1G%Vkktz@fVlD;aCd0-51Y#f; z)rtG>;d%v$sH3qTyqN}m|MC}QoQ!>6I6xIgKX1(-5ydNHLV(}@LUmD~?SB*RkccW{ zvLEmkoN4yMU!qQwh~h_5Vjy_4zXkG4x(}s7BI+j?lS<$Li748wWFBf4?4{5je|v<3 zHzbZlIMN4i!J9(o!R(7!5k6-QiKq~)kOr{)b5JcvL@}v<4Ku$xo3s4u1`+~i(#H;; zMl1LIP2mfPD7H{)9T>7gZNm6F%8Cp_rjUr@KFUZdJsBcUDlrgQgK9z|%Bes&(%u9! zoM1`>57;6$+X<$omCm(7?UIAY&lk%;LtTmJI&q3mao1tp?xhb_{9Wp_z* zkB{G2LtPaNM2Z+ZOu=wu5sn2CQEuUn@qoH3m>LCLQcKd9e1O= zNum3~Q8Zs#X@wQKKV1pZN@rT32i%d6RyxNDJ*ZGPvXJ#!pEv;U#Zn>zSkyxbM$$^h zO|U`_r_D4ar$%`55_&{wvm!wr;)W!)k}sAMxrwn)=iZO%L9Q#ZjafaL`;iG2L^`l> zU#OD+P$KGiWC@9=#wOS*t#meYonBEvMF`>mUey6~Mi57^QRQ}v9M7yar8P5YOCs;H zJ>E#`WP)*tD5uW7Bad-7y{ohXBk!}$?X+2+v?&Y;+`%<$j{UR%T_`>}w{?G;eH&%+vTrJNl(3qJoU7e>1A+NJO!9qDz_Y zIG-wIMc-p%KqBf&a|nUxZpKgaWjNt*l$p?H z85`Zr7J)>R6JHcv&hT_!{m)E%`{+iN2Z<;rzH{_Mb`>O|DAnYPb&KXPzu7)rN=l-< z?u1Tt{d-48GW{GkzF#zj=^+ti;YUedY+&?8HX|gWocxDI>$7}FM6q$u%+X634~eKd zO?e}uJg+Db#Z$>2d(IcVfdxP!isuM4cYM+1G(aLM9VHlvsEN$-PG9N>G>t#DB^YhP zJRuR)$aw4sqWyU)IGyw!ygi*{f~*{za4zEg5jbSnyJ$g%9#@*&{@iYyn2y7?$_eRH zU@%vIjzV)X9=>*x?VDRRg?HB8mZKRiBLui6|$W5bceEDG_Bp zd}EM^;?6EOtJ;o4R57|H%7@}95ydM$vzo#1Vqdz`kAdj*JfJ1MR60}AW+rP5i70+d z_#hF*N4_Z$Hb;E%1gqj%8bLMID<>_$7f zf@MM?ie>m?YwYMqo?MWKat!P2=wWO?NJKe?N9^c{Oah50$MBRLy^kJ{h~jZN5>aO& zH`dCuDI}s8W~EFR5>X6~bHlDg)cG((XCfxF(wEHu+k7b73=&b-m@p)wcvWY>WCe*R zb`DP@g&m2g*I~%!RfiH$?A+`#*;bH)t3t8At2qfS=nPadJJEj6YD|Z5qpwJ)Xl@AZLQ)`M6QQb@sH)5}%T8)my zThJ~-UBYMi5*8wPUKtz~=C?*$TKU*4JO35rgbXLbL~W?y@Urdja99(sw9{I^CwKvD z2?6K*YO}uV2NNON9mi_<&_R&q+V1!}`u}oHx zb2Bc+)`a!4bM182<1=i$xs9$>-ef z`Tfo^XU?26cQSY88IE-XZ+D*;8vG;OK3t7Hx*2Z&r??E%-}YgP?ZQvtd3;Jn4P<7t?jAb!F-l3?y0r5qbT{-k=?-^b+q;B44C8S z;(j{XI`!8uA4V8#yXk1#OJgvw_e2RM-YQT&2BFW5c1VQl&1 z-0rD@=OyOe2dCjfAVN{okFi~_vy$l@HolN^ZXE2r5z2V+oimbW?&bdU$SQo!h#ZNO zfk>IgZOEiV&Z&xiQZ>M<;F|n#E+P77AODLcV!WN9()R};iNPO?XJ-E=Qh~GLw44Qm zHK>>YB~w$zFr5twUUW@MVkk#9NomO3RZ1K(cMF%teD3V;p2vE73=h>iCXbRHJ!25t z*f*C#ACS{f`Ck2zuRHd6$|Bfpz03SDc|n_Y&+F)S@~aXTIn9ZZc&OG$;x_80_G#n8 z7L;Pu)bPL>CKf7F->?tIwQ%c{W%u-YAyd+Bz5TTg6EIQ!0d0I(??A01oM}+lhncGN zhO-PoJ!#1i)m^sXL?7d|(nL+l&o~ixzUFMK#yToo!UffNmFVQkGLKz*T2+3aZi2DS z1xH_eM;x2JI*oWKj$|GxqQ8RVcOd=Dzq18DP~iXR=|q2v&LntQfi;u-Z5=rXRcv$> zZ*&)hQKap{ISvs7;zElaM7U}<&dyXjlhvxK*~rm$@sWt-TL^f1pEw_Z!WOeOF~-|F zeeaNg0INilaM4-8O5$FtS6R9V*=@n2t(9%V@;sAuu<|o{4xz zc{hOUS+)w%&{Bms2M1CPAXOs9A*vGGBwIMV7=ll?wUc4H_D&wqa}zCX|0Hhz3odoP z0iQ6H)<+0j8_Dg@&+La!_Cp@_0ee4B`=SJ2%ROy>%!D`J?E~y1=cn&rgo4n%aVhk! zN5Hz+C|hv8iOJ)RXs-3#X0-l*0k&>hOA**Uw*Gf6b^ig_9X&VEQlCr+_7qx)veVQW z?yZFg`SjXOa&4hcZJB~fY>DBM!L^8FM{}>a-eh0UYDPeNrUj!3spw6%=MAKMtW@%^ z2>D)mH0`uEyMIM*IzM}pqdnZ4E`?rg!Bniq7My{5L2#{~4Ug+h?rmC}i`)axg0CPT z6}`z+TIx-_FvN{}^rjp4*2-Y)W1k1(-Ta&fYRfcKVhi_bW~oASIs(>)S-<~)l1;R> zAfPQ%9s=J&aH$iKN=t2-vM*|%gn(2#7L;tF#nHs=Aln}cO473si5`PnxIY&lxSF^g zTK6NMrm5@^9s^wJB&5<(E2gqXxHpjM#@8lV97o&&(j5uX<1F0V#7*$Dh* zCR?ohu@xlC|HrK8J%h~IMP1GMQs^F@s6Yze+JxsLe=?vTW< zCt6DpuytSab%{*2@PNed-}$n$it!PADY3;IW3I*j+*eXiSNMyi3eNw`*UDrZ?)kN% zQFB1BHn=$5EwJ?q5Zt)_=f6H?qarsRaI&UcMQiGIa(1fAgkmD+ATc$ z$3JQWGvYs&ApciO0Tx)s8H6h{hZtkt=|mL*i_b`Zj}3;0jSB`0WBfkga;jKmR_5dH zrC)^$Wl?V+s{EhoS<|xC6z(ofH7sA)uxL@kqWPmzLn|sr4LNf7kmYrUH?_?FhN_jGxuP*E8@;w$i%XEjEF8uxlGaBg6%GMjznNr zSY7Bc%fE1OBHA1JZtO$o!S#s85|!MlLZzo9-9J*qm3UDv$3%r`u6J1m`U0+ElQjcn><#E3T0JmFddOVc?fz zvvW~2iw%h+4vKd*rmT-6(RpRg5$&JxFheRasBw6K{x3 zyoJGDielK>SHeF(@wi`YyktIt<9u|LecRaJwIgr4n3?5n#nDw794R+JqaA{_1taL| zr)V>$=qo#!q7QhOpheK^EI_3tskpyaJgXuRO`>P2aBRn9t_JW8ifNoPkDkOB=rWLi+CaSG#SpuP*qv}^SEnjG2fej`Iv9NJvOT+4hme#sul+*HRTZWJF zYN=`i$HG;MEt5327Oq;kvY}=1vbB~ot$oA0QSny7#jTA;H+WD5tK*6qT3S{#d8i#C zRH(gS0^HF1SxEgas(*R@ns&R^Wra>TItc%D3 zJn9@CwWw|_*W9{l*-F!MGGRoMKwR2{`|D~OmN&F4X;@K@TwkH0xKq7E2_r(8Y{epW zo?8QMJ~eSE`)J!&b*=R)8<#g&_d>jE!o)2$UQ3d7=9=e_v)d+SKrivXSRkc9}auv(pAeBQi<;yr_G1?(~3^OFb+ClIh4bK z5o{t*ZirY9ViwgdUd3+2Kxfwlg`8Yi1t*J>(5pqofo5KylqZR)kh&d*I<-2N)Gc3L zXLA&>&?w_b4-~c*qU%wAOGCr5##Zh<4*Euz4o8f}6?PbK#~9AW#@0n>7i84t z)-CgDm+FAwdJpx5h1tGJgDsF362pqEYHDl?;3tytCCfZnvpOwB_~prgEhO#iHQ z;j$y#aTI-IHR~|a_6V}V)D@4y2B3PX^KceVX!5dAWDXT#}eoWO!D*=r}uYlt4rWxm`z92E~~RqwlF-*{{i8zrI_}q zbfavCEMBp4ZF2(-hSm?#=Hr3SdeWNYde{!QUM)&DH`H^>7r8yrfTPypCQdGV6X6@J zv9-2-O&#iM;9lWTT1T`XJN6LLj?lN&ggSgjq7yOM@Fj+wx4do{wgfBUx|?UCx7o2C zzI^sd_2zY6cUsLrBt*uQht*KE%+FTwO@UI>$`LA>yLRf#R zKb=~5{iZs<^km%LcWTyYiPPg7VrN9pjC{+l&aa5vl3yCm%WFVinRj!3X)34`tU?%@ zUvP5ll<29b?a(KF`M~}8^bNzuH%!;77){D7?qX?RKv+_*WZfT*~NIe&t2~1zNZctcL^`=asPJ0_VNNQ?J9&$*uJG; zu<&}K9k0VemF{E#l3+VMkn^NrrwQRBeETDEP^kUcCbuRBo7j)+;;wD>?222)U`H^} zIo2Z`rT+!8H)xyw7w$3ZOB)+8SblCh(?^LDME+<@|4ea#xI|ng9xa|Ao-W#t9Vl-) zVBj_K-!A@Ad{lf%d|mud+%9&+4qO)fOT}x%`^8_0 zuZdl70f6QC@;Gv+I98l4)`}~{W5u(?%f#!&JH&^?7sR*3B(C~%eZ^uwafDbSwuj`h7GelBLmoxfU~A=ZgUiYJI0 z#qWwg5$_eB7GD*&iarK9*WXd>Emn$S#TjCq*dm@Jo-cl1w3o%B-Z@#W{(7-hk?G5cz&+<}b(LncP>LCe9X@h|9%Rajm#s{IzK`4AJzx(8q_-1{adJ{c@So*T`Nco*@4@;^p#RDSlu6pUA#Nyi@*XW%KpOT+f># z--}H9FX9(sHynWJ?;#EmE5)(mcyW%%+m~6cQCu#zkm#4=WS=OWCO_ZX%5oQp*NE4P zcZq!EG4nks@=fZrUl-pLKNGi$xyZwOyNF##w8wPLFegiBgZ-3Vq4d3Fj}dF+pD7+H zf1S8ke!l6L>suwBB$|F2;(RYC(=QRP5w92T7x{W)=6hcJt@w`kf%rGk$H^J<^L55# zk=TvI_Lj=#8|#@qME+5-M~erD(?rv8L;i)bsrkV2tHhJV)5VL#%f#!%8^l{kv}ZGk zIm@>hlMg8U1@U*{t0eNjC;KDu6B6a{B0=LIaRQ0_lSF*|+C0Ny-iTpg+7ICw9ulSJo znE00Xp7>|+Gm*CeaXoyFl{DQ}ut0XPxSLoa_7nLG4a-dt=ZFW13q;fHLcSwpH;FuF zW%;AU6Gfi8($5Ez$&I3&_rU&+Y(B8V^jpNu;=ST?;)~*|;vdBK#E(Qi&cpf=A|K_U z-COK04i<-rdx(5CoB69nKK4U#81T->bC6?3&bLk z563aRN}MXr6b}{;6PJn2;u>+Cc!u~b@j~%Zkx$(5eC1Zr&fj6*C;Ji6&gbEOPWFo; zAI@X>zleUev*Ti(SRi&4yNi9q-NkZon8-)_SpN)ho;Y8u7ng`lVyk$xc${eZ!Km*$ zvcE6>Q2eQQo5)wsbN%;;4~vhB&x$XIe8`ab?f(uii~mP}xnd`=i`YZ7|4WdszwE){ zaB-A4MjR(j7N?7Rq><}eA~uPwA|G&M`nSXj#7o30#jC~Z#T!LF1IhCCe-g+CAZfoM zzA3&d{z?2){F~_W{~VO#(~{(FVjppL(fHNy6mfy!&kJ+@N;%1YrD(k z|JMtO?uIVKzd&}~9cZJyNE^G&mfrYeKAc|LGF%M6G%mX%a4dXXzQM@Te!XjgN|45J z#pM8maK0bGplnUB1o>9C%g6s?s)9^lkgo-C4x=grE|1{{1CDJ5j(O%|`_D%Rt;So4 z`ex!0{L_8>isP{{Zab7bImLTnBID$CSZom&8M`KO~ zOOSR09O3nj9*h6saID~ZF>TZ9y%+JI45D8DQsiSqOOVFv3E}#dP4&DKe5?=Ert5na z@t_Q%-aOQoVnj=j_7v=JeP^LQu9x+(8-srNBjQ0BM7=er?-~}=5~RHbJ6zx0sE>6q z;4)9TzCR((GQl?XD#L>oINk&c(-{6H2Ki1KfqUeGOiE+E9DI=JWu)hwl{VaZX(o^< z+`eZ++lyV8ZXd6!U??>QRh)(T!gDED7a1BJ-WKFL2TuO}71URNIM*4>HAKDXqnxHZ z<6MIJ*hk@fF%O+OxZB?TUZ79k%+HGi7mZ7oRV zoR_@xpl#X9W^T(b$htJ=GB7o3TYkmk+q^50yTZ)G5H9I?T-YHM#UEKAO>ZQ@89WK9Y*W61FDaffAyKQ)d*L%i-=+f$?T`w-IIiz6h zg6M)>OqrCrq#JL_pU~kvZ-DpFx$7VHe);Z%)>x(g?k{}rU0gjz?YmuEIAM!-!`7Ie zf6n7?=M?UGG4)wvLtjHLXJ_qlZih>9FP^b2Z~7tIvL{d9mRGRLW$NMmkuQ1g_SlBU zx5dsufBCbvJZ>X6t1$~~_fR=c9mpr~Lb>)5AJ=W-9 zpH-v(V(e?wT8&z{KjYk=*bn2mf0O6tT>8@6*&Ak}1zLM`{-wwn_4nQH?Z~)X^uzh4 z5_{Uy9W$D)V>?fXtc@;xYFp8If8dEX#h@QME3wOjU7o6%P`{SCqE{{T&+{&*oG@y_ zvu{WH&=XrD4I+7+aZtO$=2P1b-01xwzR03>;bu@*J}d+Y%>{5lfV4Btu%b6% zhC+aJE>j{|JQ<4~&iItBjYKS7%3Ld0Vp_L#=F0kzF1xn1r0cio%8tK^!wG~*c>y;g zOj?7q=w(QOFewkM(fe?qhcM|R#N(7hic)hlI=Jvq#(SbHL`r!ujQ)l3QH3WV4xKD2 z=|p)A4T7a#!j*{eLUq;y~iLvrq|_~0dJ+cuoVzkwx&r=+LBY~0be{xE zRX~EJYM2B|ot2$m&t~3{90yRaw37XKr_8iqDQ6$V*Yf#`6a-6yeeqYCzsO-PQLuCa z%?En?9!;lU=}WBY!5%qiEyN4+?_jGR=}>NF|NN^^B?L<+nVA+Wbt_5>mbwi{3zoX| zj?RCIRsE_XrTij&s`Be-KHG7DnQ6gNS5-~^uQ{AvRGTN~KaIvhur$}&JUxFJQ(x{> z3sA81ZJMv;U1+KE@{i#by^+ruOu^E#xuQR4uu-s-4Pw#G_Q8JWd^JDl$9_2+NpU81 z*^WMOf~D-8;+3oyf~9VQyy8dM84xVJ&o&`e%rjyNmO4AT_#Unpf~C&RE2bD11xsD| zg5uv`r4%gPo@7IdidQl}1WR3dMKM=O!P1VrBGqSj@pW7u1WR4|sNx##DhQU^6}LX4 zi@UHs2$s4-NmX$(Z3vdS{58dcSRR68(tMVCi$#-g(8GR}?JeR5HO*MkrXyIbwpPi|Bx0>E2j_36|c-Dj`^UEH*Vt z!O}6T6N07tS&sK8Sjws3b`meOhjx;gY#cK2SHDE;52&ul=b1DIXecXP!T#h0dRHHZ zZ6*`SQ;ye;{v3rinQ{2wyyV4r9Wk@-LR}OreHNXZVDbmU9$5=6cNu^*ZGgHj*0`3C{ zmfA0u5G;L$t%hK!+lu{*uVQ@=EWOa`n_fH!q+sbo@JIU0D;~@I5G-{QZfWuTTpt8W zot+UZb@rO#N4Y)-mL7riM=4l}|5Qw{^cZtMu=IG=0KrnWzywQqra{3{R$+pr{FRY{ zrOpAt(m|YD5G-{L2$q&`bV9JyIUrcdA2umi>KqU(J%c$QSnAgDnD6CYhw9lX>r)7p z(q^N~hF~e}GXpyiEWH(u;yR>Iu#^V-{6Y2^1WSKuHUvv~P^4j1L9moNhZ9M*6D-{h z$8J38P_UFccektAR}d`aTHX3{F;lD%1WRwgS|C_TS9hO>0UO;IV7w@wh;gEK_c{53 zxiHrJydXzP!T6(QVzT;Cx=u$6*;Q1+@exP3do=V-)laLF#r7t62^4oslL&y{VIegiZ=0Q6{0v%|d?Lu7=Veo|KKW#J{6l1jv&wE=ld)v(gRH!mnG?w(9>iJsdRCT| zEWF=gf%PHc87 z!gBg}zU{x-k^S-mM5zr{avp1a&3v!Hewn^~(I)?Ot1k;H;y>(tW+1_T!|ID{jFs|N zWdD!5aIci^W%168_npL|Zx(PBd{G;30_n>;6#X~5(RV8B_4M&qW&bTJe>-fRwDq0E zCcjn8dY*;-6n*)YuNQrPgZ&wO*W<%~yMUWJ5@UonT=YGe&3n6qzEfZygMcpk9lh&Z zm+@QgUAX--^0A55Wyjhk_Qz^V5nPuYXPbBc?EUDoE<4`3hldub(Yr2NZ$6&v@!y9& z)@3JHeUXjotrLUZ>IbFLlg;2w3_nBYYyEeMZU6hQ-=)v`@f7RF2=)rE2)X_|)%vp= z?9TLAf1Yan$*=k<`m8@sv-%E)y_7!d&(o|wPlJ6Deb%3+S%30BsO#u!#D{;n_2(0a z@&?$xP3G&v{`?5hKhkIYzQOWwRGZq|bVDviaVI&9C#mYf-g7HN|;iQuCNs{U$>cb((c- zPng~5LRU{W55L1J5&D;+0UNPKzBqIMv`W|Db4KJSq>MxgC(taV9Azo1y#WzucC11M zT%z-Sj}@-`iVOpJ3eCDR^`aP#Q!k>>Am4{#q{ona8vl9zPu8^X|1w$A9pyz!+DM7E zl{Ixzp_nj~HO+^tsW~um!=_|IDQntZN_6*~$cy$5%Zm;O$%_sQ5-`r%YKuZl6+@5< z<}AKwol+TQ5aXrfNX*WtckEjh;Wr5r;BU9|gAFYjq6Q)A9kXT=BP_8KH5wej_z(%p z%pgj64DjX>{Sl%Nm`Ur;Fl(^zv>Iw&1Z#&#C@~yGBHqRtGFaiv9m;oc1qint8z&}Stsu}~Y;lF1~?WqBJXvs}8AZ;fP9LRGSwU}-_51Zn6ZLfK}sh9HY= zu>DN&1YEv1hfqda731pL{ewa=^iRaD%Co(p-Od%-ZfAu31Y@0b*kEhMAp~o)Oh~r{ z)oEdM911z!k>0St+77=8c zmEQZfN(w)l(a)N_@%G~xVJBmx+YmOyC&=gH(r76R zx50CQHRX64?>;_pT$}NW6QxKd>+B#a+EK%t={EaT8HXd1TrI)c$VCXehKuGB%!iS^ zKdT65TL1ROdDw=D-|a&R`W2`K9&`ediqt{nJDi9O15HB3b>(Q4y^=E#r>zlfJrT-)1g0}zXx1Z71pgADKDLMTM!n{2 zTLF6_>aAU~i4hs=%&0&q-#dulhFd1&2^MS|y!QHNR;YQSX0zik`LZ`L!eIa-wuuoQ zh84=Zyl&-EIC0j&-`QpH@Rw0)g5Z2S33W7RI}v`O z!{~TXG+7qUNyRI=$BRni$-eQN?(vGQI{c_=u=o!gfu^%h<2J( zHaeb+t|&viEA)(3Pb!ReNJI;m)(YjUXa}aWmc={th$s5QI}C~^5|y2?6ehYxmzNz@ z8SgL@u0Bw~YW1gMHNz36Z-_R}ix$j_t}cUgS9JAgU{Z8-${A<|1j>+oM0D+>5zN0V zaSFu9y2N+EIue!fUD&cjdFR5;Xk>JvKN?MpCZc;Sj`u-I*WU3yz2aTV;(bz#mm%J} z7t+h)U6C41RK&Z0x#jULz2d!7@mx#njczLB&vaqQt2cZ|USaD|RDBsODzuK7RF*1> zcZrryN@3&c=OKz0^dzE@r1A?%$Q{ZP$_%CbSoGvjpZlz9)K#{Q|q2nukO!7*ht_T{q;@?#jVx^ht+UN@X zm(_&OO_fq1`3EG0Lh489CZ~l|a2t?^y)kk)H8`l=Lam@9M-B_j|0xEghAdv(Jfyy9 z#mW}whwKBn60f#-1XN7EUNMN;En_jD*{{q0E5bqCq4oSiYqLZDZ8@RZ|E7vi^R!hf zD?NUyYn)(EAYn8!qZ!m(9f%XL1F1#CBZrOEzpEk?=;qAK27ExyD-;^nG zZA9yrtb_#Dzoc38HD~hW=>sbIw+u=`|K}u*zE0IB82V#vSAHWkj`-i!PIZgM<}Zl+ zw5`Sw|6}`#yh|e&x6RA{>ZAcLDS*Uf?Hl6>1WR`ED))9VO;J;&bU5#2tyktn5`wws9(Icj&($4u>y^x=Z`Z<~Fe^0=PD3UY9 z9o?_JiOa+z#pA`3#dF0=#B0PKiMNXni@z3M6+aX|7WvB`+m$DF75QTT z{dTdQ?Uv1}v-BS$o+(}=^2M7>zfHuQ$Ywt!zAye&SvM(2ZDBdnUAwulg>gDYdtbeFDR^;nf z>8}-6h{uX|h!2VU8JGD#5o4J4v<_tZbL;o+9p(v-XzB z9xCo3f3@rh;sNr{m3^>SEB^}dXz^5WBZ>Cev#sEz@_%3cABs1~e}`;)_7(Z>lmBt~ zpBA5!|5e$45Z{si6WO1OU&xXKBHO z%D-Is0#Hk{G8DjZEMBe#E8#ntHj}uQ6H;8A8KM=1Ie?(E_d3zr7?In&C$BR=%zW$u~?EDNg%}H>v{C2(u zo458c-v;p#@e1*J@ka43@gDI>kmdDu z#bM$eB5xyPx}E=lb7h-05^Ua5$aK?00@up6hfrYi_Cls#Bz{Nyo@km#NHYRL4hVua^`uz6EC$y*G`9%8B3U*zqEOy6IeCe9Lh>mk$aJQU<@hqTWW z&lN8eZxC-5?R*vaH_LuPd`9H0h^+5pF^V|tEU}BYt2kJ!5T}SUMBc{8@+XUDiyOsD z#qWsMh}VlZi+lot_3#!*l256SuZwSrABi7}e-rt90Q2+tG%`=*eUm)C_7(?-L&Oo{ zp5j<>yf{VV9iy!0An{OqHf;M#Y;uru*q__hY4PkvDoWy@SZRJZYDRyvLLFp5j<>yohT4qZ$>ak&FFv4CfElF^=O9 z>o4MZaQB3Le<8g}b`6Pq%Val`$p5ctRJ6Mkk&&Eee?g+HAVvBYCUY-pSh#A5Q$a6t z@w$Zz@#2NBP6Z{+Lz(NKi@pS^>mk>Uo@KmsKs7@5-7BkaTD}}VYlllM#{CM&G%8{<7#g0%DD2(Op-Wi?|1xL*A0mR|2Q zhzDg5^?r^M!3svS1Zh{n4%gQ_I@2#WO-94oT z_vnC~Yf*fpe1I)A1D#GuUUombVEKVimG?&Z$*C+1)0eQ#?l z`|zI8ck}a(s=28qu{D-E?VSf=eV_6!%O2gmCb~5{4&{Trf49v$XWaJW)_L1v$>*U% zk=mZqv1&CatFrX$95mbD{1KT^}`tg4~)*sXFlBRZBnl$xGY3 zo2I>UQu5$!v2J@W9lJgH#oTSNGtrt<|Lu_vdT%fM^C8vM+q(`e%-bzC?wy|F{Cy5U zYp2ybR`Z9aOV)Z<)UVAb6Fm9U4|{qgm7hnTOpv=C$^=8tgEE0zC-o#wy2;?b{cPyYh%-FULPW?aqgPvu>nJ;p=->|PUtZUuVffM>ROuheYM{{&hY zjlV*#^xK{@XTtVfKP}zfb5Uv0kfO!a{+@%kMJ5l1md3c6FV=5fUtN>8HI{eH)>zid zPv3+szv*)?m3O&++00%0)Ic?%;L`QKSr1>yz2e=2HtzS*w$v-$yC>xR z<|oO^ukq$KM{4sON;n3Mf?|ZoP(O;g9{rOpTvw6Me7j9 zbAKba+OhaZw9#SUvz~r*Gn$z-IG-(yQYSd8#p2l;keZ#=VaWPH)N~mBgw|w9hv6mE znDv!93|Utt`7dsMJ?qTqFkFeA&I;);@ZW|k=`g&_%6HIVxEWrj!>|x}lU=Om3Mx=- z*Q9h9_}f9UjSfR{Xz(C!ehoGxnbBc*46RNMP3thchnS&5RDiD3;CWFqCjb86AdC*%=`n zhEdpo*?w|THpLe5d38OR(P6lXeGt-NxQ59g9fobR|DF!RiD=q6e)7<4{@a^x{hiTa zsAS7BIt+c-?u-rt8h=*bPm|PD+PiGB+}#!*COuxq}YFGg#l!WJZS}d21*8 zC!2~KEnf1rU?fn7A$hy3?EGukt~-)8fuX~||AUiv%5*vm$-6oRIt<@o=8O&lAJIr= zbQtVhBBR5wi2E_4!$7swWJZU9|HvoX>M$gq(2AT6L-I*&fYV_}KBYE~&ZjVIGNZ$A zKl`Jt4ny*JRaKKempeV9!@zIB??!^WONwbVCRH&7>+w5Obhtpxm z33M2EY4P|JFVK1^1kX=xWdX0peQ@PubQlh$_YA-AHsoD6@_u&FE2`Yb_D4R*PU|pGK_>EHV8@GRGX0|6ie z*_c0Px7T4P;p#rl4(l*njm_|T;L!p9>O5SEDKoC*7nn_>HV$g8?5F1t>qi6 z;r*@QXIQ)YTf5J&X7AoyQ|b913jR8J`%EdpgGk!!fjRD5y z!8ILWkZqsS7~m~V-=@#D!D$S<1^Z=$!MqMHje&AhIS65h(-?RK$unS1q02M|=xK$; z_mz~{NPq)zelAU%k4qTkA7Xr52-mp?<*&n_WY8Tno`>-(M4qJaC=A}Y^eGL#zKACx z0};x93WL9y@jfQIMpVhS6&(y~HUgf#@w_t-Ih9677&jsEBN{zmJcY;;GzP$U6Oq?x zjDV4gu@Fb791CMKA|q+=$NWY_me4o|#%YM0fG~7u7uSz?NETbiuM7XjT{~h3m5)aX zZ&u<(lz)nB{C%n#VHoo>XJrAh90bpS2xP&ir+>`Uu5coFpLRS{8M2{ikHIsV|X}4 zadELHHjMr}`)o$c|9L_A0r2uDvIU`hUl{xcgFmvBSHgfgn8!QKtWp-KoCh!G@|W;( zDWizTBNk2J)1RAIfgUKY$iw6L$X0|<-Ur4YMEDz9c^4S`F>MTuBnX=QPUBK zG}8DG2G1#vL#SZQmHQy?HL&NZ(WrOVf4l~PA`N?D&&tu zWH^m=FlHb!kp?yLdAe~LjSFFHLF9IX5uB3zLiX+R1;%RpF5ky>dYhBmk%u?24Pzdr z+EDC~4do~Vm8U;qsV^di@&o=5lpl&*6$rzahpAS6KX}Hw@|=|PN9>aaPn6Feikon4 zR`Mkt2P4?5JQ5MUy<->)FsseVQ{g!oL5-n5YN@Xw<{#j9X<=nNz+8b`d^_MU=3%Ne z<{o%9XUfwbvD81h@&j%T%JWSg&#*l6FxASx4bPjdJm)3-5&L|{mCw&B!umNezd)|P zBG|+%#Mxv=1e=(=Kd&FcFqURHo0$8+vo`{^j1!aosC`<^Q~lz}teG=&CUWup9>bVo z4$zJs?va`-d-{6U;WXT!Y} zIo?MoUk{@w2X|N_l()j5h~VxB6)aPEDLnha8jaw2dt8F@A0raA5Q@~ zT?K!16}U2Qsm$neBgp;hAU7wg%l%w9_X|O89?2uW405xZUG4|{T&~;I{cw=`2;`3L zlHJRH1x47nnMwN_VG^Wxh^La1NA(RHHC)Tlm~-)?%<|u4(fS3 zUC-uldp3tR1j$oXwwZ=W!IAqw1NR;q8X+iedyi_p3r= zG{TtIksE?xV|c0vT{SzuTY`i-1UtXut+D6P;Q8HVMEIT;JHLAg5x&gD&hI`(#=`*a+V~M>6)~u3NjJtvvkl#y{Rb ziWg!yK@B^6@)pq&1QlnYh{My4xSoLQJ? zP5C7}e3_<-(;u-^PI;W){Us>QH*5Ze#hHbPR{SG)K5)f3n(2?&=Oim$K(QD58j0tl zT?qCy!nd<@rNQ&Nazyx=&0#FeV)ivs15Y&q+QqLC`lI$~72n?NTvp6)5#C*TAd54> zit}5f6&~JKisC#*(4S|YQxU`Y-ODV_^EPs@3JmqMf`f>p{Qc78X49t14=^7M`iH*$aYd>;Mn>}(mVr3iN3My0m1Y4D8h zRzz;5!E-(S3-CO`7@h@kKJwI%^O5Isd=%=hNVN00QWz-&JD;0`$OIZZpF13pr8Iax zcRV7;(%|{r#fY3sgXeP(Bk~IxJfHguA|E5z`CKQg%Ez-w(u~6S+^X(qALrlzoIv+Q z7#5`3&^rL0i3lo>d>DHC#ICjTxm$wr3y|wDmJd>`{3>`_U3pGImWtSCPgg!ag8Lh6 z7M_7zrz6-b+=R##2*X%_S#1{n44#`2)EN4smRf=s&*!RH88_xpoo+(zIGx1V* zE_UVlJw<<>eGW#9=W~rL&-1w(k?Y3@c0PAMBKIL!Wz1^lbH9P-c?2|uQ<46JeOhHW zpTjTlZZ3X+T<@_wQ>;AaVm8i-69_nz^F)LGJZ}v?c|NzDWqCf=3psW}u=BZUM5<`; zeC|L*<{(tCjGfOdgLOE9&gX_A67|l(XZn2Z1f(91VCQq+MPw5~1+&=s++DElK)_Pv z`!B^jk0G+)&6(ryv)-vp9w~K@QH#+Q^Sm<^ME*Y6}rFPrCW$1`DU5)EX=mZSPs()6O z@@^aeATd@!ZgKHalDA{fPx4AH;yga@u;7Fh-=EWo8jH>*wjemUO2$~et@@Y`kCxsb z^v8%hEjpLjg1`!9Y+~$L1mq!DmrH=LlLgZUS$Xd5Y152bU_*~`I;l-Fx=m}VJ;-fw zt+MR=1>0SOg`ZJOeT3;2pR)yU&6|UmEzD7b4~p+m)r@pqFjG0K5`K}guOi;cY?2km zvB}f>WFuya?=uto1Ksaj_+9i}WV7hIn+(fQHK<^W$BSgKHjQ%Ku5bXl+Qp+=gScwpaB4t(IO^De-Ikshp zH6x(ci582_!lzsOQJ@>1#6L zsyqZSThMwM}q2@afa#a-=)WHz%9wc7n_7)8U*4ISEhAsz?ty=biMuCq}+*gN~p1URtE=-ZvuvvH*_W6 z_Mof4XD*jB-Gpd%;KbU#({^n^N=R%p&+2HlwWaF_JJb6qbOk@8RqC^-E1ubTc4_`u ztFxUm2cs-}ym43YUDnK=36LcIVYWG((czrw zo$F_QUhvZE^?l}IkB5dq*qL6D=QEefnJym94xE_22XsP)U`eD?aJmvWL%$G^axXS$EG@&YH;wr_ZCIq4J}X)|kcwQ$(GAs%=KDajQ%XS)A9 zpN@9Us5v?0^6>3k)vv0QQ?PgXOFWZ~CeI5uIsP>zu`aaQ4Rtc%;wGW~9T%@4zb8M? zZs`geT}li^hXm zzlP8f;&23O31|yXhW15l5(18Q1dkJOeCfA48JY?=_XZ9y#B7W5Q%ee5hY%XcTo)VS zzBgy_n{B=2NRKJ(IXf6J*I)!FCdW20G7^Cb#sF7rhZaUwIzK*biP*UjOIIV{M1kN& zKu9@eXEm2QKR#`VS%bJAoSbwiVM*uu*CBbb=-2m&oHP9m$-^LBp}u6)`Vw@DPnXLvH|;a$1el?@?fG;#C&!*Ge&*`9mtL=LIo%M< z z?&*XMMCs*2#mQQp6>Wu%i^5rZOyecJ7>CA+&4`-XVkuas!(qpzus}S#Ca7y zTVesGqsjb%D!s(NrX*V)vD~qA8D44P@;wI|=8D?5SPFw-nZlhxBDe+NeuPI5-ck4f zWZ*v+!4mj_Gt0pLF(M3KAn@!kSlCX6pl<^|x0``Sr7DE*^7po*V-AP?{@C=$KP%$z zq(LV-`F+n>_#D^N(oi0F|0neCUQ#fsY-m|!@T!7;^HlG=aCN^n* zdL+S*{ae4hwXwB!NqxP<{M+mPW87zS|8XiQ-G9W=y8no$b^jB%nke0WxV0MG)Dlwq z4+*<>+Bfd^jA!?wynAA($-2i=wp6&rK9M1^svzyigzoZ#;q529!ZL9s>Lw%VLpu_vj@NWbRzV z*9mk_MArsJEE?~Xh+dZmyQru<;m5Gx?pa<6Zf`@`LotugmMEj+Npt0qh;{}Q0 z?$pfhUD&x0hMz)?8Iuyxp{e)~Y;T{kc=z)7?nC0RyW@QV@kDR*f%Q@xjg0q%`afPj z(2K7m=zy|`-f;TSOO8iH)YdOU4@ZB4R}Unj*Bn=th(5@-4g@<0`w4Fyz#rC+Hb(FF zQt_-rbm}DQK)&pueXp0Gmv`)SlzFnn_4;qgLKN$}Pnvq06I*NF!>Kk+B`>{3ljw!-tjpot0`L+e&RRw_Ryr zx;U<@q9#uAw96(tEjQsae#Um#JRJlqza0n|%WU3`Yl6}&a=5k!JsGuwMaIwA4r{Ul z2vc|vA#orfa4;e4fMSt;DFO!;B4PF50Aq%YOxwRW*qEm`KdqJ4XdHaZZH>f%ghu-V zQCWO<9F9`G<3oD^p<_|WR~(D@&X2wP_Ad>&3Wv?~D7UxBlwsVC;BhF|hHypu1Csk1 z*x3OI-wAH=xA_|Qngde$DE4n3knEW8fBa~KL&GDU4kl?Oe)lF6o=1emn<__SPBt>H zU4XakD^pq;>K4@=Svg|OP`nC&Z;M#jw0t2>F`#jeSDXwV<$di7RKlk;-oNlRmH)zv zRQ~<9rl3dcMFjOts~}~ucv(}OUOckA5ic-kT;9B@rJ=SN5>&M-8rG~_%$Jk6cbq`9 zY7u&^rJ)tCYvM~{$l4=tqPAj5%0Ak>eWtdqwLbISgxb~#6DNGTwa3lFD?5l?54J}I=R@ARWNxdM&BJEy{!o6kE;cdqRw*oI_ zSlHUKvI%bt(E#|z-z#8ev!Sunh_O`bTDITRIjM1#d!+2_IyJPSa#ZEe%3-PgEe*>W z>RKBHqz=L9?vPPK7NYCwm!=>S*4WzEv?4Whfu9Ln};l_97zv%)DXOIY@eldEsNl&YpGwl54L&r9t}g54_e%u z8nR^3QFSeghYU>(nKleBO@Mg^w@F z2;2Ya+gARW*R1e$6?nS_wyORJ8;(cS;}sE&O$%E+4vtau)h}ym#qO_dUDUX!aYZ9M zIQ!=yT~fDvd0j1EdxThM{85|5y)FZ#W=)wqwq~AJyAXQ2YJyj>%xbA0iZU47 z?O(;xJOjBhqwnv$n&n@6A&d3XEc8?GdWyDhW?}LiyiwNP-lBskCcsy{mBq5N*Z&)D zWcmN_t5~d)F;?xsIBY0J$v5DgEN%wzKu;Y)x69ie;s5utmA`Xz$Nxfk2w!5s`RKa* zybfudI{u%;i(+5#{*;QyAvyV_)wyf(aZQ((P=n=rh)xf3)$Uy@ya<$8zRB-e;TYh%R#KVf+O`aV&1bNY+#5L|03b>AvZsTAKAZN6ecUsU#PEv2^+J%x`yNATS$1z0hO>udj! zcdOK}o{sJZIFfgvkPYJD;u?`RM>73P@m%o|@fz_*;_V_YcC*~C#aG1-MPAHiI`2gy z|MzYc*AM@Dw~FhB91M7li(SQm;$Gq;@nDgnT+Dy8c!v1DcdNL5`TyIyRrvHM$HU)5 zdxr|_Vw?ofUn*9L6UDh=z1S=sE1n@q7BnYcxKOngCnL;Ofg;64ksqm$TE94L+y ztHq^aGl^eVR*HOvl#jIXiBa;~;`t=%-z57g@ml$RD*HC^ZuuXS{iyh&__Fw($mc}4 zzRyXt=Svb#74DMn{Doq7F(nQV`G6?Pj}+~lBe2KG-cOt^&KB+6BUsNu*^9*{k; z-gV-7af5iac%gWyc$IjK$mc^@&(Flo;=SS{;uE61g9QEX5^eBRajVil5&t5;y^93- zval^&4<8XFyO8jA7x}a(?Fyw27x$EZA8~^Glf*glA0pO@O-gSS*NN-JQ%J0DgLtm| z7mC#3X8JYa_2OMhzel`Z{)fb;<^Q$#iu`{R-x2?!^e@C{fm>geSU{qmio{;>_Z0_- zdn$b&kDIoj}uQ6`5-LoyHLDL{!QYw^8ZM@P5#Z| zz2ehK|F!tC_?q}8iT1rK@-bVkcbgc+TxWVx>>&0ak*~MdPyT`8F!}cotL5KcoGi{$ z`h2lLY!q9>)#5QE+H<_f$8Fh;v&2i}=hL@5ZrmvUPsO{%E#kxCe^Trub`kkFEw_V@ z){_0@A1v-6|32baai-GeiigNwD=w9vkKwZaj*|aa@dWW)rC%ssCO@CWWqYob|3~6& z@^2RJ6`xW1bK>vC*Twh5kHk+%)c?5{DRS*hh#g6!7mK@zgOy$(j*x#(v0DBK;tcr@ z6b})XDZN=-D;_JJNMik`ir<$1Jn=j7UoBoM-l6o(;(hY}QhZYWUx_cv{|1S9^@;qS zi;>Ri7jYM{Q0z*gTyNQZ#R?MbAF1?l^6w{37iWtHk*H^(?8RaeiF!^FFC}pd_@Q{K z_`LXz7{~wG%-2<G4bXz?WRH1QnqeDMnLyW(}?4dQJi zwrjI^ulTgme=WW!|I6Z=^1my7D*sB0R_U2@>grB>JmZOo^r90229z${s0JkvMOu5plWQ&WCVYuMwA_jQID_h_6#4 zhOZGnbs7147tfk)ODsC3<6(15G z6WeM+HlJc3O%W2zlU*nl zixg>Qz6x=yI9{YmGt&PXX0id2xM-BYAcH0@zx`*)dA zC7S7niWGyUy;3|zJYJ+MG}D83nNt0k_VprlpJ{IqDep}C*CG|3X;b-}q{uV*rD&p{ zu!|7rr;0N_t8Bs1-cM0?jM>ZK?%{XY@! z6MrdEf|=>R6{*5Z`y-M1%d~OlwUI*0wC(pPkXp;M%SFm9(;hEUahbOLUIkKgnRb(S zqIjx!wzyHeM!a6US-e%GFf;3WQhZK)QKVKg(?1ix5P1$tf1X$%QqGzFz9JQ!Y40Uc z)S31i(cXRldx7jF;t}FXag9hFXqMk7UMyZNeqa2dNU3P%=X-p}$Hb>ZzRiaI-->UD zZ;6zUX8M;R-!eiwN2HiE?cU;0aimDGXr><^QWBc>0+FiFv{#ALgQk6kNY!WB-xaSF zend!d}sq#$w1(EvBwBHx0;!K<8IwXah$zqXO&a?-MRB@&~R-{%l?YZKiB<2a# zn(1#AsmVQ7?s;>3>ndx0c z3NOz%T+>OgM#u$V99=&e3W>--YcTl1x8k5WSJm6T;Q$AUi>yjSp1 z!6yW_3ce&rQe4L0F8Hb7=Ylr!WVjwP2gz zTEPHF7+=HyhiW_L2~di{9(Z-1)mWlEic305F|4%<VgQodS{oV%3o5`04NX~7qXNLRf# zh29^mviJi!6kx636fEl;Vpt| z1-~swl3j-XK#)6iP`*l#yt|a|5qwziaY0h?GW>Nx^}Z9bdfy4;2WAWp2<8axBS?Z? zhK~>&D>zBGc_}vwo+P+Q@N6Q+30Zilccmb?b}9c7Og8-tR$9h&)EHRB)Q$OhFRrGQN7R2UPFzfGy&$-rqq!P2{Tu zuNPGB>rjq+MSf5ax2vjr=tk=Lt)5qK{8L7HJa}El-wlPhJyMA2U7?AG*HcQ43l0$+ zAvjvFM9@6%m?*M&?lD{Bd4h`smk6#9tP!jeY!F;WM7h;-5a3B7ZxTFD@It{K3SKVw zBO>a1tKjWK*yB#YEkvYypWu=5Klxe2q25o!I=q14X!{ruVX9t`RlT6sF5#xUR&m?< z#`el8V0){^I^)8!nRcs~%U7)8sK=Ufs`O(_Wock?j`XuH;ZD)ugIA zRwnD4YMYUXa#vPWVG)ncNBdy?idU?}N}rV}DT&tD-KU|xDP>YbRjlIb=Eg>TWADke zwzaYmN>eN57gx4p6;D-1JCgkx2OgiRZ;08Cd6a2zf6+YZ7=&Luy0P#WKpma+7{+5b zPBdY+dhExH{P4wJ@(@bKmvufsEtJe@D5DL3C6;WlxY#==SZnJL{oOxU$> zd(+#7ffa`z>w#M~H@$n{HgVvzHX^+z>5#*O-38g3p0yt7A&}|emcvc&8MsXxIIUR+ zfnOf~QOse&n1?sLI2wp)@x&$1P4CxmGYI<_D^?^rT<5zW}6;)l>X z51#$uHtFTT%{)Eb$T}YVZwdU&VbY_Gyn1ygUoR7gFykD1z{HZc=O{g3!nl$HN=hb{ z#p60a|CW}NOqehs9xt6VscfRsUy;3W#=Mzi^EHQ!RVir+HkhkI99`cLs7uT$x$`@B z6we3K-WVK3N&hkomn73Gyy zyyU)?SqNz!@IrX-Ao2V3ohc*te?I#+Cyg8f{gXCEUWgAal(4toiH{7vu<+B9T4Un# z>N^WR-c`bM@&*@(-%IZV2Iq_W*>`+{^ThqcJ0}f}i2LDprVP#%_r33!x_%Wr3yr7S zG+=*-l}6e>g^-&)u`0e~J7-{(pD(tlvKuUKgVe`rJM1-(|$J zV0NFoXZ;Ln&Ep>ych7qDcP{Lxrzqjj6r_;ev;Gi7_J4^nQ#_0@ z7Lq;dKSWVuA=$HjArcK`>{%a5?^%B+DiTWXS$_&j9ZK(6&;1WW8GF`;y4|z>J4kUz zNcOD%6!%1-^q%!Eqq?E=p7nf-5K8Y^--Nn^(tFmQfHn!G_pIk9;i2@N^|_3j-n0Ji z%qYEQ{f#hO$g^ktHR!ToJ0yG7KZMQ~O7B_E4SPbKJ?qQS=poOZ_52eS+S{J>eNnXY z?2znPuk4-Pvp$#RPw!d(BAOt8~z42NXTdOkc1rT46_V=;Hzv%UsR zSQkp~Ss%*Svp$ruXMHHWXMGL2R4Bb?{U^*SbI?^(Yeru{-vZf+5eI^}}d1&z|*sdl2&MS^pEJ=h?HKt1?2KJ?n>~H-|iX z)|WEevu8cWRmi(%{rQ|BynEKKqlb6T`pK-4ch7pRJPG}K?^%Bh&1m+l|1E5i8!~&= ztGUFpXZ^FZkY~^O4_N;_?OD&4osp2)v!0(bgr=nTtiP9yNx*^Y=^?59{XV3apX6@OtKFp$d_N;%4lcHzO`su8t zXV3bT%+IrD{VUY>>{&mP`FZ!OFXh1U?pe=uEFtfn^~Z2%dH1Y8g?W1StgqtW^6pvx z2iC&7XZ?6a@$Okaic{S`w`YCG>{-uS^N?rH`q8x6*V?l_WcIA*tP?VO)(@nu_PA$# zALQ~)?OD%v^`Z2h^>=e%diSiq4dK|co{w7h+lKbhd)9}|p7lGRzcKz_FuE0Q!jBz) z879G=^-D2Jh21^t2kB^8>uf(?BE{cB)8jLHw8X}NpJ0AEao~H%=Y)Z`!~6Jw3y|oy z2VRYNa)T9aMnKj{w%+LeEhL_Gmfh#)&~y0uDSRp{mGwQl&&%}T=8fSy8Q~JUcLy?Z zM#3i;$XCBZ)b9lKyA|sF^Rl*tbFPFO{T?cib&uKS-ijU!3uoOM&OaD|96Mhy{JwDC z`AQB)xk4!Gexsjjg(smOW<3yg7DK^dl1Ti&!Z}~Ur4xVJC`;ncg!8AW#3b=&J0<>{ z(MRHZznQf)?A*@8nIsbbZ8(Rom2~32H_DRutKojLyotZoDe>2hJ`(>cnj&jk*y)AT z946U6mKDg#`6Cm5i^dIR6>NjGe7N-SMPXJbtIsV;4n+UT@UW4c=+nqFE6eDIqtj`| z>@2BiZZw2MvvQ1_7v+|SS-Dw*nVBz9fR+lw6@CpZpVceNSp^{&_yE5-Y_ENg+u-Zq z*yXnzZg-iO1jX#3g$%Im9JcH@ICH5p&~gUDoyfx!l09+&{Y7P|Q8~AHn>12-? zKz~u;3oVt(M$6$M#l$Z$iDZ`!puebGW>j`r4%aCrxHvKUfC2Oul?UO}l?v>~_iKrpsB&VA{-SaioUZ+fsWX)Q z@01t=M5o&5?1KF&sMDJ|r^gr|I%l{#u-_W$e2H>opA}<(=-lG!zuk-?+n!iLK}bRhXfa8T+96a3`iSvAYZDk785hG^2v{ z;+wd{RQ8?+3h6H@KQbx@TFwut@&G%}qlNSr6~2R08Ev(kd#S?bve{1-(qB|Qf>X8E z&(YssqYfwW>}LxZAUa&qr*!bmq{DX{i3?fa7Yi96ItLmZaG*QGsMCP~ll`kg28hlv zMhBa|I&-PhLc9IGkO88z(dc0PtJ6fCvsmUg3K<|e*TAW&g=XinzQi3&=DkAtiwalo zDHXK(D3Q_7A)`lHo1vuvMuP4#CJq1kfYW`wiZ_@5WjU()Ok>!~z9vOtjtl?T}) z{$5CbQQ;yzWhs0`>Wqd^#NBGMeRd&3M5)SE!X@Q!Ds@mPWEV0-l+G|p55k^nsB|pb zCD$%wh;0|GX2#GOZTv~xWNv4=bv+Zlg7=jdE z=af)rL^ZSYD)7Yl8{-twjsxu&LlEa3S}E>|TvVJr#Fjx)Uv zZeb1fw`B|!oxpZ3wq>9cJ;#*C+TQEUWo~H>vz)Ua6mcuX?D5D?m*z|suFS19=f>v{ zq8e=%hCieHoP%?s9b*7&O`Sg(osE|BCUweK?n!ox0iqMdGi+@=G+Gcs(IMO21?s54B?q5v5932|b*v@QN;GJ4~}<3=yT%T_rSs2bI>c+~szRA)<7P zs|0&+U0%_?RGMYS7=qS0l2hGm(>kgbyoL~CkLMUA#3_899b*8}<@MNyrFTjP_V^QZ zj-$?eJH`Of84jmwkA4t}u$QKleYhQCh$zi-m0*v9sf0GhW!sK1M3jzmm0*t*R4QS1 zN7yljh|)!_66|prmHx)IKGKdcM3nAzm0*vXsdOoO+%a~HA+X0sH1zU}9=-!1s;-Fg z8l#jk-5NW_07*9=O9zdP5ALFI?B;cLi~-Q$J>Y?GDtq96h%<~z{9q-!(H_7MNocuO z>04C#D|^~;c8noVVsAXztJFfJU$GfG>=;8Zd2PTvpEG253I&C99;Km1Dnbo&h8gL8 z7&2$Lk?uo>%^6{&yKq^`8EK@MOl5x~9S*bQj4~3L7ji}$DT`sn!+Fn)+y}rCIb)49 z0W(NWiIE0UDmBuD7zsJ!jI=-cLC$z1jc2LLjPxnv9blwiBBPuMMmigvEN9~ITVN;T z-kT+xWF&rJmvfMjZe}?THqw#IZ?cg(Sn5NJ)P_kU=TIZ@`>dS9jKr^+bEb$i#GZ$U zc6qMN|C2mE)L_{|7hCr9qR&y*b?{n*bC|lBo)Osw_lc>n{2PD&lk)^@j*q1pE1@{fXZf}Re6VLto zVf$Td)hhem1|$S_aE7T3gM<4(cMfLpP#Q6-3@oiZS)biYIh(!_K0IJPmRl-!vcegSY4XkeF2ag5Z zf>>wT_y5kO#{s+Z&d7t6#n6`$-i?IyR?0&%_a~l{-Zt0b$NgzT$qvF9n;(ncaBs5W z$1a1(i026k@uHgUFmbZ@6HgI;;wJGYvU5`(@U@SLh=Kiu2+Tt7FGSZo9Y9#%2GCWf z0|=|!0J`wrmq`(hcLV4;2`2&wEUwOju5)oBfN-80K-Z-@fN;4RK-UdAfbb(XfUY}q z0O3wIfUXC00D*SudIP0^QaYSqly=`h34wb(N)U=oaR`%fGN+2obWPU*1Y^pI&2+8M z0R&^pip_Mj>Hxy=ICWBVovs52#$pwl>AFA%5H825W6*V_4j>qdRcxl~W*tB<7OU7y z*Ihb*V2rW*Mo|dd>oE?Y*u#i087IrLSQ%rc4j>p~ELO&-(g6fxjK#_r?K*%!6X>Mq zI#UM_j4>7~V_c{M2sD9?LDy9{Q7VEl#$siRTXg{8PMkUhU0ZYj!5AaGA(jum>4Rg4 zdo-J|gq}SaUMGn+aT88>6POyc0qPilU!7h+e6)@$z`;1?h(OJ69f2rcd*7O#J!$@@ z_N2+&At=q7Niyl=apOz%HZ{r4JJFy~(>u}NmO^%-fy>>A25xsJ8uSFS6Aip&CmLMC z_zj{+K`rq+zviYSzG7@hwP70^*So2$9XYmkRJV&a9_8Z^0y~@k2@5-=6mXB4UQWLW z38x_8IK!NMM>&1C4~-K{IQ@csfu()>I#~}m`(gKi{6WrsYCjey9}@Ou!KN(!I&Qe) zf5D0)C2X(ZpHj?yK>AJIbBrUnr^x=u!(SJt?%-4QtUH&w6R5jf>6R61-LYMiWXnb> zKZ%m$4MCa4s{$eY(l26^l6cVH8sBpvmQ!g6l(3)39_>&?rTw5ZcrQv1s3JaM zb(7X~rZqW^KRdQv-Q1R}t;8k+t!;;oFHIg$I*vVHT77#(YR#Ocn$)@_Z1&P|6II7h zMD=YI?1jmORMQ@`$E!3nt38!L-4Eq)2TU*o~L zh=abDT8FM**}AgL!l$Ll`BRt7PA-_bV9tV>R{Prenwo}Gd2^~ZSz0o#j795e*MzUk zobMTB-n3an)&ye=1n!j$$*PW8D}z_stId*F_zfOLFHX0oyYWCR z67VKkIw7r;ZuC9$g$bxIwkwc*DzJ$K#a6VtY+X=((DJ2i;FVuq-B5{L07^=i*EYAV z9>2VN{^B`{lLu&AK7H|`<%?RISApigZTYP7@{IDpIJyPeYrxdrDF{}^HVh=-uWiC+ z4b{!ftLszbpl@K`n1;@6C8yP|B-wsf_GJ%LRQ79YDzRgOY!^XNf7K*jv*@nC^hkYQ z*WA&Xks_?f?ykCkH=1f>W=$J)sP5plvWb&vaPeicqCV+;FVvGq$qY({eaoW&SL<+IIp88Q+%1+ab1b^%G*JtMtshDTA2+ONHhhNl;s+`LwrfDz15 zw%cYKUL_P!X?Yvcm=L9RH)7HIav(i+3)!8+n+`h^+R^K!29m0osVQPlES)sYGIHlx zQcaM%r@?keZvo=Xg0rUA3dlfZ=&cRQ%uX~RJ>e~xv3N;x=F~a!mR8Jg3j?*?#-onv zb~jZccZ{>Xs()Z74ejW(A4#W@Dm#1qFcW3kKAkk%P3>DErqXuXZ4;BO>dE;M{+&Cs z%#W;Mr!r*7s)|(dm{r@3QDUx-uqJ@2oS(ImHZQI`qsabpt0 zej~Wrm$+RVWl`hLo3I%kXmZonII7%@S-izo6JmOw7Plw3JGRJt?2V&Jy!%cr87dqH zu!dW#^f-X8rz0MY@u(_*3VzjnV7wV|AnQ5tYwQVweRI^jq$94aR_$dhTwC9evRd?5 z)3aBS_a17$Bx9bbhkNUWtG~1*tm)R+b5Ee|cfR62GMxvxGIo`^c*<+*lBpLQ!&4} zroOg5m3dntLx!V4ZHr^2y9g5NdLNy1XF!3{yXT-*6{+g_7S(sqM7pfJvvN(hc+P@Z zOXp2h(@JNU!wj8PumzDQ}+W?b6Zkx4E(*y#rWBQ%740_p<7KMD6d?lv<11%Qfwo@-TN* zu2Xx1HB2b0RDTJ)#m1D>_5Fn|OI5>a_4fc(h5pC1GS!YYPH~)B$;z6Vy$qmE6Op;ps6Ux)EGjw(w_!7T zw3$7vyk(L|syVtSlXO&8&D*T%ZbR3%P36%=RNS~>w#BTwI@wUE_V23lT;sZkV5YD= z+z2r{-C*-lO)J~6>6q%L{BPN${ulFKX{si!ud=fDk+}w-nq6&#x`jnE~hf7 zx&KhuNzvnx5(@7b{T!BNLnVah<*VjDwEOpKDn~i~3Cny&MfVS`zFk%J#4S2ULX&Df zJ@V8)5G#p)+AWxJFss!_&Gib`JzG*eZcu-`yJ$TXh<%-_*I`?{wiE|A|LN$vS2YkS z8@THk!&b8;YgCVHYOHL4-BBEt(9D^xW2zcs7XG##6d%Ex%q7ju4Q+A!&y7!QZH&)o ztV-3?ppozgw>s6(iDS6`-k9UcuruDO=GKw_=%##p=9Y`oyKmDFddk6vz*8gP zO}^9Y<=Kxv7O|%0R15xF?yZFH5bvq4^&p7U;Fc zY6ntCoGeLgT%JTFP94uHWxLR<7;8}u~3f?SukKj{+zZHC6@UMc|=@d5(( z7x^H;xq^xZ5aFvt-XM6EpxUzaYOaWctV9D{qu?e%eyqrRuMoUe@Fv0A1)mdqS@5@l z+XUYh{7~>uf?o&*aS3KVF+s)a2AQA1(!WXYM8R_fHw)e?$mJo_|DE6mf`1c?Va{au z2*HVhvjvY9><~On@CSm|3;s;-aluyvKNReXIhpxP6g)=oM8T^C9~XR2uovPmUa803h=ukUoLoy;5~wBKNINf5V;So?TkNIuvBo0 z;6lM;1sesA7ra{VcEOhgKNl>*g`Me76I>~Hj^IxO9}@h7AU^3+@x};N2(A^pT<~GR z=LJ6%jN#ry*;lYi@C?C=1g{gkL+~NN=LFS094P<$B7ZIz#61twFAy9oSR#0+;5@-) zf^~vwKMlm+B=QA{OM+Kh{d`|F1 z!QTsR6MRST1HsP(zYygA54J}@Fd~>Q*k7PXEsZeZ2pL92D#&sP3!bUnufG!C`{?3zi8^6g*6@TyVbN;ev+0 ze7VTAf~y3N6YLP&D0r&iS%T*Z{!mce*Q31GihQFWzx!tWo)FwB_>$mn1z!_COzh1;=pO$hG!Th#u%QkRUS9> zUK^nQv(nAOq)`jEH{Z*rV?6~jW4`n^`L6fGfzx^`j=Inxhe@vkvNydCQ88XanI8TE zxapk(w}}I%T+6i6r#62Q<0Cju}y@^HunxgUxcW?O$ zP(EWn+zPwp+X^@Od<#GwBM!_QBPV<(i9D%v;s>EVeh2P@qZ-#Aa)+n5}3&qV93@V2rv#$I^h zqPSO1^TZvTi&i}seW4Ri+{tLpufh}8h64D)p#zaZnkSBQoqqEE8=kmc2sS)%FJUs+ zBTrmk^sqEf+|5+wbA|4B;vR+x_RbUcE0pHz@x)z$qIh`XUVyp1JaKDaM#B@wtq^wS zi93eAiYM+x7|HO&y@jH>JaOD};~(UStA_unj8 znkVkR&@>*NI2P<5<%zqGE#4hZ+%agve}E@WQNN{m;sUhi9(m#_FcdvJanG@eX`VR6 zs+Q)73&2===85aYI{h#3#BF0w|EfH3<*eYpfG6%3w4;Y7j=PU|dE#znzI)+``+{A~ z!xOid^4H*rD`0*ep19>~bq`M*|CM=p;)-ZA4^P~)A;=z{xJQ`YKfx2nah1UncPeKH zFHhVmdi-DKiMxbm?3yP|%_V!`iF=jx-xE(50_$|zo* zxXHYNeM3BPf8p5sKg|=TNMiTG6L&po*ey>SH%u}-aZjV0fhVpOv(%n>;FBC;EFdXx7I@UwGnn8oIsQC|?9-{mIC}6Zc8j!xMK4QV4Tp zZPusZ?s?+45nnevaUo10-SEWSL6yDp#65{gPi7SWM_QVs%eS*_Gab$u`^Tdt843g%F>qp7uiR1UY zd*X?k&QiNPaUU?=9(dwTLF?>^CvFE?H_a1wIqUG1c;Zr+ME1lJcR%w>^Td%B&z`ym zp15gU@Whozw&C*S^2G7Kj6GfXxjb=~&`Spxf?*&4LX4EBR7DqJ9GfyPB(xq zzCK4%gb&>SI5G}QzfkJoiRE-G=(A(1 zIPbD`E+%!^h&mA+VKF<#O=q3~O}+4qP|A4=!lk5|Yo&)Cu1l&w@{aV-!=-t2dg$TO z94pDTnRDjN0544qF2$LAlwAJp9cMlCaG+duDK)c22PVuOX1JyC^3ntUQ5KH) zn8xasjzg-OTft#Arm+lidtFCk6|ffmwJmGP#Ro9-g>Pd|-x~r}O`} z9-cVG7;Y$yI-BQzjVI2-6{Y`pccxF;D|4JnG>J!3Jv?zeJaOv%i9cf{Ar@uvX{G1z z<7H1@kIa`pF~|?Oeth$iK6-fKuns+K4z&*Ro=!6P8_a>X+}8U>08-`?WpgMQH&tFX zICa0-B~Kh?1$UH_Gu8;xC@_^y7l7S);?hKsU8wKI6Q{L1^TcW2-FV_eS;#j#7sXtQ zI{SC#iPNd{@We&*4oKurc?_L}_=?~gf*%QfD%islr|mQaQylHp!xN|Nkd3c$XpbJA zIBka>o;YoX9-cUDhaR3dZHFG7IGG=CL(KWIhbKkeQ;@axCzeQ!0Rg8C??N+hco29s_t<6$gaP%zR z?csn9t4URLtknBA6l-^7RaI+hjW?9rEOL{=iZ}(`^28lDe$oV`xgvYxjCnI{JN*FEwnlg#hg!K)*b^*=_gY{a$DR!_tL0~d z=M7#EsJ!rw-`&w`<}X$}^2q`_aOJ7T-T9fd@fXJhR-Am&*yrhn9_$x|u5@{TGNem*2uvl0UK9k}Pqor34&zev~1=wXlW;1-Y``oE1O zRlZR%b?<10+pt*8e=Qn2&F6ML7BBfP;G?Ta{i_h&=L`Ls5vL;2G@sjL)H)BbeGB_@ z{P+SPazFXP&MvGb1E1T$NFmMV#z%vG^7b1(x84Xgd~Sy^tsw`P^y{!S)}5|4Pp2NC%^lQ`hjh6(Ka3vZL1_AS>Y9;3uV3b{$G% z_}ro}igQyR`dc|P4VU8PQXl)tgq>@_6#}-MtC{BYp)24G7K_LgFt?Y_?PZwJ@VPBw z;y*6@1giT4f&p^4`Rwo)cmSsP+>V8=;d7gVWL-Wt?%A+MKDR4T%+R zu0V^qk(Ds%*X4724=D}_9Tl- zagrS=LZf^6+-{+Kc=lbexIeMUXXS8Baw)V`a}KofkB8OLd~V9#X+Ae@rQzXo8_RN6 zW}T|?4o6t9ufgZ`E{Ylsb%e;BzZP6+>x0 zxAU0Q9{JqzseGUG;#j1NRZR1_kvt)k=5t%dF7`xGHpg^gNMtKZ{Zy~9N*ocn68Mku zxqZTt z5)NPwpW6(^_wc!0L^FQdjr0?gDH!-8 zYE)oH;bsT*sM5={XC8uddUG?B5dQ#psM(*rP)!$@J~%F0jEwP2Qcsu9?IYMEH1lb&Yh zSD|#iM6Q)XM-)m@?EcS(PV$A0LDNL%GO1I1vFnto6+MzhKh>A7+c6NWV1+z9zM6bncf+`(HE)o7Days^zylV$bR)5Uq4?-(WCED!OQ1%H!FLtZyz?cKXH{E-GZbu_}ubYMlYY+F!Y)X zKDU!;zzcM){=|KD^mi<#m(T5NUWL9PKDRG9_B?!U@6%>i_+r0MV`ZI{!%G4M)m%kZ z4jYF9N#uP$4xQ-pe+iF5&N`tV_;T2|g>AIemA)L7)ym;rMGi)aiWIX#*a^_Gg8_OC zuoL)ILjWC{guTJQ2o!37eK7rH*i2RaWAU5AE`B5&(tnD6%^IZn-1cL}WBo-b*wwau zfxu1d9pS(PWVzpGXdlNOi6Vth@dba3R0d9i{>FGM%524_;Kz=uO|Yz@$KbVRJ~!^n zU=1WA@Wz2ZK?9vQ@DIr6gn_5P`}l!BMathE_(RN_;B(_91umZ(&6&yP_7)0|^*y`K z%ZTal_AdNmM#$uIn*je{fPZuP7i3)#&Uq1Xv=>U4wK-hyD7-oJmQudTkdyhMm!gbW zR~y+M{Q@S)x+dK3U_|yM0?~`8e{Hz$R3(R_qhXz_>r8sN(O0N{y^$l)v!IuCL%8oq zrJrYoZ$$O8ZVWrK;L$&pRg{&p3Q0r{VLAh|ToSc|&|+EfEGcIoI+oD}WeKTTFuH{L zgN+=D&W81}5+;5)>e~nMkSr;8ZnTNvLyeply^QgPWsPL!zC-~GMe~HmvU`xIz_xQ}>Yu}@`qx0qxsfW@Axn^|(O*=4Yg7)i zoTsP~L#u&QjsBwYccZe=a<)_DXcz*dYV;SCIL3_1XqV;W!JYUNxo00Rfc~N~9Zp?d z+j7QJXC=BeNYxl1I(4oN>cnX?(at&@GJpZ1bB?PMvYc;Ihkq(Ts>T4(;T^2bYah$m zOr7tt$TJ2oKy+Sqbzq!FsdGJb<_ur}bjWe|7dTb5qL%XxRsNgyTM(nasO*c*rBudR zPBz?$S1>X_sz!fN;lCuMlC+#LRJjrZ4Ww%H7nK!8T4(`PkLTv7Fbb z)4*P_D#ifODL`-5HimKh5E6rFoTeB9pp%cB4}{a$Z#Y%_RB4UTUsRSE71(bsRsPP_ zToa?esGML_V82GHaQhIDs?lFmt}-gH-+5HIjw&a{=r1ad!RgxXr_|ZSzI95B0iyG+ z(V_i*MV$|*b9#&cqLYgcw{*Q>zb};zdPDYEF$RcEiK_$q4TO+*i8ekr#sJY-;_ASD z<7kk!&2n5SqcX9UBj-vPfQgIHDB0J@SW66HX>O2FmEewd zAXU@jC-E+=a+{2l#AECmcbGA;6(xKJS*!NygX*(LQ<>P^h4e?UsgjL71x$bcD^>QV z=L3cG7nLzawGdk$&&Q|KY&bIh{ zAp=AwkT2zV5Oc~W)LG6lzfs5l(HRb>G7g$O3U?x(MSic4{-QG1sG!vkqRQhO5<3d% zk5+%0W&6Zys&AVJ&6cy85$3S*KQE-eqi%N}b|+%?d0=0hm@Pg)RlB${yigd)X|22wSK zz#gyA;2>4gt)s5B)d(^6Sj;Hg#EPV93_!ZP9-m=!V2`!bX`l{B)fgZ;x5DY#<1#8m zSU`}fF+`MJaFt*W?h;spHpXS!jxj`({_HBj9)G0LC}syzHHL^%VLy`{?2!$jXc4E? zBkdSNL}`kv1bd97(*866NYxkudn{zTF3;%UZ3t2JK$L1mxu4YlsTu<$-HSasXHX}X z-Mr3@F#tNe2fPnXWe+^Hc5b24(;U=|_5g-RLT`ALxa(n2C3`GL)ffUL_QoKde7h-q zMkTU(lT?i%wmrl?5WU_mPg8qcNUP$ow?Sd(V$gOKo`B9d4qkDb!*~a8<=b-uofn zM888I*fVpt!95FobUe;sywkR4DL-yi{0#m0ufU$I{J0$)*^q~y4y)SpBA=t|d>q{u z=ZNV@h}l1lbEIA2|HNKA(q2rk_HU6e_}iuMwM#5(lx_2~Zk|~;ha;BV+a4O}ljDyR zMwSM9LopAxX1*a-PR^n5#Q)=dmOpY(&cQj8a^_&_2}lSm;|#Ot6Wj;7bcFgqb26%j z&x=$PM@Pwu+BrEo1siJFy)qKavF$m1=$|_X$&H1@diBZBk9hSbqU!rFLp4tiI|Rn?#2T>7Uu~HIeOs6P1fEHJ}v`^ z7GX9{&EQ4X5judtI~5&3SB(xJw7UUxou~r{o7@1pSQ6xc-@P6M2nAIa;ZWsVN+?&( zMTBMAm%xG`NkX0WB{XYa!YSI9z#>35U6Q5n*y~Y-P}`~?7^75drfY!?AQ+=mY)%)V zf`w?uNo!SXrfUsOBt2usA9s13Y?P$k~PcAU^A953EPZQ>=y#7rB$>KK4uU5bGC z=(@N992a_oV{no5>n-E$FEKgcr7z}YWNO*nEWiF&@I3XfUuE!WeI@p*+VSK54cM>n zgwt|V$MZi4nk#?bzK$LAZ?K&L|32}egp*(D*#4$C#N4=(R|H{gv6JV|k30ThPHdFZ z+kYIK!Gx0+MC@RqFAm2!-Pt#2#~mj)$cY5~wG8o(iaWVVXE6NxI>92q2**DK`4u>R z|FUAp{$9oDn7P4yorr%alSkwNiB;_6?pFw}@x}xGrHG$3S0#irDl^jXN9-zN+xS-z`53#T-V%^YO;<@)vv5; zZ%dk0TAgEjgN#q^y0g~Gn)-ER_=K&#J&C@Sv6}mTk_yUW$|UXRT~)4D__px|sdHIaRi><2q_KMV+RBKymW<%x5|1*S5inV5KP33wk*_vtt*PYb? zl7aE#z~JFEh;A6roGAUe=8jg_rZLsJGSyVQUM)cszK>+Gy14_N4Jw8f{i_n|qL*T^ zpGvK1w=g(O@f9jI**;cX%pGDT1E_?X+(j>b%3R^k> zg-zm<#+tH;rWVQ7UPaZt6@h~K>1ZO+SgIyYI)!9q8@OK@Q%N!lB>z=(O76I8X>O}u zXB~%Lgsj0Q)0WCKG>ml|%Wr!iGF-9hGdZzz(l~DwGiHJ%l~oO?-P3@6hYHR%)(lOE;&Q8ovU!k+*jG z3Yu)IsjuM`FQX@+XQ`TdI+8oIQ5{6Ek}E448!JKVu(Am*@Qs4E%4LGlRmw<`*=a6C z#arYV&KL+y)hTtwP1d%iQVsQ>^+`5z#;-?0`l6LwIuAL(&T^N~wx+(u0$G-tP;|O$ zt5qWzbJx~mrfJdl4SL#1;?l0?WV1|tDjET4RyU+7n>t!d>PcQKLAvE$D$xpEjLOav zpOV#eqrUCmnVCp0cz17hJm&AJl9*$<@Rk`VUFAlY%iFtf>BFT&cZ-_lj?S~b?hQ2l zyoKf8N-j|ySY0leNG5Gja&2opX3BJ9BU;N6sMR#2rd6aW8*rsmL(3fxQ_)$iwmJ~D zsSBywEi((~y__$YwRGOpioMiS-J!POI?N8AF~O=aoSCwoHPqUPBqoo#DvXwf=BmmD z@6CkjDeF_1JQgR*XU<$=dS7F*K9vG1awcV>wlt=M%7*kkK}STd1u7ok1Nhv z3q;FR>tzHctJkz+szOh$Tt_0tWW$8AN_9iwEita0U0>Vv98uMV{Ka#W4Hg#?u{XydBZQ$Tc;ZFrykYp&IGt58LjyQyk^BO^T>GJwh`nfq1{Ey00>= z?$+wQ*-9ekmQ*#nNex@SvLU6{811?Cye-1jvvOry7Zz86^=--Ob(JVWilc}3=lWJn z^)KdtUXHNU(gA0JVX+z4cwG4KuM2~$v9bY0LD^VbGZndxsj44av&zd4ijUw;){^Gt zhPHTZb8CERYh!%Izm^DykMwroz~kNHBe}g4caC`q#>Zh(BYB$wr}wG+Y9pjc=bM4IRBzvD;t4HeS*dFd3{YR%O?j8BB z(CKO}k1os&&NR=6v#cq|I~%VN8U$%qUxD69!-sc=LCSci#XiLK=J=XGA%Yb4Cn9ht z5pU~8i+`!$VS>{ID+G@eObM2DtLq7Q-V7L^KpS=eiH|yw!8}~BnErUdBLp`H zUMcv9;M;=P_*{(f#t1GFJXY{z!RrK{6x=SDk83L94-za9JWQ}guubrXf;S4@CHT1D z%YttS{z=frwVL@16FflhXu%T%uMvDg@I%4gxR5jc1i=}C^@86OyhHF;f`1bn)KABs zDY#T{z2Fssj|jdan2T>*nC}3=5k!2GGg`2Oh%XV!1!oD)BO>0BA|E5TLi|^Y+$`8G z{u@O;Rq#yl|Gvl<3tle%H;R0V;O#_|?-{|jh$zQ9g1D_v;k+BA9)_brbVG&X1Sbd{ zA~;p>TY?J(j}YVs2u!a=uuia9uuV|iFG25QkPX(|4tAet*ZR_ zp%=^Xg`my*FvxsOOyoyj#8HCd1rHQdE36PcP2{U)zjfx$_u!MYlz7YOx@i2GPH`O*9 zc8?yu5Hso7~#S6SQe(q^p3)5;=pNbLC4{L8*`X2{{J&> zh7AS*3;*kw!-Uns!<%o}WXpO8dd!#pCg1gNn>cV2Za(IZPPmYj1i5 zNRM`9`7jLK^lpZmao8Vt%pQb%sUQc#c>YY#=p6;e8qpyby+_1tf}V#S`;a+Izj^>3 z-trCb)EBoXZuz#tjq0_S_z1wE zaqWhh9h>G3+YwqdbjN8M*6#SjhG9ESTQ*_GtX0EyY=Zpwh68s5H|*T8a+N)4=5~8S zaJz3q)%3@Z<|atto#Alx^y_zqo#4)J@VcGhz{4+`2mj}h{{z$4?s#H@m3R*B=ROaV z(2rr?Ua=M>cmmS>?|yu;_29=pJ9YhxdVAEVw+CiMW=3cBdH$B~tg0J%W{F}rd278r zs_OY`>+J7a7njU@`8|K)>NCk^;=ldl`%gOa>N@z0e$;yRr-6gVPp4&24m*Uhp!TqU zwd`p>Y>>1^rGy~;!5PKYYN7x!aovq}c z#s2Gsmit;}waj`SgF}y>fX!vFxxLZDf8y!z#));h*CGhiFI?y1{{r_4pnfSwFvv)_ zTHfb#n&IisM=GFu`45KpLT5nP7jRBw$S2fV*ncfU0wI2Q42qY7Ff)MS_=t*Q@`)@}P zK;=@yXjzB`Di^xLO$a5G%l9EDDwmN6%>D~z2~fHG6`tAGAVpBQ(BH~oRVTrfOMRho zse~N43_qZ9;fzmGk#kXhP`QNQizU34{~=TZR4$C_-@(LxT=*1JN#$}fb?op}^rhS1 z1YJ#WfD9Ccfn;6mI>kYvtx@xvtrs&2^pK%_`2mz&`iS;hn=WtsZ@6uO{t z(PAKS4#k5-3`cH7T|nhxGT)bFIYh*~$bA$K6|o?)h;a`SF%}^`52##p+yN2A>@rnE zP`U8xq^MjzXQ>*{s-SYAn^wP(Hkg-1kqiGLmoj)kHY*0%7x{ql;UbgDWj#W|D6Fb7 zs9d;YS5dhvfv2|jvH5f}^;VWF88mg~p8!y~EK{N32nz-(7aGf-z#oQSfC=ZU!Vgc$ z0SlZV^s)2$p(vzsxe{VzAzOS+Z@QV$wJhdZlMzxXXIEfrk;)~CGWJfkSfRV}B|`6H zs}=gW=?T4)Ypu{0k-`ynBT%`_1%THf@_lA?kBE`p$*Ni_bZ_rgm2+OCiOTm$+*o7^ ztN3U(t>jA#h+M(Y$BXWQm3@hLq=N1EM9~{c91__FcNm~@38L`6#E3`^GkQ9UoE^Tz z=-zn8Wrd!Tj7lJ)0$Zg56Ct7o&r80OBjcIWOTCAyxKkoOr#)WoeV`IuDi>Ym>5*bK z`fnxfya@jjfy(7gRo_LC%UQ_R@+SaDxz5mYWZ{YBANDTB&|>5|IDPZ?A$|EcmjD#~$1Di;nVf8t4BbSpCel?%s+ zKkOAEjK^-9Rzmz-c&OQ*y-*EiOdsXYoMmK;=OQ-KKzm=V z&W>>joT761J{(ascZ14>0>*fBB`pLh7j3~n^zW?ya9esv7&)@y!2pwwZABFnmCI{P z>J$8s%7p@xO0sc4<)Y+<)SXW2~fGvu>+n`Y)$1d4owripQ@m8;nj>u&7pj% zFJHG~Ao@A`1*lx8>`R2BZ?X+Q<-*GZsa!@eYf!o9TFj1q!T6wZIZdUvD2n@Li&QR~ z;ZI7R@3WSma?t~>E_wv@LFJ<5mS_?6LFJ<5bLBWBccy{7782VYhX(&j?=Q^L)ee3qTAs`4wuEy zvhDCqNT0+iBcbD*3%_7M|B@px7`Ox8nqK7){MnAqMr6{f+yHOdGe!BTa3A&1GU1D! z27l74XxSf~1WS-!!i=;VLNHG?@oXX%>`MDJC4`^F*tmwo7(Ki_v94oqT!RSw^4~`Wr zhoVzpGIFfw_~Ga@76u$Ey70NtqZtm46)opQNuo!N6=tqER#>2L2fe|uvJir^4L^hI znJ~S*Gicj)<>JA~dZc6jsqa;&!eAQI{v@AS4xWx5`_sNmesDf@KGW_;k)Zu&t)HUK zUzC30V(NU+hqg(aq1^qIdn@(-TEKJ?zf|rb<^COYzSR2H!#4Jpg-V}XFZP!S<$jv( zzZI}-i5HZ6INjC|dkIrIpKs+scEleX_6R&+AFAqefhwQ9Xqc+e_f-jpK_!lJn5x-@ zsy6(iv4noAhCfh#CqU-oprNX!7patd=UYQnWiM7q`OXgv#|JN$DB&9D^6|_FWr0go zjeY_75&9`hT&gVbA>_B|rz~=rvdCyuU>MF3$}*QJ%Nz~)Nct%YU9Qq=fy_?|Mkq^N zt}JyS!2`-%cmcM2LDivDuwVz zINqW#6vAKO_?$w22>T%2UN}eff-nq@!4zx=bK#hYb2PJH>SN}>w*x+_agJFE;Wuz> zrBDfB68hPAoMRdx)WT6iVLgNs;8;)LGzeG2aRr6*Av_Mp!xXN7@DUvRdpzbQ2-9H0 zGMt!H_ruSl`15@Zsy5bM=)^VU_+FzVwttF>7vzMT3F4_#H>%@;DRcoorARK^f+4NZW8KlkJPSCLgCV z<`Hl#qChjB3CAfE*Z>c}aVG^f&3?F=#BeHuE`Vb$1sZf698DBx&|kyBE0{8&fxOU}7!GAOg{cTpXlcA^)gW$4&E?U9s5 z!JnsHf(4sBE8g*s#a$bZRr*{K9+hSGYSBJd&&S;L^`g;V*5!-1uPo~qvCtbIHxqsB z;kit=NS2VRbh#)Tog{#j`-kR`H2`b#CH}w>SZY21PrKvFfi60z*gh=REJ+`p8&}1| z7&czy97uQX=_aJUS$LE2G5qDcBDCFf5ZoF9Od=$V#R=JOc z({CMTZ>EDWxCs34&2VHK{UBipIl(AZ?54z=uu`00lrmO|`%(K=V|L4HSRtrD-eKu?4;LY@v_zU6G zhi#*ftO!ekIuXvn>9<+~n^`259sc;0gB99>6Lm9Q#1fn}I8lZL#M70#6~F0&kM!7w79=oVNf)Dcz*twR*Q)e+cC2k*vg zYbime3MIJR!v~k4qQI!3yMQ=RyW_-z#Gm-4_!Hk2f8zVvt?+a0jsv>q!!G9DI);CdpKh7$FL<#P|hO=OkNLKx(-zVhZBxa&Lap+UhAYY zqW>O_e(;ykuIq3lVVd?O=sFxpcu)B*BA8q%Hm7qr68`F7hsnjMqb^NrEY;!qmx*)a zp_&Ai(PxpP#~f6kuWh+0>yl~D?OozZVPS?>|(>^3c` z4y&iL3lPo$PP|CF7ZNYUnQMJEf8=L#Fd;3(ghZcfa7Hl2VU}|J>Bn4o2SMi#CAi%q2p4B5;wJ6R zC7vn%fKEq0$mqX>({bu4gf2!w0DjYlPdjy-!wGdbVGzPPoaz#sj?H&(oemvWUHwgd z6`RvBDmtk{)G-zlOpL{z80qV1I85uacgSIwV;B|gT;ejEz2FXhVlNudVhx@+U^BfM zj5oX(g3F*O6k{T^)1j?ECm!9Pp?J^=G9$ObsfH)pPB*yQ0O~KNc&2S^?FUUsdp4Zv zu)V%>jBk2)X&;@h>S?SdX3BM&O?@F8znK+YgA=`uz+99P9lCICZ$#SqkkO`vYyfUi zFqY7Y7;%*IaPl4iw>I#hl<)BgZ>GeOdE-$&0;eCB3sowbA3{KN6;2?ywi4L*O34(_ zn+n3zF&e)<u>Vvaw7jLYc_lXUigWdL zTYSX2i4#UHU)j_VZ&z#R_L@Ux$|g0|3x}l>ch1G6mb(LONg@Kr?N!3E~Zx>|~F0`j$G`B~HKbPPV_DbU`J3oqG)KPSt-q!?sCBjaP>HMTGEi#m})x{;+;%MCJ-K?Nus z)aTD7`OtxJl}+Ed&cL`cV64-3AbiI<15{N?oW8)EZ_ziWSOtL4s2FC4VO(yd-&r=a zfQMg4En2!gYfpB%ku1NtX!tD z9^6Np5%w7qpG##>AN30M83QM3w@)zU^zv^gc4B2TVx-LJ?_XE!$%s8ZMiBuz9Q(^nRQ5;KH7gQ$(R*}`Im``ydcnK6=TJu=qIlWHTq z#yN>q;MhhGlnhuu&##A*tzgq>nJSzPT)&KfjP>ALq}*uMmSYE*TD5##uL(BHNttWQ zU8)Dt^i*O|Ft|I?6d&aWEnnJ(0xYj?sBElkEh$}&#k{M>FE5|Jc+TSF0UDQ2U%Y7f zqSoeBsp|H&vat)`d2`Hu{HM@1rvA#)>KZ)%+Q7Ngonl-7m3H$(iAW2eco#~K-_h@&5BgF&I z1sT8|361n(eNC5?oH=LSjP%NSO-p15i8@m|wKSmLw2~%7R}b6-ShtQ|d@Q&S zfG(v8ZAzLZ)zFHT#U*nQZk+#@=y1LQqYe2PrjkYhhHU(5#5OI{+uA|Rf!}e$=s;2% zm&is@VF+`LOIT6e(A-8I1($|~`A!34fVu*IC6<|FRV9=7dekwnK(}l$Ux5~;WpQgY zs*GPTm8O0%yfqb8vQC)VI5ex-PrD*sX_;miYG`dxsi?styeVIuBE?VyCoaW~mhLmMG;MZs8F#H?I|36c0s7Ie( zu8jene~$d)I4u&}6grN;ieyU1W=Cy(&6r7 z1m)$oLY>0(GZ3TiSFcix#Ps-pA$|DOY96o5)i~+HuU6A|Wv(1aAASoj^gM^(!U9;& z;m5lc@8QRa6~^FW9kx4pKZc3ScFsqA#{)vmnZ2RKOj^f285oUUh7_+QD5kVO8HgG>6 z{{#E*_>NETd@wgHPNZdtP*H0QhZ12B^{@v1v>U@G3eFUqFIXYCLU5&EgWv{1+LP(f zp2Uj;FB7~`aEstC1fLdsRq!prj|9IIf3O*zFs^AX6U4nV|jEMOR5^NMaL2!%UmZV=?IevEgi z;LU>f2tFnFh9GySqdwJ)!jBNSO0Y?AgW&0c7YJS{c(dRZ z!H0jh5~|NoD@FM*G$y1##KmSiRwhd=@|kN^V-t8587f@~56 z5fD&Okq}4%QAlDEAR+?dM%B9SRb$=P*4kQEgo?FltzxyURoiOo237^FZCqOZ=iGPR z%u85;)>`}f^YVE)_j~X6?#o-|eb4=llwy94)FkC2Vo~+zOa{&Tl7(Xh;WQ> zyl{$en(!Fm@xn5p;o3nuCre%?TrFHDJWqI`@G9Z8!h3{25KC;cDSI!t;ce39k|w(@MB+l1zgR z-X}aL+$4NL_^fb?kR~70-zMB4{6x4@=;!km^k@}A>>}(TG|zqTA0&B*aEx%gkcK3T zf1I#XST3v<)(L5ALjCiFmkO^GeqVTtkme}Ve_Z&C@Hydcg|7(T7lIhW#0wxUZx{YeNNXGFhlMn_p-i)CB5iJnLxeQ9p=_RufyYZO5iS-k5iS#&=Va)c z=VT!FuVp&l6<#c)1rPmyDtuD-jPPaQYr<{94}{#Zobi2p-UV`NNMajdT$m@!7xoek z5)Kh!nwzxT`^7kA%z*?E>GI(H29|Gw7&a!{+-E}1#DgB+>{8#nSA+f>UH{B=#|>|X z_f<-V@AQ3;M<~4|l52>}_sejmVH<<`0iGAF?oU~UFfAEqsN?w_cRb%r(A zMWg9(i)r2)1DgGILK(Md=IDn1)I&F!!}}WxJs8HL7f$whYkK{l(=y+e;pZM4KRhPm z^y)<*G?@_RpQ|?sB8R~^$J@%n3+>);bNpabVEs z=YGJ!tHTXj4%wUU2;`fRK z^&Zko(4oT(`zd5^dJiJKLGWXGcr;I@_bl9Q95}7a?wI53Fdc5#Q;@ysy^Hji7Ee6( zCewQvZpL9=JSO&X3^N_c31j$QaC-GF9k_eWw(Zh$<42J2?#9bsq2MhazlC?}%imty z{`e={m>V^2dY3`TJD1%05xanoV%{<+?2B+0fWLcNfp~Fp&ZRFJ( zgz_EW1|rOLa#bu_SdYyn1{XHtY{O?|yX9;fRyd4boFx*ibGD5>$P_Bc+13%g*MDo% z^k8v^;z+T7{g$o1ld}vz*n#VditTO=4_M#z_c!@A1;E=DcyFCAXVmm<*G8T!9$%cc zBjKObl!%OP%8JZt%8O)`&T5K7ia^SVY?(g`{^OfMkRp+bAcY_WAO#{b=0Cc_j@Uc0 zY(LVtaYvT#l^4=>WQB{j1^iPdjo4T`>Ha3`hJG8TZ?{9!w_Bm??dff%Z@VTVvTTFti0Jx@zKY^6@e>j^zm?oM$c{v<*_c`f6woq&;*9G9f^Ps_4&&S{np#|f-Zr= zadx}yeqY*qb|n2hE1JD!#2kCn4bZNe5!v#`rcjpMmvNs3`&^) z=%mHRBG+S^0{u?^+<({fZLic#+;+JC*scEglac>Pi_iYtzv$yO6Sp1epWGCIy!Lay zy&3X&$RWtM{}M zyruv!kjM7JD&BYN3-jKwHr~SblV^tCyTmj+d#-sT^kgt`eW2~D8t^?zv5eoV+ zvYdf@%}}f{9gwdb%@ALD1CMDed6hyK9_=s|OMf4}S#=;rR`AZV+hn?EG_ zM`WJ?H#kE2F&fuFkhSfES6Tp{?1HEYk!}C?QDl&{v9$gGyg}ARcj#DzlC14!2!^bU zKZ<62gwlYlEuZeYks`?2=x=4RY4~$#g!&?DI~Q{FH2ecu+jZ~;V@UM-C>hAw%o{V3 zwY`RlgRG5F{acy%4|6|;D#_aJgdbY_$MmJ!zXrM>Yhx>Bb%Y1W+Il0s=(+d@vNpPr zhsfHT90Sn^Dgv@LM+`-;K&e62=7^E#=ST-+ZI0-Yweh=VhtcD41ZVO!8|i*c-H>;G zq)4*17vUErfdk0eoCHumrZ-ArAUc}jK@vmJ2T>Q0wYiyhWLd^Y%!)oq@nDHL(Qb@8 zR$@H5oEeRim=}GAjWJ$g!fMwUtzyX9x*?C~3FuXjwb9L1CsP8*+9>)-*2V{1khQU5 zkbTkDC?6^LOt3B8h>${Pn<|5>tp-IiWNl=ta@u=dJGz#S+0k|69FV^yO~)%EHO#e_C1qxR+Ki5AZv5t#-sdj z0Ay`!C6cvW#L%C2{u5f+2eP)~*^j^IoPpAUxGBn8HjuRqG-B^)8Z-K3c#08|WNl7H zNwPMl0!gwqC*RT00w(oh+ZiVAxajRbkhRS>Vv?-QN$QYj7k2t9D)ZE6ANJC#8JVWc zGorV$kbi7f0w7si5taWOxx$3biJrq6y&2^UCRy7{%;+r*Hj=fmK#bbn{9`+`=S%7K z^hdv(h@c>YI-HD{4p|#pCw4N^1zDR@AuBe3jRCT@$4wOiu`d`7vNlH!#j;spkhM8- zB(|2709l(8KPy&98Dwprhgr~^*dr_`$l9FnK{5XFPO`SPxSRFm4~ZSX{6N;`gpY_l zP8nov`6hgH>_Ak4WNpq;GA{OW${=fV^bd($gz-SKHYfbBSOw#QtgVlUKQ$I$GlHzm z(Vr39L>Xjl=8Zkb+IFH%NY?gSQ{Fi-&MT6&aViG^i(Q8;2| z?FLyJ1WYcs6yAZr`StU=c1)Z(z%HpT~88*emx`7>f8fh22t3jQQ(yOp&BS(`KA z7RN?WA7pKgToXHx`XFm_$c;s@`Az2$cH}`$^4anMdvr@cEvFaNLhw zgJ@lH@GofhL6Ji1d}%*KDqXigZ%yJHG^v%q9jav~Iw5zY%kQMf*>(oBz}eOdJsG~x z&VC9y!N=ei;wA#&%k1pe;gc4iS6bkg=Kp5+bj%7b4rTHqm)NmLDSTom$&to4WZ{!S z*>^$B2LiVSV0eiu`wd}UcxkBJUyv9H-0q})RjB<|BZp%AWguMbrWc8&p~1s7u8d3H zd{jAnawzyABA^^khcdb0j#G|bx_S;VU-;P;`TQ!C55J@eKj-R4tPnpv3qKzUu0U!* zCJ7?AKsa-H1c_h5LZyXsUNV)kVjodAJ*-LwVs|h+_dQzpk1J zc>?`#TJ}iecO{&BeCaU-?O`93#WBKP)Ssgtw@%qPkI75#D42t%BZC5?1Qs4>F9PDp(t9TFOh zFwF^B)kp{5`k*L;;~f9_jr>fWpETLlJiMdl4l!zy z+%F8$fwu0BliikMEwe83W$fJ9DWCR2{vud!bT=JZj8G7NWHr*k;R_+sNXG(42sP4C z;|KvmmvuG-3~0hn9sjIk{Ef^#$nxJGY*|%*DW!{b_Qi#jTw|q9qQ^$9h?zb*I-7dQ=vMCNNgSQ0htcL z8Lr4OHC&J880Cpl5fV84*7ATEmOYJ7ThmAf-vpxl>Ko}8

    RpbWCxCRgH8UjT7xh znCJM{nDN$N{O1zRHvX#ujdVDpYE{THs#ZlBuR#b;zjaED5gv4e`bIj)7LAaGMmk=0 zgjJ1ne1OxojwNtiG12L0GXBXW2ptJM`1#;6YZ=^#=rjduixwlWdYJ1378JgOOK_%J ztFzMTth`1FoB#-8iCI1$N=@X6*o4Q7^JoGK4UKx@bH;lH;bq6Wf%v-do=Mo|c=KJV zbC}}F&4GoL5I`3+`EMBhFE_5agq1k`)~Yp)blmOu6P)GhxHw`ZaN@c_C^pWyglRYt z(Qf1#QE&Wb5>^`jT06Nypu64mA!yZFg#(g(>9Yz=@4ane&nB=wSodttT5((x{5~@( zGx;FpTyAEfjONJ0e^$@A1{#M^aa_B~-P4$Z`9yL*bIkt`b4>CF$b}e;-#l~7NKm4X zFl9`dKhF+k`OC=bEMed z)T}*KO(f@EFw2y@jZ*`}Fyf4$fBp$4278jp#orDs>#qWfOt^x)JMck6Mg|4bx_}^N z1=^G?j~sIh1CKwg5IRABEqqN{jIX8+84o_Fu?NN^TTN|F-<;syl?HwVB~y+ePQs+G zak5Kwnq;PInkUVsQv(G3-+X!Q!;;eGzBsi4RcCr0%ru< z8t-Hc2T{y+V>-H{9VKulF);0`sxY!TxX4K{Pbn6fbWsW7Kv3O$Xe9=4qWZ5`je*b} zv(XMlNs~0NH75oVB6hAkkV{(mHF7VaS0A|L&P_ zb|J(8B|`n+BJj|Ns$%cdIQv3Y<5?%aB6kk?KfDw4lj$mB2HDv zTVi-^ydRFFjHvMyi4k^7$-%(pOgPCzlI#(V4(U4ZI;o^`Y0a|Q@{*c*^b=`jz^PGN zT2%(3B9#oAe*HVFI18)mic1%ga^g#{<18hsnOjlw(O|REqp5}sVXw2PNSbrcKf8avtkHM4SUY6f;<>*%JG}p<|kBue>>Riz`9g!jW7v z6Q9JYfkBf~!lla$;;)l1rv_wV6;_Hi$E1ynkX@22r>eSkY3UM@r0hFmPI3jWEH6jA zed5R=oeYK-Xsb#aR+M4*Eg3eX)Ucf;d2!G#nznmn$5~NcxoB}cV(&tUvv6t6l7C$ zb!}Z@ME_=loqZC9o71p(78Vr_PV}xVUs4XHtv-q4!QA)B`@Nk2c{5c4%~>cC4h&*4vgo$h$<%1gtaiBred&r8Gi=&6G|HF$4t zYRPsc4^1K!Z0gd#h3tI#>UgrQhqVYdcS)Z6Iq}Z8J|?)?jYev*=5@;4cDVN-yIpLM zA8V0;e_e>Ez&2uzW&NFqckFlsF#dRJg5SKI@kLu`emhL$Yj~pJkioAJJt$)k_LG01 zaICOcc)0Lb;XL6IA-^zUx@&}I3NH~}Exb*5x9~yX)56~f-w=K%{F{*VV?GffUwBb2 z5c1s~_XSm9LR@xl{@rwG>zxo11$ z-736a_=M2d;3E9bl6MGgzNLnLTcNR?g*;C3bm2VVQlYVRh29;K`3WS`c}{3-Qz7SI zn$o{WI9@nI$ekA%&K-M+#+DTLkYr;M3i)lxp9ll^rIq@|<`ZbXy9E}?pFbxve5LSQ z;WffLg%1m#5xyeaCj3m8fdS9-ItlvB>YggQ`iP;BJ=Gk94H(s zG~6)=KUMO1!tV+15OxICD2vHTcB^BUxJn)ww7dkbMIWc+y> z#qg=Z8AASgP5e4KEhaFLL|0x_IF0TF30Ks;T@pMWUiR@30+!mEYm8*GH% zD%o5|A@l22#(PlssE}Xu(*J3pxxPYvN%9|rZwSo~WeER3@;`($9AG-M`6GseZH4WH z{Kc8!-Gv7V2MR|B`GFAiCJGM~8g4lF&z5Yi?~n~w9B{Gxmk3>M4s+c{_&WKYEp)j# zE|q+(@CG66VOWlPgg+5JDEyi5=fdZNzZSkK{FCrq;a`Ox3;!YHS6|G}aCHEONFE^^ zFPtPaTpZAwDfxI|iEy!SiLg$%LdY-5nBOzP7lgkN{!#d6q2auP{)dwJJu>5eAvE_d zki)#+0Jal$5Ox*9*u{kR6AluN6pj%ZOCY4feN>sA;oJZk&JCd9+yKs3xZ&J@Y&bW7 z_402Jo-RB~c!BT|;rE1wn-B4CmwdPI$3lLH$ntCwJ|X0Ort~*l9Ke?))3AsBZwa>w zKN9|3xKrqdF7+eAEFo=V=-*k`Q`lE%?&IJdD*0gH1fjXVgS%Sta^Xs$;p~9>EXn5! zFA`oS{J!vZA+4WSuAc}W6mAr57MlA-xSx~!TcNpsg!>K2ZwdLeGSl55Y!ZGUfQI7(I9K8P#*pzB2~QH%3YQDl2o1*}^v(S#@B;Z?DKz)1 z@V`;=twO^E0{{CZoBLSEKa*^X=^#HV*>HnE{=MYag>MSq6B_Oi=s`4`0Pgh_qNx{# zmD5gIXYgoh`EZSTjq=(NnYx0@Nl*mpeo;l!<*H4Z0_8xF(=j=&B$sl$``9g5Q} z1Dw`eq;&`S+CAK`iSY2I_Y~6Gjse8ofz!e-ht@n#`P{Jb7J3Wu9)#RA z?&0c{!o!>IgGG*c4D+SGn{PebZX7tR(oU9@phJfnRs-3aUhh%(vKf9%504GW^v;3X zjRU83I?|(_d$?g|z{8u~2v2&r^-ZS7cPDNfrg1US>$#iyUXCztdWRuB_7lt32B%x! zTi|AT91lDmNLbc*D(YYu&wGWgUK0kva_JCUy$y1^K{b6Gjt^I6zC0en=`G(3Pkqsa z$?`n|H^zJoz#O+DJ@43OzC4JY;bFZ7z4`Er!5>4%q?ZL`p6(oi(;AKOS4xKtH$BGj z>di;_UU8Lxu3qvN&XWs=HnXoEyeIqmqQS!wJX*J}Kl31yVGH~E?T6C7e!XK~e{ssb zeh@6|X?Nat{YmRXJ3^7rdlP(Dg)&AhDlUa>eU^Xlr&&|GHHD@Q{xmu@=k&p!Mj)j@ z%9#4n+QFZOAO#?$O}z|K0Fn=qZ|dx|_6U1N2$uC(u&fXHUVQu{N|LknS%oDjorwetYndO`%`TXbRo+cvIkp>nAx zm5*MYkhGzn4Ey;B#pA>iFrk?C^Nuv3n0Xa_nsZPgtmu);!OXK;Q^r9x#YIh7=YQ|M z+u!p?P^V{$nj+6GJmh=#-Sl24()F|Rzd+647rOSTL!jYD%|;jDyy?BL|Jp+s-sZFO zKek7pj-zQ^&-(qA^;$c9+jG9qj-7*jMbo!MyJT$OzjGcI&ZC$%2jDUTt5U11w)$B@`k`xeh6~P z`aFI6rtAXv-oC!==hlv=;ZDoDV|}~N?T>y9cc9;$>$5-ief(;+eQ*Kv18Cz{VPC)f zoP1+nKm5~BUOw#Uhku#|Oalgh0iX})%L@$;!Mc9i3vB=C@7%&?VKaOJHtnM$8!_|v z;Mnqjef=D~hw^`f3$ib1Ur)L)|4Kyh4UbPp6xiCI3I+e~G45e&zrc8w)W;(I~3rpsy`3^n%mc3hX_ggdX^9$fFZHkDBYo>5xT2= z{RWiAwXeSeDYkB3U&b_3_Vs)$^xD_ofr`8K^*>?ayV%#COy4_Mp$X81eLY()s}LSZ z`})I>=pOCs!>EYIzW!2_+GAhO$LcR@U*8ugChhC_9PP2MuVs2E`})}wQ}*@CQ5TPW zeLBmMvajbYxyQbKB;%&+>-nJWv9JFL8^dE?KbW0nr%wsdh(0<4gU@4MPcyiG%f5a# zik7mkH|?FWukX*2rR?kZ3xmhLo(207_Vu5ks7d>JK9sgz7MOIvaf%dp(*?NvFyh^+SmVyW8j;xug_(tr|j$bxwOZ= z{w5YOWnVv#$|?K$O{~$^VP9W{f#|WXzmw^D?CW>1F+BG5Ic(Uy*w^ze+-qM?JBq#8 z*V8W3YhV91^Yhr(liAa2Uq6xgd+h74r|hw>=i42xeSIIs_t@9lY(|fLJ)a`I_Vs*9 z_S)BTUNy6?C(A@L`}(!?@Y>hMStYN1{RK?p+ihR}S2m+-UvHxVDf@b}mU!&zr?bU8 z_Vt@t|2^5)(*R-5_Vt6=IUf7^Pnb09>la`Uf>OiEq+{Rg>l1ABGg9{T8(ATbef_KK z1CM>ZVFlQWeLa^MuYG+PYw5ACH}?D<`}**ufmz4rC97{zN}-$aeC$-e#^w&~YnU(Z!1Xc$W2f7^`l)G_VqVYVNBA#{z2K-n{qtt>dC(Tkrw$pn#$)Ov{rb7s}K8n zQfY=CYi?ivUdXYp=c~c+`=OlIRml%n=nvdV1!ANJ4u9y%!B~H^dw9F6FZ=o(Zeb#^ zVupX@%2}~LGycb+miG0X*>-;mx%TxBrtIq<4ksJ@hnPX(M_kz#yP9b~+QPnmgKJM8 zik-=_KjzAjm`(kSDf@a;mQ8!GuRoV1`dKsk`WunIJ(wSd;JS=9EnP_DJLRG2|UM9sBxG#=ibA z1hWv1ef=n7U;jCZ^FGcVb5Tcol(DbB3&rJ^8pgiLxFNG@4@E6AVegUe+Go09OUmvt4XXCA0w(XB*1|9Qt+K|U!%^vkyv&W4_ zW=f-Dww>t_JH?ubx!(9NRc>$hiZI>IGH5qe@?#^T@zZ!0n1@6U&dki5oSjO&Yj5Pw zJ!TTdfj64n{!iG~b3K54eFB5A+0hP??CYtr2m5-yK!nvNA;igV%^~~^Cr#pyG=`5( z^f}E^x1nK<_V_QG`twZ!M-%u;1cs9hjdZxFIR^GlYJ3BdJW{zIOI=5UpW>P0-!QOm z&A1+KKv`u1PuSDLNEnX89ARZ69V{wBRyER5<_N1B>EL>S#v`nA{2LnS_<`}C<3n9| zA_oFjPQTUQYox|+Q#VXIuzNJj@psBNS}LcJ0CIw8wFX7{xXMi}9QtZbx1!YU)o za6(o$Ho!qsSPTfl*~Y)dXN;QpErj2y2^hQis~jP%k&bH|A!N*AZ*YW+Mmi)!JchAz zn&AJLQ34YK9ej56TPs$2jObUa@)*&tSZ$2x^UUZxhQLo%5u>3I4QLJqrA*bk!;jt5 z!iYY-u%H1(^bDDR6Kxr4q+^C7q&3pPFFFwtXryC_BlsHWSc?-Qm~a(N6CG#{EcpMX z5j{%u{PZ>2QYS(Wzl+oX+rD?lZ$LYWfeefR3Jyu+mu64{(H4jdVf|)DP~2|Rv}!!z2rC=u;P*6GPgXV3 z@tPy7ZlvP_oM3PuaP2UQ4jmkgXm?cG9Oy{z;VfUYtuue_^i0Q;zRXwH(^Q}DRny=> zyLmPRD{fnJ34?HkouE@N^4J^|CUh3TsrX#C;%U|jYZcOP>n_{->!BI4YC@O!m;t35 zaAp{vlYN)@@{$uR1Uq%dhYiH$@L_3nn+5KbZmYn(ijA_((OI3Wa&ozbk8JRLbg@R} z-yr<2HLe*1{$_|ZVND|)7dZX|X9&$>dvV-=`+_jlIA;)M;6y~*&~uz^{AUr?8~?gB zjdWaP{AUt47-WY}C!2tF__qV!#)%#zus$Gq@Y>i;=AeEd+k5Ch?xx5FRy)$H)+xaQ$=9lPQG6L$Cs z{8(lWNd1!?KCHo~B<=9;b?V#F4xf==7;UWaI|mJ&z!XO_ZHObL`B&1=-XEPK%Y46M zlAi{9d^;HS!xA5^0nIG)X?I=dvCN0nwZB%j*~YNnSb=xIekxA(#(>;4kniRgcGEh4z+7BKuWk4`|@D#K`zm(N}23nc6=WSUp)Cuk5SmdJuu-R{$X48TA zX$J(OJ>c}3^k=7{x4X9bmwyFYeT>d-Q*d2u#aKUS36-+gEgWiC;V{Pd?^@v}P3w)Lg;72Gsf8Igd$S7k0WkMnKr3_Dn!Dqn zWO?b5W#!hP(~e3^EFAt-jWZMdmoBVXHfCXUEw&EozjO%X`o+tZE&x`*zoKUOkp6Ww z{mTl6(TC04AJ&*-VAWm*kJ8$Oi^rhY%ZHcuUwU9gO``vzvK6JZ75$46{ihFx#e7wD z|GN6x%7uuvq_VWGvT6~{=$BP3tcQVUe{c*C>)=;bT3_mwzX?at~I zw=7&zU59B|Qdd@4R#{bvE&@XZ2j8O7rAtc<*#=x5k_Q@$eSDnj2dHG3}Lp4CE7P4Ppg)psD1*!<7 zi;S3e&FmGGWo0Ol>liGPFA8&4}y=2y0+`Ut?mT6pdBpQD`Pd{0a}{dXzj z#~Hj;!55PFa)gNAUf4QB{%Sz%NW@PuJ%~{1C;vjBYo~vRWWL{FJY&BIESG$ukgwty zewvWKc2d4X$ZyRl-zL0U_@M9!;ctX*2tO45O_+w44NNB@j0+2dqlCr6CBpr7`cAv; zx6^mp;Y3Ujj-&l{`c6CSx6^mpVZWU|+5v_w|G(Mk^NStY5l#~xCFGCc^q()}Z+?`k zgtbC*y@UUSlCKb6BmBPb79oGnVLJB-9~EvAz9{^i@Q=bj3qKbALwFdkb4ZUr1rfOg z1@Rc+d|{bzsqkdsN+EwcV?2IcNHn}QK=M~p<|m}YM&V7uJB2?G-Y?79ooSVPZHJ(8-%9|xtSjIE)ZTKyjpmj(D3&_?@q}-7Cs={Bz!{nE8z>mmxZqh z`E?lc-6`zIAJidt7WNeO6%G~-7mgDiB0NHPq;QUKu8?1zF@1ipNBpVqVIjXuroY(< z54c70OTs@0-wmk&*|S^I7~Q7X!wZ`K1uRa zq2Vin|FM!!5LO6J6xIn>2-gbvK_c`0uJB^vRl;k9w+LzAL;ZV&v|FLPLHIM_Gs5SD zzZ1SHd{g+YaEH+FC?UOnNoLwSGlgx09fX~P`NCd8epbkMbA;u>O5rl$DZ;hFGljG( zV*D$G*9&hH(prk)_Xr;nZV)~pd`j5T4&U%NA?yQ%yY}{cFk-qPAvYSLoFj}26GDC} z%y51*Ni;l9z*5QlqL=dCEPO_2 z_@q!C*WUgQ@_$RXRY*H&mYbXC5&tQqwE^XjFe1zr#)MG+uh{A1DR{q~KH8oKE`{dk zh5vZe$2$<`7$S7R)#IlobhGbxP|y1*29^YK@Ld3Ho5vXm?-UM%9^4&pQimt=I~1pz zHk|uxr=NukzHU4Ho*0+z;g+cs9^QIbgZIr&|2v&5E8!*vbknP8kzNhHE6ai(+Xb&u zlI?O1+-@8=tviq&_1wb^I|Clx@~!oxhey+7dVF`{#$g%{A-%)hPV|Ib4!1YGi;y1s ziRI(lGPmDuft%@ZJn#r~+c!J?NqzRsPXAHpdB>nTt{y^O-tt}LsV`nxCCm2=+!)Jj zZgXsJk)GQYMBLsakAl9qPlsm=K78NBeA({I)14b|T4!QBm(robO^!0SG=eaap@9EDeJB$~1Z{~5J@g4ij0 z@ZOX{!C_1-luq)fls)*XD31SLtP8F^cp-vad+^yz%WDsQ7)vF4@F^HoDSPk(sX7(^ zn%je~M+Doy7RAJV>&uuIpFv!E@bL)U)gGK%g}V0OhoVthw+FwAX{PMKY4hZ@2j|#! z?ZMYE@m=h}2ho>LXZ|&4B-b8%5Ry&WgHJ@Fd$b4VW}F^-@B@sP+;9CHH0hVM2R{H! zle7oteXPeG{6mz>V-LQVV#*$zn-hEN!P}ruJoezFELv*6buzJe?7?4TMydVQ2czM< z_TcsCz?41s8yK}7d+;SFvDY4a8amy(-}(oX_qN~q#VBdY9^ABd${w7z+8%rG4lH+S zzjYSuOW1=)Q1YZb_({WLp8eK;&w1e4Z=I~OUVHGjnZIYh^$F})k3IN!Hk!vCd<*Vc zy!PM~jPJ1rf0(W6u?N49&Fa~2{eFgf_FLz?YGw~k`jKY#;A83GwFf_eRr1<{hnVKK z+a8=WB1wDjY*Zj+4{p{Hk3IM(wwT8r{07#4Pxjy=k#5Q!{O|1iaqj-=*l(Sk23WutrS!E0F|k3INh>;sQIcrRw{u?PQx>3Q~Bzn|-gXTSA)*3x4S zzMlDc?7?rNzQ-Q?8RqA;2Y;RlUVHFAu(DozaK7+tW)D7@d3x=^kLKj^+JlozxtTq9 zJ4W%^gFnEl(AQ)Sp364%*n{`y-2ZC(t#j2$+JoQ3w%X%<>*>hl>)LO4+k>um`V&KK5Hjqg#n__-7|xMw7rEd^@~S_Tb%|XyFFi--P8O zQG<@Px;COG)^sHc!0N66L_4kPI(V<@`g^FH+LgQ)E3MEOC}4Q4?HG~21FfW4c@TMr z(lKUSv+`h!J`XX%)ppxuNF~?@K52mh^Pl6**~gvtSFuA-Lhj?f8Q!!rUryPxkNfE; zqjw+o(P(w<<9-k#bDQx8sE>Wzc~$b|hhj5W671vdq!)?BsgHf!9T|4!d>zew+<6n~ z?Bm`EQJivMA9uGLCLiqM-Yg&N73EP8?axGNtk^mmMK?&HoK)PqdY*~k4hCSJ-y zVITL`RmtPgptOWLPcM21UoxyPIAv22u|`?#|g*}$eDu#dZw zS19%>8yx$%yJgwNx?mr7Ce3}^O`sLIRG=zDX(n>zo5=p zSo<Y#DXr%o-JIAd}i1E9k>w+T*Dt(X zeyGfh(_boS7=tF25-Z5-WdZq3GmehaUn+fEm5o-gBisd~kjywPPJgK!0jH_c8nhpW zR>7ZHr+IM(Nati%2fyG1=Tqk;7I;CN0n)iVsS~tZNc2&@R!>H28CSDn*zf>w+6|~>6RC$6btK;;S%6H*Rw%;o14CMG*7iWNUe&p(~ z{cfO6E_Ke1GeA1ON$Q~eo}f-1`ZVL*I0K~fX;KI6_bzoFW*c7+XMl7%49;V>@N^ycGM#(O{N zyvVxzDwhG$DRp%=LWi5v7u?SR|2mfe(mBi30UJ!Po;pA0+Vs0z21w@)SLaVrD|i)k zGMU$FxeSobuUwstZLHv<)S1gNzmdxT>1>D7v>&?tb*dc9WVYtgUn<$CsXHb7a2LGC zDe*xr{n6_mvTPrFo9YlZLbVkf!U&7l`Axa>SDK4ll@G1pF;w|6N5nsK=`WS@;54oI zC$!W`2%Y<~rF?cSL!@+XQVGj%BbE3?M@G7x%MdC3##O?S8hnCE+gZtooy!p0?i}X8 zZELGtI#;qR?QJcqop0r$)xj0bD%&f^oe5p7U38G74->lFk>h$USV$pw7!#s6Mu)N#`Qgps%et)OkAl zd4R2n()muNJka)DZ?+~&Gu8^e%+gGz(qQE0l%_MM+K^{CLie9Sr4v}k zgY7s&r1Zn25=Qv-RLW;|6YMxcr1Vl!3EjV$N~f~i6YV%dr1WW03GMMNmH5+o#-Vnc zA?Te5JNPiScg!g0hhH4b#6WxG!QHt#m++}}oB>Fe*W($k4%%ZJblaa(&5bRXgkgjDZQCgLVLVO zrM2wqW9&FXq!h-l3r?BP9!*p#<%m1pjxz-9aVi^nZnF_S8X=}V5Tzg7ow++rMwuOF zfYP1s(V0P=F&yTL?KlIV!+XH9;52#TsU}!YCEk2xEVc6(qJ-}BDqT&b<;?A5JI)X& zaWp>fReFp{m$Ms}*>Q&0b`SdzjCy-a#O5;+kBc0z>|5~mzvnE=J~-F7;GMwP>o?RN zo68&Eqan|vA2-dh$93mT@OsGgID1aB?D3J!aJ9v#<@(Z#_ulpd<2McR6#DW0+nyNa z?RPEYDxAF^q+W591)>4_B{=&WjD+q&f%@7reD(N0(;n2fn6ni zaHB_d8$6k2LzA30Aw@AXILJoiIY@ydIT<3)QG%JaJvp2Hk#0zCAgXtOxOb!<_3Dp6 zRogH_+Z(}^6TwQ zSblxJv(CmSDnuXlJ$D_p?9RA&0$TsT0Ty#UXI#|fTEfWWf$JU4(+qMB!HpZomd7x7 zfFg!40VgSdW*CAJMnM4nH#;y?;e8~*(U{#VcsD{n6JsWUx%jM_9O4+9LFSg9L#Lbh zOq2N(_<-es!1>HLMBXgHn@}ci;$p{}z%o%Au*)$5K49V?Fh@T#_hvoIQ}0ta(*CzFd?s+ch71gI+=Ts54-=Q^w+xO~>2Mj|yq)0B!ZD9MA9XVmZyec~QW)O&bk z8Om}+R~+oipnMBb&1{$BZl>vyN}cmupsGQ zRb5rypL=)Ct*lzOWLa7H+@+-p7i0hO|47<(r_}wM>0&SSx!A~bZu7F6O;6n#{F^y6 zPg$*EIXyAiX(N0K0OK383kZ!$xySK0$!WpN7gjG_3PbezQW(kA4OnbG&;yKqUpgQdnhx{-{9q(49?bNwB;!K9+1MV~J|`GFhm-=r>~1jN z2kSsI&A*s*0sbM0v;m2Juakfq_DH?>$+;@}EkU=AdwXozLKl6x^BgW4@tYq5w zX_KcFTiiw&_I?wq%PUF>2Nex5J6U5N@s{TPUOi^#m}Sx$vvi5s@;PamN!wztHdEal z4?xRWmsC_Xz{b%jbCM9i(_*H%yeS*IFt!Q|8LO%-kLr;y$!FsxYdhmU~JmT+*9+NmCfp3R$u<*ul~cz}6kMHTEp7gkrFR9SA- z!rqd-F#!X_Dw$BZi0x@i^jDZ&+iT0~mMy8bl9sRD?3|8aJnr(oxO!P_vz{y>2#}Z^43)>XXUGO)5EJ@+=I; ziHAAd0u}C%=Ir1!K;`$qm7uXtMKk=3O}F{iY$TSH*1@oUX}Pm4c}ZRIt=#^(=emhRKcwh zVvi^sS>$btW-EnRB%1ZCNrMeuzO=k{QF+zEQGV{k`w$vltCZTsb3oA9y=JbTAdyes4xx*qzC- zpp--)6}9E%ODgNI1d(^ZatSd|$)l!LSK+ef-bU0duPn1bg<@6|CxsOYO?S8r%NuU1 z#<^BI>rRT&!@X3E$0BTfS$>b*%+Z#Mpwq;>hE&#-p*FjT;!f*f$x1dKX3l)(9f-HN z-O=IkGfQ1^*p8oh=ut;Znl@VlH_0R7iNHS7^4RiD21}LYFpliG#HqUB2De#f;#$KC zkC&rl*S_Y=nL2&q;U%-p7&X@?YVpot<`LCptC=@P?%({H)2-4n1n>_?dg@EOQ@Q2T~5+Jz7=O zwP2tiMUk$?z?gLwc84Y-b&ue%Zy+Ks{G9xt(^!Gqv*qj8yL@mT)5XhhEt4}IfQfk)41)i(NZX&qr3RjNZ z1T#CQO|cX&s>g)`?OBS3#;v>|Olw9{gVh-K@X1+NfeGNy0yVo+_14LG62p9RFI`$` zJd=@=!R3-c3Ef*X=Q%w!pE=7gx4t^h%x-G0#^EyOve0-7Z#u*T{vW2MG5jH3ZW_F6 zPab^lH9nekM&L~US>IMp8vI7(IRa+C*qWqI>YX0F{7K6wN5OBbXOhYY$4@(+!*8s9 zQXYN_zc_df|JT4#FowkAhSe^2^ZaFeISJt*@BPWPa^&=r7`Yg@=?wU94sA>Y%pS$~R>C01BKIst6pNfYJ%|`Gd?!zT{Ay*;aPL4qMDk4GF~V};i9%C8 z=$|I}JmDq6tA*@K=5x33LE#g^-w59jeklB#&~Wb{zTw^h8txsS;obon?j4}v-T@l! z9iZXf0U9m=;FWkA&T`OXh={L33~m-~5xy_{LYRs7q0}EMoGLtCc%twW;d62s+iCcpD0!vuT%p->9N~9M-XJtK&G6?B#Y~r* z!w}CGUMsv?__UDL3e+`Us~AtA&>e9}vDO+$qe* z1&i?ug=2+B2#*(53Reiv5?(6&sqpv0FN9s&Iq6RnE)t$6{Gsqg;opTF@tZr#)k`=< zxKwzt@TbC8h1-Om3PZTIGoAjz(ZW(8f464%8sP=P>x6d;9}zwy{80EWVRu~cnNG3r zB;iHE`-QIvcM7Ap*I>LN;nBiVg*OO)F5D(;gL@Ok>mr;WtPq|jyjS=e;akETM6Btb z2tOrajz@5>L(CGkCnBGOaW&m%P)-QB zJul_{!r{V$g#0Rt;WLHD3Fisv!_`L!0quNB@bYSWs8z zkciN8z%CCk|MLVR?lU9Xk;f1RlK;_s=IDn1XmUK)I!8-AhVkfy6W!6O-XQ2OjyKUthYmMv8DwvI1z3os$749X<(ulMZ#Kf*{&*g4RIdhLj@OW$ckDA?9z@UZ zu(EKW*aS~p77Y(C)62riJUz{2Z7H%WuHEk8ria^~W_oi`zCXE2Kv!?zuwf2eh$u$( zg-2Jr zY{Xh0xd$`g_ihV$qPQF*$0580$H`IwC{ zUZDxA-MLWPBge>ebf%YMWIk??zZA#Fk!ZCP$B1d~6vqf@06iQd6IkvP#|R7dRXIiy ztYm8(BMs=nufQ?F7mOZ`k&~I#9yvzZP&vghaww~~Ipapo?)<#y&l&pj&VR!FfGJjxpV2RKG}*Y4#Qd7X{n z;TWL>*WNfr{=%W=;TWOW@0Z~ixrh1H_|lz8H6nH^d)>n^!aFuE$H*u)nulZLR&=qK zW27hJdpJfa*^GPP7%5}8hhv2Esu{<~02c6OUpqr5mH(_S)}9`FW8@@O$ip!*k^So7 z7~xyty>X2El8d5;W8_ngtG#fHY@oh}W8@U(=j9lAiwb+?82Kfq-i5vn=K}rtH`}qU zETflW z$%*OZ75<`3Q+O=NRF;@a7yNPccGsj*)gyN(=BY2izV* zLYZWphy_r>@GzIF!-|nJFFZVyeHYYx`Mwx`jSG)(WxqptF*3#dv4Z-eQrsVdu?mC_ za?=yX$Y@sv$4D&|#w0mL9t>p~juBIihh06($>)(4`8=A+$8d~naP=cr2v%%X__5|3 zBkzSWZ$oymLzw6Lp`6!ErL0&knmqi0Td6?oc!q!I%E4G?G<|rxt1pg`9d2PFv55@- z$d$$G@o}gn#|TZK!hZ|793u~=I7S|JIYq44p_t6!M_kz#dz@)M8g5JOm?X!@2A5ML z6#E_<{4rOK#O`EWHn!jx*|Z0ak%QTrKiezE$YB_8t#FK-f+DuUF>)Y=Un?9V#z1!O z93!8j4O-(ES&Dvdjbmgv>(mOz$iL88t#OQ8j=pM*W8`|)eD541e_;FVonwS=C0gMa zAqR9T93wALr4^15+RwJeF>(g`p%spi+u44taEz>B+qA+l@(+yXRyamprpn$qMzWaG z-Z@6@#46ef$H?HM7~$qAt#XWz1fo@rk>PBB6vxOx?AKN}MmDkpmX>=45io{MLQjwVJjZexYu$nO4&f@4W={n>eT>`d0+LAt`Yj5y-%fX#6wRp1K^M1(&EoiV#| zRF;<3FNO$=;aJSGdyTsVUC9P|})zl-NuiiX0G)B+H2GV07v!9Tp^c3tk z|Md})lwdM0gQ=up8*%=-oFgsA*SDQr#50U&l8H&;891(ame*=>Ki^2opx$HViiR^b z-OZ^+zC3M+S?OUNjhNnP{a+#z*-sr}mDCKaYi7s2pE|@t#bwxTVB+mvH1?B(kQ~ie zq`FqCXp$6>#(t8JB$Jy%2t$g1Z-69ZKPSk)!3pvuNwdu3QOUQBMe@aD!`qsmXJJv{;6(4*@+IZq>FSd>9vrXzNAzD%TUxbnaiX?-d1YN?bycEh z*ziHahn#>f4e_FDPaGqB@AbdPF;bs=d6#@IXnelS93yP&{{@Z_b9LA)$B6Tirp3(m z+(qreG2-5AdURTHjOcmIqtTLM1R7qB5%+Gb#Z9flF)|u$oPnP$I6lZR(m-r4ZV?z# zt)&bDqce$daf`rC?R?6eL}=HIYyjz*v~QIw8MUm5vLvY zbBs9cu%BbZX@~tBBThT)=NLgd;D_R0^1c%IqHsUQh|?bbQH~KjrVPN-@qn`O14F7#KK6#<0|2jBiihY$<>D`K;_T|Pgj>ESMG&A^1Nh@V$yq(QR$!kQ zDB;)Y0j2fzwUrB&)g#$`KE6#HBYbXk5BF)iA3X4pq%}?fHw?D+iDTp`=bOOBD(k=_tDF`!#tV(No2a2o9+ z$H+_j$T2b><@?ia@*OyA#8Ac zA}seG-!UcG%fID#$Kteqz`hXI!N>;~ZP-H4g$oo+7&qoO8MuyX!g<#N)OriTErd5!00^Gr8=y4oN)i1k- zZjy0;ZsZKOVct4{stfTCbR%SSO$(6IHT@byu>Ex?X0TtBCG;l{4Rj-Phh`y^bR%~` z2nT|<`j17Nj43D$=tla|eFPc>bR+b)GAH6+C0r5egBm#$yeWJ!KKNE>t`P60yL4w7PyBSxYXXj0IPIAT`Yk_Ib% zaOO~x5chF^8u?~!z`sfGGIc}VUC}h88+nC!-^{#6hMfeg=yUJ`-H0OwqAMvLBrz0y z6?FmKh!Yx#_C%k6Zp0C@qKjCxgC*ufr!ekViSg(?0f^%y=0$0J0lE<03L^lgmV^usggW~;A8i9t6)(VxH8j?O}-gKmTsgY1jGLHS6@XZoznI}kDg+NR1~ zt#-Ggq=s(fOr~zydtN)bnfjwFSxK5xlt8pM%Uv2i*Mx?mEEwoU*jWDj^)?!n31?n| ze>{~#THpo<*>+YJlsuHaEJXU;=w}!apc^q%y2z-4#a!WLgp?+7D3FksbR&miXtgb= zvC@CqP7&Ic)LQ8exFex$$qFm|K}n%#4yp*c5i^1FBhgZ}=fe`CZA%tZSm}?ny%A~q z^0T6uRDM)(p(Gof>$ zBvJw02xqV_e{S>%X7rW@TbY$(v#%Moz4^y>XwODyPk;2w$(-d3>hKx5vv(kUzAwbq zi7jTj3w$b+6?>SC0lE=G;+r3ch1sx+d^wIBip5#sMZPYM9Em-^p$57UXRKw##!^1f z7b0P$FFz;tT^4kyoBp8KA2|=Id>!H@d`RpZ<_EeFC;o`o73_7;jr29)qhqs~|1zJJ zl5w#F8x3?Lj{YIB<){SdMx3SQuviDi2i?dZ6Mt&#S+*+ZMjZVavG224SNXzh95i$6 z5r%_qWl9VD73t^LUEt;b^{CRz z?avs3ob)(sQ%ZJCbpJIt@Fk2f(DcNE*t#}UpuEC1F<7n zA<&Ib*_R)RUBf;A-3TuenDeopvD9b#+Bmg1EcPMOJIB}WI+Nav*e`&j8+jgj90yOc zmq9n;Ot{6dYnb1;u3Qs)i29%#al#v7uQ5N+jnpE4uIRBhr~tZ=b;e`89pirV=@&R9 z@aNxP$9M@P-3XH~bR!=!Ptc7x9(UWZF9PrY-H7Ay6FWwVY|@Q59-td}kWnsmJ)W>* z-$Qn!8(}>$Tx~1!M@XKfGHu$?ky$7sr#tc`t{k&EZco43m%afWvCla7KsQ3cbRXyb zb-wtojND*la#g2blIm<_vU50*BzM}LzS`&KN|4J{C;f6?CObFx4z|_xzD(xoPhXLA`aqZ4`8}85#7y&#ZedyB%K4}5&NuCz?Ej&8rgs%%_ z{u*-Zk7$B$V<_htc(c>UzZAY9lzpF(eX&bX#_;!D*&idjb@;|mhl3EAG#HDhe^ZM8 zV*yKYvzuNdmP!3vTsa!sgm~dwL+x24T$ruU1E_xZHt~+c!=1yKCnAYh9n|E-1cjfe0Jz6iE@5T?sMz9veVP@X=a$8aadi!sxUw(Sk#(FORviOQ zo0YnGg<|J1(FLv?iP9SoO;gQr2rWH)xgNX)+rj-7rh z7=}=ghtUF(5C&)y`Y~{t;oa2=_NU4gWCoHD`b%ZLtAhRRXHcar#tukA=r5HsT$MFe zu#PGRp~@MBdGwdct***WD|iJ}`l6U138BAKo`KUTFLuj)h&p31vp^EU0O{~?Em@~O zP-hD3G$xM$(rJfj=;)+lCPFCSBL_%A7$BWtNu4%Uum^RjS>#E143N%oNgXuKWa{A7 znIs_$fKCDW@iaJ1`^Bu_QmPDrCrCo*FO?fym4R09BC7Bz36c={OJ%dGQep*vOqEkH z-9ZvUf2q9fs%*4^zop8}R5>nAf2m|(44ZndLHm75ol97!d2t3vXMn4-(`N-cLnwHg z1zr$mfOKXib%IuKJaxGIgCv9j(pjF=$+Uvy)G24%oET?-bgoJ2pmDxK9p1u#B!mIb zA+ga0INkQUhbrXq14#(|rSiI~g7(`&mA_-n0Z9n`rQ*+0Drmotsj`|)yfRLIsq}PJ z(0(1@F1U#*tK;;S$`m-0?KhG-zv0+g7iWNUs$3nm-wD+D8FkK%GeA0*Bz4e!r&FgJ zIwRxUI0K~f)1(gC?-uGj%Qn6s&H(AWlGH)_Jx!gr*q@ig8DQH5uf-~oOO~8U@ng5NNYX!$)s$|@%SyeC@%LYh7ocUAm4qN31nkfa`qX8r#niE`8 zmV)-y^j9{j4|l-|CiYM+{ZVYHT;!^tzt&R4d?oW(F8!tQV^?Lk6}*Wm4|4Eq&ZWOp ze(S0{Zv~&E3g5?NJe5m-seA^f=`U-9CQKJ@?++EL^j}4FvE)Ko%veA}DHr5CK6Tpn_6E zNCF9lBql)uF5re})v~w%K||eZt=i41)oQEN)}?i;+FDz;w^dWE;L-@T{+?&%IX5>E zt9{$|ecS)v^U1l-e82OZ^~}tfoO9+Gj!nu2WYaJUE-a5>T%Uw=KsCq zs^Y?F6KA~>+RXq5^5S>oQ?EE#d&cC?PAC`dK{v8R{579?nM{Y%)aLI|Q-?w5H;E|) z+FJ;V(X>fV&zvTrw7H)721y7#WW${+Y)#;zWkKlo1GeuY-8}lp=$M2NF8_EM)w7Hs z389aSY7<6i;V09GyX250gg!FboG`-WUr(cxm~W7T&__mhCX7%YH_+&>9C<(zLLXcm zvbK^W#9ke9uYD6fetrC!LAa$8NkZs>czHkW(MvX{kH6A}#E~Qkp@(d^6Gx&x20-Z7 zgBb)#2z_L9V!{aZQ9>hJW8AjgJo?D!%!Co@<5U`vF`6VH^pVlm6Go_yO*GoTYki`d zM;{qIoG?Ote4j=bj0{N#eNZ2y8zf0cQVahGKBhhpdgdU2wAHF{HZF<1n zZwi}vwVOu|*l^O%okdK2;9ru^Xc}?Sl(y3COCLqFJlW_38ePin1dOE{m$IfS!rcZ$*VKub==IfOHBcWRGefU%IdMaIx- z+LaiRkQ&GpIEOLm70AYLcW$5=zw_Nu!vkkI0VW>~@;Sr7uG<4y>E2c#*@?k4T@GJ|ia({=pQ?(T6}6?WP+lnv-O^VHch2x>@dML^J$i{Ocb`+swxj z2NyczLAkIfYGMH~3fdqK-0^UtQ3BEL>CPlhx9&V5yAkz7b`!YKs=FVYpMf!iKtoF< z;s@Cel?a+Y?B@{}scWb{;OKf_jtZ|*!c^m&NAMFUZR<>69`xOgBFG@~AowBXCxw^~ zeV2nqWcKhQ-5<+`%}2o5RODwQ?7ZiFP&6zNG5!2#S*`XM4c3sTMiaCaOTiiW-A^zuObF{v;-8jqk!Jc3E~gMw20nA;$d%fyj#E}^ohqKm=q+htiTqqTzrA$Tiv-6w3&3$ z?zG&JdOwC{r}kx)V2W8;)>7Y4Rp)OPYggUwC&Yg&?Z=k{AIqkImcl8UQnMT!JC<}| zb>)`?A59g_H7l#imabZcI%z7IF>9Jrwz{&Z%gTK1w)`cX$ML1p{2^kVmWOp+KKies z^CaD3S0*LvWC;gjc95Z zQ8{`%HMRBS%_GW})*M+~-dG7md1FQOk*NLC533rn^5A6+@e#`_SC=;~8!;w6V$Rt3 zh-G#4Bk&DuO$9>L)|5BZ)Gdc{*{V7;`1-mLAY36fLC4JjljUU%BP#0anj6b2nvbks zhJNuMLFEDRmswSHQ`RK*JU6$;GSpkesb$SwuC^f;T3u1?l-1NPZR)(H&MFLz6JQJq zndVhp=}RmRMMZ6WQxyk_${J9W)pU*af1cC>m)mdhV!2_nFIxsGwAz{`jOr^vspiz6 zDoSe0mm{CY&#JE@>L%ZGdQGK+mau?K8-}&0Y;{FrbN$Mt;9lb@c6688DyPBDD2x>X zqf$nXN3Hm6e==_*4O8ozO3*^;8(~p_10&t-<#FQDeq+AM?8}nl0l1kzhHSTzbs$v!@-mpln)c>6}uh zth%hKv9YecOC+6RWLX8tiMsPAe8!-~(TSJ3vZ8rhC!rCI8%hz){_0YN>|{$>iRw=t z;cx}XQf0_ID(hF_`gigEl2N2)Wy7k*su z2DZ*I%#_!5P9;{=t!k>OL_mK?!5wY2Q(srLbd4RT3~xp)rre+_Y~h5Xtakjkax)J} zzHFG{mz{?0maH=k*3QKL-IzkYBm*(S=-(NIIL_?HoBzs{nKr~hxXutNHq|VztE!Aw z;D%2cKCWX)jNKdznyN8#h_9-X9jEol&15u^GJRev_|5Qzq`zeQIA-e9!{b9ads|Rn zU)vO4R^J$(+_*A6ZROG`@QYUd&#-;q?E)TfCG&m6lOA~Sc^CLT&JSMTZ3tZEPLAd+ zO^aquPMmK3VNN{+)S0Sm$4a z_hVLPam-pEt~BruKD4dz1t4Yad+Z;SFYpB*0}892uBMi3+D;Tg{KM65pEVprtEqI5^^ezx?6<#O&uFx#Qf*rqVrTsg?zX^v$tbU?!hH#OvMz}_Jk#M{48^XJV zKNtQ+*e?87*aI*1nUDU$k-{S3JmJ;CZwcQJejvxAos=L@eAUM;*%_zfYy zkYRp)A$(T&8{x~sKM4OM+#~!*7{*IV#*-%;E-V!;6*dY#kKcn^9x}dXgxoigGQUqF zreP97dT?+fz~hT$d&mk7@j@~bTR|6KSdVJ5z5q<)-mq3}%MF5!d1KL}HCV`jKRgmZ<> z!fnEPg)a-=5q>O8!v}SYCr@~gaGY?8aIUaPc%|@e;ctbQpqTgu38xEdg`0%m6+S0? zU6_JMNz686Wvo$-wjP7)p~JV{t1Y!O~4yjA!^;qQeW z<_e5=sBpHhQFxW`Ug2ZHKMQj($6)vg!mkL=72YI#T==5!6JY`7CJaAaxKg-9c&+d@ zBF66T2=64KFaKQlgz#x1;(JN*E5biWzgzMLLJxBy#*-qHBa=tJw{lSt)3dc!* zwB)J6=|tprrTkA5Vme~&Jt3+l0);|^7nh+2Qa2Gl8c4vBTJ~bS99#z9!PDYN0mkc#I{?*&g+EE+te8*Y4{GAKe9#Il| zXVY+Z!urV6j@*MoyCWH)-9rOzN%q^3wX5G*zSf;M_3hx=?6<>f4}%og9S?YKduvPI z&Vc;LTBhT{uk`ISSU<9M>f52UuRJw&<4OHf+MQVTyIvq=cQ7TRy(qKSlbevPiSh79 z;OYT6VCCVDyzQhnkwtG_U+rbqJ-u71HLbm``2fZ_Rg?mI0+AH67 zS1fyH!-^p4rTFcX6|i101nX(llH!nVQ-y83qlY_aEZMQ*pA{-e3{IK(O zKfq^FfJO&Clfn2`*83Lj(VcuI7h&iGhsk&-J@cexV(+gYf=+wk#uOFGbR!BsL3`p}K^jKCiJB&Ra2Nbq%f zzl$I6lRO7iILPNoDQl6S>(wC(;3uhMuwUZ`{3LWo2E&*9BwHaEev)B`GwlYX3VssK zZ_+A}MevhQZ&##Gge!yg;wNFQqg-nOeiDwfSic$_jS2)mNeZ-Bp6YmOkS*|&FsR2> z?BFMP6sF`SIfpiGWGc0Edt5yUeiGJD<~#TyKglQXh_>Sg{3LWE4e^uM6ob(xkxlTE zSTPbk&WO2I%!ppfpkwl_=<}0=kV(79bUVD$Y15NepJhYZ?TCW>B)32p{RJbKm}(<% zqMXrzpTvs6C?|g4C$VBAIvr&JKZzAHqA#*QM@r0$p3STsB{4VpA<_ari8aoP^4S~s zNvzm6%12J%C$S>+>Fo34W4BlX7PCL>k|#R-7081H}i^ zSWDz5*+B89{q988$xo8Q>-b2&SBy9)`UG?RXpb-;P%t!lH_P-`>Hs4q_(^O+34Rh= zfCN8@&GV$_ZbtP?)({i6D7uQ`vss53F~Lt_qbiQR%53~bd7c&hA+OSlX|I~{&W)Zz z-`{0(P$ECcyA)r|F#lK-ER3GT61^T}4<<^} z8D3_*>opo7Ek6lsC$^mNf}g||$ca71$^bvfc2k64>?!(#pTx?M*vm{9{3KS+h`qu> zfS<&M&x}1t8T=$qW9C49l8v+nKZ*4p73)bE{3PaqUBS56156M6B-VdItc+J3{3Lr# z_(?I&9LP^%hmxY$iIl-lV(p79UkUh0tpD_w$ME1ManhLntk}<3jo>G-_H$!=kV<|M zRu1_|en5Zllb8pI;H6-{B0mYclHn)eaw+nYu#Xsil2R(bPm+xkJo1z5VU*w}VP`P> zBr_NX_(@2pAbt{d1$&Xmh?I1ZjL6L4B7rLizxTo**X3}^2AX6_m47||Xp9(+&9>7B z;WMBxd?ajzrZbD5z0!C$Tjc zjD3^k2S15g1X5(dLBWFGJpO-d_(}LcIreS*ke|dnT}D(~Rh9yN5-W#eKVj71CownQ z0`Qa2!AH=_w&f=ogQgHWgHeH>gd;vip4eUnJui@LuVXOQ!UBPxgvR72xsula{3N_h zke}pf<{JDYwiMH2KVW>|C%M4HH#asBNPdzw=*dqqp7!7;u^p~D#>HpkC$Vxv>|ol1 zpTx>7u@{&g_(`T9eZxc{JfeH9YsOsx-7%;6H4eTAb!$EfRzAihT-xo-A6b^>* zo6a^^2#3i4=tL&51mGv(pok@dr!ryilT0!qCSoVSzCUjZo%|$xLvY|m7_5sALR~s> z%s3r4ek)=^gf&o+pJYC)TsOk0R)RF-GU&oV``c>V-$77I9dac8$&G!8>LPW>jZm{b za}XJ+LpXm86a->*KvIWT*^B)Jxg&MRjfjlYA;-`j)FHPTITD+KjFURV#+MO$hW4Ni zv2rwaFG@k`5N63xhg{1DKppZOC_v5u>X2VCU-KCcs6&3Be63+VK^qwwR!)hzOb65$gz96~jy zLuNv-)FI^=7~d>)h|P-=pR5Svycwt#sDb%>uA5*Uy= zgi(_^#N-9kA)R@7k$K_n@}v%V143vyYzMkGBYW;T(g`}wljaxlvv}B0fJK_?2hcSL zUU8g*{)}9@=k(l#dM<%Hg*u#$d#=&d!dZ!Pa4*Jrel9b26XYAHBO{r6fzjOy`5v4H zHOwFFxEpdAA1AQq_hac zax`b2sRu+T{sKNcQ%9vzJP&2#nL4Qt*34wNgF$rYMf0P_hqK&LHxq_|K~8%5QBY!d z?Ul6T5dU_`2kkU;kXfi1J^;2eaxgsPz;Y7u6HySe@j8;xcI{Z8$aRfr+OFNKSH!^M zx-)X9&lrH{MxxR5&~ERtk0#qsz_mDl31Y6C*d<Jn1GxQ&`*i@x6mCDi$EOd{~@K=Kl$;fiE-JTuNl`-`~Q~T=-#iD1j!fa{^pl4n9uALQ#UX z;QN!#!$l|@xVo?^C6t(WP9*RZg6A|hw9&!PT$Wne#sEBA^W4tH%BR8R2pDA{+(~Ov z5i}40!7UEDk|ihLp-Wi}eO#B8IAw1`1vm~A;l#pE0#DCrXlSEjt`(Zw=vZQfmNq&X ztZ-%<9UE|>t_Yi~zM+i{-ct}Qfv4x3*3d@BwN_|uqvIAUw6xK|n=H)EY@_1=oTy;J zqc~0Q_u=4)XbB%1{intYl^qj^eZFFQ>p|Xt*3DrjEYkg|l=!jckRvR4> z<{Dv?^;ytHhlGVj;G6{MEN&}>gN!w(2EtOKZwR*0QE7!p8y$^S$Y`UZ*$SC$bgZ{R zZW|pE@)AuVfVg#_sQyLE1!utJfwWIP=~KY36umKnRyhOBrJHVQrZKaP4z?j=Goy`; zYAZzA=xDJ*u#Jw(aH6dewpe{;BK<@&>&%6#93hZtQUSEBV9++gKoKI~={ZeHk}}j( zX)-j|`c#{SWpme5YjU^5`ZSnUX0zJVY_iIhhS*w6le775I@9F)V)$S^HNmz&B*_b( zW@@ylp^c6_D>S#!G1LkzZFC%Bg)`gem|%rkb43?JaGetgwMM@>*hYuFZmT0n*KKu% z>C0U@_O&KVGuk;Ew^^a3jgIeFp}LI@eg}rZpf*w0rrRQA=mY-8o^0*N3$G7>g}{RD zIYed|?&FBe8TG_7ai%#9nI8s+eK2QO-!{tY<Hjx>GzS++x+?7n- z9CldK;06uaB~EkE;c^eh&w4tX1%z{PqG;>d=(rLm^xFXU7-uQrUYux~>)Pn}nbotf z0ptR`iI8EO^9Yl0Vjyta7Qk_e(U%gI8hxXi=wqlSzlVjKMrU+k;#viq(dJTJV?xg- zJZeHWxrr;#ml?pxf!RNvgi-R5EPI%ucuoO=1l)a?AFz|a7N`3;OJbag!xuL+)-T5v z2XU_CX^IbRnJ|9X;xD*#9PeO8)M1Un2!3w7xTdb6c2#B7;+5qU)!bL%eCoZnk9fOYl#o&^2b&iesj{i>`J_ARKIoEZ= zSjwI|D&%?j@ldW;84tN5us(f2PAD}ehfCA*+;BV|KGsWJ*0X0`C=-j#-OvGEYCIka zEsTR@ArN%KMWGO}S14*kH8)-#kzJFMriQ4s0*QP0WOJZTZ^gOgn{*& z>Gzy2DR=ctG!Sr5v^()abZFOYm{G_5Y^JPQwycV4(z*~el-1XjRkh%Qf3s2ut2mPv zaW;;dz%6^1*Ok|r1!Y~92!R@XSyRngE;GU!QLH<&%NCc`G?!L!-DZ_tI;xeMTzFKD zb!;n_He#`wR*6nMeDU#3FkM_xTaI{e`e!5mr`Dbwg*wuVy zEi4v5aP=!vw3Gq<)j`Q>TAVU0n{KLtZ`I1G#^qIY6>DtPu;|)4))?jm+)I$tI#jP& z?#|V+Sd6>6qDl4qId}V!-EKN%Wp=6h|DTqnqvf;CP;>qY=9O65>Nixobj~yiQ{m_n zWn2Mo+B0j~4}`VP=uD%W%eAWzDi0 z4uY#2Yp_baVF7$9YpbS|f{no`vlq{40EfpiEsA7?nz-q}a(#4vj)zWNed9{7A#n5~ z>jAuQ`Ih3s)YdP>V3|B>u+^9~z=@I9EdI5NH2*aVearmiyQ~kh{8NKcm+^?T+=Ru& zRa^+>tgfnAUfqmwv(9iAtVRLt>Uw_>SQ0USUxA7GvyIEvT4hsxSv7`4ECla5_TvJx zkf)jz%H%~!a2hO4?x|m3jqInF#o|uWyru!$yrC7~+H3tgvqZuKQ?DGd zc?YRuX3OmIZF9?@(9}>>!4_DlCAxO&I(q{hgCV@BtfB>tsi}%fzImU~fbN?kUih7= ziuP#}FesQ>szZ}Rv5*kc_8WJ?G1*)%=l^KYDxWnbuUX|kv;M(I(k&!{vLVoK_`?G|X2wR2U6y7cTneYYS8$x~?&3IzMgM^0) zi-k?X^}??SZxH@g*e*;(cVxVI!Xd)(!f8UjuBF{3VVm$i;p0Mns7JfEgdYhbc$rE4 z6yZE!x$rdMIl|4tuM58|{IT#U;VZ)3LKh94>0}892uBMi3+D;Tg^j}VgqI6%5KhPY zPR4t@utL}*JWsewc$@G?!e0nK5~iXrGQQrzVZw>R8Nx-v8sQq@MZ)dETZH6#XS|OK zUlMYALFzvdX5yO-$^(Qeg=Y!x68=>9nvk0wFx*kXIl=|P<-(Q1CgB?4dg0fE_X(d6 zz9f8G_*Y>Mj7?0ppKyfmDBO1;Q(YHweEk{Hc)J7%_eqV;?a~I6ydBI9WJP zSS>t5cpedL@j~HOiKx44gx3mhA|jpdNH*&^VfRDn&ALv=kIMg-(*H*C?}V>O|BmE6 zLdMN>!@^!dZm2^2fkd3cB^L_0MFagO3+D*u3l|bmzO#kb2=5ZUM8x@u@K3^bh5Lk` z2-Bk0o_ka>91q5iVZ$JbW03b%>IVsj3bA~{=*@i!{w0!U3i+is!|{DCu~yh1#Mcu> ze}?c};RfN?gjPHC23(fYN(EIDzj*)(@ zkgrG>?qp$^uv*ABS@drbt`@Ern)@C6`5`myHVe&t4>I4JP;c&kz;8W_||u4$0RDZxDV%c!%(N!XFCn7yeB6xbPX_ z^TL;fuM4@Ng!%fjaIf%h!Z7D+aHk2)JP>kE$p9ySIhcPxfoSYey#~#E9`^Xx$*lj* zlin$8TC=jbd?^qQM+{c`ElaIQ&W)&O!w&QM%Oo={CddhhY?LXsmHMbohP^kdx!Pb-Zo= zEC;5&iTEyr+YbY$b3fukQ4)vmcOEp!@!gvgAE$7B{{9M9q7SnjCmAN1pShtRis{h&V}4d?TQ5H}bGi2B)oVDx~kk2x8;gTd(5 zrji3UIhQ~01UAii*NJQ>d7>k@$=lRg;_g`7F(I?GV}i4|BW2Xni=3S&cTAYOpku-k zCo458KdU(Ji8uM~c3`%a@V-l--e(b?;Z)p4Ivi>af-6yS0C7@Zh37yVqxKeWJtJ^h8JGj=tL*gy~)4 zv=`xO^x68L(|fDu=52k=xi*ru^}yDCTio_QUtF2AdHtVwGiU76PS34QL2PrcE!l{p zb{DSB13g<&lZWJ22e;<7dRweJv^A$SL+zG)S)*i~pDb8s30$VbRIwr>Fb)-8B zVRcjQ%;LkbIpJjJoE^}jO{B-eTihMjw}+#2!)nPb?V+^r)feU8*5}rC&%3QXoN;Gy z@S3!CH!z{kE$wdFCHun5z3orD8D4(wK6hHm_E6jG-Wl7|u2{b>W%+r~oY_0n7QXzv zeJRttR$i@3_Ib;LtuykYS0AvA*WspiFXQ5Uq2-tD3r)LhpHuL}n~`Z3?{lW5ZA;zZ z?ws@1l4y9_@%he9wWjj#X zd+WLni*E1N+IL6h)-6u(;J#aq{;=2WFX7szVpaP~9W9%%M!qlB$6qr4&2W7Fo59=W zzZp35vb;dY!s__GQ#<x$&3SmQNf)jbp+6ICM@A-a6p!Wp8im8jsn-^x!c261>0t#SDmr&D?%Cx0-F}0w_V$(rVo1Qv?tz7o5p_1YmCvLphs)^4)+?ifCc&K#S5`A zB|*vQNMx8>}#qd-550(~(GvyueLuXlS8Jx+ zSr{{V?l{1V16N`ksJvry$-5=NR`mFy`4|V-yXSKZxW?Un0>%W40u90Tw8SWY{=!ip zegb;bWhHN797rn(6mQ8af&LWeBb&2If;-^5grfjjbQ)qTx}iNKdRm|B`-HBJ?BG~{ z-k)*FzR(F57iabfZ;!SI1GlvYqtTtX9w%VbUyiFWEp_`Z@-w%mUCHZoW`5*yj0HP+ zmCnOmAq)LKr6AfitoRa)73}k9C(}|e9%S#tNU%I@Ti}|@_5}+rhAqZ{w8*yL4vq&s zwxN%|JOjB+&wQ|tyL}2ue6kr2Fp@oRWHH8xQMs)-+g4&^<5+M&>p5mDsK5Q;lHNP| zZtscFp!b$M^!~gp`P;GOb8&1-zwNz%y|(l*qd`xM21nk0U~B&!Ic79?ucSZ5gPhxU zm)Ox@{b!E`eca;xjRp~n1{e_n$>Tv~@z>ik+|KdfW{d}i7k|<5;J&8{%y`i7{b0%Z zmZjC#UDTt*9Xep+(2~%TO})K-uFgB5w!O^_n(0| zvzdFIhzB-D>mB;|XEt&@0y$$`cL zKY2NvQhIp|I4GBoB||@;g8!I$hva;PZa(}22?ZyP9{&OLCghw4H`YN087vb&Af)&N zs&Eh=oH{Av5!m(8QxMr9QRdeB6@EZSL3f1z`;w62dI*M)f-k|+NRRnhk8#ls-N+G(vd9Vc`1#2<$E&Py>VkqK^R^SJO6m%mE5mML`gVCQNn;@jHVkF8X zg(+ilt(Xyg84-h!!iqj21;5?1OBa6v?{q%4JPImPHl+OrL_tD|XP}D~;Rl2iHUcNQ zj`1BXF&O2OSP)Y9iEl$$KuF;yzMBO)QetLw9kX_n#N6l}6cL0J);KRZhY1x)>>GWK zVJAxjAqD@(iMS~&VN%uNMSP?jK0Ktm#3a*d?Qh241^S{ED=&L z;&fhCo=PDc+ztVR6swUn5>oJ4VAQOLK0V7k7eqpTW42fO385Xc)n&ebypoWj2zeAC zg#w6>LKzbwg_R;vzH|m5#Z&+ZDNbj7-Xk$VNYRR1U?FLA2957kE6$6)O7X!o))EOR z&ZYR%e!oZd0wAOq!0Y%(zcf@T7NM)|N3gcLK4m>{IE2_*(F=B#{!bVjb<ma1~i77%b_5}SwNMYqjY%>!EA%&GQVvAS^5K`Fi znXxEk5K`<*Wkz#jqyr)$h4mj5yPquvgcMn6^dA@dn3WGg3hO^1b`jGDAw_}lpA`F; z>4T8M4kbk~jyoizu=d37B;SYtvjQ(terZZ#sV83keW%TEF5f=$5oQSTL&V8T7nBw!MzQ*kddZ2q|bxLW-++4M0f2 z+XM+IqD&fu6t)!8W88I@gcO`)1PbO_f(Z~({0w>$Qt(X*2`OxctB!q}>4A{K$_=r8 z2uDH+E4Rd+V0s{=I2Gx87|~;#AEaCw$UMU+KuBRYh(Jie9C#$8*hmWyQZNcbNO3FE z1R;f0fRLhwoe6{#Rslka}$9}-efV4ahKgoG3i8ySQY926;-s6a@;i^Gm2*%DIh zgCd`!4hboEar19vU4f8-soM0@(Njzy5K{2l3lLIJ)z{@PU|KgCSPbrPkR83R%g*Qb zg~>+GPZ-kK22X^;#0CC{jVu8ODLC?hkYYI#1|db25y4qz2#hcvL$Ll|MHWNuFk~rm zZXkR+Vma_4*sY5%LX|pkoQ@m+3nE0k--C+06z9PT3+Z2mUFz4|oS(ra^dsmZGmy*F z%iWxpp$P}63I`uEzYjvwJ2SO9lD+~@X=4W?rqmUY1Q`UG)>BW7lol2n{Y`?^TaH;o*L^+qXD>;3pLV&~Jo!Iz^>WHw5WdRip(X9Nf_ z3jrBF=%#vzrpgeip*>IG>^NaFp1M z1hSa1ze4dBDw!KM)mlzO^n5>FPzQ2_bgScg>kEwz|)g20r^^^Gj{pZ9fW!&Z%09su{)5ub0DuaI%8Kr-Aj;vMO{U`F&si=47Hqt6G~%w z2$e@bahO%2a2bKoR8~N7GL=oNnT)`ADtZ6fVU;HM5mbH`3XXZOG{K9gd=iSEQHk$z z-5$2o{C9}>k%-ec264IQc1~_*FCXd4dRH}IOf52Hse@> zIHER=X2|T$1#1vT)W&fIWbz~xtU*js8`G_j*(nYhifVBWuo3~R>PN^lNoqnJddRzQ9&9?( zRi-b&jq7}s=}N=dm98>9>2a7nWP&ph(~(l}@s5XccnuRV{pc`=V~vV&m~M0`#N||> z8(n33(KjJ&rv|;~D$|LE;k8l$&f)At+e{xSgLu4AA@XgeF?}E6?NqS~Z8KMrpC7$! zRJ1Y;Y5_*8={Se818p;x_}dV_VN|p--DeL(a@r3!-DjJ*fCu9Lp?sXs(av<9sgRGh zI+SRe={u)FuAt8Joo%M;+zk0ft7BNxbMA+HpVcv}={UcI{490sI6F*9d*fYDPn^Tq zZ+4iHPJ%cA=OOGiJJf3qVXxVtPBWaHrq$LI3{Pfw_L)`_{#=M>8x_L0n()^_{JK#g zmR1wXJrM82Il^?9ohGu^ApaU?q3JI>P0&KqU3QwPEHu4kr>UST+Odq#ZLmJxd+t2mhF8O5 zoa;V>k(#Fq9;7e%Y*3TE63jQCiy>!AOe8u9_Lw|lk$!mk5whql)*Xp`MA{=UKRG-m zZDi14y!}KVW8ytJgX};3gRU1nDxI7_ov|M{6x=|4(aqz=fy*`^L0^Ng-RNruimJxM zDhiqc(b6RA1|{ooi%J%`RRF1MqBavVa(pVAWE~o9A{*cc>Xr@cXyfziB!UlD8n902 z4o=pg%O{J>#t0>u9HuZ?hYo_Ix|8mVN+#VIokY4b1|ImFel+TTthKpfN(QBIT`72w z9{LOq+_Ny%wG=$K`O!Uy$UTBQ=d3$iIyhUT2lStFpo=;niy%xl&P9YByvI5x5%{m8 z>ntL?Zk#6*`tUaDoI*H?z13MrIMX;!A)IZTClmNT8)6_ZUnK0Ao8XH;V&*_=gAqUU zHAbGZ`I2?kC;2zmSd|iH;so8!nQe41-mtTIL3mu>t}z=j2^ioYxfi%j2n>S62z-!( z#CEQuqXk(EIGd*vZ2?LNwl+7jV$1jE; z;6(liHmjusMvUCeB|czN+qsSoex3u?4uVQBtFr|25z-t1*f4TN6>vtiF(fY~-PVG! zP{soToW7l(G_G+3e!S$!==JM5uRR~+n}b1Vem3Gs0YlE_x#59r6qw~yDMoi*BGgjC zK9$y^2ep8O#}AR7P$h-ImF^m5Z2#miCK{;L4NMe@sn}u}2U_6Yuj3RZ+v4=?QbVk% zW%jCGzm5)m^NHp}U>h-2!Y2N@(JvyfuX@g!PI461k8N_v*D}#q_H)sg22$psY6O4N z*@)+2oJgKu#BMXrd4yYVW`Nmf^Rs7%&u|8Y`?gWT|DCd(%`aG8r=N}2CIK^(Lb0|+jytdGb2~ktciN=kX6UU$6dIu*`CGUVKQkSW&Zz&1)O7qi(+1}T`a z4p9)4lNv_IIz+*UNo+nr!M7!1W!Q^x{rSij!zAGioBu~hmd$dkiZ_yiDFjKHS}Fsb!TaBZRC z9Rjz*P9<)kP``i^ylR9XED(i8A-0n{Ukrt0uO<3Xj(9UtPF1667cCd?vbI1T8}1J85@o{fa5VO{iq z4yvZwuu)U>G)^R38BWquXX8Iv(W0E<$pd=9pzC`0^-maWKoFjW;EWDlO9+*1bnucu zsBWW!l@Fn|jSdM7MqsVOr@4)#;0a-g5!e(URJPH+3&0h zMx950I8iACn`1Mt;!;l}w{smGn{dK}z?&VXSVZO>>H0;W+K(2N@JhpP(iCeKw5AAj zkfa|%*HOU_Zn0Z%-t|rJ&%XULVotG$Ke4H8TSv#!IFVI?N-(Rl1c|#)_bC=be$gow zlhhQeFM234x@#RB6HFz2YKnC_%o9^A3Jm{urdTvdnqv7O{_Yej5ynoj{4oFI6pI;6 zOtF${h&8puUe#Ue=vZcoKA*rgVya|49KSXCMT8EcPnu#O4jgQBOvk^LiN>;@i$;47 zRgZfpPCoI#J%zvskmjGx=CY&>IMIYTGq}b$=Mln4KGSqXPKWHIsB?PDm|bTtesfK% z#}gFmyJs^-JJCp<3P5QO-eJCn6SEk?9-Npv{psv5W)Ye@^*6DW5*RDIF|DG>z_z0h zkInL8!b3Qbd&JT02sm#+lW8JaKsX8~3jM~}bj&sSQbN}RK#7PL?Zoq>JXC^hrAad; zJ6~et%sFO5>(_-($L)pDa=L{&W)!vpP9*%y0*|Lf6?4HQ&S8Z8k&|3)6izMBU>!KQ$Yo(&p|{vmqwTB6Xb&QNz0EHXEYq zQJmdpL)6*$zwm5mJ%aEwlL2|>#u&=5nPZ@>TPjUPPI7|$cbjq`XyfpN|y*w~II@Kq_&ATT40 zcwQSE<~Rhu%(k7%8HXtwU7YdpV5sDSW#_R!|6hUe!*hls$}ibX>ua0hSfUrNTDi2U zva+gj@r3x8QKKh}IBndBmE|ky8yEi@v71&T5q+IDb~I>YF!+^KRxK+hg_5CHDy(Kp zv1Dh>5YSCXBxPL*6KKJFgn-baoq*x2PR1+Co2#M3TS~55l*E?bNpgCH3#!bVoLumk z=7P{P%?-I>Z>2j4G?HF!VJ;{#U9g$D-ik>e)9ghC%>g;N(1BaCb;ba(Pp-9;jJ*sa zW8x<-lutJ(BM&9UtypNKvA%RP{R%>HYht8A>*uw|*7yy!6r1@rsqjECZW@x&v6g>w ze5kjL#d4K~Ok`uaMoj~6b-as`B%y}y(zW^sKw{wETCu@Jrjhc#$aIF=GbfSOO&8L zH9>M|WqwRx`=bj4rcwHW=(a1Rs$mE4x1vV%&;xD-{~f zWQ(KM63zagPw8w6Mz1RJpT;;~=L2_IhlPMutaM`p_ z+5EM^d}EM}KsPEhhA>E_U&Su#c@2JYrd(aaq05*cUaH9-yMQ-C_iK+s=O?d6bO-xlx?Juq3K3i=|^S;K5u{x*Vp=v zunCQ^$}v_t*h;2OMuw)CSTN|>=+G(6RrH$U*2|R5tMmQ)`Tk3Ne`|lBYI=;#K5k@g z$Xruzg|59fUm?7QoOo!4Np^)w6qoHvzv4~(bY5p&0+TbeUwcu<*g#2gcYl)z`i98} zx`|2i?sb!FV~ksc$-<;ifro)R^jxR_y)tfpVIBx$+tR`iN6kQ(mH|s-9q`)L#jVH##EQFK+RB9Pudk>^3fs>?V(voTIUX*B7+YX1EOd%I-#Ha8JG$WZ6_fkDg7J zm%;41L(EUeczQK9%UCgFP0%e_Wv&^=jpd>8S!?oesP*<570$y=&jdiDX1GI5w{bCx zFcN=|27%*(>-8{h6Z=qOVJ9;~LOqQ4a{s0?(kjAv#whXQ)%pgOq?#V4#5uB0-1z8Y zhWLNTo1w%@J{t3{)c7P!1uLp-RyWp8F-BWuKVLGHDHBfIG!rw?e8$wR zr!^XHqX1VqGvZ-rvXd+fO(rjWt(=(0$xIWWq1M+V|5@|6^u#>Q#=OdQWY^2{r!)1Y zjSSHY!nO>f8W|ePT#YfqjXT5MoRuRsIOFSKqG#^Y!>!q%&{PH*VDH+#^{Tin??79R z%KsrMc1@uztv4VZG8bcvJWlo}oiTsLahfgc=g!&?ld1mBSsUusPR4lauoE^8UddB8 zb!;%m)5GiICtBI1wcD0V3v-E#sL7ih82rZXPt$was^#6(RmGYb;~?ly(gxE#!dBYB z`=6wlOsP3}wWb~hYo^<6!ZuFTcdDOnTVxe4k-hyDA)&Kn(zdKQDLAqTgYG(R^1UO7%qGrUuKSPV#`PzSD zqGoQjUh_gGg_}l~iCUq(bz&k)-*MK@TdPzKqSE9oY4(OeolVG}bNSOPJTqtf7}1k_ z*{Hq5^bN1e8K34xJ(Z}pjBU{K@SmRzX(owX=VY1woD8#9lT&*~@-SmkAT~{Z0%!`1 z`>M4xw@H5FEwE{L7+3AA>NHtZn=O&X|yya-&W(Q?fN}YQxqvV^p1+xG?oMrhV<~uWurvVp@h{ws3u| z(TIfabmQC0jM83bAoIUL*t-W)su?Elk6=ortk_B0J^P!q%?u6Hqz(T)W71}SdwDN7 zlW<%2zK-Z{U;aJkZ|F-#QD_FV|4+@$?CjM2`*Slhx$|nwec|uU%?{Gs4F7T2aq|Cu zZZ<094(&cOd&0p5&B1gGjXR9HFm7s?=ZCQ03c+{?AYWrtYsy#-T-Nd9K)R1zDXKua&m9-IL&|C6$3khuFSbw0no3)|FZVyerV9Vm{wKUt z*bSo5>;!}jF-&Vi`>HtAT#CwY-`-v(1q$ zo87mkEU^QHwmm{=*OaSKp;g))P+DwvE34KpWP2QTF)8B!Wm@vz-Ooh3m$WEiZClc0 zwyQt{*a4=oV!ykVeBNFq4b50^Wcy21Ikw&KHzWE7HY_QtIK3JB=AikMx2&$jMj5r^ z$CaDSqY|5xpe?9de&$vsT{k81N9|8-LsFKs_sAFBYvj`#i>%S0X7?9q(HQV=v9rj( zU^9{KHvrQU|Fs*8{9kP;V!mHX-cy9HnEivVj;BNiou7I^WJAh@;fk z!cG&fYyFfCpVK&N_{G|>*bTH%nr>9ri?&MQ90(PnW&P|f<5c}(g`@2i#B6;p}5-0Yu zpI7w9SCy=F?q`BOCxCT?TuMlUslnbvROMhI3cd>!{yhgZDc$M%*;rE3P37-|dDm47) zh|fj$WO`Y`F~TC@9N{U#l|p`|#c+nl9C(-HUkF2J+w{*BlD3Gl;SC4Qm2CLIA=gPh zOL({NXTm=SKM<0@i}4wrZXgyP8hNzvR3VqV((Yp64&g1rdxVb)eRoXFg|W%dNJWp;Y8s~;g!N0g|7(T z5oX{^ZpO1vX!bpU+#-3M@O!o!6#g(nG5 z6`n1;kcc|}s_<(>+)}p7-`^MI8`9q<{XLR@Bz#c%UrK&P_=5DWOMXKLx<-@E$HEK@ z#7s9+I6yd9I7c{NSRo`s0K=^o`unYz{Z*jtu>^2Fn zkp5cX?ZSJ7KO@5aap5!4zevPb_Iu%L@_$?Y9g;s5y0~{UzZpctmnrNieO&S&;V|jP zNuD4)MtH37B;hH-I$@)5yYOn^t-?EmF1%iNv+yqAy~4+ZPYPcazAk)E_!nUq*NEjw z6OI)gCM*%o6fP2eMOZ6r5UwKPTrc^2;YHG4A^f`VTf)1D$j80HA4~s)@Ylls6241> z{rkdw(tDta;66zy!gM0+`U?jNhY%5FjO6jcBZvq;N4QYfM1=inA*Op~+{SdmAciG_ zs8)kqIK*+iuW+z%m~f7e3oU4OlF-asAy-MR5jF^$g=YxOd=~Z_BwsAtEWARvQ@Bfb zlkl6u?+EV{-Y5LA@Oj~j!dHcV5Rx#8<=`rMVnk@>!H~_qOTgaJlS_(rM+%FD(}i<{ z^Mzd2O8X^3v%eDLTFGXACCIBKlb4G2WMMW zeo3%1`y~PQO3#HGOqVM^h+O?a%n`{6B#3OC{F}n}lZw*9p0(f$4EA1CczZ#H)n6gx3qdDZE|yu#n3x818A|b3(HZ z67;W0Hp@;R4cjp62S^?(JWOc*Pl11h;o&j`3) z{^twt5R$i!`TwEtejzD+s5ko;0e>U;cfvmj-xYo=VJ~4HAqn5; zKSnrFc%+a7Z}d0&YyuZcULqvf8~s~^>x5?iO}I(?Mt?F;63zdiz&j-WK=?x;`QK>w zYhk?7XN;RN9%A^G;`PcBj7DZ-_~Q-$?Ha`Dmb3gJ%SF5ykW zZwkLByh~`F4#SzHp!L6Jdn^m%~3pNESfKV}<7V0%Wt# zD)1QTj}?{*PY`}ZST3v)t`wdwTq`_BX!dDE{Fh4JEF=RV^K-NC4&nENq#dOHlS1Nmxk#BZM=B#|g<^NdJ1_*}`*$wlHtws5TJPu0yNJ-faJHN|I5NZ3fqMr2tN{n z%fQ$Ng(Smd_Bn+bHexga-->gu{h}!b61JnCC-~TNKYf zv_EQMZ`A$16E6I0@8mbbW;@k{X}8zTb`RFds->%zZ<%0u?ehGSW&-nC6-YqN3^W5d?kz~m(DIMZ*Fd^!KZhK z_6r~Ru*4%C^ZuHF#_=cVz-2SX0Q}Mpj}y$%-Hv`dhTvpd_&mEqVADNapH2W?rd<(_ z#hGk32@Q_l3HXQaJiVLUEM$UPO!$Xy*9ZlhZ;?E9mD;w)_Qy6)JLdm#oPL?$bT&e{ z4(-rCe7{XlB*%9b;(GvdUdG3G{P=dk?T3NWNkPT)9kYMPb92BG~WnD*f3 z$HzKKwu>VNLwwI9yOD>DnP|3R)z9bc-8y0PsIlXX?dR{^x?qAy5Q{W;48=arcJJ1& zMXtExN6z^rS(`=`dz;Vi?F`sDJLjq$C3lx(Z&_Y)P;q+6}_7-&T+_E=s&oz4ob{x|Y{Oa#uxwvC=eBi!l$CQ2j z|JE5I`c^1<+*^6a6?FvL5&Gq8_7?n&=hJ)p@A>B5?2dNCzqn%nLZ<(1%D((P!;7Z8 z)qhHHNAO^`eR5!N$3XZ*;FBjG?ow9*-+9H?Kb5m1IDF1q7kfo}?pgo)j+Sp@H^WVV zErFe1k8E_XH*H{xld;L$cEFY$&Wlc{q{r5*ZP~4vn=hR*^!^?tPrR8r)@lE-8^$h( z(JN9m-{hokiEIjO4Yx*iJk#OqO2dw;xi7=DDYX^9>oZz=m2AsP+0nCPd)}DpLr^2R z?>)UYcTceTsSf9X%lGzu-`%=(@1T!^tvmM?eEcwUZtGFS&+Hxa-mrb%$20cjyyv}@ z?oEBG@6;#Z=Pk*oo>2VTy}9pS3yW9x4%#z(U*P?j`?B{0-bxQlc`J9y@FhnU58dbO znVtxlJvFc+eTmn4WpUHAiN*K65Z;l#J=B_39NyAndm8o-Oxtq6_Ecc%mdK9an8=nC z{HAP)ntcUBTem!uxg)S8I6S@e=nv~|&$%Y6wNLe;>bC0Nq9n0*H}B2;VAI~gAM{&7 z*OPk(zq@eB(|cokp4ywc`_;Vz-rct3+PwqzxJUhFiMKn`d*!K~W(UAtC0VU6{t>gv zPq;Ve|7JUzf_66W3%4`0u@1B~)6S-#oekV?JDY-bHt;{Voy|Zy8@rlXw=O@#cvYG-I+XlH0`f2W=OGkZ?1pW=`CL3arT{|tW2bqj{dI57FZ zo|7AJPxA(2#u7~IIr$bO?>yXSf`{edE(I>q(0T;)euPmsII;Iqqe|feYi}jo!P$AM zs0xNIrHxB`(-46$L)NxppS+;b9lBFE$VrI7ZV}mIzdrqcYmwGWmM5o{pxC+RB)67J z?c8(nZ!A#fo|7LkYn^*eW;1N(o|6YMq0T)gpJdoi?KzpMJtz4U-~VIpJ>a9LzQ6yS z%x=O$f}u$jLQRMSLJ<%_iinL~1ObU@Ks3!HRFNivSV0k_DnVR1&c5$G_nb5L-nnyUckXN^7=GsDdiH_mnUjyP z*z?RuKR!VR|L&QS>8RQQD|l%o^UO)p-{EIYvb%!eXHN1HUoi5SlfjBVbFu}hRw<}w zPPSqr!_S=LbLoO*o;k^9=Zz1BpE((PvO1qmhR2rinUldy?nvM>CxcHZSE=e)R`cng zIe_uZ$wF@G8D*VkP6nT?w%i1YuZj=-zF_#7lTq9?;b%@RW@-4DlOwqw!_S;dV&{gR zIr$aGK;$zggS)gL=b4kiH`M^=nUle{ROhZ$`DH5@e&*y`?2pK2P6q#@P`#`6=S~kl zbMh0`IsDAYw^_;XGbb}>9De5HO>9y4nUjBVL;q9HoV*pDN&etvQI*UyCnqtk=b4ih zd)@QQ$wMsnJah6aHrVsb$(9^yo@Y+-uH~TTnUkNfqMm0?PGsKm%*pTB`JQJ^-o)*D zo;lfoo#c7utwJu^cQt+-FSsYV#6C(DTg6y6ibTb20;i43C-hRbhgU zCDbzm>%JA785J`M-}Gwlp{eJYlcSiwCj89FwQP{*nUhsnYtJ($d4(nDdFEtwR?YLw zN&X5U=y~Sk6>O#FnUmwWJsp!b=R z3%O12GbefJFz9{eWI9{nedgpyx_F;C`7JH}d(WH z;PfclJadw>PSAbk5m!RfzJ^5HxyOaBj$*9`=lfiapH*eSGT@Ut|;b%_r z$;@__@G~bDaKmT0@nUPYrhQj8k7rJ9r$M)fXHN2$8`f|5Q*YRoZ#>2vUsh~${FZ`` z2ep2;&11g$LfZ$@gmt$5u&eJ!W-5eNAe&r-?z8^1%_H*GK(UNU*2X&SSRR0a_Z~JK z?6ac$r@Vzrg&na)ell)~$BRYzt5dZJ*}JJ4N>weY2BSv&MALK_RdtLbYTOLc^c*~4 z&US*a755k&9{*d_JANX+E~%_n*2SEgB3R@1km&gFhMS_t&G2cQ3tfba;NB z-`|ir-jT$+lbYf=e13lusxCtIOseo8KEJ;?ReU-*pUm9sC%EH4Fb`>~hTc6+_l3i0%i5<}JX}YQe zL)gwAD{toy@=khFiG8s65R$mVt;AvEesug;3Hk+n`&s$+{$QO`;Kv@Qgu%tzVN3-Y zBGCYnNHeqX4#>5G;3<0y!XE?L=KXA>tPcKQwj1aISe*wkfzpt;6p~B_nwnrG&=f%s ztP3_xy=~r+@mZbx!ABWvBy#g%H4oCFA2O?u;GHwcbf9U{IJ`dw%_9&5+lHD^Z=3f% zNLgL{!4nMjIf{0`>Saia{~*K1aefF%rUOlreuDNeG(SSr$JE=tV^Iinwm;Y@9=_bs zF}S85fF!cS?C1u_)#H_ZXOz(|=!@qd?CuZpu6xtR?O>4#Fp{QX{vhwyHx>987QETURDgHY9EK#)%xt`JECv)r zEg4}p&iBy}>s){EHaAcsSe*tjfzCj}JSWsOHNklE&G`_G7KX4*pv#c5&i4oRGZ;rp z8mumbn9)*#L=hyJ4m35RWj-|XAgUSlwkgd*%IfEDkb-3!(?tHJXa&U7>@g(xqoQOw z(A3my2Q)835UdV{1@%$peLPYK7MRLl9Z(}AW*J)w=o!cJuf zf^i&EZ=3gAq^yDd;42KqaoiYIjUZ+mcSNECB$*C0HRJdqXfA*t7$+?1ZS!7;lr_X( zIR>j(W&~UYt1-0}^pTOch?z-}E9 zYaz+5X;NL7@YhSc^9PklM3y0J^FA3V>k@zLT?}>}ir#|NE=Y?m$b5msXOLt%&@^c% zw7)}h45D#Oz3m&p@tNrlzVEh*HwMK)5?Nwe)C{>M5FMfP3z|o$SXusH!3-0{PphM3$KDXoVc_5>j{2FKB)yYvuccDYf9o?&t-J9uU)t5lCDN zN#w6-O$+$*s9cD;gI73gAK&>w%PQ~(r@Dczfz>RC3B+GfErBGvrY6`%Xn6k+f^qya zgl*neF<24CKZ9}n^RA*7AZGmUMS?%CN~Qx%&GS?X=`z78pCvOk#4VEHKO39Igq z7U{@bjKok#G974|bQQE$K$8POFdmuI+va^eQr0Yg<+~V+J8dSc%;S1#!&0;3RzSPV z@#m3Ay=~q%(toZ$_Ivur_P~4vtA`-w$b1=zZIEO-(9|56A42m!1eM{DNxf~}A4ST# z&L4YLZTR!Z{1H~)L(GvGz=UfG3dD@( zfk^a+B);X2=gW~B4^j6#XM*s38^l`Vue_Ck*gZGEiuXMwyQQXk?uCYTJ;9&dLoeIB z@1Xxue{5VG__KTXTd-#!rhDE-;!Q|09cXI0=Syflhp2m~$0shl?}S*({jnn%jNQW< zrugt~(>+}IuL?e)*o2SKgi-7^Y_OCX6~yWKMZ zIsRBohi#F?AY9J24*KIiXAmB?i(#<{Vve>ANbvrrM4Fi+?FHnvKoEpOupNTniJT0w z#UI-MYucuN_rT&^`mx0H?IGlN2bBEy#|CU)D*d+Ngy8x`VGib>p-5zj@vDnmZEBq% z-`n`{onLjW7yPk{TwmTF)e4gAmKy(ap*bh)&!^HvnMc%&p#NL`xOZLuk+2#;f7-Cr z_!mHv7xt$frwqKC=l{IpkE>ZvZJqTUC$ft2;WKW-y~ahf{>t8XD@nv23z z&fBw+=|EF6&DDmc7E7ExNxkhmpL=AVKkiGnRjud;No0v>QBUN$NBRYQm(g#(KdvEe zhA|^xI4p+Ik0r)07rDzFKlTK-cZzQ^{XX-@WzvtmFdG&#A*L7ZKw>c@k!Gd`HX^qH zf*#;WlfgyYg*t{S7alIPA z_kO5*!lFB*#R_CDMq(%=k!DFxLX(Hw6%f>jGte9avCaE+NLfGo<8NUg&OozaH4|cH zpe0D$4oRj1P0b9n0h;v?1mgrvJw7Ag{YHp^0=gK-9W0ajZeW(L}W#JiAW*VN2F z-$L^ZM5BcvY~Ouso)w6ziEr^{ulsQR_zPBvEHQh%7Bn>=>f<|%AK#a;648O+Ao!ln zJ~n-u4AUe?vTM?ceXEVGqKj`UHyRs=o9}M4JM6nb5?Nw4IuyCV5Nwpk3H@Ts`x-_# zB@nlVzC2DYht+t9IZkFGF&&aj2b!AWOM$|hmqNW#AZmcYnt>LwC_T*8-idpdO9I+21lUv40dWDu8_gnqv#u0eFbUJ0-3*% z_!E-snkMytwgygT)gTCFPUi@L(>dNZLae%h_{|K)(UQayAB7*ZyCK1IbFyn{M$2Gm z20{>wqlF=GI>-B?3|21?U%3(dIa9FEZ685Wj+f*u3Mg`U7H` zR~=`vcu2BqYMPe_O>>Bv#}Kv&^fH5`2I9YQo7WXqT_C1;gOC^iNu~o$P4mV=lLb-p zsJDGTvU!~Y!PW`zW%I6r#T1BX-U=j^K@w?Zn)e8D4?$3)Vcl`bB#LJyzVipT)}TOa zJ_C(M(Qa711xa>GlO{m>9W)2S{`B%2-vs&(4a9DA{Vkm0PSBq=EH(c1p{)zi_Nn)q z(kApD9*F(k^-qOWYe+I}SZe$)gy#IPKlOf7+Km1q@kgN>tNv-Qx|II3VX5(-0?j1H zpXUSW{Z1)T)}?{qRrKdM;bvIf2r=h`yOFpHl57IO)SMTdg62sG8pB{o(Bp~)-djPe z%L2h2Zm>6C^*Y1^`xJ@&kYv}?1Um}NuMh;|NroZ(<~^0c#s?bIY65?rWMXletjtqo zbz~YN(Fl@E2b!9bOh;%sKoE@I)Tqb9%JJR~f?$D+Ch+ISw~JtP0mOWKy9|jjkYv}? zd}Esm&18t0$q=>))RDoi2m~KuF!tFku(}CinzTUDh z1u3f_(BRJ|@aI`;7p!(d%vtL*Bo085=|EF+<~jz=5r~>eeUvFRf4jCI5V)Wz{MpPn zoK&mu#LCMVO^`@{B-4SWrkP!#=>kEpZP+~Zwt4S?lvNZ6E@rULQ8Wlv10ZJp9*aa4 zB$*C0HS_mX&`g0S81=R(?ag2l1HsSSU<+V%GsFbD2Z_5O$#kHp3HA&$PeBlj^EdUj zc|V`Qt_n0rZ3chN-*3X|4Tzb)KS$zINHQI0YUc0Xpg9UrpHUxWN-uPR1+Hc=_E}Y& zsbhJzW}h`hqA?_y4m34=)(x7oAPBayhoiSmX@3Tr5oqulgKb99U|0==nA6laB(fpN z3`A3Nnwkd9R0zIqanMp9<*O7hfdZyR3sGu5jIc)QkXZ{!q=~7`R^*er8jw`1!>lmNFu??P zQNv}Jl_tF&%yf0O0x*F3fW~wg+-W^W({U5vd=->Eaf4XiqKzYiysCirL!N#**>s(MsCj_d}b!t%?ihE#oz z>_Muq`m(ACH4QP4V&aAquGu^!%`Io3O zi!SR-AANxQUh2%6%R19XKOlby(vEX)61HQOAAHu1;B}~pnRfjxFdiXh+O3B~9SE!G zOu4DZwT2)DzoRmS?MuMB^-6FHWAGBdxiC0~ZY(gL8b=~G0)p$v+;l1u_=<}64iM|r zU=;*1n=gb>KE!N(E)sJfk?SqXp;-!16&S(xb!MEmg1s1rRd^T%8zG4-Fjd%&+)Iud zt3bD)a|QqH;9Pg}AHv{$h}ry4Nc;dv9LN~0df}5US{N{$VVcnede3Uh?%-}WP6HU# zV|P@CS34w9A(4wM=RtEW1YN?@Dh^r1;yW@v>%CyZmT>3kW;BdOLd@yrN+b#(k!vk; zp_v0gEKcf-;8|^BP5yjeIRBU-VV)65Opv0&h>8Vqu^bP z!|we6274iicIXjDCceIF-;z(U4@<(!@Fqn)(op5=QVWvV0lreLCDZO4`9F6=Fuoc}ScK ziCkkD4b4c1>UEik#rG_T^=*R%jK$q_C5#Fnre1TAm;*_6Els_aL$efuSmi9Sd>i

    -7vZf(qbDjPa*LnB)q!v zF|=<$^Ew14Fg9zliM0domSqJyrNEbM`V@g3a5& zpHuf@SS^B>!T$gf_d_CASGGd)JOsh|!(){R#`iT4tELq!Vz7J^y$7pzAZ9`2AQE3g zl3i1?Aj08!9D-nbdpIFHt1G8k!7U7S3`I4u`>S&Ze2Yv=BoZOv)fFz)oDEG^2+BEr z*CF9qU1?-hKEYtzX+vN&i2k%$4>9Ao0Gd3IH~7GWQ~}2NGUg;gNX=nr|T* z&ySj5JuLKh8!PZJ193b@VMzEmEXRu?7-eUAYA&PeZc_qVC~b z;#ple(~5nH!Pq^!V6_usy5}<_4nV@IE9{VrNdv=;&BiKE?tiW*wV)w*h?^odn zVE42}q7@{OW~O`2N3IV9L3r5mdNfwO8RR-EzE?Z=@vzN-#W;vL+GZeeH6)Q{=CECa z+^rDJ8SUt9F4h5r2LF$-2R zAm*dTVk8zpB3D-)faZP(8pCOBj0wi~42U(!ii^ePaWl;BdIgmt}nJYrGkedNP4{!|ULho5! znP&xA9pTRz zXc4S#g_s%WekAUNgjZKM13eGTa}e$I8%?k}Y~E@d0}RB`@(wKCh9t7Y?Dema`_lNC zKEA{F@qHP@T5AO#f^T?ra%<75aDgCLQsE90RV3qdemP+Nmwp4F8{thiYW#tUj! z!|E!CxuA9{5(^;V)s-GFxfhyyAPBayN14@?$E~$h`9##HWF__lGkDD zTof_az`lg$a|nWEz=L|v>dI4AeErVwpN*nFVD%fsjFxyDYgHlP)fJAG=Fl{SAQ(qW zsnwOIt@!Z_#?jIRR-GYcvcR27-+p}1s`M}9#vCdF$rRh zs%1#r0ZF8pS$=p3xd$O?-t%alXLaRGEB<%4d2hjL7sNF03nV^+gjZMCyx*ZY22t}~ zG=0VQml^ggEB?GQ;m_usfGyeWAI~@#p!Vnb|(ylOWb#R`7lL^PG?lt2Br?Crm`51QNNrasxE;A*c+4 zF@$Gz#fl2HI7`9qgw-mD3HAgMk3k|=S6+i=2L!=*k}0*i5{zn4%wRmpd;+U|5Ob3G z1&PCu$kmk~4(J#Nf|awn5{wFLWiWnxYY3|bJpB3btvwQLA(5*q{h+xBqGpy_U5Skf z#&v~1`z!-imqAQ3Cm}Hb61lo^BQ)1T5UiZlmH4OzBN>cmt-D~g8e+~`Pa^R+Byx4- zb!c9NsF|f!SK^}r_c9opxgS;^LrgP&MdD{jPII!a&2(}HIFSWW-BP#d{gME&o zX0U3)X@EC9pNT{#NaX5De`xwb6s(6C8hq~!v1&&Jdv;T>OjxBuOt8sFOoT+PuG|F8 z4G;ud*`v(rN`t5dH#68~6s>{Poe(pBZ$jb;NO*PSHJI##<~4}=j1!+{b)`X6;6nyu zpB;eJClJ$TN09gh61ln(kJ+Ls1i^Tk;$n$sbtNIHK@z4UbDC-ntEQY=TEMOg5}hI8 z)fJwm20+sf60y26nf;Xz<*cq`p)>5@ z_N_yK^&zU$0c#)qlbG5I)ow_eTLLH>VAfmWVe5ySQ3pQ!ZOj%JcC-dYO~7t$2HmtO zs5=8%6MC5v`)6wqfBiEF1!o>WfgK%HAJ4c(4|e$wm9S%?s_@SEE&=vVrKl?W&B<94 z({p`x<)|PtzB8{x1?(eu9+N#FZ>Gk*UC?{Ij{EqHy zcaIam*%ZzZW>a1Fvq~?!);#Mv)~{HmmX0+}n2z$fW&HIC*tV*%W_`2qxO;JZ(*Tf#K>rt=kQLpQ7F>+l=*UheLM#y!u z*LAbkb&Kozn+?||T-TK$*C)KLPk3E7xvu8PEW=&by&>1(F{%4~Zd-@PoXw2W)=OO1 z_A%J%0N0g=g40a{V%mgV2gGy>yAE<)8`3q=b>+1m$2HNr)kN=BTe`01Px3Z$T{)dP zu8q7~ZRFi*W7qX7?y95F+OM4N9M_}Kp8a|>+OuDOi`LE=#2)^^b>+Fras45>ZMdyJ zM0XFj^(WW$UW~n{S6o+~Gac7gyjy+6yVX}+*Sk0nx45o6^c>eM-mPx&ZuJGZcDJmb z&{~R>67939S`N3_^63K1-4A!et)}a*I4{4LoNZwC0N_4QpJg2!3;k@@CK}6Sr^oxKDIH!@vp?j z)rhdi9~uqY^RMKd!VTivMh(lZ>J3~ChLzl!(y+R*2!uCXqn0lb^{ZLSN{n?jS}S1M zaB9dBb!KI1Yon$Kj8!MJHCfbEEtRdOMk-t1>yJ+q+#=(i*1>6viQ7Gvz10wpx37A3 z74{)&D*r}Fuxk+K^Cg%Bn%lUw)jig91WXcRt69~p9??sBnW#+yo~TjLn|fgv;%kKI z4YMWbnt8V_UGvkdwlxM@PxT56iyl$slE84&e*E?Hwl!ptSj8HKfJq&~s+J)q)+6ke zTm{3aI!4y%^v9<*`r!N(GIzIuGg7EM7+Iy-(?;zvV@|b5ReQX;wrY=8*Di8fRh;&; z4{23l={sOcp)sQ^oiTs5g=Vxhqq5`mv+>0B$_sm840J+)j|Dj6IX1WVie>K1*4Ty4 z&P$9^X?6t47?5()Now7sV-)ZVM_JxEL^5hoUVT>|Gl?So0_S2ue6tfEM03g9%=A zfqotEvXe~0Hu+H-9T#rP2t+fl7;e_tbf^OS3e1m8QCLYM@sSGNgNZ&)l2~VwqloXF zBrjZMn2io4c&!0$1aF;0vInZcyKs;US7j8O&C689=e%1XniOj2^bU6tt~8=*lfpMO z_(rkDPSr*c912lbha?9=usz~3CrK1KN%rk@2#v|vj+$8IB#HG-as(RTG;c7$>x%Rv zd9lj!4JFo?jwE85m$%h%7#!G5&~yJp;V0ZA$DQRHL1a0} zn}Nj;T9C_(dJM7ANwR|G^PTTXb7|{2*8*s*NkqY!jd7g#nhRU9b; zXf4xWQyq)mA&X1A7Tb{7=~!GCvIvbcXZPtHJJVUET>}O%!h1Ad&5G|Z+3CzO$>AQr zenFNC5tAV}3JG(m(>I!6p9k1<#SW441(?KTeaVPIbLAq?>TsBv7f$es%YDTu3R4+D!6M?c)lB^E=m#Pc zJ0s$x#EH+m@O_e@OgIL64uXl4py1w)X{(uVsyK8gY&o8=9|$Mzuy7TJ!qk1Kip`M! z0Al$rCMekT(^fO#M7@}y_M51K80s>o;V3t+D6=1X7-eXeN0~j!Io31Uqs*Rlc0#DL zqRbw4l%eVctt7-wh48>}wu9RyJlaXF5?i1h#qx#Dpmq!cP_RSsZeGzLB~O~}%QpTU zko9iMbEjZ9s?VYsC1O)yxo?R+{ z=XSubsn4PrCBmPIUME+EI?!j)%CQ`SlzG`k*#~KFOk?FJJ?>PLQra8S!0rIfZs zMIodTKH0TzHqF;0G->!O>M7pPM#+N>XI;FTm+eu8`oU+>%CQVJ*>g*s*PT|AA)XES zEGisjctbH^B?pOlMTeA;#{o^JL%c&HXrek=woEUJ8j7a^wo%T8(i^~YE1h?6(2U~s zH;TDX#vydInKP%=D7q5ickdhmpXJv1TJ;rE9iP*VREGrej^A`%jJJM&-j1u8b#i~+DW92A4BZi7nO537hjd2fIdX=7; zlU9!92&Bx*wy0PKiP$w^rN^CCj%7$`TU79?4Udm@rH&8k^~DY;^Rg`}HbT57I*&5c z2A@SM$8wDE#hY!EkCt*bR*ur+PDLrDZ4{5AAP!$x%$S>AYRu8&IS9rapRXKx1^(HU zZrdR2imnYKrwZyR-d?t-*kP2O{Sj7r+CnSG($f`G>@4MOtQ@7sor+RQ+bDLS;G|ta zj}IW|3O-so^a}j5YY{%w@k^xln6k~SZu*893T9DJN@?LHL3~1i;5)>fGs3o1Q7rSU zS)<1X7by6B8MY65Y^kE)D~ub!wy5AYXV`A=*iuFDoM)meemEUrloz`Jd=?dsGSs~| z$wE2OScWb+;CGE794>rQD5`qx85_QA%mY zgq5C?gR6`Tkdjw9+}9}5d`j~EG=s$lyf4t9#&$U+~^r6v~z4jm9i}=oQoypDnp}> z_jkIMp6XM1BgFId(KeQj(&J7=8A~eeFz%s!>a(bDl%5Syu`JTk3ao;H;@QvskkY%K zV=S7jft0WHUc0quMv2&?RPdVVNtB+!ODo6H)1y?ZFXbNoLA>|F2CW>+P)wY5pmZ)4 zma81;jwhUULYCoUH2nMa@P=?Mg5{$S&vfLosBo0w4H?CgCBQNgP}WusF| z@qDlMM^VwNTyttEp5g4bsNiCNH-<+U>U*C>E5|Z)+}cLT3s9bzUS+5keHN`8%g`yu z^UL$_rEkBnOf@k>8^VPRC>&+T-7-q&(pNdk(*5Nx&)l}?-_dL>eDHXbo)*x`u?%g^ zwy1CxQo_pcFU`$YY3D$-Xr(0=_t3SBk{9Zn3;aeOR+eo6{Y#nK78N~AjL_vB&riz3 zhriFFm17y&ueMS4HtyjL2>*yYe1XqO4HTpc(Sf=@z3JqW(p zESkYY6QdtaB$?#DOPcJQf0r~d)q1{@a%kYAym@h)jEDTYq{-vx-zCj|mo$6fXrM$~ z*QcV7QHDOYd;X4zck!22j%E1DdT901^Wps8B~7dV@UjFiYeimLcD0^Mxc^r!X|8R7 zrn#?wmo)KPk;&){O2l#CDkH91dloOf%jLA44)NOh{`W6wKIPrh|1N2UFD!UhFT*pZ zXPq-NN&2ic*sm1NVgK)vX5?j9>rwR2a}Zp7*%>+JSn@a|bXj_ODOb92LGu5>CC&Yj zUBSi9zg-P2!l&QKkjT@HtBqLxpc%!Z{C7$7-zCjl3<-`G@3*Rdmo)!f(!_x9tQD-o z2r0FC$-lEvM)~iOCi>+6z9r2C-qX%MFKL!CPl)pU?UH6GbFN-eyvvc^CCyUi&0tFL zjK}}Smoy_f;Qz`c%~CD+|KE~ksSfzxv7{MUg_A95;=sa($EzV&_;%9qWEbgyQm<&_ z@vWDjAr4E|-tYU_8o0WYc_Mtgf>j zYZ7KLk|{1q@ug<%jJ}_|QeAl>?uCGVW z6>?XGmZPU`gh%gQT_C5HqouKJs`b3`V6F9$tp)r-S~3!)bUfT z`{K=Y(;+hn2Z3Tq4mQmc-qexSpf$**<_vPM(#Gf4Q_UPRk z5e8yR^4*)FJWv>Zgz1((&Ww^TaF%=KOv!{pdhz6A-yOsAv-T4J1Z+YYjo#?cBySUr(D?~ zB`^K*f}+tVOvx|E&rZos&&U~_<7{DcUV7&EocwIx{}-`~rxgD;gGNmxP7&_brl~!Dmm6KnB41ThiTabB$lM0zY3kx_x zk539k+1akK;^MFA_yU$MVCF@82_C~0JheuRnl?R3FjR~h(2kdD3)P!1rQ=;w4G@X(VXkfqNOF(k{j0BW6t;Ki@HQIz?0EDV!H%64E z{-}U$-x8aUkl?p`QGQq*DYgOuChPd^Km#W16R4QYR4u;M4828Le%VIbe_U-LRwKv0 zitHUzzwwQ>XHJBPF_>AoH5uK;ynCV?FAhifD>4dA%h=B;u|l;xQh{2|nI4XRBr<+^ zwM;0#mUFRHx2?ZMMk%+J^F8(lD`3CKW4|OeqA$yh|22Be-B$-I&TxeEl)C{mUwFUd1RDw`*NAb{{0Hr-|Mme=;Zcx zpuQPP_WFt1pQkc!4v;dV`X|q^G^+yppGS?`v+tGd*;KP-&rx=tr)Rgu{qy+RTofMf z*H!&z`{P%J>$AOVeN3ahbH@{&`fQKvL(iUOD-uEzh%;N2>AFpx-LWk)6#dKCKMQ;9 z8~X>hs?M&#+-9b~X#0lgn&w)=)=XyhuhvP%+s$Z;yDy$~1OCmtxy94=XCo`@X?v*I zC)w%?o@PH28KvB2Z}ZrHQUUurJ@z+LU_>7F%;Qg2!2Wg52)?&$uaz0W|MB$N!U~Mw z?>r;;{R-GW0DE^>yyDg;G%T8#1Im63!vcR$kfYKa7H^zvSa68D!(x#eFgz^!nuwl5 z^q{AKe^sCZPk0*mas?Xryr+SWyY(sEz?VY}bVhx9XGGdhoUD~Q;84kFisR8F+72c} z*9z1;9iK$nMq7bq_S?SJ=0nH5m0RPZ#dQ-}2LjPeYXmBxu!dc=b;9gGRl9jtd_L)y zfRe^Fp|5JEcD*nVYY$8?$pj`_2V$a|vPW@X3RTJS8u+hei12v*8lWH0WqOta= z+OxL3mu^&X&)S^l>?V9OVT^6Gz1GG+L*w2H#GcpmsY<bh@2??^{r)z#9w(Wyut5Bwiw|lC*R)@T^+46Vv2cbFEw!f`_{qoQp zYukwt;}lirl!iTVi8G_w?uibTJmc8WoPi^HYPdT=+V-dAbQHc$xE;0B3>bA(i*P@U zbi1i}X#6#Zs1`R_X82te9^Efipi{X+-JNix0`}K=?C;iz@$YuRN1+oV222I)Pk46P z%N5vZ+s#gM24pw&jx!#^J8kofGJEYMJOc*3=h+L-!^n(J%%{#w)I8KNUsj;vi#-i} zr~(y#*HiJ8%6o&nWwPR|%c5<4lC_!z-XS--l~y zm|AwG(;m;);l{M(ShdVlY3!rzI_}JB*_Tz&rGD7u(h9mX47-f1pi5)-ps?&0g7Pu7 zH*aM=ByZ;Ytnc>ESHOPjMDyvqc14{2?u(J>Rd0u$60XN%6{yEfPrbi7xqYY#zfVwK zI3I+#JIhqz)NmC(I(f*@Ws$o*RoGhr`};ih&uYH%Tyb%CO{mJtDp2L7;VRFoK*-l3 zL%P?6+F+QmN9;j7I;?1?XK+F^N*v;rz06MNnvf7>m5(aS686UpLlxqXB@s}_6dJwE^|%b`arnOcVf~p z_J7mHeUroXpW{=}KiS_kC45xkh%Q~9GIPfgPkla%>_g9<=I;8(t6G?9hA;V4c@w{bqGoGLB;*hW!bk~b&~P+Blev;BfVdNw%_Gx`}>g<_O#vq z532!pdz!sBGD^A4UgxntUIF{r9{cwzFe2A_j-q=jV872Zg149LwK604X-}{HRDltB zBSxhAx$KDw*uQB;u(=Rzf8o|AG%R#g>vlA()K#r-@z}?5ry&k;cUU~?1`HpfWv*)N z^fd6}3RHNtr-5rKVE?J7fxF%Mly2aCp$0mKuzOYOos+e4Jsc`}RckxGI$QR^tNz

    -F!mepDSQLANKC|@^5U#=M?IE+2)6nh|3MPPYc^G)}j4(-^;%-GazR= z+y16(eax23Hw#^ryUkPoFDqcb*i-+HBI|D^xQboXy2sP1k0Yb7=4GyGt@7CKD{FtU zt6Hn!=9~^}d$|q^n}>xiuXwI%?Kej#Plaf~EtvJ)t6D!@9W?d*f8fb&vmWsQ#hxUb7AXgGZLID zE;GyNEYB5*Kg@BZ&f12GyPfqMt`xf$S=^)InaIk8d!KF^g)e$W)&8>kx6Dz&9qS%N z+bXa#p7HFAg%z+r=mcrocUQpvE3@;QzTW5dk25e)JMFxcWq00Z&d&4f zid8VGYIdmGnc>S@J1S6<$2~Q_sRH)=GUFanyG~Z~4WXLr0@otX1+J}A`8~{giS9v| z>k8LxC%M9PD0GGEw!gi?HOsx26>T32UE#XURYK>z!nL&Q6|OmI(m!6}IvSccEqhi) zoqqQ?{WZDFCuwtKq0GnW;~u9!D(W;d#yvnR`_m|G$%HmZ!x=3e;h?rw+eW zz`enSQ7T+VZU(-`e}qCS{fsu9JLeqVq@tXXY~Fk~xt+O@u3!ST zKDMx+n6(&-+a}X83kt5tK^=SLj5C!^E6Gcnl$AaOjms{^t$4l(p<1(OJZ`}BO-`SZ z?n6)pL4XNp?AY9bbmm}^mxG?n$t#>tl$};sQshg^&z@W|)`u`{JJJL9Zf2q16keN2 zy8`$2<&R4+Z;{=YUW{8j^Ri6`r==D5xuEa4*biCkP}a=}n&zn8{fQRlOve5kJGMBR z)f#gCkYT;rb~LveqT7p1w_~TF5k5S3aRNFZJ1@IvTy}mYTFzD!XJ zKOrvz91H!}!igPHiVIV++IFOddmsh3rgj^jUX%qzdQs;1Zn(d4VyEnsywk@PCZvqZ znv`BNHlDP!{sQi@B8ax&qSo0DFggYHimJ63nprl14Nowd+qrI)08^J5EB zG7IuciqbPnx}l4GX@zGL`zB{iLGPpuayl9ZN-;VJL)tx7@-o7sITKZMdNWs zZrBWZcB|`zqYTGms@ZS4lQd&ONlA9m*xV`D9p>OMI}yhiZVfd9a#H4a?5cu{Vl#9* zQfxiR-BcCdr5Q5i0C)0XK&qH>Ps7!o|l(yj%1`fBaw#$?qcoB$sq%K3?`bL4*a3%=n>e5$8aV_ zMgD|BH%1zphv9(ykn?-??v3&5&Jk!-Id|B?5F-Ho5hX2X?+Krb5Yt*)8ozoX=WZ@nzIAhf_}q> z^!Cn2JWh(oV`!Vn5*6YUTa@WkhW&1QdiEY+)NFfNF@_o^*z$)1kL5HDRajySWMHr6 z7G&Tc_sm6@kJRod*=7i8XXRvPV^?4ZrRRp{nhE(6inBSUIn9`Hl%G8bgK1(3MlyCq z`eZW;<#z0l?o3V@xmTD8|H}4l%}6ZCGch%_Mb2vZW`s^cWSHXJoES z=cF_)y9B+L&0&K5mc@o+*bSjkF+-p`IZxsU$3{cL+#REZthck596L-cB?VWc<))is zCBu7En||i8ly6S7I%hgHGxu+6U_|y9x`LG%n{RFo=SaZ0Ril}&YY6z^WhxaB_WBYfuZIH1~_Ra^u&)0&ee|$5^%Q8 z%q}i2C@N0qoD%VSgO>lZXANI0Zg@X|7d|yls~Q^@@k=xQ>Y`WGW^;nqR+<|#FZ#N` zeE;?K4N*5+y{b;OTUwQ?HtSWT75v>-MeGw?W01e*=vg&>j{jPFE~1Xy_44*@RjF%_ zw{-q;!e_NaGSKPVlzzVGxR`#ysLIjR{WYyxR&A{1*R|^5na2&RhEYxMV}Zz*SK;^l zbi!MTVfFE@q3D zi~Q9j{jU~p5N{QiiuZ~eME>fLe%r+N!~^0F;xA$}b_VTZ#X4d$k-v6ic^{F#RAl}t z@dj~;_@KB+d`aZ54e57C{8OxgaYB7}v9CBvyj+|jUMDUQ*NIPv+r)RpPsN`^3x_bb zS50gu_7De%W5hghg?PXCl(Eeyz3eh}_9QLm&{~z%y@u=7YQz7fyPV6NP7Bj>makhA?xJG^c|J&B6gSlBIO5&L#4k=`7AL< z`U%QU5vNOkz4AAUw@JTR`MbsYq<>ubr^Lpb`CE7R# z(=L|8{*M>ylZew;JD4r#KZ{^Pyhmi2QM7&hYS9y_ml{iD3L&EPmaiR3Li+4)D zjzoPoN&l?4Rr*(ze?#0$BJRg3|3Uhn#Xm)UbYuGiB;r?9zPflCi8xKgM6t8VyNc(E z7l{2y_zf0ENuMTOE`6a`B3`TV`QokOVsSZ%xU0qcq~9QJl76%Jg1B4dd&Ez~&&01u z#QjeERr=pVKR#5lyfTS?s!yV7A}8I8q!VW|D|I zPArtZM4Tc0wc>nnnaWp*_lggQ50i-dxVTyR7sQ>??-uunU#a|C@ki-@5syo6;T**N ziY2j~>f)(lqRLMfJBXddZY2DAiWf@XU%W*6G%-^wQTb$XmUyjrJ&CwCi%XqSu?mU!HI=U;HYE|KrI;d~t@2*t zMdAQ)C<(t2V!HI%VxjaCNo;qX^f!o$#5=^5B<$8Hzg~QT#CD!l`A+HI65o^lW92^; z50UWuS>=9wA!dJ6603=|#CjyQ-&FZTu^ovxoyD$VKa~#>M~Y*_OcH+M#6syy#2M0G zE6x{}seF}qulRuYFp0R2i<_l?LEI_*ZgG$JmCC;re-V#~$4SJsPIXwBM1NHk>q_59 zY$|q8d1tYwc&>OMiMaj6;nI&1$4Z|o7K*b}eyw=D^f!x3q+c$slYWEvu=s+?w~M>P z-Qs^p)bB&_bLqbpf0q6?@wiwO*J9W|)y4W^Be5BYxJhDL>CX^*NZ*IVxEn70C^1VM zFXoZ3o2dL$@mdnwxk0=|yi?_C#rvgyP<&GQXT>{2modK!gHYVYhsPfLzcNKd| zf1&dI#Y;%|rHPqhiOMI7S4%%jyk7d7#ii1(7Vj1xSNT)oX6auLUz2{9_`dX?h@XkS zsQj3CTzU)FE?NJ|BreX(`cNTk!=ZY7Sh}T~nF8wHRtn|5Jp*TzB*NQib zw~9+h#9c0~mHs~QG3lQsv43BaewX-;^dBj|U;LIt+@Dk)RUdiuL$p|hM7)~H*AbhN z@N22^F4CVZo+n-;4kQuh66G%y$CHSYFBXZ{sC=HdKwKm)CE>SHTqpf{@d@dl6}O0Q zsr+4WpLjt0l0@8t;?L3_6{8wB<&{XZr!I;9I!$aLCW~!I*mYLEt9TxX?er4|i5V&% zD;9{w;$#wj)5L3~pD!+wewnyRd`RVwiO-2!#qA{GzAEmPevf!S`mac|=a}?=iWU|& zsIN@&I1=lUh}%ePDxRtGZelO#`-m5dqe;ZgBN6vXaia7yl)py2nZ))MiFb(itNcOn zN%0wR3kkoM#GTT=C4MOV0r3m*h{}H#?S@W0W5iezapT3h(w`q}KOi0yzZZWd z5%;L*YlJ-Zr(ZmUM0qU|`@4no$zpr4lh~Dn-MPwNAPyxFXQVhrEKqr|I8B@>UQ5Dn zzIdzji^aR7zgK)fd`{(C#aG2Q#N8y~?h!wc{xk7=>3<>7o|RQWsNN8*0*3led^5f4j$M6{YZpzxN)TI$DPlVkaXX6Lr9VgP zFa1z)gqWl9JaM8pRh&U0?lt0#(k~E~OMjPmkNBj@pAlaYUlDhbi2IiKzV!RVuciN9 zJS^JHoPLNAo_pvs4emx}4)SQ2qB7mKBzB+i!pI`Kwv zrONLT*NYp)$4JE8ByN>{oA{>m?~#~aKb8JV@dxo|@fZm^t2v1A5)iABHSi=%GJxx% zVnY&kNhHeKE8j`%D*buNUnCBcew6ZQVwUs;$`^~X#B0Ud#3kZA;{D<#@mcXTahJGH zJRtrk{v!THqCNf=PWvi}aU}G0ly4xOF18WR7JG?<#9?BVI9{A6P8F{cZxk1j*zOAD z?-cKm{$b@G7oV1XoANuvH>BUI{72#e>AzF{NAXwbeThy#_{AWJ`qWguj(D2%Ny@hp z+e+V6`5xj0WB~IoiE)=EeWsWz7K#%{*iBb{ws;eXIJc?%Zt3q8H%R}4@=uG~Ncg=b z?h-#%`KRKy;t%34B>awvRub|&Uc`73<)@OUZwu*@#WvD+R=%rv9tppGD!)|vbn$XA zUo0jOf12_$#T!V(St#Bv-lOvS#Ye>_#b-(QZ4q}!zf=5=^!vmE;!i67Rs2hgYKeI0 zmlzUptB5tFuOl{BjMLjOqBj~v7_`| zNo=>T^aI6V(vML-L(C%)w^-%ZNIy?pATAP@l8C=X`E}wWB;srmpA}zM`J3Wi@gwm7 z3BNDI@1;L19+%!e-LZ=iYm?}&`eHLNNlYOTx2@Pk`m@Cgq#qy-5i?ajPAn8l#3>}= zUM6eSE#fMb>nE0HyRoqS@?yKT%>Gy~Sr2k6%R{TTdC&WsvoPLQFtC5IX zOKd286EQ{l_F^aTJe6N04wQbVc&YU1Vy^T>;zV(-%C8r16PJi9NYw96@qXza6rYm* zdGSSYx61d3pNOA{Uz3RYo%pNtzlr`7r@S(W@m!z8cxogzlRicHwqjQjaeJwJi1fq7 z%fu`(heZ4$NW_^Z-XN|}`JLkZ;)CL&B>bKfw@CkzxJ&wXNo@BE>Aw*Vi$}yi zNZ9#XgPecF8YH$;mqdB8^sUAA(sxz9hj)F6noR`=tL&{7O8g@;}8u8^l3>1jVW(;#L>yOW#OLmOfSN zAfBu83&g?V#o{Ouanr={(&vhkq`z96CElv?#o}u5Zt*@6aW{xhNdL6BP5RfwUE(Jy z|4jT^`tQVFrTHCO-q#rJh5_45vC{7Wt z7H5-)J6F6#`rE`+(yt{k?w*kTY4JtzW$|?qcJC^`SNx2`cD@l0iGQg)sx8XV{umN= zRm7Uo*Abga-%?Bw&sKRa@gi}6IFv-(5n{UZ*o{` z9~C!C{}NdZ{UZHd@qqY+c#y1y`vR0dDn_+)wo{2jd0i6yb(+{hOcvXaurMbe5q$6dnayn68&(hSYP@^Vv_W@$86ZzX1)^D)NFBV5hpC*o%K3AM1{ng?u z@m7^D7FUaRi}#V(-Ujgr>7N$2N&lL-OZ-ITpNZdzKZ?JSi2Iuu)xqhPXt5fJ^4cWE zMUwQb#J19RQT}Z40up`$RDPNCSz?a#MaoYUXOZxmr}8_bUm@Nj-Y;$>QLjzPKP$dW zBF;|nE%AWLzYxC{4~s`h`28XJ&p;mIq>@;JM0s8DG_keH+lgn1-NoJ{{LU8#Nk2@y zO!~1T+A~S|tHe3tb>dAV>=rA(OuUE0b{-HP61S>+oA`$Kwz!9c-v{Dn(tjl$mj0Od zrx@1}e(0ZSVm+~;*px)vL@`zR4q|ud&n3~Gi=`harb$0u`CM@liMUsbv&1DTUoPG$ z{aW#H@fi}^d!0o6-xS}KexLFO#P3LK@3448jOpa~R}pK9b;Q$1_%#-jrEe{sDSdbG z9C4`1M~LZSws<*-xcTBF>8}#!N`IrcK)g%k_lO(CN5xGf;yx>GlYWQzj`Z(~`^4{6 zepviNJR$l!J8>(C)kySvEipm*7Gkn^mdd+}=Zk&CK_u!sOdKP9hL|UPF^T;>NBZl; zh2rhvG7@%oD}S%}D2eSnB|ayXIB;s}uyGh?u>?{3X679*9ew*|iDxM+znPM;L`-p?2A1;m( zb5&j_PLO_zI9vL;;zH?{h|9$dDt}mfTHGwYNTMAti*HK*j`*?kpNn6Mzp4DV7=4!0 zKb6H(NW`rnHjq9+JYD*>;u&Hem0u_h5r>PTNyNQO%#l7%oGkrxakhAy%9n_DifhID zNyL3nd{X*n#O>0*F1{)5SNZ4SA@L{i2#L7Ai*{G!F^*!y>LkkRhz-OPmA4hUh-ZuE zknlTC94P%zF-`hxF-M%L^6BC{@dj}LiMWfzmD1lOZjk;_@k#L&mA@{&EAAEdk%)Uh zJShG5;&0NQ5b>w=jD1ZK{Z&V7EH)RDNyKd}c9Q-qv5)k9#erhF%Cp6Mu}GXmBJNe< z9ODnB7sI@{@&Sg{(3xV6NF z(l-%Pq;F4Re(fQBZ?T^^NW7SYU7GTlVlG+3=PMzr_eGsOksD)DvkeKESH z<6l$kDGm^)iPwvp#O>l?(bvm~lOmoaju$73(?lO$T<`UZv0}VfM{FQA7qRSM{Mw56 z*lhBB#ew2*ag>-Ljuoeh)5UAW`QjRJo%o>mi1?KFoVZQgAs!IF5Wf?D6pxC3h*6f) z4)c3<^h=!b)x?gX`8_+zdn$jf*jF4V4i`s>e6lb5d#qR>7K>9wJ}H%U*NXGS1tOo` zYu4$-XGQZndHB7e{4SAC=%xMp;y&?n@oVu1@n`XO@h_22u4J5`7%$co>x+%V!6Kgo zOusQ=hL|Jfi6!D>ai%y&yg|H0Tr4gV?-K739~2)EpAw%FUlLytcZs{j_r-nU7veYK zkK!-lAL0oy+IHGqSu}qy0R2!)`Ho^2v6t9K>?aNqM~I`vEOES8AQp>L#p&W)@p|!A zaj|IrE&=NIpz@E4=I<0h|GM&TihINl#6#jw;xX}0@ia^{90!fXR${7nme^gqQ0y-b z6E6`j6SKquu~?ig&K7SH7m5#ykBiTWTf~>e*TlEQ_r#CH{o+^Rw<6D>Y;Uv}Csq^d zi4Da>@pN&pc(Hh?m@Zx}=8F@=DdJ3Vj(DTEKwKg&7uSmSi4Td7iO-5##Fs_$cOcNt z1Im9P9uj{NkBNVZ{%EIvDv9;QMq&#wS-eObAYLq*zaN3^rz@W==8Hw5`MVOZo38vk z@doi$ak02syjxr^ZWLb;Ul(_ad&Ez~&%}e`_hPjer~S3W24aHPQcMv$ie1EW#Ph^~ z;!tsvm?n-FbHxeb6mhmVSG-HSM>Ky&1O4}~@=uGK#ckpa@lEj^@dNQ=(fr*F#QQ^e z9xLW}5l<0oi1oyVVso*j*jqeb93T!6M~jz<0*&MQJg2#Z)L)t%2LUI_AAl>bQFFMdU$?njjW zU9633CG7Y5Vk?QUQM~I`ve6dKpMw}-u6<3NI#Ye@L#8m?-1`6 z_li%7FN?2=`^67L<0k_3HGU$%NS;%l0&%!lBu*D+i6@F*6>G!>@eJ{7(fE5nK37S; zL%dtuD?TZ{EWRqbejPrL?CY-f7b9YUI9x0er;D@16GY>`0p+Tde6o0kc((X$@k;SF z(e=w<{4gM$C!}}%FZ@!n@xOrZKS;KEIOR_hyNj;Bg<+CMipPjE#AV_Nv0AJXH;Y@u zZ;4lkw}^L$kBWQ67sQvv-;4XjzlpwxQ;%+9M0EWh43|7roGvaAPY_p&YsFK<&Eh5E zx5OL8Tf`?t*N?%gl3x@5D%$uWlJnN}PtZg1VDU(Cia1SNEG`!-#cJ^z;wJGbahG_P zc(3@J_zUsBNUU4$OFkglJ)QCf#B36F1(N%UMdCQ|Do>so34r~j(qAv$B;GGRB>qf%R(wPJo%rA4r($+5r(QW?KXITqL7Xhk7Z-`E#0qgO ziTbumK25wx+$NfR{HT}N#}AtQ`{2V0H~aS?KPUN3@on)F@iVbYfm4rMvA;M-96_R7 zQzTCl7mLfqO0in}hPX*I`|(jOvmYP4LHh5A4~mb7KNp`D-xA*u|1ADh4C9M=GcUxL zI9MD>q8?KvPZyVnCy1-Xwc;t_X7Lj7TjGu4E#h4y@-h45QP0Pvf1bp5JuivB5#JQw z6aOHZ{qnFk`{lv3LMMJmH2dSBH~ZtkVbYHj$BSm)Ji-@BUM#K<&3<`=uamq{+$?Sp zzbRfMep|d!yhprWH2dR`uGt?CJ}vz-;)~)d;%nktVn!dQzFovTF<8Qw*%y!e z#!Eg*JXS0g7mAC;6=I24F0K~0iWiEPi91BIA0GMMAo(_Nk7)M8BmDc4&AxcZKa%`2 z@mcX@@m29n@omxUlSljyB@gWDwAWB^v^ZWg``=+dP4aAUzPMC8Q8fGDVP7V>N~{%| z#TL=*i--Ld$=?(&63xDNgzu1S_QylMLGo?l9`SzB?3ah#Udd02&xmHfJi=d*{9oc* z;yYqSRO3nPF7_0o;sEhTag;bw{EB$2SS&6S7mFu}UlS8zm3WG{Sv*Jlrg)8bo%kK` zcJVRsaq%bO&&31c$KpZJ-_L0WvmYMqX7D&Q z?1x9ZGbNuRUMOBFULjsB?iS5Hc*MU`@^{4tMY9hc;V(*lMSM+sOWZGhApS)(``;0N zV1LaYu}B;zP8Fw%bHoMWQt?DFE|!bcVx71_{Dx@uy`vmv-#d7r^p}cPh*yhdpF8aC zm;9LcxcC#%?0bjZOOk&jCPlN)9pQhL{8zD0%xRDQqS@CDJF~AH94GxGak@B5TqrIU zSBhU36QbGYj`SKOn|{k!qcjAMbdiN6hh(+Q!ah5n&Tq%BCY!I8pv&F6AmEum(>_bQXW*<8Eg!Dfa ze@7ycG2#Sqwm4rb5m$*Pi)P<>qJW)e(*H>e4Ry+$Ef$LX#4+Loake;LED=|UCyQqPHQQhER?+OYhJL5yJ>os$ z6QbE~4ZD4m@wvt9uZH}l!rgtk2l4)Ip;PVq7Eaq&g*74cm$DIOI4Bb@T*iTUDC(d-LGJ&%@b_5(vU`+-5T9~i7x zc$2tAJXgFzyjr|Nbocr0mHedmviPdFU;IGyjdaSLF2=;cqS?RO1>Yw~o-Te}H2ZZ? z?pDdCi5H36#NFb};sfHtqS<$gbj-e6@UZ)Bp*Q<&!7ihma_5R8#WCVhB+5NU@&d6+ ztQ9wjXNud!%f;`Aw~LR7?ta)8CBGuN`(6)7wu_u{2E=@^w>Ux^Et-9;sGr%_3LbVp zEA(bRD|ou%oh4o-?htPk?-U;s9~WN~UlHFGlj1?qKia8>*^i2R&3;sHnDisXW5gNa za`7Z_tynLfE}kV`Chib#74H-u6CW2}6kid|{!x@GDfyu2AEWY%`QlJGh5+r>x3ABxY5FNtQ~C(3X3eS(MG?+Lxx?+Feb>(uK=@z8yp zOQkEdQ|dW@dfc^@i!#wl9Jthjs6Kv zd4pn@gk7QJe&QH$f;g3g-2%zSi=|>hTrakY-xMzr58bDDuk;UyPm9lpzY*UQKNdd` zGbTFq=_2+K`-@}6iQ>^D>akGrVzErD6wN+Ew7=PB2p)ESA^S)6-xD7cej)C*b`uAPL&T%Rsp4_s60uxdEw+fKh!==vKOpkCPV$Z7ed71UpNjj$ z*Tvt8e-i&9+DAF{$RUw_o;Xk(Doz%U78i+2#R_qaX!h+Py;CJ`A<>W9B)j|eZls)r z-?@l)i{BF;5zW3m*u5Zy@W%gZeZPK}OCN-FSJDqawbpFn0JDW{Ag9Lv)+r6mgn3Q#@W= zCaw@m#5H1#*dR8Go5d~Sx#Ica<>FQ1E^)WGN4!V8UwlY>O8lv~PkcdqO?*pyM|@xW zMEp#&Y^Oc&9(dC(IbxoeFZLFPh{MGqahy0!oGH!`&At%y;|j?o;wrI1Y!I8p7V#AE zT=9JIVsX2;OWZBqEZ!#GFFqtbCO$6i6JHQt7GD+L5#JXNh#!lVPwgp&#B4EN>@7yc z0b-FjPMjo85$A~J{f=nQ<0UT>SBVwk8nH%f5l;~}i)Mcb(z}>)2>)LzUM^lG?h<#4 zd&GOh`^AUEr^KI%`@|Q-*TlEPcf|L_PsGne%kPvgP0SJV#C);0I7A#S7K!7;Y2r+A zj<`TPbic_e=_|wru~}>pPZ7@*&lfKiw~M>P-QvySZQ}jnL*irN@7yc0iwHaWt`+m;uLX?xIjE!Tqdp(-Tf0 zaf^7dxLv$lyh^-TyiMFA-XlIHJ}y2b{#1Nfd{ul+d`mnaek^_>ekO)6r`W#PVvd+6 zMoF9l#39lT7mG;T2giwK{}`^vb$8MoFvJPZ<9d!i`C8X!N}fX^|7OW8B=4&un>N-q zmzIHeH@M*%_o_M3(rk@1Z*L!2*3@K;q+;Y@-wn+7ynjJ(RUKbR?!5hcWMiVH&9uC- zve|vrut|iW6^XKStDQH3>$c zblmiI;o6OZOY8C3_&-0lF+E{-d#-7BIvU_>c;<8uH;p@>@a8-2ZAi&wy(}BgT%2xtAL5#E+&Vt; zUCZL0A@^Vy&%cVUT^~HCatyhLYnO=&Uc1M3*l}#Q2lM5@eaGJNeTMQeZI%y9UaEW% z*rD4Spfbl0G`x2%xp|Qo>Zzjyc6*@g2~7ki^UcA@JUzq6%EtKH1f6@h>9LKxcEcyy z)?hafVeaLqiQ~saJ;&(r6UG#cFDjY@ZIRJCe@7P;O_(qt8XY}x%(zKLzbbRntOdok z?WV*uhosVFd0LL)Un}6$cL?f|Z{^%`*B>`;>bu~KhP@5;=9#Pd?F+vGP5q#K_#5y3 zY|r_N4%l5E`#t=|MZfk*+WdyuIYayIn>IA`Y#u_UwF_Bv;9!ws6Gm80yRb}X(xmz2 z+aadf-%0iPw@s<==QNysaB>~szUd$LaQh(5Zo&M|UXYCqwr%x;nREE;^a4y0|F1F; z;YhmhuzYstHq1l+VvIfC#Qa56`2wGyyZqbG55A*%mKjy>D~vbdh ziWZh+c(*EC`$B2lD&~I#f71H*WZl!#_Tz8xY8cu6T_{dqc$g*ehcN&HjpjOZGD6c6 zcI0vdWTXXd^m8M9=2Vm*aC3GRuTMj%1K;UJy_Ll#n1`!u+WW08p}_SSjgZ6FG0hu- zmq6`{S>bXtYv7hZK7xF)G|PVmnk#UtpHck-nfRRrtm+YI>1mhJ#tuD--U;y9pAFk! zkDjL>Jf{fB<_AZGa=b1{W3rqAgu=%eG0zdR!)wrt z!7&Ann3EfCv4Uf>dYFXr&``G^->hr!XAo4TZpeEonr1+7V(9zK`$pz{REAqWeryO% zmY5cfQ~Zj=Q224wB{)T5cKCGkNpPyfobcr=+R+m8!jl;H7>W7eJDJfmiM_-3vN5Jh zj9Oir(JCQ3I4_ie8il)|SA+92dCgY81SJkG$e`$tZMMVQOcgvXlNE#P3x~sy7fZ$` ztgNjF=?QC7<-S(eH&N1y?cmo!38rq^`|DkK&D0-Z$>Qlw6QqUNdco3+wI(zaX2F7G zeb`w37(NxJr!nEIZ{QD4<&d6sI)rX^P7bDAD7Y?kC&ci6jELa+TwXJyZ7lW%HzTCP zQJ1p{p=*NohWJF98*i|J-|MOfx$#CTc%M5Ga^oAU;Qf+9VLFfqK9FH1YAic^G~4q* ziQ(LMS)~>He(sqj=bZ4LS&4@fH$P103BkRYY$ac;clZh>^+ciBVjPQxf6i`wvhYK6 zwl6jyJcfN2rM}c6^xoGK0VF zIvb7Vi!BQuOXD}PPct=I5$3lQ!MDPk!M<2Ym@nrJ{#Jvn!pgJR*NocT{9!wE=NBE_ zsYkzXGkkzSJq9D@khI_`Ux=*}If3bx`BW$?ayuJiwJ+-yQ-!q1e=~fwFVB%fky)(p zYF{5m&W=35p;qM!Ib$s+GM#d@FU0Zbi{(WgWI=1)^ot@{lMOv9(gBw06 zvWC6h=*!GPYxrVQBFD00*ZH)ROpEkqqpf%CXGY?jz#H7~IgyW;UW+d;*Ti2Cd6%vF z4cGqo$Zj_4DZUKzEl_M(y^TENkMo0)bvf}A!Og_IC z(hCQVu|t1=6zRdiGR^Kvfl2)p3{H3D^hlCPA8U6lL+O0jSDVF)gD_IDd+rNv_6294 zOCq;(+??Ud=iQ7+J;+8s)7RDM$F#^&R%nYahsM5GDDpV_;4EK+w+YPo$UV&ZY~K;i zIGq#e&7z&-8@|<~cYNetFnF%7m)V_Ye!yZWiNC};E(OHBRe^@E^?Ca$9CJ1mzn3quHrU3 z@;6SVOI*c0c4QQ1$EB{~Av-x$ZTEAcWwhA- z*Pw_tpvA4e5fpb*-wo)X)B4i)&8dCQfcliay%|wiujEn4UPf>G_nmvqgg`N8~2!UJ#r>A9`zk6ZQGbdwBDC-u;k!R5o z8P%aYK7F$9{3vn8+EBNhM)pNcM;S9}T-hHfL91ufhPuWO8P99M|6fU_jVUe6rbn|hh#afxCw$5??hT*nTg{Fx(qQ!kT=uE{1VFqkGI(FB>J zds8oym9EJ_E5PmgG5Q?H9N(LInVg18r@XcmsHM#a43^BJdNV*a+@YVU(oZg!OvUxXUbA%Omg*Ig@@~qwrkWCmv)5!~s!!7+W`hCir z+nWKfVdsy=rD>dq72xjvSc2_$Tt4+OS>~FIvH~+{LhnPFOY*6g$p+UXZUt7;qyj@X z^MrirWwOIHdDIGQrO5>}S(#70Odi3dDeoq<9~bS|S*+97^BEwUH(VRIdI~&Cn>6-A zSv~_~laBG_)H`4W{z#ik*?yJz43N#Rluecu=m{YV?OmV+3uR4{kG8LEsnqS`P9qgKGy{8cN0xEvx!^tsh7zw zT@$q5(=@q(Ca2|7FO$FFGSzkWGJledDwZ+AkMEY%guj&S!vZ=v5%q ze&cC#92zlmYd!;HQ=PIw`<+Ca2ie9K<}*Mx7p82`ey7srW%lQ#`3$h_*s*Mf%QRJE zBUp|dnw7DsoH^HM0>=K#{IAnoi=Bg^oOz>WRgAt|GH=oRiT$3fa))M0ET3cJZg)=X zMG5=iYZudB-B5j8$96NZ2MVZ1v1u~XH9>!kqscJV?2!WMWwP2enP>%0q{)LEJbMeM zm&sPwZGmb&YUKq4$Ks z7iko<3m77!V%O+VwC8vlm9by4?E;42Ss;T0H`i9X6rRVjbhovv7S81$@8ODOmA%|e z@nByoa1K-aDx0mBozD=Y7~}XUa7DAS{L~xg`;7A*OVQWPX9(h~Wh+HfVmV7Oz}6%w zqzj|WfwpE)VNVunsI6&IIEFPCW@`==E@D5Av^7x*`H3%cl&x;jTa!qjFp3!{)}=qqfD~%8GyE?&0Vg|CM$3)Z6>kYN7?xd zkj*b}>Ew-0dxAy}atuwi^BE$ePg6$d{gHP-QHJD(vkisrc~VT2z6p^%=WGLNs#8X2kCSMGhZHMwww=!qw8s@}@HuYpm{D*wLfrPa zfKmL6vcS$~0Mh0C_y?{H+T$+T)Y4|5ozDQ-{0^6?_IQy-N3ej4?R_UH?ta5%F&!OmxhjFzX2&>k~sw1<6tqMgqW8MUU2&>mGZ zI>7t;SM7X;pglffLzlE0;kP5ivXzWILZBFyd&O<~15cqy8-RIy;{s zwmrbM(5?2YY?}}3Jg#zJ*#nnac5#0?jN+r_W}Jig9Bt3e=3}(Icrc%$?KxR|h+c+~ ziT`1+2J=bUo@;dcg0L6PA@m(*F9 zZo>0 z4>e29!A7+^=%79UDwdvVl0}D_U?Hdm%+VWvol>+-3EFrMuRI-P_glq?;biB&=KA`YrYL?>6HU~XB`PWs6(y6RV~R#k8gcTt5w)e&^^GM698p(a zml%;KEvqW2sw=NqSCJ^GEiGTepR@cs(r()L&z8BSs;p#ndHEq_pEPpJ$kA>M{v9Q^ zoSvBLv=O}EHrB?yzc8w*t7?v)Ja+WRa`s!iB2ihouBJKOys;tCG;$4xL%gZE0{HPyoq{Ae=e_r=M;GDcb z_w>9#&)$LVV*-KnQGsx}e=S4(Q=&+s8`-sS9He=-K^udKk>s*ShQHzew;6BAXd*EBc9 z#}th_Y>aV5M@_KeX!%47I=-}Vb(4i3cEuM?Up6Ox-1Ot-9#?ENZ>XxMs7cJIPgKT7 z7mXRm;bFx$poq0)7!0M&2`k=+)V+4hF3w-8#ha>D*Ok`9%hpv|>*^>ZDx&;Jf!CU; zTKLby%BHGTBvx5dieen5*73@!mPAF|DKmck);xAhyxH=!m}xF=%8mT-99t#P*jQKZ zHC;Sd_zU)Ms!A^33IkxE>3^Y zoMvmV4z~+7Ey_vBs;)C_f5@tUfVy)0JkcakUcU}GR@T&)>aXdC!*tjLbSpEgt*W!) zRkaQ48WZsb{H(C8(dVw56<;`aDaPB3Iaa(5KcB30$1I0G$2n>@dIH-3w~Y#nGu012 zve4kBp&8#b^>wSG=1;q!7B6kWZKgJ124OtjR6KXVEDYcZEaB}Z8*}rHo(UN19K-Q- zsWQY(WUmn-$x0IsJyz9XAtK9MUs>6dXx|s?aWtbh4Kqwl72GNz_N38Ajqz5o-BMsy zfxl0K4W6h?G_Fq6m2Yep%-G)QA_J3QswnaY-*0hedwqwRma9WJr?Pldvm$R+0xqd@=lV;dq29;KU zLpuwpw#(VHDUCd}cB&kYuP?1x=bcBW(d^@vM`w(l7&Uib^L#OS%;>SvA^6>EqO>V7 zH2PKCtw&56QHD`iz9x#_+Ez8;(Iq-&!o;G9Av$7p#fH+x z$`NCtBNmN~j;O4wAAz6aR+S@GO;u@A6~_69%1S*xjX+13$0+FdTV$_X*)XEKzOK0u zca*6Zi&ng0d{et-;uyzhObvqtvyPjMwSU%1>)s3^-Z|%#G5Lr@Mu%jK3OwbQE$&M!VJ)GHP1p; ze06DUZK=7{;R+8$?lQ!M8F!!sxDk7E<#OxHfHDj%Ebe$ns;O$ia#72Ly9!a9dry4% z0;GkKX=!O%UsYkD_su+XQrJ*#I>T*NK0R9v&f|i!M#OoeGz+ME-@c(M&{fK5K`!!DO%PPd`@37 zd-=jy$1T$cjjuWUtzE0uq0dcRBtE}{ZFRx3XuBRm`|(a-dKUL-4ET1zPKUBp7c81F zKfcTiIp?Oep|J`NNNs&aBWLWVM(A{|s7-6IbeJb2lL<$TcgT#M&^ASv&OL7S@&(hE zd_hgjgJ2V;JD<3`4eX5D_9;7eb+d~hj@iAY3&E#+90Tw6}P; zZyo-2={yCN)vPrSjab8&F2*6!!P?Ni@o*O~t=j&vpw6rl8_?8pICyh6s?Wd zl$w>S%(L1bCW5;tut^RRY_c=Mi0fmW`Cy_?56&&de6DPpSCts?&J=3b$KGlBRo$woSc<)=EH8=?BpcE#}Z9@KGB&GY)+C%A zI)|yAYR~1!`M5LY?_1miRyD=TTS`%c1Sb%mfXzd)GZL8t20g;o>SIf>`Q*s1s4&B; zuC}xWMM2qE+=gY&M>+g-a>k6w(II^1S!TXo!N->9bbQ4!OJA`>@p+{@(bR-bq0vbr z+I`zH^ndz@girL@I1l2mE#E0&yr`iFvU~8Gr0Lv9Zp*F#UX8_~yVV~W)|!3L74`Xw$07&U z{Ql5AD09Ys-pVnc*&1Nhw8I*-8|JCoW@?5wk1VF`=zsrQWW~LD=ZhDM+r`U8ep}>2 zvvGX+@Lx;#&vQfkSDGRBu=o%-kVNwhmwvQ(j5t$VBAzHFM1Hx;^!fEIxk)@*yg=fpcEpjAN9x3uacZ#=)W^Xs*y(pQ# z?qNC~iG%qaF643I4AH!!5BgHc4dN#8Lh)+xHt`|xY0lVzt;RZWVWkw}{^t z%{#G>u6ZXGn3VpYn1i)|`S%mYh^L7cia!?l-|DpgSe%yW$cw~P;%c!*+$8dcwv7Kx z@e=WJ@q6M!;txghjw!@@M)C{dFGcgNDTF5_^H#uox{8yJy! zApW=53u`3fO%+#(Tg011^G+t%9gv)dHI?xuiYvuaMegxp_~YU`Vm5Tt7m4N_M!4P} zd58G0Xx>4D>onZ*7;lKUKx`1Vi`R*J#7D%RioX=!5&tBn;U>rQ2aEH>TJd7>9`R-I zGck%A5aZ7jSBqQ4%f;`DzZQMCHJg0J1)_Ne4$`ZZY~FbT`5MW$i_eL#iwDGmVi@;S zrf=S10}hw`6>*hl-c^I}ZIbU3&AVoxw{cHqI)lXdVuQFzyk0c#e1ZM@l5=rmX8Z}_ zSH;cZMdEkGm&DJ+em$J{#o`HK8Hu&BQZ(;O!Q9zM89Y@ygGBxpi&sj&Q`{~6osz#R z-Y>m*hYHerQhMC3O}@At7-Cu&VmKJ)i+oOG`38tX#3FH=I7OT$&Jh=g%fuDpDzQSW z5gWwIMLyp#|Let@#Jj|M#fQYl#HYn)#23X^#5cva#iaP5_?c*)XOMr8&lw=MagyD| zo?=wQZ)-i-{s*-ZwXCB1n!GUQ7no983QyCm-x&2tj; zcS^>OT}?U6yOW{+k>sbvXGQZog>duEWbk$A-xpmUINW8%dVebV`TPSpDDsC@l&6U1 z`3v%F$&19LqU-CTOfr8n&-mtD$>2K48%6A}G~wrp7m3@%E5)6n**Ai8?vQ-1_<;BW z@d=TeP?^8+T?76~@^8eq#rH)1XpHuGVs9}j4i=9T$BO3p5b=(dY~G0sd7k9sMDyGT z{YjEbMYDkv`Wnd%A|8jZPX@mPbH}ad&hO&C?>s`kj|JS(sunN#V7~-irpff;INdn7w62cedkwcSJYgq$u4(sce30GjHj*c-7T4Z<&xQYveXwJ`)Vuj^ z#Uxagk>ETf^mEJa7yK!)7ord&i=N@j@MNoLtTjNO& zkAkW6Zosu0hiP1h^kyBVzSknmn_dgjW4p3^n2xFRcwb|B91lF6k6Km&_kH(Z7*F2s zympgD9o{#`k7Wm#V-M_Rx&p{{=J5nhZ}~QR>WfFIRQY~^YgDfRFvrJ8&pY;6CLW|` zcvwSFq2r;%urc4}FkiMi^Yk>A)q?TNvF09bdbv<|?dU(|cdilW+Krkx$#K3Bb&iy8 zj?w>b`{uY4_l#`57@iLThaRqPjz8l8vCTKf+n6{0dJNJw-yA();J*m{aENb?=}5HA zH%FAoqy^XWBU&i%IzM5Df|C%d%{Rx#D1!fFgt)#r!U%SKbG(H?(atx=Wh_a`H^=uG z{3`ym_s#Kr7`6A!!S94z-y9bq^zVIh@K@ljZ;q=_>W+PLT*EZmd~@tTvwD4V>_T(7 zzB#xJ`|o{o{0Xb7C)aIMx zc{YZ}H^&7SAfM}-<4(50KjWLjM$y`QbC~vS^Ud)`maNS;$0(M&%{K=N_7C{xn2!%u zDc>AftYk;NIZDul{{!C~1(<>!-yD1w{O9}T=t|=@-yHnX)Z?4uZicq`=Gf0}{aoK1 zmtd6tulVLzz)o-T&G9rxdYf;K%Q)EDd~>X#ahq?B@32Py2Hza~^yc-=@e?+N$2SMJ z!hex(4tf~$`sSEQ`5*AjaXItz_~tm9z3%bN@m1#U@y*ePjpp&qaTzDD$2UhV<9mE_ zgxHK8-yFZ8?D5Uvr|j{~!FkorH%A{9(CeEcK*bmO=HNG$|KYwlcCZ;;-yBOY!`pmw zn6<>?o8w%zkjFPiDeM1vzBzgz-Ou;UQNYge_~sajjQ>TxITo=(9^V{qun#=GIi6#w zzrZ&Kzh&|I=J-9w)ff2Yc#QTQ-yGaQ+|D=0J2de6=IG7JdVO>7KZM%(<~V|7^!nx) z&)cZiH^)LYpw~Btap&Rn&9RV6-M`2;$0wY7{|4V2AFyx!SA284$Qrcy=D402dwp}< zh;Y|8#|re%A-*{tgZ-xH7&N*SJqds8D1F($H^;?LeZFrFe&c2J9gm*a)b|dIqtp7n zj(kq-%m1M~r7!oNeWPy;)=Bv0;Fmus-yHOs+uk?Fa*V3>zB%~6dx!Yu;D*HXw7p0i zzB$IpHwWF}WK3{ax&2dzlZ;mqBPj2(gaScoI6*oQk z=9uEj@Xhf<8ch8XzB%~+f*ttgptqF{d~@WZ9XjyMu>eibfp3mV6uKkd92J;^9r@;< zAK{LCbJ%F{j(l@$W|2Ga&2a{6{>8pI&Sd+2v2Tv&FxEQo&2c4$ZU??O=-RF$-yGMo zP96B>=+A!Wz&FRO7~mcG<|t>|bl{ugNzBU*d~@7PlP~to@mKcd7yITog-!g$zB#U? zNe8|;!W@4c_~!Tv$KSueH^=jA;|_dt{E7XU^3Cy8wnNG{2mi0X%{NCgOa7&Nb9{=` zrp-6UZ`mp--y9P-HvVbf95Yz6FZRvxJr16K-Zw`T2hYF2HwRr1b>y4lR<>IQzB$&h z=3nfaN%h3{LS5d~=+@a(CpLn-h~x-yE2CoxVAEpRVHy)ajc8td*>KM^vzLaJZK!_`sSE#d~-w( z@y%f@7ke$+`{pP=#5aerKgnwk-yB~(oKea*N8Ta6IZP6B>6>HX|G+oLVYa_u?^$Z6 zOWUqMvsbgzX-Aurkxr)_j%^f2T{2PM03^=kzai>EZ6THha1|J$GQ!HhoFJ(?X}`j>9h#6@d|H%FT%)K1?V`0pmq(dnC`WgL9a z(50(+=>H<$99RIo3rosJS?U{$PTw46&oDPzaPKg`gCjeAb2#nL>6^o8hfd!dPCIn^ z=5X4f(>I6H4xPR^oObB+&4G5nZ@oHwb2#nL>6^o8hfd!dPCIn^=5X5KKiM}2J}Y(l z=FsPCd<-(jVEn~T5>tK!ynYO5;M&m_1Fx}N!yL5h^vz*eo6!z#8?j+JeRDYN(dnDx zb9{45Dw-s>90ncx<`_GEg0WncxoOsdV&~;d9BFLlA??QATXcwuEr`w>9%A)`hohW( z?)u~AO@kMl(Xh9{-aK>F;C;ETKvO?zAO6M*o?UdHa!GW)uXND?yX#}W$1B95U;89& ze#7jXp+ojf8=8gi#w9&X__TK6iw+ztax51es9Vz2SmYdHQN5&#(WgoO?AwbDtY4Dh zD0;}_@tKjTk(-yLtk$oAic;sl0=x#h-BzhJKKj{6b%#lAZpK&~D8 z?w}9Xe}nH1KK^_;-yKJxA|Brz=b_Xd-yJ*AjQ^^L%#%ncn1#OVFHnUwrtx zDCXz;?sy1&;_=<_Jd1X;;^u|VXWTFCyQ3L7w)yVpi(U=R&&)t+@S6MZ%WMOW?~d~s zd|c)=7=`}WW?#4$zMu>)mW-y&+KP~#h-}_r+SlsZ2Sxj`zB{T}?l#{YEZ9HbyW>Rc zp87oB9Xna<4e4rJ>>!?kv~#|Va{e#-?x<%K_hzz{e6il){h-HpM<)BR&3DJqY}}{2 zM6kia7aJ1(XMA^*F{$TsCz+(Cg}=-8cp-O=5ohG$)mT>WrQ9=3r_T(pW2d+I?g(I) zi^q4zcUj0b-yP@CxXpJ5Jw1DTcl?zZ{Z=Eh!pgJR1+($#yu10scIbXS|4@&9S%RPd zgL;fb%pqyPRld-ZSY;y}`RIA>#%VOsi zgxOY~>$_ttatKb{4wPOaTn+gV3a>(V0+hJ4U^x4Lv=ir$z8Li$nYvTxi%A z(m$!kcL#lOwDa9TpBnJpaRW-%rvm+Ri0_X7g1zgzV;bsaM-L#u|AFrg`b9mp?-@wq zl)lT6=r{V_gmn_WJDx!SQocL*R`>S4J5EDOwfEgY53Gmy?%-?5<+~#<gODS} zcgIfGw}yOo>~ei|$alxJuI!JjL91t67wQp1WX>n!yW{#c-yKh~B)i@8vLiETe}gNB zBLf+JW2k$siJxPIxP?9ACfAn-%apYj_5U?4oVURHt-#M9#FnEa;LC#nddIqrp3rkn z-~*ZzqsidQgL;_^a82+!_dHz3=usEGJgAq+Y}W*Dx1UH8`SPG%Ce^OVK`XG5CiIU7 zUmn!U6)PZ?xV?lnBMT^LA^}gbxqKIzof~lG&wDwdYOdb7B$s=f2EClc`!gWV_X}y zUq1*j`SM_ZY)(kop#5gihQ9tYx8^fIHmxZev|kl%f6b)HFpi!_3aFRK2G?Yw6csRHU{@(3L$#2*Se=VS1CfQxp3co>1eF}ZyI_3ml9t@Gu=#&wb-zbE_*J%{A3m77! z6I>&_`Xn%mMpv_6;LC#{wq5A@@^IRv@LMcPcU#M9q3g@Tv&!D=rg*Tg75Fw&bbWa+ z1SxLd_$jdS9nq{TuX^MBgmDJ39pTG^A&BGp@{m~1QVg&)NeW$G9?lFZbbWa^)1=V# z<>Abs!bR+7`0{WjN}=n^!*jo>#_)C4)MKo`Ne~KMUmgrWX)a>n;LAg`=Gu5QLd;k> zi0RKL4|8(Dmj?sT*0lM7YqQA;+(jGLmj?r6^E+HRd85-_q!E`4`to3ijI#1vBXs{? zXyp3xV2F&0QbrizeIXROzC0Krqva_hbpK2mZDYCN%Yz{@YE2oTJ*sFlfkyD&wIG9doa}9U*ReT+Jwxxr8sU^BI72c|U&EwLyFQfHu2n1798tkjJUC>oVByA$kuhR7(9GD3SSqtScp>l5vK zhRA4Z$_VYTkw&gB4~C#UTwflZ5&kejOnV^8?Tq63@?e0{ecfa8EN#BQVZO%BX8>%> z11-M!HSK}N?Z6*tG?_-VcJFkAD4`?0M!g^u=CT$i+xZNE5l7?kUZZ1Z z({b6st0hhVu_6_~D?XPX2EoEOF?iMN1Q0BR6TqwUodDv(Q~5F!{rH7g&=V0?$MLS6jHK^SYN3~lEs96IRf@;7Vz46y6MVd5@O-jH8#{5yfYJ8t#I755EIIrk35ohG46Fa!EsD{p!Zj+9=-?-V`0uGHJrllGSzVqRr+- zu=urqG@+NkmQ0Gad-H1v0!P%<*Cj^q?W-kKb>%hdDiS5NrR8g?>hLD$e?!_$8=L;g zbZe^0N>-PbA5!-J3|}62Y4LxSFOR2;FOTj4JH1Q5@6U|}j__|784Gle1-ke*L<9cx zSm20s`qYSZ?;Z%8mlw!O?-A%eJdoEv(9_=<4Rjw92&5Nvqf?J^<9g$#mh08ySmV`W z2)ugarNalvh(KPyK+nQJ_aej?Wn#=~7o)v*k1{y!_`G-v+r@*Ij}xYRQNd22Lyuw6 zbboia`}n*xAKpZ(y;c-EJZ$@rcbsz{b81∈(zQ*|_@use2C;^Y8tT@Lk#7tv-&Q z32uPo8@BP<_jd0#|GPKQo0pi^lvSFyVmoiIK3sF?71z#d+OY}AdA+))DdTKMZ#n*X zzaJeee}{kJxibr~QHob>*OoQn<@9)wHgz*5mn?5eG&Yr#*ObWI@Dgx% zr{KH1E9;uD54FC2ZB-)m2J&MU^S$K9R;^}N@D=y*4HcyuS@tD{_ED=V89BRn?izvz>lF7A>*jYvPH<&-eRr$m5FKGw_k+Fppeg#!on$T8|#Q z89MjN+WPk0i5mcK#x>}wC~n7PHHpLYHgCEM7R{I+UuL!4G&VF=VV<;gD2?!h&{EZ$ zx?N9SjHH{^)HgPp(PT2=u=3uHMo+M&FIgC0IDOfi_|mz@&0fA>`jRiGiFtGT1TXmQr6%Bq$`MSL`$_75}jj4vnjMk%Ha9$HHqS2tl+tgcH` zM9bHdHuB*#fia(&D4f8~oLE;UyT6+g$jVGh*I$%APqsJpXa&AbJS5;O);}jhqOYmCV!&J{*L9o6!pKuQI zNrj6~ys9Z)-cpJpBofGh`NZoIEgY`O0hb6{Yn4?sFG;K~E-i1aN9*8I02V=%vbMAa zhA110+puhd@n46ZV9uB^IXYzaam%C2%-1sbxDlO>uV!ZHtC=W1XOt(Jn((w6oiw7| zw>1AQA0Ye&YI-LYmtMQ4(2?l-7iRb} z)4QhS+1>4kKi}?Y_p%G@-gX}!|I4)f;Z>wrAMh88sl(4Nx;%$p-<`QCe`*Jkqxn1^ zAiLcN_+Hn0_)|NR-1ywp)OPsITUNa?{$Iy)`1zmkp2Kh6NZY3HTloKH&*8W5ACjKK zZ{FzIrtn+ct^N>MYxY4`l=mxb!REcM3l5Pvqz}1~!Uu@+LH7%MfN+v}7h|&yr)G!z zf3V$rDDur@o@L!8?h)@1?-$ca{2zHX8MaLAN&H`&k?~4n%ZI>$B${rx^rOXN#F?V` z3KsECl$;Q&#TIdsc(!B)%#p#g9dH2-E5G|KYSlr~eP9 z9XkDgIPK8s|HEmAf7JiSEx4URzbn2ZekS(A4Vv+b z#kJza;!bg|__mnc!-+RqJVC4!8_9rWtruHK{J!Qq@dEKu68Y~EZU>kvLAAB2E+MhzrDJ;tFwS6oSz@Oj5T|`Q{eU>_@E`04grAo>{eWQI;DPCDj=}iLPt5KQ zY`9)}57&Vv8sdw|;jB9Vc7vjgcQRv*m4Lb!2Z+ed(jV;sAF+F}G;ik6@*KQnK zT6Z8l+PQ}tb`ccb^j`3!heyFwdN<(Ojl(n^L3$@2roPuA%$wd@NRR!*^5Ib~l^*YF zOpkraV^lw+hx@*JFpMY1hSzS_C_F>BMhav2k9F+^uR`Y@ZhE;; zc%vvG}@6Lkg*esj{35GK=zz(GEDgaDX@B3BYuBi(TM%& z-#kCG=-tON3X3n;v$fcIFT?Ip78%@*ueYvCzOnMm{n%f#-_BgV-|ltUerwo< zJr=P`{5$=R);v6s*K z!G5dy2Pkjz%rlVF4^jHW%*RlV&HL@vqi5P5glyjjA)oa@$U5^``^twu2}QFmz0$h! z?zCaSZPPyd-sa%tp-ZjzrulzmWn7cKZLhWH-79^WI|JMNw(rvP_k8(j+n&RY7XPJ> z6hBmKZ}VRnK|NnWeS4#>ucH0>pzVH*I@?!Y(bNB4$TzNVMsZPb9&&#kE%@AiYaUv6 z4K?vMd?gQI@=EWxwQ^llvvpt5+qjpS%h!)<1bp zYguw|>$qgbyyoQ1^Cl&SZJm&uftJifE52F1F8Lkg@nq}QX5KO@4XyVW&IL11-*0U_ z9i^Nz6Fs^TJz70?<`11#ZJj@J-pp+;2X@$3MrNk%*gi9T$7M5pJM6JLj(c${)!p_7s+aB$woXi@p?zkehj(KHy;Z$FnV2^rIj|bNjxxWA_DP#O zJ~Gp9n|ydZSJp5b<%;tc)w^!G6Id+WuJ z(eLxn@AEJ&Ccl6dZBAZ`e(jGk`_Q+iqfgGx9G{GBZBD*EZ(Onr^*R>){exEY!&c6$ z?nvuJjIv)Kt?|in*#D^d1f(@F`8d+pf_^^7v_)moH*XNqtw{DCHUQVLWMEhtf!IZIfu+FtWug;dr|g({mjZdWM*+DrDoR3Zf2&LnT63d6LsD_k8QI) z`2=RxSt#%I==C>S*JEZ)NX~>!1xC{V$Y)^&J^}d#*!;G&Jh^%DprlnjAZg7ToV2h` zZ=P3~+>DWBVN`8yn|amVnK$E*nRlz1c_B0N8tzRi-rQ2Q=KAyOAzh05otwUINb$k{ z{@cMfTkIo4`x+kJzCSIqP4lN`hZJAG=8g0Eo%`@R4bx!v=x_O*hq*gs?9gkJe1ZG%q1c~?RNzwTYYg!P>tXCm z3p~k?B&`QS! zv$nq|Z!NCjw%`l~Ux+_&BgLnk^t4y;H~1{Fu>IGf2yi1+!DvN@1~*c?4&9DWx{>1J zWky=yM*mO*W*&oF12<>?11}oA&rGvQXgqj8e$q%kc+pr1+pg zhelVU{()Np=F5jz8fw5qZuK*&pS$P+cNXxAjw902(@uvDt@i+$Jiu%Jj}RX0VOl6> z9u#yVbr1|UBhldKZoEbwx$(8|45b{?!X>B(+(g+>%~pScDKE&NNT(y=Z!-9}OjgXek@_9w#ggepY9m5ID6FY6+(_*~ zZpMw&GANz){(4tlGj-!sDW2}uc@oQAnz7P^hQcfu+(@yp{IPRwG%6F$s>UCl${{_i z0YW!BCksWP8>wp`hUxtxxIUNH%xF7{xxvi{Da}CIIX|7Si$=xg~DgDTn}W-1K?98{2sG3|tf`|(ITosrE5jEJSe5Zs*GO6ctxxLaCn-;#A?eRh`_xJi@DK}D1nP-OU z*y+Di+y&wBXePLkdc)NB`0%e-$X|Dz0Qh3d!e`U?jqF-eqZQ%rvPN%(IfH$%lJKvY z(Qh@_=thct&8XeYAGSmHZ}1QG=$GjT3NWb08pL$mNU?PyTbXW|Pld7~O>B(SzN{-u z71AO@kOKXhfiIYv61hypl~DQgcn8V z%Y$yD-ZA0hB5~%|;D%3%{Ec#>FY_-Zd`je0<_|Yg&QdZh@&e`cuKmo&`4|tu4Q}|H z$nA{Zg8wGZWc~{x%h-%?Bjx0OeB@=ya3jUWK{H2YP=*_++f9BeBAi!rBgLuYk3Hp! z{GJ)?_I2eP@yCAZi|{Li;LX15uE@b3do>Ul$|}K)6sNdxBejodz>O4LQpt@Jr-IW- zze0wdPBNl833Cx$^$-m5Y<^kH0qQZO%I(j$jS=H<*tQuVel`?l_2(!wlNrm$3|P)~ zWz6Tk>?XL8;)dq@t_%pq?9et`M9kVf(9WfRIUc!@Ed)1GP79_*X0e3_+ZrJuT7-*xT;RM+{fn$~qk_!%~?x?dixYl#zpuT;|FVtLK5> z6~5pFP(+?!n_lHBpujdC$hi+UQgp!Ji@}W)S9J;|DY%hh=WrrPcHBrk2Sou_9lDWX z=N61+OTdj3b9M56!;O@01?g!DZltK{ZF3ngqZcg((2sJw3o0jPysi@?qQiJ8Ya${=z9n#Dmxl*!RiDpMZ@okF3xczVuCq-Zv8^ z+!TEVt!+h-t7S(AaU5BNA;b(_;EOGVm2HP^MEZ2t zE_W<{2gPeRV=R(g;p=9Kbn&zS<@KX2yV8++p$vIAp&UbHK8^TTS?nmsQdvl40~FO% zHdUGE{i(bTimM!@i9VRh=b(7TQJUz(sr(ZZA5vLWis-9-UGGEDdZ7+Ia1N|0MfBCa z2$c{JZMCmAg#lGXmc7QYJ{FdfjWtqOQ3zn(Q7ZZl>~9_EoK~C##o( zE=t2WXes-u*4LNH8eFfUvcD63AeB!+@eq|eo#;nW*&o;Z5HM&6LJ)m4l?_l-Qh5Xl z3gtv9AA#Z?DrccFp`1!(HhS2HbI>$|*mX`hS3+?-l~19tQ1+(fgHYT}Wt7qDe5Ode zC45HZHTVPNNLp4x`E{IwMzBbAPVRR@!RM_(s1TLYX_<#9z{k5mb6Czg-+U_9Ls3KJ zb}H+A8C1Ru#WPgqGouEloD(qFi*OF&|4l>LhnA;7(L&`Vj&dlKPeJjRQL;u2zHwCc z#+iq6&L8ZikqqYlxa5l@;Jpm zf#O4)0~#>Qo17Aj$i^JNIiLYUxXIUpk*|k*rO{ysH#tMDC;q=87w3Qm4ErXhdoO}a zmtzAO#!+WRVFv!2fgVr?G>oUt%-fyNeGBJ+h6&V}QP2hdUlG7LpkX3)LzwTGkiS7) zDazOEl<&VGe_(VdU$axbSy;P{!8w5QxY;S+Hpmwk9m?12l<#%OzcMUkFA(;Xcu-e?xjTOr>-omo5^O&|Oh;~Zud&L*>N;+g}&ESp2QY&ILyQ(?Bwn6kUfqB*RJy<`@> zVa%u5ESW>OWUe!D9)$fpIEQk@Txa5Z0P#(#uwbq;QCFaC=inTQ^>UqAE}ww(D9$6z za=Fp8&}WbjP-j-ljb^c2f&U#_fb&SRSZ*|dZ>H(JYkrL%xGLvruj{>ts4slh3F#>*PkWOfG|N9?m1pGTCa%cisPC?>yk+ zsLr)Nv#Z&aC3#&WTf&m;wPfRhEz1=H287&u!GKM%+~fi-vSb_M7;Jj4Ap{6PK!9+8 zOMpwShR{O@A%qq}2%)!Y2qX?6_Zx+ryY=Ycq^W(K}Uq(NhAHQSMV{R!7xzo?4$4!>MCGeY%a}VUl^EcV#coW>$ z(eHfov$=6Q+}q5LbK@qP8mE*Y&p7w6sd1CdjF-cGG5u_2++-8u+i<^5KbshjwR8vI z2hYAZ_po{KSnI{p;GRN1n--6?9=inYh4iyo@mOn*)8IaZem`LTjCcI9v(1D38_*#)TPNzzX>YT&SAWiSo2?u5 z=Onk;##cYiSzAm)`|cQ4IQ#M5V~c6p6V9RL1&v!w;{rI3FfVA{Vw%r{^HlRf3R^6N z+u^*$ypYlsOX+uT{>Hp8TWzuK(yj+4Q=I)4V6xg`bLmhx2jRqARnL!rF>bD^fzMoc z`_E&P3^))rl=|}OOn9A))6HJvZ1#E(?mKY~WMAOz;x!Pg@@K@>!LL93rsJdJp^RTu z?7W)z=QaJjK}^Gc#RbIw=+ERmGvC;(_WjWa;_1WYy5Gs~ohr&J^Y?=%zCm^M;;Fs!_sQQYeda z^YfhsA7Xj!TPV!;{fUM2FX#z%gOI`Yg)QV^1|*w-k@$S-zyxvkRp`f4QN{RNjOT_q zrC?{12(n2RcJcZkfB!peELHjY7g$B0TKg1q@;m!AiSO4Iuo@U75NRDpIUYy^2lMefPQ(~XDj(ii*%+hYZ3p_Z z<>Ort@{=#j%8Ydqn2vBkopTTdnbG`;y496ud?*t`O^twK0#4c~;`dv0E4vP5(93Yy zQjWT=$BE`WYcnrqL&on)Nk=xOc)bv6^&U% zv@pj=g&Ak2p@G<7m$L|dxkdKQ+sq4>r^7vmP#XO3vEMi)(SBV-eJ6 zWq%A86VM;gPl;tX(NFzMw}cKHGXPiQS;TEF_H~xEN8mv0Fl$jxf#YJFXuav=Wp>@< z-2@%{9gzOyp->U?)^2(Q{MfF~n?_DSZem{3d_>#nI2=9~;)ITASxF5i>M z8BX^yL~U^($SjAQ2SWD*Qo3`Vg1)z%?n$I{TfSp1-&4u?PWOteVhE$n5Q3Af1I@M6 z#)mbyK7e%Enk=WEx|~iR?RPJ)sR2>#aASotzLf@^jvJ zaoRUH=MSKq|?@DdHcfUZ6Z0xY1<%Wh|7F&=AgFga6;Qy zYWvt}n@UQXe|ognn=35Hsmlq|5Y@zzjSvgOeNXpk-}n1tZk73EYc!>PXB#Q z|CC5x4`f~|oTf?Se5YvzHL-FkG7|)?priWB9wQT_$;%WJZAy_Pj|ymxgeOe0&@ zYxa}Uw_1gW%`H#66ee;W>E>!ju*Sb~wKR!T8Q7SO{O3~W=2DnQ zwr+=P3Q&oIZTT!ttPOGa(X5(XZ@X?Nu<*gsp&|S zWc!6{HCNUTohB<|h0`>J+#6@E_xXf=pU*;B>7wqAkvvvd2%_5&L%Db`cW>fEDW@`b zo#Bn^14xbx=$zQ^^8=wX948&UY$hu#gnD?mHQCho8BS=KPK{Mg<8;!MH#;Xp>n&Se z>T-Q&I|x12XNEXE(@3W$n~$9=Pe-{!PToQIe^p>YPh+>skgv2`RfAtEy= z6!F@zlcsv#(ja>Xu=T)8gZOc%R2a%DH1yCc3E0F%`-=)(`9XwNA7JPc)s(woc_c;L&i9j#00 zddaRz=|Wk`5jb~MN+(4LrJ5OtMUhmarEvAKt5Ud7mSUVsHPhy0*`B7lrG!$QuEgx? zpSxw}ttIN!jpSy!I0`ueN!}=w>}t$rW(KyD)5dy$Ha9|>>Dn77v`r-WkqvE`yjEoU zK}B|Q$8Sf{#yKU-Tba!;95v83h5Wj_WvBSuj5dy+FmGkeba6C5+f?%F@|M+xpVpK& zj&f*oKrd!cW z7kd@boko6Ly4f1$hlop={VPnlteGzM7HFGJ@+L0YUM>1orWDkbgR`xNM;yQKA4N`r zHat7pW*5^enPW$hv)pwr$h124h8vHLh+4Zmkf1!iU*EPF*Da0`xbO^tpvI1k-rZ@e&QKf8RpCm*0Iz290;i?q|>^7(*@ZWnHvx!f`j>Z0ViTi zB9#yClx&Ox;B5!f*obo$!XQ8HoUF`fC*d9)QKw|aT$Gg=8_Mv}QGYm?c|JNi5;B`i zXV%zx7m`qA{&LhzGlG8njly1wny+e&bNxBccrWJ^4NA_DaH9v+Enro@;U8ik4 z>9jRjPCtYe$V?#JhhFwMlKW=Hp-OF6Ic;O8?K7us3Mp-tw;Wfe<4O0Smwk@pzLW7L zklHSH+D22`t4`ZQ(rIh7ynTi|A#W4OA*Q)$1ESfHV;=>lHbHp0v|7oorpNt@Fz9#IgQ>OTp%)0++%hQn}5^J}+VlMJ|PjWb68l zrU0cj8lG|5$8x-beoNPnRLuF3q6mpo;iRVQ#@w|vG=C|eZ zB8E^84^%1+YJ3AHG+Mvxi#WU{U3uGnUX;~CEv_HF0wS*UzX49qbkgaGR92)4BlVx_ zx99Aw^3~2kOrFpBrUjF-8iOi!2uOR3|ZPGYC z67xWK+u^s5NK6TR@hUJbw<3S;jseedc)>e+++h&z&NcFkhaUs1b$(Ew@$onc&v%;X z(y+`tm*Es24gg3_?uW0C70nz5lFSsqzRyu#L?<3^WhEz36%YHa27gXoq0X{qx}-Bx zH2WR~e@@Aev~OV*&2&jJ^AsVEis8?x6_WUlH5DC@558>h*MC@BfDbd5{p4~5pw9*rhDVM4&;DZpd9)S&5$>wv?&YwYt@zPO&>5nf%FQ-Ui@J=mc0*QY(oLakRyd0gV z2)dvKim=VoUO~>_pi4Q%RVC{rF|{zrODw^~QcAR&6y)^}+6{rbCw2|RNKGLNd5J-w z{|z{}C}`0Aos8U$9!c2vYVho5@@j^Y>ZkBDS zF0Q6IteB>W3<*qIyvYq%Cow$Z8KzA6BIk=TSwRvO-`CSu^hIaDlCy7p0x;=I!7GD=eEDlwztP1+DEUbN-D+eiZcT;7Zc@GNMl{JP2 zY`mz-wRq2<+%!x~XWFQO9xW>{J7`*6SsB|Jdf6&(6(j5H5|mm>VakJpmMIVZPlj95 za}-z&V0`3rbS@3@djv^1dcZL`C_!M1)f00gHwKyBbSC0o9Ot{>_$j_T;g^p1@zX74 zeio(8Ad1Z4KWmai{A}p5DJ1;(vnsT_S}R#Q_R}mAek59@x!^DaDkC38*;=)$F0DSl z25YJd=l8)1FLD0Es7!wNjG!y~fxA;&2DjDZtp-?|&T!suu)%E~57~d3)3Y8!H2q@i zbg)dVQ{7<(GLM9n)+*2bW$KO6g{>;V>hBwQ+DJjqvAdT+xVibx+kyGydZnYpns?U{epBchqNd!j_Vz<2ja zduWz(cSqL7U#l)N9q;P%R+)8oMAo)Lb+glGJy^Fv@%$=zuMTf9s&%)+vG4zP+!NW1 zlZeAgD-s9`jyc*DCA?<}TVQ8*i})IU@y1=nx4LX=Kz^e+SZS?~=5;9ZZB=Ujtcwh! zpIxC>Tg7$5-ja5)JRFt(tv5yMzr88?nwz2l(fb|j<;jMzuO>FB=sQUZp=|HS&eXfQ zDKZIbeEY{S6S=+0#xKf@+VG~zl5guKh#6GZ9_H>^THOa(*Fr+B0Bzm;m_$i<4>Z5c zdmwjPWQp_&-dv*R;+Ww!}gXSJqoJg4cvDDjoy)LpF#v9X-J z1H&zuKDA6qo6kkQk!Oors%qRGJ?8IpOZ6C@I^`7NE()6*Cwry?f1e;ZDA6~_*&knT zaqCqJ#2fKYX+GVF{UJFuNbbQ`RegWX!j;Rhu@p9Z3b*;&u(|=;oy}c1c*y8FZtr@` z!im`ZZ1t)-?hIFFyJOWIjjf+nF4T^)d>n=?p|JNPww1+}yEG+T*NFYQ&+dexHK_Lh6{VN+dhwS^sVm#u~+tUBzR zyAHdKEm^U8f&OPD&}7)IYh}Z_#`?O3wcL9P`*dN8Fz(sKeFEKXy08sr8}`}17F(6o zEofS_cKOPB+s3Z0uE}QQgJIL7w)#U|^>^(u5Vx2+hOv2pF{qZc))AF<0>d(X}G z$@L3XtgH99dD!T|d!}uxbKA&$@Q}en(|sH3SJYz<%YNy@{@>XJb#A8rW0bLiP)({J zY~-BX$JuR7$J$-V+MTnI{S^q^HRM5i8J z$H9pWbXj}0UpC6a8Oi#k_2uPFi@8^7xbx>6%?}*wi;&rH7FoWk<#wMf0&Rx0rb9|r z-f+ji)|+&0V71q|ojQ-P=~O#(W;f+*IIwY%Q^NW}g=6$_&c)9k3)W&gKh(mqg{bWn zs~2K&j?5aEIj{$zjn8^+a~OUAEU&Mxx7Kp=zuWyUJ6*Va2qDf{i|vi!e6;t?w#=*x zH^OAH*5uhVG+VWpsOE;fdX@FCqmd#Ky}~i;|`8)W6icV zzjT>)6Y0|WwWy$ae(Yf1)5ZJ*Y_g3OmvYL<)JCR5)HS()rnTr)N7b!ZU|Z%cj1Dok zPvX~ZB58Z6wk%_&dxhIUqWS()n?Uk|Q}wz8JNY&Z`G0+H#~Jo}uKUMdcWYC2I=bRBgGj@(&n;I3&=n%|I1+&@*2Nndg^Mix(#-U)trb<{!+XPonwL-or0MigIOJd15?55_Q62~!NK{#A$hf_4e?w3)R@}D z!HGj!X-`LV*WmhqRL7HYPL7{~TpsbvV~;+PqTf*b`zPCb5|&mX2j4cz9$X>VGTdIo z$Ov#R%9i1YOc*cXcwr%W#A#Q*Xh^)tdes4-x%7`3sEVGCnapbleJox?z`xN)8 zWRuX%{?Hla>*H;TuLr->Jdv?4=2KNjy29}|Bj{#N{h`0wIh#ZG7t>M0jTi+rD$ z{tLxb;z=T36KD9P;*Z5g#9xWFG8uAR@%4%Fm7=ZOgPZ%R(0_(lC$18Y70(iXAl@L} zEj}T>B=WsQ>TQR+#;SUUL(FLejv8PaHgITv5!bg)$|`L&KA!T zn?;&jq}{BOWiFFJ39$B0ePkQvAL6iRh!FGo4OiPjRq# zfH+fJAU298iWiF4h!gNG81)_`E)tu>6U8e;npdU#1L8B{U&MBp_87jK*iYO`oG8u} zmy5@Ur;C?}*NgXxPm8vPCDQp=?j2%Byobj0dx|T?W5v6~N5wyggD^ca-hSeAakjWr zTq!n*$B0|RbH)3`pNqd0KN9~Yw#PeeOt)MdDDEfD6b~g)$MeL6WP4|_kMTFiy-7Tt zg#X!cpD$h{|EuJ_R=h#}cgk&hTtfd=`M)av*Tql7&&32LVCE-JEERi*)#5O5tT<6T zRGcTCCY~j36(13w7he+J5kC;W5Wf=R$Q$dU1BtUxERlaNx%-L(<-eEQ`--*lpC_qE~;^1oB=d&RBte_HNm#b3++_j11_ zzAyhj$^C`6L;m@=S!4Zl5Q|9ETUzd3Vn6v0mwPX9Klx9RdzyHl{OjaiBrcQxTDdof z$IAb7xz83akpJa!UnTxn{{JTTo#K7+e?so3#b3(*w{rhpd|UpX%KaztukuggUV`K#oqECEcbA6Z~2dtdy+U^{)fq3C$1KoL>jkb`lpKD7k?n$ApS&rQ2eR* zEAd6~9q|M4ui_4|1MZoaUZGei_7QE5SA_2)_hfOpSSKzLo5Z8VQ^hmIABfH3wIu5I zCK8{8w~BWte5=BLCigGI=jH!9x&I*AUbE2mN4ftjeo4YViPPFwEERi*H2lf%q2g$9 zym*Lsn0S=9THGw2D1KM`zW9Lnu=uI?ClT*eS^Dk7VzE^0Ck_;ckcdmmqRjUJ;yC%w zl=~p@Q2E!(y!$z3j1$lvz#Mg7nq8|!I={11?OtT;*jG@?qmx#B$e zFPD3z*eL&FKe<$-eNy-h&V#z`U2iB zjuz*NM~I8XW#VeFNjyzFOZ=|*eeoyazlpYD4e4=Z5Yv5J{F(T+_`djw__?@4jPrXb z;&&6fi@S^c#UbJdkxOkEZ<=_pc&Lb1%`AMaxJle1o+h3pUL{^D-Xz{C-XlIBJ}15) zz9!oDYvk)sa(^Ml`283D39*~lUEEzX%R`W>m3y4XRoIL_OFT@p@8|GeBKMIZ?a5RA zMDYyq9PxYNCE^{Tt-3_Khva@#d|G@~d{O+3_=fnl_>uUD_=WhDNJI9_Uk}lq1Hf%- zg25s3xAn(x?=Sagk){k7->evbhsb@HxKLao(n>z%j~7o9&l0~UULxKm-X(4o9}%Ax zpA}yc?YRWfc~kCp#ckqeVn;qtfLxJSCZfZU6XMh2^Wsb5>*AZ@hvGJIyZEJ;!{;7I-=434FcE9+ z-Nh<#h`6`7pEypOB+e2K7P(IW^{*8-iCe_e#IwW;#f!x&MD7?xJ>24ed{}%+d`5gh zd_{aid|Uij{8Y5v5unek8H2R0P5otJFR`y!Ee;b$i8UfOR$%;j;u7&l(Vi0_e7)SK ziME>^{O!3Bc(MGsCxew+d`x^wd`^5pd`)~qFFh3U#A=ZneOSIl?(sqQ;Uc&9pnJV|oOptGp?I;#oj)jln|PmS&jaEAoZK&n zuZeGn+$4nYzZCHfpSjzK9mOJ%8;DSTusB*AFD?-4#Z$#IMQ%32_&*l!7Vj5d6n`WB zP4w}dfbqC730W=<5{HUY#hGH0c(lk(Oc?*W;x*#Gh(8q{7vB><61m|C&(EB;>OhAvFso>zhG`1}TJFLn`k6UT}Z#Y4oyM0-Ak z_)F#HMljU(eeoLcU&LF)+eK~?L;1Hvd%gs>JzoNM$Ulzne3Y~2NT5AO0uPY?SaGU2 zQ{?6{jAze}z_aB(U*twJ48K9VTfARm&pNfx*+=z$r_Iw9?PwtOId%gpId%gqO^Bk}f zpO1jMiS}FvZhMXc+H)LmUxgna9wgfH8-y>AyIwq2JYGCqJX^d-yi~kWyhh~iJ7l@aNmy6skiu&#o9}%ArpB0}MUlm^$-xWU;xz!Z)<%ylet|H&9VR(hu zU#t>Ghl-OD9CUzHh7yFCcN{jJliHC~w#3ka9;wEv6c$#>Y$Zfc&?^f|1@d5EM@hR~+ z@dc4vb}{}}VgfIB(VZuD7Q2dl#R1|laiqxYz8HU=xI{csY!ugvr-^5Y+!~DWuNQ9> z?+_ml9~Pe%UlLyz-xRs681)s1MPiAV7JG>!#J$B@ah%94$*Av0u~A$v9w(k4a=S9h z-zwfCJ|I3OJ|%K1Gs=G{=HNj+-ML~%u}G{CcNe+s8Rch)bHu~N#o{t?y|_{27HN!s zm3X~)lX!=CkI3!QDF43rsrV=HD=~&`%_zsM)yQgbq&Q0CHfs!@C31^3x{nka#q}b$ zTVwcHBDY$j`)ct<@n(_Rt}*;Ekz20O{kr&`_>uUTxLxFKYLxFJ_7E#YZmq`feZ-04 zRFV6vF}z-E5|0+S=^De&6@MsRDRKukhTkndF8)m9c5Dp)gZPQ~xyZfQ7~Wni6?=%> zsEy%!ietrzB6n-!?@&jG_2P1Ijkr$aR&JC(SG-8PRJ>BWM&vecl>e#tl=zJJYw>0A zb@5FRj|IILo)zG0l9dC~wtXK-lhDh9<-_A)BOXgxIKIXkEgs}>8)))-@plEthtEHL z!u!K89Nz&4d)Z|ss zqpHnUUin(<*91r3h^@jhpsZ-C*KIuuU0lC#-BPSQTCy6++x3El3$b7=8j6?qqs|3b zOtrKgd8Bq1XJ?-k%U9Kh8c|5EYSHSIE9+OGkl9#E8W*gD&;hfiRxMb&wsASumqG0} zJ}^DnJH~8p9>W|m|IuuA^u&MsR7SH_cC?mb7>_RWr!!qI0tAW1v za1S3IVc2=_i0bPLeSEix`lu(=cLlD)IJorsVIJgfbm0+(-3pKJ+QQQKtrBB0Ji@S> z;1NxC+iG~AF_|ugZ6@7^a2>|MrT3@(@tMI39bwr0aJSHRhUcZ>M}2rCmeKb-uERLE z#BR|}j@LZGuxD`{)z|S%moD|;QBg+U+mSf9^v2a-W8flQxg*r~2AolSHPA<0Jn_gR zqwiB(Gfr5>JrBZnXEuZmhVlHH7|N|Z0?%S4Lxgg$O_nJW{Xc}TK7I3H%j z;TImEKGsoG?lk1DPZ)@>@N&?|;d`Yc$Kc^3hExx)t{yo!ovt>2_kVD8^@tH8(&@p& zM-Fp7^Yb>3oiffhi<&NVANvl5dg-%$FY^!F+|d_hDe>OBW!vpu@7O1?)PCE$)C}3) zrTXgJALP#1-fRAh?Uh?=wpY%-*8721v%S~WoT0C%VNW>zV)#~ z#~=3itSf8B9r)%;+wN-^-!R^L@G5=>wXEg%i}4x6&oJA7-uxo}Vt!%}0%LyeTlje( z{s!iR*q$Y$ArXrO^UxG=``LQ0-3~UdQ%jc9D<|Ol&vAaR#-{Jac8cXB zui{S)xxpH0%S{eOE9K+_Tx^FhE;ooL;T2C8?g{bu0LJfCGzr(i4fNm-8Sw#y=$2l5 zHA)e$E@J13<>tgq6#sH6c6$e2iJXt{KluV8`0>Y)wO~MMIin3lw4l+hbMHlHqTVmQ z7y<2af@|Y@BL{h3U}_AmD}d<~FOR?c1piV6Lnsb zJRjb%N-s4X)f!wMlprWpnd8L^F&2Uw;*1*SPmsY+N`C{<4mpXO3n=5~eviJqj$e<8 zNp`i`>Ua>;mLvz|b_7!|Vh|(;7xEfubgDbbOAb+rIjK=7NODNN%Rp}GV&pnGq{ul7 zQb(XllS4|Kvty^a4PJ6+zOA{aEJ8(Hk96}d$3MRIVP(T;I~5vxCHKs|muX+XwD)Qk zmhV;gCHIyyCv`TR`^cG_x)fzej*_z=^#ux_+*i(ysSla8{p2i49l^N!%UP280TZf` zvn<8mBa;Wnnf5yW7`2w`Cnx1{;YO+tS~WR2&lYi@)}LY>Ole1FymE`5x{$%s@>npq zW2xbo*^@KnJ}KtqpMj9wAZm%KCV37zVW_L6tWm75xg zA|~%{HySEpl?AC+nbbXUraILvT;e6~?R280+%YwX!uKg|NveiL{AnI*DOOpQdVryi zmOqZxja8;o!`Y6Hmw#%`Ua7gP+^5qGf5#gjRJ zj}F5p6kp2t8)8MBEdG>Y{#u>Yn_}(k?X}9;#azvjY>p)#u>8y^=D14! zC|1a!6t8?DR(wAbxH{IEVa z5WgHAHv6*|+F-`?!Ere!bYnb!m(|$A?{+&_vIGSvNLKo}S3{!M=91oiCps|3i*I8M z?e43GPtF6Un;r3pZo7{6>}*_vc~UB2USsJ@_^8tDBhPf zSL=7S59P`NFP|4XAf#;X_H1%XEIAt0S=+TFyN?R(TYpd_VU(B-8E;zpxoH!L{(qJs$tso$D9gN1was zb01|c@jD#>N5GH&M9!TE%; !r7CRw*!l*-+-ecjh4^rUCIF8&wmlVDDnY1P~PA&`b%VUD6+!~ zR#W5xq@FjtjQ$e&5iVVRVFCLB%It<3&D*Pt0g`zv(`MA)bCem%GR-StfMk*w2Cm#OFZdH>rm-CsmM}mvdt_t+ zFX#qG#qH=sc}q$dAereInS3wUk1`urH%FE*Kr(zq$EAhJSxA`m` zJ4G&~$Z;j~mq;ZZ<7DcuGaMB^W#2lXgaMKnAIj`N{f(f^PbhOr2?Hc^R7M8%cPM2R zqN4N8C}DtP&dtc6{*I%}Z&}CZlrTUtTuPUzKd!T@*v$64po9UwUjc*JUfx9-suhEn zk4rTwEBbNdT&@9Fkwzi&uF_bm_yM|m-nAN46{|4mpndwRhpiaf?9{b?!v zCBpS{me4P}pqV1$sO5=L`b&gM>8yV4M1OynGLNt98?NY755%l+?AQyt+bKb9%Q{8ENUXk11J)9-K! zy+@&>U&;^(amk&l2h``G6#5MdS>Ts41Rt3Dv*UL1RWIc~WL~=XnpVsCW^!KF&}p+Q zU!pRNJ9>D*jnv53ee=5cB@BVa3G6?mq0?rTPoi;NXPlX=#~ywOLlEZ>4v}=mc{Fp; z%hw<&znEF>?P~;;^EK+ce!hlD`7)NEzppV=egfOM%GW?C=R5FugZ${{&F0Qw3HJ8_ zzKd1z6P@LPutV(ENNot9%~wJ=!l}h=k6~2%$cXqmWOb@qP(IP#@#jz!SpOv0lKX zc42+o$|&2}>Qnp@20$-AkKYbuP#;`^SI%`Oc~kuo21q6!kDD{~@dbrCG3}Xt2}2}Q zoe@HP^njy$C>wc}U&0Ux@ue)M3H33CLOq$>!F~xtB(yOjg!))cp&VBKA$|!%B-ES{ zLVcV=A->R`cbH$o5Y)#>tmwmA^zi2pV)cP2T&`DsJd3f|FJXZ6{wX5!Hf2s^H(%zL zFaR>V2Q0<&YAXfqL9u%QglZ|Y(l29(6xBq922p4fd+Zv&gdq@OZ>*0B&8E;+HsdE8y;{$xHp$C4`k!{N8X^VnX?pw6FC$ZLN_uQ%wL+L@mx{>)x9(%?@kd=*Lf zvwAOpK*0?Nslqt`XYYmZ=|G=pIH%BOIea?PXFbkU^jW*I0e)TRcQei#apGo~&Px9) z{P+91T-D(E8M>P@x$0NQ>o8aSTjXkwNUjDJJb{Q`;`{<9b2YF7ebOi{Z$X)>ft~5Y zRdQqKW4RjGg?`_I`+S_p6`h{n$?u&i%#Wu^QwJqF`LldmiqZ?4rSAt%d>`!U#Z!Cd z?~}h*{zP=*9EIfKi@@$4eG(lY%Zp?oBuAm<@e-Ov30#zR#eROi)8IoauYC)J`My7~ zkp2Zdp>9wp z;1cZ;SQ)xzB#~!krdWwu5vZ#qlbR%UQ!eG~rb5bD8jX+dd`yvg%ZEj(X8!`#R(Dut zP3@P@Iz&ztzeiulmEnFWZ5JqRPpckG`4v)O4dPT(R{8rEgss%4pp)O(uStBr)>7;h zM5;T6lJrLWOf|(4ch+JCumi&yL-SbsO=&-O-I3$~qJMbcp(`%aII;JmH@H`$S8-u% zNN;|Bv?G=YPle%?u@(}Ty*ze79@NE+YRM{`*mG-dfC=NW25{+Tx37g4w)@7zBb>f> z2;rm;##QEMqclYntHIf_G^i7=0%u2WUA8oNJ9c!7lqi(x9Ll&7wUA<|F#GU74#r@) z$ZDL}K$l?I;@-OBnzMyGD4VU8h3pPlSIEQLC}b~$#&BXx+JFA5(N(P&qAmaF$Zy=+ z4=Q5cZW{K#Xw$HW$+RI=i_owBhjt7z6K;4>1U8lNg3OBgCTuIlL7UwrV-G)w+g=xb zd5~8bBog}-b_vQ79R>!ugL(u-y@R}g@N~NskwuA4LB}3Jssg^S*$u1DU3&(}${?={ z9zD&2V(~=02|Gu{+oyv7+XBG32KJ%jozm$Tw)c(f((#PfIs+BRKvAMYkUJ2m^#={|f)#9!T6BpvEOg6KwwW$AtFY1J zT+=WfZRDC&?r5;pB=W-~cVVo%jb<2u#xl#lw16Bj#w!!v>UHeE?5Sv`!6TT!PL{nR zg4RQ`R+C%wlwDi;jy9)Ki4e>&E>yd4PdS@N1=B#n@XcC+kqGd+{trOH7F{^&j@&?n7 z{_a|BR~F4%C16F4`VASbYB0;^DvK)^2aVb34y}B*(P=bxnXgt_Tez+EC=@B5D_mWj zGo+p!4k*$8Pgd2V)yA&fs^3{h=1BjKm|Xw+rq&~!Hrk18?#!4_Z<#gpv#dq+Omnqp zX6vpnT;9sQdQ^|~HVRvxAuYr%-0P0$%T@R0!4w5E{Ow;5=cw(cdAlWd-GYuLgr{Lbyc&f3~oyzInh z>z+cg7oV+UjQm|0kKc7A+5J&dXjwi|SXV94{Gm-by#Ai`dEDR3s$V|^TaE0>1brkG z^bAd8W@3G3WArpZPm}N19|5-^3pQ{si@FsfhApryE~44P{J+!iw>EcoMxlXv6u~~& z*RF&f>~+whkFa%Zz_k3VZDFK7yuOAfSa3^c_yKYOn z1^GHt_q&eDj72NcD$eEBS;uc9DsK#TZ8N`(2;sQo7;GchlKTdh_QM&7D+yeOZ_!%O zVz`@i42E$-S`aNPE=8?Ca91>DXFb}#4EAu|oQ z!NC3ni`@2TUIL)G&ko(cD`jaAv_&SGQ;bwtQ%+ug7)prAH1NQayO&z%|1Lu3T{B>c)Qm=y?CW~v-ph2 zpLnUqY^{O(U7qedbYYUOH<1U53&lq91n~m#D)CnFVevWf4e?VkhK^4Coy7`qh{zup z7(Po}C^m{_vmW7Qdki$2_23-}pNk*&7~gDvfotVHN#twY48KKuQ2d4XJ24NxSy8T= z*k9aRoFpD99w}}V&k!#auNTc`J@lH*deCgvgJ!cHG@JFH*{lc6W<59rQy%kkoM<+& z;C@o>7sSuR8q6h>H=Fg~e7VhLJ=`ng-YlLho++L$UM&7tyj%R4_!qGZzdA9!{l$gi z$>P6=KNrnbJmkAz!ehL>#KXnS;#K0K;(KCy%!Q0MSUgBPM!ZaXP<%rSFn2PZ*(wL8 z%DqPXo_M$TxcF=F52D#VLi`?N8_V7O<=eW*B3tQVJy_I5nv*UNpZc)V!$DG2Av2Bvd`c(sU+CtGW7 z^^5SZe&KEM)(-H;$Ar~O*d9}PUjhH0lc+CrW81UH;=_NG+%<~#kF8B_b&Hx^Y90;1 zjcR1g_y5Y3=9r&RPiT_NH;iGpjvlCHJ9^?j<#79DM{7BT@#uq-ZT9!%20*5Dx;5|% z54Jy#u{fi0YvCTl03D&+Lb$^`Fz7Cv*J5mkM;ONYe%umxH43;31GxbirYQR)^)dge zaE5Vk>CM9zodOlqVc3~)NA+Di(v2bN!!(-FcNMO~IJorohdz##@Cd^$heuT3&Cr*IANAo@A*1g$ zT!(RR=^X-n2ZoIu3FG_~)%Ps)aja7xruU4#t+=MXYMeZ-?~XZz3F=@N&!35*TpAr{ zy<~_`?j>D^K^H^r@X!H<{pERFNAvf3q`dfO&E)SbT%&jmfE}MfU$pNtT^?kldw6{Z z!cGl5`8_$*$MQ4HNOgG|(Es*@UwDN2aNE&B&fClLJ`aV!P;Su3J@>LD;QIIX)`kzk zBerk4Hr$(R31-%Ycf;!Nf$wdbe)7#za`8FW)4$-V?y(DVKJioW3kt^Njf?%zAKZV; zllV*;S8{Sm&fuIOdoKI+c5mxrIQ=oPF@xsEhNYH0x7|DMA)Hs=+I4=;2dSXjX&-ss z2SGv3aPNDu4^n>ohfjL%crSSVCpr1v2Y$O7YyC^SA9^1obG;7|dC5<5l8H}p68U42 zV-jO}jtj<|I41qlRkd4Re(57`*T=wwX_vb${v+Okg(%6W+ z4{~y+zyCb5_pF)a-S>&# zq5L%OgX1CH_hpnIl_*Et{8+DRYEvHs?fegd-0mnr?*^>rzXEIc8)~-qzT&X$y=KhV z-mhV@x%^#+keC46M>0TYg&Mm{*@;E$tk-*g}8)va7>)(COV+$nj|#ynq`D zJQw!ZNGHbHeXg*<%5uKC7$1a*H@kNK1`L(>g%~Tb%-a1+ARHe6McK9c_fU%KnX+s5 zKjc@i+~7{!9boPLzR-|eyZ<|+9xsGfxOV>-#*ePuFJMlzcK{5xrbI;Yxe_$?!0!NmP^95`?R|J_t)-okAcYA{i9K>(Y5>YQFY?ArbFSh?A?`%77-e{k*oZB&(A zyC2ZG%eDItvpZ$i?sKz>$lCp`49%|Hry-ABuifXuyMJu${>f;v$l85=JBzN}zmk>l zHEZ{O#DpVj_a9|fi>%#WM0aHEz8M*atlj6D$mrVrRZK6kcHb;uMAq&%alA&>?pLzX zB5U`XIDjK-_urwu$l85cjE}C}@56x?S-a02C8KNiIj&l)-G7S-MAz;=O^@i>{V%98 zx_18^>iFkgyWh-e4A<_{_&|2;zRe|(wfkSOh9YbC$FYWYwRWEy%VgK?uVrVc3D@dl zF*u_}*6yFmn)_yJ_w%VLvUb0O{piH(+I?CVi>}@0V#es&{p*-?WbOV&>Wi%1znk+( zWbOXVY~{$>{oYJ3vUdObl#i_4KZof>*Y5v{0@1bm8(G+|UAxa^XD!z5cgAOPi?#dR zI44He?(=>97HjuEr^J8J+Wo(A>_yh@b63oNaP2;4oy^+(HLR;$uH8Qwsr*;1-8bt4 z*|qyz@!w+Y{=+CCY$^R2x$DmL<*nB4^HKliH0=#|=^Fg=)Ayj8VeS45)N*9){%ugx za_v4J;;>HJwqh`fi`D$}mk4*W4VU6^r`rlH&BAJa z`b*??T)O;X0o~Pa}3KguY>`T*$o53l^ZMfa^a}pPe@qJ&j88LT8fjwYV-k=If3=J zq=W&IS&)&zvg8?*fpI9V=4XIpI0&5{R1T-{io@}thSmHwI^Fue>);*M-^CPpl9kg~ zLVu{?62YH^BB(#^p&PE|r@ur#4nNU6AyedE?}Ox%ea&cV|%YcH(k zpMdL%7>jmyDgBXcihL&&L3?rUkc$2+*#o8Ym&oOz$evzs4n>}0=lN+V{U!2HDDn$0 zxP>BoY=zbQ^q0t6xU}}-YX0Xb(~14-=cNpgOglW~GMNVyZ(Knhp$GekmjGD4Vsxq)suEt_yPKSLyR zY$$|Z?}HT->dO*fH9teJGPylFE>`oqdMSU0DzKX0O{?Wo*vYY)KQhbyBGky${M>K1 zd@oiTR`W9i8pGB6&S}#|ytC)Z!#JNZjxCtSYJP?w&SusUR`birNtLVl-5@D{iwR&g zzxxO)FJq>#n%@nR@)0ZnR`a_tR6d>UjMe<^!=ro&HDfh@{{*a*xw7bz)>Dh z2&?%Sg4}TTE3W2OsX6gIf)H!89T@(MLW_c2&CdYTHD%rnWj1@kOO*MF`NnE~21uqo zhK@@cjrJvl_GQarH9tcnG$bR0=I;qd`2v;^tN9rsp+ho4=;7libRv_(YJP@DXj4WA z&3_byj$^*Dnx7#Ox-uh#`Z$k5?J0!S{0u>ToXrZyYJS%`_F4NpLc;oZgi&%hSz$Fl z1E80m$J;|0)W^G&Sw$JF=4XIpxPeNhJ__I{AI!9|nx7#Os?7+YKDgCNIojA(^D{(3 zOEW^KkAo>RkjY^+KSLyRRz?W*@f`}80UfO7XNZJu$q1o7uAmTqPULEShM+!v$%@8m z{zwmh6CqX~h{8=)%K26iSMxJKdUNr^b||x*GCyZG$7+5CK!&UN2jbG|19zoC864%b zD8$wL43VN)QK17UbUJ%1R`W9iLhOx4M}?M9s6Dfd)%*RU_@t<*A09pTvh1ws#O(MgSfdqe z5=6$~bOmd&g3&(fQS`Hdt+j$(2={q7U5?jVUifX{R{B|v*ISOCg!^%v%<=l(%-sf9x&r)}Ex3ne z_E7{sgwqvZfcd=-_uKTd0t~bQbU>7RoUQF?Qq_J6Z!hq00Mr~{Qt=SLJNxs&H%#hQKJeniqNMG zLkWF%VQGOK2?sk=XhMNA6|Q^HKYC!ymIgw>5)+z5ghI2TLb&VX zLFK-8AiV!}8L; z0pHFw?1#mN45wK|iaNZVD9&oyLh77+^VT=i#|(18SnT2wvP7~oxG^PWw(?3^DN zp18wNym`2?gAGCNGMubd)}T|JsY`rCuw!QtcHCA+HQcp0VMm2H(k>6a9JmQ*%sX#7 z`G9%PAzre}OhdD|VmMh%;lcdyV4vV|sYB-f*M+~1c`fek3zgp*CE-#gtSm{_YZ=qw zBhxL`E**}=>xVC0wCHdM4P3Q)RsF#F1q+uSKC)^^)!@UIuUfQX-Qs$0(cXtQG_GEX z-CWX3mcwXAy6=XOBl;b_bk(}_T3amjwJEgJ9O`stE+#64*2`r6xonaQ^n;wj!on_v zfuD#U;|HnHLFf3ubWj*SB#o7XaCQe{DoOpfHh7D-Ro{7AyqNPePYkSGoEyjV^w z5zk8pNnXW^{h+^j6$Ty29?l7qCC=58Xw%gz=T~&yAK?f6s489=#;6R+=#hvo_k(s8R2;^t z3<_P)5}!OE7(w(8a!jnDDi~-NFp^?&@pb8-oIXAAW8f1&QWP| zuTj)N&U;AEi{66*C*3{FQGBlACAv9@o|&XgO%Ym@7ZpnHNLX{J2-*)0@=&Gas1=lr zm&LfuLwmP34hnjKNQ6P%TLle-yN?U%(;^6^OcVxH0}-nts6vn*FB&xpGg#C#&1atV zL)Q&Aq8rv)f6GV9S|{unpPhzJ*z>AkZYF-rs3322P&_1PPu*c=duB4-9my)lWwvJ~ z(|xi*F0+GzFw<2G>R}3**}OzGGmV0=z7p|Oqjv7&7StotCEM(&VF&KyI$Tdl4|W|F zX|_<((@7zH8&D{m^~Q|5(se<&t>M+tIZ&NE$E|h3M0~05I$L~w*bnm}z0A5#JYU@* zo?oS&R2c0^){imL{rDc~)(v+rT9FfoW{?eNx)IiNd5L&eKj_voD5}B~vLYRn#=AiK zuplR1pAOo^OR9oyWkKiR5T-}6DBj73mM-S@M+N;+(daOFU4vx2J=-C^8e@`KEgv4_ z#aBUB@3470TSH+K7||i*P8%l&WHK=nN=O=3A}0r>#=$}VM0^>FVc9}f5|yUOGU~_6 zF*a<_paR3zD6-BFwhk1va6_T%EL6%XC??`1Vf!Ef#jtQz028XRQPFCJJXc2JbEfv6 z%j6Mq6kYpS$Mx9X%nZ`kuGjv*W%KAiXqgJ1;nB6)ToeAk&Po#OK*3H!?J+|dun4}f zzG>ZxwclDyG7}%sru}ELnACdQ(VSCgW8#0e6(#h?18H}`88--RHkf^uZ>=c}T)D@R zhV;Oti;rH=xMbjv^uXyu(*u{RT0IapIF>J3J8;2@Co2xnW-ua`RBK_ z`QK*GcV8&OIf0 zYT~ru^qe!|XTsjn0jZI(BU8PivV0!B3)$+}v{bL?4*`5;-KH%34;YGn3;3)RzkA~{ z*mLZ_sa~Rea%#I+UZQhOk>ABHj+gkm`Q7|dzs&C*qlKK7N7N(7`(#HnG>)h7(Ic)W z?4e&APspQ39M9hIqDth*K8vR(Uf^jJ9{xn&qR=)|%lL_iF2;91Hin*YTLBun7@n7P z;41ERy3P2-y;SC!7jaufoArv@FCkHPQPyGdEpr#gFChF4gtf%q5~8-7*v7Qow4cJ+ zj-9zGy47tMzTmcD%86g{TM3%gy`B8@qiFV>klvGWzbL*cek^__vSOJ( zv+o3&eJ9ZDJAr232{ijopxJi<@dmNQGrI|JH_L7Io!~b6PN3O$0?ob?X!f1JKK#`O zH2Y4V*>?iXz7uHnoj|ki1e$#((Cj;bX5R@k`%a+QcLL466KM9GK(p@zntdnG>^p&G z-w8DPPN3O$0?ob?X!e~zv+o36fnmt}ntdnmBe~7K6WnIs2{ijopxJi<&At<8_MO0b z3|Hzg`%a+QcLL466KM9GK(p@zntdnG>^p&G-w8DPPT)ceZ|Z9lPY^E5>^p&G-w8DP zPN3O$0?ob?X!e~zv+o3&eJ9ZDJAr232{ijopxJi<&At<8_MJep?*y8CC(!IWfo9(c zJQ>q2%W3wVK(p@zntdnG>^p&G-w8DPP9Qf=VZ17Frnpx8zIdWTc_7UsE6U85kKNDXT-w{6- z<9L&sdOC?c#DU^I;ym$q@oMpL@dL2~=5*>CDjp(!N4#8oNc@HPsn`W^8GkQvo_L~o zfq12Ov-oTAO|czbB%q!Wv5z=H94pQi7m1DH_r+_)r^JuNLVWyE|48u&@dWY5;vM2E z;#XoNKF%3`g1Az=K)h3YOnhHV;e(X%hKh5?Q6&vRz4h#_TEXqwoV1K3zOi{{9Zx-zTzNps5nua zD$W+?hz;Ue@jIg32SV@Za-S_;E?y<_6z|6VzoF-+(+DBoFGmS`HD2-uNIFMzayR~o+_Rra&KtH`+;cpn{Zz%_x0i};_c!C z;=>|e$flm(if@VUiQB}_#J`F=M837naoJhyCUzHh7yFAt#1SH2>1O7ryC!Tl`r3RJ8kKgmYCc<@h={ z*;VW=R*3z?fuh|x{GND;c%^ua_^;wE zBHut~e6AWKpB0}M`8GQJKNde1|043ubcPp-cApP-ce(kNI>U#Hqr@7KZ>%%i?*Bo) zuTJ+$ah-UK$hX%Sex7)-c$vso*%^MfxK(^a{F%r_hm?C!{EhgA__m1KbF*WJ+Z2;8 zA<<50661si^+4Q++hhy3c@J_H4|4bzH~A^-H<14o^&|W&-v5W;xW_R42(O_$++(C~ zh1}u%_n)_e$M5%T8^WXQ|6PROyZ*N}^3W7^V9K+j5B{^=F(m95CWZ**2Ec>Y>{C1_ z_c||hun+MVhchZy1jlt2;{Jtl^IOT?2f54IkULItVbC1(!4L3x9Ue@J$3~p&(lt1F zY}y;;!uKkQqN`dTXF1Qn8OFh-H@X|{XQ4AZ!Z79~yk^*$cnkOQF!PbHi*X%I_at=s zXCcRQk$fiI8zOOV>22wmwKGR|nAVSR9o08`qUWXIM|~WZ%mT~t0M0NDF1?$fFU<=b zVc0!zNA<0RzH0bUAHGgy^gWB~Fb*!gXQA&+R-BG7>}j~8`mTmPj(h6kd=ci4&!iZK zY4NzNpXc3!d%o~s7|(aaP;S+pZQIiOOmcu7Z$j?8&;c@C9@}t6^LHQeN8QXH=dmz< zJ`zWtZ-AE_Ye#-FTYCS8y)OZ*qB`52xpVK$y-98s61ePKNI(z*gnbDZAc^cdh=PWY zg+$0=7C=N2tqZkkfw+Q-wPM|>Xsuh_mo8crT-v%|ajOez(ORXYt^f0!c_z7lwzl8j z|Np-K@4&gwdEax+d-gMvnK{qghf79emvnqEV^lxt6b;;z=C6TSEm*yXscvj-38Jk)s=N}k*)>Zf&byoUj|Brrq zaKoK*4uBV+=R5EDZt1++KIT&^u-_N@i`Bo#>iy*xfBQ1D-yi4$e}0iQ#5xc=i#mH^ z!Y6hDQ@pz;a-}uEI*@qQ)7JE&t_4nO%GQL|u0^TapE;PlIW+8<_meWLthBAc)`V>- z+qZZ1wT8C`x4rPb_3hC1*2&g^k6WIBKU%~xz$JyR*?TayIcZ<4Xh4z4{f_I3ZYi=y zJKN_J_AKbJ`&aK@ zcw^7pq7#dlb}w?IZL5F&f!kWB$uF9wH2DX1wj^C0zUsyIEqij&45PIty#1cf{^Op# z?^VGYWjI-z0^#-Px8=V72TTkdj-Iw%g;ATAM!`dpm2)nzJ32-lZrk@e%=F{Ru%5U}x8FV;p5z5MJCTOx$OGJd zeynBS_8W&7K3^b)s}$#5%n9)MO-F2>FCoeZ{=g81Ol7P&UCJ2ZPdES-IQ;rx=>Uh{ z-AL8W;kOu39NxzTZ{I}v3lR*Oz9mc=^1sWFKi~&6eRo0?@ZXEy;6T{79d308P2W5w z`x^u6jXxobP}20ZKo{}{ZgB8nPAmKZRu|Cp{R+x(DM|#IKI*MRu5KOSOKO1!k8DDL z?}sNqj_|gAU}wVVQ2Vm1$Z2RH(Dc1!M8DT85z#B$4TrQIgT0SOY9!G zlW8YOj9DGJpj8Y_--|5OU(kD?>7$>m-j(9aFhwV;#f}_{P6tgND+bvYIiK=8$>;d2 z#6<{s8?jB5ds!ViqiBYvZzyWuw)ZI==%;o5r3sooug=`Nn@|!SWkN#{77R3fY%C{h z6LzxuX*iL8#?dK>v3vOoFEGuSOh{j*kvm3C}8{p%77l=Tw0)5K)8O$~Q0a7)`y9?f|eXM;1_gF+IbG zQ_}GPR4d`vGF1?Hjm3CHX=g@4?4?%|dCBI>nj1Npp|5x70PtlkjC?@x&E#pQm@jKd zgcqI(Z>Mku`?8irnwil%8f;}&rp>-)(vIebqov~s{GlHG(gQ)M4C<7IlrBvlTPNB; zyDNMulod^8tAnPm$yC7~{hZ+|eVMKtit-^1Y5H6_IXaD%08O7e*3zPBltI&X8?JnO zS(#Bj^hp3spBp|j`WZ4MP2UqHd_>e{exT`d!^cD~q70fo^YA1qFUks&rq5kU@}sv> z22GzEzaYAtod=peH+*VzBGZGW?=@q8X7mm=;~8H3xzS73PaOZix^R}c7vvm0_J$shfvb= zxh?LGzRdcArcWaRIkMsbKh1Y0cfO(NyPu}MiyzYTQJ|@*>>SYaxpFZ2J(>nhpE=iN zC0mK~JcYlG-H$x5lPe6f*3UQGLwGG*TL;afAkqv=p0`fBm1&K(M#C} z=lY^NO<>MPGnh4K`rKMfjb2K7py{hO_U1+lfu!j>!xVK%^g`AWG=1)btBn4R`GKa- zmFuEhrAX7~%Il(!GC$Dt^)!9nVn*}5=DFEZ+-gUcb24r56nELtGS&h#eazL#dccmJ!6dDo;t4zY5@Ud-&&}nRwv~7? z;<8kxO}n@<3uWX4SDxs}QLD>=ge!dsRZv8)W}AYhj{@8LKDOD_zRn~h_GPUDnHF-V zU`+L}5?fFsP9(`)4TCtCMHK8ip{l#h zWx$MX3@}n21^k@o-R+O5XC0y8^VNX=P5dTu3??S30HD)b&l-THk1HSeQch*YL!2I* zCivSr8q1cR`9IaH+SBag3b_jZ$o z*V)c3P{htdRIAs6h|}Dw98I*b*Lg^GX0KzQ-q0%_M$hOKL)Wgi5|$t!++qg|b72}v z5WdFlFa$=rgu;IUB_AHmMsK0|P$1=eBxg4ah2ijDJlPjL0Dbtc*h$FexLJO*1u0Du zGHCj5fxwdxQiBNVWB(3?v4^0HtAv} zXE2ytT2VNta-r)%-Ib7Ajn1;C7{hNs`UPBH-srcdq_P0b$fF7Fn9EtvDN*XIY!I1D z=|k^p2zm^z?--=Br}U+cmx5=)Wv_x}Fg3r1w1=A2(Bx9n8~1*?!1ettd$=Hl9efI8 zz6#Nw_Zv<^2a?`vfIZjOgx`6-_4u9dUt3laaQBOe+NfDmZI zWuc&t2@&9>|4MoaET!JTyS2Q<;Ir!d*8#7G0}%zG1<@R9%N5P^_+U0{ZJ8R}a%*$2 z`wq6x+{0CiA=bcwD}t~N&au|6+u>D_Ie2vpu#Py_9C7gWCkq3j6arJC{xjRFwaBX$ z)m~zh&b=+kU;p7ouS2At!=WB`HPbVUv8}}fK4>=eqlbLsAblawf%IkF4tkcmdVU0o z50p)OdhRm%MFc)%aIB_vJNP8{pb^k$^!ynPjY%jn%>g|CnsQwN4^j2j^Jp*X_6qo=03g z^7IZQV1xeL4IsP-XA*d=3PWCOZy0h&=fk0U2pr02;$6+{V|pPg;I16dBaS(6jx~Ng?u;+0*?7g<6TUs zhjWm*S?_N!=@%2+@c=!-&4IG;AQ;CBHRHD@0`iS_@nnEIw-yst8|?`McS4~JrXtm1 zI7|k@NpP5G_KxN7)EWI!g1fw&VeepS2#l?a>xM$f_Q&bt$k zt#|mK#lhNgjBykjgc?2eKr_Spz$H)!=62sfVJI9{9Rgd{M5GlSCde%2>@lB}YkG@o zZiKVz5?|t%Uv@piYClmOp?0mb|F)NG=#J~4PINQ8v6-G^liLD<3UXuHJVlOHe*|!Z za7eVTkwe@1t~=r&7)RSUHXUqK`eBEA$2*ATSR-lCK9mx{7&m7GWMv<=QGZqmcE7GG z(uUWDe+QY*vg(r3%Bq@w3sKOrhSUG6W&UqOaa3K>h;QAmDX(uRFRmChVsI(Ou2o!C zUQq&Of#Sx~>&hDjS8^EeGxgY%2LW>!pQ&Hv`r4vEix@}}`T?i{+Mw2tr4me~sN)L1$0Unxey#fyCKWwrVIT^7)SEnIH zHMG4Ahe>8eMikUCb|4u~sO%wzoW<@nBQKETj0Sf{kn|(zWP^ze3#5Z)D3}Yfn4ldq zVU1^Jfa<18AmW_91VP0J>4fOVwnc-Lbj18y9_&o-)X}9Q$qppChL~$ZAYn#eSSa^eC7bNX-f)^w4h@j3{Y{IAL&LWCefo2M11^9_U@K@cceVHYAWrUXvcdW0*q) zvOlF`M<>q?bcQ+{bUNRfVZ4zNQmBLty^n)?FKd~n(`|5j=A&@m)1uuid$D-8;yIk#BM<)P{3e&*LtraKvg5}L-uSZZ zy1DZg7S|OtG+M>Q6=j&r)y3;->&k1a;@X#U=GC8>~t5XBE$yv~X(i>`Aky z%`UQv*OoTcRdrSx&*e0%j@fF zYOT7tRcmS+=hv>q&8Rl>3l>e8Qn+A&#hCvVMw7Y%5D}OKptcEhuBfYRC??jRT&1TFs|hMtQ)-qIt9WwNN~{`asK)BzwPhuzA5B_ff+}nAgo(=o8>b0&VYmtD zDpuE)D0MaNL={(6*EQ9b7uPk`$JKw@NrlC;rY%5QPnqfxQGgqvzNDs%E$nin;92bI zS`aOmpTk?aqydBr)#auSii;bHrp+uwSCz30+=ZMwighh^)n0d_1*+DeyDKUh$`M*# zU0%Pkyr%SYt8NZjsI6xf7A{y=Tr_Fg%tiBIlT8422iJ4DX$x@Ap-werqR*(WT|0%1 z1y-8+#@e-|4c=HOUQ@EVsoXk#_M+I7+|e;ZhG%H=a);#(kM*xFUtM0(P(C2G6vTNs zV{%rY@}-rr`tmhZ4d9Z94I4Fj=;#qA$8xGm>zXE%*48(cugj?(0lBfVsd@#l0{V)& zH6wBw>T=3*M^VF;&%t)k3D}@r21QAIY2^fT(VEfa|0j4Y+8S|Y;q2ovi3;b>pEI9x zh)shA@|vc4#p?1J31%<3Y3FLwyqI0ZB-UVyng;a}VFF^B4#gPenap(X+R{pNMeT|P zoW{%$)X6IT?1^;TBi)LbI0=1Sjtf|6)SX*l9>6Mr?ht`tP%9U6Hu=-#wRF_wq z!G|)Hm(<{Stqc_NWR6~MTMA6|F!rh%%8+SWyH1*a{GwTfvln_TTd6h1Z9k+pbET}d z2@Px&&zv)5M)5*JHRR5Swe?k4#o87mvl_b1YBf}1gvD5MGAg)sD6Ouot>gG^E5d?l zvyWdia}v6>xB*j^iy^K(%wmK3SFS*_uC85y^)YVRo8p~bUQ+MX7ZocnM+woBC9B(K za#KxHL%Eq)Yte0M8Zk=HA|>n0%w9ceM2RN6xd^GMDfXIk#p+e=!i(u@jB4dLe9@>e zBV{dWh1NAw1>7s>%d&>r;!3PMXfmB3IKWH+4qM|jQrl<_{@w-hkgphtxK1lxS>A}Y zDrdKub!TC&3!wBWDJ!#3*C`x&I9qTnYheCpPb?#CBdu+u6gRj5;H7D-T~)lg#Ei}r zT!Xv;XquO!x5k{@*jMFcF}EJ(Vo%+Ecso_pm`g|tPfu7p{GxQGeZ7H&HIxlkV~Xc? znpwN8VpysxFRiMmDlc<8w;aR1qLz~ur$pGPYA7yU#}iXIJDLl=%R*G_MTcF4q4_aM z*-FJV)g`M@5!hyS*6~xOjEnW>s=CmyhE~+p$0mWBv{2lnvAOlNrR5C`we=0LF*%3P zln(e;7hzuNCd0+={U1Z64*o^;m3#DyQtI%2QesN>Q%;|-|zwN zGS~K0wEs0piTm{9568UG+pal!Uq0@q#~qIO3U<4~u~ORw_#E?=X}iiff)(KCefk~U z4_qio8jv?ayo2(1PXJP$dW5{_2zdo${>9C{<-YzkM}&KqPx0p(%y8`G&&I$mHmnTA zWu?`1D|xzT7t2p;7t5;FvO2!H267eE&rEnV&F9LIqQer3Ak^Guu-VdpKO#{h7mrN3Qh_IN@6sbsTP3vvqDk@@rx4ib(R zP8XWJSBO_Bd9Cn#;iW>}kfuG3SK<@GcZ7cs`tV0T!_$Q^;T)ma1BGz2=LvY0^!EyX zCVWTunb5%!LAxD1KVFFHBro6&_M2v}Jg@&^LamOfp3K8=0Lh~7Q*yo32s9!2vC9D-1 zt^>qtmi#T@CL;8$k_{IE>|7=N52U|E$S>G3zTrwhyoaTKLi*jp*M#pXe82F3^nVd1 zVC`nPlZ5=rB<**T+)J1({Se9gq8ihUk$#Hg|dxJI~MxJk&5InkcsbU^-B zNxoLNlgN5YepvW~^v_9tLHLI79pN8@`~WKR`3n*D5^&Bk^%tfQ(f`AQCle8mUyLO3 zU^td5gD_)|*BaF06m8Jlp@-a8@&IA3aHNnoSeb6JaJq1|kk33AzEoH$Tq!(Tc%JYg z;TGYQ!mEYX3vU$ODZE?wtnhi^%fh|FcZK_fp9()0^2ry=+f&$2c&sp2I8tcNyR5(D zc|yK0Ogm*lUdK>2d$xfMk~aujgqwsH3iJxQ+T(~oVOAFnB-pw`T8c)nfL2} zf0Z2M`4uvs;tjL1((pLyi z6`DQT2shUYz>U(ME&Pt~yTZ$a+k|}SjpgAdxromSpBKI={H^eJ!ViRI&o!uy4f3ZE2u zd%S-u`S(J;Z_fPq&2^#!N93D}#AAe`h2w=YgmZ*Tg~h^^!d1ex!ZU-3Wh>*MGo7VY;xRu&1z(aDdQUUn1Q|$zz52 z!UEw8;T+)!!ll9$!U`eZ=VW;d2Nv)G$rlSR6<#U4PRMsnneKZw5%2&ZtIxqQpRI`yoU5_!)v{VzOTe}tao@}yylFzcRlQJe+2EZES|lS z;P=wNYt6+VTMe7u;f1Y+!t*oi0o;6?9vxoTTFCMC7UE_g=K<~E&z&}V7sKzRf!8_-_88AQys!(Ph__c3XOGS3mG4^k zy)^Jzr^4R*4AkL;am!r1y++t$v#@-;GwRv96@I4Sc;K-hh8ObCAKt+*x_g9Pyl(x! znv>uO#RHh*62zP72|%x?kH8;az728p#jU}%^6h~iW4R7sj(xBfKc>C<661!4l{tW0 zM6pu=dJG9;kL}Jpy}1Feb^Wo}U_g%!&mQkR#>cx5<$J@61oYw!89OXD7I(C95)6&S z@E?c!n>%#qs8OS0vE0$4M*?vCV@`srCYcP|I0-tVHsmBI+?2d2Vbk_qNkz9#PTP`F z6uo>><5P}+innaR%{@~uRw zK?@FsK70cHz3=;ArSqUi5BUmDIv9?@%F32QK3MP@3((~UwlYTO$^{3Llf#v6DnC-C znN*=|^DEm^g{}&kbPEpplNTb-1f)$HRHjtHLdJabP)cFw%6Z7m&B@vd8;~A5l(Leg zwjn?8iJg2>!7ByMCow0qb<>_q)P3l#l&iKEByG0_S_i(>g8FYux;ixC)q~bhprcVCgc;BC*;VbUg|7LUk!BAe#?z0Y9lYTM9SCoIy z-#s)e@yfLA;jQW0mR8!i7fepv;_QDksrj?sx2Ig$Wm~AI)0LA7I&FzunO2Zq5Z#ut z*&g?JQDjSWYx8Hp+tZ4=8IFPQ_O3-q+b6?z*P<}2O+x7tVK0;$-jaT$Jq+6xwmSPC zOL}QHM?~{yU);uezqQ-Swz5$65yuquEb4sKhIi2l_EqnavB0(a67Ox8VePlCgeUoK z2wSl7&o#>SAJ7W$IfCO4@R>2#3JxI>HsG6!R$qYE?*843Ft*DQqyk$3FZ=xU@H?|Q zucFEyn8aATo$Ac#veBp#4pL>~$649g+_(q@#$!|T$QmqF0utB3*H>y?l*3R^Zyt%3*KS~82rDd@!Pxo3Q@^ta1rC!A^y#oO25Aj zaYLO3BR_?m z(6DZ9?NfKjL z2c9xRc4&IYk31rOK<|ZSB+}1Tk5QZ%rU?E5JJK7S9-3_`2H6+cOnIKiKt0el7xENZAJbTh=rJXUf|I{nP(SQc}wml3*$qb`j%ttvx54)Kp?@)?Bg z?w|zZGYH+|jRf);gzl9Tig3h-?h6+J$Y*dVv$|iR%V!Y!N%}^Ub6R8tBR`s!`rG6^HZ`b>>`bUzO(bHk`r(KrIXApW; z8M%B0q32Wqm(L)yTlwZio~Ef6(z$h$dMkulh0riGkQmZjeG{|YbNbz zemGh>p3fiZ(J!+Ql**t^2}s%BA6o7Uv2~&wXcv42nl4e^$O(bZV5g~qKl&-d!Dryg zp(wYaL+C>V%W$+oij;kgg_zbu!J_J4kH+*Q6f0&2BXJAO4vqnUD zBPj$v12=q3bUS7683YrVJ}=rEl?Z{)z+Fo6qr5;1fzQB=Ul47dzzv@oJ%Q=L zXOL{t&y43V)Q^D;d-l2%=BqOqL=%h9H4Pgsq*@h%ZY1`!?ryV(szc!to|H@W-?>>;JjSm$vBU2S9l0~2E32h zc|D9JhqCO@4#bF>wFGcYw20PdX;4|Q9f_w&pm^Jte+*(YHUPF7}GZYkM16Kh) zgY8TLJ_A<)J_Fv+41v$U&4qjh7r{JBW!e;c29#MSBZJR?a*ZdG&maUogDatko`sMQ z_zWnp%^zc%fzRM3BZJR?t2zZ^3Va6a98M(3T@Qr7XYe`{-MH$6z-PeD?RFd63Va64 z)y@B7FA?|*ZbB6B8Bo>T<}zSLHwGB#K>~hGbbLdEde#w|Z1@BI4){&v7#s(WDFAo} zPGJqeXTX&Ydj(jR-!2IS9w~7zsIgwxE9k_Gp+4pY027g_T}g5U)A54ozys z;4C}#0TWm~c0v^fpFss;89oCh^WmNPSD}b~i*b9ARmUQ68|l*B$R>mJ1WDdflCvY$q!>`95t+=lmE z>iB@qo@{haLdW+~vOhrE*i(#-_i2{FWpmGwU0`${!uuv%-@0{{U1(GVNHGd7dnJof zl+5~*1>`oke($qak2kvP6Pevq<9`KVeEgBkZCm!V@E=j%kx0(dem36|v8Q#Qj%R0H zn)WRLN5S+kTbyrCoDSD_1yvEMehTq!s!FL!r-~d61L69XQPq*En<4U6?J=db;2fBd zd=HA#7oW$Okxt*22sy+A;4zrdg_?mO3>dh+c#j*p?$m99ya6t|5>f3LgQ(jN`DM8N z-1TeEOkv-h*|%hPV58ZhTp$-*$l<8zr@cr1YZGX4P=}HY)o?t$o@+g6MjF!?q)cK>s)kwz|V0u z$b7}*8edPF?c(IDvwS;zrVo%l-R_%`k>sRwOIZ|5x98g=^zdbadSD`yh%GNF>=)mG z7!3mdAw*~=C+I5j2XH}v{K0tpe?cqF9z3POaoC>Z#M@gty+1A2fPVZMFu-j$?BNklTDQ+1xh_L3@B^ zGjAb+_F%JJhM8hsi9-PK0XP#t4;NIV&ZedKgYRBo?>2!^T>69f2<`sPCh9ywSL0nk zSZ%zE3FePDZUCi+*09wd>cfs>Az?=~!OL$x7tZ*DJ1)WS0|SWb&V6QDK+&2<;N5!1 zI&Jw5dYE;{+H!q!Fcj;)<7P;2o8X4!JLvJlf`j{lJLusnpAhPH(8Kp6AgtR#53hHz z-<4qQ+gM1>7a*R6Gh6-X*$0O`w*;;^M&Dl9dC1Ki2;$*02hoUL!}+WRzt?g;YmL7J zq1VA-dozJ$##VN(=s}#B*I9kqN*{uho4pAxQ0?qKA)KIz(4#^2ikS~mKEU=L9 zdSzv{$i^H9k;nCY^QLY@x;1cUHo`=t$KK+(#FOBXL7ow0xAbAZc%@(ruNde}H|zLc z4#iP$7?lM6vEW#B>vqt?t`3q1V@&rQG;%*2;t@ESNNh15R~R~=K`0u+94u`MoR^;d zO>o%td`UA6c0zoX9R}+GjmA5lfO{S&1ESG$o)J!4w}YN-aBT))%pA~JtOZN!kZZ%M zuMtcX{J6zrygqQ)5l&zdm!8AtC6b5$bI>>r2Nw~CAMQ-id||8>IL?On{r{97g5yF$ z{0&^tTG;Ae)as}IZMaSt`oS-TelcLZWuWJo*5{!CeavL~3&PP72RG7_iKg`u)8B~> zGtHzr&7z5(h-wlujJLaxxTTq%$#7m``sczSaou5wTbfN`hRuiT;)R1HBj}b5)=U%z zyYqR=re=CL7d-p)-welE-wAxmgn>Q*1P%26&d76H{qtJ=^dE=|r{5jfXPVWO;~~C9 zw?gKofOs8cb|3Te4)z!La_~z>sRiz<`iHM^1ud6(fi-D~lf9aF;jGQuap5dIOY4Pm z*8MXj_R^tf=D<2^@Bn_7!Hc!4lE~JytyAs?xKrj7ug=iANlhgW8>Tc8G70ArWN$UG z-c=L00wbFZ-bxJrGTy{{-b9&C*k__NZXmLMd{!f8w>eN@t+xm;)ZyLX!Ae75RsnZG zrT0`fgm4)gCNjnq7F!CeVZb_#YcFfbY_QIGwN!}m1n-SIo81h(Tu!(8(A#brig?oy zA8RwcEZ#IiJkz+|Zd*)9ao{Zr^m}peheF%oEprTSfp!!c1e5NHW_sMdnn$?M)6>Ic z3}w#FqYQq8Ghe#+gJaS=uEB_OtYe}1 z=h#2oosZLMN>?|P{d@R2{=)@Qol{d=Q=Y?*`!2(lbJNmoTf(rdZ1p;`6`5a!#kMna zxOSY9wgVk{6dedo!tTCj(t%*OagVF(Yoh~!wv7%1Bg3Nufx4XlB#!dqxHig<2dA%F)AP0|6sQ$IgZght7FR0vXO{*4chvV32c#QxU^s;biCOGi(x3teGB2=-3gw7QcWVVXni;Q4raBZxwfS5~(^cq9J1kxpt zF&)ezqXH=-h9K9|1~WoN#|#rC#ThUd$`hy@&Vno9N;jc%x?)4L0~v#793nWW${FZmD}AA*AQ4x+U)rVlv*_1o19-Vg9_ z?6wAHbR>gHs&i{|Y%uvmUdG$eVcQUWq&uz6YzOCnH65H88O9P>Roq5!F;{h)Ap{2t zazd?Ovldh!8BT}6fwW^`CJXJ58gy0}+LJCz&`Uj?>l}0rN`Ri~;=H=ShO)D>)5!}A z!fg$ssxYeSojk~?h!QisdxOKyO?6(`z(Nl(w!UX<1qKB(+^|=j!dXk&t*X8VdxDmx^8;8vIux{AeoHrwol1na=k~~ZZ=K*w? z9n8qXB)09gZQuX9$x6g;FbUh`R~*h-f(@;W!-sKyx65DBzVlz4C8WAAbST&wjvd|g z>E&){7s6OLTHLjO&G88Z&8-H>f7QlHKG#v?e3tNP+&Hv?drHn2dji z+eADj7%$VROGrKPzmd;GloKexHzzg$-OoQoVnSY#Nrqiyayy&IKO{6M=5l1l@;9M2 zDL#tL#H8X&Y3<9{|9t`zkFNwXkn1d2OSB$O{)Y4=ZEN(uN?vjp6N%v-`DU~uQ^qY@ z)Bv)YWu>c2Krb{jcNqvcRt;Y^W!8de3yMd&xU68o+-2b5IJLaAv0)h)J2+bZ&1@xy zF_d`hD~F$B4EfVn6PMs=pg8ZBCEBQ+b@V==t$R#j2H6{DMBX0>G zF0>!`TP5yra8oP(aB$Zv{y3VqBr!f1e;X$sA>-L-+~FLyJAi*ncZdt6oPLCyX?RNT z*P8h|pS&X8-)+T*k5!jS_lkY`Ee`w_jvxO%M`8qVi&lFxHG%qwu@JYlUVHBhoFzazMLgPax2INC?<0 zJ--UX@LPp^1(Whq!dHX=yeC0@N1@rn2YIAqvsVxDBFW{#CgHilONBdycME?e{EhH^ z;h%*`c*}(OcNgXePZ#n_Hw-tQvI6dr{CnYeEPD($+#A59l2-^<3fBu;gy#t_6dLXg zq`yP*J;Dctj|+bxd`|e1@HOH4!q0{Lt_RDPB^)j+5E_mRgqKprm{}<_TpOrklj5}y zA)h1sw)B@szCw7l^fyYrRd|Q=4@iDQ_@wlPV*~bIl>TMu-usSSee#AZJP6U-}WkP5*52U|E_z)3}2kl_lGl=3FOcQn%n)~>O*H`iYVXpA& zI6W3C{3KzCuv~bS@Lb`A!p*|Vh35Q={I8RIgYb6YkAy!JJ|)~Ed`ZaXpR8{{m@G^a zb`hHMGU5%CJVZD~m?tb0nok2F{(Q-cg~h^BA)ie$e{)_3u9bX-@EqYL;dh0t!mEVW z3i-Yx?RnfCdnCUk+$(%T_@3}X;U9!w2pyicVJ|`GaeH);Y~Hv-_&~|SgrkHLgp-6* zg)@b#g>^!YyWJzpAS_*CIS;SwP~ImYlRVV$s1$Zy6m+~e-pB-vaCL4T=a ze&?0(_(Cf2ZsEhi$Ax?$mEo@o4Tl-z_a%QOI_Yl^J|;9AXvpU|$u9^!?u@r2AIX`~2WeQ|enM`kpgdf7oN$V8hVbh+ zG*&6RR_JkOG)v|#E!zK%aJ!IO0I0uR_#+`-^rik~A>SLOY_9i!M{;QJL&6L<*MGn+ zlFfA>l0YLc^Jd^n7WY_J1$@Qt03sh5AHciZCkdCLAanA{-?gC!8WYUU-6Vsc@CBR>+ss zneP^%*y3lI=El=t61*EPtNZ1?~xdcSdE6W?=RYz-9 z^W!hF2vTcnaA|FIHNHp^pQ@t1q#BWMGkgwO*t zpE-Ktm+^2JV2&f>F^tDCaP0Gc6mJmX9GP$YdpI0FJZ8apwkh*I(aZWfgt8Yl4Sq~1 zD<6)>g@f_855^_$|6v%IzgJi;vlj>G9nWCkUhP#9O3&V^I6vc_icJe2V9a}m7jGpL z@%es+KWx$vkNGk`)`Pen&PxNYwXmmU#pu!Dh4Dq|czgbQcW%)hv-j*>1izOCUaJxI zmeZrd3;Q)R{5ju@mt_p%#ZaJ5NX0wZw3i0QJiRdwueAi@FMf`&4m_A9KHdZQ zmbDK$@9^Rc89QQhEbjP6yez|pjT}47#Q(>)wO0ec(K4*?X}6wZZKUxIz3oteDl?+3!pC7e$IL{}FgV3X6(X6rt3QWK{kN zIZZi~^rx&t-TnYpkiyLUVSnNN_nRK+JZb-1r~L}$Ur-qu6&mKnL3k3vH$1`cCi^&8 zdmvUcpy=g23ERty_QK|}qALonDhO;}b;oPqSXpw=KXA$+-{)C}I{e}KE`|GlC(Cap zJ)U&`CwAiG4+pr*l!N;X@&ViR-f-K06cVMl%HbHt)wL^OM?lK(Wgkg+g$c@O5i(i-5yq z3szK+Zu}Kz3+I;@`u@?K=OM1o7kCyX9NrA@kL^-sR0*VobL!#u&+5FEDu3WNjKxcM z|C}xt7*)bGw6z&}|H{tXm+1=y$cycFc~cy2r4Gb03K8OPt8O4Wa|!(qAz5Hh2A64P z9ODel+(>^liVzr+u?2qYrQOE-Zop5lPnSPK74UO03H}<1ZRZ)3BVkYqi{|*CPN+Bj zgnJMg0=LOf1cdwvH#oBp7#@H^CES?YlYaj3m2guA_3m!=li@QQBIGtn_gugj*aY#oJx*-`?$GL?yS$PUz6g{98Pge&>4# z4|g(6237-H#e|21vS2U5$1LI84Em7=xlO{ul%qdVieiR`CAkF%MQkHxx?*zVZ?F>{ z*3A_Sw@G+-lA&NV+$IkqIFYT-D=1SpEOh6>98l8)W(}jE$G$oj70j`>il~&JTpwuA-Bmr44!Q&2H6)$#mPB5Pckw}yc&5ALTpoIaGN}Y z+&0_clSAuh-L&^99q6a^R+g+d=r(~rlE`wGgk4$?m)j(~q9+?m+$J=fcrkwHlmn<1 zAb{J1d!R$%rqE*$BWL?zYE3%*%;*sod##rd#_>c9l{CK8Tp9jxXgtbDZj{7y zL`I$)Nnq&f9Zo`7$!)Tg;+x4^OsLCk5`H^{Gnm{a3C#B$4K{L{u&9~VG z)T3X@5tPcHPFJIB{r%zPz7Si-aGQj|ZNhly(dc3}2DnYkje;zHl*<$3Ojiy?$1-DZ zo49gv^kP;5+$L`Nv}itMaGQLND-Uv;e9RUBw}~4*G`fy5xJ_K{krB}u%n#fqZupq! zdz8U#Lh=G~n+!uG!r(S>my-PG&nbi3#EoBII4Hv4HgUtJMmI4%xJ^iS;LDmBCCO?S z+$L`PxzRsT2Db?thukKMDTCX@JZJ-_1?N>5+$Nk#hT9}UgWxvd95LJ`y!99cx5+5v zV7N_4XcGpv39II0?F&TzLL1;VnQUShZWB%gx0Aj^hH;%_L>3O6bSugf@b5!}OuGa8 z$HHJ-RI0rG;3e98|x5+9`#-h&s31M)X{2Z0(JP`rOVQ`yp z6^fd*1l%SRI3jkjg}`m%wxB;cgbf026O9Pu$chL2G~f9?lrbd?ZW9uiMxz`o;5MN^ zQ@pDh2DgbT2cxWD7~CdhX7GXAgq{wFtYUZB9R|0_Vhp7yAK-#>qBGBaG<7m%aGSXO z=#RdSjKknIVPtZf9LG|F+r<2#4Q`W@nKiggt~cqYMtiVmM{t{j!EN$5?2_B$H|%9_ zo46CMGI}cW1GkAQyWA#WaGSXDI>R;*2DeEC^5=>k%|}L{zernS6yP@LK?~qEVF?Vk z$@dup+$J<(xJ}3!69%`5s{psjHS8sDo45*aoAA>cVQ`zc3UHh78y{hCo45*ao2=#7 z1GkBr%P+xgvJ>W6D$}OmHlfTy85!Irl+W{Ia+`#~ZE^<`QSM<1gWH4x+k6t+4BRG< z8X4RsT-7NUQ{XmX=WrrP?s^~$Zj;ZU=yo+L4{j57ZZ|T=g~4sYT;2SGm?vEeUg4^U~Sm~9E_|37K(CAhS&az`YkUQ*t3RNPwO*SId zVcaHvfI{3R#mJ<&7hn9?*o%+7JZ_T@pg*J63>X5pNjVG9Vh8w*i-bWmeu216%o`CP zI(Z!VCTwH~h)!OGfQv;uC%Q}&|ua+u0y;BA^(^_r`)ittHEHmRlUnM0_%5^^hbe1v7s%484l>BKYCm9Qjp zQzOWgC$8U9x6jx{#kBKGJU&U7MI9eO+4H(E-r11()tY{l$nY}UraFet zOYHG>*TYmtFo%t3pgoeRxuIM`xQXu&bR=fG#55x&qX3g7D~WpYMgpeaf-G-tZW zSrqCW^ScQ?B>#<9luHn4E1W6HP4N5xZXn}tqAeEXacCZeQ&FgQOz4I1*=L2LscIFz zD)cM3fsDdHQ)=dFd>0-* zxfsk?CTl*Q_yL?+;VyV=i@*2McTKoQnp)u@M0x;jpciP0@Ed4;1WaPQBlRa&xNvLZ^4VK|8StDA zH<0le)3m~7XfB3RD^Ty4(D}6We#W`9#a7sfNZ*Gut#Cg)_reWie8x1b@EkPHz~KQV zX9({Z*yi_a`nuVjo}@801z!+*lj#|Up{8DcgNCn$DLwUm6M7!gcegtQkkq8lNXCi> zH;{1{YSQOW1Bdi%7wY}y_X4KxV`t1~dJd1th?Ng#8isF+ErJ`!1dM7LW;HaY!r?AA zhX?hJ`MsFNvh57hDrX@^Gn{Fa%iy^LZXhEwnrW3=pt%VSN5IcF^8$WeE#!U-g)ivq zhA(@gSi{Uar3tMG?F@PetwGU=plEK=U)jkN z+}OXd-Pi#?&5igePD#!e3BBy+V8LN^M%LElQZEV#R7_ z+e*h@@n6HYl>}Zl{yjfvL^}yr&QT;>%yBTY#=6iJD60XN#cSwS=rKj(xw~S9?rRvh zyF}+T4Q7XnR!oH+5ubo$U(9;s;dEc4j*P=;hQkj>N*N+bN`E$yJQpDP+GjlbATWUV zJ1>Bq4-|j|M;*A_!a6*cFwS@v5oiKbAon)Y!{p%9fcmhbGbE6!5Ez5}Ve{H}N#bMj zatC}Mgg4<}_pWAoXq&0#@1T!1Ob|kjI{HBa4i>^G#=C^D+IUYOxK-T3v*2MzPe}iC zVw8l3O@y;)gstMUn*2m&2%e04$&-r8^T}-&wc;^x5K(e-B2R%P^^`8R%21gbzV$9TN38A0yE+$Ncb3ie+ zgC4g9)@+DtfyL)R{|cOKE!hWP{o}dfT;jA4ugZP+hr@Q+N^0P3p=d22@IpRlHCUj_ z*+Kti$xY-!gP+x8cpYT=ua(>gnf~kHV2VxfgzJ3;z)^{gy^9^|)faMpa76bVtn+Os ztz&K6u!EkvU18%6dLDuUzYAfXtKZNz7yL+xKO*6lz=1%AK=T;xx5mw|6QD8&&Z;Il z#~C@m=4JV4lw(|?8;^zMLDLm*;HM*e00+~%;!H1u${hI9&>T!M6An|Kz??`?HjnwZ zeKME8ER7!F<}h7id~A;xg5#-NDD#mVmnz~iIFE^|0{-kbNA z8Dh;NTmy$0VH-js&XxpgqZ^UJLvWZ-gh${o1#L54u7hnc^4$-wgQB&KiZDXjyP2F# z9Dy7b^zTC;8$X`w$^4N9mDdM75%-8bOk^L5I>|FJXXB4NGjy#TPyco(~oz379XEHVKL_y%AD@Mql7X_rapitkO(^8czq9 zzhsh`eN71mCUt1-;3_95Kox!Hl@$R+6QH_^+*4Je67+uyO{j&6Zop=w$D4W9$m|Ok%%rn%k~>D?Zx)R zDdW14Ngp^ox$TQ#6!n2aZhz$;gl&h9TDrKw?Kese?xPDwEnQsU{5BPwm|vr8E1YFB zmK&2dgw5d?r911|hG^V9mG((z*^H(6=_R-Ad?-2nj;fnoq>#9}IUz<>^uy*)uq`C6 z8i_We&W8IMWnA4D%Z(XVH!9p^B(84l%DCi=r3I(0Za(i$$5D0josH;padq<><#|vZ z-EY*=;cVnt_uEul@b${L!ZDT`vu%NOY$`53JbB#Bj`)6KEH`GG&F(0Md&2U21u`c# zPvDfK+Y0ARLe4qwh}XsIIU4A=E>DN^j(A)mg54#gG zFYf5#j}PMH{2kdZ5D;(8!%03v?LOBhbBPphGtJ-qIjCwXt3S zyBqkl$fo8VU_x`cw)4p4;VnGFBiG5voDP1i#8{vcDCjoRJAH88bW+FFOUbd0Xr?}(Q9~1S0h5`tlI=DmgL2dc zmtNXnwqrG7gHkUIJb)zTYZ#2C21gz&3<8TA=+6Q@P;`63m`@%nA`VCF+}h z5WtK#ACd7#%J{`2GQQExcre%rQ=R3c5$wgxK{Du;!s&;ApmTpS+8+J-lvROlWjRNf z{O@=3=YVu8{;&#m-;n`Ns$ef2T>w+yE055>)z%^tOv@nij(LHuwhbD+gua2U;2#{4 zgJ!Wa0_iy@+7O0uET(e+=E9ROG}s3ed!W|~RD#Pc7fg29q_M+TxOk)Cwfp3M46of+ zQQG~Byhkpl-P-!9#`5CRa!0NMUmn)M+9t3*Re2o;7X3tVs)}Otp$@upg+xLaw=^SX}JeDH|~cE4V3* zN`+T(4bhhQ0f$o6%9`@B7-_ePOBzZWtE$V3S2R_S1*&M;%tEVpZ5fO74XNPzrM30ga+Om(0&-(zQ}qg91@sklYewWW)a8`r zj-rMgmjg1`36&-FWl)sVmsU=|seR4p@|@~{6?L(km1S#7>ML@F#d78hkL6U<)aGCp zRaGfct*$C*sH#~BWkpjBx}&xxrvcPlzy|2bN*YVz<%+tT(%PEF`jXPd321byxbFWb z2Ofy)OL8z0gC&rE40w47OP=#au?yw=L=H!pRG*f0di>Um)2N z>EC2aOSW4gb9t^_Z7VD)&68E*>2=s~c^KOsmu9ZeHD--(s%dH{FEi%}>;G|Dy=45+ z@+A)3VBL_C9BJGC$G@EU7xPzg>P<>n?%SW3l07+TN=mk6{fAR8h0WD={8u>j*ydl$ zsb^No>_+cu>Bz~6ze@3niMvmf+&_5T$RcvDC$S3=HyHa8(eZ<%A1)jxoFps~@;MaK z^UfJ@rEs-yy|7t$k&t(X82?(~twP=erTz)wZsBV}J_=*_?}dD>O4;Mo%aGhl$k${U zK1sMzxJJl3X$;>gyiv$IMbz{8ACaFPB)%s!oH>w#yiWu)ukZkmm%Lb5F64(>81Gxc ztwO_T13kaU!0?BKhPwvxUde{L2J&AdC*w{9#Azz#%_u4jv^ZiK5HwkZ( z{yxbM3Llf6FG@209^tQ~e?#&+!VjeXqvSsc`LZPI6UN$1I}u?ABJ@2Z_ZAKn8V)_g zAFFr;(i;vv=x0g4M0&%a2Yre3d@qvu)d`!VZ;^bC@Y~Y!g-FJ~LU^_GH%h)$_<-;c z;j_Z$g>MRfC)`g&JwKQHXW^I9CnAjbrU)~La6KjW5gsG`Fv+8YJY6_P`jaG| zA}l4MPgW~@o%9=oXGwpNiAZ;?!f%y+m+;5Z|BQ(7_l$6l@C_pB`Ht`d=|2{J zA^jm?5SJgclPpXV#)z zPdG~9`-BYcYpJMRlW68=@;b{fLb4nZQ~B?>d7j|%%p-(NULn5Xc3;WXha;d~SrU z=fWT^q}fi1!VFH1exh))aK6G93yX!N!b&3St`;^)f4cA-=`SFn z|F=nhjqv-@-zs^R@FzsreN^Flq<=~Hiu7+uepmP@5$O&J{~}E806p3#P1r@)L)eFi zbp3=wq#rJvD1Cu&s&I+ImkG;-Rl*t~?A8mo2L_LoaPL+P9@C4~k z7M2KW6kabpL)a`lhX}iygj=M)RCp5+=a_qiPYU-5{~*lFbmL7D&JnH?;?Fpf5B^Lr zh|{@2OfQ3-h32gTl&7!c0m5A2NZ~}`WZ_A|Q-tNhDq)?lQOJ*cvfgJ2FA-iL# zn;z+3mb_QUEvmHZam{v@91|WR^f+fnNFF2fxMm9_&lb)Xo+vz7SSI9m1DS8FutB&% z*djb%_#GixLYVGyA$OZozD{_P(Br1PTk`$F$Av!=l2C-{pBKI?G=KL)&;7a#PZXvL z4Yxk@y(RY*<_bp&CkYFM^Ms3p%Y@5?D}}3sYlR+H?fH_wBP8Dm%XfwFd%~T9xoGW>paH8-?PTS?umkFzd zrwPsd4cOZt`G2wZCV){@XZ!fv%uHsoOh_PM!akA&QCY$!i>MJo1Y}D%_-Lln}{fv-saSwDWp?5<;#Th zE2nJl!GQEAr)+CX0Bwy4;EU3~N<_JI9cQ}#7ScnUa+c86o`9T?O!sicj}g)nobq(x zu|$+he{kySg>?OZ_1m5^!=v%T_Ih(DgQ+Hb0W&6lQ;GDJ`PAabVVJ#8q=$cLasX}^SQ~tV;PS}*M71I5h z@;yR(zX$nA$#k@4{3}AbSX2HVA-$<7XA5o3478)K9^iZJb{WbN+H;x_A6YggJk?O~sy~w)Mr&;lb4A$4!EaOK6}>`iYph zm*IHxJ1I^VE05;_zjyk15DZ-36%G!#NA)*9?i48eFyo%aht>zO{Z#F7i=j%b_vH#a zd*hnHdRZU)LFD(;)bcLw7YHPv^EW?k1r({})y;C;wk!{q)MR-VAnfNsFmNZzdx!yT ze%!f`Q_EY$@({`L*d4!pd_MN`AQ)&q5ElLE47tsZyAon*c^hWC{;@m^ce1=&5N4iI z?A-1i=m=|^4$zk?%_2^SMC=E^ykZi2&cAhBife>9ovUjHp%vFMHq*@ z31HhpC@*!c`u!#15|Z5BN4f-*U7^9NGAobev(A)h6v)T?+go|elbUV|+V?Va{^r*^ zc=X6&iInZLxQB;~7(INHrT=X1;qz$}fYZXYuRpGd@xZ`0cTOL;J@mD6Z_lcju)({i zQ$@yx^bO^8;Y)8CH>2*v4P`t3yuM(=55PG5Hn@k=F1`YxKdztt)Jv z#&p>pK5wJRp%b=k4@{oDJ(zjXb}zHb_Oyea*&aAy_I9uPH?SA&h%7m9NB`9;cJy1a za>s$I`|r4ENzsmj#vHoir%PHOFWOPGWZ{ktkk5g9!oj#{L@c6H5; zV#r%2uRwh3jvH1dcC24gvLkQ;^N-kZ;0e_`N|w~@_!i1P2kFmVUA5!%?tOQ_yXwf{ z<)!6A%7f_ZiXDGg(u}%Blz($u@XGGxfh+Grzk6?u4x3pqdwbdm7o&e&wtFZ1YP&bN zWXD(0-f*(LB|C~wsM+zI6TH#ET~U8{>$bq9xfSRB0dS1 z+@LLMG`iblq)khUkj@M2!;2YH%kXr^Q5=dCQi_J>;1mYg@s&6OL_93chfFV6h}*I7fSj4kwu_O?7LE)-Y&y7w z*FzT#g|837!6T57hw8&OWEeGQ$iHSgGeAx;_y~yO~ z(`?n#Xkz4;Ooln?e9sV>l0h+8wBC#H9y~J5ItDo{b^_&@lF2PR7j?ge)YfHi3(rN< zHhPhhqNV788}E}lGtAQGAz`F4-3>t~_90plsmeIiVjZ_|q`Ef;OWeXNII{xL+*Lz3 zGz9{UWlypE5hL^MOC>EqOEn2A4K0nVsZ;d?(VD% z>DiV*LgueT2Wc755=eRx|ry=g(J_YsPfpyY{v7-J0iXR)H!HQC55%wx^01@?!t zrGW3?3#i9&>4m6HjOxl&llq4u3(}$-op>|L1-G!9D}gv)Tt>hx+-6+>XDj2uE$rlI z{47=sZeb^9$7ge@fm_(+&y9Dd3~u4?;m(5G!lRiU+`=xtH2w>A3*5rCcxKV?I2Tim zfLqwbkBZZhL{5-&R_2(?KlNpx}o|i?wjMlx#VFb7EdUU3c z6CpbSZegxq6}M|QxP>X;9FHH2*a*0V-3W%_agH#!g*78kBRdY#SNttJ7v<(ez%6_q zi>k(-2)KnQu&C9{3T|O1r^m^k8UeSk{ni$NTbKbZd!=S~+ZtJ)7U6nM@e&pVZsGMv z!J_!WG;(HIXLlS!aT-uYz%9(gJ+Rfa0{VtYW`;no2cU|ATbLBbo_B!Dma)nU(w;D3?dlU@=04Y8h}QNw1=)OV;U?%$>vJ#; zEx3h;AtGbF7haBh5q?C?xZKO@4*|D?_}eX-u>%f^crcHjiRNYO4Cj0m?cl+vMiVl2 z`EpwPRp>L`4d*_JY{no=nwO0C!r>>N=)@xWdbE!9F7>iKHj`UE(s1)m#JBaL*BJdx zuZRL4{8wNvdW*`-obm=J_#|D#M{MtMuc!(sKZN1~?8W@{>RsvOum!^r<~QWxO^ETX za!Q_yzoRn9GOu<@-iEBeUR;7d-Zf6i&yX}dHYVZCPDc}Ceoic2&)i$QY>ou&j5kr4 z!4`eXDY;PPy;L60%D?TDe};l9Qx?C97I@csF^=z06qUeUdIFY>o*@ zh_CbV7`y~=8<}SbRo$q%2jX2+88Pv7UQa4thvGTx#X~V&k#Yc)Ty(nvdvP!J;Ce5I zhxTD89>iW!RT}Vaay@t(@*k+HHl6i=i!2PrUb4`1)`Jrv&!%pX>8uA_!EY0G%u2op z2k|%l?q^{nM_<=2UN9#s+)k<(kEL+kI2f(n$)Ge{yzOte@~p32@Bvr9T4*NOw@OfcVxCtHF#k5 zq%I^ZEKC39IIF5Cm4;9Rip8nbOIMQ0Pbgi#R2?P>H_S|2G#&XMXAwCDi5MJ)xh`Q~ z2hK_m5&p&k??PY%@xNWTm>9(+!4ff$jh%^zypFL{6x3ns4GGjx1STO_;0(Sp-0Q~I zvta8YBrG_aP;J5E2)v>i85RS%*g?fcV9{vSt?Q7c!!`&Kh*SuE^|Ml|H=@2ISD%L- z+E$3a)!0GDb_w7$?7=|Gg3S!ja0f!&W(JC#(6pI>awn|X%)mVCV0Y~gy`1CslI(Faig-M2LrQMwKK^TC;}h7^0xcmTJCYVy z8RCr=dxP=tJB9wuKoM*gf`ngLa2COiH#pLU6}Nzw$z}m6L2kcUEYxpTI!7Ozdnn&F zYYr1?OBvAysMr?tmhcp+0wZA=kvGNQA}dcnEzmcb=((A)YX%tnpl)vlbNKB*)BR@b zF+8dqzzH}OJLV#x9D6X(ghPb@2Pk4>kfVCqnA67x2??AvEOb^%*EngAh5c}cYSk*E z6QpTWFtBRPW(IzW9Sn&CwiEhQ$%zNq8dMD=H{T4VaB~;}lqp*R;aS)*S_EdnxPxTT z<$xL*+fWm>1onQ|LH9{udN(M^ED{l68wyHpLhIe953v8T9Ot4RZ zjZ=uFEgD|{=^rV;f1bn@#!v9{sbP zO*r11JlI&vU$7(B(L~p`CPR(bF>6rT`L5(?#9J-QW8$_@h*Kn`y|Y+~a*sO;VV)wW zVNx;&0txJ#ndCwJ5o83X8~~Zcv@s58ykE2)Zs0f+@)e zy5@zm`-7otRRSbX1qrYutr!Fgn%bFvlA_cyKUh5dY@#Z@63V zm_Z#k1%RYbVq5DjYh7=4&7jIh!3N4UiZ4D&S zF;Ih2n~QFD3f{U7)L`Is`Yo(5zzv4s;h+?0Fb3}fhwP=JL%R5tHlWTf!90vl?!hb! zJpz5zDMm^LuCRjic(@Z8+R#9>0Yp(aK!xFg9^uSBri~y$&PYY%b6nFw5*0pSY&d&r zl0Ygi`1`f<28MHn;=or8f;xCV5`kK39o%X^l#L1qV+~9SZJ9WaeIsQ=B z>2j5%dNPV8P|#t-1C>*zk3Xhzj*-eadN-r018bWN?cRu;k`?_M@j0C0wp1V`G zpjp(mYl8LyJXPjMw{JnSOih(@+XaMzW*OS93YukSs+=E4K*Zy(z24gwmy`QF1(#Ft zBL5L3mClLRLwjDKUocykmg8(liL_58b|WIPgouw11Ee1&r0FKp9VwhDLcZ}}`fm$w5Z)_%Q22!KIpKEUheG3RLOFx@jsQsGIO1d>U!_pCcM!l8 zlFt-w5#A z3e9g3`MH2R%Xvn~PtcTm<5VJ={~?gZl9Z`?R|?I~5Ax}f&A$%v5S;oS-s;UruGnD2Pu zB|_tCg8o6tS@@>MblruA2!{&I{|oWv_XV6G{jtLN!iB=qgcL!iMx$Iz%{_h_s^>KSA;&;WX(_kbJUmq4bTCTZF5m zKTERlKcV~!q`zGHtA*c|-guvo?oR1{DE-5d9}_+&d_nj!5&eHh@=l@gK0)u{+Rgrj zg_%U?yGrgZ>?8dlk_QWo_X+9CBpdG&%9|tE_?{rwNjCp6$ZI687j6_9uM^^LmwcD- zVc}!K-w0n6{(*>gY?r)CXgp5P^S6opOc!<)b{8Hj93(tKI8HcAc&rdVBQ{TP*)l|R zhWw@G{Naa3qP{ib;km*agtrLq z6y7cTqWlssE8lBE`&~u-pGf8>GPWlw94;IsJW@DbI7P_s!pwKPkVa~h`7xVlzsJB9 z$t#6xg=YxACcIF1sgSFAu$*g!HweEcyi@oi;e$f^po)BtOE&XD$R9}lMCkGN7y1lg zOvw9X>I;Q^ghfL8f`Irzl1B(f3y&6ZX?m99^G+E5BV^xiuv+o7u420Lgck|zJ_7oy zBySPkD7;m8zwja9p8OHdOaGG4?mtlOo04hB#rpTfC(&E+eT9RC!-QjmM+l8)66KvF zxmLJD*dp|KB-TnkLr8luw&zNr@l!&+Q8G=(82_;Fap6-!pEu%p$+RkC`uBvi7N-1H zq0bu;<9!YEG&mz3DjX-Q5Ka@$5}qJDSy(Hi9X`ux7OoJk6`mnHPxy7=rNS$Ov~^=S z{C-8;Dtub_qVQ$mpM>uS-xux{@)3yTgoN3`Tp=wl8Q)V_ETrQF^|Z4i(qf-@tndV3 zwb1xG5pIy&EcAIN)=EA{c%JZL;iW>_@UfnIgbxWH5&lBBRrnhr&BmGUHQ}FxJB9BH z|03iA6w}i_kl0(;Pe>zc>W2ys6&@iRC!8#_`%t8(Z6Wj33GIFqa;xMu!u3Mh8ZteN zU5Q(S-x1RAkb0kg;t|O|6Ve8e@ox%u3f~u+69wWu-me04gq?-mguR6Qga-@lz8U#O zNTzus%b6#v5&FCnO_E!MUlE=z{JQXB;pM`sh1U!1z8m$>a+38uCVWcxDOIBYP0#ybuDUIVN?oX&>+?@m7DPVM(IUy2_(-z@C+L+6m&I~wAF*l{@UZpUrI zg+Ac+!nOhU%P@~0H>OLqN8s_}#`{J;59NvYU9Q8utH1eiywAj=TcAu4R~>|7jXBQu zJD5IZ1;KXlJ&m6S!NBd96D26q-~6~!pzy<*30DV z2a)%+ejWq^=XVbT5)5eb<7l#;T3+jDH@8_HZu^tvU4XEk2f@ItC@=Nxnjd#A;!?{y zE2TW%>-+7aah;zB!NC0}?`Qr&NQv9i5B(C9$NsT>csxm#$NO`ZhvBg8tUfr0aXkEu zaol;|o|>)?CJ@KK-~4nBL&31WU50dZz5w)_%J*ie{kNIw*GDo z`l4SKF=cuLh9ez~^}0gum&b8uo&KChFtF$#ToW14=9hTze@K55$>y8|zuGhxEE>2F;Vy(y5hGnf;8dqR5jWADT1Z+$&@NyYTH&do@B+smB( zRF&TlZ(+qf@Uo6?jqJ)zE325bJ9kRY1+#W%Pnkbs*6!$(@w@ZNyiv1uho)RL zGYu&YDc`=WvOMGM?BD~)m9e$CVpPS9-JxT8F7U==m466t>ptb#yF%GdPx#d~y!gAF zp40S}{_u^!gG2dTY~2WXRS0DB#ovvl==cXd(zo!p-HRSTz`|X)90ct(XVOQSzEQz? z;7IM^Fa0iJe1B>3bp;1>nTf1H z+Hk>ldJ&6>hF)SSI;FsO`f;ejp{@9vPIpN!_y+#Mcbbg|Zf9h(g(L5xIQmYX51si= z_d=N&@1W1{o!$Xu#&Jji-)ZWdx7?c}rI{J0D;^d_<{!*`lDROUN95j}9@eR5}pS^D8f2;XVfvQX>;93S{jJGbMc z?=%NXzSAr?^JHY^t{ULV2?4&-C!lHcoxT`iY&<);B9CEK^gNrr(ys`Ir<7CS4z!iN z(^+Vve5aK`zSC-$e5aihja9Rm?Y`4|4E(h3v^^{r<;IR@;`=p=3u7NqeAq^bzSEab ze6-iiXkHq8r$1&_e`hVQgXKO;`^MEXv1a4^jA zEsTfnw7vWwe(>xX2LHZ?9ryL{`&&D9*Akk7h9J(C|^1WA};RH=dN|k>+U$8{X$7$Q1 z2>JQN)_kQo3+-f<@AP55jMn{}!wBDLa*!5Qp)m8E=1LrKyLQ8O+LqeksS|*SbX7WDA#Rk{|-9@-)SbM@ASEBHGHS-sZ33{Aw@mBT{zSHi6tBYU2`rte54nS!-)X0S@ANO20>0C(mS4bkx(&s%RW_#Zoul`u6!BKX z(07^w$DA)R=sRr-oX~fg7exwI6nv+7aCjm~cD~a;g`x+qI`p09!R>Jw#|pmFtku>3 zte*+K)0{`}ou*1Y(!6eAg3&uV9O8-I)8onKp9|RtheISP$YkEW5Um05ah}N@z;~J@ zz<2s&Rt(?iQWN1jJr41>AA1?C>%AC%+I^?F2uq*SkZxU~3PT!5U=MhSt;`VU#aEH^ zot}nN9ek%Bh9a?=Y5R}`VqKr97^1a(`0C&HogR)tPwVqP(7<fmddRFf&9E>SwUPh<%oK1-2!5D$!Gje@7E&hAxGxE~2e}`=5JKYtN zC!=$E_*E!6v53B2Ci^`k+hZ%aea}I_J183t(ft@Zw20w}h$zQi#Ba&ou%f}xHA1e( zUJT>9fHxwO72N@ukAo$&74Qx6#&;laE+R0=z8rS@TC$l0md0c=H~Zzn zxd}RL9vlzN_Yl=#^KgdPi=a6a0>=?fz#a@Vw{B)&ffH73W}waqYc?~`iXDDi1pe?L zN7H5oHkkf60g>PaPeHTnE`r6L4PBFy+XbCo7`}H2vlH4;q57AC8O!@Y0XZv zOA8wbw@bgR>4BEOayZB?fVvKQ6w(lLnWe;6LDUTEO($APY%#JEE_Fftwav!I47`Ry zMj8U!Wj>F$> z@qrlxwiYAkB?mcz##_P-h}mcfXAwBUI2s-={kB;x*04Q#l1XpZOVX^6y>y8AIP=&Y z`u+JyQhfuR$r)qNO#HQNZ{A|;ed?Af55R>sXzxw;dy6Gtf}N;YR$a4bQO%gMPW^Q2NOn3x27ct)* zEN-q~Ua*y}WZ8*uf4qb9=wMVZIh;KraR$A;mR|#JFUuQAFUb$b%&n;2+>2s#Z|a-h z9zGx?JeX;NEp&v6CBl~U0IX+UL~SGe#!v~}qFjL|wijY4R(s*>ekk39mGC}7`s_pj z8dTbGsr$RvjU9wnWB)?0q)#~`ap7j?vh!JPN&kr+NzQBG3$0ZDCHNtI+65`;W!BW# zQoky>7=6kz^q(PEEqR;0<^toKLQZJ5Q*z4$XI2>U??nU*B>Kp3e z%>!RsPUFQ@%a&D{&mlt2NhP^vx;$6{4fHzDlw8x)AyPO3ATKaVp|^=WYzRxOlSu ze$*b{~?_Sg}t8pc!MP-XEv%Yv~8xOIZUz7f0l`Sr!r4|-R9sPRmJI1+h9Jj{~9NwO8C+?)hw*9t;bsMu15S)fwtc{(ZV~kzNK>Esw$iq zH8q&PxJ_9kZ%aQpPnw#VQ|#2iZyTI3msKrAQGv=fjzHk(@#DuN`X4=QZemU&PMAb( zV{_st+?q|$tyyA5bK}CAmX^lmmc*!mLraH@O5UX%lrZ=Gf5f|p&pxSZz7I&bW#%38 zUVV#>&M8fsWNW_vTlx&~TYme7H#8~RzoU;3ZIt=w!}0FmBb2I7+x! z$XEJIcczfEyOg&IZ5=hppGeNev}b$|;laYu!ihqDvSPYT!aIZy34bZ%SAVA4F8qt| zP`r1go?Poh()SW;gl)pJh2IeJ(-zb5(*yBQ;WNV5g&zpR=`LM?utYdQI6*j9XjJhi zcctVFLR8;;ZKCyg`WsxI2T!NFX2Gp;lioHlZ4BJ zUlCp)yheDN@FC$g;VZ)Tgdu!EV7 &cbBt-^bS&k2k0u9^AFF9D_nVTh6y7W}KOp4$K4qkPK>D8u z%?}9rUrDz0-;w^0l5O30$RA1mt1uhaXtqCBSU^NM3CYDmTqZl%i9&61uJE(`UP_g2 zxNxFyijXfEIj($BO5_I=qFw)icKrwPJtp-Vgy#$SafSLH2=5m@B>cJXN#V1?=Y_8d z-w^H)zAH47AC&($$?3eFL#CMv(SA381(JIU`wF=X0n-f>mI+B0NBuFv=|X-5qP{`M z508{j6`n05|2FmC6x#0(FG|d}P52w(i^A81ZwmRfiRsh$I|8&% z#XuSmQQp(fg|vLucCo_{(&-g|Lm+hSZI5+z!N!pPkQ4Hvnn&toL^4{0+Adw(;8I zmrccM*bn6eO`9KA4jGrmK$-Ld`rwNz<_7O|0ru^S?V5w#&x2rqzJ>gt>~DTtEfjv3 zaiyIw7Jlbb;;Io&t+%)YgqSFg^|C(pgV=^WwY;I71Azo|{^rLmha$DS{QkJ!L&x&) zbC)b{1HyhD1Ou~B9@F`oA9ofMspS=?l*eK8+jj-Rejb)ljqsZMUMl)H&_fMNF9)9X?{HCI4(2>DPGj;k0o5ZMTuW zeK*)hH*DPZ%qnEKMuclWdLh$d1;%bzxA`A zx9ONb_-#DOi~gB+WMKk3&+E`l1iI5GaBr{5gz0xeB%g4dy0>9+)#HAt_^ z^xJwoi=?!nzJO`G=+)46VmMfiw9&3MP|k)rIyjnz@?taaCpx4H!>EHc)X|};F%-K2 z&5RDsat(;aCYYG-#O&B_QE+r<4=0)pb#z!(o)ttJ>gy1lc{%9HhN4Z!yI)kMHHQqL6H`BvA-~Snsp3vT5KvN zL3E~M+EAa3Zsa4ibs09)IVfPG7db-XhR*nN0PIlj^3Lw-X>;tte#cfC(*4x75!13ITXu= zI(onIIveWf!!}C34R!R^C-QLX^%Frp+1JOFLfRVpbhnt6ko}<2MpOzM_6;YiS)%6t&LjO>7L0XifV>Z-L*ih?qiT{Oz0UPS;tP9SD8gjmq zqjA0%f!y24+3^Z?0yfkxe{P%)AW_&*zl2{)+E5Q*de~6A_|o`KQE3!5)Xv6vczhS@ zgAKKd9~J)^k2-9qX(Z{}P)A`y?Jgx{aS{eZVMFcGm&a-7AB7FIi=P-D&it^UreP&* zsJXy>6gJc@{fu}Q)(;zM4i0Uoxg<>#Hq`cF1h%t0ucEM_=BZ>h)Le)t3L9#kBW6Q= zD;2Pz?u{DEhMMjXQP@x~Kv&I%x{PJOhWcPjVK&q}72H9hi%iNvGLenLLAnHO3WwAM95FKL9?OeEVPqZHq^6y8NVZZj*P;F`gU}t@O%`O z9mV=nn~@@J*Am!JQ@}YM=c~9VY^dD`hT^|t|6xO|8G#zv@ojs2p$~RP&+w2-i(T)SbxfXkGcL710Nx=n%!+{6zflMnWA_f76lt>{+h8U zIz>fcL+y@ZDEb%TO@PY;#XG z1#GBmSORRQ*@9rv7B9~G@hEJlS%le8-_1Hp+1%;6KtrR0yfm7BZ$I=+9_Z| zy^dL6L+uo>q5ch1z=qn@LL2G}P&`{@V+tE;%50R$u%V{h;LEh3j$-|(%b|#$kC-TI zs3~yF*Ky2XLw%FUuo~l4oq`nw8)_aLo=B3r?~G#osh6PW!K+RbHq<=0JxBrof2SgwO&XMzoNEt0^7nkv~!^SXrzMl0!Xh$nhak0+mhE)*ji4$)yDlXGwk0@eW7I@hxY zu%TuNu%VvEieW=N(L~r#pMZGWk7XfSZ?3|og`}|l)Ws;JPaD#$OH9F#1`^lM2Cl=AyI~93oP|YTDyT?Jm<9gLa2@cWFB8I0Rq8xis z1S154>PMhEAM!caWl){ViXMl|LP|)k;vH(bsi=1}_L6nXJF@dFi04f>-)oihXA4G| z?gPlXusiGN(VZVgI&!mg!S1Z5N5`o<6Y{Cl!FqahF*Rg7`91cMS25Dwn0$7pGlIF; zi(#YS9p32!s1Af!g1z74X#E1@^Z2Klfs=B+2HkI z$J})YphDzq&9PjkAdbiR5GpOl*^th(95{A-7ab09&<89=zO-k&o*tVN+>OEp{)mU} zSudNypcPe118KkUG8m0K9M%0s-}{Ze1GZFDs?m49Ufz%{v%Gu8WpU-Gd0EG29hb#b zstybXhWG~L{j)qqVoDBgS00?qI5*v8BgvY_?`8uAVL2dy;9GJQm6=vvX zEH9Oh2}>Ju;`dy56!A{!iM&Q2%_zX9wi(dCu$RE3&i4mWPNOg|xux&^+J*>{#iDu*ib5 z3A_~10=*5^2G*5&Mh8=^UW^JpwS6Yl`DrPEHk)cqISYSn^U@XoIls~a?_R|VeR4~qmV3&mrg{GH{Zw)@ z+F#Kzc~6LG*mQ3U$GL({#90%4Qyy^ zs2NyORb4+H9REw(7S$xzIH}aq`1y<5Ahr-DvRbVNfVJoVHI}f1&{Gf36U~_`&WMCPU&SvO-02bH? zx)oEr;BuPDcaoXBTRVle@?3qT)1Yv1aMo)yn8(u2Fqo%_eI$LlGnmf~o;nuA1~U^O zkYfaQr@;`vApd~;bT4EpcbxSVtej%?_3IiQjzAt;(XYT#|3RsdG%r1PHIl}H)q}#r zg9i-?=M6#sn}b^V6K&{Gnr0?d(|(S}W6f*xBc#*x8$z{n&8S z8b1WR$?s@w|Be0D_LU188&9c+G3U7Y#k8R{d-;{NY(jHQ3k`<3m`3}O9(9dv&AwS& zhXpg14;f+ly{-%L4_M)&R=1!44LiBaifazuYn!>V{pqmWN@Z2c!q)m_HMS57j9e=w zO_>0@=0&u4-E%>Zq}i*p#z)&}q}y0q+foCpSyt1$xTay@se#X9lW%?de9L}tMVCrc zwrXf)Jq%YX@$3N`TpFN`A2RYEwJ1#tT(+>O?eK+-%~*0_;IiS6TkG1ERRe3GuWec} zd|*q{z(qq2rDkbkRqH@pz7DUeYF-3IRrA8S!*QuvF|uahvO{W{5(5`6T3OXxJ8)=X z;PhdMfwc{d17QkWzYw{W)>pOEH!Oydt7)`ixru>T_k`F2-J+`2s#LkQY2d=f23!;u zwjPd=4OBLbNLf#3%7kf0&-r|o`2QCT>;2iihk+^1p)YE5-!v1Ml9umZs^xu49p+Sm zSB3p{_KOmlhRMs}7jY1=dxCwh`?23J|KGqcKN~kw`?AaD{rO()@+anuN}IahE}zdb zU&h)Ug(!y)fE@3=+2z}L^l7_%Tmkt^hv%>8KW>*liuqx;R3SV@$mekCPZll}E*Gv7 zo+G?KNTLho+alysDrNSK_=xaV!smo<3VpkLv%5t42nL4v$k#?ZNNDzwkWZFu_L7iS zOWr6n{%`27m;8O9ag;z$ekqo_L)aHjEtCffj}T53&KI5{TrE6Tc$x49;SYt63ZE9f zCVXF5fF~o?TO=GRJW4o2$nP*rcfQd0ts&nb`A@?C5fmFTekx^ zP_nJt0ePzAlZ4BJYlRmIw+QbL8viizSK$i{%Wo9&QxxS3g|`at6Fx3{UKqx?$n*um z65$Bp1mRp^jj&C4w(uLm>x6d;9~1sY_@?k9VHUn!vHqUIfx=UT=L#PYZWI1lco;qi zFu!k?f1+gHE`PCPQvWdBdf_?3^M$rv2jcf-hySqB{apA<;WNS)g>MRN{SK7Z1uw8z zZ;^1Auv~bYa3K+MX0h-TBKp{-`1O))T@L8amHraxFB9G(r=ag zwD7mmzb5%l!rj8Z2=}zd?~Na3wzseFKqBfjK2PXrx61el!b!qeMD+VO;fcai6yGRp zm421*bm`9)+WH(Q=NpvK#&1b~o$zMqzc2ZR!Y7Dm=SxCd)~!9bTo^)a$XA_gCx82h z_8t*fEV;k1R7m?mrkf(<>rv~c@I+yauwK|CY!#j_+$j8}(0;d2{e#-&4U&q9OS$zOg$-d-pp3K4S=Rq*=Hm>Ve zV}ARaA6E;7A7t6cHue7PL(AIsw>Sid~}*02q%i`$EFT&Hku`y1o9-y!tVErDMEKgao-pY8!D z81}c9k*>@afUK9>eb`gmw>xG0IwQ_+-xCOx#J{2QVJ_UYd+d`O~w`%M3aA;U*Ge~8caZzwznjm2p(+@RgRA#H>6ZkP@h z_)TDepCT6ciN*qdm9fA_KMs)rKCPGcLVz6bk+(yR1ODQ`ro)T@zSq{k<=J3(A6;%N z@Jo9yn6*8)x_7sqZV#*m6a3N~$lmIlZr-Rv%E<&z{Xyk#ZhH}I@R1}Nd{xEF-Jz_) z1>TqeIBz$Lk}|M3H$-)JHKs*L%hzV zhftRn{4M^1^L-{X!B-jCY+>_PAm{sf=#29n9|r>&Phy6F^Zi*Uea?64oyBSaLRm~N z&iBJ1$4c=BobRVX4O6!mpYXx?&YH|$VI7(U&Ua=FKElFp>v28e=&xWmUtV+*w4E3Z zjzL;*zAr+2?r!`c=lct+V-5-h=R3owL!9rf#w6#v6O)|pPE2yXJJIKS|AQ4oe}y)L zGI`fW>o)5f>NbA`aK4{|YGZWG1n0XeAj$de#88Ykp5T0UVl>9s*D9XecM zlJnig=Er!o0q46D3u9%hs7zwd*m=x*l*B}!GrZrhOk8Ag^l7&08#t=qd}o-WPG1&q zzEh-iYwTf0PqU6ePK)K^x(Lp9b~IRY77UK(BE**|)@ArB@I{1izL%m0ZoE(K%rHxz zj)dTRcMT22-bPEn`F^OyCOO|ZSn^k3!I>3^=B^sTp(zmHuRyX{a=x#I7~}gDaK1Cl zihjXnukUA<#tTn81L??FIXQCaL|lmX87E+!^9-(8!NobN7glJlKEV=0{P zopE4&e}%{^*^_YG$@zXdd-Pfk&tUp1WV7DaHQDH|z(Sd|!2WQy6dcDt)Z@7HLR2S4 zb-f8qbe!)Top?RVg};JpRKPKM!(XAzx)6%LzhQETn8iXx0{T0ah?nW>a|26v$e+A75)X0v9LoB|X z^PMja<2~_*obUD)5k=9Ngq-hAPLGd9#h>DQ=c`6F+i||M_nWK#Gmtj8eW%44n$ zv7PgsiBmb>`7=R(g%8W*{1w~@ zR~M(fH96m%+|K##V<%-{gRU%@Hhuh7OU@KlJlLly80jRGr?bh4mj{vpsJ_G%Ye;pOt8lh4u^Q6iwmB8godt9juAeSb1)On zMAm>5&Uaqb5_$!c?CDFvRedyD$u1_U~Xm6bF^rL~lLJ1l`&iCcW7de8$cXYO+odP+>_M7RK!+_C60DU8OtLT2dY)gPb|GkqrKJ5I>Jv6gT?VLo=_d}pB639B|Uu+#}_HZ!mqJB*+Sd|PCk?+jdQ`V`aq znU_Lyl_goeCdKrAW_tr!Q*z^b9@nAc+EW~tjP`J%8|%A=5vzcjnPD_fsK!p4`&QW8 zGt5SNfn)u)M-k!7@7aMB*r{nZzi0Dhe!s;9@z*w<`tA)>DG=Qzu#rXp-`>nwP^E0S z2)nM#V4AzI<7g7@#=bWK_%!qmiP$e5i=@pxg;vG{W)Rk5Hv)Kn#FGT@9Det+-h&xa$5RX6^e8*`2w$@r@>p&i@6Y66oka;2ZhMtQ`y2{x1>0-|y|g0H5O+;0K3u zVAuUc7~os?NdSL#J70T}0NyO;QyAcrZ1BMrykHF)1^nOwG$9sjO#I^n@O?X)r2j7v z!2e&QeK$MjcB}Pe|F#71G63#iO3y{2Q;g6%+6Xi9OEyd2Z;1Z?t|9uur8QLzZA~yc zHzM%LBoFwqYI<_ih`bzR+lxR1{^i=4e*p_>_w!SU2CV`Y{(q8TI^9D)C-r;fe#-a% zo0RYN&3s?B<-AGWhi!Rj+LZma<$QqnGHuH_-g~hvcUPEC*_QL?_Mf*cAA>Sz3wWe( zs&J0*c;RAUgRo6_rjU^{UOt(d7wsDXjko>NYpL&=s2M^jrQm_yQ2+gJqGCvVfZ#HZ|vsnYKl-_LC zAb&$L-|jK}UBX9%W|Ic}dy>=e(8+Xp!h~?TaK6xN%8-sr!ZZCn!pDTK3*Q%#+KB0l zp%8e0ERMMNA;Ket{07SYR0`J!&l6rDyjl2+@O9w_!f@1; zQy?r6ju1`|&K1@O+l1!`zbU*?c(3qr;S0idgr5i};X4BRalG&nAy=`b{y||D-Yrw^ zE<8l&bH0z1?Aw;lkbJCgzHp)Nbm3Qp7YKdZ@_li@->P)?3ZE7JQRv%}NATL)+AHiw z#GE)-IEaY8jZ!?BbtoS#oFcv1oI~$(!27o5KKFa8(yddzGldrmFBKa1JI3#N$vy}C zZIq$EPkNsN{wc{m_xmf7|0sN4=-ZlqLK)>m@s5=J@NLdq%3PYRzE zJ}-P#_=a$Y@Ll1@!oLas)g15q>cjr{w%IEspC*$X5u z5-t<^T<>copCL3~DwKDDWc%HNe52&sgx?oFEPPDJZ(i14;U9%>3HP+o#%28P+Ds2u zzI>*`3w{55_-AdRd6%`{CK`i^4O7py1MwF>JGl3C8?Py;o1bm~lnnFOabr5#3i=zb zW!!iz^7BxB2RnUh{LPOmhXR+xK$#+X!e;hQm~#b?0rt9|?V5w#&x2qf6W3FoAO7aY z)k5Ki8JFmU^U3d2N?bLI+WMned%C% z`1wngw*g^44}yW|D38~BfAizcf+DrN{FL%IjDGw0dB)GfGAdCXO@;i;kGm9#)bff^ zUKBdEkKfAt@~%gidHCDH?Ls7&i~AveV;pz>Hl(I|4L?#V{6valJdMeS{x<(}a=s5p z=`XsJY~K?IqkBz$c~^Z-&iAdKlkC%6;P4pUfQ1-NmK5E;Wu#>Diy6#uILl0d$ZvM8;b(_W=zYR?AFOT04{5a>Ym2X`W z9kw;HE7wbhEi>$%gXOSX&dr{+J9qxsA8pw=9^sk0vms|o&W0R?9F-h}9D*D&*&90^ zl85qW8y!S>&%ydST6lDMMfoG;y>|w4;#&`^8(Me9N7ugh02tqYu{%(jv-PyPW?$3k z7rR5H;jKTayVEqk*c~kmB!2v-ou@bMObdMU#%(ya-Kib&?nNN`YZzrdR3`k<7Q$Yd z2A{B(o=8XwAB9Uske3B;z)wb^w6w_Y5fiLO7##3qYKQGKiI{`OQa`;LClYL@KZFV# z@bhpQz;>EH)O&EiAA|(peLsQ)C6E=o?=u;$X42C9MJy&7DqzV6;177;ABQR&+KRvF zG%NFhQJhBLeP<(rq>BgdJHwG~h$Zj)`4Eivy%!=gdZ8)cedj$>#!8e3-goMqCEY-T zvY1}H?=-KB@wNrL?`K0zQ`kE&4B&mYn=Ej?1?f=?-gjmV<}-X-51yQ~qoxfr29c&J zofrb=j z@i2+e*h}aOc;8)Yb}SnOf%n~sxv`5V9w9M5R>r(XN-T`g5E;DhE^*J;(;SSWBqr^s z!TbIWTlENz9(dmw=BW3lI3iTB+}N#6I7HZikf zH?gXYcGTc~cjWcXjvBo0E^lG%Aa?QLOpX%ms2@fd;C;Ut&7&RlP&5R*@6VW69OL3{ z;C=td#Qrh99|7-s0kmmFN#1u?QIhxFbs)+6?&=*ITg#$;o!7(imc=?zd^+zC6O+8} zuBh_Z@7av!)#fQ?@DJX1dmIAq`*Oy<)cIfl?Wk#K58n4G>(RW}eeBU|IXr`DM|~J8 zdR>!^cGPDho>>d*567XPk$2^$yEFHqMuRD9QWo(wE1#U?!6H-NjFgw=zHM zs2#8Tl=!1z$l!f<>1V{tSU>EjIXJYVeu(kleYck-u%G35Mc#LwN@hpxu|U{S^Bgfd zYEn3m_dOl=Yi37%Ig5lH^+a?vSoCr@UduAT`%Wrq*-`UUa0ls^NS$(!Og!5iq%~+$ zI7H8#eD4*gI6+gAQsp1d7c3F;aoV;gLVnosxT`;Bp`FaKqvo8^6*IzTMDo7VkEHMn z6lT2dUqyiNXV5 zR@s=sj+!zXWisrjDIe?0KJWYKP{jFyg1qk(IOc5}GuTmIWHRiic~PWbMZu1m2Ztw; zWXJpdQz&}yszcs)9^4-Hu#Mn-XRWUOXZ=jDqn?i>u%o6*_R_p=VS>E^O*q68U3~ED zBQ#v%!Lh<;at`)|XbpfJ^|#pr@V>JI*io-##o&D}H4%2yn-GutF%Q{#Z$J~)HRFIjMp8Y#yGdt=A)R5UZJ^U&ZomfO)Zx+&chh}?hCAX&?1iVJv zN*DbeC3+)^7{*geAc4K;b?Qc$t`2fFbzFAI8(q|fbeBQC1bcBN(;b${%6|!&pL~it zQ8(6f{8U3j>SBIV@eViLPa*S_Sn+!N@s7;C1$hb)&HM6Vy1RH~rsFTlA=Dkj@{Y=3 z<9`PEr`StQLnB5ZqsKqx3@pf-mJNFMZzAG%Nbv&pe&<2p*B7z@9O$R){~c&EaCjov zRn$b5z(4jLp*rt!zo_0w(-XTDH5`GV*bnqmT2Ygs;je~@n#ZE}XAuL7@?P_cqGkO_ z*sUn~L9}2$&`)VaeGM8i2B;{GyvIMS4AkZgM#HUx{PDX6yA^de0(W6Q&`)Va@jCW6 zc2F~MtS(~-l)TgOtO$NY`aO0lB90Nx!+tPRSax1E$79D94jqC?6b^AJ9Wn%kq)oyv z2pLR?%ivnuR^Gb5MWCe42nHt zSqB6rbs3B&9c>|7%9<+~{-9*WcE0+99bf$+ zd-By|4uY+oM@MsGAlT}~XwL&+8z;4IHP7oH!i6rT?&M*tS);=u9icQDreniYhUA)g9AP5% zU|@OcW(MXtVbx{^cx6D$8smuPoe%0KTA(2~szx^~PXtiTS2egeOo z1p}>~jVlXgj$z$5Gx#0sUf^WHjo5>MwVn+#AM~InaG;rE$e`qyrv-+jOoqpifKw^O z0^Uph5~c;3`C`VlRPFMlHsF;bmV1W+CPFa>I|^t8*ybgF6|pEmQXBA?j(dj!=0ULt zI|^6@u+2;U7NUTp7C(%L<=&xyIw)8P3RnZM%}f3QqJX3};4vNd4h3-jT?XYA>}fb6 zoWFOvaEPP&hzmynwz>J*o?~T7j+H4nRwi?xKK$E)+}z>F!Q#0i$kMqZh`+Y=#9!Qe zU<=t_{&_kXawpvu$bLipMy4d`kp52mWCz_BJ@4Zjc=%&OTF%bDXTT_PdL$X&*jzJs zKQBMbm{ZvE|JU3ZTH2~Bmk%4_oEa7_YpHLkT)c4Mzm}w57TjD40FOU-^f4DkOsmmJ z*M`i}@WH{%LE%j2+;BjbaHe@Tly>P752qt|aA|_>3t;spmH)6o;atkY^5OgG4H^so zgOk9W-zWHHClr~Vzu5TmI|VOpB5!}GMZM86>XMYG*E>dCniBPDYE)M60z`ERX3^nc z2r3R|1)C?cU7c&m%FnhSro`%d%H=%9nvxZ~kvWGkACd)Ev0eW}x=z9GS|f*GX@ais z0x1rA>0QFv!3l!~!Pm<3k__*w8k=ew!0p~pNz>uVs^-NhEacOUnl@=#1z6%2wl*%S z#(E4eFb2~+>E>JN7dKQbH8S~*H1kWVYg_79BU$azDwI`OndHacha<(`yGji9jr-fD zWu+{y$#`G2C;+i}X-$LLHh#?fxh*x#E%O&Htpay@>5%!gjm@VFn?HW)>`AjLM>w2c zK6}Re8O@DLK+fJW|LF1K15M>1XSekx8rwi{UkloM8g|zYs=ZOdj?Eo)j@!x388*ai}D^T~kJx~%da^T*JF1pmsF0RF)>05mooyf|=? zah?5qYXj_e!uS_CVKhx@I4XcYnA@0v3r{hRhLsEJ0+scR)h$?IrK+`!r@_+37M#?T zEsN?G)i=P&z^%>_s9apNY+03E4iHLNe1g3AnC0Uemm+s{6*JdjiI%1H@RO)q#+5TF zE9XvWY*-95-->0GEi3AALa$udoO-pXtzXJ|znCKi3Hi}0{2dqga-A|h?PFm}ZLqh= zie^umcJ$mSN6q4JVPOYeDzU(gU1HF?x@rvC(#C3BJ?ob>wKdmNHnlb*DbD*-YpNL1 zaMah-pyxOyRZH6!?r3XhYpKB~HPo!cL0Qp?YafQQYLzYIvGma4Rc?Kc>ZPaHRTyWP zTvYbyWPzmP(fY~;JKihN6XZxtHm+Rg{{Y#La6UEI&lShF#$SNIRsoU+OvfLl+J@Fsn|QsofmzhpR?Ufpr8hW0 z4b~(#xRqQ|B~XdnO*ISaYwK$kxr0!HpR(FUo+kKVg9{pNjTWxr&qfUo2s7cRtm3?O z4P?29I|YAR7vaYbwfr0M`15(d-}oFbE~oIU^s~d~guWWwkoI*iaMUm;tGJ|7z&i-R z@W=@Rrv}nvk*OJ26S;FJ-z&ho{z9*t*WK%ZbtHSI_0^NAU#dL}B!y65*WZ!?0zp11 zq-;Swo%pICQlxG{Jh%97PMp5|Ifil&52~qK(C#VQH9@l?N|iI)1%zOru!o$phs>w_ z_ALl+iPSA<42JERU?5*_QrvS^2j7bJ+nN;53Mo+pUP(}fobFA;7L-YVoP0;YdZxJ^hC80udY z{#l4SeADL%M+z&1#|mky!u+d*X9zJZO@F2E9^qrcXN6>IVg9(VpKyfG>`@UvTXMC~ z>`kFxFZn{@X5n{*_X~d^d{Ov`Fbh+c^>-H@BpfANEF>o=)14{2T)0)p*W!%-M3{{! zPq~MXlwFiZ3nvO`6+`_d;T^({D$y4;SYq5 z3ZD_aF8n|k=DT;)Qy?r6ju1`|&K1@QZP8)m;|DY5=l5^oSUg4&Ckc-e(%gc2E*Vd} zMEGstox-08w+lZJ#&9k&UoYW6;o-um!jpu{gkKR}AiPF+oA4pwHsLG6_k+i4WZ$o1x@4cTzfN+4uvK`Pa9@5DQCLZwq%y|FPu13C-UE{f*&T&VG|f zig*AK^_K_-34M3F`pp)B;hRKvBDFHNViCGop22i`*lM6tXaLdY#O4uhP+c?d-@9p2<`V7dNVKs z9wq$*;S}KvVV!WP(0-?pZ>8kZg=Y)-`k3`zCA?O6gODG_8UJhH^TL;eZwTKOzAxM@ zT`vJ3<;9F#bLvO${j9{S(mqQ-Nqx%z31PADI2{Lz$Ky(& z^#8cuk^cAa7D1~|9Q@N z&%KiXq87jQ`9(}lQ$d+{PkHyk})$IuWNB#%6mafE%i2! z{o=iyse`2T0OkYv;bt*;6;PNo^M>Q*vcYu9l{XVm-w#)Wdg~;Vn7xaTHg%A+o)Wg}L1|5m!jk53{@|9+1&Hm@F_mbYQgJ*Q1uMA!7NGP_$= z6iN)w*T!NPg!$J~n^wQZ9-mRThSge!{=KxHa^M{eDu~9HgYu60_v<@A6+bxd=qH0z zgZtwhjdQBE?)Elo=FxD)JQ}*qSzfZ-zt{Qv-e6>FSxH05h?2o2nbqy9x9(}bGdOcv z_0;NM-(Vpnd+_L)_O77)(YAkDn~EPS-dNmWr{nLub>o*-{)1my(P#Ix`@}wBJ@`Xu z(0QQqXkFg=-JbjabYAGZO1B=IA~%c3dMJ=$_J!BJ2|Fd}S?o>j@F!dY$Rv0~$(U=P zz^uT3iE|^0c?V{WV2;N(AEyKL6wP~V$5WIl&<%y1vyk?V&8(ry>!Sy%!!Kof$9G(; zRDt6mfm5XZ#e#unut(#ZqUk8&+yRv@n$F8sXFBTpaxzY0dKN1B`lKtOP#>1b&)~d+ zKkI0=LO)Y~_l|Eug^z3F*H0#g?VN;O1^OhjL(bpv6KGKB!0E^hf?sqsbU|<6W{1~_ zA%09Ea4RCMBYht%27ZxFz4kC4iBuxXlV23LAw=3im_LD=0;`~gpKACzjA-CCUplmO zOLd;0!P^~HbwW(v+4%(&CBH~rK-$5lF_BZ4cFsb6sDm1))OJv0hK>o6{TyC|pHM+M z(`bYIqEMl<=nbb}Lqdg#x&y)RFVX8zVTKly!h2ySRM=UIieD7!n@G|T*a{e^n~G^?VKr#Six>>^qvN5$A|{20vM)nK zObs&>N9Y6*Gs2x{YN&{rVP1cRibU)Z=A}$%n20fcQRt+g7j1<7*sGzF6PV_x^V{yB zF(HcdMi2L6_Bgd+kUilGDNhs`7qAHzqU{WnR+|id(Hyk4(hi*woJs3yyl1pyn${cH zvr@kv0&m#IewT$b%|-KzLbJMZu!LVk!wC!U!&O@Fc^5+fzlhNdf}y71Z4kq}Rtqgi zW10;OVK*0=hOm2hZce2Ocy;L4!EE%A{G!l3?W6+vMWK7mOd!7~v{9sBxB+!T_k~8N ziJ27s8JoIaL>;Fg^g!AY)pBZ>hev3W)XfYha1$Rg`Sp%G`}eHjBJ4B7lpP;yMx0I)6}zReO29} zFj)(s=hDay^JHs&QRq)%syN(@JN;#;J0{$Vd+C*g57qWg2>%Z|`C7Z-0P>6YlrQvV zlDe5goQ7+;MQZYWDVq zW_p4goyY~Wi#QE(xG26)2>ha()FyZ%pD`c&A}t3acd}vdi?o~+p%;4y{32aHHNuC; zA@GY{3$ddakqVXvzewljNB+Uh0>4P}fBHrGaPYw|()oiTcTfhui0mE4Y2ZzA2>c>_ zDk)N&hY^;zMg1U-QW%eh-Uub)rw(&x! zp9zJE)4*A%4rbvOO*S%4>Kv{R_(dDAF`48(CWW%?U<*n_)VT!wA__RhBU6wY0>4O) zpf{4q5eC0VW&~Q~hWorUpLq{9AvrYE4sNHZOYjo{zlZ`&HL@!BMOyYpNTmvaU!?wz z$uDAJ4+=}SJ8lg%djkBNe}oUKL*N(j-;Ac-VpZ^q^nUb4{>pg*eh~|kU-Ulr0r*Ay zn;^gF1U3zRk=}~Y5%P#a;1{h>_B6jJgg6bitFBIq{FZwe{33n8RY!KRJ@AXPtocQu z9~*g5B*J{~i^idSp3x%{U>FpX)EPc@53i(Bsz&v}U#uWS_%IuVq z!7rj*Yh?0^LTfyMHBdzOKqv%$5e1Ir=U!MU&Nim14-mgJ3~u6 z&TCL~=2<5Mei3(W=RNEr_(g10xBsE31b)%aPz3xUs)R?x^A;u;!=CuOoVj?PibKmB z3pq&pyd?7_a1I`agz5lzKz#HS0>6kBz%P234TE3A>o3~|zo-fMxE|w?(sc{=kLDL8 zobT~p4l7yw;?>gVc^Gsniq*2C?KqvRBQ`>n0De&wO4)WdUCjf2(JN3ySFmgrKgYE+ zYZZoQN!CiVWB5f^L4QuxNEiaY=u~!~+4lV$^%UvPvqJNW0!N`c9*~Xhg)LkkBEMtM z5`duY2yP={Qk(O7dBl-e#*IzHp$ z^S_*~v^Ok+o!@@>-x;-~S$uEcSDO@jR^xg~&-#PZe>Z%pU zgk;Y=akZ&66!}9~jv1=fX^>9UwVsu>!m7cUUH`;dA3<4%{JB_rz6s$%Brd?(i=}#h z1q}m^ufd8gR6`tugoi)JVYO!ly5ku~&t=Hqfqe(oo(mytM&c2yN12knS3%47pZqhD zZJ-5bG|iOtnnp9+@=uXZ+M=RDsclHc!0}C~)G9*4nTa2}?8Hk=Ek4=nhP4+nRIMS9 zj>n2_bIXS#;o(mSR=ce0ORUMQpM)|DCZo1~HWHOsk1{3I2rP!?Y^>-2M}QVQi$uuq(i{8{!Ru;3Jsp9Qgi5`;nu zLn#zKh{^2i@+VQi1|H^T;Sx5+vcL) zvRZ*U_gWJOe5t1?UQDgS3c?A2^$*1TI!YCrNHFy$x`UEH-)dne!2Kc^vu^H}<>N^u zPOic^K>m-Wv5UI5lLP+ld+RPNgog^ z!RpPQPEdb#)#tUmCNz!qatclA_)`a`v*5Oi0;7GwWtm^Hu_V{#5wv_q)J z>R1bGwd0m)J%PK9HNX}#d$BcJ>}nKPtIAKnuUc$B`@q$2eY}A?)-2vwjz_&@(0YH8 ztNf$x@(HmVkhY8wyrO3LL0Au@ZH$$*6myMbTT!{F(ED?ODXQ6QRHD}}x_jYOHrf<- zJX93v;;lB)@(h+7SCbx_MLB0-z124QV>z}p75QqhZ5A!T>Q<`yS{duMjY(|Wb1D5t2Wil(He`y}p}vvsaVaw&4+2P9|^-S+QJpV}VwgZcx}Ioa^xsz;6CLC}DiZVwDGmAgGBM(_GZV zo;2xvoTR&I`#Soa6^(Wtw2t$6lI}0+Iu|tBzOggRh`JX5S&>IR3jxi^FSXlbNK*MGGs+&LU~Dk=(1M7{Q0Uqw2b*26M=^Ch1`q zI4s`-YY`nN7(j{)i8El7{x7f>=N0s4gP{C0R?fHZXoCc#%DI&dvny-M&pOm$qexFJ zMU#sPOKZRqD%I_c8aFjMqF`WD5xk>?`2~Xt3Jdy1dpA@f(okdNkxpT|wn}(FvH6YYa?%aNm=T|q)odv9dzN&sfzud<9 z+=_w$)Xb?Xo1Y8j&XDS|h6*Uk8p^AOV1F(cSeZNb=&Jf??(B+%Weruih0)yceWSTm zwRO4RUDcGM)|{HM#+usMP*ye7md{5YavMRI1vWxQHk(_ns?RO2tDWCaRz80S#@8yX z@9*Lfj~O{`)RY*1Q88%?29W93sHlF8hS)V1lq^H#Ek~dA#GR`qE)K?0_Czs$-E1%& z^eCSk#{UaM#@M|7CX~i+&W%?8vFbS2p{VL7;?VuK&>$B!)F3WaY~mkgMV6Mv&$hEG z=i|_+ELC*CvWf~)WGB@vBn$j7E3%0sObdkkuD7?Ab8|yxnofA2FxtHK{?EeJ|hn!jWV#kAY3uOmKUiW1EGA0ls{SU zG(q0T(jFgj5$6dm6}(9B5<$AGu-rPq^@1A(9~Jzg;GYEF6I3rTQD1%f8W_N!(4OK? z0QpT}%8CyGoFTH}LqI-TWWIc5ImLGX-YoL}2yPYpi{OWX-Elj{dg|2=@C1>^3QiY1 zQ}Ap-6@LTeuNGPH2_WAq@@B#31m70?RIokn``B)_AU|bDd6?h?!KH$9fnh#hEfVh% zzlS#XEo-vtjAcZ#o#*`G56=L#+nyi9PN;9Y`K;0?ffWrB5rO9d|z zTrYUP;1E!bDESWv~4LVh`A%$eDOXA-fEO;WB|_$X8Jtet#NWGWAAcJPv0D|U3icN4BiL7v4)*N# zFu{?6V+8pkhxyfla|HPci~5Cv=LudYc(veK!5ai`5qwhc8Nn9>Ulx2r@EySq1wR)2 zQjpI4?1z`v7eI2Fi0XR}!1f|{73?l}wBRv<^q*qADT1d9mI_u08h&V_$O{FR2%aza zBSAU>((YA)>Us(C4Ix^pt|0Joxh1p|24Mr4?%jXQBD_B-^su=h5Akg^tqy^e;Uh;5Il*9a`aN8 z{tQ8Sq*3N~tci3=BmPKGT{l8*5t*)M%)eWZ-e;75FSwP6cIbab{ab?cHKV*+@SjAK zqsJNbD()$e-er^xZ#0iG%F)M+`eB0fC8KIOVjWo-p3aaZ|q&th8C7373s3t5=2Q=cTf>nY) z6r3m6B)Cj)x!_L)`L%o6xnA&QLG?Wmq)Go_{u6?K5G0F*`acQM{f+W&!G8)my#7Tx zK`>bmp!SbBKSNaIFf0mjxv9{c$1_D%FKb~hDsqk>U(T`}zH}w3`%WNVxKbW1*!H|W zMf5WTD+Jq~?-z-Fv0$^{GQpLCs|DMh|JRBBM!{PJ*9&eCyjyUi;3mN*1pgrTJ@Jrn z&wrSQj3HJF{z}x+3%^0EIQ6K7bIiS%a($p=nsb{A%W;33#Vd&tps7REi&zuEM>LDc z8x937y{saW(HlHubcD}dFr_WpW4|V0HFc1*-h!>SaNakI$*X|Eq?z|vJ3RL=opt5S zMB3f%tvI+gph33F_Ds9H26EebE7P)~(3!>L)j{F5H*LT-;~_hExWutBi?Me;6mEOf zu$PZa_Ad#m>EG2zn>t8ZufU%6H>MQN<1y>DcQq~wxt+9!%gdO(8HSYkF84Q7#H4pAqu;9^0jTwrS=(lGckj5KuI>7<;VaF1G>wdnr~bKF-G!6y)bC zUa|f;C=a=y@4#=$L*CF^HQ0)Wyz}mD?^&Z13;E$ws&5#6hT4Yo;ww@fA!c*}hV9v|6a&hN3$JhAwP zk1)sU%Vo}SOpotaf%=Gfs6HDO^c{z(fS89@qgI@sJO)J^#7BJ zw4!n9L`vVjh2KvH+3P-ftm;48=o^HFV}Af0Kn zK^}6TP+IhcA3`?+g^9WY!SGlmW@s@f{3z-K3Oj32@sI<36W>sV$U|;IDxn5HyRfQl z!-4oROymRxB90Z>&S%@lhRpU&M!CRoB6`D}DIPCkFnlMrB`{dTr0|E_pdlirh8x+n z6GY6w*W@7%6)`i+`<_6Nh+V?>u2kvPn705#l+-qh6dB}l{BI!7X;Dh4K z2-`{FAG4{}aSj6yq>WQ8>o|vjO;R^Aypx;wh#DpGkXKOLe8lDGo(DW+-Z2CoKZ1;E za1z4|zZTdMep89P!!{dwGW2&PY94anX=zCFkOR-i2525~V5_t{I6RA{o=tNAp6sG9 z>7jw=($bZvdB}l3iK*i7Hg@A>sXHdTozv-+ga_63P6+dMCGc8162Qnq{tLx7lTJh- z4|vGuaf{wg<`GODau(ZtMnce{_U5tpV_mbsWVpk$X9e;34bs6CycmA3S7500a;DSIh?w zSv`~o51GeR06b(KN{Wa4M>YT+GLI3(L%xp+@Q_KAR6OK!X%al-d~B-XA(Q4901uhO zNr`jFLqYGPdr{i8la$ELVJB5!+k9Sr1tY`W0u3jqt0+}wfAVih+vBv27ef8NL7~q6 zoQ3LO79Mi8kDLM_$51Bo1$U|Pq65t`zgyJDT!ZyJ})(Y^D)7fe8 zkhKClWIlQcfQPIV;34xJWB@#5tpE@C9hLwOS+_zS@)jc0<=FaVW8^;PfWVWi?f6!C{54i|Mz(c00i_O!3n%$USTafm7d7w-DLvAB9{G@@7 zf|$TLn1I(+ssrE)Pv;hZhs-k{c*rx^FnGv{P)i>22;}2>>>c#3>m2-OLNVfL`uVag z>k^b-8m+~UT2Z!TN7ZS@I^tTW5X3Tj07}`m@Q_2`A@kd#(R!B6dJ1KhX7S4&OR}ob zj^QDbDSl2?C!9{eL+*i$P_yluhk5~?>qBeowB8VKNr>N$!O(|rX~hL?G^Z@TG^%ayJfGX3YXGtm?KitLY3ZUf}?SaV*%X4+RKv+;KzZ=>#Y z>aJ2cUbXR}EvG#;+y1H2ZG*g-I^LJsYm%-&oorsV;B6>~eZdwcp3uU6W5TtKWvBadYTWjzaodQK z7q^W#d2!nd-L_9fbF##@H5nRh`;@rtQ{uJ}CogUraq{A}4-_Xa3X7LwMJPJ_ss-mC zF2dSUXh)&wj@5@CYG5ZasrxaNP=pn8gwTxDvFdF#t~AUVU?(!khYo0ma6MKP@{ZlT zN9zgfFl&IFX!_ooowx-Bo>t{2;8!hO@as`2uU6ofQ^&oyH1zEP zjg=k_F!ujhfH7Rr@P5h7rO9z!C-X9SSaRwz?}g4qo{McyWy0f+ZGJS_8iwZyhhvQ; zyGDw)5UFkCc5P(7<&G~0jWwqK{n~J9_(!b$L;e*`4L>A7AKA9C#(2+1{b_=;1#1PH z1TPR=F1T8dw{fh0i{O2NCf3-KBL7Knhv1ijS-96^{XD@F1Wyv2DX4r%QEq|A7YMEs z+@}rTo!}t8eA%c84P5BJLxq^I>O8q5**9rbo@Hc`_3I17dhv44@ z55}b#hg&kX!@PS{aH?RXV3XiQfoGw@{c%IR%wZT=Z9nY+{eC75y!u zzg>`@iDJJW5ZS~Yzu` z?iBn~&~Om=jFJ7}Yi(k(U_`L9V2+@PQDry?eMLW5ut-q33BcZ1kxvo)fgoSNus!uz zb6~T`%LIQcc$pyGnOJ_U;7x+R5d4)OzdOxxe3?UhUhq}H*9G4dG@OJ_MK+uSoBt!I z&qq(hwp;|h7^1$Hp!)xUY`6yMe+)9eQOj}_g6e+_a-GQhLO=5t3pNY>SWtaU6!{0^ zBHSV64JV;37lALR*v_8>ak~CmU+zLFm%(zl>@xHJUyGThRpb|aiSwLUOx|!PaH_V7B;yZVE$em6 z5&EbC@a9MNYZB1ZLDI5u{`6pen8oDroMzI@b5bnpulp%C6M61-*XLN)PLyN290${G zTVLh(a5*1EzFACLbx^qNt;K-yyiI%fn~T}I2x(IXNyJRi<(TGT^3F%vZEwBH9{(3i z|E_k`LDK37dyMU77GrNU6mEN)V2|6${_&2+*t-#F*2%}pWgrSv2Xvah%;S2epefga zKcxlGnZ=ab1O?M($vmR<$L-iI7ry6l_wP~H_F|J_{rf%A*t~jxS|-4rd#;+ch_2mk zEkn5|lpUbw9U0r@{$ZQ0;j(VT{ObvwS&Ti_ahH1z{d>t20-AF0RW3MIyD6*Rn6L7n zXf$7G^e;S`2MibxjTZFH|Hi(`Q;ty$w(?cZeQ)RZXWz4Cco{S4;q}8W*if|dy5zKSoxQ=`rQ5F#d3M>Jlj*VSB=1VK#+B6Vv_?(dojT^cz21?&J)S)$?eXkAV`Sz- z7jJ*(?4sSN>nHC{IzV0$@`4A*3nI^}@}7DR;fVKmKDDnahV`iW)(0uPc@EG~zX-pj6O0Z!cb1?(xvp$17sC-e`P!cQD_IIvalTx1E=%9*r?QTKZ|z zop--WZ|RTTwH}&{gG|pKug(9%Bz~~qR@V+UN%%|CPZch}Clfrrp*U?h&tN{p{iWYS zj#Gmgp0Sx{5WGHqkH9&NHO6=3WQOnbS5(mp+A}-z0;+<(5=z0q&tR>MA9Z^c7C-82 zn(vc75p|p{C<>qI3Z}cF-_D@)g~}E_D+eizANW_l36;co8jQ-e!{{FHuV&|*9n5S{ z=|C6c(!ZLg8RcKyANE5p<4AyiwV&y;VG;h-)bA(G6a1^^A}2f&Kk%yJI8VGNhJUrr&D2iK@i*n9A= zHgTSgrs#_E^c7`SoTssv1n{q3gBG3aW&4Tq)B{~p{?#+F1$w;Wah~`E68Kl^j(WqN zVgJCt+8yT!{?#0;ZxZK;o{aRbrdxe@IyW*N=gG%z?i1(fcjz_!t4UW7|7uoNGeP-R zOUJ~&T1)%*SO1hv?c-l<;ym#N3jWn*U+ke6kMqR8Sol}}4qc~zHJ_fqzj}ufbHel3 z>v)`}9h?KL<2=E?S~nE)uhtt7^RL$J4h}D;sd${HjuczRd4hknHdP#clii5NdD_Y8 z6p!;XpSkfkPoGna$9dunApEO&1k=BIBpdopah~Y3tNp7vIuTw}(Z5=6kQE_0m;Ti^ zp#l0=zr%c2oF@i@r+>B1Pl}MlNdIbGKQ+P|Ci+*uhJSPVSNCCgSDdHE&?x<@=@jXK zf3@<~b;WtQj(gn|=P85sTydUOQ+CC9n$7;Y;yle_eOH_(l3wXwt@}42GJ@^9;ygXV zd{>+&9#{0Q=3%A$tDj&4?l@11lHrc?bOTMg<2=>S#(#F4r5B8Tk?pmK^F;q@eLyaXyvX+4ah{5J;JD*FRnUSv&eJt4;g0j9Jonvko@Vpl za>sdE&aH6Ac{-onbjNuz{?(lCpaXoDI8XGiUc)iJkYnnK^R$#>_O0SP(Z8B!g3dha z(7&2HxAOxWs{_V)szQ-N73XOdw;&$p={z>;#cJ8nH((Hc+qXbP|LRt8p6Flw3T`l?^g=fN)pM|emSokUn(?nb6-Lj=3S!s7 zznag@=wGekJgL}Z2<>z`ss~1)Kxnm{{s;sU=P4AHI8UT>gi`#;Ey(17#Sq$|R3m#L ze}O)f=8E&gZp#MD`^a*}Tf? z0e=X4M2MYjfOra3bxrf33sYBs5$lWh1MBqM zPp}=#8q6`QCKe5!iXfds9E53%bUsl%1&5xfo_Ir#BKs_b(1=U-1QgXS-AqlviVOnl zA1Gc8uIQA7Nd!KcNBEYdEle15lUkUf4Oc{nct7|W1K|`1rp9Dfjmhzn@bu;aMcfIR zxqNUn2rIm{2~)5lkj;GM=gs>=2#Z>n_=y%4w=i)xR?nS6u=)^c1J2w`>ajeH zupTR7$PhMQRWW4PVYb5>aOP(6Z&=Y5;RCFQ5oD_|BeffP0!NKC;LL3Xkj~ufDPQ!X z5yEh+su5U`WdKwxg}G={_L)eo8$N1@xkKu91i+Pz+#;w)F$TTC9mylQq6)5*&Y) z_EHg>xJ%)T{~X|Tm7GlAbo8TWgO$^w(yF=1eBQ&!X|kB^qq7K{sv&Eh9{8Nt%*6r1 z9in%_6j)YE7yNou%BvOl<<4<0Zn-y#IaUu;Iqa?<{aT8_f10~~dD$F%YrJp4zsX_$ z_?W+bLOw!iB;@%LjK6+579B~%cIHQsnG|KTjU*jUq#)1jub-DU%@=k;QTWUsmF^3* z@7S@UFVpW-Gup+;U?UQb@pS;Ag>W}WLwqSpo1cz?-$SwXXf;K(9`>jEI%G-13Au>< zQ6BZB=(r~Zemf6}8F^~cdY_QoPq{6zyHZRYYX6ISCl6r?hnH7!;3t>NhT^!8BP|u7anSa|`)` zC{m6vGPOrHy9Ot;TAEu2Fmj1}6c7 z?$ELuVrS=?%1U$(d$w%O{F=Fyr3@`m+Em-rSgDS%h1j(V<|En+2BvJ$!U~N2oB{pH zbg@};&TOnXyVAmOD#P{dI1RD$_Mzi8oH<#YBM(OlDXpDbHV3;EJCnOqO{@}z9fGIk zza?-;5^gHoT!%icn+)D#3{TEk7P>HaQQ%_#a^H`iQhv}=iq+Zy*L)0p}H1FdH%!|j`C1)%N()zawy`6WWpS8?>OGA`27()E-21o%@&izJkXI4iy|LI7x7(V5J~mPqMzc zn+IMb@+E?YV~ObTxrKM*7@vCuHw&uoxk3N7$e#)xjwPbU>tE$RjKu-LaX&+FuHfNV zB6?i-wIzkHp$mio(mZSR} z(eNht$d>XHL4FjCa+x4M;6-_kV3VNXQ=BjIMS_M$afQg&2-3Zgc1%o%+eLm%aEsu< z_!RF+xgCO^3+@r*3t+Yr5ab(Q%Jh>Ys;A4qBSq%hU+Sj_mI{^&{!p-1uu1SNL4HM+ z_4!dz;wnMKAB4PC)FQ`KFrfekRDb)Rfx^ zb{5PM>?wGZp!zl{${#1Piunb3q{w{5O?&*D8&SEO0qGw?*~E0XMC2<4*9fi?yisty z;0D2a1s@Q6L{RY|VgG57`87(mN4HesYl4a|3Hd#dcL{zb_>~}EtFm5DFiDWF>#6TA zI9RYqaH8N;LHa4O{7k{wf+j}9LXj086Xnhq`69u~1+NmMTN>^CTyTTn-GUDYJ|u|C zfUo7#^pkmz!E$(kX3mHI0-q*!mHvO7QPUY?g42Y$*8sHQ6i~*{sihl!Sq@W2E&Q)= zFU;f83oC9}4qC1c%Cv2FnlXYr>{_*q#;;3l{RG09{DYIlyAJ>J8cV~9D6(7#u75%p`zflt#-#Kqn7!Bgsr5;Ul|HQbSI#FX&b7a4KP+RI?~@dt_mdQF(RN?a zi0$4Hn|9ergJzyH)4wa|59|sCUIZUzOTr7qTZ=pHbVA*?ZUo=uzFl^RcEMr!gqH4r zu03)*%t>jT`Vi80`X zrF#LVWjD?l;Ivc&oC`6joPn7mPz3yzK{%?NPce?pu^mrQssLRXom!-wv6(egd3~p_ z6g}je@f{Z{RiGnH27M~RQZVocEVSXYkVor{rVpf{DC&E2GEQQ;2o=43(iJ(S8_VQp zaK7RjwMlG+AFlPa;^}TmA_9iJLG(fAAf^N2aZKVBf?v*n@{WTn}$TwxW7;gG#wR zvZ?z;OinAERb>Sq5PnE%n4V<8IH%>G6yuy0-m(Vc zoR%ZGALE>sN7?H*r-knB!PcCXU~5iG@EO?v&1ng4l|By+zd}=SPRksMtvM~hIH%=H zb|cPdVNAYYoYV4S=EgZKVGeto)3TCV6z8;D&4#`cr^Sn!y}iMio}l8iETUZ(rzMkv z;o`LLCLMBy=CA}KTiCFR(=v-2;o`LLCN${cw9pSe=;E}z#m#bYTEcA4#cAP9L(s)( z>BwWw#c8>ZvWwHw%mdiPX*r4YU7Qw%UI@B4Ei>7^i_^kzBS9CZg~wIU&1rdq4Y)Zi zB)J6LoR)`a(#>gUrj7q>P7A*+6f~TcUtj~0f`}QQI4$a2;^MRva`RlAmM^*e2jaBc z1-r>X#0(&9C2}iwzKhdB*ZZK0({d?IgVUn^kMZ~{fr(a}mSD37q(Yc#peYxpP-+a16INK zcjUAL4X5RLj;V{&@<)!@x8k$}4X1@?ouJ{g{E=gIKu*hjD0-+kEsS~)jB{G9X2Why z%MX!{>#-SVvg@7LKbq4LLd*cgX<<~zrBTx4tSDB?j{31jz-eJ%rBGW=i^p(Uma=Tt z3n;TR>q6|HC0YC=i{Z48!+TEFu`mQq%NTZ`SvW22X?%s9&WRE5pgSHAT*&b-oEDEG zoR({t>GLPwj!be|)FU3hkv);OsSmg~E%dzg1Y2=hE<^v^oR*hShl@QI*W1|>(Mxbz znC=Z_6l?Yy+%uZfQVn?)b@ea|W(#}Cd(hR?O+oL#Y-vQ@KR|vAYmR2Nr1E_y{cm?e z*Mkps>=TrZ&sfjJ+T&E(8`|y>5|!U`IJdb(>qn_{XH{m5 zN_S&Ar>3^RvPY$m7Sjv1dSLBUQ(FjK26f2qi*!e(2P2QqAd%k>x~|mq9*zEdjyv}r z>FmV94(#ki6yitKdVa;uXr0xYkGU9zyQeC-NR`wjblU1Y6D5YDgtm2-Dna6MMa-7g zS-p9CUJnErp%4u=Y^>(mFomycMf;wH85IpvvW* zg;MjOkMgp`J~uD~@-bJk>T>*Cf!AU6$yDjdD=2$OAYS|y6upVXnIpw< zsKqHxg{9c>p3m*hwzC1o`ffvE&lh%*60$M7JiF~A&We5u%H~*}J$8r!OmLR>zkmgv zx4YO>I=b=;y0R|+qLe?(r24O7QtgL0)nh-zsa9kvoJ8E!a2`ptr~2)59EL~O1?iLQ zjl&bu>~{9F#M2T_O{D%PpH-0V@!vZfrK9k$#wt$r$E)ShE{-YI#zDdI zIEMBqiU10Ewv&8Z;_<#?6MH2^Rg-;%BL)?BXg}$(i2dCaPE3#D5K#+`Dg2|Jt4;*` z3qm@oGTQv8Q;ju&@Elf6?_%mjtl-)ZSpPu0uSZp}i3C%BVhdBOgcu+AZL{P+CN&3O zYD{v~pc_t`B?B^eBLq`pva7~qS8*G=1OIMnL6YYxy@k`v850bnJZR@*1;fbO!o>Ml zp(iX?$!Ub^v4X z{DTSIiBkz{v4RIixCbkEV4fBxwrIiI!i4U`5_czDJg_b(aS>Kqea96ECe`9mDAX?& zi(>UzXOZ^Bq#myy5awV7n~tEny4Y@E|7e&sK>K1+{RLR35!PXK@CiLNX7@ut`-Dwc zSp&2$CfWDaF+8?H^BmUw(7QN(98sS&w8844sA(*XIbGsF2Ysp(gzs2#(L{lvjI-a*BG+v-sP!!Ri?sNMw5U$>dl*s%v`p$z%oxI>TBdnV;AbV|J0D z7Td!;orl$LeavrE#upE@TwTNFRm%BL?o(X7)flXb$2KtvCq6ypQJi18j4eIY0CHNj z&FKOihefVpRElR4v#>|`SdC?)FG1p@{piO*$FoY?^3$N3z8^hxGxwwCVNkmty<5la zF$;I=Pq41Ux)$s8SUE3l!^(-V2`guXdvR~)+qfS5E+n_sky5^oC^Cm5)XdGTt*fof ztt^{WGhO2L#KOcF=lO#En&jq+9)oGUPmCJuWzA8TpI6PlYl%^VR4hgf(y!x6r&g&<}%M!Wkud8(tGo!v&Cr#Ilo=h`HYO;aP$r*#mW zP6+Lj=s(iesjt5ZZKrXI-NAH_?+2GI{PhL${Db3_ll&bJ5GV(GCLP0Y`_k__x=u~) zumTVvW>qP21ZXp5V7w__hz>#Xf1IU;x!;s2xQf^gMQ!Pfkt~M6~Kx~ArqHKPdTdu0l zEw8JcPY%iujIUK%-`_<99W!#=s43r5u$@D}T#HXNOrS$aL^Ja-7H>v-bK#)+wj{Os ziKrBtoCjj6;Y&C;JC!1vAgndDb>EPy7H6ixRH22RzWnKDwI-@5f?IrY$NDw-#Brmh zju{4eVre5L0S{aJIb*Is0bb!Ogff~_H>+$;Y0cdFriRMW`uPpIpJ!E;F?9%|@a)4| zD=nQga+_$- zd5gO4Ie5!4JUO~7cwyio|HZ!L-XA$Dz<4{%b5l=`;sfzypfS2vXTu!zXpTH-uGzGkC* zk>DkQhk0&#TyDWl9LMJ{&rOfRxqO?0@wi0rI>BEG{zmXH&rOfhl{lt3UN;HeBlx)B zi-PY7?h#Cc#{=ti5zG}lOYktyO^;7Ao-*!_=eAn(R|{T8#CYB+@_NC$M88SohXuC^ zJ}3AR5%u2|`EP9J z8GxXGKUeU4(O)9+D#2@sIM=KbyixFO$=@jW8`1w(aEs`l z7JNzcuMyF|4@Lj6Ah{80yOVXlyn-o2w4Xsly(2}RD_AJ{;Y5@hCGs@MpDtJ?`m>2> z>qmlD3EnICm>~9mvWKUE3b9)hrV92J>?7D$aG>BY!I6Sv1Sbeq3(gU26kI5Hp5TRo z*9iVh@Fu}u2>y>CT_HFQe-PX%_$NX7|11M_Uj^ye zP5Yk+D*qnH{Jbyq^z9)YBY2$P34$X9PZVs+b2Ray_)%`!p(7))UT~q{IfBasmkVAd zc!l841g{rt%WI^M5$ziuqv0>UDf;&WcL;td_;*42Be8x5LHZL>K3b6eLzIgI=_W*Z zsvuo`DF0B9?mCn&5L_X6sbE_kqv0#wE%{FgZWE;UKka=e7{Gx`IZ=>4K9u_k9!G?W z7`=R`A1g?Y9?JBiBi0a6j($Cq7YovThw>`HtBEK_KOO4nbVvM^=+%7(^3C}Jhn>nt zwnAKvC`=OMJr3)45sV7v2<8j+6IAylC_h-_(SmKyJ5xkIQ?Np??fGbt=obq%3oa8} zDY#njYQeRFw+gNo+#qOCak6olGZOGmK9|}7L&(k0B(D|ak0Sj0PQ7UHTISxZR#Lt{T}xI#)K>;Zy98_ zy+N>7giP8?!fNdCn!(gT(z+`X_RLOnh1Wzh)FN)(?|WAo|(YRT`>+MXE; zqHB6s6(|>lvIF#d9>jKOpKZE^%UXu{cNBDHG4@!;U2Y}%cL1K{fC8{4&2mtlWkErq z=4Bq7XSsm~DGm!ge!amvk6870Z+p+`@2M`SzGnC+a4d_KTYH_I%Yr?&`gf&ze25a( ztz^;;@7c3IY(CpQb_7zBb~sA%Ab$kXlXm!(%=ld+ke;-|r{od9H@4;2J&Su3r|xvD z_FG@rVQD*qHX{{=Y-_pqW~6+OJ!kj&usPwv9i9X$TED4&lx9r6fopobFTC~=B$7_X zk$r>OmexNWuXi*C9JEO?KtP-9LGbuK$KGKSJ2<^pm;2&s@p}j7Kph9~k!Di@1OcsRp`ZJWF0+c{#FY2v?f%xI4 zrxRJ;0nG)Wy^0}+i}2&SDbNfxJm|v zTLB#g>u1oWFzpOQS%miDfTaE%KMd`~i{CK6yn)bO>Owdc+N&8Q5QQbY5#2;+FD(Yc zDws}Th8B~;zejz9_R^vW?e#adoJ|_!Vx$u2d%qj2+BUTPEG#m#*Cl8+Je+MG8`1`> zFvOP8NLKL0sW;^^0<#B4mAbY}5oC*=z ziyNv#dre2`eUw(4oMp8m-9?4=8i*~><2|Dt)3p8r6hvq*v&}ov6NL5}qH=>_b_}7t zI9L+ei-r@%BActU;PXy~kZz|=L)RGEi&4(QM{*+i@q|n z*B%s>&|Xp@tyG2fl8#AeFD=DFdz}Ciq(N4&sry4()HKMz18M3WAUie8XXFU&rR!$u z=w**2aFjgRUBZ_!ck>Zz&^-@Ad%a6jk00@<5_7`E9NaBoM)~t(_YS|0jX`KHGIc!J zebVq1L<^z4bVISwUU~y!p}lmwgTpF9(6ea?s%}yE1CGaYX`PffA`PA$7D9VzQ^nye zoK7!GpT~rGTZqtJo6%QK_Jr`!%zdq0M}Q}LO87;JZzfGpTQn_v5x3~=WFEl`?Ul(* zct<8%1wK2^4zX%`^}}&!KZ8HiW547eD}`AdevK~b&|Vy!NDZxIG@rTFIUjO8XfCj1a^CN7O zp}n3|`TZgvvpvutb^f3TiCzrt^=FkoIFf>mU}!IWDk+NaTSN@)rOOvbDp?;iNS!}A z!h17@_IgXz9~0StZDwdMU4BC32(}LzBnJn>93j)0p}khB^3x(bt{B>jhms2I^%xrf z4U)$Qcx9f*FR1_x@-x(MvS0N@$eL$puYnjEC;N3@Bubm0LE5+=bFx41Vf=Y0=$-T+ zO1pNF64^NvIum{Jd0S8*!`=oBC#b6^Rc3!~QH7eJ;k1nxLj8}BrOy7Gh3a5NWI!I5 zM;RHt7!h#U`OXs`2CSEof*aVtTC)CXL3bR4k zz3QQeEaRAh21$XtZxY80G{|NpFR~JNQly|v9bqMK=kP!hxzkRD_WCsxoq5(_XfN*E z&NpzZK!aqfy8X?jQl{lU7DYgVq^gU}(}0@Ym|)wG_IY`rgIYvAw-K7XO8*{y6F3Lc zaMY;|fUa1^EdULYXFl6LVh|e!4KhoKxDa~{-RfG2AD^8MTj1IHXQ6u5MJTW|ItpWH zMX_3T^mSN*!Ly-aOs@ebW!v3!HOBP19g1i@%Vw=ZnWb5LIJG2eE~**+V=|1Mlhp_N z6#U1dkinQ<^H47^j=~x{?MPJjc{f7UF&O#~&W(xK3lq@2&`w|SrO4!7=mztlT}Jjq z_~ttFu`hKqs^R#w0$<>C-$mrenybq(HpR8dgB$zZ2WV`Z({9n9)9fAO2<#hosG2z zzu945nZ(=37m<8{x}9wIDy1VW`+e%@Qf>bJ^%oal@19e&d@CuHmNn6gb{``n}iIKGku-FgGe0dOX&gW7$v1t?KgRnAzCykT1HB%AVsar zw4!6U%(vC2Xp^n!7o)##_QgKLiv!Rtlq)}@$1vIl9bwDhlR9@+17clBsE`rIO`qC` zupraR=aj)OKEGgkRb9iGeW#BYJNd-PrTsNdFP=PM`hF^H*)2Fy-1%guBqW0aVwM? zf4tsYL_l@>PrID2e=xFi?1_`d4x2J!w2q(yAMF1HUWH*)$UJXFAi=@q=2*0LglA@~ z`~NcG;xNVHzmH;}+`w_DeP0oOz8iO;Ey$P&(vv3Yz_P0f0&m z9d+Vx#Gf`1fBsEje$@MAcbuOnFJolk74fj-q-D;9o{MbH*o4P6KbmX}I~?2RP{#J* z81IMkppX20I1l`L)&3a&3g_WC*r3nkFu@YRDT1d9&J?T_Y!c+XDeLoYjL0`V#A^kA zA$W)2!-9_q{!#EX!A}Kw#ZEgt1^K*+@<_png0ltZ3G&-rEVn}N7QuT2Hw%6#sJ^3y z^6Hakz#Lq=vwmMezP+S8QE;YUogm+9GyhUS6_Wt+?IJ%Q_@v+mf_nr*xR+r4OhM&) z2l*6{%LN+*mkT~5sJ`Kk@*jx2S1GM@ z1Q!Y}7d#qIq?tcRute|_!79NE1Xl_ET<|WzR|V-KLwjEdCc(Leau>lqf`bLe2u>HA zBe+=b62YGd-YNL7;5NZG1wRq=;&D6Mogg?<@LIuJ1s@Y^m!Qjc6D$-QD0q_K1i@1T zrwf(~o+o&*;3a}r2(A%q5xhxoz2JRZco-uQ~Itlh9Von?-m`B7m4U+s3 zB99UrBl=TCK3#C8=+6|nPH?H<1%k_oX#Wb4RqP+Mw^sDGh+f71fqsMN9}xXRg8WVl z?K~s0iUEZ3T(~_rtP~~*rV8@WncG)1N95juMS{hGCku`jRNOV#=f}Tkr$Vq=uvu`K zARnW#+)BZaEf_zL!`}Ex)8lQB26^wFc!7Rbvf_((l z{{YGzD{_$_U%0XUSV8sw0Qm%A?>!e3HG>s>>q|GX76UCX)hlumpe1?6dKnb zW?>%Jy97?b?N@}FOT778-e1v>w9@;2D0TeygwEr)uSmY!@~!ml zO0^Q+KPkbxa$a%b-q6m(%blH$=UVuxIIB=50pEci2qJ8}Q;@`s77u!Bb8L@qoGiJBm) zk@@yhIU@5KDa0EeDM5f+K;Mst8(JE$%I3m+6CVV=6;E22m`S5EA(;pR% z$m!71jm06G0*=V6>ex*06OZNBIQVot7P{rY5t)OQnvDu{L{5Y~<=qTNWTw$Z8a@OS zh{t2uj&8ycS$7~9K2wRYcr5&|J{*yCu5m;@NIaHA3=JKT?_t}=;|Gq&X8USrFCLGj zgkn4%%ahm^I3nx9Nnu_Z!4X*+58pvC9*^Z{){VzwnZ<_U@mRKSF!qVZ0!L&o+6Xfa z1ssu?=BSUN=!(aZhMf*a5qT!9^Rg}wkH<2PVmuy;!+y7p z#{x%W4wg6~XTU}R!xM5<6DA9DaxnxrBJ ze?)t9M9xMZ#Sxj6)l5*1$WmS$k+p=0fVzSELiCxWBXSFyx?jYYBk~euC^bBbh2!y9 zg51P-JeKR38;{3Q$o&|P$8rgK9goLy1RH7{j|Gm%x}lgOvfhB0BeL%E;P8z!6_3ZF z+#6fRV}T>GHdP${irt9EW8wQ_I3jx(j zbVO!qI4rbRKNn&++F#5c>akzOA}fVi9ln5F?TD=6u`H%tS3DNw$m@#7@(J_dh-~7q zT)~E2@mNTDr6aQLNopia*%gmvG|RiZlG;o!UCvD`%26_14{Gdd#cQ%OuES#itMArGEBW0}bipTOMN7WUNg-*A0MCRbo5&6%|cg17jaYaXD9#+Z`nQT-# zBJ&tgj>ykb;f}|$ktW^oSgL5_KRX_aa)LMUSV)pkj>sw=i#nIM;;|HP^IY**QaQp0 zipRqHXyu5!9s4~pk2~KLkL65Ob;V=3gr?z$tp1y`;fTyct9UGdW{JnrkEUGlSRQ6o zI3nx)=#6aVyl};1d5rtO6^~^An|8%xSx9?r;<3;X`F7|%+0!D7IY38b{$+Zyt0Pab zy*BY!=!mTI7ezj1du`*f&=ENnkENLw-0@g$<)P({$MP4p>5j*;mk3cZ-SVCcm$8tGKrudUvkjXtW8Eu79jqHi+ zfIgJwipRp|Mxl1C;<4P1p4lfP+3YeGGPbzbf5i26_Vci456x!!6euTQ&3=WtBBeVQ zGB0McC!;6!u3)Q49yU2&um>ZRj^9>b zA9KEpuvCf1yJ z?D9!T94At27)vTAm0dnr>2SeoWnsQRG~3iQH{ z2k=7zJsRp3Lf4VGw?STuHD?&7?${%#%fMdtW6kM+40~KMN15*J=VQhGj0gQV>{lFOoti61rrJ99v!(NRi|@^C*fFftaD#i333`xD2K>^^eTf1 z9^TAAg;oonIKgd}z#<3ovhJjcO(fv)4Qfm!Xrrt6M6k`myI}+(Ah0VmJE?^!RzXI* zxUGXyK!M}hgH<^w@Bx->O}QSh9;@=NW@3{T7O7|n&uL+CEWQB@zYHBOsZpc8dx-H~{oT5SdT0iSOysOCX^vv8b_!-^pz=x$EqqeOPq)nkM+F#Yvg zjn)#Yd#uYrNCi2K&~O7@$4X7#uGCO^8!M`_^K2PL+26rBNjL#30&pyDVS*cgB7{jQ zIf1}o_F1c@_<4%c3p6so`Z=Qv@%hj$!-^IOT~N$pttuumidUkwYP5gVhNb@QMO{>T zyn|+e{R|uiO_u!+6I*08zqM+Dzh4(MAHKfN+8k%ybgci6y)S{UsyN#}=bn3S?oDz- zR&H2xAqldE5H^K?Ea5819#9Z81PCMwBqU+cBH&hWt3XhZSh4O~Ew=9aQnhsj7qn`v zb*Tz2sIA6Q>;HM?JSVxJ{rv3qec$ij^ULI!_nnz{=FFM1-g%$FY;pq41UR7b{cVky z2IT=8j|p%1Sf_*F_SqV@&$tiJ6KKJ)p!W)U{pIeAcVv?-{#5I3Jkoa}1g)c+{Kqu; z??rs4k!LmeXE*tIRC(~cbjDe|Co|5f6K#4;@$#UE*>J2L!Jpr{?>-BJ5X)NHiNGo?)L=+U_tNVYcJxo(Tkj-Z(ip189>;-HV zPJZtk`wou-o`#8AqI@Ab&2eX<*!$BW=6Zv?wEtgC7_|NcbL;2+XW@!(Te#wHcpNMx zw>_w-|A!n79(7gN#_fc4}kD zmcnev>$)cd@ZH#rM$NJpz47haF5#~gmZGDIe~Vt6meEe2(;tM7KmX9h@g``%Os=(XJ<3A2)h0zHt7hao48YN z$DA}H<|C7{%r2URB{`h-MNZgO@qxslf%G1Mc368O*q`+|tFW3!(7_INMco;t5C-JH zMIt+p))$@?#lifnoS+SFihn;6F^oUt(V(U7ic-JbTq7;`E z+is;WUtL>Qg?ak5%POi?*ECiba_-iNz>`N$9zQvbRSOn0)-IhdkA#YPE`LA*Z}6j& zQTqVOZcKq4Tf3xT^gpup1Qxc$Wc+`xGsL&>z5kv55t!s%y8?a{#vQ`-uK2gRLZAmp ztp6SBOnCkf|Gl*(;43m@5S>W8H735zjRKbpYx$6YUbg?<3Kaiwi1;235uRs?cZJpn zGyXd`DJ!@NhVdb4tX;LhJ7wWrgtNQY!nhdCe`DYZL?tX;Mks6`YSR@T7jY1M-I#B0o=nk8(&_j8w^I|FtP|Hrhs>-?=H zD9kWkT8o{k@J9CE=R{#ju>)E!o8Rd_@n1dr^gs9j;}-lc@|8$fdO`;ex1+Q9sWBKIkRsj)*uM!EH!CW9Dx$E*y=0#s;8Wq<0dRpxaH;ULcn!rXBwpy*BF@*%5ONL{ zG0DK-K;ckfDG~dBgyf@yQ>C9Hxk9*5`dY~i!t;fjgg+5pExdt62se@x^%Rx&3Nu-qxa^M&Lor2fakp9p^{ zyhV7Q@FC&T!d=4O3*QlPk^=2=<}H!adx>d6{+dVm5Mhz9M99etOg~CEU3j#R)8m+4 zCFFDl%Ik$2gy#u4wSnn33vUzNC45NusBo8%(??kDHQ^h=_kVznsBCYu5g~PMrfX|5a*N(mODqdNqC{qyeHr_$GhI*vSjk3 zxdx5@F!J)f$%h|3z3Z`6)Ns<$#>)9Xyo(#G_G0+l)Myo%1vQK2H#As9R1_WjW#j+6 zTa?uaeS*uCdDj9Q;A=t|r?T0);Xm_X=$mbj&;zD%I|KobdEc3@FY+8*FW(QnjmM7L z5eNxt>pTd*;|*4umo^qMZ^fgeex2}NSP8+zkBMLyQc`nVs&Mg*@6qSm1HmK9?}o0nDxIniFI*d5oj zhsVWMduJi;l|j^+0ec+(-sYv94n?B9+yr~M3ZR18v7#`MEq!IJ zJbV0xk?upJ_c>|Z8WJ9=|yXJ{9gDxW$zpipBGQA?zlcP zJHI6*HlaGdrBlp4bjqIYV>*`GpM>l_WgqW4x-4mL*tsA1!^mGBAMm9wC3n3&Y);vi zyX@w!WxkdY)fRuTZ<})|e6iB3zLR$1p}Yrtv387#FOT<*4~%~n-_>Hh z5vZP0y|cytU}!+7xPAPY{f{o_5`TREQ&o0pNxV<|!(D^pUE_h~*W>WG+Of6lvNHcA z%WoNF%8zXE%_(m29c3T(=>9YEzu46^9&FBuZ!O!Ca@Qwzc+8&o7~f~@e7#$IeeQzC zR`Ry2vZSWeZNBELGG9}u*&ZHhx^|c6WyQAbdbiEj>Ua!jcTDaA9nhw2K-XGwv3(lt) z+<{ouIH;VTphTb`dluuD!9<{M)`^V&fO(3u*BU)c1P;yG#Q5jTUz&Xt;+PA3J|yQ7 z{0nyPz_*QnKNtUlcfgSCT#j}p^-W`w9lE9`)th+I#YhdoHw$MRe6y0SajK9Q=0jG} zb*V!b{}>jNuFs<0O6FVG3dB;FpT1d1SBANgMdTLzOS(E~2h^C>8{rB#NjC(>LTh}p z`q0RY4vRW-Y5ZrMf{1gGi2Inw4t0aJ9pet4yu$5GSEg4&ksIzGqH9#-*Z3D6ki|Ia zpl?>VL^b*&!?7dbk`%WAp~zdPFkF)Dim8!9S+t~+D;nRd@W7PO#t;{YcoEek^UY=& zRA%3Bft(AA1>vEgKR_3`h6WA`d;9kQ@`i^=^heI1I9y^V(t~?YDls*3GTSmjVtV9j ziX$avM`~F1aEZB*+gQ;kiJc=un0d6sn3dTD9UQX56GDS9#v|o8s^O!O8E3Cw!#Kx$bIau zl^Kk)B6{kCS9ulT@Nm?n7sGOO__k0v+DPB5@a>r@z(pd$cX%U#zFFZrC50j@53SyH_+7M zUAmyPAdHU$amNoo5gB8|o)J#94nG+_&WP?J5#eW4k?WfkepWl+`euc9s@~E_7n*uL zV}U695#2>1!Y|2GS!5Cq`YS3sF|v?H>DA<}XgU{(c%O}YJ+mIbMIugM z<~LKXH>tBCS8$KsPU9KOMIv5dMek^^(Kn07nniQWKaQ51JNS=!92b7$ZO5ecbtu`> zAD-t6v3H`p42I#G<&G7|>1 zl;N9|hNnF)67dil3g0X@y*NseoG^T|3QYQ-=sMO1-z+!%&}atQ7=~}w5R+aSZD9TI z&2ld#qoO|Ahi{gfzbwjys>1Nia?_8DK0^#=ATHwg);;e0#vEFw{JErD+q1)Ss2 zjqD-#X1P7+kJ7;^4Bsq`2-L_O5BO<5_s?i!TKI4~)Dhz(N(Zele6uLf6d9nx@Xd1N zVDvMZhHutFv<~i=STF#Q-pH(Gci0(*Z`Lv#n&?ky3cgvzCaV?gK^eYT?s4=-Ih`~N z-z;Y4A`wxVhHn;c6I>)>6RU=Amb({6M)$Eie6x6i$JrMh4-CUM>s9DE4zigazFF=G zR~;S5{P4|kRtVuDm)rmi56mYc1->72J+ara|~-{m3Y=NW>qQ1HM^ofmtNt z7UqC&7EPE%B8IU}_-45ZEE4f7cM85)t^$ihe99c~&2kl3B*LKrzFDpUi$t8ju?OEQ zw-zoEaUaaHRi;m|NCagz%E(wGg7Rga%ta!?@Xh))6j8GFhvAz=frl@f=RSP1eq&@T z62YrF1!D?}MDXD7M3UTbUl_hwyb^TcRVNJJEFRoWJ=hcQ&0?)?{aumA6v84A`;isC zSyXklc^NRH8w0F2;sHNT^v*UllK(#Kgc6F4t%q&L4t3+ z9oPj!Nyl@no?~a-fqY3vqi!D@wa9`5M^6ZF)Or^J9u`qahmg++rtqhdC@&bkKrrnQ zB=Rts?`T0!_C-IZJ}H=bI5L}6B!0w7L&3l}DB96PcbhJ@_J~xQ?dNtAvT(DnYKI>* z;_R=H`Hb^PoIgP4Po(Z}qvHqq3#j`!S_0>-8<3A5<8P(zcJv;cw^%u64t#-7V7#ct zwkv^-AIs?iQ20BRJtCd?o`C!?b^NkuA8B-1XdpjK7al|1c%$P3*aZj$bkv$)R5zl# z>91J$JhL5@$vzp0=%EOOm8@c-(Jh6{HCqc8BZEE3=$aunQOA{^?8!#=5@ddFEHI8* zQ!-ygcJKRP0p?UpiBfYh`eGA8fpOTHl1CjEF5~+~;oY=0r9X9aWE+Q2xEv0;2!tL-LU$v687f>2OZF$Z&qAJo1g`#4*nq}LM`nP<2-YDxa4472 z693gPQlIudEcAQ?31=hASqQzn#NIohy%L(Au&~vKrB@?@V}z1tr{$%o$cJ?{l|Au-~SK z8j)VlQoJ&nQa^%po+)+6+sMV)HV*%hoXq}h#xX3Jk&a$Oo}VD}^h3B0k$Wh7f#l~9 z*@@80E7tD_WWgTL9?dxX#~-Kc*E5W*cai%Y7N;#67qYJ@&{lg0*$BP7BC>^x%=s8N z0Y9$}{rBSd`Ci2AAPy$yb(AX}jltsEZKqNgu(EQA<$Ku;h6xTgu*BzR4!ORVKVa$ti#w0IWHxJxm$x)fxOFkIVp`62CW(bm$ly{ zr7@p1V9Ant%XuX!&=pD6U>Y))eeQUMU6_`Y;-qy-n;Fcor`vSL^c7esDI=jod)ixV z>x|&ADFwX}XopO677S(~3xBaqQr^H}Mjwje8tFRH*~k`-9AGKgw#R2tpVG}5pVc27 zk(zZt{zzi}LvhhhV}-a3_dtHUI%U~TTB7|7`FI*`SN-qUuRrAVkUyU?&h}-&eXlgK0MVsINYNQTn0u3FCJs6$`2%Tw=a0d z7#!DvL^nq1=}Qo|Q5?K035oZWe zdE_MyjCvzOM`MsihSCRffdbfcZoYZzP;T)_er`ei5!PB{t0TY_{!;>se~k5O>>Wt?=_xD|g1WjwhJAt2K=fLx3lne>)>=KRnzBGfeb&0w*ju z*4nk(8M(;SdwT+d+@Wg_SP!Z(+W}pRPR65ITl*BVObeGW!8)2yXQI;x=OCC?F|x(g z6D~8+qX}2ITEcY*$h~$uBR9MHw*fq)@cf(T9a;)y`M_p zfkSS>EEAnda66*T?Fb%MoD*#wG0W=+><%h+H@f+9p+d9+ePZ@}A)ua7tDLYJfnK~n zfQK&Q+~W`=*Nd0ZdD6IEyp-G?DJR^7084KIxSKdT?p?=OkI(hAOM%YN` zk;8265#vzd(>?ql3G6!P?-%60G2nh=+HSW-{<9$sEpVtcVljzb8sXk z%s0{Lga;8&&rJ#S%z(;l=Bci=CUkUL?@r}tW3%X|%Fl*ogN!=d|A?Wt+0h(VNmvKV zIA&5}F5laazT2)H5<-0@X!Z)e9YLlw3)o8WfrN%r=(K`8I+>;0Eba@R+wClBi$SaJy53L6pUEt;Lnae~YL>!zpB`;+oO=ZWoDS3wT>si8$ z$!9Kj?wQ^?rfqW_aFuht;`l)qMc13+2^I0QXX{d}KLvUn{zb1IUle~~wcgTfpLZb( zTAz+cZL@{LRR@V7vE8qk^6A4eLH? z84|k2ZvW91O#3uIFJ%IUc0=FvymKYJeuVDUY^f*17A$S3X{cDdU;#ut5LGO!T2x7Q@5Ynr zsv4lffOP%+8X;gE4}3y$MB?Je)~WK9@F9A9KSEn*?G$cAMl*)ZrMTGZ#=3m zImLCm4hMU*50oHhJ5yzj$^DdaBP(36e~zpXXMRzj#3_sg+7%%SysLlhEA?#cIK^(C z(>@;+Ix}oIXFCHXWP7z6-|k2e8e-BJYkhx#N4T|9JIcBa6ljgzwS;>`&c04 zoDgFSUg=?{x-pRM^p7^|Vs6(_eFmzntv;ZWlrS=TmHx@K-lMeTRg< zDB&+k2xgQ9;f0RgLgH6S-0vo4b@vk1ueJS7AkS&R535dg`<&5U!v5uM!WT+_%l$x; z*3S88xlP~q6!Z-aM4fGX=Cjee+?kZ%9AZ(Qd@lof7tZp@vjVxOJSo^Ckn5aW6ok7z za);?q56Ah^U@_Vn2uv)((0Lsm@lLRSUhz1@@2)L{?n2jD{&e2~&hq7xCXSw12Jb`p zth!$FHOt1pPyK(D>-<06YyNwOM_QA1VZH!k3bixRdv7$2|%q36Ba>X-j__}`N#z&Q7lbbV`c%=SV{4KLkE-$7#QnWU$vwP&fdLZb8t85cWA%) z=&l9TvHGf&HT2evl?)kLJao`;v3^Sz)U6n?ptc^bJDdqPkeW#S2$e)-UQ;66-f* zV65MwWwre<@3>|GN-e3WY^Yhb7)rXqH=+&w8n7lNumL*GM^2O%)%9CYyR5OkazWz= zbiY+mH@KnAi+kd@$w$oi9*+60L;3$6Km59KcTv&#|2%j6*3;tqI_6Kq`T0G)^WnEo z3JWYi`ak5P-+E5``@Qd%)K@L8Sb@EtKCb*_EgXRfR+x?7q?u6b=)P z7RH7Ae97|s3`kroTq5L`1?txc&lheMUM{>^c&G4}!kxm`gzpLeDD!T_#itS432 zL1@-Ogx>SnCwDaS%@fuMPZb(pe57Aa8Dr`y;dMmp`_Gl{KFJRWACrEU}9Tl&G04-<}*e!S#K!nwkE!YU%{)=6#@o+SMl zk~avAZ$9#Gm3*nt_~=7_ljI%32Zg^Bk_(;twOjZH;U3|~MA-SW?SM}_9h|>mVB6Sr1aw@PZCa-{y52%!bQ?Am%KuFG7-n8M6`pmeb}E#!c-#kIg&dF3y7${m$093gwjU~ zz(aK7}5h4jy)-5)4@o$w6lHwZULf1&Vl>8~cDy|+n!m+*e+AD8^3a5oY4 zy{h!R(tj-cqx4@%wlRN;{gX;WxeQ^Buu$o}geAfu!o!7Qg+~%$XQFVfuu@nhTuwy2 zD}-x>rwPv$ULf2;gx#&eTZlNuzZAYB%)_H2_1u^rw^xHWO$_qMlKNbs`4tFqq2yk| z0m8w;k-{-T{%%e?{7H&fC9DzF3HkdZ)7J>s3!8)&3ojF1A-q@kpzv|wlfoB-FALuk z{z1s8wyf9T^B6E$m?q2-n&(2K^Or2rt6nT>Kg}sGE!okABgkywp zq2ZK*J>xzAoF%>Cn1Wm-xkgwgY!v=LxK7Ba%50x`js-p_nVwqIKPh}x__FXd;afuU zyo>xFN&ZwwFFxA&N*LsGE97KhhA>CiMc7T)Q`lE{FsH>R>FEVSyWhoWQK@`Y!ev6U z_BhHP%z1H!(l-b>kDK+F=W*celJ6EiCVWEpvhX$G9wAp&qMbhpzZCMqKs~4A5F^42 zp?S`SzO&>)VJ{))l(XCzA-#ksPZD}u7{^NHd~>FA;x}=PaJ`Uo&#C8vWW;NP9yi7< zl09w=v!*)oJuE%vsk5AUuK>O&`47Smg`Wt$IqZKg2gYR7!TRXrK%6Z+PPj-&cNC^C z7p@SR_ZY-algt_P%-1ZuQh2TKXTo0yIlG?uUlP*git?Mny+XRgQvZc;zc7jKC5UrX zKVqh^y|AmWyRetgyeA<)XY#Y$F~Y^d6NUA{mBMwx(}hh!I`z^HeTa!y2yYbrO!%bm zS>bNsE5g0PkA-v>pgq5kt^$-h2J2cICi)lfq=)P){W0n^EuG8d1+%I zV>nu)q+e2mb-bbAw@?gK^DNDASdQS8LDU+9&$IjS+~I9rS``#toM|Iqs23~H=A~6a zPOP^KgLMZgV!f=7`$23(@X8=+E$V7nF-Ej`X?2hj?fr378;1%$gS6T^3vsUuqSg;# zk7d2hOFJEkM0@_xm}?0g+sE_KYu_b^du0%{K8L-|>^N;++J%r4?QMZQ?jP;p)M~YN zHR3E&jKD3k0Pb|msEuh1JA_`o!F~UG95go}UzuzXxF6i^LP%`irD$I|bZj5L#C!Yu z1mbv{ssos9AMEjZ<85pkH)6u@unPKF=6&P4IB3c+{(2eaHe}*+Z6xxCm zyWQqRJMFy>+bN%feA{xvn;qbsG09DjShLI0nymcDCal;E#u&S)U9+z#8Ea?vy*xBL z*p$>9x}>5y(0pvQ)0~Gjw9Ct~%KY1s_ToO&+uGOhRIA6W@!R7&;?KWtjXI{qKWBD} zztfzunfv`4X70B>nzrBn)U^G0$s6|3t|@ztbijz?o3dx3z0#WSzOTe?9{awpeQ2QF z{OkQ-z)9Z<7M|oAKk?gB_E=pVv=J+mXMqvNA8Jb8pY~a>=}P!G zXEggZS$jwM^7q+}gT6T})ouzj&#Lw{=a$_KrX6eFFV=@XNw;UjeQ~QWDL$1hG8?7e+7)WvivBt@o?GTL zm)|lPcKm(()zkO;XWGMOm3^@*jC8vhs{juFbqm}BntoGu&#sK-SCUSAF>_n`*6G#u zaIC2PiErgmm4@cbM#Ze#q8T~;i|td^b?Zy(QyfAxo%@#XK9$A4!S zecTl5ftk24xaYXv{t+UnYw-~E3{FZuC?sxJKm9>IquQaN1Ye*CS4d|c&TXf4{q*ON z;#`1IPV4&VhcXvkXPwsd)6JuOC{T*a5r~2wfQ7a-)0eVvdzA5O&GdFC>erg-M=-0q zW;(cd_!Q=(;a{M82VT(v{+;+A?1=)llZm|uYMpd5e_HFLhme{CE}rv{HRKOo<8*<| zu#Kh!uS@+1%J4#13|^l_z3Ug>53v;HCl^of%J59c5mNO8uTDA>YItr(eu$n6-VoSt zM68oe-|66um}`hqpW>1i{8^{_kwz|_70{s*?|`-);||{}Ls}=D1#(0EL!SX7wJ;hQ zki|IaAQw-lL^b*&ccYo1k`%WAp~x&FX1ii)gkM=gC7oQ+aPfo&rhI7(k&EYi#F9_N zzc8vW`-U6Et1wXz8XCF`y2voreOTBvU`0sg5gI1ZAE9GFXt=~sgul6kN+qU7_|sTu zgv9g+-xxz9C1ytkv+Us#b0c$D(I|@0Ed&~WncNM=wC0sle>;Nl@EOenM>v>9TA z-tnQ88H}?czWRk$c@^RC&~`e1kgX2g7D_=I$;A`8JyQk9#S^;28wup%3Ee3v6xqNI zYg;G%B35uSEs#S?l)6}enIp=Y%NE*DQ|r|K<@{F0`g&*%j3 z<&TQ+RX6lPMjs=(Ts)zdWU4Ge7KYF(DmyWf!K3tQ@@}-1Ts+4!_4Ul&0CMq=nkV#T zY9)3I+#r!#xJPfN@eC#x&qP-Ajs_dKc+NyRi{_Yr94$Gu{6{^G3xCsX$E5a8VXu4o zL-Twg_D+-!kRfpKFdvR+l;l()aPgRz?0kPT9Y!E$yK*S{3swv+9#>9{@}p!3Ts&_1 z^k@gl;Np1Cc4B?t;&Iatjb2I_Ts$9{^wQ|z ztRGxF?xkc@^ft=i;&JnrMOR=vguun)rXLxd#q!|dF+YapPmKON02y37ZvLs!{;VHd zJnS5D@%)tO;Ntm-sc%-4=T!(?JUo>Q7Y`S&4uOk@=ZN9r;b*`QxOjqit~Xpf8)y<- zJS4$!$i-7m8{p!}G&w#9p#OO)xCiN3|t>6Xhfh!?l?$N@IRN|*waGb;^D`Z=v@2@jj}V%mlv3t z&!XVsapho?zx0O=UMKxc6jHN0><_>|2 zhndO6a}kdLxOjM*AQw+RRt+v5cQ1~N&Zj+a@vJrWrbg!iL*U|Rf}UJFH}EKfi^o0T zs-v8A5CRvEE7wIQGe5X^TzPf$Vb%vOo*}58SM+ElGk}XHZWQ3+nMw=b;$aI67te#t z0WKbzFkC!4Stq!7Tm`szR-o}7-PFJ(9z{SH_-THTXg}}wL6j{KS)QUm2>=<1nVV9rEL9~=lN+8?T zI_b&a;^7>L*yYG-<-LqN>+()U7p=|PfO<~J8wvHAJknVFAg=(1z{SJgwvyM|fwNIA z=|!X@gMNn|eRw29B-^-ERFtK z6f=xFV^KpgmPUUIigq;7-Tn(~*kCnaE4lp{S-9CDJWA(to{&8@pYd5xPDjXpj=D0V zI}7sZ)aBF4xcoHa`zhpW5enYJZel5OR-T21yhI&oh_IG9b-zGGq*O21Pu+N<2bV1MjM#@?xre?VOy zQ`XqK1@ev5Rilyi(4Jy+1!Q-#rdHhVOvpHUt@_ z-Z80swX-kG9F~USZ1Gdb^aO%2{Ch-xM}dYvN92zPy;+#WjNz12^bCRwQ}3A6=Mb|m z%53rs$B?Njf-%flJX}@77@mO0kqEt6n8l1?E}n55f(qHXd2R>oe;{J=BJnLPCf z#_-vQoJD~x-j2wR5qf*YjA5>(@e2eQra8YcdKC@7mN^bH5KLD*flR+bFowzX{aXq& zjBgFr=Lo%7n8l1?PT9fCVb3u2ev`U`hTqD(%rl&iOq|bS3?GWf5DGM0j>t5G-Ym>w z#&8WZixJdf>is75UK-w$Ndh3#;U*_)+V&RFgN4X5JB@)BI8k}UpT ziC_=5GjH@P4@a)U5R7FKl1!#R%Zm_Mh|t?BXDqLQ=41p}rai}4J&l%!*qH%*Ry4iA zsW=xP7|Yinauo$yegKjC5PGvT%NffrLi0QVC}7wd8==P^HhZj{d5mXu4|2SRV61+P z2xs6JtJydVnFvKJV=VTD)DuB%-2!ut#s8Ng*kyL+EuK|QzZrpGtj<7WIt8}129d=G zy}feA@;YcvK>#BS+j=YQng91QcC4LgdVrH{HX|6T*CTQ*1zLRwk^2yOvn0zHt8YQ` zdjxC&e;=IdVDH2K;(RE4Cxp7%yoovk$o~YfKP3ny6iOuwq%fXB$;}uHz9pe#3TV`S zsGRVk`2P`=)4{Y&q;hIyz!E!Ck3@PW+*%Vw5=`~$^nf|&>jCc5z%1{+4yvHW z?cTi@!s_kb{S(5P?Y!sx(iEOX*ogpr-F8OYd)_Rmgw@*_k+8-HS3rS7N8n0F$W*tTkvon4Xu`urzjDoXMqYOH zZvfsi(PIc7nCL9RJ`+8fz+>h0A-d|o%`qEvIBK|I`-4GqWKg7a!`;|jmIf1>I9PN{ zF6A+~9P%p&prAP!<=wuY>h(RyPrRNFTJ?tX=qlu5pSz?-^`Jqb^q@2YyHZ1m{g2`V zw_~Tab?glGB?FF#7Y$m=jeW}e!tUB%4r`P)N;9x4HI#NBpg6(p%Ngv;H;uNO!2V3P zHkrK)Zn}J3u=~j<+SbccKR||kCjShAdfDVhhj<bW#wK_Hlf2=2%|DRJb^Zab2* zkt1=#dowzLn-A5PZ4CaOfPh{n@PPQNm44!R2uaqaTh|2-?Yy1B+X&!;TD_f-k6dBR zcAhA1zs}Bt)ocXxHet7k&LS{4R{fgojJUlt-D{^Y+14Ag+j@hqvSvdeYYYOL=y6_o z%}qjcgCxN+Iq{FXXf6}v&@wR&NSJVC=*$2$`*$nyl1qtb-m0uw1nwYcyu5M99Bl(} zrZ*6AmU&|k3^W{k=1JL_NpMHqOu`!o$UykWjd}x+hB?euvUOHD;WQJSPS|3iM-$AG zoOLw89d6|W^Au*46MlsN3+z)4p+tTth)8meXX5@oVf4on-2FYCrFkF{OLNeDTj^(v zelEc+J@?y6`~OC1j$2&T2yW@4zpXU#m_hGetlf+=*UJO81=T! zi17Ty@Fa{vKHRjou6qNK4?KYu{)m7~1R67$JR{x}!ZpjY-#y_sZCuC5=LonqY+M%{ z(0MxrURbch1l~YlYvVdz4m!GZ5RNp_gwq~bP||E|EO!*WJ>WQ`5td|}_?)pao4{*{ zW1X}v;i8go@tEy((t)GdyRs!}jY%^$ER8p}4GBFz2F)TRAdCMM0Xul-I!3xp8g zz!Mw9Xj?rJHOlTuHl6SS0NS&a8G>W2Sht;#9SFQ~0&Yb}v`_g#lRTa9 zFap|dZ+`<3_FCe;QfBA1)`|TyTf)~e^I6nY+7APHl~3&G1m#SVjsI-sa&xxciV{AQ zwK1kSCZ~HrZGDhUR3_MDE?s(A2e*W8WQiE;r{~Pnqy} ztc_OEF*)6FkI5mwYJgIS~knOHd^~S;j@_4rZhQuvraN(nRrU{jQCrVV0yKuwQOc) zNT8WZ_%N1enz?xMXPeg~8uk)kcukvOX4NBur%e1X*4k#<=IQnZg3Ds)W`=0=uNeLE zHAFX0V&kb{NN9YLq3_o-hgWf%lJ_ugOVrjS97Yy)4NUj4IyM!&bK=_aO{MO1-%P+R zB^*YUcWtzeI-hyw-eL^5Dea9=xXRYstglrGqX`F)*$yi2*i`7Ts;yCN%7k6;lrWlb z@L1L@-&%jdx3PqKzkMrm@)-?pqFzntBg^RTH2Rfmh;E*h2@R))A>mP?GfY5(jn6Xf z#=Ez-@lk?Z<8_axCno0Ouh5P)89DzR{=ok*1}>?YKNloQb3t^}Z&~fKe;Z?<%kSke zH6BPmwWzY8v10ka0WOJPB5fcJ^EYS%@gUJg8;HRq+CaowX#){&r47UrtVbINwP*t| zh!VI8@hesWiQuCanB%fQ)|OEUw!h36hys_zz~9y#{C6E8tfY`{CY74@@Zvqy=*VDJ3M}JE@4Id|B;DG)Jnz+|odX z)3@|jWbAuj-Dx@5**SrXpfl7^&Q08iT60huoO|5^XaqBzGe z(WN;nOY`#bNS2oo1C?J+A4L0;)Q_BYt&x1p4D9N>)Xon0va|bpWO-NDk(95iv-=?Z zHPXL$kp5cfUpPp=qt0*}*4VL9k_-l&PHak+X*L?t%`_Jcia3*yj(r|70ec9xy+Dd{ z=ephO9OoIZ=Y^0bDR?+~w|yWvFOb>|w1w@80?AGt2@KPV0^OZDh!X-ScLchFsP8c3 zu0dCY+l!TNQq=Uy1ZPDldHiq?%>G^Iws*F--+St8ax->ye&i-B_7Xnv63#j(p~XvB ze^A2L?yfJiNi68(#dy%1O4AAXi<~g~g$H7!scui2>HlC+aD-Rmh09IXfow3n2l91C zerL5A2C1dwfV^v+9msYbx4^H6c+A8&8jy4+l2V;tAxV6Yw?ToP+zE}>lgX$ZJd??> zKyl1O*!?5XW#F@n1^Qxeb}2&FhJntiqTOJHJgF!+*d2Qqa{U7By77NF*e%EH+ETA; zlS^GXO|xUSxjWX{!HNx~z{cs`RyP>DJ-u z>92A1=*HHh*W7Nbv|~j@><=e@LR;q-o3?ChE!EojAOG#n2RA3W4(yqr@{FLXISPMm zj=~*?w^O%wV@Eo-ngfBE#R0pp6loW&jX4inrOqoD(y7i}Ye@^~Y)Pbm#F9Y+Ec^p= z)qxz4&<$k5AS9Ge0!^g#PiBP_ch>wx4K*iMfj4VO<>Cg^1uC|ICFBhRTi3GMHrBfG znPbO}D=)VymdkRTcABpm0S) zeEh_57Fx`vu&FKwWQD8tj(c5gL(S?|zQ&5GrB(HdtClS|sjY1X&@-A&012UYV>^(y za-cZwPBOhzvupwOb{P&A_s1N=`o`K-3mSCX{=>)U@iBroZfxz6hS4}$3mVWz80}sk zEuG&s&|Nw?Ln8Qh6EoJ0H-vSls2T^Sc76k%Vcg-mU`cHQPRWXfg*6Lnmet^Z;pv70 zc5&s>rIi(=v_mXm@bRQj%dLv}|2$sC1xuE z*wFZWi5SJeXwII6wJXrOR>j0AV~?tsVNPfF99dOggX>BKE-tIl4=!^b_tunRq?Nn0 zeEj4iW=;L@>jJ#ePc&S)s4*e?Z3wjg( z-OJd*hT4ki%4G}DDRpJ&+X}KAo@iApSlP&HN~;MC#J20-zm9D2TX`1$5qd>Ek-MDY z-aCQ00CHR{GuO@)%T_d0Ei~6(3p3fq;)qvZ=j*B#)GVq&g3JAgYuln)-NSGv1q=Ct z)i~}ARaLm;@!GBHo|hd)kanW=-zOpVnuk{wo{Wada@o?#C8!?_VpA>L$%e&xlG1iY zEiNH3-1=gp>zBsHEuCMraADQL818ussu~(<>lxz|Fj83sc3jKug=k>txPFtYU?gc$*q0p4^k>^S zSd=r@?qGMcJ7LANu0DQ3K5$D^_^nUAPE2+9At7PoPv(i6gLnMI&B0d#PO@y<@Gh6I zIp&9oHid()WQm(&JWty+4nD*tZg5sg6j6KHL2~**a^^uYrYa?D4t_4?7Z2_w`}~_+ zjR^zjV8TW(31#t~ipj$6F(uy*Ya!+c*(c;pDkNeT`by8k$9%(thYKeO`IU(2^MqBx z1|fegVEU=T3xr#QmkVza-YtAUxJ$@MxwP|^@M9ro4pW~Y^!OR$l8+Y77p@kbCgk^A zmTwl`DSTYW?~Y7QM&A<+Uk@1I|_RV4;3yJHVRJ{a*jRAae6+H9wEf9gsB+*l@7S@c%<+QA=mq4KEtm9 zd{FYU!qWGeZKOp%L;d8>>!aoT22tOvG+@B@?Rp{WFO??^>`;{q-O5a^_4`Cnahe#eKJY0HC z7N?!b!gA@4mpos%SbEM3Xa1GKA4va0$>#_!kbaxw%Y;`-|1;s;(%&z9M(FW9z9IQ- z;ip1Q7iT+y=nG=9upJShqvWna&Jm{`t3#UcF-&Oq9Wh=eQ-&SG>j<19xk6YiTp~35 zjwomN9f6!G&hn=T&nH69S>r^*?+CnB>0E7?`EM28DSSxysPG9Q$~`0G#Br8;Rrm+# zIftD2_6hko!hD<^NQ?+GgdK%lh51C3KSWq8{UG7t(vK647tU7taY9ZqXMHCK8-%Nb zoNmr~)(g*;{(Rw9=`RyrA^f@0Zx?dPIqP{u_>^#`kdx0@&u@fpO8*DpC(?f*+%HVQ zbZy#gC(IRg78VLU-p3-!sK@X>0*5Qz^r=G5MQ8qn%2zG?F5btpRL<}}qCBUf zvz>b7kXM`^aUlqPVM0u{6O#D##PlSJw-iOCqrU!*l zBJ6h(76^L^2M7lXhY?YJq>yVGv;0xQqotoKoF`na^cBLj!qbH33NH|DA)=nG!k{wVxPdK<4t?2jBGu3<+B@%V4@KJxInmAxJ+0tJWF`4aI^3t;ZKFP2=5f$D||%wxR8#B?2o80Pna(> zeDp}~FL}6-F6S&~-hY4-B$o@15gsoz??uR0BiT5WLS8AEbEIhRbm3XTjlwNL^ZtZ< zbh~B#>xAUjqWlZt9YW5pqW)pwlfq|(=DiE)W^M=Y_tL*3{6M%*Xh=4Y?<>hczCS@W z?`^5(99cvJYDi^;c>!+!fGKM(^xC9f0zXGQU&AJ7U=SrR@Tq-214D+8XTq`_Fc&>1>kVGNO|6}1#gx3jg5_&wQcS$zy z-6;1<$xjP+3F*L1yRQl9iA?!3;nzY3I_gIW&AJJQPn0}Wc#Lq4aK6yvEnOzLUU-u5 z6yX^{dZn|z3xrL=ZNkfh=Di>B>m~0H-YUFD_<-4DDt z=KBfI<4HY2`YFP4;T&Ow(0pG(xf3PRd!6>q6rLyCDBLQ%R7lTu=D$sNukbonmk-~{WdeF0ctFULiE=i@^R*CEqT* zTlk3Zap6wk3qrCGuze9>7hyMHPhnr-VBulHQNl9eG~rC)T;V)njc}>(6yd4D4Z`z; z7YfaHG_>;?$z~lC$maVQ@HXl17d|ZfweV>ni7vRmW_=Xkdy+p8{z+)oM?rd+-<^OF zAsHAb_Y{(Zf$|6;c^D{97m|U2@?xR+t_FFHWO6MqeUtDC;Wa`MEinBaA^8+2?-Y_! zfwEa21xQu}%I3QnkbDZ1+X+dVK)FC@)<1!4);|H7?_ogmJq$?N1m<5LH0zu|UM-mf z2~0QZn*hm?K-qlf0+Jnp@?AobAW$~nxq#$Bp!}AQR0x#+A|wd{D&Ii!@zB5btNH@UzONAsFpnST} ze8+)ozT*H7{(fV=+d%)Q@;@!yC45Wxt`N6z%ZGcH_kIk~)Q87FgSfmK#PBkB@cXm( zUX#sq^o5uH5As>J{zCbGoz%J$`US6^=66=W0ldDH@mglKZurl9cs()OAfX3L<8}xF zkI8rC>x(=G*ZUW*GNkeNa+`?Y*`{0!!?W=%#oN5JBcZ@8&>E$L%MZgf6@!Am6Jxj; zdu$iKk9cJewa!L{y$SVtX(t?%uMq?1bBsxE^YSf%BC+1OINFGOte5q1KZqwGcx4c^ zPUvY_F-Ej`X)7Qn+Pi$FJN9W0x3X4y=OONuLDV`2_VCxbd1)Jhy0~rXk8ia&kG+j)47Ulr zd~=548;+MrY0USq;$G4V$XDhGKySRr4x z*0v28Jfx&}aB=ZaD2t8S{Xd|%c*u|;F)RQ*WN?Ym&r4o6ZepAs)ZS)eWVA{62C&ei ze1p?^`;I`o-G*dvT2I{2Z$rn8caG_N@#N|bTXHY#v^lG3)V}Lay(FHs;l?pG_^huy zwHzGR-4VO&)T6+7yd`x?Jaxa*GB+1|&S@>VA+Q{82raZSHcr{|6nLH|C+BQ_+G>su zkKYRp=j@#W;`8Fk)g9MoX6Lu0#3oedw{(ixhfdkkeN4x4`;(B}r|jchlgpC!hMfD6 zKZN}C@d01@QgYYZ!{(HIx$EdM@I(*2XUy(h9k%9P+NpUAUIA@;VQ5ZubaR(YnPAuc ze0|3sj|xrMGt(c~hq?1xQZAgbXSAKY(b{+6dVBABJ3a0%*_P`cnBLU6x!vYwD;4b1 zc3A{m+wC`{HKjGrFEU?dmW%`?fWg*?XNd-(Dw_(tP?Y&L#JJX%*l3r4_s7ODp~UFEMuZ`=0Xc zw-?^#lm@otxA>p>IxD}$x5hs(*p$^J&}26|Wpe5YaWK6U-9cxAi{{MKpJ6RMM{$5n?0go=CY zPa4>Le_)_p`q?gfn{&yQvb&HwW#_#3gm`g_Z_a=g-%<9koc;cRU+nU2+fw#w*3B(e zakTmFPweE&%69F_1vB@A7dvh1aEZ&zZMXRL;$5}ZsGS|Rq0c^JE2r!ko5J>?rD;#U zZx8=%%fua1_B@lE+vpzS55`UV4%wfI_65|1<&@`xZODs6!#z2fnIk$Us5G9JG^7~C*{^q zYVa@Ey~CSO1^n;fe~^pg*v>g}c)VnOJ;}A<>esXRnT^Z)D0TKQLkaTs@Ca8U&O}+|Ul5|7B{6LWp z&h1nhxzS-!XDE&TtkZ5}CFl0}(4ljmLie|0+_?|w;r6DZ(tAUZ8}1)UfxQTq{R$7r zVjOjlb30t38vPN@)y6R9Q9}Nr7@5;^+=Qa%|^V2?qY6$q(Kmg}9$tXkN6(O?F zMlRzKUzx!;D>{YET;)}S!&3~~={#Gj!?%U<(MED^hi}hR0dj7K@9;(fIk&@iN(x2J zWV`MPj|KShQzLJ(s=FnoWmL>xWQFg^SZiudkMQIS->b5@k?uS+kCuA2qxgCBbd_)W}_I z(oGy)@#vt2n9{hSqpbK8|u z4J~jOoZD{s^yp~r6ganE$CDp9w@F7D2Isb$UL5U78JycLC-$J|Jk|%!Z8!bU=%Yty#qUw`#y}NhQYbL z9XX=rS^~~(3OL83bCDVb=eFB}{^&&ZFgUk0B2XiDJm9DK+()nrX<=|~a{=q<3-}iv zWoJ^Lshe38oZGG(jJ`EIJe(no#5Pd72w=HlSc`h+pYqf+s|_^z`5-zz`1=h zi-2?6Re*E*DDF2nx7}LExqUv&vsI=~!MRPDjWRMgw<$04WO8nY!MS}26wzCe5(eis z1@`%0*$3dTGVWN>aTLN41D=e7@=+pj_q`!TXwc>`HEkEHf%^L~tWoRT*H>NRH-=?MA#s2gW=XF)!lI{u(($Mdg4zMCLlN8QC}jeSHuD}NsHlL!UyPzBj` zJO1u)2oDNE;X^DtA)Wc&fc!FbrRW3uD5INzXnTah655++bX@S@hX@6r!>}hA6@RMc z@h!ZS*(PV+i0ZC~#C0{`r3M#r}T{(MvW>c~ zto)d6)V&S)HR_{-TMPkhlLhjbyo_S&+_Z>4S&+dA9yZUjFF zd`;bG=9`_%gS8SmPLRbx05$sT7is5lF3V@xnYSU)l)o2| zyAgUZ4^vHfEvYjKF7}d6B12%E=>MDLNDfFswp49CsO_-q4L!GP3l6H zZ*OM~MxrU-5fT1a(TjPQYRV6ShEr5g{!Q#Z^?vien&ms#nVetRGX>*dJR(O>_$%@q zj|f*P@A(OY21GbbwHHgXTv0B^jcbvzW3)?Xv7?>&8MzlEX#SR z<~US9a~uMOH_Nk>-~7g6pN%nq1XH#Vk$Qx_xyWeB{Rq-|2r9SMlq-g4pJQkC%TT#1 zk%JRl`!dCpV{`67NGO+L9m#U%+L={ex#y5$CqiGQm~tOL+GEO@@vr(4dwY48EMeEWR+*8lU&dFI}e04}t)_WN`4J9*}PXXc$bGjo=E z&bv&*Zbq&OiAoY2xfMt($KKD@Gjno2IOk!{gV}q3v^ZM z@4G-x`A1K=KzFg&izomWfR=UTK7C-4o2rEKr?ua7${7UD={z*KN*|0P<&JLFtDKWJxJ)d>PLJwDzIrnmOz_vjS9G<`*qEj~{DrPvZO+xezapNx z&I|%&hMf=G8S4Z2CON_snn~~*zHmzGBBb}j4%c#oqfK%i!Cd2=!wIa6Ufi1O1+E~d zf$NY#y2151#=o+|ciMbDq;FNCd5Uu86E4E;I`eM@JmDu7;=0F&02U^iTc|V3-n-B* z-oh@zjwIo3KN&`!c%x!HA}_8eK`_^4XBL4U_`xNV`AJU6a_m9JuQ&>`^}zo<8w^y$ zCsMhW27v~|@saJZgf^Egab)2|eJ#D74?z}(%5{z;nCEV19)UZ&+pb*Cgg<=qER&GGx`W}2^MQ}F0dKemNOjW^*}}wb~v6Um|s>HFeER) zZjOWr>L%a_3D=qAVT6r7mvB3FlwP%-iMxG%E*jzTH)qROB+M@$XD)%e=PX~jo(X>@ z=U$1VKazdopFlLk#5A8j8{p67k*T?yo0`BQ?F3?=F*^Q6 z=j&noPIl0-6vw8B$+P5G5X;GMW)b*f);fJ>nsem)%|E2edd?%~28zVL}cCH=TWcAd^a&!}l`6tU< zv|%<5EnZV$UxXcJ5rJjkwYr4JYdP59nvGX*Zmcm0JAU^Qcx{6JR)Q**rYg?{*KBw# zq>a_fuw!u%{OU6T)em8Hp3NvhU^mdELsTE5!;NBiOA9&28>9e_w>I0jA;2^n2Ug1k zSKd&HLW+xrXLl41c#T(U5@%vZ`vk5I{@Pv7wZRiRiUnp0lDHK+4xiwk<#0L8qkJYSEh*{V@KsnSF=vo)SE?6zb;+Pg~payA<*=ttJ$W*fx?%3oa|%ujS@HsKuX@R`1P zJrn+=d$zsvMxniD>RgFDdHW~$*K#bhFgnSLb#g_L=!+dgO4tv(5zd5v<(_S?+)3fQ zewSj$Dkk{XZwR-OA3R_?n5m;d4GwFv2OK|chzWxKE3gNgJEQN&2$?69i_G}UwzsvY z)994+Ea|>uALDUHns7OhvPrOv=&uwDji1fMIA;_Z}{9@i9$bj z)2k*^X%4{`HHQQKN1wYZQS4Rn(aN!>4u*3!>KtS09YNrZQ+DNgCVbIHY(SDTf(NFM ziI?P0?uGBIN-MxKEPBaR7+6)Qrq~c?#dVG*aQB>5E7vnY$3@^@2cSUkgTnYTCa^t? z^vBrw6v3!KOn)M}9yHUun&RBx13?;jV3{okKe7DlA4}NlF7F9U+iOs84&4xMIXqv| zocCM$!wQkhJ#f4s*FMzjRNPsEqUW?M?uIz%bFriNdw3a?+Ct=V$MwQ;!-mQ8YbWU; za=GKqm?}=jF@AA6^GIzWa=8ck9yUzQ2c)0TvN*Zi@x*F{1m3Nu;v9rsmhyipruq?J zCXXfXB0Y7<_gq%>Pqbu1L1v&jOX)naUGm%%Gue8OnY>Q$p~2oCl21{dn_>o9Pcf6# zu_|yH@p8EHyphX2@Vp!jk-=-<&c&B2CpZ!Ka-1yQV$DU9If46RmdoO6eCaKU=Ol9i z&x(O}+|I1j$g%$E*aLz+H^n^6mULW}@=K^y6w{RSnaSDk0?g!acEO=wPu`Yp`FS z9bh&tQo9_vr0hl>wd(AuwEQ5CD}}dZ-rViRS+euNF|`|c`(U?&Z}~wUhbp)Q`@ay6 zwtF7!zo`0FA;5YH#y-HZ*eUh_R=Mx{x2b3eUuG)y0aD4>2S_JlAK>?djeP*NVju9AYs7UT zX8C$gI`AnE*XwRt?x;vR5B}a=Z&@PJu5b75J>W9FJ(3K6(4}*vT|sx`tw_L$da?2F z&R_&gL_B&_N7%%O33D(C3f69d|B42Tf}8W+MTl!qlNiNx-l!&c_8&Qk-so>#orpv` zMCgb=tuyHYc-!|rS#@ffmoutEM}~j!7R^N)Ue{AQM7o-R zIFcjV5wQ~5c$uRxf+r*xEulEy^e)G1LU0EhCZ+@VXxKZ^#2JVu%!oYhn(-Upk00U> z+`Ec?_q%wHwa&O-8IQKkct9DCw9fc3GQ3E4@75UF2*ixo+~D(XX~lm|{F__xpBMk8 zR{Xab%rqY1CW;b?Q#mO6!&^Rw5YY|VrR8-~!ZKQ-!do!PL?H|MK?NWrw+JE-&7(V( z`JgTw$_QgJfP<(BX>KBc<=|bjdQv3e{mx13OX_N@&~~7>6xcM^=KwBL?@E8wyyaja zWS}yZ&}7ac<5sL$jirwDeYQI(8Ev5m5hvV8=iZU_USlHCqkE+NzLET)5kw>?VElmP zqar;fVSVI~Xef&0mqJeSTu5DJf>?CuV4_!e%MiPObG-uXr1dou`V7wB)R}^rzIC-f z(@!e{VNB8xQNs_QaGNrp@-y2f*T?P3*rbdew#J>v;B4QY-Ey{{X!QB_wctVMIbfxC$&~GmGfVY|bxKY3hjA1}5SO?%8cUux{#bTuHI&Er zBbo2B)7nl-4P=F%6*pO_VO-#|JNoS8ATIRB>hxA)wL@cgS}Xpi$uVU2b4KlA;09t0 z+aPybq&tol0baPCu`rLs63q7c7ny()Io{Q)61YsX@jk~I&MEMQF!P?1P1uQ#TZNtY zf`}7eA<_h#*N=sSWtDW1Z$0EU3>ksj6&$a_%X$kh<#g1Z@~mI;e>&y_?z$~QF%%E| zm&T&NSo*H<|9vqjjxQcckL-1e7ByDE%|GH6AUw!d4Nu|w*#AmlC>T+s9E~j>R9;QD z{ZJ`su5##6eO&SIJ#~?uC|p`u-#ogqt^qLw3YQK6-L#~6=>p&)@E6seFr=`tzHnjj zFmh_@Dw+!627UCBiiU+?R5VmB8I5PQ6NXn6F5Q1oeWGyj!etc=iwXxN3a1ZF6fUZ* zD{RDsSE5!;bwy(}{QDO!TGU*N_#bt(g^15VYy^*?2!iyY`ohY(+NOqz%BIm6S*N^y zXk#jx!IbgSCeF4&DR7$oD`Qc7U9b1%(Um7WJ?tY20oKAd6uY8+mLFPX!M`qqMe=kh z|C+%pX5hT7pVd$~#{3_fnwl{)C(fBVe%kEv@iS*mN4SY43YB9P`cg#4*c;J;!A!nl zL<{{MYWY*i`O-KSoSCt+5!0ip2`5$+r@$$%Sh$e4nVEIV7-*-_1dv$FOGq-dQZj%^ zd840!bGNDPxbhlAq+?VQ2F20cO!1NGDk~6!0|f4Ni)t$x5F|-WjCEQBzd)3xDPu|z zZlbCRcRN2)Nis|aZ-A)YbYguKx@ICS*^nnV_y1ktF1}rnE3)ysba!zp_)cUuaVs{s z-fe#1im5q0_r|Tr3BF3gyQADzbh}nGbXfyiFm46Me0Omx%q?KoaVv0{{5uA%G*Fo4zI8-=ZI7e6| zY!;p&yjXa>@Lu7Q!e0sB7Jeekf@u`n?;7pD22=uuS|TMVAW~ieD$1W^8Qt zG~rpoi-ng7ZxY@nyqk#rJS6%j!k>x%s_55+e-?kc=#PY-h#!G0_9H`R{P`i>Npx3X z4RX9`pBSn`BX@AG|>V-|hGn9X}kmhyl$0fq` z!fS;aiI78sJK_(;e?a(z_?v{!3V*NsKM3Cwns^du?{A`QJc$r~worbWu%obxFd-}^ zqW)0fNbwI6P88q7qd>XC#Gg;ZxGz=y@xl|tUoHAH;dhDX&-avnz4$i?Zx^37b?ncB z!k-aQkLGo3?^W?%7yeoNzli=o_zxoLh1>g>F6=~v{I0^@!u^DUg~NrTh>%kvJXHLt z!nxufEnFb1Q+}gxrErb#Y~gvri->6F65$<0+#?WIe(sj^1; zIHB=N0h+49!cDi`_Z3NIF3Cfp#r zPI!y(4&nVmDuh#xjSupq=x2q`3x6$qRrqJ&JHqY4kA#00;suY99~GK-lW31hW^9-G zN5t+z^E)0iHL=Mr5)Ks}ARH^4Ae<_kA*5jd>l+n)V5Mji&k{6sW0~I|q(2YRn}qbo zM%u>zct!MU!ncK6gdYlb2tOBk{Jjr3nZg`lTxjBBBEN^|-ogPw^WFjZBSjx1oG6?u zq*o8NbC|GPSSdVKSSws6JV|(}@J!)(!V86$3+Z=_?OZRsNqD#LULig5vD{CDKNmhN zd{Ovo;cLP_3f~pl_#)=L3FLhuzK1mBM};}UcEV1=uEL%|nAe(m1B7&rLpgNbLfl=P z5qfQ8zIhJ=yh8MPp?M#J^j)Iw7yelIxX{KEc~-QICt}{)fcLuiTZQinKNos@?}Bu$ z(8detEV{d}udu(+#3@C+14K^{8mE%r&k$|mmx89VEw*!vuv%!|3xVGxdb#k+;)u`@ z4&~h@yhmu`i99O$2_c>2usnSn6aOrHN4Q=1k?=F2%lAnrPlq~08#knv=zco_4#ivN_59?ICCUkT}aiuBt; zx(X!yq0q#81?}?v6);nnBkUmTBmEG!Y03MUJv3+D>w3r)OOw0nx^)^SA4 zdpP7@ru=J!HwbSN-X;8z@L}Q4gqwuF6uvC9@j@baw&d|=3v-3}Li0Wk`8HliU-1VB z2Mb3DON3K}GlX-6^MzHyYGJ*wNqDmG6yZ6-?+Py#8kc71AKf$YI9?L|S@@1{yYM67 zKZGH^-$T6&p^YoDk7)WQV}37TKcR`Y3;r2Qp4j}TJ(2&U=$D0bW5s^7jw|Bfw+s1EAzfLK z?jh_aEEJ9u+IYU>MIS1p+bh;zC^YXyL7Oco+ z5r3Z0yzhj(WujLL&HGRAO6bnCb!FN*(b;cLP_ z3f~p}MM!sH9FMlbd?8(Lkl#A4$w2XKyxs#vA1pjXI7MjQe?rbtqUnl^a#sk=`%cib z-68+G!i$8L39k~~AiP;fH)gE&xbPRkUkZOO{DY8A&R9Moj0sKrUGU9&PM~?u2{i9D zfrC}fyx+vVh5pVcXR5IE`^;+cQH~DISkA^rp&K*OHa?1ptBZ1UWJbPue+i_!GSc?F z<&&gQjtU($g4e z^F9)2-ai7DiBBhD%(w3!=|_z8)k3-wBYm%sF2YDZC8U=y(l)-WiDwJ?Bk^q?w-Zs0 z4!p?!iIA?kNWUaB?+HF0%b{5Ac+bQnIsAbu_x#AA~|TpkU!eqWUkzo&4ZaENe(aFp;6;S^z+kVb** zSL^p#OT@1c)(e}2YlNo@*9y-SUMjp&xIuWG@J``9!f!OL5Hv{k#udUqW5eq%v-QD$ zt}(p!FdNrRaI@w5gUK}4D>s%q-Bv=H>y;bVm90biew68x$CSU>Jg!4L3Ogk}+c|v< zEZK3dpdJsFp^?XaaXs2PNIJid<5?)suFX5PRk}KV$PO#ic^zZk!5YU!G zT%qBEVCrMHFN-TwJb3uPA*S$`#})c{v1xFpxI*LCX01(IJ8{YEC5J5e&Yic6&A2dp z$)RgYww<%4!`dH?E!lSFnwe|Q0iL>M`aA2=-L4(o^a~OBr|o0!p1RV#FzwUy?H4=V zh0i0((7CRMI4)N>(e1fe;ddjM(F;QtrLDVVd#)E*7ro-u9f{YxcQdnpzomG^{fOl< zYjfy|(g{Dw4^237!bMx0W7}^Dub8#Pn>1@n=-3OlI7iId;vR8$r#@TLR(v11%eMAe z(R*vpW2bi-wzbc(y|L0p)$E80%zRC+~e7*TQD18*)3 zuM2O^xMJ>-AG{g4{MT>hPslP+V(PYq96!a;ybC9jzfQvL8AxRR3RgBdRByc@Cd|di zLfDeFgixd-E>9laOoR^TGzp~<2WBI4!jS}X%!|C~ofa}D9DNQf#C|c_Xz9^gQ7aYu z#l&^_2Nt;3GmoE@ykcZ~1M|!+I6eFhbNKo++@sUo$c}{X$N#ht+H$?;@ITT&X9lZ< zP%YA6($RO&UK(P&tU*S4IC6srdrT*TFTEohvtI%;gMpkQH^D3ugz@sv5HVRS&loR} zYcocJj#1q(a($Fn!4SiAV1yz!NB&?)#CYM`1|&BQMt*ca`fq`;MGzV-ZqGE@V2qdOAhj5dU4w2$2W9ykNRO2mGS4To zW4}V3=%CI%X=1!Y2WP!*1Tn@-Gg6t1V80!^IW}BW9)gIT(c$T5qS@G?Z2N!=dwh#g zE;>?VI5v{xfg;mmH{)2MqeN!MUgrUg7MUAk#A}2Y@I~dty0h-VBJ*Q2*-(kdE-}7# zkB$+UaN4!OsHMBnN$J#+jGc#BjZV&FnxoDT1kouOBt6D>d63!D%z=Rp#TcI zZX7Jdc%k4-ezxJR79!y(AQ0n)!A8=f&FL#Z#zyiWPiV_D8{(_s=rY?7rib^KTq>k4 ziT*JC0~BVAm*~CiRDm&GqW9UAz!)#l`$eUjuq}wSfx8oAXUA5tsUL~-W4uHkY&*@g zoEvN8LHt;C^J8szh>x35VvLuYnETVN7omHM@xm_>(I>k;WXPT|2Aqy=ioIdTzOlbU zWb~;F^SZjgkMRpcmZj|c)1;SVa9mr z!Saal;^z;H^P@x*F>UbM~oMv zOp4eZJg=gN@xoKd#CUmz4Ist~&k+;j;_}ffz3g zO5qil7%w~({7JeGr2~^>NOlgB#1HL}@TDk_=WYUr3p7xaEIXf%n?kI|Wt%F5`fq_@ zuKrww=44ik7e)~@#(bqa5Nl6 zj2CmSg*s>^6I4T1w>xc)t_ekRFpTjWib9N+H7G$*44@W8j2C|%!|}&?K#1|e!i@2< zioHgR7v3fq-b* zwucxmK3yNjZw4od7%x7(Jbp9VLyVVhX3i1gh4=3$V!RX?24cMIM+u1W!X9{x@p1=C zAjS(tm>4e)vrWW!@fnEmQp1x8FFFpe?UZ~t2MT{4} zm8TKobZ4@zH*s90G*n~;u#d7^i5x026e1c%|GBH=giKa*=PGgBQvES7p60b;!H%7+*) zv)C|VyyP1aF<#8-Ne^#A@4E4Gs~_Vf9Wh?0B;LIqng@e24cMMn@QpvmhJv1%B=2wJcejh_m!x2a`&!auk79rLQm>G7*mTFFQv%H zSmQ>HN4+R#BI7c*ZC?<0B*gzt=^0yLX^syH@lohr#6u@QUES0T(@=jN~ne*ohdGOxow_j^9`5)^2_ z-t#34ihHroq?XKS*n2W|mV1fM?2U96>^+N+<9^>~E(e3UA-x#i3!A7kII@R?Ml_zs!JvYS`>%qPHj7<+FML(k4!zE`>Z$fPF1g=Dfv?ho7?j(ZL! zG7~$dm=*w$Fz05khk9xi{7K+QoLKO{zS$%OfuIL=;s~3;1W))~xn}2k z6S&4Bun0Y^m#qiUYTE}ieB2R68A%t;CQ9n;R;8W3rua;Pl{zyZ)eV^qxj4&x*S6+G z*g{k7@U?*3vBNKE(|RWOBN@c<^-MhB6D!vsr&#zzqJ0!Lm{!9WNWId;0 zrE!3mjZVV_8i$Adhx0Uh7!e+M0S8$dFF-6pU$Jz3j!xSwAqUOxa#<6S>^6qd_8!f! z@Anw);RN$rAHErz;d#*>Njj+Fp7htq!+9DzIfJ{A^E{|mutO4$>0^^DaK zc{HJ?&n5K6Zrn&R(ckA2c;JT5#4w*v;3&XT^lUhWOby7%B-t7_6iCh$lm06`|L_mz zRkQ{>rh>rVo$!`hO3cHa0awUrCpkSzx~wP3KBXf&4cs2S;gq#be+vS7wlqbOBQbBqek!yuzh-{o`JIGd+?Ev#o z%xt_h*#o90>M|a333fxMkboD0A=q(EAaJ<-6TbdqUvySpu16<5=O9nE9WYsiccxUIR8^hmTSMX9YfuU2|#rGl--kV-g=? zM~j3{u;W7KCf7<*A~KSjJ&|z*;JI6ZofiXbU4Z@=hAqn!NfJn~irp^3_#xsCs)XE6 zVWMU(c$Db4U*zlKpY*N=&kcpOb+uK6Rq&TGf3HWtr4`54HSF3?qT^44^~Bi9Kj7d& zMU|YaoxJ~HLQ~%VFvs%#hg8!0AJR$he^@Nm`ybfy{)b1{fXhKH`jjug3qAO)qAS3* za1)hT6iMq7=|m56IdpC3rR@uMb{)DhL9c(tXP^gvcxfKoPq|)Q0)^q_F1wpwBA)UH zScG@%Zelb&;Po6eDghUG8K=S%+MuRW=_l>>)uZ4CFfEZr_gonrI>hP0%WH-kF)xdL z&d!SLljcq>o(k`E@O!pT*WyT<{pmU^kNilNAt;AFT1Ly1D7AGd_cgQTj2kz8 z)+~BEX*Aw;;LC@?;d_a^hMKBcc|aLAa{ipgs)ok-l{FP`gfy^t{-U~u;|9+kH+9yb zv&x71IKOmO+5EDGx?|z#sB!+papRo&Qg}Kt3%9PBUQg=l8tLFX+#ybRZPoH7xLcC@EF3r+#%B)Ww#WQy>9(b!5k8!jRvC|G z@G3Lm&?)0FRSO&G1gRMPWS4!9T;+aV`J#pJJi4?T2VT8A={8IA*}^y2B2H_{lUDt7 z3|Mki%pN~$cKL)chfbL@6Af}W;7!U;ocNX8Y3+5O^$j`DqW3G#e!wACIec_2!SbW$ zBc4{xTC$-F0C+*@{kIwJDw79ljoE#_}BTs`kJ1v z_By>f&Uk3zIcMhsQ_Z`tKUpoW54C2}cP>2Ll-C+(T+Ox3ja3WHrPsk5x^eW1g~6<^s;pjA zjSRn|<<+%|>d@Poip7n%K2|rDS1#ubrK$>dC|foj{GSQcA1ZNvR*SL!%#=zJ0c=@_c;PzEn)!10q(3lue*uw2~zdiLji07tkgI?lJzzg3?7*-*mWF z8$CPPU$a-C9A9^dNWCp$Cn7R?5ur=oU;M$sk-~$8Q-!mI^Ms3qwZdlMX+r)wWqaQf zUL(9w_<-;c;Zwqwg?@IK+sgvO2&<^CwT8%`g} zFBFazP8A*{Tq-2tO0X@I#UHy9x`1qlMFi<-&U5DZ-vO z%~`)#c(8D~uw1xOc#iOL;myJqg~oml@;(wB!DWN;ja?qFm*}Cw@xnR6Dq*wmOyT#1 z8-))Djh!6i{#NvR!q0?<;u^sA=Lx?jyju8(Fbf}zSkBmw0rwYe?8QJ27j67pfi4q$ zm~g(ZQh18+Ea7=VV+V%%mx*34yk2;#@B!gV!aoZ?78?65$k_+qwb<`IM68MZg#(Bv zdw}wdT^DF$*9Dv={t+s7w9xp$f;?m2g>sGJFIRcv{|fxI;-4q}WulG$E94uyFUYxF z{JVwssr=)jpA+GJ@plC}f@?SVnMAbHQS?4SKq3HcS7^-mG56`m_J_ao$AD*9I8ox=Ns)^EliM87HA zDtuq~sqk|lzmc&0Y$3HINp}(^g#3U)exZ;$oTT|3jmYN};&`F;r%@)_`qMa4bh+>n zA$4U~|7zj&!dr!R3hxs>D11!#GvV{XmxO;5z9sxv_=&K!AB=3?-_Q@nDkR2*orT7a zB>25W7Yd7oBZbDlB+88!O+`$~qn;%3Frl>rp_U@~)N&zO{~BM{Z-((piTV#p&L*Mt zm+^||*Mx5g-xGc!{D&~Y`!nQa2&s%f+WNmJ7H$1s7{8XtA1^-jCRx5rc%-mgNIeGT zuN0mpq%IHn-xXdYq>cmmcL~k&1n3`&{;BYPg`0&h2&sI)`hOEf_*?)wL)cbG6)Ez& z3e9r}=zgLLg+ql02*(J=3ymL6)SDxknirJ2RCt1Lh0yx5xLCCD+llfUL>vE|pzjb( z{S3;p{wsbV`j^7r3EvR@P57D6`1wTr4D6Ic)eT~yaENe(utZoYEECQa9w{srE*2gq zY!IFxJXv^((E6*mR`i`hs*AE;4+2|_S zLi3ykK1kz-*WM36n(`PvgH&B&eg1|EwMpGCoTA1Pmo`-_0Ky@*!6h~YxA{#@5#852 zMGG1mogy-dTK~xZuQ%axI%7<5nKfewXko`f8bfEcees{=a7vnOh|mJ_xb?w~$Hgx# z*B@nCw_9R`Adhp$Z6fvn+k}AqAs+y=*}QR}@%ZVKh@aQfan@jA@HZ-^-pFIWW?{E= zkaYUtIi#08$Ut6IAkA{qu(;?4#cozc1sK70zqg;`B-Ae3<8ct1u-iIFIx9M&9244X zUOnibyn6=vAGdiNctlFdI}2%B2TA90$m9CAo6S27jG(+H0`fSFwttr)ZR=3R&5(Dw zo$Nr~#YhL`y#RSUKK2honUr@u(v*j6vz6in#OYBH0OoPOQ)tWmeBWK$a6P1Q0JD|! zaCT|K#diR~{=EXhx!|#X?XcV9-Gnp_uO48w(;+Xorr9@c#K7`!?nk+SU}AWZ@+hBe z28PRds{qf-;MvW}YYRrO+P@0K5lJz?X)GEcZ4rE>&`33y6e14O18bTCUfoNwd-KH^`|vg;{O|KA{S); z&-87pj$GVr!jABRoi|V42IXld?cGr3^mo=q22ODH{rs>0_&oF7NZNi#mrbCRmb2}t zHRQSnr*C)DS?^EJxmRF-w*7F;RZhmckKfttYMs)*fvGB!0O)+GKPkV2}0~ z1}A8b#Y?-?>_kM;uO zd|i9A9vGUWJsMv(2JF!)DKBM@HjHG-9?ck6r0mf;vo9%ov>%a7*`sx4-IP7r1#Bo~ zkMrn9(qCkcHV0ix*`t~9PT8ZaXU|gh zXld+s${vj!`x^FW|AVe3?a`WfkSTjKz9QV&9_?wgw+HrUHSAZ)9_>yxwOf0%N)}Gp zqh;|BQ}$@rGdE?AHiq+a5l7u_Gph$RLUN07RlY(qw&E%V2{T4>H&K+ zV>y+wN9)7FDSNalc|<9DG{zR#GkdgL)C}08HBxTC9_>&LM!+8JW9A3!(e7fy0eiH| zc@P16G#U^D?a>yoe83*3}^Nf20TP(fHCn zXpcrGfi@WN4uIOg7#=nvztMCG+JK$ ztL)Lv=a>fU(H`KK?U_9quR2M4wAb0k-P)sVK+%7dJz5QqAZ3qsBO4Cdqs>BoC_OwL zO?G<}^V7;6?Fp1$omhuKcM|;d>L$!LQK#z*VC~)>?MxJPx_^Q)tGnNe30l>CIodh7 zdmpe@cIWG;le+WeE$q=skdd@Un@3`I_Gq`DdqI0NzTFGjqiuum7WQZz(LyVGv|pnE zcSpb;jjy7)xr_1LyMQm!+`qX6Bu)i)Irf5iXxIJ3EnrlOXTkUx_MXtAa@@cBCSmyy z%2)io4uCNCGoQ)pz<0?U%-Q^h&wLFGJ{$Bpz-M-(DN`e+}&tmVzVRYS) zu`%PNJsW#3jwS3&4D(>54g`bzJ1-O&+G}cFr?el1nvUx={Fd> zVlumt`3@Mb876#``qC$%gGJbT-Hf9Hv&}kmlGlz8vG@5tdz>DMlSvynqbI7V8tC+0+0eJ`ZUIWn)HzQ3mpOxaI{PhB0cNg9W`>%<4w}>L@4AmeemeSy<96G+y>i-T zc{!bP=A^ZCXS&8yZ%-#H>mV@k)2E~3<&4ZaFzbLUTA_uNgZD6SZI@+uY3)&j0coNt z3sWzaO^>@-S$vt zO-p;%%L&Sd>qKJ^W_rr`XGlWkqnW-ee`#|bu* z7O<^L^03x}CV5>j1%1yx)y2XoHe=ZDoKtb;W?ncJL%yHQz#FL|=iuy7*=LpH__K&r z$PFtGFS&dZJ-*DM!5#5BTx(#W_ozwm2Rbu|@7N3`wkm`8q0L}|&q%C6(tu5%5Z}trii73L>|Ka*d|5NBELNJap3+zm<~_E)pV2}B3fPS= zGe=+#IrZTm0Qu6-b&e#g!5*b)*fOWfdJf0!LB>5GHerWp41pgvWuaz|h$8JF?PR{^ zx6jv$Y#sJM1lGjiPDvfbVfHA<_Uo`TF3lwT|Ax)J-%6GBl_wgA2lS=5dbr5gSXGz#c%d>4-^|G08K7 zTx~4J9*;o6AM^QyvDncS!UXJ|vts3XPJll?N7&j1QTvEw);yM2fE`T2BJ8HN9Y^qO zZC(fbSKAv*h1ooopZQ5HJ-@5TlMeS%^B%k#5K~8B2@GT@l4hesy8^8ZAD1B)9qs=7 zQaqikJsej)2i2BlZSFyuYX!BZa*VhXn6~}1e zqf;+Fk%L6O-FV0?HoLws0QNXBnLNb%vBLtE@ECS1*VXHpc*Ext-m`or!e|QRd29ns zs{_{)R~YsT!Yb^ZbNuS{Ol~?iBL2G(bvVJlkb{qWvw_ErV0JttTFT}5vaxQ_V zk>@O5y`GCA7du9QkcSV!`Yu#tn@9jNUu z*5c%3X5w35=I5X9b3ASyc2=`fyaG3QO9_^QpyZb7-@x_kpFg`Tt|0vRz9R9Ich)1I#doQPRn-X|&R%YBA+kK}ae z4)ehQupP{Wk!1TsWFN075y|On?JqmzwQuj+SZ3oZk~<*Mm(ZR65~D{&vb^C5SS!*Z zvn`AlV}l}XyMQik593M~ri#dFx}ZHQIy*&T-idQTFGWsAl-@5{3_@Vq8GR!W$@JPG zF$iXvqdIoz&>jM_3nS41k=%nK`yLX>9SGyd(WurY(xxC1?Fy<#Bo~E77ez`Yng0ov zD``~@_NAF96-_(3LkDk^8_7>|7t!D{Kfz8SHGr&0tY4&EFHps_3x#8zWkoF1`3nod zBJ-kE#?JGc(5Of@q-0?%ig3J46}Ru0hlH_fh0L6yNDr87wk<>h1CVqhZTm&K^on#W z0;3q?hgL^LI?&7%r8_0QyfixqshMf{7~S!(AN7W^GX=)9bvzH*J2(MzS9IzsbTi%i z11z&K+*hrdM3dNeyrR5FNAx56Fj&@N=uz&blSi4E%);1WM$P0t8Df?j>Ar6yt2>15 zizCg8bU!4LJuuR}KN{=-Mo}cUD3Xma!_o+)&5i7DFgFqfd71`jw2x0{x;L z*_WHa!n2dHD}#A+LsQ+d%0^i;@3n^ghOA*>s0YhPW3v5kv4JfwpEISd7N@uUXTZ(&{Y0@_+mnLciE`D|m)?i+_MYp8C5O{l$^8Qahbs8Yf% zxN%8cLsNp*zxA-a_2rPNsjI8!T26Lh)}hlT&Y3a>jh8pVgq?<*@ET#v?P-6!0H(z? zbqgwLf@bihdnZ;^G^7Tsx~d92G{%-G%XZ&3ljiZuV7h!l6Z`<+%386UmhR;>!-iDI z0Ny;#RM(c<;apG?u$J|WU3Xzb{|y+)(pr9Yv10&cq7@4l!so^EakSXQ-2$C1Z!|`y zi))%`g{`|5p8=~eS;+M>sODOCTzO3ejdhnU;3dPZA>SNzPwi&$VT0YnfAr4W*zDS< zTeOI$%g#2j|7VS1v+?8`w1wrbVY~6i)h=yeC*+ibHW^#k3g05u{Qp+k#K!Hx7z`UH zM(N2Pk$m-&+C03#32r;vz*2)UwRsL+X$LmX!55am=0T}2xOv8-ev0Ec_>vIVJfp3d zVtCL9rF%>KE;g?;XcJ32A-m-=v5Ut9+>TqC$p&uK_F_8)RWs520wIrlul=mz@8Z4s zUi(?B2aLmB`&oY+_S(<-)jYutKxe*RhbJ`w%;Soo><>A1nO zTpkhm`NFQ^_Y++x93=ihqQ?p+ia$&A;llaiH;G;@JX?64@JitZ;q^rH%fuByzi2PR z{{2Y&=S9CH{H^$JiZ*c&QT`Lr{}7sZh~S%eh`^4xC9|C#M9{s3`xEh{#Kt)^aSc(< z#5DwRV?Lh{h!Ag(_gvEX!acR;ouvBHgog|HWs>qMg^Pu!3eOatC%jO2neZy%b;6Cp zyM^}(pA|kY{I&2^;hVyDh3^YL7UuJ1J^I;2$d4YR`Qd{&KsZ=fA}kfo5HhF&%g+}c zBRo!6CtM~xNyv`}tarKaYN56Fy-oC8!uy3k7QQAl9~~g)>&Cg~voYJZ_Pw1%8~+*L z_Y~b%I6!Fa{94=hPE`J6VU5t*?;1ZFkb9E&rwi8#&lj!}ULmBGIQw~nkSa-}sdY&F zq3~hhW5WLxJ|m>E7Ry_^UKgLxNL#z!nCP~`d?6ipCCM0X#9tOPi->hUn#s+c%$%k;oZUqg^viSYsUJ& z5xy?`lkh#^Hlei>{!Fxau0s8exWG_OYy057;`bL)V~yp;2`34s38}os{6)eBp|uO9 z?i%yIC)^;sPI#w~?&?|Y$HGU2)-Kq_wWrz}%WV~YETlpt`F2lJnjt{Qqv|SgAEEK1 zf;4sJ$e$*piZghvT&eEVwAHopDIqE8X7 z6MkPv6-&y!Pxy%NaUr!Wng1K%8^S*eaadny|6Qubi;k+yY^bjCp*%h}E5odZTto^wD-9*5EPZv)b{4wB9+$m4y= zZZ?l*S3!BXkjHsq|M&*a%DWY5*5P{Kc4&9_%V;%z%)bwNuv}X#v=dlC8}qn7Ar#wL zi*i#e0kmCx6zO39@&m`qH;A@>&moO9Uk@FF`)rdNF|a(G^uAbwVDeolmV}YV zac7(M9757Lq@S;l$TT-AuPxHSa(&Ui*G&okpDj0_cyRI1L~2XM{2Z1@_;%s`|KfoI zhYbU7#IPYg<15&Umvu93CGEvK;@zpcX6%}A$J9?u@VBtZ4!b>Yjn3xHcXFVEHVIqd zzakA=;ZhtAY=w^jcr!7+DO=%bkmMaj*3|r?SU4ORg#$$FO1fx3?8>*vOpl%lNZAV0 zJ&@Oca@JOO6eag>Kf@Fb|DM@5;a^Kz;XE|sdT|tmtuPz&hJpiIVWy*egx}d#_*!tS ztuT!bzuZ=s))A3Z>`G$~9Ee@Hmdz`6yrEG=2kEIcaUHK_S zFkmapUqb;~VPg%PvK2m-$C0uXo=Z^yTj6eKDP=3nAEp6YVf3+ut?(Kibs%;nH3q-X zRyd5tQ?|lpyi>NqKVi>Ow!#lkSjtwI9s3%#!c7pCv=z=^-IT3xHV68`*NoR=7Xwrfh}ZBbl-l{uxE3Y=sLr*s0i+4V<_=v=#Q)P|8;L z0E*hJt#CC9r(#!9S2JKM+>1w)vK79ceNNd5U%@F&*$VUb`<~ef^OtGBR(LeWB48^_ zHPxW4a0fONuoZsB&rim#{4x6#uocEVw}q|nub3aO75*9NfUR&g>42>;4Z4E1!hEq2 zv=ye2LeN(DT#k4kc4bf255%tI3!0#<@TsgHuoa%k@&Q|6o>whwh3R3fg{?3j-CNiS z5246l>`FSp`v=z?BgGLKm;Zxb6psnyF>~YXm_*!-;Xe-PIx)!#=G~Z}pE4)8T z1Z{;!k`c5OKAipf7sampkcSYk6>h_0+%sEYV_-`??d6?GB?I0-B_VlO4A!o^X52a@^rvnL^yByO80IFfkh483pe`fO~*X%`BjN zcVrgDyR*4U=drTgh;CWmCaL z6x@RJ9ITwZ0jv^DCOpA^mrVtN867{k_}^(z5ip?`iTG8B&jgiqFRdVn)c$w(4I$>E z8w|(c>)<8h{-nb0NQ1JK0x2|yjY6r_AKt@gNV|(FWc3jhB*^N%*GhHKS3NXJwJp`{ z5uqulqG|AIM-B5 zE|-=uraT#l$k#wM0kqHxV!+f?Q~h;WWk7`*Q*VN6C6Bjq36+SAez4VjPH8UtoilN% zq<3q=;*={UmV%9$1+5TTHvU*Jq{~w1PTTNf2m=F!|LR)kc3VZHUm5(?~9%L|td0o}BudFcY+BJda0pD?7bvA%F& z@i1~~>MEKF5iN2wR?I*CDYMUA=Dw{@QvCAfK7UIcO zRt=b10h!AuNK9igU=f3K>2B6SIoqDxSd4xFOd1Bdx^W>-8nZZ4di09=WrFp!R41<= zikNYwzP3KkO`a_Oq2NS(ffm%qCT%x9nEf}z9kTr;{`=z$wbr?AXTEFj=Mu-SMO-1f zYVeQ*h3S+gwbl}TC*jASbiXhW{LaA`LiE#1>_o&+M&ScOI!0x^r-UyHw+R0x?2f@;xgsGA(@9Sf9wR(f zc!JRAM5EjW(RT>>!k+c{DvoIUX94;7fwa+y0`?bupm36Ko^XlK=sKaii75oUSp4gR zCZ-VhPl*1L(8Lr1-^3IG8eJq{fm&mGCyVbt=_>?H)7LMcjLK8a(^c|uf6+SC8v4b$Dzab6$KztY1Cdz3eG}kqZEx+-y95*7Cp+T#o zm`55P)UB@Tp2s4v7uv5Li=YDG1Q+A+ETFZrGpDAywh93dsunaa=EI#+R9UxlX%(I% z1GN@4R4hdySn3s3G~wxDL30zte&y{yrE}6BJ;dd-g{}+lUv}eMahr&pJiJq8e zyV<;PU<7ptnlP!qf)MHta0yTz<mcbI16gkd7&ckes@z1ZlLRYhv*jv42iu*} z)n9jPm+jehmm_WKAnDLOA=jtfY+e%>L3#57^03^K^3Flp)}f4LkjMLs-E7{OUjlPdVtx|q0I4BbU#L+oN;7>T2>yBZ9-mhn}YSyH%X<&md`}N za;KwzPwk={bUz0Fr*%J$z(UWy2#a8Hpo2CE-H*?ahVDltj>mf*lNlPGKaQ+WWHnhU zG1kxnIn1!4NAaN}95MRr;ph-j>5=WsYpwf16>;xveuNy&m_;S&VR3<;7Z^xds1|qSDvvA9%b{V?O5()}>nH7VVXCwa^%-4Ax`Yv_JZlOw77(Ux_;O!wn))Yt>v zkExXXK*l%>O{gF{HUUEg-4CD4X^739V?asX4hALjdeO84Vaic0Bz zY@w)>?#EOP_P<8=!}zC9>3&SY3A20MkK@^^l|LmFW2S0}fbU)1J_<-&QjdFszA3fPnK=DaL8FH+()~#1SO;`J zK4$rV?#E!#0o{*(kPi5Xr*TS9_k&t>U!?mnne_v@AN&Ct)cv@C{SWAV9MAFr-H-iA zUmI#a5a<>BJQSxjP7B?SS!8SsWpBm((kpl+5~nU;3*C=>$@q5riNA}7Y5l|(^ClTB zaMSDX3n6Z~-!DLmeQ?gzs!eMQ|5{z?w&ew;-*p!;zXY3P2K`)fhAlgY#;bi!QN zLr$m7(KVrH4hA|N~Ey1G*n)u$Nz;`(d=f&J4Bj?<VDAp>0hP$(V4OW zx*rpHjC-d0VU#ee?nfD~lK&Rnk69e^l7l-1cXoU{d$PlkNx2o-!h7IqQ&#TYsG4F*DLEE!~f3K=D-A)J!3ja{djv zAsW<{YDgU0y*eXbTW2KY*fQv;Z?Eo$+rf={`EDn7AGfpH#qAdA!Cxyawjd+yZ09TQ zFACM*p z`N@IwJmE3I#lpS1AO864)&20tVKiP8aJ@_w9wl5VJXv_2@G9YL!iR*<2wxR$5q>7z ztNY=P^IqK#j04uhH>LZ5OKLzVqq=rcomJeZSg@d>>V#nKUfmD>`#SGI-1r@zItg~e zD?zhO#Q)$Od#~?xnX?<+kH4ZEbU)~p1Nt6w0Uq62wDkM2XTCo0O(E#t<8rhV z32(svG@3&v{d>#+$Lj+QbUc_&`uCv9Q+haZgSQ2V4EguqhvE$R_aNWN9Eg9PVb5ZD z&&f`YT$|AgLlxs!ROomt1)JIiF*b2?oC&sw0(UBscwkuV9TEo6cTNGY1Ab6q|y|@bAF`^$Jc8Ihmu8dK#t8A$Nz)F&Z~I9{EW4 z<9&2HrYZda_N+Y3?{_#R{~pGexgb5pjzPzRgXI;hMVO;71!vM?ox56ygol7=@8;G3 zsN=!Ijb*Uz32m8XLsW@_e-AYTNnCZg-$5>QJbsIVYFl3KMDJ~<3T?|9oalX8d*Qa_ z%be)_qS9krQeW!dW0+|CO?YaW98!AY|STH*#{~pDt z6DpV+qoxgXJa`6&3g*Y;-@_NR5OL?2V$}}jA6H9aVX0;$SVlPt$z=nPLEsv9zLBNzlZ&Te-FQYZru9!xC9^OLj`&9 z&CG|6ho3(%{xE6ic-(68hs3Ra4?llI-1z^1j>p3$e^lK1_wX+zC2{ND!!KVNH+~o3 z-^0&8B;J$qq2uv{sXrx7y*KK3_~pyu*1rb_CsZ&yPKTn@@i^X;pBv|SMI8^GN=C=S ze5=1M)Q;zfSMYQwUP_73@puU}jE;xVFM@xMd?+V)1+PWo*1yLaro?*@j6Y8Wf0EW? z)B}@bNOlf|c+yA0YfvE1y&D`Z&_GeL?0hn$wJ(p$HdP4qH-llW{#=FTWX9!#=Vcc9 zrz>XkL>?w|JeC0S+hTDT9go9NB5tnT(D5LFb38tp#|s?~e+0wvMplJ?53LBa$ODgr zDLy~x-{TsJ+QFjm??Hm1=5nz?$HS-7;wH3xYyTd1qp-T|>v(*Ohu!!VR)vlS?`9OW zkTi5W{CNz=zsp`i$Ag7K1?llQIC%Q^;B6vQ&@*oRd-z9jNc>864gNhA8F^*#<5(X4 zJt|FC=f>&yl{y~&3AZFpBM18T@ag(EuawmB@ag68fxI`I8_G>HbH2unTmK#%4P&hv zHwux^@n8?Uf(>r`T6B&6Jt)E}xXz6~haCF%@ENzdaqHj1XWZk)_h$*{c=(JTyK(E^ z!)H9<#%a_-9S^^ir(Gv=JjAnCW=uQzG&^PJs89E{blmB*EqYlfIs=TjQE`Nh2MLb3 z(Q$;1M}?u6JDI$ylQ5#XI+>gto=Bqi*%n$gj)ZxlcX4_0*>m9)!{3DenOuYKBVjrKKOCL8N}%Jx zE1&CjrMFt@csQ6W1cVQV%`H*>Jsw16O2>mn8Qp&m)-L^f#36t>9^FvNb)zLXpp47h zwz(i9;d%HE{~lW-SvMkO+RoS($)S5hj-v7JvE9<4_-U;Cek6Ah3LF0(^eB|^K_pTG z#=h>p$aY7z)bWVmNtXUS4(!U5_3tq%+jwAtL9$6AOBguA1#!O%!%7Vm&14@FVr#9}GdwqJCXHWAFFQ-!kQl693ilzl>YTG%E;+OgK@K5p9dL3M4_-*u0>2>VR zr^jr{#bF&OTp+9#E)%X4o+CV8c(w3G;r|G&PmdQxzb=g8S25e`D5M=9=|RFngfoRl z3r$=ll*4OaQ~vwH8-%|R(&n4;J{I!1k93}}KsZP^Mpz~+7uE?+7M?4-Qh2M-#2JG8 z-->=m_%~rX-aN4V;lfhkEMc{9gOKi8S^gQ}E5dh$p9nMXi=XB4g|mf~!c&AMeh$j5 z7tNPDtoM-6#Ki$^;@to{;DrJ6dkKdM#|uq-8{}7sZWf*)yjXa>@Q1>m3SSidN%)a4 zf(6cYI|zFThY9IDl=*Z{POKJY^EDXgPQpII;lhc+g~A5msltnd4+)jBU~vwTX>`J10ntTuzY)= z_36=FwDsvRLi9nxQsHFb5yEA{vxMIlZWP`te3*#2d`$RT@!uByRfuVGLKsV4DOsKy z5zFzL)Z^eKbgv!<#u&>A_bq=LBD8=@rrG-AKhvBmZY;-ocH>-en~2@kAx%AwY`o{Q zo6Q>s29~E&qKq>5WMEt_`l{d(pghW-h27Rc(m4dOzKRcz0Wrr(u!1%#qXKlW-TZ(L z3btq4U5>P^LlM&22 zA0aQew%9jrMBEmWTYenl3}zlURvwXU+BM3;eX(BpGNH}NYYRG9t_=Nq$`%6Ja`53X z{Ojm(z~#sAK}M0|%k?-``h%T}-;xinZG~@d8}r=T&IE7C#3j$~2tRu5*!j=3Te5EK zyyx!R;k-6(t@mlpKg!?vLHgj$(e1fz+VQcVkmo_(%g;@JCp~{+>4efJO1o|Ia^jm0Trz0M zsh^zo!Nc3#oTqm<19LW?w4}ju+C04@JTS8P!6kPa&eJ>62Rey|-r9Cb-L{bP$(wgz z4f}H!c27eh`*AG5`!UFgz<@IeeeS}~TuLZXa)7~_cP48$1C$}9K`RN1FKLExS zLTGw%d#2F_by(5|sl{;Y`{-u+pe(-w>9L`P%=5|Y7=4?h59;ibMu#PRaMs_9AnLH3 zhg9Y%_?Lku%(3A_Wn{sg>BG~10A7sYLDLV&@C7)rO3E84G8`L9@<5U4v5h#E^id+S zV=wW5MvKgi9SOPV2Z_v!?ZdhUi_DMl`8>TuWS7_vSa*y_=&<052pyL6N$KygR~KV$ z(KpLsk+65(xoB z6x{cvF0EQ?aM!AJsS8@S)}>b4idC!Ds?+r*VFT7Uh2zxRIM%nO33ZGW}@pD&-6 z?>*<9d+ze?Tj!j6sCibLq(>W;_n1A$bPRMTQI1Ivn=hI+EGtp>-yvy{?3eI(7 zhsI{02X?#<>&i5>^Nk@^nPG<@oWQqcCsq}=OMJuoh78WIzb8sI|nD~gWVd48r?1^{}a6^UGh9&lMRb*{gVo$0A)`lgv zP4!Mr97|PC=k+mV%Mx8kK9jenA*~Hd>^Z5bNL3?WDE7ehJ|uCqDe-uiou5EEYpQ>ay#>}PKl*s$(5{ld8ogo zvy)$ACt$;3%jYI}TE-3!#U8~SlQt}aC=VMJn_rSVi!%l`Ed1d)R5&*2vOcU+V)G{^ zk0K2l7OnykDx91wLMLLaAzez!l2?;n>&sUp87L|S8y0)1nUUmLPchiAd|=AYN}dw| z4I37#e_k?=^<$k94i0TtPG>%BSj+;1g-eniY1pvvR5CU!Pp|^mu<#r)HY~T10UMT# zOfs-e$>CH98VPR$XjXl}U{=4c=QEacPHaCn_6w>y5dUJZ zVIe_PGk9=d!(!=-B!iX2cC=x64Z>=6uWhl-p(srqlI&&-HY~iGQ56GA#bCo?k7GFb zC_4lj77EjbrG>4A4GZTZZCJXoYOGUYdod$9pZZ|Ka;(ueFS$1`1{)R=tQ7O$o9rcQ zSnLVckle)jV8deR=Hv*yvG)4>m00Q9rNf$ubIHos#K>0UH+Dx5Z$?!WI}C zmhVymHY`+OY*_APov>lC4A`(RT1gD+lvoCASZKKugAI#iz=q`{7D0>}%YY5b&nN*K z7F!E#SX!Z;tukW@8y3=Rl%Zk6Li!+|rVUFBHY~@1kvs=EG1#z>;Fz~^%wWUv4MW3* zg;#YFMip#WcyM?kiSGSQ3^pu}g3*UpofvFbcyRk1&#{6H3v0FY|I#l68wgHEXl+>H$A>aDK+AwS$ZaY(2t(==V0YYt_gKK`cLG>(*s#oj zlWg^s#r9;WL!Oujf zo0m|`n8Hj%4Vega^Ewz^sA7+k{8yLarL*PAFuWuQmnP3vVWG zqTw}wt|pJ)#oWCLTOoH5=nJqHaoHbt?@U(yB(sLe~83#1IpwhyC?RdU-Jl+8Qy-N_ayIq>YI|o#y_!!h zdrPqo@gVcg_*e~lTnex z(ays@j1s2!Oi<<6u|>jrViHBdoJxBdpSUTwgK(~T!<(8%JE1ADQKUeWlGumDh|5r0 zs63WM0=4G3#W~%wyqrEci!<`v1#T|pQmDwu%Gwu9XzJ%>}c^Tax zG8uyzm26}$!;dB1tgJ~{dm})P3$b{jlcr49o!O22tbxwVZllnJ>~5Xp6G3@?iOgYz zICBO=9?!JhTrVf6KM(RTTiwiVl<#UJBIy=%>){MRGrRY2hh*Ej@k06EVmcLe_s!yX zqdOR14&0#5E9T7XX5uAfC|*(_;w9zy!x753YbuUw(b!M&iu<{vyDf0HPR(NRC0U1L z9c;7@jyR*csoan(OcTCN4jr3j?vX0EIKvjhG|h5ps=DV$92?tEjx%7C1WZA|dV2lW%qv;5{ZCN47kg9+a?{B_|rChoOFtc{7sERh}P$-!Wm&E09! z4od4jD6M;KQ1{xP?zKVP2l={#-OdGbB6inVn%2EEt$Slo_r{>^jX~W@)4Ge0{HD=( zn9t-$V>2U;nuspNhGLIk3`>jKn6&L!LRgF4bruo$AmBM`Tr;jz%o1aIw=sDYcGo$K za2f_-{5hbteottDASmJu=00+zJSA z@1$S`7>lq&!5Vsqr`mjyM0A{nNQo6*tK#6sM z66;bWP#^xbpfq>aSxEKVk)(F+NaDZQ`rMfd$eu{{Fb9;-nyOQaZw1&B~U>mdfQdH6t51XDVy!>Z`E4PNfO51Rf4OmxjVJ zQ6Mm#7)HycQX=3&0tLaxleCEwWkpt2t!Y3Cw@q0Mk;3awz#w%m7^HTKxEXno%#z43 zFLPuh(`zk2^tplEBAF%(T}iiY$w&s0!%7Mwkqj?;WTY#oF(V_nq{noRWM#M`Cr6?g zhlWFu0p6=!Xye*_d4?NyBVD{pnq6d-n5suN()TP4MaS<_V@@3>^yBh(K7mwrWLdo%4Sr6j~+Ykfla- z*0eeMACGvk_yiwLPsK`E;c3$AfZiPJoD)fE1l%5x7_ zVzZ)~S<24D2Go2-P`{=YO!q)|LURdsDm%w_OiwwU)_w>?1-4AbFtnDtm5XOJty&JH z3Y=$yRPGSs(?)qr2Nkr!>1cVupoN%CHr`wF!qqkC75-06kK&XC`!Ak7ZO$Tp9R2u+ zW)?CCqiMV!5>pHLrB4XOceLZCFq7=0DaAzUa4noUXaB{srr=Ojw$xkWbKC`OOgW5f zH3n@(Q#G!Gfm7U`3Uv(L=nsdDBe+B4I=e)iB0MTKW~CobF%>Yd(vS41*orvMpm+Y1 ziV717PnU*HR|S+P=atyT(^QDd)HSTOrKz$3mzfoHh>pjAdWz4ez@aHkntthvU#BRF zxL9*eD12&*3AY)Hfw(e#SQX!tv3%Av9Z|WWij{T_)n`VAw~SR)tCzQQj;CrPOWMen zsmAdjecIDyD#l>?aR$m28`9jK{K;WMb9Rb9Xd+~C3BO&$ysTeQwY&vB33xQBSzm=& zQCEjxle~1BSfF-9t5($U{6iiBi{b<`u_sgUAWe|i|4cAKzM=>1mia#5Z+s7!nv;KG z#z~Qr!>4$shR$}sl(7l%5h$>w-($%9-(R1uYoINxpO!c2&4UF`Pmp|l=lFJtRhXWh z0kdZRK?q+MA)i{W4&O|vnX$Wi2zwFnk*S!713O&&F~Uj0{e-iH3xvyrb;1@QzZS5b zFF*d>~c}j}&eeo+E4%-Xy$N_*3Dpg&zyE@Pb6W zy@h)SCkmGf*9cD#UM%FY3oOsi;>3@I{Arvt9ixfEgnJ43>n8ap3Ta70`c~nC!Y73< z3+bLuIa(OXiz4Xa9%Wwei z7X6&CFw^E6yJqB0360Q**ExcH0ViuzO)uL|@-YUFHc%SfL;Zwp6 z;r|G8a1CQW1_(=q`w}rnrV6JM(YJZZ|GMZ(VXgR0qFaRP#XmvxDZ(?w|CZ=)3%7`W zgXo)uw~POP=!b-liT||d=Y+o&|97JQD11l!k3|1N7{fK3{pE^0#600ZBKln{94Ran zP9Q>lZ()V_GlUDpUm{#8T%r7C;Zee4gvS%1_hjKY;-4?PO#CZ_*9z}a{ttu?3m+5y zj0n9?34bO2%fh$B?-0Hx48QE}I6?T!Z{wfbAJ794<8XXYeP8o+6wkoF(M9be3-rt`M60 zH2CX8A16FX$j`?tcd777;k82kFwXp^g})NMEc~7DkHQaxe--izFUy0Lniud`kGNkRh>{{~O_3!gitYr$YXRqCMXKK}Ur&CLrBcNJ9eB<-$3_ z1wz`xGyhN_4WUSzSjs^2d;)A0-#n*)hIyuuJ40xmTfo0a^rgZph1Uvi6W%GLQ3LBU z&ow}rFOYs!NDBtie-YAlfpkJh8wJvXgfvqiZJv98G*BRI>_CAuL?B%wq%8tzu5U!7 z6$0@b;TGXlLK++}{~jSt4M>~kC!mS>417y`u4BXe?LzZh1)3&+@l$LmOU@e71S!h>}jOnwfG zSH%C~v3>n_kk9NEgje{W57C!pwO1TNj0H~1PX0O|QyYfPYy2{)VYww(0oq>n0-x;`_L-_?w?M6%5?^oHAuBE5y&Wcs}L3Af}f2 zHIMD$yPaPKN#_Tc4~)6)Z+>1a7=D_0Q}J@S+HX`KZyD0TdSiRq*yya6^|1(%_oSe{ z+aXW@p1=8dO<)A|O&n$YTc{6@gDHI{Bkh+#(s>2~B}{1Z^Nt4{)HehA%D|&OoAMPPmhszk4_?Mk#PRSq=5fDS=*#Up zaOZwU{GFBZ{&qX${4(VEhh{6%!SmmlGhm$|Z zaSFiXHw%7mpuSw}tTQlN&P2?=!QlCuua9Mda$C^87knY0F9*M)y~Y-#x6$LqmzInx zDVZ?7prFLC?f=mwCF93~H+tOIF#v44_d7asqN#9aen)e>hHZZhZ?>LCQ;p}*eouL) zPCqr{Bk#|5#gf~qrmvn}K7I1^{DvM4=YH7Zo!GJ^4T~FMV`8PG+{rVRx$nl@x1ail zb8p4{6PRad$a|+J?u`igk( zV4TCLxW;*ym|i0ahG*v!u;y(YrTF3;p4)4qVMPZ~Wh`RuQnBa*)DVvFQ!D(9W}O#V&ffqGf^-yyxXCa=}VcC?woh9XC1{_=ueO_sMl*?MZ&+w{|v6v=X#US zs_5_>Hppwozvya{j?!c+2LB?SvaxXV8gCqQ#)qPl(d)7^nBD@7(d)aBZ!OHHA(cgW z`WHp7jMMEPL7Up>)zNQ&4Lj8Yzt%**8|elv%~Cyn^@!f!v8XqI>6`of5~B1kG7pe$ z>ACr}56w$xvYGh|#jDG{cGJV5|n8eT&#V5r0q?R}k|KfYa z{r(+6eUn6n6U8L=78x_^^~NWQ%uc|}&57?LGBPig3{5b43Yw?e}YJj@~2>2J>#CaEQjeQqng6<#jwRudlq7iK7I=>9@{Tn%TmPc?y(*iZ_>f(E z$cz&Gi_Gonk$yiy(?jqtn#JSz<9_XiEJ|F=RzIHT3JAf!Xm3{ZM4Wx`{fpv1S4Gyp zDE_26VEv2Y+f?u5#4S|yblw*Z3*qFOtQY=8mX0Oc zSTX#IES;S^jGcggku9H_EG7;AqL*=Jq<_&O%EQ0N=9eTp*e&=MS^uB0$*HUl{zW!_ zV)9|q@GqhR0sV`*qZ4uX7uicmS@I6j@Gr9R70DYgAL8&YviUQTn^+$HMRYm{70ya_ zpwDsm7g_mv#xErf{~`_!{fpjWKKzT!M?(0O@VvspT!)+`ZUGiUo^}}82=)k3icrV4$^^xWJop+2k8Q|DH47R z0^MCsXim_8C|UmTeBTJM9H(ts2<5qAt?@77EHo#x{EHU)G%o546ds3v(Jkmq{_Rkf z9fyAr4{p+2OWHMjZY{6sCXCFL(^#U&Px4{fqeW8Haz7?Zu4b3DgJwqSK8&>t7Uyf6)!5sY{a2 z@hHQ;$ewTw$=|R(_!n8)`WMCFUu5a^$^T(}@GqK!`gui9mO(LGP;w754EPt({XP!= zBDTQe8o8HH0{%r*Vf>5u!X1Zyk!8TY=sP@_;9q1J@GrWWy?}p_Wx&6POG?M#Ut}5Z zFY3p3z`w}WLjR((pq{NVV+#Kw(rlEW;a^00l~2>ZC=UOki@`{K3psK47m?tYU&}Fr zf6?`ZhJO*S>LiRR_!sfu@I(^b`<*!ai(Uq!53f3L_!sfu_IZ_Ugntohwe@%Sh2URw zHbmfGM3(%Bc-_JTqX!X|V#b&t-WN_S|6C|SIufQcUnb|^BqU4&;0LsZJ%E1^HNd~< zT2>7IBKjE_|DrnN<9Upi@Ba7T_{dQR{zd0O%K-X#ZYuZ|2Hh#Z?zjaZPA8||&%w%s zf00>u)|G!z2>wM}!$kf?5f&c66YSUln^BMNUvv!kM-SkSZSXJJpAFdTMlMIWsCmjk zIAvN8N9hO|g0s2dQ_@(wk{yvmrhADLjsDo{(r&U+NR9Myj zIhJ}GOgfaU#6I{n5On`L0s9b24gEVf-v)Itb~K>@PA%mmK;HaQXY^OW4&1YVc-IP0f%cRKuQsfc*Ec8&@dPha3zX?`bMk zhJ?2a|J<5=&-P34%icijLzrPo?E{L>NoY2EJ{5@&|4qm4*7SdYCE5E0keP?w^nN)K zb=Zgbl4b-pg0lfT8o&{thR}MWCfXOY>HRm5&zB3+`)iQ63i}XBnVvrg>VE9-En#cu z4B(#2f5-PSt#}1_Ph&T&;2oVSFASlCX~74e_*{T366UXFkuXn*;j6$4{TcBDy*6ka z@c}f1{^DjEVgM#s=&x?}c1*aDFx7KHAG&c8D9njI>U$J;7NH2q^w=z`;Fnf`E%Us} zl+4GJ_8!O>;64Nm-e~$~fgDW=L@9~=NR)mLliB-WMm7m_@GJi;Ji?|tx#aqkly8`E zAEK{Ue##q6620V1CbGAD(M0wMmdD+N9$|E;>KAlN+Ao_MQNsbRJK;QT43Y*SXRwppmUS}SGKk8W*FQ&F& zhrgxi?-rX?~0EoE7=;cAhE`M1+X9F}gx z0w$+o_waSQjS1U`1?ff{mTttc!A2Y#Y{ap_MzDatxx5FbM}nVVZTFWF%+1c3Pnd%p zE^pyBCTt_-6As4?$1%dO*ga=ssEvv9ED=t*Y#}Guh^5HaRsmg0~oxwy6gb%nj99M6gYTw;0<;#Vi4DF(y}FM?HjQ?4GmMH3#lQ%O~*A zu>`!u{G-^}TkIkTTx#U!;lJ7347P!LhV$MnJh1*2PUVEmj|`TdksXkKI4GZ)$_bgN zW#zM7%1^|;D=vS)&}KZ>DBH=Eiwt`_=cNRVB$;US^TAexQ#k=0UWlS)R=iUuozP_E z1jIuwMLB1oy;C1EQaP@(82M&%U5ZY}9%P#GmYHg{{n<|}-3gz(u{+_D$BFE3oRI$1EAyE<@HnmfZ8{R% z{mX>UKMV=(_1M|T)!O}o%5mfFA4VioTd-eT*6EA86Z-CK);9br=feL~d<)-C$U1eI zc-%Nm1AcxX#|b(YdOLA0#6(Ct7vgb)E-fRC6Jg4^5Zsh=VMf}y5NtUY;>DjvN)c3t zX$5z}xOFG&D|f=abSI2wjOrHY1Fyk&2HXiF-cB6~3xW=XAiU~=0R!OPS3p<4!Eos7 z>wOS{Z()z_-MT|nU*p0jD(poDWO%Q^0T8Z-;ZTP6t+j60^WKV&%oqjlzYr?-Zd;4o zp4|r;Z@_4V_uGxk=`KRwqWBC!Kxy5YqYIJc zq+g`DZSLq7iK`tyhu||#%-VO-4}+SCJ%qdSi!`5sAU|F52MP}n@V_>qfvq;Qjv zFS6vHCFGL0q_+rf6mAthEc}Jg_ltZ>^xMLZgi*XKQJ?Xj0PZ2$_(Om`OtkTb0KGx< zxkBUb06uLLsOS5_ZNgWC9l}9)KcXBLtS0U&oGn}`JVLlZc$(1o7oeQ+Cjj0h{v*O? zgl`Bx5ca@(AL}a=aw$X7Q-t$`n}lZy`O_lhZWaDs_!l96mSujC(AepNrU?%D^M%WV zmkMtX{zUk^@OQ#L3;Fe%db$he2oDvm6!Hgf%AFVKgjCSaFg&H;f=z3gpUhASlJG*|)xtZ4KNdbOd`tMDFbnn)tiP{tgzzY#i3fvx6HXlXl=yE8_s+EC zeZR=Bi}w8@my707tgL6V@MPhc!t;f@@`HRx`9BdpDSTG=YoUn?gL?ifx*NVMv))4C z7-5C*U||grb7r~l2qOB}s{GBOPZXXe{sp2h5`IVg>qOruyjA>rML#HfMEq@{pAo(w z{u`oyFKie8ucH4hba9JeKeLHwcdoF9_ywYigd>RPuknL~j;Z2L7am9if01b8{|LP` zq*1Ox`RkRxQFxsAr;9#Y$VFIL&iFk-@At&NP3ZeOJ|NooJwnd-JEC6W?+E<0^t>v3 zQ@CB_{wCyD1pOVeNTYt^_Xsrpj?icP9f3oXKb(kqC#!s!(D*xoKS#9h?|3L_=&L3o zf3@=03b|e@`6r4#Rd_xTY!p25m56@R>NKVi9W1`&GZi(V{jB%<#1!jpv82=5j?Bm7v1 z+qtP9w+(|htOj$1LxsbIV}$=HztAUC|C7RB3V$VhRrsc`L-?NXZ$btO;kbwSd;z3S z6ERQNL)c$9NVuoa*l=$(7xY`ru`b*`#(Zj ztC8*|H0xyGnZm4-0saW_X`e>9a^V3)$k9rT{6mGbNF&X4tcf&ABc3KS&yAqlMAP() z`L_#ceMb5x!fiy?l?+R}vqMipu)6|^#v=$@2E__dDo@>GXShR~Y z<#L7QITz_Zq6Y{^3QL7FKx4Ush4sS2g+~fog(nJ66*3+V%YR#Vh431oSx*G%yG1`H z{HgG1;d4Tozfs>`h5rzGeEvn6VUCD7LVy`J|N0EllReVdRd=eFU@%TGDteF=Q~aT6WaW| zCeT5BOUC1R2Ojm|wJW9XWTgEvNID)qE^%!9&Cfd?jG(>-=qo`c^<`uC+jkMteiIxyiDo43Tc+XaF{LGA7hAXzrQh$`^`dM?xo_-=7+p! za9THY`c2)6bg+F}&^~|sa0pZF`w7yRqs;)bod|uwx$5_q7?>W;R>&2A*%N$z-($Vh z&pQ1%kEHWFP6UXiHeVmh1m$i)`(8*%rH{d=(PKxCpgRnqaKzc{oGS~x|dcAsOVqO z{T(mdXWMh_&W1~|8|{-HMJjLGuiM=X-@a{cR0@8}!wIl_z!_|Ol|!lchYv9)94ThbB&O%~szrJD zAe+x)u}CSV0%9KS#6Q_%8O1!@3lqUB>Ar+TW8t?^#`_5W!h?F<2391@`3s8*Oa$*w z_#YXbGano;6U8E{O*+cYZyE4I-i(Y`IC6~#QxYf6kBpJ)viWWlpAU)1^{^=cVLZ|J zW|KvE`XNWIjPCwV0|ClE=+reK{ndc3`p((F!H0LVlM&{YoIhbx*OA|gMP@-Qq>qv&>JXPnq?ah zOH4ClcS~A75H+{p2NT;)+=mf;ELfyRWNB4^R z{o~i@=p>Qh#8i@di;N|=1+#j2RNGijOzB)(<&a-JgRc zKV&M-oQ`bnsv#1d1pacJ7Vuc zm~jrHcXm|)`XNW}@@E45kfU2gSwCd>gPP9`h1rP{SXJjZhtVJ8*@|T%H}7M z?BYXal<0?iI+_uEq~CdHUI>23**uOv?suOdixLdK7JWSNnjwcKGFj0R@sAB@;~YkR zu8OQ5a`Z`c!1^Iax2fLAiE65PI?n@y3d<674~;&P*UgaD4>|grR8=H?!e;zRWoISm zb{2gx^L}&Y%}X4}+?Ts{1<((fZw=AcvS*@WjB|J#d-O&Q&tUo?4`97-YO>J}na7$% zdzgQmEj+on#~R!Vg)eOR_Hq1AfSKgog)PlJ3x; zyIVSD;=_UNZ|Q6kiY*F1WLrKrIhvh=1(-Ps!{kMGt3$NkVm5vQTQR-ONsSEj=~Sw%2y;gv7+!pw)r!XbEpq~$Tp7R zEE9h&3O{5kKQCFt{=g5JgF`=LdVfdZhipE|!w;F~RTO^6Je75vY+JkA$f{|0d|oLG-p5f1F8< z!oMi|kj*bOP{kFfqVPkubVhOkDvs_L=a4_=sM)=?MK_0{IT*&|-zW+{e(tYrtm{1%|;m-e#oTv^=bMcN8yLu2u6}W*hb-pOoC&62*(V5 z$mWNvLii!`{kEp>WuIs*Q!;MCI4lrTKq7 ziXP?wPfza07&M;(onvx|KNp|Ki4U1vz$dm+aNu)9py=lgY{$23_%IUu@}C;muDg+6 zKwz_2U(mVH1hB%tv{N6y-`GYjB~)NHVeOb$WQp}{Oz>?JISs~fZiOXQw4IIwZ$0qx zBV1+phzZ98Uqj*87i(kUF-z<;Cfts(>}-1uPU}86ts8Oj(z@3Lb*~HRJ{Z+$OZPPg z9IN}FwC;n_x)CQYts8Oj((T?=oV)^PJR3Vg(c!<@aQ)%t8iZREuSW%748k5k5H)xw zGHKhfm{5itbA+%NyXQ2!W?ZS5CE%UNBtJT!9>NvaO~^Yo_fE?vu)!<=??k`toxKwu zhrrK`{5Q~XmEWZv75(RfkL@Dl*uT#^=QBHn*hyCTzY>Ye#3M^bFk9J( zfNz0-MFGqGPl-teM#v1+}EC723E7If7x=cON*A4p z`8;d>L!LDD_wJxCO;O-EnUBd+a&k`$pX8k!I>imuW&ZflM;^{`rr>+R6dFKQ)ger+ ze3fZs9M5zZLpEG*R4N*stEg!9>i7VZxC_^lhT@xlSVK z{e`o{H@-ID`?1HCiSPT`__4> z2Sxsq;y*3qDpcgZF8X&uTnTZFd@e;_p1edvEv^jpGrgdYff9|V3|WP51XL(CB- zg?)rYLO({8?}IQ#{K>*Hp)nJHzS*J=5`Im{A7EIYS=Jo5S@em*Glcx1igFhTFBM)b zyk2;l@J=Cr%wf4_g})a5M)*6S@00L>Xx}Hn<$VO@xi$`QM_&Z~Fhu?k;f}rr=01je zu2D<5TA{hGfu=GI(Kcs8k{Btpr_$>96tultvY?yLp8-oA1y`-M5$69vkzb`i&9Hx2fxKZvIld}K9 zN>2y+Wyqp`(cf^L^EW?lDj2v_J7voFX@A6U!yKUvExk@m|V>BPHQIi|V!dB-Ci)OTY*AMXo(`z{KULDK03eT?nqZ@#_@zzFKQ z7y8&gwhyOPO5asTvrGwgZWAET5VdLkXCC*Pg}z)HZc1yx^EY4aUND&UxBPyc7q??S zxbb(MVEY~p^cP)9weKfLqkGK&v(1CP;9T|VA_fk-b0Xvl!0ZV=?T%S5j}Pk%43~2i z=HFoO{LR=Ud`Rxs-h3)T9 zrx&h>xpy4D%xw-&&vf&rI|Kjmm;d?4vSqpVIS(x7Glgki*saEilzj!x*u{Yc`$^dQ za!muT82>_h=1(TLv2UQSu>Cb&SE1-4Xo9_O89M3Rjelu--#wWVi?p*;EP5s&9gm1E zblyDF?d5mlH1QfS=xKXj6K>`q$aJ>%t%i{6jY0jsz3++O`1Za}K>m~VzTW`XxA*PN zv~Tar-t<6&vo^E-fW7b6s55Qvdk@Kgz3;DCz3hD-NBK|M`_kCO+WT%p%D4BW9Zt&L z_gZG`%HDSxGt>6I52IkTG-dC*Cr0h_+WYcqn6meM1N{xy`(DJ_()PaHSXJ-j^SLVyb?0`|Ui5DnP-vSFXY-uE%ol(P3tux#4imzU#C_P(5T zxxYh+hR<*B%V$>D`<6pR2=>1FaPT|F9SYd{-o~2K_P+FG3E2Dc^GCqm_cv6Pw)b7l z;Yr*39?b*y1?_#g7D~Y0m!ZaXZST91!fAWolSroReMhlJX?x#au+3?E-?uTQ0ej!) znfrz8eHmCNVDEb-$0A_wyM&Dj*!$AyH)!wsw9QZ1`{uHIz}~kvdl9hr9nSoKy>D;Q z0ejz}>{r0vcM$Uf_P$)iC1~%<7lfd_?{_%j0ej!0s4rme%NK>9z3(wBAF%f|cAWux zU!GT;?0uJ0LD1fpuNs}~eJ4_7(B8Kn8UI;(U!I3SdtcH)d*5f-P2b*k60U1$dtY-c z3E2CVv%dj*-zQmgSN6VqUP;^gGT2Yh-uH6S0ejykNPjkaUw)7a+WX$bq5*qfzQ6_T zeQCWJwD*0T$0T6yOXujIz3=gq57_(i17pzMmy6T{?R`&R`GCEzF(nP!`!=&dL3>{= z*VD<~_cAsqXz%+h&z+#X?^%=x+WU^9M9|*1f{dWOFXM3itL%MqsViXb`w_eJ#q51~ z)k)d=&gEF{(%zS!QvOx;zUx_S+TNF*0a6KTXV7=M=JR)1~C5poNlL33v71j z=^wv6r{@XCq;th77?}7SIXzD^bj*ot51J)miVR>YI|P$(;Q=XvkD z3yaNcX7N&qsPUk9}k1i%x_HPgc#{CB+DsfIkp7m z4mV6c?AGd*FP=#Aox9VZrJJS}7Aw;}O~4b4KK z1q3P&In6Pm6vToGf~K_)krbA?4+>6wLH?}3X1?e*(>^ZaW|ITd@Fg z4XnnhYU^NDS+}~bsj{}dbWvsFs>U^y_NQuGi7RXC>Z@pZw&tkjx)!Vek3;>hx5AuU z-HHh^qH)!}W}?BPmmkJ4wI0E(((4{^Gjbz2#gW{8u)!?s0n%F!{!n~ffth0hhL-NY z0u*rFpkYg8OXCJE0baGLcI?EU6O)ZVjs~VfC(I8Y%S&yrg)6&qidQCxR zNh~gpF)T4stEyI1n&Iwbf@vFsexY(>bNs2N9G0tJRa3{)&Z(R=xBS4$Mb0{Omfbf? zC)>k;OtbDYwBnc^Rfi+Js&(bUHC4;&(BM@ot5!hRcFaE{tLoOT!9l0|$|j7eZ8#V$ zwT(EUji>+%w4)wcmwjpz?NtFK&AHmRs&ZxB%9gq{j52eDs6@bK5E?Eg3y=bSakb7`nO+ z!`f1}N5R*Z*VK%dIHDSr)HD>Vu3OvKg8O|z>G%mH6UH7|Fk)p*bL&1eIHl^=k61Yt z^qPj&mDRv{@avn`jvdj`Jfe2=cyd-WRjnC;o8&&YsMUf|wYsKZAI#LX6Y55++_S#9 zV8rs;bychDN0b(fm^-FmME$C!5g63Q8kAbmSk;0D4lsEZ^O<7=E}G`q13X^%gLHlK zh?=HVYgSj)tl0-A1dfoIe|Es^98cSDH@4LBh?yC+rg3GRJ^gD|H1Tq~8aJEf@}|1_ zdJON%>fnXDd0dNb#tU&huBjXK$;YBmpYc3|kAyv`dF=i(riOgv4B8oX=N(%cpAo0z z#7+#I?S3ik3itFIYB2q*OVUgI0&0ak^J|(-+kF1Al-@iC?~;MdbMOOZVDp?V0gC$h z?491c9jqKZti~POJp7V35)8fAcc8Yc!zU+32tMSc)^Y#+qcZK%|pAfzv ze3gjrd2b5M+TOT)|D7~1JV1Mt;U; zqOWYfco@vaX9aFUu*b0Da&NY=LLYoN8gVeqpYyaS!_MtN{2ogE zd@i93chc3^ecebpoVT>m^*2B7FffAp9)rG#m^akNw)pz^9N?Eh(zy$|dSZ_Go1eEC z3_s1hpW&S5a(Mpc=WPTdSg%vyINQKuz2y7#o`bYs21(~SJO~vqq0P@b19VW|wgP)@ zP#?SP>$?JJzYLPjW6)=w-$-Ed^DaX=sP8ugX?^HYO5g2)GDtelL*KbO8JAm-7u5Go zLHfAy>C|uEgGjRtoDbX@@PPMce^P*E9``4NzT9D$ENj8@H(%~~FqrnYXCOD!CxEP% z+cVgM?fYv%y1)1!pK9NmNMkNH1I+e!=nKwizb;~67@QJ3n9_zK2|l`H^yLCsr+;oB z=`6$iJCq4+zCM--%Ebmc&URl2=*z)IYy!-|Qrqrq#PIe!ZoHA+y^YxLa#LZ-Ml2t_ z8S&OTb4Rp?&p6?hbN}i*IQI`v=bYToef+eB+;MaNaCUF+ooLKGFZ9REtk}D5eC{89 z5??pHXM5!EgWAJi>)Gyo?V$G10X^H@1BOrU(H0Q@x!la^(Yc{lWoC3LPC*`*1WX@|(Y#7|(oIbH*;OT=qhF~qr!c4C{=k)US zL}p#bW|TkGl&|X;G_0s2G;B5MIkMx5VZ|NS_Act!vSD;bw0AM;t?d|mcnkI;vCnJI zhVHE1^&N$%_X?nka@U|u*}co#vrzU*wBzy(V>+UfiaVSQMIEtW6FNeok3&6IY$)xB z4y!|ZiaH9+`kJL3Lx#<3&pdrzdmQZ@x?uw9wCxR{y_u8B+vAzV9oM1k2`XENHVy3E z(sB8u)g6VC>d@ZWjxA{4H5do?@LKd|ZO0Xc&TWrDZ}jlNXa{BMI|dIc?YKO%ygfF_ zYmZ_aPDNj@+`us`M%_iI8}*C626>w&jqdQEH{IUR9YcE0YtOi3UV8-Nx(E6&us7O` z^abrb4dXimdIzJuj@mo;@Z9z= z+UpHNd!e@=6UQIpaShrV##neLd+H<}8#}&xY~VOd=omhU*eP2 zVaz~p$ZZdy%`V#MqMcEU!$31ny!H^r*Tu0qZdfg3SEHZBro9DbtS4Yj)OB2rHeR`5 zZO65TbFQGhkh|8jxwykkjaePqQHwEN2idZcvN89+>*j3w;F9mnuUImD>$^^uG27gC zV_vLeW<@u&W?`x|A+_e3Ne)_5mTnD>)FAAfEten8qqMf;l*8GIUDX;J6Dv7m>XT1} zadw4qc2(f)s=(RReSGe?yy^G8>t=8IV8ZvjTkiW)_>B90|IRt?MYsL#!EFD^6?T)j zgk{rZ?1aFj#!q57uWVd)VB|Ru7ig~ncTE_1@)`jnPqQ|AC~^(1uc1)11_Chhd=-@U zOUljdbp++Y(c?(PA~cGGkteu7Z4vah}F#Rt7m2@}Hnz8V))OI@l!N`-Z z+mSF|wlmC{Ti%(d5k{U%SmH;_Ty4@(Ek&r`rNi@LH4@voy27_j3NYJ+fMxIQg4lU}s84@sMNPHa~fsv;rV+pQs z3nNcUW+!NH0V7XK`ir{$-YDXtt{aic8wMj!4we>mrQ*!l z$mXsZBH@J~u&66z575YyCsX2G{DYAv)2wI{o4L-f2#2Q}x^q{ddK!6th&F0bR~68r zu4j)SR1`OW}K?wrqalNsMT&w~&bb**QQ-pJt@%tc)vU`20gvT;#YHi$)gn17rtJr3hP@^M^> zkky4*J(r@SHS*->BzZ-mktgMFM3awlFks|qyg*@hbPw~fsH>%8c5zKC>T2oiHh*H0Yh=^N^Cgo% zIr$dr$D*$GQc{*Iqkb&vYUL}EjL1SGPn$m@$wjVd4yGfRU$*FC|*km8XI|NcTfJaF7hi#^E3xfi^|LZ4l`0J_QaZXh4)K|9C!b zgf@f2X`2>8`L~f}uKt{b=48g@qa2dMd>XAY2F5V*JO!P}&p-)d_Spen#>omdB#5M;Urvax{=ep2wS}E=hK$JQj7eCtO3al=4{A)zZz$ zLdwI))6(mcHLMRtp2cQXU{Tlc6o8TEIK#lAuKZ3)BhSsqFpIkK!#s^VslqJkN+UiR zd0GY*b*1A3jXW&_i@NsX0K&-AGO(zt$09KDv9)Vd2Ti|7Io!Ck%Uo&MO}Gtcp{0mi@M$c zMju{vXynO*+h;OI0!E&!)z<%rUkHo3a#3O!d6L!FLkZcH!+Kg8m#Xl`G3JNfJ* zI3F4QTlk;JIhcpD&NKkVn8gsLkteTwSk#rD)oA3&FhE!)F%~`vb@k82zX;73oz!Zs z6xdYI1!L(HAlGpV&V(i?WWbAnbtjig=Q6B&K<3k|JCCLutUJ$!97pmG7`UKy=aZYN>_X$pf$pE6!!5NYp1(kOZti_}E6g}0!%JJy(U@|c`J z-tFx4IAhNFJfTv7APRgOEcJ551{qsqU7SNwg}y;padg4W|Y zxD0zS``}J8yo*889k!VLaQ8N4=^*nGd9SkG$=zu6It@kk#9sV6!|P367)_gP1m88@UL2`lFqUutx`jGV;$Y;r_qSOGg+Cl!&uqahX79%UT*o)5t z-`&^f-vcx)Rg14=xAyHtIWEe~l^Kd^M^`!SenxI@^rjGdQEe%C`IMW&8HOEl)!_9b zZ!V@D&nU=|H;BAO?B&>tZ-P>{%nb3XS!gl#VhkyGy*cbtao8qf$2@)x;$NA~{!yY9qV{8Yj~S7r7Z?e#<(dSrUlLu?6jIC@-s2gMMO>-q{kBZ@a8$kJZKV+gJ1^n z=QdqLHp+Kjt6qHu8rHoz8wvz-1D>R?r3+>F%_F*W1nJs~J!c5n%8r+@hTo}}u zHmh}UrFK1U*E_U@C}Yr$M+4HRlCT0h)?BS7@jtZ!rDUQ29jV`7*Yz^Qd&l-iNAhj+ma;yQ#z7XMfny~M^z$09JJ4ij0bA{o5H}mI%b(B|qc-yi#96z-EK1B}e_ZDv0@Zlr`})9_vQL5a$lHoN40x)7w<`S3L^i<+j@rk*%w%No6o1Ra6(59ym z)r#^t=~k4dYu$N@2Z1vmZK=2j_*0uMe*@Uv)<11Bu)(IM6Hmon;A}r|kL~;K(SQ5Q zJ+_zc(SOkP1NPWn26Dz8+vkBC)OG=+9>fmK`}5gU=Sq16TH0(|J>^p1pKN*#@dNCG zjArPd<|)#=&}eRH_;c9krrhCn%q!LcHKQufXlvq;l*bvV9=;BJ8%-P6w}zd>(g>4{_@*b1*i$*%l#xGj`~o&DpTcruXMD=W!#SxY4F7c$A*8>2l&b z*zGKyi!lw%;;CkcTNY^+bNpx6eoQ6K!rtA?{@J!1rq!VBbN3izo(4D`teN;5o1RMy zqi^?PPaB5224 z;s@C6$YWA+_MqW|+W1Pyv0`h9v#?t!jt8X7QCtMBMsqIlx|Eb1CZ2kO+Q_{TyPZj$ z2C$8Mjy>xk{vG=#>j|Sn9BH|l;174)1u;^G}!)kcx)~GDr&%Ij2iGM zR?Pp)E^PSv=E!Mnyla9591@9l>&A!z0Bn)o;O2TgM|x+v$49z&e?E33$d8?ZNF>8+ zKXy$d-XoF?k$A?a-5_1w3XB|G-zeW1OOo9qT{7Isk=z*wrZhB?3#lwfSuBYpLFbJ$ ztW>fj(oIqpOCmi%7mbYc9~tRlWp`kdbnEd?YwqE-jEoer1~0K=B|GMQRi8a*pLV2n z9J5h@qqt+%(D+FiFHX5nraT3WCt%7eR(`0~m(F(q z^u0bi`ICM@H(mOd8o$tgIvR-YB4|A#&HuE|*p6{Oj0+(A%zXFclmqMM4)76h0hObq ze-z|l41YE{YA#uYul+j)^Ds_ibS5^5ql_nD+Go;tsH8tMyrSh)xf^qAnOg1gT3{$PCMdS;gr*P9*o+d-8px9!F1n%z6i;i~4l zWt%F@rO9~FTOW11d;pIR&a9m|;redcsSBfV$KBC$R9>cmbqS1vG~DUwsQ$@FASuUt z4uCwwP5U}uL#-pb??+zS(p1?1$6vU(w^Xfc1~gX~zhjPT%6C7dLGv}`=Ui1&gYo2l zb~WgYZ2gq2zjn}xIN+bG)de~`Ja_huHO{m+Qd$&%e z9DfE_kM>S3yz+V8rOUUu&A`82>m8&Vc&+a@FVgba_C3YvzHL0e{pAUK_j|kc!hgmk z*Z36$eR5|6UU>PwJ2j{1#P~_ElcT3(oEkYTe7biAJanh#jE&4oMCNBl7Gy;hW=_c| z^Imo{bH+~1Sdg(0)}`}vil*Wh-zjuP`jW*5864_$GnG!nlqTqay4qzMr7HwsS|o+JFW@OmK) zHz@z0@KNC}gf9#E-Hvh`Fydh0IN>zmeBpB8kwPwo$a1F(uN9g#+`)fD^xuRT_+Ui& z9>OBw7~xdme4+Ug2YIvBI`CNW&lZ~R$Kc-}`Uk=%gyuH|r6A#J#CsSRq_2WVmjE<8wBFFZl`4dLa&TZO+C{z>?EVRp>w?<*WGoGhFrTq;~4+$cOtc$x5K;e*1b zgs%zT7lvWQ!+y;ZE)#xRc%AT3VORVBPWgetFB(JSv-;+~ta?n05FFD#kOp=T(Iyx7 znv_p2=uFaRUk~w(PcHcV#ot4GA%I#zWX$m@n){#P|#qJzO|i zd|GBvPnnPl(ve;ytQ9s0*9$ia&lH|3ypV|cwurt;c)j?yi{2{472F(OTrLcPZ7^4u zFEromF%ODF4;9j?mGfhqa3A3m;Y{IdVYRScxKene@D$-0!t;dR6q@@J>bp%eom*J{ zeZq%@j|pjX$b5QM5PvKDgK#+SFW{F5CkXczn%`lOKSQ*+pMhR1+E@pJt`(JHo4l*9&hG-YL9K_(S1i!k-FhL`r=$z9*X4VZgtL#)GQi^Vc}$ zX9>Fq&GP{G{H>VzG(aWNsGm4rXgoAPA1azQ?#yo#t`xQkxs){XX#h<;NqCmf1PTEE zV$t6bUM;*{c&qRZA=izkz8?u67n@_NBNkLOKy|yF6=8T5Sr%~N6 z9}&{#m-LH58vK%eS4eAL(orETeM!?BfH+RLmvD-3nsByozVHy?p~5<0qwq*!tMC}% zal+GtX9;O#%yxWV_yges!XFEt5I!w@PWX!Ob>Sa{Zwvn-{7C5Wc@62Pu#2#pkQUC& z-%q%|@Ic{0Ay+Y`T&2)>MS?y;bd&Hxp>e!I{^g>t7TzShRd~1XKH($6p9tR-ZWn$m zborbJ{j|m=P7}@+&KE8h9wBTIt`nXmG|#8dbFt{}2){49OZYS4Q^FU7FA3il{zce@ z&y~>IP1r{`KsZ6Tw{X7D#K=RrLq%5!*9ngnenWVn@FwA{LbE0f^xP-X%9w}s~U z7jhqo{)ey!o^{y%Uc!OGVj(TxnZHo@bz!A&x$p>Ki*TKAlkf!L8NzdfcL{$Wd`S3X z;j6+oh3&$3g?|%%EG*RX@(|%D;TR#U_Sv76!dBr?LN2z=d=uLb_-)Z`!aIZ}rXTWu zDEblMi^5lge-VBp^!VJ0a#3MF;Xt8zUPr!pUI&(ozrS#wFQ4(io&<`;{d_URTB|Lsfa^ugHRvD17T z19Vy|gfxcIYyiz%PlWU3Eae43f^{c*)}TEPwO!)`8)tnfFRpoL@Vs zw*`5@dY^}BbP3J}*2{75>pdCipuSlH9H#(0fAjN>2P3F2HkB4=Rv#`ODSa0s?UzB) zSpj{N^EW^5LNJ2*@&o$V9lw1yAnli-j*ZaA`>wzFdDnsw)Hf9R*iZHsr&>ziT}ZPG z4uje58;thtppW@K!XA|S*@&I5lS9{UzYSDaF%q`kOlV_2xIKYA*uIiLe{l#??fW&- zn9I!ovu%OC;GFjBB8DVGcm{F>VD>~h4?FASxU)|G+(6R#V3b|ciD_=WK9&i}m7#rq zG7|QmFE?uRI4l~Q-gdW6&R*lkjD|Us<10-dmfGJ)24bo8A+1SvCnHi=~)$~2$Xu*?QOHw9v;@heOq zmfEeH66siKxA4Gy!B}c}toP|W54Q;}v%#Msb{$J?9fi}e)EK9D*Rj-|Vi(e})JC$+ zZ{+NQGF)ckIp%($SZZfNQ6QGu6Vw}srN$4E!B}ei02hp<#t(j=Q?b4fJm<`reeTTjz|DrcZ4b|Rkt6PlrFK8<`C_S! zWqG*SaLbR+xrqJu#Zr5Z<$bZ#xL?(arM8L&{IS&dh_PNQwV^cWkEPa$ivR9dYJ3hC zkEM1d4nB!kYUWtti=|e<<@Lo<%V5=mi>1b>n{>1BpxHgFoXwPdvD8v{)H}FXYJAY; zkEOPQrr>7dc#JijfBb^Igqw{FT-DIc1|RVFW2t3uzAu&<|0wmxQoE1keX-Praz5N_ zxI5gO9J=W7$5P{iP=747tJyz)EVZ?4&>u@Jhb7=;>XW(YzBp7LpQ86b=xY?kb=gDxhL3yAjdu}%7LXp#(wtTVF+ED&s zvDA3fiN{jAf@Ap~iKTWQn@z-0<5SjpvD7wTiQsKx8HcDnW;TeWHWI43D6clG=nMFX z$5N}q44=1+CowN_z1@UQZQL+w2%z>*M(S@N=QKqdk%toj)ZV82NJcZpS>u+w5u*|L zttTUZ+F!BdL>|ouosR--ZGMNeR{*uqxWqL9)bg2Y&;B9hvZ;mv)My?7)Y#hDD6@d& z*aZYoqmFKreuHEJs7-{ih5^*L3<#h$6-#_0szEvwKrIV5Q(3l?ks5-NgwRo`HWWGO zu73oGqq6#8n3|gssfiLTvg}l!*fOV{c$mLF{upX%cQT>Q4wv5rW0z6Ou&D;o_Q2Fs zG?cL3rZd`ag}-p4CWAHE_TS+N;!prJtPAWP*e5aJaH5Gf)BedXUx31nH3Gkf0;pBa ztBK;>@@U!onPszPmCc&b&%~GMetK_2emS+Wdd9rDGiM;W%nTIjUQt<5_TLjg%@;YX zZ|}TP3kTvuk<-eoANWZ|;)V10>&Wh#*NS_z|Hx_Pql>=1&70#Y{C_Nl+CDzMsJHPk z=1{dS0M`G1f~*}daN7Qd&3nhcZ}0fm0wxUE!ADp70iRyfTV*(2#J^0xBMgi-y7G zyTGT4bbLQKq|Svb%VUI94?8*kOK^_;m>;7Zz^^W`-mgNDPozpK)g`ATD(>K zUx|xm-tEHjn|HauU*h2s$Kz4)Iq?+|>-2Tee3OCaxVtHXpNU_Qs2{>JBI+Yz1_^x& z$>tp|%x@>XdAAF4f#&xm(cTozKSAUnnR=dCNS-T69;->7f5^@vUOOi2VzE@@V@=vSN4!|POuSOOM!Z2>C-M;}>pvnsA^uUsW`4kTw=FP1r^DH9h zu9a6>Ie&f`z7Y4-Dz7e?k3vHxj>#*jMPS~U3uI*?E(9 zCDaWHZ06Qr&A6;39`+;8>kpP;qI@C}?RgWoSH=kRCT||MTfe<4VQ*jY&}O5YSBEy% z!`8myq4BRBf4Rr7&+>Z}Z}R5xQNO?4XYhU$|Ha^PQ12}V_ZP1YvewTsEGx>4CU4&P zkp1?qi@N(X?QyX^dux&R>L6=9414A}jRGcb-qpza?X8a{>|v4O_U`o6LDqT}_AbFb z=S`ly+o15<+Zau(w?>%f_3r`XS%=#Lr>S_s=^gImnmCW?anUPxBsP|XDnoeXHYxAT zx*O#>djiOIIX#Qy@89Fm#PZ?~gn0k>tt>8CssJ;+3VR3ho>y86_j{xq)H=|6UIVcG zjgxJH%fYGPdtQHz;`==_$Nllj;XSY3MD6~%TG+I((JFgU#>y6v#w*XA6WHB3n0Dn*Fw;t3@khJq$|DL>hG(sEK5FDN zS^b8Uy*h1e*3Oi(F5hXLm9;Y&41i%U2nNA07yy&cN?)6~deVo%OD267nB91-)z$iF z)ByFx4heK zpfI&Czwjtu+b#BLJ5k4Nn|%rGY`u2!hpp zTssV7HVoGsX=^+8N?VPqkY4Gl-`X?a?u@ne(HX1jKE3{q9K@0gn^=;KuDj{|(lp#< znv0~M&99==u5l0TLt{l@rWN%CC`e=NykXhg9j z>2hW7Sdzy>>&BAYgPa#jlCK%ZV@c-0=ze2K9*G6<#ga6y*(PF1J`X$pY%Ix%uo#ae znZ~vgu_XCcyf2m{U+MG3lAOUMNW_vX$HMz!N%9kAUo1)UHfti5BtJCr#gZJ!!uyRS z*$!*f7fbRYj)5fUWr(eC$QUl#gcpq?fvVqBu(73gN-HGlZ%*$CHW#YeqSuf^SEjfu_T{muM@E( z`GNlrjV1XmO(kMU&ZoHFSdyc-(qB(nhRy|YN2h^%INujbl3qIeu_Vn)?FWb@$*3{@Sdt7lc%WF4gV^2yV@c9aM7>y&uX306$C9jK zoBmjmy}5JwV@aA14E(Vqk75;nEXk9&?fsi#Nz#)XUvl?iNxs1`_+hamdDMx=l5EbA z*l#S!$58a&6-#m{mmm>K@@)=IB9>$@Sc&%HAxj)LCX?Tz?yd0U$S z$L&kp0FwNEgOhy|>ESbioY!N)wTBGvw=$Ot8qSjEZC09LWTWyvhWNoDGrJ} z_sCa)SZo3@z+_J(yc+w8{fPfPP-7zD)|leeaIBT<>Y%PS^@U_xlL*hMKl&qP9(Y1M z9w6)he$5|Xz8+s_Y@bMMMG9KA7uUs@!H`K+Ld&QM* zt&1@?5eFa4ySpyN9Nlt3y1&ju-zmbe5RnZB$C%-D8-$TDW`^RR0AYNLnMYh1dg1_sI#n@d?sA1iF=mG2@MBw(iOERlz_Pj+bF<8h6Ny)m9P6w_ zF=n>9dV*VoSqt8#VVnO~F(PIZ-H~)0Gmd+&M>ax(Xq|8ysr5H9xn3j2EPgOdoNNp( zCjLp;5s5(~$vh-%F9bIf#J8-9F+)>H*2?SZ!h>7ID13~B&R2%4o+AdWIlkgNw!u@UL9O9Wp$8J3X)fXd0u~@#6*;sv^q%XLSG5yzj8~+1|{wj zo(<*~A|-54qUT+&1oI!eC1isVee8NAn6JRvOxU2b5XmdSJU@<1EDI%Gta~MxFUPt` z*q~H_LBwk8rfaf%yTzF4JcM%?bB!N`AA-?%)eQ$ zM8nOj5Q-us*cb~N<5mYL@g#r~fT4Et50-jcFlRKJ#zHX>DPe}vg-FZ)G#T0Vz>}l2*5NTppdZdZmGpf9q5M zYY!rMn;`Qq8hPsK;PI=2%)f4AcavnkFAf$s%B`qlhR;dDmRoo%@>lxg4aon&CqIom zW0rd5dB;E8C)2UPWj^_KX|$v%x^=g*BXsbITage z+z7hi8KIuZGs1j1Qrw8w6DnUsiW~9ugnA~=2=iNz;zqdK>uP0O%VyB54@%4myCeH}-Q<36Eyq-|`7*gDb zuP4+qc}AEw{*b&i>Gg!lf!O`xMtnV?p2;)9{8*&DdP3!cNO2>+o>0%^8Daiuq_`2U zCsg*ujvP1Q>k0Kto)P8?k>Wk0Kt zo)P8;BE^k(J)x3sjK_`mdO|&uXM}nB9*G-C))q@;HV!axBbedsI~}1P;5!fvM1GY| z-iZ8*KKakcy9X-wz=k7*nXprs!xMH>i-(j8kxUHK-W_7h4@EuOnoblUIo9I37&DVy zJ#h+>sWPZ#%)4OnOu&LS(b+O4zJJ^d2{*+AZ%lCJyrGVnuaIzgbVFUZpjC_l&Ee+O zvuX;Wl9_mgg5G0t4Kv3j^iO`7!4e#+C#oF!-u-|5d-wAH?5FN{CT)exw&q-JGsJ2n ze7=dSs^F^8P=?bq8qF&&LinP*yihRgtXMiAl+-kog2GAR6UaPddh9<_fLZY(D9TW( z2(DTb%9x5dP6TbhRtkb6W`m8&k)0E2!UE}e(;&1pK@-zmy{VWIJ}#RjFtg{rDrbeA zg{t1fNkMo;);&*VXtJG&?h2h}roeBeh|yWu3D`L!ZU_B5WXG(dL*sL3`}z0n7uc(& zg_`g%@Z;}Z^$r2<0mOunO?Pf(7}-Y7%h=tM!krjI7Dt)^I0_u&KQbJ|(P^(EjhcZy zr<#XMr%7I@u{n4iBj%eZumeJ=&f)=~AYRoE*#j{e&X;Ew;o01ODh}*Hd2{%oZW-Lu zniqufe<9SY`;j{Xclx~{FnH^KG{EdX66PI8{)fszX)PnFE4*sMqYAgsrK zdMRHa`FhE>OMX!DW0GH#%m>+~U((~6)5s|#?6#ELQF33&10|1@%xBrOQz1S7HKu%_ z5Pw@cn2`7z0SsLgtOEuD7wKQ-mAB&T4Pq1=qb{Em|IBoCC#=h`fHvh@5n zoAN@*7fN0w`6kJ?OMXx?A8oVV>(cW-Z^|D_4&Z?^<e8x>Z{hhEJ z|7E9KE_tEkb0x2myhifvlKGgM^`4fV|HV_@BKc#<-%8HF<5SLWMxx!0lKG^Ydd9G& zo-u4GpDejT@?y!$C9jfvlVm>ZX1&Lx=Rf_FUzfa1^5>Gnd_0W#86?_mEjdr@D?MY| zvRtiXz8^sOGRfCTUMKk;$&ZWANRMH_$3^lJf)D>;!uTO+D&n(tD*y)r9Z0+j+D&@n zF9hZLNiGz}h&+eVp9%dmkf(_J8=5lxBall({*6xgCnEhAP`*vPOMFy(QhZV5cl#{= zsmPN6<&I(>afCQQc7KtX79_pJ|*U+CVeW~i3Sl7^3OMiy+Ce}6d7fOGr^d{Cd z^lPLyvGyRFSbN|`=^quJ7he*$h+9PyV-NMdlx$+_K{m1Vz*abhb9tg-53!fnkHqo~ zlYFc=TKeN9pD5yRYy2-^_cw&vkk{tC7J>T|L-V&LoK;=_|w~;xh3P(ThR7S@OH$N8+bq zfah_v7Z#g{yuYEoz39b^=38~td$FSVVh`mak@r26r;A=p=y{SCiF_N6<(7+AhB@BHz}dexvxP_?*c5B+h?Z+#-G?ekxih!*W5fiO4tpsBb6o{)uvLkv_yI4;LA& zgfj1^$mt^Qt0&4r}yF}w50QpBHKO?>%zA0`NcZna1-->~- z+fG#E+lg$qr^uI)C=V2eie3!pagzB}70Y=spU;$hw#YXdIsXdrYH_W2zsN`_EXVsc z@;QkGm*O6U)U@#fGt=`QaDKuN7|- z?-U;p9~S>4J}-JPq2H0ruf}L^m^eRMVx?FkE)kcBy#J%U6(a8gDc>Nj7w;DN zLKWvfD)PRN@(bdd;%0G&_>uSzk#f{>l;xpn4;+x`TafkSk_z#h>dCc;QnPMw3Ds~g|MSily zdV|H$qPcE{-drz(r$|3ftP=T&A?t4w&2=zja~%wZc^wFv>tL{r1KZCL4-?IGD)dK6HrJ_;&2=g` zLwbI<%KD4MCE~^6W#WzEE#kxC@5E=tP2yH@o5*Wrwi6bch|R>VVh{0H@i_5#@kFso ztQ9X4SBTe%H;DI&4~Uz@m&JF)_r$NnZ^dRAZvR_~9mONWLEw^@lWE5;wvIfV+ZtaJ4Dx!*(`@K@b0Jnso3P->))1t z;rg7+{%^XrwGP7=;kLx$m~!gvBL0h^G*esrvK%gX&D5|Q=W*(Ugwxyimdi((hVA-a z(e>KxhH^MvSc8!`jXnxr&EPteFAM`Fu|0k<<@EtsYbYws#_`6Rym=F$@Y~BC2-{eA z+T$3|Chg5c^6DUK-PRQTyuD8O=GFT0EcXbUnZA$h)SEmTRZ#fboje@v;&{S#srTAF z4|%T+veqpa&?qySym|bH(r@p|2?^h3_JQ}ZL?^~e)Iw#(@cNdEq9^ewO7x9w{vhi#s#&rHi;&%f<^ zZIQms!@39M21AL>;eftvKgFK`(_GW$*R$6clDDsM#xv;Oho*%49=Gk{lqowyi<|BYE}pW}IkoA|z^PMq+SBhToVqj6zu8W^=#kx6 z{U2R*j=g)Z71%x4sV&Uhnc2V7uJfk%*_Ate_AaNW_pbAc%6EkfJMKEKzq2!Q`uLrV z`p@2Vb5Skkb=Y+Q$~x0K?aD3cvnx2gxoGyTV1KeB%Jo9|@?Gb{ZpQS?o#~i&KFXXYyX-@-Kl_rfdp_)@!*1F^+D(Jq z)PuB}3cD!>X*UISBL`_W0=vlvX*U^mlMd2u66}T#(ry@bLkDR$1iQh5v>Sw7=OFDm zup2l?y8+m>_iMKt+fB``3;K7&w$%aKRc~yg!%%*3{@`BrfVxlD-Zg6YiG}xL`)=`q zy*)PQUBn4?g-yR^gxDui%xl*%^a2zY$IAg5wxZ6%D6AFi1y(0XrPR zLDUK1sw?3`@e)db5Q7}UhhlRS2n0j?)7-h5bK*V}hf+!ot-$dIJ{0*Bwt)}DQ!vN# zp|~4eNcd2!qBTC3s_#Q_F)Y^iq4*f8c|H_R#N54oC{9Kro)1MnvHE@=ib3?$=R+|W z1LgOj$Ya0fL-9Bo|K(wKq8Ay#P;izRv*ec0x;_*iLeBG{_!kt4`%v7ClKb_c*a{2c z^P$M+ZAl3qihS+lpY@?guZ(dYipB|J!iOULNcwyz^6eO(4@DFEIN?KaHv4i+WElzt zax>Fkp*T=tcKTmgH{nC^RazdbxvkPuS$Mxb6d9Gp=Re_eG)r}K{!pAW^~u#*WNiUU|U;X|>UOZ4yXq1YHbK7bF! z#T*Qu55))B?g4x#Zs9`sd?@~w@~MI3dvVzq$j#1K#sTvAQ2dOG<@2Ff$@Y9c6t`0L z`B3E5oZp8cuNM726u-dXE6L|W@ebDa`B2Pedp;kE=TP?fP;5lm=R=YERXrbyLut_O zL$M1Lejkc_L8+b(#XD%@zuSl6jT}bLhvGw6fP@c4b1d=sP@K%g^Z8Jm&gI{q55<14 zyMG^w_p++bhvF}3dZ^t5SMAtX(ySC_Heo+Bj(-DI3+!ltq^8)EavJ(je4SN&J`_v1 zKt3OeySNT~J`}nC{xd!l(^>wKK(pbn8_1oL^FG^K?#Wd-x!f)<_2fl43^RXVABs1z z#1(-?%TUwFy}`~|Kofo+ioMvT--qHCTqwT}#Z4^X_o4U?ZvK8Bicv22zsZMU0h|B# z_)z3gC+8}{)(;zO|mmmuLo@%L;v;X^Umc+zhDJFJ)nJ`^{jU|sb07;P(xo?CYG zR&EE@;rvt6=R=Y2)<&+i8+SpOMyKOJx$8(V6r?l47HN@RWTZZgTn_(hkKC4Ur+7Wg zL~hS$b{=NZ1E_JQct=LFON^XsC3Qusk@XoNzP!?iCfeE;z=r)s7{Bg2r=)!vE_vxr z@y&eZ+CvpZ%KaJoZ@<-)=0-stLEQo@ru}wPHp%<+Q>kmla(^}61AhkjS|rz<;yc-_ zy94qgNFAPL+gq|(mw&fsA$8y~*ncy+1&~jp&bU*2*VO$z!I=u{Sxai_S|xKr#3kr(sEo#IyGPH_mtK}H3qh+B<2#p5AP zp~|>ZeBaoor}ERNqdUb9jH(j`;%`QUnje@ZkHazNDGYfBzNBh@Xa?k2JRtfVQU?qG zbjF=x9tOEH64vuyFcyd0DgH0JQ@r{=b-wqMoLKFOj z_T>YSFKNK19Z_wv69}4x*54@euFXk)n|=?72X=qR<4*u)UH^yJjf{Obr(iRD)(C%k z!(+_cK$C%-Jv=Ao8n3?Db(_+jlb%hx*W^Q+dQ)0}#;tI23 z%<#hk7?=}dCeIb-#h97y3RT9jBEJ_vvDz3j{73-8q8Kx8yTXzfGklE(YlVm+q0rzM zGkkppOG!*M`qP)hn3?J73ExU^N1m56W(v4N##eTDf2}nzk#=bV9yMuN;To9XZ5^hFXAM2GF`k&bKEhfutqn$U ztOfI8%*-;@rVun^^qxK2nt~DsInm+Txkv$PMG<+In;%8KESLt+a%8Y(krt(2hxHdnUA_6IwjV_v{{*(ALjQg;2CsMZ z$C5X>`r$tZQ{29eB%7Fg)e>&yMXr7X$t^Qroz7S4|7{b$rz%H6UymiPaPuQqfot4+ z5y=Y>E)V&nn;%7Plb-z8%@>i)+%;ZEws!NQ$f44cMQ*-``jo=uJ8rK=g9|DXIs9L2V-=xji#+ z49E+S(yY&p>+)F<+&>kQ8T@%rdg@jop=J^J(|wfTUcrPiW)InbylZ_F ztQ-sL)cgj?wLaWfr=B`(qobZio{3h-w~-QkWNB))Ah}jX#;s7d4T*jH9Au&uG6h>v z{k~9>!DNSS0L5z3pJ~dTr1P!R;XKp#J>C-WTF-FL8SV9q2>`J*UF5z z73!WuVqabanP`RFid4TZ)NDg?t(+3KLfywm?8~eGB0k0x`jxnIqF=H ziB`y;BGvB;HEWPuD^+nT)ZK){zT5>e(F*w(QvJSA^CXgMr8aJby62GCm)AiiS|N8K z)$a>6A0xR|7R9Yl_Z1TR62?(2!#%}qC0b#t70h!1|6n~N8L79~&-dTct?WeEN47MWjCI|n&D z_24JzlDJ8R;tt&YY8<#ZaK#qM$_hDIgxt8nnNT)exxHmyA9BLZ%B4l2a8vktvqNDP zKOhS*Kk6$-_ibs$JKM-mvT@%A3AudZku5#XWHX^kWwwX$ab&Xjp;S|_M|Oy_Q^Ky( zwFqivLC(lSL-{BUpKGk!*oowY(x~iVESqdTo2Dw;*xiqfCdLLT9I|1?^w4f))uI2W)B1ZA;qs`#(19qm6xdUvrO4 za7SspuSMy7EgA}Tj^ZDNP@41A*?EEgobR>&CC6ySAyTiNbmdcAi&N2mz(v}Ay|DD^ ziB1%b8a)CipEYmp%=yJtl{Ir0S;dv*e*!#rDs}I;})pPHD#r4-_M*? zawhz{RY06u0cS6V+^3b4)*geQvx=+w)L6x5l+uSBJjvm@rKI+d`!sCsb8BYR)LJun z?KWxdVhqWg;D=H zLzy9TKw}(tSvLRI4;?w8`xtzMl{6+2NC`IyX4_5e9H+V6!ft6FX1B6i2l#ZY{^VB# zt=-@G=Q_NL^Gy!#;Cz$An>gR(;Fhh8Pj>&ENhloNz4;~w9^w6yW4D10d>Fx=^1C>; zNaAx7!xp6et3TvR2;Z+@6XWrjlET#)lB}T_krGjSnH{kC8k? zoFGmSjSnG|E0a7|G(Lo&KU4DAqVXXFz4_)E{WITOgT{vt^f#*9E#f`m{o+&NpTyV2 zx5b^}ZjlFajzdt)7MqKm#I9n0aiD0v%|^e*N}ebhA41U2lw2<2^kBZN<#Y1@PM1&{ z^2|n=*9K%~5ueu?+4!P^ew5@f;$)HEq_G}fs3ZBEBYBosC-R?3>X(ar*^cs!;;rI( zafkSk_=Whj$Zt4UKUr)nHWgcoyfR_Au3`_7ujx`hKpY{C5+{mN#fH9w=1E^Ao+%n1 zcd&b*v!NSbvxJnP|?3 z(DRau^Mj)2Lnv1=|BK`NJh6{>lsHr@6vv1Y#A)ITkuONn-kIV#;sxRr;wtg`dd{f*kzAt({g+7(MN92o{wAWqiBQiug^+UuF;uz8MA#{Rd&xcT%Gw!4ik?P$BD;_{05EXOU2n@rC1}LCDw@- ziI<9uT24Dxi!t$L@eYw62(a9JBEM9i{Cn{!@p;``!u@e}b2@jKDMjRx(f zijBk^@h~x0>?HOOdx=MjgT!OSwb{mRZ#9J9wi4gv(Mh@og)w4i&fKx~v-8fH!&b_)0Yn zCDvfgI3G7~gJGP{2eDb1_u1L6laahS$Xcy%1Gq1LHN2nmmn*;{&lC31?mU$9xBGY> z__xD0&vw}!F24+UALzHYytQRTq4Oqh9`76d_O2Y_`k|pc975vuRw3`zLDsq*_OK}N z$(zS_s{QuX`Rs9Vy#B32-m60+55gY(5PFk0?*=IR_U?f_E+_lPr^cSWyOC#|d?Zd& zI^vB=Z)HQ~Jf??4uiT*S*bbocCa>HdpkUsc?ngPego#gVm($}&{{C$ok{Ca%!g&8) zMjo3|6=0^1V9&p;dTo*3w#b6*^DHY0Wi#aY44Um`BC$=_i%-L`{SAyuiN3RrzuYtE z-+TKg*Q20sK|wSz#r@Uv*|)!%o=3uCjVb>9{%VGon+D_lYFfba7yZ>-e)rhcX@w~( z-`X={Me}Q0#11bUHN4mGYlm7N&pzjtp(_dpe>~%yl(j9_IJ>Rk_JFnUVlzA#*d9!4 zQRu9WzF_T64y@mu?DYIHdB@Frk~jDKG7N^nAQ%J#U|_R-Q~)J!M#&F1Icpx1f?+T_&L)D^=alDu-2`)k`KXZ^+mN<9IqleO zsY#u_Zc={#ZaevfO-XCRYa-j7w9wk~e!T%BGGI^gWdrsEcMSM4ykx+hK&z~;lc!{T zoiW_O#c|fxc6o5^-+r~>%Rv5sFN2qD+yi%0Upts@V}3H`XJEeFHT8uJ7{QHu0#RtE zH2&JLT7T^fZ}PQMZm)f7Px6YLS?^|rK4}yRe$ps-=Z19~9?kkZ%lf2|75=1Ac*Hhq z#PDt5!oyEF`IO{d_G&nWKH6Gc_vzeUrmjt1V@7gSWKGNAkyXvPCWD<`NLd?MgHc{~ zQnK@roz!yeT~=WG@Sw9joVK#?q+hqZW=LVzLaW_`J;Ckc_XO|A`#Pnaee@TblDCJQ zlET>!yp-j9(#YwuCvfzQBa(LqlHc28Mbq!5ub0Cvj$Di-%Y7qWVzeo->jkU(OPg9= zI}F>y+wV6m%qwiUrdwg>!js>uO3BY<{JxQZFTdk;H#Jq}~e3KR<-*?bu0!c~m9+YKb~rpY-Ss^FOB zCvi?N^b?$X96Fp0j%&e#O(2*w5fa?S7_Y|3N!O#Dgxi?ODB|!LS}2-zB=hH^aHw0> z1m^inFO;7>i)NC8(`b1Xe!}fqJPlPS_yT^zKSKrES%#h@b<1EUoWJ8IsoLa|sxddY z%+9$Cy5wNe&z-|zGs1@;Nw=o$f-=IOD@nIyQE#Q>dYb=8+!BpMdGpVKh>Z#XQ<*Tzr}p>8Tcj=}|05q-Uzzf#mc@(CbLgY*$Q6 ze;RcnJr8rm%*MrwtVpj^^XM-(8v}JYW~ZFPGHAjq8xG<_V6lDV$mHvxOYg$AkBYbk ztn?z5?JqHy-ihMT5|h){V_6~tB&Ma0V_%Mun3?`A#eovD)9H37GDu?c^qy>Ju*6pB z-*GU8NQ_!d8e!Cu?MPAb4)&@y)@tOq6y`bVmvIb6M<_bE%j|Ue6^@KG3kErmzLoL> z$>#^Gl=*0z{sPP*x3QY=Va*CVa#He0EP*@TCpTf9)`y^Aq&VyjK`@;Upd%%bv1V>^ zIy)Ab*_wmpLfENZdR2gTo;Q3~X?O23Zc6Nlf9uG59gJg z4u9E*?bB0m)f0I-{VOAOPN$Fa$e$uju`HeonaFc$$aNtTd0q?Px{!&ypmqnO^O;5D zrN)Pux`Wei;duPHaaSV_Yg{~UrWN^%Obt(`6Ya?BsyjNJ&$T0Oq`YF5cYONe?Bv@` zjsOC=lhYabD6%E31cd^*)6!RSiQdiN9vsM>k^VLtdQThMEGyf-0P|V3srlj7(zKF4 z)MLH$!K_A{)oeU!b`C~P2_$oLa?C~R%z!#&<+S9e!-dS{W)Xrp@3URFka6YYoJ=n8 z>_BT*PRkj=D;2;@A^2H--5 z`-qeKOd#hsRKSHy7}xYp?wg^U2p8$jK;}r$$=w{vd4M+HLZ*o+u_J`>=dR$cr03C~ zZzUO#okO7|=u;?oHwt9iTcF_v>MKf>w?5x6g;Sn^ygM+c4iztxL+Ra z$vCLL#$kjDnQO2x%|C{*v`DUt#WqZCoLV>1=xpLq_#+Ac4TWK0DWQvSwxR7CH3ks{- zEnbMgg-l1Rnw&dm>fAtcp3P{gF=e=rao1xo=Uy%lT*$C+AU8SZ9~kfmT*&Y=5y)+y z)0RzN7--}!#mJmbS^uIyx24A3_?)A`$i;z{tD(pKma~RS2^TW%4mT&KHOs?=j4M~= z;GV;Zz=ez}FUsl6MY$}H*%$5eh@LZ&1uhR{78=FHcFt=o0T(jtfpH;o6HCB_3{5z> z>+GCI*(O}bxQg|5&MD}81TJJ;#XWWo|B8sfg^a7%Xy@?1mk3_!Us{*N9xre24B;Z1Zt-9^M;#F#Hh54A+ z4h5-dW%Dp#wr*@-Tad@aEjrc8=FaEs3u(xQf?r{73b(;_5KRZ*@nsU104`*By z3$9@raRCQ3<`c|`P!=NP=A+N{F-`73{&u9BsB6k{15LSiA-_%CVEovFOu3fmP$p9D zHRy*uxbfd%?1kZ+{!L6#e4>b?P){|4tiPTg>$ zn}?1wN=y3;{Mdz=Y~wCuFQblr)a+x8j{gE)gw%d0bt8@LPssinsXhP7wMRADg1Y>7 zWj0d#=h2W|l*utT1%t&1eeM5D-El_8e?55l(xGaRWsf$hld*jlA$6!a)3V2y7Pdm% zg4FR;%N}c%tHWu?HRUL_#1$hX)n_0+X;i(S%3`T+Abv*GnJ9I0UjZEj! zT)rN5Yi@<}p*W37MmF)3=R>g!$?EhfexBlNf1O*Q_&JsSI=_YDAtbBQ{rK6ATo+R( z-)*OhDJ#M1vaN|PjUn?hq;8ziy+1S$K)MeJPrO-;S0+L8%NI55x6?S^RDBMaXOMcZ2xpq= zA3(DeN!9zZlKHN?KXY3%_F$f={tYr;BlTbr&NS6?aM@0;_UbhCLF4w_em|oJ^rmVz zWR5`U)*R(bwL(b4kEB^vaMaMe5sxw*r>&(Y6&n)Pb$gHBk z5xfnVUr^wJK7!0fq#mryYWW;N8KmqOZ8;78BQpyR8jZo1P-PQs(BKEiY^6Yh-yrif zQV&*UH5n}6h*i;y`K@IxWM|H&MGjjNWHKpm*g7H8fdYqZ05biNdayR@nW38i%{U|+ ztZ12fd@zmQMM!qo&ipNA8q4L#%%VWcXCZSY1zKK#%oRvIyn6XuDfqjHI}zu~401(}tkB3b!{)`eYBAH%%h|K#G z*o$wG`3F)r*7174b7d5V%z$+bE%mUI7Q#}mFQM+b13zscwL$8}+4*6Z!9cJQUoA>8 zzYJ7n=i5oYu2=DBNJk;{U_ln~Ds!2au!{Lz#@u8(;}aA$%RL2|Nvy{*oNJc75}Nr) z8Z+v#>vIhpZ)bF6XE|o)qr|yL-8je8yB^YYrd|Q}eLO}$J^o&dWKXv<&t_fj{OtX& zkj$3$2V|b4z%A`9WZppP;nmZY)_Wtm^C}8l2OE9t@pgV6dqUt0WG4pjCqVBfG5dYY z-ssK_EW(@#fm$b)S_iQl15-Ja=&95Ou%aG?=387y_%pxv-gyF7bPnzwSeM2+nx z_TaF5+2w|O!yO3U$JlD^)x24m(sh6?K5Wu;^y_eFPqn9n+5OJ`?yGDUzYb^F!|j5s ziT3?NLsP=jQcp-d-i&A0kX4YS3f*W8$CTa)RbIRj7a>utM=CbYCfF+Dxe zhIcKTLGpIY%s`=iPMx8Jr#fOY%DVmonfm|c8zj6QO^hXKOl(kGVoOtN65+OI8rfzVnL@Y=F^O=S zp3>0JU6>WHR+_s$7Gb{Oq%uKLWw=i2O)8V@E0bKW00pPv7h7*ai5AmH-v7d#AHflW zdL)^QMs4c^g6HxiYvtW_;eM@R6viSsR4`MG#7gAPk!))kJM(8ZOKdjT69_E^4k+~} z)_{>rQe|+Z=T7JhCtF0hh7&LRw;;iS;k(FVkq9l)Xfh8q(e3qh%=9!uO)$ocmT-Mt zI5%jPurHLbK#Vm7QHvQZ>}ZnzC18Yzbx4kN=F%85?jW3S7qX8cp$PFLk}1NBJ2)qJ zgJU|i8Ty7>LV%tvu@qc*Ik|*jv~*|b`Mpf!s0nyAc;}6JtZ#0bc=ZD3Jj9bGJDGR^ zDH$>7&6P-u65lnz?nLm4B{7o{2Qu3fUpYRU`yHmFg7)oj5fkGa-uz*Ky?a0`a4^;m zI&;@y%^-Lc>sU*IF=nnqvaK1!4X%DsjG6mgVR4L^M_pk_j2Q__jqo@Ws80OBEwnhs z%&V@jB*x5US6CWjh6y!@cU^rT#>_TXSQ2CAb5~dzW9BO))F8ff^??{O@QUCr2Qw0u z#<*d)*SgcZ%UKNNGH96`cqEK5vkD1%f}m*uq4LJ-L9}WepF>YpfeMe0G4eW+TEPH#d21_Y-oKs&Q^Ym zEJVWLoZt;0vV^+z#YR1ma7TS2;qIgp6Qgdj9QCGFjdf*UaQnd> zPZwKPW9#Ou4M4!2Tc)7@F}|_#terJdcr;YO-PKO$#NvHl?UR>x{m{wo!AV=CpN?C z#lFq3dWml{tX^t1!z#1*6NyDg==UPuW;i~v8CC^+n_*SZw;5K2ef@Gz-nXK|97!&R zyPgu8r@J~ZMp$V4n#2yDN`*Cnn1_Vrt&1_kodSAdIa1idA+lG?81t*ltVzUAk#NM{ zSjWs7B%E6})`bgN#VD*p!p=r;_X%N(D#(j3Lcl7hw*)AGlRGEVOK=O)RwOi@9PZg6 z#{4cM*d(~oVR0uLnngd`9K8A=AI8NVyTSZmBvc`|ZSXpfoQz~FW3ia$gKS(_5!`&d zS>BO~)x0UFuHst695L1L06l!VPYk&+V=E=-ToL;Qu?oqt7S+X=akuGd#0^G|k>kk ze0*Z(RBZS&zI);Uq` zW(n8!WMZSMeH3`p&29$LOpBBE)gm5qz~a7_gb&c*37T*>im8O#+Ek*Iu{(8NcHy@O zmfPWnpZ{U)UI_fu&3fgbMHw@>JCb9bzH)Un!oHXC-FGcdw;C^7wxng-SQV5@-0H+K zq!jCPQ|2tIt+}9~^}XtO4cO)YeT}ieQ?8~=EI~7~6!F^xjtI9}p3_3O+8Wd`#w<(X z6z5g6%!54cm-RL}w;b1S2rrDHDznl0rD$ReRPK3j(ne&TF(n#|20LQmJm_Ahgy7E> z_ISy{${0J(hURbw;F&T9L$~)y6jeEs=Lnu<8=gino3nT#O`K)D6DekzuHYve;L)oY zQrP-<3!XY8rU11}zC9^ul-vsTE>10zZ!53^eWBp4hvIy_KQRTUW%6Bi1#K#Z?yI;x zP;+q5@QnEWhe)hP$7X$A+4v0mmGPqj{w$1_jBf_MzaSF#xQ;35?yGTsoPK3|MdJ@c z*wkL_^)qM`(@mG+$Fra*=_=zk-IDv)w!GxqWOJ>_VAh-vp_;C1@@zyPy zrF1CsM#cB1LgJL+n3C=>JHAAIW!$D?vlNeLdySvXqZ8-&HtV2K=n(34A!xIdtBkjn zQ11UgX7g~8hlIAD^Y4KXqwT$qId*^-mOSb0)!zWMOt$&n!SpU@lsxUBc!S-LS|;1v zw7A6+&-fENThL}Hp6dN2eae%)foO#cieci}&z*RG)-A9?P(KSkon z$eX-9YASTx%)N=L%v(7edT(N$X*m*Chc}rk7xW_;i6;P_M0pbMCe9BcMU}dNTrJ+@ zuam8L{`s`U)EtRt37$-8%bWbV_RzDgzdlzQ$9M%2uVuW6Ck&n%?o#40o#z<;DaCl+If)t4tE=46Cdz>)~lj`_HJVuAE(6 zGCx{AcV1adwDY2VeY?y!NJqQ)qN;mEWkp%{vXYr|XTVDyTbePyq;$^QiZbiRuw8Rz z&A(_DE&ylDE-jr=zwiC>dgc{)OYkqYP~Wmf#r4WtT3NBMxT>VOb}qcFm6z1i7FSl) z7N1_wC(k$p<`-&m+=~@nI==>KfTl&pR9S~~kEI=*~a|?2s8b7~D;WLaM&dfac z^K?D<9w1wQI`I1&&Ev#2(({}MS_m6=pals_rr=_mMsxSlLRqh9s97_ZXc`I~9zHSW z#HOJ};g+G0vnX#scu>=9NL-qMbR--_rcXATi$;s!g%qwx8#z<*LMb<3@!*CSb}=Mb zO@o0@E9WcQ4mnM;gEpOtUcA(X(sB0KQ8*&YNi(Q+Bwr5X9ACCs=SGn`Nx=Z$o9Dm%M} zr@yh<)xX|Ae@nI9+*Ekgoq_&lgq`cF?L255XG?lfIBw(Tu)zg>t6^`hSEEliFup;J z{;`4nH`Qzft1=SqWg7oOg97)c;!_RusAzidta{+~_U@&2UX-IAc3!meyd}PCsg`V` zYs4-4pt0;YPp0Q37VI(f2kUMu7CI1$IA6kCp1a~6UTR~@a2?JTV6&lHYB;v;9?Hn? zir)9YVq|q^CW{M%Ony^ZT3{U6n(|Fh=KISIa%~rQMp>W6{e&Z`IxOrw#qny!O|*5`xo4@}y$6TOc?P3} z9oJpdUoXX6o^a?k+^zPcTdi$48g@=QM&h7ow z0Zp^buwirVhehcGd##*v8g4gVX)FE~Z>nGqN^IWWXoK3GR(~sAU1L^MtfWT6sJ|O@t?Lr&knPO#2YV3q5pZ4{(PU zH8JkaLM&jYrIV5u9&i97IOu3WVep7N=hC`pd?${!!GZE8b(oP`fZSr(OLNZ5%fo{n z+m5@ZT~t{`&zY4K#q{M_Tv9!|#u_qlO!1f@lSdYh9Wr***h2bUrPo!@>1uWFepXF& z>Cn-vNH>}|yU~1W|q62H;rFNxa^!;QR{l?b^VjZ8<{j^*su|kCc%5>OnG&! zE-Qh@$oVs?;nY)&4(mT-N=;dH&5Y7{CG$(F^9yE_S5}|aYsRoKlSWM{?&EUC@JZum zjIXXdwXC$ZX2!9@hM6-~CEe_n!woMTT9#M9BV}o2y57MpYE>XMgU8an5IZ zazc!^Ru*9K8@M8l_j&S&Nt25Uhm0CMW#R~T@ebgiIN$YB3|GZHnd{{)qgk17)eDEc zT7g`ry!2Sqvv@8&!Mc4ocI=esu!19_=7K2NGryo;LC=C-(azOn^U6wU%DO~P#05$B ze%)tcq)O*RtIHP7t(jX{5$)Oc$owOFpA_vrzqD$>F{SW7TehhC{N9jj=PZ~%6D)_m zylP?Z?lo22XBG6NW?p4UZFgKc9y6z;dKMHV)unTe!FpYIWLfw5UCXPY-Dl4_qolgL zd(UY1alNA5%PT6o*VIzB)`y5rib zwz{78;`sQE9x?V<>|7%zP8>J!KjPEa+ipweRn}m=7uU?1i>MFq+{=v`7vl4{VyxPd zs$tw4Oh^bg=`EQ*zr^g`$Z>xk!u>t5Wx9LLq%ot144-Bd&&1lo-i1rPd2?%EWIlJJ z;^HZz;XW9YFYKCybFpKeQEHqxYr|j%*s1tVQCy03UxDD+s#d%Z`#lCaet^K1{5>}# zJ-A>8y81P{yz4r-Y66y>j*Eww-=T@4-;jyNP8l;|>|}3Ed7hQ4CY4rWZ^JKlH z=z08~b(dVRVE*_@EO(7NtQ=9}Svj$v#J8DAqsAUPW%LkiFF&4B<%4vke0r|}9!nAq zm5Ylfj+o>wLcPNkd@q{~s-Ab{^10PDwWBI#l`Z07&^^fd94=Q4=hj0H!KWFw&h^eK zrPy)JxR=zH&T-cOb6g9FBlhgFTI`Nx^nwi!)w8g@71tOq# zyH2ma$NjQvsp?F#D>wATOh3#2+di1P`JPztfyF+3Fb~O?=1jCxGTIMK{crTe+}5`Y ze8ANn@~7rjm@^U&yeK(%+~%M5_Qi}3J$#d6`Jeu=K3)g(O%DDI@lTHNLXproc+~Ho z_V(3`w;@r0PlGuA^vyiNS0NMm_>)WIDVx*FfsVp>=e9kf931FaUH=qSZzH$vM-wUN z_G4r=UcQ#hk)w}L{$~)#aQ$tNO(h$j&zRYPGKPuU7U%a8`-z3(7?I1za;J!8VvV?1 zJV*SAc%^uQxL$lv{H?f2{EPTE@$Vv@oVd#)9w`=ze8|cE@wqw4hn(cOA|Gf{UMt=& zJ|(^)@?j;*<%k_cb@lnzE#)DmcE608tUwB{;#{e@vVu^UVxL$lf{EL{I;@0aa4ik&S zapFvIj#weqif4(}iZSsP(fEo(KYu0J_=DQmj6&6!TELSthEyXs{A0gTJ zmP5T>(ic%pa;i8khvu(v?^GsUIS zFPD6UcqNH?Khyl%q`y<#ApIkf9~1vTqTVLWe_Pxk{b!Qd7p6=ST1NiMyo#Smd{z?2m&>K`uuYiT3$*C)rB+4wAcwy-C#TFAfyPYW_r#Uvbh- zu{cMZC!S8i&H{0%^yi9~OTSvYTKt9P-yz;3-Y@=6d_sJhL_5!k{LGX6dPCeQJwNp1 zIQ&C;UbM1YL`)a?c_;NP#Wp1Bb(Y*sJd#Aa$B0A337S7eoG$&z;%wOtJ|#XYZW7-iVedV0m-w;Bk3Bj6J2BYUwVNz97h8+% z#9k!o9VreLhl^uGe(1?^Q%Ur9x>zdxY_VGUMdA|ia?M{Ut`V;ne<9u>-c6#Nd&I}Z zr%9~WH%Rp7uj0GX@07e-h;K^2S^QA?o#Gzpza`P{M!5H4{VcIL z34L419mISR{q8IF7mw5YapE*_hFB)f6)Q;CsTP-tKNBAo-zIUa+bMn}9)^2F>hr`= z;(6jq@lWC#;$OvW;w}-lWu`y4>^H=s8)7#xY%ZFYTF~zflDminVjpp$I8`*R;83qb z@@ZnFxKK3rohWyX#3#K zTI?Wp5%a~~;?d$D(cIU<4qxJ-J$nBjOT@V%9Zpeyj(CB{4`iudDc&O9CjLsiSEPp! zmjA2xzPMfFTl$>;x%jPUUJioZxcdRqc^?b%r5&=h*h%av_7aa22Z}?*QKA$^Q`fx(MwjiRS(ta<=5= zVpMD|b`^Vw=Kdb_21p(z9xECja+p6+@`+-xXxy`5J_De$KXiXXo*_1jAI5T{~$gizAU~bZWiAa&2tab+b#Jk@mnzo^Jq6!Y$7%j z+lct~*p%xg(nAvK9VH$k4j1X2h4bk!k(?yX5Kj?ji>Haz;zIFk@f>lvc!g-5%OHQP zE8<(?JK_i84)GK5 z3$Y2GC!xJ&Vh^#GSR{@WPZ4K{^t#0QUaX1hB;O$3Dy|oQE#4MSNZS zoA|!?kx2J%?8iSuI>M&hFg8WD^mKj3`EA5p@dzzzZUNk&GR|5^SI<^MK6{G{adkr+r*E>&qeyU;{4WP2eFIT zQ|v1qBMuQ8#W#e~*Yyi_eKKi(X8NcO-i; zEp|%wVp@D7*~T?B?Iw%#F-JLDY%aDJJBvNUUg99pJikPJ`U0aJFP6m;$;-rx#7o61 z#cM?K{1WwVmb_lPTYNw?&o5E#Y01xtuZXXU?}+b-yTp&hFGcgb6ZS%Uo(Fo*JghI7h4$YeafPqdoI{6I?0Ti-|$+Xq<0i z+<_Y&n4 z)ToIVjdK!3qb8!kA<@L~sc`^eK%=(7;lI{C>)c!2fF$|y-sk)N)~`>mv-jC&pP{PG zty^_#uQ9?2!c&B&2^rOm?XM7iOL&QJt?&xr)xyof8-=$Be=fXB$PjV#zg_se@I~S4 zLc7liJI0TreaQQKz~;i1!nVTpLc5O%yMdA!Y>xG&3K?FG@>xPgmZQ8{$ar*=uM{%0 z9OYYuj4DU@Vc}E4XM_v~$MScDyM=!jGBO;?n+V$oON4fx66M_`4-gI(o-F)^aG7wq zkWuC6|2pB#M69)p9Y_5yg$yA_`5ED#h_GW2IqG)_{r$v{_s^iuCc@6{Cqix|eK%oG zVSm{%JRIwd6x#hm$aen_$Utx`Uo5;>_#Gjmz_I)qA%ne9zC*}(Z=4 z{!<|%woztqHzGr^5uX<_8XM(ZLIz}`9O`})1FcbRE@Z4V%3XyFw?^6S#{upB8*q~J z45!BOGlYz&MtP->LDeW{WXl6VbiF8SjYfrlwS}sMjBz%;iW{_F=QF_*9z|t z-YsNoGL~->zAXGNAudzR4|a#y0SxhV$Pi5!V%ajRe}AZ0`gX#e!oEWLT>{$YYy0fS z2;nH%q)A2*v(<{}EtFy0W9^a>uM|3nOo4IiQ zeEz&G##=QTFLA*LKTs^2z8F7}ov~yw-2T&BD_COMQonNIF&^JAmA19Tf7;^1wZa`d)2SX%p8S3_DbI7z|VtZ4Nd>@bvx}gIf^8nE1 z%O*mO`+FSz=HPRb{qpqJUFvn5PWZj&TroCDJYot+nOQiV~0AL%#rrn`{c8jr`-jIA zss6o)Ja+pcfNk4`;QpfW1m6}hcK8OtF^+}1439jeyQY!hjt!Qo!I$MB6H`%nK{NUbx3*U z`U0>Z1wH$$I-yMtatQbjHl?s@>tB-_sRP)hayAuhEZT5do2J8q;@-wA)uns@SfvdeGuv#;&RySNU9kJkRmn}S))rs;Bu4dO0OqDJyHED|%uQKq!y_`lLiOak zVQJB(4duxcw^S74mip@|a!XBn?SF<_Dtl9waZ6<$fLp4CaYv=Or7{k}Ed{2oFX5I- zfLki>U*MKXtPjC06^dJ`2pm$J(U!xD)-?yeRP%L?DeQ>tIoL~Mc8t#(vtv!}_ggpL zkl2m)+;-+RIK4b^MYwZV_RV_|xjB0h1uvE7m*21_(css21f?y@pTyBJu(tHUBWg<< z^{Xu%a#U?;5cVnDn^$uG(58EXlHE_g42#^InGL3wCpMib9;)`>p*r^1%sq+BKRxYO zsO|?tS)7N87B`v2d)wJs(BrYEk1roo{*p0KwJ;{C^0x#0O!SK{HuG7gogT@MFM#L$ z4QKVGQ1D_UzJYh@3f?yjvoiqEcq{~I-l@MpN+hy)12>wET4~;?j0~tcLZ9ZHx(h1s zPHja)iR`TDXeZ4(H5`?rAy9eVsh45wd8hb1FwHx)6>UaO;a^?esgF=0jL1*nd8fFP zdfur&qI6&0sVa2E^G=n);^4ef&C$ge?-YO08t0ul8{P7}Q*-HjAKocGn{vEU9bxNv zr`|wUQ@m3loF0&O>LPSA#yeGFV$+LJpL9cfQu(j)PVv{GDc-5=bdctq;uUR-cPf)& zns@3*j3vf9buR~$=AGixl^E|77ylUVlySGDd8aO5-2?JYeGhvz#yiE|uf}<&9%gZj zcd9Ku&%cy+>SeT+=AE+nPV-K^!$GEbr~b%(|J%G%!_l=A@6?|-UuoW{ZS3|wyi6t59tyi?~1p1npK~vzd8azDG|fA8GsQITlwG{0d8ZCxyZ;vN6rWhdc&EZz$9ShMW_vN-sj1vm zG2W>U*?x?7>LmJ)@lG{k{TS~Qf9M|Pom$RmjPXu=MmfeiwUlyG#~^`?h7@6-jfi1SX3 zW1Df_sVshs#(AfXdq0Qd8ZC%!*Sjz`#Dy2l27B?jKjZryi?<0zp}UorZgx<3c}*+;1Il1 zv!P1!PGvQs))Ph0ccnQ9rmaJvT(88a= zY&4YRNG12dA{^HE7UaK&bTM^T(r&ofJqGz9>iC^JJl5=L9+?BAU@F!@ue z(krPOWxBsWevG;&s5`L{+a+n=9Z01&u+O7S_XM&RBbDAt-5AsT3SGDfsU1n6#+tk7 zI1EliYDW^Nac0Gv9E{4;9wboXZLIA;0yW-9pjzXGMK)6D;~e#PBZ1lic{6oC5gzd>q8vZ#}+YH0&d6CkxC zyVFTcXvIgWqf7;Mr<01Px)9=dRFP6@idEzb8!wp(6{lFm4aYxZFAsNoI&R@u z+J&uapvca{*9D}G{K=A6@->ZCNI{1e@NY={I>S(OO#M21lsVbz+=Du^P^Xi%)84hy z$^1(QI@H335BRCOebMj(~ZgoRd}L!6PW z-i4I{{x4(hrM$Czb-tXjl+}HqRp+D5wN~9a%}OGCdO7bVUzN{4Nv+kjh3_=q%y`hM zbw3hcRQsV?l%|<_t$=cML%2r_($!yHdSW&%5Z-DFx0T zU(*`>3*pJ~(UFA@d^&oHf3_8efrOsYG4+xCx1h0~ z7WBitNpt)5RLfEzJ2sN7oUs zvt7U`9*BgS!|cbos3x|j%&_2Y-w99bWu4%Y-^*Oh}l2?iiZV)+uRKToN?uj@&Y zR6poffQ8zTBs~Nd{nucLCP|VB_hHgVlEe>!0iGm@0xk*o89A^824f^iR7RX<=Kv&0 zbl~cMB+2Rw3+^k~Hu~Sb3uqNfKuV)*xFFNs{v; zk|gIxBuUPXCrLUY3@<~Em=YjKf|!R-Xr`}8l7eRcdq|S%G9uOCL&6O@&y{q%ry?p9 zcTt=Vi5yAw`H<>xB=I#|@ga4Lb03M`s18RG7OJ|`MB+p0LTVya=<4{8y2bdAx~D4D z+&HD zsLO{mFkaz!@gWVW%ZGHtzsiU7IF=NnJz~aU3xE%a$Zs46?DUW#RgXqYFHkO@4aMdReo^e|IueTLLMz~{wGe0Tb+IU`0*4bJ@LL6a&vmaZh z7(#gh3sA5&_z1{eGhb%|MFEPC_}^{39EDwyXjlEg$pn7ZAawtoMm0o%zAex`Gv^|) z(h4A7G6{oI`A*5BQojb=r96@Sfr;-Hcxim=4&MR59lo@<4d$@-Y$U9V9>Icr{gYg7*8Cf1BOv*lkY_s6J{X|Z$VbNn1+VF;argv+J>#;+#u2suafv$4JT`AS*1hIT+6mVORHLe|?VF%)A`$ zhh!8Z%(yY1Mz|9R!yr6|WE3OJyyb*sjo*RT4V(<7Yy^St-R>N)t59OR;9RdMP1I1n z#_3j?6?B|C?s6RZ>AABkC#Vkb2*0_ZZQD?W-H`sz3tbM6M=FumFgVJ#tYoHx31Eg| zrW2Cmz5+88g)T@q9S9te)$&85J07F1hm#0QQLto14Kt4-;lN?fxi66=FqsK6?wFnA zk6CkXL%_cbhNz@~|IA{8aBwy#ScPnk$2KnBk$8>96N$JL33LvG$C1)(Pn4dt!f^y1 z66r!pTw+88HL5NZ6z4RT%?2kEnj;w%6f^dHB$!IzC9Y9HG2@Psh6 z8fNZv!txqsB&;yu9w5SKL~3(K2D;=AjSv^M_9G7L4*s@bC=w_&2qTe<0g9RNPDsXhctAkK zCq?s+aL^MLJEQEH<;biy{ba&A)1SSfhMB9Ku-tffZg9f6sZW;u9KB(>U*psLI_un; zbicry#SXGNIL}vDzve)|Qb1Vb^vh!X8lUbL_>R*30^bok==xQarUb$i+flBCkD!mU zY?QdoPC3r4EiRNo_ICyq!C1m9B=9AztYL0 z@d+`r(ex7t?6A0ieBa|-Kq$qBEH~?0@B(sf7~=`^?LVw@-64%1;q|JP;Tb3fw+~Zy_1C z4>N87nBo@ztWQIDHoJ2ZJU`6vloVZ3nVp{;5GTT)VVS{Fe1w2X34OgDDci}VVa+y3 zOtdEMvV6}P4u@})qIU%Dajd%cq(;VR<;sZ>+LUq#{z`ziP_TOm^IVqT1~QgVV2;Q7 zDf=>-9qy;N@1xA&M8YX9OK`p?61F()oq+8w%cTr`LzgD*uSI-sKHx~~CQ2}w;P%gC zf@^Iup^^EWyg$G0x-J(+Ly>Ska&5oKWxYMLXx%o)%ENVJvLrp+gKb9Y!r zc8iSu_aUX21?3`Fov;`w&dTGx?^Dk=kg$7`XPbwUywb7MuQ4T;9c@X>0>hNyquZ-E zt2_!nM-o*Jv$Tv^xw|ktt8l#ds*uc%M~SFgX&RJPk0Hi+hx5UH%08o zohY~qNpw8SvMSD6??ELz19-_)6uX|hJmIe>LAK*BIOEr&v0~qJW`f5p_dRGjZov)p z^p>EODYoyErsTfg*PL1=bk;iw6J4MvbLPCUpWYJGGQ}=$@zW$I`t8p=?5z@<=H5x{ z7IAuaMj`7DLW((#D^tgDV9Y?heO!W@zP3=+qGwS#_sO4LC5)Ag7$@`m1H$xy0Z%2|}4lBeyyyM5oWUkK9_QlLY!r-x#n-eppv?Jyf!5}$ zM`!bR0Nx5PQZygz*lcn#k0ghUQP_awAvzaS5}AjaXmmD*WMpQBV1vkwz*_^#4(1A& zt12dwNKtXdVepp|H5dsx6_kSZB{DXf9H=wEX442*KysQM2g~*%!Nk%~Y&LN2*lgg4 zJUU0GtC!O7+>rD$rD?5INB2`o*6Ia9kLEBh&4>=o$bocd=7~k8HV0kB(ao9{Wi&(Q z4g;G{NycGq(C-phhTxw7n@vtM4U{^KqSY%eL%ud(V<)EBY%WR|7YF!0!1M9>`NlO8 zeKV0_v%v&?Y+CSnI8(9Npx~49jUFV#OoGj(K?F9NT*qe9fNVBdVzc?A4i5gQyNs7(p`4pQChI$j&Y~Y)lXR~?QRcq_mY+!R6*=%sa zUAZzO%@fYczv7`H*lg^?%7YAs0Nw&8F}rI zH6p5IFex5`IvpJ86)NYJHP2{~VxwuuvlwhNXmwJEb*gM6szwXIJ;TX>9b89eV_9h7 zsb}ie$jF?lzJQFXby>6qgfsp;D?SWwSssL1=D&qX=Bv#dBkq-hlg9jCV~6>2UKr!H z_?iLcKfnNkgTLCSPdq6O4%{@wk@zG?Bw}1dpqZ#3*$mkzj7rDTQGne7R82j>M?snl z#8IVC!+Q#7n=7gXK=RBnQi{h)v!5?UeCD zyRSJ|3h+A)?3@IUch`vD7k5ZEO`o6M1 zTKZwa5zmxCPZ!RX{w&E$gr1XSwd5;>n}jzDeQJVrQ9<$SA$eom3zxLMGSak4;vrpnJ&xy3@nIMzsineYlC^w&tf zR`^pQ{23Pu@NUVEsr(7yb3)I_Vq7d}-?&(SJ5Wem+4FrL_CFJ^u&|vxAz$yI zTuelHJ7ITWFQIX=pxiiFfWxRqz2k&qWj9giV=Got#(0g31@-uj58LrvEZ>rRsn9rC zP=1x_@m(I;|5&(%h<5o}5Ai;sak0S8xLAPCO8>l&@A1&jo5H_I&sTcr=M&+ZL)d$$l_ zf1B_g;RC|o2!AVliimp82w#-`RpAclcMJb6OcuI!jEe>B6-sU zv_rec5OF+MEJ)Z{EJ&bnu|WT&Tr4R6j@t8FEI*L!xmd1~?73KOReKK*(f(G+78?@n zz9jqql75fuJ{Im37B+U{ZzgO>gugbzF2a$*GlbtI;@sOPyisT|9-)6x@<+m+_)bIn zqlC+ZtA%TXR|+=?@ioZ$!*7!87pBS(yU(zN(0&Pk^7fKD3wsIqy^i%q3&#ujQ+nzd zGK)A%$e&_TUMQ>#6yMcg`OjXFKn}XobY6!=K|pmOIXeygAkVp&k@@9F6jBgMwZ+6FW@@K z8-za;9*iS|KV_z$2Zeljobn%pd~uvIf9OrD&k4d`IZ$u!zX1=ETq@-6*;!sDG|o-P z10^3LJXSbLI97O)@KoUp;cVdr!i$C12(K0LmlbUP9wA?Fr~Iyvzj&kkci~>)7s5>3 zhhTZGu!*op*hW|)G;UAWcbD8xI7oOf4v=ZGnY;;k-SUzq0n=MWa31(@e2!u&4g`)B|`iD3%_NO4;LCIDfB}nmkUo6 zjuTE1GK37!uM6K2{#{rr{6ZL^F8ve=@z$ToJ%oLP zc&W?uM+uJ;o*-nj3Hq5VtPsu=o*`TyWat{&pC@EoEy}BfYlWV>;~L4=3V$N}sqil0 zeZq%@j|sO6pA&j+k5?tXBitqYQ22>3fg54$U#8G=dlX7;DQqKT=r!7R74{Vl5HflU z%ZCZ;b9$UE{h7il;n~9Tg%=1f5q@82G2`Ih?neL_q=M~j75-NEr0_Z63&Q^r{zdqn z@O|N4;TOV8zBCK}xxyyGB4Hb0iLk5CbAJqwY}~c*!w4GmS1Ft)TqHb4c)svk!b^nf zg;xr%5gOMm{N5t@HsM{u`-Be*9}{jDJ||>25BASEa)F);q*i){^k8|hkTFRqcNO*( z4iFwK93~tioFF_!=(#{DC3`NAD#@M;#5i}+-UZUH5qd5Vh8JOf?iAiH{I&3L;Wpu) zgf9!<6uu+eBm7VpA|wg@X9)9zjfC|%K1N7CN;pAyl5m=EmhepBLg7;3dBTf?tA$qx zHwb?u{IT$M;V*;_3m+5yUihr=Md7Q$w}d-{49mjtHxM=v775!3ON5<;-GzOH1BCTC zKp5hM{!bS!6jlq*6|N9oEMznv*1JsTxk31TKJ}g(UxWR}l0O$BN~X2zxj^zImkK)y%Y?m!1BFKlJr~Gi$=?u87kVy`d6F*_ zep`68aI?_vo1wq_2|nk=?w0|7E!pmmLALv2K*qnJ-N!;kyrJy5K8%wXvgh`w&*{Nv zH?%)aSf8_FuJrSTj8H>+yZ;6JuH;LF3|7N(;~)m!E%|=oR^g+$_=7l+-)g57A@O(MdMaco$Bj?lP-A)hb#BH1xu4ehQJGB%BkLumK4 z;Exe%sDD&w_p>0|{VX73(XiZeb1)nYXDAOB+WjfWo|}X5 zW>~&J$j~yBFBCGm4CSkY3@}64--lv&8Oqy*cAp8d=ltD8J;rJGm7xDZcK&`+Q{7Kt z#2ET9j$feNM*@0oUq*vr`2-;Y!caC&U!dJD0-i5DgT1hPo$xxLarZ)RT)n^tq-U@f z+CMF1Oc%QZ`>Tv<1)s|p*BANLtG{s!o(1#hhhEi`^D0?6ZRDL6%G&%7LE{( z5{?z}B^8cinsAnIj&PoEnQ*yqmGC0rYT+7T{rdx(rN3TylkisIJ;Dcs4+nZR5ER->_?J2d{AJ^FgE2(d7q-j(Pet-|kPTjg0Xa+k=F1j9 z;qxpzq9wkcH}Y2LvNNEHx4Ua3d}4iMyVU!3&qqG)FSlzD6hr4XUv>@@aev!Rala9v zKU|Ka{9T5;uY+vR1^!0F6h6BKWpRHm!QXZi(jTTL=? zaeudBLOHMWhheAu{S0~5;qk!j)joI;yq-Un--{HtJLZV}b2&UJJAiHXz;1~01b)|untj#W1*KlpHd+Vx}<(slI*1s4ec1H;?Dg@bm8myntCb>S^ zl)Y|akhv~@W4N~E@KzgMt?dNfh1QpyIyCpPU~SI&wdKL4mgU*K6YDN7&)9g#oKxon zU4q?jt_s?{T-*A!_T|Op9m+2&f2B59^h#~AxL{9qLEF7qvrG48O$vA9hKK#*!o4T# z2*b8}i-MPGgGQx$6SLdyO-zb*q&4k>TADct#RqSdkEuG zW9at0jjcB1*Lc1K&$STt35{#v`>j3O!Z(a-;ekCt!(+FTZy~r6YzvF(vn^zm%skey zE#ONhxE4B>hnt$*o9Op!lg!uB%nFHqFE)ujXc!%_D%w|w*7e!6hWFW=dHY4h^F zy;$L8BPIrzbL*7fzir z^hR&sUtRtMk`adyZ|`~jg*K?>`4^r=>Aw66zrkwe`4_sv;^6!X3+eO6Sr@Y_r9u8V zn7KIr0;2$X{)GqVd>{UW??UVN7kEe9^Dp#)+Z6x8L^wSl{{lIlWBd!Gp3do=;$L_R ze*RVdg=^s=#lOJEH!=Q&^XYF;jvH<=zk*_#e}QoWWBd!`#E9`P9Lug9rMgY?k6_)S zCAP@##)i`T3sKPy@H#z@%Gm`MQR%8M|5g^q_!oE&_DlH}c=JEazhLv7 z=3h91JxlX1bYQ>#ZT^Ms=vs<@p&JL8=3n>)yS)$p!YgR+-{4=k6h~x?f8lgCbzjaf zJ5CD<6C2}S;LZIw|3W_wBF4YagmR33;U&(<{DgK?&!PpC zWBdy*u)P@n!cy+482hLeLq|dK5|H6ly#>2vv zS79(M_+Tr|zhG-gjDKMpN7EtH9!wTJ!SNr6f8j^)o9162OMIMvVK65*#=p>sGxyK& zFZ`aSG5!TUY>V?R@Zo=)f8iVK^~H%Id+1-x_H%&vVq(QO5e|3vB7B7Bdk z!@pppEZ<2qp9H^&(m6%b*xn^xUQ~1_?PL54-(h=k{)PE8i1RPBqK7#D!qc>f^Dh|p zNt}P-6rN0R{slf_uEW1DpTk=3x)qf^5*FPG$=+2!eU0@ z0RIBHmSX%1bE&Pvzi>5b?w^0*M*10&i5j>Ai~Y+j%*Lf`iSZE}W4sFEp)5x#$wx!s z(8jkQzXj=9>MTJ1Ftck4H*{6ff|EAf?9PGAYrK;8(1-9?<5l=2W#Mxt<{xw{)Zy&b6?NEAj}hu?$rCQ|8d*x}Jer!WFH7x;X&^nE%TeJCg3 zImpi-wVR6vBPChrTOtMRdC-hW)oJAF@Q2)ekUCl&DTDUgVawkrJO7QH z?MT>-NZCpmw0{S-x20@Hh0WRj3fS>S->xrGlBvE5Dd@z5ocED%o?#2`&wUFHI=6!M z6_me()P)6IJ3&(miO;QY=Y`d7MJ8$g?FQ4Ya@*rsidE&0wi_UIrwI$KdPitTHLvPh zkqHC-f0Vi3tjua%e+BKIpyAUo z42O=XkL>>+kqduUK&}9D{2q+>*vuS9XpYa!%yA23_`s|?E3=w8CVf30n_=$^hGXhQ zx$s;8soXm=BK=Sp@L5{tsSr*=h7Zy@kAW}`89qhp(vuF)hUQX8-$T;GzlBT`@c#~^ z@cBIQz1x1f9!A$9b@zofgTI320au*^Wu>J3e~;DwTu{~s)j5OD!suxv8|XX8yhVXC z_!%;M;?|v&-$N?n3~J^mN2Yxrx$wmT^1++K#^@Ly%$dWE$ndG0IUI}(AIWuRWmfYJ zIb)yFjs55C%<#>E7wC|)HV#$ziAP~ahPBr<&P*M(Ko zevjVBld1i;sNa+P2R$ACK~Kkj&|@UZ`77UdU3p>|tj2-)faQz9urN{eecg;D2w_>G z+ClF#v3{os4En)QpBu4)CO}|7p|6o1cme}QdeFNR25A}t9&CrlX$&CrX8Dj?&@_ZJ zjX}qsa3X)7mB$kBLS#Zp(HL-$&W~seoFCB`I6tB>aDF_ELBBA31G}4vGzJhqgkz?! zX$-!mF$mgw-hvMM;Vr1cWq{K$#U5bP0^%*`9OEtM;&=C)ixL-2sc=E3So<7#}VjyKV$?MxS&gI&igpR6eI+p zrE4aHjwF2FvJ(hbAtAu;2;!}#9!qd7j!(JVC)3;>lhT_09|(bWv%TWP9B`dyC8C$2z8Z| zc-08&B=HAWezA8AA4DFZk2f1N0)=t{-%&;*A?P?^GEx*EDmOFyh7DnP z4Kw^0Lh36m|5k7WR0Ib zL`Uy}zA&YU2`CLliW3u19^!N^jexUoiRlk;cA>Mj!3LF6A3%Q%rfPI?+A!vip^6Wkj8cR|R|8_DzcSP5{LZEOmgonk1c7}CoC+T2i-Bi5 zHTTwLQ?E6=-qaHaTbz0nk)w@82j;h0G|T^P<8WLqAq>NGjwN^<2{oXEC)+qBLy&l~ z5qXt}@X>_PNST3M1=cV>!HUKac&+G*IEnmT$RYXfhndJ{g1F*m(DN$-$O{O(&Nbcz zX567Ol~CsN%W9Y@cfz?f%#3!z@)~9&tT16b6mU!6b3eE}w}zS7PFP;U%mOE@s9}Z) zH3(HspQvGGnG=@RFmsU;R@5-F8VNNBYn(n&!^~w)NY*eTVMUEU^08KNH}h*tkEmIuUsAVTHbPrT1e34Y`FV zb6W|33usnw7Cvh-TieIjzxQd0j}>lc*tXN~e+?3rB?3EzBWxnk&DYwiS2FWB5=f>B>&BD#W?*$PI?sNe37aW*ck29K@q1hvK6wWb$JSbkCKg7fEjmyPvH^j zj<>Zpt@Otm#(WdTTxQ1{CxWf|qb3vd4dfEw5mSzo?PPEX@E~ELwLf6u%O7`w=M3On zZ$$?l}FoENEyM|0pjg5OUsxQu3w>W zRmXaNQLq_G9wTB5@C8Zx=ycYpaP;`BO1a?Tq-`FK-9<>TnB<(YOr(iWPeBq-0JA*8 zVM&;VbU?}g7S2J6Ur_kV35?J;o|)h&!ChZJEP0TimMOODlcwaZ-`AX4rr0>b#8xP{ zcVK=h?KpfAf&=6Q~Nz>inpwvsY54emQI=S=`8nqlAyNRLe{D0EJ{$p zvv%LzLM>B#FPh>#Q%=Tz+ma!zoN~N$SQOLB)F5N`G2?T@s_!Gk_fVKtrsh3%*D}pG z5QhGqWbAl|D^sn*Kh7d1E_d2+!a%{bJI2)!nWa;vMif`3d`2OyxX|n~e<7D7mc$P0 zq$#w_`Yt3xS~+E^wY2hpt5<6{z4x)$krBz|6TY4lrM_cQ2! zuH?%p^Rwt4B(8^k<66g6&8OMOb7_ok@p-u~lb03zD*bgh|Nj@l`Bzm{&O=b!iuhX* z2uX+|guzwkPhUKzYz|M9ne(gXR#%)pb0$Qb_7$@#XHQ=;Z*j%qa~4%rLx-~nF>+@i zMkxe*wlh4g%cV@9g#{`?kE5unveFx?89Wol6Zs&+4!`Kpz{T`$!z5S<3_2)^l!G*0^vuQ%MdER459K{ z9w<_N;oxZC$Y|30QP`3%qijjY% zGffw~aj+Qqr4|$ZGFPvMbBGw>@5+PlK82KNhW8{C&$H;%hIdQfd%ySgI9gmT}*~Q2o8dBxG6pU?qH54-_G8)ICsgoadI(eBRU!hhDFMs$VmA;iqV7U4X^{G zxqVm8kx%q&Jod{7;b9HSJT8giyeqZ~BeAi61JynMW&_OHjs|K|d1A7Blw zKos!>)8|#pSTZ|UvVcP6tYR#XLB+fov#aNxTgfQm(@#g-@QPGu=gO+81q&4@c7JXe zki2>^7VMy+s&e`)i%*^oV?J!q)JfHqRn=2x&YM1edR5O}Q)e%%IA@?h0Ot0oCitChlbE|P+%;&NGl?a_*QE|-p<9fM6b^gKyF5>;Hg-gI_5LApB zGwg(li9yBEs<~Jua9$7Pwb%q(ZybF=P(5d1)nZ$U<}F-sx?7Vfs%K*%z#@ffyXlLk z!#RizW&{Mj zEqN777A&c*#1gfjaw%4mvlnBX!X!>#wsaO&mwEmAPIqQA=ACJa;aPop8K1)9`R3_N zcprc41UI%i%O@%f<0`tqNEeo3@j<=R5;UuNVa1&33ua*|77gcaW4GW89jLPqi}E48 zcAZ|i7z3}Yz!Dr(OrM30S5&hGW?%^h=ZAVW*4Me1bCkM*>cwD)IJ08jbUQ|7EMB;D zre}+=3E?rcV0snSd3^+^BEVnBv@wqbFf0`^hrvi&I`ofQ#-e9b#u9&$DyScg&`>48V z=Fm~xJ@jN;C~n@S&#Po(u)z%C;@#$E!Tjm-FfugAJ_Ps#8C2ZqxY3h}CoWt#ueul? zImO3R%`ZN7{)|do?awO4XU)vY>gt76)x`t4_wLziK=-rycAr1}jD=O5iwBhTF6&iH zWv|}7`V@D*Zhi1+xuBtqHE@!>CcfbBU`}h5Z#qv8)JbZp# zJwQDCInltcZan-p@$cODLe&=XJ@#FQ1?k%ql)j4b@Y|tZytBahXFU9)*->qLx-rTN zK+0conS*bj@u2woy%OU0)7f+9&9lSWF@fk9hwCyV#=RgPUyGFweK*NHg?z<=?G2GU zTxhZKp`R#uitu#dnL@rbLH{d+-xIDCZWdlIyhCU)!cgx4%1FNa(e6&lsJBP> zp)dn&*!YD7MA%vEd|)f-EoMIabWwRvVPB!eAVc{G*`FxA#m$7c6N1nD9U`^IujyAJc4y>@8+K>VKkg zAJZ(t8v~q|CPb7M35$j8gx!TcW_~})sOMvz4O6+r%!i-xDxX5cJXp*#=;z7qU@`N* zt9qBq-eTsXzK@Ca6YA0aPldmf-9y4hrMKAmu(O!?sBbazfj(B+JF?p)5$ zNcAjsKKxqDeAKs?`M{S|{)X^v;m1Uj?-d>_W`4^;H*Slak9Nu=_a)+Z7*2%05yBIt zpDfv8=A*olGU}hH^7B-_Qn*^UMtFsAgYX(6+Pj$uKfe?15au+79_K`B;gQ0n!i$B! z7XDuNtnd}#>p~nk)(*eru{|_xh-owA53#AY$JW61k~<4~34N^k@sjyF1J?V7aJukJ z;X>ir!gGZe2rm|{5nd+TBD_<0zwp<>M}@x=J}vx%@Fn4ELcU+fe(n-}ApBU!7hhT4 zLU@?4RLDp1EH4ud5Dpd&6CNiVEgUaAS@;bhU#g`)MiU`kBwQ`D-^oFLxn$!MgIpt- zkLOvBkLZbfA(!}&@VCMzg?u@e<$Hw@zC%;a5;hbv+yeE*!gj*$!d^ljv;IiQ!-XS+ zUQ4GAyR z!k2}7DVg;e3l9+2;Ua&7XDrMnJ~m} zMriM2*cV7{COkw~BJ3daG3@(D_A%^-NIp(@g78#fg>a#;T6nH-h49;TZNAbe=mGi$QTN=e_!~8Fv5??Z9aqr!sf!3!nVTpLdIWUy-`9R!~P`6 z6~dXqdBR1)`myU*OYdXYUmIlT0<5)Ks}FFa8=Q8-0dA@nir&yc)8 zxI}o4ka0HHpAEtv34biSRk%fXxA1=9R^g+YSm@_rBc!H6Ej zmcq8e_QGz$oz>G=nl#=g?9f5vfY0Ien)z{4+Z&h z$yW(~A-q?}h#vI!y6{~h&PB%cp#D=K!*@_F6t*D3jsZNVH_k;M<8)9SB0NrZjMPE> zDMAM2puA9cHWB{pJ`(ibk>2hfK{oD1AcJtQp2emIG7bmj$Ayf*LHT7N18q=#U&vS+ zl(U2kw?VnJkbyQR_Yw{jmJ1nHgXO0R8Ciq!A|c~yP+l)&_zcQ732!4}oOXW)`mNG4 zP6q9s7cx`^6EDa)~MTgWabt3GG`;^{Mh_?d;_9G_cUxomMz zWr5O(`Z{;{HGnhF4|V#j%D0B zBJo&1m|aiU)NhyH<^7garW+8KAi)sHtr2gV`?5I_ZJ5{|-_r4YKsMM7UpsLx%x}JI z929YXec_LvLG;Ht@cyPF@9Q8Nyx0t7eo(Qp>R6t3ucCA0AN8B}u@H)QyW5V#+Kl6p z?NaaC{U-9h4zj_Kor9p58Ew971?0HD!Fc(I&C(w}(o_DfK;G9uHuwho@t&98e0D7q zaet%WZxssZ4WoU>mVB}>EgbNG0)AHU59+!-?k}kKhYnCo$_~w>hO5r)(1Bp zC*Zq>-{_C&S3+<1tpWRw_x^fZ~P3n5;{Krt*zI_F$?$OJ zwy^2$C@R=~#V0{=?y6JTWFZ#@BUXi7TL1bAw0_B|aObeFcX>Ky{meESvkTTYTo>$q zU{%JZtg901UJP<~Mj_+XCpYD;-4JB2&EL>!~?#@)e&OQANG%n zJ|Dd!LM-~i;D|ZN9St%Nw;q~|g0j7ZZ4sG%EMwBQ+na&7_8F_o_BIQa&q2L{Yk!{I zf9Q^aM9JP}jqlwP<~;LsgAL)P2E%hV99EvS>AX8`|0L+yzczbU|JvlX{-0z{?O&T1 zg&6aQM4z`h+M9t$^vROUO)uVl`zMK>{Xa?Wy1O=bFvH4|C@(;H9?HY6x!Z65B-!&E z>Si}Zoch*#qt%F4Uy`#4q0ZNSRG9feR%UK(G%dO5!NM^+-f0nhkQHQqkd=K&EuIAx zqGVO#gRDeuZIj~cO&fw_4}!Ofv)s_x9svq@XZ=N1kKB)Z9Zx@vJE^obI3nJMMdAm({v+~3d zEjQ+^Z7}>RCRSCqq&se+i?-PDDp?twx0UnKf@x`H7tng8XEgAMeCT|i} znoA+_f+)Tv81*yRx#(~xqcC$5KJ0L0HUK2}8zscEAH$MF#$HHKBI_=eOos~b?B}v1 znPK-z8Oj7M9McEk-W2uU=v*w^p#j}r+S;JwH$b>4RY2(h!^H~XE+Ye*@ z4OB#IdwY!Z85D?Z&ows6P8zEz1KcCF{p&1Aa^1`P6cxh6n`j-e?b)HkQ}~D2_RMF! zgi^+~zY0QjGV6xuaI}?Ejcy^fJ^PT;7Z!+ZPkoR(82=c_v;pm-ATK-Xx*Uf7&Oa3Y z5Zj)gh6%*B?}!;iZ2KnACJ^u~aWuMx*!HZNID^h_YxPH%79=y0--8YlIuP21%!8}~ ztv0ubYV-z-7~8%9{N*z~31Ztbk2VS`&P2F+wV2Gm1l>ezd)I;N{7xn|bz)vVpAI3m zy%QT1RxAs0`ZOpsM@=zNKSpux2K;Lam5mJ_I=8?DW82>aUA{#*9+>0DXHm}wNlfPF z)BO<=v-6MQ2nI{c%ioH@BeuO7&mYaM9VM}8{!R=LvF%-Hi~K*+)ewoT^GCAoF%pXd zeoMp=nlmz+*HroIu~!k>o_WstPI?}dL(yW}KgHtFHZaJE{KIg4fY|mNXjF;^N4Xax z*A&(^0cwRBKJx`^m^zlT|bUM5~(U|8*RJtuuG=d7mwkNfz#kQYAmp@H3nue)~ zN?*$;;&IQ|_Fc>ZRLdDjs@zWE)0x;#GLfBw5tqJ<HXr zhi%#j^%>^cR(~Fab~0o6;CadK99l86uH!T!w*3|iro}iov)J}Euqd*%1hMTY;2bad z14o0{_HG7~Mdxt*h;6SU0xfdj8A-ZtF$R7uw*3ye>WF`gZBK!&cCad9+dDb4=vXw& z*!GjrJDl=CE;IjtvATW8_MBCTtfR1NiuTYHvF-V3Mpug{Uzlj@_G7YWB?oj-q7jV~ zrP)QZ*=xkM=f^|>vF&eV(}->FMlqs@)5h5LmzckFZ2McRt5b@)(H^nw-3d3Rh(y$k zZSUlCYvF(3I3&gf}t!xVsf*tPJ zE1T0poXk#{oaN*NUM>m_*`2ciR6kG@4dI+#ooHob!kF`MoHN9>{|O2crOSd`uId!b z)uBNycMeY^$t`#1tVl$!K+%e;4rAMM=eAnHxk7Avw(8n{&sS;@WDbA{V%t;II^;57 zM>h_ze?XIwn4sP@;%tk?3j#P3#EW#rjKaBjhkd{$*CGCzfySE^}L|sq(3y(HC zUJ>#-sN`d|G^7!q1o4Aq33Z2H+~F~We}e9(ka@{bQcB%W)AhrA_eLtcfo%+LM7x_I zPo~bo@gHlt&r$q4q;|{tB6@y9j*M&lBqWP$f1FvZz>TbPkxJh~GvSDa55nvhkbg+s z2c~OA-PzdJXCRf14VW&`&e zsvRQgkF+_-!5y*Bplx?1G|f1h--f0Vsq`t%(#RInt-_6=c}S(#aMni_Q`Z5{19FjE zjQtY|xm$Na{tHs+Tb!j))YQG%vay5QEZ}|oQk>C2IJzPCV0YYXVSs51l+RG?9qwYshlS19qxVs=8>z$n z?2(i?g*f(*T%i2bsXE8HI^9v!70K0+awrr-tj-ox?r=sX&q>k2(lrB&{ ze>m)Hk9W3lLo06sS69b&PR^1!UrMY(FUuXfoe(nKaZ37e(oi{>Nu1#KzDbVu+XZX2@Ru_ ztNJQdvKxo|fm`@V-fw;NRWMq?>NH`YRo@8BRj&GP0n{h$KQ6t4@Y8}4?AFd7q2xBC zpCWaB7ylkX+DhRi{QDEq^GMxUnbo>R_)h#DG`o<{FFK|^vj1!7__G2YS>~9=j74mY zTOiY%0v&fprYll+R%SJGJQSKCNcd^s1u&vsq5ZSMf+y+qXHcI6i%CeGe*|G3GG|b@ z9Kr?2tVD8A|L=!}w4~P}fq0sGfI)g9`){XcZkU&kBh~iay|B6)sXJ|0YIFE3G*7$w z>=9St(Ec-QPuL_ZIGy#`t9M}a7LxVqGi3HsV6PhEIY}d=?ySvvUD>ma(6mRwSlKh` zBV*NdzE^``F$l>8@t+UF$&e;my&jzWyR07n--i^o2n+VGE_dshu$qfxv%d|7U5$JpCagc|_h!WW-Y#N(Zx=DY51#?BTxH`EXQM*jL-4s}f$+J~M(3gK z;cKu$G7vt6em)RBi}5+lkGsBPKeIsiT>c~Oo&G)$J~a?rAbbff5I%*DCvk=l2%kdG z_eQK%76_kWWPLY32!yYy@Pk1365t1c@F_Sy2!u}|7!ZbQBfRf{#6b8#SQxf1Xwo1m zXjL#NvoIVVHbOgz=0Q|2sKF5p1~xbzlMuBF8ZDVNU3gZ6p6Nf0<#Kfzi$Zz;vEuNW351-KvtV& z)y5G>-iLsG1p7fXBK;D1-vqHF39gNabiMD^4Jw2=B>0|ravoD!%PyrMnL*x4KsO8$gJUB z;3cxn7BlmZTpVab4X1Do62fB=wjm*QbFzk+H=UmFj?*u*K>8RTjn1uMhPOQ+EU#fk z!U_}epnzLKBWHAO4Ku|~SYE?SCnv0^VTK7c2;H1MQNs+s(pnqL40gf_3)wsb0%{QW z1_+E2HO!1~Lb8S#2`g%NWW9-m!-?<_l8YL?4Bw&?HI)D1bch=6ba^BVa z%#=G}c?~n8oq+J|$ef0R!;mn?>6g_oQ)T)IgcYW*PSh~7+6l=TX1?!)%o<*y@mLCj zQ&s^kvg}lXyPjU2tYO9-G*b!Lm`k)v=!9fk3Cs*|LefHi^Q?zU?hhu%%5W|s{nyk0o@0-KeAU<*_n9={Z65^2@^!?M8I4 zsXq#pv+$dYl!CheHs{NRB2&u7?;_Z&kPUYfQ_6>?*mnFE9Winwb zJi)*(QLM)^fJZkz0|;&z8lOJMEz5(v84iNW6AZ(Bmat6~&L9>IL242!_OZHc)pCRB z$vdI8!4{2iFz!@eg?{+~@GCwpjtKlFi7delU@T#(4PY!kr|bKrKj)YK_w~KT98Mwd zn=2Mrg7ZCvkTl;@xRSJUS*|0~Ty}pg^4{8kMq;-ig7JjsthI3j*V=f(0`oh5e|}L4 z$F?DtBK|@-;3FpT??WR z@o?wi9N|!oecCTc#6InpL^ZssI|B*F41rfh=mzT9R)?@f!@yvz^IY3di@^2Fddv*h zDhMlLpDXAwSEngRxY{Mma7N2xpDW|jpDR^i>~p0mVV^5&tVWgVvAd`p>o0224V2o( zLx=5i;}o|*$_&mj&IaarEuNy(puow`3Klz#4bH{^uE|%~%uI&0ZMI{X^Q*ocK5?lH z3OgWy8Dm6d@Afs!yEz-jHF<$A>eI4@`LmJm;YV18WUL^}EJwoC*PX_~LE$1K7!tS) zXJByPs$iDOFWDz<1@b@wLkW+J-AEZ2AsS+~)=DN2xb|UJt*l{&3mqoXuXl{~55Gxh zx!Tb$r@$Q`<6xiOa7oXNQ^KtTnc+xqM&QbZ6>uVP1P&gIZ1YNHzKMj9fxN0$>lzAc zkZ^nuHY1rKGdCc4ei7#HLV_KER|7TzfAU!+*AFZMC}iL8m4gpH@rQbegmrfwy0Z!i zQ%P`V_Q`}7kfPw6l{L)p{00dW!Clj0PvpT7FEi2BmX*x#G7}@&Vyqz)I6Tgnzb459 zT_agTc*TfnxN0#OtRa4NrZw}tIOGz_@k~WR_Xu1e(cG;o{m?Q|6xziek2BV$Nfi?F z#8p-$#*qTqP6>Ys^lFEBkDmgj@C`UJ4qpHB)ox5TFZW+@SwGp(rp-}gUlkrPn~B>1 zpSoC2nKGM z9+$qROs!>b{GL4Ew6U#z<}k*BTZ>#;^!Fa7RtSPMe2>t3g5)5*es?&B;8!mpTS2 zYA7w2rcWDcD6K#O0~KgxoNhB@eSIB8bRX4Ic>r*-aN?%-=33jUXPbHgfu|r&s8Q&m zwux{-mofece4yD;$jbz>iS+MK!z?XhR=61fg{wN&dy9FI^ zD;F#;H@~S>n1wCS%{H#rg8@Tb)>ngsjlFDyY*QpIIB1MnR>e*raAs7(+3AT?6uUfe zS24VLK~)wGL5g4A`0JP0FftR|vpllFvhXe3x=U{fYMEk3cG8qwF7`F2mMKO75hhka z!2=TJ8|!+fmI)`dZ!`9^$gbW^pA2c`E&_L%z=9=a*@!r znRgs}Zj_$lxaDcyG6-2!Ylc@wrsN8;&%O)E7r~O))lp=M`%Iah{E${onOcFOm@+lb zu?Il$-NdTDs@G7MR;G4+>}iihbF@K3A*=FAJKoQjGBp8FNULo~`%HKEh)QCIbuy%> zu7CY}#g(bCrj-X=vRlIe77T3ea*a8zYJNKfO-)6bjl{FjZ~nNv3OXJve&cTBtiOiz zW=zi!`mwP4eq)|#I}(TFH-2n0@!lg>O26?Ffaw$@u8Y%X?bHDlr8X71b}9DG->%v8gE6(cw)nFOf z8aS4bmSh>3T?~ehBb#J|nT?R?)uc&=s79EJ8pfDLS~LTzK||1tke4Jnq^x;nh`Pl_ zKyYf4jO@%pFcFM8aAvfT9aI+&E@S=1gUNLelD(jp)hR=+9aPadAt(&MY2ZB#amspz zQFEg<86Pd9yWY*|jMbLBW%8YlLzQV%8VmI+b1>y4NEiR4=c;aDakmj z4U{G9PexwUCcE)SP&~{aEz8kqMwPc5y$2XL8e~RSuOKH!6ulWv$rR-Xh#sz3;g~?) zaHeTSl`B_-;JkqM-01AVDRzjm!wy3}pUe}EQRO99FU?_61BWC|`E5PQkvl|1@_0S{ z-JUq*(Kx-xmMRgaY|oDor`#jjk|*kP79<$AuORsa_-QiFw8rnN*T^HP_-pkxMe}mM zdi&FQ6}GFlx75==BmM35^xM?H-RhYmNqH26DxCAo=z%n!$|IgnC9}xy}mG#(b20{@geqj zuPm=gW7}CNM}nRX+(%BOek7wkoIQ9DEW^=z&`6XyxQWDGytF*)J2YP6tx7TF#2oDW zI1k~FHN})kR7~k&sw?vg6Dyq&^_HMJO}wi=nFm0y8; z$}dz?AYIUhv+Vy%JY{;hloP0J!+G5+3rgltiUL1mf(8RM1_t%${m+U97D z)1iG)TG?%0FW42c7tNan&V+wv+2UT^%FDXV=y4c5a~Djl=!Q$XBW6!sI0KHU3#ZRM z0+%<7dzW^b*JWl|PPbVzmP}nZvs*zlMY=_%u z^mEPtvcEV|_<0osd$dKP23@VDfYu}-dS$Ac!D@hoFy(3SBYnee20$Z zH;7k@cZrXQ?~9+3*tVaGUy}%XNz@a?lP=onVto>Rn@iK1$$n6LPJB_cc`s4k=Dh^Jmj633 zjCUrupQMU5|0Vim^IpQwcPf~E5Q#FKNu(bpe_!!P`Hz-8T0DkCxs#NBvizp2f_ls4 zuaf_C(dNZOx%Eo7c`=dyYNcN<|J@|=JuG{_`YPz}`^vXd`MxJn-w)!?^4CLN`s<6$ zNgQXUr-F96%imM%L&85m_7HIliE7u9E)@F_>r5^i)v(a^?G- z(r*^;kpCX>5&5@@e~|xW@io!r-^BXb{F~r+%5QoqusPQu$0I7%BhiogBHy`XI^Vw~ zgZVkTDcy8ckbi*Ehlry@(^EmY6J(c&Gf0#(eHHLj`2&5GRZ2gT#Q0yT^lFi>^s+xU zh_{P(i#D$(%59bXl=u>f_Ffa;5!}b|h^xgjNz`+$xJleXV*G9=QT}f60r|JeeoB0aL_M!5{Zsir7rz&O5WR+e zy(wY_iT0Y2sHcxOio`KERXk06P<&Pl<2wxVH5U1%F>Nla50{%pG-1T%F!FmM)9sNz z*ghY1W^s#ny?CQ|hj@?pu=u$6jQE21k+@U* zTKrD@S@ifl1?!tGW{OS3<|1crV7|k}B5|-dLL4LVom1vNL7XP?rxNrp6<3IyEQtPd zM9u<1`*!hu@gea^@mcXt;+rCWUcvI8h+m1{ih*9s&$6TZ-h}+=qD}S%yNT>JqJ5u( z|1jBo#erh6$k{1a-!0-j;sfGiqJ57;zCXx*Nqkd$SNuf$O#DvVBjV*UOCbkkW zOP%FAL=5y8V{pu^HqHs=7OKTj+Wj}&c|Ii!!1JyD!4&Jq`k%fz}m zE1TpG^i^yMEYy3e{11zPzDiwPl@FBuk@$_cTa5C42I@-}v&EKTXE9IgCmtz|632;k zbyYa05bHlpJV(4hyj#3q4D?Z+ko~;4UHp^yruc#Qk@&gzwYW$8n;7Q(7xX7ptS>ea zTZnDM!^I=SiQ@4h=R#tA%f!>fGsO$UKsV(w*_*{cKjnJaw}^L$oL7nUzbbOVF4}>9 z%BQkF7j5c3qzC#bKg%EJr=;UrmE|+VCSr3jN94R+%vU517DtF<#A8Lfe}(+hWOMQ@ zmY*k{DprciMa~Dse7_fO7w;Ay6dx6z5jn>a%e^YTA^uqm^i#f&9q6an{VtUIS$@0k z1>5d>fsJ^d2h0|8#9XnP*hB0i7K)t9isfgCc3%tjLfO9&13i_qWuGrzEM6{d5w8_* z7H=2t6CV_x5T6lW5?>YH75^;m6u%HT^A`JWdck0G*{#LSVxHJfJW?zc1AUfpvhDsB z>N`vJdE%vFwRpAoTk#I@9`PaZG4WaP58|8RyW&UUPSNgTp&xr>yS$GB+jN4#4B1&C zCK|Eyw&KB}-Pc0?p0az3{YBFYM*2wEV@1;qhW|v_oWqRmpCO(nUL;;BR*Tn)H;8sW z3+3;Z{iqn|zq}xOhZyL;*!?Y(`$YcF#6UNAk8IAT#{P8{1O1mnWfzJ?;xIAL2c95% zk~mc?745zj>R%|^bb?`@F8e$&xUW?$yGFG8S;&98?EA%s#3w|~1IG2(E(Z6tI5!;q zUy8d$Od)RmKo>Yg_igOH74qlEu6y5#lgP2YG2*eJ-LHawn(RPlhVy_if1od8_orZ= zEB`w2Vv*C&G5;;1-H(E8_oKi+$RFI7;@ou1zgw)UGh_FckZ$*vz`A<9gLPkKs95*@ z(h2gHh^L4P#1-Od@gi}9c#U|yc&m7)_<;DZ80hsrBYTJViujiJp2(T@xc<0TZx=ykLf)`POwM2Smca)v`a+0e+1j^AAy`1kLl-$>%~h%PLjv;JH>~^$Hiwv z&ez3!cE1RGOZFb|Z(=*%-$DApVmA`kI)$=}M9!Yae8-5BN#x`FdGs$3SBYnc=aI(?YG4*#J`H1OpWO&qTP>z-AXnmzhin2k<;GME*3e# z9qkiD&T&V(Ok6Fl5jn{n({B(tl^yMe#BC(jlatxe|0j`C*3te<CvWJQz#4+Loaf&!YoGs23E5+sFD)9_) zt+-LVOssp~@>=^DGw(~JL-77U>+2jM^S;g*>#b@MTe%OMEd z&;MS&eB`OyE`RS7EMY~ug7})}6v^H^5O3uo-V}j(7}(xugrE;I6Zubmy zxC}cc*Mt6`-Q|b}We|1l@9sD`jA#kcDq$zr_wDq=xZvwfyuOPN56ZBL*HIs5KMIy0 zdLA6f^@V3R`_-tr3i*OEtmA8J$oFx-C0K&AE8s}3?~GD^J8^yMBLwSvGvX}6{ejC% zeH>>>o%)!5A3}1zf+Bxf3b<`y8p9K!Iq~m?qQt&KAKT^f7(#OY&PV@({ffIy(7%@u z$7U}BZ26>U-(!Srav_6bg?6g}Xcx|G#Bo_*^|5}onY0@@ld=C5!51t+eYgbLC*NlD z?}H!{8072Tqjy2ioWv5>sDjhiqVoUu$j?9Qu)}h43i=fE>SfvgzDCvDldZvDXjEN% z+o(1f#SPcJUAug3&gBQyv@RYtxaZ)@2ReWK!|Lk>t}QP5>(ZY$#y@EZdpIuX%`d-1FC>RC9U>FR6q4(UwsTXw(a(=oa zW7Ffi29`U!9(OW!ZOv#{-3aPYu?<<zI?1W)%DlA{pxMVtWMj|s5*5+gX)wGDb*RKDwV!|EmWmOf90ej z)N46=-0T-V4d3{}rw&5sMk-AmzWVLjv)4w~z5Qv(eI05}uh)jBoLQXqb!u9ycyVK-d-_}=FSw9Ht0N6WA`=K?tb(TI!h7`-!Ngu6EN>(taCJ2N6r?0t2> zdBsuad|h1}UH5N0vNokuHyT`j(`Ci6YNyMD?daF6J1~}gYEviosSS_lvnQI-r#94T z>)ti9(DE$wZ{pUyXH3L;O+?Rz)Vp%)-c>`ehC{aQU47$k@AS)u^84%wPlh&A(W84$ z56aC#4#dN#!$F+&;Re!`ZXW8pFdL?pJqUBlJthVs1$M>Fo zBS(-u*jjJU&H;noujhSJ->bf3z|J89+;8f;gLb-u(l1Y0mv%YJ)tgeUIJM_r>!oc- ztsc1ZsDYz*zL6jLrhaJs9Ys5jE^_-h_yRd_r!#Q)lvLfQIXQ-8pAJU~7e z+xgLBiw9#r>sfqkZTN)Awc%5;iklZdvG+;WEesXcEBeSV~W|29Ur&bl=X3!;#I}-+hi4YC~mmn(2t;YmH*1e&LhKly=sSc z*nI?%j0J+-dk*yJ)$>4{w)k<@voWX+U!ylg2Y#m*xk!7gHyAquV&uQL?<--xY zyy1A%3xTfH2)I1TW)g=Qm!+IA4p8^l7w)@d)!2Hogq;P->V@ioC1w4|-QW zz!eGe#2I}NnOyJp=o9p=*iEk%|Dbopc*?a%rQTI<7^ZhM5@phwql3`9YQy+Xs1bTs z^gHQ8@b5&#>M_6cuJ~j-HVOZrcXch?AxIYSSG>@>q8tMCuDmv^r%?Y~9fIDX5WpSA23EoBk8cnLB#5OW{l&u)-Pzg!!yfmm1MwpE7S)$M4_^sXvdyN&lr4H@S)ozI??ME#!O=Y#C`)U=hBni^xrpm)W= zlHL_7PQMWU7}NsfcVIy8sx`Vsy{pGz#`x?PdRL6Ip)1(!B|$^jJVUrEypQ&%cSU&- z>0POS^sdw~>0S9&YOI|7xuhGnSXVamT-p#b<9b(qLvg(;e+A-t zSAM&Nv0_&B#|B4R*`nC(AoQ+IFf*=qh z_gcw^san6BYO^40(w_| z`K)aID1~}g-{XpsdRK3AM4)%&r{`y%L>qcnz8+PtZ2oAUdRKmWpX@ODNWCix+EDMR z04qVgEB{ndl+BkMsCVV(ADsPL><`qt^3#WAU(R&sUD?C5_9L?SFq?W;e*Q7puhNFz z6$giUSNw53^{(v4;_WA8^SGkk6%QrTyGmgPp?Ae&#PqJdV2jYZIt)EDy{mp)CFosM zf*$p*_``ncT@ADxrgz0d!QV(fqrs$&WF|X@jdT}rIvxO^!lbNp1>3V8 zlKlF(+a@xhd_Ej@_UB$`2Q&1phM<8{0vjiFexy?G>S?S@vs@&Y-qpQ`WZSs}dRH`X zjAviL5rW>8KZ4=xwj2=XU1^U%i(K(YnAJDC5%rqh6>nT+H{#AxnE`rNi_HPOD{eCCU9krq^{#GY4(MI6 zO4GZlWt-5u@*U8-x_}20^samd^sfHGwSeB0?||ObV=Mx_E8hXVt6ALlpm*iBf*E_# zuS50hm5nL%u4uDUW<&3aHXogv9q3)%4oCKSq)_jQ2FLsejv4f>9y1$yS3D`wu%ghr z;>O{DB-_`!`W}v!JnK;JiW|2je{e#*E4J#lAH|Vkg`jtpi!9K)qD#6~Ja1tKqoNg* z<1i+zTpoPEu~2A!ip!;Q9~_5>)djt)1zZE@U9kq}UBzfZ?`n#fp>TK#9Jn642F2R& zXp6Z0*(K;*@!@#eX6R^D4uwgb9QM`CvES%9t*KB&y{nbT<+=y?#X^;?_YE95=OL@p zb~N%-wdIe-R<`{O+F8-|V7QmJeG~rQv@O7DEOSzLt%ljpBKM8eB0VJra)Le>-;@y6*PNaM?N+ZWk`@OSosyeh}BTut5Q`j)Sup zq5VRvlSH$A5BqBRhB04%%l9Gdcg%->63uFXu4W;$e-@o`iyCxAeJ8>`j=me|8_;ko zvag1{g1%0yZ=m_Ok6lIIXUsRq%JS!tPtf;0eS^(chE?RuPr2Rj&pj%OZQO_GTKdXZ z-%#^GRoLNcVY!Rx8|M2E{WC&tIm-^O-xg*64OL%?(4i8_QAgKr2v>dVUMUD2mcli{ zTt~qigpkWO<=l~39I08b`2tg}iExcF-(|2V*43e`(s4(ds}#G%ScDE`OC5KN^@BeP z;ZH;khP2jLTl)@>)EaA&S_feR#Sn5Y;X03P#_{57LpRcQG`Gn(D^ZCaoP?0ufxhvL zxnbMkb|7DM$*tu2O||tuS8`t}`@AoNwqm&3rBC+X~;k2puY+vvsVk^x=5g z$~PoBRQ80c5r<|r%xQEjMXpJf>sFY2-h0TS=;?OU&~YVu-ra3;FC5#D@;E}r<=hN% zz7EHq5S&Ba!@qA)rc-j6PRV(lL;7IIn<2NKC*QBv&m+S*gmd)`W;0fg+&{wc0}EPx z@w`tXZ)H610=EVG*$B7x_%?*!PdN{VqX&Z1xjt@q^5#6&42%0#2G_bvJ9wW%`ZEY! znb55}Jb!`pXO?pESS%OC!uJ1Q#N2l?z6gr)t%F*G?##kOE8ZA4+xXsrTJ6t5P7X}> zj#GQo-sf;GS|_ApxIFPp>mo~yenYd(wZf_D-!OhoAN4h+6*P)1`1 zjI$6~gV41PD$GB~?gQIe7h6UA)OA0}ye?>eGqP@Cb|zT+_rSUf0c*|nC!&~V|ED14 zewM{oEvygEArqeyTOU3}IQ+kg zvA<>U;dc*KXcfH)>vaUH=qp6NK!_*6r0)*~CISrN7$a*}hjV}_rDQ?z-L5;&u<|tOefuD{DUv;n=D-l_Y(4D1O zPBr%A!Eg)fan@om-847zTh_*rzX199OuH*nY}BuZbsYlEKwP&wP%iA;z;X@Tto}%_ z_2T;!571yQUPa_(8eFekh*0aRE6W5u;Ah=7obp2UDTT99N;$Ih_yX=O@8e%4LIy(D zEOwhRXlR~=wxdwGGn<{ycT;ZIr%*?vAIw5bR-po}E58o7_CKGo32x>mC}`^&$i;PM z9;VtlPev`rBcM^1r$6l6#zv2IGjot&Wlu$90YX=%Sh@3Hor8ca$wRM~mE-?H1ot>M zYatSC7u|x$l{9$#KY+-6Gq#W{NAm4{a;Oq1V?z~|z6d|ie^teUqA81<9(dcooyt4CpU3Ay=zF)N>!qO^efrbf z?Pi$KircEz&EO}`;ifY7gPTSJmo@y{@B2Gucm=v_bb8!T{0g8<#tQs0uc=JmarmV4 zK1ylpzKI$WR8j~2l#<3Xv)_T&k~{GFJ{@=?B~r@{^mpCk`4wg;by`Yr|QKYG!if z#S2OCOvSp_!lyba%c=DWWYM?=hbHNz9Tp@&iZEF(Eyq;Y z`s}NgcDRPbRvl-Z4SrfA0e4OrT70wCDzJ3oI0EpwGJZ{ z2$WbO`9;nWcyig_(h*L`VGy?xvYi}8OxK6m2m?lm|>J(B2>f37~fcKq6?fV99>*l!$=tdN)XF^f5;>v zR{2J_h7lQP14G}H!|xnV@?_2u*+bhV$0ZqJp1k`woCZizYuBI?Xt+>%;!udcsj&h8m(dEc;5)uFfz?ILN$z3 zAYlI`mizwHnlli&(EO8$&E{XevWAfxd}DbHBe(g+viMn;{eaIFjGXP)Jf9(s#sAOs z#a;k2WV;>jRHQps#?OSb`Ar@>+}bKe_{}%!oU|c)%!V+(z;cJOL`J?34DKg+2$sUF z?r&(+!AJ!{)S0*;eC&oW<2omX3!Hg1YvQEd$E&fndM%3frf?;@Sr)iA9Rp)t~bnaULI7!Bj8iIVhl_ekz7hms3N z8Ea+-D_=zCRt5O(IHKG!ixKc4o7mOHTS1lO9h*xm^W~4^24H zpudsBSgd*4c;6oXJ0jaE1nl*}DTez8w=dg*kPk5i0Rlha8b-K9;U`|T=s3bZ;vqf7 z2C-HWTa2B?zE3cC&hq6ojBsngPw+zk*B%uBgQ6U8QyL6btIk>3j)+D;!oiRJRy!i1uCQ zB!b6(kQ5vkSkoJ-(6B9GWOdPD6vGLNKv9#e;%A?Kn{_NfeG8P_QpJeBBaaPsWE(r4 zp;{n7@`vz0qM%?Ed_-YYC@hv|A5&aEjvV*w{?^?I1W!dCK5=V;eVBO|x2XjnRTZoQ zwy9PC;11*O@M8ieJlr>Mp^k6oi#WS&iMAeS+YGKiJA~kr&Nyemutctbf4P7<8Sz)a|8xmf!E*k4>%a#a zXd7GLz~jz)p;71f4dD|ugc*OpY>X*7AM9p9I{VMD3+#WdZOU}{&kjyQ1YfFny~YO| zh_c*G+&%0P0@=9M3{#Lk4WT}?q4p67J0H#~{lY;#zsO_t;9tm2`0VRG%2ylF@kCowCR?EhI*uiN z5Zb*ebKxIP8=TXs8A1z$b_hIK1Pc#*hJgq?B7-IH1;=7=#0Tljo1FGM?CnYAry$P2 zM_4>Mf@KrpS0eE8fICC5FwSrf0=I3j@H6uagtHMYL|BW!PlRCEUs~{q!Jklbn==Fp zZ-d={a1+8U2thjc0ES=*^4tO6JqY|k$b$%vBCt%|{H%+41OLm2bB_v^pzM?IJ&W)> zLXbDPUG7ob_9GDZy(C!pfy6KYfgfQN3ah}=5ICw_!8}zSX$^`l4PZm z|Hn&`&0kznHg#deoT+n5?DfkYhyFTb$+kK8nZWQ!BQJY6)O_aTFa{}|sCP(;nO4A z*B45OE{QZmrmQ>@Q2IMjlPFr^=Hzi<8!<@xP`nHBLKHBH7nhb1D{cP^Z{4hsrcF@= z^om+XPsl!@Nu++XMI-`2vqB0H!Q$HVk2Hw7lomSFbd+*(hDXx9C2O%-X?aj|TEv#T z%)ErO*dAZ#3gT6E|IO-xd63(F1 z7*v!Nx!t-&VpwTxj*}sH)yn%qtw2HRj0^~sc|Vrt1>$AcWap{I&;4xO!^n4fh6}N* zsP}U@wlnHSwhJZlwbKN*nl>2_B%C8PuTPb5Vvuk_AWHU?QczK5)LXsK&4Ip{=lvWj zjE)X6uaWlGzEWstH;_VmU6u5-5}DrRko8K7qPLJqd#z5|l?&Zgxt)=miw2pkgJpY9 z+2W0EP}kp8LNq7J>O0z=&R>#wXtdA-K8D&`M3?azI8x`Ae+ICc1= z_JA+6=UrNb(-MyP&+*Zju7f_aqnDKjd9#}^yq%~T#=*_#6Nwc>GK#UnhoZVx-fHds z{sDz;`-6^)pByyaq_M>Lknp39gda1I(70(6e|L&`UtkMocBDq5ZQDg|p1*C+WyC*5 zt6Xj`i>Ku^jkG|UIAugyy0oBQJq5X*SYSfzr z=`?N~)_`Mbu?u0d7GC;rs+*y<;s1VZs9WOz0l3cCEib7mm(9j2H}&o0&79(mAiBazRsPeOL>iiiPX?39F z6ld;&`LlBD-=g^xrYoJ1V||@k4l&w!r6toAp`McR;$b6(V3W-#cglv%hp^GG`P4M> zy}?#5TTniy(t+?98(J`PW_f9a<7=Oll+G(%IIDF2^rcSO=tUKYePP0o@e@jl2Mil= z%(x-!Kl{2zP0$W^%giyf3<>eVcwfd38+Ft%BL-k!Ie?@a z<;@aD@6uA+XEcCwN=wlwc8aNU6X%pg^B0wuVqE8!E^$hxFRs82hq0Pk$#YD}+{1cJ z^-n$1=AKeMXIZIpYR?`z7g$X=am`&=I;&(6Iy7#`cz;jW=M08|wkyrI-ERrHhw?M$ zEG(}WHh)HGCC@fJ3s~ih@&zTcaazPUl?}!QDPd1fu|DzS7q8TggI}4p8_w_8X#RGL zca+=lAC+_S<@QG4bOmU-lxp#EGfb3b~V)0CIy?BGj`?#$4VevWf6LGf~#XV5wLhMrf6DmNVmDOLDPx@zg4=6a~bQgIkLeV*?q-g68p+m zajCdMJdH%T3uN;**X-XV@?RzUI`J;iG~kf$DcR47e-=L$KO<59ZrOW92R{1ik*KG> z*jRp>D;xgy@^_Tq=E{cO=E?>O9tijpNGZ#76lIO21UxOu~PiY}0x}xw~ki+ymmn;vban zC6O;kGvAxyhw_`&8|wK+{yikxNy7`aT)&vukc7Xb?6zWO67}XQy-5DS;z)6fcHOzR7toJ-7l}(n(`rMx3ssJTM^h@Z><4T*k* z@m+}hNfl!x{7q%I5Ic})zl+#iEK>Slailm_Gqr4$;+JBr_@fv>8I}t) z^Ri@{W&{QEcbx;uxR&B5PwGYcJXC#ulTc=!uuVF*Ap9xO~txed0pkt z7XytvP8-O228%<*v7+6NK{}^=WWFil9C4nwSX?HaE}kWF0xOn(MC25)v;$4Ow`9L3 za(*qQe;yAoFoDL9&;4gg8JPD;^_G6-&ia#YG|~;$?kn z#C77uA}7#f`rTq(ZM|Lce<^Y{FXrb=gJcV_jo3l#B<72~L{9z1az~4Srrt!^oCb{P zr-+;ajP_>n8u5DZR`E{p0r6q+De*b+CGl19ZSj3^r}%}qTih#pxK?9-Qp8Nr?uWtO zQg&PMV6n5MJRm>L;7mpAF&Ap+rCy0~85^=gXS1c1(h^xi3#q-5W z#cGk0zp;N$h&x2PPYC~8vfmRw5kC{Z6ZeR9we=d{y8-KOBDN9RiFsmyc({0kI7}QV za$-8xw_H43JWE_F+I>UhtCnr|4`JJVL+~c~?fxNbyMG8iD*rZdhxm&4w)npIiTIiL zow!GIdH)RcM#Mm4uYqh%s>k$$MNX(kd$d?0P8UxR7l^+RtHiU!^TZ8ept*OA?CZr_ z#XH4+6CV-nJ|X(^qU=A3Z;G7kkNu5_t;K`HKr=5-c3&~j%(MG|C~x-x!3j#AB+d|L zi>Hc<#FgS{;)UXRG0@PfkhfIH4@phb% zGZE6x7TbvJL{3V`^drR4;&^e17--mCA^R$k6Be@ki{h&!J}WtGA^o3*JCv=@tE|9YVGJURCPNE;2 z7m)rlMZ2E`+wNz9!F{W{mCi{3ng3al6Z_GASLED&v^gmr$vOMTG?CNx(QYqt=04he zM7u8qd!%f;F9my+?BKrCa@iM%>qNUhh4tdhd#v|Hk#p?PepKW%d$ivWIny5PFGWtG zN4ufeoJ75xCy)NFVo&)8$__N-?0ysSb2dEYpCXz5Z(;e+VQx2ECRu6U)^8-eFeKO)Q%81jcG02D8QD*0exnf7LtH|F*u)RXDNE|E< z6-S7Z#L40mafUcsoGVs}%f(gV8RA-Tqj;IPS-e5KNxV(GOMFz^CO$1bFK!oK7T*&; z6h9F^6TcF_6>G&GMgFja;}sUO#Kt1ujbnN%F-PQka`bl;yNZ3pLa|63EDjY%h-1VF z;v{jhI9r@6@_jkBTOn48eC3n=v&Hkpwc;ia(0ebswrRw+}w6ng!b_uYBpeimB6}NmsGZ=j+gpb+9= zIHzIkx$)9wV^gTQAG+oeBfcNOBv_1%Yo z%7HIff;65tlj|EX)BnvH>%&)sczqiX56U3wyoUNxacl%jkaiIq$@NWUeOO=ChfCCW zeb*r#ltI*aufTDR<$!4k(yoG?T;JR|{v^lw zEr8T5L)!*sv#@)vh+R)rLJD7zIOM z7<9o^eQ8MYXr_zhWPNP=<~>eMi&c?LZr_yc zt@gOBj$7q+4j~rmx@pz0;=aYc%3NBt_ceZ4czDUqjhSh?2Doju7qlL|^TO27uG9?o z>r|)Vo^WAKZE9h|JsubZLtq%hi*dD~!f?T~AyChAcJ6R@{lP6B-1sXmoVooH=(g2c zHN8y=Vs6gxRc@D7k6f}Rlz-kTch_JyXuE0k@y(l6yX(`Sd3RZA`nq~+ov(JU@~T^G zez&&v_BWkYP`OLp5ZblMi*ATir)+flg*TjA>|OpwZMY~M8hoJ*ZHwQ47M%k%yJuH9 z?cT1P{pi}_tm3A{=M=wH>twax>(0#G>z?iHtmn1;;f$X~?ex6%dmA|YW`}pyi?sdW zba?RA-rfcWy;U0?lks(GM(*Co%=UXDXXov0;w+zya+z1(k=lFU&dgA|y-gb4|FxU; z(vH;Xl*`k1c`1?V-`sgS*0XnQ>Sw)c!_W8L6P?_6_UYk3m}P_0Ddv*K7BEgGU=g zzrlU$Z&IA^@4&(HZB^0eou4#&sX^*DDXF1vQbMD5rVcIM8Jd~;ZB?qf>FwIoEyX(> zZ_v(EZ(wb>U!!7oeRR`?fmPqmxb^K%(+jwVq;F_O4Y_dF?P=9fl<2tX#8fEBrL?HN z#c4d)+ZD}NSG?lR7MB+lcPVz-jj0Xq8e1E_F>h~rJGbBN9jUvb-qhmy_y4g$_`R0U zfNQkZZU1Hi@0%1at=8=~Vo2)Oq11PGI5{y>iOVc5C~k52ZN>S;vp#NL94(#&-M5V5 zv<<628U%mm;x|5yuD|!=7S-374%~;(f#Wa0)A_vD4y&-c8Ig?VaFjm`$C%)VwnSuF zimR}2r))mZ_1q}$H+ydC`}m9sy^E6=B;fc_hQr|zKK=1hQ>Zx<2)~6>rXfp+zsHRM_4G-}t09HWvS&`L+&j2)V>KD+4s& z>_^6Uf)?^v$&DV1hWI26nr}RzQ}c}vbTOcuceTDf+~qH1q4~yv%4YQFI)Y-|Dk zLG#U?$i_9_{1(G8J`aKBn{TGZzCnY~eDlqW7@z*86}0rtK=Z8u>Vtw528s`n(<$t9 z5L~uyXq!(?sQJbjA!7a6_Tg!M1x~Dl_4Sn*juq1ECo?r>nmL6sGh!FAFGtACiZy3X z`^#(`;{$bQzWFsbi}82S(0udFR_8AauT7$M5Be$(GG~ez(Yo_@&g|*vwpVW|X*3MsQL-Wn= zS=bjuo0`VC^dN`CpN&!Tje{l4H&&d^*^wC3LL|H#1~lLJ7>Js0oMkF@CAawE28^?z zo7v4JK||O)-0QObguYVq4YN}Rnr|u~%{O&Sns2_98mnZ#?oZ<}3IV9t>ul-)nQ_gx zmDX}rYymSrsJ*yZES;NXtBn#h-+s^3Ct5#_Q4T@#?M7~zr&@n*W^T;%o}P_0MCU{8 zJH`gFq36=NnHkr7^Ban5zWFN<*L?H)To~gsBxt_%w6aC9$2cA@HyC7QT=UJZYH(~8 zH~Jgu^N3hFx6+&GU)cJNiS1!0-)T4ypyu0enE8W@rC2d&P{pp|8hx0_Bbb_RpR=LA zXlJA58#~0JP3#}{mL_NMAN|-aBau{}Nlp2*&DVV6=wzS6dZGE|uaJ|?AHh@e?K)e9 zaQ1ghhvu7ar)Ib13PbbFw==TGawVYo=9kaPZbloLZ||hBqm8p)W=Em<=BMXp^PwO$ z-@di;7aT@t zzTJkkYIX<`O!KV-)OL^TUZpDZ@wMPZpn0LzD-2$O!JMAAK+BCea*N2*fiNsF)K9R_-V$f zifNx7YUppraQ3rYA!xoaGd16Ou-DLhjB-+a3=`$V<}&9_l#pJ()Jt_n5ZPBI5H z-!fSPG~d_*(|o&)IiUH*Dopc@FRD=U&38caZ4nP9XukOlXuk2MBGi2I9ngHclHG*n zo9}?;+X(J^(0ub-!L6e73s60KWn&7>H`?r!+0cBWJwLDm&9}?p$UYA#)O@4CF+YUI zJ~ZEcXErq7cv7TcRYCKO8;1vyY+v*39XML9;mSkvjT^UR5yuLeZ*0|X|BIjyG~Y7O z3N+v7YUT1YV0$-qupi)wgn6J#3y$ju59J+wMYwcsrM@t&1JHb%%{74L8_#^ue2cPS zXub_K6BBnIhjd(z-HBptcpybwUOQ6rjW2byZIAp_IS*pcog4(m&G`-mQ13TzQS)sk za=9)v-&l;AZ+w>{XD#!#?S)3F+VaOvE8A9}*owBT;a=YME%<-awj)*pns4?SyH#%F zDwIpHBW{h`um<_+^XYC%n0v2O;8Lgp8VJDQiV^9NFrWEiWbnV8JC$qIC&OhQxD=sj zF7Ds(?YwIzBgd=#$@|U)_0`&GO#v$xvc${%vaPP2W7{= z?n57co#GBK-xshyLC8IUWd~(3-w3Qs3xwQb%-4)QULmYO=up`UqH*;(3jFN~FZgqL z)6*SNpR3yn`%M%f_fzvVrSERoHzH7&t=Kw8VYXruW^0amb~FFw>{4+v4o?JS_QIdb zAB(xgIrQ=U8NOp<5^zUZQv)+_`whV);D%bq`IL4CLhcDzBX?N+6qMi_8XiLK6!SHq zk54oCWHXnq*SW)5(#JOv_;fP&Wb++F-wxPMAefBZaI3BZuIO4Ln4;V8M$AX1>O@KQ_R6A>{HWSnkLc^tFIZp{v|Km@kLE?y$Qd9I_U}n2D9?xSB&< z=r*N7+hC*&MCf=HOUQWw9LFL!hunaFedA@0@XJ&oX$3+jDlmP%Lcs<=tHw zg+Z~~k>OSrYZerH4%RbPERU_7fnu)xKbx_?X7Y)#wfG(~@n`1UnT3hg>JRYL`o-@- zar(pd|9lqzF6(6$|1(nR-H7Aqu?2VfOm9Q zG5wzXU(1TW&*GD1tC&AEpNe1=S0b{Q1}nY*5k3es88a5Mim!%;j{|X2bUrfCAGZ6W zm<%VYinUh5eJ^s{jnL&n7|$c}EREGL-bdtJgs%ChqT3Ddgb_jrPz~b{Zn3WNKTmY7 z=Vm^_TDjGlBV;3V4^nLmd&1KL0sq+}&a3FgXIFGH+^pu<8LU@Bkz9;my`sF?2{hQN zg$QK`-Gf;ft!HP!vjzd{%AWD9Ue6f{)2;7jj%BUv)nrPpg@7J0`hb<= zf4&b)v9)VhmYelC1dg?h{(Fc}M9fD2J4C)g=pK|S;AT~gtjDw39%qgC>iAtyBX8lP zB3O-W5ot|>ZS+EfKlJa;(kvI$$Wf#1+5ab5V-q*)DD0LtYQs?GC|1I4c@iR%X>ioa z5jhp1J4>@%0k@|{i?-)Xf$3(unN_Tfqjfg&pNY_wDK=VH!`gzNJ!(73NtCdyo5f?x z-=mP@ZUldiLgZN*wnriIE<#s+s||X<58}Bvt$I!^yzT%u#ZHIN zmB|GMTeofZE;H=#|7!?tiJSE_+vQHO9J!Vu*d|?v$VD``Nq>vT zwFupVa@wT5ZbEl{LWYk~M<5dyT51Y%OVHhp=me9MG!Ei({=*F?bXW+oalMe%r)+F* zC)7JskH+B*(Wy|MP(6OU^)=bJzM(W4xF+J~R=+cufwFOQdb3%E-^4vM#rQ1rUVwHRKjS?fDt$~m?gd}F4F*KvUhuWsVDzLhig`O-jTP`-Ov#|(^jm>T z5$}nh9Q&l4#X5oVbJ556K3(Y2^-NOIUa{HH-TR#&c`)}29+pkJnkGNM7aME-upiCT2gue3I ze?rSGwQoItU2&j8r;Rdr(qZenue4jg{YkqO{-auLeDem9Y_HiXIO#B;f{;rV1qnP8 z?0@M9H|D@6nj*I^zs6V_1SAl-7M)1+Lh$o2*2faY5Nzte+HGtbA2FzKEWy?w%rSz5 z4}TNbq~Ffid_-A0yaa1zX6F6n!i!W)3{C|7A7^??er4m5J3Y>1U07ezRO0(qiPIwz z#}od@SjTew-VlDZv5j$opla30rNB771WyivOrKGoKzy5R01d6x{KOK zO)8O^R3f!b{y<}AA9o)NJ^GeG@~Z&04zZG-vCi=X=hTL}$Zb{8KCNnKY(aoP#cfrL zs1IX|SU(8-ushriC?9N5w!l$f?~sGw7Di))#w25(j+vp_vy#@(P+*GC)S(4JXFKTX5R>#TF=$K5v}3128WzI3BLPax_y3I@h^;*hie%52myYA zx9c%>L}vukA7aE88G*pv78t?U@nVdZKPW&jpuqAPMn3TU1n+Vn3-K9()yeI|y_{V` zcWpshe1sVf1{+hZrl#6(n?fB`=r|24mqg4gtN@xaExM4^=3EWOgLFE_5zkw6EWrS^ zv&tGqUiOV;HH^IF8_R1L`Or63)-dud0?t~*kG{XMhLMmB;8-F9!Pbxw-dlnZu3@B= zZ$xXjNy-qg7ZVJgvn*W02(PXnutsb*|B`SGBmO2jme}e0D{C0xYC_>{Sq&rHY9{x_ zh>VprjASC9T7s98R)UdszOlT9k!&Uo+{;`x!Lll&or*~^Q=@JnhYt9>In{uG-u&*<>A4>kOCzwYn;Yg2*|TSd1x}k z^U&b2gFHc7G#TP~Xnf}93HnU)$K*UbxKa_)@bfOUMU%H~KIVO4HX7U?kulgUBiQ92FSZ%ps}U$2_8{nw`AHl-_9Ws|IB1AbZg*T71)Cqj zV^uZW54f#yc@=DO3BCmzob@KgfQO_lxOt{n;zDK2mXNPr8%VJI7B=5-N2>&fI!FqJ z7+XR0IQ$yUjRbYJ5ORimOaJYB@87H(OT1>CK91mTnxQ#ZRl|sX#y>7`#>W8i{OzBO z*WFhYoQ*NG_nAH$&&WK#az%MgwYwS4c;XENoF%Jj7!B7`8-#{DM? z0Uy}}FSKlv2Wy8Ee}N-$l;p!2h=A(|f~QC{=p|j};2a&C2a)31by6j311;Jh$qI&B~AzVHNgiX`{S<}w^Fd){>5VQdTz0m8$&$l zM+tvD#}K2?CU*SfHiCM?@p}CutnL`DwF)N@kNZ)=uX_>^wYn#z0|)!j&cHNzwPz-; z2_K~RTkw}_a)&ixdUE~&H*E zxT%Vfwf@i&n=Cq>*n(hL7ijQS=pp-f%aXPCu8JE zoRi1#j9DH+KGRz;&6rIcyq?jcow_fCw9p3r@WL|$O?vlz89%JY#vCV1}2-tTD%d4m%Z&s%j*Oi2C=Wxqm5 zoVS8g6B2_Vh=#b=@Bo9>8DCjWET(VAl%%67oJPm~vZusTlJ1?jA)eIE_G{;h(upNR zF9Sa90&mh|z{ExhyUgXE_!Bvkobf?*O!Q745kZ|vPXH4-#h&F{yKn2s&iHx3ahc1{ z8Q%}X=GbDz<9lq_a{A6hKM#CL2|DPwEK{d4FGL4VcE8*#^fDxEmW0e6jZ&hpk`n1I%-SCwa*^lbrE!PI|JJ zyqQ?v<5uS}iGC%V@lBuf7%y=(=(#NVWZmKkXM6xWm$|kh{9?G>rvi(e`5eL?gbqq37Y@$+WW~aBqrdQUA1pkrFw8|LLkN~BNxo$NTKE|@ zBWytk7VeeYiQYrtb2$p0Y&+x&*IKxQ@ zJk|3ug{S*qN%nCA1`Fd1l?eQ#Iun5#H&}vg^d5X4B>DL{z!QHEzCxTI9LY=a_;$su zV9yzk9RHH`oAJL;+OIdJw8!qt_gv>qt(cuRn@8L9dF9Ysm^FPmOdM+^GfHPpg@Q>* z#nQ6Ua`?Ke92o^At9od>(AV;7ILV~-Ov%p*QByA$HF`^3NLE4EDyXW+ zcf!>p;fgeEasrzl2jxEWvB3I*ENg-+|B;?hU##J9>jzt}+u{Lw5zodoLenFgQi6-> zU-b@!;@8p~INOJ_w6J0PbSbD)YQu zZcg;{xFjGY`zUR;6CzoUh_{imCWLR;Q7NRM14?pwku?=Y!Ck6}YQTfoIg)JL>qKlmEUt{wLJH z!|Iv87LTmNT9|en^zed#fOucFwRwwQho9AN(DUwv9AJEXw^I)=>W#Eo(!9^yyh7xL z0N`^;0)RarH;J{6OaEchK-n+as2d}c2Bh#`k_Mok-&g+aE78Cex8Po`-A zHi22rdiy4Z-0q$nzCf`hMVm%RPvX^dfN>3zr1GY!DjQEv^lX-Xbs4LO3| zUe^Tj8hGc@-ATUT(W3)(zq6$7cS)6-Gl_@a=MMDmaBvhtaL;QnX%ffnH0LPUxpE0){!*Hl2LtLY;i;)PL_l+F03q{-lM)YZZyZGbyu2Ko;l{-^{@PRH z54wEbpI7F@kIkI6IDhV5iA-^MzL@tT^co@Gmk!-N3NLQP{|s*$H2cE1JrftVs{Dtg z`Xmw6yRuiw94P(#uMzJ1`zn19R_a3mBZ_y;Ua)APeH;hEX8&2SK2*MsMBl>Fa#JJo z`Rh{Zi!1b5r#IIh=897i4KP9-!v-uCFCpr z2MY7;e@2?#ICc&K)&zP-u#@IIp4m?@i>J7VxZ*+WmP85r(7P?`KY33LVE|6 z>ieIr&d2-E2h!%_O^^d<^G)(r{d%?eS|;Dg!8i3bunXfi%n~=znC;i7)prp3#rtU- ze`@s|&W>uyA`fr^#K#V#`EnuQi(47f7u416>uvtHI3Hg3Lsit_%SB@(Zc>;|1osKf z8`eO?+Ye@A8YqYQdmTvJKJ6@jAMr?Wu*iFztmin9cQk3w6;BnbL_P{<`UPUOxJA54 zyieRFz9jxh{8ao>+$*MFJz0Niv6DDjBCh@l-rx2l^H$h3$I{?3s z-Hx{mVRsk#3o_ax#mV9+B5z_c{T%T!@p|!I@d=SPkeQ!1G|6wpCfILiw-*aU(*uBi zjO;4$e6d=*UHnAcE!zD2D4&Z%i1qgr2a03GDdJ}FM)4W(HSuHdd(q~-N4+-BJva(? z(Adt2qRmGSdxh)^#4E&`#fQWf#J9!I#lML$?C`9=wb)IxdEnvalmphjI8R(DUL&@2c!Fp;eDKebZ906g zSIIt8wE4B+-yr*T@m}#EajR&$eE)~N^8l}+TG#)~ZrKS*2oTsP2pa-OjiCrZP(q6c zNJl|YLJ38w3DtvuVnIa(W1*~)`2H{Z6~*7AWOK0tiG3qq z>`Ef9>G2`oVA;dPQ%LxWWlt8T$v*MZ9Z-A6Z!WkpUtNY{}1xpJle2Rac<}OW|CO1!(<;J@`Y%o=ZQy?$X6h{ zmw1Bw!(@*TXNa>z)8Rw;^JFg-O@|Num9noD*NZm4Hu~|f>}}$cB+9)c`!&(#)rS8Q z*?YvVNcew{{jBL$a`Tjap8QM2 zOXXifBHudM8tAP#8Z{dcl=q;c=;!ZGv%KxE|&iS@nUhc(yte95!Z{R z*N6Hako^#e{yZW+BmeUvXA@xh`{GC9w@TkHa?(il+h!U7Gh~~NAM84`QP1IGj?#}5 z+sU6#Vmwcf|3vX5@f2~KI8mHJqTFoR^TqQ>w0p65nOLs$8^v4Y-yr@){>|cJ@;@U! zFTStzkHpVK&ZNNcI3WHc25=$G{zSy;B=Xt3=3oQ)n~+$aqm|xSJWl@OW%m_GnGDDTqvF^ULsyDavlYiUn!cNAM872ZxSCR(O=W^19!-NMSNE@T|cCMLL2p% zz90C5Z2YJ(e@LuNBL87xW3icdlxVts$mh?W-j#mT+g}_)V*JJ_zs;kL{8QwgE&qJ+ zJQC$ER{9$G%f(y84dP$K&Emr(+IyZvJ+H{#qx3ID)A>WbAbw*pU#iF%7ic#i(N9jg zKprW-uk+VI{(P~g(oY~!uj%`toay_4Nqk!bH6@qF=WrLPum6mJnXiua0} zN!0U@__X+$_%n%f=Hb~MyNCnC>EdnT{o+2+#Sc!F4~zKuX6@l;f)T51#NlPEE82rH z=vPzOEyT9s(c&x25U&!i71xRni`&Gf#qHv&;+x`5 zahJGP{7U>@{6Wm-?@g>nU9q8~(a+f;V2&z5bE zQ^V%dgDiKsSSH>oZV>Mk9}u^SkBM)I?}>aEiS_OgzY%@?z;yoZMS7N4SFA5K5u1yH z#9^ZS4oCSS*%L+kT@HVV>^b5R@j`LAc%^u)xK^~^@2F?J>`mf*;=|%L@o90pXutDO zo)3$0J--yc5q}VW7JVH-K1R&^{YCrT4|{~{QDU(;Su7Ffh<2X<<(9~{`vtI<%f3dm z`v>r^lYOhmDcIPLdqmDVN_(sLw76Y-O?*rIQ2a#vLfj|*ApR_JVn5cODrSk<;t^sa zv8Cwi402*TmOn=9F7_4&h(pAY;%VY|agsPwoGo&?E7t$6xJ&#@^mPF_IT`c$x`2Gn z$kt2D5bKDCi#9U`;z!EnOkgb6PV6Ff6MbF4zOsE?z>{SciQ~no;!M%k1zaHeeDNaD z*9E*%w%xBm{Liv)6*q`~5jTt5#3#fTM4RImaZbd>_1h_aD()4(6DvfQ_h}FhiritWWtVu9%E2KJLZP#hupx`D;Aeciwk*}iVz*|N_Omx{~8t3*y~ z#(vuUCvctY_2OOPed2@SqvDg|^CG7$W_`YHAZK-?-BQdIyNKPy0pbvGv^Y*I5$A|Y z#0$l%#ns|1qD|q5_U--{_^|xXioTBEd$KLdsp4pHnph$(5|@Zqh*yhM^#$#I9M@CnRrLhllK(w%ulSW{_vcVP&iiiQkzy;c zgP1RN7ki5X#3ABH@icLQc!oGroGmUC&lN8bFBeye*NU98kNxBfljK&>?jyo}PWBGb z*9Ck>_Ac==k@Nhqo+CugBT2it*j7AR>@M~e`-_9bk>Y9M8R9f?wm4rrPh2W47q1l8 zh~?t#;+^7O#LeP1@df%f&KrwRpXFi@09ASA0NxT(tX}sJE(K;5$m+Dee}(5Wf>ELWF{ zUqrj_iTbz6=FF5_KfBKfekA)-(e87?|E+A!TFLx5Vk_||v7_kg3U-&>TkJ0m5>FOS z741GJ>Ypgv?svkr`<>u?`Og;56PJoNinoYc#m7XuZ;5)|m;I^e>kC%Z6RgGicgXMS z3O114SZpEMeM{u)AUj{|CiWCLn*rl@15*Lc+ix-K$?%Tm&?9c zyj{Fo{ENt$L)reTqOVK%f$Y!3&&6-W{o>DJK=<`hMNTNsdN~a#Y4nrQbkkv?BGCp2YySBQ5161LsH1UJclpXlG8d{_1^@iXx&(e78G zyxpG!qr4vnau!swv)EniE%p}&i6h0+#PQ-Jak^M4E)W-sOT}eknRt!3R$M2p7w-}u z5Vwf_eaWX}`#Op*%YI9IPqh1zSl{nthjkw=RpiXB91s6KBxiM{-Cpb^_7ORSE7M1d zXNc28&f&`RC1Tb4i=3jB>34|_iVuq~h%bw~#Lq-d!OHT!-eQ*QY_Xo`>o5BE2@B*u zRU9pzD_$U)&LXa@IB6@}Su1jWR@!zS5Zpo=`8Z1}{V#|+#a*K5Eg~PMV`VcF;gpW_KPYm#Q`#?xobiV+FXA7l0SR6s3Jm(Ch|4flHgVJ6sa&l1GSBab-l=kf+ zem+_~IL(+JFyc0b5lt9z8Dgw@-!?9P6ERQhAm)o*#Xe$xagaDnEE30ylf)@v)%&`O zGx2k=Li|y5bRRS%M#Xf| zzaLy*c3kB1UfgbZVh6G6ec=N6dx?X@VIp75WIfsJ559Bj`u+MR>P&X>lqkm+kDWac zkM~ZP4v|WWj~P3*quJF2q{b_cii-;Q~BU% zlDOrBk}*?}36K8fj+r&9Wb)YAvrz3nu<&_A44K2@gG&bwiBAlpEsgNWe7KEiOVxZ# z<8mZI6ycBZ$@TS`>TM_1hr=;Z-$uk) zhWi7TQ*i?ASfxIu{}mxQ--=%NPG$iuOk;RTl-r5+uH1L%<2ZA93?aFH{n0;vzrrO& zqJOU1m%Q(@O)jK=tk7P-cHxX6UK4@svVOLiv>Q2F3O$(&xNY(4!{y{5 z`9`6CA1e>x=Y!5LMt!_RPAl)00bN7oGs~*|gy)>}*kw9ecqmdd^5DXqx zm|2#&V-qwG+b{0dAQiDdRx_wmx=?%E1U!pXTtQWd+Q+P#A&yj`0Q0ATPTk!eX);B6bdD~I< zz&$nlU$<%Cp7j3i^60*3wD+F$@Z$$x>wZaL$||?>4TUKy{`z9p>gbwUy{fNXS(v%T zX*FyI`ZbZ`mtPSbm0uC+pMM~do{tfH{NR#_Xn7*~chaK=&pQe0b`pBlJN^1c4=(PF zHSGQ9!E@H%e2-T?ke7cTH0ps0r(kPkxrxYuIzp(!LHvBgor&q!ySb=ueM~Kf@*b!N zU_F`2)|`2d99%LFIp?9}iH})rp^4iLE?LhJWDg##)^ktyo*z^Tep@}bW>fb)y}P^L zR(E^uaeG!<6Q*PWBNV~fJx6t~$vTz+#C!IFO?Qn9OxYNkFW_!iF<@pskGrCsf zEbmZ}v$JDGPTXz(_Sr|du~wJkfrFm1~dQ6_aQItXpc28_2v4rp7_@1*s{$7zUF zV}5B{o)0^t9X_CKxeo3C!j5Dz=sa<8JXFL*ud92K=jAPif<78%M@FfRmTY6R1&G?aKfz0|D7qM)2 znQ^BkuDCpH%lc>|gMSc0+mdmP`unW8e=1GWw)~9A18l`i+tQ@l2FpGV;&j)cvDV0K zs|;;R{*i6kmh)J2IwoyP&x&S@W4|`1+93;VOOu>@P-a5g@@i{2D}(d;K-;3*8Gq+miqOL)$XUKP_{bWSjw}K9gbpy+Ye^1FD3!Wp7JOXj^&>CA2NQ6-a1X zdhK@2IEPieT%(_rEy!RC(6&6)%!Ib3S5>c!rQGOmsn7j0p5*@Xc3K1o-f7rmwKn5gB&DyepGOFtsgBPw`{zY}B@7hgh_>eQZ)wZOPGz&EiNw+tOPhC-x2p1KO4k*(!u$FEAb2mYyAr&EOhB+tRbsV-fCZ(6;o- zXT@Gcqtv$i9#@LgwxrS`wJp8$yx1o0G0?X3v?n{n_}~h)Exq*o7$5MUwk4G#scl(< z^+DUxJCzi~I1>}KExr7`Vm(;wxySUP;5VKXj^h{ zsBJl!Hnc761q)~z^0=b5B@ZRjw&Wo}ZA%^_rfoT!4rp6;L=R2dlJBZe+j1UOHJGzA z96OA4Lff*3H;n4L?YZAk;ic#Jw_ z)VB0SFciC)>kn;9?Gb2^D;^H9`nuy$uW4KIrdNzlFHqZ(2CJ&e!G*S^XGdb4Idagp z9D&}Mwk0Dqky+jLv@K721eQ>{6}}v@MyL+LlAuYiL{Y zYl7OAAFn6~A`%mHmnR$D+{ zmYxIJmYlJa+LoRJ+Lj$SfY7$|9MHDx!y?eO^c>K(yoouWZRxf09JDQOLiOyGjVZJ( zX|q#iL)((}1-|WTTiy*vY&cS=ZApV;&h1QX%SX(Hwk1!BG^{FUTXN&@K$7igTYe8m zJ)U)_ZOM&WZw$u@+Lmn9Yo8L9RtVabe8dIXmUKzOlIJb#U^U?hhj^gZcX{yn$3j>0 zQ%E+A``{2ntS)F!p1?JLwk2zTwk7ZOQQNY}%s?n~4AOBuwjaG~z(T!?dHvs+;!C-Q6skqg66;qC@u@~8R&!-Tf@i)jJnaE3FpHE*o z^A%XWCt*KAA75&9yVraa*pKineSBcc?NQ@n)W>Vo+6ayLlAhbse7t7tOka$?Ugo1j z^~(r3eE8EXto{bd#t_|4-!1rXkI!QNI-^^i5OR3_a{HL?4A}kY+ezOES#0+tbd}Hj z<=n|W_cdQXbSniRhcfAIKl63QM$AEIGGm_O_P6TZh559(=0h{la*e~DGzOt5)F}tp zx;BA2#2JJ3pOfqesgwYi2vYz>#7r&AGf z4mV$Iu66fnxKo6X)6jhN=sO7eD}*NVAQd^Z`m=D&OvgzUp~<{~ z7+o*Ge3~w5Ob)Yxbuw@^M`$u11&3KdJ~+?eLDdjlU+5o?}Yrg?H+ry1{1uSn!+NC3j64q^kJq-`^Wd1nf>vK5 zFP}u-m&kj%TbKR391gx}<@HlezDsong42Tk^6~c%_Bkx>_B6ic)RO=8HA18zLMtY; zeg_`D@zfas?@F>5AIuKfXC1`c9cg@Gz>4x!r~wGM%)&$~eg-^~5Y%c*7P7nQ?i=aX z!*4|wA#yfCtGdW%#a6+(1_8y+#LrVc)-BP*cQQYPzvW7J??hw+4T>&4g~$^$7Q*1; z18*a=;zjLI&%>kk`6Dc3lYF{wrZ>PHMQfjLM}5uggOJbKPe)Q30@j-C_dv0refH-H zyqh_lMcIc&h%}_ZKJe**V`;Dt!w?yQkjug>=J$i|QqT_B?Lqg`Ouod_GKM0P5t&GX zudefzsPkz2g#2p|S%uJQ2D)_AiAdJ=;1A-U!_OiFcTYOsWU`fd7?CXqxqhOp*cdmW}hq+=ZbxSOnVV*#Zur6GleTw9}&L)l*_^_rWLc1n#5`xeokTR z%S;NzC^kfK|wssIFrj9QMtK+)snU&ex-!L&#-e7E^_G z1o7vV>nz1kx<91zfdLzKzCrZ?LMtZNkn^3Xg9wnKWIwJ)v5>PCrW_lru7}$yKh;&0}#WLzZTYgz>#91-m$tuL%@NQ(uFT=-pSYufz%3kxeA2iQG zTTm#?+gTd9;Rf(j7UEk~3s|VAvQWGGQ1Tu0={RI?vMa(rMKIP z^u0(w-AjiuA~FP^`hfJ=xa<9#%KK$gW;<;$r$b|vcaBcO2{!P(3l+utP({ZpacT|h zchk*y0UZfcxamBBcQO^lAKX+L_$udjTYe$OfGUb~206Z71yE6B1zs7bC|a5Pm+&1F z`~)r9Ho^U_d|dla%gej2SnM#z5vh<_2^!8vHCJmB(I}x$Ti} zcS^xO8NWHO)AY08umC%88y%qJh5G*-kDh+P=DPCl~)U-dh{Vf8xjswd#+ zb>LM`z_GJ+;MJ4?Nga4SC6#A0uLEx+ci_!KI`CFX_$GD$3XKnAof)Xm2(vA|&KUx? z{jOkRr9xxyQ0>OhzXcormjoMg-EQf=isq5&R46QnT+<`n#Wrp%F~Mq`tDR6wI*K{i zBPlSL>}w*G!DL_4WFIbIs=31>tn)~fPu6B^p6tWdX+ke?cw|Jik=0JF#)7yN+Sczx zE7pc{83h#8uQrK75?NHS+-i^xdAhi=DLU(qPO_E^tCEuLyM-lVlr@iMhedYSld9MmF9h zRyd4I;xP)1Mv}itEP>~XstZnQ_}&>r@Ola2T|@(m4klRo_hlEe zy^O@+79CD_#fK6*JTE@0EcIbyig?1yesXeaL&~dUw?Ba~&piLT_3{s@n!{fIa#lDi zwa&?M50*FN>AFa)&s@B4MZOSu1F=B6yp;#uG zDnx+t!YRO51lG0~T&6h59wCe0F>Az{Px|n-*ovsX#ZV7^{CEpmbg@5UJNSKv2XW6E zu*+{=45vBQC(6+Ft~6IHU&IJ6t|HFqWuf6^AzmYGK|oKIFJk0F-(ao$(PSydAi|dc z&0wSmA>y1=7CN~s#JC1!`63QP1BB!r(C&i}aR!xz2A72x=Lq>W*OVdI=174gT)5Xk5-TzIvCPlwO(2apu07+yf0Cz+Hyh82fjn6S=)%4Po(z)5U7R z%L4pwAG;{8IkcZdIjX$uhrkHY)rM_;sGJdwBmBfRiw+?Is1M3t0aNGe;~Amyq@5_r zabk!%rB1sh3vfGtRvto{@5u=y1diZaWVztuhz>x&ap4c9q8uwIECmvW5w3%pd-w{qaJMp${FeE84Jo8@y-SF7M3$I3IQdE zNeEVg5lRlg2$lQ#127hr`zHvLICSrx=QRG+-tGCgBY8W@h|0a&qCD2EJ^!FbtypPW zaFKB6K4BZ5yLdYUo>j>L1jz3YeGqV{M9LZAmkNwfIU}so4kAX*K)}I8lz9GV`B{iu zVE&Vc<>sHWu$+uK;c>=R_<>Ig1u%-}a0U@$ z5un()sGJdw3;e`l1YaPK@rw~KjKngF4kj)`K+hMIGqTeBLkW(ZB>engq*NWe{t`r2 zu~^^0*ARX%dkEp}i_oBAbH?SHGObGYIGlp)axxc4B)E4)l2tMGYC}d*k@x zAo#`aCncSlHY83>IM2E+I)%J;z*%2#GV<I1oYR^N!S5aZlhO!GUP+!qYEEw&*L`_J{Bx6rUPRxVm2*QKx@a^sk)!Rj{1@(K_&EF`C0V zczgA4jr(F`h&ZQ|g-$ICF@Cez7*llK-?jX7_Mc*f}Y3SK`!Iym-Okjmmk; z?P9Mm>tVCM%HvlRunV$tE%&HOXID75zK4jcEyl{9i;&clut)*$Ix zHtAY7k^-g8FZIE!~YtUOMqU6q-_>5Coe;Oot<8Wr1fzF z-2Zsli|ktut({))x;U{3LM}H!56kZT0PuTLnF6KI-*OH~I0ODw_OF}lh??0#(gqH? zY>se9RIH&S>H18yvdeJ$}vFugn|e?+K>-tZ9g7amRw zxd`0P{l)kBd$@lb`RUA?ob~|hElK6M^D+!W;6CRs+yECN_(SabIZ_NaAaKO|h2K*% z5N08qg|GmDXHb9ntu+4(dol8HBpLjL_fpEtSP{x~7?l&Xi*js0aE?tJ4* z47L4R`0W1^;j`&8W{sZN_Gru$j^p5eTk-5M$AzjQ3mzY&M@7kpFFXx5Z3y3A#8#SE{m>gG~+THzxA7*+96-qeGPxyJJTi1&Gq7+n=9tnOk(~ZL&3|^MmH8Rl8 z{5@)+$kbl-BGEkvtXUv6X_d6gOWgWRS|Yg#8f3PnmhCHL zOEh|(WXir&LL?qx^?~3grO*;XZ-dt_blVR_1&yt9Z+o4q<>{h9C~K`RQnpJqc&m7s z)f)_c1C=trzwlwR452(6_CRReaYGNJ0v4sPE)2xkAhz$FrddX{x|B#a9yjTc>fw5j zqk?i-R-15oUaS7a;c6|z=}r102UNvS&1`1QNy?mcl%H{IIK4xad^RSmv281)^wSVc zB-t_FfvUr`>xApOxG;el7j*N|CZMmu;7c|(^@BGpWZ#3qw-a_(?C!y}i(G8SolZPb z%&`pDiv(ZexS3#C{RoQTxI?b4UM^M<3BDuYHw?f!q@z(Te)(6cl=qvBG_sumh1OHn z3`g!Yi`>4f?+d)kn5N@9y*ZEe(%cObFupCQY=+Uz4X4$|$`*00`<;x~QSfGj)0-mN zmSZ{(=YaTWDACO1(YR^Sa_fZaax5Z!v3aUX?$ewxcFYFFCXQ zsGcVdJz?nRqdku5HFVIZK_%1AC>}Sfbky-Zdz!8$RCl1!GGltFr`1yGK+j_OnUm4) z-;mY$V|B4gSuuS1vC2PI6dOIQc;2iDPF3kJ=*mz#?0-TtY&6toN{eSXcyePlRJ^&(h?pcrT#%O zb!_F{JZ{pM66`n_{i)-}%>SeqAat<%;3}`F}#Kt8~)zl38)S>1LT3 zk$z&^qvy3V0mad!&~bti8+ti@%q%D>ViQjq>m>GhPh+pxHmpvalZ%V7c`%p2m?^U+ zPc0suBn1UwsN%Ue6U~{0y#nh!X5QTKI5SP@*kO#9ZS0gYO-^cN`?eYltLaP!&p8!O z96cND59vMB>+bAn>{s!4TLBcb%|31N^s%MRT&xPpqM7jK?{9bg8Z5L_6#F z-yr_h{ZA|4RsOO-gYX ztK9WZ6YcW$?ius>QwV*SGG<~a1_^r4DJ?F>s9>&$@%A0y4fmKS#oQD~!@%R1 zwBegJb<7mbIx%`SN6^8S*D>+t#}61DA2xmZl+rl9?c&`_rp9|u9a{_?=<#uU&5bKA zEuCIc8qaUjF0XBVo0%QjOdWH^^pY0w{M>fAZR2#dZP&Jaym?76j5XxyYY=De89!!F*gW2d}M9ZutK^>l>a)9~W&`QOp-nist5UsuD6Pux^4mG_<4|R7)0kv~Pg4?X+(iU6lt89`yXxd6$laWY;14E#^f-HEA_* zuZOJV&C5VL0-J9yalfEW7ameIVk!)y>3HGRUsKx1)LQ=b;xS@(k^j`Po)g7W#Uhda z%QC%GJV)ezv-Dpnt`awh4~UP6JH&UyJ>pj)|0`mBe8rWlCE9%Fu#cAAU7RS+5qW=* z<*pEK6*q|wi_eOmiF}uY<@i4($v?lyoP7I}}4_TR)8#COHd z#UI6V>{HC&M(iT?75N$%(|KQywE4I}n}-{;dAC8EXB*^gT;{7Twh_CE{lrtm$>Kbb zufeeVqv8kR*Wxc?CjK8{z9Yoe;skNFX!AuQ-&L}25^Wx6_#c=3s`#<^chTl?M!wqE z@!4Ke@o15+4${vDEXiVVws^jHwRns8fcUgHg--&b{Cv^oFNS@MY@4?j_G7YN5^Y{$ z_`i{T1ddJC(?&d2JW)JNoGP9zUMgNE-XT6DJ}?_2T;`QP>alQDU_?-Br_^oJqUD(#Y&<2Az zcLmU=3=-|tm0e$KB!6q!dE(LX7s&1%|-8 zzf<-m@e%QH@fGn6(dM^BJ$q&UApR_7pl@uahR8SA0vHpU{}yqZ_ZI0k?=5J0Uhwn9 zHJ0lo_9an{@2znhibR{&7Jk$3g3so$1+QQ_{A-lY=CMV6>uG}<6Zvu)(@m!f zJWc*F;uNKqkZ9*z`7aPJk>BRGMZ28)i|c(OiTZ9+y6JPl|B%x8MjG=yBfc!YF1|ye zz0XP1V>(^1Z5~^ci{K3`maj&_pDnwtm_wqRKd)^Y*?bF)a2(#VI7p&k*N} zXN%{OD0hK)wRo+#R@_LUo_ocI#79Ka;X=CUaDo1Ox34oD^?xdUA?_1hTmZ9PoA(yX zl+Cxu=&vU>6q}H!ueq2n9!Fw34Ioi&h}@ieseIt=}dt(uPpe!{2z&5ir#HZW5=|!={(RY8#Xh1viGcLs zvPX(z#R=kcu~b|j^4SfxyG&dzt`e^k?-1`69}*uCeO;y(W!vvI)cb+#pG23x$KbCg zHWWD*0sY5{daqbqjkLQ@XLgzD|;mxw(e$-Z&q=aR5yy!3J00oMWS5A45*LY8 z^^wZtzeZdu`ua$B$Tq!h)X!n&C1eF)gT?$Y718;D1Wt;BXB=cr}5ZemZd zzc@(bEGx`6QRK`jv@aKZ-KEvCtLiV^DgP$%VR4)Iw76Y-MKs-XwDW=NkHybLyZ?gp zgR*}SIm-+C*HmmR=82ufW5vFruhTSKwy)DPRyHS4V!b6ICs3k&ws?+ssc83mkj@!q zm~X52r1-4(ism}L!BG`7n2;>|`%r{cxWJI(Vh@5bUcA03p?y#?y&AEq|e!uv%xLxE7Moj;^$a#op zHx*lxI2Us^BKm#(qN?|GPE|fmJH&j`M9wfodx>~4iTXIt5dGJQoKlGPCXurW(SA;R zSNuS<`!z`aUiMEU>gD`FEN8mvAg2kU?duTvIzv6>=VU=lA0cukAlg&Ks`}`5-v#OA zO6O!h%)d>1nnXW1-4Ffmh<0BEw%u0&Ik6AZtBIW3hjv`#d_A;%eW60xeMQd2!}QT2 zr{ke*_e(&|$V2-Oy>i$$%Fo$$m~Qt)KwppiCHXm<4%7YnAYanPdi^B7-3LLs-S+_N z=zakw&|$eek#p$K?k(E=4A_%o+kFkx%NcN(&veDXi)h1-%OE3~wRFIU%VQ(H28}qp zj8%W{$K`J#=7}A|e6g!oAodamiNnMZ;wZ65952ogXNmK~1>#b1nYdiE|247RYh|w! zZxuI)4~SdDt>Rt8{#|SPH~s`nfST*wfLP_A^s>v^}9P=%o6#o2De{bvA!4= zn~0o+jrlr=`6A!jpua%uCH4{djt0{QiF{v!c9Fj@`>V1o4@-G*! z6jzGZinodz#Es&;;sfFq@hR~+@l^eu&*pgIoK;uj>iqX~PW(r!lB7odZwj2$!+2n* z?6?OG(QcrP;j^U?KA8`<4Q%Nk`d}KDBN3tqf0Qo|d8)RX{QgP^>0DYP;8N5nK;SZ} zz}tp(5N93+w$~5A?*pRF4s_rk?pgYapLRSP$@R@Dz&Rit=TrE3?(^&8R2+U8M4e~x zkjOZHrIOMnC&igB7Xx}V&ZYk1*HH{da=Y0lLO%rGRcx1jzukF=`(+Sy9>V~{8PVdW z&4Qg=-*=U$%};YTk-T5^3M+<@JRjnDdUsgkJgI>h}l zh&o$xajy#B8~);_@p+Nt`W_qYZ70@;)lSrR8{#a({ejE)j=1)(QXkXrMM%!K_t@Xo zH+e+)09(c%SGn)d!ExsD5JGbQo*=Evi>P1p4`)Z_+tGUb!UnP1?od zdFJ*$+veqU?AS3LZ`Y}PCnRC{V||m*L~HO@`X-k^-z2>-r7T?dZpDbT)HrETm{VB0 zFa(X0l(LjHr#Dy?4eX6L?h5DYYtBjA7Yzg(uHAc1inFs?VcCIDR^y6j{jvi=Faid^ z5a@z|`hV?l`f6F=$XuW!I?N#jxJ@t~5HNkyO_u6aR&ZGBSnI7ER-EFX=)e!^t zEXxe;%}jxcN}$$(P&)dOUh6;*jDP_!1iD}#J=FfMJ=l{yFV61e?tRY9hQ3PXj;qji z+Tv5t_EiU5r;oLL)qz0#;>GUXo^EC9^?Qwjc1pA?71}8^&T-egU(tNic8u5CSeu|5 zZ67JiUK3ss+HDJTO%8@9F|sDS3jIq7 zuKCkFcS8lGQ$_UiP8Ff&Ivt3N>QoWv-{4?yLal@8OM?f)POXEX#(_0&-+lLiKwhT< zq0jG!;!4=kLrBj=dOFhGR%tu#hVsmO`X*%K26X*{!KF101{;50V{47bwDHFs1Rh z-q{D8##AT??~O!97P@Or-TZQm;I}EklnS@Yz}}I4fykRLRx@Q1=#u26F0FOY&3QYK zW3%P>a);mAQ!frK99#JIr_-XcwaLoMh=HsDJPdslrRFq0{r>JDT|ARNQhS}>4e!tsBG z3rZ!EnGy=OLP~%t3{WarV6GJ2h7Lxd83oLqn_NG{%pmKQEi-&R{h373vBc#0NAD`A)>37->8<->5$B;kKSH)9zGFZyhqpT8fkNa>tz!d~ zl>-MgNvMaBF#;dZBw-wFNRz~CF_f_e-GnBIXGSwH;U3Iv&rHvF1@%Ca#4~+Ok{VVK zHAy&wdfF;{G=j_44PPew=YX0dd}}y^f6GCW#H+x`IFt1qBQuo2KOLb-;x|s+4QP`1 zjeo)wI#y;@#%Ol!IGNcQ)NO$#iI=%YyA3}}*^ zimp+U-eRiDyMKRs$Hk1&xUXp#gu+D{%~ ze|SKX#PkTB$*74j4nUKH{}V!!q>Y&gO%ku6geHl%0trnLuidU0oCF`5B<-ziK?eUi zfhI{$GZUI5URAv^?qE0GQlI;0;471wBwyP44$A1p)c0!k0H{gw2+a@E=OYs|5;FKF zed?}E9>LTkY0h>(*3L#v5_X71Yug9+mfAcQ)utcY_p=ye0lFVn7&?G6ss+uNA2i5^i63Qe5b4-(jhl00} zK1J@NjbtV}hmFJ^{^8J5$dK*+01tQ2q^xxL+w)t?#B$tiD>I>dT{!IQ&%MwNW}H5F zTn_bZoYeU&12suDVrA-%MP;T*QjQ!kJC`(dYtXj_6W4d z6%U74ecj7ZuW6F(VO9C~pe6|oR#m`_15Faoj>PznDK$w>LhnqIgpnVRS>5(DNshy& ziSdRUHA(nw#;VR?(ItVJ-gXSd{>Bx8CJ8fBlVmP?4NVe$O;D30z^0)|;;luWn2Gv8 zljLHnZ&2(^keVdxt*awq=W;EfN#Y%FlVX>#J!q16_KXhjk{#{H>680dNv(}A0!W_^fVHKuH!Ur9wN#Z%6Npd<5CTNm)4rr2$ z;#xqH#B)HCWG0J1lf-jClVl5XK$FC41!v;4OHn<0Wn&6W658yP+0Z1RJnw0aTjLi#$;*TZ~KbS{LD^Elh+mBoB~ z5~(?T&(hc1eAM#08llO&4iqrqn(;*is{S>Z0VR>+EmvpUplXkh(+kDjKGnA(+n-?b zzwewA%vYPfuGrT6A30}$`RdWP682L1hMKPtecV5|U*x=rZo4N`=SWRL;D4$)@0qU- zeJ*YU@qf&wP%!ChV@Cy(zNTO@25J27GKWHOZr{2b*S20onA$VArOvk>xv_zSgi?($~y< zar(N$?uO88IqJ9&y*%^UAdH%24Xz za)jnqMoy>MR^or ztBXy`=e@nWqudz#Ux9qzA$ax68Lxqh9t5Yw$2g+6hhvY#;=Y!)5EZnnfR|6Ou0UwT zgw|pF-n;|WdY1Bvm7rM2n|b@qw7>Ypwjsk-7OU$Qdk5BAR;&$My8y*p`{aC1?#}e@ z{G$7i=_`a>W?`bWS`B4V5%8@(2A!ZkWS^I@_(z#1VpnK+8B*fNL>Y&c=fF4`k@hrZ z!RU)fAB0>MX0g_5;N_#Sry;0f`h%9rcgWmbnK%0t&qAgW1grQWL@uPkimyk6PtxYH zFpF8m_rP;E0>pmi zZG>6~=qX3=22>cd&vl5o`_emN``R{ZiA>EAa+!sRHiEt2>ERV;fA|-PYoGj+#Qh7PEd)&E#qX?GW?_ZSGh1r}QWMKHY%~>k(S@ zK|brxldvAQVzx#3*G$kR0o#h0`%7jF`+#jx%0j$_U<1Dok*{cQ;3L@>Q-oX=X0fBV zMR9uKE25*4P`7o^-G@%lS2O$Y=-clm8#NK{xZS ztdZOC6qFgkO1K@TBQli+x8r$;oQsgl(kyorw%nsB)>EP*~bnx^~ zj&6>wFf#=GF6fN?R30J&&h!tE}holoKoK zc~bRsaa}%RYtPw2c*KEVL(|M!)qTI#yU+Q3Q;BfJWR60LF0!PNal>ItH7 zR$1b(F}o_^l^mYj^snVc4!8V62`~R3#12`C&?+YCHemy<0^^4)3AqubB`+!&A{Qgc zbxtApx@D{<)!YMn3cW z#OI!WUO6NDxf^umo>k6Bx@RmXXGF$AGqT{oeDg%Mm+7o>Mw)oWf^tS$d&a_YMi@|n z$n*RV3_+x$XDldZq`)&4mNU`|0VN2&K7?LDP6Uzuo)Ic%M8?8$?shv7u-g&eAb8p& zo>Bwt?>!&1NjzT!I~Mmz6yYg?K~ZmygucXY?vW=KA?I)Gk-xF8VTZLnEyOej?b9-y z4-m7AKxPgB8;&SIusw(oUPi-6)>bG<)>bI-v=z=kHta#fG_ORmw!+X0;9G8f2(2)( z(lbKkjI8yHNI9?Rir6#f6#qvVrc&n5DDSF$L8zP&Z>JeWq;p-I!9;5W+d~=Q3tuoo zGo;Tr&&2oh7@O}lW_1Hi#$Q)p~;ZQLt})OC!jnu z84`JD6d|A8c@`-T&6So%eWtM%0rf0Y z9{>D=<`>AtvlK%LTC-K9!Lt?eoUJ@G84`JD@Fa#je$_M?5_xER?&a~jNb|?!JUq)q z5mKQ5p|)tIA*4Xa#QMXNUrjHMKV&p{8cek1pA%7!KlEtE7VK_Vnj?1+0(KRGdk)Uy z_T5orJ6U26Vt(!|31tS`TLM;^2MFaTNV_-ToJ4Fzz&zdrj}Jr%yM^bR^$%#asue|lj;|*C`;6h_u z8E^HISKtQg>LB7NFG_eTFo+n0-r~~8|2pOhc(r=hU|zj;VEt-vuCNM65d3M3Q!C-s zJ%ZrvRd{(0;T=^(c?KEpMSrVB-mm+;HM!TC7(%>d(ZPh*+7N=TmSW6*t6o-X3s%j) z7Vs{rc&xb2aQ~2j)Xv#SU+JX_lfKeR7ui?(msVmZ!Mz+M79@S853l@6pY0}nrOyr| zeWlM1mUDmPHw@ZFC0e*4xim)Th=8?ejuk7i)&0F)y0WGrEX&2)T*>E1*5C)6(2>Xc zS{i&7qKgrJt&cP0Vz`$f;M`2`%!CuNr;o$a5PIjIjlwvL+vX;|awzPw1vxmX_?qD` zflkx( zR~f&kZb$Gna~S8;>=6GV_#Nga@i0z91-{KVFCe0x5)U+c{KMGKL7T^9We!^02mKs8 zTG?r=me))CgQIRjq6ZfZIN31O1bV!SJ08Fob;8@#M-sf_4{5SR<&1EL#|jYM<=u)c zi?UEr9s)F79$3T(uecH#Jv90wa1eQl;@5G+S%4YA>f2ZIkFcYj4UHauJ(=5IN1hwF zX2Wc41`}L4GyM{u3fSr422RUW@8ip5-v4BlzQWRJWtO*$S? z({G$MDvzE){zV{OoFq5ndADR9tyU z2PrFF0`Myyx>gGl#}|yVlMVznU<>X_k=&=SAdZ;#>0OF0M*@E$l2_Ou4k z3Ul}ucZe74fR8&2F4YNsr|~CY7U*5NolG#`3Vu;JBi=>#$?Xv3HyKJ243>ovZe92Z zo(I{ezhK*=ojKOzNtI6icR$LUi4}I8GvFvOCoj5eaqX7q0&^w~IqbD?oMO&Io%p)3 zLxNx8VMr}@YF5rDb0#Tv;NlLBDlI#|)iS?;nU~*iVSIa|K1SI`eD`_1<0o&~{;GfY z-wWg5joeUeti5uXFj>jUhuRgSP zdKqvw^gEOEr%|PlOUPv|?`o|wXOeTMU)*t-%gdSA5t9Bds@zUN%X!72ttUGZrzOW_ zE-zr2&ICL51 zSDf?*QsodQ=RDod>9{Pa)1~hWnv*{rf3@vgzOuuVq)VKnzlSQfUC?E&tyOX+ITPcY z^k-1=W@6FDsur(wCN_Q2KR=aQBQ*{^%uq& ziV%1*0juyMx1Be}+!&jR8T5Eb8pch(m(n*jiyXl7&dygwl=#cf!HgAByeZ+17CC z(Wr1f<#*ar)W#jr7xET4wZhRz4Mh6?eq;a@FiPF764t5Nmy#Hstd13;K2HZz6p-f5bZ0NW^KV%7XYp9O$lN*mL@ziWEz*WR{ zY9$hWrg{%mU#R;7p_nu(0L{*A*pOO2aVU%AptkzKzk5wos`p$Vd7KYTfF}DW6GVXy z$!ba4d{D)IeThVQ-uDtb!J2DIpy5JIp4}OJBZ)fjmw`39%WG6pL#TWuBw9RSoij~X z=jAGmtXIJ|)Z2t!&JF7A6IBY_uiidZ#lKnpXR7$`Q3E^FGjA>KSctVSIhj`_CxgC1 z875|(-0IcgW%U{i2A_sPPhx!^rbJI9c%s#k8vNPK?TXykYMYZZdD=qI25X;CpSspLHC&=?hdAoUaw>?4`Srsc!rpfZu4rfz`rdGU0Bp0dSNG&>& zqNu2LJRZ(&mHV4{vN25cAUfpB@<5{px>DhAE|i8ig277zxpAy}^E{dX znA#K$>Z=#I@ew@YzHs`QFjvN|@AHzQXHH(fosoeo@?gxpT`aC#2b(ByW` z!pWggH9gdmY4p%HmZf7LUE^e?TkBZ=Q)7!C(s2dVrUBj_pYA!^$epLiI zUrD{m4VEp6Cl0iDL#*qM3#nh!q${3~rUuV{AieXCi74<}<5004$y#)p*TGaR{;x{+ z{IO0CR4VeNoH2UR^w}lOe^;)@Q|p16!~c?Mj|q%Wt>@5*{X0Qa0zxwXb={tSi}m~q ziS_&=5)eE{lWB+MdJ^xeEJUSR5#nl$O>!CtD{|R{>l*@A}HF{vSbMVo=QmqF< zF~2F#^IIBUcDVe{3-$cp6X^Nxs_l3?B+rn=5K!{AS3*$;yMQyZ6VJ#Krp=l^qZn#O zCU7)<`fMm;IaDlT;xx+NjGjGhc4_f=6V9PgI-_{pc+vFzy*VT4-d*t`D zcKDP2ceHi}1(*HnYVF`5y`&{%^H+>d+^(p+^}|g6irPDep z%NN&IklJZ7zN+8sgxC(|vqn+s>NG*+WCS+n)8;HPE29J|{qR78Rn0}_n z+ikQj5?6}1i1&++i?4{g#P7t~*iTqbj>ubcw7ZLg#6{vVagBJl_?ft0tc^p3^)wON zi#^1_Vv%^QXpgI-+|#n(5I+@dUSXt%@dpj-&lU%Wr-@U=v&Bor>%=?6hs5pTyW$t( zPa>yPV0%Z1ZNy{66UEcSsp3NMa&fI_^X;NOo7WZ`gWI00f4aCxwE1e`-yr)z@fqE*A|Cv>{Pnx>A-J#I`EsG4s6rY0ZmT_e$&%|ZF)Lj z4V?3BKOkYp#isJ}eMtH{h@Iu42uE1Dc)=XnH!J>FI!`rvsXv4)`_eLHh?)-!Eba-);0)Cy}p~SXcfW*++`4|+|6UUL9+GYIt71KD zepT=#`QIa9e<+#`56ap6tLWEH^1FyLUxY-+CXw$5*)2$C7oQhj5>1x}^}a9Lba_zD=8uKn=8pyc zLtP%En=TL75ErfNUyjHZk~xm1&jWUmpD!gdUvF`^@{JV7iW9`?VyQTfMEM2c`SM>R zUMc@-66W3ido ziR8G5y~IA^U~#y33W<787pIA{#Cf94XN!6-r44dUMsl@yqj-zBfkeFO@mq-L!^E-Twc-YGqlljuRzEIhjp&LIo7-4dw8st5kEXI) zh;7BA#R1|F(SARnoV`X0j+cLuI9)6iFBi+i)#CNyP2z3hM)6*elO%Dx{wBU6z9GIZ zekAS@zZ66K{e$vRvASqeiNW7Yc1y9H*iqyo7c4(soFdK;=Ze1Gk4^Q0{FlgICh}cY z*5m8^+$j5Y@lNqC;%0H1_=LD!d{N{h8LXGjl9C^byTz}???gVz&3t^8o6HvLihRU^ z{>366x1haDEEBI0*NW@Js(L;T%KxzVr1-4(lK7hVzW9;2NBmOUFCG+at}^s5%HM@x z4bgsg!sc^$^vA^(qUpQB-$8c1XunJ0?=8E(Xunh8A1V7Zae{b;SSrpH7mMeKmx!F7 zj{RCGUMt=t-X?Am?-L&q9}%AspBG;j-xha?_WK#_eI@%_@kbH2a;!h8Vun~p^mT?B z$@X=Ij+Wh7JV88B943wsM~macDdG%quE;62I6mi!7l@p}h5qNoSH(BQ4@FLr$9y)6 zA^5HAA4NWZ$@Ek)L$u%fh}V_Pxk{L?sc5>oi08@X#DGjcRxA|zibF+Tm*{laV@1y1 z!}3$bIpSI3IpX=^GI6=MO1w_IS-f4mTQq%N#2=N-DOK3+>*CwuUhymOd+`U+<^2W3 z!=kTKR8zL;{vv&(Y))9j{8L2ELq_{-ahbSWyiWYHxKX@Ud_?qhgI?LyYCYC>094}51tLg(Sm4BJIMzo2`P>kY}5od^|OO5o!vhBVZ>`P?Z{WI8h{|qdb|3=a7pTU2p zY`c#J+wP-*kIVnGX!q0Le?|8D;z!~h@k?>P=<5jaw+YuLBHH~l*tKOJAvO~2z8TW( zz8P3mKWMb_jT6rhr-^5Y3q{kXMm?9wzEq27gR;Tx=p%)fdW_zpL0=JV883JVhKUP7v*W8QPm8`#jO^m%+bW_Wxt=OTeS3 z(zUC)syp3DI(yOq0yZShpdo}n7$J#C*c1uwjx(b`a04XnGUAN5 zuQTHAxWbJ4HVos!;sW9l#kv0P`_)&SCgM2Wx%YqWeV$uSPTuo<=bY~>b?Vg8RqwY> zaiijOinl6mQG8tSX+_sB(GHd0P<%&Go|mB>*I&_hswW`=$0tTHPLZ^4)aNJ;QyisO zqBud3oN&y)NKu}TL6+xZKoZ0;-St0xo64^LBJz?k{XxaY6~!Ml^e?L{{-_~~A8O!E z)qkY8Pw@-IHpPz5#X9;s>cr-rT1zf87vlY)* zyjZd0^RM-)-=s)VGuC&TqC5wKe6Pw!^q++E7d8DAMc1Fw-&FoU@ngmPiXJ}qL3y7d zN%<&uQIzLjkmdOou;X(t((f_nN zg5q{XQtL6lJkJ7>K9BNuit_vla*RI52`lC(4pb~s9Ikkb;zY&c6@Q`VKBp4D(XcOm zqk)^4j%yEc@39?sDn70#&!3=wQS*^(kNM>J6Of#Gl)qH`PVZ3w%vT(wI8-{hAlQqQnU+*T% z=z{UUP|3Up9OeUvGKNpK?)cAqcnl`nAVn9L#;rGkAK|C+l?h&9XI+_X|CqV0VQd%Tv-fS$*`YmcAGx@8bG zPK3jwnNjU?(`q{8+u9kwsbVd0H#gs0D5C4lnS!~9Ny&Ptck5k>xLXEMvrj-ld4UWe_#~0ecgo6mIk)q($2+gS~A?q&*Bz#2(iTw+y1j zxB}-H4CCC~G_Etz_TuL``-%2&7)I=E)-s$A-2B6Ejf7`3?nZkIcPqO2mKPt{Pu4cg z2as)lar@k%g5%8X5rpXWrJ;T9_;K2}`{PB#vD@nbvgMCH{1|cjOLUJFW}J(B#ZY3} z;Qc?x9__QvsA*)}g!wlZI(KvJ;d1A&d^u>}yKW|+n{Qyj(1Ic1_U$MAWDPoc@KDMA z(|)p&W=Vx!=UDG!bi(SHyJ!F8Ys61hTFa`^__f>ipMP$T_0M>CRYMV{=*MqEqU zwb|Fyb}KA({8eSIPrJf<0Pbr>dG?L-7MJ#bSFP{A{*UhqOZRkga-?m@Dw)%5jXz^; z2%fcK&+S|qfAt1`V$0ix2cEGqOZ-KtE#=*UEpZ!?)~+`a)~2sdS>3th#XbI%nPalo z$E;0;Z?42^I+ywjC+|065#nOkt}cCXkG-XH&CHq?_ZVAV+~e6oe^dR>eYY)twQtS4 zdpzcwZN|1Y+w9pFl?D#@1HsbA554fgyL)WYE`8$A3!_uwuf8kA_KbaZk5T{lp?B)v zXfwi39D4c#So+}cLr;(H5^t~TVz0Z)yC!?=DW%g<=AF@x;Qwpe-e|M)Uxe++dsE7; zy=(H`_%d^~|A5~=Zg0HzsY9=g{#B{(8gtkUrM@)}??_!Avmv!4W&PEqNgIs*)3>8t z^Y4Ops-bQESwq|GvZ3Gj;)lX}*i(njpO2d7qkShmdFcF;(6^J&vT?ypPaIk`4m}+A z#G!My+;X>5-jhG{8+#V~H5G4bFE<}KV8ezD1Mv$HH|7U7nR!nfx?oF4Yqs+rX!D?- zOl57xvd0dczYIB-q2~FhSu8w$==?3Li7hx7w<|7rQ($B4H8E?(?j1kYI+$qPSe~!} z`Ir4YGXS4eWA=_4<2jh<>9Hzq{Wo!w_r8^Hju^dn!sz0?#}%6g@jK(eMC1Bt{+1l@ z2seMx`Ht)jok~L+%zaOIve%|xld#@%$VyFb$)N8mYy9@KYqGC?w{7}rv*>ugv2Scl z{D#{MbH52cX!LuPwC#ed8xDA4H)S0x-B@}Pd|(;5!_;#%!#jooMaXO`OQd)$dJ40pK%{WYJ6^9&lh zceM2HxA24&x8ad7*Oa`tqm%f?ieKODqs&t4fHBrHBDF12q+xc}4BO=Igz=+sygiA)A5Eh-k3Z&qs5~C;F}RfR z*fGnI>M?zH`w0Fa0P6y*Sa6EP_0i*rd77##5r;RdGpMq?^pjwXgC5?nR*EWSH&r(N z+4D2kQ04dXcPfiiB=&+%eOcc2@`ZbA4eEz4tTL#qL>PfDtO~|YpgupXf$=bkd55N6 z$T)wm@s3QB%T2$Xz=}HKAADqei)1f8PlM10hD_@-{D+S$Hq)}8hL0@9W9Z+2KC*^D z5Fc5`BQd}q?BFA-8{>0e5k9i0H)6-(AKhWaF~9oAqU)UCeEfrttec>QrvG|q6B)NoL0w6sOS&gg1*2nkGK7meIP5_vtB&(|Rde zR^fA+Vh7{c?#h7Us>vT@!{8%}gQY&QXgKyV{A17>;Ian-d}Pss4t-=j4ly{Eom`U4 zI4j!4W-oOs!tNQzsqi-HqmQf+Xrubb(gNxuOB<#>vK+}DyqxWNFd&C4d}OU;RS&5c z@sV|<)SMK&h?yVJS)3V6Vi%u~QKFBmtxSEYtN1Q~kE|ZtkIT(&wVIFp0>T(F;r zeS+llhL5aqB1U{lKQ-;AD^#|#K z9pZ-vkkcI5AL0w)^pWMr@uAV|1bk#U<l;I=mD_q&pM;3oLrH?EpJwJ3KM+iQ$ z93NJLLZ5Q*;UmjQ9~!!e^}|ONJy6j{Rw+6WfR8L^DJc$JPZ>V4octvrPHOtda?&S+ z_#y#)WYKYsC%Y`fAGYZu%gH|_G?4YfN0z)$10Pw}GaWv%we@2$yx#*Srl-LhxpSyePlT!XovpB{=-L>&Ir`Vj(csI z&%6e9#YYw&9)*sDiaxR^&{R2h4t!)evMx1hBdd=mHNWsx`heG->AJd5A-aP2cLT^j1)Z`(#3KP(mj&cf-kF; z>;Zga(E@yA@#z_TWX%@QW7~C5c>MNmw60qn{&~$~*d+MKx(!y2T7i7c;Ytjtycl4Z z;cr;L==yu8=p$<-a+zjKCAI1iEAc_-V*Z4Zu3M~_0?xs8X6nn*4W@hTr}4kLc^T}O zqj&}|48AhP&Gh01xd&fNGLK2#hiucJEJf&%OWm<4Paw_{+zr%;YocPw$Mu1xdf=G> zyk1E@UOLaCE*rgr*Q*a;k5o=usT+lV=2+3~Mf4SfY%&~~;}YLMzD zRmVw#6EQ)&2-)9q9~~!7tmZ@J2SV9>Mc0)Buov=fgq#JnRfbuXd_Qzv%qPCsk?mvS zju(5S&=n$NlW@wMA|2ZY`Bmyp6kR$y%NGmykxn+BkeXAvP*;T~M<*kQQ>>|p&qMVl z#J`BD&@iW_QYD|7#4{J1VoeQEH3VV-Rm%$ubD9+757{e3g@V(hU<<@G2t6M_+xY=T zuU+h)-%MaS5;8IdxvPMMuZdJmzulu;$#)x|#G56X`H zcqi|d$agT3SCvN3eB|94$(!KhjfH~0kUMr&Y4n_dyzfWyPB1gr?xUdSN~N?xm3*XF zh+y>L%XEu%gOr7U#y*5vIne6% z>B)q*pzr$;v_*&%P`ahmvuT$jpx3PbJwz<|zZ)_0sf0N!$~N4BOgAA&8=gdjKZ;8m-bCbegj^P8 zF}EH38IZCqPw>o_6ZjoP-+9pTLy?bJ{uBst&<2=N27#Z1bVKM@PeXK*rTe1|5y$fo zf4wmO9KV-ExGVWp$Y_LIW?`aq>@;X*B522`wB(E+4&(!KPJeKp9hIQ zsbdPV9m7$~Hm-wc?oGJGZNpW_z~9-W4R<1P2L-m_X+)kx=*J>je|{n2{V}cilXU_8 zM-@2!qY51VQTdaQJ{;*EI_aKe$Tiio82_hvny?H^*Ya*z?_y)A(L+lcMdxDu_0U%o z7gDPTtr+wQRzUiSqHwhMmx8Y-CgVKHlTuL-8LSWCvtr+hYY``$n{Khg21`oVZLF|FED1+y>KkA&S-5Zs4xSy*3b4~@vLng+*Q>qyk zH#}~Hik(A;iCuz*>!oNSGH0cmz2jM`E9OapQ)*%=-5FuMv`s7Fn7FvOiK*@8j_QMa zSvVnuC4#Gn?s?|1@lrN!SX}S;WZd-?`>q-zR`JZjO_`YL@!dZLXUuG^3ArP>9O(S0 zBwE)q&OFh_ruB+$ni}aHt;50)aTs-?Z${iHaVN`2;7Y5&t+gMm;g}!Pt{M<2#5T7V z%Z-CyG+u}1F*8qd%gDv0tgRp=(*AU=|RD0rK0A6guR+E?r!?g8AZOV?E# z62hQI?>}61M5hn?xz46iaCpI|)Fmb(89dhDY>LQBbxGiHf21u3O3?liIwP;+T8c3~ z@IwM&xI||VN+dd!K+{L?L`7bK$mUp|N|=EF(pj2j08cU@EYWg8KLn6#PauvF^%R0r zr2 zXEYxHeIfivOP$@ZMs^G9izX14YAmqpOT+~Vyz)d&o0x@UGdcLBt z%t^hjnUUKOSZphBHv-ta3Ev@DM$^hxMiS5n2rF9IGWJ1iGr}IQw7YwwxWH)(M+^42 zL!8fy2%}cfx@aAH&W%14T%LXyJ#53Zi+I!E z?C62G?*Fo0$T$)KhYn!|0z5d})a+}50~Si00<#k|fDRt)3}B=YhMl-z_95PWdTgUhd0#>*vXDuEYiZW0G=D}qdDM(#qu!LqIy z6sD~d8Q}!PY$u%V=$ExJqQY6x!is2Nr3jp|C{Ebq6hEt#5fxTM z3o9c6N-zVbI2z(*usEAJu4!}P> zm7=+_vA3MdEFf)h$65p@4||1V*?QnV&q?&twPu1ZOU`p)8Qq_EI>qV7;IFs3oep$% z-c*7!q1Ig8%m{z2!{KywvkwktC~)xsaX;6Wl?bjU8OASlk_c-N#BmNITz}kr?#x0L zuO=^*ZaskPnz-O_l{l+lo^Y9T&cp@MVP~BxXeDyMEFi z@J_?Iz`)$@K^5(}iu()I$!S$u$;STZ$+Qh=T&#(_Kld3p3F6E)7;*N4X~e5F&Q9^W zYo9S)&bf^9=LhCv$J#VbWS_*|j24@5?o;M-_tB9~X!g%){cf}xd-{@QM)=@EnuW76 zFT>evNo0hN^F?3>ZbR@HxMILLpYg}tME1a031QP+3EfKrw+mwCpY?$cGGPdN;K#>3 z3mJUIsV(-*7Mt-gB4bR^cy|uD>1;p8&XxaJ-Oi;HPgHvmu)^`YGzA8@*kNj9a(c*9 zb?CV}kR<1{Sjkh)GuJdH>Q)owMgxU0iX3cOPs9wR526Ow2N56t^lG=mYJZRi@3UmUv}$aa0m{wfB|3@3CL^?e+DLuZ{L&)fkTCW29Wv z#r`xX=81BuTZ1hZK{SR_jjP1|Lw93kym(b08}CFcIsAAX*DdNAF6tUD(h~PtFDoiv zyjU4rT7VwiS*SmmFgWlEF>BFkiT zoN~DQyrj9sUh`}GgD6{jYE-q+%E+FxP1n50d zs4Cl)Kf2Up!2pgiY>{~r`N5G|9$;4^{2qaale_WIV0aFJ2ZFn~I(N2m#>%~@W?tMsdTsKv^3~> zPE}6v$yd0Z^Z~_8XO?P8j2|{$*Nswn~aPzrWDqP^WmPT)U zY~gPF1=@l`XzV5PP(l#XQ%;}gsreJk^oEl@v9@aA;D;lliap}A)c%3W0X zi@JtcNX)IRtF6whuAH-A7JhJLO|uqNR@E%1tv3EUY&R}%{5S0`Trg+W{Hm%BZ6BIf zm{;KT;NPs_h@*lpzZ(`+RMj;!R4=S-s;;Q3Z>j)6KIm+*E19&YvZ*GohR0&nqQ(V{ z6=)+w%!G=$)$=MBFKnt15@+aepjHTNc@qSjbV1R4h7*fqffhMX5PD1?;fHpzXf^mj z0Pi#yUQ~zq^@QO#ndwGn3v=jX<~Z>!gMWe4)Ks`VfuD#ZxSt!S8FL9$n;7_D!fC4!s$!t*ah*WGc(|{;@I>~KjvH|d89RL2E9i-*z6zK?p>vo z-YQ)0Dt|vGES^%T#WTfbPo7V`lc3l;=QwUlHaZ2`6W*hb6*RKR%%xYAJot}Tfbv<^ z6>1s{y&xWit?wG)7R2$*0v{9atHE_nwt+VCogZ(Gv^_rS`$misJY^u;N62P*kFwSz zprL6Q>7(6*U1vH8t2N;?H{ruG)fvlGn&LPodFxCwEZ$gdNf_yy>}GxsR@m6{wH1-( z!9|DEyGo4|Nr`yt^E1V7h@^cl&QCJZ-L$XIG_!L0q18F+UZkgFyI4&`D*afSevu~l z!akbtSRXdROA7p;Sa3j7R1QNuq;Urwhb*ZPk1v*tNnDT9?L zS1j34nH`5L%s9szKd3`K853G8=#P}+bcp5?*)Ufju2?d>3Gh*pKcI&Ldf%W6qk-x4vqb+ZlX!rAW~{binF$V1;`_{)1gAj{ajPL%S>PR#_r0od$`F#!d1D<+vY+1B!l^PUZ2~ zOMELyyG}H*YUI(u%Ev25Qf)ob98Sm4oZ(IOh0&P2aNbC$vr#?~L&kwy8V*|lc&&-E zHk&Y)<*{&Ps}Mf>vJ!YK_$Llo4tK9o5$#arC(eiie{2apj5EJt;hcFwl<&~pqcM1~ zzo?L0`PB^#wRJ|tqB)ICSi{M?Upbdz!@}xXEXmZ39X{*C#_EQ~Syc-w7gaXo7tESh z*KkJBtg*+JPb{xE+QC^R=RabY$ z0@O2qVcnd{g%t}H)h}+SuBdNnFe-lFkEOo6s-d!}s>bz~Vl0j{oBkL6OFXi)yJCSW zf%&y)5}gN#KMDDF_&8QJRy8eHR4sYn>7aCC**N&dncHa8PpmEAze0?yqjmQ;I=^6< zxF%?<=6ElvZkS(PTeaM%pNzplhXxPg;IKn<%yQ=7B3Jy+yJM-S;7Ez#|MSf9KgctS zE(UP7@^gH&%=s^K&2q%W0&}lwVRdEg;(Eknk*ZjNqkTbLZDd(+XXJv$xs6Rm{nUb^ zjr#J2s?qX)j8Rde%LotHA3A4|)kY@cKXKE7m0}F9`pOrah1CJe&awrr`wvXzpLWs` znedJ$qyK)_EO<$#dVa-XjM=nthB^c8RdL=mn%j1$Ju0Ih=RW+4Z8Rc+x3eK-?n#+rAtlJo-xmc?!8pYko z{Dq4#aPF!T*@G30PC{c-LsQ)u6$>j_*`hg3bxW&sc~^fZ^r=$WFu&2@GFUw~?9}|D zZdm@yJg_)(vVJ*l9ngk_mGc|1h~jRcYFQ@8u>m7hQCq!C$Ek8*HD@H!Fk(28 zWGreIRW8IB!qp3h!@wD6c(~8_6HW|ImzzGEvcjWr<2P=RbK@7rxvHwVv9Ye9F+4Q) zuzSG1VYzjZ8^eOaf}(IA+~8E>AnY5SiCdW5p}BL=psJd1L-mpcJWj%egNNh~8AQHU zybp7jKbCynjOfOD;2-hFa*1hOpsFQ$%O+7A4T+^4b?3Pc&sY`DgWrLEPfF`@~TN~#5v1hlQ<9NVpE*=*y*Qb zipsca#S8e(9P!}QD7-T$epyHvK$&Cg!86&OL`UZZ%s;sc6LDsESNN0Gk;usxqC^63p_@z(+r-eBNSsy|wBv?4#sWd0?J z7b&h)+^l$);vW^CSKO`mwW5ztl3b z_^#r|ir*>5V{S3O@Zl>Lf0N3a6@RDt2ULDU@iEoEptA5xq8{c)IGvUkl1D zQhkH!&r$hY#fwzW?{iqs6^b`0^6MPx?^onUIh3DM6uwEw@2dPaMe)}H{TC{KL)0;3 zyYc8>?4&3P|0Lq#uLb4AUkfmo=_ogth%kl-eW{}OYeD=J%E&i|h)_#JKH-}LE>-=7 zMC7|n<@K6xlj4o4zmtf352-BtlCblf=6hN7Z>#)Q#XUqE5Bw&F<-b?Gl>iy#{Y2=K zRZdrQc_w>NM)`hWcqlBG5sQk3zbBe-CiTeIZ8FoG(LjF?Izft@T)yLp_61Iz9;1Dy2D3_%e zR?OG*L5iak`PB`}O;S8Tv787yCo9fZTtq~B#19L~ol6ri&jIq<^ORFBQL04B$ePcKB%xF+)-Ous|07E5P2W z@5n=0Og-9FsyIopLi1NCE>x^nTuel{<%;5O1@h%8w~>M?uUJ6Dei}_g`EiPqR9~+0 z$%=D`uv4Sy;%5crR%rT#isE+#`n4*H-xbIkw4C@`ft_b413yyq;U0kNP$$LVio!by z{lhAMsVF><&==yKf#pUij#k7KqS(h}oFJA{K@6W@rlS1*jdt`@xvye@;?auJ6#3>2 z+wJ-*sZ{w4#X7|$if1XFt9YT}uN7A-ZdJTT@nOYB6`xjoPH~6gtBP{Jfp+awdAH)n ziU$?HR^&@y>_>)TSHRlZp9SBi2! zgK}4@Ori?fxnA)e#Rn9(DL$#VSMgKDuN1#kw0Iu^dohaq&7X3nVt2)!in)sNi8k^L zRhjPqu-rJsiHdv&fO@%)0+K9&a+RX^!Gv6=@+QR_6z@{JPf_lxkpBsl<^BrtUsQfa zai`)Q#ZMH!Qv6ntubr|zF^Z{*A;qv_j^ZH2p^7Dn6BMT_&QNSpBs~V}S*v)Z;w_4| zDZZz;OL4CvX+K#0E5&aWP2P_|4@M-xR7KK~P~Tgzzv2kRV-?3M%6%d7PgD6M#nTn% zD9ZgJ@-0$%vEp*YRf-oV{#tRhqTElSJZTr$zE2bnD7GoO{zLr8!+i0Isfr=RY{lM+ zuD=j`2qoo4D~?kvQ=FoBisEUCa}{e8&s1EjxKi;v#a}62u6VWLM#UQyZ&lo?c#q;A z6dzN3PVps0xi3ciO_g^keyI4F;z7ml6#04s$1O%NPBBd}Q?a|E+*c!ip2~%a!xTp; zihoq(o2qi9qTF{w@A@C9SA9o6Bp0ZjbR=vac@K!Bxgp-B_(O7R6n*MCVzza{%M-SuBWx(JR>s$y6%N3p-+K*b@7 zBNWFdmMYFyJVUWTafxEH;`xfJ71t?lP;6D)qIid*_^m~IA5z)%U-FE~e^Gp0ku(?V z-=~VCxS$+ROjb-+?5fyZk@OeLKS}ZD`Yj<*49lOTc(LNI6k8OpQoK>|R>gZ2A5?ry z(e+u6DUxG_@>PoR+y=7iFNB0D zOn*#~3@Vi0S0qacWqD2mBohi{c}@c)+X-cPJ_97t3FVQBvlZtmUZi-bB1un}|29Q= zzJfK5)F;$GsYr$s%5N&}BqETNzpfGp2bfQgimkEABl_fRB%3FRS*q%fg8 zRgo+vl;U!i!5qU*ndv?NS_R*}pklwE(d;-41s=cj z0a>0`0LlHq^#4#K{Rib#Me=%3?xRR*56WW{$?ie z9h5gHlCFdDy^0;5FW@pl>>ye40R(YbDu~mHAf~xs$NS~5>T?wH6$dE}RUD~UtXQHr zMUmg&v7Iv%XDQBBoU2%`*rd2jafRX~ioaG|t+-C{I>nn5H!I$*_<-UgirW;QRD4$P z1;sZM-%;GD_`c$9#g7&DD}JHKA6(gQey~8~2U^5<#U#Zv#Y{zhSipQ?#T>;w;74igOh^-p|k0`^q%-2ghip+pmAaUqFXyH1-hg)6QI_6^C!PX=^XLC06|BsSb!r9z>zknEB?>!R@A*W)!)VuYbgScA;QRAI{$j69oZrXCl(e_@M;k@@i zd$??g*jtUbTLw|%JJ?$lrEsIaMq0GJ_hFCUl+Yed&k=h!Anuky)L4NX^szg6qS7`Y z9&IlTFEemI(H>4a5qrN!oc1^$xYZQlTS=Td+>L1r4=TF(cH-rUC2l57W4@;~?k3F` zfp1-00myOY_BcXx`?AnJ?l!iM)5hH&e?c6(y&fRjM%as<`>c~25yKVPwj*CLlp$#F z_*m@GKI@E{Mn)3mALpdIx%OBlI^O`a@9%CVpqq~`sw`a8SaD`iL0;X!aQLTu1{4e_ zJbG}L+fVxp*zCMi6Y&|4iQdp>K+9IU)OShpYGc9tnwx9huSvSn%ztr@mA&mi*b`ja zb$!BBiC4s}i(d^ky!|=n`VOorF-P8L{HoL*ai@RsUbEYwOz)b$rM?z(UxMX5kYvOh zNb>tzx^4)p_U}vZ`u1C~7nQ_-YuzaEt)JOuj~LTtAM4%VTf6x{QoPaM*ni5ofvZQC zf)gWqYFpBZDQ!s$pFR|Wc>KaCZSgCfIpoWp(q=C-uAJKDUpTeRUU6sX6vUDWo<0=F zHa7ic409W(_pdv^hM(=MC#`Xsfn1O`ZyTwY(26Ke}fbI7lu)Q%Y&0m;zBy8xq-r9GbmC%yB zp`s>fgLUBhkrjJ4`f|4?Y|JiAD#E<+JUr%-M{gLj?oqS5(Y?N#*=OCOMtArSFu?)0 zef(bAoES4<$K?G+LOHxal<)D3OE_RAEEzWj(ilkAfh5ZVE1&I1*f7{EDoJP=Qj)db zijUu(u>O$)W_)VRh}pjF2ctaVVh3!=L=z`ww0SRCM3fXf~n3(Usq4C4DYkRMJ5He+G4 zE<*-uSSKv;P{lMNgH?&R74a`{KXdW1rWNroK&Q@D1N9OA0^6}bxjqH>Oxey!<5Fg= zLRMRS3M8N^TYU<=&bZ@K0KBy;XzLRE^Y-Yp3&p%PuSb24qp)dhMw@)*s7|yBCCNgdvLd>sz z1lWU2|3H5n>;=i&;4esJ9Cgr-fWJ^{w1a#`?k|jU8sHB;g$n(Jj*A7*$Nv(B{e@ke zRPiI=FN#YRL-Zp+*5g>RRr41i=^IX76JRmNKg7>pXM%sFfnfo+e*-BFSJ4iJD2`AO zP7K(Ckt)Uq`Llw5l!{5geH4#TF)g?sUGyKTVrG!PW%-L$%nI_S3;$>p!$t~Ee}2J&QZUFV^9{LXwi?rMNB?HItJMj{5$2TDqjF1@C#8{8gfgQ;YZ*) z)VA96pXQ%U>oVS_r!Y?I|6t21e9jQq!ME9x%D_BH^#`S4bGmV`)QMIr=j2n_~&1eEI$*WqRW}K)U61+hqEr}TvT7t^N?eTMTLTAt}{0Qjb5_*V(0Y3saOBd|W^Gt^y z0Y~>~UK%*N1I^dqp1HsD8q)aL3(fQN#!lRiT3sGTGt8;6~=4t?|5 z&mu#b`7Jb@pix<=a`)#!$;5J;w(XfvJ`)OA{W%NeV8-&ndX z_tF$w=`S`@DA3fGEDApYj_eEl2TgbMBk(OUYqL9T_pkEA9D}J6;tz0s_z~dQjHZsJ ze7+~e*^hRpi5-F;0cNHj0gI;LM?hX2fFFU!ST+0zIK7w<`iAAB{0QLQ%kaaGz!quh zj1YfN_rs5XbHLSv#xOtp2smmP`qJSTP z1Iz(G0&IarKLY162mA=og!mEo1?z+#0Y?Ep0%S?>!;gTYfFFTm&Mf#5a1`((P{bne zBj70DM_@K{z>k1a%M0)$@Ee$Ct7J^!M}RULB{KX7P_A`l`VsJ7`{7#>Njn0>2d*egwFxQxH?|Bfy=*14-r1`~53D)_YKN;i}_@9|7*%E-4%d_z_^O zPW_*{h2TfPMi%%HpeoDcG9a@X6YN`PyfzPX^)J9aLPM7!j+cR0&cWdjr2*jk=VLZM z{0MO6gCBu6I5_Yl!0QE2@Y!}>q~m(*3bd|U7XEq7Aut($9|68teAJi7-yF8^-{23F zh8ez&1&prwP{Bz=_B`Z*9|4-D*MKd^lXyLJG4ftNTn9V>jn}5iYyTeqJEeJ+CB^l^ zV+x*y4bNFgX{|(zuDo(_c2deVWP?Yi&_1-sv%;1A-4`u3Jm(}O(-uyTp-vbF&&s5< z`=vPUB)ef}c$$;Ee8oADHS{ny!h|`7OQ>^dCz^CAo?UL3W5bN`s;QqHj=v{^yErsmWi$k^6?10>X*SafT-w=q%T6R`Z-Xg z(;6K^&{sq+43c?*?1D8A`Bp?v*fPw?(vT-1Z=;T%E0|M67exJkr>+|R%qgAOV6Lf0 zA@m~Wv^h2LZdAcv$oXq|uWGsm;9e-hlqf;yc@|5Si|!)G=OOgIm^DlnUC#i!c%sBN zBkd-Zu|$_aJ1;@5X&dnLh_(>}=+?;2o8rkIOW^w?m++~KR z)f3<_!)~(KGa)t3O6ZbsqA%H;W+q{%JpV_69mS|T6a$r++JQCs|2qkGG)psE)Z?G9 zV&nSf2W;0lM_|hCsU+9Ytk@*O?#Ptwl3`0e91;;;>mMb_};i z72$BoYR*#wOAyWl=LlkoGM+<}n>yp1{Sxux_+85a9pJ`hM))%o zI4M`OGD1rrc-+|R8bfo+$pjPQ-aNGb)VSI7>d(OXot!=VRF7NN6K?RCwJ@Z=%Y zGNRRj%K7kWuWOE~)=7=3_PX|J-3ncl#`J<^vIrCTBOK_r2=eVuI6`sRSK{$g_X6Q?|p0 zVgPi55#o&{-(#~1bI5m0ja*tAO`z(fh7zs%jV8m7$$cFP2*&D0Ku}_K6((^hYmt~EB7J??1!e^VN}y-f^5ohjbT8w*vIl8)YoLc z#uhbKS3$gtDq|L5J%VMN+0@F&Esn6Pl@b01j+7OxjBIm+g~If^7Xnrh!WW{iU(w14 zl+?SEojV;GXWpM#FY})FPf{HtH#owwRz|iv!irW#64-vcZ34(ZK#BU+&WQ98{Vc)& z(XX&u8R3AVIu2U~0*VsC2vW2cA{;nmVKce0fGJFhpF+anN^p9ELzEF8+7ZQ~2MxA< z2%H;W1}D@aIC~3KkM0tj)}LucMkj$j$f&DK?j;He+Fu)-+p*~%!V zEn3Pc`=O>3b#7&pTy+>g!siHHLB+7P$Sx@1m3M;CpNb-!U0Ba(OKCbL3RcYGXjD$(9;M_Of$*}Ty1e? zxxJZ@(-D+d*x~Z8g@S7gfb&Q)awf4&BEW)d&Y2idODZ;2A$l1?G)pgK?kJxzt;H^H zvE7}Hg4Z|Ag zA%=8avzti-Hy4pRaXJDjAaIA{XemZiHd8XFw#3ys_bHd4tv&-x%BQr`mO6JQ_Z=~X zcOvf}F@^UYozZ5O*SNi&3DBM-DIkGHRc=ZaBJ8Adxh4^5yA#7KMudYu2bSv*+^rae zN)TxG1jm4zbXa-bI$Cmf`)?9J{&&zZ{vXxj5eP6Hehl};0o>m^igtp>A22#%syie{ zWOT&LQbtF_B8-lRM;IM3BV0yDsMW3yv&S1@bbQtTQ(LOn^d)<{jsZQ}S$WzfCFMa;PjFMbq5Z(!w z-0~UVq_g6X10pyYqcD9~LH|k0SjTp<`CzI;zBsEs&)dril2mRic_^L2ONn{?v$c$M zmQV=BO-fHo_vZN$^SoJMFMb=$vzCXwSuilt8_b4<~k9R1GT+*UcXh2p$J$HH;29c{z#9dv^ncfY1q#4L3ot;@q=;m_n&&WJ4I1hi z!@B`Lo1xGl5i1xhTy8&yqOfY=g8B-fC9LCXV?T$oP&vCmE(!9nrB#i}I0j0@rt+Ev z^Vny&I0SDQdAi0H4EfIzZ-sLgRn;#Z1uA0j#^o*=1i7hZ@uE4vdCShg3&?f)1C~LO8vZoZ;E}jXdF(F#|3Erehq-syns`K-!ODg8HI+vs8~j)3 zWZN(El$CI?9;`o~oDjbSRn!>#zmU`He-2Thd-QQZtH7bjBcoQDx43q3WA$9290ZqO zZDW0P)q;5opuxN&@!*2mdEm?Kz*AU176;ipoa+9!^A+-r)!lew`XhXW^;WY(SNK1X ztB~)Dw{N(eh}tYX(uv+IJUxltEP3m^U1Q;SNc4u60;5IT#wK)-lRC&C_lVjodAqw^ zVd19>=HOj4$D3S*LO9rd5au`xgsMP3-WL5&Mv8h@cu!6t?F-3z3~1)f2Zp2Q@!y1LI0HMpHsc? z{y{I_g#+JH{T|KtiQ?y~|A)#ZP9f|MzD^NLQ_NQEtvFb5xZ<%y^jCQQQ2qqfm#bcQ z|Dd0v`uVCC-aqJ+j)w?`^ZJPfds`sNVjz_#=IuZLHKFEd7tH0_8Dh|{1V-?3LmTUUSij}ILuXu*y z*_z(0_)FDauGpd|Jb-A|t(s51S4X?jqS&BDTrscNQqmQJkm9pF5~urFgO8uN2oRUa5GuBH!X-xj!mC zuK2v-%ZhI(zN5HD@e{?b6u(uJ^EvFs@q7#H$ipT4z|arV^f8M3O^5mAybt7S%#>#< z&Q;`loYbGGxKi;vMZR9g^xrDpsd%sABZ}J;pH<|GT`c#i;+u*eDDF`_p!lUCf3;>g zuVR8?iXva_V|qWuLdC&~a}?((E>b*Gahc)@MgG!BdzUD#R$Qleo#IW3!gGxL_o%#0 z@kzz!6@$ZTsDehO4>l)bohsq|eMBKCJk(;&X~S6kk=8mr7C2W3iYdGjFSnfi_Un;Iuyi)O6#p@MsQ~bT+ zy^0SiZc}_x@kK>``o#L)QhZNQuJ@qdr}7tyF29%XNF$xEi?h7T@0Fyo%kR}iWxTT{ z`T8jGwQrUyQXH;$jN*93;}mBry8K>es9dMGOmT%G-(scxD->Nmuj^FaqIicQ-*9FA zXBA&o{EMPoeqcNV#U6@%73I1V>4Q}st~g%tIK^p-Cn;7aRw>phHYj%F;d1%6 zey!;(idQMhbuQX*lge8Z`JoNl|B&Jz6`xjoPH~6gtBUU_?o!;N_=(~difxMDD_Xoh zMt$*$Ns98(5cCBq4^!Q&eD`pft^ zydL;rp(!u=sbL96El4!a2c8>7ilm$g8Sbw5S?S-J@!q2M?FXGyVzEK|7q#Iu zE?al}XFiYhxA^(e?Jh z1$#aete5q%AH+HYw+y1jp00)wW<)nP?F`7#_GX}Cyl0?2+%iY(orkzv22mr>t-bG* z-L#cVLnubzRs(yyhoC*)leq0$hqzk?QDY+PeZ+y&%}rYkIojR>u*d$<9-o4`_O3&m zW%3cY<>%l{DC`e+V;aL2MK|B9{98;+tAX^$HWb~YN>mo)?4`TxIg`v!VJ{f`bXrFaPO<$u1^AAH9*<5=p z6P<56+V^TCS9>2Ls| zzBvBM7x#F;(vfHdT8sn9R%}bB4RKfb*O8mzPpf9B7+Bl@*@z|qm#$=pC| zyH+)o4lgyrM)#Pj{@iA4?OkJ)21}nm^vuyyYi8H@3;ly0JGAZSyT)Xe_AR};^phR$ z?(y}00Q?bw?PE(vw0UM0wt0>-M?7`t0`uz~!P3|bp7qxj2R6J>Y;Ew4^&U+0W+RW) zf?Oj!YiD-xukUh~b;z?nbA1nJ%ng}qix0k>&vtBF<=tTIi}xfP@LPp#{#ixe_{)mE z@nxkSGQPC;eK5#Am}qCW`O6C1d`Pp)s5ke0P+%TRG_%`$S%qyj^qvm+ZRGcq;dA{% z#uw|xnfu-^uwdUQ6Pxwi4&OCHO4*x)?Ve#Jr9;|0{R_VF9Gh~;_}m<6?b}sk9Za<1 zR(-z12IEEi0Z+W|fX8Qp@nYs3aT_{;@nTF&aKp@+xR&@0r+3@x@3}qh8teg&i8|Jd z8Tx4Jm;sNP*+%x5ZgxMgU1VGPP3!Et<4Q-2of#8b+Hc3L2mGdyeE{qhX3^DScJ20z zYugdGVVhx<#I?kfWbC(m!R>MD@BhZgPhDjm6SMvPZ#?w?MKEZ+D99OonnBwtV{VS&s_OwAK`UArbDLMl z&%tG3--))xY_V9>K1kztbnzihE{i_^G42mQo5;952YCY-GKNVu6q$j6{t>Vjtj51U zK`P^@gIpGYLaosb{ua#)6gr=qX8VIvMND(r6CeB=>;wwCIHGV_1d8HDiy?AZ@L^2s zpYU%gRMIyr!em~~2@LV`&Fc_M3r8e!dX{VF z0u=e>bCCB?ffJ--kUhb1m;`~TD&ql9?7gU)-&aeQ!DW$&rmZ#ur}<_dR0gh;RDX~S3(V=p!BQ>@8jigM{}{9eug&W%a9Nzgc^6phe+y!; zjGbJP%s4Ch2b;artq8kk9Be1?L0L`UUOzct$Yl|@FGUNG%OY^UI}^xd5qLl)f3S+} zdN3e|GPo=*W>pWV=x|vC9!~zf)SM*57lB8#Y-Vr|%RV8aL@tX9C_dHob2QHbE{kOD z$7j0oTWoS!oXNp`E;vTSK0!Y#dOmQPhz^%U;3cid;j#$4tQ~N;ECSoL-jTseXzDM? zRZ_M%m`w4NA%RkPRbka(sQ;+>}4w4d?l<^kEq>mk# z?eTMTLQS*_E(<+eLfttS;IepCx?qQ1VLG@h9N8aQ%8J2d;mGl!nd}6(ES&O5AwJX$ zfXgC*Kk|UfB8U0GW#OdfhxpJT04@uDfbPj26r!`U0Jtoi^r4}vD1*ylu%wR+^*|>A z;IeR*lH$-gl)+`;5Jw5;~i1nrQABMdGJoe`*!9rxNapUKlkLI7MAopEOnIuWV>xGX5p)GQVSmxUwy zLS#4yfXhNo)%f`Ti;=J!0GGwv&~qMa;a&!pg>%5wgtoFi za9KEVeJGFl!DZpd%R+auK5$vAMEzXRL!+4iTo#v!0$dh+%ohNc1zR9o7MC&yxGZQw zxGeY}Ish&UM*%JizHtx$mxZGMmjxdc2f$_FD8Oa0o<+cA;V8gm!H2p5a9KFDU{qrN z0P}2>j48M*D6>%_gUf>QCRZkxMF3nDe}W=34=Dj~Sy14Z^M~;OxGdfj8C(`z)hUQ6 za9MEY@IX?z^Zo$1EVvSM;i?k=mj!oj7jlsWz-7T&o%+cOBZa_aF%PwX%Yv#blgoh2 zZcH#z!+32T=vgKYKKEFdF8VR}AImxT3q-^gI44eJ55Q%?l@DAN2RP#3vfvYA;j$q0 z3a-a26zg^=n&>rgPiDk|%i?iZIch2LHHUwJAvMChdo#m9PA8))AHBzd%i>Dp0++=o znz__Wy&riJcR&{-&y>M#!Qaecj$buhU1db-j?DZwrFFE%96YR7*Avk zJ(D7O|f< zQ+G7%m}5jY35JIv-t*O?6|6Wt(;Q3^s&`mi+1IT!jR_mC=(w@u==W$oC=` zy{F*cgOL(Z2?lj0JBN%!_CHwZ7|Vy22x%_o>vh1F$)v>S3|oWnon8U zDNem5sp}9k8~cCn7WZO+EQEf{!bB-f^8Bs{DBcKb)LZg@BVuM_a7rR-zYZznB`HMc z+XCSPM9L^!1fdEMzSGc;g;{LCYtZ6oVs|KGreHIhGA^buc4Zl|FG0v-g0y2Tq}2#o z>;^Qzz4TotRo{&acd!_qjyP45 z#{X?8Hjq{OQOtJe5%zkeTJrkuN04d*7)vigUOvmS+9F5=2-v)KJ!WqHC>*Jtui(Sm zIu_{#{V0BI#*2^x^PV;{o@+rNK9Vpz-GcL}_Zz5X&{3=n!V@-2nD)n*QjftrPG3N29hvg4O z=O-Ua0xQHRvlsH?PBy|9gZ9u)vhue`^O!$Ha(LTYkeY7r{jIcgvv<5xce+<>WkhnK z>9hrRr_xsG$^Ws_^o}!6^l@C;d1(%3o$2c}3Q|43`^Vtq*Dnrpicik^4{BEqU>pba z57=pFHIL@;j_(f=aU4cd*Mw!?6e!J(&ay&f(^0V~y1>L#rwAS@3geFEIXcvVY6#wI zqtl0QYVx?jhLbZ^(;t%J6yp#F_svd&krE#7AjKi_@=X$?_+kIJK;d(90vB&kI}lg^ zU!G4#G_qmzuuVX~*YbpViJr0<348?#LTZ^EzKd>B52S(p zfUpYz_HJ)xbK(5BuVX)1_YR<^RS+N9e%HtF`}s3tk7QBAr%x=E4L$jRqbd{-V(LLLJ6T|BLf@ZB|`fnkI% z&_nRGvJa;spafx-M9T>^2pD*~l@WFUdkuBVX3FJ?qdeVJVy)H0sBWPcnkPRr4hJgh zO-zAs+)z`D0FIkxM?;ANK-L>a!*O^PCfccKP)?MhY8g%$QEN1pxzW%2ECj1TSv&!JWgX zbI?!W#1A7d1>8A|@)0k(L2!7BmNW}*(I7`p;32>g;LdT626E@P^BpHB&h@!cU@F0x z>!ABV^JU|m9X6RRjBxx)s4&V295}9k#3n~gaCXU>t<8+wj)0TM)@ENpRx1U*=!^1% zXA!XCZIz{+%@P3?WV5wm3#S-l#O5AX(VR4#ts4=1#*`L&YKzVIW|2Xab7G7Ad&Ie` z+;qmbN6C!8hLB<`CIeYcz2Q*g3;{*XF6c8*bqvykGsiu;A`185if$1K$%ghvwtU1m zN@U9Uf?8PRVhiAj3H>&F?itF1GZarytQl*PfpfE4FOyi>-MB7r5V0%WEQq?PT#(#F z37N3bWFbNqqhZ-PPjOChuX=<3yB*uBQ58K}{~vqj0bfO#@BNuG=bW67gd`A1fCvXd zlp2yyMO13AfK**nG_+8pC!weah+ILzV;{1ej5`)oc3@zlsK9Z}~?-i51O zLiGCIN{$b_A#+{=6WNcho1I>Uq^}SmmyYBUFHBo%Q}&rXN#)ZEvHUd%KkebwO2MbU z)rx;1ms!^#)bC+5k&<)-x`{huQOEx%2r6=2R>BX7j4D z?4Sb29jBC}Zn>6~ANNU44G%xZ6Yt0+K)b-?1F_`JJ_z* z1kQRsZkgK=_%R(UJiRgmC$+%e6vsb92ZSPoVBrTCLw^LGuY!fA7zX|x#dA=w@RY$Y zAA#qUVBvwwuoi(wcd!K8j^uy^dqn;8bfj@GgKb+son;xg>4J^K0S^|Y1$D3<=9z%N zJlrVBOY%6kjPk@j7&-n$Wj9}^0{;ihuB_;C_^gRD=1r<_e${*HTmj*lvAv2)i%P~$ z`>z`n{Lm0g6o-dU_o4STac0%Ds`4olCqmr~pEW;`f5Tx|EB}VC3lwcZR>TtWZ-^)4 z->};R@^5fU{tdscCCR@%=0FRpuKb(nr#1JgA@T+RxDx7*K^86^$@Vgeids|ttxu%6 z2*2i4%bi{|3|iE{7wGmJd%54 zZ4(f?i+Xe2NCPh&qJEHji&L+zAh~CePEhJY-wNvVt$+nj_SN-LC*24z+>@lXWv58D!jf z8b18vKM{jtt-kaiHQt~E$Ci`S+00k#qIR1v1sC(KU(%<@dkFe&330bbruVG_8N7DL zRh-;;?z**|ZyofhUguj!z1G~JQ@tIh#knV9V7_s==OnGSc1)}e2k;a(L|y0d@=-&F z^cynJ`Ts^8Zpw_=6UNV|BkJ~_6^xr((%mGy{!!Vugy0q4Fq-s_$jAM|@=*4vP(Hp2 z(q}U(%1t<_yvkRVTQG@|f3;#;<>n4PPip1PO1dN4ehn|2wqj5=RKM@G8d7 znl~rdC(GwoR8~ROkLw44zUm4)@UZ&RswP!cJNs0j>o;;R)WmFz{vBd;BXES&RircB zy4u|qifT~y!2i)V?v{m1-Qh&PBgi}#9;iM)Zs{BMaLi(iQ$++bmPpgY%0b}O-?*i#%T9xE;p zdBcYFTrJ)xZW5msUlrdIdFP7dGR2nSNU>a;C7vd(5Z8z|iuZ|6iLZ$tiC>FhT)4B{ z9I>r9NE{_j5a)_Z#aqP(#b?BK#5~*tVEqS(gT&F|M6pslUF6)*EcdMVrudy0!z}`) zo6ZQhzwGYfKyk5nzIc`RNAV%?Igt;}vfj_c{}4_81OEMR05IKjKEQ)z4;4=kXNsqZ z=ZjZ~w}>0XEh67kWc_F2#s_(kXp@SUZw_*$rRkPk^Vh8acafoQT5Xkoj+4qSytu6d6p7CHkt;FeK zpgZ?l*_>vQ`S^4*d84>Nyjy%w+$_E*^7&?#+a>1Uw`SUH#ctv#agw+|TtZ^s;4{nQ z*(BCwwRp97Es1(>k)t$S0ba|5e#UnqN#covD{YK3^AxK`=w#6QUYNAYg??-w7J{~7TG@vlmM zPyAT^PsOk0|4t0!p>6i3frw{>&2C9zecOl~#V%qmv5(k~L_LGVqs8M%jMH=y_01Nm zEa3!^<1p2Ql(!f{~yF#z(sIEpxZnT=|V zd~lcjvmZCXLfP%b5|Q7{nQw?VT;xM{^xOAqaDwc~;v#XWc((Xkkw4S3{AD8F`l9`S z_^9}V_=5P7$mdd+pFf_GABj6e`~D689@!CoABLSOHWK+mEByuH0V01;rT-}LXwklx z!_Oa9na&43$oe{w{K1ueKHWo7Yl8f(xJu-ca`ay(+AGRNt>-2+)p;&oTHyF-H`{2CXN7`Z_&{|TbwVRBAzZT z7cUSm7T1dF#GAxh#k%Bt^^ddLQ<_q6Ue@T2zd{6vH{14IPbqeyQ zi&*g`aYZsg;u$;{7J8OcCD@;KRneq@F0X`)>>A^&{Yr-^nQ1^+p+SBRI2SBPuH zb>i*f-Qq@Zv-q_5y!e*5P0T=>>_62ONWMx>=8J_QUgR);u}C=<<~v9{R6I=N>-0?L zJM<)l63B5PwN+@(6z7VZVw`@v4g}AZ%^A+==WEF1DzQeqR=io6-IUy zdy0pO1H>c5qr~5ce6^qDr;33-q^WYizd-(_qFryp&zE{x?k4d8(XO}Qe@3)=e;bH#rfG z%D+zJ>&dMDL2W z#p`o0N91eLvk;u28X%7(j-ZSk=vCjPi`0f4xXu9*D-46g?Q2w3bS7H-h z?;^dK$akJ;A13mBXWHY%W#U=l4dP8A-+N~MH^g^H?7MvPnSRr62l;|CZMADqF%nTO#fvf-%h4|lXyFce0)cl{>MeW zicI?rk#8f@{z~Kv$+Ydd7v$T(@1ovLvWvx@B>Z;0i~M%I3-YyNmM<6i<}vO0 z;%OwxEt4Hw=bkS=-%DnGyUqpq3Nr0`#D|q{v+O6u=jG=M%FO?c$oG+Heead{BH!d{*2dzAU~j zz9oJvek$%1zY_O|e-mT6en=Oy#2k?tavYa@F)p?h`6fEkyNOimpxsC8D-IM76NiXn z#IfQr`re+y{$U@>Q$PO&U0wXnl%#NLQ*HgKt9t;(HHLu83tPI00kAo2>4g7`^Elx3Nd9*{`Dzf-;CY zmtu#=4?3HaHZCcSsB>E`&Y?KB1WQoISU8f~y?Frcfu{TIvOTT`IU6A;gQ)ZE{*Du8 zL`#r19d>ekV~69r1$#99D_?)*{aOiV?W{z6cMAkJ94q#l=10^!0Q7|0Tu6J$m$r$4g5O?CR(LWnJBukG2LQ{`$7VxiHu1{K?K? z(M4xY8#FcLoXa=3J)Zj{Qt-sCc&PEEjV@k3we{+pOV^e?J~i{gVcXw7xyj{Omu{Mt zO~u`Foes{<>}4stmJV_cZhYlUPWYgQV>wsFE_*Mphnuo8tyS-`)RkSzZfcg*GrTJ+ zJ$+^CHEEY+Tz==klpWEAp`Bh@gO%5m&EDw@N?jAWa@3x1m(-OhYX*Qz_c~KjRyy%J znhoBO;%;ufY;S1FBs`6JJMHk&yn%>21x{P^p<8TC=priO-gLTiz_6W8EaU11yRzKg zWdq7a?8zE(%$}_D5qr`XZQ2_yIA%{e;;|u{_NE{nPIoRmW={;Bu%%{|IIC6+Vp?=p zR&?9eRb^>w(yz=dYk)~L9)RX;`j%s%{5zm*_@3~oqxXcTy9Yjjyx(rkEn8KVy{6IX z*!SM<1HKP^*?d5h>(DW}GO`BiG(EC1zUJ=c@Jx@d46X6LUOFdpjnnSoxb7w zrC&{H`Pi;jVf-Ze?UTDB6GrW66F+-z$Q`zQ%fiF9_lsS(BNkf^`=#92UN3uDX8-M{ zhhECPW5@58>4A?%{TejCL zcx+ePy>nMQ+UEQ4PVaknSKsZfGiKv}@1x%g_&)sAn2p5)Vr%Z)vCZ0fe-20Z+oc(6 zIJOwq8Kd@Oby~VNI%Sd5Xh%3UZ2P+l2Jd+P|C)Fo?dIm zV4I*e>}}C0i?JTjRIEqUfE^#6a{rD`mOS@~vwHdV?eoWNar-nJ_wm-ZQKG?`ECW+zn!j|zU#+gw;gnjTf4BF_M^9yZ4bMLrwreUy}041Pr~jf zC>=N42=T98ic;)1QxjVg-23s1hb`Nblwd=UZ zmQhoy#<^YcH?Ev|$GBY6Ja*QkjdS~)we`x6FfJ>yx?XMLvgE7g&}H^VX6{FucH!r> zEq8u@ruN9YKFqmdOIgK7IadxZ^N*}kKODC6$8N0-SpVVpGHn0!{s`E*U^*BBV_+Bz zr&CAS@9QU9*MHRb>dKD><3#D7OT+HTh@^9po7-?M+K_YtWE5J;XW&FA5#>Nq*^S;X~<9Xen=_>vNpNYqgXI z(#pWUNM7SXET4`%fqrrdN(cJMeAXt=PtL*mNIw}GeVlzJ97Zu{CV!7ABA8+vMhg^n z!x{J(3^bE>A~DcR=64}#CKtnJn#p{2CzUs7p_$y0@zJOen#uG#4LATNAZFUc(o9|s zJL3@igJv>5s35oJWXwg+pqXqB22nGa(!bD5X3;Qb2ZCnu=g3OUWc$&;jhzQ?Cgb4+ z$Qx)TN8q4lasleg7><9?OlBNyNHf`QF`RKHx(Ur>-;8DO)@W*Jj&G)C+=_ajne3Z^ zW^#M0h?>b%cx-SR{v8OHts6dIsp~||nK>C5EPJTTyo`=$4VuY*+58OZ0zxy{H{(f~$^8D9aT~TC zG?N+UsAtj~l1kH~X7Uc&N7;(O4rNThP5{khuBcaVCPYuKLaY;V+bTmdxd2@=&1B9t z;g9!;jTmR`z1g$!sNa=v#vW`xXeQfl2oR}`)11(fgC)&mR@{K621fmG?S-t zzk_D-qcAg$I^|MnRo4>nH<5OQZt!fG@+T?!OV6U zoMRN4$&{%M6(ls1{e}{n$^Hr?G?V>y`(#|ls$R-I(#rPD$f5aiw%xTYNN6VeRSnE| zg57vSN8XT(SGYU9*&qr~Gx;c{{-x1z05y}}p!sh4MV2}y<9A%6_Z#vEre^YSZ0G~+ zY}8CvRXeRqBlDVZ87=#$GIN~xLbpGx}Xo=h8>$$tKUx#O@WQZw04 zKP#K``#1Nm=lYKjy`x}m2ea+-X$gFPrn#sptSITY9s-T(7Pd`?5 z0gFO2+24-g+|^tmXeKi=HIvU`uc4XDj|plfcW2YkO!n8}uw3?eUz*9A;iqOYC*-4M zvVXu$%{5_cXeRr1t!A=sFU)rg#=Wn&7>WZLYM+0aa;eO6!xn#s4pkvkqK)J&$qF~5>y2F>J0%!XbMPl`0GDrhEi z^8hq#B*j2SNV4)(eZB(1(GU@1z{S z>Oabg@Cnj3?xCp7?Z=NIJln?g#p3=BH?#_%uG7Deu_NFrLukuqlOc-Ch8Ds;iN4RV zC%6N%+4tSB-=XhE)aDK{A0H>@BPwlgMuJ;rzHVqTj?nf+wC4_P^a7F|gS`o%kb~hK zp2hkapz8PO~oM_XmU;1d1$=v{v`WK9Gm7{{qM#o9B11meVtB7FdKg;}c?zKe3w3-Ro^%xA!@FkX+-U+p`S}sH41|uVwIgOv@KVEqpl9&v&KeQ|hJeZXKQ8ga)q!ej|RddcwW(7A1096YwUh_|}yOF0Pvw-NC`QFR|Xz zx?;Uu>&pFht1I{0UF$4m-yZcVw4(=S957Jv#Tkq7w&YtlUqGyPsmsVV1SXLD&R_|u zAc0cEpbtg(d7#XiNc1Bf%4=B)LaT~62LXzQ>y|_d!ZkEjAV3w2xC{Yef9sYoas-Me zGO{nl=u5&e4h9=eQouqPE|73YUh-f-h?6*x=Mv|lOO`M)&J1X5GE(HXb;*)wxBMC! zY|pYX!fRPH?5EP;(~y?Rh`Qyc($IKZQhz+^bqt>(*0oW@F@D!pEn$Q|Vw?OYBkJ0! z`dwSKB&lnDYEsu$ElKK{pUSRr)X?!&OKOKNA;*RIM5#qb6TJ~IxYad`^!JU0HH;kL z8;fcf8H0dLL-<>{YEDhCm4lVTy4eyOAxQ%ft2Yp_rO3(hSj*w{>WTTaFfFlYr>Udp zj6{AN>yMD_Ea0ouUTIr@n4w-w_dtXUXWo(|H(f{hZYRl2*NF)GsEF>RmQ-244Z0ax zKvz6kpw!*&h(Ay|x8fsEK0)8y05+`yaB!&%%wI zI6Lqh{VD?XSmHwjC=FNFF!H5uEHoMQu$>*|E~;UKm!ddl6LH@^r-l(e_=C?AqPO|y zEUIB-mhW$amW$XQ=Qx4^jmok2#-|!U`l*r(GkQC2v%iNY#N@<&{GV8Eo=a*VJpnv zDWEDy`0H8iuO}~V;18o@%u0_|;RK2i>yH4@Qer8Bwr)D(+`>3k`vzM&N!yfdb72iU zSfD%^95eW2Tndj0kFG8J8+dK8!hQ`Qh$GR*J%#^a`&sCX<6kF)6z5c5@R>#r1dKW1 zuPxM*Ip#dICNk29+enTk{EYy?=ipFrov}PhcvC6@?OG^2Gs-)hSP|k`1SoyGcF?@& z`w5B|096o58r(nBl;fx^oVmP+*k{U)h zTuEO*P(JDS@K1i+2{6dSQl{d=isZ)$&im`_bEVjfswFjy^g+ORoZud4nYJOqE}2og zjYgs(TQIzKE=D$6HsL>y$z!-H&N92&C2kYm0`yFCZ#jJ7@-kv z20`-~a`n)EE^KW=&)iG15cZW8e5@z8&EtVTK9f`y~Zfkf?WdZFJu!S6OY zv*ZT{LSP3SL8+jkkn<^O{R#nn2%LU9eF5%6I8K9I2GL+|Ks3mX^-nA;beR|*<|ukjrPv6=7$rT zENbJ-TCjnF3X-;!%6q(Td!rQ?N!*Xn2q((a58I~xP^fQRIng%szvyRUPZ^T7vHzjw z|6h$H27E9QS0ki4>G;C6WTBH^L-QJhEZ;TPDZwE-tgv-{&13K~U|%4fKv1~_C`a>Y zgrAlR27-cpTzdwd>JQt$hS5z3F*9R_HcuRU%>e zjBV|7f%EinwLQp3gD8Ndwo^Qef@KjROA+Q^Y$_4BFTaKGAp*xMIDUd%I4Bp4@GZ#0 zos;9s@G3%b`5-?>mqS{=o?zti&`F+rgCz^=l7odi@L{9SR4zb-m%bA>pW}rtcw434dGd{AtpSxYsvo|Lc&ivkXMBQZ+1~6qac#y z&5TF(EA)kf8+qAr#Ae4Mjl4!hNSj@R7<^gY9H_v05X#N+CdDBq+b9kN)w#&r0@|jn zAuilF(je+V)^vN%>Cz`s*gDdsbEIRJc%-B#GN2E&Uyq0k@a9uCwjejh6nj&>llwpr*GpSQb7)7z zDVgh*1hFOu`cX8U7Wb;+9#m%o3F0|L&6^8UevKbH9__j=@3h9lGDUg zhcSdu>&-_|4!7k&J^QDXoyVbtEGY9^Rk+>>>yC@I!fw=i=v22!qyswBu_TfT zZE9pgZ{G2qvfiM4ns?(ODhhYtmF)8OOK#p* z$@~71k{c5xt)CAqqQZ0+Zk9A}Y8*nwUK106&f->F@blg8d2~DwabE;tt$2kBQPU2C7ygZnFUFX!6k)~~Mpuchhbd+_ODoGGx!;n=}G8bXJ0@ZfaC9=Ek) zDBcI-74v?8w0T;)I1fb=lEzsPXOB1vM!ly}jwpf*GDh>pWf0cdy_sc&2qYC1|w!wG8Ur>ssl6Ws391~~EuEJqaUNvdj zq-nFJRXf$==M2Dp&ZCI?_muH7XO6ccA2DBrc*g8mQ{pHO9c5}bJLMC`vx>=>Y+}YV zJcUtRF>}r_<7Z&km^Xum%F#nm0F*3w)%!#^ocs+wIs6%zI~@K(eBYCULNgY`dokT&P!S=A@cslX}NhDsYB zhXg)+{FCI*>qG|v*>)_|3hVO|3mjb{Ma6VG%JAWcbLq_SGf*Yk;HRsD&#~U|c7u;PIzD># z>={*YeDKBlRnCkLnmM6j(xi$>aeU%Utf;D*U0D_H)w#5|q*v#;-8#=4f70yA_HmoY zCQfHbX-U_3yUGe2RaF)3UF-4e?dD`Vz1BeN-=QJRCvrIk9P>IF(n;s{Bq8a*i`!ke zy@TJn*&}M_Ws7{LnD)Y5*VwAVdke_cek%Pr!#0s%m zJVU%#{JpqA+$g>vnx-4-H4QiLZ}O+(h92ANEFL7D|@PVxwuX=?KR~4lWgw# ztS?jSEcOwP6ip)y`RrLqaH0Hnil$u#|2wjGia&}CaY(V9{lreS*aV25WrO~gX6yEsVXvvSN=A4w0eFTN#yBBnI(>lr0Z5Ua#MOWL%d&|aV=y-Mj*f-7*SCCkT8qu_)VXvo+a(BpY+R^YoDF2i4n^qM3 zeDIz5-<039qv3yF{x9S=?P&P-$nW7q%=S$?8ce5+dUEAA?P&Pp@^_Tqw4>qgCjX)G z4-iL+$A}f;G;yJ5+R>=zblPZlh5V)+4gaO`ua$qD_y_s#lzp%Gl=!T;l|;R7$=)V@ zE}C{U+QAc3HV$F2v6w6FFLn^SkO&8fW%3^(4wL_Q(X_4*uT=Vc@l>UsC7VzEb9?+w z{?)Rt7O$267TKnOh5QfD#(rg5SlG5(mHvwO7x7(jhxmnP+E^&}AF^FM!ODI#5F3iQ zVhfQ^x-wrou|(`H9zvpD1I5Ec(}qSlzP-TmQ{*>oX!K*T{L91@O23#ydX4@ z-UukaiPc`CFwsyJX^HyU+}Mz&0mL^?^^L@afA4f z_=xzt_@cO5{8s!y#BD{ZH%-hG^Td3yz1UgoA@&vri${ulCWQUv)5K(jI8Efk0QB4U zIq(YEeA$@(>qR~(K>H5y9+5xX)BlvXReVK!SLBbo%=d-3TjV7N{q|xAm?1k`KG7Y`SQibsp~{T1zum(7>D*sjfq0?w0ty0~1t zNW4_MTD(U5gZM}BPVrvx5%F>Hd6AFcvHds2zlwa$j{fZ;Ut**Et;m-EX$M-w(8w_x zDi+2rVps7X@lcU346^*m;)UWR;tk?W;=|&j;-AI0#jixFd$8VS2&8=<2M>|mUmP!1 zhl5c!g-!Tc{_{_FXUkZKBQPgY-b_ca!|j zh%bn*if@STi64odi(iWWA=>pD>QBXYA{z%WN6Zsji-lq*u~_UW+T1~?ufOavahNzt zqsst?1x8Cey{|~ zXc?Ev?jas5_7jJQ)P-a@zHvt$FHROu66cEZM83bx{42#ZqFo2Wf4%G*#oNTYM7s_~ zzD=_E@;B?Vxs$+mWPc#q^)LK({R{HVaOQ6;HWyopg<^ZLyLg~DNIYERo8+wTM3HZc z)3!O1z{RoyE#`A&pD*%Fa^}BTyhFT4+$h={Nyzt%>=(rP8qV*^|DkAeBcYtljReMc zod;qHMq`ecC)U?=<{RwHZ*wDoHU|=TwESbmapDYdj<`Uy>s^%N8}6*{5^)WQbF0mP z1phkuP3sx{4YKbP?Rpn}z8uebUKZaJ|0>!XNJ!rpBt{+vbjjz8K<=XD^M zBj$;5(X^eBP8k5^>n#S?r^96P&3>j&7OTaDqFsj~eYNc0i`R*_ig$?jiw}!@<)8Jx zD)QBS+B-$Q!cV(_$XE4gw-xzHKJ7z9zJgDCjEJu<|CClWidlL7{=$0dUkAtKZ!5MF zJBhu-K4M>Spm>-#L>w;K?-uO0?6KlhafUcYtQMDwXNu>DE5zV>`bybr#dYEa@lG+g zp0oAGJ{YY3e_qQu@l((LdO_zF7$aOx+izAt9Zg%>xD>UeHU2XnF12jwCI(;{mje)D z2)~q%`&RvSlOL20Bc01&grIKPtB}CCwSpx`8vqBso;ZD#F#I4~r^CVD+^`GUuZ`^2 zD1@L4qRxBRDfr4%umoupa0GFtwZcv_V;}8~M_O{bPYuK)@7TxKF5BaJkktsu_5HS; zodG+!zD=kvjzrd%ju7;Z zzYzvy5Ot=v$2MfgwFGIG!cMMl+h~9NSRYn9QQvilvrI7pmsz;Eb`w6!f`w@e8^j=A zvjg|7=gfO!K_3uxE<`>Ibz9a@DpAJ?9>!cxpOW zeo@c4XOGfumid?UoZC&c27jXGy!_M+-=+7Bo-=srhVOE=ZP^oB`@0R$OD=ePSEkos zWn@>j*X*j)OVTgj@Lkis8JDH4bUHgbPdq)k%PDgYsdO@~j$L?1EM-?L-CY^#{ibt& z-oa&84s11W)WGP_62j%P4zh?-SieOdU5hRvPQ} z$lgueFYljM*1qh4vd^}@{YiBHqi*Y3cF>;C@uho0N4f_+zV}S`+pQT;W{zEPRo@0{ zUhnIzi42JB&Wscwj|Y9_u6sfqLn}wN$XnCscKABxt!%g};6i+|5cT)#B7E9N%X74u5=#Kw00E;gj=chU4F zdqZD`cYM$-ygM^o0M+S|JyE2EhtTir_@LO?o#_ykG30e!onE^ryE*R~=k7|F%%CZe`u~gjy71^t1PdcDa4L9q)AYc4vCt(l58( zx64gU*%eAj-xW&l^!yTYgT;T0=J*VTrTLy1;z2j33+!{NucbQYL z3%bN^*H!)B{Wvse&(`!cn;dUo`pT4nO?P_Hj4kP_-9v8w&M7`riQyg_v{j*)G_QL6(K zI>VF~3ybW~4B89Xjps(R+&2Xl6!k^=$66g;v zM;noNV}9)l|A36pBA(7T1-zg|yqNI=nWs4CBF5vW2U^7I80S66NFQH=E*9R-X1>8c z=n{8eiEuIgM|+?mH#`rWhb}Su9o~U|&?RO(g{sBWCGH8sbcs(xnbddDLFf`6#W>aX zpi4}@uS9u1Vy6EqUE;f7XN<%@=n@wr6XftRII|ygiI0aDYIshVcVnST%%b5xv+`S8 zv_zb`#P$P%8{_@xOvb|$w}37&$1{shtx%VE6za?1PXN#*W*luum)LJHoWZ%#piAtV zF<+0hG{-m7Gx(GWbcua4&?P?BDxxm&XGm`F4*pGp%hnBTzl$2FOZ)?T8SU^d^}tlW z0w-e}>+3BuoY9}=K{8_**J53uOB^)*8dvCGnOPYpv8RW~%*klMvWLpd%jn65`pV4D zxSeJD$&4rI5)VNe8O^X&p-ap-N4*0!CUl8udekN6y-Vm4bH!kXGB(g2Asau0GXSM2IV54OU&agNtf7fD4|R2uRubV*l)K_hKuiV z&?P?A%J$7z#F}5u{;in_U1Gngff+Bc8*k{y8r(iy2SRY1ayf% zqWNz6Bgh1u)C`^ipi9gnn7YL4+0X~t*{Dm*4zXwx`^UYd$qW2PKeo%INXleV)6OXA z>k@Nx61v3x3OTuac#68jpV=yebKhgT&?WZmSnf_X3|(U1PS52;qSPh!%V*^_pbcH( z{Tr~OIk~@Me&`bW>BYI(w4qB(F;VIga{^5268q`BeC1W>5+7yheR4~%64WL3PbGbG zFQpA#Vn6@D+-jDGF0r3}SZ-hTAG*Xg(Obcg-1Qtr=o0(+hvyFDfd^e;4i0sRIdLO( ziEScz=+W}HqAoEHCDSG5#-lDVj}g-)=Fe`_C7z5PnlAC@tP;A!+$LVZwn*;btOL5l zm6pSFiFqja8>tI&C2b@#**R<^zA+mKXCXt5%kva}$VkdcSFk<#TZmsDciY-bC_fGk z(;?ry+PMU}#P+iV^ip%Ude9~IM-WQY zTz}{iYmY#ST=7Vl)#veJ!*q#DabV;=4;OWbY2b8W(yP=Z_U&ly3RVqWV*A)GNOu}A z(jS@CZC{s|^0m3kSQT`M`RT{1zF|@568qaRoO?G{2)e|~OkLt-+y>Ak=EnqeiTTzs zb&378I4t*N)^~QO6F=pl3ZBcGFsbK+n(v06y2Shumb%3L0XH?*V}9ro`*y7^v2QQT zy_fAlmzX~m@Qj|@j}@LD%DUbh&?R2N9z&OyJ@BYYd_C_J9XN95A%(icG&tsaI0n!q-eop)iFs0_VO2qwm>Y)&l5Ag>m}i0(ommvR z#N4|G1$Bve=7TOVFF&bEe4&}4aQHYlpi4Xf#ah0N?Nh5u{03@iRgHX0 z;^Q!+fiAHmL;Gb%S|fiO z_fZayM2acH#KpZ8m-)U(F=Hd)Dnn??hhN!g&AsX4fIy^} zzV=9_d~jhQDuqZfeZ1$z=YAzpOjkFoV;+J;is_;r^;>k|bwPKiZMg?f?|le`=zs%} zVs_*e*!*#~kn#l(DWpMh78R%=qt-b`{gPt3a;U(y77(xnlNdE7CS16h6)M8DqY7_@RRjFBU##zNXA~ zFzkcqJDFvV&Hf0@jf6d%zJrdSu`)AccIa*Vd;I!X_fBa3vFY%yN7ls`|XlEsSpVR(z1hv-^Y14=O8%kW7w&_Wvcc6B`fiJ*nEo6FX8*{hJ7c3(>{(8 ze74Uo@v4>h04eV!O8CAXVDGUKy-?!#M2YQIVgc-V^jWWb--WQxLvT9Wg=4TOO8JX> zM|OuS>>=;K%cuBKXuJ$#C?bPtJO$%-h%86oJz}Tx=kWXm))s`$dtr>hJ+v}}&auY0 z*NVtrXf%N_7^w#%bdJMViO6peikjo{zB#(!+J9anhO)et)^vL$J&Qa~BRE}{k9>&O+bE=R!cokc2_VmdM` z*B#rp;}LM*f*dy^bUYZwtc3eP6nDcz z2%VT>jTgfz;yrSw3mcz(F#vpWJ7Hjw{SZ5+&iG=w{+|8cu z345*G-SBy=wL4C@p@?Uv%wjc3+gN8rR3YTz|w zCB06=2f849tY6;)=f7fj1>#*antS7 zV?JI!4SnyX(m=26vu!3byn+|b==8Wp_!YeBSJ2bSysk3cPUotf zHMGe|UMg4uGVOEWXC6LNh)&2$bySjN!_IDZxXHr4p%n6)L<(c9KUv|;Z^Og)P%VD_ zBZ&D3kO;pM64Id>8mAyYE04Gs0Sc6NE@6ZnNMvMB*lxm6+w2JBOh9GTRm zU|{O?G;aMHMSO{X3T|G)$TtYkIVJW4en!4G1N~=2{lB?>|8HKB)PFxUssA@GN$S6! z%Km@vuiec{P_e(b7%MLIx*UZYJBw)*H$WWSB+}(3vk)N4y|{)E_7cjEPVykLe9*@r zE$AZCf*uBGK?j*ue_=iFhe@skduR>xJ0nY)obW* z#t^*N!ugQ68^PLP@T%zfGoB!D;K0(1MqSVV${UF2oR$V*D&IDeKheZ z0@jZ3yI$#co$rpp&u(9cfMaN34I_LfAI2%BaJtDi7S%BFx^FD5VT8W`Alv*JuJCpQ zeBKdM^TowvsD=@q9pNXU2^hG9Jjp7&T6#KwbD zAXR09BLekqLyqlMULb6OZ?F|T~Cp%(gnDGbAhF&J7Wy zGrld!X8c2hM$SA=fzfu3B*UT2Z4&_$qwy4^nTB|9{3IN~r(<%Dg2O413ANkeI^jsf zp7go^w(Fe8^F6Bom#|JdW6=^tdhyX63`UahJq}g-V+mx! z!g0I=p@lPd;U%HIZTs$D>F|HcL-((eqfHGn-0WvMrG6$k+SD)u-!Mf@i|S{Rqm9W( zKka8)TtAZ>ZEBd|bwAVmpUuP!+kPgKO0_YmXnroVaOTx-ZVpZmT+uc)%)rwpGS%;R zZ6;>mDQRDs5*@b@#Xr}Mw(S-h9ymkhPQTlXXSr!->a=-6Uy`bW*j$x)3bf|7kAAd zyZ>SPe*JzhnRWa(?!C1=3O>@Y#RI4RZJHmN{{uTXI)NPzpKEBon~l^6f+ruGdizET zvTFCa5w-hV?X_~EG>bqu|8)Mq6O;+;pkQFL#kvdIZ-;^@DXLI>hzhhXi?;RWX7Xf{^W0IjP@JdB3Estz@(f-DCV*ToVSIZi6;iPta)c z2akPAW~=6W^^=yWu_;; zhNj=IQNPr$Fy`d-M}z~*L1eE5yZZZJ8`VYbkAS1UerH}+RqO+o+Fz$quoBjPKcV(Nf1A1+0bdCT zb|#Fxt!$gV>L(Da+D{0|x}j?jy&eJk?wRRNt9 zB~7Hbtb|`yld~r|6XysBtA}P_WEs%tVH}oih`*a;2empOdKr?=`yrQ(_v<>NX(2bM z);X*-$c9$T4r-0;tAY&AvkLf=QqV27!5boh9aP}BA1WoOTdrmO5(!C84`%|_xX`b~ zy1^Qmt$w${`>G%xZ6YrgU7aAtF9yNFOTIFMsR%O=W+BW$;GO6k1Rn532*n6I_4PvF ziH#4!@Q4f!r{HvkqPFlD;eqiJKT?DJh`Ua(B>T80Jb}Q=lVI6~2t)AA15sOoGs7hG zWhz3j@GAzx3WN)j{Fflkunu8;lK*DJ86HH~l;nR5afa6s-b(U+ia5g$2%)6$4E7Pl?B?i@b)^-Ouz^M>uCemUrzbzWsK@6y%{M zzuBMbq7Q}d^EuyzO>mLU-sE?Q;6G-v;H($ZOaz~^UNq5k7BO!&=edwHJ>~7wIK4u? zx0SO(G|B0bgI?xSZJt(ZSdg!874`N&^4`m7+GH4~USP3n=5l6*d~b_iu5~oKD9XtO z5@j2=sb99Ml}+=mn(G##iW1~b^A^TYO{({1D456Nw$t3&xiW03ji1bw(Vz&c6iIVk zn=d2VYls;$yh;oOrX1;p88=ReN74$SMW{alt^Z6-meH8=Zp1MMLPqPK%%j1)nnvSI zO`~yLFpb96eNUrtef?=P+I!EOW-}A?h%`iXF&lf#q=89EFl24L%TMKIO!YoteKxHI z-BItNQ#q3Dy)VKx2SE-xoE0e;5=o=k(I(Hp)C6)Db83bT-UU{s$otajD%6A+XJJB& zCXsB63uZOIL<=oF%+u1jD3XoAKwTV;0!@CwxjBj(M{<#u^Pw~>Dv7k~$UP^wiwzv+ zX{npxUrV={C+2Yym$Y~!_sH5NxPiU7F6N6#$7C&Om=uCNElBQJq#gEW^sS&y-wIgJ zW>WAPV4j7j_swDqe#|@1Jp!xgPd>48u{-7n%+lapf~3UU6LEN2)5OCzshF?@W-##t zH%#ne+pqtGk--trn8!nlsMicu)11b(DRBT^xY*zOpYn5Ied=aBGRU}cF~0G!iLpO7 zb%j4EMQStyZ6{3%QExU2e;OD}U4hQw==;L!gIz~+Qe3mIIVpJRhgGkeN6XBdP7!i{t^|DWG-$S_kV@ZvZgcOl$7tson*PQ74`sih3`(JgSn$ zj=L_#4nxB2b&6XQ5AiPh|M*lE<>jM>4(T^!piO_^i{Ssa&SJ3-z4`y_#1?Z)x|@#t z#D8{r3kb=Zg#Q19(_947|29p>-=EgvXJ)Y|H$8rvKY$yy9HX?bw0zol=hx{i{{7Qi z{O_ErBC-GfJ7%ruH*zp07_eDoX8-#puNYC%9g}oaCe2`B^IX*K%|ADx1*Zq8ofzi7 zU>b`$vn=4?!XzR;JFmrz%8DuFoUUl(pi%$Tvs~2aSMBT%?4X?y{HZghR8&vGR3V(# z$SEH`X_E8LP0(W3E_iCRe5%9$m?@>aiqk$|8j*RN1w|93%*WhEn4f{EenM3>=1iGh zK4Uy4St*}6p?da$iNX9S{&W&Rwr;v7VnC1T>#@#vsk!e~yDI`cODyQa+erzghX zC~GDtj_m)kX);W|Bzc~UPP`J-!g~+~=kgD-^P^55?D>|>4$JH&o6M+SB_T+-u(Ha=7Z;>VV3k&n33ZbtGo z9}=0kZRzhV_7lrQ{<_BWW5p@r43W<|F`duwk>`sSi)+Q}#5+XZ6J-9!#4RG98=?PW z@hg#oL4Uf)7f)yhb7b%}VcI>#0pc*RLYymJE?zI*Ej}vp{vhjnSNvSuE9UWz8`2LD zdx$5A3&gX;OT~5K9pa5o+_RvULmd*-xqg_*|^`t`r=|2(KLGDA1ZsSXj;7RoAxev zm;8^5uZSOrUyBj!_-v<%SSWTE2Z?;toB1lldE#>MQt>+RF7XMGuS&E0$KrS5mAGw2 zziGsR_sD)yd`2qmgl4k$6FZ7FCkFEK z^-`AWC)!*Xut&+BDb5vbE)2w%(MC95{)@!R?@fh(wmc5pO#{Q{Cq=|{!+0QiE{mvK1BZE;?eR?Adzpn z?D-3Mn?)P6IWpik%~9B#Ll!6b+ze)U)_?&23rO5Y&?Dt6Y%jVty zKa>4~(nI*F$bO`gNN+@h!s#dDOt zLcB=+OU0|@zefC{{C9}=h)*j08S!QDb@3hX193Zv_5NJ^K@8)IEXN^-#Cqk4`^mq* z><(gg67?LU^dsdTCXSZ>1li-o86?V8iu1*@lzyJLQoLMTE3Om&K%$;MiVumKNvy}q zB-Z0~@oo7(l)YX2nnXQ&m7b1E2bRkcn~D30ZAjGLQFa%xH;H=sDt(0fM~lbFKT-A+ zv64i&g-Ty8|GDDD;$`9*678>(ys;Bb|+(=XwOq%{R(Bb7fZzM;z*GXe{(!e5XXzt#F^p(@l^2) z@oe!T@lx@2k>e<22Q*6>vV`tA7* zFooAmV49dC+I1WJg|gd=rJ`NOA$@>sn+p;4aM`29@nVH|o_K+HnYdcCITBINb+Z2` z-X`8JJ}f>hJ}>h5Gp^4YBA*YTyh;!JU_c#61KwCi`YcdqOU#Y@CBVvV?7yji?M zyhnUkd{nf#GEx6?vZ)-z_4`4L@VXv$s@Oo z${r#9(i}I{%C}HFU0g1%5HA$35U&!~iIjF@e<_PZZWJkrMElR;Ht~J&Q*ozAxg_Q< z6iopRb`RMHi~YnS#G}OH#bEB6$+AxptHcH3GVv_Y?wg>!i)3FZt`%<(ZxZhm?-e(S zn?;+G6!pC*JDB_CFS0)nKM`%tQsnd$dwvUsTXJmsSx9NQ1(w4opz?Hff(v(dg^d_sI$d{_KX+%0}9hIzjRBBUQAo7!&7UnUL}M~D>2Vmc)iNt=@uTr7LJc&>PfXmhk8UyW?L9|fDjZLH^Z zvHl!5l;2{y-G>6-ll_rce@+~m(-rwVeD`HJo7)v^ESut8^mh?^iU*1P#WHcII6|bn z7t7BStHp)l67dZ2Jn;gN@?R`}op`gjL8SZ_(_az45x*C0E?1TR>*9A}FxL#F$JkCM(e4Yuw);XLCC8Y4j7YgL+LhwT;%VY? z@m#U~95PfSV|kk!6}(IKec~qZF_CIz%pc4dV{@Ux-YviBmBEhjz6VHEGIBrB?)Sj9 z`#oU&xnQV2#{70a2c+T{?dwFUjnTeeq`nyKPef{q(GKbULNMp(0kRJhhlo@gWByY` zyB`AE?uUSP$$y_{_cP%Ci)^Znv3z5(x!6){FLoBYiM>R-UxD%?WZRr9`0O}A_IPnB z3I9ylb49yv0Y5d)*pHRsYSHdjz<-16o5b72yTymZN5sE~?~3*BPkb#u)xy|rmafP7$JkrxdyAJ`owe0p{XK}E2q&Q0ajaV+)eF)Su zUH1QB?@i#Ntgim?=gG`uCd-5X2{XvzK*FLDOxUp?VG-F>P~6dwl?2HmNdOTAcf~I5 z))i}A>QZ;>Qn#wDYb);7)?KT%LiM!^YJL5GzvrGib0-9%*7m3WH_s=N?>+aPd+z!y z^UPVA6;~=Atw?WlZ2x@44T?WiyjJlBMR^Ya{=1c?mpazps7R-Dq(4&JqA2exke|u- z4Zv*0o{Dsn$9%e~BbF$RA!1)nS9(uH`lKV@BE@PV_~@06`70FZe2(<#ia$}jQjsp` zSbn$S6N*nMzCeUrdYL2N`-*fZNBVyiLws)nKDw1-eq52><4Bh%(t#Z5Jr(Igj`Si$ z`iCRks<@g6xoed^L2Wd>D?<9p76eG{0DJxZ()KQpGWf6BH*YmMhLsoTWHV z@gT)Tii;I%6k8PA6jv#(Q9M=g`-*2Mo}>6<#fuexrg**LO^UZEKA`xp;-iXBD!!!n zN5$6_-&Xuk@o$P-6#u2z@jY3-zE>(xOehvB4p$tZI6-leV!7fB#rcX06%SIR-IMGq z#TvyH#WuxNifa_tDW0g<@jcs*HUDD8%M`Crq|FrDy5VEINMgK1uic#!X3cyDNrpeFVN z+B(cCh2RMVTIiHbM;c%IymEYaTrmUvz;iGzc{D;2OGWl;KYUzy^-yv;!FJXut98;y zdVkpgG0-VY4=bY*wA=3W3lPT)_iM7UJ&uFehL5d-q<3Pe=OviX!v&4*#^6^<<6 zGoc5^!Q(D`-2P2M|MHQ?{$W{?{d*i~EPD$;j^Wrq?q0QR5iwoKV-ffg$n1k0JbsEi z%4eI9mpsQ;+llq z3_rrKyn$@&i;VH{eVCOI;@h9V@tC8GiG8aiD||64a@I5UinlW>7`lyIhw#O~K7CJ> ztnjCl90{EjCWLo^gkUfPC2O#Up9M=`CzJ%@y}8u_kD;4^MDOWLA4yro1^ihp^bj+4 zV6R5>ZeW^z^8=*?YmkPM{#j&gz`x+&zF#0KGYB(9FFXjTvO~)y z9pU?zOax830tH#Y&{ctbQJCEuy$Ss+w}@#*TMk{*oB3W2r=|+2T=EAHnLG5;to5Mt zXrCLpGJFZLGm5;tdQ5ld+E6Kq7&Iv`4bvF9F2JgR&v0E0-PrGAu=WUM2CpTLAGv|K zOb4DpeQ<{><) zz>v9l2V%yJ@(QXb^9Ct^Sj16bzYmitR9v^v@Z8M-jcw&|v zA3bJ;cT+N$w-3qhDH+M*%kuCfC3EwpurHI9%+K42J>6Z&g1jABcZ!nnyvx{7xsv_! z+A(qAsY)iiUR>*lAD$B#gc0SnVe^IOW;4xMAB@Ee&&whiK!}YzDj|jU&gQ^CXXNqa zPI!URCuVp#m!qT%+%jYYO*$7nJ;M(l7CDB}WxfyZ#Wbbg$evYXnkfk8eU7@}%B&Nl zG?K@Tg{uZ~vLt9yW{`q&_&XOr+CpaV0uTtA#P@5FaC?OMmU;JZ#aHwc-Agp|H+Fla zZ3xT5U6;QPIP1f=N6N9a7&IyTi(XoRL6gFF*qy+jN#Q${isXIDe%+NNCvZ`2UXb&7 zw~{7kQuvoWFM{lhqWrv%$b661jpxzOJ^WBMX9+=*^44+0zaH=!Ru@5&@)!<1{D{U- zD$e5@vGC(j#;ZZlq`YYy(-T>9gdEYcqP@xs|4th+L6gEy=>Sa7r0_;=Xx#{(gaNkzo?>SG5 z-rFSK%so#^56WA~5xt$qGZ;aW@)%e;{Elum22J8xvudII<2)4d!MKq5SeKV0dvxgtHT4w6$}I6k_{thlA&{B*K(^N zXp-4$`LS7~5j5#DOgV!ljU_*VCYkcm7`6Pu2%6Lr!(-5-*=!F%lT7)97=u295j3et z$|uG6t9BSclgy>0Jl2zwhM-A?e@3i^CoqC0netgN_A88_Nj!Bk5H#s%P9uUQ8UFdP zu{`k*G)cZSAZXGGmLq7=3)0_%Vmzgs<0hLng z$t=5``H*7daoeWkp+0|qldC^>p`6UPeDJ(%u{6%-A8;BGH0ig%_^lW~Zn(&g@a&Gs zwFE(vNZ?`;%jNJ8G|9|hFxD6OVFXRm9f1}(@XR2^$Ep0C7oOrr_>>mAfQw)5_aZ@2 zPqHe4CK)<2##j4c1Wl?!?-2XN%V8o0X6<(0jp20};X^T!)Hk|DtXp*5@VsyzDKHbu*VyCk`1Wh^u?FSe%=@Bv@XwuP=fuKpp zaIgrP#2y3~H0flXS_qm%krFiN5w?k-NhSk9llYT*7(tUv27)I2oufd|B$I)lN&Im* zjG##-13{ChB^^f4B-0AM+vZ#g@$8k%XQ3>p1+)d?eL5*N2$4d)6$ zlh~?hKLI%I zgnEft_~$1iETK1mzxhTGG>MNgz8_f%F?hJ@eFu0#_aQIxd;H5n(4^;>!|Q(JSn^!p z_iP6ddK3RLgUrtizJmXK6Irk1=bVNf#CArFtk?1j9s=^5xeTpmy`JCeZ(w8iB&q{v zyn_pZUtN$+ArGLa&g8>QC7v{h6;U`B(*!vepanTV)ZijoD@WnXfFPEz1{P2-gd* zh)VU@WBW5-Sq?5nsnd1yE#PhZ2T#lkD&I09mEy)w| zLcb%=dd^>6oCV4gz;}HkC&vp>@4RR?&dt&|3zTPAk_VI12Sm|APEJ#t1>kuCEzd#H z&fjiiVfeZ1<#FaKOQU7M{P7pcq9?fjR>YaFEN562%-=e)G*imzIP;a|R?C9<`zcw@ zAa&H|UXMys3W_e%}75X!IZX?ghaTX}gj`%s!%njx*4@41v zc+OrQXMyrePx4^?Mv>RDMdfoIO8dIA=;VS%zQ*K@7tJ)F4NSLs<*bO|nq+1Kj%Q}hmJc@O^n=AwHIz(8oUQwir@Fod?UHdU#S;{TTcrR2+mQ%TT z9_q(@Wub1kNO{T&?MD{;M&xBb+K>6late|%&v#(IuOLqr_t$Uxu|RqF6RYst4<7yw zTeLqr{7gRqy(EcbF$oBJ^ztNtVQ?PGVU zerPK+d!b`lA)AZ8r62QE=FOJnuU_aUWZ9cL;`4sYSC;3Il-|FFnR*z+0Nw+#GyHxm zQKnCmOt}2MPo{C4&amH)CCaoT-m{r`zd#jdduIjqn9de^yz^Dii!T3ozH@ zS#NpPdZE?i`3L(w(T}r0d2U3~w2ei(luUEEvXlKdOO%N^?1l-;{}7q>=NNbQ<1A68 zPm)a7;qQ^Dmd#D`<1A68fp|M_Bw_iZAO=*k-_!j#OO%N};U?!}6qz!~w5K0u3Ff1o zyI_`G9oYpdP-5q!j#a3yoITHvvjB2=KfciNU_SWs?f^#2&ECt8vp{+7M>07d{H=EY zR!*+{~CY#~!WHg|v@XNfW~G+1&z27nmA z$KLD%{WwdMX}=^B_Qy0b@jHI@p?;htn2%dI(Tmb{IDgia`9PHwta37kQRBy1pmMKu zcrGN*MsD+ZKh6U1@EPzaB&CCR(H**vOf=ZbZuI-JLBm_DCho?* zcq^Wi6ag{dJuYLrA7_d07yB<_82)aV*jo4*hyQT+AEI!`exComAxsTLRsx@)JF{$3 zuZIAK;Il9D_zdk&?#V~$i$I^vJU(apyGtH_d3_F_A&jLtr3W9aKL_~<+5U*x@ymO? zj`Se3KLDSheCGD2_Ph>xdw`yb&#=KD{(*iB_vZ&b_TlSyfnPe@-#6IqjVk6-KcDq? z@_j0kUIY1{x{MXp#|z}8!bAm&y_}rga{>?$8tTo)nUmQAIZT9mgL4vQACo6lG(1vP z%$MLv2sFjuNqD++1;XXp?B2}J9RzXI?u+(L9#i&dwxTi*C zl7LoZ?3IiFrX0NsytU;V7(0d>_r?T z={7+tU_mls0Sc1`P6r6sm!JY7j(`XSSpoZQC4i-HgY7cyw-ply0e|x{CW_)jbUc(N zXa@`)oYU!t@`~C^{Cc=Q|_{cszq=L+M(|gMvfX;W=HUE zw$SOUs9T`fW{!-n(q)aU6-~|Xf78&^&{lEe=rZHRbSqD#SlE=OQrx)JQz=qOPo+pF zJ(Xh9SWl(MR!^n4c%WYuO5r*{s=B$cvAL?0PO55eSk_k3(8Q=WxbWkt zLbhVyR~}t>!ntWa{1J`|`GHk)LU}_5z*S#SVP+!13>IXT!BZ)n73K$4(s5x?C`vN0 za*_~P@ac!lI9&MoA%9Q;zpD6tb#rS)U1fD!^YYdOqsuDBmW^WXrZu$fTf1U*Q%&uv zh3sJ2s0p5R_SZ=%xa*nC7oE%t5Y zGEV+9>;tc2D>sI46x9kBz8+nY$$Ypn%{s6iU8mJIw=Yj?Qf3nU*~-CT-LmFNBdwEN zg)ptg6I%m(Z#6Wwv@fr%Xla8Zt)|*lZFP2wao2KtqFZTh5WkWuFy|tm@nX~8Zfqh$pi)H$`#a_CT2FGr)M&i)S^u0nV zyG*F0T75)ZmS{rR#8FAQ;}yYh zZzYZ^Rohs*d`WFn^-*bk;2?h=a#XfGDGAU2sdskt6TNr(#a0g3qi+)gZ#8U z$dr=F8L1iO)?O-8XBkGh=id7#rk9OR$Q@Ab?`5OPMkj_ZuU%GK*;>0(;!xZzOD2?5 zEw5~p#+QyCb6BFJvAU&wa&`0aw%S!CjblK!)wefR0qc-o*Ro#9%GL(#{*t=7_9pE1=B5%X4zU$^@WEH<(seB*)y++9%W+$oj7{lP zw2W;{n=tNtTrAu*lYMS3_*@n&j=knL;{Ma5gmI)N?ipoE;HqE29`SlAi)kytDLs=8C$|Z=i@cheGrkI&1Q&5U zaV%>PUxd6sS5)jj4_7LnUNKr%G}L%lJ~_Ee#g)}E$9A^(_z8Y{3AKB4DyGeAtZn2~ zrQ*wY*X-mJ>Ug%BDdP$@v@%3_CspiO*V#$NJGeWQc3qu3dqJt#>JiVYsPFs+t(TyV zPdz-(x81+gNbnqIRt@)BY}T~(H;cuMJ#U}sb1N3gK9Y-lZ4)k-xU7jQP-lI}YqoE4 z_f6#`v9%uOd4hW)xjDAoIe8*$#i_^VB6r5j&U3dDZy#)vXEBx;d%ubvFq^CJIOX1T zxn`YsAa!P*XPKE5af6w8UuUOmmj%qJcb=bjX$EQ7Pxx+AD5^!eNFB^Iq zJ5Lha*L6)2bs}{#@ua}>zn-iWxI@W~6wj|_r;00Wj>5f$;Ca2Ny4LJP^r;2UD|HR{ znqUTni)USPX9L%H;kCqk0 zUjjP^baowz^6=}Zb8PKv6)y;#V{6~6h2D-R_wnI;(--SlhaW#ddQ=m$2kDMGJozF7 z4qJlp|E9>F zCMZ8wF|JswC_ai%K2zysibpG+u6VxU&lT|-wa9%)QEZkVXOq(ZQWRf7$e+TujzEd3 z1QZ)4AQhIFf0QDBIVXL-;#G>bD?Y6FoFZdGk^dt_AFr}VQ#+G5O0is#8o|sLpFF@u zr7u>zM)6L?-zkQ0O0k~!xS?F7rz*}@tWa!HlH6lyjJmU#m5z2R{XQ#r;6Fw@N91f#hn#*Qxsn^C_hB$rHZQ+*DHz- z81RYD7a(;~Dff4ZN8-mU(#I-_j}*`sD}BAl<%)dqaRQ`q0Ojth zSf#jJ@p#3v6fal2Me#w!XBFR8{JUZ%t_74IQxxAJpeHIlNAWzxs}$c*+^i@*T~Y5K z{7yo7OB7cru2noy@qEQg6o0D7pXONqCdK;|pH_TJkw1fxub-m$$N)V@X)!SYy;SM- zia%G}sQ9sBA6)Y&Z=$03N(FtK(pM^qZ&T!NQaT^kNY)#zC_W`Xiw_ClC7LfjLP5Wy zbQaRASE4AsIgxHv`aH$E6kkykADBoF!L5n)XDc=;iVp_lpQiNridQO%?@5&ZO6jK* zUs0sd73CHw&Qxqr{DI=liq9*G4+GR2fExT< zU2$JUvEc{b$x2_RC^q@Xe@y9@6yH_+hhhl#Lbg+&I8kwyqWB6#`58*zuK2Rz7mCHW zmr~AbMX_ZEy+-NF6vYM|`F~cr2X3^iCpO~1gO#pV{J!E%iq9*4s<eVT|RIyp}S1Wz2;t87nL#5AB{E6a~iq{e$_jaZ4QoK*| zA5;3biq80QoVt4eLg<`vlOF> zgA|7-mME4fQtg5DW-BgGr1lT)PAOSu^0B@7_}D%m z=`F)22>WS!*s^)ZaOKrN-j5-G^0=R@yhTXcI!JmgkVT)D_ONA5$gpXa-HI<4wN8dj zE=8H!?!U&Fc-3r|`L zk9_v9W#31JD{qk_54ZEAyvvccbtq#NIyj+ShSKczn<2tc_xD6-e-GDUZmEyxA zf-iH=ut7ao#?M`fmha_VI=99Cjq(BHn2!x)>oCLas|S&G``6}-7q`D;|DHt}d%guA z$2!P!_r9GAqB9NNZQz@aOm0EkmPKAZkZsy?2uUx9{kInrdRTdQWJu#X5&h%!)gG2_ z*RqMF;}fX^w$`Ic$Cj3k|Bu;Xhc7vPap)uHq=_xIzYaSame}`x5?^esu>-TOZlyJL zu-D?nR~@&tE%sbolXF*LCN8w2u%iOP7W=$hjJ-Y^>7*?-!xscL^ZP^67P}Rd1M@ML zDO>DcuwnxFDO>ED&`dy_!6j|6|3S%-&$Vy*?>9*K3Dfa`khOxHTjF)0L%uorA7-ZHv7E zU2$x&$6>l%TkN4Y53MaW-F9wmi%t6tV~hO@Op>+59ssdPTWp#ZY||E-UxXZ6>_1>0 z99!%mShKHci%mC!Nn7k%wwF0Fc!xaJIcPKY_W&1rzu-(dOdb* zvH8W{vBf?Z6Sr+!Y+Ca;w%7x)n654MXDt3Iw%FC^Y04H`<~wDJ%~uhQEp~wY{@S+K zzd=`%w%F8Ib!@T4LUJox>;YK9f8Q3H3b4_Uj~5w%EsTMBjuhHbauV4eNE%xcmaBZ<;9Fl8`O>@+5xh?jg+D(4#=^^rsrGN7JCVs{tC9(%^am;i#?6)ZO0b-6t=frTkP{WSl1T&`#iN=TWm(p zO0&g&geQ}0i%oygX|~vhvx;kr{Y#!d-;gc#T|C#m8Cz^#b&|H&i#b>S6Sy^2#1^~1CHr_0zBSGofVgwOZP;Re43S;fV%K16 zcVUbD0a>)f&Z4etu?Lao8?ePL#A(}gWIe|Y&OY_U)0dTzrOJA?g5+G1zo zVzMn;Z2m-^vc*0Q7sQk;_N|&h0pnH}!J z7Mo7xyRyYDV_W~eEp`pXY~L39E}k_>TkLDtx9!_vzr?NZ@7rR(&6c{d#h%aU?8+8< zGY7d%TkIh2;f^i#CSKUOvc=xQGa+S*ozMN#l`S^i+Bmk@yYm!DSZm(_uW}$MTWrR| zaBQ*pllhmn#qLMRUD;ya%|%MtV)HlYu57XQV3jUxu^(o?yRyX=GwZHwv3KV3cV&w` zo6U7)i(STkcV&ysz`Twv_B<|d7q-|BaMio8#b%tRE^V>jCet@!i~T;k)RisvWL{Rg zvc>*6cU;OA`+QDx7q-|7InQ0#VvFO0u57Wd;knS2E%pK2v0d3>(}$O9i~R*g<$rG* zw%C(8vBjR;i7mFVyS@m|_GjZWl+W4zl&x*C%X{$Anm<;4LN@xI^QZQD9clhRDYn>r z=Juzh+hP}kp>td8G883ku|rspD<%_LY33v29FwYUdu*DAdjCOt>~6d2Zo6vhPQu!Xbufsh8I*g5cH33|AF`|NM6DC1 zeeQNJrlsB1*5Wt>CX1M{tt^)5ZpFFhrEHY{qt@2nX}jvL;V49&P`j_U@V!pW0>9H(qavHae3*s(RRH&eFtr{E4nSQJ2-{G%Nx86?zY9o9M~fu+TNDp zJ0iRUc8+hWEw!1c|s#YR4k1U}ui*q+yIi;efkd9V!*80@yiHuKPJ zi*4qi+ZNl*L$@uqnTKv$Y%>qtw%C{l{9N8`i;a1J*1@%So+5VJVs~MSjmOXLdcbR# z(&7hjV}}e#voj@)pPA(tg#YBjqm>-4Jt{L;#$y;h&_3yskM^-0+vU&n_JBf+93$`_ z$~<1VP~EoJcAmdYw%GUCO@cMD{rkGM*qL9_7W<`Lx^1y}O28I-^jC?CJ#pfMQe(N@ zbzJNMs>Q&3#hmNIJ;ueJaC^z7jMFnOK7MiVqjfXhEcmHj84PmxP&_4zDmfQ+lN#=_D^nb9$mN>G0WDdW^ zWrVH-1b&9=0c@`4fHxx}+y+UAc}-jQz%%%VnAbHd35MsgBoY!YAd&F#$V}N;4?|gi zHk`1h-W?@@Lm(99(+9C?B=`=C@4!EpPxHX`B^t37v|G1ATw(W)7SK7zL(9bULjIB>yQX|xeR4J8FX|mWnLNP zS&dMM(I-h>8+uDfgtGoEo4+o=s)0Y_AIzt(LRnrg6g&(hLRnvk8agpZ63Z4bu4X+C{2F#0$22IkX7fEV4s)^<}e7-h_Fm`~frC3@&2C3B-& zAOPmm+IaL2BzIS`Ai9uUo1$bqdLw2E=F^6`fAnPNbi#bvkO{BXD6}M@tm*$P`fIj3 zH(PwcVb;+{nopBt;M3@H?B(7vFwhy%#bjTgG%T;OsjK`pxMj!)WliUCVm@7pgqiQd zdoj&5Wk4sGPn)g;qrauF%B*ox8i}%F2xZO5l2F#6AO&a7L@__wLMS*71VUNg1)%x# zYG9P=qA;Iknho)lC_-6lLs%Z}y8M?=O7rQD(G3k{trawsweo8yYePk%2UGT4S>quB zhG5ad&?%Tt8!{QndT(htKl(Gae2?zpc(j~#ACg%@DC=l1*8TN>v#=xxWgX=-!+csC zz7-Wm859eltlyN<;nB;ua8G1?E@U#4wP`3B%GwMd8Oqx9c~UgScAxDTfbMNZQF*k9 zqMqx?`0^P=$xzlt)QspcWPVxuJTH1F$vj}5_m+R%~M$EJLsp>tzC>%)B7)X$GGHVw_EZ@`lj zLs<`CIYL>R^3qriX_!wxEahWjSsWM4r%m~USZ|iYe3~Z68AX#~*RXwX~KU{ zjOP{2r+F$#DC<)w0Or#?Myz zi@f=?e0rd)IYL>V z!3Gh^dZc6^l=c6x$1tB}4+0EjeFwJ*%%>?rLRr6q5}Hq&41}`2iX1SXHW>(IjVDnt zpEel?WxX3SU_Na!5Xzb_q-j2FT6xm~3tZ$B_;Nd7}6CH#47OM9$wN|4sbQ<{r$>)(*hTc`cho zC~IE%5Xlb_n#FuNE+j%(kH7%%JoY0_(HG!NnNL?i%8n)ATbpP`sh8jrmY=u){~@;q z1vH-?2QJ?a)1eH*R1XIk3Lc67edAfz<>zcdD)tKGX8kXdbhlT`&iGRb*|&2+|A2YyuwO2D&w&0N zK1B@jH?=qW_zB35@flLYNuAbdHZMf^!N4i(U}a5*oWU*0^5$|XM^}<+8}=6^dNqb^dNp& zZcsk#7#qYd#|H7sO%LK1b@>^a521zWy|jmkA^3kjmfv>b^qi#f+dr*X zi2hQrfKY@_hSx4g{%xC!#HG@{1hxTt6A9g?0>oUz3fQi>h-KQ^T*UU~jB*O)ATzu( z=BEbR&Ifck*mGRYap0`igL2)&r7s0@z++_b?f`sU1`Yhy8hs$#!++E0W1EroQq~=l z5MgiI)*Xzs7tM?ZR+~6`CbS;2B*dOZ*c+L^uJrv1H-Lxl@5V< z5S=P57}D2_3@56Joy0q_5rRxiv1DYt&h_OOkwfC2R4%J!zzkd21pMn5fXT-1N;S>M zHH=16Taz$hoZ2PghKXTBb_pAYFiMD8lNK1z2B<^Pl4b3+sqi-%!4HvyBytAgl}I=x z+cAlIRAJ-6F!YSX-LY{$5Pe2EpkdRtiU-CKr6Nz+m?c2O=8!-(5*@}y@sT(?$%s9>`(*J{u~hlQlH4n@r>yM*A`GusR8y zqCtg9O-vw-m6#s9PDA`j+U8V*Mz-$>9zYy=av$V6wWtz4cK|40M$Ng-n+*>FZq zh%6g*rDISZF+g!cTBXH*OooDy4Wyy5zPkRdx!9N(L^dK+D!P&rajwF|+mWb16(%;H zH58IFKx6%-VmacpmccU~nX`A2k?S;A3>Lf^5#E~GTfA*5FealSNjy;-4hH8!JI*7G zLzIlg$Y3!?P$Aq6SOd?Ynjs-RT7g&vnpY?X<|A-;k5QCmS#21n-tp>Pf$En@f^j=6|Yvj zOYwfiClp^)+@$!4;*NMb!hVfZ++A^w;$p?6iYpXPP`pg>M#cLS|3~o)#XNoyLOXO4 zOdO%e*W;w;C?2d>ueef?Z;{D&uHqGnw<$iX$X^D@_pxF|z|ayS2>A)6B{mS~MM@u` zc%0&$ijOG1qsZ5qlpnyiKw>XNx{o7Ws<=$?XvGT@<;PL*-J$ev6rWdoTX7&>>rfuw zpb;l4?xlE`VxuBopOWtfikB$t8enooXCf^QalYaKii;Gh z73rmx@_wYaLGeb#-zjcZ{Fh=7*CgtP(T6KBmxw;@s92;poCx`&l^(A+N%QwqdamMp z%|BG>3dJVH<%%nbkb5!_?Mv(-&^K#7E<=)!ZEyOg$d^py=er-GynX=|D?MCsl47~y zo{Do77c15%9--K*xKifhbtb(E+<@dpdJp7QJ zkB^m&q{J|}6X%gVY}q_yxboIP-a*(Sl*hhUd5e&?b&&LmbJ0KSCwtg3K8x5i%NAju z4RJDTaw*E(c3(<(UIK+|m-)8cW01CWko1o00X`=5uw_SqcI9muWX=Q1$Y#?6p-c_;JIQEx5|d3N1UB`NO)mB;R9fv<0=6_jf>9}#@5{a_0qeq#XuJz{P=7db@&BZaAlJ`H{=cJoLr_QX; zIAi0M$hwW20&~vT6g*_(rqJrZxuK8Nm0vis$3^~m{)EiGtjqIu@jm=?-SC+g&%7=& zc4mJ+f9!@$tLF@v5&26n%lj}8Ub6Y>)i;0OuO7R3$stQNhgaW#^!Uvu9rD_y<*Qlu z_vhr3htc0DX?_mrohhgH)Sj>*p#u`{7wEL3pe?@4cnZtdg$iC zOIL0l20UT)3SjN#p9-B{`m<>(&{7a`UVi#Y{C{HRfj3W>c^g{$>;r%4u+2kP`x91f zK4taapZ+uQZowz-$1684LBE2lYc^lK^mXQ(@f&ckSEsXALG;SYACq6Ya8m@mh#Zo? zDZF(4rp%@Jn29Buf4W=y=ARx?j{Jq2!Wi3?hm6}iWT^+90`LsmeDcy2_>?2Pa8qdM zlFe5wy?)ww^ut5#XW7S`Su-cithkx|J7bdviB~Q4Cz0ba^yTBH@A=5j4Sf_0{R7n6 zza4s`e^HMM1AjR_;Gdmw(P8z0ixv&cxag|L30RqjAThDgzo=|x;G_JE&`0@!eYfQ2 zPRD28ExEv4U<4Qe27$p`e_{qW!5w)2Y5$^e{^%M0*<)uEd>9C3Z}czpC-tu1WpQZZ ze)UHz_DA%;|Lpqf7Kd)S_q`8)R6g_8nOD5~(9AJ2_jz~h%zNI&HkDK5SzJ5Kxe@fK zDv^5%&W82QX0}P_Ov{@3shORg|lb?}vbS5JdqB@h)DSRuP$tZG-&g3mfS)IvO(bc5Rr079z zOJ{N-2IA;UzK8}9a^@)1r>fj(=+9TxnWQpfQfKlJ3P|Zp?n*MHGs%EIdF6)r?c46nLLN| z_H-tx4U*ECl=)8SOuojRrF15rX1`N9lkC`6(3yM^T}|ptib_sOXL269xs}f3acKT) z=u95Mex-CKU*ytkQ)hAknNvEGFOW>>Odd%xr86mUQBpdS53tuMok{A1d|jQ%7bz;G zGr5@LHgzT$Ov}-k*!1# z$;ohZCV$0pM`!XkYP(KMKv!q7KQmmN zNyd0i)0upREBWo#nY@70Xmuu^#Q;(|lX5L_bS77Ec#h8Gz8wFybSCFQZc1lT!u2>h zlh?DVqciykMSnS+$vW;EM`!YXSk=*)Y~z3&oykI$J35oA*tDZFc`fBRI+J`k?CMPN zY1q}7{DSfvoyj5OcXTGFvfR~~P*sRAx&rUQF5GR zRV1M^`B!d#S7&lK_ue<8GdY9JJ35mLF8(!jCVACK>P$jsYCAfUw}bVY(wUsV5u|h` z#l{06XOcRT^2$9D+!sv_{5^WrL1!|IthI@|G3j1{-zNRUWe^CR$t}oobSC)?-0DpB zpdz7BoD2o2duY@rw;;tEZ<_k#xe!D3$rDgW^~sCT52{ZZdMowGBeAyIQ=g<$cB)VE z#pGcB6$tka^Ns%G81q2v`5WHY<~@9daLj(KUqG3| z`E-uY5Dwh0GnwxqgFhV%`H(V~m`p~L`V^T%TUL2~y~*nf@qb7D(3UFZ^`%6v*k{Ne zN~O*QU$i<8MBe`R46UrL_WY$LvmF^nFte6faV{F)$N!31D?R@R!^Nln;rI+eS3G~2 z8Omy8@Ll_mr5sA5$@~K{e#y)uApw~?oQ)dP4QH6GAzV4X$;kWy8K2=ZbXBS6H=8`Z zI^PkWq4Jd zl%iyI?+z-ZZr+eFMy1rv8;U%tqq=$6C-_#050pa%u_c)X}v`0pUO?mGj z1-Imcb5JGVEnl;NiHoKFzN}9RImu^&9Rq)|J`;|(p&;R?oba|J4 z;uG+|$OL;}8EtRK*zr&SL82}am){=fbO8E=av(1wnH&y^o$IdjKq8<=LW z7mOBkWCPQEl639{J2Lb%IVz9cH%otz%>>F4`OYZuV>+_U_B@=xPs}@WVP?@6I0B=J zkMstk*}?FV-+u!O*+yTNfhFVsBRb3C%Q2WV84k+^J82>B%=s9d9XJ)SF(!^R;I*d) z4I(vS5N5c%FK)917Mh_Sj?T#8yGzVzz(k;v89cxs|EiE!g%75Ya0NctY;7BuxZV(} zHZXCUA=YeQ;urW}PZJ(B`7Ilm*eLl634HMr@Y>dFV1mseegT2o9gPw4@c~QQ1}12- z38H2L6VnV)zk!K;4Y6#)G9=pY@x4O{Crkd(Yc?=pE+mI?S8yhrT|vsnKW+o|@j2By%^rYz zAL3?B6M1>a@K&$kNzDP+I>?s8`4LH4<)*YetdIVRTq5Tdn)qut8N6sPZ7&|!fV|4s z-C{*Z8~BH3KRJfuzuN@Go}*1rEW62JY)cLvWb~k3Zv#s?e( zy<9B>ha6~CMu-30v3fE~9@9Q&@=1Kc-byd~i!XNAK;mU7pHDE0+~UjjX+e!7BZ*@v z!dpl%OWo!tPgZOqUf|vqmIZ`A;e&hE+6_$bB*qPk@W1$kyf$z24jY&Z%4il6BKTli z`*J;_iVYeg@N&i)Wh0YUwhXUq1Ntimgm7|jjKpU*d~mxWd>2&;-gp@Pibq26Vo>_G0wQ0A_o0f7}GLp=j|C=V2n7mz7xeBE>Irc@Xs}UMAQl?Af%v3JiBSJQ$;ePBGjQM9wotFk zK&~I^6KES5%4HM1c7?cB7MB$k7WNM1LIlz=3J4tKhjPYF3WYQG3iZkK=gpfJSUsmS zlrsW3rN}ARI*Hmjft86sRsuX_LZPMpfvic8IxLWdVq~I-0!NMvTSyB<+DzK|vOu8vcnmI!SHLhv1(WKTGN&5!c$|TKkteK0^*|!D= zG#{Z6Nt%^P%N{T~`I<&TJeS4R#M%gmrAu{l^AQcu0H4;dL^?%79nrft))&*;m$R#C zIFhnQaO`=E#ey;HNW~X1+T^r4aLp5FZ~*fkYaW#}kV#n)rB6|1YjsMEy+X|~R@PVx z9kKVZh8uQW)Y!?I{nR$rE?-jHRDG1!vJWk7*z?v}7!ELTlvo&~%r}fd1nfOvl?B@@ zs~)dL5&u^#3|huwf;*a~rCGcf124{Cqs(B^E{WUKH7tO2!K#L~QmY1->zRFg8`F||{cCu$8O!@vX>lMBbd#abMt$!us+uk=PZCk~b}G8k*G zHgBKlb1N2lNjo-cd8U?FW+uI_WDRBR?J3izmi?AjJLYv_ipR?n?){Z*l{h7^ELEM^ z@0gQ?c3?@fK(XKHXlY{Xcsyfz1p_?TNMSK5SIH^6Y}}Yi*n?poSereH#dQ#y!t^Tb z%17rGTt<+pwOH-4!bCjB_teZ1+u}ZU6GImVH@XIwVYD}%L+96^CVlN+2v8+8WL8(y9k$VzfI*r^E7RYTg9g?6dQVr{zo? z4erX?%Blv>--(ZwN|@C*G|Any0|ckui9{r!O%gYlf3ez+My z?<4*ml05M8EtzH_px=yaW(zG{O4uwhQ2#B^}DkFg2?*Njc=KRwJDBZBfTu?f3SF5BsC^ zWr||kgZ%rH7TX@sH~~bi*!F-H+a93U_5j7U2RH|7BJ-eFuPC-XC>PrvpxE{R#kL1{ zoAQZm4`{LN0g7!8P;7gEV%q~u;A2Y2Ye%vDA~WU zihC&TuUMn9%L-7&CClqnHmUZM^ zmg|XZ!F2->yD4wn;_apHA zSZTgTX8oTk-lO<{;vdsM`XQU zD)Kcy=|>fxQ+!GB1H}&&wqbT=b z@ExgiyW+8m$19$u_yfiB6fab~T=6Q!TNHnx_@E*^a&jEcD88Ubl9B^{E_0>iWe$gs(7{Hb&9ts%5wtb{z~azE551tCq?Q6 zvHbyx#fnsmV?I@+h+`G$%a8OlMJj-k-be8O#X}UU6_+SBDK1x(=MdDV8Y$(RthiqB zOvQ5*`FkPxE?2xx@kYfv74K2}wIb~iSZ|{ueeRN`5;5@&#rG6HP^5ko%X1XzOptUR z#T^yt0FU`QD~?ngt2j|{n&M1F>RPehp^8+qB7KzNNs6Z_o~d}QqC8I_Ee09DYcyY; zuaK7KD&W(aFV9yn&JnFA1eM+@iWC>*ziXb z3l;k+CKToQ5pqkEmgh*&6O^8$I9+j1#rcX06%SRE=S|dKs&tcLyW&xb$19$!_yff= z6)#r2Oi{e6LhgM^|61`e#f^&3DZZlkhT?mQA1G4!j`JDdb1E=Lv4^5O=OTY6rOOoM zxfl79m7c0dB|XYHRIyrdiDI*2t0I=k%Rt&bPk@yAI6Vc&>2eg#Qgq2T0z9na zw(I_W&9&pPCq7m-Y2MRcMlP_{K!~#b-rZ2T5-V z_QOy+NT;mUNt3S@FHKJ1!1S;(DnYyLUNO@17K4xNlHIo3hP17Nr1u_Px+Iv;!Ce9LCX`#93r%Pjyo&Vf94Pusa5I@`m06nv$~?1OwOFCS^PY0nKLy)8Hq zc40yfE06EqT)s)@-^-Q>X!&3hJbrv4b(D=AH>z}OY3cZF*aRb##u&rhwM}r%U}-RE z6Uc{C44I9E~P$ z!6x)AQXS)H@YP%37}imn&_=d0qW1zY8(Y!Rf*Pq9jIiWo@WVcos~-w(#Q)4n^vDm4 zMxg3cRu3eJEp0jdtW=63;@79!v-L z)Cv1gPEJ1c(r6z_r~A=gvY@Ot(`Z9uYM2&-Q9hHyKGcwrXc!e?A8N?l=z-BGYsw82u-ORc4vc4v{E32K!J>md4be;OxUunICNdF8)CvrUt)~ z(LVGnV6=dBSM+3>4e_!K`%rBN%TtPs{MS)R`%r!f(U=-qL1SttzsA%sR3ti|vQze< z>(HsK?L+IN>_g>Ix+ob_!!(qPsbL0?jHzMTofM^pChSA|h1pPfw1uLc>$!`N$(R~O)Qo5w znP1j3Z(fw|C}1D@0;VjZC>c{jzL6oO#{2B^o4J)>%0Ntw_b_hQhw=<&ObxLMdq+1L zV`{KNtXe4lxLXSO&ZUs~SQmb;>%pQvGckB$AIjN@ozA&{eJJ^`qOl58qJ5}5xWi=W zaCQUsp@xpc`WSkkp>tzdtPlH8Q$H0`<2SeqWgw=;5SGI})RdQ+m>GzvVPam4iP5V) z?L$rZgjhfF!#z>i!Ba_MYFtYJun*-qA~7}i zYKHcqnRo`0m>N?k5-~MqVbudguZLpA%z%ApFX51w8ax%uB0Yr;JBuVFJBLMDgLb(jDzX-vqOE+r-ouilvOrKp$xz%DWjw{fbp#A8OVy7-PgK+J};vF*W#w zoc5u-O)#bgAFOE~YDO_D_7O(``_N-W-u&1G@*}3k+0xa6V*g?}VrrNZu3jP^&_2}A zEitichJC1^SH;${f3Oc7hxU0zkKM`!5mRHPWFV%--`Hcs)L;)Jrp6oGCWxs)5fW2_ zFL7xfYBCU0V^JN~O)F0#rbau2uvapth^axEoe~-` zHAo*|X&Y1HIAp~5QjqqcBsk|QI7YbM z1Wa1i(fPg3Lm`bqX+)j1#?r#xlZT?~f7{^!W{ zch6)OMLC@4-+?D%8i7vPfvI9-CGaU`PyF&+c4QVl)0oHB{i!+Z%rT(bna3Xb(JiLVL^US<)#4%s>PL&!3SieL6EZlzsH~P%<(sfeQDc;o&Bn#&Cwy8197A;I!=I z`;#Gr7O0@Q!)f%!t+}@!$jb>Ci$59<#x#_N7yvSqM_f2^QXG9X_6ImvVFwKzqGUg} zKF*p#f0!604seYPr{watx`A+|lec?L4y+VY(svvVqs0DrR!v9(D>?`glO~Dm(cq-* zW6m~hA5pTE?W3EA&E$mLfY6~G<7*5{#n%|_#MjuV>-ZYOu@zzZ$k%LX2VN<7uwEgM z#g`xK(l{_*QXp|O@WudQR(eG8f8{tDDj?zt*gB2|OJN@3GNs~ZusgV?;J|6D2m9h4 zF3tOPz~hr}x7o#a&FrF~37*@J99;&-$+)urcg!xf84%;wxE%)yp!*KZ{J=O^S*)6a zz!(FdRbNzyT&UQG0>kmbM@#|YP~Klnje9D~_eo&)eFvjoe3LOQ?0b5Klei!ZAkZ2OBXXw_#Kv7xn=y3-xC-_tA*tj24{I2mH*;AnVTJyUB}kgmnu z9U$ZD1;~KTyF?{P*LAj9@J+QVlj@pDg>zhJyb7z6o>B#O%pbl*Q83V1szMtz=IzG9 zNHZ(37A;*xy@2+#nLjlU=#GEU+>{tKZhYzZF^45e8mn8{Cs#Kw$1jj2jblK!)wefR z0qc-o*RoiWsJ8m<^$Thh2oT}z^5NzKa2 z<#i>a5+(bLPL$L&HJ3o0zM&emmNitiHZ(0kW?g#|?0cGb=zcIqSE!`%{BJliFyHRp|<_%8|tv@lIAS`Z?xf!zM88K&xb;L@ZoQ2Ui^g2 z6GJBjPY#>{P55tR%!>lsVZqeHEXi+U%!?TM#qZagU+TNN583(1b1taKr#2_tg}sp` zBVBOK{*!So_Jw@v&M#K1RcuvUt$3W`j}*^QyiDG+d!UQo>DR~yhVMZV%AEnj(nqN4}g zPxGr3MF$W0>y-YH;s(W^E8e5XSJ0IEN5#(-bMWqh`8z1?q&PuwiDH`~U#pP+0>zDr zuPJ`6n2S?_e0&v7+*xs=;w;4z70*_@S@8kIrxagR+@$y~#c_E5Liu|r?yp#@*sgez z;<<`fD&DU6YsKdk-%@$n6h$Wp?d+xWVTz54$0+_l@lwSb6(3N1 zTJcTAj}_s&TEsaT0aSAm(aXsv%kfP!xeW`9IZG@ah~FSiU%rI zC{`=-{VC-hr+BL3_Z8*(igK&leVOK8p(xi`l=J6y%K5e8V~W`R+l^0Qb&`31rH=jA z(k)wFyKH2dep&MN)vaHKdF6rIj~v7BAEz*$SmcbJ0eSL#MgoT|I|XT1-XcdHE<;IqmpFBh^p1wS^_|QM z_0?Q?%OKCL8>%GbU4u0H!2Q4@1f{KK?WO?DGJbATw0tk&L|%bBdsx0-A%kgq%!eMI zt;0Od3y*v8ar@UcC^dih(IDBs-yw~?+yane9pt%t+O|b>rop?7?IM%U$vyF5yZQLA zO?z%2>Aj7&?YlCehn2@VF5iiRjIXDTe9%Li_|^2#%0}U}B#y52(3TCB);j2+g)csS zaquH=hCeBHM&?X^U6mJ~=?%K~lXy$y5^AE|aa_ydv6Wly_3n3d(bnM{%l#f^VX+;7 zgV05z&Ir_~4#AiMqS!P(J{=s;OFM>HR9J#u+5wV*L;Imlfc{kxpMVPlT{JN< ziNNm&s7UyHWTxU1j7P1&7Gwnyy~h)N#QMbrbC@251`w;D2I-7Q@b6@O1pm@?(RKlo zAD}jb)kRy49IK1=6!^E+Mf(+Utu7jGMqTTo6;WnN7wtBZjxO4jY+iNImf%d;S{Lm! z)G)ee&md)W(Q?puQWuS;qTAF(6HTd^Qn;li0PCE*hg$Y)2PuELuwGqWyvGZd(_PwkWPHS~c0X zr;A3T;FK+`Nx~eDPG{YeF4|z$P3fY&O){m6b^|B- zo6$uR)y6NYi?)uPOzEOsO){m6wi`$EYA>oyWIz{<)?Y_3D3+SXS+V9yfM;DDZn=oP(Py>a!Xmlp+>Y}|x z+R;VpOWM&z`wMAD7ws;#=jfu*Sdg&_%*eOaMVrR@jxHKsM7X+WG-`Bp(VEHc=%Vqw zO4CIY~vi&(%fyEotbY$$hsd*UM&t>Po6h&!OtvbAnVCtq4MPK~s3O)vb$$FNNK@Xw+H5Zukau(RfO9ri<1G`Orlpkj3$M z4N4Eb%Y%zz!XSJy@Irt{{%z}`6`&NJ+6fd6@6i#W3W&G@w$?>sDRj|XrtRyZu`ll7 z(x>4D)UAuQq^Uj8*8JVnMJpTot3lWiwlb-@W8AIQ)huhM zYOGMFrOT@7#5Leo*HMEs@rIgei1O*&v9=~*JR<&gRnsubP~}N_v$W0*)mh`Vwaq#> zU0eKT=Lj6>LN-7~1kh&Bs+j8>@Q(29!Ing%#jZGfhWdYpta&W2@e z4NVn|wT)E$Gd_GPQf^e!ycs7quIwgP=j=P9UbcP3vahB*Dc8)erG;jk)2i;7IOSCT z!r0ixKWNg|v~gCt|Geg=C2-4H+Xm&R+6wXCX?@zRs9oL)&8g0uwmLp(Ew?yr)zz*r z&RW&gsBx+cg;jC>Tp^xOQ&&!^zVNEq(HCygi)hlf>;DxW$w^nnuG`lCf2pI1|FmuC zqwxW-TOWs2hEr8fa&I8y zd=vU;6Cj8BATt&DJ2mNp6&EYkDz+-FRyIgAyRgcI=-7|aO&Ac4UbM=O(KW6os$iok5-si1sB)!G>d>MVT;xDO>woC4p z(?@IjlKN;TCcd0L+CF$x18efIV{Ai?J1+|drSz$`r;pYQdDM%thn3e+AFalb$EQa- z&mHyA)u^8t$o-P~Xs_Wd^a@i&{!<1&zfzP; z{5yzxVU_^eebrGPZOx$6{PF46j<=&e+NqG|?rFBkgXm0ycMsb|W>@-XAACuDwC|&T zuS!eipKW*7QKe;HO&@LC1Sq57=vp7`iow!Wnm*cu+eZB8K8&uLu97((8MR&O{}9n(e{8)=$;+Ks*yB5Xty9M z6ucAvGwC2K=?85AasrEy1Kl&G!*61(se85#g!nj0hL1uvehQ8LgyglxwHwsZ0#tH=?is6EKWJBhm446;Lmnop88vz^9iVq! z=$_S}Jn09GN>))(_$uqoG}=%aT2fZZ^}Lb@Y*b&`1X8 z2kjd6a&H+J=#1!kvM*2?x{%rXBZDebGGx~eS}A&A=KJtoOjEiz`Kib>JxlsQ8z-fa zsOWfA4HQ2KMW-U>V32~dXQG%NZ6Oq-dIkKT(X$S9&sGDY^bH8zGp5-P?ojlDrVT+7 zuY36qp_IC3A7fDJ2Td!eA2j7xKWK)EL{FgXuKb`GXKwk?+t~6wx{Kpc#utI^8E47y zgLW2H*YSgPuaL#jy*b&BN8c23cyvAYz!O=Y3z_tTW*SQRK{EqL`av^&o)n$RcAxDT zfWAxy{GicoGW?+R7BcAv&4`*26=k!Rwa-aEXkzvNKWJqf(W|}0b9KrO+H4uoLD45L zr_ep)8SMB$Gu@!>8B?rUDE~MQh4iIY$b78J02K9LQJ9vpcy*l2hGsAu@BfU=$@JSDL-g8;7&~4vk2wG51J`2js1iC&^>!t%2R&O zO!IbdJ(&*jI z95!^%)&b+QurEaStQj0JxpqVMj0Dc{q#rahgTdH!tO`G9x+Bmc2ObJie98|R9bCs4 z&4#*X;_VuuP9+ULXok*=(Nb?KKWLAmrgq!tp5YlB`klCwqSQWZwW*t+0 z(8x?bXh&lf=m(9r3D*yr8O5yFa~uWype+}9^J8a{AAZn|M(gl97^86_bKoTbG1B4v{39E=0AVfrz9Tm}#Kp-HHm;{Iv z0TmT@wkqN>R?)gpwP-C`thBCmD_9pkw_0mmKoFEFi>?3XdCz-iZUWTh`}()v|L@K3 zwq&Uw#z*E#1oZ1ZziN6bAtUu5v0@uEmUOo0b&8A`(wNoB)>b{`Zic-7(DGj?u^ zbJ&*PL1V5a|KGZaz=OueWXwIIs-?}#fQ)Vou;<_p_<5o$KN{-@4Ji)|OIk9=U~;k+ z0CU79Fk8$$4W5V^Xx@Pta)LoQ$SR z5J(=h>zKHiE1S7z%`>uT1yisw{hH}pWCWH&(a!#q#prK%&)k;``x3ldDzZa`Odc80jYjuJHz`OCNiE3`2Tr^StD?)83r_r zjgAR&vrZmzv(Dd4ZiXR@lkkEJVxIBm5P3dO52$zGeHU+OLVCt1wl%R{um~h4z(g}b zdpI8$0f~%%?1^UhAb>>U2+V^M&4_9sInr9<+-3?y0i?&L1-)eV*X4%a-zCp2WUd_p9=X3jL83*oMK-~@g$C+x}(%Ic5 z+w30wuV<<;6ni<(np-u$y1b;S7Ta=vTMD##lh3^STOVr z$2Q9Nkr&NM_p}zDfEzcE@rvd-{?$A*w)Hp9Lo@g2hV#&P<9FwwMPcWEVjkK+*x|gh z6BSQYoS=B7;!MSPisU|Lx{DQ8D6Un!P4VZ7k0`qH(4JSBpRZ_Vw<13rP;P@~RAQc@ z>=6!G_DTg#RXxAqGu{G4{vJU2Rzh$nl517(kJpzIM2ls&?MvPU>j z_6P_5L(`v(@0rYB_6P^c9^pXlFhRZS5e}3+!hy0!I8gQo2fDmyvPU>%mlsX;2!}ig zA75xk_6P^c9^pXQBOG|GhQ}1|SNx;m+lqf9qEA0o+)YFoNlrxcD~5@%D|?7TFMEgs zTdDrr@}-Sdd*c<)(DXBjD91G_uU14!M32)zkoQf-%TVNJ8_M$K1emLGXT?E^g^DLB zo}xHaak}EUij|5B6@Q}0@2$-52E|(yHz;mYd_Zxt;ub}In`L_b)=zv}@h^&Uy@mcC zDsvtH#; zj7Ob&aJ=*A4#(565RS*Uzn9 zvezExIq{l6d#tu=?@IXHH1JxBV2|qX7HHh~TE_@51a}UO$`<Rsr)RhQUV)4R<7LbO!oaWuy0x6jm7CV z+Sl0wg1eT5ux07q`gHtx#^{CRin zA}og4`{J_jzKr11;*8z?MNN162WIScW>4Df3>>rDH@oR>-^ek$?a7mN+ao*eaTayl z(|-2CJ)MBd7cBsm@7W-7Mz33kF4*()MaVJu#`X>PZ^c-W4a;(hAO6H%^yMe^>`r?+ zF0uzK+;iEYzi;0K-J@`g)-BvKbJ4r>tt^Kdy4%aXC%UNm#h zhLIV4=kM7tIipwM?$G3kyOSo*+;hj|etSC1wst4Y&fXnFK9|m309OeA#NC0}Gxyv% z`;MXgk-N1!u;@=LUEthbTDRmB{~e{eZnp)ich0s4FvguI$>-aDyU%Wvy3e2L-{{9IP%kZJj&bR{^sl(vL9Y_VH0z<$M z&=2&d+Q<126S19-x7#=Nu)7u6Yx0V+_B#ILZT5P5P-aE%sex_dD{7|N-R*5_Dju8~ zc;K;*_Fg->IIr01wsilL`;XmXOZU&b|Beq&E57bSS=wVQ#)FEvEcoqwcv3rHEb(EW z;eq*!NjTpzC67ClVgBN^IQ5(@IF}Ri7n?JJKX3~}mNV99nXZTVi+w1C0>9$hMkwh@ zq)N1}<{$eW3k~@#{3(}gvD7f>?q@srN7aO4>p81O#ks-MA&POJsO#3y`f7khoU0{*i zc`|?T?=+B@zsTtsp81Q%Q%uZXEMyH5^A{(xEGOt3#EdlI1{|znmf6HKF@N!&G?kdY zD3f(O^A{tiP-6b#*Q|76{^D5_J@Xg&4(FY}D4W9mtNDwUp`^l{C-WDjy%X~n)7bop z`HNqpB;d|-=P$Bg;LiKD^A~@HqQ>VhKF9V-%wO!sVjnSokslhq$Na?=ELURwVt{?| zXt+PLzV>nMJa_)$Qbtb9U-Yvt67v^h41KDVJAZK*O+C}GjXRAfH%P6_?jGP(?aj1FbFaC{{0(Tx~ zEph(h*^KX*zxW=j<(a>DHS+^^o;m#oL{iuap81PiX%F0a=2B7^xsWor^Gy7rNDk9` z<}Yre4DLL4{$h~%VINl$e@tW^W$feX&R^v2jo$f-Jg>-|7oWd4jRwJ;7oWd4k_vF= z?LiG?{^H{_;hn$ubK3aNp1=4Eo6()Wco!;=n7=6363_g_Q&~N5=b0AtN0zbv$C|%* zKI{s2p3GmohMn)3zxW1|dgd?QMAHrTaXtF{#W6JHnZNi9lX~Va-o^@nJFk(9yHI2& z`@l1Q@lIw9?mSbA5s|gD=b67)%5m}?z|I_FS+xYGTb|V zaRwuRJ1!{p| zD%q2ak{`hM43YaF{@JG+C09X=g3BdiwS9)&WDNqjHTjcp9auAavYjP0L8(YV-GSA! z&oWB>D6k2xLu-WCQ;hO;C`c*Yv8v9p&o(+v$mOQV9jnTyYetJ#Bg>_59XZSL96OUu z{t@I4s4Ja@%@0eA5;WHqw=L;dPE`)$&4y|!T*rl$J=Mh83~>`&2h_l_OHEZU?cDl^ zN^*tTWk$)zv=q1w#R!42IV;^F3ClF#(Cggl;zuID|NYZ6u@P>k)W&ubyD)hDP}%zy zM30FbY<JHAnE2k#!a8m}XC@!fA#hjC)Q^kBlJeDQ%jTv;y2CGzBh ze*kg6@#hkGepAo1-orCN(?nS{!5fT}ICv4j3{AoqILA6~ag0A1u7!ghs(Ob>L>0e} zVU{MLNW7Do{uSdT?1XcyMaCQ!L?QNM7B`6E!b@PWBnqN>4mXq5&|xkoVVii*A{e_r zF?M}o>@0#Y20h}K!#0L&MJnHb^I59|`Sl7DSPAc{nrQ4-8T+X)%=p9%$!iROPeW7_ zO}>bawDk_tN2~maK3au~PW(WrP%<7+`HT;$C?wOMlh~l|!(nReRfu#G95Nk6+yLiT z)wMBtHX5NWM$bb=SRAA0_i*SW!plZq6{BYd98D45gA2kRZ10cJzcVg}V)XBc%c(I| zrKvQ-M3hSo+lm6&2)1yu7%l$WiAq@=A)88_!AdQMnG9>ym|%O(xNr(`k$bxs#|Y~d zuvSe#Vcc?p!O|_JV=YLO5kjJX5KQSSkteOs`pIIqW^O!YX3p7_quq0s@eo}OJa+35 z1#(EbDQT5Gff9`-?i7F3Vp?HKQSY`GrliL$CL^9D_3>Jxg%v1E{ZuPQOJw}xgFzII zY0xVK(;TbDz$*t*GmJLGN3ZHQQsM4_=3%%btHw(H`s?N~e$ISaqKzRu2Zv#6$Jk3# znZ_DJFuepluPWET1*}@DphJvao`5J2VT*Xj5;!>ow}z!LdR{hq!fS9$+`D;<-nS%V z0^waa$EvmElJbGk6L>{oiu}Cz#l>gk$JlT3<;<-LiY^CJ!r|aGg!eey5eQ~B659WU z`NY<=fm5ogD`!@h&W+BPHK)8L+PQ8(zb;e0C1opqLg_KDa$b3la%^}yW!AiDbLLMk zpE9>}TE(n+<^LAjHRsp-H|>H{bjr+W)27rf`+&THynMF?|IHlgTh>;wOi!F_+9=j7q4oxp;vX1n^UW&6Y%3>r1^F^wqO(z37 zyfFq^I#qdyk`blZ_B5LZxm$Zi52OU0MK)t6M+0ey9DptfnAS6p)CN*dYH5zq8C;MZ z$wn%BkTW$8DyMxkK=#~}y!`z9K!&prrkT%~Sw=k){!@}wH4)K1C~OMb*tu${owpIK>U?G8KgUoAC+0L)piw}xIjwR&q8P&32D6^$&O&o~r^f3t z19!cRFmV>12Mt> zY*?&iwTQGJ#&`*L5SQV~rgK})Fdp}^s>YRr2szHw3hNbU^2#!fz&VvQ7=Q^*5s(PA9D%XjU8Z;fRBDiH^M|PA0tygw5nqkRT7WZg1=9UP}a0yldm4aS+Zn<2B zlx~>AeIeR^K`lBqvFatxA6!y4=Uk;gubperhMuVP&QU~?-kK-9=`KC;uCX&I-DO+x z#5#u99Ojx*k5t*LYN_E>(=Z^%YZUL9k{Y2##yG**dTz;_(i-&9+%oU*lX{n1ZYRx} z=Uq6X9Oi7 zjCSV5X@YEeFr%_MI;47Tbokt|^6Ar2wK3I|)5>dVDywUv1A2f=Ye0|l`t+DvI=iyE zOH`giqg3V>F&NB0Qt5sv{CNz@Fk&3lP(Lc2wd*J!nqPFM20jP;QM=Wquik>|B-7$INvRC z__5vs9~a_pK8d#@#&Phv<~|z1e@vkEKZ* zN3JEwva%73XM1UXt`&(7ee>9lWg)rKy*gS8!g2mIOT+z)xk80VTf}BW1a=@|f+72v z`re8I6;D(=RdIsinTj(N=PAxtyjXFCBEKHd{%wjsSA0bAamD8qUsv3%cu-N+fxu24 z8ie)+D~?p0s>l~*hA&W*bs&&$Raw@7K;|1h<9((m>p&pOIuM|&0|9o&cwszQ2LhCJ zAV66M0<6$*SqB1H)`0+J9SBg?fdFM42vF960A(ErP}YF}WgQ4m)`0+{_~C{5$~q9B ztOEhcIuM|&0|Cl95TL9B0m?cMpsWJ{$~q9BtOEhcIuM|&0|Cl95TL9B0m?cMpsWJ{ z$~q9BtOEhcIuM|&0|Cl95MU3SJ}mDEiu~c6^4W@W6)#Y{TJdJZUnoAN_@d(5in|s6 zp(yJ>U|-gOFn#Y)xxMCGN5%T>Qp<+X~ON-N^!g*Ka$fve~2fZ zr&y=R56{$JqIkLDor?D;{!;N*idz)7Dn6t5yy7d0I~4z{_*cc9ihC5@^)G3>PoO+m ziaCmMUxL29%H0)vDfU<7)JvwHqA2$($oxo6{T#&_#f6GX73DsLc>I>l_$w9HDc+=b zyCUfV8Bgwazz0=+R`CVJR}^PZr_Y^-+ z{7MlIXc8|)FgZz;a3__5+{MR`s@eg{aRy)ruD=%5xg*tx)+Y#Wjl8E8eQOLGfP2 z`xPHm{H@|sihodiS@AW+w-x`Q_=)0P#RH08DRTZ3>)l4NqheP@dA>w=UzG#d4hn=ca+z zdJE5f9o&Nn;DdYBTg`a79!SR^T3h&xHN%deD-Mxx#ycW4fUnjX);{oJY zi+F|VC%8p@2!3z*iahn@mm|hwd7pyASgr!d@e1rAYW#5POY{s6E7SpXg0d;}uDuNS znWuYhz-tY__-jj#9@j-+xJ?Xt-XUTboOQ0Sp@;C z{aao<9%}^09>^HA?6804-_wWhJSlL=q5J;1{BWb;AEX!W93H&%(6TSEmhdX9C7d(% zKCYZcy0>WOaEX6ugZLrD4FhnDTdO2$!K z$+%^oooesPu%A3^-OKfiT-Uf}yKjB+jg5=#_05WWs~Q(KD;imBuliF?c)iti>^9#G z%_~9`7ag{S|0R9M&f)fjDE~E(-j&uHF0FUbXZB5PE1FOJ-C^Io!S$;j^sSp*QP?0& z!xl%Hn`c!_)--n4$Tr`)^%cv$MXI|i)=R3C_4W;oi!zJsRrdPE6;B+%T%N;8pS=(X z9`?8Y+2P>KHbqT$B|9hWO7Xp!K5XYu$G?8)0srxV8~v;8;{$7!?*HJvq#MtwxS=@h z#?+ZOc2>6+9?vWuy4QA6_kCSpcU}9q z)!u=0?t>@q3_52eb=jV}&rS;NN{V1TsWs+f|L`#%``Typ+B|d!{6pYptADnA^v=|l zrxZ^sno)E^aq5kkdmUfWw!8QF9gNl%=$|(Bz=PY}WpIru#$NX! za2Qj-RA2}g0{Vge?isx=9?Cp+Zhzs!k+=|;YlYwD`&ud&iCuxqt~pJzbj z_yhb^10(6i^HZ{OYECs({s2kN z{a+!4GrHL&qDqQE^4|x&Gc#u$Re1PjEIzCIbF=s3?9fDL)9LqjL)=hPX`c+%AScu_ zlmdHc{7fCn&!iuDaLn}cG83Q|k~LTOy}6)MOwVrtrQ7!DP*Frw_45$c^H zulwz}XT}`}P9}?WTiBMm;Rby*Oyq|8haP6$pU}W@VYhz#5)vAyqCYK#;_)hm(k7!W zp+PF9rtx(xbb^W*X`NWK!765@?L`$sC#sl}md;8Rs@O8^GNv7(V$^EFpL;@fXk^Hb zJkrY0tD#ep>1V6IM9ZVX6lKp0zBhzUlZwfn8T%-YRe3o`?=L~Qvk+UVj6E~B9A>2* zIy*F#)}_7AX+l4(w`R#of~E=lX)m!PrQsP88cLIbm9=JLIcCoc8ctq-e{`Bdz`qy* z_RMI;qJ-v$?tz#li)|J(rk@$z&9H@TM(Cd5$SPwo%32ZnRS5I+WzUSz!%Z{+_sj_W z+8qhpGb6NFrBK>97W0wtC;%59^Hn_bsETIIY3MhNmq^YTX(u!C7EPOz_9u!@NGoyA zj2enhwfa4Z=W8EL0n)|~Pj zkv%h}Q-L+7t&xMQIqlCXVa@4OG>y~#-9Ut^oI+T0+ErrU69zVvKsKh6K16I!CyB_y zA<|luDd2w=5wdL7n*-Dnl`6MCKbJ^M$6=d@g!DO3$km^tP)=rCK87Racvr^UHH45yRQNWW6Yfg;< zYfgu-0kP)PD6nTne|c z?wJv~!IyLc6p;Z431Q7C1-3bNqzGZn>D?k@&kSDGDTpcTnZeHCiKKG#y`d#O=N%|o z@TwESo*C@i7N@bTu;!Gxn*8^;iLhrzGNNG3DOD|PUIt`zV}NlBnt-1tdP|!ppL;Ik z!XNNA!T)5A!GZ8d0kAf-J8OV7r@ZoE&x|Z)j5VhtM8uvMtq_hir~EqCx+DGtZ291E zkuSI!R@&qv-qI+)AzM*6%Z~E#19oRX6~>+!GY|`VW?Y7N$=BMMeCtmC8FWb`zDQnc zXFdTK**YA_sI15BpWz@Y`Vl>T#Xv8wpi0T>Cx9 z&mP$LX{4@$Je#^V*f7U8W)XHl{tI=h8E;UNU&G%IhWVDB%d*;oGZ?Q9@>J@sL;Kk$ zijKd^WWnW*VZ1_Vk}}AJ)Gc7V!lrDKktia6p~!s`#_htk)N#|K_o%y2(srkgYXa_s z>mch%honCU9e2Z<1=pdfF5j|;O1^)D{Fu=dK-ZMzn}X~{z;&oP7pj(2@#E=xqFMk| zTdL+_;G7NDk-cIMliKF~5~l1T@$+}|U2wU7MbYe{=4_2g_~0=JuG5=n)^nhMNgQ^0 z+FSSp)cG*985pvS;JWOA(3PRxLKzsMPz`{?e2%6NYw45!>{ zu5$+ni{Yt*>%sVp+3iGVZ-(YZI4#Ep`tYs~J4@5&&<@M72@xKE>&$ZSgnR?8D`QD{ z{t4+TIM`r$Ho@aqh4^n@nErrUmTWXrV>l_xRCvyT>&jSCj`@&k;Ite&;Bl-o@ZY{V zeZO0dD-dA?oRs4scs9XxWh^PjA0Rygr{#Db9;~FnfBV|>0r(6iZSpQ6yagxa;P38T z;JPxFl!L#x4~Elnq@q6^*)|u%NsDQN?ZKblNxdlL;BV^}z;#_g8|)wcs!rxbEeC&O zb*x(<+Bc_fb<4q@*nbWu<@ggk+u^!0mXzZoNc=Tj%P~l7Y=&sxo$f~wq#UG^I}9h~ z=!8+z0j?`!NjU~V;xFksPPm}RtU8+npM7uo7~0`D8H-5#X)1fE53Js6)cr93fc zZidtHTqm}+LA0MqU+b1)@muZO~Gga9tTg%1{ky4jhhvKNt1x`4@P7C*w)vUU(cD?NwQoPgPH9AQVtIfkOUC zu;V)=ltRHOke`}{xJga2A>L#|yvc@XGRtmkcW9KE;xuZ}XkxH2mg{HWwDsj$DJg@Y zL?P50!uxGg%ZYFEf+D9Q64z4)GofeSBxwX$bc|a|#7;>u+rrq07EY^|JlVES&ZIu2 zEjG{TnSy7o%zE+DyzvKMgg0V_xVCqc&2};}ZKsjfeq+SvQfAqOhVh$7j6k9Unb{Tx zRaUm$Db?itzi8v0Jp05{xA_|^0B@%Yz|HFz^(;yFBi*A#p?k8tPB|rRBn^>ui(eGW%j^W=h3C{@}xJ%*z<;Z31 z@}wk&NB$A|m59vEhb&Fhd=1m{?*HZG-S zln7X-P0w`1Phv>0PsQ(j20%$h)3u=BuDdW=xLSaPU_ z0+9%6?t%K|klM1Ma9H6;Fx4LGRvYWJCqU~tXb}B~e{#Ur1dj2sK-E77!ORS6ySFUG zdg_bdf09Y8Njm|DjF<3FI9atz59^O8taXm@5~6U9RZ|$ z>I$HPmN3$239LP|?g&FGBVReN_}u)lKaJCRCVI42YzE?LJy>v-8s=DVmKt7`c!PK+ z5j-U}URg-*DY5ZRB7FA}WSFkU{T$g_nthHws?52I`?@L@QdNCbZ4fm#@5b{aKduTlH|35-gkk0bDBV8q7# z)Eu(*Khfea>bAWpvuW!ITM_#$IP@3cGdNhOA~t6d>vTdpIH+rheB6QBed>X_j+J2d z;5x>F|6aU8%)kO8hOCVK!l(&RQ&>OIbk4ZMz=>Z7{3rwuHZzBLvUN+mdXy(1b5bO}xUbqR|wUjmA zBt{|7!zJ*zv)siCa*P6}3#uX%qrjY0ks5P*T#Uh}IdExk^nitU-{YKcuXKpNK{Dr9 z6M-I%G??BXnN#4{Qbj1{4m4Gy#`++Xm#laaPiZzJZe8)a-~g1x-0@aDB)7jANQ~xO z8lz_(90vw~Mp3ATmU;|66gP-KoDe?5K$jzloRiea0B6&NNF9>j5{w0u${59(LNNWk z*p81ljR|^!tq3*)Z`J0d?pP!9K;pJIWhb)U3y1s0m>|;7&s!oImLMgvs+Y#-VbP&? zYmg|CdrL!+kVKB4&GEsjcT%cjfOivIQ@rIe2UE_Yln`+k_sE+ll;*H$ zht5+6wiZ>St8g2kVI>&06)s|(SM@Jz>4+&t#nlx5&0%i^(s}Nyj=cj4-YDIAEj&ic zIdXwxOi!sTn~DZXR)wmaV%6AdSQUnS28XKDenVAgic#xTg$koQ9X>f6OfWD{DQ;C3 z9J4BJ%z9Pfa{`@5>DW~8j@1<0<^O76C1TbqCzI0QW|t@@Zv#bQ(+s6!m(z{uDUxL~ zDP29Kdn-kQF8-GdielhRy56(HB#5}ddd>i9=<3x464=7c15{J1TAHKbdHNi}`6zX) zaO5LTgvShbTM0JIvxb`^2CZux6=xp$$i`7(1P}BWcvc>CRgd?+`8YUUk$q=k1Dj4UH5!Y9zPDtg!3c0_am5%fcrh zH&dvYHyzY|Hyfy#8y(c~#~jwkvT1|PlhzX-Ubh@A;eiDle)-RTd{=Rgf$$818w^(j z$F`#@gX4wSJvP8YcOTp)SE+u=Ti~|Bxd$&qbnn8w59c2A)9r!dDeoRUhv_olc$T_{ zdm6Wfj;Ee`@LZxRgyZSs9@oK7cPkvn2uB&+D{vfQ(imuvWH=5k_i+2j?G(2c+;F0| z-L~MHv}0B;d{?#{!{LJe!z!!Gd%9dMKXT|8{+}O&Lub~kYAiLct(`TkyyU#z`FSAE zw5(}!Yp|RfE2i@*IBJfd*1=h1=nQHR!H*BDSW9nwCAH^QmDdDdJ$l=;y4f0y$0V zK)-fm&gs`H&^sC!3`&{qh3TUK?j?yv&HaB@y{a zZ{*)X&+Hl@m%f3tZh^ia{vlNl@@>lYYvXK*+bIk>TdQo7<<@xRk>&3+%T4j9$nrVK z(zN-*-q#cEH z$n`DFb%WQ=+pyCYErt?ziUta!flk`d*Lgb{jq;J3AzO4rUY^sJt(p%qBGz?y-k^~q zIdBF?vq>ss`g}0@IxCRY8WGziy8R+!83PR!JR}vAZokyqlhhxzTn8I@1|Z6H$$8r4 zJp(CikWtS};aRG&+4{`&2Q2_c`wvh6bZ8(rCD00(+AGkadjOPEEkMKt>MZa@Wd~XY z(LCvSAeVCXFUbp}J6A#GC4%%&dzRSIL1^TlbAz3iX=tH3gTt#X8UVjjxN{)csUv?> zAH(q#2!{5911yjgOb;}f0V`v`nT6olN-jl;s=)}g15L;?MFy(0C@z3+Sy2p}89EFN%hUxTU5>mza`M@YOPhKKO681kzP4&Nwk}4Ii zL}bmjE#KlsscFJf#CLHXd>=msAJtT6sV#(5LwX}(DVb$0y9>O5{=<8mY6a7hP7PzO za}$4-ooz>)9J`s_+-_lGexuL(m4UgK4>`uiuPFPzcKt+$Z;GD7(XTD83cp>rUO@*I zBK0(QbMzeliTqQ|Q9jm^?H%WzI`Xot+mkm4KsvnSVzMW`?+`IbiE9RlTw_UWM#OxZ z4n#!iu6ll(V)zin5sIS~`8}WEWr{Nu=PNE!T%mZi;*E;8DsEKVtoWqj%ZjfneysSZ z;$g)kG!DxllUjjYR35D;zve>EpX3;Cks^N`q`Y47PDSD9fPS0Ge^%V1*bZMKn69Vd zV8v4vrzoDQxJZ%vgfiVa#h)wwTJb5xR}|k@+^?98{%893id+IfSvW0#V^m(Mc$MOf zioaC+NbyTWu5F>6Tt(rIfIL)XZs)`BsfwIxP5EBMKPc`{{7~@=#Q;9NFg|A?6FCi< zc(&qP#S0Xqq!m4y=l^4TiSRpfqm zOn0r~t%|=?oPh5`3@=rzR9vcft>Q*SZa>BN&ndp47{Iwmy>LvhEs6~9zW!ZnKFviCSpxTk=Cj+ zm7i1mqw3#K`5nc-s(z2kpDBK+dS0Vhzo24M#pa4#74sAaD-KoUWHqLrs3;s%kSkQ4 zOGG`mYZGy~>Q^XUt@?E;-=ug45&dv45oP_2>K|A9gX&*a`8CDA5RvXf#a)VrHT-ME z5XvH)ii(&AD(SKnTdTgEVh`2#CZasURDY7<7{v*SXA%*wOywDh=Mho9g&KaD>aSE> ztH=q!EZ@yU*tt{XdlY{~gq`1L`17j&qv8(5w-oHRgq^Q7JRLIunJ?!Y z6I&`q6*~}NCr{-9#S@6IGfczBtNwJwsfyDTXAxnCvzeLC0>ul7uydJ)U$6Qb6*nl} zrT7aX>^!XUql!-vVdr@be^d2;R{Tiu6UBW**g2%~KNZ86)lEC;ikXV-i70m`#a@bi z6pte!-3f}tsvoI1QT1mLk?*;xuT-p4T&#E@5%IW3IP<+m@dhIDiD~$~s=r@xv*H%T z-w|QwIh9{he2a)N5XS6rVnne}5sycb4{pPPIE@4mESRGxzfqz*9aQe3n6KDZairpD ziW3#NfSmQIQ(UZgvEpTlD;3u&-mLgD#rqWbdnWDuM)7gQ7ZkTC?o#|z@e9R6ikQzM zcI5dG_W0W-?eaHGVhhDKiv1J^Dh^Q`t~g3@jAEVQV#Vc(D-_o%u2YODy4-O0sC=K| zuN8lz_BYJB|w>8D6Hy`BaoS zk&3uLafu@5G*N$z;%dbk6mM4Cpm>+!{fZANKC1XzMR^{E-9MCyEy-lGcIguU1^8xK8mV#oHBsu6Uo~CdF^!r2C`B`;#J9oH1V?pVNWKid^JI zS>6kPF4tUJ)pIo~!@Dc?QgpfIxEUkE<^2Iztn#Uf@;(9mnJS;HI9;(q(dC+}Rav-k zk&e4A(*9+NS1NMB9`)BL{$BBE#TON~E6V!{;=iTx`-(2t+@~s&5`%URD}JpQgpT@T z#U_f}hL!qOift9KkV5p`75gX-P~_5GrW>YsisEQRE{tUOWJRt7qo62;3Ef2zn8 z^^A9i;@yf|HAwxR6yH*OSMg&-dB1}H3zZKk+I%m9KcLu1v56uH6c{e=VL&c4rQB7q zw<6b(Q_mHP#Hot26y^O4dM==3_#(xN6)#gOPf^~R5pTE3hZVn8tjP7Nl;2bQSaG)^SF7<%7u#Zo(x&ulYv}c%J7R6 zFISZJVd%Nil;O84a#1PeEs8r7-%>oF_?05poicu&VqeAM6bluL6i-nctvE?>vLaWl z(q4_?BE=<&mndGY$VIG-f1Bd(6rWQ3KvCXD5s&L!8Na<^S4DZxgub830~LoT4p%%? zajfDQic=KjJrj21Jrj6=>fQIv6)In)h|93$!?ntNzkw*_!|hrSr>!8GThNV{rEk>Uu&QHp0MPEnkyI9;(yu~xC+`_l^5U!}NG(S3iqRpkwecPVaE z+^opCq3oxvicczTQ+!2nhvHj`?<&5p_>tl#ihC9JD;`k%N|DQ-nJ?#+5*xmM<*2@; zVrRwfis$I_dKT@Wk8{-S_v2V?_`66Rc4f(%US2kTrrASA{iS7P*q6ofgkoNyS1iTm zEu1dliE*T64!2HJi=cnC@}^bJom&oaHczS<*sl?hhKxHk4^tnjXO+#bh1u_Lv_M=m zmBn$-qmP03e>9&QZSkM+@VGBW!*~qi(FraD_f7G-BTmD7y>oN@2M4>lD1eG0<{zu1{_aT>at243rFtVHHJpnJGs6;QZ-hW)H5 zo&_;}+`|o<4uv=0%|oytC)MQ3c5w4u2)~<#HU@RDtSCKtxMA!(uf4lYGuI;41GmJu zy({2%)4*#@fxQ79h3mZ(VP1QiVQ(t}X%EGW+q(&VHx0bj+Kz~a>!5qMVe6pq+N&F5 z+LiX$JZ^pOf}d%6!SR@ohjo$->@oa7IB&d5`{G*71bQ%xZmS|dj;|1}Q2hkv%Y)Y` zZ~2y?d>k$;UlTaDd@sU}p;QHsV^F{PW1o5QAbN&}RfTv_C@~!5H&EK6edg(od3ddr z7=Ng8{BZ3x!5f@)*HrwW zV!%OPw_XQ*$2%*3S$s|LaR+@Z?8Cmjx9@tlxAS?r;~cj4`F8!K!1sB&uk!(4_rV8! zr}z&0_rDj(E>2qi;>Xr-5WMVdaba@5(7uqhuy}3p`r>{ELtAILR zyWW%ZzQd4q?aH@5Pq)LHq6b1P`yC8!Og`)!zHQeojgfrF*|k%0Zh;uVL6>hDveOxM zd+~7m%h3ceeBC!}I=`YD*j0T)L;Zh$_;(MIRdq_Sg<1sng@Ub$Z`>Z1`mHLu zu4sJm(4x={R+lrkZ8~UWJaP~_7ag>wrrh-Q$DkZOY=3$Ct`D`fupD^TyS=Q>@p1NW z@QdcVg2|`s`rs#Mr+YJ&ZFz9hK_624klHuZK5TtsI=eelj#<`x+am}4)~190jNcyg zPyMzzu3VOU!!q~OA3Unr z+e5p8fenZ^toXB!efD2J^4a$eJ-GdWqCQ2!m+CZDe$=7G<3GH$+0f$l#my=jPd&3@ z?9@>2bwhnf`Nj4RKfG(7FVqL46XUL@eZ0%5x)c`!b6)%HtKmr{7sd5BFDkreJ7n;p zZp6u(;6)upr5$_~@xkZG?+|`|Z1VTdIfEg-KsxR>ett*wAJ^<$Q6=qRtXc5;Pt93E zl|MjIJO2RcM>ks~s-!omdYQIn=4_xU6iB5+S_J>BW?h(mHS7kWnJk2VF9HL(Sta!Q zU@6c&vzmVHPZH>rbqW2Xa0?8`zOrV7q2bn8MFzsbC8j zvi)swsZQ$Nh-LM^hJQ)b;!on%0iigLYSNufInsnl0-1DID!+Y)M%I=Dhjv z38ff$RFiHG-wZje0{@Z{JgS$Vlu7plhCwSls#l>{N%uNT>VKBT@5lNA++e_?`WWNb zq3fYdr{B*nhT*2th8cb+a>6}B+~F&2BL0Q*GwJsk9@TJyNA+hYW;ns4S}052 z(%$DZp`X@IV#yLbs_&pA;nMJR5*kWl!NO&&*;vY>O2f%_;vb#n5b$q=03KCbx2#Zj ze&`K|Y5ay9UeK6+W|YNZ9>Jr^i8mGDUxhg68<$jB;fI@O0`jPa>+z_D6FjPAEY~Ap zIhDbqTE?s%RnhRMhJVvoKAN}BNaK%I;RKKBUnxEztwbKxizzNB*m4?L=T3=Kci zsufBLPQ|okEcJ6~Lq+VI_BJXLem+bZHD7zfqZ)omGcr7?;Xi5x43BC!!J~RTP5r6y zG)Y^S)|uifjcY_SJgVW>)l^a1gDggZM>WJ=dNY|z^L*{cq!lytohH=)@~A#T@x9c$ zCG?CmPR0tq--u^0c~m)$xU;iAJk=Ls>qO+C z*TbXw1selAs;^2F{E?TKFL+dq9Ex1ZjKQO7H%h+LSVQR2%Ul5_nYkaWw4V zQRT)VVeqKtN_d~h`^?Y7qgu^g2ajq$2_F>cjY@>UqiQZCg^}ARdw5i9nI1fl zo+HAe%5x+P9@W#3gYc-{Mw8%CU5TnXa4ue>FnCn? zF*!0Fs&Jv*M7}J;R6aWgJgP32!E6bgGY4<^5+#jQpgD4QN2bK;87h$3tk@8 z%NYYasx%=yst+(v@TeLEcvR2g$pju%qX3U8e}W5xN7X36qk2A*fJfCRz@xf}G3xQC zJ_hqFm9!~%R4KDiB7;Yj@-41R9@Q{-RQ~`)0aWUHpJgUsqK~y=D&QCdsp^Li0)B=E{O{m@Gwk}1o-!c?P5m}4{4_o52}EI2 zH%A7(>(ZP21JOvTdL>HYyWW*Ukx?|c&Xqx`+LQ)vNDqWzEuALY+NVKfAIFC`LsUYv z*WxXhq^biu(>DpKad7Rq|0oDl9VA>1c>#4z(IEDq#w-G->h7lQE|kkYp~;)@b6V~h zaJeii2viyG7Ra1Fk!!OP3q{u(MddSD?i9uwlKxl3TMwDj4|2Ibls%*=b^N(}8C>oz z7`KPCrS3c=ISVfLdP&=zx^fh?Kb#>|9h$xuxNT==I_>hzjXHpp5D9FWdR;Lm8w=16F${eP65Fx*er!cw~AU`cB zrXofwhDshkHF=~X4>*&D(T#x2`C3+|I{X_QPq9w&;0&#~@f1e40`f(YVk=VcHwBZ& zgObOm2-zJ^VRU|cEb_rwop#_K%WYCTEO~T8NEbL$Dx)icJXlifMT)=0Q*4zy?nTJm za3+P(ZH4?>II9!Co<~>$sreI<$A<{{TRer)eFgcDq?n2nC&yEKB6)PeN!k|9e~o-3ySnN{X#W@r!thujKl41>VP3z?nRZ?smvG!&#kQ zM>@Vh*w#w^zd7Z7B=52l+UEFvn*-OC0o}fYrVpe7IFe2x@kj6kth?~vzBi3bz+DQU zB@^jMa9uh;m(C0F>62Z+`Z(DN|^G`PL!+0=TYG1WUfFA+3bd zeEE*&w?;7Wt7$j8`TiUc?tqhge+SRwa3)_y)qL|<-&=5LvJIt5jvaW_&3FeAyaLyi z@2HZokH2luS$XR&eV-gWfMx)l4TD--pnRaFX#;@ca(0YatCV z<4+;&hQkr?m*V2pOQyDbft5VYc7*3Q!$rsUrJX8529o&>*r~h*7c3~9WBCr*VG2mh zt7dQ6yZcov0;1C405Aq#GX_kW9h#;$b9G)#YGZ#+&jQ5mLk3-_3V1z*P(Yzj1oCG? zIE``pzKBwVoY#}W94Y-4_C~xNNsVZs-@<-i8~v}OMvP|_%$ZYdId3EdPDGH^pN8bQ zfZg*WnJ!)h1VJC4Aw8nE@iQhJKvpeHaN(bHpu>Lrr<872}zv-%S&w6tNq-lq*^%dq8c8s}$B5YMHRuzZFym-t$Emge?s?~7d zlq75w?_|QWaG4-*TV&B>jr?zYV#k)T7ZAYA(e=#%?cg#I%fvV@5w9ZxDkR=y!V2+@ z=j8CM#``|tkny%ewR^##815*Aml^R8USBk;TWc2+J>M&K4&rG=*28-b982{RDUYXA z3}Dqz`uzZ))Y6o`Hc@&%0$4TMlG5{QIZ8xeMKV#{s)nYoLI6KiAs*qM#!L8DRbwG| zAetONpSNN~(9VEMLSIPdQeaPpt-2-Ji>&b`iDPOSqhNk^uBy{G6km}zrmisxe1OFu zS)_6HL*&Q&BoJ&$UKIES?HNcE$&i+0XajL3nPKvc`dz~)i^KVJ|fB>tZr zSO%A=c55t*HdEzxF$S>S*?0ptWvv&?pxJPd`oV7dw2LvY4i3G}0dOB&rjCtj=3}bT zF2(@19rDq3s~7AxEAsIMyKUS~&W&wi+?+O&+O&7O7z5boFs=<=FPK5>4;c3byPeZ6 z#vvJkd~e^l!3=r`4!1d;70<$D>bX{D$2Ff&Hp1b#j^mQm zB*QfyC9i-(?-Fi;!&tCm^yrh`m>|fs`JDL>oJ)UAKWl-S5w^l5N=4~OII%`= zEWH6gA2N}W@DZG}6+L^69+i><<-{=*$`K}jzy|j7VLeD6o787jFOit_{_*sA7Y;*+ zz;lNCKM)7Pp&bZ3bD&;KWTU}fi`Wego_+7bq09uHa)`KyI1~=27(s0<@z`468sftq z$L0aCGBzm`C!*j!TmH0Y>g9*#vzVBlOpS+Iwn1L`o_>`fKnXby* zU-+nI9zTxqaGH4hSQLN4FgHMX^4^5ByzoZwVCz1BxX&IE!OaS5E8u0nqEB6=ssF$A z@yE@|vRqyM(2t3>{Ol)IgjeX^@`to`&t z$+92uvfxI;lp928B55bMN>g?k4N3Zc!^4}K6@L3b7Cbxg+TtpGvcCo^bkx^0HyXa6 zAPP@ZoTRQYAO?^5T-Xm#sR?+WiK&1Ho(?hM!Z=nsJ>x?3bL4j%?v9_?W;9*Z#s!ewKq zC!Q7K!EV;J?;Ut~u?||FU6<;ri9TxS>Ro`S;KO3Whs}WPhIpde_5ie55!?~h?ZF!2 ziSC!EBP6UHy7^=M-mV5A-#MN;ix(BcB?iJpTf#M$Y z)1|`k((WG3;iuzOm6u%ipr0-ej+ayS;7Fz$2*;}_$FDnvIl|q;4Wo_&);)Nwbg!50 zW%fzv+-sv7k70Cc;dpsu9J&|ac#Y&$h%Sh}MD6Fk$IK?kJf&7AJSmH%hq%FiKJeg%o9 zor6oF!j%tdX)x@EItG$SOfTH`LO>q?0ewo)nPUe!J6VGQ?VOY-e8N@VGmvK6feyjO zffNw%_YCHNWI7Pc&J=a4hU!2g3C;&8K1jCn1|dV3O07?O-_Dso!vrJ+3j$q11)km= zwB)@q1L?LMBtdp3X8|$;1-HpBDVUWR$U!mMAU~*cpq8A-WzHO7CmV+7=}9AjPA1~F zPoEF6^_I?NAGQF%b^vxDJ?K1pfgSZbVBX)-2<-39S2fXKTaa-h5CrQ_U0|c22yWxt z(}?>9G|k4&04D4Okgs1X&J1LT(YC^Ek4EQk@aEH{Pu#2y z436HU;5V4g(;_j=QF2HO*g%(H&iBg!g*YW{8)XUv3$p^5GH^2jjlc%q3TICsoY$^( zAhTCAI8vg3!#^BsRnp;P~J);YbRs< zG317^o=JZB7C{FyQkUN>qm@lbrD;F2Urr{7sQ$EZRgLz zVt?=gu-K;wi+*xjj)`OpHQ3agc`_w(ZhMTJ+XkJsc3#jaMK+1pnHa1f<-cJGn{Ft* zi%83hvNk{Q!+hnZXQE!pvf%o;4}HM3^UE1gqP zHh+dSe;$SM=}~YrgVecfhVU4Jy1R5Hsovwv%|9$j{>(X*Whn5hxmEM4%S)=TQo3a5 zteH~elG?c?3&{xIkS{*LF`wVp`WI~a4bz>6=y1Y!J*{#+nq|hE%2MS3pL=wkeUv1> zA5&n7_w+sk-0Vuu#SL@b%&7dU-_oTu(`skUEtfthDXA$wdDL(V^{BDF2hlzzNzE^} zO3LS!SI;b;H|_jmG3tLm_Wb#%oN$^~mzPd2LCe$?l*}r{*f80iblSw|u>Af}*$^mN z&?|pHenEckXlE>&FE6br?-D%=&p$l|^e98qOsj}u(fq8MS(Wp!nzetg{(a7l_Lw`Z zYW@k+DywVD>w3)X1G%giCFR!^%q z0UfxYe|e9&-DXrpd(51^u(WzckAi5A(Y>QRX3VSXfpzt>rXkgwS*10z&>1~u%$Pq9 zjbAyh2R0iZ)<8GCw6@eMA#t#V#%b?LO)6Dt2rwEF+~1o`oCT`~>5Id6WId&wzT zP+rY$v`Xfd)zp^OmSgaL8>)PXQvfSN#+{_wIn1S%Z%LeAQp0Oj$-?ScwHWZowr*Cf zRa1e%BiFC0u{d|D##c`>ryZ{k64g6uYmlCoJUr{7%aQZKX%%Hwe2|-Sq`Z_nbLho& zR(Uxx!;^36oWv^6A!pi%Fjk(-tNVmd`AikL<<`A8*QC?@CcN=iFhuG|!t= zSyp2$M4iyo_}{yL*PH)2LjCW&$Ai33l+2V%kK0u7QBhK30&w!xR-TJZyGZswx2(2u z;WT%<7HLp4?2r8WJNRxyBpCjxL36+B>0nH)edysroIXVZwoHj?};K!wlUk~wNFoX|e zM9fgd>}Wx9TTpIB#8=P`L`3SY`hki=6h|nYs(6;-R7L*mMte1i7b;$=xK{B7#h)u~ zROD}AO#h@Je@3GGmLfkAQszfMq7RKibUFB&soX}fn__>(Qx(rt7|#{8Noc2zuHag^fOigznMqPSntPBwPhD4wh6a`0cN@@mEF z74K1eK=EP4Es9SlzN{$Rekkugm9ucoV)=6w`zQ*hAN0cM2dq$i6%k{jRRiD(#2H1UGXl}KdADr6}PDV8I_+`+@|_BRsOT$`>Ov`<*EWRs5JlK3__9;b#08iQR1NLpEFcV6np6i=9dIo!Kme+iVpgp4ln{k6<`< zvr&k6<&x)+2%j&StwOlXMj`xH%YQA2bn8j%SIB>Zc%A%jmwcCaABl92D*Rdb|6Y7a z{+lJ6jYE|CA!VfdOyM+;#d=1>3=(05lADOFNTh48aNpLx*+NA6gXPcpkj!s{IEF;J z;}q`O+@GcJdGcQ>d4;%|M7pyT{v-KcCf3RSCds#ocaccb7>i$$}+k921!{CxReB$^F=)bm=&H;Q+XxIUQ;ex!d&{=XGBk??<2@|)ro66rW^ zl;K~?Kb#90{g5T*ip@yGJCH=WZjuKnoHIw6?g;shlYER=K_cBug)fo+$>JJut#|>6 z@~$S4?ncS?D*Qq5*YbZx@^j*=B+|X5@Q>vGnfR3$!i_EK9VbyuLOB(XxQ64!`p#q-1q#Vf=O;!nk& ziT8;QiBF2ph*Sz-z3e_8{JZ3@#Tf6m;om?k5R+mnkstaQ&+hxdu9EptpZ@%CPnx+X z@Nmgf#A)Jeah_N!E*0%L0qL)nY|jgjZlOxNXt(wpC9?j=f&5=KZx&&?~9*^ zpNn6KAwCx%pA0cuY%Ee8n&CagKH^Z3mX;VkUOZNuB2E)+EiuGfAo((piUmx6hxiMT zI)8RFaX4>(f(W5i>{<3)QeLcAH0 z=ZW^51pl4aKDbulH;VTBgm^!f{9AFONFy_>|7+r>;tug^G0f*8#M^o81AFd*eWDLyXRT5IrsQSz(e7ICZi zh4_`2jWo8=Do0!4pGq~+} z5cJmoD3$-=;*sJEagO){k*0>2&$Xg&)BjP)Pm1q|?}@Z0!gNuwmDol+L>w&cY>U52 z{kS~;MYrsLiUGg)c8AXD>J#T_v$v=nBgOKw@--do0$)#csaiBOv z93dVhP7q6F(RKE=KtLjQS)*T9KjLN$eq-88i4FB6+YlTpTG*5RVh5i8I6nVvR@> zH7sv~c!PMec&BLZ0}$_F$@V?~^3#%^6<-iv5jTtPid#i{Z-DeWB>zK<;$DsQq4^;) zUu-NMAQp?A#cm=^>M-3X@fdNESSijF=Zg!)lf{)H&G9flTf+~0O!8AA6;2uMuQ~9# z=#9XmZY$>)DyNKPzL&U-2aB-wKNt`0udj^ze?-{@) z^0)U5ko`3c&XoUo;)Nnj5wX6vh(8za7VW(Q!tK2SNHax@|F-zPxJ~@4_=RZi8xTK= zdv2!77VW(QWSTgle^(I}2u$uT4iU@5QQ}z9*7igC6C|G`E)rLWt3=vJVtGFncU~KT zmXR2Kw@9lmtztsYr&(f8v5z=h94XRb67#PS*NW$e*NHzB9~13)8R_gf7^E3w<`d!bA(#+p zEs1hh(Vll950~se-&RRpCE9Z>;?Z^z)88gOB0eV4QWC>I5NRceGC#bKw2MS`5_^dD zJPQ9qBo7v8Gl}shi8Z1*D3CyTVMM7c&>P9ptE$)}6!E)`dZtHd?p`Qk<5C8Gb{<3`E1h_{P(iI0eniBE~Y z6<-$p_aARben;Fcek$$|{~;#yJ|IivBnTdlLa|6J5j%*T#cpCRap(6XoaDg#Mv7y^ zqs6J>ba9qASF9FmMgKj@3dw85bHww-i^NOBE5r@rwc?H9E#mFsU7~%*Mg2L+g6()p z{H^%1_`3L(_>TCV_@TH%{D)}Yfst=S?>Q1;me@q(>@k*KB$kLB#Li+jv6nbV93~DI zM~Y)aPReHfHj5aXEP0kVSM=ZS6mtCFKe~y=(Z67A8|WJZR+*VSf5rlTC7S(f+d#L& z+j@yUFpO;Lj9CZ8f0VJmssoN z%AN9K_|LHi<6U;>zO8MOI|$!AEobkC?cnwR_F(aoG6n{T?OBxG zzG-cnetr7%_F{kY+BU=6SXEMM+cd>hvHBNpY>8Aw%Cd*8p6af8bm~n`w=$>o*Pnm& z^^B?24>}M3l+V?cEaKjR6Dq48evUMc`af9q<0JTB`H2(IPAv7Y3JBMr-$VVHj$lYA z&Wm;URCC^CvMmFL%)(er`@Bv5`?VQ6(gpYww zbfLN9k05>wYj~W4fJ7vEeYhpc%D5B0(Hpb2!83z@aM7O@(BEm$4L@Dr%4B@5;Ss$i zV*=#t&dl?=_!;nqwdicVeU9D~wU0i<5hu*I?9rRUOd94Fljv>D`QeCbcr1d5POL(T zhIEIYhb!LLIw$v4cr=N3P4H_;HeYeayBFA(6K@TVcn_5r$;|XdhhJT+ZJc!qcS*cYf?q_kUqx-> z{WARa&0%T%B}TF{SlYo76WOogVjmwMF$*(`As!+zH~V$u7au6GFnbxRcBsTA*);PW zA0)9w_D`7AV2MReeiM|GaN{EqAF@_Av)m&a(9K>)9i8~d42oe`e9!(VYk8D4400&D zjM2wRUIQci{22BR#I`154Ua4oe!d$&Au${dufM0{)6LweNfs}Ud0i06{y8(N$T-SE zv4#i5X|32vHp%9M;`pQ1OI*X_BZ`l=q@n*1*6?_NSv}d(*8ag79>dt# zPiKE&p&hdC=Ye}BqY?fJ{53q{&#EAA4UhP9YJj(fM|`8o9gzJctMNa1%`NSq>@^f$Yw)7AcT9F$X7y(Nf#@__!-I9+oK=BHSW_VT ze)MVlogALQT*Kpc4E>V^+jKl?@K`fxBm3cKX|#Yp^v7|bj$cCtHExQ=cZkHNh7#7XSi|FW3-6Vr5@j4~czEG`liMg`4G(*HUOXU4<;*zN z@bE4rgOdCR8^;B)2#~L2& z9CUMXA>(5W4_kN_Yd7$`ien8Ao=Ucc2fw<;v4#iF5nIE9>ZNh4;Sp;7jq=%6~@9NJ{XeTo+A3QI)oQkfP@t?4nSi^(gTAQ4X%4Nl|hQ|*OBWc%e ztl>d{BjQN57i)O1FfJ!>Ig?@y4~+r2D$kZnAKX! zSi{4UW69?zV+{}c4=%8F)7yY@Q!07 zc_nL!H9Q!ZYj|*>?>N@*u#fXt!(%g#3D)rNS}{EN7+ZlgJWjRz#w35u_*lckKH^~< zJjZaX;o+Tdvy%L{7{?kOo?M+goZ(o*!;_aLuV($QhDUFd&ntRzJu8GYJj%=iYj|+s zt~l24U=6~>8{FiTtP3H9$1@0tV+{|_18aDk!x&h@!}Guz9-SBiYj}7bSi_?~ zJ+Ov{=Ycgmmatw}!^0~DkJt?sArsch`V?z;P-dk}#u^@!kMU)$;St9g9;d-0$sr%d z8Xgqb=Ufjbjx{{in~XI)cvYuhSz!$i9vq%XlACRhV-1fd;L)5{ojBI;;K6NvDf<#@ zc(7Ej{1^R1Si|EEcw!9?dbMzQ8L-if0k#?LXoM$v3zsLKe=cOf9gTc}&;}fXZ6I0& zu-3*17K=4Jc;&+y9{e&M#~L2pOvD-6Jwj z5b6~1F5WFN-Fc_wSqMmA4G%6Qf;BvfkTe4;cF-JOG;$U^o91R*)iCqVa3$YGFJ^3L zSa=}<*^4Kl%#5Ej%;)+aJfHZvI^$|zP9$TDe~m9=c@F9WWL(=Y%I|iqT|QB{n9z;f zV9CbY+)HsQ+y*Oi^lC#_34DvN7qe*hpe&X=9QzRZu{gJPCQCmB@*?`NNVkvqQCaAh z*h^SVx3Bqy);lHH?6Q7YHzO#tKGK$#dFto3bH{`h<9Dpvt(`kAvdHOy!lMy3yuItT zMWS}d2hulMO>gX&rRvOnFzbyQ;}Rz`b6{o|&#BRdaMCYUfG9Ko9#>qMpian=IFi!3 zc7`m8E2joDP)+~L)>uBEE9#sjL*$B&&rRu)X}KKwi zf5y*G*+N&0f=0H!cp+_=du2C@T3-KGtftHAxb;v7J=FHB)h-4A&6&4bx7u|=4b~5V zcl%O@7Ttd^D91Yh7*pIZ7_pyXtoLN^VOSNGOIy5ZEw)BZe0?vF>Jh#cf@Lbg)bin2(BCw#zZS)1MKao}I3Vw@WH9 zHFVxIe>&)r${Lev_MAL))c7ODmmlPD^04t^ zCXZRTU=Aj7*GxWq=umG0?QZ7V`!iIl7u3vN8ZdO=&Fkg#<@y4fRP+SEZc+ z%oh(7z;`(^o=}PT=uY_}o18oiv)+*zqR(2eh|`EU<9NaRa?VvQuUJU43Y7~MoH(12 zyjikVUFPPSU6@@{Ubz%=lW{a@Z@{m6&Enb9opMYFww~pbWivW3eZit>bCFx+;##W! zrmNRf*>qd>DEig!Vzg*()qG#lyj#q_rJ)Dr=1nQ~CP!ncedUSl71RN?AJX;~W>(Cb zS79@#;i92~3e;&~Rn4NgwJ>+Uc01LJhc2i>C3Z3{;mx#WhFrUf)kSS~Gvm3O*CBtx zGfOJxgndo(t~WPYGr+s;@m%tzddt*Bc|Ds8UX@W{%>Q=EM~)tPWcktl^lAlwML9I5qqulWMw+w(9Ymc8_kVTH=(?D);Pjq^H7r^Vn$@1LfPW zu=(TV<({R9^sIdZ*YonuSY*2t^_Yi&l^QU(x;vPskHhUx-A-EtK;5dVDre7_T{Yc5 zqwI?kt~E<()dC{~7b6FkHycw`m^xpM(}31B%DvtW48W=?bbip*#|)gcOy@PyJK3z8 z?d(XM2mx~?^DrFQH*7?`Iq0%lfl*((th%aZHzNn;4CYr>@k$H}1Jha02_s>|!zrIx zRSS~=RjdU(WgH+i<9$~XCDS;H#@j{Ek8P#|bkNH^69RUDbiUzVy6etHN;sVKXJJ-D z>~NbIlzKDr(`Fjx&#Rb=`rz30?p0w{NB*xE?wD_*U-lZTpJvxg=SgOxIBn6Pa_$0N zxEIoVOMOcP)d%qk$k_Fk8#e8LVC%L3c3bN2C^5!iN}{aNqeq9bK6qJAm}Xr zo+97xFy5i!C~=%PRjd+g#O2~?;(6jl;s)^+k&pc>=V5V^_>%ax_!kj(l@>ow>?88K z1@k#ZoF*<6@$hHi7{1%&ijd941I2!# z%_%|n8p#)mcZiROe1pn--V|*P2;_fA?v2L-h94$Q5Ua#R;u+$_;&tLL#K*-K#6O9j ziBSx6meWXVD;^{sCQcA-jtAl|k-S#qt3l>7fNzY!BgA9Hnc@=hBJpbRPVv{`R`E+Q z8|NbPZ7FsU4-rR+Cy4XJQ^a#cn-hV2Zj=0oxJleBej-NjcGCJstPoEUZxQ{u{Vz!_ z#%mI$vpE6aP{||2(c(05mN;Lm6;Bq|iKg?9{O*?gr1+Bfp7>YsE0V_=*D5kbqK-|) zmSP(c`F4@qUFbvTW!Hioe%xu+`?&(kNzh8;0Ir=W?ue$S;;uuSsuruUk5my zqp|-CW8dHWu+i`c=C=d+O~p82ejHPNejLw!8aN#nCro?4GXh~J1>B6+0b}hoI<)zD z%!3>(cVZFr*x|==>F<}j3T{6QoDOXT6w#s04_g5_m|ut1-nq>D*la()3*q+D!08kt zKf7DM|y=$icvBGja4-YNVN z8XoG?WGKBtQQifH%{)`TrpK69{CeaAU9*9R7k+|~Q@UnD7?Oy7z<4|Bnzce$_-%xQ ziwdYO0~@pWDJdL5H$RQ1b+71Gi%4$xOa%J6X1Bq|*ERbH@psiVdmFyK zt{L?zzFF7o4Ca~EHQP=xplcSVEM2p8I6HRLHG2p#JYBOGdfnGG+k)1nbj{vCls)R2 zRWmTHYqkjq1G;7>GS6?RYnF?K?@8C}QI?k0HRHq4o^{Peq3;8_X8cYX&^4=O)zZ3V zTNt`$U9%#Tl-4!7m*wtR*K7xC8PGK|m7l%onjM3})4FEX-)UX5LCh_!YxXOaoz^vD z#lD5E*(WF|rE8YSwBMv_mXG4UgRU8EPe9jfC{Hfvno)Hhx@MmEO}b{L?~~Rwv%~Yu1C+2ld zMc3?B_Ci3{%=EB=x@Ny-g@U?fIcz~t*UZ$9_o{1l87uwmbj@C5z5YeIW@XGPplfzM zTkzd<&3M)M59pd*!(!9AW~Q(h)HS;bErhPw>FDQH&C$A@bj^-{*UF+35W17D*(wAC zbj>)6FJqlsz$c)TuGxjsHS2~lGA?ddSZDuhPV#BWKk{|Sq-*wLUrr<&Vc=w3;>*xA zqXKxwrM|A&R|wu$T{9L9T{D(E9QzRLyVW&gkvr>}v6=y0vqRD1ebF`RUcxSruGz6j zbT0D2i>m#)W_Z-wuWPnn*9_+%E=tanrB=J#9K_~KdgH8-E?xiWij?iYt6LizN2#5?mx$1 zPXE71Yi-y3eZ44_@z1KX{ePg!24&EHj}qHHtFHa;X{YU1G28pvP$^~E{kmq~v-M;C zkLa51X;B$Z*9=$ef3>a|b>OJGQ6}>97Uko_sbZB_BQ6(D6Zy@R=`IpCh_{IMi4TjL z#QnNvUcc?vHS_vmzpk0r5Bqh^&<{{B*sp7be!yGKb9lW3?fMG-H|v`H|6s6ezpmMS zT{E1L&VF69|5{zMp8b49GccuV*0-proB4ac-Me+`-5VCo`t|AIc@%xKU9;Ra92w5H zvTL>;ijMe5hArY=gzI}2m6-ORYxWUhLD!6?#-Lxe6bM%#c73~MJJ~Xu&NScBmRT2M z3Z1fvOqz&rWyCP2Qb4EdPIyHl_uw~1b1!Zh8AU<`w7DWg83Z@-NGp2eC*aAh*S?3Wz^IlC3}ye_^B-Y}<;{TRiYJdr5v z;%^Q!sc*mRdPJrDGJae|XHiY0A>CoFpaGq-=?G8RFXL)3*_>tpoie&nMjj@?!hV@o zB20)eut%mRrtFt_VpjHK95LvWd7^K>jG8R4hJ=oysgVY=@k1p6Ya7b;?U$X2&hYJ* zc^Np_lUZ8-3{OniFZ0Ai_HUsz2m587n3erLGJsB*C+229N^zjX!t4rG?NEtLvR9+0 zpi|~WZsFOk8Z0qrzwCL|O7_d>X0M~iXuphNnD)!4)Ciq2HVksgewioJei@CZyo1=* zWY{nJ1a8wQ<9B1Pzo+EW&D>vM&B|k5%~JNudRu79ei=JU_RE-Y18NX(R|(O`NC>cB zb`C(DvgM#}zl?4c1npkjOf zc?G5Hmw63H*)Q|TP1!FCb9zkipzM>G)$@4;CZ_C{d0D0Gmw9PZ_RDN4LvhM}Sw03C z?U&ukI&aQ8!df&jn>OK~Q^qrx_RH>K=$|y$Xuph^GHE0GVLvoFmOu2zacPO5h74*< z>w%t58G9!=hJ68@GOto;`(=x)32FOfo}9K{=E+&f=UFemW)GM*##?3dBB zQa$@+-Oy$A?3dA`Qn=Xcm+@5a4$|G|^}sE$0! zuG!<|$6=d}g!Ejt$Ly7H6xzuw`(?$xj23c!9d*i9fla8!YdU2M5F=^VZs?Rzz&W0> zU*`2-BzYl|LZ?h40wuEH(Fn6o+b_G1S#c#^>XcDnRyR|IPMIgik}pu+*?!s6h^%UR zI%PTN#^h+!kve6o&KCU7?3XQIy`WR( zl|uVvCm?&)%K8-c%P6x_Cc}Oi<$=EJ+b^39k0kZgsZ&OQeSR9-2%WNJCc}OiFNzc_ zE7&jN!QqJ{*|T4ED?FO>szaSJ9^B@qu`gl2jHPvG*#$XH*3H#*Z>+#Rsq;A8^B_rQ^qSF?3X!g0CdWlm)9`(s{|z#VJ~LU&?#fdDV;JF=k{*M(s#07W`2CR{7dX5tft%7{Ajjk&PQyx&}a+lkkKnB^B--${jzNa5?B*6G?+V+$v+S;7OxfgzMT0!CjLp}>t6bY@Rowi z6N|*r;$-ne@ig%sk*^Dx{!ikkVi?bQ^yf5tvbESvoGYFzUMk)w@--*ZJt6XqDdl%W zTZx-;v3>t@k`OxqDOfx@ivL&b`cK|j}ptp zYLT!07{4U$vAcMvI9exJ#J1u=;$h+hu}WMd+FI^N z|6|EFiua07i?4|vieHLH;GHDPKTf$lteLRwjS5TZa6mQ%1S#5u}_w}kM_xmiuTPu*$2oEQB#{=r=9JS zZAT=Y%WMam?f1)taQkWCbTS)y@#yB}hn)v^uwR_k>HKh6N#%E4APt;ObL6)#_Q`UQ zpMTttB$eMC%8&XE+^)%kjZz*6ZLA;no$ZsYZnAIo$#x)KXFoHL{le{W?7{Xn3ADEW zVSfKn9|*S~)qrg!P4~?{*+j(K7yD#uG5!wqGY8pLZs-P)pq6 z!@Qqw(i!XCtLH&b9mDp`I%7xovI0{&V@+Uft;?3}qa$lK?ua~c#_ea7T~HR;9(J!z zI2Wuf3ti}Ra<*T$YV`Y|=Ib2yg7ErF%ACvp_My9cxc~UA?t#;{t(ntyTia$! zw!OQ2=C)9?l5OorEZO#}<+a;NMzr15e$r5+KYFV>XUVodE^o8#`Vot^wVl*{Tl?je z2w$@8vE@UNZ=Y?U<&Cz6CWVoIuWe_}nX&DLIhEV4L%itnMcdAt)O*|2b0#2x0akKi-j9Hn40_S#8;;AG(w7L@WRL zp*yEN%5@K3vhDHZES$_ktjY>O?= z`Y4ih6XLD>wCc7uc4Vz$4~H(#`rvfOx%}^UxIMAbR8t4FK(B?y@5r4z1pD|MSzs2J z025#Yj7-k$dDRf~bm;v}*CIueVOI?6e#e*{k%LEKXL&m|MQ?xbz3u1Kp{4JZUHWGp z|Q*DE;-wH~J=ouK=uq8JPsnY9~4nR@iRZOFGOFy7TO4pAI1cqr+rM|A;UC7Z5 zpMes6T|Ztbd|kgQ5W1_b-v|`%>-v3;9AQ818+84?VxDPTzwM}aP}h%7CBClTU}k<> z^Xri!pzFuyB2U-vcDQ_9zfFil`*HjhpZyAc_NeQ33>p&9_4@z?!hYN`q^H@iY9{@b zx_-TeJ&`)YmPIhC8X%+7GT|fRcnEf~^^kw(KQHA|Dy79q3oAwTax_%279MJW9gz{MF{^6_N zF1mi_qqMZHpY?ZI*Y6qDEUoMJ80%e;;p_UbVz3{#ueyHQP}P*K-(~Et#d%WQ%U;TA z?xO2A3&np2T|e4i53E)C0*l&Ztx{jt?+8YIKq_KQvVTMIQR^k@`pu^JcuQZ`?<^jg zw5}hQYYXW59m9gYqpsiInbrT~h53jHUB7cE?oroo77zNXs`JR~4LnM(HSl%)K4K-` z%%@rkb^R7Ia$47KDqED+^}B}!eJ5SNBat$o>vtUU4e0urt`OEL^)$I6$-5X1`*G6j zO1{s6XNFpNa#oV|HG{f-H&Vu0rPT1Du3sJF2Xy_qQV!_)arNk+uHS2v1G;{1v;2Ur zUw`J0wMxAccv$ieIH9;!sjus|f$0Ofen+tzu~w-Ue@yaz%CH~j>-y0|R8ZHC=T$vj zzXO>e)+&7m1(~iNUkA~C+%~k(bp5i}B&=1M()D|ndBA?$_gL4@%;@>Lel$3r*7dV% zNkG@{V)hX1$9X*%NseLr_oVCB1Bb`fDm7idr`R(AUB8={G@$FZg<0>Lt{+e3psrsb z<$$i=@f;VhAD3g}E|KiWtOL4!i&-@6$9b(7o_v<+1G;{lIL-pPexGq%1$6ydGk!qV zuO;ILbp6b}T~ODLPXYCG{a$B{g1UYS7z6g>JUzW@-DGpt5o?ut9?l53TE9?o30iWHc zs93A?U!v>BSJVMrzpvOiL0vyC`3YUWQ&D8AzoS+=>H5*6+{z-p&vlBhJ8sc>CU9Ev zm2N=SFAKiDu3tl{`gsa}(Fir_Jhi`9;Yu!Iynxyt)n=*ocRJs!LG5o4%A?w!Cnu5{ z86RqYo(#3W&zJyee|(kKkXg2NTcS=o*2bVc3gbX55n- zaWU0ZkQdYMHk9eEXv89(f&3`_hA`eK`F!B!&7_OHgmraS7BU{M!6n?Qc&JvHA8$Fh z&`8^gO6awmR={5P3i39_>&djM&2J$F?0oDc{mrjA5O zxg|U*?iy?Dk?0KmBb5A*y>f>6&4+Ua{br#U_l#!jm0KZSOTUwlfxFgP_BrH_u(v%C zl{?G4I--Ayv9~=DbvrA`HXH|$3wE?!j9BX|7AFWSGcUwiXR+2pJP&)j#XaF=oz!k| zFE|fi9vEIU(6?WIk}KH$U$M#8%So@O8;adMgaZbCiT;@fduzgae(i#O7$e*;Msd+P z#fZxR-6iBx82E7aC7~5={v>^*b$${A)QcX%>1$gdez9mQ z(aW625mS*t*jcusjt=JGI>-50nLpyBH)Y0mf>=tHU^3U4L~su~%e|~vd-$i5dahDS zIiB#^x4wRDah0gZrk1UeLwRe*&DD-q=ppe@41g8|LVDqA`@23`6J1Ra+6*koPQK+$6oaFMUvFE z8m=E=M;W6#AP(P*(4C3^M;JcdU|?*9GR4($vt~?5{{f&%9qpI8b8d)Y$NK^={SoA4 z=B}wG)tX^^6`nSi z{|eG8w`MM1o~qoV;O%WTpxFyfIBds={f>cDT}KC#W4QRam_M`2$L=~)2(|`mG!yKk zuv5FDjt-U-T)R1hjUyX5T5)a|!Q&uZfZZ~t<5f?nt)qjDLdeoOI#jO}`&zHQR{jLS ztJk7ny(aj>DD0dXsYCYKP&KQfKVnfuwzrvOHje0kJ?t!8QAY=d1fuvO!fTLa6-~9$ zu@&gpQr9^)-Fe5d^IBQ@V+bCdu(LQ=$z#&_@}r<_(bNSY1Fz683N`rp>t?C?H((Sr zfh@(2Lq{BKrA#EIS}9B2z}0dhV)z@52_o3xEwM!739tWZ+`4-pJYxP6iN~;qouw=5 z=y<~OPv^w2)evvOj$wQxd7rs!YM%z#74Sa{PTQE?yI`(^jF90Z2Sv!KttM~v{8NLM z2(g0SEK+{;JH8x|j8&^t~>ZCoK+gl=>^Uz4QId^ZeAK~89uHw+>pXaOp44JHHx;3h4bBL z3wn8Z*s|f4SBqFU%SG&3FE;WHHEqG`m-{Q7={@GhFVM z5>3X!&0WN*DrM}<@O(c6708Z-GZ3aU>5yonn9I1gtSkyY?-W^u3*>k8N_J9svon!t z(H{&R8O_1+=kZv#XmhYp_h?b4Xy$>@oD%qTMHSp=HjC}XjH5YSqnTY8P|%27UF$Nx z+!4`2gk^P$7IsDle{gDP_+r!{8tc|5nuSiz?qtURhcEorscva0)>;qW;FcDkXSnYA zkV1qoqYEq>v^0u>nd4rZ-4UD-URpGRnPuT%L9|TTq*Hc>7wYbIK+Gpj9T3etC=|gJ zG_};R)!@YVmG=HEFG7@2~e>HLq&n%&Pg7 zT=E;$=VJBdSZ1q$r&jMytX{(9y9FsWHQ8>^Tvsk8?ARh=<=E|R7f zaQ7mo)(hXOcE5kdVoCO$<5A&irnl^RT5mnD5W2rmy|1N~jzOwY=@C725&Cq-{Mu#JRp=S(4Bx~!E^=&W zaFRqhFSAZL@~N(>oIPW9)pYL&RKbGyj0HUHDrVMT9L=sNuUv`)>KSZiB3=3X=*Smg z=q`V**!+1FbI}as&A#})tn=R4e`Ek(#tr6>oRT#eXC%&y{~)$DdRAmz_-w5BJ}jqi z=*B||d5mutT#18v|_Q8UQTqb=T+df#JW*uh)pz!rA!H9D~Ex;A`+Kq#N2_%blP zg`J$V09Ux)Dxj3}cM7M5S9%L$C0%|VV|Cg8Tnm187eGva#WaeN>AMSKZg|6KddBw3 z5>;X;A<))&2b)qxU|SN3eLU_A?Hv!tb3DD+EfY7;A4_)-UMWu zHv!tb3DD+EfJJz>#&kAs0Hv!tb3DD+EfHrRew0RSt&6@yi z-UMj#CP14v0ouF?(B@5mHg5v7c@v<`n*eRz1ZeXnz%DqQSl>g$QQ`^WJnTxW&6_}ZHgAIEW8ho)qRpFtzs;KfZQcZE^Cm!>Hv!tb3DD+EfHrRe zw0RSt&6@yi-UMj#CP14v0lt9C2Fta16X0i(ZQcZAn>PX4ya~|eO@KCU0Hv!tb3DD+EfHrRew0RSt&6@yi-UMj#CP14v0ouF?(B@5mHg5v7c@v<` zn*eRz1ZeXnK$|xK+Pn$S=1qV$ZvwP=6JRASkL(AVHvwKI`6lr`@oDij(dI`W{$DBM z*nS~?MPkp(^l0-WAUC6o_-*BH^CaM3D*t}+w|Nrq$6uAjA0_{>;xY2CkX$9sk^dse z%fz$9bHxit)ZW$j{2TFE`M)Ch4RNdZk;wJ2*&k7{P;4T$ z7dwgFNR)T5l@rUA-;!nie#k<5u#V18v*6n!n zUzx`p-o{+9iD+**5ndv>gGfygrsGF3a)fx4I6<`kD}+}{w*M{2t0b=x&lb-U?JX_h z*&AB$8u{D*7vx(d-zh#LJ}15?zAFAv{FAs%{8*&Q0Narv=8AV`RPV68X}dGF2PM=fsyp zQ#phGSCaWfhwj&TCyGEc|mT3jlw5Z8!nMXHQ2UuvU~KNs&79}<5p zJ|jLSz9_yb{!z61738-~^2Z|8QCLoMu|(`3b{7v42a43fVY(y5(c&@UB(YMQDb5!c zip#`P#52WpBEP1voQp;3%22*bykC4+wEHK7KP~xx#FxZ3#myoWZI~ZdizO3cmPj*V z^iPU*9|m_D$+UIG@UCKSvA;;A9fpqeRf-t@ z1d&=s&Dc-pbs^=3(DIkRQ(CiZUTwuR5N|n* zvwRm`@YOn{_JXK%T1|~pN{`ary#@QPpLXc{r{*1Y#&N)3k3A;?cK^WVZGYqOfAhm; z!NYemtSKJguj63T=7&v(94vPQ8up0F#js43y991O4YPO%FG-5%(B_BLKn~_N051f1 zFUEG@wlkIAI=KBba5`@yKgRPnKkQ6+1oImi$dBFV_sbP<`)QcRHsr@^s=xVRm%t;K z-(=*+cCvox%2a+g!p$_iKjd~gZXjJelldFNxc^-AM@1@1DR@Z8%YWoOK~ z9kbrv*fH_;jPq|P>oBYB+UIvf-fB17xp?~8*aerCy*%vxkDP|i_Sa84zHID{NT;KA zloYwWHXQcy!`FV0h`0xTx+&xG$*X$Ky7ta%Kgf){-OTyu7pG->aCU>y?_VB2u53iv zlpV!`FgNZ(ilG^+K}{nh1m@ z>V+l{8VQ6(0-^4qLw7{7{62ed(~`0$%5F!g4H_pd=RDCDR`r^dn8k8GNIDn07otAJ z@yqj@G?>cJCsx(Y8orxQx6_EJ&i1=k-8F0NPN5k{yKd^FwUJ9Pat@BH50lS?*R!{u zX~zDIq93E{SAII_wj;{C-n@MkMoiIQj5N3BI*gbjQX}U6kKD}dHfF9`<&T+xWnNFB z2UlQLW((H+y;Kike&!1L%xW@phu3SEshNtC?x|T#+=0QKc>z5WyZjLMr^8wfOI+oY z9=q|C9e5*&);Vs2rtZK4r^bKO5PlJ7uJ2bmXKD;S3Fj91+%(ncdgMmrf}=ftOJvaa zEusABxPl!4Z8rCiq3{_BACBF>VC;rJh!?~zOk95Y9qz&L3!9Y1E-RRIyi+iB&>iDv zxgAEoKQugkYG~ty@Vjtow#^~s$Q}3Rp~L)hjlH+>)3RHg;>3j)zUy@T)u#9V?81HS zyWaWvcC+`Mf4Z!^Y}=n>S6=kz_$9ylbL`Ti%0hpRU2#NN)w|BalW6(<2AvMYv(k-i0Iz>Ucg_cGbz_=&b@`e%5>B7DIe?};4TNCZuc zbfW)kv>)D_~B~5;X$MOza`JKO0zJXRh(rd;$l={s;>ZScv)9{D9GO9p3svN7qkL2YHjE2Z zN+y*fx%0@2EqnibN&afqZ zK{z}db-7ofuCo%qNOVB=aiNODFY}dv3sofU_D2F2sz}@;DUmas)x0<3FaWcdb53AU z_espjE1x#QN!*`zx|N)pb37wIptMbL{zUQ72J9tFUd=g!;^Qr!MD?&xMb3-N>dBUz zdHMS^ZC5 zUrReECzImydBaWg7OF_Rq^ySJyn_BnysES#b6!Mc6R$P+#M(P1=R}6SnSVHd$*Vd1 z#F5yXb*i;!V$KS-=$#y%!C0swrwNp3can>kFD9?*bV>4!OahZv?TZHHQ*C58Ca-#OB6&Fr#^hB`&PtYYs9~WB zFMV$EGZdP@v+J!?92W=gNhOCnkAbC9qHhPbFKZ;zuk1lUI3;*yPny=z+g}xP0)uoaoD_-6QNqOkVv38q=f}nPnx4 z-Ndzsk+f?GCa+S!IiBR)+yo}CdOa9P@*86UlUFq&P$C;1i!l2pM&dKnXwd0%XrxS)VrbWLC=LxF^^6G8d{yTpEgB z1&`z~_9-T>QedB7!()KStKP))rA{WV>J%)imQE%Q4o@V>&9)~_4Tax^M{{0v5?H8$ z2e&!j3MMdlm8E*+f8r-IHMYT@!SV51uY>}&YMB0SMsxIFp%bD<;Lu}BiX znH+u%ygJH6EL71E;kY0B618i!96wRF52}>0Iu!dc zayfvnGglVjuE=qU_ku#i38~@*hWH&Tl;& zEew5{m;a2(iKM;B{mhS_l{_1*2>ms$aFd1SI*IYj@bkRrOYmsz-pS7G$BQb?Q??76 z+XinWIn}j)d%ActTZX;3C41@MJeI_};l=bTMfUE1Jl5th$oJ4MpYaYczYfTl->8Z& zMBeVee7*;{88W{Qm9Q!9pj@Wq_n&9z$L6?$b6Ey;Dq3U5)KteEV$qr)1wWCrtzPE1 zL(Qu{GA_m5wtAZ54l^&>rdfl%gpUgDVdhtbI`L(A3H!q>%V&2~qpT^|OU9yB?%`HB zUWxupKX^Ir@O&PIemKSH=9R=tFMhjiyI@hR052F16GQXR)+lYg3AoB7y zcU<_)Y*-uXlndKG*nf<@eJlJti2Ys)dHDGg_BSX*@RJJp9623;cRkIqxBn2rk#HPN z;SUhz!7&?q2Nu+^FB1M3(%INM4u$X@9PeO9jXEIqWH>?=*PRwV6ffD@UkTqVynTvc zZ+||7gW))c!s)?~#SrGfcP2w-L%14_A5oYbOfwq7r|{jzkYNyd6yWI=d;2~RD&ROC zdk0pw<4y3n0@6C{9e)9#5HHrVuy_15gz<2U;+uBoKvtYrvANjYpGNOQwL7ueomkyY ztY#-x&#JWsNmgL*#A{caBl)U05{6CW|~D2cMq; z-M@$TSllS28H#?#hI6<$WV_QUuOO-;6R!yG-`+F0jyjce|07mg!zd_vz5C3{@%QYvwjX!kg&3&`f2(dyvp9 z2|UR|vy)jI_&sJjp%ariboR8badVT|EV3up{|U`Y=CCSG*F#x>o~-9s3^A{sz0&nO zNI7p|nZ1)a7Rl<_NA;|MCT*y1vfx-Ie}j4V3)ZH8x;6t;n-(|_p+mgdpu2d6$0B#* z*ZIc9b4r}d%z>FBTOh zHOQ`)OQ!1{Q9%E!*2u0aj$?K~z4$r7_jCaU% zX?>t$ue8^JOqA#5yXh32m;x7$OboJojOH$kj>|*+m^dR!aVT+^Fksqe6vRB%S*>KX-cXDR1B3D`Py-4mn}+JmD8H-imnB3n1RX&a%hX(Zw>6 zg80y!;|aURagHM}qe;=}Vv7;oFWM&yLshL%b*dj!kF6lB;-8o^g=oM(7iS{zv^l3R zBd@MgSUayCQ_>|*@w0Q|xZOdaNQOL+S88J!{Cjns$wVuJg`E|VIy%~zfQj{Vw8M@u zL99SFVQ2kaE9qEe!bvOY=%8)1I74E+TGUZ^0@bppbg-(HIUTI9h0wtRXd!eY&}$Y# z2m8lD{2Ft{uWj(K`PmTU#V86yHrUo+zX&^y0kHu)WEUlx1x3o4#nvSQj zV`4Nx)h+l}+wAVm=0BGB*!)k5)Y0*kCnW0V;9YjuIVr1-+Dz17a-Cxc-Wp=Ibfk`s zV>}^IN5@=G$g1PbgLhz$>wx-G%?A}HhGU0mhe#bAlRP0&N5?cz$f|o84)!Ec5FDYX zMx@T~!@w{^P-^4hUu8%3pB-YUECUXXsQ=*k7D*3~ur^kX6Z^e0Ar$hw)4n`67z!w! z>vxwwn0S%lxY&#x_5uiRIMfD*Lv3(4)MnMOlewGW06MPngxWef9`J;vb#%Py2`lR8 zU_~)2p5TbG&_wedp|2W-tvUnIyye~gr#+KL~In* ztf-@-1$NYgXyf@;*QLklg!DLF6db3Eg5z{iRvibdDW0JwBzJ2R9jiT|wvLW7Jz+&1 z{{r|z4uum}VP`wY8?ndWjul7h=)Nl@C+g_FFD0kX5T;F^A~QQ{sWJ3+7QE&TV2kc00Gz*U6)KovgLKTz}8Xz?JZxm4S=jJu7*hQtu5p5xo3a zPITxxc+W~?ZyWq<<7ssu_J;T~jumHlHWf~G+SJi=1q#N$1i^8Fj0x|bXrd*@4_a#* zbK+ADZyfw9G~MhUR)Owxm+WK<7U^tD{hv_5g+;_1%)xS6)X_Z)I}Y4JV5tSwfGz6S zJ!7yVXcelr8hgw+$x_jM8FmD*O5Ejq3eFhfEJai4<~0vN{5D6OLBCkKS$PDZMBA*Y zsd{>UW(UGEhW5pJw5X%IhgD}R!Q+L0pa<;0t%HF7vo39LbdqT7`YNhVaG``j2wp@XXUUMvZ8yAg>|nZ`EM6;x}~m2$o6S?<=XK&hA6Z? zUF_Bkfn%KKPaKUsiWgGIlulkqSU-~24rD}}YR(D7nb^b5BDd~(ICynn{m479<5q^? zMIs7S9Arx8eb|{PM-~q$Yw90b6yRSrTxY^p2<4dpU;hNrQ9(D_W_Mh^0P{aYo9KJVC0k=oclD`O#D zt(VUKuSGh~r(QbGtBw5$^N$$mmU`*@zh$KJeCnn1yxQ3RHUG1bZiSbQ63-Z<^L*;1 z^Ss*B@lTw490SpsN1+uxaUrEgFqIdjO&!Bau{Xylu}c^Dk$6YIJ(V+s0oeDJGsAfr zBj?B-bLO2Z_f*alc!DEUVvnhQj|kl3&JwSs6kf%?yZU%h(5(o63w!h39c(`mBXE!7 zU&Q*5!pB~!T@SSvr;Xj@FjA^M6e1YEC~MaP?U%&}+*4&yDD+b8dYJvPdLaV$xDIL^ zg}&IE>97ZnvUl9u)G>S@_U6vAU5~OKX*eQqPvuNuB=)`K%y3>-k@K!c+0S_rB5+UT zOo3Niq}uf;`>FghpX4oxcdK-K`d)|M@l%^0gV$X@3f-v)x>hh=U+nm|BL-l{za7j^ z!QquK)=!Qo@Jwxf3HVRK{Zc4ZiZ7=k!r{loEmS%;-pHi3bc`wK7*qV44klv%v@kAMRTqB9$*zNzA4!&H0e>&q-SMioDUG&lE7)K+(wvZb_QIp~3eS+&8 z{}c`s|4HEd6!^k(dXZ79dePbAetf$91i>RwKLwsB{RD9O@dMA9IF(Sgn<~b;6+Dip zW{5M6;BJrJba)jX_YL``a%A+F^YJNJpr6K<{R;UqqS&@`BPRL@am4*JaPBGklyvkd z>FBA$AK{^o;8?kIap&=vik*Xi^m^fV!gG!#R%6F#URg(n*9&7=(r>XdB^fxBf0Z}6 z(_zJJ2b7)TR<2jTE;rxI_+{)EXz3=T{;%PUZEC6>lhS2RN|zUWsb#~Rck>gmG>JvGVB=1#MR~;OK`VK4jsH})r-xqtS{4-9JR>%By^|6 zJD&I@_ONsE$~rn8u|&u7puXcdc_3LcoUVS~1nYFIWi+0+$uhz%JROgC{!HyvB-N%C zNRB{k$WW4c;P%IlKX|-Y-fuAf>;&7}5mors z=H|SGYmb;;Id{?YDyOplrzw{ zaS{8gv9v+f%PiC}MmUK`;YBWD!CKshU0{(8X37d0H!@RnFrs#RG@}`Vmby`xnKRpQ z4PnD99&2ru(ehfuc__`SEp%zkE}V~Q#9S*4M$cH>L5SYGDB6Mb>K=_D5RP7rSYr6A zF0iQ<#e>rq-9}A(+ihn=+oLWGN1&eF_TtP4FDZ?-4`&obVNeeh zVtq1bDG&MO&X5&13-K};fJnvY)$nq(n+eQ2qh+*xv6q7aEt=K9OM$*`4$E@~A@`Qi z4#m;IrO|>;(O5eaw!A1hxO=pqC5kL=#6CmXHfS>2RAS939RVAC181NYGs8dXGGGKd z#p@|_(@A^nCUhAO*c>}b;a`n&N1)e`9K)d{%ow&C5zQ=(w!<+fisl`OfNuYafN=GQ zXkIwa3PLk7!*fSOo6#y?W;l;WbQH=ih-MxDXKU31H5hPUNz{f|F>8!5$icR2#3I!A zz>*fxytastj@o@UQIV(Ds$%QZw$VN~1eu3>N8~{BqeVsx(l~lN&pb+aaPL^@mRfH= z-^IFX)VJ;JQl5bs;S0yR9Dv71TcEueUEu5rq7p3*jKZ2@!`AR&kGH^~$mkwz(P>xT z9=nY@B3z9T%PzJti=yU^fZfS(YkC}tp{C-{z0H|-X^UvXwg|G(iLT|q-G@lUyNTr0 z+A_+*$&v^UwbSrWm`_Z^3VMW>m$qrs1{K1!DVs&2#o4h!mWcl4sTFQIkts$peqJ>D z5V+GPO&iZQqg6D~CYs%KcVY5%V~uzq!(W^-z&}~`dY!?r8R15d3!YwiRP8V^xVwaS&muK8$Dx2O%-gPrR_#mkA~(Oj!W-e zw6*3Nkvyq)Pl!wW=w|({zDdc-1ywU(J?Z|RoLu{wwj`bx)W6@( z!er`V{l8^tvKoIxUayw_yKGMW+bm6159Rfc7A&i(rtg!T(!f82_e5s~JS*l_@nG%E zHswx#FG&0!GgoQ$p}xlEI-wOgS=sg0^yO=Z-P)@hoHH@}nrj9t2lvDSW(8jYIBrKi zYxX&;%P1$79UqkuY7onh6uOPvWVngj)NSTAcU!ovLi|owe+zmPbZtu_QfK-17YB>O#Ze;PmNB2H;(W12JWV`PR7CGbbOFTJL z94A(Y)#6I=hvJpuE#dmpx8fV(Ht}mQ7gJ_fKBv==J;YPR zABw*bUlczT2Q~20jTWbhGsU^$O7RTwY;nDKiFku}uee$KSmd>d^~@LBh&{xiqS=>3 zyyGZiOq?K^ok`TamNK|hJcUI3wUW;f*USG3$s0sYEn@uJCEq39EC0tNKPCQ7{x3^@ zUHqf`Ka{*({8|j-8q9j;i;cy$Vn?x*M1A^6K13WM|51|1ipR*mLUNTjNB)Z>FB4Cd z|5=jH6)%uK=TEVoW_J?2UjBE;{}gk!o#OrC z!{SroZ^akHSH#WYyW(HOPsD$SG{(gK$q=)}d=m9)F8KhlgV+ugU)p;tu)$LyTf_m9)TJ=Ecsn=tN4+)L;Qyr=KUMe$Hg2mU*ud|h94@H zi6g}E;<4gXak_Y-xIkPgQpJ(^o*|wk{z&9kc7|Ug-XPvC-X%UL{z|m_RHS=W@=M}t zViVq1BAgoQWU<&@>?ZaS4-p58BgCUbyRSt)$4RCh6!V=S&J#}(my4&0oaxW_XNwn! zmxwgH!|-dwTSRJH(*IuZL6Q2R^nY61B)%ZNF1{sh5$(Pk=}d_PG`#~b%==_8F7g?V zve}IXeLJiN$e**a8SdL%JxuZu;u!I0@p!RZoFQ`cV&-#_xJcv_Z~9*$UL)Qh-YVWH zJ|I3KJ}EvUz97CLz9qgRejwW9Rh0Wz$zO;O__02;D@Ag;IXPRTB__&?#1-Ny@htIN z@kioiBCS_2{SD&n;{RjsJ>aXT^7sEcx8zhAvc``z#B@95!u zKBv!_b7tnwOwMzsXxCAFNVZ)^^;y}kh;N8{#Sg{5i(KA{^?Wb>B-(XVtMhjT!ZO56 zky7pqKUTEstmez+Dl3fdB%UHt!<^v*#UbKIajZB=H0$&uJ++;g?*eg=xLB;Z9_t2$ zZxU}7Zxink?-w5t&8lIjXOHZc#J9!0;wR$g;y2fC4?f}xa zmEB3~D)tsn7rB%H%QwIG!1HC#7Z;0{i7UlFiyK9=#tZV_BHR2=dz<7!!{c8;M+Uf$2{YjUEE*Ub6d%Mjrv;=g1x@a(M>kzf?3j z39#47-Xv}o?-1`6|0+HtJ|pfCUlrdJ-xEI)zY@O_e-e4G$ad8b(?u>F!SJ@?$zl(& zk60uc-3FvTNA|hm6mhyZTf9)bMEsMuQsgoftp79dJMoZ6Z2`t7i8aMq;?ZIwkxQ^J zeXiI}JV88J>>(Q62&5k<+vrBXHox0J^Sd29Pw{2qEYbXqM?6L7S+DsW5B^E^TCrR- zzvmHuvurNK!hH9L+r^#Y6XG-C%i`H368uop^%SL+mA*=L|?UNOq;?3<#f~@JV8+I8&S_UMQO93dnb(Z1a2pwt2n) z-mmZn#a-f);vVrO(L85BzISAQB<>Tx6u%X@J_`4{zG(C;U>iLPut4GMMDv^h;U~*J zUFiLP(CAr!M$ZD|+AM6(d*T7{8!^V;yNItZn&17f&F_A& zufhk2=J!0p$IAYLXn(h_mc3pyzsr&SVcEOI7sao|3bC$!uO1~f6Z6E=#r|TcI8$6C zE*5VTZxOeN+r_uVy<&jBQ_(q#;+Bx z5w90-74H!56aOmi5}y?Jh%bp;TZrXFBHO%mZ5vNOeo3g?VVitEIU;`QRqB3F)L{>R1V#23WZ#ka+e#C_tI;_~>9GuxA%2dT`GV7_u>nK;jCa$CxQrXyrbG7{yXte& zCJJvMwi4Tj9mI}e7qPooBn}k$H<;W%Qy;FKw!VK&7o_sbci;bUS&;hZBRsCeUv;?~ z``Ejo>&$ix{$)Bm(lT4sbd2M692|a@{c1WM+p6`Za=>V_-d?b6*^KIrh+!N++H718 z*!WrH>!R=m@QgqJhAjX1fqx=l+BFEYdEoVJ!k~E3?xZJfyvNUUGh$fk(DU(#En_s| zy!FmSgCnSv^|Bvqy))pqdEoUe&Gq@R=+S25N??1-TZF%KFm|F4j zu7{s_TETHUx*c@*a80!v!>y8}Rz}cXq$0p`V*A zk9oZ5I--62&c$vvUCV-k{DQ2+_N$s8?c22at(qV`Ik+(`-2H8W^I^=F`^o;kOSXmz zcUMF<2A9>^uwcog2`^QoF1xG3w{_b=-;T+P!z)^K_vQKaKee!+F#n+c{G5u~#ZKEB zy1x2gZawFOZ}tS&3|auKgw&hvSW&+}v_Lj54D2g(oaOgKob`7X)-7yvFnz%>75+<| zf~8#}57sSQhMej3wjXe69N6PrNj;F;7N)NW9Edon1@{(iD9o>jbgXqK<*Tk0sU7nx zlH^Z;KPZ0$et*Y%4>%DwU9h8r+|;;uXHWVX=gQJT|Gsc~jeUrqZbOAgdg@YU4*#S7BchxUbQCtVrX_gE-&WnjH?lK)C)y)WfLt$1sO$)RtwWtJ1eo@)tm#Vk!^*?S418d z0#%S96)7F-AM&U5g#Y-8qy}k+{P{hhb8&n{5b+Vl!H&T8!wz=bcECw?!-5Ua#%d9i z_UfLuJ_)UI)&^Gln)>#?w&1=B-^N#QjOwA>$3edde+J=xga;Ll)qhtzNdM4+S1Tf^ z_f-U!)ji}-f4m}+6R1uEEc1|mP$5)cI#whN zt$oPv8~lksqYxS%9id;6ddQzzSP_BW-+&_reR6UkbUji~N)k$Wa}P?~_gKK$7fubV z_vKF6-C(gZ!8s`d`|FJGUs-+k(8VW13x@W|BZ9kEFTQ93$|$&Sgs2G-v3d@cW1HT~T_^>+)5==X`=6Yg}hG2KRB9~|F-i0|D!=|<5b zePtMYED&B9So;)|J^WDiK>2IxPjJhvwV?R+^tERjg^%}Iv!($HLTJHS#jjjY&1ikN zJ>KIZ&Lw|$&L&^p{I3V!iY1{|Y=PFtwbc56fAfc$e_1y{?Za8wzVP#p(pSy>$iM30 zk5(7HRnc?74syT_aYf)3vurp(3}X&VAs*|U#{L?S1t3C`J2qu{d5 zfh9P}2HIzKLoC!juz;d3@Hlcn?PIVB3ZIC?0iIH!_A!w`!4P#P0(^l0wU4?unvTC)bpBHavfAprm5E-HUaSr_yoPg{HE5p*#{PHXS zO%@-dKK3Fg6#N+fCQ*pk3CuyOAoalp1^B8OQXlk(J0sRgeMBhr(H3P^DW^$!@Qkk zW=31GqAoHUMDJzZlVxW4(i@;xjMN8L|A=Pcs6y(4e)c-Gry=!0lMBN~$1wVIvtzLR z(Yt8(lfB6AOTHL&XCSrNWk`KAMAMAa#|V~g`g>S9{Vcr`TQ)q&-K$`fe{T+{5Az;6 zI}$Yw8+Ek#YxC^I4myJ74=c-BO7g$)Q2)i>O&2a)Q4+Dq8#Or`sfBg>LYp)tJ)?rF7;tvmS?9%M=cg!lF7@H=KwRp>ZF9$H1&ewit+mP9CAyI2i)r1A8JGHSi|QWznay}zZSE80 zdd86Y_`>XOQFJ+D-%jreK!YMmWgkd=P{0Th6w&qEqxWlY21Dv2%6D^+`f!^;sSo;? zwYK?({ZRW4{Dch>S8skSJl=^tP8XKAscf1bncXJFJ5ox0 zxbYogTt1poALbIGSfYe7blLAs7p&+M%dyqatYR^G3CL4!D{NN`P3fO?WL$R5wHOd{svuuUXFe)h0A`*ReU$&Awn=j8xv<2v#JyAe_!{B|UhIt)hY zqZ}z>=3D})4;q-`u?~o()Q8)H!Pr;ae@K03M4(3Qcqqu?Gr5w7k^1u zMe&OdN`1I?QtU1k4XF=vJ%-drGCkiTv6}5leRRU1iT!~^d89t5&OoUT_c#V)*Kmg* z^})oH`gnrJ08$^kOhDcz)__$*>cicOp0TG`9;810h#LLbMXoXjq&{voO&t=O#Jz;n zhdbdW#FCjFQXj5e9BYPrl=^V(S+Q?eAEZ7`NBumb$MD0@NPP@50g(E*fh~sA2U`%J z)W;U4fYb+zFj5~oStq1E+yF>@^yOrN)Q1~zrxPpVUO?)@4R`?hAtf(AI~ra zq(0nQo_2i6OHn*qW%{(PYqL?t4!bsA85`S5eXK@6>^$}tH!QXf3?LF!`zD~8lZ zPh&#rqX_Z1A1g(+qhH7I3E_7HZloafu>z$uydUZ2XAMJ_TB(oMnZb7y1yv~ZF%GF5 zCv3h5{G(H=90_Y)jj(V8g;D(D9@9bwg@U)5fBBXWi>xr+aEJ4`TNq-cOWwbKmLja`8b3L?Rcbh16)ow z=Iv{S&Sbo;JrfSXAo)J0e@%{;k6^#&h7}+zgJIS2_$mz7cnAvbkI3Wdva(#K0b7-e znC5WDy~)}XScrfwaK6UH_{Ru{c=Mc(sM%HXT!DbgO`aQ&XIs3Uc5XdSAnLJr9tHA+ z@0%vi4&?cwYMvP0yVizt+on9N5YPS zY0PLh=ZwIeD4^-X28^TzxM#={7GkTHv3{2iWs zG-kp`gNwp7V^z&}!*?QFOStB5;GfIj7Q>-MJCJ1{JW@xQ7?_NPHf@W@t#CKNHEn`_ z{s#9N4XUxkV`{)i!>``za83ETw-BBaXz*QdJkLikRv~l+W8Q@EGCX{%*z`FVA-oRb zE5l|@*w(Hnr3*sx;F_NX<6d~S(%|dgL-6o*8iqI<-XDix2Ap$Ch##5fve~(8ZZ4ad z%jUVw!qaHJHOpnQa@m|*HY1nS=h;F`)t4aETsTuTUvNDJ*OFDM%08F@{6jS7%fJ8@ zail8a$|{Ge(iUQ>JQdG)jg|`cb_tAyaH_J^-w~FD(~RFdUB(0nEoQBz!+%2DLrBZ_ zPtBI0fh{x9jnGVCrV~u2k6}9PoKPae8%RtEmS&7n2At=4b}v|oiRpiY`X(Hwt^4w1 z{b;N@Pj_vg!?G(@okP6!B@BNo7UdbK^?R)6aW|$7{}A2(gqx!^WG8(7CuNv#xt~%2 zSvX|=r)BUw>whMe!gEhs=&(E&t3hwONetf|i?YggR73LbiKVb9z5??h;VQQClXyE< zC)&A2C7bWX*T!m?M5dkV)J~(rvOZ=m7OhiR_6Bcj$`h@*TCFjEqqxa!4Z4db*@8*T z_$~g#Ho!Oetxur&os(jW2!@Ei!b#y7uT+ohSS z?b6(%?b4#MVhhX8b+ujcthP%_SKFmk<>EuGbWHv)LNV@tDf-g7vgk{j%AzlAwX0Hj zY3JQJObBk6>o~<-V2G0t{YLcV3Y=Y_?ee&hQ89mCfC%za8^PR_H=YBroHWtMcn1;8 zfOWHb!uyLY4F1oSKEcY7vT^=F#kUmeQ`_aPn?CssB9p~*1DoE^s!XNkdMG& zl}SRa8~BT+RSH-E3u|2xZyWD0g4ZvE5*tyJEAm3$-KP8j!~^jN`rO?bK)fH1ppVT! zQ7F`Ik|9CaxQ}-?{E(0bfmMC(l98SSwjf;nSq9W%NIIiOLeB=*fPw@(H@U{Fa(eD| zjk)FYJPU{JBA$1{i_MboAG+a0g&Q6$rze6&qmD>9J$Q>iBc+^wv_u#1%_=qqm(qse z>Q~(48mJwfZLTr5oSv8Au$(IKrW=mh;rY-FCw_9nA;bVr9b5oVY^0o?7Os&}&O3(- z;n)u(9dr_k%jsF+8fE45Y;uiR<@DU@8gt9(*#!qR1mbx&yttg6S50^k@v#Xn4wlpN zt!qTe=|OGyzc{6QBRm`#Y>6Eqm^B<8{JDd^3YOa`z%+Jv&|h_PC+6~?otQ|&30-N! zZIszttl7?F?${j2>RyFI=$n8${^GO1F<;`d)fi`$O2h9q*g1^wokj2!O8{%pm($Y* z4olk;<{K59SjaA>Bc{zOr>8rdRZXD(3RKTC5XlBY4dLGT^su8CL9*4R7TaTturta; z*g3@r+hr!gHvcfPKXyVfNqjzerjWu=H@10joHRNQxN~RP9M9arQqqaJgT3Y4dD7(Q zN4yP(#b0N6=1#xF+?nS0%pJ<^pbwMbkR!=6U1p;~gu2sZHY$YSPM6v9%yfAk0a$pJ zaHq>`R0zYJE@vjD%WS`AxGOe&x)TX-6P|UNw)K! z8RIw_RW=T1&k^SFf^Zh`pF7jz$ejQaR@!JD+*UN8pZd)r1NXqO>3I zyR9z-F%*fRa7KTMXNdxHq=peZI|O|5=9cqJFxU;Zb02-rYIm7x&m=gba3tiwGMniKEKrmP|s>z)aVR2DAk?#4phQE>Lg zc;2%gfR~NJg3I=tQ+e%WM!B0k#%85?7N6uR@lAt}4gI6w(6y6*5=9jwis#X@*ss2R zlvL;fmxN{f=OBuHx4-(aJ#;95*bK+Ai?PS_Z*`-d1h@`&5(HXGPyqdI)BB@Fv*A7i zrPv1Zz;ol_bI|$Ja=s_!QNx5Mdcr|wZGJgDZp(%yj^t3b%@t!5g4f7(7PQD zcNfGiINUfm=KQ=D29rVkhThNMaA709hQpNTP9~X_;HQIo(j^Ip$pZwFw_Yd<&+z7yZDfxAP@V%DnZwba=f9s^FDJ_yI89@A7N%CB&-y1$ zHbY-TB>N3%6Z5A3`v`I84NtdbbFhQ9Km6ELc10IB_-ENPew^eyY05ll=GruPafe*> z;5@%l%<(W;GY|pwt>UE4jmzn0Vk9J3nvF`7mW9w}CQ;(-V`7=5ft#g_rP0sC*i%BK znW#i*tq@aS62&V{bFS zYtzH)wuZaSX1KyEY}F{5z5&F!#@mmeGslr0x8ePMrCeOB{pPI*lS6oA1>Sv`I~wk+ zwQYl}jU;BPx)Vi-%8G0r9Q-3CADBo!Fp)fd_b(FcV4I$`o7d5Y(p2coBuTgv9JgPW0w|iIZ z-sBD@icOX?i846c?$0l$XOSDuqWJdLqY`9`;_dkuld2zaE*wVR{BnBcx#7&st7Mh4 z2zP{Uh6cl77!$*ccPK%JJKK5X^l&K}SCR+S+M4k)9Kn-J)L>!?9G))CFQ;dL8_t9I zs;N6Z@oj$Q9$`}TBgVm*meVuK4Nv5bpZ^>u3&k~t!$jaxY4Oc5m!+PEiD`f|C=i=_ z@urWr40g+crxBbz9Swzl6r4RL!D}`SK^w=xvk_%n3unil9ei$T_eQM-;?v=HiMN|K zjN!b);9l8{e!3hu?y24Ar{g_Dt196(jN!a1Xam;{j@M|r(NEV2j{Rh}G4PLrn*dh~ zR|Yo=ZVudqaF@U>gY$0Q{<{Zr^moCUe@SHLzecbozir-V%yF{-?fLop1>V5|%s3vUKxLR$Ul7&A)80QXw_s<1qkVzK%E9!HElvCH>c;wGBr@C$zNu4 zQx@g*Hqt$i*MOeSZ&0Zza8+tJCIavDgGvpvXNT$}Ij82rcPf40c<~~`>VY}ELv`99 z{4`fb2wFb1C}tB#rKHPgN_;WPp2O@Wgz`D3RS7bUMGc{(lM&;D+Cx~TIjqhhk4y{` zRg#I>Ze?Qb%FE-(`0b)R+Fc`^R4s5FWO>Xe!7)p!MVXlK@Hl;1z}J#K8-nh{Fvw^F z+w3vbi?RZBhQRJ@(&1=jWE;y!6v3B&gm6~ns8Xa&hG0o*;OcoCl7V-f-nF1n<2Xqj zlk)IyR#s9TM3(#*7J(-m=n~b*fXqn)=;X{}Xdv*Mlb3XikzqpayXHB{orioTJK7DI zq6UGQo`QCG3)-fFcA0|msG@?B9-N1voD?|E2{c;9hV==>kf~-;Rw$O0$0mg^xLoy^ zDAf}+7D}yWpG*a4h zz!LZq$4?nKX*hH*e3b-J{t11VDhr+`gjn+1{@>7^nU>$yNH>h0I(^~y3nxx08(T7Q z%J{_r8QZ&T_MwdY7X86hdPsvxOA^Sg}M)O-FX!_v{ z#fpBj4vkTF8jd45t6=!Vk!aU{vjENT;r)9IaJ#J1seRO>^Sa?YH+;&(siR7LGjY&x zG=5En#RtcH)CQC8`K;a+QuT9%RZ;>fphJw~($J?0xeery?L-Pqw!C4(@~m@&Ul z%3z}5r7U^)cylhZVrh2t{0~Uic$@Aj4Vku&n_|Q~dA*!7)@SvQaH8Nqo?@CjeaiIG zv180N!8aToUOaa6#Bmc50!2{j%}ks!4q9wRqYVRlV(IYFvqt(V3)+~>68o~*Q2sxX zsqvlCt=kD%O-?y|P}abyQzw;XjhkAMb#lq%tR9m`jfLjun5?3bsiVi1mQF1x&FYX_ z&?>(}?zA?!lSiIAwWMiQhrEKk{456M7v#6jYEm*5^R{$s)2y?{j~<=dA$Jt6aHA(= zm5iM+k<&M;pk4b`?c4D0e*d8+4WBF=L6fFu;IZE|Y1n^wzeU8ifLR?QZX!NCVZawK zt6U_40{EcGYSOU3535OIE;%{B)TF^oOF~iqiY85K=EEO8bPx;0Q^hmIVd5llnmAv) zL|iIz-4m9(QQRWlD?TDVFTNsvBK}=GB!=-MgykJ2HWmAd!^A1#9C4YrM%*m^Mcgg^ zP5eUSi&56cznvyKiKmG}#q-2DqFECh=~u}%YkEb!!Wbp!VskmOeMf|JyjQE!Lx%i_P#eiphM~S)ON#beZIpSn-p7tYBm-&sy=@mR5~Xx0cuyjc?%9INo@ z;>F^X;&q}~^B3tKlWo@ah5d=_@5So)OE1>nK+F|qi%Y~u#69BQ#S@d={Jq7q#ZjWw zrkNvqfq02{nYdEiB;F~$Cw?Uc@b@QdZ!IxfY%O*d`-^9h7z@M1Q6$WX}=jE8MIZi~MHISa7An zHz?gE@p^^dA^UFeeueLn{iOJu!e5vDwrJL(Mf<;y{iVo#V!tGbb;NpNLlS-2goJCO z@DAch3hyQRG|{YGi+n>BKSAM>#Ayn@K=wk>tZj>Y%M`y(;TuJxNdy1wvhNa&CJpjE zLL1Jkd5irrYuvJWBR4BL8%g@p)o< z@kFr;iFWmpeVRB}JWJ%?c(R=FVhM@;njx-HxY5Qzx_cCUzxasa9~X^Q4${3O`vax> zM2x1o^`(i;NYs}nwpTd+gp}?0P5XNdeXl=X}f$BBF!&F~AwCE`-?&!V|c zM!HS1H;a#mkBiTVFNkl5e-l3uKNr6dkE9{gnD@D;x0#qPa!n?NcNDvbr--MDgTyn% z5h6c%V19ES4wlF^%frCFK(<*91NNn|-xog?_lsYPKZ^W}mgOgl<}+2;G1>LS9I=UL z?&FcJwQPRK%yPPjr--MD1H~cYNO7#lFDjV7L_A+K+LQ=iEc-I?N^!NgN!%>nBHk`; z6Ss@zcLU0OLiY3G%i`a}_r%Y{{bGgqgBarP0+d%xxd0S^E(9LEoAd+2BtGw znc#`CyNmpaf$@FC0pd_`gg8;0EY1-5g#+{RD+iKaI*?1n<>DG~gSc6|N!%{-ixK93 zQsfsQv_BO2TbuR)@f-06ktYzwhea-^K$}ZFkXAeBWZ70b=ycir#WTfoM5FzQ{1auD zh%>|s#Y@D?#TDXOv0S`fG{4tS?wzu^*caQmLwrQ!@+%DABU&vXqdAIju3N$Q0`Yk9 zB(YHBsvAsaG)TcSWRDQXi06q@#aW`&7P?6GAH-$i72zgLm3 zpKPlwG*q_L7MdvAY73RgzCc_k{!zSK{Ij@L+$3%mt+vo#WOI=c?%%Vb)e?G5_B-PH zqFKlV>HjX9E1EEWhFD*0C^i-{%OgDOzozhO)E8 z=3+~+op^%Cm0(!T2ywi4o>(T%66cE-iI<7X#9z}Kx<%=37q^MqMXo}__PinP7rzz{ ziAFOQ>5_17%Jj)%npj)p3O0;yCAJq&6uXLr;%Q<(k*nP>{~Xb33H?#_a`8&>YVkU8 zi?~&MK-?idCO#!TFB)xM)Vo*qhvMhr0r5xC;qwoq=Sn;zmtrIH#kOK6v8&iiJWU)d zo+XYH$BL80VsWN;zIdT%p5LJUrLv8-Fl?hO46ai+R|#S}zY(ogP!PW@7;d$KYRb+O z8;Hk=Rx7ALw$%#iB)h9(@Euvk;9CDs#<7LArM(i<&fut4Ef zW5_%=LO4IrWx2gXqiGC#i0q-_7;%DVwT8-MTdg7U{0R9kQMlC}S}yxaal5!vG|z{S z?^)Teh;NARiyw;zM5|f!gKQsu>v4au$cZ5qFEOkw))kKxn~H74S+b2*G3<+ETkWIEWv>udi&g{aTG=;}$mv z#M{Kbh+L10`JWNF6c_Ce#V??Ae zE~e*dS7ezuOPnuWBytHarn^DBOT16qA)4npNN1ksfaZA)_`c#l7XL1OCHnc?1nH8* z+G1TXOUx0uTo}`L6MKuNi(EmB@nglw;xv(qiZR|k@3}(uD)DO3JpVzuEwZk;0B9Y6pvHW%7H6-p?Z;-u3{ENcxm2EYn z9#%M4c4IlOi|>jbh@Xl3MK1ov^wq>v(P~81mu)nnkd8~kF@1N@YC#prK0`cP93_qu zr;4TG9C4m_iTFoxxp<|xUc6f5>U3<+1LDKtW8w?qE8^SYUXcshG5^nEQif|Mi?zg< zc(m9^Y%W@@s6yGj#eU)-@z*q>xc(j6^G9*Hc%`^bv>H)2%DzRsQ@mIFPisVFV<|hf z_c*bYXf>j^xE|yCii5?o#L=SFh?*k1MC5vW%)eB;LbO^@SIfRm+#+rjxjrBBKPo;= zVqS3>K8F8I{7~We`TSp{`P5U-k^6{4ME=zk+do1aBNmHg;w*8lxIkPaE)%a1SBdMy z8^kT*R`E`8hxmy2xcIcVTYOP`ReV$YSo}=fFMcih^xQcpa#02DcZ!%QW{8<$12Id? z5nG9E#148Mo5A{UkCSQZ%`2TfxoqSpXla#|xSU{pWn*WR`SSS5t1oXgzITyJx-Dfrv{CH$)wqE$x=3zhIJQ8E`fayuRKou`l#!vvDP`z2)JXPxF-<%fn-UczH|U zw|U_8os06icmk~VV#ImND?@qjAd=;!z}fck9huDoukWT-(4)dR)NVG8@6^2I4IJn0 zAIrnkikEji{LF)5%r>?IR==oH9^>zT^QIf!#qBGTNpXySP<|W!W|zdVW*GN_+x>9f z_6TXjl}6Az7-)|76NgI|DlFfF~%RqxZP}d zxHXN>4aQAE`*@zTn@tA|t=4U_65Fq9XdU0dO+O-eevdv7ud*d^ADWo`uyrh(XneoW z(7JSM5;e582A926F>uF%CG8hapYU=;>c+JPeO*F-p0RiYRFbgN(*ExjI{Q*;q#bn5 zzip7yZYwmQ+SR+f$G3Zet509>I+U62zGL&gl%#3U(Rv0tS}95XtNMPrF3Gvdzv08e zhK02cIt#)T&ZSQNc4%oel&+Grv{w7Cy1S5iPp>R=pfZ)Qq3@?lszDto9N1SaGNZ8W zQ5y==4pKua_|+-U)=E1VkUs@}zx)ySosPkLrdr(N6zEHZQNrFm{;Qnwj14y)2s)*O z)4C_^3&$Gl$DbozReSgHgP0VZjy@Fp>9GnQw6!i;xcs2=j+5tx1m6iFg+DdzQ1HNg zBZ8}6uLyR5_SUks2c6U#_oak8)=xeViBvy;Ys*W)?xAu&^uSgxa5hw1F|$Ev!-KwI z-LF3oOb%U@v0+X3XDTu`-cjgmNZyxJCwx_4gVQN;)is6w4P&5ll(nN_cVCNhcW)|O zU3eDy$-lK)g>%1Ca60s-R!eh?N?FhxTZ2`n_n*8lV~ro`Tft=LhE=O~F!;ck6{#)G zG}>EEqh9dWI~Zt@e#j~4RgnU}AMw=Qq8)+lzz%kVHW;+GoPslY^r{H9sD_eWgYs6= zjsCR(Q_DvS)*SS0g*sXmQZ;%4bVtD(2zL-3gzeOH)VQR?m9ffM zck6**jneMEeGtUi;LDr7d*wl2QPu>fQ|&{JFKa~PswhI7q7f6EJcf)I5rXaaT{8h? z`W;8)?`8+YXRcccZsp5L7> zF`h{4_Ni~Q^HtcX7R>JEd_CW(-mPmz@Wh+CQXlN?JsE4AHGzHpS{cygdKkJ~k(Kod zGuA?t%aqr=xa9T>s&X~!`{{eo{|X1rD-NLrP~|f5Hy2k=sB$f94^^)C%6MMV*<;Ue#q8u-1Ff_4y;Q)wDWpez4u>y<`d`P&pygnSN2iu!pNEjKU#xvTeR#G z=yPS1p8yJ9fu^yx2n;w$&2eoAIFajcKM?ST z%p1%d$RT~MfIr*`3H;|Vv8&G&2!_miOTJ8#K35B(zHUT>cMHrq$;< z7qP$8=i;(fR-bDpN{s7sbwt)4sMSbS`~!WimFP^5K9~Pl7U=48`T2Ieiar-R6ro0+ z%fAq5tv=Tw)EC$1nvOz`sLz#&9f>6Lxo$?QJ^EZ*(dK_vpX+#(7}w|O&AN}M&((s( zC-k}a-GN7+s}b9h(C6aYW{*BsfO!-8TxYYQggzHv#e4O+V(5^BK36u5sz;w|Hv7P% z&o!9Q9(}IsY5yaAu3>0eLZ8d@cS4`*T(&Hs&-DdclF;We4g2l-T)Wv+tIu^FcQT>R zHJr`#>T_|_rQU#k`WN)M#;}= zMgNjMS9|32=yOeHxgLG4F6<1CKG)lfAD__YdW{u(^tt$9l~k_8-=yUOd z0z_z&rGy~{rM z*Yvq~)`{zL1=tfu)aQB}N&iFoTt>7luFr)fL5nbIa6dK{RUZ8oS`~75?-oLT-DM&`drnmzLqa`7pqCJwm&uo z_4%XeM*WKVT(_~p8tFy|g=%!>GrO8LeM;;L?2A9uqtEp+#)&`8>T|V2@m8OUf`;6j z9eAc;^tl?-*9Sp`aM_E{2hK@GCyO6P^PyAr#VFqCWaO^+(Boc)&1SmJCTs+XKOHW6 zIn%lNTt{OlzsRunQJ?g=D$uB};c~cpPPdvn@H8q5-b}b0?xNGZ<}QRyfISe-)#ozF zTA;R%O%V0DOwe9bMvXOBpUVVMt+x(b4)tA~o+fNN>~#!dA4#8UGajd{fXnHJJ&`_F z9v=BLg3CdW)#q9dn_nR1G(y$V=L(^L`xwSghNaK-5W?<)%i(8$(&y@pCx;nuIVtQY zSD$M~3f|PgL5qv>T-2Faj1K|E!R1V4aYZ$*M%a41Y+eHAN_Gt}VSLeC3l3qB>>5yu z>G;P5P28~72+L#`UpSxShP6T1Q4AXhyFXmxBJA2yRCXLcXLQ;)>GvRDB4WnF9aoeS)>lp<s9{qLh|+*x3-SIXikCJba5qk*^&nDS$uGx4ioO5faKFnM;JD1JP zWixZxJkzXHJnf9Y<+541Y)&qlk<04yY$2xVBBUyWGgYsKXE|I;R;?-*VWw>1Y^exb z&LWOf1vZ%gWk4( zW_a67qtexOFw1I}X#~T3`QI_>N2+x3BM7&hKgHth{Ml99D)^e!_%dslM5djN+G$j} z{F&yGQDDT#0^ZgH6Rk;7YX;!x`NM8&&|Np9h52*wkH4KCDqStmjjfCOwZ|h9e{~uK zd>rKO;IGaTW*ei@b%OslsB~49<_buf3)B5~l`d#JQDmyFB*kRblOmbS`cfE^AXJ0e z&T&Rh>nN`>ROghAxS}16h2&~yLDVj znv?GQ|3sw=Bm9?oT==UE(;4bu%5z2B?&Ec$O=UeU%5&97#A3Q&Aal|{!iK~poqnUo z#Xp;Y9@lR3_cP{iXAnX1?$1OZag`0{e;?L6CUT5-Fu@F5zaQRTYy}9>BHWZic4fEd zI~ooV1oOKQzsO!CfENKQL`?AHj7kTRY&8q$UryhbaEu{qm|FT1byQ3La{BVz2%I=ljZg_Dy_x~q1oZxpAC^lG5PnK&$%IV=>EFvbQd?!3~Sev=n7}Vy1 zQC3dRUe}maPS2OFF}Iwa6hCV}lSqd%*)!m2;D!@z-0)yIJ$+mwQclk(*GMVf0?*@c z><5z0D0$KIrfZay)AN~Y%qpjce}{);bIa*T!9m6<>O=!LlbxPMCVU{lRf7Y*GPDF9 z{*fJwNI5-R2?Rz;e1Nbec7#BIhy#{$#`GdR93)I*hX?&tH+M=e585e>G{{wX%Y@0D zgb)dnu}XMZU4iT6jBsbcAe++(#7+;0!8q|LVGKJlk;v|{3AYV6oDvsW=x$6@)#tWeq1bb5m%w@E^4&18 zWcCG~@elogod|WuKb8Tf=S4W2#)vQAkYlcA{P#qjDJY0ar_U2gIr7?KK^kQ zOAP;+bITLMf93_A;XiYpXZX*YZ-)O*=3t&dxWgaW6T^Q%V)&P$A?R;+_(Qadp5AZ) zUumE`g3-n&?`R0eU?v>8$0@hR9O39=v$@9%X<+@cBN)Y2*;tC_*#D25$8m$racP|y zi9IjIY9RwogmeX^C8-6RW(|C;%#Eb9-eAAtBdiJ`8znq@; zT_f;|%P7w`sDR*!!L6CTc5Vd0If|2qovJw99QGOtEidgeT7mko@s!aM4kMWu1BY=L zG-nSkSdT^i37$cq12DIoXAk$74@sOohVZ^xNdh9u{!tUS%jo!L-P2> z>fGC-Gl(&03OcR3Jqyy$!nj}b+w(rIwp~;(gX6`~W6li&4`A)4|P- zuI>tldl7=CSJg-_PZrEhj)F5;9)V| zhp8#bj#t#qvx9p|7?7BD{q4wAH`?wE`TRk%xdHC|D|&=egzd!PH!Oi4w^n6FHjL{G zz?fA|51+o6n=yJe!J!ER&wb`*jGnC~d;oDT97`p+)27gUNZ#oXD8 zY`oP))_Ij8XU{@b#_;No*!h)X=OUId5sVDPp8v~O-W{}XV||rleaLIaA@VwvV}pq0 zSmgZ!V*Qn4BZ%c_KLsrJ{ZW~!E zcLvWgjNlCjA}jaBbe@6`5y5dqWaX}4WFthhg3IugR_=*1(-Vm4>c&>?i8A&CrxkBt zkhgMAl(8r55IG#P5ZDSw2q#gC~T}B5#@f}_3j0D_VnDr zy8Yw*m%YmOy{!L~`RwAc`sm%!m_{}T>`JH>}KL3U1Pk1SN>4`(lwL~ZX;x?QmM9lH;muPkT{ure= z5!235^!f%9YzJ<^?wxOIHwFUjW+oqR=(&6@o|zGJMh=Z0-lHI#SC3An?lWyxP*az` zM%^C;1Bn|3PHrkLT7-FgMrg!t5e$f-^G1^z3xQ6IWC3InLx~?lmUW zKw={t9^K6^r-%1FxHvI)E3@D6t8Tih0A2fAZ;{PMcLHOMGUQ0q;(Ia z9|L`#SqY`ITD2$`1ofkqt}t4thOzR!@@O>!J6akAsr0~uMbbcyU#wb@oBCEuRE~QtJD!LD1WtHU8@7Nu#`=Q9mD&tYCg&s_U zY*?L^uv!``ROeKWe|+3O4!sPyv^s%gN~N)Tss~CTp9VW2pr#U-%P8v2HX>?nX!TP< z$@y+gi8!|f(0;39MwQv=)}i)EwOu*2{C_B?cHevs;_89bEz79U_D`#+nK4%_u&bYw zwSkgeXiOxjR*QmWp^TO=(I1hdw8~Z}XpIlY%+(c9UsEr zGsR`&5C+g8sweI6aoHwcM^BbyhzN#~CWO+VRaUEIi>z7=jgna?2{Yb-{25C$UW)K# zh0>1>)o&C^Z;^{e)efaM_a=5s;tX_J{lJfLIW>s1{dfUNfqWnGTts-znCFtB1?Z`2Jzwbxp@ zf@;?n4M_;9dCwcQT_v^Nu9DiLMU|A)wm2QL0&m5o)K<1U{Q2pZQfl5BlBm*FGw?8m zM&OBg7~zq?r@pM;ETZ;5qMs&Fq4u-d7)>FlO-Y|^?8q@j8*0+nDUycjcEZp>rI1n@ zI(pK`$s{Zd-(e_cmyT6_08^Sf-CM>Y+gr}}=z z=J@<`YotUgt*ODM3`fvRD+=uY@6}8*AK=FymtZG6TL7;?yjuVdB)wa}tR|BP3HXu| z27LJA@hWzWDmK2l_iVpKGc6P8@wmo(GI3bVG+x9HBbnA7d6MA#5q`P>;%nkGk$qq^ zR!DqYd@PAX%@p22>?{_Fr;27=_`7DB+YkS( znrWZo8pPvd*1`tArHy&)z%e`|nzgTCo3*b&v*tCJt9YZ42K!{${lr1yStPD|qe-}_ z3NIDSTG;R}lFdIgW&LIiY~=ehZMbU`e!aLw;rGgZK-@_p-&2ZzMd5FV?g6+s6Vdsd=NaSm+_|6LNCiYbLK-ojYQ6z4Gj7A#r&r9ktoluscp5= z`Y7J6oy|XFX1WrE&k*N}7l|uLq+3m5|87?JZQ`8@H*02NT)s>j{6ah=*2aw}!yAb$ z#g5`Y(X4fibW>%|6R#4l5&tSaDee`&71Pt*`f%H5+RwXw?gvgUhG>={@3k3j-adoJ z%5Ey=i*3a|Vv%@;$R&4J&M0x5I8VG#Tp}(N|16sOWaQr@d$ahoxLY*$$4K{v?Dxcv z!~^0t;*TO<*|U8SkssvJt|QhHj}f_U7vo!st;G|?&f*Bse6)@9=gFQb&JgE_3&o4Y zKZz?vet^MxH;DYCf;PXVAdSW`c#rId#7D)W`Q97xjl^bRp4eVIQS2`E6#I#TM1Eh) z^2|5J;6&MzMSgEUoPGtZV~Si?-ThQ2Gj2npA%mY`3))K z-w{6&_laMN72?k#KlWk16fsq-D;^~_7MqC$Vmq<3*iGysn%^fV|4iBEi2Q1T_43OJ za+)|@oF`r=E)kcCSBY!HYsBltt>T^H1L6+xG4UypUsSLi{HlU{N8~q(v@1k@NkTh_ z6A8&LO2{mcpYzjhF18fgiAT~@o1pkfVyQS&Tp%tIFBShJt`gUY*N9d-?N-@$i1&*R zijRv=i!X?;h+IpA`_)S1!hEz(6uXODMU3J7#6cpLjAHmGaiTa`oFUE;7m62)my0XJ zwPLw=gSbV!OT16qDee-V6JHRkYNmap@O@%c&9t8t&SiSIUnwG&(xP2gG`~k-SJh0* zSA1KME15B0SMgM_ulVn3rY%-Emx))3tHn*?ku=k`DV_^7v7L{JT%C$G7nUJE6h9Xa zh+O}R@jr+GJYJ*Cznvtx3JuvpY%Ow4B!-)1D8a6>dx@usXNYHuqr`Dyu~;UaFU}X2 zh)YGTfWvxsicg5oh%bp;>W%5DYNUOk@Gr$fqSZ=E!m~N%OBU0_+Tzh-BeAMxS_g%9 z6uXN(#lGSI@f>laI6<5wmWngQs+wwC{fF(nNwivNcgeO|X**>laI6<5wmWngQdE$j4S2be!R!i*$ z*;Y&KPTBX0J4B;Fk9<$d-Yvc&z9DjjB$i)ItS#0Rv&0;+mDol!n)b-wS$3glH0}}p z?`o+1LFHX4t`M&hH;J3Yhr~z4XT&|?TjIOoC*tR#)m}R&yQ&5oSBhePoi3g!o+DbV zv`Mn9R@zM23&cgD)k^!5>@}j*O4}^^Ch;%gJ)+f0+bR1QagX?#_?GyAXtmP5l>M#v zqv-HC2=+5YOcgW524Yo>w0woP6}jFB%jqJXD)tr65YHAzi{r(AS0inQ%6UY5THGzZ zCcY(pD1It_C4MLVB=WZ;_p7>CQ>-J_6B~(*#R9RN*i|eP`-_7`^Bf5ETqb+7c$4_B z_?Y;v_f-**6s;uFzcUA@&lDCOpy^O?Z&Yt+8EKi(Gz-_7?FkqSc1qE_u>sZ}6uI;pZL2X>Ra3sI#u%4-V|uG4Z=Z`;Z85Ix#`sIb z72;LmdeLf&aj`e1zhC4!Z?vBmUlZRFt(Mq#vbn|^)2E8{#fD;Iv6;w4-GT#b(LtHq7twc;(}?c!lIz>xnj#d8fi zmS;78UitmUYi=T;HPLJu6#Hg4iW{M3&uDHkaCyHIg zLh&@wYJ8m~+iHA`l|4}`7RyAg+sE>kidT@h2VX6Fy?Cv{53BWs^jz|fU7Rg05EqGD zrjYe-6t5R=7Vi=77k7%g#KUTRp}bEOPwgI-|DDJs4QXeH^~Hu_6S0NZT5K7;trAPB{KgT;$HDX@pJKj_`Ud( z$W;`Xzpj`i=7_mszSu$RD01ON=08ImCXN!%6Q_zZ#5p1tV`Tn6iC2*r_xPFqZ)vq< z>3MUG*hFk0wi4Tj=DQQLqoeFDVt27f94HPE`R8bC{|Ir6SS*%_v&6aL0&$VJOuRx| zC9V@Uir0!ah+D*a#RtS4;v?eY;?v@*;+x_-;``!$@oTX{{6XZ0LELYyu0d9Po?lg~ z%|7qWV1C>KX4-Q8Z7sI;|JSA1eD%>6=teW<0i%gV+6|A&&2|j_WjZ_pHd`Cff^poA zgTv#CUrookP_^EkK?G{E-kz{+*^HWth}O8zu$ztRjsQGP@O4qdWe7N&7TZ9?+dNFl za~$6f*v-a`LxA-&?wY!AI6v6U#*IRNx88Mq@thdxaLPCR!2Mu%D*9Lj6r39#Npi1U{BCd%7^NS2oZXWO?1 zewzng-{l2(AAobA-E7=d2=JD-Zi2giEDuvFUfyQ-nWq&Tw{a(6#o#LCG5&TqZ@R%< z@jjUuv@wouyQpB_(@59F8X)(B+cr3F`>sX%Z2xiC*!_J9evIW}z-%eqDvy2E$&K_I zpZiZ2q{~7ehK>2Ikma#_)@kPkyuK0L-R}zN=Vr@GgWsF(PPC8jG3{p4L5rwzw8sU7Qh%?@C(#*NTi0&Vpc} z@0j4KO(WWN&l2`E15y4>}YiNvQ|pV%vHT{m@s! z&iI|kD(tV{AG#k1m{%*u*X@mjet-BnloWUyUFbh8^Be{RLyM6okc@DD-?}_F{$O}6 ztw`u7mKF)~A|rhz#0_By{0s9yPDUrh1eURu7Pb1(KOZFrT4ju3F_B;$#(a$Q!A5nT zL{KQW8~-NFLLw)?S9PHlHQ0#2-3SSl7=L&_(kG2|VwWKz5)5q)uoczzA~bYE$`=T% zMtzgejkOr=OKydKa^b7a^wd-eT~lok>}WB|ye`a+@@M;^4tg$hQ|OQ}gTBCLtp4Tz zvj*z3z}xC`z}E&|@5^mZ0?vdk=B`njkn;)HugxHwSsN7j34GX3mz z^r$b~ry9*b_5vqbjYXesb_}*Zx{AsB$;O}dCr?Je4@hlxxuGxpBvii437-?`36I;~ z!_w(z>Bn-PhbOsR5R8V9FFdl^=_WQ3Wy8Xwj%H^CvN6a*K^B}m4AFF|Aru?~qn4A( zSFw@s^vDV@$`KTvkw!l&;%PfP(^iC%IOciV))<_#ZYMd{8f0}t=ot+xp%bFih-puGM z=6%@ol0Umav>Wq2delugB>wEIXb24oKX%kh#>|N>X7@Z9{oa^OqI`E2eyUn+ToU}* zEz*WhALR=_tBP8|#11^C9q0fPd$3#ec8vCAy)UFuDafDQC3+2udNGY^ZvO0UX~QR> zs8>`}_vl?r{JQe?iE`ns@Egf5oBb_{4(A@do!$(c=Fc7&{f@h^H)SLe`Ll;af95W{ zUxWSc&mJ26k+C0Wu#NF$I6T(OTHE}?(Nde=eAH$*j!Roa)nrtibFlMGg5eSV2zw{C zoqYjKC8om>jcr7xFf^6S3pl8EOkzdQRC4V|EXTEvcI}i{7V}T^N8J3WG2YaKp{cYB zS0R6PMyw;_p{eA?w~95RJ;h(=O%vZH)`R;6O(i$JLyT)hg-iU&UzqrgvDaDObiYm| zU1Ggx&#>vc$M}LXJk!SajLl+s&{X=`4Wp~L~EmUA86=8lS!ee#H$&L`kF;u?)Y#%h0+M#})(PIy>!lnMyLKCpqi5F(u@D26*?=uh>}>`tw*hxLv9ZV-USR_saAIW)fTogL z#v@Mb4z>%LN^UJrJHF)UD1@yteOlMG*(hU&U3;*#W4^lk!>j$_g$Rh{vaEIf`ZU<* zH*yc4sYF>BfA%b2GSBKXOi@Sql6i1Ak!07~AD-tA>_R|&o^`@k`m6Kc*1wT`2~8!| z>em0V&6Md&+J``BDlw>m!_$Bn-56kd;SU9QPtm~PO4A6ICDzyyTdc(1H4&qU#uj5Q zK_QxmV&eb%z4y#}vlK;R67&BtpU=GSJ?EZ#Zoe~c=FGW4ggx#r5Szp?*b}5G0QNq* zj@jm0VXl0p*=-^#fIXFHJp+$YZg({*fcvq>ptJj6Fg<2J2AEzZ}_>q-AT zE%O=`pNc`o;(V6oxe<&W<}eiB-ax50vgBdDgo5;(Wtb!TFq8{c1ZNJ5W{yf{$tL3* zM;@~`N2f9OHK0!?k3}@cq_KqjmvcMLTo%JD&QPUTXXLV!*gHv8a-BPOE;Wx!zaEmV zb^cyGfv+Ry-sW@*9_V|UGt7eC=1h01QG~*H+-#^mrrC&8$3hYEG1JUmDH+LDN|%&5 z-ZXQjsZ4wl`(jw_cg%20j33%M7~IyYR8%`wmz!o?IQLv!wJR$NSr~Ggf6)*FWA=aU{+A=3K1KUd^Cu8>mkxzp>w@Og@ zDW9$+JPC=6ETa#KnaNEnblzDWrK@9HQnslGJGZ%@uIzYjBJn@DO@{0(p<2j=TJ>7< zBNGFl5WUd*tRLZH$fR}S!0wZ8a0`#06sPEYIWVYrVCBVmib9Tfgj30P9%R5l8-XGY z_mWO2K1P5$KmsLQ_>)fTp~5W+nR;&@fMDX_A5wU%B}fuK(M~dx3q!kuvG9H86q*$m z>WWBKjrrLJRXGnQ{WAz##z_2rYtK^$eNAaUS;O;-@(XQmS^uIpt9^Rl+QY}!p8hfD zN1$}kphA3LY8pmqMXWN4Pyb8RC(`-V91YryKnn;glXOs^Lvays;b;H}!N;(H3xRqO zu8X!*gNYTE-}DRR#iReS)|%RuyqbDG#NZ{-;QvPqr3Z0YwlY1YH#Oo(84dp|IS7Y5 zX;w=A)h(=4rMZYZse)>qIy zL37P={5F9aJX~64zuwXIbfw{Fs?u0ptf?wiU%m`Y7Hx^{A z<)=aYwAMH4@9gQdA?}a?u2X838u$}fsVi2B{)yJcltUEp*|4;sF$O0Pb!8~el5*Qw z1Kp)G$IAEc1|eCfPx<%qQ=!L+fj_UUl}4#{7!minqP-wA)R)GVLN3}=nj2m4DFyc-}O40IafT>wrQ(syatD`>mKdegrRa?M25A*FW>}zQ^srJFT`KxZn^lYG zmMkqfa>_&wb5$8tzUFo;J?mBdDCQU%pJ262a8)M})l{K*ndv4X# zS2jRHbm@``3}Ut18CXD>WpgYBE#hvdRQG^m$i-p{_g;Qc-um(wmtYj4uCcW#R@&Ht zk!ZU`(k_Cn~Op1l2wNW~ADaEF6n1GlI+Ve$yYaMzC zg^yOSxZ>ocD%OIfEXJk>Q&x|~aO?!9IdCFV+farv=qO!P(#ihdY6II2eY5l7F7j4vD(QCG=GQ9zuk%Bv$yvBfnkZlq}Fu!3QOPl)8zl{dDID#zT4 zEzPSN47#PdwXO_U34Uec;=y^%jd>M#n*a{SZytPCj;f9}Re%v~Dz6@eWpMGZSYBQK z%Em}uRmGBMQ)OOJByZZFNM2=qLmt|>rW~niYog6H^;KYgCqF~=Y9#9x)9qB#%nc6p zm`hA}@c`6>i&x|Lh8UJWj%DY<-Z(@WTDc=K;Av|_q%WIsc0)sLa|EurB4eBCA`|P% zVz_2kMBtOFJl5RY(9|3mp2r5xTQnF|U(nFh@4L3Te%I#oDZ+Qq_QCtdu_>uPcCWV1 zaGhrwV+Vl|rO!}9{WbOso0vD%@P>R-1Fj@*x;xX%GQ(E3*~#o|b}_q}-CaF#qtgCx zGTg?_ubi=J(-jB9k~>_RW%0Jgaag#C;d|o5k+>Ho&x*f2))IUB3&CRo$6?W+*>PC< z(R`d^VS5$lVW~H5365ppFNx#W+n-35(H-$@1GX*whYWSd^WVhYt4{o;Z*Q+6_HB+m zk&&GGlkngT_ilKYq5GHixO~4yAvi{Gs^Cn)lLTXe z&4SAXPZK;}aHHTB!5akc7Q9dJS-}?s-xT~CpcWNO0Y%nbiqx6+XVT5mU{jn7{nAI-9?a(;7K1Q zNLvTe>YFy;2BB{jykGDcLG_jta@&ReQgA5#N>C4xF1ZNa|@dN9zbKTEKep!$Z3`3pTquu^b|p!x<2a_XBa;7C651*&hEfa)72V3qKf z2yPU-T<{jb2L-na{zEW?xk$a;1oH$(2~HJM-vmLfPUuqv&lS8(@Rx%33qC9OhTtcH z>Kh&C%feE}{G)=41l6}P;NK;*`UVDc4xXq`zDRJqp!#+N{Aog$304c%3$_TJEO?gS zoq~@Gz9{&f;4VQwmSX1LNwAL~AGy)CYLMVCBFe75Jprn3Pk^&T{zQo{6RZ+`lhBI= zPZs_eLZ2n5zCA%X)Hf%<8%1s_5#@MO=ywINOesF5fkG^;3e^)M$ma^(S8$-9T6YmY zS?Hq$=LjkvPl%5S9TTh*TqL+g@LWN)?jqeqLT?egQc$hGh`(3pM+Bb`#5DO@o5Q2H zULk!Z`zM=EiHcZRYZdPPaZfMdXjvKVBb~NxyeD-CM{%=R z6>D~~_U6>m>A7gcO`?%s-cVPECnL^OmGHC6`+i` zq{Z)q1|!U|XCEA=Jb3-bv@wct@~A+8v4kjlBFgY2&Feq)*~feYKEl|y4?B+I*Qu`- z`j%pxbOfJc%GP%x!gd-2jmelWeK4l%!;WhN!wxfU5yslfwvZ#P7GY<;Z$+>J4S39# zd^_Kj2s`yn!L3~cJo~WYP6orN@3tQL=`Z!M+P1#+2-|58G-{!bbKXAexbwhp>U-Fs z56eqj-<1g4X{cib^j)=&cG-eBr@rT*&+a!QiR-%wVd^Wu$)gAE5&7M(eK3yaJ%YAe zH{2*LwuK~)a*s>cj@k%0jv@PCyYP4zr?Y&o^hmT{2IB1Y`#r+AMQH@6<9_JlShWx4 z$%E)<2IEu6aepeBK=K}!`ciQ+Pw0yuxfp+=;#8t-nZ_yi7nJYqeaOM?ZFo^6aeTAg z+pq(+drQqx86J?`+XAD#-5c-Sb$hr?-YW&YsLfH13fMu|y?u@_Ot!9vg!Ka2%rz`~ zJXtQ!J7m3rwsRfU=@`X=83U_9_|kir9IralrjCk zg+vF2t-eSLdpI^!>ib~O9xfS$2z>?-*uyc5Jj5PO=jaZtVq{UWCjFsjkr4K9nhb`{ zrOu)*nzZfV(v%|F!(9dGq)qtg0hX#8@=isV_HefYLocB;u!qwMj1bKpVGpNCcPNdy z9WJClgt&TF%9*!ifCqjG?4SP6N474kBG{t8KO?$Z2U}QpCRT=hh zw3<}*a3>+4+xx_HhN*oz>s;#9MRA87pt5M7QpNg1EEw$J*jQo@N5x6pM24s20P`FW zu!pmtjP`KXfea-x?cy|snGt3t?cpRNbPw0m)SgH|d$=4_O6=hzf!M=|yx7BO${#v{ zy6*~%hYH%m@wN;0aGH$U!zl+Xu!s9ObKWYWI6IWjv=6CPqCFhf3)sUwh%TW$+=C<^ z>!zGTO(=@)Q}jhtnCw?csC<;`VU5%p*e{=KEZlavK4A zxL;A#^J(Lis<=IzRy83+=R~lF(`l!KxZx7);XYFJogV7N8oic24vj{8xZ7CfH-gI` zM0+@8NA^|(H>664-YHD8Q8zIdpKSuXb-oOeFA$pU5iQKK}-*OxU-O>3-)kt zQ6Bbi*Q=t=4Rh-?+QaDyR~@E98QQ~Xx-onK#|iA=G`%!@56cI8xTBFjSM>0yED-GB zPE-uo!_f$f_HZnLvWL5#MS?vXRVaJ7rw~JXIL&}P9KDgz9!@i057(a(u!qwO*u#w= z1NLy50eiStSuWVa>0D?JcP^B$RH{v34@a7XQZ(%0NY~r6Z4b8zjBqh^!5)qTyYCj( z0QPX#DjN21Tog$tRj`L+=Wrqkt?l7n1EUL99ooaObGzKbwuC(#bJh8OWG8|>+|6LZ z9*!)rd*ix=0Y-~ASeBw)@!TC#%bpALP2zFW_%w-Qa0CLX0I*xTmD$1`jv8POcQh*i zdpLTFQuc5sqXM`eI~`5XeH54pdpJ58Ibkg7$Egkb*s2 z3nT((i9H+*$2@NR`wJDm1BqY{_hnjgK{A@P3lazZnU;Ayb)i{zqeg+RY}yrm7KI8J z>FKv3G40{rM{@0t=%wf^Y(aLIVGU##SF?-m)G50l~PbZH>G>g+%!n;A= zjx(3VFvn)7QotULr8I2=ICpN8n#ZR<1WDT-ZWnUi+a9hEg~5FU;$RQA45=1C5%M`` z4~PGf2kqew+QVT6VO5i(w;k9Aeb63m_|SgytLj@LE$VGEp1ek4@}_zIaP|H^{(5=- ze{1i>_IqCL`_*XSkROCS+(Z9ad$|8^tlDgwv4r^?ZHS!KZU12_wnc?QXz^s1>)&F_ z#=ViWNznf}W468C@YqIGg+umd==LqQQPV~dYFYTNnaJ%`OB!*YhX329a|dEH=QKMz zXc$LZvHvTEarTaQrT?E<$Q`tibKXY(aBbw&ioZV_Ijp^6?25{KUp8{Xp^G*uC4xr@ z9w*3m+l=QsY2qS5zI!HphTyq^7Yl9?yg~3z!G{HZCurNqy)X2~g1ZHMc&x#E=mUb- zPjH&xiGuZlY99c|trc4N`v-ls(6x|;HQFFcnHFLa|DY7#|rYXHRD$bo+Eg%;LU>X3DRW&<+Jctl9(&V z$D*Xi3C<8aN$?WE>jj?>d{I!nO-1^@3+=%J9O}yycAQ!}~ClV0-+~_v6}zCwwgD>w-H3X@EjL{Yeocf`x)( z1dkwM3>+mmjfm&PwoP26&BZAKp zQI6e0eG zTxLBm<>U3((`JtQb5YJdY<+v$%o#ls`mkKZ^<9auorXF#Lf?Vd%%wt~-ET+|*LRcX z<9Oh47;NTJ@Dj~Fm>17`1Z}w^V3W4k7Lqv1JuYE8iZ*ToYy!ysicyz zbAN$8=a{zJg6N`RIU=18%w}#n#@~V1%=Jb2-nNwk?R*Co4JtS+VKNu_W}CU90xkZ{ zzT#d)o;dcfnRAyYZ*fMCRqo3!KgsB^<+O2~dPkiWa{{Ev{^Pxua2t-G9rkkhBop>>{NTl5 zFZV8E6ZUeyrYeWM+$`jju$Oy>`R?CdE`_Qc_Hw6D{Oj!HN|AZOUQV@l!d~tO);VD> z$3J@xdpQ>DTiDC-#dq9Zj`pNqXD`Q5m)Z&0e+PRx{+D&w%Pm2t?%!VSA@*{@UM|YC z346H#Oq;Nm>%*Q(*vrv))nPA32RYx>UT!$^P1wu*lB)J=FLxP*6ZUfVkxbaj6|+VO zdpYhL=dhRS!7?Z8aoQF<(Inqvh zIUk$ZwwL4PZwY%jwU#*SZ941bCxsN$_oc3~$QNn32S3(J=y&S(aYiBR_ zJj?Yx*~?9%E{DAwKk)pH_HtZx;`VaNs(8Qla!;d5-td$WyTQwrDvsjVa@C$pns}SL^m!tRBz-lwS4Y3{e zYcCf_*YzpqFJ0ud$}7x{~Tv7i{Y@BV<{c>auw8^u$PM<1)nADVK0}w&b`r<^wn3LTlt4E zZZ@|9iI+hivfH=WTzlVfR>G^?K{s*--N<1fRwI00Zsahc@ZWbjfsP=Cxx_jkpKyCsns!FRv>}zUsQWJ))BStR=;9V9KV&Pq?_|Bkxq8r-9Q~pFpnb{x z01V<54dZI@weI5VCFP*kxPxBfz9+A7UvCq~+s7Ze-#EMia~y6*n76z5m+Clv2!7+b zp*(zaz_z8|IOlsl_0DwPw*t71?9U`_SllA6D|CJrpK*sG9qmPIJGe1I^T87NM+qLZ zhtutG&>l{=!$EsE-3~XvmVoo*Zowx7UlR1dD1q@=g1rQX2u>87BN!8G6w8VrU=dwJXWw& zuw0N&VySnf;2DBv39c8sP>@e)DSwk7Kj9`#I~XFbo-T}GySyM3->%POK1_mKCi$>Q z%9eQJ+w6P#^*-bN=Qluw>5aPH+jk<)>pi04_B=gA4iB`|v8NpG8F=);iD~|wY~Og# zVIS;69s_V20>#D^j(N~ zW*@e`HZYv}=#S0rHzbMc`z69mQ-G7lA$Vf#$DFng#_^an1z;^ed%@;yGGkmmIzP5r$%^ljN`F6=a;hBPC-qP+_kPctOtYttIC?CyYMDm% zNj;Le$Udpu{x7jl>N6DOkZ!+EYJUisRshNDeNv}_WABrC8RYlgCv`2j_CBc@41eQ3 zsc`;gIQB`sh@@km)T@}i?34NgYP0t~sq>LS?~_V1JbRzimmnM8Cv`O=_P0+eE$JNl zq&|d%j(t+;n&jK=lWL;k@qJQXLgzU4NsThM#6GD3=9bte_3s!mj(t+MLy=>jRONju zu}^A*MN90HN_Stdb6d^90AFMeGp%Ev)NJIG*e6vv0owmQsase|$3CegEaunkllph$ zme?m%wRd8l)Yn+D#6GFFQdwf3R2J-8?320<%HsQ^T1@**`=rv@)OXk?bqsYU_DQAj z;{NwZ{W*I%u}^AmrcLaVs=PoY_DQ{!suKI89?r&2?32o^D!=PKssCUx68ogqQ`LU= zNiAm~6Z@q8m}Fv~)LvAT*e8|N-mr6{0U!Os-N`OZ?2~#uW53frsU1;y$3CgbPn%<( zRAr;(*eA6!GlHF)?1~xw9SdFMitm&9N0!U6Pb#iS?eW7SX?2~#X;~o2?e#ZPA`=ly=U5RELzE7&MD0S|W zdMS(K+$Z%Z&K>7Ispn9_xld|;N;vmP9YKb3pVWmc*Y~tf>N~80W1m#+b@?6lN#&{& z-zT+&ZMollQg23;zOQ{!$1>Z*KB;sI+-{%L9%wE2g=UlEI5omAqk#i&+q5f8 zBiq0`X&vnyQn?#);N7&2G@YY`+nJ1i&z28{X}=wKKP{8WT{)>R4C8+y-%KX^AkD)q zOM94VQ`kNI!rA+zj%vS8DhmiZw++z3`{Hppb65y-Ocu+q2K4FVv7lygR=a&tSs2*4 zsj|Q?9LowjH>z@BpVW`3dHlECC)I~`PK6@my>A1zghkuIeNr>FVEn-yG-3PqSfVM@F1>Z4>g$6WoVH+} z&F^7@(;t9Q+Sl8omHx*K(e`BRJXIk6O`$&)UQ{V?Ui~9p5SpjJ}CG*!8Zi|D(K>qOvoMFD;4d4ho8#c7#QU` z2vqAXuukYjf_yT|_;Ur-x(oUup|=QLDX7+8#NR9QBZ5x|;+gN)+PxixXG{NHyEk6n z4*GpVH>d-bH+B3gwr_n!2LVsx)v>4TTlIcy-+2AE%fN*5aURHCsg2P0-`Fely~u(2 zeLK*-Qt#}Mu-(EE6}K&;J*l%@4s@^7#~u2x+{N{AemeCX=w7KWLf^h@-)<6pw(T4D zN;URj`*zQsa{IA;dwh@bU9=zDw}&AYz*&rw$Lo&z@@|>qkLCS6PTZ=*ZQmX~K-;%n zkUJ3Dx4syEqmYMv*ln8z2J(#`J5av2<5Z##VEZ<-D3Unhe&2>hA_a=Ae+vr=h7JX< zsBqZO;fnvwe%~g|P#MPkzGcIbFYo;w)7IRyZI}P`^tKX+GX5d za^}bh#z14oO{d*evbki&F8ARRcl9nXhu${s#ruYKxof8x`1IM5RWI%`Qg6TI?_Cyk zo>gM(Jo~hy4}aoyT{!K7p9Wl)nd|RC$~n7wL?-WY_csfVndrZ7bICbKALw$=PBVGu zv#txx&3ElIIv6|7Jk8pfn&jGdM>msGcPbl`!4j9xYxTb^KG6~a&3t*aLG3FQr9=OhIxT&Gq#xC@zpB# zCbmXu;puFP<7ePZ+ioqGvE8*GO_h4}@obyck5(VgHW`cf z-0oX|c3RNqqcavP#yJ+@yf?*%^UT&hTwmtjm`<~9`1=giTp0VS)RWEHf z7OX?-*fOf64mEaMiWn0yriw8SWqP)lv12V_T!>-2UA=sXwB223yScmEUH8ZbMrb92rwe zQuosu=18`M0XeqC^nJ8N>K<(|eUG+ymgA<=Q4=Olur>v5eGVr`(v@S(Yr9hq?E$P5$`@o-APi%NhaqZh!;hzDr)R+Oy15AZijm5+ zxXYw>KnhLMtrr>Dq{99PVtv?@_#E&8ZtvArPv}f~3`?l@=fO|FO!_fO?Y%aGd?T5c zn<9jQl(&qK-+M*ic+e?5@Z-J8w;F7CRZCff=JQ_X;U!OPO1vJ$@?LK-sdXEb|FX+N z5bfahy6FWEEqOY)9)_&~$oe~W;-w>XJAShL1O2-YkwQ~me_;m0$b*{_`->z;cgjmB zroSjz7r>uVr^rlA22(a5jlZaiCe^0I{z1uf#E30U(NNsUHTewuq_EprH{|^{sL1sX z^Irj8N?+!EnAn6GDTh&C-1sylOfqhKnnDu^|40!Irrg5{jS@07BU8ACssFh&wu39D zIAt)&=hF%lsW&C|zaXk6q+okm!yh+3O?eoF^}n3-vZ~) zN>!t|DJxi`w^BHRu_o~R^}+a5FD1p{6G%IZPfucc z7@z9+N#O|7!}#=bm3~V2cc`-;P8Qh?+o?@G?dBfrVF}E^IdQ_KpmoF+5P#t5@I?I+k_C(d%#euKS!aO%ve4+ zFN!$i_8tSF^$C&;XsA?&G{4hQxK~?l@=!fyCroG`-s)m!r$tWH6Avcm4co)J_>`vSK zt6aYR=$h~ds&W{gKFXvpKGpr`4xh>j!T6NIw9~sC4ep2WDK8V;l=$x~wZr)IRO)jW zpAJIKei)x#q>4H>%}1dLCqLTyTX3G;;Usb*kP;^R2EV0@|>*p#@O4G7~?&A_I_ zF(!fWsb*kP;#(-;G(JsU4)rXRYST`JqFE?K`!qezrnxDxf0N611{h%)qWfWdN`l>Y zIok}I5?`q3rA9JWbrMQdHzS#sV@@QYJMZwH>av~!qYGCZKQ<+1=XQC7Z3W{~=Bo35 z*-n%Vi(iPCUN>1?O)dj!bYpzshFh zS4?1Z`w>_HY)U)}Quq%vkX#s_P6X*W4?kYF{-t$hr%V@&Ps4a*!3(e9au}ap#B>hh z(+sF}!T59wlF_|lBg*B1@#)oy_J@x|d0YBC%YjliR(KCgrOV??jQ+2=VB zoHUn{cof8M5qOluUCx*rK=`5BjkC|sK;$F9ZSVVVV*tcMz)) zSVkhvnZ^y`1#q8b%;(53D~Nv(IQ#qs!~_IJFt;`z-+R83G@ZSOS90 zRe%#!Wx;tj#D4(h%brS*{aNh(EN*`mvpCa;HXZ8bZB`WKO zAaxf`m30u&Zk&0{8ZFE$Pere8VbA86)_(Jw48d_Y_nDuqLFIP_q*mcn`Q3rQ%{V1L z%-?Qkv4KZp6uV9ecQY*xp8~E{u4p*K0bMx7aFvCVIX(-T$uHOZf?s3cx+-)`VMTL` z;fhI2I>jo5z%KQMt4b7n1ud>>Avk?qHQ^wKbWx4rS{P1Ya8L>Pwc!x69K`nxuDWmv zi((9%Noo+w=}ooEIXF?yA)@&O<~cN+qJ&gAhe@NhyYR{9q5L8;Ax9Wwet|amv$9yaO}D-=z%GN^vSqgP`A5 zOu=*|;Ynnjk!AEj`7*Q2K0%#nmPgg$|H`K2gB?xp^4>8Ht8p*z;;kmU-rdZ?jG5-0 z<2-Y`bCZutK2~*HACFO(ArgI)%{fTiZ*YQjC=;cb>1HBDf2P37k&G`O(lMIzD30~P zA?Z05T{$oxU5ReOfaw#AsLXIhwOJe`g&`JO#W^qE7e-=T%f;*nTEl=PTmtZ&5 zEY(!HC1%BwOMpTyW1SMF2*Z0GnPALEeb5^O_J}H1qS@!z<%Niy+Vu0*6t|(mpqB1r z7$*|cC-lat?luO>R0p3(sK;p;r>p>eFjN$)RcKf={GEn|608w0m!Vrd%#w`-!hje$osQQP)90`K88jpGSl z;zV+H8v}gK3c}yUfF2~vgKd|CcvQ!rOw zFpE%t(=wXfZ46A(gujh}`I-o}Ek|G#PGm^Xqa6)lcNh3*5_KS29p7z;Nn!v;)W13* z?BS9aChdpEkCBHS9y4D@PS1$@Wx@|_H+mIsBZAg*mHl#>&+ss54 z%uIAald}t&oL$i5>;kpm{0QxA8OSct1zarDVYyuBDO44cAAPQxavab!<`Vci-!hi! zd3quQz$cX91m8JN=d!2I#0e1sXR1n?n6mNrAa1DDc}0LhqcNzx*e@}9wvnR;>})Pi zT$UVO#&L6}4tDuy7TlOm(5uo4ms)F?A^3^fvKEO0;_8U6O_M=R!Rf`0W{ZrjZ47fc z$7P@%(4wLi0lT)1Kw>_|L=?aO=ASSxy!#i?x!aEU}U2~9Y`U)jchF2sB`o-V}vL=VJU z0_l+&zg!imN6{)^w+mKGEdibCu&02>SYj0QYU6CU9H(i_Bm54hWt?oPmGCVP6dTmJ zjlo?wP2(6sP~|p{z}3)$)+@}9FN`juu(phm83B{jULAfx4&jcdk;_;+jhDfrRcY5w%~ z89*6HrXYgfaX3xm*u=CuRz=BA1V{-M)fQn`q6w;_BM9V^FlG>naAK`k(Z+zzVTPR? zB4Eak2tt&wj7C>H3q{055QyN^dS)l|%-*-eoP0+rcUF}j;s8Y=$)T-d|1fIAJSkcD7DxA1i z_y)akjTHA9f1Miy+G%XsE|5(_L>+rpVz!+SQ_N1|SitubpOX-ulMs)0znfj}Mqil> z@#Lk87ZMHvqHcv_2|75Ba4JqL6)W2qScMZ)lQ}iwWJ;o=EBX3_Y~mi>iic>X&+w^y zbq0G~6{uJi^+Xk%a|Lza!Q!5X6H6gs6;7--#Vm_XeoSIfSy!AWOZf9dqqY8K%n32@ zOK@T?5-!7O8B12SF~C(5{CEOTrurMXRwbB0xKJfPQ5pD!=GzInA^;8!xBBG|S7G~L ze0Q7?oa1n^XdD{$8iJrYI8^PpRS5HPT#M5lFZN(j!t&$H=NbH^wv2u#%D3K^M1Qz+ zWPN#UYemc`A2GkNsiCSVS{JFTsf{&9`Ys(lwBP&#`~(^wPUY1%)W`B-(XyKP_ zjnSs&SgHP02Qz{Ex@b#vel>?yX+^9u+FILE+On)M)(jp-MJcv;fFFAh70mvammhH>f!DfgrimCvT4BUnOH2rK^ICW0MLZrWU}kj8%Jd{- z!xEo&o+r?mQA+^wQL;77jEsb8YcL9IbwEivdV*f7 zjzyZ9i6UfsLR}Fq&eX-|i6r&;ssx=QUR+3+{ZD3^S%WiCVJhC>$pQwB@PrCM6(}lH zxzFHaa0}T^ElN#l3z~#lsJ^hB8YQ)y>i5Ub(HUu#XzecEEYFa9PoTf2Zy{5S?eEFx zkHVr|(Kb-jQ?;+<%~b`@_k^s$m(87w=1R6c8W3R@Ow}!d=2*1<=J0uo*eeT6_PO=R z%>2o!_dMCiq(go|L4haRT8@V9@99uD8A?GjrV_y^I!LY~IF;(qAX!!*g0iHtcczLu zPj)_(Dh7nm9zO3FM-(&3X%}1Qh}8*I-3NJwp?M(AmN`_h3O#-{ybtZd9dtb2Tz1So zE6se>B$ww^>Uya`lC7E~s5tu^B=J^>sF`5hGs|p&&Kyri=nmx%95~R^u|GQ}l*1ka zMLtK#Q94MjBZ#ix?1_xDI%4La&{~hDqw3*M4tPpL4G}w+Z;lOdq)o-V&Kik;we{4I zsBFkZ~JYl@8H3f5NQk^QSj8EQpo2G|xX`{CKr!H?(qllE#K+y-f*nE^la9 zSc4LctEplcl^=j5713n|-httoj4H*NvHBZyyr4_SO<<}UTALtS-q4CP>KkPJn~x#Y+x6Vcig z&A76lsgJC$h%E&_?hm50R7;eKKMT~c1_Jn+x;ciXZ*D0?16H+E8%vsMT4K{Q+u@(1 zaT=QDTYf{Wub8UInq%e05?gD0o1BCLf%1kJzUx+vpgOmyrC~{Vvvg=nv~j#@`^C}P z)|hd`(Q_i>3x`G2EkL9Qn}ie=6%LB@g^%r6v^mxegt1EA89aY}Y)Dl~oS2q}ROLc2q8L$%k%ErZm^O_s;Dhh{^Q~TfB zg{5(bnm^5G3k-LA3e}Y*MtXU5l*0@Iu8u>JdoYz&wsKTrLa+txL>Lj6k_8ysyc@yb z#;B=`HK_rNDO!!8*igpNUfa-&!Cu;2QG*+pnikxeL@Q)0se2luv?^Lx7gf7GA>Y*xcSA%!FNMDYAu5WF$HI**LWJd?9fx`l*9m&ur+FwT*tE`umYJ2%mO@{OVIs`TQIoLj?txDNlI&n z4vy*trmS|MUXY5zq~-I@d;HBal+U|NE@p%vrnVnuU9X?3)|0$tcRfun*&S*SAQ z8Wz_igF3OGwsXJ{tw3Q*o0(#d{;8?Q%2!`5jaJ2#B0kjY5z>e&mTqh4&?3z(7-9=c zYoltQmN{pQYAO!odUY+6OO-C4x@R|ZN5_lK-i&(_L6_lDCXQmb&~jKhol}%zeL`iB zx-nK>Q&|(M(47;*vRH|0oVxa564W%8mM@JOjpMmSqF0(@>@X&l_0moT{fI-8Vyfag ziQMXo;W#=z4vEIaz-OPTP$%{1}u0Sht`jqp#F^yP@DB>_s{ko^-QR{BE1tiCKcw&2PGU5g{}{`0O^y@j)(ejNnv3K2jn7 zB*BU(*(~K+$gw3@MgjL1RoasgWxNIe8I>3J{3$tgOFAa?tvqPK1y(&AV0;S z+$n-T5#)y?73?oKLXgge89!IBN^r5@YQc?yR|?)D_<-QE zf`1ltVQx`xs^B4l`GTVa`523G++~`0rXc+Xlm5NnTY@eOAM(=#BZ313M+?%iJ>}L2 zUL;75^5j1vNSjL1ZwmfZ(8M$%|8T*{g2xLk5L_;Jmf&W=>jdu>d{Xcw!4Cw#5KO{A zXMUXp4;36CI9c#`!G(hK49j%q3SK5S7So>mqXp*+)(Wl=+$4C7;2naG3I0`(bCCMd z1$zn>362w-DOe`hB={r2^@3Lj-X{2n;2#9v72G8lfXS$8AHhn&#ez2r-YfWuU|%e6 zOgBt$lHfGK*@9Jqb%M=;%LG>mo-cTZAni`6{{_K!1wRw?VQpeOEl!C81P2q*_rnE8 z5>e)9g0lqY5|OT4=qkZl;V%*TWWiO!KU?VY1vd)6P3S8Ge=hu6g}y^@tMDHa`YA#B z^<_C<6WlJiQ;-WaQZoR+;ff3mz*tPjDd-@(qG(g}+hoM&Z+NnR0gv|6akz1fLRojfk>s7xciU znRL3~0KvlqO9W>LE)-lUc!uBwf;S4@E%?0Pp9Mb`#BGHtFD_pSF}xJQ_E=%IAYVDL zUcChS2^IjWPV zd_?eR!EJ&s3BD%yw&44M{FsA!I|!=#EYO{W&JpY*SSUC|P~DF~zF6oZ1*Zzm7Mv?s zCde0=%=a|G)q;EtO8#2Gp9)?q$XBGQ9RzO@yiM>i!KVbD6IABs(8~`{n4X`C6Tc9o zsS9Zz@5_M6g6V=C1^KZGge}_h(8=ko|_smT}ZH_U}wP|g1rRQeJJFMgywb&Og~1D z7CNM-2+k2aPOwa{Qm{d=S#X8mD#4!!o-MdhkZ-h^&(8$8I}+(%2;L%im!SH>0P&9s z{iGm2^JTgh1YZ|a_s!sM7ka1QF2OGa)tCQ}3-JCIm@deD6-XZ z^C9h32_XPPBH~D`P{9KTK z#L0IHh6K|Dvjw{f<_OYP1k)7=4i@BhYUEE9EEOylTp-8|k0{4)*obQc*9vYFK;F*Hw3vLj+L~x6s`ag&C{Dhx+ZV|j)kl*!@ z{|`Z$*^>?mW(bA_`GqLsa|H(q4iX$8I9hO`;E{r}1?LK$Bv>K1P_RL8vEXvS(*=Jb zc)s8U!Oen~30^IDo!~8kYCm7pY9@i{K8y-GW~U`fv}* z_DUAa5DW`;7wjq6PcToA-&ivJ6v5eoa|KTltPrdfY!u`Nm`s1B;Q4|Z1o=%SK47jNl&xUlQc!q>TSW z@C(6z3VQHghw%YH_5UAqPoWPL%oiLgI6{!$p)&n!!FhtEf@OWoZY{BydFBIG?_%p$)1b-oT zi{M>?zZQH%@CiZn{~!6O|Np>Og#Wsr`o9mp`o9n4e?ykfE0`|WQLvj}4?%t+O!?7* z>i<3HBZZzJsQ&MRKVRsR1giyW1^MkT_5DQfJi+yX7YnutUM+Z?AipSP`o{!+EBHIX zKMKAo_>SNQf;$EOCdiMHsV`M9EZ9X*{m(~yU!eyI4iZ%V_YtrD?*r!u|2V;u1SG;|EpB~sDqvVx7u$U z@B3Tw_jp0dmpT9A?pC{?jqrC`y^{hMY;)&8HC^_u7iJ)6Y$0v`2oe%j^Zvnx9d zf=0jIhCvTH_F>2U6bz@n+0%9XsE^HK>$?VFrr})X@g+L^W?U=ngK<1>5wzuQ#K2-( z*@rF1caaR+NA8eBUz2B#mwOO)mTx}FmkJ)s$G5t6`JP4?L#Yv+^9wQ_&(J>?0oH&X3?O+{Dy&%$T#^=EgUj@ z=->#CZ}y=&oG*|uEp&bRVm;J8R6QjdZW?fA>e^pTs;^Gl;NH1v%8k{@7amd)-1*hW zExWBZ0~gHm4=HgC^nQ4b*T3;M?}yTZ7k1cC{MVaTU0AYZw>whoKeNR6u-H7y@a)XA zDmwQq30&&iIJV@H>|mj}@rLZC64$z5k#}d%>~OKQE@`7@y|L48x;MBsTNlmT6&zWN zbLK8T&<}Kv^lvW4uj|km@4L=QE-C)&=c@vn&7DDO+72TbXK+TztGnD=yc_11#7a&q zsVWH;&3xawY}T$|@QL02s#&}I=RB}GF!8s$&8qu%2e!`IcDFI{@!cs~ zXH9%!w^8NV8FWE@B4oF|_N;mFStUuEf`|JyufI8|I=lMu-L9$!cPCAJaJRA5x7j?@ zw{3Fuyy_>xy??h0Tx;ta9n4Eyn}UNs>0oa3Tr&QHBdiIiM@~twFgVDy&a=VV? z2QN1U3&(vh(N+Ax6vI5+S~p>re}H$>gkA2Sd&A04PyJ<8=WVF)~9Ul zJRxO$GJccS2k{$RpLX%|X`M^1+3o7H((n852;ZN&^xhV{_|;tlUVrs{|J|>?A6j$8 zPInOgN)Lw*(lN73=9M&+7!jifYP@jvF84h1@JDug&Ci~FsKfXV##-jUl%4LBBOz^W zGyA;x?r)&Se{pH|)Qj)+Kex+$|G;g@m!JkaQ(dWpHjW#9-z5`!lz4Z3RWRT_vxm{c z?7Q(k{O&MKqu=4%rhMQwkMs?D7Cn+O>wUL5>wVY6l$~bE?Gwj=8V3rVPc3*pb$$G7 z^2I~VK@*ZU+(w_azRZf-Z1-@;wfbIfwVAuOLAmlH|P@YHazP8Xyc0UI; zdDrK^TUat{S88w^PWJdXoak|&ALs_UgXUp&&hJ0_z`MqM*I#$tb@yV?)AQMF(pgvV zWXyzLtNGCW$L01-00-_!i}={Y^wU2X+>vg@3SudXgu^<`pn%Ia5dv0};i=gb1hoh z$XErL3mIkwtl=4_DkbiFT-y`qvzTT@{Ocn_?d`MGUZ`T6QI(&s0>M6f=P3kL>9Ni(>GWd#;bpiaLKT=6irY3_SzG3hcb5_o1 zNqu+NBZ00-eRm4w5AhwJ@2(Sv#Ch!7DrvJr0ao!L z)k<(p8oHLTk92zw#e-|o(2Z2}Shwwp%nkA3tMAEBI__=YnlyAR>-1DWJt`H~q`u!u zM%p#0?-{9pc1`NrCi#vG@p-N9xwJt_RdI;E7JbjBjaQ_0P3n6=R80s?Wv9O+X{Us? zv&=6ieWdC;J@h9Q^0oAF5Q5LlP?W-N1eZa`l`}WQn@rzZDICpkO&a3!W#8K}*ec-4 zl6}pjS?Y(QC5tv%S>&T%m~{t6bsUY9ecis3Tz^OO?oEf;hI#(7leC~hHKJK zRs7)aP0SCjNp<}2Fkj^O;F{FS2Us~H!xN|vu1WP$QXF1K8m>vT{Dg2Z)5A5Xj-M3% zgfv`}st0~KQ^I^f;)82aEk8Z{3({~+%EqB<(tOfzO?sCq&)hKQl@G2-IhB-aQobqk z!8Ix8h;mKZL9$~g!I{9sMVjNP)%kmADox7Y#OEG z`&u7dld}1<`O+omgKN?@NQBi|0@tJ@Fvr8ISUtEV)h*}_U%~prHK~jU)5A6C zI;C%Vn1-4@xF%IEDstwAkD)wVlj;dq9nPdYT$5^AyC(I)HL0eThQ~8MxF$Us`Ex}N z52r%7COuIx;F|OqO29QKOJL<}F~h&41YDC+g>p^G1=k1Hq?!TOq{W^%|a>Kr|Ei|rfX6kT$64B zBh0U!eQ-@mf^GgL+W@XfuT}I?BZ;dz38ku=k<<@0;zSa<^9~H^4W7C7h#V(9luE& zgCh`71%M0D#jF8blXB&QYtp~4ap0PCk|N=nv4=tgg)@H?AR2`SU`9Rs<*`DVuT5bVGW4s%g}$vAUS0>eB)mE?8Mui)$j z`}awT<3-U8oVoWPxj89|PFs=QOqWsxdqJOD3t@>qSEhkF3nBM zqq3N5DR{@??6tJOFsG&uk#MR?cmc?> zaiZrk(L4q`+Vx7wNVZbCq|EWAnKR8)WbVp^XTs57V)lyS-e01>y}!hO)BhnRgzYae+4h$hZ0|2Iv4eKkc+hQPvG=Frg7i4q zQ=AH_J`%@)#l{icuki~(ISoOhW0xm5GD^zeU;Y^%9W8Fn7y~DeJ(hY;fB%*eRoPqYO-3adLK{)C4`a*4-2z zMO^y~)6NP0jF`b2IMKj_cW|Pc%y!j861KD@%a?d`qb3|`-fltQ=Qxv%CgZbygFfrm zoMJ+H*suHa;F(Ctz1#8f|qQ~i0Im;r=8 z;8ZS)7+{+_{1l-^s)^7L>_{A(xg&65x=!H?UanhU%Sr}#`;WdLY_a(_A;7;{UZWW` z=-S5cE}W<`;Y*y#ZIQC~RYidhBYUJ^5!n*&eine|{)Vd_p0hW&=WK8@JQ}Ch(6p^^ zUqesL$Zym;Z-aZj*2}7S4NZTYUU(_vg#hZeKsz6a;wttAfP)1=0w*sVR1tJ=x~&lc z5RD(GxQkt|1)RHaA`#&o6`a9!BSop2LC_f-pUA+W^>~Qd2m99gEhsh@?gX*{T<;LH zmpvDJo#un3OBY|qP%o{-VuhGJuUTR+?rKsLcfrf<&!prcRE3W(c5OIMno3 zA&x@l;iRv{jk;y@gv7UY33bp3ly+eC?{@;#-uYJivsu39EXPRM+xru`lb>JXOK|N9 zir={FP~7_y=26`H6NZZI{RwRG{)BBx^cf!0S{8wGmO~<*RI4oF zF%R*i(KA!3)tG+>9J}j%8?B`K_yv>^5^Csk_SgXRwhUPNGV=52 zPKiygTMQnzCZh+gTnVQ2su4MSAgC)qb+BGBln4rh{-FmVI3(J#65{BWw~V(`5fKdh zhz_hM@iW~aOjVc#H(!2qT)MUWRCJGZ79^73vMFdUN69t@$xih=L+-SmM)DAc@e zS_0mqbeaq_N;i}xU{#Jp%d!T_nNt>vbrO6MSrHs4+fca03VS;A^91^$5=+S%L?L>3 z^8bRK$vS#FcrxjnX}Z^(i|F}Q67*^(Ts>7C0^L0wdwMXmbhSf39kDN#sxLh%p+}!N zb!05h;~&aVeJ*Qcr(>o(~;t`<0Tjl$3W~98}?AL{n?LF$> zB<4p+ll}YqN z@hJpPO0E0w8+6cH(0|HXkhb&OpT8jff7++Npm8aUR>=?7Ul2@e9fw=lcD@z=ZS1}x3ob&^L7jcFQkLJ?^sf)Do8-&PS zr134n0O1c393ePXutbng)R>-+yNOkTwSvn9`M8Dg=L&8V+#+~`;GKdG3;s^<1;O_P zKNj3A=tF~0Ki?h_)n1RlX+obUSTDF-aIN5G!K(%Nc9D9v3I0j&BSH0~0PzF)!~i&2 zP<1fw_2vo=5*#NuL+~U)8VyqZdch|IUle>-P<>|%Is8{q@|l81 z3!WfYCwPkBxq_Dp-YEEM!QTkJD!5(nAA;(8T;$sg1E1y06C5R|zOx1Y1flB$PZd00 zaEl;cGE>iNymKW+1seoc3aal=5r2cwcMCo#_>!OpkHo1bOR$&V5W$Ipa|C08t%9os zFA%&+P<_t{y^jg~qTu_2UkIx2Fd^3!Yl3PY!DWJL1RoZBR`6rN!|{ri=_U)#6D$){ z{(}&&zDoqI62AH_5%f7iZxFm(PXALFGRP`jr15V4Lu-5LDj}f`7ZvShiKaVVO_}w!&1wY(e!L7ya8y z=zfB{sIlMiNrl2Gg3|?$6`UtnCRizWmf(4U7YJ?=+#-0T;LU=+5`0kbQNd>fpA&pp z@K1v82!0^=iQs2~d@slPxOja5s_PiAhtPcm)gy242Max1aE#!1!6|~%1!+M;y)}Z3 zf-Qn43$7GY*FVVLA@se14+=gZ_#46J1z!~Wv*6o;e-Ydv__^Re1l_#8AwR#MGPDMr zC3JT|b=?JDU3Y{3MbK+v$rB1k1f#I@K4f(ir;t!S-F#T_kL>WWqr*Vc_vmkPvM5Y%97{eQpD zeeTSFbb0%}zjyiky`P-DFUvfY`QKp1m+xudl`3DO z_+!QOiri_$_`gtmQSoKPHx=Jj{G;N>ik~VTR{Tn_QBn41!+wC@&%jJY`TmF8Qsp*^ z+|tB&!xZH?0P;AMFI1ea$o=MwFMNZ*r78>WAmr65U#)n9;yOi_r)7)EE>8>hFw-vg za}pm?>}8E+0!zP2X3Md%I|FvSNkeLdDA! zs}$EN^27ww$@33ztIFFIxowx>yA+>M+^_hNV!h&D6uFCx=~5Ik74fQ9(dR2h6}iKV z@h?!UP;_}yu2h+aH5l*5it80?73&o5QQWS$Lvg3#(~8e4zNYw=qCAJe&rSNwPxu^x z+{{S%Wd0PFHzmO5Dul~MG$6OPQa(+wonof zRlbymH9mI|GySuQFDUL+d_(blMVD9QkjkGap3I-(@}{)n^C9eaQ0%POPjP@EcL_4y zOvS~DE>FspDqo{mqj<9-w-hq{6N=9$?pAz7@pVOcZbkfkDu1kaP?7r)Y0u?NNmtqB zO=+fbOU2U^+bMQY?4j6CaeyK>H`4wj#p#OjTnv4M$_o{jD_*WB&&i0lN#(7I+Z69s zyid{PMR{E1rxc%4L^oo?F2=2XZv&)!xSa*N>O7u984C{X^US}0Zk#{l|BoLSM_V+9 z!&knnM*vPZH%l4KCRb~GG9IRXxq2wNz%X8Cz@Z!dX}pezb8^1P|Nm#d@frl@+NPY3 z0zAcsQ@z}z z0?nH=pqCrQO=!vamSg|lF2rNLjPB;U0Dd;?fEaA8SmDkSNCrCxAMPoW_&pZEp7{^zKJvAwcG93 zo`Vs~xVEhPj`GYKjU%8fIr8mU9b1wfg$nn>^Im^WeJ^#$p+Q5=K2&mc%4Yx3bbsv7z}T-J@EuL} zJ@P>5p<$)oqv>AzXu5s&A@A9-Lv}1OZNjubx0LmP&7s;rx4`<~=0LaLdM`e`IE!wc znYw<}v0nEzt5ZEtk1;B^vw0y_{?6Pi_hHkd9~Sxt<;jeO*UuaZ2GvZ=N%do z%G`Y05l>nU&cL6OdSib2<~HQD8)k z*1Z}E_V;NhsP5TNP|~}hAZp^w{&nV-A=8Z9-g0l|MhmCe1D-(lYB|kb{Q4y=&31j?o*6S+7;VgM zqZ$I|jBW^AaN)F@2IWt)F#e9g)|WJi z2aenD+g+N=iS@i#s5V@azQtd?CT7J}qsKk5D`Hp1tZHw}9}D8#diUdjP#c_6?|$3| z^Z{+44fFs#a&A3<6Y~Mj!B>BUbL;za-1)>dFT=zVs=>^4FYd;?jb z$@D$RCsi{r2w=@ZBD;6qXoh&aT`*5uyD@XveVfh_m7jEi7T5UgbMux_WqV5*YZUbM zc}-=t#r7Yiij0%?oV;5YE8tCoWKBd_?72-bg~iXZuY`GTGVkLc?TL#FjL zKK&ijSY+!{eE1iM-=7VA0B79!H4(7=cUW9M3Ch{MJ43zbp9hQnUu08nr0{8ADSWAn z&ol1++k&@14v)o$|91a&s69BQd#`-Ss@odf+~FFX(*!LHf#BackHr7GA>bF{;cp_svLsZId` za+o*REyoc<;iq9I*sZxE${F`y_f*<*&bYsc;1sU(a5Y8hhA(|G_7?_w2gpPlPQgd8 zZ_usZblN*pMLW!T2K%WP2w#i31dCM+g^#d8{Z-5euVhKjQZXl-&$I(n%nLVVMkOld zhe>A|9H=7BxJS{z0W&x}&;xmdA3^U0&q<-5to55$|I#>a>l(Ue!~Pu ztGot>R3Ap(rHCz6#u@jvC|b1{yf9Er>(bs+vgoJvwk+9HpVI_(_!vqOoF2SMLIYtI zEI6Yj8%xi)({Rci_@L7qy!Jg1aK@egh6n_g2Ht@fCbw+x(oFi9(VtoDWo||o#~gJT zzd~8dgAWJBqKrJ_9(*KA6Yz|C@KJXp@QizKhf0C)a+d3{pxn_oiqE#-(-zOTw`M;+-=YP77#0+U`Hzy|i{U{c zwheO~DEQmpg(7y$#Jg~e;LDnkbH+XRidMim;~w0r`4)$l)70yk@{_lqBy3WABU66) z7C2|zgTGT#rQzSQ81HD>5#fUzPVc6)1b7NYh37DIU)CZ3&$$1A;s>E$Na)0HHEZ-y z8t-79ap%eA;Kw@Hc*dQ5&7`^V!O@b-b<$kw(Jvgy=?rSZBcyHZ;51KwtrNM9c5%kt z87oGFq{Bg+aeq@$WSnv5B2y4& z+z;aE6b>7)o^C3TXBEF2;|gSvU`2AIn+dBlPPG$|@oZhsaa$g#&^n}~$; zq^*_NpQBK2W=tQvFS-7rGp7G_HY3is??+|wmLSJa5NF)E!V;0W1ZUi3xdrENL#!Uo zxH~OqM_yt5amHOo1af4>y*AC~T?M;oL7Z{t;!0!)R6(3^mz5Tn;(u_1IOFcfzDPMu z)6EM$GNt@z~J7pG1WSnuQe5)(-jC&Ag++Tnqaw$TBIO9$MvwdU%+YD#i-xe8X z+&QaL5K}ng&d%YDq;j*vL7Z{tOwgROP7r6@*}2WPv8`~%ow+*s^T@g+!Ws7o$OUKI zsmeDw4an%m03&6D*XE6$Z}R4I?*;PDdhJ2@OyL;32p+M8v*;JG1~}u+nGa{&O^P_< zzFb6{alZfxJdcqvqU8#Fc+K7{63)0k1uLz%QoSlV5KU@CGx1?Y-(doy#d4@paK`;6 z#KIZ(bE&=F%zhMc(qDzn{{~WeaO(XPX#CkIvIhs=KY`FRZIXB1Eat-+ z-uezdFLOe+bKt#yl)e#A#o!7Cum#S_r0KPgx!h1tga$ANWHS3=7~yG_f|pPxvm}fE zI(!ZC%W#D(Cl0qWUJKOh2z4wg4!6_ZXk>j3TpdNyce#p6U>@tryoY$W}~2_5GZ78;dnbs!j-yjsQU!z&0(VJ3tcO?LN9AEtQq4q z!h4XqZnQT->|Kq5^2JJpy+xPHJPt$t6LrO+Yfjx13{<`-NshdqoBknG+_&(usBq-{ z+-#~^p;YY0)0X4N`?(RSu7tRfs+m0U-kd5DH{SzyI{!0TfSpW*+!|tjn9tEcw&r)? z&N#$ob#%t*)rfiSNijc1ti#`lISn!SrkFFt=0{@FvE}%U({~`ornoIf>qoJ?a3{v( zGS42wY%8{M%sdt_AJLk@wUq*@vMUsw;f!{hFs!bI2knQ;T$*BI4Xph=(2hp>}ZA>J45_(gP=b2Z87P-mpLj*EK zcj)6LdjS&P{e;{u#ZS&>;IWNS_%zp~ksG#s9kjfe-h*qu9zp{=UsAXVLKtH?6|Mu5 zbb1pS9FL`;-SAlQ`7(UwHEE%AHP!~vqi|x3_X1xTCC2!!sL^npnV8Acpfn$4Tj(y$ zb)msD#^x(WbZ!CZP>x_}zSWSb;82b)5aB&Z#?Sq5=7zMjOxgw|{j!qp-_faBqf9&5O5tBAQdTu)CNv_<{Nk{V>>?0ZE53~j6KsA5qiT(W0FgHGzIod zIXv9_(Sb>l8DkR>lb%9>J+u@azBa1Ee$-J7 z6|sj#vOMxRhQ6mlkI)#0+eSp^8>Bij3InC39)O1LjnbB)-j>jbO#W=zS4iH4y(KL~ z#_4C_y0C>hGcu#OEyH_rdd-I*R9!=0p8GKZ1o}3=DWUhIJ z@XxeRUKz1FAjB6FwzQG=S*aulN?32z7MwKsm?xs*!H{oVWDW?qJT+&8GR-XW{~4>z z>8a*;ADiKfWEvbiSS6QUnR42-FuP`tF?S5|j`vMW{Xy#a(tdceQP*sZ(Sg=5+4V@M zI?<2$D4v$pNu=(a3a+Ir%mG*|XS}Ybh=&=Z2o2{n*%_gzWDA}^SH*7af$|2N7!-RZ zCm5FPB$wi*TB5OG}^8YUSi)>aznlw9NmpC=C%}QBi7*4s zi;?du2+->!0;dc7dL?L{+}eYq$gMlPZp}eTl&Cd?M2#W%>Js&t>{`Y*I?7>kXO`2q zCW_3FD;>?BlYg%p`5Qu-jUE+1MFfHUicv}6j~sMVLnS?YKu6m)RC0(@=mW>L1#q1M zcNY73lH@*tKo0?hTIEd(#!Q^(B55!xG!NbGO;$G^2BNv!;iQznf z!0mlP$u%MB!^V%-95-#kR;S#{Z`Kz;5U3 z-mH%PZg60dB5)FSgWPVA3^adK2G-;{)%e(t5dK2-8Q>opQ)9P>pX0%muZQ0m4Nkb5 z#i@GQ`iD8ajGXw7Wg#H~uT~!XJa*v9^gAOFBt`4KsjRX8QC@aDuTzivW5|tl@fqMh zn&i~0NMvLUnf`9Bj3}HvoO+Ly@PCxI2kT>ea&aat)(hNUoStUG2pEMH0j?JBXqw?( zdPE@f67Liyl2n@1LrXeQmjLj1SiHd|t3R#jcztaTlY9!?6VbOWf2N)}^TOP1VC z9FK!2as`pQQ`9s`F_9BzmE(1*nZ(<~@#2yB>`NrWti=iJEQvmD41l8n4>@95KDI;g zh$zobDEU*FLl|G`t}-CcE{<}XtHhc$Vr`I^V_l^OUqa3V6EeOq+70-s-RWO-0lk?U z?)Pvg^NYe~e9l*%B`%NqU4j;OwYKnwpDMaP9+K1mrpKMoVLc7MKN6RRvpXG{#nsxP z;5_TjvGEX-Q5ljPJxLiaVPXj~K#DFI{jL?uqy=Y`#WPJ-PIP119>(IB`EIjNONZf! zPq}PS?1$gI*&RJ*N0U(*l2mY0Mk4Pk_nv}RF4N?2WJq%KBxSr~Et9dnf%{I=nhhF~ z)Nz(Xg;hj%zP=DgE+@p6QJ2(;wCpJ3jbfVo%Hxp#PNSH-9~hF<`Oey5@;s$EV%BEV zCK5d<%Y-uCu!-fulN;7FIqPx0O{!(GGSO1VmUs3)nzQ01lm9StHcPT<#g%_|VlX`; zk%ss5cY4D^EnU)`ZiCR*S@la&TINJ3WdSfTCwP2|prpf>nOjP4k~02%888{^a)}wA zQatAMP^>>uX_}l;UV}qnxhNjLg7MY0lSA?m2NMY{TR!>0FKqYXEOI^EO>mqZ+>5#m zaMaP|Aq{tGyBFt&U2spq@fLTlUGTU%-n8z;+mh}rINn+AbqJnM;oRHD)w?%IDQe59 z-Mu)x(WLS?$zdM9ROgO#SARP697L|;VCn|vUhKAMaP#37!m%&t+>8DtaLeJ?NAAV1 z0J@EEo8j(&y9@3fxb1N6l^o|*4SNXq2;Advuc>q6GtO4HpTW^4ZPD$5WAD3{8)s)y z7&i=_Y|kwd)6(tLIIbOj%T&Tu!SQP-`AQxq%>#UB_XpJ_j#YRMvUe z{FxO?XO$V>GyMH`G5jTHE3gk;IQ_UWUAgzry))-6p1XMJoS8F~#cx*G?CDD@mc-fo zFpVS#|M0^`3IE`WM}a?1_=kr?m+%j2&4$l>UeoZ(c(ZmHF2`T7x5Z#E^sR`tcIf;v zeO5Xc;7AgeMw-4wQ4qyl3KGBOpiFC>MD^#jA|OGt79g^fDdc_RwIlCZ$jUE{eh#Ct ziC{sqT1Oq8I6(C85chqD7!9;-VDGa%-h6An$MjmcIlhTDN#C}uEP~du-t$C#twHGr zC9d#rC3$L)e2 z@aM2=d0SbprlAZuO>(O_#+rw$Uw|;t@9QDu*?n??dr=-X)rD$&I)(({_j{ca-L z(U_%6aH8 z4Ab{L#l=XEVervP6C{MfxhU1BajMZd-rxtc4%M1%yxTt1{`^T&fX6zp*eOHf%4nf8 z?5^+(m&SqyMJaT;`b$$rXgrszE1khnb3*0by@U;JS+}PpDu--~ieae8X^rbNfiDr` zAgb^6_3-B7fik;QG`mwYyA|qYS(~IJ`PL^ZqrM^rc4~b-(s39x_gPZ&COIf;zRyCf zJ9U;s8$Ct7*3z(OtxwQeFw4tLww?{vB&W4cItp<qP5<9 z+zJYZBDonu(Z{__tYx?I=1%E~;`YtW&Cc=W_^f4My>v++dpQJ;IW7gHH%Ru!a~$z} zoP>r1%0!3#v56C!e-bHVj<3XuKggb1L;=qj{ts9o zk70H}swOSGIm40gbog^H0SeJ&%EZ4%4(ZT727O87kf%@;vm_*kEJlL|ts1#QGOPoa z7h%BmLmnyC{Aj06tq}H`{{&wo)*;NPQ^%e=V&I5UWB$^4nje+4DT6ub5`z$~|9!Mqvxa+$salw^x~^uZU++&S~7 zS4^F;bhfc{K83PbQK53Hm@#|t+!cs6yJ9*F3Q=75ZX{PLTeN8Y0^uK2JO4fWkRVc9 zFat%MJ8$9AMP*YLE?M;NvqN6ewWrX;&0Me)G?KF`7EDLIrY^y^^r<-_(IQ=YF~y?k z^JlTy9O6kFQxNVu`8cuprZ1kkWbV8&X;^T*#fFU-g7%-qhFluAHq}wP9l3D9;xjWjFI^7c=x|g8_Dtr1t5t&r=n?=cbhtQItuzdpX7fPpJdX>M6~O& zndSeKTT<`#iTWsLOr0}*-n{8@yTX?=?0B;}oT$ds8PgZ@hQ;Gx#oWcD2*qP1@*6*5 z!TdQuoi7$&I(HW50E%#o$~&u~WgPPQz7WLr!V2yM<2~F;&+CW<+8Hrm~z}!oLg3g2E()Y^oqodzI6W5 z#bs#R`DM$DsWUHK0xnWC*!1Oc<5%?RG2NLDW>j1(b1RO+%QUoPp37EQv8Zg$)TPK} z%#g88C!a8_AmL#0-p-%9USU-)ELf zMOZs0;heH1sCF6K-rECe~?7@T2jJ7>{^hNP3vlhyb|#TcE`u`vgtGMzOQ!tVc2^}r*jQo*ne&i?}p5>bIe>b zV&$1l&1TpKhWEjF+F%Xi#4A~08%MrP4o&<^#?i_PdXpkpSl39tEUc7a(`eF_SUIEe zeZp2l z6~oU|9HlL>u-mbVqkt>XhzgLkfh?EZ~aRd#rBH*6h|mtsQ3%T#}wsNzesOlGbHV_ zQshYq%EDC%{E^Ch^(OT8s{D%L8>;_<${#8o zP(6<&uv}j$`Y;z$<{1QHQ^gjFJcYpWc2c>kVlUMXRC$QvaMh1j`3H(qR6kecd5Viv zFPxOf{|eP#t@?E;^E3j>w^{YKtNaVa9f~^@f2;V4;y%R>6ptu=q4+fsZDOIWtZy0- z`DH0$XRhcAiHO%pW$e?Gc*TkXRX>u5c;~A;Q*oi{FH?C95&2xJc!TOU6OsNlmG9H= z2Nidy{uz~bE51g=IQ%^k=?|#>Q$-#Gp#E!>|E3sBbJC>~5#EZ3auq1HRee{Ldn%R? zkzY*1C#ZgsBDdqyUb)H@ipz*dw^GAzQ2jc^&5E}w{#@~H#qC7c-9?0*=M-O5e20kg z?^FClv0m|*VuRveiLhhhL5-NH7$G8`Gl;O)L9vVK`>NbuaVQb#M=Fj{oT1^f6&ENj zR$NI$x+@gdDc(#({y!%o|GO0*Qrw~V8^vc8UnC;kJ4D#sukv9HKc;wG^_~pJzE3fe zh;$Jm>#zC_iaiwjC=OH{qBxw0bd!j%Gfm}%8oosFGS#nE`D(>=M5Mb}u~zYJ4Zlxu zhvH7fXBA&ie3=M4uPJ_@ctG(}#czmcUp}}JgNk9rCW_4zTM=QmK(V`GUn1%~j0ijD zDo#+Gq&QP?j$#E7=`JV2?rO!W6>lQK-e$!*)!(LgkLtH8{z~<~QG8bM9Sz^7ctG`^ zDt@Er!4CkI!>8Dsi2PeAwo`p4#r}$eiKxd|BI2K~I9c^&D$iA1LPS0*H2f#3uTi{3 z_4g7H??J^!6<;DEpS_CjsD7W~XNt#&C|5Asi62(XB0}GW2>WdnJ1X`k!u~+TnCgcs zUP#0oTA_HE;%3Er6?ZGXtN5j2mmDYkGR1opF%qRbc&rt~*OMTIsbHR>?8ZR3PgA*_ zVpqkUiX#+9DRNgC>wAIX48_@sYZa>%Z&s{Tyi@TW#m5w%P<&DGWyRkq@&FO@{ZR1} z#m^K!S8P<|4{yfjE(~IdVy0rQVzFY0;@OJlD2`L)#v0n0u1GE*%G{Mfyi{?e;uVV5 zE6VRU#N#du#^+8A;!hQCSNx^o1B#C+l1zZ{xvPRGzxROetNcer9vo+QYsI#T9Ti;; zWuDSzJb9M^aFEL9D4wTCx+cb(toWbhQkLJ9uve${xMP_1?@^TBnUJ4Q`9;N-72j3- zgCe&XGySKE#})soD8EM$9^mgsV5VZOA~%9k?{X`5P`R@rH;FR*Ohq2Tr#xP9vf?zw zixn3r$~zelzgp#+73Ccb(Em*3I~3*jFZ2(pEWd*x?^2nxRLp;mB2W8M{+r@|lsma2 zfBzzV7scL+{S-?ThboR&{DI;$MY4v`&c%ug6fad=p-2`i#&bEA{~5RPuQdLz6-i~l z^dBgm%&q*5>bcXM@%)OZit|Me=n zoXeY4zE$yLu4R{Fd6$OoRTN$e`1h;)ks=q!SWa6pRWV(W^b8D_bpzlqm1X?^GRaXG z?s6p0R{0{urHYp+Rw=GglywHAU#Id$#Vv|ISG-&CLB&TEg;@^ipHkW7P~M~RTZ-=} zl3If0{Z`S(^#{l)irI>!_o2Q}v8`ff#qNs5iY1C86h|qZuXuqXX_#pDVnxzgP`+Mq zv*N9acPai-@o~i`6<<_*S&@_&w0BJLWG>|#u74mrPq9$3tzs|5GZjgv!T2*27b#w< zxLWaQ#r29eDgI3H4#fu)T~1_qrwHu7r}_^SKT-Tl@pHxFihotK@eIWB$$Acu#2%Cj z6#FO^D~?tiuQ*w8nj%?1nEo0?67Eo5ueeF^7DZBoF#Hk4Clr69xLffhMY4u4{vQ>| z4MO=#Me=)4PE{m{2j!?D`8z20R3ujiiRgP-hk|~A>Z=sjD9XAN;*p|*>2Fme z8wceF6(1)e9yvLv-=j$S4ay%Vl7WNrH;N?Tpq#1LM)7n-l58-1kRo|DD4(w=>r{{{ zR9;L(IaaHDwIVkMGhMABNi!%vtVl8p$}cLC4}{C8Gu7)hd#>g7S7na#v7(QIYf& zl>eYeUJA;`6iH1%S=NbwWT&89ph)To%4aIZ6o)I4je_B`6iG-yS=NPs8&%$-DCKi-A_*cW?^l%d9>`y)?9+9Q6h)FdFutt!0Lj-txrZVt7$^@@yHhKU4J=sUFk4guA~}AWC|CoeN?*5kxZzp8Pu|s`^63wu&7U`zRJGmME4gy1#G6 zsXS3}vSPVnh2lcRC5lywYZR|lT&uWIaf{+s#chh)6(3UEp}13Vx8h5RdllbM+^_hN z;sM1^6%Q*OQ{+GC*gxF4P7El96f+cg_=4e4#X?0M5Tm}MVjsnme@~UFeyHLI#Zijx z@2hDl&r&Q`tWaF2xI~e=;F&*n!V{|$*C_olXu(KfJk;5oa{U|6#VJ_zX z#W4)T9?LZn&P@ZaQH6mpI4NH@Y}!fjo^Ea!TuXN^Hy-D^i%# zqQ10;V#e)lfZt66udx~()QSby%MGiBoNVvf3!M7V9-GIl?^gJkrVAXepQ3{+@qOlA z45PbS(T&%t*dehvIo=M9=jt~iUa2bp-SP4e{K@63M)}^T2>pj>* z5#yIzUt&_T8X5i3eo!`n9!t1lkM@~o(l9c*VEna&&b?fFOp_dME6Vq#8wu#fi_bE> z<&^``u04Bo>(aAJmtH-i(JoP5&SzJsdi9D%yY}wV$I(nnSv6!t4BN5eR!tmXPe@>w zL)mb7o%$x;Ibg?b-oED`m`voI1Hl{5ZrL$b8|Yt}Tb+4R#?5;Ure%e1G!DN|Wp}+M zP-~d$HpF~4H;d)en0OaJ#;#u(y<4Qz`0K6U(Y(}}ALRw)4Fvw04lO)2ALfT{#xCZ~ zo=sWDaay^-F3vh`0WF{h=mDBQutsjSYO{}971_r<_hcV8C+EkE_Qv7ERp%WxLU#91 zoww%J*!0-6*o;`@xV#ab}ar1|;(r@dKCdelnd1fQe39;-(|4Vnp z`o}(d)i~|7OwUojXU0*#*R$EIwY%-g^sG0I`VH@9YyGsN>8IJ7U&u6%`pxM_BSX$R z^l5(Rs6SM3v{l)l2KxdVZws)y*9oQ|OU^*}iY*rdv z7ha#u_XC7F>7`zPidK3+XC-x=wE8phtf92@=#h|gE?SytX~Yv@W;(_ zGLM_7cMr;GG}?Ui>T@W;2U-3jrk`cDj$n6ugW2JuSA(@POYzQ#+KJ^EwYLPC>viDzzj9$j*!}J9DEEGE&4yTJEF*T#C-)kYn_{fwTMc$T#tP5^ zdVn6F2{iNV?zau{9I-uzUVZM9&-vUf!`e1`!4q1AZXDR%ibMpw6?R}K79%1V9nqDg^ z{|_Kp0q?`O&8>j{3fy_%*~gwpME7I%H9S1oXys(Jqkj(l(d@zWbI*-cn8S0@o+=vY zm_3*N7L3y+=W_V1fPFc0yEVFeT6zD-DAddg5jZ^tw#;|B~}B!2&82=#%p ze;afG+k1z_{ZqjeD5CeyP)qt>g+=c#vZ*&xFc}&b!k5bU2dJ1A{tHc&sF)w-wk-cZ6{AL01hE6A ze|R7td4%)PtNwFR=tql$uVovI2vW4b@Eksm!6T(&kUe3p75Yc3OwRsWkXc8>mMVj@ ze=BmUHvJa{meabl_mnL9Y5i|3*;Jp?1a|lk%RN0tQ z4qkf$1aS7hj-m$qO9M|q48MpE|D~DqGoy(t<}x=UbPq>e2FFIZ|KUJCq$Fp*|B)9;`=jC%?k&VK*PnvuiV z?|(%r;BfZ)_iDby;S415zn)13a1S{9D`@$ROj%h~&VK*z)KqD>FFXAmO*EwOBsUF8Puc;Qnt1I;OuAXM7SB$56*tQT_SaC3~=^8AvLli?=T#k{f-=n zaFH5vOGggjTNyGq`<{5dn4JB5@unY~ z{Z4qF2w&9g2WNjv2``TDpO$`b_B&HaNn{yiaP~X#OCv3q9-RG7_|V8+%HZsG-U%=w z(u&Op&VDEUsK{2z;OuAPpqV4hD1)XpZADx_Mb-u zIQvN_E}Z>GXab!5e1C&*_V1z%aQ2f%+$s>xe%=aBC$RyOI!Qzp4xPjw;$C|{BIF3S z9tUVr)GP$M{h5j&#~z1mA`;SffkI|~jzYPaF@5m92Zamy z!P);PVnk#v0cSr2+~dM`?gwYT(}H%SiuDI)zm5px$clSyn$KGRyJ>!K_H%=C54xIfnP&(o4rzZ=Mwb)Jf`l~$t33xD%ETSoJ_HUD@M&vk? zg0tW0M?1pB4nH{i8JV2@7Q?~W&#wvG^AY~D(GSjkrxrsaAJQH;`$@fkH)ce-1O4Fa ze_CoiG18s!!P)QJaODvnl-6lB?QKa^gxCrk#w+0V_et-e6~RnY^er4dEJ4Kpfh zVMdEq2nc|)zY?*)**_fV@o<&JU&85+LFeZl_n@-)`v<{tPzn5-hJyFnsnJw4FCydB z9tqC=r;$%^yPe5E4>>nhmp0LsiPB{Aq zOUjoZ?u09}5Y;SA|2^s!LjiigosJS3<`5~#891yG6JOy*L^or(?;?=f+#iA~yqNWf zwVxwmtvT%m4bG zwj8Ye!?URR3&c-E1=jxIO{nUCL0ABH+VbvDHKS@KM848ii2R4Qq>8)JuYhaIinT@G z6!N_;=I=wVK>iW|{C8<#1uCSvFh*dIqp)orJ|@Leydx>PBBV2%lfuyrgN<)Ib(jGqi<0f=du1#Jr*IJ1&0?-a|l0@f{pWBIaV%RF&*!qp5C2xJM`MEvH7U$BC3()=Z8VcllK z?Sa62Mli+`*h*;bq#|vTBBe-?&L=oUT9#a-^V>i_2o5c^ZPf&Lrnmw<7r~*~w}E8W ztfR0fq43mESdmazLZa+&1db+bfwPQ7E9>at_Z@`FI(oRL55lTCdUnF0F$ru1=r6BB zW#U&9KBsmQ2-;Gm@$jV9achGi=+*^Zw^$imXKCTM5 z0qzbsbRFRV@s4YY$US6ajU)7dvy3IH>PEoBUP0#^0`T8^pfn{M6Yp3;GpYFERdw`m z99qWG%DO6eR>L79g2RhE4%xXE=$f(QhRD2Fjs`fer(Rx1Pcs;Xu)K~%V|lY; zECsZL366IXV4CA~^QQ?Gz$eun!xmt*sfG!;+*}ch2D$t%UK;KKmqM!64IVOd)^R|b z4hQPh5?{B|>gX?q!%agNloZ4PGuf3v;7b1tI5a+?91fh&&Hy42G4ur91YVHdb}fqE z59Fm~q1Q{S@dVxuZW)|fIECiG;KMS)Mvyg@eoj%KdUm5Br8M<-o7rj5QH0r&W>f{h z8Ed0X)p8ss4$th#J?5AiO;|3bM)Tk2+Z^wyOxbSn{*FQRJt{%qqc&J@2^^7_VF^x- zlL>1?JNa6GQ~1fJ%F!))HB7!J)+f;VP)R(2V|t9^brUDCTq3Q9?Z`WKpQN3{5y?d0 zjwXx}@AyR8NeI`=W3k~j!hH^hp~I>;X~!q>JwK6lye5>`PvX<5>^R_YOqSL&S2~kJ=!$g*2kxs8k2%G|kyU|s# zbyzgsnO zd5ue$lwOX#B(`RZd?<8iBqwD&4jwOPrje9h#!R|-@HC2=aSBVS1?!47lQ~A~%IStN zlVb5pRbt8ml9TN&MsSFjcGZ%`^`pdBIA<+;=+MYtTX<`E?Bx~W?ARh+=?Y-i{{Rs6I(hT z3_AyGr;Gj`bUt*Ra1!YdGB7q9=$6wUu0Yhnx}?Yz@<`lQ9v4FtmpCHm10@#7@`9$dOq8HygNbHVkYsu* zimav7b|%xHAgpK6!u)vTkdHKXi5MvR1jcAjb=Tb7cv9Cy0>wslE~`5jEO1s|HryB? zW0W8iB)5ZDVH6O>g{5;KMVYJC|tTjw%G$(gpX8SJ9a}GDSEJ_ zw@Di(P65)M#A|nwipdIu*A7E>dnHHcisDwS(8y@0ohG%UEAF%-kc$4 z&tG!c!ZNUG3ZI_axnR&_;QSfnuyZ*1gt_xyXDs9sEmAICST=L+?73yL9HPH6OklG? zeJYfw-7uXko;q{+bYtP*1!dsuL?OyZ{zr~bFaTmtx)AV9uP9?-5C$qf++RYnH-Fyr z3Oo(}&$7$mzZAx|xUfchd0HqO-vi9wX#8zgepBQB8|*vsEHEuGSFtG(|Gzqoh)C^K-$!wPA{U^U zj!P&+F6j`<6faU-uDDY1M~dqeH!1#H@gBt;iq9zSReVqJkRtbVF<<`LC%U|H*($eE z?5Q|Vk^3V8*NXh7IK$spl=J+Mzfn1aU%CwMq}We!xFWZUFq}J-h;q&zxJ_j_PY+qn z&jY#K!+7b6ofL}|&r#$S62_aWxLlF{T&MnN#Xl+@R{T~m4Zq77uZ3bqMLAav{Zf^$ zQoK>|cEyJkpH+NQ@ngj=6ulVm%qLgzG{v5ZLlnm=mMJb(yh`yVMLE|EdplH?bK8(B z@Q--rbD82biZ?6%T=5yj*Azcc{9LgG?oHb1q}X5aT*V6&=P9mKyg~66#d{T>P<&bO z4~mBsO>D1Wep!lg{upu(m4_&>~QrYE|+oFG%#1O{27X!6iXC`5-}D=D2^hc%rh0|D9U+V*jc8s%QII+ z8Tuco-sPFwp!z!1yF7Dus{TRMKdQJ>_0Oy9^33g3{ky7ndFDP-`Ex}Rb1}<}bpSy* z?~8KDIbY~qp1GC`hrWm60F6Ibaj5F$+%M9}xnJO9)z8s*7b`AQ{SQ@MrMO1*KT)|x z@n?#6C_b$CnBs25mlWk(F!Gmk!9c#Np7s1(@hc+Qz(Ac?uT&z!(-m`6FXx4!m-E8F zcGM$XHx2Kv@r6$g;c|W$y3wj1uXq6w>Es+S{0mgim)kSn;hlqjuj=1We47aOvC0P((IPUgF`WvcnFKQw^Au$rALIWt zmD?$HRpeGSxjz*79}CLzeGbI2C6Q++&Q@HjSgm-oVy)sf#XA)rR(wqHImH(hf2YU| zSLq>lC@^jp=@^_?+U4imxiZskl#(|NdmUgNlDv{8I62MgH%b@%V-w zBL96u zJuuy!iuWl#s3^}l2!CDWcNF(2eyn&<@pHv56~9&FKP#D!JQo4wO{qZcB&5EtVu@m@ z;yH@kxXpMI6elUpRGgzYUvZJ*Wr`~m*C<}AxK8m##ak7BruYlRdlk9Ok>%i4b>iEK z?<@XE@sQ#X#V-_H-Xjm6w~#)l7*@Q#S0Z@DV8f%DXvkhR^)zK+Tn&% z;{A$`DL$e2jN)#^R}^{hhUvIHpSVwvn^h@)qv-M^1^CV3luL^T%mY{qC8*2&RUhL6>nCoRs4_gC%vKRey_+a zxGeus#jh3rrig#6NO(|@XLcArN0Iw=DZ4yMy;MF^aiAhkS}@+pd`jHhOTEjZG+*UK zio!pQ@EcX$qPSJ@PQ`l^A5@eB7)a;xDm|t8llhh2RQ=nEe^mTfk(-HGKH;?nhWYyd zn5mer$Sv;Fb1N~iry{ozQy!sszTyRn+(^vug^JunO!*qc^@=Y461NdE{BA{VA*TG4 z;vU6U6}gX?;lh^q=%xcmmr^Fm4_;hP;{TOxSx&X znWi{Pv0Sl2aiQW8#VW-$ithJ%4rMH0xzB&#yZCo`FM1pQ$7wH`qb=~bBz+Ay;oLuE zJTl1D8lQ}ZuTHtxhshVic%1=E(v;KxneP5cm^VPuk;}uxpQd zF`1?d9IvBou)7%j;a&`*yGzlH7i{kwqB%Lcqz>l%K5Fpnxu$Mfh-TD%fhKJFBcu^>uK+kny+M|8u>E0Xg8hIFh=#u#5+GCpJ zc!en68}V3)KIq)7d!HWB#Pv@(FZ%ZF;>7>woEOG$$?!Xz7eC!zT7Ffzac%ROTLXIz zHqFY|ka=UP>inCG!+*G9aLbJW>#*g|skY2$i;gW?R_B#|nAfD{hb{AJQezq2(`&Nv z3C4_>xi`1i5UEbD&D=b;A)_LzJY&@4-ypW`>`t<;>_+|o9szWQNlz8k?8QE#Uh9gM>tU6HXV zb2E50_M1m?f;rvH^}(7y#r8Brx1WVi+y=Gg7UVs7F!DEQ$2DZUG`1mBoKj=d25ueO z5a^h;er=<#z}W1oOQ|1h4MNzshET_~jVY$Deqid_#xyffKhU?jF_p4qY#P`QK#V{! zwySR%*IW8JQZM3iR*AKMUqCR^L`rty>c{cesqORA4Z#C;n zOnYN${jgMTeJt&&#?W=E8&f9O^|8?EMsxX2d+T}nNe(QX-n5~SSX-{P$=O+o7oG3tjHX8kaaKXzqfNb)x~ zUD=p6WHi_!(zbZkUD@b?HpN`iXaQ~0zwt_x%Ll8e^(Efaji^D|m5nK|UXs!WHVo5S z>qooTH8yJR*|G*bhSDH?n%FTmSsOFD8tcqWYZ_B_qKrGuBN?Fpcu(wI9+YEEqxU*5 zET0kcZw%acMWekFIS+w_A?Qb6aqJrOxLuc4Uy_!(aZRIt2=le-hXwrgBT$bamR)Ua z^wk7wJ@q9Xv!4fjyXshz`;NtW$C}i>k3N4N{T#W~sL8E0IxOF7)b=dzJuSc7Q}^RW zy8wBc-ul5_^G4q-S3zby(&`7M`D(6hw9V_G3DplYQ=tv4vun_A=8vGe24&3SSg_IW zDc<@KrqS6rd{>pRd2#uYX=BPw^kmu)jL++=`XRQjHn^b*?M}aE!}ai?4Tjho16%y) zt6^zZuzvN!Lg<&&HSjYo(iWiY3(Sq)TC+3y(PobsC`V+kv1xnxL(^Vu2vh}cscH;h zL=8;yY`V75JLK9%YYtk(ytdI(;8_={KRbkyr)JlBHeqCc3VxBDgAZEyxc4?^gOwzs zo7pdYeHL14;4kxQn{IAyHY;tqzS-txrOnniC-;cae{ZYWrgc+VX4YCq>`+E6dknsy zzrM<$;eVJr_pO$$uaX~z*WfZBVS#{T^3hz7f#QCm0Y^;cU9w~3E^xE+1C%Tu%I zlNPl`P0L%Gev%q<mv$q};Wxf!;GG?@Foy-hG&+ zJpunpSX0gt#N*evbvx4+@|(r5_`el!lZ>Xn2vNaJGK>CC>F<-h41Q0*UdI%--~&7* zA3)``58%_sf5e#9!zc-ON?17STLvx?zyC>ulBZ-Nbiz}@|IY=<+W?*tAN~1=0iF`- zjg&6<;4$1(##f$_d62{Wcb@ll|2n8W37!)9=O0!wtdS@dcuM31?+rA5U-P#Rl{_Uk zASD{N1ln}^Ev}G&r-Y4`!PP_Zl%(S8(d8+jA9*NGiIbxpUW8(Tr^FEh;S3RT95EFB z1?+&Q#1UPdl1wo~o|4-UoWi5At)Y^-A@3TPAWz97%$uiUz*FKFFv47&1W$=0+F>qc zf~Uk0<2)sf7z%UA1w18=m=W&9qMfB;PB@=w2dJ1A=4o2+lsJ*|!=$kWPl+Q&jVwOW z3Qq}n!^4-LSHV+4KU;VM&$2Q}Qr! z6P}W3w5~iQ^wT<5G{IBi6vYnnAH3ixnJuA#Fbf8r5;m6dl+bX>rTC!J9K81B5WrK? z3PmAL$z2e`NAUrk68f3Zoh;@uHzRZpM_tBGkso>KLYSh#Q}RoidcMV< zQCjkpQfpwPJ<=o)X7YX_yOH;3;v^jtIZaGQXShnbdbwxCuk|Weoz5r(`3=4?>qA z5_w9tutp!H@eU?W$pL2cu?{x!l+Y-X=E?_0OYSxNpdS6gwYPKzHR0-!!&Ac6iQGuL z;3;tmWkg6^L7tM^r3!ZBD~5xo#E}D$-mEZqN*p;9;bCv`lsM@#B7a1t!BgUdcZtlU44x8ssTO!jxQI)h5+}S*qzAhSJSC(l@DvnBPNzNalsHpKNn|l) z@RT_56FenO_)xH(Asjp<4iCzR2+7vTQ{u!Q6#;9A@RYD|$Wu~A89XKOvM=zI@V+8X z32&tncuIJWoWN5;3I*XQiLpxHDVc_*u?qHkBV0HoPYJ0Ll&6HZg40Pn)SlEyBC>Gk zqzx#O*WQf?Ip){UaDXO7rONG3uE{y}IBXMkMPUQ^Gg7#d%8PwQgXic$BpPPl?llc4P}%7(699B9J31?zL$??_$^$o{~c} zg`=RDA0#6A$hc}YS z4o}HGD4KKDAx{ZAw>cO5$y35yo%}y@6M?5B6H&lZLRG%WX+TCd2H4locx~S3%3s1d zLPJU-hs7j?WAIFfQULIjOk@qfQ^J`KJSDsf$x}jJGt>0g_ArFwd5mv7Y}peZUb7uc zlBa~5En1Zz-l}LOn$(D50mLw)^1n!<#aU31r(`x_fv4mK#3K>O-H4O^Q|SDEh2h`^ zGy7?1yf#%{`S^h#P$$NxK|!xipf9wlc`N1hyx!NPX57ZZDr zL3bNmA-So{nAn?$u~rIKI1Ys{V`A@5kl&z=Oi$aE`=t@`cR39~eS8i2iq&JrYzN z)`=t^-!prFz=C`vO_hd3#b(N4qGEGpB@wm@OflpVVX79%EEoeqq(fAb>1pr=2OGzoCOz^`Xao>BgGc~VCtnTTt!a?95@jOlSK~#1A1mSdRB%%mZYeYaKdRPS{ zMvi)6nsQ5gLb=Dd`GSh1gxN9+oE0WG*G#N%-CGc#~8MVb$*Y zJK z(N7_a6Mg07b@Vu+VG2hB-yH=zb{#$Jr+7UnIBf=NsH0rqs^Dp8zdsD5M#lxcNiDTS zT8foPLpgb`5&1PDt$ombxH&jPHzN$0ep5-$9dIZNft@0HdUn8RG8Bh>#9wom16Bao9VFo3NE#)j zoJep+(sHxTZD&Mxn>bMf7ECVk7-qtk?uev2!J`7IZO4ZWCp``x40^&-;+;aMLerzL z2P%0J?S?~35qQfW+qHlni+2=3t9GE09&YvmOAG5XTWt-7eZ6=` z<)G9(;LuKe;uRQ`DCiU^4L)#hqnem}Y(&Gnz}Fc$Hwb?igI9yVpYIZc#8Tb_hmvww?}w8d=!r>*#t#Q@a7$7a?W7W+Gfq(+4+byRNcjFy z&@r%d+u(Xgt`k{+wc;Jet~(~)2`oz`95`#(YAKTaL^jkC@s4KOIGK-i#~7-R$eeSQ zTmgK_6P_0r201sCC+1{4@vte%C0DsW{^od@>s?ZSDFo(>xCG{m`ZrY4bBCiRurw){ znQ#X+RN@Yz?38e_TS7^eC}aGg$|og6k4k5;ah!X4G8^X+DUjT-OPm6+cRq&`b7PPV zdjh3%O9AgGGGXZge8&;&ISo+kSZ1@Ah~>#_cG5p#re_2A#O|aNz(U8%*54{#xwUzB zpo?gb7r!`I7k={c8T=O*FZbC4j|Hrn{D+Bc$h`YVh8HC6j`6%ZP&=5ufGwUU-m!$) zaH#fyN_u$C2@^8=!D;9V5^XL|85c?M#uC^dk}%OST(%cKW(HW;|MGm)HeHSgQF&FbkqSN3k=q5?9u=1sq7 z!J^3(b7xGRGjrx-MCvqu!TkSeVxEfWOP0)?SvK{O?p<+^6r=FJouQ|X%h2P^=-=9# z1x^t#@Q};JwB|&;8J$5@(%PFriV&cc?G0vovm7Zq540v$ZX}09C*I~(zhZA%)cUy@ zwcf5Q8V;_Mz21SG*-ZQLOATjCeJ>xWQlXj3YqSnPl-X>OR5&ozRSr-+Z4(gn?9l=18O9q_@(L&Ie zz(`k+&Y(zONO3)_vzuh+l7_|6cZIhJ<=i}EXHHxV;+qS+X-LztEs6{yWcLX}_WQa+ zZ$%MeO{2Oq#a5l&qt3W*k&K87h|B++Tc^4! z0TdnIe|+yz`Bc95{_cM3*3#9t&%I^oFsCNQ@C>Jpfy}fwIIqZQ%l^xLK*$gg5k_$65Cmcg8P>CL~eP_a%-d9(jaNm+iB0dYGQC9s~*mgv=y*T z$H$yGta`>cled#z`+EeB!aY3Mz?%8>SLuUv)^zyYGY0sis=^0=uzTS6`{7yEcOq^ z2oAi{HilvJE`)S4oHJ~?w=ZGy>2_P~^&lmaoVSq5qzo&#w-TtL7nob zq2yKy1E&>-v9Dm9YRIEke^jY2dkrV;Zr82r_w^BqPs-_pTuVYdI+vixUT#}^^uqy! zx9bi~FVPTpJ0KKgr+4X$gVGnSoIZ5qptF*l##4q3iw%q6%I2&IG{hyOGMrAa#}Uh! zHPyQ?VGP0G32TLtN)f>8N*9cQcDN`lE-HnnRZqsrhUOI2wd_zIr-40z!4`3^B-EX9 z50iIIDb+w=BirQ@3qj9D{rldLXV zTsyxKLNm2BWz<_KE3cak{ftEw4Yk!XAd&$U7U*d7A8gI0jz+Nyq^_@;T~j`ef zAp)_RYKrnyRnK2gS6Mc{p$^g}=oV<3P-+Cdq|C4alhL>_|C)D9c|F7ut1C^=hfC@P?puttb*JVrW@|e?w33=|D!TEFOKDo-5yVM}y zjid-&jTsw@&}-;x{5RLl*}P5`<8woOZP^@LY#^OAe^fnBc#bQKq=gN<7{@O*6?4jQ zbuw2H_qsc~vH=V8R`U7_ajluS*p}5Z1unz0D^0nx=Plq^)O{g-+{^0S050-ddtBMP za+X>>gVzr4(t#>KT!|u3=Juf*fm;P5Bq|xNc#LFM-%AkzE441Z}S_1*5>a#JL&Kvt#6~KyMN>N9{$b2 zE03t(;Clr^^Dj{wif_uY%KdEb6N&N#ARXUS{TRKd-i(hId^~jIP;t0; zu*etF44*DmiuK}R@l5et@iK9}c$0XKxKVsT{Hyq(=;=jmmp_coVLdvDJw&4e0sFD? z*N8^<0rpk$uNAKs?+~98|0yHCWNiU*6+#N)&h#k0jr#T&%C#Ye>##dk!$ zp=5b&FqFwWu~fuwfQ)^D$f-Y!caC_Oc$@fv_@&qeae;V-c(Hh$c$fHJ;w$2Z;#XoS-siLYj$$A21o3QfqsW!s82?}5-uOP8 z{&C{bqNf+dIcN;`^rDu@f2Mejc#(Luc&GSR@qO`2F@hTk^X(w!kvQfBVlNVP+*jlc zi2egeq?;)J6!B=;XURWTtd;#l`Im^N$$p;v7mAn2ezpA9i@z7|6(1L$7M~|kuh+#7 zWdB&)Ec@5;^M=g!82u=u%aT7wY)8VLFMpxfNA|(;bIKU=*-!TI@^d~F?UQAnF8@ri zN_Nf%WW2@VDYCDS{~YlG*)NxWy?CAMx5|H~c(3dm<@a=^o{{|(*KA*KM_Bd z-RMoBo&uPf1(zj5L^I?>B-(RD^YsY)-Q@2fmWTtyapEE3WRa^RF~8Hqv&8en z3q{WEVZ3X^Tg5xYhs8(5XGL>gM7mey|EKt#_>s6p{8Ic@#48$8ZmO6mdOAz|SrO~S z8Mx$daf~=lGyhve^Be&GALQRCJ}y2lz9haTz9D+LN}J?2&ke|LtNb?a_wa|rG%-tT zCvvG>#_K5-iJUJ@dzm;-7@! z=~6_a(+M|!j!An=&4%Ro{rLe@;@j(Dn21TCwe+cugd>V z@jdY)akKcj__fHHQLHzAzd)KF7lK3O-&Z_9gf@bSH&L7-9wVCPXQZDaztLTVzh3@D z;tKH`(bH90Bma8wTJdJ_Ht`O7SA`67fp$YVo(?@5H;r`^1OEM@9brhWURaZWccm zzZNkw$HX)Gx`>}DKi9ct`nF;xv5QzJ_7?kzgT#Hs{YCS+3;7)?G!kg<^>~KpZBH5Y6X4 z#Yv*k6-NGL@*7=Y_>HbGc%tk}MBF~VSD$W(p38F>FC+2!^QY^*`QQ8g4;OwzpLD>E zk8bAuHPB4|ihgvT*}C9AmEPusT?&IgzsP}Z z`&d6TJD%SLxS6IHJGZxb;8_gE!`m3f{SMKKSBw`x3%y7RW4wpt2F$hr@kV(bkp0Z< ze(e7GWubmv|FuS#cRZef8)JDsV78BupMOlVOm3uacv!JgYqzxDMqvCEnH=1IUVa#E z@pFSAG1TvMH;Vc1#p_$zzj#nAvHg(tTfcroii=J3AJ%@mX_+Z%2kp1Zr2W>$XuoB* zPG6mJal2J*q5YP-+|z!`SoJ4seaD+R<{Is{ENH*AzUY|`Q@f{*iS*07B)YoQs^p83 z*QQ)nx-By8j%`+P`jw^If+v@5OZxb(ZPxnIZGp?LhdP_HJ@nZ-+0OQqPn_);pE}#a zo39?#Feyzm66ljwrtxnpUl9EzlU+~-*d(Gf&k(&yk-Bz+K z^7Pm!R^jxNeByVPy0M@WuWoh0f-eq4U-|; zus!3mWTZ{qp7v=H!mY-)N}VfN^MG=(m22VFz?QtZP!^y91dHt=SyBz*)l{;ZaQ9p7E{K*jOCgp7s^vvvjm(dl;=o z{Yst2rhaTU>wv!f*4du6&EB5&wY?^S;}l+FHNIIKTEmofW8>bzHGx&=p;Bi}sr>3*~-mBQI-v>gP7vliK)k3Cj37*x1xR1z~KP-4`W)9cXMSO@f7` zrZj#$G`X>92uA~3%-WeFz+OeEEM28y75Q_~-n+L2r{9Ct1}&7f87=(+E$h!#qm-{u z`vJ(u4qOmue7iKc@uMNgEtNSjmj|{+CZt|=;qCi>lziamk5WfV)O zb(;f`^tDdo0b#f@E*vuyT643$#;D(nwtwn0zSWN- zgT2eKal{?_j2SbgVa%P|tgQU4fz*N90;%>s)^;0L5$hAgF0~uqC@~`iv9rf~^gP{f zj_$QJ(Cew^I~e`BYsLgFxZr*KzxcfOU;i+As(rz~-g|R&`!S5kcy~j8t`Wb&cCY(E zy9$o9^Ks4m8}`9`n(%GVpEKWK+L3P&;!MH~#u=155;34f_cnd}YTFsoj!z!YqT`Dt zrv`54;M^*jf}t-ND~fQNMJj!q4cEQ8LSW{iojiG++oV7 zhvWKlN!L3@e~ybFB}spdFFKQUsXv!=O>#A|OP|g>6Z&)I=+UGbLvj5%ie@B9f9@e> zzJvZ;J*=+&Tp{8{+M15a>Vs@^BhsJaZ;m1*5{)wYbCFU{z$kqosu@Y>&+%*WNNHSu zj)i!|4t zi#)4>T>ZJopVa_Ye=hQz>O3sHmRTkA=iX+2G}oVtB=qN2@SrF3=Xgxk?DcRBXC7IX({5=B>-92ZN7`1I%aWmd$eKX(idl}~?;U&cm!`g5GT6!GcL zaS~8uk*7~LHk!-yKK;2GcB4;!?hE=)4kVw2e5gNHMZZsfj^|axuRq7xM3HL)t#d%5 zKewEQ4S}?{{v7AiMEv@5co?)Izij=vkJyc#{@f5WAT5$-M~wcQxt4UZTY36(53@Bs z{W*Re8QGQo9M>Yuhzz$QMt`n=gT<#m*Oi^?)1RXpP6YaM=6+25IXWm0CH=5=&qbC6 zAOMPS`XQtG^ye1P@6(^-;zbdk{@g^?+NVF)#9I6G=P273@#)X?;(6fHpW_d6BWHX1 za&w}~S)NaSj&fuXpZ?qumgm=>qZ}QRd*+pL>ci{Q7hJ;yAL(Q5)*aJ z%=s;%;MN#TMV^7Yg#KJ-^g|%ur$09V6%2H1raw0j1H{I1^T@)=LXq6;-{N_>>m2D?2ekeZ^FsDt!tu}=YQ{0@pbhWQhi-^gUzzQ+C$_Wa*6zmctIh?b@t@sff9MJmyIz zW=0lX&SH04=i01-`G`3$9`h6vvly{@$78xStANMn%6QDnv)IQI5bF@^ZXdh0O86_V zTLsjoc|4xtDwE#BH6*Jc&4A9C1U(+9sXG2Oge zw^gtnF$TtC+~SMjx~+oe5MydQ#%;bBuG=aoMtx3<$GFoM!*yGQTuS&Z>^!#a@wnT> zx(7ABD_(2YW)-YL%)iHDZZt8UL9C~+yM5={-h%%P>{h`;Nbz;N29Nt{;JU2>PKN8w z^rk1CHZjuh<~9Yp+ase4x0AJ=9Te1e#4r5p1fCgwoI>K~8k+N^>?Tqj$@>c;%Y z#5@T818Fm7scV}K|FPJuLQd7=G`$gwVe0xXlWHaWE3msg!>Z-Xrd?c-)X1H^8qHu)A?(#QBW4^W$+_ zxpCXU(1u2nuZ;V_Fa$fs9MW9NU{jYiZkoTr@K+j58X22l_!v9J1=2jnV3Veunm;L9zzK+7$K!T#y^D>G8OQZrtNwsEWsx5oapm-WreF%ZZ$K z(WH^_0T}MZjx!v$$z=>SX-2zg-iF~-8ciA*JK%e?D8EZ9;6%ln;%N?a)9i4H%_YGQZGkP*)$D5E#CGso&? zJJUSyAYK%^TZWAL!7v27)$2CIZ;LWw*5mkZm)oJ^Vd?!0{w+d;1=xE(1kV~cF2UZ1 z(Te^K%N_9Dh8+|Cm`Ne*j`?58jAq!OVrF6zzl3Oi!Ct~h3@&8`*j$C+e(apU7x;mn z^8xJrHz7vgOFPYYc!>>cwbS@SIRHNdw*p_;=5Y{-AA)UhvbC|Qtin}HoB=W)uya5ojv?I$x9^tJ=wz2J-QvpH*Udf=1hDP}?dN~hZhC4Ybb=pnDN>G+r@5duhl)HMMnx$hr7 zb>T5^0>L=DFO)pqBs`2b96KadA(T9@<2rioj2j@UOHaa3>KcZciXsVxODQG?fwlXW z(s4R=Nahmn82brJ*3t2vYiDD4u|WLQOX)~69z>#pO+aEq@irSzU1q~Y1Yz=tZW|^N z?!^mAvvhDF7YC~wucL!ktGEU&J+4;dB!aa^O)if&gSyLX1#1kMIKpkkN&Z$G?P~>O zkJSpqXB*rGA%3DkN1GP-{&i(rToGnA`3FRp-GhI@wR|HU-*Vw{+dr95oP0^YLCBqEaDcn~vP|z}MGr*15Ay-HI9Xo`J1MBE`!*~`iUPlK%7dh7A6W7tf z?}Fetc^w^m>V;>?IyxT2Zd+3c{(uE`B!}Y@kc4BQQP7VX1DFmuGRG`qBRSS<=C@T#S=|`3l5f9^F>}{Tqp`2~=IUTcGygd7M9y~5p0_d*cAxv-*PFEx{h$FOIs*yFuo>(OQgJd3>z zu0!r2Y8Lzgf_|Q36h^yxTIreDfk0+9>f#+8Tq4oed@+X};yLr0aZYBx7MXsV!qbBn z2dr^G@Opr_gvRFAW^Df2bl4=0O$sWY8#&nAPME;K=8muli4is_F~YF;srNWD0rfE( zpY(X|=M<26Nf5)f{ZItVyI5x zP<6XuGQr=};%SK8@R@P?u5?Ew#vztHM#iQaCc6b;2&PfiJAjitYIQ;bi79+~LE_$MK=Fa`3V8WMKp?RKH*x06jf4kP}79XHsommHNSh&}h5 zTPC406Fv6>#k;2sT4FXf>tpN~pX|4WTPmCNj&b@fj?)tTHX+e(@p~?F zPMnL=5;3MRgq!pIcUw0SA0+)5`HG5PhtrzHz~aI1H@{FYFP;@{2m78D;^z=!_(pLe zkNBu(3=TFok7E-t;zNZo*q1tti5T(2&bB0C_|9ctxA~qOm?5`-5hnkh=M6U+`^tCC z^NeZ6sB_XYx(}kdmnMw7Na&%{GltD0>-RmWdNEVYhe%yxJY$|Q>hk9qdl+Mp8E8{H zqbu^RXCcp6Y+`=j1C$rj{XXdyljji$qwgZ*8F>_F-q|_k#c@9a>uTZ|lgtNW-h^>6 z@r-FcZ1J4TWac^9i-UJbX5(e+MC`wer+cqr0zd*!nj=nHF08ZOSQ!@&qPNY0gZq`( zuf~28c0L7p+v#v{f(~td`&#&!=0@yZ8h z!0{D!+WdAt)y8D=+Y4dqy%T#eY+N^p&kNkW?GV@|?!->p6zt5~pFe-wP`4BNLfEMK z*fRemur0^V+c$S_yB@Y1vA4{hAFjFcWsJX`kHhvf_Llj-2pcEJw6wnm8)qE1w0{BH zS39wP4I2jv*C@-t-m<=4K8GM|B6e>pg1Z!ZjdssI6#jj8V&~^t?tH%T_lK9BlSjDt z+lAQqJmPJ1bAJ%~BR>0DxUa;{&jH-M?OM1wsf2O4^X|^w+dNy#bY8qC5%*bNeA;Pi z8K1XW?(K1X<-MEtR_=FV_io_44K`ut=MTQ8Fwfbl2-9#MgPnI=@9xPo-1$L?H#%Oa z{dsup*k5URedo?HnFsGN+`W6A7oTNtKLk7P!QTDUyP5jqF^-on9|0J5SNSq8?p#TT zcVFH~xj&7aw_xvf>gDgn_44=P?ka!g$+*mGXYKOZ*&hAW5qo#+yxMx(IdF65nG#;0*Zb3mAnQEMfG+3mBQDG_GE<+$`eJl?xbQX&x@g(Kpo9 zEMSz;lZ&X#WIV1F!nHoIRtOd-vF#)$lPh>&F`&+jkO6jdQp_4gX-;iXekcQLi8$T4 zipSA0E)>$aJC^ULEW(OLT=pZQLr-{HbCIJAXI`vhQjy7!R;yOTGoC9L;zhTk20jnM5JK1bP62qlRCq}5=kZ(tb&4E zx^R^qWZcD>>@HEn6^62$-bF>uWE<9(ts-aIFeJtzIlbUV*;x+O74q`&n8{UDOn$4D z#(JOvpPS0ufi;pcoT<#en29DA^$2D4hXX50Wua)(Md75j*=#DiD4c}u+o{_hC&w3O zM>h`;^5o)4$SKq%$!TYsHF!!_dvU;8U*YsTddN%3}9* zaXQd4yU1zBm~$AjlrAjZ)dg!IIbE?TmvbyF$uTx?5tceC>V&XN`q=!ezG|cz77G9S zEmTkWTG$>7+Z6S34|m%lCwUlZgvEloaLpksm1EYmG6NyYnbN%1-QIHR#J(D2_d@i8 zOtLIzffw0d=^YP+o5_xcV#kVNqSoS~ensq^+M*a2wKAQVfez+@$Z}4ICB=LL0jGPL zQkXNb6jTP+?@4t&!!kTs&e=AX0s7J`BXznR!=dbjah~NgG_NtQ5Jg=0$CqbPd(@%X z(EI-SH*1%-K2-{S*FFsGz&b$PW8S({R$(QmMHQx}Q;$IYvqfn^K*3;3}vCsdlnvb6G5Rb?fbZ`QO*EY-K5WmFh;AT5+;a>4>#WfMnFax2_y6|7(8qF*hq42h*9d5PGw zBG>}1oMvIQ$)T~r0}h!SJKVf>!t#`{{je(aXst>e!@86emG$+tb@j2qeVQ#$-6J-* zsI;iWtXf@CTGB68SXYUYtiG~G>}af8-Dhy08MuK|%!$=iF0A7Ed$H1igNg_BKgN8| z^&K|b3Y?sQ72u2cc0?QBw(Vj)uvJ(Hc+YxZ>L24_uDE5%i2se15QN zajYCOA&_4Pu+MkC9+-Kk+1YwvIEUORF#pbaV1tnd*O?h39whRsSlam&J2_80UR)}k zDV{4{CaxFxjTO^#0u8xQd_nxH_@VeOal05s=P=!#^}yVI*s~s(#sgmKa$M|L56ta{ zJ?nv?AMi7%J?nwF{jgt}J1)kP=okKMko@1e9vG%qTLFAC*qY@1f<$|bZammscB2;$ z{{V&WO(LDqi-+6j#3S73#Di0nu2S)8?29U8!!J6 z3O`z$E_*eJcnjq}RpDodD`me}{x#w{66rQ5{0`ag7Vnq+2@>&MkpFdszbU>a`xX-M zzLq}%p%u2b4GH^R^7j-6$v#5<@#2xP&yc@HJc&dJsIc%)>yRwT-8Bes{lfJAx<{xIG!@j%%p%73hQ zoa_zqFB8v|{nzqSwuj|iC*COg-6YC;NPf!SFy5cV7iE8wM7)pW|6JkQ#BXI!h5`!H zr;FJn`aLSfNVKb$!uyI8nxTC^66K7Of3m`l6e%ggc*l{5*C78=g`Xx;ScdT~CK2yS z`EL~OCQ+|Hh#O`9Gl}~DMWg@>^Ldv2a^REuN8@S?d9)IBEOzuU)lE| z5pRtA6BRy1JX-eI@*gK2Pa@rk3O`f!mE!rbUnc)L@j4ReZc+GsvOg&PN%rSS#QVGa z?6+mEtwB-$o+deeyr1@F>%l@kT{}kUPk*-PMU&;Qh=;R|I7s%9@*f}`Od{PBh0l}$n!vfoT1-d*xP zqVUJWr)2*diFj|x-=y$Q#V=(KwQ=KRkm!f@B>G`5F;Dgq68R04e~iM%iHFL5wESga zC5drWCDxHBXNkg>i)YDxF^O`nl>bJB-y+^2`yb{1llTOQa-I=iCQ;5?3V%;*lzkhC zastpwVZ00y?QShbWzUnpKrA6q&L9%$$I3oloGczG9!nzLZ26B9scyr3P8OGm7b^VM z;$^b06K^L`--pF#MSLtb`C&4SAs#CYaXB~470ql|l-o`I9%6|&KpZC?B2E^~`v;^y zP5!gQ^TZ29PU>a*t`Tn)?-U;v9~GY!Ul3mv|0%vFek5)YzZAa}cX!=YDo?V02ZHXEiYvr(#EZo>;#J~x;!WbM;=SSn;zp6PURlrQMI+z|KYs>9`y1ki z;wF*Pwiq51Q^ib?ikb{B5IKvL{!)?Zn)DweP82zFm3B&Pk{64Yi|fVTh&PLOiTrsE z)BQ>OFY!6?Me%jGFBXae#3AAcag=zlc$hd< zoF-O^RpNZHK|EDFL%dMrFA!MIb>cPR3*yV-KgGAjPsGo}?c#T01SdZ8O%uKKR@=$n zRphKt#_J=Nh*XoIeP7XAkM&Ubr-(<172<5MMywN05|@fAM9x5EIn-Sxxhetqp!kT$ zH4SM0v-q0$hWNhNC~{UY<8x*)$=RwTe~3U*9-GV-JBxWDHD4Kih&WB0E>g0a;niY; zxL7<@JVU%l*m9lL-^+fl_=vcxby}%M%Y563F_9WZwD%JGii5>rqPJe^ zH2EvU+2U#9S>kWRo5iO@it)3&A6nNmnUW@mmoDarxuOvsMtGk5J;fq%Z*jQDwWOGz zxBlso@_Xx_&XnI<|CE~fjPI>~dZPSG#52UR#Z}^Jky^h@|GY@4ar&FY&&6$GPQ(q* z6+4T0;&5@KI8OA|E3J~hT5J#(i%Z4R#FgTC;>F?`@h?`&YM~I`u!^NrM9C4m_ zvban5r*D+p{eqF>xH(J|HrNiI#KD& zdtj7vjQr(d%XLGkh0Xe0B(4>&6t5G1Bi<_BDgHtHqxhKkr1-q}lK7hVhWNhND1It_ zAySu{_4C#T?J9qFv5#0H4i<-rBgF&6L&S;Vk>WApOmU7_E7ptD1ZRD`^+B(Y|0;2V zc$0XCc(?eV_=xy~_>B0X_=@;X@oka%<19ZSW{TOOw_fO8@_Xxr_K?3=>@S-4zsPU6 z{A0v%;$h-sahf!tiIw9~C=@<~=dOyUS0_cBVf_oG4Baj}gnoxnhmDKs-TQ zCY~<-N<3fuwYXNiO1w^_UOembnD~tNy!eXvn)tT(zStyEs+{?36TcCIeD4aod7lhY zf}Z})Vt3KJSB9N(^b8*^Qh=WRIby9?FH&}%;VZ=p#EZoZ;!WZm;@u*p<(d9j(Y!~7 z|8MeBOrGK9Ju>*E{M$uJ$TPgP*iP&un)k>E?=Sz};&732@l1cXSSePC6o+T{g(4;3 z>AyjwxH|p!iGZ!RQVyN|ERk~L^mh{}I!^ykk<#MyA1Y24XNnXNXZU#{ zrNZgIMx^XF{r8Cvi;s%t{Vu{^lb1-z4xhu=pQ2F%M|dRa z#_J$<7Q2f*MT&njztQ4&ae{b+c(gb}oF!5hoas*zDGg5l72>rdK1)&{oc6m#s({n~ zH}MS;@$fO+5SM2Y4jAHfh#@}C8RBux(2IxRYy2@WUn~@Ri)KC=${i;E2yv7+Rva%* z6{m^Q#hK!Ku|Zrco-D2q&kqi>t)d;-%u{;s&whd+Ix7e@NUYJ}y2jz9PORz9GINejlLxLUka^xl(i zkpCv}R`E{pA#tPlxcIdAiujuNhWL*7f%vhwRs34SBv@1LpqM4*h`C}%(R**+TmE9P zzu5Bq`B>SeKykC4=d|G@?d{KNwd`teml6Hh%Uqs}_ljyL`qB`~blpil4>!z2*3o!t6@qoJhZ; zWgdk!lq0HU6;;$$S6AX^JHAx2pyq){`%OH!sJx+}u4=}D24wpqwhoAkTZ4JdVY2@G z=iAVIX6u6gjEB?6Y%Sw4j9UTr2=*U}*BfzKmdj)9Z5SSA8;Ad1-ZYFtoPXij(%ZbS zF)-kju{A;grym9x_ACn3;jFfm^`94ZCc^yr1@S<5E1qjvzclP#{Vs>wO9Q91a2OV5!aG@S^TIBL!Jprq_+bRw z$^3A7#q-+$H`5ej=l1*oSg!}=dK<&I-ywSO#vF>Wy+{gUyocll%yvKGjq*Go+rjOA z?Ed=QkNSE2hgSsg`aJ_T#^`*&-6k|2`z(_i=^Gwaf5eNy$RUVVASOTN&oaF+52tlF z#$OQ~+PwUj#vku#)bDjK66nS2TiU;0aV)Ww3>a8iJfOIEVEZ0u78^2P zNU0lpddkw#qn_!C8hZATP`&)-gd&b|n7PG-)% zv(dwd9Q>AeG>D$E_?#a0j$+N zgWen6X5s9&`}HEN~yxX&Dc%bP&Rek^239$zB0{-S?M1kKP><3W|fo9HJ!u5<;_jMjgd#l+cEt_X0@NZF{^bh zN{ZOwagi5UtKYKRgHq^bucMAucziOwPTn#*{Tw<)H6_+o+2La%#c;U&eQayGnR|q}l_k0L4yND1%*vAon$So(D;A!y7dy+zTLIan zATv&(=o)vG5DJcmC)>{Y0}u%>h@1$fJ50N<72Pa|m*emvuOQ^aQJ3|1gw6^7KC%VX zXjL}f3g6XQ30jraS>e0Ak!}H=|YAj9FIr z53MM}7Rbv==fygFztZNWcW2r^nO+Lybxfz=U-;2Z7vhiv@?z<4GpqmV^nmf^r_W{g zJemHM@fN19=7D=E`5WWy-KuQC3@iMs3Mz&d4fwMfFc@C6;5n5$Ed3i+<1ekKXCBBK zkv@-Ez1S+-ct^G>n}@9as;ow(a{^iT?@Bv9ou9wMucka`+B+e=8?*XH>(&@#SQtM2 zCD!?^v;z?-kT*5`EwnrQP6p55K;E?UR~h=Q2HQ+4$L6tS(l+KFM@yR{_>XoRmre-E zWKi1?XnbKXJUtL$??k!aad<{Rm9nCgfDF$Lr1HiW$O}ftv7p(39M>O-{+AoRm+Mc9 zI!s>`h`3`dE83o|m>Y=Pg1bu~FDKfW;niOL#nE*7YXWUIn(+S7u58zQFMM#6la<1C zfs~g`_^{|bEPp{jmy!|Dk6HdgFaD_LUF`8iUijGPLCkM)Ajf=3pEo|r$!g(~y!aEM zd46Y5d<~iczJspUiK*NSW zS`$(@d9Q_{Ma=T%Kvprj%*lHr6wRjLcYzcx^z7t)3@zOtPX+fN-Hi(S4wCWeAk9R& zQ1DVj$g!V9KXQQjqSE9Y&p(++OvhoHh=lYXz+kTa9EIj&#^r=1SPWJp&+x*`SeMh@gfqGzBN!e<1cyiEl1@}qy{F*!4k z>5kK}(MGo7tU&KNli!5sWsJWf(EcP-)v3`h7=Cu3t$V`FiEd!{O3yz(%7yR4zw-Qx zqbIR`=LE7i`Gr^X=sH&D+(1^5F|4qoU$MsLxixU|*4xo5Sf%sbES$V+?dVgeOL&!M zxXF&5!x$HMhCA(OFUGjgGu&@ShthD7XV_>*uVlSeyXPZ@t8Jz5PR&}GK5ggvSt;WW zyZ(JWf7ELCNq9{lTm?fkg?U{b=s*wqypCO%K8r1KqP+6icBfo6ps!kW1%YFfEPoVrs?sly1k?;6L)6fq=-lfxLl;W!vEcP)zdqcJ@UG z%{(5qP|*Fq1nzce$vrbupM)#=8OB6%@64RDm==Wwt)s z_#+t5%(!o6=zJKu*cFIwmn5+|=3$<+skPa4l4X|`(v=TW40|4nvir4WNn^3^PaCth z`?q55r@+5}HdetN(26y<5B|Hb^ZQRTDW{t~!P#O@>SiBiW|$rvQwRm4jGe^TG?0u7DWW|t<=6Eb=IUs)^k?BzC&H<#J$ zwh}7Nfs_mO=YS}(hNlfnJ8MLSdwei4c{K{zT^|fb#g*>QdTIVTPUj&bo27s!0RlA zGG8Iyra=8M9jbtKml)~=xwx72wPkb4Yi3gC$>s&z`rSGNCqAHfvrv z!>j7cDi%Xr$_O1JnkwdMYI#af3p^REnY9ZbA7;d(s2)^SJ8M>bB_z3^FV<#t`6wi2UN}*{+Nifr9SKg~;K{b@o_+3Ra z)iH{);b3qaP?4<6tpg18Gpit9U4?vcpv<^4Ctp=fS#@PK4;+p{IYJW(Yl|u<7Ka|8 z{@Skk%tB@Rl_I}*)6JmtRNIWa*qkyP)tXw%?IUw!SwC03udLp5i`$)LV-6fY+6*BU zYHC^E%w(Ap8>(gaA_ybRH?DB;#|W;0q#63H+z7tKW!_M?`IQw_v#Kg*dMBRwRwyob zX0BD1M9%6fDU61*WdX;a4nvuw2oZ>b;ul<-g>xG<-LZqvaWxfCaq9<#IJX0Q8hceZ zHf8a1$%xaLZY--dx^`{@`Mp=|ab@$$DR?)l#wd;Bkj`ZFBz!l!vH{n%N)`a4&e(;x zfI(wx=lXDdRX82`GFJ`G^esjjCE$2~78xNxbFEO;W$~PAs>|o0qtV-*RvdN1MwSfv zsX}0}KGhZT7wl7k)2MQBpX&bbH_Ta3Jp-Ht`>gp3`}e7z-)CmYKw3Cf`{16x&z$nQ znJ|>sRm|B3hhX8L%0AV-X3dZFnLTq+dEKl&rLjJT_KWqIRa4ssy;)U(RP(CJ>#J&J z!$^I@26R*(Tw%$2*m#%l`)AGXQ&C&fP*+~jun*20DCU{*>gngPpQ`F-@&K7}mpHd8 z=GE5Ygstm8*qT4Gwh~uIj#$5v;`{;XXrs9JpOIhNL4PgB+=|_Qe0+871u`=UsI(F1h!$$_+wxi}+8?%ZuTgiT<#@b+C{4Bb6yokgf%61~W=H0g}oyO*4 zL<&CF;^Qek@atm%-ol%Y1R%c)Y`6UFJ`Y_Ue< zXKkiCO5bqWLC_W|rRooPbc(eF`_>B0vxJmp*Oy_$T}BG7@l-KC?4~af&2KG{-=XrCi6@II#kJy%;!EPY;^$%r=OF9XM(idI5J!uX#Y%C3 zc&2!XxIw&Ed{TT>{8%)8Zs{YaEIUEwoDlw|A})`sS_3gYqF%=r0Yq1ab6*G+_vm4CcANjyR<6Dvf%pJcwL ziYvr(M04FlIOldS-g@y`k?%5TH(#!SkIMgqh++P{bEL=fx`TAQ=l|q6Sez-f(|K6& z+mmlv)c?%MSpTWHSo}ToytoJ5*MII?Jo-5v znV+|DoF0dY#p)mOKn}hr~e~=P`P)d12?n?ayynERi3Y6wmKEUm7?q{uXfAPWt64g!%JZ6-yj9K5csS zyA5vEf#ZSO)K)mxc_6egjJx^v2K3@}!eCjbID{AP3Aw$X)reQ}cHm_XF*%~m|orGon|Nok^HST-nY@LkrDUGwRrh2vY5p%Zq1sJ9w z@ykc&Z*&jJ9f=r$K6z&c9FI9p-HP zo<}(`XKQb!P0ZQC@;3fCTU34W&DlDNo&EF7*=o&lcX!U#Vn$BP*;+?$V$N16Ta=iy z^=H;OF=vZE{P4}$GBdh<(wwbcwjK=4`#qO3x0&=WK0b zy}oD8mYIX)o3mx+c=_gRb!2+qoUK&W$2Vtd4a@h<+2Xv^@0+v5Ss4B~Tm2Z{H)rb- z*55a0>wL!d&Dr94)ojid-!?Rxv&Ff(&E{;4WS0IpTZJ_Ivgd3)$Yy$TwkGi=8K1Ld zt|h)XTa(yc-<&PJ2HDLyTl?@}`sQq{rr$SbYa9KTvt{nDoU=v8&gX0m;Mf{~PzUQ=J=4n25J)D@c zbtD3ObGA-JjO3Me_E`ws*_^GI=4|noHpyKxbNES!bGG>F!sNUbbGGt*bGD9Qgl^uP zEs7oP?wl zF6i*$G~6?1Yd6x?@l;=4i=9QtHo2qbHyvfo5csj zXT;aVP2xA=o;h1?Kku2d<@Up#Ia}xloEv||M;A({|y3Kd**EInX`pc$=Wk# z>woN=t-%9-)SRvU#cuQ;*4diYg(Jh-EuF1HF;Nh&%CQCQYFwYwsI9_>>y}$WXNw93 zn5T6n;F#s1n(1uqp0?INzMl7KYqikRT8q*{!S(o`)F0mt#`UxggT1pu`&E%0N33Ib(cNJ8q_LIu^($ngO2B-ICp4Ww|VaE4^>3h?AW9TX4 zg`UuI^(xSp2l%}F21sts4< z-1JrGDa_4sLp!=!O8dzh^XX~b&srIUr-M@HX0M~isHa7*(bIaGwLHW$%&(`#hB|qt zLl9>lxSmFA(`3J%RxWDc_V=-^>1OWlvu0&UZq0(}O-PHmS$mn#xSkd}OL|(&IE7!g za#snVV1Ia^r?nQ~+^iX(r>8|X3rb@%7I_8X@Nm9r*1ZVj+^kp8DCub_f%LRgG3jZ! zzTMQ*az(-7dRlJUxSke!iF#UH&>-k(QR2*}r*)n2=BIOZBIag2X}pE$XL1ZYmHe*p z#`Uz^g5r8wZUf?aT5h>qxz(bV*Z(WjW3#WUEar{!ivJuSMJw2k@4erPkC|7gc?31R4FGN>&D zuH3mxH>lZu*3t)~}OU(VVE6 zCWyINZg_Fj%z44wteZ@DLQl&L9~}LR`C)Dr<#Ymh2|X?MQZgc1z#|JiEjRusSLXdTi%OGsJb!BuI?? z7>r)U9)q5iMg&S^!$U!4pU~5~nptthM$XNmhgtoae$35s{Yg>&`fLY1t=kb<)pqr? zzQ7L@q7)(K+$`SBnAO!xin&?taZKoGF*5bE7NPOf(=rpTp{K>^yPTWlwqk7bNwxxW zvu2t6CPdF=eCTOan5s^VzQl0M&2mq;InlKYhn|+}Pv~j6{>9M>)(>;DlFTvp>1nk! z2Iy(M#TsL77HeSiv|iy*#M~@q(M(UvH9$|xh}U6mmTU0oX}JcUo|bEXp4KU>H|A!! zrBF|6G_q%{OrJtei+)zh_@Spoe|OLC>1iDXLtIab9`^ZBY$Nov%mR3M(9_~Yksgy3 z^t5S^&x(80*+K~IYZx5H8FOXz8_RJZ)=y+jE;Et)#oybPGpjRAH$+@T;( zbm?rdjj&KU&sEz>;TZfBUQ+?gp*oO#j=5R9@8M2aNaiVyvc$|o(GfaB^JeB!eFaBM8U*zf}3=iRz8JQ#IiKXIx;smiwtQAiY z`LjvpbGdkv_>9Q4AsEipOUP|v1n(H=A0&Y;&Smq@d5D}@pW;N_>Gv(SFFGzZd|U+#(24M6C9`9dSl11w?<&+ zHVhg=%%9I|jKiINjz=$VI4zFTNf`Uy=7k*!gFnAf$d6w?F+bMD%dZS>FAbd5I^?xG znpwZcx%w&-X!G)@hTmWAyw1C)nY9X z@?$)2^TJxrzZxG)DT|z}vjAt6=cAcUmlQ+%gg7)$caAnTF$m z+Xzhk=Q2dz#xU+JHM72i7}Y{AlHxGl6LNb&^D(FjJrBroxjl;AU%#2LM0>Ll=GE_I zxbbK)A28dc$j?8fStd8q*A3Rwh_^eMSzou?JH>5E)u-ds8D=Ti!N=n(B6*_%P@PajC{;|nAvF)bd zxVD>|qo!;M%>C;oYh~L__KCBbP9HkE>5Op&P1nyYXxaexSts^u+OW1?Q*dZ~(-}ki zH=RCiU{mO*hNkP+E^4~|#DPuWxo06StEctJj8ns#bDWILId;~V>`lQFM`Aw=`=m`y z&qV%~9PEwxH?sqfiHwe|Abi z(^)GAG1x*`{Drs`sFKFu8^Z2G~+AnOnVea6jeB{&Z z|FQQb@KIG~|M5gsH6Q?!$0`Awg-HTK>xK4IC?qaI|ifwmY~h6&C%BJ7z<-y!UK4Hc`G~^ zla7|II=Z7Z6TLAK*4UD!&x`Jznm0dh*Kwmu+5T6K7=!nse-9v_j(NH-*gsdU9)R{O zKDrL!4pj#&*B`xQ9xbzf*k2=2!zlFgDAa&O{n(G2U%@C`am1W=04*vxI$%jDdMM@S z&y=@2>GOx~ zG25J5lg#duS|=H8amOrY`hHiNd1$TkqF$KSQD^r&e%M^H4L$MGBgT^F5HL!p)4h5n zdU)m0{!4m3FgR~vURGWU(mptBu0Dn^0BP`PHAl%r8-BF<*wM*LjvTl-=T4;l_CVOq zUmkW|^UF_;{p8ruMXf*o_?=H38RI|Rd9-Y`&hhktBOe=29KeN}UT2(UZ$zRdVzKGAyJ#5TwUOex1dP}DsNmCMPm zzV3CfXj(r(ji9KT%VLL_Sfk=$OOQ&6x~rg5+aRN0GrS4agQD&oD8pZdMQnql-iRPG zUNT~l%rDy@Cqed-c^cawo1w-}@m{j&x$blwR3f%PrqIY;7K>UdX#CzJb|JSx^0jx^ z1~~}YE{t36B8F{{?2s4}3T}gZAL!*UU>hXks6)0vHtQ<9e7!cdL2A+CeF_zVqE3rZ z-t8!ZZID{Dw?TfQ3~?JIx2{H1<6j4YY8&c42Nt;v^2eyw`vDR_QKt1fIbXR7iaM#>`w7LfMU2<4Bt1vOMDJmm8ZTn9S26ER5E0uT`AM!Q z>i9L^n}AUTMVteQ`dTxW{<`dZlDFtL3q&Ozq zAhqQ2E~a0PhVw-_q^MJ5W{-&&q^RTT{P>Jwb7A1bd0wAh%L{rsr0; z$8C_SIF8Ttd|HY9ykFAm=e?gQaiI4aw&{g%XBaaFw?XQPg4-Z<1A^Nib-mf%z9O;G>X4+*>tmOwqmh38xsCUqNxl6o5? zd&gIaWNw3GKJLsRGbdjws`$dOGv`C5gQ8B$9$!~B7~3GV9OdIZGj4;_!G z`VcN4xef9TI*M(OIvuYSrHpNmFR1k4>dktjsMG1AeY{7-ZIJJ%^lbf#PEge8rDVL1 zd{Nv6sq;_rx#=&qLF)7=zLzQEwW1%W@&&$Rw3!rjI{ysc2Fln5sqPVC8>Ejiwn1)C z`RDq0UXh}Xr;^$RIgbc5c=G@>oS-3Dsj|nDJ0!I|PTS5*DE~(!snwse zP@T-!2Fdesur0&8$JmY726+`4llTf6pteD-Kn|Z;yRi+D0%wHU;0KDjW|-h!tt;7n zY=e{;fg0Ixmy_lbi(yy2R`f}ldK0d28zcpqdYwhF4N}W)-{b5#P}I#-ra@81$N^*) zxAiv21a!3TMw-Gl$g5OV!}l4BVjH9$N2l)^HV71T%*<_&YR4P4LGojQuNB?Fs<92S zS(TsSdyn?84RV!|XXqDpVjHBo$ConKr>GOL4N{+Q<-TuOAGSeix!TtgX8*`2n zby|UKkZO}KDC)EV+aM!Z1Qc~zfo+g#i#N7G>RPxBauLkaE7hmi21%JtDH+=!Dd*a< zy$!M&3ZLRh1w|bN4j=EAavNl`lCceviy{SO3fmw#I6RR=*4rQ-f+C5l4k_w5xJimB z4%;AEtFHeUyAZZPa!WZV>ZnRKxeTb;jR|%DahH=Pdb0Ti^=uHHHi*1m-m52+mt5H|4Hz2u8e#s8LPn7RVZ}NYH<{5qj!}LE1 zOE4IRgb;4JY-qXvaS-yHiJK1lANej$->uAt{g2lnAA9miSmypm`+cInfgjxe7<`{- zGwR{~N4`(A3r+Mf`DPMxl^d1}qmiEBFki+cFE>H19>`cRRQzB};r2=MhY2*-2Kfr= z*0RxS5?JL#7|B9NIg9x&jcr9bFMCOe*pI%MP4UcU{vef}na%OE^eIyLQ%V2o2E)8e zW$23u`i)XuVwjh!T*FX20U?!bHm^{&--P@cb$o%bxmM}IP&N5YQ=eD59`u2&=4El} zH>~x_IBwW1Kr%`3Qs*JFd1VrHQAqxVIu4q7WeRoILRW{7x}5f|970_-rUPG)k!siMEQxxt;axlUBLl=Aju0!iEPxNg$zR4ByP~G-LydNeow<}}m zx^y^k0VbbiT)JOH7D8YGagmPqBXV_7nNZ-AgEvs|9#{hN@V%}x_$ej_-C; z@cW?s-qM5$I_Cu|42c9(U9$-s6^1J#89~w;Qx&Xrtt&9P6W$X>1=1@K_%2yw=?2Lhgf(GYC9wRA_1YHossQY zSkunPvj}+mE`jf!LZ<3=M)+|6J>fjm4860Rk!@P=v@`Oo7NXiYj{Onf6@g#Jl~;`L z=`mO$6exY|ns!F!X+8UAiPk&Y8PU@gO+q8ofsQa777nK~oN*lbztPzl7k73>qf<3t z5`4onA#71@E_b#wqJ3WOX=g-)&<0%G*#KB#1I8fWbRpy+SVr}lc1CmqW^^_HHFP!r zg|++oKkk(q{pq|ZK^@QG8vq6> zr#IxWEo&ssN%NS**(fe0EE@rT*f_+e5p{f}Lbi%}d!8eHo;?gKYqy7a;7;g)YY=^` z1#m2wpZ@X!pK)%3p|6b7U)|9g@>qYK)Jx>_M4s=h7p7b;tS&ggFese|>-Xz=W)TYPQqTF1|&Up#l9pH9?$Q@bXlZ>HOWk38qvqfa{_{WRV7 z44<8tJtn3&jD;LL!+5s1jcsa5FG5`UZ>GHBH^k?eAwCy`xCdK2T=-)Pcq(o{Kn?lC?JB;aj+m&un9P?w z+^*vjUjwFVFDA2h*GinT^KprX%+ARnvu!d=$^j!d<1sb>>6^*PP%hQAOx^%wP4H?m zYm>QkW@~P@(}{6#$VU^;G1@}eDZ~XjK9eZ(Wg3y+{Mc&Fmu&6%6t;*hfnI&~vp*RR z>DMWAorkH%-Hk&po9c>VJ5o?$8c}MVO?+3^HiO7okY{#CZBtq6Q=$*)zu6(9J2k`$ z{su1x3h_|q>t;lxKW8VSCjN|onx@_elsPqZGzzG#WY80(Z@;%D6ALcqJ1z%Qg{fU*VjXN&fs;3MF8)I~jg*er4SAZ;%Q>2Y;F@!Vm4 zn3F@TN$6wy^PQ>e;eJvJdzdv*&)RIuA@e_I4cXMnAf_Q|ySsrXKb=V14qODW2c6pE z=|r{wdWAJwpHF0Kpm!2))B5Q|?MJOAWFF;*^lWf7OICH`Ux;h`qzgSl<=!tOJN*63EDk-n1 zEd3v`UAwCGzi9Vglq_3s0mhL1@9<>fu9(5Su$VZ1HcVG|oXd1~o$HG4>k4-db6IiJ z#JWwFndAz$y7^tPR+S$~ec}@0;#^jOFCK#FO0u%DUD1Jnwa(0Ub+P*7yP~baxh|L6 z+ShowtGnBZHeFFxO#qr|(Y#DLX1VEF^C zMC*~Jz+hK&=3tlC>Kbq*WkH4ddj^oJgy|~-Ly&HzFjtBe z%!Gt)@$vCeWoCj8F)N%s)Qu&o(YV@xwK|YtMF*^8R!|&Z570g2j4_eL79vfnUJ10= zO`AeTCZa0z4LyX7`as5TcoC`GjQAUFcq> zE7Drm6hP-hTL+DxM`v~qwI!mARLrhUXBR}et;?EBS1(MgfGff(_hYQAUVbJp&)Fyz zIxHD#SQ1hHQ1o{?45niq421(LX&RmGw!9`gUW9P7GsQOuTK1sSj@cQfJSh6xRdFyP z1NfggVo(O!T!jV?v@7^0YwLUFh6U2oIdN1!u`$Zi(=Y@5rd@aWaAH~88cmGt`=&l| zIDL5nor>vhB!^pD8v_BC<+cu)b2;B|R^p7blKk21_40f`rub z8#2Tdm7!0vg!lxGj^CAR)%#tZ6!e4@=|8PKnR=iC=x#NmIMB5`p}c+$0_T_2V4^cu z&}}XnXh{JZGMrN&onkzeQMOj|cK<-0uAdyUyR**}2OD3XK*ouP=|!3&+jLgA!t zsH!f-^NLlKg{2L6|9DZ&V!Wq*Wl3GtvSK{XS5zl&wO?FW+EABnD9A7hYbzF47A-C0 z1BgnM)k!oC?t2iV7njvmtVY?grA0JYT2oV5^;d5^=ib-CWyQLhvXc6mnk=KRrnG1g zwKYpiE5(C}V;1}~&y@zBM=YzZsx5?9WtDKHq^jzY3V4=Nu~@mvN0L@9Dq6*wYx&R_ zS@JudRw}Qm=c8*SRrP3>dXh>1@64edX{%UPU0+jLSY3zA?5Z-DE2>;He6(%0@Dii* zZ2-Xs0+k0vwIy{G%Su&m78cg#O)bd95G<-SD(jcct}9wx3a<-;-2H`xI)gocXj?@C z2C%HGwiInFT~=DNxU{ka?P1GmOG|WQm1-g`DhyEeql4+B>in9zs+A?R_E;CLC|X)y zYD_-weE-CZQU1|^%s_@eGd*K;MrKBqe<0rfTUu0GI>OsXtX))rXNM~=EO?g!pOai%v}{?CI@b^jnLeB~)tDJPIg2qIuv=4F zy0oH}BdVU8wCU&VNunP^URk2rX?x7)?@?_DhP1N28Zosb6s{<(;aIB4!8&;6bUwFN z%y%EmR_AuPoYrauz?sZU%TQ3wbNdw&1=A;Btj8pfeQCp4) z?~e-iC))WR$c?4T6@X~jZ71{ z2v(}$T?voTg^RhorNiIas={)t4CwmmNgObFR9PP94jPhq*SQ#-@^%#cT7g=wzgRsN zm#X>}^UMt{?7?9ytkns%br}6i3YQkCX;K_IcU5O_8da+GpFLZ;$gf?%%tB-IPz1f> zD16VCp<$;FvA!lp9d)a!xumI%w5JJ{FV3@2?tZm^8ilB{y0oOCtfF+09<)*{U}aT2 zm+;YoX;)EOSkh2rR8Oob#Tp2^>U9xZePxlei@`q9E-}<64Ng>!2+mLf%-HWQsa#gH z6#apU*}KN%i4({82XZ}}Q&qLJ)?ZdtKW7Eof&+?;8)e0=zeR%uk`#V>?-%wu654!)-{gn%$(@q zt{Gm}%qZ8aNZ0I$3DGmGJIsja;W_SE?%D1c?wQg3a`1EMge({-;#W+=9E9k}3skgr*#K1Xn-;6g$B zxzk3GuM@PNJH1QfUkJV+cv$dj!EoM0Lp_Ot0|YM+ED@{`yjt)H!IuRO3!W5=z*M5$ z?t%jaM+w#nUM{#@kh@q|?s37F1m6}sB$$d*iTQ>La_c1JIf9D>>jb$IhUuFHcL+Wx z__W}wf*%TgF6hKWXZd)+euBdVCkdV}SSCnnK9=LIBjOPJct;#9m?wCFV42_*f*S>I z7Q9dJZNbBW-v~zGT%`SE!J&fLf(3#L1eXe~5&W^>Ho5 z7Yeos-Y)p8U@Vq4=IZF+C`F zln9^HbEQBR)+)*oMEIwkD}~%$^u0u{o-2huP4t8Zyp9Mzwu*d{;4Py6xybhkJ}mktMSe!`dC~t?bbd5~a0^k<1YPB2IG(?p&rc!B7PL@pIvBKmrfR|z(Xex1la7ThHI zn?$}@@HWxkC-OsrkBR;nk$)wKj{`MduJ%Uk!ae_WUzo7aF2Kl)Sk>w@}o+mg<@It|h1l14O$X_n9`kaMa zFY+3}X2Gijxi^^gY!*~MG(lER`T!pgJvT)&-{XSZ+d}zy!B+%-C&&$vOg|#nm!G4M z`wONClBJvaF@k3cP8K{@aE{m@)>jgIoUN6WWr0EBL z$Rn!j0^q$O?-JZCxL5Ew!To}-3aW=$Q2swf{zOn+S3v(Kk-rkeMW(9PDafs&^dn19 z{n!urY>_7mo+~&@P+gB8U!lnAx&-o4k=2iZkXMOJYFO5@R#08HK;9_w^@2AFZWp{m z@aKXL3hol*PFdQ0M(|C+cLo0-_^BYbyfS~JV60#_!JdMB1P2T9$s(2;BY3u8t{}-? znNHGt;)R0Ef@=jg36hPN`S`2@@n*q01r^^1^t(mgBlw))3xcl*{!Z`%!H)%x3UW6! z>p3a-t)Lq^>LUab1^LVd_1yYPoFO<@kh_SfUnE#ASS?s5xJIy9@M^(p1vd+-r~eS& zF0#5FMEq`%cM9$j+%2fC6A|Ah@_s>e-H7+f(3#z1m_Aa5L_f! zE?6yCC%8tiS@3GXYXvt8ZV}urxI^%6!JUG;1a}KQEx1pRThZzNQNb?-zZT?oX{Ngc zqXlCHdkFRt>@PT2FjH`(;MsyXg872y333}e>r>wYfOR4_2sR6@6}(nZ@zWsx7Ljih z+%2fSFCcxN$S(>i-Wup%7x_KG4+Rek9uw>k{6$(u0`p0j9|PVx9d|sMleS( zPw+g!S%UKfFBU8lTq0N_xI(Z|@N&WRg4YR>0G#!=3i43_%DV*>RX^l?BJUS`RgnDN z%>SO?CxV9sKNsu}nGd%M?e8l_pmx==x}strZl)_N zw`2JE2lvF)&k=#*+FBz(Mc@oK2LJEV{TNB;7hK94>_;BMH3a{o`_$0~|CtY$b?P`h zAJcdYK)_Pz(6`>@l>p|ImjyBD{TKf|1}4?ArU6ruITkHj?<{A0bW zkL@6?M6k;sYTVq*F#L?jVW-tX4z>4S4%T?+Xb-1)(B68)?J|fOPr@Ga*@vC>BPc@c zJso0?-DvxFBjR=$+Bg7veA|e9*lAm!2(|Yr?6H0Hk9Xs3d$%LbGU*6B9!|xYjL&%c zU>XCzuZQM)7ZYQJok`M|zDME!b<9cA+k$PG_43$_5bEFCA?@X_0k(g<4}hsu4N%8U z*bAN0tdj@PpqhsfuLlFtM2UO(-z-&tqK^fjEAe*x(1!?wpVq4^HOzjy3RKs(>C z%n@0m{GCU}h>@A;Bhu4Hg4`!vsrCO1s78XoCo?@WUGx5YKabDQb5(`G_o&%CKDX|4 z=XKpM{^|$IQ(AiG8ONI^rskPrdvAWiQ&-++gX_>0?)c5UHg@0SzoG9>jbk$|yTUUx zFRmqdM3QM8k8&JJ^tKqsEGw}kGA}0Umc*nMFsN7w*ZVg0Xi5HQQfrT`vpQn3Cm_t~ zhyq3dJwOl833O(6ZA)tC*3u)-7-Agzra7T4W>d`Ao-N(mVq46VE-hX2y0pc&CTxkj z@r53aLswYQEi*n1dwE7j{80R;a_ol7BJZ~j;qFR5BXyn8KW|uG)W+?3Ta7#NA~wGC zsbldQ#!H_%*F|o8r(^W?mpY6+-OccgSL7|vi)eeZ1KZR)toMwz`5iGYzJpwQPFjm2 z+nzdUtb6&Sxfp5bEc@h1BX?)sqj~c?qLvyr>^ix6Dae=d z;z?t%qcsZFJjp1Fdfn@G<{8@_&3o!(R4#Ll%6s-?^g743XHSNy5>K9VuY-@U$GXjR z;VA1I$~sZQI&#j?mv=sOFNSBi%;{~5JRTD{KX=c`sKqxOh~5(3_72)~U0&Q)+AvRA zmTyaROJdu^2V%Cq^r?|M{orL0MR{oZo|igewzuWI1KrylM*55n=Up!=n?|nl#vPMT zU+yoCn~~2$w-;@H>ZG-9c^+!ay&-Q_-UkO*E_Ummx=cJc+3LD2a$#1(`(1Jl<~k;H zr1+;Fe7!caVdBB5)`X7CbXsC6#>BF7I5WDm#%}Dkbz_d>xM{ieV@xsPF)iKmx_;cf z%{p|M)x9OFp?fRKaD=SxW{J=eZ z+j_MonLQ@;+T?HTG0DHFH~#nDltQi^%Q$vNvwv%!8=Ys};)&YWd#kZ2*1XAZU~aBY zjM&txwafK`Cz;@+ip-1N6qDsVW;r4^xm$X*VpfjrwJEAKr^9(p*S4rl?$)G+@Rpb{ z-c81k%Kh(jEZRQ(m>GUS-nP8w^Wxj?ITT@{1ty+7#_WBpxy#qreHC_Sa+JHxalKAv2!F42a2^-4S1a z^CadO%#F5O<{2~T!vh9*h#cD@TCJ1DG4oKf8QFI3ebWzK7wsvBx96H;mrvS*oL?OX zZ{=ukEN12Ap&b$E@0k6qd0pFDI*j*z_OX#-^c#@ZEAM8G?cyzY$$8`QdT#mXBaXu5 z==X@W=vHS|M2ox4nT5V+YsrZ`?u=~uyzbuKZCzU9CiQOV(^lB4Yun?VS2{d<0{eS! zjXECV0E?8hF=zA>H|9p=xsQLFKJ*E*kI}~*xcLeEKW3UYKTvScX-*AGKY%`np8cuQ zoQ+u$ecX&*k(&c42NKz+FgA`q9_ZaR(#%3l4^HwOv%Q3?`d0XxNt@$`34?P@}gMhvTMgcuQ56}s8Mww^Xb$xnZ-^WY6_B!u0 z`Jhl#IaXGLaeWO3K(bT{Yn>!Ztj>A_DOO?} zKU%HFXscg5FOw|ZtFea0UBq}d6a)DZKi@3g%e6+wU4b~B|G$kT?#Dk6F?|h{OFgaN zK7hie#aE4ih>4C`A2YE=#luMCKq96c&?zFOX|Nf77aRc*Q!mDOqYFe#)Eg0WlXtKq znO}&Qu7vCzgnuAnx(R9rxODvJX%I0Dffh6yhP8x7?y^|ax`oE?O*)FKBx1Uic}!0x zv|SjtQjr%#OzgmzZ}5*qOk^$ghT|WIm>5SLLd2wNbb3qC5D+nG(c|TNpg_c=#VGGa z7zPoO7HuM?LCO$`n0|@mi2Lx5-zrqwQ1_2ukwi={L+AYs4V)FO4H({06vv3@^!BDW zRz#1Nd@CSgvMX<)FXKdv@sh9sL`*t0-s@!9b3{z^{+{A^5tF_3EIUEOP$H&e)Zx7d zqY5G>#@Xw8Xt^Mqq9S6tp2_E_hAASZk0{R+c`cY!ZbD^4ky|wxL`=`4HbunLKHQ;y21HEUUlBsY#Lf~TCK`^o4*wXW2A6X)1Q0Pr!W9xRJq6L* zg^gU%m2p9H zvUWI926|tBNf0sRDltgJq$>&%G3f>biI}v{+1?2>^-9-sRoU_0``I6_cAc-pAQ6)` zHOae@gZ`%YT;P3#qx4pU8$cqaFX-gEv3%(piI}co=J%s`Iyh41daq%NK8)rWOd_Ut zS#mAfdBx1Tj+3O@? z+N)YU*O$utAY#%dT)B^=?j&N;awid!mK%J0!8M7Pc=MJkx{sFzBw|{j6d+0?tQZk5`DF4WoZ6c=opzswSB@9GN6xipZ(KjSwdQ!0IQ{|L^(S%@fG;7uCO7J!I}D<6oMcz2cWqg<#& zJS3WdbXPba@oIu(x11e6tz%7Bns=RW9eV_>Y%UI-(=FW2a96zJo+}y$c!Gx7^GY?uw38 zn_dbDFQJT!Mn(o@f{EPIsZfzGfnO?ks+u;DAd! z%nDppr+}(y%uvP(pvpt&$IWc!*se6c4l?hJ^?Q-slHHY641*CbLceC_8yEX)q(`9V z`Dke>eKB*CEAt=^r;h%b6P3FcqA4VCOudG>Nh)7ELz2h z@$CnxvB+#rRb`iB(k(;izr--}m4>fI-hhz$1sZHlQ+1Z1UcOf#^=qX|pdTM2yh7c# zN|!|4&FJ`_Af&Qm%xQh7I~O%UQ|45;EbABv%xgV4Vr6Dl87 zPeOb|sj{F-qRP!1dI)0M3@h+7db z701Bke^WgDU!i#N8j5+zbynomxY3vteFNq>QC9Sr$gz=UMGlDSii?Hu?w{sFnQ=JP zT{<&Trp5_PQ$Oe=cTo3FQ#|2J!rj;+@fE|Za`5tu;a>Z1}6J?+3*fIF-+ z2>n&`0)j5E@!BTF^??V)d8k{zIJwlZ5dT4vLs*IsW^8=0$(^0tPN6QS7@gcsfnQ5? zj^WAe6u2=N97hi}aVJqCmI*N0j6Vu=t9BqEI@pelS(F zE{3oJ0af1J#K;n4fv};8k);S|3V|D^l>P=p_+UQhhX~w|qzW^_-9=!gB0Q}1`y09Q znY(_-SOs`r=~t|2XN2v7KBRdYn%GV@5qi6&%07pT&4u1>wbH}q(~fSC;T-|LP9XXN z0!I(sG>6g711;cTf^b6*rRt~7XfhK0%wWtR@DkND&L=EX(K#HZ7&L>#L%jTEH=th$ zY!+PnrqOPa60*^T8Uz;Lot#@FPP_*}(eb1>+Zlg2D0|u&=WcJE9@TF5hce0@;Y}sD zNq7@M@l-MLz7`tV8R2C=Qr5IH(t&`EBIvmdo+?B`j)91eMu1(yLIl)*ZIe62$+(;m zTSCqV>CjWUGk~1Tj-d!&Iq^MA=}b+o=Q(6 zU|JDgRQj4V?TqZ#dfhk<4(i3>Wb<@f&t*ssNn`pBga;8Yd77JcBl0u?rUHSTp!AH8 z3IybB-2TbdAxb!kpt3OHRxMk=Mh@1|DR7Dn#nM4wGvT}4TDMVy-_!c42D6PGNE!WV zprN!wG+Di

    z)dinAB^O%O)ea84XV3CC1)Hi6SfIcA@7$YP%;h@wI2fY+*n^yx|; zBMk23*9T?R<~HWGI4^8*GR}Hz*|u%Vb_Jm}Y+FRu#-o!8YCWXQ213+a9$>a*EkbT{A*VP``0)lbb2jUVerW)N#T^1xwTz$?ZJf&PG73Tzo%4 zKvjnuL#m>VP3_dLRxYr~yrS;ZYuA(xdQ>EKkiT;ckxw1F0~Vs4{P@5K?P_9V7Xm*0 zb~S+)t)0Ri1h_}wN})0`@+JZno;hS?WBhXje6+GLpWsKpYGJn9bKWk? zN%J@Y%6{G`Whp<40M7~fM6Na4ZMW^RoeSUvTmZKtxbW=JiHtz-V}rDD_C&So>0BQ#;HSoC%D_y*=LjH&Y-(qOt9;1G!;30@E-XaA zibh}#EVu=X^3Z*%AkZNqXFbMiZIeCy(L45xSNdjT;Dm+~X{=B7)JArDHbZN7v9f5-W@ND^uw|?^gZ+d2w##e@?7~~^HK#}Dc}}?pGP#Wl zTAV*HPK_xASv;J5V{UlGTf=xTG^qoP!X|hhAYnp2>H17|d{1 zAfV89dfpe=&{eND^7+Am2= zNSB^R;4>ny*=dMB#)KRmlzdtlSwPS&{^7!}5f>|VW@uoE`R5^E5hL(Y$ALFNb>^Sl znV((AXI?_QhomkEgM-b;Z7L6M5vwCi<={gzsKiz#BZ8*jkSWM0&y~<4M4p5@MwSsk zk$=;Z@qv8ou=JP8!}tqEE3T5@6Zi}M#puaEn^0O)UA2^~8q2dX0wtIT|N9hW<3McG z4Gd+`*`SpID~nh?wVu3r7glEpM|Jdwam zlbew!j7(-eShbdrqzINQcdF(!i?(`Y2LjpFUgI_L65Z0|cg2H*301^{3Qe;zDaCh3 zGZdo|N}mm$q?o?>uCUqeNvst-VXj_oYc-hB{H_Ri*AH!4;aAc`5Gf6F;nzwA0Qlm}v+p#H(flVpOS{RHKF*bzx<};Qmv1n_L0X8UWd^URrlue3v z&06UP*%sKCKu;BAttMp?9FKO#4@HceYgSh>JXQOx2xJ(}XdsPAab$Z6H({nHl<@JA z0J4x%YlR==WckVvDXo|<0&PtVsS5mE$n76y)zcYpQ>lJo&Q<1xR%HH6_)@2Qp)13N zTMhocLx!bekY)tPZk5KgVR3PZ3E;%CCYyn5KN!ovSv4*{Ua@4sqrm0JW7Q$MyE|yF zhNy}l#7!RpJ9TVx6qwPZDJ0GshE&}F7$tN)TIRKulH1Bk%626~GuZEn9_LE#4OJgx zro!(6nHvXfFvREpv;37J+V2`1(CTzd29pF^k@%t94RBjmH=!3jR)?Wjw5YkV$;{4I ztZB_A8pP?~a#y%bv@zT|()d^)pM+mOHMfNler0cS#ardCxnlEO5jmji!&pWP=j2_T zkN#EFhUK{n75g5@*)VYQd!+Q&EcAH!T=a>WYL)qVDp+w)xlJn~o19+Z?kvS2cg|Vt zEKdLEl*uZ}QK;rTiBSWSLV2k<7xt~hd^*XQ96b_w2dQrJo&~lw5DU7q)Bx6Vx?5fR zZ2K?49M>D?9R$SlU0qe29B&@jAR^Nv=pZ|woh7bv^FLXP#yM~na!aKw{FEL zi%$B$_{`PK?Q?ktxxxoxI2))%tt2mWxjoxCLF3(BT(NZ!XSm_BOLk zycdZParT405GmeZ!kJVomcdo!ZG+3oFBHL9H9E$6*B~{bHu-lhBB%|VYW{!&7t;SQ z16nBO*(p3Ye?@i%ei|VVJC*hH|6wY$+WKYSv-(~> zw7-`oD)j8o*G6Y#OCurHXpC-kIf%~+N-G!Ffk*AH7}V;Dsud;H|1Bc5AcI;Vmk>3l z{~j*2!v8+HH1HQ@82Be_ZvOyrnj$FV!2G=wY8YcVN&hh-HS~<;Ui@!oQnRNNdF1|A znbb6w-$W8k{=a8Ov!7Ty?R@;#B1pq`<0yo0ap0ENn&>ER@R=d?wHe=+&&ZKBA$pf- zUF3++RA~Q_Txfi@uJZ`FCjjNYA{UzeQ5DXi&rjh(J8c5t%WeoC+G&X>&Kt?xWyf(< zTseY#MvU@zaiV2N`Z7lXt%5%jyjzg>zL@`M z!To}73mz2Y7G~z-ZwbUOLB;g~xwpt81SbeC7F;3tBSGE?qn+CY?-%6lB_j@MgiCf=>wkTJRk~n{koBbrjup%o zkU#QKuU;1o{FTVOJw`qEb1S=o{CR}(xq|ZqD+C(^`AZ1%ac4D=&r=YO z2`a7)$kCX`)b|t|Dp)31FL;(j6JRf1Oua_1TK+=WI|oD0C;i2T0bXM)_7#(Zgl z;{>M(UL?3o@KQmW8|@~Me=hh-!IuU9Q&4djpdJ(Z+gM+$V2a>y!Cb+Of;S5)E&!C{ zYc5$n4BL;0vjvLbd}oVZahyRvS@g3+uQ<-2 zpD+3{(JPKK=o>^{BY2tQyH?~4g4c_FyU05P?-2ciBJUFXrRevG{G#Ang8wOaRPZxF z6K!XIxCG+`69oqd4iOw9c(&j)!I^>!1s4h8<3-IQEME#yt-=_=L_ziY0_Iz)$b$sc z=O*+cL@p5I4-=f9KMY0= zQ1FQ0alsRUe-`BaU)G-`I7X1a&{1!5r=2VE9KpGQg@Pr5O9iV1R|@`6kiYNH?$v@n z5o{4uKOiA}yU0Hiyi4#w!Cit+2<{c+kAt+oU+{N=+^0?bhl1+!9`YYW{*zz?KZl{` zz67G;N(FWonLnpd&mZN8^8_yzw7JwOM6MQ8*9pk~Ly?;VuM)gQP+dPDA9r@pe!Jj* z2;MEIt}Bqv4Ij*BbE-Wp@;<>=1z#8ZP|)U5`&{G>L6g@Fu;&s~*CUX*LxlS7f;|QM z3l0{vxz_l+9rJTj0Wn8VUB5uSNaRI=>UswHI+4{AZjia3oaO&R@J_*d1i3|o>5mCM zCCI%Y)W0mq$B!t#A;`_+ls^>YHV4Yb1-}sdiy&@(s&t!MOGp$(UGQlcA#Zim=t3_@Uyh`vI!A*iT$6C9{{~>s%Aa_2p{zn9VA;|43)bA5K zAoyFscLm=U{8aFW;Fp453vwSn?TrvTTQEm(s^B!i3k3O~2Fn!*mI^Kvw7J$+iF~Qx zT0xs@?I$9)2(}7t6I9oih~FWyy3R!WQIVe$d_nLH!FL2d6tub3{wVUF1iu#ii=d0w zkBEm0@__`(-2{6I@*x!J`OE|HY{BycX9->`SS(m6SR>ddc)8%|9BRK1{S$)E3O+B$ z=L=c?`+^;UHb+_vuVayJbE5SZSv^w;eTK**1g8p46D$%e6;#*LD0ivI>N*>bhnUhs6zvM)q`LeS**3-*VgdK?vUjL1I0B*DId{RM{!W(kfFJX>(G;JJc)o{04= z5meukAUBGp9;1K{!CDPUqZP@ME->!pG~6uLxLv-zZHz+_X?zU5lj;7EjUDQ znBZ8!a|F*7oG$nS!TExUOB(hUi(D(XQjpI{vHn{H9};|2@F_u?d+c=1vHz6x4+Q@x z_$R?{1bM@Y^@Izm?@f@qi`-L?&uB569jt-_7UVmbj&|SaDrg2;55ORg2jSmf_%J=GkkK5NJHc0qi68V-Ec*xx51s&rf~DI6!)+3}Q7#{Rzf&vWFReor`nw@n2Wl@`}8 z)^B`~cu{dN-ZvG>qQ}>@gk&zlyI=UytPs^-YnJkznqmLW(eb{OFP~c<87%vIU z!?B$dbA$KhQAF)r#K*VVC~cQv)*Z2UWDfJhKJ2umP}p&%J&#Fr59W}4*lFcZgx0%r ztf8J7WxcGA?I8XT!7hWS(U4*oen#Z5)A-DAsJ$38jPslJ@UauLcOBw(8AOdOu*ZD% zVW+K!BGjHg#2%KxpuO#g+hq_nZil@o=s)|g({6+!)LuI5v3>N9-D9`+Zp2w89f8NO z!MMM1nmwlT(d^KCqcYFTllQdb1E^ys@=dY@AnWC^2O-qI(IM@{PzU`xfH=NxRs+=W zIqYG|1P{Bt#E|J>49qhAE}pz8Fg7x1t+Q{tLWg>T#}xSY`=HdB4?KCK#0wtZ%afOR zR%W`&{rx<7`_5Mtx^#O7VqNqZX`ddO{xk68#VMY=RK=5LD4x7NiYG4xJb4q{-8TC- zCT;3_LqG83-t^|K%8TAa9c!x%i+$-+&thZSm=liOdrn@L z`z&$|%j*v|I!CUt1(sv?oV=Pg%$HAIZK9kR-I|_vR^Gmo*P8F3Wb4JqV;WnZL~W5< zBf(bZgx;|Z{-DI=xi6l)oIHAFm)3~mo`_kw+YZERjciM3?Y_lv(u#{|>Cu|`Kx~`l z!rY)Qs~L=Ukzl*aar~)^!`~6-&uRbn@@xba@Qr(av&*0+ovllpGz z16I5~!jP9L+<5mj_uZOuqvNdU2RBDXZS1pk`oR|*7l9qm19m(Q@(Md%1ljRC!j9)` z@wZ|&j`f2buWyIroH(%KIl+$SZt*B~y!!n&g6YnT?gm!Er5o-(6z#MQO>+L?xY1?y z{w`l%`(?dxZ+B;#vAN0k(&(FK_>Dd!&7j7htZtbk+A1!jDJ>#yCAc})vV*r zf~*e5wNGOvc(Pud-u#$h@0=rPe;gU{_H=8zAurU=yAF6;>DTYh$duQ6%Nrkc zj*16dd5$bki?hv`pWXjZ&FV8y#1b2qCwZ2$cy9O<>qWW~Gxgfsnt<^hTouTNWMo|%_i9=~uw z`J9Dhz4L%!&*S*w!0R6yPaN%HuiH+OL}yVQxC*!m>t095V#_F~=w@M&cR0hcDLGu~ zuAb?>16P;U7!G=&M-h{M9C60p1x&j5Qv%2#`1dMp3&{vFj*0jVcsB*ga z{Im5Qi%su-gHnZEL8*@V#ff)N<#9cU4+NpYvlkIsIrpK>moHTCE(Q#y{0sji`YFg{@&(*hkEK*#~MErN}MPbwWBYbra zji#H{v-sz(QSmTxe}I}#5$$-K?%S+VlnJkaQ|{ZNMl#M9Lb&gUquz*M$J8Sh$&Y#R z;ko}KoHSY9X#8{E8nzQ^5V3gsU`vJ?IBVwYL4+VL~i9(MOXC-7F5LBrJj{`MHn8=x)^RgDfc|& znT2zWB}ayf;UQ1HGHrrWe95 zQljR=^Smq-X+Av9ucZN+56`n->dp3EM^mqKEm391dr1K1d9`b;5;Y&5=XYXilDC9| z{-%^I@b2I!y%o_5Kt4QfDe=4;%ehQGJd)>m-jBLNrOx#(VT(SD<{3;ryuPgW4>H-v zhsUvI(FFC6vn7FidkNHIT==^|7bbOk2rdqEdKNl7>>XbT?Sc z>3f{%;KS3h$HyDikb7x4%J(iR@qiCcmyhvrW041Zc+nAbG~O4^{NTgW>FK_$>>=>s zX}-GQzOAeee0Vy2w670)0epBQydodo5!MerJiU~R_f4UF@ZstFlYIO^&I3L?oj%3) zHf8YPktEBJQsCncFCOsW>HIT%&r=2;9y^D8c#|lD4^M6Q03RODD-Zbacq%DAyoEFf zK0KZyiVu&kOY(pZ?>y9?`0!S+N#MiVfTmh0@40-h(FXYN=BXTt509sU9wZ-fg$$As z=^O^>Y53%F@~4M*b1>qZpdneQvd1$8N!lK#ZD%Hw=T}3u`g0bllNrkg&&w-p8J{E9 z!IlSnc<-SxiG`>!%9CPxevKSHwU&Snj{+7G-;L}c@Zsqmbo%&{qz8O>G9yqU8}4$_ zeByZ6jrN>ldic^5-x#Po;KNgIP=TqBSQLDCT6X&~*>m8-tA=+t<&6kN_*xZlyZe4m zvm>k$Um6vEod@)D;y@5nW3i$B2s#8#=z=y}d;fW-2k7J%jhsBj3 ziK~tWe0Ut(q)he%`0!Y(uD=)Zs6ybwI~TQp505J0z2mxt2{srSFiWCOl1-j`_PN0K zr?{LXpN!xfcyh=?lp5n2(!9j#5W| zL5@dz+-UJGLh7&S&m@&EfFkh-sV3{lRk~x4_fyBWm4O^jl|^;C5mLEp0_1pn5zP@K ze}JIL@#x8X7@mfZdOb@{NuZ7&ZM-%~-NBMmdQ!(#svIHp0wjPOk2=0;l|M;pay)9@ zhr~^VsoWU@ay-__HDw_}>Jg<&pzd49hp78Z>5{0s58-Bn)UTAT4|N=j(Fj70$HAX~ zn|oss`Zp+YJgVv-ax0pU<5Beshz}^0BFCfZPZ0k|Rf!_Uql){%ViEe|p(K#wQI!WV zN2wG!9#v!-U!qis9FMBYAT}WkK%0#x5J}}Fg84=&XY37-H&eHW1Fm&n_~n!8?p3~7*R%M`N*8?y|GOQ=-EM7b7JBb`85Qc1p z5Q`9vFqGNS9zZM`VGKe@ICB8y^tmS60%6Ia1Y!X)kVym>F7NYMdWukUDT8 z;-cVE^#ca#Wn9rka`PEjA@`V!+>gKnB0rB+f-WEWAIm$Iq8Wt#Dyrxrb%F1pi{vvZ z;9nsuK>!)n&L;QBeV|F&h ziswu~fioW_Rt+4mfnz)ZSXKzPAi&DqO^k4tD1;47j4VU|dlI41)~`q8TCFFHha0Le zBhMn3#)Sm#YP5`1jqQxkSLj1r-q1wf={EGX_sR}@IPK^L8D0>2si-1)WWS@ib56|+ zk9eF)^r#xn?b3cG{T0Qd9-KMsTsItr(Mf%QY!G`0K*!8Ldg*j``~8UTLcjzeJf@xmB&};(xL+Kg0R<&$4Z*1{C5L{z>d7o5eVdSvV zU(ELM>jF5C#=t4I8MDi7I()PnPKL*Nus7Om_dwDNkL-Z!5U9}%kCe73OS9Mu{K^lb z?16W6^nHL{Cgu=6Q`*@CS>&2SR*c|D507!%oBuPBlRkzLl~HDGZevD^b7qT^@i#+c z##vct8T$;k%fNK-Fws}63(p21Y(hXc5;zLzm@@Pl*U3(1$K{Gvu`lWvih$f4W>$+V zuWLp|P&R_%k<~^ZoUW&i%OjW#Ux~qv1?!^x>FH(3A0d5d@maB}6 zyo`W_LoqKheh>lq2wW5GB=(k!$1Xl!sgBc`7uiL^!WhcE=(q)XPDL0~yo>e(4CP(q zJXBxXj9CPI5`qPA3@RS49Z_YsBYryq%7T$nb2d`mi2%O|`t$4 zFEkeu*eRH{1ojC|c)M$q5qnM|i#-i3ETciE^*Ey-*I(raM>q6jqTCy?a6AF4 z-{u_*@%VM+@x@3~?$hH+E$nODj)-<&liM=RrO7t)x7@0YA3(AH2pyin^kjr*bR$MCJ}d zZZ$Bp#{(bbP;XYb_`ACtbp1A^oMo#t6{TNwK(HEz@{{L!l<|do&^ccX>i<>xS4ME5 z!QB|74OfMNmK;VeC?@Gb&NCItMq1wKg#u7;3ZN#>nF`H88lRZMhluU7!x%4xx^QK{ z96W=EPhtG`A)HbU*Y!|weMNOfXEFOC<5aC(pXoLo{9eJ}Ha>fa-(~GD2DWVHH5~k& zpuaK%uZkQd75b_=sB}j<%n++z(5jscR+Vg9b)Ct8*RqrW-rTa?U>*E!V#~Gx!+cy) zFg0wYsj~93FGOkK>Wvl~wH4(CEi&8bZaL3nfZyvdJUCE74t{pp2TuV8Uc$#BaGH@0 z)jl|j7&s?6&Fq5{g&`e*Gs!+U7dY$k5ja`w!|q!m8)T2z>FKMH#>U!xe|kF0GO%my zPGpDJ2h(gDw8K1m5bRE~^ASV);V|y6|C98hn(1k3Wy#X|MWsf`m<81}Rg1BO+Fw?& zw6xYguwnGbK?@dF*8A(KzL&TYEHr7ARh6Y_rA5UR3o5kD1{y4LXTe$+ zB#~*fD{6@=x@Ukaryw|GLJIZPN|UN^_c#bWkdQV^Q=XF6Q*(h5hYQ1~Kaj5pMzc>R z7)1-dn_$%c4-kx|nx-NdO+};nxKew&^OZ=dQ6|x^RKI(!D2Ih81Hr6H>xN6F-<28& zX8wCwNB!idw3^MbP}0%4V6HsUxZ%vCqj!Hl>F8+myEgzjPfP~zcY=Vl7n*Vk`{*QO zDW98TlaA)Iu~tNWDCsE1VzFW$%}`yc*he|3L9F>-rXB5Jnseb2m~Mq%^sy%Np9dQu zgOsdb9OX0*&$io<^4IMkB`Jtv4aliXH!NZsP&+@_PvrPkp_Q{_6WbGZZVQ!}1xXZ&L$uDZBveJ8Cc2}@H@cL=TN z8C2OSm(ZGqTh}yYYdTfXs)Exr)Z;#rWWKHg)0}; zLLjN7wpOUsg=LFyHLWyvZ7#r_AFPisnx z78RmD8Zrwjir}5DcJg`W`zL0M@{bN=1~L@QdPZhOmVY1~(klfO=OF+5#U&+aqtlAf zAtmL0Jfc@oTTxZ%&m1`_ebn%a{AtTds_VyHapgrdi=Zf~DJdU^E14CeO4F7NDXaFUEnc*;sHQ9})1Njy%b!+O zS(S#T_$o?JYH3ALZ3TuPt*orR5?x+ZnFdl=Vl8xwit36&<+AFulB&wOnxc}r|5+Z? z|7&cfol~*|16)~OjhUckW#Nj_8jfs`wpeI93oB|D)z%rsyn>uvu^JP#yigM$7Zy&K zH8}(2c{;J+f0f>JX2uAkdUj2TKG)!>v9hLuocf)UwiYKDxM@)tM;ukIEGaK0vu9Ot z(b7=v;{TVFr-g;Ha%byCoU&FFFTF(3*H%_k71tUo(LnSu{{J@;pZ-&{yy`neVbP*R z-}RLP{anlS?cY?YrKOjgv6DK9zcGjT%?qapICGa3E#*_ph4t(`WAem_WBdcT;?7ZD zmCLGX{1fn=i(Glng?~m(RY_@WZBK@aY^KVX7b|4N5KhA|7)+tX8Gd(sm8FJUtavP8^4QF6|;+X#&FZi zqsNt8e5{Gc=ZT5kiMYd;O2ps~6@8ZA7{LjGd4jxG$MP2nmI~GiHVFPm@EXCbg4+b| z7ThKHv>^Ap(f-?lp9p>~=)m1#riTe~dn;v|Q+0^QqXef3UMSckc%9%jLH^KBJ9`A5 z7ko{SPvtP3cT$La+c}Xp28pu-3k53$FBRlY80Kpeyi@Q|LH@+b^xp}7Eck_>6L)Kv z&aJn^euBAze1|pl#e&NPn+5L`+%5Qm;O_+!agMY60Kr_rIf5mEym`rdmkFvZEs$Rn znGb|9{e++gw~Z+K1p5mrt}W>K2nW*}1%E7fli<$D?tyoJ+r>3$~U-U;rJ}&sB=uND>iYrtwf(U;SL{?ltsJEBs2Z=sSFjMs7MCSf<+EZLXz}X_t zm3)db2>QjMSKL9UZ>7jT6l|9K*NFTRLB$z_@;8foo8-Gs#~>&ej1(P@%TATJ@>b)}dOdQ>)ciY_0mNTC25HkqFgR>QMh{?X%9k zJIwNItN)kt%gNf`9=<)Cea=0@`o3*^2|+f#gn)e&f0*zH;Zefr!r8(yVTG_!xI(yA zc!ALP3c|6vhBEe>6#so8ne~kSiR1@`n~5k#UOm&FSNu!DR~7%ZXqIkY*9S9 z_pJAP;T1%bzm|ylZ&myq!XGLAr;;BLK21cqElU5R;@=Xs3jZqnhzR`-sP1My2s;p= zrxOwBeHDM0aFF6hNhW`vbZ!B@meqZf$*2Y z7lmlKsSiJk1~I)2W(vCq&Bsc#t3dLh!XhE>?bz<=!r8*(h5Xph^hLrd;d#P~gjWcS z^*r)_SMm>p_X^GZ8PcDS{FLxF!WV?E3EvQI6}~St_i4~`2=AkS`NIA}nyWE>xbSG< zc;OVGxt~M6<0O-Kz;fk6+Rsxa&xP11JXLsx@Lb`A!pnumMhxZ5eIf8B#T!#z$ahGl z2^IDKQuu4(Z-p-lUlZ~JGxPHUGtu|Odx+$GVSnKu;ZUJ5kwv*3(1n9{z4&Ho0N|b9wjvQy@;P8ndX&E}Tew5` zH{qv3erBeg6k$}DBkUsVC8Vh^^P9CAfG`3v@<`#4!tufq;S3@DS+M*G!Ue*mLf@C~ zD#_+K1>uV&UnaapxIuW6@cY6$gm(+?7d|9>Oz8Xa-6HvUp?S_hc!y+{&mRc;zIr=K z?j-CjED#PC9wDURCCk%%oLD7XCOk#BTzG-dJRc$dm6ER&-Y)cg_dYK9mqO#s0p@OT393>nhoFJqxH0moA9xtQ;DdVpcZW4Y^xU0`z^W28~ zk172b;TEBJoeP6$0B^L{)319B>xxy=iR|{_veqVT} z@E+kK!pDTa7XDU96Jz!-$mdpIw$S(0n~Fd-Q`kdDyE~@Sw3>LF&^)(8 zUM6{0pS))){ygD2;WfhV3V$HHOK8?Uf!>!Szao5F_@0ooLbk`OX#(UsQOZfeEMaG1 zFCiRXn0)5B8~GXiQ^GDqY@TzG z{-WY(jL!V;3Tbvu`EwyH&nb5n9zuk^K9bFIF46}o-aOYr9;9j^?`KyIANT+;<@LnRyJs|mE;p2*@xjOTk=U*Ux?oEFGc^9Hd z$8DcM{45y6v@_`E%aI%t<_r4^2M9+A#|Xy?i-rDkviW|2_MD*j1;VAm8exO5S=b^x zU3k9mV&P@ND}~nzuNU4Tyj^&g@Lu8l!iR*Lg^vrj2%i_eBz#5qy6{iJw}tNscM3lh z{)>G$;~SLaO}VSV7m2f*g?p=lmehWkqLyJ!a(h9^cgP`;G9LM=Rp3D8sPpd(M zA7zjuw%`5cXYU9NU_^cvgQh> zcgd)d&p-O-=XWlQmF#@De!J`JeAszp3?`9x`h?t*aWbc00;$UCkRJ@VN$KcZkaY(R z?=ptqCYx7Afp9j4F<6N6G;l=M=g1a5j>R z@6-8AzAeb2aEpuZo!wtRR{B1@gn8WL7)o?tIQS!kBAv}ZWx^AL(u6OHfF$k4QoMiG6V-i+L- z*Wn+1wwk`-xX| zV;?z6Vy5wo8aY~GPLwZwBF9MV5qV5M$CO`#!pH`rKkq0GuzE2}R?MMg20r)ON@YJRQx#0Sn~ykFMf@`&G(7BYM71Bmb?6Jm060 zU#kP2@6*T@)jK9ipT&{ib{uNTj*ZTts^>eJw`h5u@6*VOQdJz~N0P|PDmy*ObqpiF zPi-~*ogE#-9=(<|9)m{Tr+IAi8|mhQOWq05TDJL58JrjNeR?QU-_m5G?^7OY7VTvI zakg|ikN+5tNZ=IG>hMO*~FPj$NFE@z|Q`}Ahhqfjor4nxlI zQ!jmR?zNQR`_vF1@`mNs zvm@|*>ZOm$-NbbGK25@%2z{Tv#rom<)Vq|7%_UJN0^g@z{^H#0IpXkr>ZMQ4-AsM( zeQFkWqVH4YhwoD_|LolFviwR}uI=<*8(RpT5Qn@O{d2 z#P~ktr=JLXpVB#_@qIdvD&hN-7l0srpVGcP0^g@}))>rtFO2c$so))?zhKm@gJeWD z4w-1z8xHYRZ;tyhVmLvqtc>!H=LaSe%W>K!GNF7IM3}2TXQ4TnarxkR$#=QBVn#~Y zEBHR;_m(abpe#KC-=`aqBiCF@;QN#U&hcC>Um1b#Q*Q)AxieT4zE3qHP$N4Y4pDs< z-v4Ao;QN#Wo!pn0b*!6Z*g8-(pOX!~Pdzy)mv8eU@O^52kMRm9l>t(E)a_C=x97DM;v6b+B%FOhAdNQ;`;QN$66YzJOo5FPXKJ|Jr zIhWR*5%@m6(CC|;dlvJ<_o-QY4)cJ-tO$IcdMDh{Tsk?9!1t*qH{?Fec>>?3p4^gK z&i29g=}gqmD|+rTtPs9WPcjkkefl6<4Bw}0L6E*r`Ry|T-=|bze4qXqDG~TS^&;T= z^d9Db?^7=VzE4Y-1HMna2>3po#|Zd7^&;T=lpnw%@O|pl@(g^RUIHa-l^Ij`KBde? z85zD$Df6|ik?H$10^g_CAtLv9_7T2MDR9ikQ-<$TLuR7yQ(o06n4<7~%7eobNpiRC z5%@lR4H4aW)rr9ODGzS<6F8Reeac$B`dj@%@O}CWBH{a#Q9WE<2F&cn1p62<;Sf*s z9xhKl|6HIO*o$md>|Xqb-YGcR$?$#3CEi@Ow^uBs#SQ)* z5wYROoy|?a?iyWq$Fiz znpenhl=@Fr5y{B>7)o$vIFW^DOiFS_I0?G)+#tH*j!k#ja&99$aNGg-anCPx+;IaK z!n2wa!=69gamSmwt09$PFW|bG?gUf+J&^BU92?;lcVrvhg8T=@u_5lnj%-IKw7Dbp z0y+eCOR^qA`Vo+M>)Ll9TQoU?4Jw2D4eb36Lk4oR`n$6OEAju>Kr{Z&$+$d}w8H6= zN6K|@NIpl5BXp?il7M*)Dufbv(ksZwP77vq&zP6g(VgRFqJluala_WgB603@c8m`^ z;-6WUsm@+0371a)c8t$nNCyLo;(a zx&6|;x;ur9uFmnCXgb>j=9lmJ&(qZRo{x+@`=~A(c>%|Mcg9B&d}yJ=PMkM3!_$I! z$PE`E>}MF{8G~>a#_ziIMFjkr5%_%QI`as_yjTJYhnx@G**u;1uwhQ4)UgCA3E*`C zk(a3eoPH6hkt&Ye$Pg8x0RHc?WkQB05`tf1j#XmLF4-YcIoxd6b(C5qN_Q#&C+#v(Pafb|;JHA5(M9U!qewNTY-|a&ZJd-S1UR~2X zu)6MOGrPjBBWDdyIZNCfK{>=QaTM|ynhY50jIvfaR(#jm>%j)HwoSag4HyT4t6f27(;hpWW2bkzHBKBWouv+*ko)2eY4qw zF{@_=JBrqX#$<2YoEc>^#?75vRyuFOgo&l4FqW-oY_6|egyAt}#49VBjNGJ%38NRx zYl3a!f{L1QSd0!XS^&GLlZP&tFr#!zY1wcO7ZjJyUI6o{WiSbCS^z^U&-`u=_PV>+ z;MOdv@>*VoBT`;dX{;V)rrT2AP-*NT(VmqRe*0+d2+LEe0$M84D6w*JtOAy;GWRN5 z1p8UfI&x|Ka>SO=c(J~&tg;0&rMz)TQ{0|zN%K;ttfIdDg|sMMPsw zWu4!-syfrKvZ^}YfY~!n^lUC+z*})LN60sD8(+P|G;v9JZEd+R%tXky1dp3e(?Zl~ zV+rZoZ9-4|a_B=V(Fm{4Z8Orz3=HXv#Uv{zqxG-Tv=j!%u{JsPbFm!6GpDM$kv6K8 zjSclRm}>~f&so!Wn2?&mYGc#wbprzqQ&XpG`m71l%I5mUoAJp!cVg+>vXXIArq7!* z(VV25%*!!`95EfjA(-m4XN4+Ep;Ie4Q+x|SbF}?qR#(~5Ok;B2t`<$jltDz(;_Ah0 zvoRgVafnwxed5eXIHe}enKNq+@|nv*bzNC)Wi1WNJ+t?C=F%xMC(WBa4jHR(jj5@I zbuap6or3Y4Gsn%GGP5LZq8cA>Gs_!Fz4NuMa%I9M*gG(0PMA(EE#D`Z0&R}SOh zc{3)?oa?vRJH)b-ms0_AHp-?x;b#C>oHC9PO_i;=3wJ^|OX_eoc&9Q3B5vc1rZ-ep zR9973F7{7!^WhQ~(-vc_Z?3iuuHR;QS5`ucH|&F{#&{1X^A09YF`X2&2DOcj%c@}6 zPX(TVw0AKuhq0RG(eaZrJ_e;z=1(k}F{Kn2#0is;Bd)p@P6zh#GlQ8`R{^8wp)kGn zMgb=B&Gjdj)s*u{%B~-0u<-@t)Ge=_Ti$?~Nc-NhvU$_t#{dS?mCd*sSF)jq)TJbD z0lvFAwPpV8=dP}-tlUczy|W6}!Mf#57;ye5;HS+yAw1UznA$5jH(BL`?RiJ| zzVH)a1cS+RW8VTiRPrq0NkU_ng7j6AFB7g8eqYEpsMNPbXg=*iZk5~zQ&R*li&GL&;pTihA;d#y$h`ILWhxtA!T} zHwf<*@*6Ytd?f6Iry0um!lA$0$ z7OoQ-J~Z^*C;4HaZ;xzv(MbQb;tf9<@+*?x5%$70jP2q}Q{pkg*}{{AKF_(0oih5i zmgzv>PTBCAA#YIpCY8TU@|{A%b4GoSNPbNCOCsWbEBQsC;Xxz*FOs(kw-XWniR90P zAzYIKnA^jNNIyb|%b$tIX=V`72KgJp{QZRkg#77d{750+N>CmzoFbedtQOV^n}sdH zHNta*7Yi>Ft{2`Yyhq4S6|DDX!bgSA2)78|622qcF8omVPho)9W$5Dv0%BKTZ()Iu z9}Ad%lyIWZw{PT!1EyC9PZrh-R|w7T2lC;vuuop?Y+kpKFNgW?&44d^DLaKtr`9%? zF9PDpz~E9pgh$C{&^75isc=zKlgH#_WZ}MU3cmh?&+Zr&3~&5yjc;!44MS8aK>Wi)^LcYzca$j!=3dVkKJzr zf=&(gvFQwXo1az+(bm@jef-i$eVkXmz6yl>G6*`iLl@_jzxip)5#fiK_9^Du1y+O~ zu)vT=Wd-)nzk8u!gYKVNrD+!cuPH$UIAh+x>?u0%e+4C7cYx2Le%?b~Vf7fpz_ z?`4EB=NkZKdmQ@gx$oCSw1&ai$$Al)i+JAmv))YXtkXY-5On%u{!L;)o3D>$?0m@u zu$%BR0sVY~hKv{j3TS-$Pw+w=ix)cQ0C=H`aH6HV_*Z3h$Pa=SnuE>-(O-)f`Z>lT z_)o+KMs}ISlt7r)!NGnwb-@u`WTHR;ffNc?vivq?j`KnnG9@`o=H+g@Q2H?s&PH>5 zUMPRxg0buggzr#Se$H_Wlk%D1h32zKB#yM@h0@s94K^du=Y^)CjXp1wj~Ki2LZ3ve z&kLQx@P2urucH==7rKa5SiI0hOcpP63eKk8d7-3|dA!gy2>HCwOjI7{h0bEa-gu#g zBa+~S?!+)zyim}nzA!IzBIF;D!E(=@u_^6J?7RTFs7FywF>iZt+6tD8uH3l8L`B zUg(3=XYoQ$V1A1idN=!L@j`Q0pT!I1dDVs&N{=3Gc%iEqVe>+1OVEZFI)V{jZC)ss zPLK0KKfxSG@IuYC#Nvgvu)h{BbRLTy7%%i?X0>>sQ#jcyUg&9*!3$l)-(d1W8Q3!~ z)KK~?Ug$g)Jv+e*y_>Dv2QRb>(=A@;nQYoVc%c_CeILBgKXRT}ywDSH6VQeidNV7u zd78s~-nBO2$0@>NL6$I&eFiY8CI z&`+XqUT75UNcl9H;DwGv15!SViWmAgBzN3Cc%kEW(sTGq&?W@l@K*3njHw zTv0B`-OdaBz-{M+^3smIofoY`U$pZ=4b#s2i__UWx|&E( zTAStId7;o|7JW%nMEze8eyFz|PMnD5GY-F0mMB?l-m*7eL7HfS)yE_9l_GrZ`2(C! z_v5+}hR(&6R{r&j&^#-W`T>WxD?FVq`{c3!AA4(+^9j00Y|Kg!@CU>@Rf02rqvB{z4xrFx~l5{DtO& zSM7~Y$SuVO`E+tTs^Y_y2<+Kk=qLC(3@&I-oSs3tZAA%0{`=AM1@2AolN4QFK+N` zB!d5G+=(WkUEqH*9H9?M@;@(zVEls8b}r@b&;tHvD^!mrenCAkJ!-rH z9wjj|N-I6^KfTnPXm2*{7>Qk?{n?MP5_@<)A;(Fy{er&7RvEI-v{Z&U>KF?81*K^G zf*Ln>Gfl^Azo6`BFpqvgYZ2m%F->#i{g(%3U>tLyIB6FX#{`BmeUXh`wJ?hFKBLK>7t$ML0ahFK9JNkpGz$ z27%r43#tP03#$C`3+hR``31cRjoRHWsOQ`??ibW68}|#!QKDba<5~8JLw<+@M!%q= z(OmF9e`mz}=!YDhr=uSmv46CNbKqAgodAKnxL;7OqPSmBuLE(vpkBRkzo2IMoxHKp z(Ny(($HR@PxL;6DRopMAS2pe!^aXQT#QlOE7G^W%MhCFXZ={!-9-R<9g>C**2G3yn z1s%fFw=~)47nDj_w3GSAap*)Fs7{Q>aT$)J4ovF&Ybf&gpB$as48)QD$$U7XalfFK zm@b5J*Kj1^7u1szenCAsJ@*Q>3;a*7e8Mm2ldx8xU(o+zI{2Sn`rup|qLTmlib)@q z+ro~3|LLWV%KaYG!T+RNK>7u3W&Q9A>Rn34=AK9yenGwb#h$-L_yzUSC+9vzec*q3 zen+S0p3nT?e|q^7enE|a82o}}vOe%Xzhmk;Ur@R#lwVMu3f@8bHAdY!NJeDiaFFPLFdX8NP&w`!h~WgavNFm) zp1(JlSdP;+kqPA;L>NDyoQ39OmS4~#eHraPp52CD&}-4nE{8*z;eVco9J%J&4gMzu z&WKysU+_P@5e((hw3z%)%?Q-Uj)y~3pYRL%8>)JNS;7CLKvh*31@b>VIVtyA%Degn zeFK@*Y|k%fUmTj;WVDffLHTP&RgEkP{-<{wL%DxsE5ZL{X8Hv^5nAXMls^-;Ur?_X zlXF+GY2bgJY4pv`ZDM}-1?3My0DeK&G9CO+?}S^LyN2oT3+l-Yxvz4bfdA>qExGg* zN&e>u)Xyt=?(f(j@IOmT1pI>D%ocJ)tmwmsWXCWeYA^QmaCk2i<-I|dd@;_%HR~x^ew11Xg&?8Xy>RuP3hBJH7AN?7XDY(;DCIi0<5&nCw%{M`3(fym@gIIcqZw%vNy*L#w<1HH z`vN5LKiP6_BRp{29Q?S`FX;FI4E0BJ3_JaTPB3*>Ln^~wa2YieoBHGYPd37x*okd; z3wi#)d~AqY(uwWpgf<($pua``!T%)Vm8QPKvG?tS!3F=54Qk^Tv>ThTU%#LnA@~KQ zjo2nAhmv;wXFLD1tq;(4{wE$i;YqZe|B34j-#xYSKfiYT&#IwAz7l>x+xefC+s-&o z?aSqVekFOI|60apoTjvI!skKL!o1U`tg*5jx5WXNxXZ32zquSonnScfz-Xe-noBx{iAJ?vGd? z94?$FoF}Xjt`wdxyiPa~NcgC5oA5JX6pqK3{}ACo z;ZedF!V`tH!ZU=I2yYbLDcmf4PWXoK17Qg7zFBW4VY%=W;q5}M%Ef#y3iI&(lkyPZ z1flN-be3e_59m_Kb;4%hX~OG-8-+IuZxim#FX-b+e@+;|rJC)^74{R35|#+(5HUxN z6V4~1Z?(cxgsX*T3(qG)|2oOn2(MTC48NzB|t*}|x?)TFh zXIvJ(3VuKN6W`A7#IfLppJ=o7!+%`n;yw#)ABoK1=Nqgrk0m$eI}pF0li??k`a5Ii z`Ny3yZC-rc2pYei{dr<)^V3QpSJ4ceH94%WtjC!=sFO;pMN?) zzn@+5oCEUvS&NHGj1AD{w`mPzyC2u)d)FWK1DCCMKdwR8FN2_S3H0$gbL>Q4#e;0{m|zhw+@!RUHyKZkPV&qefBrj#eK7IFp%5dx*eF` z&l>vQ^op4OJigqX!fy9>v(;ZTA>Q9z{eE5#efFI8$AXC4#Q3&_^&&DCG5hlS>0tg% zikC`^?XG@5x1fFR?jaxievTR$OKkh)ca9o0{6N=(e|w^-FwXDng5C^#XZx&6?q|mA)=Y4Z3~xOA|gC0^5TrksX-%X}(bIf?` z-`trFOa~?dlYt>%Xv}3holT`B5AJ{i+3ioPxqU}w@Y$VR?h0&t6&k|p=9SFa?q+P< z_TZ`o+ajYEY)d+<$F}fcH*d`drENVYw7qrGeC$)PFT3ApIO(igokb;iC3Cigy8U*W zvns84-8N@*zt-(_eI)H&ON2!CsSdFv05vZA%`vWnI|smQTx&bGi|%UcWP_ijDA zTXSpv)RC>{t;%Z+OwDV}8*OyVXKX|3_fvbfo;$UwHL$FxwV+$pHutcm*2t=g)^q3g zZSAwFymf82VaPYU^(<&!J9Sa(+W9M5H!U04+HX}sYhZrnkgLb16`#`j{bkLq=S*FW zQo~XDmgkZ`34h?O4{Z(RJb+&G+;WFAt>k&M{zvb*%a*i$7j3?2D%)KJJ?@b!(3=6p z+glfnrk3rk)FA_wmDN7dW@m@!It3G2|>pHb>i93 z9@!C!WbAN*fh{+dgj=TnC9vUDjC^qGg~7nOU`t>$V^Y#k(m@)xBA2MJJUBr*7JyUce@owu1HT0B{#2EH% z&0p5J>xkBV%lfviUG)OSX(UpYwBEcbbLfo|4=p~dcqQh>OV6c#68bQ>-r0JN!(*1d z$7ln}e^G9CGc?Az z-M3P~5u&|1(asbT-0lxi4Sf50wIxTB*@FbPn?!&3_VrRTqsBL7g4_K+ESunV|A?9s z+;0B1M=WkPZ%2%8UlO>Zvv5@5+m~SwvZ5rCwc&O%+2VG;MEO{8z4yfJCigJG?Kb0` z;CBCc{@+)y}_j-=kijJacM=xVDcjI<1MfC^4?WUbM zeEUuSa3cJURXr#%?%UVrc28mEheSB-66JjteEa&`?rMq&Zg(*cO@iAU!i}KC?LLkb z9VEA#q;B~3B?Q3j{vO9;uiWmFdC*^0o2N&w=27~6>IgW7PtFN)^BmUM^nGW?S366RK((Tlh0>! zySduB&Fy}gGJN~`-0p137Ps4QdTnm^U@Ek^-MNggx!w8f(j9@!IJf&|9!dE2{R(rt z*KinpZZ{WJN^rZ)wZ!6f8v?e)?I!DeuiWk-(3=rC2EVSDC%JEPWGrs?4_VaWcJJii z9~ifrh6pyddjMsN+x<;;$l`YYmB+y1cCTR7@a?-6^C^%wIk%PNEpGSWoM#rdn>JH6 zxBCd@x47MSzG};)(H=hpMaJ#oMht2J-XAb!Gork6yZa0a(FdtI{xZSU_Q}FHU zfM%re?v*&B=uQg#;>04e(i zi0D9tecVz+xqorl54^xfbGf;bac7(dTK3!S00t)@?g;GpwE1%1aXYbw8xU~;BY#E} z@4B5>4L`B<#-5+XoLgN(x_%N7o3R(LLGE_fG$;cTZ#yH|YIlcgTKy^_U&LN;1|$FK z<;>z(VK3N1oga9Sry}BbM*fbGA9}?b5uS~`fJNNDx!D}V6VSZL*!yB-%D;OJdKn^L zt`%I4e~9dK8~SlMs${hVOIi5u?jekvgc*AX_JR-_^pRJ*9xsee#@=_CmLz6bH! z*bCTK_Y<$?k@yKa9DBj9yvVL>&JBpTl#yG!$X<->h~33r@H;QEfRUGAKMQ-`mcfqu zsi$%)592;;gl?hM2=Vei{AlyRn#ry&2FaTU<_nWry;*M~0l zz7^2-nWvA-i48Sz(D#|AZyMw&CJy>O^Ym3fF2jz=`WdQhr@&9a3%aj^3*@L1Odg$f zWSGv1N8!lzDRhrXH@=Dy)i1rHo8^v8x@LU3i~i(=t<3UloR2tqHZ}?rS0Hc4b{rY- z@rslW^Td0J8Nib^PE`lz6)uQp@E*u1L`2Xz<8>3@#fS-r-@~>ER|(gdO}Gr_YtXs; zuGI|C)(r6kIvqFh3{V@{=(B0T65n9L!3{F>m>sKjBIG*95*C@@NrW2gLFcsQjSMt< zLd!-5PWOb~QUZ)AW&hWNzD9nX|XO|5t$RbxM;RF+0K=2OR<#Q3#hU&SYE8b|E;Z`t)ghfnr=5d&KI0Me*#Sa0W z#t!uaHV@Hb{kAduG~!2Jr`LoW_G8PUE^aYG9-F4_XYHZJ;K$*?-(u%>{d6^nBxfSSP~rAH9LLcolJ&Q zlz$3h*wbOy88fseV@5+_KcR`R&;)0*hi7`hZvi-6P^&*{(5ytiXQTCILwmJh9wGGK zYHpHqBc`X70iGyT>u51YeLW|+v@eO-R_OjD%>SZ`us?h7GZ zjU6LO;FZaB<|mmWaupcWZKbaPdxSz#QICxjrejA}2|UkDMh2E)$JJqO($H=j8E(doe1uI_l7DnfIaFpgPF!pt zt{LP4rru`SY$RSqp>Q+eIh#?_^rRsL=JdQC2@&U1C-w8syKSWK6XtYE3EuhI~FCvea?(~VDEX6F=c zFnwJ>;H*V<0>{gB7Wl&keg5o4hV@9?ggxk-?#A11H;&Elj<#b zz>95jLbGQLUi?(z3KMSf3mOhPkG}UH;zjeqU~jhk5iTS_rw~N~?k5>h?+(LE;&zkH zuailq$BxHj`1h>l!JqN4nPK9Ix>Py)P(WK@D!mjIZ4@r z(STrw7?SG?2YTtI^gzU{Fa_AEEDjL{Hzlda6w4VDOrgrfaTIbqYt5f|J}aF$_oWsKOkGthK`!6bd$@nMs`vHx1yi7=+P_ zGBzWa;%m)~9V-1^yZwG*+)=m#^4D;vgWY4{Zah|MN;g(G&9ur6jtQp)FIim}?iT#O zVUEGxQB5ieC!4}Wkb`SiyD>BvGiHrjl@m@yN;s)H$wiZb+s-_p@J39r;5F`p!4%F# zcMO`_qmYw#Nirtb)Ntzfa8__tES%bxI#!*~sZ)+u%|slP3``x4S;P!_Pv|yNWrRki z7+IEbWV`SX)|p|7jtO^7a*r*V5$=wefs^CZ*l^@Hl>;&~hiT#N!w`WgaU@Ix<_L$? z6EH>%V>qapCWAR7H5{s7mn!zb9Fk&WKa{$rhNFjvGx~R@a+7tr$%@&8p?P?<8}5J; z%Cz4ev->b+JPvv0Y;eOpF|{eHU+HK8nvq$Ek@?e^g;UMwzUYqWgtn&yzqdNZA^nq+ zoE7ezlpBtA=Shs93(P}9F!bT175h6~t@F7Eg@P?;(o`x=pBhXxhsryV%{8QFIHylI zi+Wi>6xhepzlSIm%i|^H6~`TeE0^oa!mqZhrM{sO3z*c`l~uODcCfs0Nz*RNiIg=C z8|9Q)tFyGV(~d99Q&m&WvXzaEb@ecYTm;j|=1Q6e(@3~>QDaSIU6~g*Vf2D|O_hyJ z3o2^LYs(u47cHo&Z#;SEf(bK9r<9fr_i#aR>Ffow8|#-}gdEH`;MBLsvVOZXFM9P~gnyYIo%N8w1sj{Y$Dbpun zNEf56WpT6bvNA8)H`CNANA*=zO_k_bWo>2SlFGUY^n#X#O_dd1;8fGG>N<$kb&H+y z3cT{izast{!hb`315}KEV{`q=iYASDS=oy6n&p+wq?z+#6N*O0MimYzEQ$>oTr{d^ zNYT((|HjIi%JQblLu21uQc*E*)WAjPZpG4AW95qKrt12-*pLw;2agI#zZ>(5) z6zo=4jI113dw5ktY~Yf`E6W?J1`df0oHaByu&SPos6l=X|<%hwzk}yO9)x64>)rhO1%?i5e@^YX{@ZQscu41&#bs?-t_vqB~Yzp zv6@y?*LhcM=gFpM?zi?CFbb&}#lEpqS=X4q`|sg>nC%QaTjm6aG49JlhC#EI#xor6p~ zC(XgDt6b^q*{IsK^2X9!m_r!L@)mPW*NhleZcg<*6{X2W*`k`0o2pmwz%8VK zs?Pj!@K{wYj(JVM492wf4sN`4-cjaEpTG-oRbBI`4V5@m%?SB34VOXAQQP?1Tz;K0 z=xL~|sIIE6TmL#l|((#wOM-s$9Gnoy2cbMP*Y{ zePdH>)IeTH2c9wvm$+s1jfWoW)fEq_>DX<%>;cxpE1zA*XXKxgvNrkL$azWUhc5_S z7`!O(ZFgM8!eCAyBOiIk4aL8&*t$G0O|Z6*(-YE_-YXG=LJrgU&dl4|KClPzBGBG~ zc%f-;L1X2ShzZhZo3+7tu_f_&9|kkl7Hngk!gPN3N^HBY>yzX3Mlzl@%}d8Dw11CR z4et^MlkI%`PB+$;RaG}~A->AShWZ+wjl48q!z&0UfF`q*0T3{0he7Nl>`DYxqkxE} zb3QP=NO+8}L^w@I`X2Kw6jloPwuJGkgl7pa6<#UaB)nbtpzskPS-sTrqVP@O`$A)* zjdWw94Ky~|z!D4`%N-|NBs4bKh&ONlfaXmT(Aa1Ljg2guEYt#b{QLOps~>g8XIk(vC#$^8*QMm(FPhD zZJ@Ey1{xb}ps~>g8XIk(vC#$^8*N}T*{jdkXhR+-+1O}9o*~)TXhW`*Y;3e4Un1Gq zXhSwO+Q7|mh z_k|w_gS5Fpdn3YJVRzx-!a>4ggcF4L*)a16mnnl#YcNyTMc6}FAUsq!LC6m;oR2ew z8T_3^e3r1Q@DO2v z@KE7k;V>azbFutb;bb8{>ob0?@C0GGuu@njY!sd*TrE6Tc%g8e@EW1Hk3c=&l}yL) ztoI(_Bf`goWXLj|uE>dR3*QrdDBLL|6PEcp3l9;JD$e-+!U4kJLRxMyeY}t~0m|gv z63-BxE4)xhiZ9cz5pEKGPk5W~PT~E+hlGy_e<3vYJ<#{OWSVzSzqt8A^9lbIANo3h42jFS;F&$7Yoh(7xa-y z&HDH?pLmn-R^c7OdxiH49}zw#d|LS5LRy?rpSh0%z9)IR@Sj5F;ciSCflxJJF z-XgqLc)yU;ZkBsZXzni&en;|l;fF$Vzlm@P?;n9(gj^wpa-OiCaFlS2aE9<$;Ub~A zFGYE>%Bkln;q}5z!XF546W%MlU-*RZDIx8)sPB2O-QG$G9)sGlo35bqG)Ei}(Dh<{k} z6T+v2&k27gd{y{I;XA@@LRwm|o=(Ev!UEwyVUh3%;Zeeg!YRUIh4X|b3d@Dn!dfAX zI#~bZ!W)F&5#B1iL-=Fi1HzvRpAbGPd`?IM5$bu4vVUW)sNRJ3_x=P}6Uc??*l_zIzU{zANY{sLa0_)COW39l1=M|iXF4&mKG8nLjw z&kD_R7v%qu{72zi!fnDGLK?iVe3~#@Xr8+e-%GN2{(?+n80J4hXr8wqo98WHh2ob8 z>xE51Ty~8wG5`4lqS1$+VS`8MJ}rkbGWpLhPGQrjwaw*=fOxBJaH$`{C$(m$(0u7A zT-4O$6f&Z4Z!ZtO_O77Jdtcn{I~+@H!#s%p#}JyWH~uppZvD)*Yd)rN>xUhe!~NzP zfIPd_JB$ZTn;+yeq_3MvOOY@O&#V6Cr%go!E5VrMQ7IU0W z{7GS@U5~J>?>*>aKiNLK8jtI{9bxJljGfy>m>9irJp7Gm-1+Qo=exZS&%b^qr7`_+ zh5e-bL5X9{IQE0vX6$zRK1BO?ePH|eRe|}~UcM8+Ty6lEZ87xObDDK>Bl_n6~z!^#1&#e}2An;i!kr zyF61YJOR1k!-Z#QAP_N}{uV~f=yD>X zLg7j1c&0#)yXGG+n>uNtX}?HXxhKKKbNT};jPulr%m6V%U0x#`*Zmz6ZYoM z6Sm2WXhI5mj^lGmOqz1EN`vVIh6UWwK^|h`z?PibShx`bK!Z_ zX06VZjIjN=%x8q{&*d1ZwEel{GvYt%&xPlqy;dh>E@Wta4bVEi$Bp}QS;!yHNS>Q~ z9&+TGYl-F0g`ddnwK~_Z=z*=(Nv{yLKbLP&w*0yLg);oPnBQPLf~7L>hTqJ9W3AO$ z%xkZ;R_D)I)bi(YF^3ik2f{JHR|6Zhw`f@8T?e=c{UOJ9~hmq8r!gg=)ocEI-M(gV%H zTAk-&oO{yC%r5?11|e#7tO}`4>>)NQb{+o1pGy@IEPpOxRFiV4o4paK9q5k(K3skt zN_zpJ+&?hwu~5!Bmc-JUvr%Qr|?kbi)3#9hdG4UMsb#M(5_XLu*n4;igA`%qc^Qz7k7E9s}E=9N6^0 zCMu&K9L%Hr6pe-QI?>Rl1*!e`p@woQ8*cR++ zOL34!JbN>m@wxgkgo#@fS#)hbi%gbaQe-pHeLI;%1*Dp{A*35(cj9%rcQC=vHwG6h zFXJFu9kexw@{Nqdh&Odmy+=Ebv(9}p55J|Jk%rIzj~oB^G8m)=D^{al@N73oGJio6(LNG8h{N-)4uVBW1qzOv0SS zYooE*@=Pu~b0OdOOEz+*F)|ZVlxJ-wiv`9 zGS$ZZ#XmLUMlQSC5?KaOer{tyw5L@RW!Hz<=Gh$DmNW^wtGH=N+*s)UiW#15!h>0W zaq^7LyxE(u#**P2O-KrZ#1@3pCVTr=teKdL3S8_l?6kG%5A-+l{E)cb z#4i;vy4f{0zBVF{S1LZn;RzWp1n@eHh;O?5Hb&&PI$~EMx>rC%rU8l{D&+eZ<~v3> zLumNMh+inVQrIM1B|J-bsqjkSCgJTuKC82yM}*G_UlhJ6d|znnZjiryZA5R}jNJ{! z!`R&bufvNAj;GzW$O22#XXyM)FwUM8(gRJXiP)#T$DZ)OV@mbwXTz z+VG#ubrtz|jb{7s0?{C^-;_aRFler)kooSC@zaH+!sCTy!U`eZYcjvNjsnk@e6i46 zPZ58uoMp3%}<+z2wUGR&^H_Nf%@1MUmxeQUj{*^6}tNI-KaJ{ts1f)W>P22 zvEM5X!B4A1*sgbHFZ{M4j`cF$ueSwZzYK!TcIb;Spv_NfhHUHmWz0JVsE^(D^<9Lp zUj{)ZvxAq9VQzlfc?jG3UWz63;j$FhcY{?1K_>=%XYOHK_+7@<_jW9C+)yO0?^cA_ z2F?d=H{u45Tzh|G8uxpJe!e9*kyrScl*W8NSJ+Q_9r-wi{Eg$n?P2V8`?kjt{mn+2 zKYss>Fm6Q}0A@?a4JYTSzp+kkL~9tFvB)U?G(7_+Vzi zqRwXVv&@gt+c+O=G_vfK5B3w(VDZ7;KtYQS_9BZ8>AsdjoR`_Lti_28P2=)ySS<)2 zAIax1%U-3Rvtl=7(uyz62iuC079WfjP!=Do4{J-T?^T8#T70mD7<-EkR!A|y2YZF8 z5`3^+_9MXu>q%7>AFK#9CHP=8c-#jcY#voxd@w`H*%u$I8cj>^!OVCk_+aO~v;M@WH-IF|oc^ z0eh6-gLP$_6MV3RY;%GS){ChJ#RvNt6j^+*epgDqjBto6NWIg%D1?5|#WoDX&u z%kP5^b_3HbKG;Q+Ek4*O?1;q&qXDJO2m3wixAz?4z~5*Qe~k z!STU()rs@LI&&=d$_INCUHY>4VDGTn1Rsp+LABw7{SZ9_AM8qubI&zM+=UPJUx->A zt3#?2dzQ_L{Sg1b2YU|*2|ieFuUJZp8+;7!VPc0Plhdm|>R#Q8FC5S8bqMmG(d%V| zPw#aX{-4&12K=j>NCt$IHEx(BvdCIglyae)&HKs@^tb|A*?pljzPrgi2^vx!2<2>K z18^$sWWfhRS?0wKXl2D1)0CfvvW&rB9%*G%5DvXc#l_70P$*31Rv)(mrm8zL-DO+3 z9p-`KzKM#sEZD3VL;VpQ!=BHo-Pu{Jxf(lP!Q`_#_t=iC?H-a)~B9_Or|du)JowQz_IWcs`ALny;{ zwkXq1Hp2tt*MV#na*s|+1DVWQN{XvZC03#`{Ie<9dt8fZ?`*TA`^IDL`fE|y`T8bE zX#Fe_TL1l%&^Y@+NaMrvZW|t+@#H<5kZ*!>2|O_nOJL#Mmz_eSHoguNON~lEICF@H zm~gW}YV;Uu3{fEp;QuaLI%H7S2wqc;OJwKArd>AH0J0jvub^~eqD1K~*-a)aUu4i5 zk;~&*aDHNoVef-I;0)eK^jZ-g1q=ux&DI0|adpEMGXMFHI_=Gtzl+T6T(~85%VW*P z#Uwsje$BXWMZ>=mT)5xjz9E=xoan=ieG=W4PYB0=nL+pzr|;`nQm1g{;S44fk`&hg zq&Rxaru%xj=mur3Gd!6Gk2j9I;pg5tg>5NU4QoEc>^#?75vRyuFOgo&l4yLssS zy0GX#*D*eR_s6FDw~^;gDH;ya(!Z8MN0O4~*?8X^x-Z6FGUv$Gk#-lK%yTD}&Mhk$ zH)Z;~ITH=Df^OWGgJwln*a_FW`{Ly#_!vGbtY~=Lv-v3?uFDB&pC74%qcTVoc|rUFRpFeoJsR$Oq@B_Z>DkS{2wO$ z{j2DH@lKacnLn{?#*|WA{w7TJy_S=WNe|1G|LFfbXV0I#o=g5OOx;UNWqzy0H2%NB z<%=_n|9>O(@!s0@xy_q*f8+fsIDO}Y)&|dQ=k)P@onKiK+wT6c@wjJgyZh7bWWHVU z*@9zx0GvMa1G*ch4=0`ox#r30%i#2lLVL)SDG^Q+enYrWSSf50t`eRlyi|ClaFg(M z;e*0QgwF|I6uv2ZU)av+^Nx%0rH$j$>{UqZ8hVaK07@hYKeP+c|yS_!wW>7^i1nCWW(V@`6kILg{Kn{f1c!vgqJDa_|k@+jf(%C;_sAvkMMrQKPLGX!e@wR-+M~m zF2rTd#Ph8Y)A@T$xDN8?-AZ7^f`o&N`6ZCtndxtpM~3mJA|JIKNs?aIs3zJ%tWp+N+gAW$d~8DF~VXY z*Ue=7uD+jfIdB4aZ|{#MM3c`S?|&ti5kJ%ITt*H!HXI(a^~3*U?D(uuZ5N z`r)NMw#Ck%1fAp4VGj{t$lLrho_~IrDOZDgxX6m|gOy0L>mA$&ZA2pLWxQW6 z&s)C?g3eCdlExU&=BM#IxAk3?m*C>D+rGYw5cbPZMHieXJXie9Pdg70w!Tf4z9`as zeK#QNm!XdSP(~+U{^qA$hX`BWUC`$rH{NCY`ff#-WjG(W{TlWw)i|I1jcMHP75e!` z;giFGa2fAHzCF#WhoR4I-~Cp9d6)0EZ&xnkE6``pX}`ZjYZ#nNkc1C}%QzPEZxG7* zo3F1UB7%M-@Rw-cYnJTi1DA357vVA=!c(QXI`8Fn=HwGb>#DH`XtEO3v_Je_k5DFZcI~)*nlRh?(+=TuH1L3Oy0po)F zh_1&mB>>6-AQa{r$$?h>^SFz_P-G!flEd#YUmIU`NHcEoU&Mh7=42g;41t?aRNTeD zG{z6kS!@c1K8BhAm%(YvT`Wc>H*hE#B<^D1WW@N~#pjWKckbeoi1oRPQyBKSi(^pL z9(~!3q0R(%@pg(o44WU$JS>C#Ggj|$7XzQ82fJ_=gKqLFlrY@I09VBEec5rj_c(X) zIwtJRmt8+54oO?fG0IDhl9y<47mvh|{G!~&k*GV)U3?RIE$-rK)|T*P#~T8RyZ8Vu z!WMTiiq2cy#qH2*aTg6=Cc$0Y#LNlqVhdGS+{KxwDZyR*BkP@(YStjgb9jksMK17RaTgz?xL59?A?+o&i_h_pCb)~n&D2407wO)~;x0CEEG+KgIc${0 zU7XFKv$%`Km)w#-oV)l}wrd~U#SH4VxQm}Mzr|hbN!j8q8tzqNAhi|0mVvx6xj$q5 z7I$$VWsAGW#Q<#X;w0*`xQkqr#O5yki2bvC*`3e)7I%^7RU7W2p(@(kMJ`*?hP$|! zDs5kObJ^$rEO(LTq3z3#vhB<6K6caRE>7i-XWW;axt3Vm#TNG0;x69Jq6fxZ9KnIG zxQm9EYH=62GRFaO7rB^*&0XBcq84}YZno0$Wp_5`g~eU$!gPzfNFJHZUF2eDHh1wY zrd!;_?=#)vE*{Hti@R9O_FWvv9D#Wo%vKJWMoY)g=mha1s=4c7- zV&q;FOy6%*0#;5gm zret%0hV<+<`J;CJQD|xgE5v`y#E*qZTk#H=*_?vK=4Kn}Ueb`~{ zq0k%xmD7hEQ3{fYzJlF-*fABfKs(dEeb`Zzz1gzo!)_RUD+294?7o&h>_&biXnUJU z+e`Sc8)AIek%0IAu@5^?%*#>33g@nZ{Yr?&ywA`|6j2rUZ9g zIzWJi4zeX73;QBlXd!^Iix3F`0s&b<5*AS*zPK>1Y&t^F;J%JB>L@a>O|?>%>^Th&#SQ_r0{XJN&BIH-Y3 zu%dQmoaw5jvUbUQ*eqW*vq~!;b=J_4Y(>BOcrt=PsyTQd3!8T~~tx4?0R7m&%%&g^M&r`Dcyz zTu=)t3P#Icbb&ggr}lPR+>2IbFRVMiy0TU~DNUVyVfdM?Zc#;DUd4>L1F9-&W`*(= zRMgC@8h}~3v{z-`g08cxLwR#%Evu-RomUjfJF7U9H+$itJa`z+orzNO=T_9tT{s6y zo}qPf7cI=ItyEYG9eGWi^6cuonTrkPrgg7tzVDqy-=>lyefk-26I_55QQ@g2c$1WBGxeM>?9@r*LrL5M&5xmn}D zPpdf|Kl`~^^NRq!^!9fG#s z*>fVlB&dEL@Xp$9Kh&yzyMIG@9YT9DsK@)HEJ^?0;I8ZSpYQIamWAN&Hph`$cMD>B z44>NCVb6THY^&|Wd`#ok5do*{_vR}=o)hcMhR)u2{J7;J;FQ+}A#l42HyE_f`wiw{ zpj?Vzw*gW0q3(LTKejhJjrRdgdmCZzWZZT1G_lLj#(S`JGVZ#n6Y}{n$4P&n;99J0;h1NKhFUB~m;Y45dA{J5b=%-&syvkjaN+}7g;?^$~?LS`Dn zLxOg`i8zs$LT7JwzNevJ+}>V6KF%R~V?Ve(j^J$HJE3@g(~)NPcQ@jg^VI;gHNl>9 z?%Q<{?Q?}0b8%z(L;StUF#qzDWou{KJJH|k(-79iJxMLXzozmB#^yeT4e7mUE5;#jU5lgH`MAj)C06D-vxWl*We5gTi z5+F+)e7oLPqNy2|VhrHh#iE9+Q+fx|l1;aHE_5LGTZ9tL7&l%+48C2nke>1h6!h(S z8yL8i35Ds5qmI<_^Wd%}HJX8TOe{*Y8sH1aI;EDF6zGE^2H!4Aw0Y_Nstl2rjt)Qx zbFn*up!$Zo?R82o!vF;Kp*8UBviqk9hWd(V24tO5yYgS-JcnpkZ@n&|at1%3l&x>qml@&PpF1wAU$pN0lEH zwAU%M@{bAH>y&bET;U19v)CT^cKt%-pB&_QMc*!-N=EoaSI}Okl;?;Me#I5E*D0m< znGt@+9aNl%@a-zVkQw23-N78#rf=6#l>;1BZj+~ib&wv#s5=gl64^LpqLY~0d#rIPG(#_cwUBW8LeB%Zo{{$9+)*8^FsM{ zEkcfTT; z1sDbTcJXJz70wBM&SL`KE~^*AgEzAm;H9fk_QnL)F+X_eE>KOK9K4U|@a?irxGLp> zL*Fh-t`6Gklv?ug;2gFOzFlq9F^6v#-&)bPD_<$r=)rf`V)%Bk1x9$Q9=xATf^Qd1 z7~$LW;LAv%ZS69PsV36c6jcuFL^mI!p1m9_&j6cwG0I*AjSDr=U!= z))MN`8lFfZw><1!=`!wzq7|}j zHzwFF#N8%O^lUv!J^KjF7fSyg_6eMW2?^2w@W&}HOZay2%BSnCkFph5r!-56F4J_b zQ%Vjyi(rnvT{B>%Z4miRx=!htNT6?5Pvp{dFIRE!Z_-mcL2R}dI}pmfY$iU5Snvgy z_3t(_E=OBAh{G{v{@sj_yv$^^TQTcY!fZJS&z4sy(-ebB~LujXe!;ul+ zt`Oqf^o6+FRlZ#z#&VzvA%s~ie7jidaD*Y$u`2!aOxDDAB1@=abM%3kY|ReHk09g( zI6Q-tr<%P^X&r1keY>3NlO@Cge6c27c`*{7lPAT6b;RgU4&O_NkcH|`T z1-!fXd7aY#TyD16#YI0wC$FCuDy7E`oDwWQqu5HK&V@?jE;wKq!g18_1V}%kpBE}U z-YttRR5M5~^|Sxhq6ITB4p{8;r{k;jqkIvqtJS~1rs?;%cl|ieuK4*UE^z7`{1NV6 z|GlSI`Ohw1KM@x%wdAk0h%&Fr|H;l>eDQfI4l~~8{nUNC__yfz7QaWO?x*P66-2x6 z;IE!-zn{a*y1bp}+{Md^&0&T=q5WIFUHm&9eLso?`Tm8n?c+6Cki}v#cPZul|oGv&|aH-&G!L5Q12tFzJ znIOOVr~PC+w-8$k<_fAmjzQ05M3~M+n}}6{e5*?NazQSBLHRbphXwiOp8CHDelF<3 zYYXaA1w(>-olAY0;CX`lgpK;`f-ea26He;C5HxTqP)-x%->N9{O(t=^;01#G5SIG8 z1RoWAUhq$X9|*R=OA_YK6C5DO)uE_AS8##gMS@og-YEDh!6yWF3+@*@B>0VB0Iz;% zzqMeV-~hoh1G5e{!Q>pLATE; zpDEZuu!rC0%V5#63!AXK;f-?nc1g{aiN$`Hbmj&Mv{3{X1^lyR(h-ll_f^@u~>?Wd} zDI(kJl(rCkj_B=mO7ldoxXn=BUZ-@h=+*k9s8?~9!R`g3$K~cYUnl-9vVAFnIf9)8 zy9ui6C-My!d6eLI!Jn!xR|&5_Xg7a9|CfEa`1ABLcNfN$8-8BY))9N0qPQoqw(f#9 z*!lSPEyi)VQXBJytf<=K@~bxfeq(xTgOsFc%klS0+NaMF^Ds~ziD27CRDD(YUzqdu zW~ZG2h0|U=>T+2_e z_vR^lx#~`^w>D&*!|VsUZTI6!#GUFm z@D~@HWA>Og+i=k6;clG%(zFdVp`xIK_UElA^HRg2I9AAet3(UlM2M(Y0 z&^9yDZLPMZvZ`RimWXzweyHBh{mE+Y9aUY{mLJ?=oOWIQ^}7$`rgi;g;RfySeHULJ zX&Esh#$m(gupu#0?@KApjpVF#>!A$=5$}-{Bc-72hT2F@jUl^CQ}jGd}Sd z#)ka|Tyv(Pp509;_0JyDnKB4@lXf?S>T4rIBF`Mt!pNz&jig7?rPS^N?%v*Y`wy6D zELql+a^LQzPAKh8OOEV6;L)d|y^!?X2Q)nx(IZluC)Ki@9fsZKj_KhR5xpTLGV~Ll znF7m$(H=kA<5O0jJ(iH>i=;;El-&msdzT$BU^6g$|AB;IRvp?f)G@5t_4^MbL1Us9 zgV2tIVOqoPrZM&Tkq&Hgi4JLUJ?qItJ&{j*$@>o^PojnNjmSMow8riOslE3fNWplR zqq0$Edi_potV%EW-URZA>p|h;(Ym-f(y1vPg#pt?TJ~T5qVqk=M5VIdWB`UnG0e zv?g=v*d}vi_Bzakgo?>eGWe5(B(0&_D_5=ZWg zPZGR5YAKPyIAW$g@)K90IwD6jU+YcU=G{&6x9NRQ*V=xOyCbdFy|}j`(yC#a*1qAa zgTq}zo6Ou1T4?jorj+c9w4n!#Nh!rCMeR3)8$#<_Z)m%@T|-Kd-mmTYb{kfGaq<0y z4Y`|J=`Blg*XM0+S(3N@H0)1X-xd3=>kAsv4;!A`J!c)f%-^*k_omZs+9ePAd(EA+Td)C2H zWA?B!QObS9bpK`VX$>PwPTSC>p}bAEh9`Z0Y%-tjw&%1hVUD&drFi3z-cM~A)-K{X z@@+xxQ+hl6t-I64r?5Y)>sseNdrA%_=_9;7_M+b8@dr$O`~lanpToOENcmsP*+pG^vuX?3PEAZ|a4>Sw(ZrM+5K+IQAyzPmP4_}*) zTkID zwXWHwUVuo_K>RvftFC#+@8EYjn9o(Z?>XEm!0+^BWHfHVwL0#1IsqAs3Y2q=&N`Q1 zy7w{HA6X){PV!Pn#wF0Z=47pAE}#1WKFRvL3t%n2W^xJAj9XYfCxcgEgU^vhZu(fp z$#-k>4*r4h-s#JfE%O?d*o+-G2;YMW&PCXJ9zkKeiMOC7*Y7Crb7$2 z3C(CrBlj9CYVau^9E7hUEB#dIY;3*!Z zw-chOzheSXHuBGDLy!p$l!0nyelO{K)uYJ)`qRNrm1i*hRJXCBzsY2ypDG)~qM2&P zamc)!JL+*ilbVl4Ny|@_qZ2%jcHyULbw~?xkxFt9-mbb}2A^j-I0!A-7d*&{ z!9i%rNtXW~{8X*-DZv*|sdt{s_h;O-(@*u6%nv_RE4?6CNEv>rbS`s+y9Y04ec&Lp z(t8Kp90mBPdidf69E56tYH$!*my$ujnY0fMLMwksFv#-oQ?=5E2X|2h2Vs&bKPt#R zlY`L8KPJc*d*mSG;LuNX0A={8KBn3;Imq*heyTi`l%MJh8UzO+&k^OPI)VzUpWFsD zC_mL?b_sr}(=lYqPxXD;fS+m?l|%Wd@>H-6(nrYcI7mul<8Y9;jH}yx5g9V{qtI}I zIdM4`U6+PIS8Q`ZnO)21~`e){VpDJ6R{8TSy4*03kgz{4z&pP3! zYAN8S8bssir)nwSr+Sz<;HPRS;HOGQOZur=3izqkaPGlR)vASls#n82TcySneyWt& zC?&&BmGVMcw*6E$K@psQ6mk$!;Fy2LF@T@y-Aaa^Dldu@lqvYB^5F1964~-o{WBD; zc-5hwDi3a}9vlhysj^n9{-|9DeyVRFEBsWc%GP-qP_r8ojBej-K zr9bPc(0k~m7UJ70J+zGlwARgFh<>WGkqdsRmB{D6R!_edd79k}otN(X{*8M2v(Uh4 z^%*nq7}Wgb)%?%K2??KoY5z_$jfr$xeHsn%KWC=tcsFDb64IL63$kQ zGcR(q(|4d9`so%cAqhRX>F?ownVzcyLyV1rDuNK^pG@>YsWg2BWWJRN|C$3aIF;3h z(c%^e;U3I4B<)e8p9i@TA&2eMOH!EcA;|o~B8P3&ho#USZcwy(gq#E<=n<8VpH*>X z)DG3lHT?{w;)E!EnQZScbf+^y&KmY>WNYfu(adkDOxGij?Wb9phLzk&(}n14q&1%+drv(Y%7&GBanNAOeXcnjD<_$EbcDRh-0wi5bD zA+yXTX(UUv?yech*4oY^(g!Ay_p*%%D#{ZVeQw(c`LgkHHKZau@BTL^9Hn;WBG6nI zI!1iyvKEWRw6NZCf}~Ns?Zgzt73iWIVm;=+pmu2uvXITA&hG`uGjq#BRQNG(62R~FMrwohGz5;Mu1zFZ zb|%uJAQdSQ%F&HFA`; zAb_uva2tZ5)z&pK!qo;KEN^7wVN1BMk&)jafL4=W&79imMl?LObwbSQ#U#gQaNfuk z9|gNNx>jcQ1yQ>vhIV1R7ZBn-fZ%L>nQhscc-E2jSd&pD-Gu!%1T>rQh>A`nyoi7? zzGM}B9bQDxwW);PtLQX>`aD#_RN&WWq^rRc;hpdf6`e?UT1CeYc$^Ha`ocy|!^^Cp zB58`asH0o!;<<3VQ^zcPo*rru#pkA3dg*D zl?Uey1x_7wseV-dKapgJTr?QSJ#>uy`M(UtJ+ zw=EmlKMt;%D~wnZVeC;vc|PKL#2Gvt!L2RRid!}^I$NcjO`y+;p)J$ZX<29K2|OuT zqA)*pe!8?m$Ei7qr{?3Tz*qu5QdYfUgyVuMtfN;*M3YpfEG@5feU&_(V4a!c2otRS zY+S`i6#}Nw##Nre>_!ST2sl6lnNb_nm6&%>9&Ozi5BkXX7L{)jf!8TJ$v&_cu#K^! zhC#Hh!>Ikl>6NPv!8CjDF}*nEpQ?#8p5RjzooyR-&KRVqv+3kEC(vdm=F!%Dz4Bz` zF^VSgoT61IRr_GHFrh*Ox`EeJaiaLFL>p&T=sXExh}C}F3HP9uDv zqT_6{D25UzZYG+GjTbeZm%28Ez>lCY6|M(tRaV9ltkZJ}Ase?;PT9uzecwSXLk#JN+Cy_7N>f=O$RpB}DGiM?z=# z^f5LoV&Y>8}B;^KYV^A1m8C<`$d8vMyXpiFCZfTqe9`sq2Wm$|B2! z#PtZsLb%UT&yQC#!LH_HUlj2ibZ$=hZM4czJ_bLtMlbpgV~w6&QH!;%iwplxeo=&X z3Yr_!53}ZXn(p?4M#Pia-`%>0JH=QLa_eo~sYYskzPninipBZv)*ak_Ba6a}d~is& zbEkMv%F{00ZKR`gdU_^eK^QR>>F#DIicCgQCu#U1EYwaF^TCeWQ%G}(A$NkYpnt#qb#AZ6 z24 z*uT_RQfefIki$qUHLCKBtU9AAgi&BTxwOBLbdx)wGYh7tdyE9#Sekz^@{i0zgoQHm z5gCx@=?0^jv=t~dYC}fS>{4S|zL68kHKvss;mO9i`9?VZ>~6-nrARZ9?!$jHX~kq( z_GG#fjncaQZm&@s^0XU(afZfY4AuLy-F;@G@8dF{(fh0X?gWn>?uwEFGd=y!Y1^$` z+jjj%wax3+ZA3TEa28yuhhPgMm1r!n{{^kJ7GdDC-Zr6rkaj!kMDj=CN!^^JEIQ8#;_xXrwqrC8Q9VG zs`36d?&j?|OId~A6Nn|8OvPe_I0G`##fMj_!?PmPwq2XH7^6o~fo=2$PIuI2EZ0N% zE)zG6F;e3bn9Ub0EU#RS@7OA8=G1EVVyiCxsZx1O_uj`bWgq`}*Zdi?Yv-;2@%HTb z6)am0ie&3!4U3Mse8CLslc(~U%8FSU#2WB-%V$tS`<6|tt*ognn>oJ%6v73CWwRI6 zoL5{nboBTUR$NW%FA$+B4$=WEsD`61TOB{ifD7rO5yv9>c?)gq9#l*8;2WKkcXSnR?J zNGt8+pC+R;KK!exSU8JAWf=o`k@{@#Bt+%MF^!kkMn;SphB2ST!D9<7vg&e6Z67C4 zT+dw&9{Aa_Yb!~0y`ZvYPUXUx=W8g?vpadK?JpJ=_bj%>^Vv}x5D>`ET?nq^nRq#e zT_JZx+!cdO8I9*rsjaD7v}|Ur9GLR*r4{p+RBC6OIWaV}uve&eeo=m5sHmW@cVSUs zai~*G<^0Nu+RDzMsdHw|%l&Y_~7y$X7DKNrN%Gpm;jn7OE? zu5x+ag6@#(s+KI60h|r}?CPc6^J=T}W`WrYn)(0tJ~*oGfze0zF$fq6dk_}Ph)-1q zt+*Q17{NSeG>6VEgjt0%3FPwV&&>1Gp-?397BBtG`HO0CvXs}(nmcRm!nt)?T}Aa! zPCNvV+L{ZT2t2k!gO{`W##<2wLEwhRsFDja9&z*s< zSC`Jk>9%a9>XO|!izB~$CXU`hFceAV@})QjaoE&6;Avq`AnRMJ8SKb-p5#CDYeC1I zNO_g;vd2mAd5KVSR-GI8EEK~WBiWCi0n2LU;!8;(>yMq*wrL^ux5lMLKGdazu_a49 znEkbKa*0D>eStb>{-PNm`*)tXJZH|Ytl()bqc*p)5_O`(74ze(0SMPP&Xr}c1qjL) zR4iBL?EIeHE36d+X3RfNT?%o*kpYyo0=|0x^m8{T~uC$s|kjs zx`anqmK?y^2mHi1b^(?-8NX~D_swF(EFAyxTJ=%#9G=XvPR0&*d99TIX7;*8=atXL z4J7A)b2_V`K-t*~)o+9I3us*FDly=-RXDvvu|}z5V3X+MIAGe?hZt8c4vdq)U0pTt z>GZdKjOXV0yiC7+jKlFVKtzbg2)dTwp`%;gnY_0UC?xCG+(R#u{SyyVIi%q|A| z)_0^hq3{cY+7?vIMH%-NA1^Z&6L>fA=z|xN4o>{n3xa-uU!2Bsu32|E0dmyq9~{xPM_@ zVO;6DMjxDfST_c^5|VR<@XsfM`8V8(N^tILdS^u4y@utD);t04Xg~Z3(##A!Qx6(h zdJDa!-b%;c5M5k}{P@kOFtsD!I#UfiO*%INPnyonz;mHQmaF2`oX-YHm0 z18-}bo1r}B;~Im@d^t8abvYzHl_sAcr<@?Cogk;4AZMt*P_maCbAAu_ovR8SogCl) z#jZ8{YlO=OHv%I5Rzl0fOhLF=AIIgMD|#L>=Hq)T;y}UCg5w0I3swr&3N9DqpBq^I zYQYA zslNN8zk{k@aDm`T!D|J#3X(6A`6u8KK&%i{WO0yJiF~c#eS$j#cM0|i!J~qS_|rDaXA9;Do-ar?Go~xLLf~GJ|1Q`MmpZ1~-}_A! zne<`Q&k^KOk(BENFB7~8xie2Ebo3l@w1bdiS$o+0{iB2N;W zD*D+X&l6lE`V}It6ueq+o#0l%+XNpHd{ppx!CiuH3GNrfMb$k4kC9JEEMb^I7)Dg;Ms!wDzx_&32%1rG~;CHRe?$=@H?_X*M~h;m0k_1!z#n-*?!1N#s8WzApF|!S@CES2)@`EJznE%B=+XM={E$ z3DPZ+a-m>f!P5nY3DQZH`PBUakbjS)OeSz*g zvmpJ+X#Xj}7X@Dt{FC5Yf^-aFemaK`|1S8sAa8-G=O5^Z0l`$kEWvC+d_ke|brhs8 z8_SImoGe%-I8$(rAU!;opKhGQ^94y*Ntu6FBd!s=R*ugJ6{U^OOQGSzhFSHxnN7dVS*zB&k;OVaJJw)LGsGe?h?TZ z1?vT`6r@u!^Ib2vS@2fDI|c6-d{9u`-y!~t$S(=1`#r>86ZuWSzX-lB2xo3pFF%T4 z{q!y*1_j#)wioOym?zj%u&>}5f+GdT2~HAJyb-WJQ{+X0wSp@I)qN%M(M_7|xkiwl zj+7q|d{mI%?o!Wh0Eo{E?iSoD_@>}Hg6|8`ZJp)lHAysh-w8|4Fi#Qb9VJvc3g^b%M(U zR|&2byh89AL3MwR@|#57DtMdVy@C%2s{4QB-yt%+T3P=e1@{U5S@1)_gMxHs=^VFUP^Iw+?Z;45He!)|wV#L^eCE8nV+~{{hy#rae5q#_U~= zxLpQOZ6)k+{@a_Kwi*hjy-^N(97el+d=|0G(8e{e$KOSJv(v7F!fCGz_SjFhk8dVz zd$%LbG6e|S7K9<=9JM#5F>DjG^DXRReYJ36z9%G~t^WY|N^AkhdbvG@;B4P4M}PTd z)NbD{#Buvq4NzOBu0M=Rq73;$Xn1p!;`>k9OF>|ruov4d#Qf_Nlj38`GR}N;Xy3k* z$;JU=?oBgsyBok~B&(yE>C2Y{aAn~@g zF=BpVB;0z$=hDC}kpvD2U-9k(o@aiOWp4OO(_IfHU*|pIGu#{Yg7?AP-W;#XfLFBs7>2t*dr8`QrUex%Io7a@K0$U6Iz{v1k)% zd-U>uJrjAWNvjVX^Udyf%s0_In5dt5P}kpS!t>m*tag_?=slR|YCp97v8>*2HJO9_ zM|}Q{$IRL9G?~@L^+`v3NugurMAvogk7cCMnszYJIP;)k=^8y@U86lI_NN4n?pW}ZhL zJe2;2bob}Y+^)}?xqkIvsNhI^+0Ar%I3GVmL)0c1K=76tZ#;Wv-PRir>@T+?|{Gmp0v%)8d7gO z>)^QLz~)rv@u7g5G-;x6wQI zcxz@vZ>_c0i^eqhMviUrO+9z|^+U3!8<-zoz~(=+Vpz2p2vYV0z(DZeS6ab+;2`kt zdGIS2VlKr(@ZeV_;$}fm@es6$_!|5h61O}Yc`#Cpnd+L|BT^LU049RsuY5`E!8}m> zl?Uhnnm`li0=g6vfe-u#KG%W0Pkn^D-ES|#je_-)VCpLoN#X^Le>|AXE0$ve7r{E- z8|ywU`)Tlb&+L^o6gj|4pyTRke25ZepB9sp%FFdujJpvxM`z8Y%5;P89^VB*Z=TiS zLZ$LP4;8owzQJVzTm-+N1=G#HCt}^KtB}P|pOA*qdoj+hque30a@vb?5lo>N=OVZoeeuV+2zblmk8=@BX4B$a1jQ^H=OXCLisD=Z{PT(5 z!9~D1;M4u3J`;5Weu1Ovk8=@xNy`o{f~T15;37!DZ?pfu<0AM9wXN0t=lZ78x*G2| z7eQ~fEY3yHhV71X5wKzYAI?QE2u<_(g^QpSI~nI9;K#=P?{E>kh5D-eaV`S?BWVsU z0{^4-OduD5f4fM&z%6XoWB#E4auG~oRXaqqxCs1lE&|>l`Quy!d}r#9a}hkt)HoNx zXEYV(BIwV-jdKzF9wX>Ko{PZ$dm%lrxCs2ON(U@10{K8e)Y$>2>8hEKc0)g z|Av?<3EaVh9_J$9hmig_7eQ~P#<>V~P>gdC>|l@LTm(MW`)_d(+>R!8GX2wCKE8(t zK190?E`pCZ7!EFiWDcx@i(m*Vc5o3Cvl9+30^Yp)9b5!|=ZHAC2uQ-|cW@E#<)Gie zMX-#A%E3jzm)d>@7s0)h9b5#JEbrhVAjzrU!9{Qthta`B5MccdE`rOM?%*QedF6L< z5o}`xPA-C9QsLwxm`0OME`mJT{AqI$9N{q9Tm*a}mgEoXKE*|#t|bmG0zP*59b5!_ zz3V>}7r_?TP4;8WEYb}GL!2ywZ0-Rq*p-9p;3DY9kpmZj`aKROX$g!RMIrf?yu}`W zy$fV8F!dg@I=BdCQ(hhCB6x)za&Qrl%ERyAB8alp4laVz*fa+h!38`I99#q!Fu#L~ zfG_|24laTP%=J&xd z{%>&+T+ANCxd`}X-0$Qfs6jgJ$4E@kW;Avd7eNBn%u-wgGmw8(s1Jrz3-!ZJ50T{u zTm%r(1;^jROMxCr>y#2ke1owPY9?OCLM3i)H|*-m|kA{6L_IY~Z<9JW;-su%_4qH11< zbGUSya2C)z{KJ7hqUE#5&UZ|AA><69y-~_uZ!|O?A?FOG%VZs^ zA)im(D5Yyf-7AoHA}Hp8(W+~u zhhjZ~*5w9Ft+j|?ys+s@5?+RZuJ=N_1L@lla+#2~9h%o5{eh*dV*KLHRDb2ymnZNA zuqt){89rh${`p@OGcdF|0*)SQdmIs6?Vo1s;-tZL(JW+Yj?j%+n5c>uK~rEA?~f-) z>P@xZiI{##@_H06s6nRA`Scuv4YM|v>c8d_u9vY*HcK|_`i85inJtvB}ix}=t1f>q=495OtMkjn(s zvA;mtuZrb=!O>O4xPOyHHzuElq6O{H!mb(EeSw^xA$0XZ@Wa)FEGFIT?0Nan=0ej2 z0Ue{kcWFlLKVa;pJ4oS_WI39pW7X) zM+Um!WqA7;_pl1oxhE05R%$n+}&b>wy;@;eGVa&IB>20}Nx zSRs#`wBsK%qg8Q#XVL{U#`zjW_D>OVnV{N12OJNA9O$En80w?be<7ydll+R^j@HQ3 z3PH7_2$2E`YzKXBh9PugVHT5ir~yVJIbvy$T^jd%VW2;nywEn-fFhe{g9f)Daz6!5h361?7NMJ6%r?k# zjn@uc?Yl7cyQE*yAV=$C6#0`(sqI0JVf{~fl0ClL894KS;1U@BTL8wOm;6-a;Ioef37GVHp}!|r|L|0~P* zkf-nxXy6mXGIZogQ2Tns^bg$eGUVJohR}_9m@4Ij{-#*1;qVW*W*h5asCy!Qpj`jd zla$a5KaH*?J&8YYJ@Dm?<~pkTDWLE%K+h^>_!GRksWdq3mVwtT16G+grA$xd2JyU| zo1<;zenD3}O;+xg?A&Q4Ozs9<8h_Od&WT=&stc(qq6R_{g+U?|Q#g}C@7vHz<5h1G z1+CAGxEU~>v+Y4`>itK^BERDGPD0;8^< zIfB5^V{`fR#tg_x2a``?qNVzOog?V9M9hjbo!#u{q!q%oGf|)Dp}w=|6$z413w3F& z7p9NXw-0eo^h{1XC-H1WrqtD~6{bs$To%XGse4?NA1lNvx?|js|mQ2hlO;5lE~=T*RzlnnbYjth;YjECWXzTbwtF6U!=bwmmb@;m6geaIz}F9v4s& z*`tD}JtpX2d^{k;#{z<Bl`sG|*xw1-XTd4#`K(X$B*KCMJw}Y4ld<1OSekpg3dmi zuxB4kjLp{g&{}7&>IrAx(+D7BA$*Epz@@a2k&tT0Imb8T{O>dbn(s8k(!qw>K(zz} zou-o3V$W*H<+Brb7y(R5eB9w19YlGH%r_B;+5^JOY{+S_f$Idj$fM=t1LC2|MX=_` z7=oPA!x6PN^c`ksgrmTy8V!4FJs_>C)w0#NW}yO~C5QFK_{^HbnRPvakUlZG1p(|u zgxe4l=@U=9`z<|zr=5^K*=Hb0pW>5l5>KzAs=!#n*9eOAi4k_iLHeYfK={Po)}uE# z&|6k9vK|4a@D@ewL}4oeMvfp?mo4h*@+1^Ce-q>TRK9Zvyy)6V_K2$rIDp*nLx4R8 z(0NebgibvwYGe7dW*yXVeAciI>Pe5D_37k^re1`pf3XT}BCE1YP2_WrWh!=YcTNNo zS&`$oHhloOIh49KnP3?jZ+FUB8oq!y+nr2HV|cc*PFw-)s!h^_dF=8?Ko+&p&6PR% zsV7^{&xBowRGQtRt4Y}u}n2H!nd0+rU#jkAaDJB8VVz6jq*;0Tu@q^Y)fSmQFg zM%Y!GUyTf}L|-6a#`5CBLWstDbGFKh9S^Wee;P3kAO`PKKueW<0-uDfqc8zV*(O6d zMWs)&Rn}ADLZuvMD}Czb;1Z=AZ!4|ebzaLcQEeq8ErcDF}pXGf)TNe=q~#@iR^oixBfITF<@}8SDUFujMuhP zC}Xol)0xZ485=M|DLHW*#huDnyENUNVmv`)GhI}2ik;Xu%|$JPb0~Bwc+NU%Gh<47 zmerj&lQf-Wta7niL&uA__;Bd@yU1xxpx9x>gMUmJ8#qHLImf;;&icpDG6igg*sIM@ zio=NGmqK)!p);4IjOTPHW22|*{LSGBaNvKZp^PI7pvfxk1(E@~MZ z{V{ba_^a$t8oK=^%b_%VygD)9cjC6#9fvojwyv9YI}&te<#o$pBSDov=@rf{hm~hg z=7funsSK4O;lH~8>N?+9tw2E6r#Me#f9##qi7DBr7nd7srrLAI-(!1Qi^zI}EeO1> z*c)}55$tQt?_lJ4%aF=qpS*h@y{0tQj%NlZaW-1XUn+a!r2YcIp0>8$9&-*##F5|D zpAH?NwWUx2pWtfk^>-};BXF7FtqI2qb zd1q*k!0WnmbB^;S{I(hz{|5G>iS;bjl@SYP&R;Ui=3s$t=%Sj+Znk!2-?HkOMRRH@ z7KF(0QXA^Dym!yeWpfrT3Dqf{3pntHDuv^sthb`_i4j|rAu(^^qJ@=tq?afIVGwI7 zTTn5xYVN{H?f(zkwddFV5AA~FrVQjmC$wD=71=%bAJ%ZvQ8|$_qOb=zBQP)cfy9D} zx~lvto^CT2)Pk`D&4Y-Ot$bGH>iXo#bQ~Y1%(L; zLXWppifhHnBGq6*IoS7})*S46Llyg8JF@Mi8VMl~hb5PSysQR0WmK($@_|;P>b%^28bK@-0fXAI-X#X}a9m#=9=mkeT7>Z-Q#ixb32R zXbs~X7kKG1JUW!9qTwQ4<=t=PO^+osUZg9UI`nW@e=yf|F3oG(7Cd!ER;eoRnpL2i zRRH=sVaaf}HJ(XEtr;2JR1MHSvDnf-d4m3##d?;qv{RbN79|Dtf<+ zOswc`DcTS(%7(v-rmzghVC(Toe_5>0Kw3_gO1$2ghynT-1wr&zLL=$q`CAY|#eQSI zE0iA!S%>KZG>F8BU>H=5+F&(Gjw6joqv|c=1MGf&Eu;T!KpmBszP?6A{~x-VB(cMI z*-Gnh9kmK@I6THzi!m?;CeP)``JUL3y_7cC-NTaC~V`;q=WU)ozyy%j}iTHW&iv-o^LB)jFUroFXI!8Ul`1rzn%*K8p#nM?yTEwRvT#G-J77?V{FQ>S*rS|OWMOX<#S0)_cO^N>E?ctB#Y(aM~@m@GWmalZPA{| z_SL}phL%@?f18LgK9MvB!Q$X?XMpOIq=pMX=J;dS6)g@weri)a77eQ&?_^X|M2ya9 z`;#MBEH587Y`oRs<9G=F-=JBvrXq=Df2LdfA*{1_!GTAkQ}HeGq5Kqli}kuORsT=o zTMVL~zSzs0_zNDsg!n1)FSbOx@T{y}K%IntQQc7G)M+{3DwaE^*tL?+z>2er$Cj?F z@N-kh@2@GhAR@5?k-l4^FBa@A7!e#P$WMYs5lsbe5u8D@I@4nFQJHQ1vd-cA*i^ekiJJ` z#lZ+UDl%VKv3xf{#lZ+!aWDeQM6WoUAg>TvaWF!@L1e|j2w8D30u@ISP;oE<6$c|w zaWDcE2P05%Fai|^BT#WL0u`qcP;oE-ae2P05%1pyT|5bz^OR~(Fx@z|vDD-K4;ih~iTxPE{OB>f`6s|9Zq z{FR{M=t2J7BJUSGB>0UWKc8az6bBxI^+O4o1lPL{=P(kTZRjoeqLM1cwPu6s#0nB6z9b zb%M7GDh?LdRUC{!#lZ+v9E?E4!3b0wD?r7;2vi)5K*hlbR2+;z#lZ+v9E?E4!3gXJ zKRWhbaWDd>imW&oAuA3>pyFTz)=RqLV1%qV7=ar^uQ(VXD-K4W;$Q^6E$NDb5whZ7 z1S$?j;7K_cQATkv0u=`%P;oFKzv5totT-5fih~h)#lZ+!aWDcE2P5=~gAuagU<4`- zM(7m>BV@(F2vi)5&?^o`$clpzs5ls*R~(Fx6$c|waWDcE2P05%Fai|^BT#WLqMYJj zgseCifr^6>dd0yAS#dA|1Gskccw`YFXA8CyeXhuK{APL&(GL>2L~w-YCx|>*@LbVX zi9BEM0>M>+*9fi`yjk#e!G{I63qC=_Is1&D;$lQU{v_#&lM(IxGiB&MAtHPs^0!2! z8~Dv4`iRI!w{7NYBQm|PsqZEFK_ZVNqTE@66GUG@MEQ9lFO~Eaf~!P-rO4L`ZX%*T zjYO1xK=cm@ZWsMCB0nd%hlp~oOZtbRKPdQj(Km_wwV)S$V!41|s$e@J`qe?Oi|F$O zdx^fEU_|tz1nIX(yOokYSFlEKso(`fc| zyGQUX(eD@hSoBdM#`#~Ocj2oI_S;K@K1JjV!L~%$?I74$@N`KZA~;g;EWrsxl$$JA zA^J+eYSAwhTp@U^q;C-1BDhuXb|UQFE%>159}#>;^e+(6pEpGRw&1&>KOpiU!6qW? z{!7r6V##Slj8AjHwt`{7T)_gt9z@vbBRE3vEF#)dPK3Rgf>oklEbHVJ+$=*A5&)BS?UMA%IeY%kbJ zFjufY5#J{Q>sKXbM-Nida&eC>$H z*HN&mV1FWyui!Azj}R;);#zZ_;BvuDg7*o&Ah=KPOTlg#R`~&fwSstzQSHHPvqCgc zA*QRsEJ5XvfOdBfxwBxQU=P7jf@1{f`ojKB6`UbBTktBuwSvDCRL^NBcZQ)% z3eFLvGXl%eQGvKhaJAr7g6jDY={JbHMetU^I|a81J}mfK!KVaY6nsVSkAiOq(g~mK zI4t;2L7Rh^Uo$hkpWqO|h@g7zL^??km~XP6dJctLDe_#w8bPw^F#l@7%LUg8ZWO#x z@Mgig1n(34jo@Q~baz*FP|I>F_F>iHSzjUwM6sQ6-_e@Ns<1)mn=+PAd(vf!(N zT%(ryeS+@`lGcR!!-8K3Dpn`xbv{=E`H4C)U$BQDIRL0v&+Wj7$Y%+T7c3K0&-2JP zN96MaxmGRhEEilQxLWWE!D|H7`vBzMD)KhLhXr>Ez9{&r;2#C~eLd^@LhzX2w}L*T zF+E8zT`(xvL9nx6AHe~F{8pdk=LjwmtQA}#xKi*^!Cwfj6(lDV?T|);xK+^R6uwtv z@&GXXS;1X`zZWDY0Mow~^zl6d;z@!n1#QmY4kFu}!QDmfEjUncsNg8UF@k3cP8B3A z3G16DSR=Sp@FGFd;4t4B!K(zX6Wk<7J_F`^T<|%;mjquI+$Z=~!M_Pc1wRw~mmv9B zY1c0p5NsjXT9Dic%ty*3Vu|2z!LtO(gT(aj;|?b80`pxisNU;9-XQX3!J7nc7ra|= zo8ZHOZ@Sgu5nWD}In z5hP&*<%NP|g`m7zkc1GFHw)e_c()+QAejE7;B!Q@nUoOJzbQ!e2g-*8zaSzXIUuO_ z3X`Xta-h6KP`y8ce1*sjf{lWtYG8i#9t}uV z2Ffo9?jfQbP;L?=0R!cLAgLE97YLGEf$}gx^*#+U{c5QvvjS1QM+1^X zf$}ASR}#^V%_83b)5BNw|?_IvEg% z>U|iHBnXsy3Z5Z2Qji1(OrI`Djswa|1W9v1`3gbu7f@~#B!vNG^}Y*876ZyJ36h?G z@~48I6VYz|?S*=eASnnaw-O|y0ObNfG6hf`CP<% zUF+%0s4s0Gga>2GuR%yd&-h_Y5BG1FQ}`S0mN#F3ajiG zDblrkwc2FdRI}_Ivd$Vm+K;f+S!V&mgNV4i>eRjQdh}&goBfYbxg&2{|PUE@n zv{!;JiBh0rKkzdcvv)b-b{RyqV%V#4DD3EJq&e+PfIU9X(;k``v$qLxy9}aQLl;fE z5%+oaW~W^Th0`AVsnodA9*4*7@9l`QOaTJ7-bJ`CI>8>(w;?$5t?To{IMaQ7aoPJEz_r_UzsKj^Jo8Z0Pvvx~l3>eY(H)U_#-4v?t)xv)yJ8^$g#=HLYyPGoB z>d3#pDQm4~U8slaNXWb)GN~!le;C4~rfgs~FbkLk%m8KpQ-CSJBw!NI2lN3=pxM9G zA#azdhdeD?9dfsvddN&@b;v+)T`~2Le#Ku7eK~JR1iW(ho;x@7NZd zJr7|s;+ui@0Pg|rNQjJ&q#yFF7S9qkxxw=WGfcZ}-0Iz~f%=R`FG-;|EgPDkfNb5;zDUb*9tfUD-)P&uEL~^P{1C`B7~b?XY}))Q7U2`qB=|&x&3%rF}H{=*sAwEApf54lamp zoyW4{Ffw`3`hC5ki976exvoCyYAum*zL%P-mSImm~=8eOQu*Z$#)hpU{#nR}V^ZG@* zVcae)Wh8%Cw}5{y&T#4kP$idslMW~Pj$?W|LQU)dNXFt#h5Ky`*w`hm(Gc< zDeZ`(KPP(o3cX*ys0)3&1@p0@OW&x0xjDGy`O#Z3Pp7x+6E!hs2PO23=3xE~Pq-j@ zDduw373{;|Xyp|z?|uA;o@5^K?I=0qy~jM{xu@iid$W1SL@?%+9CAUg&-3t%JrZ)8 zIQy=QtomZ${d$9TgMagWoUQv0xYte9vr1Z&v@F?FqOCQ-#qafo_B@5}1@|}k-qkLaoZE0rd;{N$A_=Q zIeyCX9zENJW2SfhXeOT>Xk0UO-Y+I~!0u9|IDQA7eD&T-_ucJA5tsWe{PY;t;U~e> zr$s69x?EoM0?c$j%9KZ$>#P>Dm|}WIQ}Vgh8&;op7D~nW@Jo=zSj#dw8K*P;Eq4VO z_=P|j^FpR@88x$giwB`{o7=JXa3L|>sK9-cJ2!bOOYCG~jf#60Ak_oj`+Denruz=V zjVk?oVeGyu>2)amdtuRicRKZ2LIHOCYer%{B3Q23=f2fXTGBup?A*6|&xab+tAX(t z9QQr$_myaBMk$TlYp|%n74F;*w7LUn$)?*p7dk8|K!($1j2rltMe{aS1CsIBi^D!s{y_Mc{RO78J3t7Sc@{=qE?oel3Ko8 z^A;!mRT;{_KrKNmVJ>!LZdQH6O~DXY%<=Z}U507{FCoF($8Q94H7XsFp-%Dix|?4>lOqhtu_(u)Z z<+fVdR@Amu_nzx3Ko6|(o|eWqk12=CTkf%jzzn>?c31d&s#ITq4fD=u!@)AbYjg}M z4JSm9%pf(m%~252^_17pRG)W=Zw15v*C_NZO=X-FO<*&Z*%iSOXI%F~#RvuSfG-;ZR@`O})_i2_@zP$ky-O6(E(iE8Hn?FZ=Ye z{~IOdrj{?6p?QBV6;FzD)0!8(%T77s{W1%yv#=aIV}yDT;U0UGno0kB=v{K@Z>-hd-Opv z&tO-$EU=Lk{Y@s@EGv>sTq@+7oub*(>vYe0A-A#Qq~JTK#0%bgt9(lENy^~8zaMweu5d>1 z0_F$ry_H@N>l|DT9C1vp5zoW{J3by4ig7@CaKPGrHW$@l}a4^ilmXyJJuN)G? zlY>03yx_g(sbqv-bOpIGh8Mi|JV%W1E3P2_bms-{eH1kq;dk7@&u9X?_XQX-BmAyA z_%v;R_x`BLfn^)rCQk+HAaNB$$3ape8;4B%4RM<{AVY@EhZ;^$M^>ur)UugX-E1-g^o-$AerZ z(+l2vYXr^U?d(5z?`1}yMt0n7(tH*_`cL+P_nwZaK`t!g9i*pGps8GhkHyOhiTu4*ky{|_OnmWp&;JvqwqZzz_9Rlw?GrPjR zpuu$T-t%X|70wCr52Rl3-dnvG9(<7Yz-Au7W&rPfzEZ5wgTG@A@ZPfpMtG|pT*e&W zy{8Eye48HRg0o)m-dl?M^k4?&oENo;JvpLkL$rRSOmQHmSU$KoW~sC zy|-$4Mb{F}g?YA0jcE%@W}}qswdB)nIjFTb>;>=rTquGgIi}#fr@%4iAKAR%y;n}W z;pJKauj&+(sn%LTJ$l3wN#vG?z2LpSABtAI>UhC>&x6~F*C8)>?^&x=|C4s1EX~8K zG+WhHz5&uh${#~(-4`k! zc<=dV7G3x9?WTW|p4tgwGyX}XMUwwzGx15p_+zX2cbgfP138HFjQ9WEY|cbi*bLr= zy8W-3&37uU;hFoH;X-nIw}0l8^ua0wKtjkg$tUAV8FT-y{-37KkJyWPzv%xYk`1 z+&~Sr?t5FSw(h%i1+7b6scVJS;*R3-d!FxkPG&%@ZSTGR+xvg@ymIpXem>uQIp@rr zIrEIY#7T5a-_hwu=TT-Mo#k-O#ojyYI!DmS$LD{G-AL?LyDcij0_Mk(Mq|I) z&S1JK*hd*3ME0xguJrMv#mkIu2z{oF@4|lF_=eJ#!*sdWyOFKK=sSqM8tg|I-*Ea& zs~>{>TjLu+-yo(-#>ZXMM>k6T%iQ)YgU!d>u{K{qlK-dy^O?O)M(Z~a)%wK;YM#98 z#MFN?HDCzZ9+XJw+%dt6iW4c#+bdSaR>HeDsG>cPuXn7zt$ew$GP&|$S>R1Ac2DIN zYn)*|Hel{~L(KLa6L=1(U~IG*c+oZ9F@aZLFbm1^n@NS>ej7hFfYcb_raABHbtACG`BHu zrE9ddF>s@6tZie!oI0&}M2g?kvZRdxzO6y+1b^8JGK_267-)3;Uawutb*dB4*7Zeuo`nw6=|b zuU-FO^l2n^i186cCOCuOI6GFu+O}5^U?*axUXw=neEd;GwE<-^jM`7d4wc=?HU^$? zjpc0&@Ld36YK>m$JlAMwW8gy9Xl`TRIoD`yV<6tN9Gblh^foP@O|XL~Ye^derN+OA zaC>^3+tZI-f3&BI+0!xDq2NZiJ#AjwKCft{*(fE+Z8LUuDrjBKu`uB)&@7*|aUMzK zQ-sS%wuF9?E0{aS=i1kYIsOsoS{T%Vi8im<^Fg z=~ad-tfvG!j!j|`c8r$2e?NKO%ACPOhHbXqyivi2UliqRqj4g36h*iLjH04TcupgV zKi||glh|x(TeZH80WNQxn}}Pn2OtMNq)Quvcbb?5#NF5(t95-F1AOihT_AYuF-Kv3 z`(a2GTDQ|o#crGb2=GKQi4JQv!MhF+6(-)n4uxaeoGd$`OlZw+SRWkGrHw`x>`+c5 z`ozY0BaK2(oY^qTrczeP@DDAIR}hKmoy!-Xeca_Smt5+Gk6a1ftT3r%GdE`0%=M~1 zaA}|)KU%NKnG;jaoF6L(-9$f7`49HsJ-2nUdB~~M*)gTg{;^WIaEA*y7e%oP;7T zck>jJ%0Dh9fAN0#F%b{L@rIj!EUyUWVRdWcSW@|mWAcyPFFzLE<8bscUD-H>7m=IY z`p1yUKQ<=+m}q_^FxN5n`dRIkF@v*kyIaN#Qe})G?{)n%$@|^#jF_@#M9Yqg!#cyZ z9s65u$ul{pDs3jI5+;+nY|M-)jW?zD+xYd8Z{4ycl9Nme8kdl>-0+wspjU2tW^;N+ z=2-erfO;Q9l-A=k@*M1#^`l6x2p_KLBtN2nzm()m!@r#DWWpO4k(@#JYsn*B|3dOY z*WW;1?)oQ?9Brg;CWEFA8;>A4R`9oyI`Ss*D!;+_H%=$rejc~h>t_}MCZ-X>Ow^fnP{*V{z6U2hXh#nan_TY8&VGX}X&&HxEPQ)*7kG2%=h2a!GOY+Sb>zlds}pW2su;-;*s#+;nu3j=8bU||KP;mnhQ zseb+VY@8^!__Fy*8S17^5_-u{dLZ36@K(id=bL|S5}Y4sbvr=eG&Pt*71L^Vr3*^a zd4z;}2_#vAPT%}MdJrezet~dbC?vP$!V;^p5{J~g_e zY*2)~?-ecC_~0sVU92|;R}##N^YHNtbT$n+k$gOz9+fKnySk%gYbu)S>z3k@SKeF& z;kcnAarvuRwz9moY-vliwVy^Fo*<}hsyP&hDo3QMc&8&?b|9XECM#Mx!TT$YZXJ)?9+WBt)p70pehhmRX) zF2VIJ5CN@jsBfYeX!T0eS5aTTq6XC$*DRv|q0ui~Q(1ltR0!GpaV?GXO8&D2NrntI zLZXm4TwdSO7<=`nqGEjul2_N(m+OBtbzKegS!?PVS{kd$8k!revXyvjzZylCudL(< zxmDmvBBPvW{_Q_f;CuS2tCm8&!2xjmxT5RvhE@v#F}W4g3R|qU9A8LoNIp#(%^4Z-m*HEaa_!Jp~~|UsM#` zPfQe}fkTcbBdFq+H&X={BeoQSQCq(h=cm}?ll2}`Wu`($Q%zMB1{6&!uZ+ct+E=%W8})%t`(*Q`<-O9n4)K{WmV1Sc@;<3Dl4x<%gdUW14Gcl<)Xf} z&r?~G8^LcI)vqY4EoWtQOJmoe84={IURmCVb2x{$sxsTH`9HFuRX75gs`_Ow!Vfa! zjm%q$6Mn_=?8d6qH9Qcq2M-@nFkRX!w4F*{d{Sj` zaB;9KSQxCN@`){!hd>!Mv*jV=m%%UFm25YR1 zx4|)+gPSSIF*a|m@cS*-w%=oM<9VCk-P!}j{CCtQ<#&?I7-63G*CsW06%LRk#R&i# zZvq%?9ufo6L1bC9JCk@=CYQt)o(9U#>0~^<9%MLLoGQ){7mCZom12u{l6abEZYrbP zD`a0I{#LwCd{TT#{Hyq-*aHK>_T`I*iIc=7;?d%2(P+;g-!|E|h`Ag0isomq;a?-$XuZI`K=zg5ZQ{e?yW%IJ56hYLbr7?~=^}3` zGJb`4f_SI+nE0;vspw#tGhausr&u7?ipPn3YMAMH+>rbZ0Qso+g7}VTenTAbd03-N zXS6{;^F;yhDEavyKjV)V&lWEeZxZhjpB7&i|0;eX8ZA_qc zdy+UqoF^J>1*EHx-6)qWFm=rGG%9pJ>}1n zT__HhAD1eVzeJoY|9sg-s}$iS^4H4WAhyVVg6vbo3&cyr>%^PHUy*1pe>{=xe^7i( z{^w=CB)%u^68}ab|32B@iAJLo{uI10V7X~xXA=Hg+5N z7yF$c8Vv{7J!B6Ohlu0E!^QdHA`zDtv;J^8Gek9pDPpE*KD5C)&6V9x?=m#d@(x+$LTr-XPv0@}pDMbGP`2_ zmHt=ao8sHzF7ZQ=&$qI@--`V7gf<^sB~wH`l}@{>*hB0qn%4=4A13=?u~;k-57d-1 zA3h@AV#Qa9Kc*?SUh$r`+!op9!%CEMmF(-p12yFMm@@mp-$^Fl6yFxjLlE$PDEkX> zpXlf73dDy*KH^L}PaG1T-Z#YN&$v0AJXSBb}p>qI_I&GK#$&Fdl9 zcguc6{Jr>`_@elx__p{LagX?==xN0T`ML+?$BP}rbg{eGOYA4+iNnQF;#hHlI7OTx z&KDPnYsC%XS>i_VV)0V(O3}QYL%VO4?PwU=CKikQP9)P$7fZz@ z;xciC*eb3S`G`OBw~051w}|}e731#``JF1-kBQHU&x@~${LUZKy)W(-KM}tW`E3HG z%MkhH6xs)ggTx`?A)lOR z_^kN6_^SA(=xN98md&p_u)K)qX~lJuZC>XizMt$u(Y)@5|4`XuMSfF)<(b$2;40bX zeE{s^WuG9PE}ku3AYLN=T)av&zgd8Co|OHPXx=x#|F-P+#lMN4i2KCv#5lfhKtA(Z z2Vkn~43S^xVEi!gP;sni-j^VLs%(DQgXzuJt-w{XTg2nV6GVQ~is{c5`Na_0*NMLr zeda?`hW^_s&enYco164!|9Me~~wDECa+=ZY7JTg6|9*NC@>zZUNj?-R}Y zFO>VF?B_-EJ`DahWxp-%7R~!H#D5{%yf1_8@O=pwCnk%jVpp+;h|{F`%^>gn1x%A4 zms7(+z0OLbjYQu2kN<+!7j6vxpO^Wvx?()=65ZV21oqQ9qK#oQTTlFFI=pN%+fdO1 z~i+uJyA+={V#Wz**CoMm{A>1|#dg)wkSvBoH(2sd8&Rbt+s zWw9)e?V5(&%Y&e`6*sffy-vo&Er|&uXx)m1GYD(V+q^PL;fSrb7B_kukdF1TKCfQB zANBGeXuX+jS@>(;ytozc#FqD33EnHg$MSHhXfN+XguOfnTHj^6=@{nb#qldBvE}_G zraX4XYaj0?dwCGFl6&IbE<2#ji`xi0w!E)V9+Rpd0v@)^&dNQERE03QW#HLF_`(E%8fnK^n zgGUY-k{#WCO6O~E!H9wall-T3zOts83IlF`qdH%0w~jyUl;uh1*{#3c_tEEmqwtlo zG3&xH%e!t4>^{l4Jrug2%f`;ci4(Au-~gq#v*kKC%MrAIePJ7`Y&M6F!XD z6L;eDJyr;N_~{RPr$7Bc@br|zl!Djy&bZ$?Z+ywrl9H0?CD0X0g04`4e`D$1P*(Un z>ypwB{5dnBMdZKa!F|@U#R$EQ-1qPEO`sP>FW#Ft(7O2P5B%`@wmi7c zLCVB|GoWKsy4Qae>@CQ#<@FEzTNc6p5K5)b+8W+68wzHj5?H7wROH`?HX@yG%R{Jb z20Y-F4$vc;RD$}DJB0e}E!HK_UP^r2w9XGtXo4TL2e)h~nE@rV^GY7t7gCMP<3}l> zE%93uKT1ht|1X_jotK1OyR{{t?$`QZr9Y#;LFjb z>-1fxg$^HIGM>lEog30F!3^TYp_TJd$*oZ0N|`caZ%QdvOzp$_0$9C?2q#Xt9WkNW zNA~%1QVM78O+y-g>7)CSa?YAyAvaV0X$R&iC%83y@iRCY!n+;+T~NtO+K$=CS%{M7 z?Deleu0{62kL(NPd|^_TaIWl>tq&%5Z7tq4);DRde?Zdilal;fw@g_7>6%-f#t3!Y zTGl;f>%F1p_lE8tv^{ibP6<|@FJ;JPjL)SLdX@w~`mO+@)YIx|_vHxL7$K|QtnE{F z`R$2u({|vPO`83I-=2*%lJt?Cbo+#2SjDiY0Y)vbzwHQZ9c~X9AKG-=_>4VHTx5G_ zi#@ufcznzB* zOCmo2JU8Y7;02*4R)y=OGas*Bd;>Cz;D=n+2ef>Fn~}-cifaY5#pW@_7sneGPC3I< zGiwNc;2x$jH&Ui|UTa)&R0VU)?>5?&wI;2bH*65G$ej9YjTr(6gZ)FCjxn^SILKF;LGS~EU z$@-ass7rPaqT_#wf4tjm`i8pCMTyiUdxmwt!~zZuy9HR0BATOQ`Xjw*9wIXoDPj+b zWF|(IqVv!tQ{|DqZ0TV#(;~akMd*^bv6+$gSkxGqS&{L~J62|Pj4oLg>WCbLS%oec z!yI+q`-3hSO`}W3-(i3*89Qcl$=;(qQ})Ra7P<^E1CiQv8MU*2>cP2tnN9 zjtsMO%4$HD%x$PY@*>+^9ya%{bJ}&uI9SppW5My~;2(F@5b$q?0bQ~*G=;ik55kPR zfq&2?W0)0P&StLhD#G+|)uo(+>Zwb12s$ZUGG&l1nHnZtGS_O?B^!q#s7uzF@w<1voOWF@Z!TVC7auaCL|wAuXg<=-{7MCM$@m3a=#t^dXyol3=?FrXtiLh) zMovMI&?TE-%ywNex1x4kGPeWmx@2y>MUj3i>iG_nP2MpPqjvO%4vUQ0u1n??H9oR| zlm3d1yeW~pIZLnNyCH1Vj0k@k1-fKM0@NkjO!KY8^Gxi5NF#gnP7;q`>XN;|fqz$v zjk;uP5VNM6e_So;ZTv?+=A{Zz$&Bi>3OQX}GLB9L-&9eT%{nRCUgbjr*nHyh_F_$)U$r5>U z2fAcuu|DXMx$z@2dT^?sOV-`Q7iFZfJm`|Sr;;%lOK3xv%uPQ&BaQi?OXkKOk-@Ju zQ{WgV`nMlC@%J9O{yN!!n>tR%}ujT{0dD?j(JO)G?D}Og0XabR*gn z@b5%|G$TL61sapIBci?eOhA-d9+z!25%Tk`y*c}H6`F$?rw<;ND?A&myPCrYU9!i~ znar-J(dd%#j&-{(nYn!pA*Ek)grH02j-Wqd4f_vWGOY;I$c_j6EIyMu@!0$`Jqd8p(!t_OJ;7? zL!Yic(?gfcJ>ZsS9M1I6C3EelE}3h$W~^p?&?T!z{XC<$>yoWD4(O8kSORp(*aD+V zb^-#_C1Vjrmy91!QkTqi#ORW_4(O8cBS7ksxen-(QR<1hWUd3cWDA)Bx@2xG)FrzL z#j{mrOrc9gn~gFybjfI+>e-$y8SiOl%tQ=z$;=IIjCnR@n7U-<#x`}ycv7Tcih?c~ zCx-`;Y*&};b2z&4tV3NgPHxxf94qLOu~xVKAdVE13A$wbdN6d!=)yCc_-|G>7Fb7w zA%BOc zLzCbt!QPt+6ZWAUSp2E5kEZVh4$EO3SOt&cV(h*7gJbsSj?W^V&nxiRgP*B{vFn z|3^UV|B8SZB+Wvu!kH^+)+^s0ooF<|627M>M)fczM$E)iPd!YEVzItlDT>AV`bbeM z)^|{BIxHG)So=8H9dC%kjp5$pUl0Mcux&O2d$2Qt`b_z=61cw%5Y4tbNF z0lv|JzReW?_mH*98q#}>)vJxx_1NP*PmaHB8oG8Qc4UZ05BWA5LBi-=TC<4$*iBvS z4M!?$Fi|?-@xo@Fl# z_Q!`?wIoH2Z0ksZt#+(q*TyveNKO*F(4LolGld6Pz=@^@%;ZEhhee zpr_*Hy4iDVF#2LI#*Wz`SPi7iwyh85gc$CG4q#R`tY_!1zz!8ELbJ7DJp+7|YFmqm zG}FO_ggYgR2?|k}QYen}jAt4s%0`$-8gE4%p*9-3qK?EiZ-7i;(ZN~FF&bsY zX%1109okXNZ469ujn*~>X1T`NHU`Y=3~M&wF8ij214ghvhF}(U92`W<==d3CE==ta z2)1wS$BK@V*n!VSs^Qon_eAJ;*&KVkY+fHdUgpOf7n{vUyT`@6{f~>)-#aeg+3&cR zSB*jBBtRF+n*s#A34qR2bnszB2OdUZ8^_r_sOCk-xzy`0A~6Qou$;`9!7MBKUV-yd zMp!e6B#exiw*n-ehTRwpR2rjYZ5sopVs}@>(5yBZ+e|E$$ZgT3#`V?5^k)uHfZeg6 ziN=7t?&ff*gwQzDPOuZE!rlnDhty&;%51jd`29Qqpy@g;WUJ;kb%2hKM#(VvBTfo#=tJuXl-NQFRrn+je)(cQQO8|_Q#IZ zN4UL&#vKDiuHWl|KM=rraW_FhS!|8%>PZx80 zp);IEALfu8>4sZPSMZP1Wq10cAy8u@*nGHa*><)MsiRF> z71Oj;F-@Dt_He|};xrJWX7lWoX-)trk%27i zsL5-kq!Vp(pC2(e4KRvl1O7L!uuRx`4Q|dRj)5t`!MWzh=j_E>=iRn`v(Kmx(q3(v zJd1G8290(bXN&hayu9Ab#97C=vW1+Uf!J{xA>8AAl`C85p1tSs?EMt>fVGC2gbY51 z9j|wYm$5t68rxh+ce;M!E$qwzO+p5DVW%dcH|1V~INklRdv^3}KaW>c^Df<*Nt9y8 znQVO<1Dtj=*&9rEpxp6ueY{jYgOR}b_eyiE<0I!7eu8sr{0!`I{RCe*89xKxVn?H9 z1kq)N`(PCDl8E5z4=>8=kICmXCy1_MGv^FmkvMyJbyol{CkkoLTF(H_V7MlFmmr++ z*P6=@k2(0gvSV~b@pkrrvOi}<)(nExpzMw7V=CHcDq3y|Tuiu2V_j@Ti=!3IKrz~w z1qEXB79fU?CD)q5jwIZ|@Pd*79$6S64k`x_!DzYd%RUecIv76F3Ga03v(`07&!_9m z`P6(9!dkbMWTi-BPN*C!oLtv>Cx4!QO(XG-rw6n7vDh#Y$cfziNfaNhfaJAqxRtyf zJ9I<2C$E_vZvX3)mb9jAttxmdSAKP9wTxdG~bMsbM>=~0w;YibyIh*`*H~Bfd zEInwsHp5(jp3U$&>{vc~)-k{;y-SBTjjZwW>)0ON+cpLR zJF$D02!`J=_QFm6BRBaOW`j*)22S)02F}3lb%S9pLzB{5h{pJPec-9dhdkbf0X@!r%GiqS9l7#UR{f_i;A4btw}}{Y}@)tfuvw4 ze^MasMVxD?iB*6PbiuShCu7=yG;$Kuvl5E};i5oC{GZels$S4d3p=Z`d-Z^-6x6LK z3y7WiR+O27<`&e(AT-rjG;u-pA$brnbJCirg4dH`Xe%J-*9SZ{zo5IPZ#IaD20>hq zMM3DyX|k6&k?K6BIonCf&l@xlrKMAwtS*1@;U=j`%apA)Wc!>ZbR+1*LuV{T6>X5y zXtH~?9MOx)W<8Z;YI|kPECMkL6*HN1^TK-)t$g%)?4+VeY{O`l;>xVuyFPzX5$0pa ziTT+ai`0C#?{UFR$VFkYcxR1Cu8u(fEH2n$N*pw3AT{40nTLCl*=7LfN4zKbR)}$Q zR-$f{oKY0$7VH#A92w{~I*{0n<7@;TyJZI;0ZC=WZo$+*avmmT!}=nKj%~2nBD(FK zd4u5o7Lstu&WXltw959avy0H}93(p|5QkYu<pxJ2v)|Fn*h;DROK`+fQF>TpI_2vxYNG6Jt}#_0-$M(_CnygWb*Qjx1o)xeViiYuvIpg=^aN?abIVbGFFo*|zp{+dRb@sm=)a^FSJp1c_HUyc=Lt5oUq0HEn{XZR zgx;*EA`^wCjF#N~`f;uT*uRx(9L9S1P*1Uo>T#=v5An=@Kts+*-Wlbu{q*AgqX5?o z@vQ%T1vsv-k({0%Q-b^6LN)92|EN4%8P5b}bsFu&%K8>a>RDw|rjMIkHpd)ou0rCP z#u^MagdmHfT63&k1f4p9fIwV+cvD!cFD)8=N+sjtVoB?y~lkHtHt33|tr4Mo$6s-~v;#-{9% zdHcP2>X&WaCz*Ftg@X%+WcO|S2bJgW1jK&2b9}hk+xS-Y2X*JhCT+8wCWy#UAQlHY?PJCm5K zToQ=}%8##)nfTFSi8xtYDDq=9mQyRP68S^{{U?j(i>vGS+MKR=`7KPZAf3%SAq0#q?K-e59DR z`8EZ}J65!lMWa&!o1Zw+KUp*%9Ko)U-74NDJ|zB0`IF0Jt~gAbAo9^?##f0g;wj>V;x!^4d1dqMgmfq0|;0A42l zP2xS`Gvb@#9?{0bb*!hOm?I7qCy3{XKNrnUOCz7rNdV*UY#Ym&EiM(C#AC(v;`!pm z;^pF%;tk^O#HYk>#0bt&tgoAxFOC%_l2`*%#hE19UMVgY>qwN-DtoPXg8XO6-Y6QK zH>BSt`%2O1y}^H*>^sGKNcbO@{gk*v{?}yh6!(aqibhWW?KXM>U?-fD*^e%w(RG8J zCwnl7`VN&nRxFX9PdGCFT(Lr2Cf1V3zee_P;s*K8lzpzaS^gVj-y+^8J|sRbz9haU z?h?NgzY!DB2DURrOee8t%kC}qlYgk}k>a89A0c~+h%?-N`UTliqE z?0%xT4#Gc7_9StdI9D{+L!>)Z_8H=N;sxU6;uYcz;w|Fs;_t)<#7D$u#OFjl)6Dk2 zDZVG}68DNEHcx1I&KxRJsr1Z*{$L!;^`tk zsbT&t;x*z8;;+R!L~|WR`Uhp3>oIJ8hmYmFD83@TFYXr2rG z+$);bW2o1`&i?bc8PdEy12bfI6?=(&L{G=9P&OYGVgAF!W#S64S!@+g5Y6j6gwK(E zzIcgvnds@bT`$|yaWk(6;q!Fd9#s63;moxP7X4qc4oG&DVLL zr`uK_`w(%oI7yr)E)@9{Q|33XFTonw&7!BK{LhKzTbM}C?<}%?{Q3qN6eD5>v9s7sG`h)1-&Z!j;Kuwz#RK)+4wrwjI9r@A zE*6)HM~f>(qqmImFPD9@_$%>V@j>w!(Y)S9zE@{!!d1z9ars{7Bp@el42!Eoff?-&cVA9vj(7>>=ie{3aXY^TmTjPuFdNY){v1 zuIz*AlpUE+u0 zSK_x~fbT<4eppNwJBvnF8}a-y6VsXZU*H7U)5KZgLh&fET0B}@B^sS=l*2D>vD^#A z%fz3H*NZoccZi(n6`vJ7owrwHzajEVVXW^P(dcW#4)J{nc%YtJmi*b`LE-?> zydOip;j+#9FWBb&7kHHX{O^d`;Xbejxr;{8Icz(PO@vqi78^5*iGyy z_80TTQQ~3Z;o@X*zPL!N6qk$5Vyk$vc$$cpA?7uR_kJ9vX+K`B8k+m7=uaAL^vQd_ z{;%sH#@;ypzb}mFeLlc(rGBf96x`FEw4AqWB=Gb9A53^U57BsE5Od}ivc(XVm`c$aolecy>xw`C%D>6q&TK~ zKw&THQluO28K7U`d%)QC4UFk8rnWl!r>3Z=1<&Q8j8Olcwxf% zkgD6-(`Qi+0{EN=~ZIo*h8SXHW@l%lP@pc`?7DVy`^hwU{jqH-aRfUZfpPX z_WAvc4&28Zpxt&^R!NtV%#u%`WthMGrM=dzukE$AJ-P4E>?ig;I&>vGet7)bLc>BM z5R>9-jlsSNBl4Twz2^E?Jroti>+Sa-2s1U$;6WFd#(EqU!Jr)RPgA&r*ft(4;4PT@3EY-ia*{Fytwc9 z;KuliQ}D9{q3yxT3(>;iU-}k3yzh}5d*l~8e3v|z5QehdxZ;GZ>~nbc*l?E(@mm*n z_iep3)V4fldl*W8RQ)?|LR9UqxVyhUl+B&H7r*sq--Nw8?ziH`pD@1D9w(T%{kLCQ1&3^~4~s*{S8&`0J3s5b-+t*YxNAeQ zQLW1?d7{Lf<^C8|-y!&t!6>vjA!jdsqo)7f9qj#v9qjYw_eYgXF0o6pmZvQ#T|Q?C zRp>%c%M1BF+wsWz)_s3V^NwG?eJ2j&M4rI@iha3vr0Kx(`Qug~2st`R);ss%qTwHq zInKC3Wpw=l$GU$+<~+K5fpJLSe2qf<2Y0S9t~knAIHw`(pPIRrE`MM?Q`N!mpWgXg zB!;`A z@IddhqZsDz0R#r7@_dG;b`dT}JBi`pC^axL^+JY!#`HyLJT*hNj(6^yPWTt>)ww@& zKs*q}3>0KLJ#ngz8<@miI0NC1Yc%1w0>p-(Th|W}A%EP}&hdy0$D@I9*CtM5cmqm| zyDpV}E1tu5HbMzZPu;q>Uxa@HJMuI9i@PfBZn!Bu#!s>1t`97N*XY(g#sY6}nAO4e z>>$9@wL8Mpt$TrK?9h`qi6%4b@RQ_lCo{S!bKuAf4+_mjd65|p2@6d@)UEp~qT~OBe>HHKzTqP9 z1&Zh$9ueYK&LW55U-;m#*S`x`-YA*=$Qqi5$P7icqc7ninW&r{I#gy#WFwn)n9Q^Y zKR5}GmYEsh=MLd9GP5H5USD{u%xtS;HU>CkhbM)2pFP4KWe87>H}~8z>bwUTo)V_% zM*~Eq-Y*=_{cMg_x>sWC7z4*snH3a+*!+>tx8C-Yame9vAjj&&M zbq9u7Q5u`M#;XX^GY(~^{0;Rj5C0~_8_CqI3*X*R8K_$qzQbDy)U6BODJv8?f$jQj z*c{~0t-Fll`8%1eZe94U4v(6eQzCp(7rtA0Gb0DHiw~Jm@`XXVn2$w=TS0^%h0iSk&_! zjx%}3M0jg8{D%%_8q?LS3%{hI#z+3lX1t=jQzHDG!tkr{!_jo=)*Z{(H#(jHP`B=D znr|gOU}6_UwzEg?B=HEQZrvPK^sW{gb?Z3S%$jcgakZrLbGCH)F)tS&Dw$E8_$wfN z{oy6P5JxA25BG$jTc^V%V+02Sx^;gwUGQg6=Mi?AYlkw)iY) z8T@8c7`kUPAbK{T5SkC;=t(#-=Psw>4z=+;p{G7Q~1+oWHR!Q(0n-8vphMz@aNeh)*pj>m}6t>ed6Vd&OXBZtwgyOu>l zx9(bW)uC=(J5eBdNxk#ahxXT*0Fb)=b;0M;T${kK2l_ub4jk< zfd-E8jDGAMbnDy^^k?v6xG;3v<#7-Exb>HJc%~%vaL&!JjXGX@6C^vkXugfR! z`=DFLGhrCIb?yPTJmVhL2i-c?Zpg@I`ZGPdHRBD|2i>|0Q9sY<8D&gxwlC#sY)w;qyEPbnDJxFQ8lJrhsnUP0Rw_ zI@bZ+I(~>4hHjl(%Tv&;djZ9>Rc1_~TSuFXGB$MUXy5MH)U69&;*0we92xwUZy36D zG&trLa?GGxXKv6_w~l9Z8m1`d*7ZY=cp%B{vM0RG=kQF>m1mtWbn7^|UGLynLAQ>z zy7g0r&SZja-SMaex^;AA**p!H)r|#48OVU22YQyxgU>q_YK{L${Ez1vJP`p?7WCyV zXAhuT$1@*v>&DWAZXK`dwhi67bK$`2u`bBg{US6mU>C4SC;Eb~pp+h4kZyhU1`Mf{ z&3BJ>b`qD9)$I(j4TEp`|!k>2Mi%%_Z^IY zpYZ|z=lI__(KkDiz}x8%vGdK17~MM#G{?m^FOp`S5XtdnRHA*p`H_xYkrXe|GR!ZE zEr@h9claq{SHuhpBY~bskjw&m*?fw@J}iiq;YkaGx!HcaB&Ueo=za`Mf~y33Z))t= zV>+<-4X}@ACdrlNEl-(x(Cq znPrBAADY~c{h%Wde-ZA^2C^?(;9F%7Sf$aZ=3&o_Q^gju{Z8V4LlMtNr||$ zV9#R`M&>Vrw=X<>uwx9FoqoUhe=kDzy2J`EJ0FcZgxQ&dktX|mc=(}=veWN3u@53- zuTQ+f%g!g{j%IcyVWi1^Dm*8<*;`OM{eJWRQD#3eiTB?JUV)gcNOTGIffvB|4Fdec zX5eWsoo&R354vElE&lar74iVkor2yV1ay$?h6_$ke|)) zIl4S%W;PXA!11AtWroc@HSstW#-YtY@}AfW8DToc2k8#Mj@w_%_96m)bJyKIJ@Hpw zHhzjTgV{2@Y_+iX*^RQjjDTZq9@=Lle&A(00SVSK8&8m?wym%(G1*M7Uo+YGeh-NibTf9->n9L+oCbUSCIYWx&-1dy4kL?kOkwY^z;lw$^a}hGSw3bN9L6Nf zRw8GN1?C{o6MG&rGh1wdKAf6xn#6ye742)2Uh@hZi7dle1`C{p06!8k1ujFN3VWWH zEw(@wSa^dALZJiC&8=$Fd9-cp(CtX|RPiAaEV_JZ5G#uRzWiMW1c+|8a(1 zPON2toa{%DhQy?N<|j;br{{3Am&S8DX*|V^Sm7l?^Wv zknLia_8W<>c-eX*K`-ouj4;{wIZ~0yHlPJfdIs4X^Zz-7>^~(9z)fD$``Jh|6T9hs z9Re$8u=gh-umO7>Gc#Lk?`b>6%O?ZvcM^|gf$aT7$Z`R*F$p70dwvPeE!cI~(eId8 zK2T`CpLCbko=1`BVeFdV`gSkdj_+EpTlQ@Y2AOw<;h`wMdk`&>( z5T~>ODwCpR8FoT~D^zO33`68J$WezlOM0oSR>2rCaqQDADzfS>+VNC4ol!rqNU2;qc8Gj z;ewHE0_ZiaoBxXvu?hCvAlu(}f34VlvE7jrZU0ywPITSu!qi#zoyCC;P_|!?urOi1 z8DV@Sr_fWc%}c;4?1;sfKQ!tb#4yhH?fK^hqqz&&Aj=xu9;w0uZs9}P{U(#VL%-+6 zah{LScgOvp#B9^D;nLF8+>Jng+O>IcY{zDpnCfOZSdzTTGAhGcnwn0$#EC7Vh)W;G zAUC|s#oIGiX_p5l!o5jK96?ZbrwN?H^9dqIzB4irNVMOU4GRikgqsH1vIuL#5^^^_ zn;x@mKo|;ZgE9J3csj6V5;IJ27I7qYsN1e(Ad#{2>D6Jc@$9tX} zUmM>rZNrW-37!-o?6$6rfva6V!S`0iAJZzoKg_oz*dWj725>Dx02*lon+qk+Td5V< zMkDGN>^h3!#Apy~cza?Rm2Mo-5tTz`bqbkg8q(xz<1n-F?U`u&4m(qNt?}5~v}!iN zVLwnTH%6n?Mt$b1k?uuxA)oSJiQTpq60O)B>lj}f0~=h!-^Rdct`Rg1yB`K}5D%K* zY~mU05H<9-F~D}jND#U$EdbmRoJYKa#z4gC&h_UYG5cl=H!04^4EW&1i%)k$(6pZe zJ>JcG<$7;0k@w2=-lA}q031PgS=@@$iDp?C9~MS;6zq<{{OB0WkB-5b*fCfWI|gfl zZEUMM2J;DiWdVzVcn&*Os=ti^cMN8+AKaJ=;LaFDJ1`3HK%0Dt{XT zAG?0yE9_>GGGI!xX5NfK*&39>lFeo+fe+O%gIg(V<8h*IIIX#Sf5`Vcj@5$N5ZHqq zQpp5gx+6&N1viqcYh!=|55G6;2zos+v&X)em*Lh7!hN~hfHeVQr^!0w9pFRkCOrdu z(Pvxpyw`q?wR&9}`^c}d!0+{OzturaOZLel->YsntzX2~gKkF_eU9L_*u&Pb>o)tw z^d8fvjb;)GhHI@{9P~f9b#chqK2*z=aoEE+Unn6>HVQ5;FG@2T+u^<|{sRa>LcTe3 zTXE!92(rpJYprG40NZR76lON}KWF19?5LY_vC9pz3!H>7CP2-g>2{&TYX-;KZFec# z&7llq7?pvh+wRp~29#C9FHK$EKvscl)Na8JqkJ?~Jh-=CFJ5ChWBa>4OM!?7aAMu!y!` zkF5jQ&BpcRjm?j@<_V+9s*EGC3pxxDb?S`04s%`;Nr*HB;14g*w};m$Rp95O6*ADwIt@m;ztA`u~ghs zOKbxcvjGp9(n|^Vz6Nx+qlZB$8^A*W;>d*CfOWAASR8G@;%EaFBeB`=R)F=JyDUc| zgiGNJk{3-1zIs{c=bZAyNWYt#M}(WV1jKoZ;3*o(c^fdgnTrlhPQK|g`;EW$%~y@! z2J9$iJR+u;__>4|oK4KbZd865VApU#YzEFZ!MVIx@qi0iEx0sMZa0J0=FBLpV|2xSoMg*zp49#`VF%tTq~B zuwxJij)zIe0G|y2m6uyx)T zX&2Mvy2If>B(gAT&H6S5cpSpd8MzI+R|>;-o2Xelv+eStFewawWuj&fUt@QyhV^X> za82U1pVtYmw434Pn0q$E9Q+vFUA)sXD|{4)F(Ejx5&iqh^6mR4r#>6_?k1WS#{ukXU z_iv%i7pjbjX<_vKt(gtHl!#Wzq_3Fd(X)dcb+%XOzGmcU?7%WC`*V01gUg3kaIBMO zC$nLOd~6%RPyzU|n(^Ni<@_3>QbZM?3fVef>!3wB-@xO*FY zy??;(9XU@Rjz@sE(eL@VpxZZe#)sXHJ%l|TdlGhDXt;ZuH}I2O234yc*M>%9j3%_ypiAq@ zE0))+{2x(;E^Rud>A$Ep{lBGW{R8@7g~MD0Ybu99(|URSavp*ebxqK&gXA_$ymTt7 ztg0?=sckMZ`gri+_@q=FQ~+V%Ll{aXx}o+Y@FE2=!XJbPL{*iSSk+)r;W-&AU>2J5 zpap5$R7ll!2y}B2@&jF*)%noB9b`1BJ3G+3wVm30NL#0wP>~xNOA+1NY|2R|LEzX~ zMX_rLChsR|ZKRW(jP%qr6z^1{9;Zt-gnv61Wjj5popPfpeDngSSrs#)hl%{qP(WOC!F((A061nKIiPHtmSAViVeW3qb$!b6yf;>|gJUm(kQ z#RnDO^t7H3%JoxL*!lVKwuyMjjTqD(afKpYJTT%aL^y#S&htqqDy>uc5U;3htK5j^ z4vhE(B3Svesyx^sKR-K|?&Z5tH9h4x$473Cp6xSyhH`v(V2+QQo3+`UkPg|9yS4+Fn1d|-hbVR?T>H&OvQc~wI9+g@ zrwt5*a|0<|aoG1Vs@NRA(D`Ql-k}cT7zuO@I-SwWPHCxTQDRYDp<%h*O%==!rtX(; zvX}6xbyx(H-5zZ!;E^9AVx2=hZB}}qFY4kN&Y_@o5vK6*b?tMC13urZ@0Tr%Q;Zfm zrN&(u?R-}}8#A8`Y5fN+oV0RLT0w08cyfsLucz1S1NzsKO87X3gq>~cva^vNV(Sms z`LS73gZW5+p+S!+L4K@_7b3P@RyKR;l(AFBTmOOp_xH3Vqw>{-!=P$9bR@0`HOp3( z*OpPU6ym5bsw$0cZdvWpY9p%ZN~1#eyInxmmFIR}8O*M4X{@LkR8mvhT-8{!a#=~s z%8KTi`jt(CzE}AwbK!zIa#J%@da0gW4r$f8rH!>!D{*O}Z``QTxlL7#O{EpJ<#pwa z1%;)MO| z_4O-iP|vd3`laY$O>zM@MT~p}r20+Nx#?&rYPDZ&~G<^2X}C!P$A! zhh*nfudL5&YHqBlK(5-F@+K@?IIFdG^Pq=r)-ZgP<;~@>c6CEuMg7X=#`22hLoxVP zS;Md3?`eTIwbT`u|0`jpbIW5)khG4Po<@9nP$ZbZammv0j$mFGdc zgvQ*XevJB3GvLu9>X@o>oJG8msi~^MAfPMdwbA3)m7PYScJ20mS>L<1v1(aa3yPXG zVYWMk`<*}B)d#t2voh9TE-=XW{~xvQ|DUUUyAMHphYcTnu1&&2!~?ze{~&J%{Gi_V z5lKs&Lu@1WJ$48ZmRI4-Y1#ew=5EAgi7ud5ey=r}b^LNnwwWf1Eg7tP)p= z7l~Jkw~G&oFN<%9ABy|LOw14KKS&%d9xbjBPZci^uM~eR@>U+p*&*%}|0aGXMzFM* zE=wFJ7KulRMspMCj+K47c(M4H_y_TA@k^0k9AQ19#iK-{VF|y{tOU=H{}S<9@g4CK zu>)=cvAk??kZ80b;Wtn4g8W%grn^wQN;Dde@INB^1@T?+GckaL&;03Pt~gAbAoBS{ zrmGTL#8boz#H+;Lh>wadiGLQq6fecyES7tnc!&6y_>%ak$YYf0JBq!;sp3&$op`)> zws@I%lX#E#wD`LCSMghs-xy-O*{TkvJ%_>l=zysQ+$_1 zJ$qz-D)LK8^!u?he@N^k8Vx!4d(g(-U;cb?i2O!V4(W>JKU{vJDF?sNlmn|2Un3eV zIn2Qtr9V;rQ^hmoH`;PY_jB1diN7P^e@OPTBMgHz$Klwe)xgoO0DgJQr2es$WE~7mME?2&lVxxGX@*C|rq&rjobH$4lf2rtc z&)uZ>Uy4R^4*4HZx@W}a#8<^P#dk>b`_JND@mmqvFebhuiE=xMJ;WSwpjaRdBT??b z;zV&eiFqp{QC@{;wCUhqCA&rBmx@@N5&A&GpSihD(VDTwV&6w}4dBEKiZ_&(wQ66FjMM~f50iQ+;M`Hm8+#iPY0agDf^ zM7bNpjpBvk7V&x#<=!mbA>JiEEIuwiO`_Z#;-AF##ogjQ66Jm;hVX)xcA}Urb{4yn zD7Tk5SR5%9iBm|FGeev!|3Y!8{MF(r`PYzG7eAB#OmU<9m&m?Myp}|JZdUxg@;@j( zCjWNXe-Pg!k?&pc1My46e`ZKVHro z;xcZC!_koMuh~BH=mwZ8yPsGn4ihJd(?mW#!~Ev`CAdNM$>N#fx#ET57V+oeRpQO! zuf*Sq)D&brPm0fqZ;Ee=yTlL0FT{N!ALU{>eDaE)kGXD()3=^T)(HeBX(5d}M{>V=H8a z*j4N;_7w}oVPcUuMm$`cEb@^Tmdi&|NXk5r-fwKQ%3dp;B6`2EahvQr#RtSkL_XTW z^7yC{`Ih*exL5pI!p4L zdHnxl?@QpLs?PTBoja46NoGRG!UPB~kc6F(1ra4GgfIfK1OkW}2q6R#2_%vLK@d>E ztuAaXEE;NE+PYiCT@lo3-Jn|KYelU)qAe)eD7F5d=bZP>+yE|Zzwc}N{kgx~dCvQu zbKbMxJGt}T=LoJ8yhQLS!F7V01-A&^DtMdVeS!}PJ|Vb6kmMLF?@PgN1j*P&J!#>H ziGpc@?FGYvS%PZsFr?2Dd61ymOAPv9BA+T)A~;b{F_Iviy@v*Am{`8Ohem_Q_8uB5 zL|!TQ6TzzluM^xXNCH6GyH$`(Ae3Jad`0ke!8Zlp5j-IHg`gXGncpYaMleONgCKeS znC|esGe|o^J(*L8X9!LeoGDl>NKO)_yGl?!FF}|LGt~c7P(43E_&$*z6#TW|^Mbz> zd`(b2S3%g`8-si&w3{qQvJuMN1@i?53Kj`Q1Sbei7MvkCOK`s6LP2t=(Eb)d(lb%M zPjH*yQ-V7MUln{?@IAr(f(HfRe6Q@e1o1l6=1o?T9e=GQ!;9G+43Vtm3C&4cSzYm0&N9&wGGD!M1|w zf*FD*2@Vw;AvjvFRPc1c>4Gx_=LpsbE)+ah@It|h1+NrbE4V>WJ*f>#Kx5xh>&-UH+Cy)W*Scv4!io=*tw5d4kcOM>tsF}=O##b}XB1noU9riy&F;5@+vf{O)7vPF9r30@(% zMsTB`+A9$0$Y#X!FAJ*Ygpl77`A>qM34SH0_7Ft6ID9u&?G(*!39P7y2@tQ4#hY!F;7c%h)Z=fy^m)pJVJM?I$mZWsMCf@Ef5ebsYF z;Cmu}BuKI)#@l;asOOE4lleRjsGd9G+Ce5I%Idizkc3H;hYF4$A{{A{s6R`vR=kSISSNFpT4FA0+2i1NFF>iHq$Z$u`~5#y5uNn%8~hoE|H zhjgk#9U1xY+axrZPbg(w#al2nNDWI^%@QJy16!XU~k1j!jhd7~g{ zgDBr6NIoFSzY*L;L_5g{M7{mIj^sa-zY;X~oC@hk0YrU@AlZH>_Y~|;L^^x#h$7LG z+K1`vy(7r(Ls>nK1Cro}vU&~&By$htO@cQPVVB%J)ZZ^iiXO_p5hP0w<@W?h)I<3z zK@#v#P81{u59OYMq~W1_k{~H|C{GkTi->wm7kQ@O9MO}2hv}CIl4^(YI>B26)$=px z@1YEPTSfn{;FF>!7Z3BlDtP$wvd<*lUnE{VKSO#KpBKR{IeD00JvRfAfroN$L6Y!L z9x6D3hfT)_c?Lj;QjM+lA3u%!cFFtUBaU;ffhE=2tCr?)(CO zE2mficgxvTFdfT(q^6cHn21Hx&B&>&n>!b8IXH98!dop!G<3q4oQg*H2+mm02(v%_ z=!m4~Due5a#{dn{PjsI;y5f`R@b9}i4o}B89zAgSaQ;xbzDRR;xx4Mc5a-6p<20PM zZOQ={{+xp;haGn+WPIf`hKPO;0wl+yUkaw3vd4Pyl{`BSg2uNY>?3Da))80Z2s7Oh zbkw=H2HA&gqY4UVxtEN^tHepVT$aan5Swt?c@Q+dKnH{wki(8^gzU8UARJ;~?g#gF zN$ZC)Y$Hf-2QNO%-m|b5MnAJ(0yypZ9lp2A6*;)a;ks-ew!IBdIP3S(blpDMLw85* z{Q_a;$;HXz^nv(}d6+%M--pwg?yo2PxV>E(PmYZ>?c4K(&taYQ+dnbMW~oO9Z4FVQhAjgOEn3}rj$IUQIo$A@J)rjg+r5^Fo6R2zxR<4k8%eCOUS zgYv?$Bf7UsZa9oT9QrdaH+SH`f#Gl-Kx=+@Zk3|6!wyJ^*VV)~V}+_LCXo@?H+B z))cD7q}Nd8_S7-|0erZ|wO^`K-b$px<{0X3m7cHTfH->XlITygOT!{wYbtYKq*8Ux+JnoP18TS_?GOe|U^z=<+g{=0d zoM*lYdtXQTIP7_G9U^>g&n?z*D9isGw4R>__$=Q)n&DrhP;bPu^}`WLV0!L(;rW?= zF67{!QHtkg?;5CG*tTE^i}E8an1YnSl`n-8545JM0dEw2M65YX9QGz!=L07;R{3|SZ^Ha4L z2zt<)-u#YQRC``{3liEYL)`O%9UQ*_A6=nRZNuU?5#cQF@xHCVAY0-+!Ed*ZPb;2k z6)|iik4H&9(>u!NhLzxZEcdi{hS}@rQNughPtoF@7ZIeTZUN>FYn$(c0m{(&bp+9$WiUR-hw?HDlbc`*{1yua@BsS>k-UUv3xg2@;#S7y)PX&kuc z{r!}v_q_1FBn9a`FT5{H1N5F3-knlzVUWL-d0%N;pz;n0X42HFZHFmQ?|I>UT}%}R zH#70?CGY4UDZ{;gi2svnZ%J?rTl8jf5h}+$FX%PteJ8LOiNL`hT*e`NFOe&ldtP|h zqW5L8anB2mHM6Fv56+e}Zf=uCJ;sGTiftIx?hP2~>Gn={`Pe(5uF!e0=Y=enklGOk zdtUHHN_urt%zLrtg_eCGE@{Y}wHydFvtHQqLg!Bkbzm#7=f#`2TXD~eM;MPiFLZov z=ogf+=Y@KhhdnPYW<#*&g^nK-x`*-D^Flq;%Pb7>$1pGUywI1DA)#E#*z-cCFAiPI z9><;+I(|fGH|=513+3FGIXZL}(__yIoxUV=KRU&WJulc!baSW^%fp@*52^Z232|L{ zvF8PslG^j4nFg@u1=on$^Wp+3u;)c*JeE^?Ud*OR?0GRARZ)9h@E-{;_Ppq=Qm8#I zxD@mtk^SE>NJ?boFi7i>&*Od;2~y3kq2UB|B&Et8&(BpN=Hs-DB|`pmDAd)TvrsK& zTt2uixo5RpF}*X{Z0vb)H(HgR3S$8;_Pl6DijcZ?W6ui;SmU83Y%lh_&^_o5O=DK< zc_A|bC9>hzi~yhM{Qi^Z#hw>@$RFCvq(jVP^~4{hW^l4$&kHTbh1OHXo)_wV%snp{ z;1qGBw zo?y=lEjNYuBNDz)B#lM+yrPGG&H}OL#WbbBo)`RC%ZoiPSOY6_iy3;2(*%27(1hCa zg8%S(vFC+WV9$%Eslc8WT7f+;W+JZ_dtPV-_PpT#VP5Qcp%vKkq8satJuh@AFJRA$ zD`14RQhka&FDSE8O2(cSl;_zp_q_08&x;LEgzDHv?0G?feSRio?0NAEC1cMEUezfm zQ`qx@gTsX+a)`Ux67x*y4zr`o)cED)+u;;}r zq%zH}I-9@AwD>GPT#7_Smk64?yvqiZu&m2a7&@=ZeuS5H;jT?fy1a>IoNIUw0{kmX z&rgxh`z~_$u~EhY$lm57Xz;yIeSU$@_5uI2V8S>&3-30@@J|n>kSvO$aye}KD}t%F zDcKd`mh}D^!DLcx@(Rvv+x(TmeIV+`rVP*14CII~%tIW(E2)!;10nKcGGVYFp^eueW6oY|~|Ijk+~@IGX^sARJu zW^r5ABMn{J7H2kpyETU=??61at>RbL?ti21)I?T@xAik{_UMfSVOGN|aV^5wUS zX@Z|4ID9a;`n_&)_~81_x2JU|%HacTl*0!T$L8>XS~z@g>)>;Dk>c>X%!~yfZ|GMu z56|Incubq$=V=3!9Vuy`&PWVK4$2|5#^W9Cd{|^#QC=!RGFge(7gbO=EltM$l z9A2efewWwjo9gPT)NAp0pFZ}|Ki_%>`@mr@>I*GLCD;v&@&%;oDA(`oGkG-_IM5M% zZM|+@c~ui;P{sV&4*rYshS_9?P}SvY|2Clq=%Ol{@PfNyg@T1v@A>1Uay2AT0*aY+ z3ubVjDi=1Y3JCKA-|JT`a4;S?2tB~Wp(~>pIn-$B*V6SH_EBmB)B&&m$A~#v(-sI- zNR&u}o;2)BBzzC236z`6=W zN_i`;4qYL1og!u!J#N@(PokC;NmDtcVKyEVu+ksZU~DH2C=uq#QN#Kzf0$tl-=)kFr~QC$qrZiYCR}qAt7! zF6CVF4OLaJ0zw)x$dv1W=faYuP*sI_;H0OqX>2qjhF#T6!^_8v zEXAd7*a)PEn$}Dn9C$8stkXH=wH2iJ5Rw)wPsI-xBNwWe$(joF$Ly*`Tvn^d%mJlb zAEJyNNAl`8=sfJyiW@^FOu6R7P#uoDlwJjz=LU09^YExkm6R1F4~bsnYX=UfP&7IJ zzp%^9Q`g!kmk7E^6Q}4Y8Dkr%tgR!53mKj2ht*Yq73jOaT#$>!dCwt(jlL>ySs5Ty zIx*an9XwG{If8*HJQQ?}!{^SZ0y*H!FsPR*s~Q^W<~M`~^~=xA8`STd0ifJDyKa83 zf0XTqUp)A5-N|LaFTnP}FSR0TT%2L00I%WK`?>H>|GfGrr(V@$6Sn8M1n8Gsf-=5>Jz)s;jEc{{}hJyc?uz$&2 zaU#$@k{CG3*RSX|)T0qv*mosEmOM=GKRUka#@7EMJQsP)hhLCR5sV0)CaB&+Li{w5 zYX#2{TrPN#;1ztsN^4T5jrQv@GVy0le;7~#SipY5Wv_QOEaFgIYf*%R~MNqw`g7jHfHq2Kb zSR^=JaJry+KLqJ+6Ztv8-GUzqektg|e?GLEDyZJ$fUMrz0L~RX_m5?|D+I3>yhHFY z!50Ph2!1N~jbIQHo_0D3_7glwaE#zo!MTFV1g{d@B6yD=_kX9|3c)(T<$_lU-Y)pC zAbn4m@ArZpIMGl}6U-JoPH?#3B*7}d1%j&tuNJ&naI4_21(m-)%GoRO*MbRtU4DjO zKf%R(ZZfW`Wc5jiHU zyi4#tBGNq}@(#ggMgNM(uM55*`VU3kC%9kqheZBX(2W~3>x&<*R5{!Mkmd299?MK2 z)Czh3puVSIU%>*w;|2NHf$53_M+%M+tPz|m$S2`U-z2y~aHZhof~y5L3f>_2D?$G3 zKs%2MZWnw(aHrt=f_nw`3mz2wo1p!kDIfOJZhOJ5g4u$6@Xz>@1cwWb6y%QpjJMx2 zog*@Rb*Nt`sO}$-aas6Y|6O%IK)O_>gF{)m)E9o5Ki*%HPL)UZ*^J)t9gdg(k&c^i zM^xX1*q=NGXo!B|_NR`n_{0$K`I|ZpPscbOJ#gYu_k-zjk%oDk`M5n!C*xQYHLVK)>ZErflb{+(c zjj%;xdHb;A=0jnJ8TT>f+NBPK9h`?aXSo@fhOq*XESGw_-18B(^B`!D=OWC29CqA! zke&86XKDXI+QX$QYHvNlb{+(kKR--H4?Au(G){ZBJM8gtXV>o*gzY>u@-rB__bB~x zBjTL)9)&%7-1rUNws$YWw3myM$0U4xzXtbe`(PZ;#{}(k`#K!mzwWjkB_$i1~NkkG`-zgWh#~`Z&h8JahuGumdlBJ!dGD_dJXM{5$z$ zvh_zMj{0{_WQ@ybR>-$`#H>suJI{X2PYv%)FE2v^fqR_bJi_h1lX{+;P8 ze;e|)_V0WRiA?KMMB4tHEzsEho!rIZNdHc5BW3${p2YAE`gguWn=${+64c)5-IBz#J|&x!lVA3Cn3pq`gcBr5*+@W%KI?p-}!rH{X6|T`=IQo ze7PS;OSt=ifO1HI4aqs{W4ocV5aKj`?@KL1QuhPFC#i@bCNtB}M%^ zyEE?(`F9RQ@&AB-=M36@$gkEY{5xl1P~qRH#UuPXcW{(r{+;|T=wTYp=M}W)@b9G0yVJk(X134a-}xJ+cldX5UA6M> zTulQ`|IP*~oc^84U)t&4shocQz5P4evYT!HP7-0n{5#dP#Npq`O(>oIoe9kP@&&TBbO9R8hN+$vl7cWz*TPXEq@tg+L-^BGP>r+?=M zyaG7=JMU)-r+;UJDV+YDlc;d|cfQPe{Wtk{X3>_zzq1YHf6Tv=SDmPTrDS;NN)z`nfY-u{g}X^B$;{ht)f6VSbx8!}sA6{+)kD z#CQ959*0Cmm(O8)d6%*HT-GIw^yhWC8R4Z}mf&+q7rxyC|IYUTQU6X7UimLGQ*J}{ zqxpB1#{4@c#r!)fVB0@An5rJnWV%Afp?CeK$NW2YpgjK+hks`#I>mp6?cX^Sk~!pi z{5yxX_U~kIW>GRrtHD{0lm4B;1@WrvWgpW!71&#T{VxAla5KuH5Y!$_J)H09ZsD8+wPmkoHpT+TUi|j z-%kzqjtl1xJU;jM0aLNB-+#uIfKjjZf5Ln72fouCxx1$R9p2tz^O%1pz8kA=#|ruJ z-?29tej;}qc+}uH{xA7=e&>c|_AL7!^zST2pVF^rg5c?bRf6cgM!EWJN5rn$NW1n zA#m`iD~}#HkNJ11u23I#zZ~=L)boP=r)_ZZzXZ;cWB#50w0~#834fn|XYK%%{)hQH zS7u{?@O!!TXYFbHGyI*3r(c!@PRhC!KM@%PE|l>P~gIPp9JSOh!FypH5PU*_@sGSxRo|Oqvm%&IJ7K z3_nhK4}09aN5+xXEXvb46&fo6^@1NK!`>96ryu9#5EM@*-+%Md)ewH1e}dBH>7-sW zv-LwLf$4>(a}wm>A5jYYI9EXpnx|kTi}wJX3)5*?>@^pUAGUyx%KTd{GhVXQ*(nSQhpAh^wwHW2;)M6mWx4YoSsYRQo z^DAYDJe_0}i$5P9ehiXo8_KqMI&Xk3D1MyUfD!CMdnfv}=nj(18-AQx^aZ&m4R|`W z80G2IVw9&-i>blSJV<evj;(Ku8@@N^cSB<08X32P-hoeZHvsZXJC4=yEO2veyQ%k&I6XL&d3UH@a`1Hi z606a{)A>6kW(B`u_xvXKwGw*<$teb&&NP54Gs@Gc3ySh|>IOu4I(3~3gXt{ym9`yK z-XXyRntHWuA0 z)47m!elL+Lm^__)2NZssx*Fu^WQbYQ)CXrv8sB3|qaNdO9HQDVsvTK!wI3&YC&bOT z=*P))7}1b&Aci036{-m_o=z>tcsjKl2wls1!H-ktkMVRqgSQUI)A=jL!;e$P=Z1bt z8Gf8^sQ4I9r;Z<_c|76ANt!+vcsjqq)TAG$zLdmxI(7PD&7TOKP8}cP>C`-+F`iDH zz9huW?divy>K00}UsrBPmt( zc>X~pVm?mWSR&*%pisP=oP}yJ3s2`@TSo25*lhT5UWaC;{}q)}ew-vd4XJB4{5UCa zM(}lI`f;)_^8QU`R`_wsj6jKOxW`TNF`iCt))o2#lMXSHDbUm?6huExEysnHQa+rg z^Bp9XYHOa(?iiZTe=#ZiIC(dtsmYY#$EnBB9a3)3@Z)4+@^t3F3jH{Fn{e`Uu2T6& zgqE{v@Z(&jjs!zewNtu;WGI%;EPqt;7r}KO$qCA}x*ylD+r`oV96Fi-~ zC{j?Sz|+aW;X)Ew^K?D~MMuTW4W3R8ZpXIlOZaiJR9*gSb|&z2z5pfsIH}4oc^Oc% z8x!muggtI9bm8x08=)a3uV(R#=N#+?QB?r`mfx~B;K#`;A9y`*s z`5Gu=ew=)nxyw^fEf3ct)@bd=>B4B!k8>d;bQr?GOlUcH#ry3)SZye1fO5Cg?vNFWPkjPv@Lq$~x4FqtXc5 z{@P$FssCK?1d zNYjOzyXNU+s3)SrII~$Ccsf~H4NlvSv#2fW^DCTp;LK(v%wcJ)!~2lmqK*|Yi_=(- zG*qE2&g_S2ZMb6nLalf@eXPb|Je}+h@N|;y^B7Mj960fE+DO1L zKh9%*oLEH1csh^qbk184ZdCMAaO4SB3AI$&pl~Zbsj}Ld8D+C8E6b3`!KV3d!qYjc zApaOoXVv`KRr4wr!&fUx(sqoA^IyWmc@&R0@ukB=rB~d4AW!E%<^`n}X8FGz$LBGZ z(0@06&SS2f4OKIb@o`o*!p*cH+;0|dUH!nnY|FFi`&HJ>Yn)$E*?1DTagFj;9-WE+ zS97?Mo%N{9oJYAT!%taVk&nXJ`R~ZgiGOd8@p7UM?88#5LbilwWcp{5sN!G9%c*aC z-^t6#S@*xs%Q+oALx0UG!3M!|1s;st`Bm{sy7!3PC@Ey(?hm_DA5a)BYi?t;e&l5&Fa+**t{ zL+~8I6@pg@atAJ^yF>6%!50MI5adq~OvfK=iF|ZN>?JrzaJFEh;Dv(Rs)y-!3ce-y zjbH%J#TegFu(#j|f+GY;nZb1H1i7UdW5Kya1d z)q*z*-Y@vH;O_+A7yLqyJ1w%DG{J1a;{=BbP7<6YxJd94!3~1ka*Osx3i9_l%CiL* z39c8sQSe^D?Sh{Qej^x!vk2{U66_~cGFk9UBHA`r@EpN~MA$oDWSggRoygY;ZkBYn zifr?A-Yxn^L~rwSJ|+5>MQ`(T?iT&KqPP7xKcS5JCg8@*`m_pyJ_d z$3-cJ9ajR`X)gozp2fPQJ=VpxHyvR+4}!)8uvLQZ0QO4c~Zyd!pt->llObuq(5O~y1OMs+8%NpH2N6(r<^}- z|F`)`hs>@Cy@q@?{`^}yFZ7uMeJ2fy7+t^E>&i6q?kRfvBUfh2D_I-5Z|Zh^$EKT% zuEkkvGB<28K2GmiyfZy>O}`Dj*6m2|xHh~xd!5nC*k5=-@6F@(8v*M;QoQFtQljfX zl4o{gR-_{GVoUWF<3LivJCQAs+apHii+hc{J$sGeQ(BTXPisjkENe;1FgCi@`_?C} zPhJ1qA!~R+CYVoTpGw6NolYxZE&Jsr7nagM+_ef6Hb@f)YK_-aGz%36Gd z9j=?!;#=Bw&5lEHu+wfpNsF&6<65*2k{i~NHlBs}jEzqpiW@-tzec(q5p(mD7I#@$ zi@UFPO>q5LE$)nIE$-3nuidjZfYL{A*?!0~d(YnF%qI_dGTTQwY}&IoePd~hyKu)L z&&E>pM;z?AH%^M29N8FY6Y09C!v^1hBwteAu;Crn1P&wx642MZB8eD-6#a7%dgfQW0KFw>w0W52lrSP+}V9o`=%>D$lR2*v3-}!2x^fqw8h=V9Q@U;yFci& zsbHhE&y~_=UH+yNtP^AZoh$M-=3dul^SF=K`pn3dL?p*1FVxn|Ga&XXs!_(o%X1fD$Po{aH{M<0!z z6iF)B26^*vtV7p;$ZvOb+vM9AfBmD8>(a3{?r9&%j9>)kOv0!d-JUuWmua4m5jnUE zt9?Vqral|9+MBo<6(JVmv8m76jYZ23Hr$oBsl0RdO^^FtY4L6Azq8xsOq7Bd=h}>3 zT3^&P5_jO+T=Z2}w4x__%0y2Yy-wRX`eU~_(tGMI)Go0UE2DI;Yj`5&#KPf4kcuGT zs$sFFe?~nAngy5z_Z5fsTi)Q#ZX3;0QmS8QF><{-OM&iOvwy}D>k#tgo^bbLAML-2 zSDg)!*^!yJ*6eB7wq?Tyw;ynu^IOf8Sf4LH7`ZF=`fk@5S?7M37eOxvig4me0So|r zKp)TzbO+26?3(S}bk84h7KN&e)F7E|QT*2^|^csTOvz@8b!-6O$ay9Z>_0YR!r>n>h3gYvg zjk{WmAGsJ7EK()fzVxL3w0-HXqLIESQ<Us60-#MIzEG!Z`bI&XUL16m#;Vn$H0*$x#EKK3D` zRzCI_C?hxrq%=q*hIak3BcM zQC!JQw66MlS~A15{sn7R9;Ykn4!*{ESNNBySYMD8gO5EsOML8UIQ~j}@RSlf?)4Dh zW8WE7p^yD`h{1R90UvvYSwRR4>uTehI~=JN+KjqmR9E1pjp> z4~%p=AA8+^sE@s_b78Q6re0}#n#wyQ_$d41 z)wX9TG3sNlO%(^Z*${l}b>7jzM>$G=z(%R8RY~wQw)f5CGm(fs_A{9HoxmCuJ0-|} z=-^||6-*!dk66(AGTG>3PovD5ram}Z(&)pVMm@%*3Q=ts)ouxLY9D*{PG}D8!pB}$ z$_PEk&VY~oW2y=6&@+q&SF)CUp>Aw2xRSLT2<=B9^s(3ZlR{5XKHKH{692W)$DTgq z^s(3RxuJ5(@Uf?3tSfUs=oXd-u4ElQD8!AQ$d$~^?&)KnLVNJB*O!tZq3M(t+Ubi! zsmu=_dmTR_w3jltlCxC)(V+qC#wB+8lF(h0;bYIvK{to`Q-+Vd+E^%aN{H)eC&%<3gu(ZrJx7tTcmaj zk`mc?4ASkWlgIrw5~O0!Z@e=BgN~$B+2fgjC~c3^HkJta$@;5&>^Te7Viq5Jx{1pb z(|ZeS(Z~K-G$x%7!Ih8w14t24*An>HQ@|PzsTZl>W3NZZ9a_Wo!^d7`1WIJXJ#Ly$ zp8~sy-cw8;H+c)u-Jd@86ljX{vGlRma$IN+JO6MW`(z}RYHJ^Rx?+d6vyj@Wv?W}2ch(_ z-vK?|X$ciGJ$&r-f~yXVXL<0k*K&O*o9V%otmURqG0TIG{VbHvD|(1ejp$>)P$}SJ zzmqB8W6v5WAN%u}0$j;7p?vJmW|{D@*9!R9r=s%YO4bVa*tg-#f{(pcz{kFTS-_R7 z74Wg2#uV_e*QLV{t6Y#NTsk(f=uc9)+$DSVe@Uf>V z!{lW^&2CIEzOv$RbD?LLTzvLgC{+61_>AWqoPdC`1t0t2Yyo`idF6wT{k!ZO_}EWZ zB7E%0YL4$?ccONk``{zyWB*H7>0%(=^00|qMi>=0%Y_};mn%IbVbQ8Bc3$%op5He zE@p8O({V$CBI;OQb9fT%RU&#S&g`qHi>P$Jg1ioA_xh$>IM6FyGfZEMvwQsv!yKWq zo`D*WP`x`-jZ|G(0wcLNyH`?`!mi{^m#-FOe~lWNquM+V-2upZsY68#^E6dq{zx_w zXZISz9IZ4LLgG(l+1!879G%8y4Z$pIhco+JHh**{>XyRd**JULz~+z6rVdrlGt6OS=M*NBHMAG&tzibc@P!3kXfbQ#pW4*5Cin6*T;rwC7M2jT3_oF%F~S3z8*RLEEo zViVto_zKSKZ`s80s)>s+ehYAByV2q1_%t^A4#>Ztj_(qg<2zFKN633{V#=L}vX8Mx z|EIil5Hu{`i3x)}d_Q0i2C`cYUVgC>p-MO*p+}%Cz7!0JyS6A`;z@9(M<+&1loUD( zI!PVXWe+$~NAhSEcjX-p#U z?MS>`K$w8jGUhLBX5i;aKxPKG0gQ>=V%bETJ`jl&WGyqgH7g04cw3X{ZhjCl9~dCR z*{EqfP6P?+g(G7E;WC`6ELgM;({#Bk%Z;o!T&A;C{AUNXB=kgGyvCaAmd6drXr>TT z6dtY^bhu)GR7&SmahU}(RL&hfY zR~^$RB`^&Mxl5ZFapd7L^}(1}uqUJv5ug z37eI^p|P2Po3zl>%)sqhSlZ0M!#Gi0g6_YD`op@WH(E%3J1h)>qw#Krb*?oJw(50Q z(}ye)XSe1cW*|2SeHYHbvJ}SGbfl{QDw1?F4K*~Eerv*Y_N#bWdRR8sd)*XpW(#BA@Dno z8Y>b9+-=Vq20q4V8fOt)Xu4%AS=!8i4=40Vs5<}URGBY9U_DL@2;oMhuV32CfL{M4 z_WD4%D^a)T96=q_Vfxj9FbY%)-*mgZ-gsQisX^^oRkfp=(bU+?z)V&5rlw{F@P!?9 zXy&;HL3hXkXNT||UvXu z4=2=3#Q8eBl(-Qm)*OMYMv_`KSq&wIk;qYW8B3b%rn!vy^^S0(BdpT!!7I`%B`#GB zn@G4ot81?Wa^zh`{ZishI!x!5qaLxbWs~i}G>tQ2Eu3Jt&@?8qf&8%^lZU`@bz!WD zx`9oqf#`cA8BfsdJ9lZU9Sx55H8|SWpxVdLa~Tawi5xu4WVVTe=Q0*7CF(XUh_=Z@ zA|~XD;@pfk=rg8|B&282PMy61oH~0cICZuSeqrF1j!y=8hXTlz?a@|OHUn3*=%Kz6iw_3 zRLTnx{|!(U8CZrB7VV0;AmD%vg;>rSxv&|8T_AP8$I0%*P3O_&arxP5;qrnMZ>;(G z^7XFxZ@=x(O!;p(@oj>j7xOZ+nf=}lXEZa%k^_m%Z!eR~l(*o-R3Yfad5+oq5(M4| zG2wVM9)QzhEHVl@G&6XjiaDJy1gB*zGS&TXgw_*yH)M{yoal|wW#p-QBD*SDDUSMO zPDSkcJ()Mk`*5OigsnI&u4_C1u5=Ht#L7i-bL8A0J*8XdPZ$ z35$D*F~*vfWel(cRh+|m%QA=c7Kil`+d5aiIymv8(-MuReNI4Jt_bhpL{V=qV}RFI z3m3s=`@V^my&Y{CuSzOutTC|_;!+2SvM+}&W2xhcKgqrxLana&)hG(#rNq@bT&pXL zLiEwf*pjF*T=*Mf)|M!1waUVhr9?ImX`xQn9gE72-;E9!^<34L5R;#bq8!45}~vNQ)JIY^$38m{*)< zRWyM2vmoz(^A%@2gf%>Brdit!)8kL^m~m}Aor*n4*5a_o?BW?}`NN*Qt_R-dxBO%*yA4vc~;nC#dY;0#lcKm*A$PH0&_UhQV>wx%$i0Rh3Ygfc&rlmq@dg875qt5Tr#p8{$QZMjykApjn z)us^YsvPL@Qd3h=*_1R-zc}k$v%jZ%j+Geh3Jd+Ld0|iY{+@pLv=Vb5&qoOQLMxbq z2#Wo}r!f)%NL0sL3lV1}*O8f~W?QqLRo|h=dU8qySVqYPfq`8&AK^xv-Gy>DMLq)UN$q5uV4Q&mV1iM=+?!PU=@W&73O$~EPQw|oGEGOzXa>?f6mSEw8{4bdLw~q zSe%*T@mq(Mg>zW%OsG%xcrkfU`P3YbCpVnK>1VAlM_GQ(Q?n38LWqg8YJH!1@cXdG z>kEeqW%fP#9kb69H`8G@!Ae#Z8b+n1g;alVPBpOOtfVPvv4c~t%C!82XyhU+r|y=Y z?Onua<}g|l4zm%#Lbi)@-5YmG z8af=Ieqm&X(J=DDQW49Myp5`7+lD{+?LbP1F|XmFXQ?d-2^ zh=tJEliH2T7$b<7U^L=rDrU>Wr6djgyYIZh!C1>aD}dqhTHhGjW~4>)Hi^SVb)BrXUr{c zs;jS>cQ_%zqRPg)xiiYa571a;l+Pb9$SCK|R28-5GZxG;qI&>w$Exz$8M7K{&PB3W zwH32z7+U?(Yt{Vu^Xe3{fY_<3m`QPdZ2z5MCzefWsG8qUR#{syw_<*7UfHa=`Ev@& zhK(s5Sz3Oa#l(_5^H6eSUEQ1-RHUe8 zwyGIlx?ME0VzF_Qmu&5AgbMP|zN&@=wT%V|Dq?TzR@W_<3~O}3UuXNn#*d_$i4;~I{fBlZ^@qkK^%sWCv1VJ`^h4pNoX6`UuW8LGdrPReI3m{+ML zx^tTyETyKJ#$2wGy2?3fkQP-|V}R;rG^n{Zh&p-cyS!m$%}j2lVl-CN592b!jOWao zT`_lVg<6aVIp!EAe0`~2XEQK1C}w_DRc%cJvg!?^$|sGkn>RZ)ry3U4U^OnPR86y6 zHmjx*hCxbpz*D>NZot;=#J(b;&4K zoHFHTP4x`)QElA}T&kRll+{^WrAA7YR83VC>Vd*4YGccB!Mp_^Jb>jWS-6*e^In(&NIZ^D1j&JhlQkI4u#OjY; zeWIgZ-k>8I8Zl|+l-J^408R<#ELRSoUOV>PuyX=;Le)Y zxVXLw7em#p_H@C8kKOBJSJ12!<*-v{i9b<{s)bp`djfU*zXfDj{j8`C1$Pkuku~w zy*Ta?&!z6mte?29G>0Z$;<9da#V2MJ@j?4g`Y=^gRm_09LoWn9#}Dr}#)u1g$M{|G zamnsfGtCTH>1KPggW1u9Z;h*)e%^+(_Tg0g&+nDh`tgBr{Eic z9}E6jkk7Yi-z!KLP0C#aNt8)>sNihDg@P9et`+>b;Jt#63qCLSk>FnhPo_D>W% zRdBLkm0+Xbg@S7Ze=5kQp0x9XAh)llyho4(=#>8|7{H@8%KZe%f=zjp;2DC|f_z7S z@iz(52a57@f}CEI>C{IgXFIV_@HD|Q1#1MG1n(2vAxQFk=HD+!f?3LRg(TALj@Val zmf!-xRf1Ow-Yj^(;M0P?6MSFr3qcPiJng3mW(yuCI9za&V3ptk!Bv9S2;M6Apx|?Y zwYW^MoW+8Q3>xyaBHt?bl%QgCM*KS>eW!K}Aeknd?z?jYDpu%BQ)5%oJsVBgG~Rr;0J;q3w|Z| zjbH$EVEQD%G$PKh$XSBDL_a{}L4qfVeuT)Q1#!Dj^8%M4g(yxT@5-Dn>4NH)1<2VV z_Yze1LFh?Y&Ge%L#|qN-fO>U51YRWaWrAx2uNJ&P@J7Mg1n&~uD)_MAlY&nR@)r}9 z_gg{w_ELUJ@B_h*1zQCFDj4AX3+a;tLxOxyjCy_>BX$?;CzvNlpIpXI7gYCE$a6$i z+(nR=ihQZy6@nWDZxFmq@Gilvf)5KSjw9Gp_hH~~MgN-MTY~Qjek}MWL3O`IzC$AW zcprrv5TrjbWxjz%>?^2#GlERtV(QNpR9s1r7l?em;3~l@1=W2X={AUbz2Gf^zZASj z@P5I^1-A=6FQ~p3z@Fk<0=_N!PX!MM{!NfS&$8Z%lL^>H?Al_r0LMKxFm(1M&kRKQ6dk@OipY!Ou7$56h7ll2G) zCJBZFI|_Ca>@G;>c;@5VjzsnS4M?X9$_;{x1Xl>sPlNG45xh$9Izjp|GM?`LMD9dD zyjzeC9F!jsd_wRU!QTkJBKW%C+k)>2ekyoCuto5%f*yXqL)b5vB$z7LNwBLR-wa^- ziGpQ<(*^m;CFAD^HV7&%FX)$xe4*fFf>#Qv@1aPyQREv1ZxQ5MBeZ|7;KPEC3qB+G z8^PZSz9#sl;5&kQ1wR%1Lhvg=liyoW9)18)$k!k!A1`>aV3DBWBt!fdktYgH5iA$v zeh8|c1nUGB2`&-5K=2~LD+SjIZWO#h@D{;e3f?QYRq%1a?Sjt30^38vEY@0YXvt5s_*@xzUkZLLXyH2=>+cohiz}3i1;-0c608!e5v&(%6g*Gx ze8DRP*9zV!c#Gg2g6efJl>4yAj|)C6_?+OYg1ZIZ5`0(i6T$t0e-S(+$Tz^)K0415 z`TiHNouJ~JgWN;p0fKyWg6U2XR9tkBM~TdhQ5b)^;8}uv>4*9ig539n@)d#`1=asg z&?`(*(x}P7y2<#AwNVi#J_5T@U^?w=g4$*HFd{~e# zL(%>p1m6+-K=4z+1A<=*{!LK*UxxgO^A4EK|6hO^g4u%V|1{|NrWNDW|6{Q-61o?g$Pz1(=*q>}klnGTO~?f(yroQB178!Ki2@sotY zYCD9V+Zv4=^}|rkjD`jyhl-r^9Khr(&^BZoa)9-{VcMA*(l8_&Sr zQuLpF*l~R3;k4HRdu%7`$L_J)dndxolZ%r_Q6Dg@9A=O458-sCTau5L$(cb8#_@bc zP}Igjq${=sAj{>k9jCK?e8^+>UoztC`n`fM=4d@Y9fR;&mvgSNOddqX^e}3XE(~Qm z=-c9?J=$lPuopcphp`i*lD0#Ud7SBzP``JNk`8=#CmbJ+9Y4r-H}JUp0V??q^WD8s zsR}%T@6H{$;_l&>>}>J9J*(PW?KxnKG{Ahf|8sC?x%~&eJt2O5na_8%`x^h+#C;?E z3G0phm#^p(xx?qVn!I{1UIVSmqQ|8;-oxjyqaUt|**yhcxz0NIE7y`9hdjnWjor+`&v#jyN{erZxWHpJ?&G&} z$9?=xzVUe*!}WO^S06A-^=WbSb*)Q4yMjB-P3cXmKl}wA(iBAEBl%ysP7AlV#*yRf z#t;3Q62NhGf#qKpzscxRveUdSfxY1JG;ILu)|w*Efo}`8?Z0@1zt51*R<5|M^I1N# zAP^Z5!K1qTiD38|f^!{u;QoEXz(JPxRc5$XOJ>-&X_Ig9&NmJB#>9Pbo_h3GsCr_x zS?$a3ddOQawAz>3^^m(@Rnh0W+#BslN@SZu&I$pt+`0^s1+q`O5 zedM|iPmDA~%t%Ic>h!YeiPOpPb_ZgV{rYJj^Z-+}qfhl9=o z8(PnR463iYaL=(e;ilm3lRiwTd<9f3$69tDpFWu?mnRJgth-^%eM0*hrSkIsZi_#L zy2qq1rONH;#Z*I~caLj-l~Q@t(+Qua7p#HmYdI~rJ@h=WKEuNIq^BH@bk;QJJ>e9r ze#7GLYo4sssSGE;mZxtDuS<&W%afaWA;RF4;L{=NBYecQ;`rhV)TZ?fKD~VtSu5)k ze0b-pu-6T}4;){;p!2!Cw^-!z@_&Gec!lF@0$Sj;IlkB(BkKp*a6lH4$n3?No0inJ}B~7mlylFzRo` z@#W8#65YXjQB8k-g06rs7*S%X76U;(dG_ab)S}|}@)sn07snUdhKn|zE@k1N zKh;MvqM+*U7{}KX)~q~EcY!;25Lx`KIllbg!||m{h;n>QhjBQ5hJLE{$2h+HTa(puWU{@@H~bISGl3jm{s%?!1)EsShx}^MW(InzWgsqL7L;s z|FSedbA0)CO1XtWKL7H^IKJEzTXTH*Ul&uwL4GOr|6cNr4({W0igA36W^9b(Yd6Ih z$Jc7MD8}(cA}9a*GTF%S#j!pUSz>fgn&XRlj7t@wG{@Ht3|UXNf4a-3IKD2WU2uFc z9WDo<6n2$^((!{rmr_2AhrDN*s;ji+T*w?P%K%aePTq z&GALy=p0|e5TiK0xR}B5MOkrtQN~665q6`^@kM8gfIrjpJ%GUqscVUYIe~@ihx}6a6;F7dP1UJ2<|^x**b9vZ z`W+l!8`(++$JZK`cNoW)-@)^}(zszMRjxSzy{5HqeI`-9(9AC^0j;}LN%8%pt zVjHnwj>hptTj1h4jV*|AeDPN@zmwyu5b^jv_9bf9nLh=2%v@xQzrYpuOZTAYudSFmJj@4DY>qF6_-rMD zGb;-f6ppVeATOe>3wl5}z6Qcn7SD&!QnM(T{tWj(CdXMe>mnRqA3)}B|JkgsaD4GM zdA|Lcy@&QR$JYapuf+)hESutsE^wT_4vMct80Ig>Lh(hysy$FWhf}d+jZC5Hd{mvk zV`|o~5LNs+@wYg$w<5Q&epRA$x|3y3MY-l_iYDt>$owfTdxp{}nyh}Pc^90h8d$_e zD-JJi$+J@HK+ZKg?*(+Ga7}X``L$?@bHoC_!$12?ukRQTHX0dTf(-uo& zFH?PqDw^Zc*qQB7>ja$H0e0rNPSnvEYaw-f%w>+trfw=8aG!y*J6_u`C#XhT3h`o` zJ$57hOguo#ev|3%Pv>Og19v`r@A(4lYMs%8?j|dvDYvSW+mY(=XiBX!dQ8V)K8TdP zl+A#tlJaT%+c9R3gs4Ov1>1 z9iZ(EO;4PLk;ClNqry1MWq}+#eNtIZK>~VE^=E|2#^>^UoxVLE=_s8xJj?)nAXZPcel15V)7Z@erOv;MX|&^XkxV z8Z>V~+Jh6-r@==Nu#6G-G%rl_wh@B|k>E3&${?TAd)X&6*cpKgoc)K2GV6 z?Fd-LbbOi@1x}_xcI8MUIF;ELp&C{RiO=XI+Y1P|4Sta}FAXfPvo#^XLS|!x%C;8L z>R7gyptlTu#WXJq+-_&P6$x%;Hb$sye5(J1%GR5$-l?+j^HpZOBJmr$<*y;pt2kB5 z_aU&C0$a`}i+_XA*Upy9?!u{=;--W;(6xi~o5ZI2huboXz@83hS z8>d_?XwFhb>CkPy7s$o~UDXSJMxsxdokg7j|dvVGX!Fm;zDL;y*eXN z28V|uQh-1n1=ec>0uh{jnVH#SRPs3SUQ-4~;1jGZiQ8;zQ<0v#*(hs`2-H)cwObIl z5odqqu`O|Y2l2+DwhA;mo1PZCS-X+;Ri>vSo@$Z{U8x=+8+ngOKCf{dYk+**Ql`&; z;Uk1pY3%eDAmkv>8)tte>-PaPQy_5`pq+N%LE}Lh>0){o&mV!+ z=tA)?Wgw|-=23!>PvI013Mh=BaKb!P!uqv0KmiSHYi1{=Bv^?Z6DP&B zH7A(LqbSQrNH`fvq-^KlMnvyOj1N_AgG8i_j7ve1LR{ayl2(y3;$cb1Oi0iaiezKN zg+Io;h$U`N!}sC<-46l>3!VPuNVa{S>+tSliF6)Pt= zyFjfdUP7>ng%cDDh2bnB>2E;&xmyJ^i`#iwME;YaBE*0L(h&wj86m8K6A3!Qn%nv0 zUJiZ(Rfh}49LF+*!6elgy*&sgf&~7<2YMw!1ScqymNhf5Lg~k^2k;~%Sbo+ypf{wn z8E3q$$#gX@MM)RngiXRqoFK4T*37^qT2Hvf);ntDcKh+q0J8FNxjrUPG$s&OS;a!g zfC$T)8R&@hjt-d36LQHGGC*TBC8KDfPWh`?wGr)fYA-J0vsMSK8s^Jz0$U(SK z1xpEc;snE*yO{x23T#v;&~fxdSohgv0(qD~IQ8Iiwweu9LM*+SA1>(edyzgQPBkbW zf}Sa7s0P6pIIm(e;*8caV(}3(0vgN++Shmf(_@`+daN@RIXh#KvojXOsp+%=22e2J z0-Tny*wxI&=uSGFa1&0<6T-bXF?HR|4Cqc`SEvIT9~YfrSs<0=)YV@(r`caCv8wKd z_Hos3_3mZ{evcD+!aG{OteF8$Dd@?)#oA!FbRqau-3Ogzp(;^HQ7+x`R!750Rzvf^omaLHKoUNVBk%q zA5YND!XjmWPc5)`?Pj%_F<72x8X87F012@TFR@-mqe2Nc5p{FQK0=yG zirQj>ZIP|ktvlTw6+f<*l7XY6TX&9~fhKscc+x1cB4%_hyNujs&W49^Vj>Z?>mWfF zR7&7bBSCD$OYIS-301;jg*6ln`FkL4qFi62d{PC7>|;mGDButFE&U zh!`i`k|PVz9Xo-bhiWoG7czmsMS-%`H!D$4Rg$uV{ka4PI)9gYW*8w-anDYNRyG&=PXU0mM#8NpGEn|VZ znE~CpNd!(pFj5k9sS9v0xz$~I|9Mjq3$OXIi?(0eZ~^}KlaW9zKZI8`!jd$ zmOYR_*u4-yQ3!-hHf0M}L69XNh|v%rY_fzTK%@w$xKy!aQ`t0Daj9CxrL9}7`-&F& zcNZ;gRY4-S)U;@QpXbao_YMJT`+wW_{r7!4pG>~zclLAU%(-*t&OFBoOo!oqvYf$o z@Ztk)BwS}PF$BBO6QzUg#BiMgtTfIE-o-~0=X8}(C{2FQjNu2(80;ZDWCiI;I{CXV z3Lz$AcdW%LYU!Bj`V;&ZW(o*+dY{PbCHBmPCe{REm2noY2G+UG*2%qq%c_# z_h856kDcgI)Lr7f><=CnemFs?m1u)d%(vTD(9zj6vzTDxjXxdyQjMMTzPW`a;Id2pvw*Y4X zcPcu=^9`nWo`}98-SY+`i4cDFdRtnyFFqf+PHdTp5PlANTVqq;!!R*DCp>Lt;(8`( z(m3JiFVC_WtwDOncs_12O>~oEV!57)Op`JFm9lI`YZx^^j~&>L?6@Zt0%>fx%oem6 zm6P}p9hV4!+`1bX!_j6`&c29#Sigl6AsD5J=qBpRFn!(T*i7$wChFn$^p(a~`anzM zX(v6C$&>edlcl>?7GEA-x@CU~57%>omnWmp`vCR^*I$h3yZ(Y@HpgV~4cz|b+Klab zCi2F)W4!s{)Zn^_G2wN@MN5G5!*=XP9zyzZ_aDL(&lAx<@SiG?L-Y2}e-*LZnKd!>@VL->OCk8Ov0hSLJJFV~&S)r*EwjP2zbI$8!9 z_-4lp24MH9#WMJf*|WV2ESqmOGsIUd{QdwBes23b9bCmQ$0F=rHN0q^?d2LgS_Z8U zinQ4HS?q4Sc=9%H$|mpkJVDR@VYnYTia+Br%-iVp;y&(qf^>URBxgl$qu;aGy_wSU z_xo{5^ES>T-fY4N!Q1HO&Y9pF&l60=c*?}y7<*IfZM1t){9!GQ67HS;-pT8wqrd0J z)79HJ>b;TAf$MGjDCT|u`=5ON-dOX7j5mV4bYA!%94j7tZ!9(p=iuPZq2>)L4iIl+ zn3o6hVVqmBdxOY}NBYMFe^Ym?35fX*i$S|eXT#@Do4aUwxpdFqH*`T|c~{SOTECKt z$^|nk%jU(XZC4dLuBK1#P9-zvFN#$g885sL6f2j6*Ae2&2<$R{!TjuO3!mFIOTOsUV?b zxL0n}<=iML1|tiP^jIMjhcV_?jE2rJ)S(x}LaiwX-GW-fPPnU4gSOj1JvuiADe0Pm zPzQ+7Ht!uu8G?ulV-OOC`0ZhG(MEvT)r+2My9pg=`{q(L7FxZ{2SA}7FGOG~2ZW*&gN1x;N(V+l zept9D5NhST8L&f6liaqDh7D3t*ZJA`wh4I64ai9Z+@OG08wT8j04H>e^F$`H%FPW1 z!p_=icsZY?#ll^^d>>fo#(Mm3#(EgBSgqfwTH!_`!VvCtt9FNKutPOy=LP&i0WUNR z*siMG?-rV<%#*6juN(M3vyjTd&P;nijNRB8g2kTHa3MMr$HFus>|6`EYPQvem-7dc zo8$Z}vmn`C*Yg->tJ-T~?orI^{W0Hj3$3(GnGg?0gK?moJ605gnmMmq1rW&&WpzP? zVB>Z)21y9o)(K~mP!=SJQ=D5?KoJ^Jz>z|PLsa~5O=#x$D&&kq;ej~J_9P51yuo0H z*L}};3WY2ESwQtz;|cQ8kQav1@=#Y^mbU&H4M>iq3zoZw`D>*J zH!4UT=2Zyfc={m2jHkpw+g#};I;cd6!+*IFywf1T^_Avmo(lzR9L(n4!Njq}=x@@* z6!Mgt#yya~uCxo_>p0J4_>SZQZZ_5K@o|-;d8h{Q5TNhvP_tMpTmWYA$mEBd7MK)r zJM&!2ZizXfoe_*?lIS|qQNK?1N2n!ghITg1%`u}H6}>^7^D8$Na%RURBcA3(ylFYc z0wGSb zTUa{*C7Rn zfO?>vl%rmX)$ef6?7tyK%}N-c`EsazdQ#4Xy`by)?=DsSH^itH7WOh4 zvwyE7HQrQmwRI&;Et%_oszUVa(zT8KGI?6?wgh8r^r7; z@p|yMQy?bq319y+n=lwPXhQh2hX?rH^+U{G~wkyNhJo0_lelwe@oBWeCW2X{yw>DOi{dJh}$<& z_qb9Yl#hmzO~mFT?sRq_aqxM(8Qw$eBgVzk#52Wn#JS=^afP@_Tqp7cQ09NVc!$WF ziS*}9L6SHA$lc;z@iUP>?K1p7de&|~{728)?FXYrh;h*b1E1rggV;+PCh{3hhVvCm za*=qk_#ZuMw_pCFXYKX_U*DqM@;_V8`ZMMGg~&OW<%Gp1VsnwNW-+|8*k9xuS@bU= zF`h@uE*2-r|L@haZm46;cd(fMjpD7!?_SwPFAd=j%l{eqzaYLL^4%=v^B#$M?w5T~ z{FD4`gfU)7OeL`!JvI0nJvHz+g?APUN%Unu68kXu^9?QLce?z~A`x%8>;($168UNt z(_c&?-cMw2CXvr|;*IjZOZL6uZ%Et+e?ojld`;nRiF@S#fw*7(2gPsXPi-~UqcMr{ zn~E*v-(EIfzhZa~66N<*_;C4;68V}H^E*p+sW^v3x(bE!#Vh8wO1x5BD{dCA6K^Du z?;W!FCKl5_L?YkE6uwLTuZZu6?}_`w&%`fDfMpZzq4gp2hGJ z++=-1gK z@|!0v7MF?_iI_NC%F66rRI zTSdOY#d>WQ9}s^dJ}o{k{*FXG|0V90{~mFl{11v>i6MO5U^yvbCW(9+i!J4UjCj2K zyNNx;B88tSjuj_}=ZI6qnIy_NSNxH90f~NJN1|R=i?!m7;vM34@s}jhJw+nl7i8~N z_#W{?`Pa$*T>O?qIw!}?CznL|&BV512l03k<@Jz#qBw*^KBp@DO!=QJPL=<;vKNR; zNu*n;@GIrNR@^LJC*DY+{5xcC7at+#ZR^W({%r z7&a4Ii5UMa2>H;P-u8^v41JH>m%hs58CPm9ls zuZ!mUBI@y}>;vN0;vq4}?~jNV6|+RME)x8E%kC!*7Ke$ai{r$z#8PpFI7h4!mx$CX zWBC_}tHm|qCh=O48V`*BOOa1=(SB6?qqtW*D1Ie=Bk~u1ri+MaVy@UsY`D%tf&9CR zeZ`YRK3KwhPZh_C=J65uQ+tBp^TkEtdE$lQB_eex82=&haq(&KMRAw-y0}~1E7pk( z*Lg_6qYcbIL(CPMiEYIWVu9FQH0wwq{Xp4q(R>ewf3fU|;yL0}ake;5Tr4gXDZ;_} zZ4qw}Zx(+c-Yq^Tdh0__vWDrO6MrwhDpEm?;qQu6_@LcbY%aDIJBr7Pg<>ypfH+7T zE{+nZNXPsqiDhEBI9IF?DKf_R=ZmYv%fz+fRpM6hdhzGtFU0%A`$fu^nD&dGi2KE_ zL@Jaq9-nj}gJO>8t^eSy_i()Y&0E)S_m+LKI7A#SjuK16DI&F0Sl-3rmEu})lX$JT zO}th7wdk$?ut)X>;y&>+kqRg*?=Paao>^n zwzr^xq-AEWR%OL404_E7pl$iQc*m z79LSzeiV))sp~~%i4>=yT_{p_m-b0wkw~R2`i~Zi#mVA1V!1e5tPrb33g0lFjbg2M zqv);IaHni4hB5v_qPJed)3Uww8g|KkQ+!AKQ2a!s$PV+%6q|_6#hA$ViW#qq=&j?> zNA>`5sCbGvMjS7mC6MD5ch~5i2KCPM2d^Czy2apR*80NvAuYlSSa=qsU61n zgT&$DC~>?vNh}k~MM^d?{ng?P;?3eO#RtSk#V5rV#a$xRFqq$N@ni8*@eA>5(ZRJl z<443yv9Z`vJVxv&9xwJ5`-yRJgh=@*=3ge7_4;7Xl}#-whF>X~`3D4KQn5dS^d-ntKbcZm5P5-BD{J6CK;V(y@v6#WZCbDt9SP}w6CkNQ!JceY5W zDB4xxQWE)5FpBuk9%%04f#yCQxLENhti*Uf7O9^^`#SM1@m`TCN(_Hiq<#|Zcf`*`2%8)K zzmTXmg_0OAL!=%O?RFw1k!YVNQWc5zNRf(1w97<_9?`B5&3!l6SIE9uyiI&S{EbN6 zBc|UizE7f_AItt!{6hXzMPmH0Nc|()Ek#No(e5txC6S-GuLl1i@*ggL3M4UpiAX6V z+Et>tpN8}+WSjeH2)~>*{3(>g_}7Y*MWTI=NM$72&xt!pq?27l@%G5!}K zE(c9~G~f6GhWI*Qh|2;)OdEy`@1Mlv-(Kt{_7wYw1H@Csk>VI}yf{UiF3u9?iZ$Xg zaizFQTqAA}H;UfOl&W96MKq$iJSQi5c$e7?UCXbalAN1oG#81=ZZDrGI6E2O1w<;?&EBf zy;Zzk+$P>C-XY#EJ}f>eJ}Evc?htp1FN=G`55$kfPsIb`mtwv6jTqH^l5}ypn9JjX zIk}m4oc>ws`rzr5g39u_1=Gu?E}DsFg=Z|ll0e2?Hg#%c`C@-4UNP~TWq53MW;xak zN~S;3XD;6ZQjS=7$SRn&VBWm)`B-=;nQ8`JK0>6y<3<&fRaaNep1P;8pdN7w_~wKvHwuK&WO{n-21)45EjJFjdO^XH|Y+R;WgXDiJ98nx|J|l!v#^lF(m0+>H1078pag z|L$#G9&_N~FL(Rtc+nm6FUw_lYzNtJU7y?00WtV{o0s2t@bKrir_|`MnEY^Ap2&}L zp_hhvyny_8-_zT?u+{MJ=XU`49Y8$RFCDvAzZ>B8(!goGUw{`8@tNXnUf6Z;@aMN@ zs@p#1hwe_~cPHFT(+xYfKlFySZiD<7{s4A=yeTK+x`qj~F^v1uqP(rw5pR%ZfZlj{ z9BzO8K1Thr;m7*%@Okb1FSv2oD*&@K8+iEGXPMl{fN{D1Mj~Deo=sumFq{0CKg;wD zBWv!Uzi(ZiderZIr1dth+^#*kb?=S0C%nyD*QZzCSgf1zbpIE2>(;wBA{O@P+sF0! z;dOnc$4zM=_Z&VB^J1RW<&y)WyX=o%!Igb3!KyyNxLMQZ>(IfKL+$?4XQg1xo{Q2R zibgl2UK3fDw%$7M)yfU=7ICiY)71`L)ghkU>(2OqBChZgSZA$uu6m>>ydk(g{a|)V zAl^5=4!3=B;w5pc-*Z+GcCLeCZ>in?=wz(nv(nnK&KkYhk+l)@>Wnu`W2GSKY;v zJJuaPr$=3+Usc^L{W{iNj_{u^?OE4;MDM!LoEddL9xt@CS`*1IQUuMc}@vZTV_12h47$>Q5)EA}h!T&$+vbOwT|KO#+usRjpj`f@>$T zkb`>R*!APFYm8&Y<24R7EJh6*V?VYoe<}KX&XT%g!EH+ygXMJ>8#}wl)**}0ckHV- zcZKor#fbRCyZguQL3!wzImgy@MCnWFE?xT7F4U>pUiiN^45K>yi(M&OO0c@oO<3Ki z^-hef0LGTnDL$?~JAEkjarNn7Iv53`U=R$Z+kIJS7lZbuG$0-~>~4_L$Xw z3SK4KSvBiNQ|!*IetYk%ho)dHqfet({O02WKOGZ~Za(It=;m(myRa@1&qVW_k2xiS zc2i6?=>@oQ-)uY%|A$41q6l*KVipUW&};xg19o&ZKHsnqQ4Ktub(lW_eVd=bkU*p* zB4hEPOBu46u|_xNgoh=Lj-?e1U5hCTiw~6{l@=dDSP`N)GZ5l5%jrgUG1Irt9YJ># zQJrqN)0s^)IFKQy;a{*_^XK6e3hu=Ja4B-P9o`NPbFol06U{4{)KLeTnuk4 zE|QUno(tU;GCz*y2Q4RqncVI$sWX@J87I;`*EQ2Ku4K~gEnU;B zH5BQQ##N^R`MKyQ2B%(te<`T9X&XMMS|P{wkrSiW!7t-!X3#gq&A`g&L9?ICU`8XF z{bfco_#0njfXwua-mJ?>GP5(dvUucVnYkH%LK7ncWj4$B9kUuFvsFejMjk9PW;MnY z5`JQijEM5uD}z^xk<(J?X0M-)8b?N^&~)-w+8O+fByzfG80?l{6cl-OC#%9HN4+J~k7lr9k*RIi zSx)|CcojRyj8pkDC3lq&3QmWSV`uZ{q-bPObREo$d+;x^xDnlKMh&aE#489nanxmV zNvm0rUq;iAvQcS;75P^2tTn{QnB?;Qi^l+K4e?_F=X~BzSTxoe za$9j~-mAyC zv1Ko@JJC4O~9sraasyOz%i*YhfPTx2|_ zTJ}meHJ>vIVmB)dU0~<13;B%AxAdEab$~9g^XT^${P=83hxbua`$9M3FHz!+*gK%E zmVJ?1a}I}I*tzV_D%Xn-Rm{Ndt{Ak+Zo(FR0go5y*%#R&W@~yj#en)N?m=~!#=cl( zccACP@Vp;88iTceE_EC8M|kk_44&QT*@7L!U$u|L4$mI+jL~x$_DXs(^<{3&xxB(} zj2{wXo?sJur6Do)j!b)*-I9LS!d{EL1MlzJKXw!U86NxTx!?6{&Y1imbu9J{pSzyN z(DMm+{1Q9H=C?2{sNVl)v4y6IWf>r$Z|7jVX`u(BsLzEPnkANYP>kkU8A4_YEi56k zr9V9;DlYH9d|Uga`3I(Rg^D&otO{^)8rQ9G*9Ks`V~)eZ6kLTUW*j)OZMBp{qDJis z?1AaY^#r(h!JzOpLrgLG{sjTFz(ITeQUmhq;IEGSI>Ilp27&xAPH;|QKiU!k97R|u z;7RE4L(Uc_GmLuUFyDe1LdP8JTy=ot3}s>=MT3nury*%c#Ef%1;U-wSdIj8vZ4lQn zw)>yXDcB)!Nbq8rH74g`N4~^^*d6F~*K$T{gPn0m{^Eh8#4O_+NAP)6h{Z0e<)t4V z5=9g?VyjDT|5>t$`gkX&zFkfM+CZpPK z)c6gz1^nFx`t$@FVUp9~$_%gFwt|j7VYjWxgt>yXmb&fvtLxA9uo)&X9qe$#N0koS zTET+SEx{N^u1b*9@lQ(nXCn5koPw+~*d(_L&mdZ1N7q)@($U^EYHI1|>>A5z>F9?Y zeMQ7w|B6~VMjHP!i1EgMaj=#S-VA}jakT|qV(bMichq?;?2JepVps%%?VE18^elFB6iMMrxUHU;toFoYwXy0z zvf4}h)n1aG7*M86n=<9hAKhtPjh**o(4g(G`MV*U1RnuM2P~_lgLQ)cGJr!F&R2o= zjB^ZO?mqB*pu-&yV~)~UzC(*#kTL$54K8M8o67KMdB|p0*V1u@Yt+=zvD7t|)zYyN zI|dTLx+6tJEgk$36o;B{8-Y`bj%-uiagBkdu9Iz{PNpf0jt5<%rj`yqERK+6wRAj* z9fc8Wx+#o~cZ~ly!tDbTmh6LZXqVY=5_5wa6~T=`vzZh6aoB7pw1X?W_QGB5H8)_b z8PC>U?#5Y0vXzK4mrdlc3g9@A=4V=KagEomfK^%HH4FKi>a_~);cOHe0QZPD!S{^2 zVi{>3cgMN~rt0oL9xQK%j}97q;BP&Sow}IF>on4BPnBuU$*%uMl5Gm$z>?><{-a2? z5B@cz+qN}DY}@O`f6XY;ZCmBCWZSBIZL6wg+a57(STl-b`0FoNYwQ@{JJMJ=3hGQA-EsQG5;)Bd~{{Kn|IAI>(rh@x(anMl_y|Nv=P^j|HZH(7yKx zL7{!`I3_CXb{FHC4N89QhL)O*6MsMKXajMMagHOVV8>_1eJkh)qJ1#dte}JU*%6;; z?D^Bdw{PH2aQvD0bhO8g3T=#14&WVzNJswRb$U*pZ0PsN0^1 z6Xwan1MmAlnaG3vD0Um93`s~X2oY%Aa+i;SuOKtRg%oA z#LLQ@!lqWCPEn7yqB`r&o6bzZoT$Crvsq~ezW`gfiXbj77^IkKQvopI7TH?z{ zH}B*p278Gc>0M)ZbK4{Ei<`7-Mw4?~_bH_EA5HRT;1k8njXWG)dgjZG{lo41${6S7 zJDjX^-KUZ&W4N!3;oj(JScaMO|7I!fXWE((zMdM%p1RI0aTKW%NBBw{@qH!oy4dZ# zWZ695{F~pt79SCgbprd!K9reZKA900rP@EB!uPLG3I30E^3fEfrCsf5Rv$%bsYmyM zX*^~}=p^H~CUufA45X6`S3)Nl?u1S<#*C+v3~%Wq<1@!6&df`Sq-yeCpu?Mz17Xod zq1IDExlj~^yk}e3*`e0Qg$B0`b%;UsIJKYvVGE$A+!11;kW^0T4SOaSZkrQwa*zeK zPzPv&riAn1a`N(;AQPt?9!|>`q>@`sip64+oM)|qH53ZHeg)-{A!7{rQv4ilhfh9S z+}8HQl1*qgMu|~4ITlK76>8i)lu}J`WQw6evKjf+44_mqD?w%E5cE%TL#a?#w!3se z#6|_zK}fa`J`_$a%+1Yh5^5Z_yLRmwN-adTDFxr_bjFyl^b?S9 z3*4$v^Vy7=1`^vSmfqdm!PCaG(wuCJ8>fmRWs)b1i@KlH#0&!`1!bAPa{Oltm$1(u zq08fqTKp{!w6=ufyFEL_?bb63LRn55qhy>B^UG43(r_xJv4C_Z#Ux>WRh#~D^@>9o zh3Jf0^i;a@4tkAanfp_Jp$nGgzh!W|N_#gjwS^fd~?U4O`l za&Y3i-w24vggXd2QMf082Hd=Ws9+m!Yi2(nD zGQZ`OmGc)^rO-fwl~r~tESa&O z^4uOJLq`=4FD~unvZSbZOv#wa1#`-$RacdqGIXe!j~6Vewn}GIEU2Pl?~M6XR_U|_ z3(lQgZj}z1Jrk;1F4!&X~KP%ok(c z?D@S*4@HCNY2hLuR%976y^Q@ zQHJ*)Qs4c5LwI-E-14&diz+a}XH3U}6{U-Dn$2E-0j-nNI}K)6O|Po9rt+$$c=l49 zKC?=7Hvcnqb`O)-g>3Bq7)@QO30tLX{okvjTROdJLFufr`P1i?TNOp7EkOu zaU4sl+yJ~3QN7^Y(z#`<%Dk!6-`4EPdX=G;m>$b2XI5Ddl%8KcJ?57Dy{fuD@SUaW z5$#0taOqr8%&C7U=hPYV%^D+Au*QIzzF^T*R${@7860!-O`8_YUsP2--OQv`Df*-W zV)HX*!^f?%`yNT@jJahqtI&5?$7EVfnN=}#LHUdsnCYv^%h5fYhBe1|$&f$7&NUwp zrXT0eE1QcfQ3i{(@Zr%fcHAkaPl$~-OVi-fCN>z$(+rz8wH)i5OpoDXW?Few)q={Z zSf4K4yA}57van~Dd1Z4JRCbD)1zuwG{0GH&({a7;*W&fv9x*p^zDJ9fp>8=MKp977YoX5uO+xAD$2%7cLHu36ITeKLo!r{!i5I zZH7KbZb6Ih+|=L;lDj3pXw!DQdvywRaPQ2&Ip%GWq>p2MwDjBT@#N;1w=(=T-&RO& ze~*@L8$`#qLvy^oN6Xio29WV>KmF(zK;~95wW?SC$Wz>Q>+&GObp|15_gJ!5c%K{!_zVR$(Ewg=7HT;_Nn43alLrA z_^9|h@g31<;2@uGWE%||*u!u;g5^yR%f&_F#o|@sP2w-br^Hvp55=#<5N>cV|0ZGw zv6nbZoFL8+mxz~%o5TS){h8lzaiTa=Tp}866~wzi_C4a`;(qa4F(c~c+gdbQCrE#i z>`~&`;ym$u@k;SJ@h_=On69ANrKEE5-scZd&&uZj71HiPN9i$lc`;%ITI zI7^%_R*OFpFBcybcZz$&gJKY$DJ(aG#4&CpHX#wGlh{S+`b61vY7aEY^$P zh&JYA(|!{18i`Hi-%fT%v6t9aJefp)7>x|1KVAOC@-LM=O`IkFYS}fS(ab=4qnQC- zC;uD7dqtz+i*Tde3mWZS@GXTK?F`tT$^Jq#+8L;45T8A4XH+yA8t^w-z3^`>f1{-V z{{q?FMSLunae`^b5ZN2@Q|MFz4)rw zP}9)7>WKJt3g>gwOy5$(gQCVZFEqm4Rdx@tzc^6j%ZE&VnpiAO6#42R!>5VoiVMUg z;*Z3O#7o7WitEKKVy$?Kc)R$P_y_SLai92w__g?*=5l<6~#ff66I88iPTp*h3Sd{xC*%yhIia!iyqjhJLcCjiP<%w>6aK8<*J6;@)v%*tGqIJJFCHs)6MKq-#bM$& z@eI*i|0Dl0*`9XceA$b{^Td_nD$#sTKzdKpaHIUUinoZji}#4X5`ReJ(9<@2Tk$^> zKN0!z1N*0i*jDTyb{4ydeZ`YRzF@@kp4Q=5*`C(nIkKmUv&DJhVsWW>sd$CBPP|&Y zQM^Uudm1eNQSlk^1(C08Fnq6gQ2a{#M&xZG#!C@1#9XnN_(K|orzqZOVnYqXQu$94 z`JxERT`68FULiKrIINZbjpA+Mog!Z{VSc|8UlZRF-xog;KNCG|!$Y#a6FqIiG=ASf zzByu^$QM}X-&Y(g4iiU-W5qK?Pus9u_H5C7uS0%|WSj4Iu+8^7kT1uuyq}3b7k?rC zQhY#sOngdwQQRfIA-*mCS^QQ^;rAbumm!+9T40;CTEMpQ?;v&&3q|ui5AjZt?P(vD z$(|=J6wedS7cUk)O~kdbuM)2ne8JUlnUxR%4QM=7@)Vg7QLorrbi5Rc`uJg?juxc&L{ zk69M}5}OxR4Ih7gBZs+ToB3f%OyqY3++G?ut+QfoJi57gVVA<~&#%OnA5O7Ee%Jca zz-gTu!yLzxOPiP9CfNS`<|03~ll8;xmPCF(hns0|7|fP_EYjhc$lDmk{XWr)*QDU+ z`cjW69$>cBh*#kmpf_HA1Gm3^)xP#NRy@}CCF~eVi7dWBem&vmZLAwN(l(kA#&x9*yAVkGBf-d*>+epfARte?%IYgg8iR)hBrweKJHQoWTuJ^oJ7Njo2j zS_e+Ku(u86DEnai%H~v&Vvdi*t*c+GPhUB*`^AUGuN=boRBU=@mv!CS$Y)7BbzeC2QapWM zICuwYesX-qS4vdQiI_0bz^!Y~@^o_&L z!E0ChhT7xtih1h#E37{8Tbelsqk(&xIqOn3H`y?_#lu#xHf`;$X2C7lYgbr@n)Qn3 z_KL0#ZwamM)I4x7-O1fxU6pZ7`r6F()|Sl8Z`U8Uz4(*RyGVO;B+G)=nN}q|G z1BgEiacu{s?B2CHp0??t_^!LNH#(c0S&e7C8-D`%y^jBZAKRUtIFvfP~0V z&{@N0J#onXG5ltt=Zyb*S-9D3`I8OZb>UTCf;OAPEppTaU*Ux zWEYIydroHNzSA@B-j|ta9oW6H@#e@TyT|Cg>r(A~7e!OHjNY5tJaE7XIQvpCsj#wY7cavtj=+c4d0 zu5pYCghVi6f+h9jcrOG}PI2^sr zLDV$*=#4m{>6=IIeWP;7-VuSjha5j;b$n4#>dvybb=1i*Jr^h`(Lmeod2IFU6rzhh9Hv&x<%Fku6ymz0FoO zLLX*d<|W3!SZTrut+j&t52(+0`b6b&YqFaHcNvAE}3UgqE4(g>#oj>6t@m`G+5= zJ-bHl&1_@UrbEB%rJ}q8PN?zDcW?{4?JWBw_I(;G9viz0tssudJ31=OL8_KRijtMO={#*bpFgF7$ zqYce|GJ_dZ&43n|S2)+}ffkroxX~p$NoICNQ`YoknYkJJP!_bn+{n!`crgMkFxPCA zLCFYcfw?BM!0-*nrv)|`gUqJ|_6z3x-_inOlc5E+6Qw1!z)XK9wZQnx2(-Z5ssuCm zLzGVoj1~J^T3~Jo2`wfTTWnKO3+zWUlUiU8GpnQ)*atioNiDDk*rtC_3(PHdK*k|v z_4jIlP3J*>Q)k}DjB7a*lUiVZVkMJWU^R@K)B@woaikWQTMcS~(M83Zq%4%H1x9}y zmtF{RwZQl^g-;8N=PtFt+?=eu7uXp-EwHBp#_7%(bX@L!4{?Gz*;}_-e;Tpdd7$27LYk`em zH$n@{jXx%j52g6Ez=qNGX@T*)I!p^}DKqqIf$?Xt!?eJfvPpg|uzk$qXj)*b#P1N> zcaV%pe;lM`Xxk5Ifhp=+$i+SAN7n-5d1$o2crrr^j5hDrr@1p`-b2tbkejw7~eIBDKKWR-Bsm64OHq>|#^&n7k7} zzZTdq#`kG~ap5b!7FcV>_i2GqQR#1Mf&Gy&pasSn7%i|1n1x>p>|B=V*8=OrlgqCK zMv11ww7~eT^kG_H{PB@mU~Vb+sXeI$#;)^gfzkGBfzdup3#~iO%)>~>&2G1nzJnU^*8Mnm#Id(~7su8f+_)C*d$Hd{ zze^Zzh>6F#r(Zo{5`HfuN9 z_;Eq171-NXEt+T9W3s4(#T;v}=Wk@o#+n+BPsidq*z<2Rer?!V>X&h0@BBNB-|_TY z3Y&{}x1VF#<4nq|Oq@s9+n)=cCX90ztZCTu3z%+PGx~7>l%HYGU&9_5cMSb5z@49& z*z=!YeTz+QC*TfJC+zKK&&T_n<8dzqKV-q?Lb&yM z{cMs^0n5$Bq>3E{{zt$I_xt`01iTV@U1@#Oj!jSKb>YmEG8g=Z=SXoYU&>s5zxGn* z^80ZFn7gZ)_0hI*@Pt|xQHc|WI!|M2 z>AISyku`?k?>=q-UFkfRtT6<0cLNT~It1^;)($S{cMvSZ=z1`J?(ioT8)q@G!8j)o zZUx4AMVf?(TpKueen3o!h+&7O#{6?PMg4zC&GI6wHeAbQZZ z@m@2OI|#SiCVAZk6{#ZJ!!o6~4J#&=V@Deaw>9Gkw#ZB1wa&ICc^&En`3g2p_pq)t zhnF=D7&S*X7A9@8d6Wq>#va3tBSyG~VC~iwbnpWM>KO!Ui~iWUf{w#Fhcz}KbXZ62}|oIRrZp zwb{6Wjy`Azj14R37=S%&ErbG1yIQ(OV2{FvUQD=MEv+%wQ7ADNyGgkWj_t0oaRnXh z2y_>5Id&d-@+Zc-nBZe|rV4a?Zu}<@EpU{eM?@4D=U9T@voPX_0meC*7?0iLK?lE( zA_@<#j@(9Q0eDC59QFk_2Y1wb8`5CO1^!PS1-b%WEHs82$66GurK7?%qP29?xJG*I9dO)ljD^*;bUf=CHMMlS;~L9q z>3GjI=GO8uOGkIBIl5QFBMcG2@Ss+;@4>wnJNj((3Oe{~DinN-o}3Xz;zOPg%^|o$ zim;-Vj-9SiT}#Jq*QlwbW3OvK=mw52vE#fYve7vvIUS9$L&A>WwhNUxm%MFdv3E?`&5-($StYy(!I^J}R^jbRh7-M0y z_5d7TVu$Jv@r`kgB{+S;mk49W48E+E4!+BRX_0WpXGwB=j!TZu5{}Qfi93-uCOIr| zst|LGvxHcR9X(TBO9#II!KkUFW20*qjJdsUY%ZhIYKzdks^xXICkOm4dHDoIDB8iZloCL;A>Mb zX4Ue!YxC^2wRR90MCI{GGzij&Mu@US!j77ut@&x&3XVc|K$av2NbZ1K zmR{={h1<+1RNs>OGp+>Q2=*u6NMfp;5w;`-pE^}+Yx zW`d%vQJB|&NOLs@?yj~{z`NHTvSz+V|Ul`pSt4v3p;R~ai$CqK8 zKRICib)d~*8n(_{ADp~CNOu$m#vg~nl{1^)kM;oU%y&Gm_!UI~vv&c_%n4$a9)U z6rZ>R4=BC80}F5Oc=C9&8`x4tY0zR_<`M~kt{wHwYRW8fb?tIXAzWBd>bo3Xf|+HOpfDv{b9 zNoOE&2)dOJG^CSPjc7bE6}w|Cv1_NpG2itk_<D+)F z3bzDj6DC5)<)|7zrO4dwrc6~w5jx2g!`fQBfEAt41U<*gYMLDkJjcx z&|H>UV+no+ny;O7@B@%l@unV=1|@RZIe;BgDZ%%2@L6WpdKYSL-Ysf51@USPD#3#Q zcZMmf^=1)Vn{e{rhaS2p`Po;o+xc9FC?**wt`4IjU^y9AdL^jwf!w zZfe9y<9_T+fg?ia$NPb&eiJfN~XGXd? zD9|P%)l~9)ql{hww_`1LYtO0B%tUltj~%Bc!B!dnKBxfOV^Vmt1PbRQ!8y=GqJynK zVz08UR6z`81XU_*U)U;fUjrY&IA!_8m%%(3oE!LE(i|9&{pwgL-zAcum8=24v&jDe zL;FtbVe5?bL40oC12-Qi@N6VB8@#?ZeayrkzdksDFHE@`Y9Pn=mCA2kVQb9#;8V6&K5KojWPOk)E;U!f7Oo@kDa`ZMy?AxQz08>i^OwU`+>9MxcG-Y0T_o_F& zk6z`1xm7U;+QiBw08`S(2)razUrHdIR5Ekgv=T(>GJnDR@-F3NQ)ibLDVP%cqA+*S z^zwg&is#YvDyJ=|#FEF92wK>q@c)un<&*dY&&i|OB(){aqaI!n6(1oXNb$#z<7C^R zF!b+i=j<3H4fCnN2N}O+Okun*q)M!$G4~SA9egtrN7~auu-8<(@+cK zpGx(=78I{caYj=Vv5=W}3q_%#m)aW6{2WsgXDFos^Ye^0V~l#2=M_{VBWho|YK^nW z8LELj>XZVXs-P>?=&BMfEV!`1Bu9j>^O`k+-LP;#lO}8qJ1rFMVYD36CWq1?od|V5 z7Lekk7dX8}IH!#mL89VoS3JlH6kbPpODbxnbPuIcu(A-z(FIW4goraFJ)H~`NEZ|^ z<$duc>i)8PMqL<^rKa zTIk%v3-cxQDhvfg6USNX({*dD{K zX)8F8b2vAKBM&XnOdcrL3qz6;s!c)}Vdq?wf-Ew_P8vlh7nz`@%%G1K+s8sAiZl(i z4mTZed?;%``%vpv-9vafClYR#3*RQ8tk!V1%|(@RLRrUzTE{}^Z9}b(31x94w{6k{ z>2UxTQyFyY3Re{LbL&;M0HeW4xsc-ljp{vMl7l3vPSzTvbIu-+$M&XCIyPl=D6J)` z04>GH{f8H@y%vy^!aq+j1c_G{A9 zM4V*2(D+u!F}+);Rht+pbOv=ek7wh$VVpKY4=&}ok&lL&3XkA<*V}FAz30c!0Xa=W zjo8N20;f6_!$H9b$`dt&vQxuZ1vuxN=L4}3=#K5nW1%+ATlT9sC&PtVs9IKjUy5bQ z&06C3c$9ZK`i+XH8Js|HFwmi1H5f9LO>@#>?2FbA2j#hq+W+k&=xV1&0U|n!2jD#J zizYQgHarZeM$PrSYE2o8c^)PXoa_|^W^S7V_sk~E5IHfiU`jx&Nh~|f%qwFk&gxET z_NcycH918Nr^=4;8O)xL=_pMwScp@|X44;}w~eh52D6C=9q$ocRD)-*XE z+Rg@?C1K|e%h2~7c}VPn*a*zgpFw<-tqtIdf}PN;t65M{4&}iG^GnNXW>=RQF*-;x zRxg-0)sw2L?Agbvs+=}tBqLI&u551UVS0H+(sS3x_;9@9lsFpDOr2e0^!TdEA(&S_ue@?*`TS|;Srwz9srvWG z|24c4!BObl(-V}eDxYR8?A^mN&oc_FeE0$f3(9EI@c0A%74jeI_8*PX8IX9a=v8I8 zLbU%Ulu8p~pM^=?&+bVllw+sOT~I~M$*SqIr_Y{0o3e`4a6pT)Y~H*wbAH0b6Lv69 z*trYl&y1OW<}96B#>6wAFgbU&5v8Q~ZfWU+k%*QYhEDHVzG ze^9)%0+OPIh>DZQl`y3)@ysIeO@6rQ=bt%GuTB z7F33ZP#n~iM#Z%^<}ZASTTodYV^foD{?|#G&M#kL)I*_~41LeCnkCbrfH}8!&oVPV zmQI~}u9*_?oj|ADKPG3Im_ffs*7V;;xb$D9JNoagH`>kn<`42lz)|%^2WPIdo$~^z zu7v3SNDWcG|C-!_c%~FLJrj47g692L-eGgMJ;SdTc?X#GgW_++UE*uv`{HM!(MLnNM(7--H+rHVe|4gLhB#HM5ibVQE-#Ojh-lM zqbCX)JyFo;iGoH?6f}CGpwTA+jh-lI^h80UCkh%pQ7{8HR#|>)v5R<;I7&2nLWnm{ z_W9zKqR|sYxX}{@AC6f}CGpwSZrjh-lI^hCjY z%pHtx^hCj-vW=c7Y@;U%PL;pW6NPQ`L_wn`3jRppMo$#>R@uK2A0crp9~Yk{)9^I3 z!i|0n?6>5XTLas{&U~UI$~C$*a2wqku$BCeC9$6%c9Va9*#pHQ z`Hz-ubV}i#B>!phpD8XDmx@0YuM~|wDe7hPY~W|~Y{0t}Zggzmevmfe8T}f#pHuit z@;CZ5a2x#^@ICqOC$S$CzY`sNAke>&X!LAgx1f!3I>^71SRj9+V}p1`#|9iC|51uJ zRy4Xc2rrjCNAVWPHu^RQUoL;6YXkdAg|Cyp(Y1lU(X|1$EBrq33DM}>ApBL?Z;GFY z`$c?wm~n<_$`Ia$*&?qOI1bGZCSV8I=A9DQg|d5z=0{EV^H)%&J6kLh&lMMli^Zkl zD)BP$r{a3?Uh&uBBjV%Y3*zs@SH(BQcf}9IPsIb`*Ww|OzrC9Fi}@m7rlCJIH^`pi z$>I=kxHw8QpTmehS@v?#d=A6^$Fi>!H;5a>ZQ`xsUE;msgW@CNQ{r>t59y5Z1sS%7 zzmAdoy^Ty4`LYb{e&S$pn0UH4PCQdQTbv=z5v#-{qPadm{;OnPA)4z2_-~ZGRlHHW zMdafMtlxd&L*j46XGL>;fq3uB{z$A7KNk;)--%qM)AWbPmx5?d5YHApz0g^*=ZcHO z^Td@RpD|}XSBO6q`TH~dH;a5Ti1sbwcJV&(QSnLf_u{MK+alkmVm^DtI+5=*)Blhd z;Pne^K4C~^ijBqQVr#LZXs(|Szfg8Bkw4%wpF!d&;%Oou=wtX9BHyB-T_*Bj4%+j@ zMdEqlh2kY5-_T?n2-3&lR-0CAW&TpTB!A(o2M#JOUH$X8oguWQ9^;;rIu#K*)} z#W%%w#Sg_##RFo9-(Qfwr$3r4+tVLyDf<}lII*+XLp)I&DUJ~*if4&@EtlopA>J=O zESm3M2si6KfV<^yzJI~~RQ3V!8_~kGIP*;xv&ER$UNqmc5U;1~0pcKWq&P-2-?I?E zM7CKE0=8KX0<4yQjkrp@Ok5*w5Vwi9iuZ~4i_eNX#NFZ^@ni8*@f(ph+)Vq$Y_XLX z6Zr}><4qFH_a@lpdlTCw{|a%LxKjLyXudBY{`IoAiRSwf{LS|z@G<#6CGHYm5#JR* z6h9aLBz`N}xM#?Er-)|#2iRu)2hgnl0P=Ni#_KN*5#!=$u~_7*-i*Ioyi~kGTqj;F zUMJol-X`8D{!)BEd`x^w+#ymclI6ZG?iN1~KNdd|zYzH%I@9Hd$B6mj@nV74Pdr&1 zCJq~55ib-k z5q~1C6Dg6v`adQ;5Ic#5 zVlQ!kI7mEI94U?$CyA7MVEGq|tHm|qMscfnt9XZaulQ^6x8f7x4soaWhWNJlf%vg_ zQ2a{#s~Euh9IR)Gm?1V5TZojZV7#s(Wh!W&E}kJy7N?3cL`qmN{srP%@hb6W;!Psu zEg1hXahLdtNT~~ke=SCGTsuw76I+VMiYJICiv30EWH7(8#Hr#8ah|wPtPz)q6xCq* zYsBls8^oWBzYy;e?-!}S!St_-e-Pgn_lcj0e-i&9Qm%vPn~BGW`Qq_nfrzh17T5d3 z>0;6WhWI*fc%tsZAi5PmB=7#@e@{32@Sg|&-9@v#-$vPo+|WlqOE50Dj+VE1VMXx35U>U*U=@CJ z&Bpgf{zi)==8=8YYdm%@4V>0!oO9p#JUr)&2JueE;5iAqw|ViV!oy$ghQW{(L_C(u z^4Jb?5q2*PoYob`Syqe=ZC=H)uL$`u8taG4phSK*!_73^uybo)2ph-4 z+Ze|EZqbX^0WS$I_97{a@p#Xk^tP>t$7AkoYzMaovHR;c($`)b>O}osfE#1E0x;Vi zkMY-q4sBk3_^3K8UJ2^=mKO>1 z;z2X}#KKr|`ytKjo;`YZ?`fj{ux9qHJUBQl-1Z)a`7qDw^2veGS3xs7WsL*H?3XWS zv+?;B*1jPDh^4g)tg{QBZ{ZxY24$~vHrssy`vzH)+ca8d9hh+;6lGVwT~B4%=o+hC zqxhw5;&HouF4SzB?EKZAtv%cSY+e7-q37G$CuP76zz(=}mk{jWnC*WKLc93Uw&ksU zpLY8YXbcbO6Ayfm6}Y3`itQ+hL9O>H=qaCk;pn|DWm@f``!d6g;sfG?;ydfD>tC+7 zwm*O9g|<8EgK!78N4rIP(%wGgvt5yWc)WdJ=lBC3MK%RCH@+%xDA?FJAp*tg^DfBV zvMHLg);bWp@b+lh`nRkbp>!SW;cU%VAA(+Sczs|?XzdNnGS_XkQrAT`w1zhedaXXN=k5B=*IW5p;w|FM;;o_9-8|kV9)T9`8}(MjlZT#Z`qH6i zCP8m`&+hubAh=`j>;Fc5up;GPGzE53*a!~}+Fc*slYTIo4m$?_{tq6sQ+Mx*Zm?@J zwjNs)-fDNY4s5+3(0R~-$_p~LzE*Foc^OK`s6j<^>yw9eG%bq1bZE!;>*LQI+7Wx^ z(2oAWt?9MTrR`4}yf;30*xplzb&T6zWZ9uFvO@0`cUT$N`unuE(uV9EG-T-B(}uFA zoiDPS?!_JJbGxN(u{VFwEVw?jCEDHYZ?6ljzhqbHmdK`N@tiGCPi_ot=XEXO_P)o1 zTdeHOjiF{8U01QQ@g`>@M!-t@fRjFY@7lDKO{J}JiY{*z*f-QkKlok0(R*J=vG<)4 zftL0`{1UP+C38YNyuMHTy?A(wy(WmhKQnH1w2lpK=usct(Y-#J-UC|aj~-e*vwM9Q z?(h!R9Zc_DAAoz+%pUcDbh~c=DR&%NITJeN&bzyUTkVa(eJRd^P_=HnvuAxu>=9^P zKX&NCnP=bqNPQrC@@3RfzHnx6=jO{EsSkF0{Ln=+zet1j_fWR~)_SX3V9Um$(3ar; zV(-o4t0>a{-(Jp|=e$adfWB1;lh5fRzUAR>!^qM{){0w{!-fPf<4t_(VCDw_s( z#$gl{6&*)$Km`XCmr=xJ7vd0Fb>8(n_0-c< z)z#H~x;s^+PRZ5%AAT*oGP2rP^1Ly;k@YX>mMxJyBxE+-?zYO zm0Q}g^n}tEN?*fXVUOH?_@(4)2Lp%))eBz+9_K}0mVyDAPhi|k4J0C%< zp1NWC;j8Swq;E9GDNE9RL95b=f$2N*O05p>y|%pR#{S2dqu0}ai&o4^X~o)s(Pi0~ z1^mvPO);PL^2qYi@Ey_H-MabTo%c|G%xd4RbW`c{&)kmlzq|dx%r%Xcqn|HEe_xBf zzL|Y}dqHFgd;9iLFCE^V*l~FK$&FUdpZxHljKz_aEq=W5&?|@EDS#Ho!j8l5;8=L) zq{|^W7_O9p~ke?n{k_f$)7UpI=8G!C5i9E~7c)Cu1Yw-{(?qrS-uVSJq6YJ?GaB-yOXca;yu!!uN*n zf!e|R+I%`3ejwNZS|=H>+(jr>_zy0#y0_8!LruPdX=Wf8;M}=r=1OQAG47rM+h~Dl zzN}whR2VIeB;hZ{i3X#ca~a1rvdb>EqFuDbKYNfUIwVTbO)juwpHd!bDhAn!orr6>=m^Pp@Sb)% zHpc(WH&w>`+Ko`O#dh?9$ZUEy?R{YmWApS+x~?JVzO_%WACX6Mj$N{Myk?k|MDQEZ37!bL3)v?eW~yQxd)TwWEK^ zHV@yES+VnI{Iv2G#y+OF#k7)>Y#O_U;`7aRqj*j-5j#v*FXErpD7KEB&&GWz*4~Ki zVtnr~`q!v=OqcAKT{d&P6@5h;DuIX!ys8THgoqmK)OLHvYUt{X>@$q3zA=~Lo7voe zlN^v;HWjYkmaBm=PU|1tt-M2Ge2+8wF8=S4#=~RXnfgJFd0L$u72{Lk=!Y3gOzN1} z<*d=inLL7>P7#%ltQF~4?mlioYdmuI7x zU)vi>`o=kXY!vfrd-en4r!fC4KYdWV6Z6k@@>-kxL*jfWAI1FIp8fE6Z*G6C6J_H# z$x-nKnU49jUo+($6X$Uiz1zvMjB)ZPY=z%S`$@hZs zo9GhrYtKei-Q=ENoG&UwF~4?yWASAW?axEO+eyE`I%Ovrk%fcNdXy;`;A87NI|p%g z&=gau{Qa4ZB+nnaZG#c=mq1}gfA&IiFk|@Oae1*XV^HS^8pZtD+fbRpOR>d_Xwr^6 z0gJd9OEAAS1@?$cRuA)Qdo37kHr`iz*zgpv5c{AGA z&Y?h8Tsc&gcRs%;%nQE(jI9$|>a8jIM5B zR?M&M?Z-fzFK0zDzqWZunvBG`=xY@7Yx6XLV?OS1)0kh|tHq!=n=Oj@wRuv<(HG~B zwdf7baa*8wl4IiMvX+=%+dJSU$M53y7W#5^ye;i9zqXe?JHCb6TjXR_qOcs%vx9<>8k0S~Q^Dhi3p>z#t1h_Vbv#z11JF1^d)&zB@b$%2I?@ z+0^yT*@F192#-?tD0Tge9j`rO2(54r1(R?ayDK11qpk$Cvj=2<0)P7;^CBsEKfdfi zS={cjrx;eMX~Q&@Dm{DiMxzvY!#&Oi~5{QS9H(m7^3F@xH4&%DJ-gMPxw55*g*|tJ3lX?#^MHz_J-)U5s z)cZ`Mx&pV?iV>1rz8VvKvlf@(7TJXeW>V{6js6N1AJ$!hU?#O5mP^$O5H}kYCbb?G zr|Nr%UmI0dsG3mKE(?7E!OU|#tOZqkU^NLL`3!g4aMQqPxZ}hJOUdm<*PJ`&8|c17 zNWN)w?WyaGyJO7|I6wFZlan)YKST}Y2Op77o1wfxkC5!od?N~}8-Y82Cn6-n+<_xn zP?v+dW8YB6yZD%GoVw4T`vk$8AADpsJ6#b|r5eI<{h}hkL}2)OWJwigg_t#SCaxAfpMXOpc01{0W#2`1ZoNLQF_rr6t{cg)1OJ51IX zA0wMRupCB95lrzPL}Wb$?tv|cJcm%s%*>|ZcR7S|w8icZVv;(PqmiBQ61`<0&o0=% zh0u{HC5@r^8qz-z@SiBmSA=}7wV3&G>Sc5w9h`|`GWaq!&K8oTzvLtXwgQ@PrYltFJ%7qb|xPloBa8( z%ta`s4O312j?lD6Kz`PUde?l9XZ}uh)+Xj>8}) zM)XM8HQ$x=SYl_TVI(&muSK4#>4a@mhsf;|=y4+=k02B?H}m-(*$*hY=DUg>yV{w9 z>5=_lJMz59e6(Sz=?5P{^A7~ok$Tsp)-Zn$J8O+!qJyyd7lJ8KPE-73M=&Ki9+5T( z#mvooeu-E|%9x24-CPcJ%Q9nVH&6b07tVnn7O6#MynkKB*+y}ys|T2$HcU17w?Olp zm!CDdin+}9b&L(LvoOi6g-Gf%-qc9*N7e|yXJc#J(k*8 zIXF`rk4=&1I0WOd2O`}l(Bm11oQ_b;+{`DBW*oVXeynw#=-tVgpN!x zb(;yP7D40B2IO*1%*}kM9{)l=W?H%z7^}hY?|Zxo zc@`iTk82QFMS&h4MtBIJn7NrR)gxusXkVhoS{(nlk}$P?0eM(F<8conA5fsj?-9O5 zC}wWv^F8wT@8hzJ{5F?^y`6%=^vL5s4c7<}gknF{9RIDMX=Sb+%z1>lT$8tyo_aey z7W(;5g4K!4PaCG1{3D?m;pOLkq~0~(gT4H*H<7>L0$?&sD-ldhu0Z5+gkt8Ry=v0M zoY9P@1#Fi-xbst}S}cYAVuX%NF(p_J=>Y`vVCEZT@~!al^%&^qdkz-QG9Ob+zIP$L zWAd5N{cPlO%%sTYA%<7>Fy1C2av=ro*=2~_gwTRpq%migz~ znQQ(0aaiRe6w`*OCVvq$9Zmi&YzgXJZ|29V?5w@a%XS?Ai+%{EB`!eZdUI^(A#H-d_sZVenR9&gknEmsz>^9jkm|?@mf1;m+vvV74D=W7>^wg zIe`K__C=%*LNRkQpI=*^>7Ie?n3Xr|C3a>OPrlq|qhUW1p(B^#Fzr1PQY`{{*6}dl z{Twa9af_XG9`lWYdLb-sKELNRkQpI=6Lr0kmSUG%uZ&Kl0ME^B-?@{FPr*0>sxDhl*?Eh1MV z6f-yT$)h=YehAsICOhzUuAO-Uy|LX_!F~loN2Zu|e+bea5zy}JQ=cQBWu`{3FR-&- zXFj&nR#^N6!L-x|h`dLEE%hxT2M{_gfJeWT=;=#%a?STQh}jp~S*_6@jJHT@{76SI z-dZ7&pg?aYBGMh9n7NtH_sCZI4zg{&4>DF}XI)BN#Walb{udaOgb`<9(S;lxYJr&{hVJIZ9-2jfkp?oZO-1wRi9A5HjqwPtb;r2(w`8*uuVbN<= zSJ-_K&ZLK4vwC#1oW0>p+F2(~omyi#`@+F;Bw1;6#64;5D%#e`G;#js7r@*2-@;uQ zHvYG8--eC0Neree)YdLlhci<;I!}(x%a3_>t#0?;`F^aTIk9CNS} zp6d|-xaEIe8*AkHk01OXMmDo>ohq^Xh)SGQN9UZd3Rc7p1XN=Ad`A3|AGL5@fX&_T z`3g}Kji58kMLvXU)iKV1B;o}VHH$uZ6&OyO2Ujp4SRX$xrs8n)xb=nK>08`m^p z-2d2Kgo_~^@xg6Bvz~=^=TL}dM={bC#+aL(=m^(F&utvh5G<-mVdPT;dl>O*HO4O<&bO!mF1HX;_7w{Nzsu({Qs1w*appHEz6X($!sBTc zYtESE!d9OnTZ4xO@5Qm*NL(DDpl12T5wK+AEN)XblC5z{WJRRj32*wE`e2WGRMX3Gnna>E{jl%jHY=GSeEH245 zKv{^N5sVu~`k>9R(gZQyixLw}bR@9=!B{iG-38|jJL)X%sHR@q-ZP&OZ%2(~_4(mq z6I^A>`{M!a$8Bugv#_jjh*Tq(b#$oEd%s9K@V1!hA%4Z>jEHpe;j9{F%Eq$4B z-cIsm#&@R3EE9j$`ss}G;uk9rt($K=QhLBxU_l9NVH@JS#P@SB&MxK4ssLWQQ~Aw7 ziA|c%|5S&wO_{J>1=g2foVQRzmM1g5IYs8pEZ%xD=_nNAulq9cvrhbp?B{2EhcCmP zKjU_#$c*y`i*L`L8(xjDec1aoa*x<2|JxoJZ%Tuey0DrCasGrcJsSQQ_e$&8`=t&1>e5!4tz%I!tmVP@!W5ZtudTgw#=lBU$JTk{ zAY^&zjK7s4GtM7demdh`X+3+twDn6~a{6j08R~~~*X5FyI3&ym!=hIAqs|NLZTxuo zXknHOK`wsGX~Oes`I!0!ALZFV31)dP9;}EtH0q0lZ z1*5MH)G_j=r~e#iiy~qOUO%6a!Je>aJ|pGKrj?q^%)5DYk{ zV8s)xvxUX)D06RMQ6^u9RRwvb;kbx}lL!Vp|Cn9J$Z}7(td5bjo-ntLk@cQ1ua1$& z5pc30wt0Fi=7|X3zQm;o!TA(jtJXEtN zEWq3%wnh-%UDHbfb&POy#^oQum3`2nve**>b&Ra=1ndt)yz}Si4-n-@ zZQ7lY5V{@eM5LMMD55z6S|?D)NLx<`)iKiE2v`cSHzIuzkeL{0qN9kxo|YJefW@HZ z)iH9m(T^g=n&?>subHqJ{gB(VU&l#!8zMn9T(%0$m0odU>q#Qw9YLdZBlJO!=_;`VktMLjuCcG2wp#J?+Ky0K8P@&OzfIoCqxeRvAGE7Sj*?LH?2TGJF$;^ z;6;B1)JK-5T=xw}3m^G0WATxyqjvsRNX@irf59i*xiz+kp@}-S7FNF;66$+K>!yAJ zmFo~N1Q0x8u{zqkqYqvFFgn^Nb*$MjK7ZvQ#Y^2|@>0p)C+J=N&y=IL>sQ{KT2Nl^ zEr|=!vv4?H2HfgJ2@c0-^>wDz*P*aRV7s%yjc|lJs|zxmXYyZYp7)}=VbLk>GiE?E z#T=L6H1$pz7y6?=cK%wJavM1I8_dJ59SY&B%Yw3$C@i1ru!QIeYheD2$#Ndy+B}+gJc!v?19JupwAis*kF(N;JeT5iIe6oBH4U{tBCU z&=n$}S_Jo|pTsI2dj|*x=7UPIiYDN=!H3s>Jh>SOq=e#mHk9h^jjeA91NM`%5Q4Z^ z!6J@~jzhpOMT|$lFg3r9k!l3!i5Uo5#F5bj2wd=Q1-J%*Nm$B~(R&bZG!q*dQU;?) z3t33(JmO}S(7J4X9V6xuvUQ$$UX1$S7SZq!N;U&=UdkC6&KZ9M0T)cfQwX>-hUF#^ z;i=8fw;OR@w4vnwd5uNo4lhAqz2S|~J_xuoLGZUSN=;mdU{*|I#JfVfkf=gXqcJ)c z0YxF^A()$Vj4bl>#A1XXS5Pc6S8qH6vLru)-bLETG<25c2q*>79s$>y^UV3qySN(3 z)7uT63E}m}vj`rJex?26DPzbnMY{~z22(gazGahC94~G+r&LY#Kq3EN%;;EpVfD#|S(0&@p zdsh1qQ2Rk4>`ca4a_kQxU`o4W&3s035W*IO5SFo|a2x`z?FrTrr>Zsc8R>yw9HQ?r zeij0bRDxa6oYFo(wKz(m`h&>N5nw}jHC{5v-!sN9>&f8)1tT;(4kB4?WJSr%$2Fq` zhlFF++{D|}IDSJ&VlsPB!#%Ukb-S@`7VC&LH;qg4cH@1BVl%w9{J@KH!_AM}xc95P zsj2V?FE87IKh@bX=o`KgPvxPE7-fCgQAsF5MwxOumv8|Fg2*vFp(41%zYEu~{jp<*;eG%`-ou9HIJ@lycbhZ}9r9 zjhyCV+jO!6A=NxZSzp4S%|o>a0Y}QB`d@FBO%(&qx}Hy17$vVDaU^pcRHvcG*i|P{okic=d16`nS=1*DhXnz}Rlg>l-6g*|5F( zcW3>ZTMa&#zw&4w4a$ZV!V8k#57uLLihYq%Qg%wi%dtoA6xXhTdCk$AY*3~Yn^u=1 z9J^Eel+;b)RYSc!o7(r7|1tzLbs(kRQN@tj)HW6KJljx;EmaIDeYD}l)}wceZS&69 zb;i7Yx1=f?nza5^)?;@I^LtlZ^*&s?L0R8MwpqMbw+{ThYT5jq!;tbz%MCXu>wSh& zl=VNQc*deFf4P}o_KYy3-pNVrwtjlb&S-c^_2~T{uxb7jLQ3Hpl;%Y3SES*^)MI-9 zJ#0SGi)%M1Q(EXRuzCUE*gfT^q?E+A8v3rW1Upl%R4a)kaww*pW_3y25G{!m;HTs+81n*fixWqod0a zs!vHN2X0Eklo#TrwQ=j*uaIr~DXHcu%K8#A#|`kni*Vly@161r+?Rc?XaoGsM#@|S zl-tjUsGsMU>wyOI3meQYY%s6Ch_W63bv~b0nFoqVj5-rez$BYJZ1gq z(>2PqNH7OjLv5&HNa>NTQQQaR(T9?2)08PGg=kP7btus;^lo83h z#j_2Wj&4TF=KUU~q!d0?nbH8XN_|4t(1?CYiVxRrP}Uc|;ib-_8_~93f%n&sEJv!c z-iP-Z=UcEmwh@`1DMyr}L0R7~olwL5ta@cIMVWFuehzOg8xa?bxG0Rhxj@KUOn)9?|)Ktsd}E}7+yixiSRnY zTL|wV>_OlUP6q#zYO`B5AO8oty(v28{|ez7gnuFYh~R(zQ`*l==g#nUh%x2)%|Daz zM#Ej|Fr`9I08f&6r+W3lz6DuZ;?V0FO(z$1+OS*NMR({d+nz2aiR5iV- zqEkir_$gztHZZp^c3Sy_$y2H-tp7KB*UrHLyZ=XJo;qdx*hv#6998z7MO}(I`!)DK z+`@ls75v}nk?Y!a?v6zvu^T5$tDRC?h7uJ`=J7$RY2`B}LqhK@n^;jwWjdR-_pTJt-&ACK*=luM_d@SUS#mJil(~?Dr1eZl` znaB-hhU`Qz%gs*&Gu?}epl#`9+WBU=^k5biN2g(NW3I5C=shKoXy(==;LmNF$m5#k zTnW9kS+G9f1Y3mMYck;?uOPo`$PRGfbN9d{SeZTK&cQ~0ttAY*{5O}uf?$Ddqe5JG zy#Q;~WA*d%6Nt4zWx56nnuM^zy;0e@%Q`!uk=_meQ+WeagXQv_Tx+$ z18%UXyWBx5=jRpY!AH}OJG)-;s(COSiqvZExx_a4mMUK;yLTu*HE(V!w1{b=K`?4SZ;ZIcBV+me z%HvmYeayHs8A9$>YzlQ`n!7QEV$@p|FlMrMWh^z*b2SZ_9{#nNwjz^XygF8_-oGhc z$)4W+h7RGW78>oCTD_A}%DP{> z!M9RMx#rhqdMBln3y&@3F(vyZrM<8J753kvGiG=@&Fg)k&h8~y1M=3S?-G9v# zHl5)U+}}dm7V)b$zY?L=dEP)7a`Ok9STuC1IkNU}=*`ay^$vLlQ8eVPneQE3?|VrY zE->stUnl);PhW4pcD|j@in*U;z!yf4etwRdYt3QcetbkirVBkBwltYOQkplqVl#`C z>BA!ua3n9QwcWOMun!PkefLsPsXQ;Q$Y7JwqBB&lakDFqz?>D`gHujw!==bH}mtIs0u z&hUEEZOZq5=PdHU40EELWfzTMyJt3>pH1zH*nvXs!t|rg&-=V=mw7d2JN;KnRFBR0 zzZ&ZNjJ-LQXXVy7$KtGfLj75})lp|c+%`-)5~z_f}WDo zo4dP6ySo*3ck13AZ;s#e1iMx<>`ixeA{cAOd})dQJzt{8TvV0xHl4#h^xS87;9zt9F!P=_W}I=%VDi#YgUKTrWL`W<{}}WfW8OGoD8as1 ztKs5xC4?{p)Q=^1D)F@=#uDVZO9?xVPPhj{6OI*hb=Tc$B@!6=GTf)pccYdrlF`mT8SdF_3KPgyLd(Yr`L$}WxdH8sZrP~V_so@s8L}T#EvTLVeiD_{-Eu8 zgLeH(_^Q#Ls=xP1kg?dhzjonpQSzCckRZOd> znN(3VVUATj4DEm-^yp>^jbheTOt3EL(bX5{nCjy9JIY=)(ZatBm+-4Izq;_Nt5wE| zm>pF!WBRNKwSEUEW9t~lHQ04!Xqeeu%BGZ~aQHvxnHAP=hK^1Q=zLO`kW6K9pzRCel;=rpWrqEltn^iH)iYNkv;uBlVXYo}mebgHbJS%tQr zUeyV$MAkw#v3y2(s$5y!X~OiX88zh-W}Jcsx5}!!gJ2dFwJi zMjm7wz};MBy45Vy7y0q+jn@-vr35H9>~4VDqU;}a>TH&Zr(6-PO6xJrmEoX zLDNn|1My#ySdGp1i$HnrSzwehJ(h-pmZt*kOh8uuU0NPb7aG0bMFGDY&5*o@U|@7n5$2~#SkR7~`CUj@2SCC*vqT!v8? zckd?5MjxoH;BMgnud&iMhhLuaLdMy?BAAG#rUV_>2CTjyrGU*>H0Z96Tqb^r8!U13ly_eWeEEV}Mkm-COjvOaeiM8UD;&tM3aizFkL@gE0(nHCH_V{TdWZIzAEjm z7MF^5iW|gd#aG4m#V^I5#0+$2`s*Z~Eb=)S^_-5IoGfx>3d(%eMLsHW7GBEiPGlpo zlh|7{Yuh88{|H07DdKE#qqs%4X(FfaV0wi(Q@mEZRlHy1oXoV}E>6X;KzWXMy?C2= zzqnO=UHnk|Mr?*-lYTmhr-)~Y7l_luE5w_`+r>YMe->X6|1O%fxv?D^FNAS>Ibu@m zCY~lP5$_b=6Tc9{820FAq&Qxz6)zL#i%Z27;vM2W;vdAPM6*^k{J$glTk$Z7ef^8* zV(j9Yi!l=Rg_4_!Ev4@$*{o3w`|i^Bm42Xjy7Z$Yn>DIoe}VLqr8jF-Lw||%bERJ( zUMsy>qZ)Q*jcRbE^k%JU$Y!l-(5z7nKCS%E$(PJ7tJX#1>+a*hM^%M0@s^Tq=$h&lM+&W^HTuzg+Ts(X43=y;;*5yi@vn#Ro`i z=P}7oiqA;DUGmG~>(ak3`5)rfBG+VOJ#F|TgJK$qkT2P+ZH@Hi(w`uGC$Wq4r%3K6 zju1zS=aFdR2_!<5^flrv>8~MSca!9mO21vaOZp8Y?93Y1h?}*oQO@nMdqs9;O>5YF zBKd&QzZZX$K7z{+`pYJvYevFfOR=r=-AEi)J;i>~pGm@ggm|{}<0V&$Q%P)RrqZvJ z{#tRN^eaf%-6{ExN`F{5P!%7fMRjQs~n|4_uTdZt`oiw8xs1~$rTV-9XpZxVju zViU0g3A{;jdQuS>ghvUnBlb`dh@6;)6Czz#sx6*#l&o}6^ZS(6+1{@EcTS%tXU1a-$;L^I6@pRyGn7oSS!vI7l_xA zD9?@JO0iD7Tii%uyPL%4#OK9V#Mi~QN%(zN+$SErW_2jX^P46%B9SjwY$|<1^w+HB zG7YrrE|x0YtYM9E4wHVQI9BQ7#EYfBM4TyJr}Ty5GVwNXt$2_4dlKdNqv)@3y+!hi z;w}>9dQbdB{6hRj{Fiu`gx_DpM!BAxFE$q2lki(4c9q^=3%jrM1I1xVA1$6MUZnIY zah7$&Zt>_fvcIJs+c_luTg=S!{N{*p z5_V0**3!2VyGnnO$Tf^<&-IL1K2DoPo+JJF;za2ui?!0v5w8$$R{BzLwOA*v6W5Cm zli2=a;`8EP#aG2WB+B)%_)qbG_@nr<=;DVp{f5Q3*o?&ZRz$*I7m-VrP~TVbKyere zKckgiDg8y_bm?bHo-1BYBHvBo67epj-zWY-`iI0#(myS}DE-UgYvPAW|5W^1{8s!) zG?Pm7zy=Sle6F1{oFokYLh zPoh5GiHD?ja8rx=keE%vPn<-)cG7ngJ4@e7av$+@68VOSBgKhIpDbP?&J^c~SBck? z@bg=7wRk6q@;pMKypM~|id)1T;!g2zB=UVi!tXxuYmqnJ=r15fN!Z220_l$v+eqI* zEEfAJeV}-{^k<4^OMjloWns9Ti^b{U0;OLg-YES|;;quJ67QA%4Tug|q#S=*QIf;ayQ^f(|C=%NpBXU(2$`xXj zSR>9N;fD*pkiQj|h_{IMk?`|?_^9}VxLMpPZYSaIW$}ISBNFBRj)cF1;=iR2HSzRm zB3EsppC%;oalIDiD-ll;PZ3MS!QwCy`N~N6sSu}#myz%{PrP3It+-rVA##Zp`ngkl zSbReKlemL~-<{$+;``#K;$HD<5`MoG-KL%#6=Py^5`J5W9mHa>r^t0zXxEQ~-_yj= z;`t=nWhx1~YH_CYTw#U!tHhf~_*tg(d!%0{J}f>aJ|q4`e38WV-X`JaeeoY67gFK& z{w4k*x|kZA`V28k%qQWev3P=5EOr$KlE^o9oN}+tWxL({KK1Ratli~{`?oYfU{wT(pd-`_bc=7k*-$mTXHvVwC*$}sZ4Dqwi z5W}t^n$fV0c!Jnj>@JQH$B1R(1aYcZEnX(h6R#C-6qky(inoh*iqDE$#FxZZ#J9zF z#Sg_##ea$i#Dn5bBG)`*dp8qXi|xeDqIqrtyHh0(5C@Ax#dE~-MXsMn|5u7Ph>Ju{ zDZ}(N;@u*bR;2zx(L8^F{G{YRi(AEQ;+x_wk!v;5&)1@PP6PR{HdE;$U&4c#b$uoG4BcFA-;pbH!`L8%6UR2<5p|^6jE|E(HApk{=YG7q^Q$#WzLs zya@UJA(`{-u)bf3T#u4+SJ6B-f_$oE{>L%X&2uDhq~vqN3&ru`6mgn(sd$;l|G%O? z{@*XTO631uQGQV5^dXf0Bt9#?AigBNA-*ksAbu$B6~7X{7Y~UJpF?3gAu%R$sZi<* z#in9XJYFmjyNM@@r;4Q_|8I=`xBxAAj<`tV{~%M({~;#VitEJ<;?v@0ai{pExJTsw zhSAS{k^d%1Ie$K>!v-&-6c4iU$QW5vnhRB^UAS6n167T1Vt z#SP*{ajUpZ?v{?Yvvmy4iU$QV@0m8OuH)aGI5@` zP`p_*&jVrqv}CT^%ltdV_ryKom*Rf$Cy}ogn0kp>VpB08b`-g2HSK$geZ?Un7X@be zSaF=l^<$}DD6SIk5FZd96rU2G5nmEt5qFCph|<#WX&L#P%~qu3byHr#MI) zB90Nqij&2u;%srQc!Rh|Tp_Lz*NN-JP2$rc7tUpQ28koY(c)NfoH#|CCUT)@=D$q5 zTD)GoSzIcv7VE_O#0SJj#V5qg;#Tpm;;Z5=(LAR`IX;s7nfR6Xjp*q4DOZnXxeLXn zVp2R_ED^hjr-=Q;!QxQy9Pxb7JRin(DkV=B>Zmn`AB&&GK9?{#INrn&-zzzfnC;#=Zw@gE|W(c$*L6!(jV#D9w+T)WdQP0SVJVso*T*g-57dx*Wn ze&T83Q1LABe6dV4&!Mq>^Bfwim422uPrORJQM^gKRa_vOq?fPE8ZwB6>k;Ib87g%Q}Q}- zz4(}Do?FB2FOpvnUlrdF>#6?UDS2_)qa)qIr%DJD1OQL9UHWW{Npt6S0NZPV6Xh zoowbiQS2l37taufiCiI__VYyZ92@eDl5ZEyb8P6%b8GM^>7Nsy7tM2Qq`xlt9r1nf zfcU+b#^<-N&lK~;#$qe6t=LKIES8Fc#S!9Yk;}c)|9tT}kxO4wzeMz(Q{N%^F7XfI zLn7CTXTF!j*Tlbx?}>ZF@5Mu+c}|V|<~cQ(&gZqD|Gb*3%v0_tb`{NYYUuk&?k}D$ zo+*wJ$B47U%f+k2>%^PHCE^Nkjd-_szqnD{By#y{miHCWJg0{Ij^s2wkIfY0ViVCk zkA}T@9t{>r-$m>r_80x<&!Z(*h*QLw;vCU`-h7kfHR4+Fe(?|Dqv8|d7V$;#O>vj_ zjrcF|-=eMOsZlW|9{oJIkM#Y;)5SBz(c-zHd9I9hnkadi=s#bcBl!yP8u12kvAA4Z zE!K%oivIKE?UG*>-xSSrW|ZS&$)Af~i{FYv^&Isq@dB}2oGeZiXNq&g1)_N_jP3nS z@-lI?SSLOpJ}5pWJ}GV$w~4QcZ;0=Sd&JMgec}(|VKL0-p(t0nXr2>8E|A*8DDXW~9F#OJ8kUYeLA7KqKoR^mzGDWZ9PjQoQn`_GX_N}ecA7Uzgph&PK% z#k3QEP1K8QoLP!P&ChhvAriLCN+B=--$85Ak!^{UG_Un4#yMSz=4kf6m)O zaxbwTiR}%SJWBMR=T4DaExY-WuNIe!E5rxIN5n1Si{dWvJ<)$o`>o^vpHHH`5wV4s z6uC?_(|d~Mxh%>*RPtHk1aXphg?Od7RJ>KZU;KmkocO%>mbhEoCw?tjdY%{%{pYET zC7b7|D7Sf@3igx!H1T}Ve|}mmd4_ncc%xV+-YsqvH;LQDm&G?pw9`kDKNAm%KZ!Yf z9*FW4h{ucO`6u+|c_-Lc`m@FJ#EZr0;sWs+@iuX_xL({KZV}CMOl)VD#Cs{8;>6JS3*I z@XD7d=9B1GttGb;PZCcN2a>QGDft|6vN%<|LcCI3D&8vIPQuT6$s5Gy#OK8wB<$Xm z{C9D`_??)RfF0U9Q*0q7#U5fWu~Zx^P827L)5TixGI5@`OuS9JL%d7;z4%A*8SyXT zb`tg4CHXz^pW*@0Y3bD~B*w)iVv*QI93cKiyg)1$Ys5>%8^xQ%yT$v(P2$ty%i?R| zXW~BbC(&xVqbBfI9fbcoGH!`7m7EF_lWDnC&fRDuZXXUpNn6L{}%0} zSKb`4KI=kxL7G(BwjAg7rAmhkE`V(7q6%Mp!lq~MZ{w()30$G!`K0a0TGW=jEvi$ zhQ1ws))+Y@5xwhls<)QQ|mpqBvQcD$W+?iVMVR#Kq!rafP@> zTqmv&Ei&Zo47;VCB7%_5kD3`7rzwui{FU{#h=88t@akP#5}Q3Y$_&1|NV~= z$=$@BVsEjpI8YoU4iU$QW5sdeL~*h>Rjd|ghzrDP#2ds#;tFw%xK_MJ+#qfgH;GS+ zo5ii-PVr4~m-wEzNBmgaFMcN;6n_%A{tAzm3^7a06BA-?!sZ`-%g_;o>N9 zj5t=DEKU`x#TnuP@fz_4agn$}TqF8^^Vq*|FS=0u%qps#Gi^rscn~u!7*6(Mn1N)5 zRb*zkC>mc|YZXyZbj&}gTSb`6rD$Ts_?eTusSy+}A3q+`xum9Y(t{M^a!i&msRDi* z@*k_2%Bf`K5e2h~CQP3;4O5z?=BmW}wJ_>;)|o}+Gccda_?a`{_E&#!>1|=RoBye2 zrf&R7`Jf5SrzO5==X&BXc1+{vc!UVTf3xcdo1?eOxd8l6K#@V9@0%*Vvr&NSC;#K8 z4TJ)ZfvvtuxMmWbXJJRM6IgUxWDQbHYKexB~H87QL)!y>wkP7 z?4P-j-7|{&Nn2sp*B3x;m!GE) zQp@)=%9jNl%ZJ<4_2v63;%J6yz=IDomX(=zg4?BkZZoAD zS!2-u+C%4me1CXkaD?3slGQOZT@LPO3ey>@@re|>itr6!*wPh=+(C!#>2SP>5KitZriZ3e`ImS z(#`u%xhk>ZrQ@zD3@^1?xl8TN+mFjylCko<=8@8zrPe;YXVKo;fAdvo2ZGM~2NN6K zKiG8f%U{@c?JONzYA39gS^M2!{>~MLtZ~Z^p|MUWIP7G{Als1bgx!g9aOd(vPTv)W zoJ1a^m$IF2!_JKdVZF*aV5i-+&x*LKMxM50;E6lS_O8mb_D{UZSv73$&6(*30)fE3 z%#6GCr3I~)d4~cW^A80w@(#Ik^AEXGmp-!Kk^Xzb{rm0>^=)<7%Fa9FAl*T_jdc5% z^gy?JP759g1b4r-e_;B)%)s!{wV#DozI<@VTIaBp<8}xy?fcD(S7xnV8OdK_?a#TY z{eIWYxII$0yJ^Q}PZg%^$IL5BKP=o=_;a%xt?Xq3nx`$REzDfzu6CBLveK7^S4Ec} zH}L%avBkk#^Ol5`Hd+?EBf6sCP-sWNq41XlhcG2@s}?`re0bR2jKM8_Ty$vIUVD(e zG_N$jH0w~HcNXfj`jIpCrlk$o8y?X9usizny^%<}!|uR>LxDwh-Hng*+Z*ZE@~}Ir z;E?-eiyv<|IB0L?AfzX=Q0uHi_L_o2&W@#Mk7)mvhn>;w4m$(=t--4e-6i&tf!cwnKKwt=Pl4ha(nJM#E}gfl}=bv7NUaa!LYq_^w9E=-k608)GzNVVnKK9&H`WOQf#~taM9r z2Zokqt`77Fbbhpd@YcYR`QMFrD7-R%wR70b4KK@E6VVZKbLYxKwzc$-o%PfKyAid)ol6fnuyGREhn=qPvi9!H z2d$FG>Wl++hPy8#UKw2NuJY;}smof8T5is{lg>N%iWjdck6~ zsrP`rX#-jvc9$(OwXzQcoVQ<_Ij~^A>*Vje1+~KQo@Mu9En<*u$aa?9-m4Xk_pDn~ zE4$CIy&vU<57=SWZV_s?b>O$O_E%q$IXoJ0QdCuYRH_xDLV>_1| zvKOFNRy!RE(a(ZAZ$yAMKOAbcw*RobALfKg*|XYLR}4(wSyF0sc<;69rfd5j zSK6Te7OkA6R(|=5a7oT;tHbYiHZOfNvbZ!{$`)r^&;M@7Lo-Wzm(KnyZ%O2i=RRdA z*S~hlXAOHKQb)V)pIw4ca(L;~PpoH`^0}fJiUT&^+0Ni%3BQAaKLAoc&To<6o)GU2 zB~~Nm`3@Oi4&qKFXsftf5UhpcL3wNkulIQ7iVcn0WXNq=qZ(_zLJEfzW*} z-`9^WM6p8aFeNJD9bggqeJ=G@T5o)vhFCi7F*Q{rba!+bF^iJ#aEMPgR$G#0Io#Jt!(R55a@#KIW=?;z4wV$;~g%-c_5!pdnxYdbPH62LZM zmtwC*&PZdNt^OfB4~bHAlMC$F!%QA(DhAn!@%~|Cgk=1HOS={u%Y(J4atkYG2e!7@ zj$9BKNAIS+FU(<_-nrUJq%7n$K_JHc7b%Zcn$$?l6l{ERHkO;jkM3ZAj??%WKZCXq z3~(i`Tsx~1ix!y~c>rRJ@76~y&1Re%dWvbY{0+eqdtDZPz)y}m7D=L#*=5yMY&k17g2qoP zZ()qrhLJ6%m7HYL*yR+TZ}t}y&q*d?T#+U6VzYl5v30C18~3GH4&Wr)#hzfD{u=FM z#E#jRa?gsqq79WmL?xlCrzB2V49&5wY4|4hgPI6T2eu^Jv%z=@U922WyjXuug5$q(# z#(w06K2c|zXyw`5*UXx4zSvvxujd!_*e_=ysS%S3mLg}nKxCW~Ve7;%rr+_73T4GP zIap+plYXzMLLmME(c$UZt-Why=p(bXS^?WRSo6`HkvS zeqg*Y^Uw0r2gPyKWkqH?c^M}EkoX)nd~4w^YWgL0h{e$td@Oq|D6 z+c4%Viv ztsWAHFJ}FZx79-;*di+)4A6byF!;@koN7n-PXX~Xd`0@&Ip#kE;3~+*?dQv(IRA4a z(%;TG8>Pb`Z>2H9e;-h>8}E!PaKe4CYvOOx^eU&2XET;+B;~7}9B)4c;`3RdYn&_^ zJIP4=0+#w(C(hG^lWZN|$x>hEH1hiCpg8~8B67XcaiQ@yJl+9}+~6Gd2k3FU#Rt&- zMyJ3#;3mh%aeE7WxjNpA_P_Pz+3_2>y+uyeP;8$gdb}qMZgR3NG>RMScoTZK*(-sY zTx-X#q{Z(%7jE(%JI;TsiY)dO>+N`B6h5-VS8TN7E!lueeZ|vuybH4|^A%g|_*Jx6 z?j4WluC|rNGc`+P+O)AJvrtA3dvcX8$F0WuBP(%f1Vy|r+jNc7gaX^V8{6!5r||bi zo^7RZRHtBEHM7#Vb9f+0K5lhZT~AjQ=t`V z0uwtJpsK0OVZiimbg&!vGP(-r zMk25mS@!9Tm^Twe*bQCl>e-e(*qFV55==yBT|LLL&oHXHup7o8Br90DAx5_hd+$nw z*0nRIS@xNYHpANx1n$Y?t*qHlQ{px0xbuRLywm8Kv$lP43$8apa=p>Dr>+L_IE2<0 zS@tlK^PiADqUK^~@@X>zZ<6;wNH%A_VTIJ4fXknBge0evw1>5zj&CCWgSux~-r>gE zZMa=^3qotod2Wx$=FWQ@@&<$?=ESw^QKk+DAb&(%0L@~L%4fZ<&$g^t2+63?HKDF8 zZmSg{Br}b!C3O!$zL&bzEZ=D3uO;?AXC6v+FuFMHPQq=u76>RyXUjgj5&z?*6W*5M z%p%Zrfi91_-i@&*5n9hKvFvj)+0zE#&h?21t!E?WIXP6Vf_Sr0A>%m(RPkT#KQXGV zP#s6rDNXSoqX?}r(Yt+4bE^0c?^hcYeYK*>!8rI6RBh&=d9Fd&&F20ioAyvXo2&!| zMF`2|Y+6ruCgcGKR@=q+3gLd}@g~PMJI*Y3AZZOkJCj99tL-i%b*Z=A;n_Y4yNBy- zrL@{^fbE6#wy%1&+hE84HTV2VX|+8FTTW5umEm>I_I=pBTW>3+)rLz7-hseZ{XP5R z9aH9SV7tHGUP`O&3iOjt>ura6w$bJo01&)#NNKg54cp_;2|d40I;QzffF0jAIo`B| zlzpM-jbNR?q2h5waIE2D?~Gjx2kkF|b|TXG5A*G(L70QcEDGZw+>6NF2t4Ci9j}Mx zHAt@_$l+UvM7^1ZKZtGg9exS}zHwq49!7+(n;3`3<2gecgbszs*oh9Y%UQCusFC;0 zM|N0%Ju8F*rI^JtUihNP2n6GWZ<$mglrR_VP0Lwdx2@`(XA3g7IV}Fsef6KwIM} zADUbQ)pDEh#BVcBR@+%$9^tJcOxqzCZxawHM=0^_jmO#0T#6u%9~h7P{t&^w-p=AH z|7N$|1gqa7nD)C1k+l@KTc1GWF@zF7U+SKqpOEqPDLpQ>vljavcOcJ8bi$7E4@CY> zfgb;b$ae@O%*}lAX!ZoEpcLLFg3Ni6Sj5C%vOIKk&P7S=|e>JAar0JQ?|?`F3%CLZ5{)e z7)YbmIC`veV#Zq%sVxzVx1Nafpg?aE5gCurf%Ynw)z$n*^Yh^r_7*sGyG^g|Y&p+| zJ5z$tg~F*4uy)?_;WH_;I|nYD7sDA8u<>lWO=fPoo7p6DbST>#+(<6Ke{1zhKRNxR z^wY6*x3!g?-Ul|=!-_^Q_BDc*$)Q|W^SmBbwxE|S61UUSJuf!QqOl{KrrGxCxzwYt zou12os?5ke!akO2-xDV({3BI5%o??YJ#J6r+HPj5|7_St{6f<{$5;d#N|2jx9gkw> z<=e++c-zho8eawVmMA*Q6xX&*P3WtzervL5{C~0cCh%31XW#$KnX_bt1QG%m@Q{Q> zAc2HM)TjX=A_9g@QK=z>u*ep&ur(y8XvLzki9pap-K$p7y05rbD=k{J)=KMIMXh41 zHWgdn-|wE^oHHP_KJW89|NrxTKF`3N?|ohOzRW$#nVCzKmDp8nm3WjtJx+94BJ=Gw z*zE(8@5yQGwC=Dg*zTlMb|q@6^hftWJib^MH6FCON0EJUnl~uD(=zQ2c3Jr95hmBX zkgsP0;rmD6JT_k?nIV*}0J?Y&N!K$KGoXXb%JoXMr{ISQ9HsoVRJ=ZZ9gZ;F?Bb3S z?FUALri7=ao}GG@>9)QhtGJ^Q^kZ(A`hydyLi%|g;iYBCNF8!h4`6DnQ*Mp03&-P` zG8C)iJ6bGAMd(Af_c*dq^w(hY3EOIV+RSt=Pdw{iX^5)PUqD`h0LNOn%BJTsI0leB zmp1{*;4r|Nf@P|L!1)tmuiw!^50eM2zuFZs`ZmBJ7O@%5#G>a`qn}K$EH?pCC$9q6;$gQeXl?VwMz7X8532P>zEF3|;f{d3%1g!O@C`O^*+fW0@{EH*H`Ca_b5qr|XZ}xD>9KP`SvT$CEl{=`_ ztd|)$FWZ307JqDJ&5hanx|Ve^oyNS5GzD%#m~Bla;w8|-wwlEB@Hr6FnPB6L-jta5 z6JT}B@8G67l>D3Rpn36)v!17U>?N`*97dWL3y1u-x6qS|mcep8VUD8KL}C`4iNa6d z@bfpAm&6XZBx|v?er*dnkkU;?Q!5Rnop32eE-t9G@?w-3jO>CKg8BFu|z*=R{TjkM@t3}yfu zgG}yLAYgM$CNjvHOw53DtOh$qPn|0SV)QI=1t-SK3OYnvX@u8Yp*cp6gcc*TL4k~k zuo>ZorWl914lZJ?-_#Nwnj52#Pz-SuSHxos&W&|ObqnCoOY2(b83~8<>sq+`Q<#}h z1Y#7L;M!a3$A(LKmK3m{yy9Fl3wSDMTW1n9iRfD{K0<^~;7}Yv zhuW@;(bLXM!o|%odL*tR;aMJ)gRQ6Qk!ZMyL(M0+_{NI3y<0jJJa5;A#op2zRX7mKZ&KjlKet z#B4Z4cV|6U9nMzHeRuX_$u(OLTE)Q+lky=kXE$~h%RxA{A~?=(+d3yP&8H@&`7-}B zU*=BpX2f@_Wln4hJe=mXHI?_z+>3{)gchrvEu5ruXh~DdC#*CAFZvMD9HU15hn^}svS$rn8oglaVN=Q zC&mSn4l|XL#GMXE!KqLNXR0y=9k2%;voaBfm+={5BD(aT|03w z9*twkVRkq+WT&b7`qeG;ur|IVtdEYNt6LJs&~tpp(A6zoRWK{zgX zSwUH^#pZAKdK?rlg!;0>2T{#M3VC^JRVEI@%%Coj0cQ{$V!Z}%!D2;7u1Qc6MaFwJ z;Vw>-hz6sbWQ2ixo}i-KCtWQ_hte8=!N)(R0nN+Aq|7Wl1#9Bv15(q zKFzbouvKrZuySMcb8cXeM~9)nzDALa!5PKqFpeM8c@x7+=1l}&GERqya43-Alwg70 z)bLWGe6yhti*>vV6-T@>mcZFfzlnf9njgNV9nvaRlZBAAh=vuHxDXC&v|DYSb}$af zY9o$Ud#VqqwyMAzT4r<0M)vXZ&@g5}J$jDkq@Cc2QvP#cBpTwQx8e zBY64}vKp=8B6B9gB|cyk$GE3mYl2o-B|T&G-U5fyLgKze2%XU;pgR8M#H#0sgbhMmsSLym@vr2O> zM3l1l{F&tKgNThTG8+u);bH*IMqD$9tO@^{jnmfM1B=a3)jgD+;~h%5FMH?bn3EOk zwp&btrx82h9IL4%Mh{nQ+nVMr-v4g)vyIHYFKT~;J%O$9uPhi0RT~9ybN_lelGiR# zcRG}DI?z7?4zrx#3WADFW}Enn7>2tnjNzjH8#weP!DiyfwyDKiU67`1Cn|i88HtI6 zTmSWC-Y$z0yyFgIb9G_;u@idrb4>|ycZ^_9EiS-WuNQEe{tg`WFoMsD@!|*IgLs)%vpGuCyT^(~9Bf8I zU15Tn4h`b@`a%=r9$|c`sOIj3yuD_aWx}0h_)Rt1+I#89|Q>!6|= zP%GAGvI#n4{hr)Hn)o7xXi+w%C(5Y?=Ur#Oe^%O&AxG{V^ zwb<8FJTLp?U*^Hkc32dSTn~owFoYOKsD~MTj#?5H94jTv1;_P!Ow5Z$UuzqEt>vuw zCtPQ%(N{{NueA&{mt|I?ueFW7)^c8O>^kG(EYYX6zET)!uEB7T=8NGgg`vIRkcY37 zT3;!Nkvmc;9J%vMuOF!thVnH1$fYDk?nw1WjNFmx!I2wmM(#-UV5mE`M=AxKZZRJWJfTaD@8R*C-d9D=6*|Q7N~6dL;;Vo+U!d~Z?@bV&iZg=FSE4sb zd?j*L(D_RACW@~_Z)W(iH}e300-;ba7~x|E;pAkzS`_3x80zTrg))93u5UVMhxAVe zPsL?`4%0z9rGGkjD&KU_j_I2Y8fxz#fd+V)b9T7XL8DKBGr%{l-h_ycE2qPeXNXrL zZ-&H^CFY0f;~fg(Q;&0l4&&fekRnIlS7(Z@%3Jx(RlnwkSG;e2cpbv!g(uAsTm_k_ z?wc@P9N&cTs^FV2p2|02yz+b###8wwjF&wpfZ6!70VfGo2j2F51P+%H1iL$6Em=wO zJO^rGn(lPg;sz^X^`_yvD6S>XCtkfm@q_ajEa;mmVn zn4WW7Juwq5byG`7<9*BI0S|yX;(neOC@aYXcNpj52<GdjtzC-wGIA1aj+d`-s;6gav zMw97fOkb=>{1h6K&dV=ivp2Xb;_S$GX5&A9I$Yc%or8OEEt`4L`3g%mimwh)nwV4` z`TPulW=ra^zvhH{C5ep-jw1pE6!;-veNYR)=lxFy@=ger3E$VVlRd zHdA`M)qZ8X^n~)@Dz*@%u4iMBDe2eae0|X zZ0|6O{Cs;;Vr&xm`QskxI?c=1vb|%qZ5YlWi)C%$jx><@af>m%+ck+;s10 zv1pX1jkmMC?LK(uUWR+kQ_4^IFK}P^^xlec3nnDj18?K)gS+9pz2DPw7ohtK9Crn8 zAWq;UWT)aiU#2Sq(zN&)indk=gx1ashhiS zc6sB%>V~ZT#EaN(kbHH9@* zGv-din*hvn+JdU;IsD|ze@EW+%j^G>`Ocp^W7_QM>O<;2tf-`@*lWRmvV_C-iu&K{ zcMFj!s~6SbyFFD6HI<8xEy7zAmQ}r=er|mws#i1zr>s`x%$iwMjq@8S8|tM?ijMe&T=%Z9_<%?vvf4%;EyIX4;#J3Wg+p>T0_cIWI+3bc`K zp_Ke+G>U{yk7%e}xFh_@PBy&G`Sf*?&k6VF=(Mx5vqQ;9=7a}yp{KM6SuURyO788{ zMV-tj@^<=0on$+d8n%l{_NLJY_GM|x3sK-fkMq+L^I`x1ZPPrSD7Fo{3&C%(GQ zM!i#=s%R-IGp30B{sDf-L?16M%Fbr@a704kL8i{p=!J-PpASK@0B%j_$UJ~|Y!0zr&?d!(W-n}4$6J|lKKSmzT%#vg7U8ptR` zp`%@75YCDyF_^taPuTe?ttf<_%ap$T%Tyvd)jTVM2`TWYbFJnX!m#>$uqJ6r0bZV^$h4q@lL z@6m>9>g`aPsYSd1O1?I!N7}pD7bUWP{d;8pQ@17VAZY{~^o_>Al7 zdoYUG7d5Y5{ghM;5uM3=!Bv> zJ1elMhhr`(T5+P`imA z@F#xcaETxHCw{hp3w63PBU$%z>+OC=G{LjFhv2hqvNvi~Q?HYBiTJEUI*bw_IRWJV04UoBzq*q>mW4fg+~98>?VKW-3KLB@8020{CXn~pG{&E^iBjFb_5;5=IXf4rk2^EY-g8+HYVkSvX43FKyQxaII9_UV1lHk@iOojGOUu7!Q+J4vHB3rKbb;Sd@gUT3MDdQ%cHmP!m%V{GgRZOd>TXcR+bwmBMQ%^a?oEI-@L=m%U7uB<ZBTspIAIa*Rvk27nl(W@FbjL8^d4z8lC#l=I6T)n6fZJITI zQI$d$%thPhE~ss+tEsHT_cSXP;-j9kEM!nTlqv89&Y9>Y6`+Ffji3387S4{EKL__# zRXr}z7Sx!2tgNgrKW*$NboQ#ZS2 zVfAvW_6&9b+fZLq{hf;pH)OeKKi}KNxXiSws__al{uJ|13I7aon`DNmu3^#A>UwYZ zE0+IS9X};{O7XE#bJb+735!dL2SxkfYNn>DzUG+dxwwQW99B33T~R$Jif@?C zt;a=Zv}EY91CJg2gJ|J`>e|K=aruMKp%yL}47p)W=~6T-pq4$rNyydMKkKH8PrX}UR0d$mL$9wqw4vK>M^w|>u1iz72#ZrySX&9DrZ+MSWsp5PWZUH z4(INgn0{tYn1O*p$+$k8Kerxf7jSQ=tei3yvlP^lP`_j@_Rpo&rnO$Zd8YtT;u9V< zsi|6s4*@AzF!_3T_TR#&8QZd~89br|@@fHSV>h6ZaC!VVK z3y_nk{LDp-=w_>O>=~z=UO5@ns+)^72|N7=udl31w@*3_V~s9M$h#Qxp5u(7@d zUAnMlDMoNf1EvkSscISb_saQ02Uoevz>N9x%nG`AP_da84GT<8^H76{qb9lCanLG) z1gCK6U1%oHQq&&l@Yh{-XVx#OoP%Wvy;nPuqs?j|GgRQ9)mu|Hz9?4Cu4zESYdAdU z+nK0%Wj#}%2e1yrr%8OkE9>0=egJvVyvq4iW@^pw&wA4#NIPqxIl$<+p^_(!8#{a? z7iWH-*d4@!nz{H`cE_xR=7tD|21glhT40xD;6hVBx1Y^gY*iwQ+M4RQv*y;!bjPCx z^K2H5L+1E|{TVl1s+VDS>uWeRT)@qu?)FpFd`@77p~tX`nZ8)KplUu^g1lLrg(J}M z(LP)kC!5=5IAleKM9^P)1?UV&l+7*nz3!T>RLHJX} zJ9w6T47{OZM-`5tXp5sBAUlFuE|JEPK zCjtE%uFw1;?rHgMtRe(oLp3k^B_iRLmTz--Tg$gO_&wjhIpzz^35|oN*!>$m_U9K- z9^Sw9ZSKRP358?cZ1l^S2?0I_wao$9O5UsOz#DUiSyc)ezN6*6I4giB#8{&MUQ1@q zBtB+h*oDL(^&}CA4-qqbn0T@{Qsi$;4CfCGf#08?UHIH;xO5P#zyO7LpGL`_cN?atih*yfY ziw}t}h;N7??2F7NTkI(g5l4wr#2T?tyjZ+SyivSQd`^5_+$Vl5rs4}wEI(H)6qk!@ zL}Tk5@m`YrnRo)0I;J-^$3bIb95gn@!PyEoHpL;Yl6;A{R@^9FC*C7IA^u)`m&Dk9 zAbw1uE?+9#!rDbSC?=CAH%oG7v77XLB=;AKr7x9SCXSN6Lh@wsZ0To8HnzY~{sQTj zN#7)1ApKg&>%^FNy?D2HpJ;4-qaDV^H}Zc$dSlxgva#(AzDqsgeX8)kh<}rwYdZTU zET)o(-$}Bu^^Nd8lKYFtizkVvkVrRP@1RluCC-z6iR2aHW#Sd0u^o>_p(jqPuQ_mw<=L_UMWQ^eE6apHL-(#;U(iHpQ#Vv~3Q ziF_{>uM%5H^waGm^4lpsC_XAaE50E9nnb!klF0Xc$;K8q^7&fvoDOcj5ivu|61$Md z=NJ8}v47LDz1q`N`#E#l8e zr1NZmKPB1N{ziOb`x|^)@!uCe75^gsjYK|p^UL&WP;5`4e%U0#^Q7-34iE>4rDB;l zibOhNQylBjrIbN#%onG_hB*8fVj3ED7R_^2h}To{F=DYeMC8+w%#Tk6l9gh$IA5$4 zSBQM@m+>za*N7X$&EhrUPsB&XC&XWfFN&{IS>#9B7=Ns2uJa)Ck$39N=exm`lGlj*C@;e|iCe^&$nP^V{8sS}@m}#k z@fq=X@lEk9@k8+wG0f{ZG%?aiw^H z$mib}pU=RNSBYCiKJ!LBpJ5|^Cf+4JBt9mZ>sG{jUNXN=%XA&Yu3~qwr+AELu456O z&%iO=iK4l#g*;mFSdsPu81HOxx;Rs;6PJjq#Y@F4;&$7*PML_-pYu;v3>0#P`L0;(qZ9@gJhi`z6Si zU$7_Ji8&%aQciuINRtwjjS&g3Sn@EjR2(IqCh|+!Om~y`Gx09*0r3&>8S#1XW$`uf zkK((c`SL#U|5Wmq;@?Hyn`QZ7vAx()%oU^JF=C-OR6JfBE}HvD$alQtiQ+lpdE)uv zLUD!IEM6vFAzm%Eir0xZiFb;y=w#aUh`399UfeCdCcYuQExs>)D*i=;*)Egsw_*~` z`PhGHVz$^t%oBTw1H?gMsaPhSDxNM*7N?3;VvWd8=(GGfkzZM-e6@J3c%68gc>7 z_@rp=w;}zjlKJs|=J$^Hx%j2{PZ756OuS?e1 zQ{r>tYofW&hx|U0Z0_$t{#x=s#dO}!f<9C1Ear*@qPf3^cx94DietqJkze&^e&)U% zxKi>3;u`UCag(@3{E2v@_%rb?@d5D>@oDiFqPdTUa(^S4HU(Ip&&7X;Hm(#|`~)w<^TpmGEfP?_OuR_^k$8o;L2MOc;!WbM;=SU7qPahZ{GXA$M|?#z_vaA) zN68Tov4?2x*CAf9&YsGcqR`D9q+}A^S=Dr^IbLsCF9~YkzUl4yKzABpgd`SO}{Z}ZO`+Jbh{XMWu`jO&Tu|hQW_YiNIX=>?}sb0&$>d?*F0PCrCb794(F&CyP_X zO0im;CoU3~h$}>MUl8S7BAHe{I9{zHEq+jbNPJR!R{WLtvgqCK`%>~hL|ga6l0v}!`RuUH}u6;Bk0i=)M{;uP_0u})kfZV)$%cZxq39~K`MpA}yaUlLyxKN0tf zJ$RoC_3tU3BAzPNh;zjsi9Z&9BHk$8FFq{p7GDzI6+aNa6`d@%9!H5si^bv)@pSPF zae=s4yi(jK-X-2E{zm+*_@(%Fk(OrIA18|Eik0F@@d7a>UN1f&J|n&>ejtWAx%nrH zy~TdwY2r9>p14T7TwE{SDgIo1NqkkLl^nLGSS%Aqij%~%#989`;&O4NxK>;zUL*cQ z+$r88J|R9MzAU~bzAx?*+r)3gRNSCt{o9MVVpJ>?i^Vc=q&P`DOPnR1FD@5XifhGn zVobbVyj#3ad`5g;d|iA~{8;=jhY{(lv}7XK;2wzvsT7Bj>w@hI_Vkyf#o z-*E9Xahy0sJX@SD&J^c~i$t2#Vt!YPG4XowHt|mJe(_=PN%2|n*Wz!)H^e`P`@}zs zwBN<@!(uzJgVqOf3qI|zd z8(x%O6ltf6^4lWqa8dqBq^&K=>0*}HS)_d}h8K!7twnjHc!oGhq**P7&k<=^i}Fg5 z#5k%qJ=e=E|K7Ug~-O=M9%OQe-7%JW6q$D+JWq!BF2H;S}_ zMfo9-RdHYeTkInC7YB;RiYJKG;%sr5*d$&qt{1NpZxZhp9~NH} z_lR$c?~7lFUyG?d-1@f{qhf(LL_AKMBAzYM&=mWlR$MCnP`qBeS$t0XrTACzZ{pE; zZhraVU~!munmA5u6qk!X5pNV}D$0zfNNZ7)|0L2@6y*+LzSvu&aVUnDiZjJIB5r?M z0o)tLWs8Xi7~#BC5m9M%o7oES#M0&$=?SR5vnilfD`Vud(aoG#83=ZN#g zWnz=KN?a|j6E}%l#O>k^@dk0Hc#rsi_=vbmd|Ld4_@el__@?-l_@4No_=(siek1ZB zYmQG)OcK+?&SI_@6$`{ef3F@UeW`fp@6{F3PZp<(GsQXLd~uoBB(4%yiEDFAV2+KD=bqU=^9ySBhrT<3k`+ z6dn42x>baiw~A)g%xIkLz8fKb)r=W>6a7NdH~Ue0~o^Iig-x zQT3t)3;2qMFV!r3gana>PaIcN)qwZ6W;8Y++wZ^Ol*K|fnP=*mYB2x!HguiYdf+eP zIj;Dfcnss#8!id%-^J^XIER)?v)SGjl;>2?%bTiO5N9*4Z@tY6I|T~-Y+#isVCGqP zP8atZafxW&d|-a8*CaSE4ZPM#I4A$mYosr%#^-0eUb*;yHP$n4^YW;I!e8!tGhv(v z$6c1o^1N~z;P=wNYu$6QWku=H=7rTl_UD&%k-Kg(Km42!&+kX@duiacUO|4ld$$2??(8UW*{85 zedA!B6~_Q?V;CLRMt{8iQ(SXFhsJwU@jU$vh&R#`K(>S1gK+-(ZAbkwpkw`TdnR7L z7vOi$6@b}3M1KCc&pL4Vr*hvCIfZqrj* zMvX0ZKXK${Y@;S#dyJ;W{0+J7?Su6&$12>n|BSbHZXMBcW8Za!8+Ppv`qP=am?CQTQx?%Ue!0hWk z54N-Ote(@$ceizZtHXZBj_$#OPghx+_wKW1cbgNOV;}eQfza#|%d_@a1$mqDuim>a zZ}t!7jGSX1< zBlc8&w7s3Rf5}CCThI8YU5AW8IpxmBfp+0-R?mzQs|QM5k5cVPZ5h)hwq=Z6RgMzu zHRV=x;y!11VBMs)w6sy>8-fl+^c{u^W%#hgAZ%b}rgbxGinJWBsOc|MFxzZSZj$Pw75kV|C~8 z8~e4My?(28`uhG`$F1u!GNa_&5ra1kTR&#Q85;+;?rrPyHtO3yZv*PsKe_?6OG54X z|E3K_%rYg6u~-TT68 z_U>!9Z1295QGwRTw)73V4x}#Ih5Rlk-@C7?{p^8cyPFxCPU||X>%6Y}y1o0-?7+6{ zt6n@1uy?nOT(x&!)~MYWyS@7|;BwatDu3}n>Zmu`lBVY%j)NT1)|8Y-H+NZYU)vF5 z*U9d6?Hg@rwSlXjHSOqyT$+$;=TXld2%r_+^Pf8q&OaKZcgTPCKx#hn9+g|(u^crW z+!MVUTxXw#71uhnPip4Rf?T6=Eqy`{?> zd)-gVtxb8?6m2=7{5s@n&E8Y~#DUOl(QB+ZAm(=<_5^z9jPf1jTM=TdIlX)YOUvI< zKB3jxcy{?67y+x_xILwtj@x$PRVQP*YQ6jMzAGWBJC> z8;@%pb=B56MXeaoySB`Uw4So@RFpMh@ZNnRXYbuN`nJF|d-s*Ec@eoG$J$Sg z*0#P|3%BfT+qrIcTXfwSA8kkt?03Rbx9x5#+ll?V-L}rD-Ol(ZwX5^-g^u-cN>W4j zw2jv18BWS3`{OIxjoG-ntzy;gwqZLuY|hv|W@}(m8h<9~i8+6jwXqLpeSSq-#{3D` z_a|Vl4sUt}<9`hFeFj%xKbp{%Hou}RX&Pq7VD9Pp<>BoUxjrCO5GjKFbIT`{KZ)Mx zTHX`m5ZG>)qIAptJi`ub`sGWQKl$xiJ8Vn)*a?4qS5|CVn^ST89D8d@Yqb0s%;EI% z>+hPlX%go6M7w^@3anxQJEhg`mtLNJ`k`S^m3n>>F#! z%1=*X+BQmESU0ydbdCv*uR^dx8ozU%=a!>c= zOMCbA>rsK#rt>auRI5k!-FPNyx_-~Kl*Z4(-DRW_MmnRZ_@20h$yUi?fPgFvOSs z1Hs5hggJaB(dplD6#f6;pMhCZ2|i=&4C^=#{y+yl`4t1}j6bp&q2U@kXDxI|!O%?(-;Yh+j5ddEN&6Ja=7`YhgK)#ipik=JI8aiOapyfRisu?>y=; zgtZHXf{oCj6ZyVsd-|Om#Eo<^9hLDeB6W@oNct-R(!ao;NO4E{QATFvJS$S75`*bu z(2z(;s#}4i^beUyNtP?7rSobyQgW0lW@J__vm%31|86qMLPzl-@01JhCmHoNZNmxZ zJmgpqIX3B9=+Yl$2FE448Q>-*#p5Lg@#Q3lCrC_6?}N5PN+qVHU(ULmC@~|w9rBHw zBrz-fV>B^xvc%5mFEXn#iMi}z-WK7a0tW^a@HFA0i{p|G{ne*6W zicbD2JDu;UM#h_lK@Ozznajuo$*Tia$^sPj4Pu)nA8mE`1xj0IM}Ckr8ZB`9`@9bH zGxy)KW|d*L3xesdvEEh5<4tH%Ix7~L(Vd;;!1Xgm33C+es3mZ zRxY(74@gQ%KZo^tF!@*@ke`-b%Ay{U*e7_t^Zu$=?KGW@1R45${c9ukNq-7iMt+%`jmxt@e*a8- zoWY9xN(Bvshz9&x4HyOyE!d-SOVjx*YvebX=F!#svh-Hw{7Pm&lhrAi_@{Sv?@djYrK@dK$h6^`7Roo{SnI1@D@8obrip&V8 zQdSNhf{)A&q+V{C5X^a&;j;r-uAG$fcNRQ5(A|~Oa$Z9rk-32+mV%DIE_7kK#(%o$C2VW88SCVX(t3oNhJ3m=xlm((M5fs{{8cxld;EWa_JrKBup z1oL0w#UGjTHKuN4sTV#vC&Kj00$E>}^kZ{Ipv{pVdhsiA_;7fnDUi(03FJ@CIgxTK z5c!FTKQ)K@Rpk0WNA5~a{x1SKr?Y}L1UhgZaq?dbq5o1q*&=N~Go^~b$?Bh9CvWI%vnjyg)zGe~WZEJ=kp+q)36lC_Dk4L`kA}8BPe26;dx5zkB zW_K`8R3ocQcFb^34(9|IKEm#B5^9HC-b$h89i&vXyX=Xq3PkvvZw?<`k6ak&%%d4= zRY>`wKnHgmgE`e~(CR>jc_=tPDW?}}eQ_X%hlxObK@MN)h+GnA&n^q(kIvc4^gjyp zZ#Hs8PCqbmX`t&yl#cx^rxW9^33PIIxH&n;GyY|sT$_X6!mP-TJ$YHqM3%QUkTDdM z<%*s&j1evmWRx4lrFITqCx~3(*1*Z%Vdq@H7+1PkIQci&Ii)Ofou|0n&iR^+TJI_D zv2zO9fg3!o>XlT|k>g@eN#Npjcyk>-H&EEGp^ z)rnjcNaf%j#l&+GvIXPVUY`fb5cFq8&+dv}*g2B!R$NAXhD6%_W;|STu zph`&>2EzQ{vJO*VGu}uO@1KzWLLK*Qdz6XCpBN^><=w?n$}?|4e(ytm8!mq({@9~4SVnv7 z75sX0{)NeK!7p3kGkbgzpXGYhHy0dY|l@G%fEE{OqXP6>_IJx=AsEVQL$XE|Sbt_!KvJ$9r zs4C7tMsNko20?WcRa+o#psJdA9Zl8y5TA$3zm5Y@VLJF$+`!xfm;W=P>(0Sx#EsQO zaQP1yU0>?%gM1xa!TFXw!K56CyY_s;v|t`I*^Kihq)XuPzeNw*6FO7ZA2(Jzz~%F$ zCws!t)a`@JXRz`gX7^4sxm})v=M&)y_(eW@Qszd)yA|?HaEO#?_iWcO)oFKByD8yJ zd!n6zxg995Qd3WY5(`u(%V~Ff>ItdGrJjZg1QmiC_IRg0)#$<<5v3FZ6H(ld8#gJ( zPEB=_;%mfKa{56zrP%gq9jV7}#;0}UgZgP54~n1ek3S5Z+>QleLiR#@oH};2op%2G zGZ8<@t107mFfl@j8g$IIdZU_I*>>+Vx9seY$*WU5CaTUl<*01a66V!8UYcTbQDr4| zRa+$<<-x?2{;E5^*h7B~v4MSW3j$ONRw)3Ur7_JY>8R z2)ExR5^K>tCOJKu;o`|DxI=T8<}yQAvo-lM68+wWdZ0{hSca@99EO6p13iwiRy8yA zLG5lr7AC}3=qjEdnGK5+3UD`O>FZg`KSZ?ls*?Bq9arU-f_Vlc4_5a+wz zCBQP{okZLUXJXT%DfW7NkHQD{yg{(-0Ia2%xsRI#)GCaJt$0|#i*GwT494~Ge9UBY z^F(;S*2rSC5gVh?A5O!z$_(2yGg1{q1DpdxC^350xlYgQ z!ZN?mWCY$H;-mov!qa}#uEXl=|VH28&Oexb<-ea!r+AWF^r zL2`OdGWs)#$wt2<7^7#tDG3 z!W_hkL-62b8b!}&qn}KiXY>uh7(INe*|8duV)R_$3TZJ;ea&}wLD3vv)l5&&oy`Pa zCU&f)NilkgTs=|h>FF71g!*8t0v>k-RU&!zGw!BmfsqrtE``s*3|Q$!%HHQvd@W5zp);G%(K#9PKYf%wLFrx5rdlo1FnE*O-= zIS^{YwU>X`DA=AoTzin@iqwtJ{by&CJ_<<*!0u!8krX1faZgo=KBrLX9> zn!KXj(!8>f>mdcxJTu1iF_guQK?LFjT6C`=;t&=khcRX$ln72 z#5iP&LN0;BX$X#L#knyGJXWJqc%F7QT(VVXMH!qIqsY^=Bon>K%8gMv2`-H5Ps;Rj zFHOYYG5K}4goX?HHn@a_5|6dGW<@#c?`a9=n!_rW{6sA80N|B{%J{ba@E5_M4+x#K zZ)suqcOxH6s4XpCeAEyc^qQ|rn8A1YVg!`v3xdZ-WU{k`o*l>)Yb4=bCO6yW985P- zcD8soQV_{I!!U{2Or9|yQ$jV{8LydJA@}p`olq(pTaS*VzpJUtBq9pOYku}uuDQpv z3spf0iF;C}jX0kGb*-ybLxUE$C;JF97X>yn#?PA3=cdD7Zh-)f0Pc1sz#qy(m=%M% z#^{|7hh8V@;BdptHmCoWxq4zP9PNA;7sW4{16FbDKByluK}}Xk<Tg!lBQImlGl0 z0)cso$$_Yey>AkiQSMx(@rgshB<@~3t9R3&u3RF37B7iD#f5UkM z_d5JHvkU{=AC7a1Mcoc^iE;3$MYGoM(hqriSAaZ=^WDmNpk)WT?|bc*Y&BCaK@E?z zi?Z5`lc+u~XwBwU)~m9ob#LHJh8i8R#dHXTWpLOX2(E+}+6P)#>-lhQL<}N@&2SiN zLYI*{S9+@@Qf+DBviSxaA`xta(R&LDO7WHxqvwLc+9SSKM|UBKLX2?tE5HQyg7D)Q zRu{{P!kONOz~bqL%51s#>+boeq&6;D{>?8xiXRmms}M>4!=`@!I}GpsuTkH_m^%K~ zMtx_&_)R4Y_!Jq_zTdIsi;;B=HqksUc4J!PaeZ-HzR<>P`C`_1wtS(M^e32_* z*%vo;&9A|jJI~^$cgGm-g)QIquoG7nx8w^mzBw}DyC@3taG5k4cZd<+qNp+An;-2M z$_P8zHf&DLgDS(dn@%c+~{WWppLvOl`WwWSL~b_JmV z7_{qG8cHn>^@A~A&!#WT&wlSv+I%db`9D|(45j3SlJY~DM}<Qgyolq&K!7dB+>l-Q~+Y(xvk|w&nPd%*{nbNq(>+%oE}OU6lz}-N}(bjHXz%Fl40W$HYH)GH`96A zg5IKGQ|EM4fWGWdAEW5ZzbCm?XPsr9?N?(Fwv#_f-;lAw+TGRlVyf=0s;}(Dj-}4n zmNkDmxuLYr$bjSBgigDtt9KfrRF8Gled$kx)fu~|PP-yEv_#cgg3)0_ShrN=<9T_x z7bz-iN1G_lk|M>aRc5AXdCUfu5>2u3Y|C6l*y(C3^?XxF7+GY*0{-c4e9Dt%swtyF zu8msL^8Q|BO1C$GoqOsfZay#!OLOdU4$O^mZU*bK>XGYEI3 zkn0xhrKW*cle)~+hZT9euZCs=t)yUn9#7ZTZ%Ogl}p&X^=#iBYVxtNP$J42jA)pp5K*0Etc(M~_Tc^~w;odr=0^v6rhb!I{gY&N zH(mwF`3GA7M$7Z^*yaW_z7H#+wws!uG)xGTjX9J%ummP#3;OdfECu(c{o%ZBXUL-ST0>*0n&}!!=`U4EZuPO#Q;5s%yFTtLD-Rc>uW5 zzSgXQm@gxoPNmNIW1LP!>#z_e8_VkF{UW;)N^ciR?FTq1W3o_>UR-2O3Ke!ge^{v3 zz))dyPJhFqb4KTd@ZfnN8&*I|y7hKZ(HJMI6h$BJ*;LLC6~dZ)s29euTc{T#csPh(Fy?P-nFVwNSIs%I`8|oR~J)K9HVwzYzqm)O0&#VT| ztbHSFvxc(KJRGZvxazw{ozx5cN1fb-&azT-c!{2`!_2huP=PrFr8>0;!g3KxWdq$q z&U|yMLC1C(6F;)%yGK^kVll1g;@BE?&`=&ZyhHAkP(PT|<WMTANBeQ@YVm${5VRC`{=V8578~Zu@3n zDopN%ookx8bA4>z9_lj<9ef)0o{pjPLU_wKny7QHVvNgFj0~zvJJ{0ZN1?_P3XeCv zU&0nHpuOdeW_DswNYA=%m8|R9hz#?(41%rQf0u@4buog)Q_TRH(;3gYZYX@R#?c(@ zL#e%KS@+eIILAqK-nFB~w(e^%x0~8KfM0F?*Q~B*t&w}p%52kbR z0?^RGl{Ank6S|9s4)VnRwVMl@uJ!*hySe|xmU91N#$0_DVE>Pr*!?dwtc&?fL%POn zubJZi_a=4!C)>w0bvwvp?0=7C+=IWL;>|SJ#r^-*VD1qO<^HdYTw`h+ch}P3_+$jG zSifT#PqvZU)qm&E|LY6%{}XNG@--XW#MJ{HxSe(QT?lu}zGEpj zzI*W|>wm;vE^mp`&eI_AcyYK`E>0HD7H5m|#TDWO;+5hiafis;?ktZ#zmSiMFNwbu z-xWU-ao5ho&lHap`Scd^Ia8b=@{Tz5eCLBS@3MfclKG1>_0NfXwU2TNZzqE}VlUCy zFM@ug@lEj`Vk&N3vV8tXOBy>v;4sOv#Rl;rajVGR zrCw#JX>5Mt`OIVmx~)nQ1?+`t^xw|AkEj~{o-7At`7xzm4q2y0QV|N4bzmaUg&vs^r zSt1TIWFSu{UVV&3+Ye2iEu4iP7c=I3U_|AFKxah|wHTq2s|DB`b{ ze5q)Tr_gVde5d$x(Hu_^{+Q%v#OFmm-@yItHF2-_w)jsmz~dm|C5!1|C$XzoAodXl zhG`Y-bmcd@tFPaG@`6NihVM01{id}c{rAe!?A=vPQ? z7JnrESllFT5zTo8(p@i^kF2qt=9?R!d9oC2lb)|#GMrCDkZEFu*hTCn7KnYsVsVIg zk~l&9AL zfv0|*XwF+9d-e|bU?9V95$_W36(19y6n`mt_73^@57WOXzAt`XJBLX;-$nW~(R^SA zau>;Y;`g<4$nS?Tzf;BW;zaRWu~IY-@gx5Ek{64OVw1Q^yM|Fd=u&s9E^;v8|l*eEU+FBC5kuM{_m+eC96fp*+1`8M$$@d5D} z(X)4WsGY+P6#lXJg^16inSQcyj>Z1MuhNDc#7<(q*jpSd4ikrqqr|adg?P63196sk zzF03V6<3L?#mhzWc@NZcn`F=4;mwjgdx!T(en5O&d`f&#+#~)@+$;V`{7B>{BiKJV zVt0`r^q~HD@g#AwI903^J^P3ACD)3F+C98V`mN#)@doi{;$7nN;%@O3@pbW2@h_se zPC~s$^Lhg`*Gr(eUINdN{ycG(c)qw;Y!sWsRpO=MT5+RzwRo*~o#@#syi@XhqPea@ zeV&y3thifzNqk*=Q+!waK=kYx{zdZFqG#98TxX%2WL|fGnPRq>D@H|g{e^hu`U@

    gh5 zvA9BP77w+XxJmjgB0to_@pw#pMtolM>><7;d9V1k_@VfT_@(ICPYmG31@jM!8KP%D zkzWO3_z)=T#6BQ{IsCx=+xcJU_hR`D+JUXkA;V*GvL ze(?+OfcUK#&UE9ah?!!xm@7ub-eNz|vzItj@`>VbakMyAJX1VJtP*R)#bTq_B(4(q zZ6&tv4)I~}aq(I41@U*{Uh!k`Gx31t)d;^pFck>7-3{D;Kn#9xXpi?4})6yFs;5_8B8tZn}122eF&jLp(+-6o-kW z;wj>(B0vAb`kX0Ni?hXrVx9Oyu|>Q@yiB}WY!$B)ZxZhi?-m~ypAugb_lSGNx5W>| zPejjt%>jsc5#Pzvv`|$kNALisNKum(!V6WF1{)56aOrJA-0L%iun4OnHT)l8t2DAahO;t zjuJilnH7>Ji_^sE;#_foxI|nbULam9ULkG}w~5z^H;cE4cZ>IlkBLu;{7xL(^JnpE z@t?Lxe&wZs*ZO6VWku=H=7lYR?9cDRYJTp-%@4N} z;`v<;zn2DH>tp1{c;4oPt%1UyUz;yKTyn2T`8|PacW?8;TA}dgmo(FD zAKQydl6Zc%!Ot`U;kZ3=JnH8gUxv}$CwlQ-9F9*6K<8~zzbNYW7CqX$a$);u5X>CKw|{5*XmIh6AtfgEzqft#f7p8y_$aEh|F^2EmvlA) zNeCcIlY~VLfw0S-<0=R)NHZJ2b!?>d2I_^3SDmXKa zGj0qzZb$~)1_vGQ?|14~-Ib{CJMaI!_w%{;^SK45zvp?*InP<@)T!#KPCe`RzBC*b zZhw=$k2a0I`rZv?PaU{rO{Xm{cM0wr9SCd)U z`-LC}C*Ai=Fss*LJ3n~Pj=r9K>PdGWvSJlwFO+tLPb1vNKhUz~YwOa^bIR;8D?elY zAK~Sv*WtAM@rVWQO({tkOzDx)2Y09M3)|aJ|G2WJK6>X9yQgz>;Bc_RJ7`s4!>G^4 zuZhABQ7ZfpJ+Wrur<lQ0`ZD32rx+$eyOPvj8j*cF1 z0aci6{x6SW)I0&1;>4Ew9T(%2!f`d|S{5reup}=hW#<#NfXMdl4=OJqn=UeDmMBY4D37630?cDWsijKltU@luYI?s9!!Bxk;uKN`@)&lzLO)Dmu)VK zm7!oySq09z!SKaYawug>$)Rw1hr`i9gAauv2e))UF9*Yq)ZjybqAci34h7Qf zV}mHk6#HO`{kPqrP0mK_y}P}4+Ta|UTgQI6x_9b?URRs zvG#`pgWh7F2iTi8mIgOJUKSYk*yu;#PsHvSrf;aN@1ULZDH6CQx*6IRt$in2<)3bb zcdV;dPs1!~LVHu^_r{op2aTOScRuG3$FksCqeSUX4;~)Y9~_ zPMbnyHjbvwWs48k&ZIK?n!tu%!Jp2Q52H6)M=jeGy>a5Fqgi{{E?bScW=pDY-i{Lx>$Ht^xmN3A}ltQ!7S z+QFOB-rZMs?Na9H=x@dD8Qpwg8AoPRS>T$w(#H;3?Y7|<+nm{>?Ao$bUoN?)0i*Lq z*_w|YJLt4q_2uvHcD7*7J!R%$1?ORSes9dfBFsT&%l2>5N8NUR{^6XCkf#?N&RI4Z zBbqblo)4Lpf;4aTLc5GJIA_q!AEuRERQAk=)=_JBFXl1&;=qpvmPN`6K5UO4ce?9q z(B_}4r+gS4amWYjq<@8Y58`1gj@M(8Ng6e@ib6R>bGOWfGbdk^h!j8vlX+mSdrH{kQOmezc<* z9M^wKRQ_AIU!tx2w?vcvTh2r?qe=fQdub%;zhwiO7j5OgCHmj`Z&?Y8g;Du$d5s2= z{#%Zu*xG+fH0i&EzqN=a{kN=VTax};da$Lf{kKGu{#)Lp<)r_X3YPtW|CXryx15i? z8cq6dd5D&M{#&*)+2_9ne_?7x|11A3&!Dz-c2xdb%y=jLw|vBwwf5f-gS|Gr`G;kqOJY6L|glBi6;HG zjH0Qe|CZexkJkQMqDlWPi@4L1{#zdAUP}6J`JRnT`fuT{Jff}rw?vcvTfSpO|405? zZbZqx!RTzC|CXrFe+z#E6m8?b1#-fFOMiCQ=f8#T&Wif{xA4bdQJ?>o57-kFma*<3Z>2J_7lq`1 zqw}t)=f8!nV4^<%EoV~p`EQ|fim1I@!t~l`ETKC+@e1J zE%RAl8~-g)pZ^yAXe-**e@oQwzlA@WinjIN67~CUIgNGt{kMd98uj~c;ZNkEe*Y~! zSj6wYWi503@BFt!J^w9y8C=xozhxN5?0@9HCF=Qa;i?n${I`^GB!1F=OLx@rf0zH3 zf$Txje@i+m_WN%sKsv6+o<-}r^EF+r|CZDXCm) zf9(@G@RrCg5U!(c8S}ZmUfzSeo4Nt`fUg(k8w=BPqm=&)+F+L&A1;qVeh8u927K6M z#>2{Ii2jv2{{GiK+2|Hv!kvLo@G^C$7#}YDGn!WrTu&@x+HJi82wzAmlcYom)%$8jEjP;l7jdQ0JI?qxUh;mgC0VSqOcY zaAX-Y%ONd8@D+==t$2FKAG~5$Bg2&}#^#w~cR}LA95s6@A{o|veA-WEbmb0UvrTh< zi(F42nCAWokv|~xVb&wr+yHfm5c)8|6ytN9lTERsIojKy517v#rf3F#XJJPCY-HlY z9@B*eM3zwCh_6ND5`-caW-*O=znMtvj(r!h?xnGIb~=BR(R&fpzd-)Y2z{7x%tx*mf*FZnhzy~?k>Eq1 zu?R&h&2nakRzOpZfS%DZ^^W-*P0Iy#*2!72ycD?_5sYPeHoA-gEpJ8SCWIoEW;tW| zL1-R8(3ny0m{i=K#CmLJUP{XxZ{E6piRGDxsb78-1MKCSviAWEGB9>-39WiEpPk%zdcFboTEuLg&UFca%?}C9wFcy0v(t`pm4n<@zLJ>=|oM(|^#IO6d`Q%>&+Y9W> zXK9gRbSlb>VL9eus_ElwXwF8!g39vLJJw4O?HW7tuvfMTIT{f9FvXO+9Mam><)YRe zmRoFR4#J7c)VUQoZels6m~sz8deD?JvxN0!nOb?T$!@T-E@oM-Pp=@??-ATFMPv^J zGp2}qg;2!OEa!~?$CR>TKCh?6Mmy`zp2c)LB~3+e#}tts6wH_+G8mzVrCClE`_Uq0 z$2!EmHDN8l>B_Y4ROBB+1DwUP5jmRztu-OifY66!{Fb&DOIi4|m)cq9c$R*SyqB>s zEp0{QCJMClAR-SS^kEs#5|4NHP2PQJ>DWN-t+d2*!tasycg)WebDaMj()$S5zh1eB z`KvXQ8}gP{?l5wE!*Zj%a=EaUjev3-1J;*e)(4c!=!Mfx@3+7abatphA~ft`6X%kc;wiX4Mkjw$A78xQH!*5!g$ z3ddoUo%t89TqSbMW;v#qa?2n!nQ~?fSznfU$#WOB_+mTDocB0}S0dNX5lpXdL1Zfh z_WEH&9z-Z&X_hnRt)0-kjG!|j^^QsHPRp0rSy%E@L(6|duJ;g(<*yO>k^(KK^}zWW zp@^kf&RC8?(;Y!GmU_pEv9FifS?_sPhakrw1Y>n9BBxNG)pA76Lg>RX#$pqs1_ZUW z&{*VWUj%!toplUXdA9X(!E8MP4~$`FGH~h@kz+uWtcsINN%S zow_LavexQRWl`)5mf|&Z59RHX>4wP{h(K zr#WugNZB#kk+itU&YDMyY~y7pb199mjW;2(g#z3703!Dx6tOhRsg3>EYs$FR;b`4x zXWi#ndkOhppaEKY2a&fZ(AwvS96;#9GM*)#?Z(1Vz?x4>v+T@IXo=&V(i2aE5c)91 zjC(goM<8gF#-SXp^6<$gH1=#e>t|Rz%_t2=uAvBKl*S`+Dg};GB_gvCio9~(C~-}p z9rOvG(`c~*$AM>Y8Ok)#2+s~zAaXecTD%#NI6{$E&a=o-q8-P4&Y;Cg90Rn-aeoM9 zw$lhl>i3BJjsiz&4=$omBg(^6_ah7Q44>VZf% zgg(qKE7kzMcEtIU-PPvzd1o35mDJGc8+JN{flDiDEay!-%4FQDq1)O4=P|2x`F-wucnU`eCy=$K|n{ROGI~Xb~HH1>&<(jIa6DH_THff|N z4fhf{V8-@KWH5Dv+&YRAS{0MNe?sr&#sOB0cQm`6ZRvG4W*S+dZW}+iILPFhR^lL} z(o?O(!G5Q?ICk0^Jj!An2z8ZWIVw`+?h9KBhO@0DQs+0E;syy3jP>Ve;hLUAc#Ul1t~SWAOK$HX3daOQD&_z@A#7U}hJRXC z!GJX4Y!jVKxK&Ie_89Hd*)U003W>rLSiR5Vfmb7q(J?8>EI;m>*2|4sZRUO%c0qTv z?lZ2d*7|8Ie444dZU5I9?IdD@iB2Z|ZK5;6sE=)>3DRxiB(E}@P_Vh5jInaxo?ruP zYo^x@xOUjSiVgYkDdJW+)2q_tPS!b-_I(>Xxxl!)xh>$^C$yp7#KuXE>rZyU5Z4)K z)D&VY0;;)l6(esO{n^ClCOU;++f9~ji0m-^nL#{`5Vo4(Cni76_)`cekV*=hp`o-> znnB&E;eIIQ`Ipr(@+t!SauIKOdPc^Xfj^zYRENM;lkOCnLU8vOGmN}|fJ2P<)QuAE zP);Q{obWp3O*r(NQ>`As*kHunsb{0NW}_P&+cBSr@v!ycHtcbub{0a7iBBO`x=}*W zs}S9aU_6n4I}lJi@su0oFpNN84)RU}%zuu;$5QkAs`=(| za%65opk?xL1k}w@`m5Cc0y#F!;tc}hXqwqDvrvTpFv|=%6^0@(7kM0$tkZ~DZj|6X z3}}fv-6(4@-`uRz2wtXRfg{ZIt92T|{exm&?Z#&*6tG}EZ8H)5wU0K&rxUYHbP933 zt0nGtqpaP0yR)Vf!%aQY30`Gl>JV=2)4kfAWZ!?H_HoAe=|qhiCAPRxV!InpJa?rCFomb76@x^~Mt}p}K%9{}R|v)#;gN-uaC|Ew446m6{RnVY6*R7fo`L}Vn*e95 z&I6n}aA-)F`>)nCVm^X#70k#52=E0(@YWs*5*$w4F$$U$j7KTl7!eF8+H8*8v97Qp z&IsM>A!TKp5x$xT!ufGVY7kHZ!B-KP;*6{|`YFU!MqeL@GqS}Mf^kM}afNW4k=qec zFdj>-{DN@YTQSgNE*uOP0m8j+g^^(-1$z;CE+ScOl!zf<@B(p02Dm~n&In(Nh?H=A zEFxTxVV?`|IyXw(Xrhw|t~1z!#5M%8KN#8W3gI{-JB+X_7=I3tmk`h%VyB6oPQ2l2 zi8m2o=lnP$@49;8GZQ_X;LQs(izr3Fo(jhqDKmO=&gSZdESL{wYvn>YEzMO1IAmsn z4a7ak4mg&{qlt|g&7|haBp1reJOII+%#)Loc`~b$Tm?XhCBTpef{}Qm%L?;uR=9rPm*>0{jIL&c-+rEks^Xv|j7EyY&G9H5& znc)iQaYo$5W7cPg9>uY+W)eI@;S78VXQn$z&rVL#^Zk?be0P#^Ucx1_J0&?SVJJBz zr!jiSWI?AGaZhN|l2h{REDUiB0apA|681SId44nYy$b=@_fB>W-t%S7cH2y*6~QZj@z@Lx7fLXS&g3y%|oXsgc#8R&N0gSakv3$YmMK_GJEulM)W& zLi7~mpKZ!a_mwd>josUub!MetdDsf_)*DADVl9W`%~j!i&td@PZ64U}-ZY=yfrF9d zk+o?-HlL24uKjn9{Ee7&Y6%fYJo-&qXX1 zp}=;kNQ#Phtwl>Lq$akmh#iFh@9eAMjJRvknO7jn2^Y2+(BZC$$phe19&Zx)^CTzGncf8Qvcr0tEqQ{U!e;RNfu*FB_0SIENqbW~dsKUd*gfPnJp|2` zw0b73@(U;yx^1g?-0&ydwsj`q9yjMEyJa%5e|r$j_#_XQGrhi=Ovy$iI%)K3fCd~^ z65sYb&z}6|ho?Je!xVyh!%JfC7b4*Dp5P$())00A8WYeDY`psR%|V;jR_;}pKd;G$ zoNgI+cTYgZ5athD6EezU1sA!**$9r+v?|U>jjJbkG74Eu^e@TiN(6ci-<%5M$Sio_eg@L7WlFq7e>o?@iZR+EhFj> z&@wxI1tPrg!J)=W9-d9u6z<%&5kl6vtdLQjNnn`x)z)R(-I3q=_p5V!bo>4I<-g$>D;km}W=9zjEqT3MAR>D2cG@NhFGk-Pu zsXVO&F@4ccB5a~l3C=igFp?*gw^Q8bUA*u1&VhFk&JJ@=pCo%{K{jD!3y z1k5v{uNjYJtKzRB@>7Qg`^2)Jf^HMd0l{WboowD2rWN=w%}IVc@YLYj2zwCFw^Dj{ zW!$|ApG-Vunl_Vo0Rd<1RdGiC>gw70&k;;%>?_8T+_8#>kK1b0qS3_Z z+dGVLWX*+^OA410lAXX|iPo6SF~@FK#DC10CXOh6M`1FDn#XRP8KaUo$=V$&`hD`N zGEC1#X7`wy;vGc3`q&3AOhV2X2vNB4yf!eZa8&O&#aRgWf-)PJkAT#GQYpHo&!FjM zHx++vXv$JtiO_mEX;s@aQ(~D{8%4La(`F+&$4&KWqv+Ol8f$BGQ@z?Ky0s;~EZgC& zP%?zA&;Ow7X-Js*iIf2P>TTilt%x!p|A+qksfm<;sTWzWrQ2Ka`74B<(k5+NHuEv~ z2Hy!#aX&)a23mn_O2I;enArk0vu;Od+rDrj1!oyIGb>`&9SFWEZ9Az<=JY8OwS{aR z7rfBI&i8CuHWjWiabe{cB`>QSYk43s`7HcI%)Q$3)$atn3;(u#umZfCVZgfO)#v+- zUh)xDcgM4>N3?+I!4K>LVSPn4;EDnz8&uSwVjo?3FFwzHO}Nrw$!Ke^`5!hoXO(J z-`V+G_}a`hsjbbVGBHk;&0KEIPo%W$sk(y4Kfx z?pQBmA!jFqD4f+_>t1V6bg!MK(@tME)w^<_=$f8R)5G0V@5+JVNCe+;@6|-IHuD#J z$*UrYZf(<88(*64yDFmS);5i`4R%w#+9=!4%0xRIQ=CeFKP{V@w&jgNPb3npH#uFU z&nSz!O5Z|DMVsP*uy@Y|`ze?>d4v*bvHO&-HPAfa9OcZx~O5a$s=nPZbHvyAM zU-6{USDZ!9HpP8snxxWK+*AHw1iE6Bv9@A^9c|6YsJVdVNP6GjW+TqvePiP}p27Q$ zhN#)L;?oPa7>)bk*WLajdg}OH#@iV8zQNq@Dck6_`}F*(!BB|M7s1=S>kpo?H~xs8 zr{b+XJ@a{andWVbdwF?2_crfTOMdDOs7dnl)X}$ww|RQ%cs}(u#=WyBPn_Q7*YRZN zZ9J(kc;_viMi{&^6;B)t-nq#u#}h>sLJk6#Yj5-G{CaQo=js^q<)`fFxSn~Nw_@=q zJw5BNMO>XJ+v3BKHmgyh8WK|EY_c z>Z_{zmo2Ditgc^BJFl#%wyKftRxLLjpC>M^ukJslwyLISPPMe2R5fB&UH#&D^%aX^ za~IT9H^llj4iR9QV|PW7Bw!(#&nlnn2;WN^Pl6$=;F z&q89q+Qqfi{i-V}7tC7V)-Y>PMb-QTwbj=D6Sf6TNqr6`=S+fFyes*2$yyQh_qKQ7dRba>@+7Nwk+&?oaT-KoQ$t;w1WZXA88|#1Mtlf+Zfs48tEBsKQf%# z%1}PW%5Nw!cHb^BW7lktWsBfzKJ2_~aW^?j=H}+Imth#fo;JG$`#0*e8#(t;=NOK) z^Vq6&m>9XH@`r8HX6zEUe1G|TJCu&$L5k!2){cb-csuL4^WC;S=w^5I!Lai@OVE#d zj~=v~KGF&V?T+x2L9hZwoE*# zm}p^lxZT+mE=bIj3;%=G9rpER^?#K=!b+U)>dhz?hfHqB0hn-tjp-?XS;=G;?TRA!IQI5m$ zR}E%%JGc4*IH#WxqQp;Jq@j(bOq9%nx;exBzrkBs9kqut;ki&TLRcI%3I2$4!s1h_QDi=o3#$SpVBQ zMO^cznN{^;>rwCAcSdffP$*ZY2A)Wkk3>Ny%{?J(#NPa$oe+Gx;wzjZcviXIHG&gD z@qc3sZMs;~Bon~aGSHV5Q?UW%h< zX7PVm70$<9xZ`vp=A_9FrSL?2G@`x}vF!{p*BCdf9EmBH-7(Z2mmZtDPP0`Gd9OMc-P&W7V@J+7U~xFi$Gi6KzUA)xfI)Or&UdkhuzQ2ARXcG$-twj4tN#vZ2{DD(pOo z-RNKVUXb12w6Xh|^xNC$Uy}ZTWNZJ`U>3wn(#?Vxb64OsKWNvdzVQn?>&#m0Z`uAf zExSQAebA-_8>QdZM!#PAPk*XqXc%VHwOE9+ZA`nc^9?3JnzM$pIO;ri-bhRi{9Mwu z%gg7^!55)L<;{!hs%x$C#kJ+t%?ldKE9&PpSmn#A8W%6B#8-@p#%im)e(-Rsp}uPL zIA&~EFt4_vro6IguGLgap?XdX-$ShOn##Ei3sxZe+?op7D2H~?z;dKi*VorBw#pY( zdiJU-=1{D!sjgKWCytmky`j3kVOCX5#iEM(0VT8MF0Mak(5w^3PaQM0e2B|grBf%( znpD4dVRcnw!>p4}#JgSb6=!i1s+e21xPev8#kbz_s>O@XS%8L&UNFzJth{ki`La0` z%h8kS27HaOni5T8(tLb>w#qB!%(0e~451MiXhM(X)-0}|ge;2|pyvw~)iu>um)A8S zcWrfZ<6H}7N`|sTeMRjY43f;Nn(}k-y{vX#%zU&StBMAELtj*FMzOrSp=`{!lQ8IW z8mzi8wI%!*hrE06$9jF_0gF+#Z;HQs20ESyhAfLp^p)IfkKmVEKXy7{gyxHdR|EPnaG% zv1C}xd`C8S07?dy42t!wudb=CXsA9ib|${K_8Z=>65~)cKUQD8bU_1dK*RBt{pOSmrG}&44|fxeonKKu z2a1aNs`ub4UF}hI4IU{ZtdcJ4UP2+s!*zCK}7@Z zfIvA{H$nPgP|VE`=;l;3R`}()b^WRq*EZHyR5c!paka|phTz_U+4ndC8Za=Jvfe?k zs4_WQtI#xeq!*cy#$iy-3eBYEaC(Js_~4)#z+(d6(9PUhRy7}cWpQPLRY~1c95N-z z=)hzY`>3jBaRcUYdBdCq_^!VIyV-o{x60>LELv1y4n@RxY@WblGdbJbX+L%RxD!fe zSml-2M`!|W0n{vLfRRN!2FlB)kHhQ)wGcEcU4Wx2|#Vdy|Wkxsig2hndR8 zxjq}vnsUwsv=Muw62n=uxDsoc{{UxemRFnItnpb;U5y5z`ih$5vD;MJ)KHCKtF2y! z-L(Q0i#))Tp$)|xr84BbHq ze7Z~NoQB2a^Rd`qZ0bt6FWI1TOx3McWX;gzLN~9v5nZn4VCx3pPu@1{&zny_95dXf z!c1f>7%waeiHVb#0_6>E0*=PU#pjgQRG7(D=|3RM@S*J7T63b&`9rNW^OcJzzf zt7^tPXsG5+?08k4Lhmdcq^O{ z86OR#hC2jv>|8s~>121dyVytI@8`P*@_kPP+e+@C`x6%Oxe z`Zfo5H2F7;$*uJbar`+`G6^vUKmGG>j`_`BQsdwqC;rVbBbL;-KOywXSxEsg$NV8^ zQso#=4}Lkv!dqEPFFD>Fct`dp51YcqpGf14Su22_D{_AZ@MgXCVy=i+a##WU%B~lQ zOhwXj_c8x)u}mB<@<|%gXN%QhgSbLmBVH|DD{d9HiI0lE6?cn&7T*{DA>zKW+aGb5 zSSFq(^7lk+XR~;L$Y)yAZx(lmFN$x7seCGee0(_s*;^bUmWorwO40b1NB-54uNIB( zc<6s4`EhZl__oNGX|ldFOk=W(c%;Z@Qq<2A8^sGnzFv~)yF}xA9rAaQ(=nZxZhWYN zM@c?LJVm@nyhglFd`f&xd{^8rek%^eVa0k*5~qvRVv~5Wc%Ar5@j>x<@lWF4#jix% zYcuuaioHa>l-$%W@{I z;~N$nePjGggqjDG)2>80W+;$(5U zXnY`}oaghnj(W(em2P|;!`@}mZ;<|a@n#aogYj{Uat}*yd>frUzz7EnG-^S2;K8^b*eVEdJCXSMRjO6j+3=;L9t@K*y z>&0c#uaSJQDg74l z0j2Z((QN-y;&b9F;%?FNY5Z5p=->O&ex0L>#__6qz_?7sL_-_*J z4RmnXLF^=U75kBBUx_$EJWf1WJXM@T!tOM2j<`^)6<3k4d!e{i`YXiiq~9doCjGC( zyT#us{aNuP>352MlKwB^2hz9osr0*}HS?ng}ljvt}ai};_93@UB(a-7P z*%Oml2~8glm312W9bh{{z|lR z-1dY?l*=Pg?-625dgG%R`hL=TKAMlCjQ)%krz-t)ake-|TqG_Lmy#&ILiBtxuakVO z_)8M?-z6Gf%#a_FY=sErR_P~*W5o&L>EfBzIZlSH|@Nu=||`)v2K z;!DySU&_$)UHnYnL!#V=O8-`R{)IHtqhf~GfrR}dB=-=HB4Nk)Rz~^>(w`)bC83`x z`E;?8M7jA&UoQQ5;sw(GT=LbT=R0{TWt6{7d{F6+h|h>Gh_8u%5Z@$Gp0CpLi#I7Xl#Ka?| z?=bP|3J{zRpNMii%lKwa1L*k?2v*L^5 zP7>w*B>6Am2PEqKRBREySGt26c&wlAz9+N9&SEz)pM;&>Vt?reiN{G_N}?Upr9VUD zi|?tQC;1$4DG9qP#ns|^rC%rBB;F$aTD(WxPQngfYfru;zAC;hzE7f`ABhLVFU9Xf z8#jBIFHFK7Usq3d5o2PZID|z0W5m&7nK)6LD$XEbZf zS-hP@xra#DeOxkMG*3Ib#W$pXPxAX>3yE@HiigA~-mA;<8DdAVi&!A`5sOIJ86b`l z%fzwbnI!C%i}S@Ak*}F&`f~An5_T^TH;5a>E#hxTl)F!SRD4o=QRK_ynQs>fyMGiv z5I-d`p8q6~k1vrYgZQHjGDU1J=89cNl@0Q@`8OyWKmHvGIaZt?ninENe}-iK9We7P z6qkri;!1I~c&Yevk$>XK^8C9M@>cN<@lo+f@dfc^@iXy&_)n3(t7wle4I(3Arr1I3 zEOrwM#lB*HagfMYq|n}RVwpHrq=PP|FA^KYW^t8xp~zROF#kI7263~U=QZ&ymkj^(nv0PNl5c$`e)bnp|$ev;^k$<~MJ^%iO947uuEEV|{ET&Hs zr;6obmAFJ~63ufGl)F^&I`LX@vltie6t{^Fh!2au6`vJf7GD+rEWRb~6+aaBi*!rL z{u~m&6&*fLfj%PgZ;&W=5Y2NO$UP+UZ{C>BzyBf2#VT>3SSvP(%f&U~#o`s>I`IZ^ zvv{j`hj_Pmzxb&5r1-q}J8_rzNAWH3J@G^FQ}LkqmH3^=S0S;#DIz`jQO*%Ni7~NI zq*FTP8!Ju`PZQ4)E5!L?jo2VA6VDef5HAz26t5LGigEE)kq+_Lo|nX3;vdDg#P`Gx z#ZSe9qIo`sI9*=T9v=vk5iw2dAa)eHi9JO+<72rpae_ESJVQK7oFmd5Cd(}r8^jeN z-5oRiV(~I@op`OdS&WNMiO-2U#a$xZfYR<;;$HDXald#_JS2WAI(%M-@)0pp>>zd) zyNTvGAo6dN92ajDeaJ}15;?iT+fzAf$%KM~FIMb!JH--z4A9pcmC^Wsi%muQ|B zqkV5l-Yb46{zLpi{FnG|kuEzqzSUxlSSKzM&2wbryGZg{alLq*c$0XGc$fGaal5!f zd|G^7+$oypRulFf5y$a^J!DDD>zivJS-Er#%&g8hq%9mI}e53xWzN-P$Kh{uR0 zh$o5T#7W{A;#uNcaiQ2CE)&leFAy&iuN1ErZxnA9e<_;h)ac*6k{=PD5MK~q7WpPH zj>n%x^W2)_DtVvy5Al%rt!SQKb3FN67t9iK#BO3wv9DMp4ibln=J_`4nCIKz80p80 zbRWxlmWts*GRrW{Iz(GXr5mq-=mVB6<-uz6<-%W5I+|GA$}o7_&gW((!>s8 zN0Gj5nLbiHQ9N0kAWjj_5YH0n2$$uX#Z}^k;^pF1;&tLCkzR9I{(kWh@d@#H(LBFK zzP*w^6!(h<#c#y##1Nm~qMUht4Yrq@E7Bh?(?^TuIW=VSoEn@az4yGjTymATP&Ci4 zk-tgua`6(8ZeLl?FT|V0JH>6{BjOVxeFL-HXX01lH==nijr5?Nzh;R!Vxibq94rnO zPZ7t7Q^nIo`XOfh%SG?G^F@-c5Z8&`^XDy+Zx!zl>BE@zUK4-xIWyADb7rtb`Ml@N zhb4b6rttYH@}-NpVrMZX7K;7E5^=aVQlv*^+B;J;&zT{c=geTe^h?DH#7o30#q}cn zG1J~>;y=a1VnEM3!(uxzTkIls7mpPCi9^I=#8UATaiTa?JX@?37l@0*rQ!;4jd-!R zUc64+B5oD$5`QCZ7k7x>bK>VDzb5`c{Hyq`_;>LW@pJKO@jKDh^V4)OOUx6G5DUe= zVt;XvXr3Qqe~p$rR-7PC7tau9i{A6(MUt0@&EiVYJXePOOC?_=ZV+!0ZxQLcoAc-Q z;vd96i|>ki#kS9nzmonNF~H}iuoo6H#P(trvAgI!M?Ok2{W-Dx5b;>?1d)ElnO-Zd z5YHDc7B3UmiPwt15N{Um6usxjJ0w3YJ}bT`?h^kfzAf$%KN9zepNn6M{}uy$zKVWi zi{|+u6U}pCq?_l&AbqyeUX{3z#CJ-1Zm0e{kxtqv zUnAZ~A|G9~Q~w*$JQs#+o(qHKIWYJarPCuj^Z!FM&w(Ka^;|TKgk8E|XTI(ty{%Io zB#t1Fk3QF_A1~6iI%V&*obt~^x;v*lNu;B5%GDy>nNwaN(xW-$t3^6Br+k}8 zcjlBI5$Uv?@~a}&*W#3$ zMS2&fOi!yM9gLH=h;%JZ`C*X`#3`HSr{EtbW1RO&|DpI#@vvx~mmDkxsrTFBj?FoANr5PP{4qQuLm4J}#L~x|zOP+$(-4(p5Lp z4~ulcO*u=X7jDYEL^|T8JVK;{ZOZ03COBL29I;7UF4BcI^Is)y6>k&iDx2w#iRL*a zWb>R7+$;Tu;y=a1BHdlHe3sZ#>?IBrM~J726Gi&8X8AdydEN-wJZ}VlF8$RaJy$dT zZ6cjlQ+`A=&l4fPCix8#^N230neP+PJV%85z2q>T`yroseh7VM${_ttll?`yo~C?~ zNXOHZ&2vSNE~Y8hiOWdXy+rcmA|0VJUtGMML_WGsrT!6-?xQKcD$*q@<@ZH8k*0h| zq=RV6?Zl2^7m+@rnSP9Tia1W3DxNOR6&H$2#3u0~aji%<)UlOh__X-E_($bdSvRN5$WZuZera55%v;Z$$b*X8BC9hgcxu z@rOAs@HN)t0}Sza%@DW44RIUF(94I*P$T2?YKUdUFeVm?eZ?YixHwWAC6ltA_Dp`5$U(_)bq*MC+{Ls>O>I@o)8grRL&A zqR4c@l<~zCjd&|ZWm6-}{-+x*+bryQJ_a}2V9^7H&ul&M$$a?vh1uHXV;Z+U2q_5v zUA`jZX0{DW{pz9ofY^Fh3{zi`fUD^o%YzS zGZ4Hoh+0qgbpNK9ac*APIlegcI}7o*-}#KWo0o4MM1Q@p<+v7zx%IL>uih1idu0%{ zf+t&6j1g^K+EU1Vdv9*ScLM0x4?H?c*t-&OuMDDAA?)4h?JQr~Wr+LjeGGf|V&~9a zI)c}}xUUSN*3L2T%!%X0+q}9qL*ci#@fYs6(jK#W_I`~x%M3u^mOlf(m58`;elm^W zA<@e>zZ}n$pz}5_-?LCK?rnRJZ{0Rx5%i^T>Qwfk8zV8GC!Lu0Xlg9Z&5X!NsFSDiGj%zb6CYuL8>Ci+87 z^XWz(a{JpCYhs?&?~?-)H;umX-lq160_|txCVV{=XE9~Q!wOqQQ zJ#;p7wyWz;U1ZmF`vWU>?++LqHS@YYHu`rcdqUa4(h^y+edBOkAryAftIqF_acB} ztI9@~h4z?fYpvTKOwAfNb$@VS_I_u@RE$#ge!EL$OYaf+Ew_)YXt_Q0b;xsDRxiwN ziHsQ3a`DW@mR>U}TP__DYl)1lYq@Rg(3VRUZa`gqT6(T%Xt{XAu$J(OSWBOogIWql z3~uQ)wzB08*tuio>-(Lf=Cxd~Vn|EDOzwfkmJ7$mTI|${mNg@qS}vNI-(s)m*^RJlNvbJTYZD>oMg;`~H?Y1|6@c{Pqip~2iT3lG!(g&@)W5pbdcq3X%%S|np zn*0-x(_ZlwW$LJTM0*ewv2)|H>!M?7+U%sI~9X$eyxJWtnC9W##)9uLvQ>pt4zIoSoQv zW_Dr^n%RlHXl5t&}O7F&=3f=e)TAqns2R2*#F0>v@Dc`?krgdQ3Y93#l!9``0G3(TJ z%sSI{&cLzlvDeu4xh=P1F9dN!{c_%MV(eDw1u*R!mtG;LRU znRWDAyVJY9x4+$rr2dQDfz6{zIkHyqwp|aVythAP=Bh8J-IH5pm!1DnsO+^5*`^0~ z-}KRYs4rCZ;@`RQ9>j^)J*Ncio`|I9;p}y_S(96T1nlq#{{GHRc@merfk4Q-T_g}0 z52b?>j1?H)X)+NE{RJkRoy;|{^Bkj!ET)tadI_hSKuY8^oV0?$5MS062u4bg#kn3C zoTBWL82^qR19EVdM&@9g)_#qTV1DQOp$Y|e;4^#=3fRt4)E+9zWW~;_OsqHY$kj*< zSKE23p-TydZg==jn&>&GK6GdL8&F2SfW^>Vc;7jM)B*U&MJ#PKB6wX;O6b<;v5+&e z@DciD1Q$|Ppuo!DFTq2<3cYW{pygE4$gdq1bt-B6o+EBYT4pd5JPSGuRtdE27$%F$Nup3`}zykdpBcDvS)wamDlu zzA+~<@CaATYG2-LMFyq)%^1qTK=B9msSEIN5W(~f7a((Bu`n_$~njhvdwI7j^^S{@gr=oGBBGiEb+g6SCKK*oKPCriec zvDE3P>;vRBUG8CZcoDU&vmm)Bd7hrOB5zI>S#*&!(>X$RjZ*&X#W^81iejokLq!zWui_omdtEy-KM0DUabznF|^kA3j9hvbN zP5q(0`T1_asEqR{{;_>FuEYZcC$`5cM6Jl5WvVpeOz!l*s_eLoN4S^XN`2DwcTxsl zWfXb0LkDCE6imxlz|4Eo#~@RnU`9qgd-OpjkKjPTtc<%@(cd-M=2$s4_ce>=nh(yF z+|&6%J@!jCB(-BwNB*L^Z!j`DkiyZ);}@|=Wk8Lx@_xm^m={QEGF=Gfy}R^4A$ND>^gQ19h%5-CxN|Kl?`g^l11Wdoiak(}lgA%cM;3YZ2jm?^xi--8Ig>s( zkALtGsq@l@=bg$?s1KyRVbVwDeZ~5l0$NH&-ZIu)C~AXF46g7^FuE?3BgGk!RNKUUqv5IL7nVa)f%@njyhF{%K33kF6P! zf*RTJP>|+3mBMajuE^>@gui{xyO5?X2y|L)vRZlVC|?-p;O@s@-XeDBqCgfiW0A}2Mbj4t@_3pE z6cpy&$Eq(0v~%a_DS5wT`AY*uJgx!-lk$!RBWnX)&NWS)kw=Gak;?)d-2-lZURUP7 z+>`6_x-tLHJ-In=GV8k{kk#Gn^VN3VaAvqNkX39HYwf&0GsjhK3!H+jcHSE1xY{-0 z6x?R#jb)wdJjFIUk9P|r>pjJGJ1@YQwZT(7Zs%pQ$TgngIXmx4=D5~99x+{QE0t$z zw#tlYXIEyUj2v<0<2*Uf>UHam8A^S))DdmDdm@gRXkq6bP*q7*~6+^J>*hUtxx=n|n zlq&-TLy^n2BlKbw-DJ1#3$fi2e1wAT=lO{DwE0JU_H15x;K3_QakpBp|GK8k!3H*<`D4r{TCw?EMw2=O^g2oJ%9gRaDmZv zXK&Y};h82v!IegL6m>fw-;GeX(6Sp$$sn%m`9`tAbD+s(9=^wmznL!JANtu1ov7n) zX8F6?f;AkGh91;)X@`q#gaZCynB8cs@m)suAr$hx(son(OOfw&$UB*@g(K3O!9GN? z@cf;+FO1IgYdmx(A{6ijzunxK`QnhTqwYJS>p|T?$b6?yVel%oc8r49ka;f?U#P^MA5LCwgNw~pwJVGH}er+%B##~oIe4kxI9!32k*s)TSJr z)mVvL)K`f|_{(G6VU4ugZLm8A#_sXy9JKE6ijsL;8ix`sRrwx$k*_O$Lmo2`^txxU zeSEsNC;Ftfw>#LQ!Z+~G0P;h=aSenY9?io`^_aaTT_JRd@sW-*z}zbhSm!0~!6IIW z{cCN-ly|K2-ZYWhATWXCT4WMT@gIEPr!%;(If-EIp!J14Db5)G*b)iEb0&HkL2GWF zR+d6gn=OV<__-wV5gcpDDr1cnp(ma((W!)Mcrr5n$mX_eioa!3jIDc(fhmM*U=rcA zYzo&@{}x1It1X>Jt~Heyjo?^I?KmTcupox5_2a??wy(`oZ$o*rpjeX$x60|n2rfO= zRAK^xF*FU48J@rh+l5T6S^$Ao1J-&&W?|gh&=wToh8bh=rUP~a!4@LpBo_9K0xxfo zgH^k=O)`b?f&3;=PTHE{vo(#jetciEPjDQZG&_Z65*sfejaNUs&N-oUBb<=DxzA3K zyyAoJS|Zi-<_yB^*ev2X+Op0dcADrE;#GtcxB@OITyEvZ-+;scKt6&mtA$O1SDdyr zgJ5r(BWr{oeW?r2Q(XpDFqj@tpj6CiNDRD-2xaYk}nAwAw55u7TRpXhC((}=;YmKcg)TF;0(ttTg^bz%+hW-R9}HXgQ| zubhvFX~G5(*K`gz-pn<*kr&OtBOGo;2=2i=IXP!1mqP2#*(Lrti%uoy?2`2OT4cKs z0i7Z^g)y}dEKWygle2OP=iTK9j@3{XXXIs9XpA%Rp(`}U8R1(mkZon0k*@5AHI?9; zHN^)b!hm^6oNe?tx){0K6;k4i-0uqMW+uDq%M?yIclMo;oPEoK@#O4V?w@_j-Py+( zh@~?*eWoX;4{A-r?3}kMpFNZZ+^N{?5R{dMwM{X*Athx*A*1)$)AG z1tx>%(@|p!^IbJnTqZJ;>h;sY`R0hd5naa-OYk6qYweZhXu8SOb7Xj?ZCyJx>}l)T zsbQyeQsim4bp~o?nhcW(j!KHvXt|B_#;A2o?r`9Uafb-D-HWk=-iw$N_b|B}x`4HA zBFX6K&lEV?aG|nxKu_rUmVP#%#1idu&nOoa2 zqpk}=Zv-5wtKy8f>&t0eEjYKrR)e+7>YA8mDfnpvWL%?hj!i*`ax%Fpikx4mRIM)! zGn>~z&yd&9q#-t&O}4Gmk}Y>@MI(G0PuV;muvQVbVR#&C{k^ML1&=Btc=^#3D7c$g zjE#kTf(^ul$vE!O4M>KXa3?*kMLlcKd$y2_4f!#T@m&caY%RgSbd594ODtU75FAY} ziOu6xHr7LeX3=nDFdLf(nX_4!B}M}k^5MUmf=+RB=e%<3M1ekV8<|)-u~%$}DvCL=8d+`>~`ragGRBC2<}oS1D;=uQ;REBiPnVf`S6uHF>}vvbe2AcQa%Q8}X=GMr$D<4klK!Gq2i;t_Wm0!yG7jLt>Ct|9p1 z9L#^)oEXk`^~7p~5Oy<0iBVo;u=;mF_Yz{NcV0k$k{1vS=bN(vk5*K`1C?*0QDYgM zWKyQj2HcauOmx6(0n5RqDFz57(IkFi;{@h@X5~CCd7{P+CfucKfH`IMMFAWF+gCAS z?yXzPR>ir1{nRvPPXg8ebFy+5?9&J~jOt_q-Cx_FYPUh|Cq!+jQ1Iw!0=>6}7`@jl z*MSR<$p{YDlERX%i7%%qux6WI(=nL?%fpr5RTw9EygF9&`$Q4+!EEe|JNIuw7B{{Z zI;^~74ACXT%Xod~t~Kk%xFxA)FL){VV^$t=t&DvEd{=Rw#gly&$9fhqV8*ID$ZgwY zUU7!A3@v`>T0E8HwHn%Z3aK`p>RCjmcqt0;$J!_><9t>o&7_D&%^dp_G{Kf2a&{NV`1VHlhXd%U5`cCd%CeUi`iDYSi)YkNE?+d-dg%(TR2 z+rg2@HP-Pe(mZflI$JwH#@`lx1|6%GudP|bjcdYwO9sPf;KIfAvyj-Yc5!WWKRUXah1=FOO>?Se zEvl&czu0>ZIH`)PZT#N8-96ni(=$VIhCDEUAYsTsPzQvTC>cjZa$HHm5Jd(sEV}BF zbV=H%tYTP2*Q{#-Q4kbdv*4;L1~7neaP;;6Jf}`|-x+k>@7v$|z5D+DduL8R=bSoq zs&3u7b@Qnye3ALT!}pwpm_YDfsx#)~9Er&kE7e^lUbJiQFP8ALt)g?n^)YR9!dzDE z+P1-Bve>od(-B5ZPnR2;7t7@T~Fy7M%WqB83I^7(vMt&&T6w-LQYT#wLHSFxV zg*7?3Zkw~b*)sR^vrfK;`HnLDy=$OCK;`fH%J{3U4ls zt7Deq6IhuXxFnx58l#>fUDT@BI0}1TI?^Z?VG3l{D2((_xSfZI%(0gFXc+G$r<=DE zEBo>dD=1gmB-IVwt15TPw7@$Ekra_wM7Ub2t zO(@fQur$AA%TTtr%jp)X>UAj&$^7VH?`%v@>tLpI%;QTyeMAh)wCyLU5>;iQm)%Ms zR9%?!MHbUjjH#E=%A_?D1I)ReCCnUSsrh0mnY8IxLmHVf#dCF&Em@m3OqY~ol`>o{ z$e5l&i?-??l`yVnR&-s-t5m#(&$W~gmUV4w)~CbI6v7Oc#JobKjTxqwmdvfS_&F7f zPAuspx@v7Ug;XYAGcHJGtX$<^lIaOufY319$WEq?EzdSYUpI&b3cIaaqkggi&}V6S zMQl?I^QU8m@u|#Q@Jmi&-bH9=PS?#6DtfT;&wDxv^~ggN{@JRe<)Joh+hgB-W(lU4 z_wIMOcVT|}SXlZ!8EP=AJ!g>zlbqH5p(Xh;nCx|5;~t0Ij1w{!_VvzfRqSED?sP8; zdsWn%-51%sVSRJGnzZsbUHAoIuTFjlGu-#<*Y7M$Xm4h-KPg=8XIPo7zT(98C$UQ2 zf>yPpQfx@L3dJU&x%@NPi*kJB`R#qCnBm?GU>Vqrx%y9I0OKIYjfy$mb%OKzO3^A_ z*!!(J$quNe$t3r=UM*R1tmRmafAw3j(MJBWBN|&{j+^hrn9Gc4voNbQjtDjKwMm&$ zK!2eOtcZ@!i==Y@NShp=G2{7z7{@Za-TtB3KY{!mNOrxuv4$x3wneEaNfL%yWxhn){o# zU4CKi?_#fi;NN!cZ+@?vT7vRj{8HR+FiTLr59Vz$E9Ze>jCU(rj_C1*f^YeEm@B+C z>ci@D`~2Ko;WF%Dn(#&wD$f*-12h)i6ydxld}bBE`;k=?*>03;67kw%VesOBGiru2sBQ@ixUr6rWUlLGg9P&lHa<)<>hT+*XRG zEA~|!qxc)ed5V`RZdSZU@d-t_*$clvsVuieAe~i;s8aNZvpAkRlY>=8pRtF|D^aA z#l4CL6+ct_Q89*&&T{K2wp2V#QRX#3`e>DBDK1lNlxFg`Q9MI&pyFu7#fn!cZcvnY z0O0>sl@BR?qZqCdCq)SDE>iltKuVyyA|J7{8aHr z#Xh)|PCw@=u2sBA@kzyubYoXbvALqm6OR0yRF-+dArDe{gyKlW@rtt*S1GP1Vw>Hd zcoPwW(`}l5pUN_SIP{OHUgiylyj#;>QvF*hzoYnf)qk$?mx|x1o?{`)3oG&kX|{{R zYlps;>LqSF^b)TfdWqK#Y^V08t6dMp!HUBbCn!!)oKA$l1u8FAyjpRk;&nvWZB}`U z;_a%xUuC|t&-IWv?67}cJy5$D9SwI;3W<_@LARGQk40_!5>ihh@!+@2hWB55yO`tRg_V*AkP;l%cCn`W0jjJ zwo&Y$I7m^BkFY;q<EUr~HRQI7X0S004|`AG@u!S`{9QN@^Ib;Ufz z`icdLrz`eQ?4vk9ak!$KFTnp8l_w}(s5nzm9<#!3k;?pPi1o7bbUmQ*BZ^Nc%6SFs zUQqcZMZUq!{BJ3~rzqzi(0{7(QANI+L3=qL0sh*2U-fyO0lNalQxsb%c2qo7vAbd~ z#r}$e6wgsSUy+|k(f`YeZz>*C{6O(z#bb)!DE^ls?mUX048?54JjFVSjTM_IwpHw? zc$#8&#lDJXEAj(2*7sb+af*E9i29j|a}*aTE>XN(@k&L$#lw8pD>A|XVE zO%+=xwo~k+Sft1|rkH<#B0u}2%vVK;qZB79@+)rYXDiNAyhM?os4@L2#cLJ+ptw` z;!pWa#dj4yP&}geg<|FTxbVbJ@<$czJX|NKTwjqNoU)u#6k92FQtYbOLy$&{7Esw^L>r_)GJFovG<(De~J>=3Agx zs(7j5b&Bg1?L1!hsQirLPQ|wr-%&iI_=)0|igw;Ext>A!F0WUB)f96Tn<=(bY_Hf^ zv9IFUio+Gk~tgF~qv6*5U#SV(6DRx)vqc}iuxZ=5rV-@ZET>RLT^_Z)8iQ+QFYZT>r4t5o; z;~?Lz>3>q>H^}t&rsA*7ul1waxx7w6zHG&6iVYQ;D0WmlRWYvESFu=eq~dtR$%_0Q zn&n)sDA!|<<$4UbUiCL9%5@j?kE^_0@j1np6zx1%avcVHI}g@Jnr`R8lIt#{M|fQV zwDVlabr1eyAuhpitg7D*vE}uTG>Mb{?y2mGPmk=<6#sQ9MPlonj}&Uz^|RJhdC8I8kw` z;%vovikB!ZQ@m2~8pU;rn-p(RyiKw4{8x{u{z=8%iZ3d@s`#ejug!<`gW53&CAVWl zF;lUcVyk`#pu6U*5O2xH`n-n)I-mds3 z#RnB1ReW0US;ZF>Usile@g2oOik~PRQ?&DHG2Q^%sh(nU#X`l7il-``sd$#+FvViU z(Td|0rzy@-wDW3RqOzS=YlX_I6t7dX^J;BYnXwR9--i?#2Z6GkSL+>>-&Z`WXy?^p zj0D_?+SkihosnU6FAd=Uk*Xy@Hx5D4Z!OR@6&TIZ{N zwBlsN3l--m&R1jv3HtkkVnXp2#XA-6QG7`8F~#kQ&ndp7Xy?;nI12jzO0it=C&e^; zY{c{o#cGOn-mLm67brGYwDV>$wgvO|Q5>vj=gGQ2<*|wkd_ntFit80`Q2e9f?TYs* zKA`v)#itc_DehH#Rq;*5_Y@B)ex`U#(awwYqsk!!iD3PrigsSC8YAv#cegd;G(k+m1_bko8S@Gx`b7 zQ|w~XdP0HIaHmKUdUkc3d|XfQ87Z>Jys*IE$mfK1vFs!$EYGyH=scWv z%`P@=92EX?C-i^7fl}kW+S$dXT?U2UUy08jo6**919+Q%rwwkiULc`_>nmI$6IL zz@snE0?4uw{``H~t}oH<12o(LyFpN%1Rk4N{IT6xrrkHdI@QttT9VPl`or*3!EO`k z_qH_xT08Tm-i&#pFKXAO)y%^DUyZrlwoUui`CNWI=Jw-5q`(tmZeO=;eUEkV(8_~l z3pNK|&WMLrcaI0+>*A4POZ#OU`>Ctj=B6VNZ{XqIWu&hO9LexvYaTv^I6iBfqh~D- zZQ5Iwv&}8oAK#1Ifn&j}XX0DpPQKIN7I?@z>V>NBt3KsGnbX=mZF_mpjqMv!7VLkZ zEZEv@NjbFdKv|?{NLi#CrR~{~V{YWk!`;1Sdi5y_cAXvXj9A>b?{&29azs`}9l~|I zBblMQkL3hd#@;e#Y2f;yWjWKTPu)=-c88W__J3{4PIyX-uZXXlGPEpGXJ}b)+OR24 zmAeaa+I5b1kKfRPmN&!0`}+eo9)yRTN5b>6j)bco=$VE3Z~16%S<%viSgU<;w#dWB zyzIAn7Jd20rRnPv{cb6D14AN#W>r=feYt&E&ZY)&XsQ(>&To-hEk4}2${AZLvg+nz znQr9N?A5UiX)8mBW4`&wQZI1iQq=!yCu2?e5yuO!Nk5k91=oZ&R=cixJ7*1YcvV+s zu8OX4HbyrbEUU9^=qI78xQ@YiEFO+$$6x*=@Cnv$&#v;wWUSZKyUU}!UMx?ayr(>h z^$y?+Tk46gy$_ku0shkFP1@BIY9Y1bdWH)CDq25-vR zxU*q9{2lxxaOKFdK)%~-dwJl>?d9pcV0UHazCmTdZqEAbb=`}%m%CR|hqTGhlzY9t z%0Bb(S)Q{VIVWefc|ZGTwzDd@zQ^HSfuh4_Ihpb9WtrW&mql7+fD2}Z*Wc8G)nP^24l-FFZZsz;ND>;+H)i)Z+$YetEZF?MUfJ>JzAka6>3jPFaca8MrS6;kp^dfT zSsTaobefOYcd)Ge%5CvY@$2KG593SmwS)F$;dJ$O#??ORq=PaBp%=xb4l0W*9uhx4 z{%m=;U{G1+$QP$P8vi|dR0vXV+JGs~m8Tal&F#jpWvk;G<2S*_yNH#&{fJi*Jrb;* zb;Qf9gMMFSU;dOXQ{2;@E_d$C*oQUATsXyTNh!GRVXjFX@&gaQg*E9Hc>I`~$==r+ z_5aiU8WL-|e|&!2*6!7hoG0(R()s)^k(5%7$tiv*OiyrmyeY_vUi9>A=Iq zk;swWk$aCsBGdQfYzVD)+YLOtI^8{TX*9NR_mT7^fuml)JCao|r)zjM;@a09UN3D; zr+C`>y=9T5nOK)$ai^hE@NhhM9a>^>Z0fV+Y0?5OVV$w|p9Icn6~AT**L}bgv-Y&$ z+JA^%g`3$MgEyQN&peV5JP40}z4st=Bg-c#Lq%|M2`idfqesyx{=#HIz1lRn7+X~vfSGiKln*((~a?y zJ{p1jwE9y{!2;=5rC+~t_o$Ds?;;iYcf%hYknt$zL$=>vd5=Se!Jy0cgEB{9^!~kX zAhs;xUbn?@3wz7$IFCTw>-%x22?WymLFtW!RVwcF6G-tMqE#~PH6L|&3`!W7oHw7w zk2~#Du{>uIh4^i;1Th#sW%Z&TY}4=y~e|4m|PnV`*NrQ z2x%Nf%OM_ixrjl>JBv>4^qAG-TTY0F%>y^%Vb6sQjaU!bZ1NtT-c^o=&7gs?FYtqS z*yK@$#=|xx2J!g^65D1NF%sivP9dwBr2TrUW#Zy&G#=|zLkrDkC2DT_{cBVfV%wnD!o3l{~j8V}>Fgwy9Y%9`@Oinv93d z#?pA$bezt;ha`&lBQdPm+?8@vu$aWISxPk}n?i9jG4TVgHe?o~tVl z$qE|9{>obKj(snwO=EX+onDC6z@Qr2~?(nRHT56(*w@k?@vu#L z>)eKv5f9tMt8SnB0Lw!>Y?IzOw!D zZPI(^eo23bhs_|lfr9?I3>3zA*v5WP?oE^t4_jV*K|JgRlo1bGUcf6T&gFi^c-Y*P zBp!C04iOKV`-sHDZb=2=VTW-oC-JahAkcv4i?dsj}OXVabg@cH5K@@*}{88U5J{WoOoS*nBpt zBW4-{3I$Ecjd!~QKSa%JpBJZuW=5p%eDh=Yqd>0>?YWhxqLx14e_vf zG@~mCLXLRYW;+IR$8&`c51Yn}hn-H>h=(mN4j~>kU&LiRY_k@u!+wSqh=Z|UbRqGuJF!f}!!`=U!~TXVg?QLTfq2+_Er#*1jRNtoc_GSp*hYbP*mG%tc-W>C z9HP?a!U=07ZHjo-u4#qGP zh%Apv)p5D=*?l1sd??7^^Xcq^4IxSe5V!hdt^wj<(*xpR|Ba1_zZW{|DHY=BMM=$p<-Z{yx7r%mWHb15+D_O- z*Sgj2geDZEDipjPzYW}1SoRtCI2_ASddA{5oC?k@s&Y3>&W0imYWNyj*X>@FuO6-j z@pe%|zNh5&5If#-c$GRHbKNt=j<4h68+)hWbu6W4m96miXUO+}3NFEq+c$@0@C4zn z)Gep3pXm7NTs2U^HtPE4Fz*wP85~N2V-FBBzCrZ`Y9_(4&lVM5=J)|kSTKaO8z{P$ zu{pTq3yMXT$5I=C>JcSi_Mq&I;Mp`oK_(FPU|EZEGBwCGM<;i1J+{D&&}{$}+#d9k?vOm{y5b=YA4nDOE~Pu9K6ST4{vCDi za;=9;o#x?g&k-wscDo=x zEh+@N9+68`6t}TFkVLi~QJbpMA$A6#690*8jnkC>zecuh?2mTM?tle*5C$C+=o-5j z`9?(U9*AdMCd?)XOdxVxkpvi>uoOdsXpn>#VP`^EljG$h5(sqgGqJ6czWDfs@#O$~ zBO9UB2u+NZa2^Oz=SmaSu?SFBT53T?L^%RIAY|C4QZlvzL%5Ir%EEiNr~zS=u*HOi z+)thJ2&;uHCh$F81i&j|U~BTLIXXDSgfE31MBv+*){6XFAXpLjfsIWf&x)cL6j)*5 zAkK)(cJ;|uUbvpDsjM`aI#SQ`33M&`R2kOb}x`wr{jV z!;`j`#32OJDx*@ZFk}Y`Wrba56v3?85L*)Z6&AD(=C`94C6nwi6&kYyky{oFY;ru~ z>a$6PfzVn6t}x@#}8 zD^^eDfYB4oCLTdxC}nI?0tq3X7bnP=0Jp{5i?)GavJb#rkTEC$)rCEWAcr=mn6SlY z2_(dMTr5%S?lXGA4q+v9{0G9GM=*_iE{c$)QnYQ9DnTgO*o;(cT38|$+ZyX3_FfWQQrzAn< zfDslX$b4>u#R)QB8ev+ZDaz%Blp@L80SaSa3m4T%kms=#!5>Q!WIhLBwxg5Jp|X z2&12sATv_*=Mbid9_5mmXM{+C%u*v{`nv9@P0*RHJBnS`^w*ID5-Kq(L8hJ&N)lw6 z8eu_#OnW1sdSJSNP(8vhqo0)^bDrpj5oU?LB$yzx+z99`U{)F-Q+5S@x`@4*@TjmO z31+VtO5pAw+YJ3hmSD0wL)1QwtxYQqMARS)x;8pDT)R;Ftn9Af)7cQ;w8Ua}0Suhn z6DEMb63h-Td$Df^n7zQa1I#Xw0cwZj7)2l&3N4#(JnF%sx_n4iR;3O<0wATHlWa^>oA&%$$rQ!B<5)>FR&?q|B zNgn86{&?wXq_Dpu7At~EgE1YyWI=+=gC?aU!LD!if?=tyj~uqYi!XL_5_Ybf1Q~X9 z2${YrIRsT8l|VY zG)hl(X_gMNo*Ljzd@@lO?jbjW!p@*I!NF^S>&{D4p^ZZiL+&5T8Y9ATOZFw~^>(WHmV&V7 z5Lh44vqGDyv>h*aCvx%2G0Si+~-N%r+2?_$y1p2(3+l1BC3}JHT-F zzyXKA{aA`3^MUA-#}m{PX|7b6Jp=cRKzS;;Q;fP#SPjEh01l|wSXP;$bSuzrr`rG|M%El5J+G7Z4MuM(^NYHtV6pe_nVwTQGz+rE0J_D>WfaPrF@*3n< zL!j8cV{#D93xU6mdEw2yy{JVYSi<{8T)e*LnHS!kT$S|Ji z#gxIFPejyY2|ewe(FJihHOy&=TQS!2q*nRe`l9A9BGNL}cvd$=_vAWgtY-#o?HkHy z7|N`N!W)YFsF&Hw>rhiAH8H^^Aht$mW2_L@-GskwSPvZ9GVCIBaw7z7Mz~#Q z+A~^L@KWFN$8R%6`$fWYt4|li2GVU?DlU}zd@)2!)_18fldn#Ab*DGXBpudU7%u!b=RBIigABgPywou;mwj*%GH@w>xFjJG*Zv;&s3t$w|M|e&-+=;g~&HBlu?_l?;##AgF;8c=T^eW zl)Xjym7+FFjP?1&SVguxyAwhKqqxd(o1yE1nD`ZgIYWtH?`S>ro_dTmo#BmO1zRIZ zF^XctqPIvT`!ket`+T%6wpem289ig-f|5zj|ATnHzZBhf>Wq?( z?MIg&nkT9^XX1G0qK@sXxNySQg{Us3dBzVS5{@6=nm=v$gLuKLyEA(FxH+>+X3if! z2lGFSEtv>M^Ttk_JJC7o?BV%mw&|2FQ&z}?9BtaRX_w!0_QYuu5lgmN{y&ayncs5y z_*rvLLx|#%i3?gzZx6X-%G~MWfRmt~G;3b_mUCvcoY1BtHPdE}Eoq6#Jx-f4cJ>4) z#?Br;JYoLW*^^qf&2KrdU4F|+GiJ7&Q!;z%c;uQkb?ls} zGbTehY3_{iC5W-v674{o1KotNC1d^aq**P;&zw;*d+hj<(-1J(89l25ruvvUcLtgQ zjew>=gV?5+K5p8?87hoN)l4f-mu8(ab@FHy$QG0aw3*O|3#OK|c1B~Z#$PDgV*dCk zIx)vDPLZMkbd#rLgqd@(6`axi2cFq)^e}9s*;Cm|O)EQdrl5o6bB$7~HhK;=D_0-WoM7vt zWVHV{w9B-ahy`D$IXSaxijX@nTUwF zGbYYQyU!~@ufS#>yI}r=Ik4^6eylMYH|@eX*kTSo^wC}Le>}*q|KlU}6RAibw^QWJaoTlPj4Sf33F`T>0CBP+?>kdoq_|A+_lj#3H!I$y_^9HOiu)C9 ztlz(@{Doo&4Z(7%D0WheD~?bcr?^0IxuU!~iToQ?epvB2Mc$#Jf8JIj<|;N(?4Zb- zj7%S@I8N~*Mcz+k`tKDJiV~|2`o~q?qj*5^N5u@@frMQx#b%0pT15S1Mc&`0e5vAk zMc%@t{%?vuDrTa)Q(s&06vZxzy%jH0dkP;!BF}C`wE?*!`d~UqxoVUW&sN zB}N9?+;#M**{`~72j9DnU!{E%$0}Z=c$cEYvVyvy2a;}oYT z&QL5-yjbxn#Z8J5(-;1qpp0$#jG~S0yGQL_Ct?tLTk&1hA5r-W#jjQWlgb{(KIV%M zQI5onf}E@RI;uZe<>rd5Ro_+RGZcHOexS-j6(yz={7Wn;_@Au$d5Vh^uT;E7aWxV7 zB$gEN-K6?kRe!I_4=6sXxJ&UxBJ#hf@Qtah>9AigzkL zs>oNZS^vF?`xS9`kbZ>WM-Xa3R85d?iL#%`GX`K|m76KHQS6|2wj$r2U_LqC0Wo!g z$deT>RGh6iPjR*4^@=wr-lVuy@h-(bE7};oPpP~^kuTb_9)DB(Q1P(hSBl>$@+ExQ z7bu>h*h;a3Vi(0C#h!}&6bCAvuV`cUPEz?diWe#JLk^a^O!1du_iobk&5Ha$fcYL$ zd{S|{;@gUUQ~X%*Q$>D}!TjGT@<9^iprSk_f_$>dtrXiTc2PV{v7h2V#Sx0CAixSEgC{9x3n={m3q{vU3 zC@)dus{oXLr}%rtb&8u5`SmC5Zda5yXCObQ@{@|&756CaQ+!kLpyIz8i{li+_T z_HK;lhe)rYSWB^k&nMl1O={;%>$LimxgjP<&VMBSjnIw{mP< zIe&)V3wb^aoUJ%d@&7co?iS6rRk3nx-6vEp=i?~v1(jb?d_(boV&&MnM^*o|V!7f! z8(X&_&%aS_6UBClofLa2_EsFMD06-w-zb&GDPE{JQ_;rUU97T=x%*p{S1PVmyg~6M z#XA)5R(weDF~uE<&nwFH1?u&x$_EtRRkSgBKU4W@#WF>g*A>W*N34Qbid7YBE7n(R zs@OuYgJKuO9*X>klzs;)4plr)ag<`^SiZAWKTok#@lwUB6;~>*SG+;-R>eCM|E&0s zB0oK3z4!$w@u1>+iXSU}s%T>XA6FS~JxRWxqRhntKiMktGe-Jts#rPp@9C=Vp~%ns zXm4ZoR-Svs#^}9Q?f#k)P7Ce%C2(R@|a^r{X<|4=X;dxLxr%#g`RdQ+!9!#^n7> z2dnzAN{7lit>@8FI z2gMNXL9;!hiaCna73(PGEAlgH+Ml6lWBB${d8pz!ij`ye{zmmP6z3~mtjJHY>HklP z_bWcE_@v@?#TOJ`QhY=4fa2d3KT6@)`o?;!v#){1pJ1U;4 zc&6f6if1bhQ9NI9v?4z@XZed1uTs2Laf9NGigzg9t;kQ)nSZz9TZ-=}@-ua&hZRp! ztfkmQ@f5{&ik%cI$L<}Z`eBM=6elQ7SG-7(-^8>0Rf_8rH!0efy|<}+x8i+@{D7YM z_bR@k_=e)&6#uSxSn+d3er?bEF~#bNd5V=|_3~4E+V@cGqc}ium}0RaPQU+Q>{@%D zqdM(SCwo8a|2B55K4<#h9=7)1DsHX+-DX_o%W@`uaZ4+?G(w+v9mia|*t9dCz^S8C zqzR9A!t+9O3O?^c7I~u@r{c~)kj(?uVN7Yh%54{$HWmuYGcAgaGZ}r&E;fz#L;dC6 zbvhJyz{+x29@m373uN|)baLE-ne2mZKzTwff@lKyT2&pfR`T&A}&+rvmE zjp=uR{B{>~!1pTFNYj}9i1Ie+71$M70ciWn1K|Djd&RfD+QFK!lDs&_OW zQCXQ~av}Poa%+YE7Q z)7GSI^o}`2Zs#J$ZBrv}SFN1uvRB<+?}B>KRq59`M|&*~CGI=!jCts|Gsr2ZiI||z zmhY_7IKC^R`{DlG-LJCU#$|!pY3n1`1)4cWi5@mlew@jmhWWzOb( zWzM$U&{*i<7vm-w9I3H%*Xdf zHXcM>yd(X*2-~`O(U;FI%ig#?Qe~BMG_pKxU361$)$+(QM|#W&9@*|i+GVbO8BuSm z)r}!yu;+P*dF!r;Yz(Y%69>y0t?V}C^|HXb2g_P-b_zDe^Wrt*brCtZR=gfc3}(Jr z=FHkr{(6%a%U>@>6ybLdlm&{wyU=w#w=B5$_G6JKPJ>ekqYJ!;JT$DPeP%XhbRPm4hgjA?&7aF@s}Ly&`m z+8+=0f3|!_TlUtsGcN1Jp6nj`sg3Q;efBxcdhYvu#3_7af7ke_@t*O?@s~dGT9ker zxhG>&)>`xk_KeNw6;H8OyxAnYn*HL6Es|(>H}T)c^j<<49?; zr+gQB4bsqS-t7AK4^7`{e>}V=ys7^8SAVyo{5k1c&%uiQcNhBRz7Mkz2YJr^Y7*@? zebq&A#zp=Pv5Je{-4tgl9gU}B=5aQo9eK#kOcH_XqXJ&?uWV!|Kp1PtnY^#=gU#^Z1JpBH}Phd;O zxTQDUUlv#zXtk?+#hn-l%7RO=t@}S;eiKe7 zC)}{+_fR3|B5cEXsD>NN!l_GIi!9bJcnCjfvxQG9gNq2__u}Y`_`PYjdIOLrdOzAG zZEI#d^1Wb@c6&AIo%H_rxd2=S?HRu}?UpE?=*EihllI3np6mq>f|YMSrQH!~4lSZH zI>BpEt+YEmW)0p+=l9h99Hxxl`$yWikwwsElMkK&+vrKsZaMhu$H|KpM)>2h}Dgl8QTUw(YCdXDDiuv?J}CdAEJSxq5gv8 zbj}XTr@pdoIEi@@E*eEUMfgNER!#?9qIUhxrg*A~!B}gGT~&<4O0h1{ZYpNR4seA| zQ!yttoK-tr#pADywD+j0 zS{h+wnPkyF{^3Y&vVbJ0^2b7Br2$2ba+oqP-;5#P5y1s0Eq$z0sF+1x)-W?R*&s-&`#jz{7MjvF!I~j=I+nog+($2>Cz1-H!T0?%=TWTcuLp`?3 zL?mT1>7;kiCQXCUF@XqMCwDphjtgj|oLs(a7)AWvzsM>Ca}P3oa-h1ABe`=}Fyi+b zIWw0NDMt~%*YvfV+`psHDB|~ii>nIkvAIoYkNCYNy>;$0C^U-ry$re;C}^MiG0Q{z zUX$KAw}e|A@p~EPk@0)$)8E{H4kbmoizp+0ud(l$JDB+qzt;>ky>knhAMtzTAq(R7 zUe9Jk{9a=}D7QY#NBmwk4w^Z471I&FcfZuPSmM4$5xdlJ5)h~N7> zRwj=Rt}~+rZsZ|YK9hTp8{ z8EzziE9>0BP(=~HmjYe!P1Pvk_Zm5zJAf^R_`Rc1y8xy}Oea$n##-%~`=Uz&X(O;{ za%?HJ7EOTkgZ@1-&0_by_s5x(ffeHSo(ipZm5J7y{Rnhvk07Uq zh`tXYR~lbr^AODUB?zG)(?dbNEZe{x&5E4PBLIRDf#>2z>LWbE11P~gqYB@Z9SyE2_F3JWnbwqmC1TyWPd^dC1RDcNTu!9%9Ee{+7CGSUdO3Du>{Y@geg-1rOlI z?VZCiP6ykKItfqFM|5K$52fyN{2=fz^YYAs@7tRYy#2D@fNlh;z}O-M3?}3Dt4ZJ%UAUT{MuD{)<9t}|f@M?j`zN;^9WR2}0#Gw?tV*ZxI@o?w+4lFayXHh&?t(S39h-^Y zyNzGtPX(v(EZCg(k8Muo+3gAtpQ4&Ne&p6-9k-y&n?X&bj;eeFiibdWnHYK4mrS0_ zfaG}_Nw0%UJyhv5X2;!|w4D-==K2wK$CI|IbQ-@4+v7>wtBq~lS{VL7#;+=!QwHUm zklm;c7WbA|4?J3IzAzvAB#c{wnooo91ek3UMnh;`8?Hbtki%(t4>S%Q2w~_5ps^4@ z0lyqq+!u0}(b*M9xe4Y8P@zq1y$0IHpm_v@?7bi|lPACFlD*SY%wCL?eK2~F*=fSW z))S#U49&+T`%4h1_vANAvd5yh#oXoxq%{8mKR?0pM^N+kAymg3-Bm$_%tUj1rOSGp z!quRRV3QEty}3njBCF60<|l(%FhQz+CZz5lWMlO?uz3>e+}+!0KC`jv#V{DbY%7?J z)t(J$mSk(iYS%)xfc)}G+T9y_o>^J#-@@o}kW~LBFbN8*{)1rd2Ng0iv)Sr%b8;}n zqX>}uPK>jh%I16t=DV1mn=@7y#|DsW&Te2jf?6<(ZqBwhp_CnP6n371)~)Mi_MxZy zp`HxeiL_@*>!+bv0%vhfP6dK zlV84{?Y3~U7<^n>aXYM@1{KnVsnU`Mp?TZnXG>Bal;5MwU+Cs=Zc}N>FJW~QBu$xF z51j=hP1yiUeNZ8DGoLnPJ9?yy>B8{K5KV4dH)o>t*b#Z!(+T_5ATVcB;KrESpGr4O1omW6(Te@^g)-_vDukXmC$BrxOkh(nkAW^&&{t=rEX%DR7N`0`nuNkhz)9 zt`R*_#z2N&o@}_MyE#`{kJXV}6(k;8foVa39?t}I2Nl|U)+76YoV3VqCOvj{vv$#= z>`h1>!F;q~s@bEUnFT@{u}0M6wiAAHKyFVrr#233W|ureE^ z8f52V2L%<4-@ zY4WoLm@6p1#mv9l%~`|z9LleN)ny=Qfz4oUq`($<0L-63h0M)-{x+rTiFOn{Uh3u? zvL5#!&u%(ln|=u90}Aw54(2$hkhz)9?{N(MIQ*SJ?lSEExyZ*l<}}2i40n?NM zJ)QyPG*F?<=l4iIo_L!A&b=J_zx6l_d4_<*;|wsgR>yYVsPzxrvYy%B89y4u5rgZt;0?xhLO)IaE@jhhQ1}dZ> zO>AZ!@%i0{E5H2m!yORF?V5)IdFHYQd3G}&ZI~*D{tuz~0EEIhVo~qO?~5jXr;C}N zBUU-Ajx#@Pm?|SyjRIV3fOK!9-jmdq!J+)vv&f%1cR2;7O+jXBfH@6R$Xv9yZO1jC zjAJj`ZcrfiN4ploU_S)Zf+?~FGayX^VV~g|9PpTrM=a#))Bz`zQu|9`u?*CLDN^$r zAZ-L`&EN63t@!&s2zg__WnT8D`(U*VBwK$EnB5e(_1^>YH&CI?XV*XmC|oGuwr>F5 z#s*^h>1|;?MpD>+O$R)GY0}7X@!SBVZl^7214SH}Ob6oC(2v9p(PP&Dmu=zKA?~ z=!70W2J;~Wdi)VgIjGR)vun%kb_IL|Oo-B(+-#R8z1-$in_!FswOESQk@ju_sSu>? zeKqo7gkgLC(aq_{e9}s==m|2d1ZETkX(cdoKrNWZt`qz4N?9lVt_8Wbx;Zz{8~gE9 zuwOw3?8jTc+)QCKgh#+U1S+)oY+vRUyqPeZoPbaQyBFDV``#WF`P@uQ3z;FWdLgr>Z z>yfSWIQ_`)Q{*mkb0*UxTPe~Mmq#FJrG{YgDX^6~f$0D$WNzm3w>xD|v^(f=wwuG# zbMe?8dHT``x8x)+6DZK*#b6eK3YnYv)MI~v@xLgl`7YrEbVD77QEjQ5?JDZ)V<0=zOellPuFA>fwdeeXso zIH4eK&~-*nbG$=t9hXXvM!(?hoz|LL z##le+X0UAIdzZET%0o~55VHin%_N>w2>^@1$qKB^YJGOTMhtslX=X9DjZMG9Ql7_&YkkaXhn?mmXx=uHU zPT*Br0aN&^X>C)5znWH*D*V;7vwelXo)%@7Hif_8FZ|64g};>+x&n6C;=eZSRwE}P zzE?3G6Y($W&QA|5acgvDKq})#PMas4+{b zR>L_N)vR8_Jvq~qT_YsE{ufWX#r0|!^0jOr{7{cD?xSKtt>ng1T_gV_TdHfE;SLYe zNfUnt+^xz$A$rKzUKX4P!X{5p*Bb=@}AhPV&+2n`PxXPldHj3;1?QHq@=s>AMJ6+|C7w8$8SXY9hfH0D6A`e(E4g&cYOfNc9|V&3 znJ|-C=T%!ueR|Z8wd6vR_d%!_;ad;_^<#o9ByR;_GP6P9wsjIa(XM>>2s^&ua|g&K z-4Fg@5R#q%ut1vxZ)S0ET!V%0SEPW|ArUdujV;3K1PM8P6 zL@Y}ZWL6qIf%kHyFfyC5ZV=X$lHs*5CJqQD$ZQ26Ap5$~a6vFZ;SLZsGhqiva*+W? zVOuF5d|WNUtU!XyIuQCR;SOO36S~Rv8ATvT70C=SdIC42_)l%mVeCV%852TP*_49` zBy{E_2{PP)(8&q;qDRH%fmtNN+(3fNQV?48YQRdXC$rAz3G6!XLtxL56-;%ZVeCol zMxwX<3HE3Xv#=9^>@PY0ADt)v@Xjq|--4uooH`7G(m!Va+hN^kl%XWq&I7rpnej_&fG)(H)3n7N_@7|ldLVfH_2Z(W%g^o4%<)`&ZT7jOgALY z!GTX${PvWO$_B#L#rzrMb1(wPj6RUb7yD%L(|j@;k@p|0J^5K6%zC%AR6J6eEf(0k z@VFBE{UVzZ$#YDw9_$)$GDrS7$#Iw|zqAf~suFgvXJGaW^1QolW%9gJYUMHDdFMl9 zREqo(D!LE|Ks4z8X-UI?HUCuY?FVqMI5P(na_%R zBcDuuf=?#Tx0>ygBdq-*sg21`euGaY|CCQAZ)&UMX>~*YbZvuDItCfcUPZpCPbP2L z+N6`8?Mr8E`O=H*bjVNsMxRW6hfgMNYHR%2wncyEOp+*Heu*+zBi+oOBm=VPOVDAe zP)XOhl{oOp!kq={ZO#|a1G$)-k%%pdXr>w^XKa`c1fK-?wLh)FbOYhAvZa*F1Q3qG zTW}N(Bq(semsC6QCsQv&%G#89FhOB6NX*G_kWZT15nmO-1c&?&Qx@R_1&;BO-#)F! zF^*5(^F)ui=*TnyLEje8Uf5xTo*+5dAv4Sf!33ExMhGWXfZ}HS##i z8A-?oVaCo#g3Re4Odvy$r!&qu1QKS{Tw5B(%rgxW6xn|=k}90W?0|wt5X`kiAYs13 z1qm|sjIby{rl}DYC&;un!V;PFuNwrMYZ3Yz{er|0FvCPYlrTZ`bFjU@lo%nHAj6l| zae@_2kXZuaytWISh6UloN=TbQs2agMh8Ss|G+-_%J~S}5=5cCB=CD`~`w~zl>^X!8 z`aGuh3?#_p839`f3=e5Y2`5q~TO+wgF#?tAoI|(*kYa7I~HXb>}p*@7+{fj_?$5Ikp z5_*df8iEWDmD17dF%v>CVGo#+eF;pKf{>kH*kOd_q8&!K9wdIq@K_1!8v&bz9ZKNo zAXbpT_o$_wWO!zXEk}65>dEXB{YU~YIN%Wblq}q0=;J|-^SZd0bj4_`&U4JLLIX2) zm=xvNuF2fii$%{vXLnrKVBxqD2chQ@CV8Dx=3M?wdiGRbV)>#`6HH+2bkgY))W_6S_TMw*7@-|H! zuYs7o@|R5zIB4g6W)N+E@4l6X>V_H(4MzAWswlqP; z9H@p7T7g2&e9kILwg`kiLFfUJd#z-6&jWe_&xAwHMVw95o)ohhJa9F|nqyu?LJKyC zv#2ydrlZmGIMo>hM}#5}3UCvn!0;G@o@ZJ)X)s3FO6HJ{Vm24vri|z>=1VTR{aEQXW0*@y=h+uRf zd=HW)CBp*=^t}N*ox@{0HyuRvJ&dGARIOOb5A7CieY;bwn}AIZ7wBqHwe4sW*O2bJP5)LPT)#l$KPB^ zW;aM2VxyA(76gX`7$uYJQAG0D@efC|{#@I9S;JNRi48$0hrly+ny?Y>6ZK#MS3ZP$ zT`17DgKy+9>&;`&I1p;G8gRW~d57B!!O4LN`#V;BiL`=Gxg6DBA!{-Od351hV_fA5 zWAzHGBnMt!6>#fWm6^^r!DeTC*R08RoxXFDTZ-=HVI|o6kd3#C&1HeF0$6+W+TI{o zq(*0-MHaG|UY%0n@F+P@0FON!&ipspW<$QLl8!QmG`aJOdqq4E=TPR)_b6lzX>x-E zcX6Kw@4t%+(JW|2)PN@^__H;@V8?=&FwGf3V3|=|8mtWzH7aV799^+D+tSg*wov4; z<$*;`v)H2Ov_fIS?OMVI3nJl46Sq1}C~icmxWQa!QU%jg9ft2f8rRvk@p-ogjY4w1 z%*jMzatVkQDHv|8G9b!yV~!63eM^8^5{6i-4!BhC=Jzisla9Rrt@1!8)}yMX`0L@) zlov!WuTYP0GR0S$x;#N`;!Gl&SK>DkwfG-h9OwFtkjm;3K6>wUA3IUND@nQSfQ6N%8wgzUN+Kd+w9)Indrqe?HTQeLUx#TjhFK3l5vn$6m} z$#?WCZx+|hhj}BAuWo*2s&2`*^6foz>)msiziCAuer2+aT$vzUZ=2Zcj?1e#lJ9!b zOG_z}`%c)WOkObZV@uld`c&>-k|FtSJ^FjCP4=yC>UI0dn?LB%ycp!GTS|%1WNUIX zNxfo!;$BG)qbhpw+?3MSKx1Gv0d(SqvMIirxNb_BY>?Dz^e1j8dY)3b9w}wArCr2( za^wj=_Mdfl*DAS0MY~mMSTV&7*jvuXQ|VC2JJ2NmAu2!xZ&97Fiw3AQ_pp-3oPbNk z%OKxz%dboxh`a!;c$@pgdhp{_ruggOQo*}pmFp2srud3@&$B5Nyrh)LJrCEi$iGN@R6cUqlnOpl%G8=CUqC-`&!cBPbgbYbrA!`z z1K}%RMe>bbsY5|1nd}?C%w4aQ$WwXza$Md5V~Vd_ztXq zo_e+X#L??|c-~O49LEo$Jempos|>EA)8X+3N58fjwyAp`Zzpbfg4?TbJH&NnvvIV zi$Kdkmnrco)n2eY3jPU@y)pzV3$J)dLqO~{%(EKAE4PKfEI(6fOyZsE`FO?(9Z_V18r8ab~cT9uK=w8U9C2>wTr(D+O7uiEWj=+eLCuI z1o`vxsB4d}Jfzyiuj3IixuAOlK{=r6pnOmxkX^`=nu1ONwE(pSwFmLWiCyd=frI)i zpPsVSaj>?_Qtq zj$LMh=dGa?Al?`9FaG_cRt^tyz0t}6w><0rqwPK5qpH&X|9j_VCX-4+5&}pWNa!Ra z^u;JWDxx4DqDIG*2}IM#BoI)Ex)$t!4Y9<6YgxOjVs}^FRo8-Lb=Tfe@T*vM6|ww3 zpL0KVazXj6|KIoZyKv@xp68tNoPN$NlRFu>*KHn(U}V|F#iQ_luRp1+pWH^2=}j%M zQ3o|v*SFQgr1hlgNfpg4O^aJ98zQxJ^|5$lX#2$R!zvaxwnbW-n(E^byaqQCYp9CV z)Wm8kCPqe=luj&KIu<`setc6)1p(;V-1SzC;vg@gwL+2z>}^K`hp&$g-P^ zVHUKlAacX7dfc)@b};00FALgEVqiNHL|%;=DX3jkfb6kzjJjNuL$W2;pKp*gxdlow+FJ zG-;7KaA;GU>+H$lf-Q$M`~&eJGLfZrP=>04NHp?D<%y zViuun_ae;kS?%^KMfB%t!uLq;4^NaTnBwFV2YaFfp<*;lnv;#r8Hmy}6r*_(jpOvn zMW3;Y8fGyG119I8h0(mBLIgQ0&~^pE6ud#OAT&P73HEW$37|Fda!2JNQlC(7&+k@h zXWAZ3^{=J2Nwr$3LQXfkEab%5(@LE)5G`Q(`4_3*L_ep6oaJ_;35&T=s~Cz{ z;A^XIGu-Y>w8c+u!j(41(r=52h^7C{q&w#PonFdDIvhjK8NtRIkQc;j4dE%pXNq$u zN{Ye#n6)S`C(lX2#4&+~xV1op?q$xTVy8UfOu7~MJNI_9=3(aKnI^j#qZ>#*@FQf6ehqc2pN7)clZ)Pn`L|{p~+@uJ0ro$F?lBr&b3*%-QI3Mg5km*1Vg9A*W_Z8-@SIB0q61}%u07`yw z+;#@p!G5+K%86u0a?18C3l&o+8i1-e&hyqR6to}8X?7y$_6a#pv#>pK8Q|5xabB>B zLjz19VHVY*O&(C0M5cy4atDMWNSEq7h#1MC5m>jl0>6qiCe`@^meVxn^;O)~5`MEX z-(k0!HLWa|GS=xnYgXBsVCs0TMAc<^J!k;?NXpT{w7zW9RI?NB-w*y#Tyeo8$x%g~ z##tGOjD^5eG{ae5>|~X3A)l11=w?Mn_|cHv^Nz_3`5jkdF5<4v#6pRnO70QtZQF}r z4jUmBdQ+)|keuN(JRlDtY0kW2b7u0970E*?v|;FAEXO!4F}q|jLb*NmU|epOD~f|@ zo=?wiy-w#8H1OuAog zi+hjB)?(Z0#OYTf>QpR@O{nJxG|a*XPCd}D-Nu0{ip?nq&dsnZ=H#&{@dEE)j+vuw zgK|&z+LK$m^B9L1b(*mInx=JkLL{H+w%tUdO-#udu6Eq++5_C#_|k5(5jL*XjC)Z5 zA)G@drsH)A+_KwrM5^l*@WP$}H(++Bo2leDqa&O`>CU07z-Y7mat>o~B$k!K&FX{s|2i0wRJmti_PGmFb6J9l)Lk@C9bKds-g=YYS#9q=o# zaN+zh4dW6EUIaE8aMi$5}~^;jZ|wRw|%+T{dH9tmY$5E!6DZope#59qcW=) zUM@ITW+oqivtw_~DZr{=)~w{vpg`)^mYD01Ud3kdsWH8g7Qy-(%)sfjSr&gK zjky@=N`qb~POMJ*`BtY$#GKowIa^PTICt4ttFoN4PR7MmnscYa8kZK&!Z#9ZI~tvT z$n2@JXIRl_Z4It$8=~z^&9O!++SC}0wb!*qD_a)FaUED$6J1(5u6=a0rqYTouWoH> zsKT{mWoyiewv3%<#apVU&1SNA-Qvc|`e;>Kt<}~@AyyNqYizZm^;Na;x|N7tTVDx_ z(I~WIMn@46YiVh0vZ4)Do;_qnv86uNs63`msyI9zYl&A>*H<=Fwv?1s)Hb!8Fs5Sq zA@dKKA06kiV#fTr6?0pfj*nHh#w!k(KHXgHHnky(+UBM>v#M=G&ecs#C)A-Ji|d=J zP}I7H=C+ntw7Ip#icYIrYziA~ZHO+fsa%1|#p1Yxw%QVbo2yVhc_;cn2+6?tTJBRTGtRWjTw!` z%MY486K!7;x0(-XEak^&Waw(W&O<%x+R=HnweeW1h4*5#p`x*dSj*yAWAzHFc@A0w z1sOlq6di?)$EvNRe43ao{`wt3muqIh#r zP3d@Q*c(N-rL^CY%9a`^DqE_T?1$SU%O=E%8b;JMM~W8LEU#>-#hXit=8TCH)iyR2 z#amnIs*$R`t}T1e z8%$O#{X>Iwnh$8JeNbmh}>0l3^m2aOU8Kjp?c7)l1Mp zO;vHLin{rjSfyRw(Oq72S9N_;9D^Vluc@o4YpmlSb*KCy-3`J_sBCDcG*cHo&gH3` z%U#0~9cx9a&`Br*ZVA=b#W?^tFQU=IXJhn&T0P>+>M(hiSDSi!HQ~Hh{l-$ z%PZF&ugYEz|Cd|Nqx=n4jJXhvyLK=+TboXZ)>oRLSLL4{rX7)0ZKK(%wCT77H8(KT zrMtBTVw>Bd>__ZM-jKiyW~(-u8n``T)@v(@)XlN#y4t!}joWiE460h}TV_AQ7{!g) z>UNBUc#OTsMP4hV7aevHhBn0=R?}LI4VCpMJZv*N3p>`N$WShm3(SpkY;lpPxOqNP zH_s#3+p1&ncvDL}GO=j4`{={|Z&y{`#pTxvf5w3;=94nZ)WHV{(=rQBPdOue zX7X8~)xooq&T-BSTwqVlY<6k_shNe-(yGj-WlbG}M3uaeZ`s4(4NjO@bchwoNIoPb zkQ(ZqlxyeN`A$!}7rqO)4_=zQe&^+4~R2{E}do z25(^H&rX_JvfaD$hW#G%p|Eu~4e!xg{1pk7B#`0$HX)fOxfhA=-3%fTX{7Y*D#n{6 z9w^Qc`Ba+WRpMf?OV2ZGLe5N!*utEPm3Hv)OQn$#4_<<@hGuQY!^3)kBje# zJH($wKA2=aeZ`Stt=J}>AzmWhApS{wQv8Sbk@#;hhyl-h^29+Rf4PkMnIc~eML8z6 ziD!tHiv0N$#@j4DE!JZxpnipTmdM|3p#Dbj3GpTIeeo-?FXkrW7m53chlt0B4dTh- z`QlaLZQ{e?^Wr<=4w1hX!Th?51>#t7rnpwTR(w{j=y`?Fyhw86?WnQ*s}1fb=6Jmx$w}pCWmNc#!l9Brg(= zk$#EfdU2`rCrLgp9H%xMoI9mGsBu^E~Nwn!4g&!sT zv0}CK%_PQYt9Y{Xt4WmSJaMh`SCg=NqvU%OexLY|^v{rp_p;=76#jwuiS+*=5$|Wo z={WUZJ$sYT7f3D<_a{-_Y2v}sA3>tLM~lZvUoW{?Tt>ofhr-X5{zCC$>8~RZ?~ju2 zQ}~18W70oQBHn9~KT!Bq@iXavB2n%n{P+gr=aMLIPjP@aNGujdixWtsJAj0pL&U?x zN)q;B;_=cqip!-xQ9M)n^TajcH45J--YorX;=R&8AU-Mm-^CZi4;B82_@(%7@p}^W z_({yfDJJDy67?)3QJzJx7XV z;xw^bJc2|$j}~jhCE`-COoSHypc zpDO%+ME>L!?egchNGI22vY1XH|12>g4i<-t`;tgMSv*jjEgmi&DIQD0Zk5;~wu>i; z=aaCzR=iaD4dV6E-zeTK{bunY@i~RRD84HF>*5E}Zxz3i{yXspF#{LSEKj!BTkIze z5l4t6B{g5QVzanHJXt)Agxxd6OT{ZmtarDOuy>buuk?>feq4N> zgq>Fu{*m;bil0mWt>j%|sE3;_UCa^(kjQtCI9&Q-af0;wisjPJ7UznU3Xh46VvBg9 z*dd-yq8_Wo_2Sjyb>clF%6FgmnD~VFocN;nDha! z{D4IKt>S0W?+~q?Zn}_|D(*ufU4OAq`k`W}^y9=S(wB>~#G@4+6>FqlA}*D_O*}>V zGsSbnYZSgwyiL4Iyq84%9}u4rw~%PJ_ej*|BXOJbUrYX04B*BZ?Sx6B>qR16UvZ%H zBP5R!`3r0Tva_f7F#@k_Ng#A2A}9Dtw$cN&5Z81EfD#Tqu2oc$~OY z;cend=~szoNq??*sq|NpsON3c-z7dE@}~t^&%cR(7q^f|_b!QgeJuG~h3^uR_HomP z#cVN8>`lVXa1wS(#IfQ`68Rq_&J!1kQL$QFLc&hHc#?RUc&2z63AdCpt>VKZ(*0R{Mtoj;O?*RqmxSF9 z#c#y##h=7(_&pKY%@O;E5pkGUB#tIwmp_R}mW#7Vw97Fh>{W`j(l<$ti~LbUraxWb zmq>rPc%AqM@ec7GaWjeho+4rAdGRIj0}|!fD)Q$IDSspWDBAs8eTak|{_-K&Ta1W> z;y4m^ekV>7%f&h3d~p#8dlh26*di_y&mv*>T=8OYy?Cv7gLn%GySIyvh);-5iT@yB z_g~`s;>Y3_;@9GLB<%hmru2u5`#3$tL1MXhq}VE+C0-}~N!%i)MqGP`iD!v;%wqDz z?R!JqPBX-1wIQ}SLkwHPLE%^PI+r)dt2gJw4zlmGKSH$gLBr+B@1tH>9v(awG1gW?n7Q{oHa%i`-I|FDwjw~E`v zuf+d|KZ_2Z{~`WD(L6_le7t1-;UvRXiu}`c$`^?1ME*H8_534A@^|*7e5xi68|HH5SQ`!N0ej_k#EJKJXjnqju$71<>D-Hp?H*dyx1tN6jzBCi0j0w z#p}e|MZUC*<>4z0$-juti!X_9i|>nHiT@D;e2xh}UZrW+UF;za7Ke)y#C^s2;t^uC zxLE8Ee=lArUL;;Gn&+!1$IFsm6Ss=n#c#!3VltnfB3+u8FYY4_5l4s<#C^qs#6!d* z#bd-eu|YJ?b&=l{lK&{)AwDQRD*j!3L3~4eN8B!cA?^}?7Ss5=7Ws7(_YwPxBg9eS zzT#vtCf127MDzR@cF&e*5FER`GN3D{;@~;31rQvwc&=Y%x#lCk_-x zi2NBerkg01i8Dp>JRITkBrg=r^Kj@ZB_A&~if!Tw(L5JN{L>|0Bwi+(=imsxRq{RJ zed1%{6XJ8?i{k6z+u~MnyZDv(AMt0=;d5f-n<{3C`J#DFj_^XsL&Z{YoH$)PKs;2O zCmtytBi4vZ#HC`JXr7-VU-SGNJWKj>#f!!D;dX ziM3*bxKvyzt`g4@&lN8g*NfMRH;A{2cZ%jYJj(T;AJ|n&;{zH6Qd|%uyej$D* z{vbMf-kdCEiRO7c%HLPAc^(gWsN|927|}eBNBI7dr-=uPbHs(>QDU{YSoEIHw@5b6 z=V7-)@@mn0PJfZ)%fze2>%>2bcZi$Chs4LlzlmGKSH!o(_rz`D=i;~GE-}F8*C=mD z>?Y=jd}#;6`-wxu5#m^JqBvFbp6eeb`Eap9JWi|=&GUWa(<-@L>=1u1o+qvmFBh*8 z{~+EX-X;D?d`Nsud`f&)d`0}H_>O442Y~Wzll-~(t+-1J@cB2}Q_K{*i@n6Y;xN&C zKLF{*N&cN!EiM+#^MAx^k!+s-L++65eGlLq$!o<+#4E*X#GA$2#7*L6@lo+{@fq=X z@gL&9MDx7>l*fE80Q_G1pTv-!ho_2#;!tsvXucPK^phm-FCHKsEG`fiiA`c$Tq&*+ z&G!Oe*L*JkyjuF}#GA$2MDKe5nD_w$7S9(i5ib|7 z6>kvDb9tmU&*j1UrGHp_QhZu`QT&JarueS7RopIqBYr3TEIN8lohfz~dx?F;!J_xv zzEtu!af&!Y-1E8p5z-$m)`&~QCNVCq6jzC7iRX&z#7o6JpXc8!{cYkVakKbm@k#Mn zaf|qd_>TCo=soBETJpEzPhvpNzca*av6t9aEEK)x{i7t05hscJiwB4Yi}S>V;xS^S zc&>P%c$s*Gc)fU|c!y}7`(yk)DEU$Gui`V}OX92ITjG1-Ht}=uKjQadfX~H|kN5q6 zOv&BFUSeNyjyPX5&;60UTJrH?qqtl=QCuyaCtf68CYtX7z@GUY0C=bLo5TmjN5#L3 zFNpsX-xNO-KM{9`--x@!pT%T77f%zri#@~v;vmucUcmm6XNm`jbHxQ>Oso@EimSv6 z#f!v^;!WcHqWK;G+UE_)?}#6Z+r%G5o6orsKP;w;eZ>J{nK(t9D=rXg#3f>@*e>nEm*Bg9eScyW?ARW#4< zk={J72al4zQjCe-^ZI7Vr;2BY=ZR~?YsDMHTS?qYd{FYE;ug_7r$_#8DBd>d&2xI_ zf0pd%xpc1BQyeB1iDOCRH(l}p;v%s^tR@k!Me;K7Eb(0NTJZ+)Uhx6(1@UF^9q|M4 z3-N0)gU^>yuWYfWXr8Y_Um$siSSC&p4-gL)=ZOo&#o`H~_dNYH$rp*2iMNY)i;s(c z6V3B;w9{LX-xI$Q|0AaBxp0;^KpZ5F7bl5x#RXzatP@v?tHcY%i^PrMP2z*%qv96v z6>*#Rx%ji_@cA>^Jy$f(vmqBt9xYB64-glL6=F5X@g#YfXr6n+-no*m6>kvl6(11) zF1{dsBz`J>Fa9KUi@4>_5eJLI#eK!e;yiJoxL7Y4PahLeB zm^D!2MI0^`i<8Ca;sSAz*eJG$zZcIE*Naz**OM4mcT2ukd|3KtC2tX5lm27L+r(Ys z&tj;+wVOv`eD)HDi^bw(ak{ubTqH(Gl&?{8i}-u-Eb#&o@vf45t$4S1ulTIEMSM^E zNc>LxK@1nV%aE_?h^l zXb*PF-CgVFiBE`6iO-7v6yFrz6+aYrh~J3ci9d*8+ikyeF-y!9z3+_`O5XGPV(X*~P;KykJ>S6m=268Tbj#y?K15u3$Uv0Xe#JViWRTrHj_t{1NquMszjH;K23 zo5hF3$HXVZr^IK)e~NF4?}{IaJH&6q@5CR(a6s)ZW{LdWBeq9Rv5)9|FK(pd5^=0J zQQY%;a(wAN?adVzi2ThR>MO)0V!hZbwu+~Sr;Dq_^ThSymEtwxM)6K@lek%YNPJ3s zR@@@KBEBnrD1IV-Chicw5%Dq;Q@5sy&1T+R*IKn&#pVS{#Z~dRRZK;(|Ai-3F?<1 zo^8rMpl=_E(B~dr*kp+KYK=9;Ra--`pijg-6Wn$-Z_%N>Fx(tCFAcob12`{O?iJP- zR_XIIUg>cB=*Cd`+{3eR3`Bpv$DM;8ix}kQ%ly22QJmfKb>>@E1Um2V?A1fzw`XDF z$bydbNQLw4{T_ZV4ZKzX><#^udUPPnZ!Zh>u7MHSONaC9T>`(~-oXpqXS-0F!wXvr z$#3t@O>Vo=9;Q{o-nH;EO$i*2x>|hq7Uv7z!7#d8MK9jh4fxRrFOtF-?|%8cp!!Da zL7o7z9z6a8=P%!8l+SBFJYq|f@2~KqxtalUY=S-im}Z_lNN)~M{si$NP~!Hxc{>vG zrG4hlJ9#Z99kkGV*nh-rFP7mU5+;;C#>4m(1cwoOE5-p1l{@$#afte6@9v6&P8`# zJ}tN=_)=1NxIDP7SNXtlr`#@G)bHuu8EaD3+T~e2)7MzTtQ{wvc3A)5Rd0RQe5ZBM zbD!D+)|KB>ZWmgS5#_l%oIu`|4Lhy5>vvjN_N2UBww1A^_fETF{Z2c}9!@#9W&O@T zR_~pGk=eTf)?cy%Und9BzOzSI8|=%IzO*x2W+rX7Q-8N5y6x()wPWsSfen57&e^s) zC24y~dSH8I(2C^lOd5H~&ZMl|oz6*@>~xM>clX(MPurF}ZR)nr)Pcw$7q%}!9=SVh zgxkLePa3;%<_%va1z&&hsqL%VQ@5{9Z7p}Ur-VDV=9Kr@@Z5J(-W@o@8PR9ml&|hT zHRXyc!r2#DJAOKKY56(f;QI8-ue2_*{<8hFmM8n#+fNIG%b)ITukF=8ZSBAM1@_I{ z;e@(fG@@7dqIkd1MSZStE^_*3UmUn3`O?&NnQN0S3S6CZRgayaXM5~S{;bDNyykvj z|L-r@HD_D;tp4Ahw{y-m`#@`5R(Wo@^={vC)UX7#Yrf*{gSVxoPT!V1efTbC#zEV{ z;i0=6tH;iy^Q_LZ@1D9XJaxb>XL*mE&S(9`=L~QP@uv+y$acO?cB;S5pZby+H&tKvuXHv9u9)^+(mu|*@P?!@8>R&=>iFj1 zJNj(Mz9PFkxS`jKK5Jj=nQ}!AddAw(_tfkSSyy1>z8m<`4hJ`^nbBv%oNX7S_Lz~r z!P((BbGDt6;(Yn@zSc$0Y(HmZ%9lxYPXEC6b5d>e-E-fC@3gN-TA#e#N&j76s~{Vr zaLvx7DcL)nht}+L=B~SYBicD_+Kg?%83T7EjmgF+T(dKPa2w(FFT#^b&zpJ8mr2&^ zFItx;Z%+x_d{_R?lq}30D{y7jE_+Po{*lQVwoe*EMg(xGja zqc(TG7`!57!&{%GZ_Sx;WqEYlWtcskr=)+G6u2F^q;Fpxv7Xf#-2Q9+Xp%6U)t&H(Gco!!;3k0KK#j! z3sW{&!w=okXG6;6!SxG!qCUswmiK%2lATrrEqP-1UCCcP@}<=+V@uvn`&pE)IWVFR zMoe%E%G{i{GmxIY%Npp8jwGxqo2G@!)3(^<)`+)W>|M^ahT5rpsQ=ouSk8>#MHv|1 zk8bI2TJ5dxO5T0zyWGb*zNx%pdU;j(j`9n)20P#SxX;yxZe`i-dhwR6eXeEv@yjbxc0se@ZGc11`l#U&0z{Rv{8G0WH?7+P!RcK@;3lw;r>K5Zq{tH5rV|M;}=)y^%KRA3BUdkCL zR_G?Ya~yvDQA6nF9O|vqGJMR0FOBgXD?J>#KBWP2#xQ(@Zb;@CN1(vU7=#uL-4e`! zHc)^8_9mh;6Fe-|GH3 za$94Ej|m?~>!!Vr?M^@Y^xrI5G~_lxQpWo%No7i{2@PkMf>rfnV>t!50T4{0;nZdL zpi>UPB=&xeoz;g$3AcrBftaxaAK_)$^fRNI8MfTZ2$neNvN$i7g#Q#SKqa%I%~tr{ z?n;myZLz}lc_Se^y4(tHmK4r7ip9J?g>y7eke)Gu?fHPj%KDe1_TNgWL!$|{qz-x6ew7fv5GbN zFq1PlP*9QaDKq*=gRREOwb|E9nrA*ZTJp}~2leQeLlD%BK|M}I%ArZ&;{su}PX2P* ztqQ16R{j%gjKzVp8%!0F@?T>3;y|t|hx7Mgg%=0d2J(-h;-)})Kjh#Pycx`.nu z$T|*9;}pCb%uk`sI|8Z0O^na5sU&eKxShnmfbw;c5!Fc-qfEi1rw}36{vPel0qToN zmDitNn@CK@VcQi6>3c$9R)3B{Gnuh`a9+;$Wb7mSyV7ufyEp%Cux9~`rH2dba3^Bq zo3&(+olOCAJpVz~X0WXhl9bOsO$-mQHA2G3krfXn(R|ONVK*~8*$!``shuz!o?>^W zKvTR-3{UmsP<}qcr`g>XqI8(@Rw_N;BeII!YfJc)K=S_Rn*7HZ^|U}w?q)PKjq>jU z-Q9jfsaT=Y16hn5C6G^k)S|o@4CI%^v}V zR|k5VKL9IOl)pdYpB?DoPPirca~S^|Pj1e~b9yU$t|zzWw==)<0$GP5f3E2H6B*(B zK-RHFvD(g0rG*RJ5;z6d*!kx(#)Ym4r(mOOxUAfVd^Q~Sx!j}hdz&;e%<^|}P@Ku4HHygR#O696f!ISl*($s6(6v7`&>WzEfC(Vke&~pKbRYz>G&ZeGfFElay47aGa0bfztIGhL51lbH|j^0wKQG zwEzBy*AdA?lUflt%Z}WO1h5;2D&_n@K`mn0cJdWSioK_MC*pLw7P{mD#7jNL&iNxW z$>+jM>Vt#fn4P`mpK>o3= zyp9rtfZ((#;JK7t-i>*1 zFS?()Tc|t0=y+zB4_CmO_V$6@n3ngSc@Mj=x!tl4GSLo430_0V3Y%A0_AH|cU3v_Eyf&&Ice;R?QItq(J0s>Us@`EUhzS2}cgEN2M4#J9~AB%wL%!}g(W z6LiHf*p8G7x>I#C#H)-72^aLB>L-YNEk|Md z7^r$v#cvJGfGfnWeb@{7QMCyozYJ7}A7QW;45W(hqUaAdm;-JV+#{wd*ku38=a`<4 zz{B7Q__k>2_@athIBUond~8FCp;t1+jdm|4`2a!h!3{G>q_l=?K~N8Lpd0rlH|}?c z_n$;uDXk%QA}(KR>c+j1jHSeh%cozqU*1)K~%3r~u9T4O(&vEDN{0uhG68G}>c*`ERp*28l=+(?W@tC$8YYZOby2ZQb> z9}U{2b{78xs)WTeR@NiYrEtc|ZSedNu9T@5-xTddXkLKBUk}nE^&xYE+n!`+@eiK5 ztbL4VAHo@H{4UW>xRE7DYAo$D5Z}CklO;ZsbZ=+d)9tKPyICqhG=9m*SegmXbhwcR zBEGS76r@FPswE#^y1&-F1wMO@owa2*YfBNe0nS*v37$W|l`<9M8;cJ^^B|lozHcn@ zlb4Zpt(`Rxi;n5mmk^8JKQisN6`qeMuor%S=XZKK5|JFC^Rm|cLi z56)N|3{N2iTHF_&-@%nKHPgwW=?Tgq>o^qIZnv`@@vO~7{6pc4wHQ3r6liTFJne8J znZ|F4_xh8}hGm~_XYnParluPZcRdqx0N(}AZ4_wf6L>y`8_6}tZ)vn+W&&&YFT2}3 zSn3)b{L)e?oUt$wp7C%aEyOiF!0#Yc!D)2NgC$G>TKd@TcBNOQ6^OAM&Xnl_c+R81 zGCcs#X1I||<1f=TQ>GGHstsg(?pgX6aX(~Y)@~O(J1Nl8kU>~g;YKozDcgKVhrwCa z7|wyzB$n+!T5Jtun6_Gi&{{ZS?PPdPq(Eyo!*e6tNXA#Wtg$O_P7-)Bxxf85j5_0* znoB8`Qi3p=!ej~f4c8}=51}xu8YTjNOHQYN%(Lx5nK@}r=02H+hqCQ?b{38Hu$;_E zY5S)AF6|)X?i5;SY5OA%dRSiU{=sh0G8o&WlUbIIPE)d=n=G7fr=_`8Y(z`R*v)9F zZ6B0FecAx)pd9`&dwR}p@iYAKCt{PzWQG{!gApIMAaZOc({Dc;@xxxB8Na)U5$q~K zPM$Rc#mvpKhorlC=LLxW<7&D=kYO^K2!egC0|*9SXl#CTBa0mb&@bgxr}q-WdR?J1$lrWvaP zgT9sxgzn>oQ-N|aT_{~4bcq&{ZjfJx6M!@fi0(GaIwZ|LJVeh>f1#CZm|uqtr>|X_ zGtb^UEqHinQQDDdN0?R|5wuEklwc&SVJ3|2QWevWwK9>GIU{w@O= zFaqm86b>f5`WyXj89Gh?ndM%1taD1`f z{KEtFM~%&a-;KiKdvgQ=4zB*8#oce)W)mhQIZhD2q>R*xWv=TGrkK()3I8*#!n_cp zr8Ssy4>z9c9|*8h(8C)$=$Q>?TZ@Paqi?r6>8W>xKqo!zuHbau3J)Dx;$$N{>k6wn z>5Mu8N?1Yxzp1E=MK^FeL5+0DaN^qHHjEw`*c!R2Zydbsgs_^ zT;b$SdbYU2s!n?NRXsBT=;?{JKqnFX;7oFQis4eNwGVZKI7bgp-Xh&kb4CNsojMBeX(+ z1(#UmMmnkUGIcz6LBww7BftbqlNnJUjhgQ7hT zaOuICLVRMp6$H;9F@Om=$7(sblb%$JQ3$I#>58W=G$2Tu4ym@H`1t;dMCQ`HANe>+wgm}!=2Yj>iFwW9+1wGr zB&5)oP>k-=NrBVVjWMQ=Z#p(7`31)}H=6^#xry<_NxBjaCr|{Zq+=mDCnOyjf^g?1 zdZcS^qDMG4IUOAfJ<>J(j`il8vD7u|njPP)LqWP`9STCB#2xSiXP!ykH3b)SO~LjK z-xO?LWu{=WNzs0?IU~3R0`{pXq&w}}I?S|t%*1M2)k)9uu5fZEXB!N*nNXzOYpvpn(DjkZ-mxSRS({!P7tIscc*?d5?X zfC9S5ZymHX^vURLV?d)B%IuI}&=YJglR8aEh;k!$2cAVFOl4Vy}go zGxak!1~C*Vq2)Q!XgEgZU~PfJibtI1dWm&#+4x@Ml)@>4mzvLhacf{FZ)jil>p@g= zJAo~N!#LY=leTmjpqkFNr?4O#;2f|}6T@9EvA^pjmbu<@0G__1F5YM~6^CkzQO|oD z;3*f?9BpoIlyrI{4k>v8%Mk{zH_#Xx&Ez{!s9!xI&<=)UYXT+4dlcwh310SKLEY5hML?mrMNykLnC918 zh!ce^M7AIiHc!Hxvdi6zGj6zy)3xy)!P>DxRPRwS_d0Ct3@>w29?T-p=Ct92LJr(z z@z2w_0hG1*!nAv^4`;yztyXJH?@oFb!eLh>xEPsJ7VfFXyLzG?E{NVPEl%vK0jso= zQ}a?2w8|PisFU7X;cz0&p8(}nhbvE>9CmWg;vQvWCD_53 zYG^id1gro@8&vKw5OC*RsX2>rPdAPwIAJ)gIajzS&`-JptZPA_zH9F(NlXWnT$ve+qfF3Adj|1h=@b*>ZW_K+ zRP)3Pw!H#Eg6I~|O!d7KaqgWc7at5@01+$~yu>uPY-_i2G^2THZ{03=zzeT7{TH)26-S{ zcWtg}C+sT&JE@-q*F#}E)4kX}u<*da{Y*G3z~bSwtgDoVAscgG1hJF>E|h!g@_Abj zmSs%LCs-PcK!OWaHtqoUy1WI=!B?%bIlPuy?zR+zsCHW_G4OCx!;~f25bXv9Z*zEh zk_+gwa6NISz^z^C&p-EWJ=yh7DIAcvt$-M-d@(w@Vt98O5M!k;#)(}qykVY&Awv60 zEw&@AbMSNIXJLF($50NV0iD!tf=f@Np_ZD>M!VElViOJMd;*%Mj27Qafd$T$0iD#m z3D+GrF1pI)hH;8<4F6gf^&BPXC{tH?s96U0%Q}ok)6RqIiQ5ic`7HIdAwyf;7``@K z>T5%W^4!Xz`UJ6~mG{)ZT5F0fUbazsG?i z6>k&w{4TpjOj}Y{Iocf8&vxf{;)QEZt1aM*VRyywE^84(bBgWU7VL`QjhMaL;K*U` zBF0|I!O+3zvAx^q>bYj0jb>k6*mJ!0>}fUo>eB413qyI9j~KqXH2dn()pL7`(baQ% zD+hb7#Prz`O8G~KRxbYt(X{f95X~ds2vOg9x3CgD;%z19 zSueM)5u!vKAsiIGuJ*=AqN_PV_C9F5B6@=+k*sUTXb5x2oDP>5jlLn{wGdSt5aG~PEyP9W3Akjd%^m%|G33SZjUlfH-rD0Uf^Q6Yo#Y!sUJ-m_ z$TRPbAbj$!ta-R%C$*qCAA{qS3&7?MSj$c(d6ok;alG+X5NtDCFLj;JEb`3SJdxpz z-ax>Z-D1pE5bQ9RT}8TPE4s`cMzik8(V{N1yaM$O-Z_TjbtD%MWY6An4IS2HXi=A; zg`S~s;u(c!3@3c97mMl|SmVG%+1g1y4T1k8a=7bn=Q%!4=5gUh@Z=p=EZzf;U$c)U z@MYGOM_Yh-uss4;l*z#`27jO!^hnQI&1L_pa9~2&xIi=|-8zfKAg36>re-0uv2FFJtg>o1G;Xh`jRD9N6YpM_#4UczAxyz z;J559W!E6~DHFx^eW|ePrcnrAn)7Z1B$E4;i6Vt;?utLa;nt*AYroQ$+>5!#RhLpF znR_R?SoSQLIf1F@s^<}OXg}>yQwqJ4PL8au_Up3t%d0uhc(Uzn&N#E*%hkcJ#ogOA zpcmJ&y&c}yO(|x}Z`pkXNii|0-22ssXVo9qJJn>Jy>kd&mw9oM&4Xs{=)Mvp+un)5 zZ>erq+`V0DdYM@^Guk7w6r&ivdkIoZOe%j%b!pL!>z(Jay8g>yuLOPI!KlE2BszE- z)H`m4hwdr3XFa9-ls|#{%%}HOlv^>ZxgK~2Z%y!TM7$-z({o_c{RfUyA#t!!aOrRy zw%*~LSge6=9o)rm+_SvH(_IH0-5=n%Q+WsDdV3thy@PS+?u6qe<{cd7bce#tgYyph z=^Ei$e0uL3l79irUhoe3=?25GXS{>E866)@a4X|eMQ&%_u?2o^lpn)w^XVDx@26hr zyeoSEN*=IxWoGc!A6pa7E-oI0|MQ#LTB>8C%IoS|V=Z-!i_6;@t6S@u8u3mb6OPa6 zO)are2Q^mLx7Ea~>PZ#NElrE@x}QjGU41Mb8QMN^{IH6}jct+Erl$IM1aAz9#2Tt% zH8ruCiiwfYC8ZOKmX0lIs64)@r2>IPjZKZQqF7~BT}7R1v!bE0dI{e#^#8(kd`0|! zX}7+vs$y|<^&VxPSUkG8)T_b&GKXJn6}7+D?w0>eEYV|k-Jc^PPFX4=c*2HQn z+v;1Rtt*;iap*AmqVd)m{N+6a3=zEg=>*r8hypEQAR+Xa+$}M@)ya+0P}#Z!KHTqM zzLNOeks!VSX6AwO82;+a$ zC#?*=Hu^HDYl$F@GawSo4CVA6&>zA8cxh;WlWFJW^$yvQNH8T*772E9?&x5Wr>#Z7 zl%YuJWJmCQ7H4>|lVS(cLUwU58DAcR=YRtEO5t->+W#jV!s>#-9zp!YY$y^cMz-B> zsf3g%A?M)^n}z(Fh1{L{JBpdp6INMX9s}>~V7!9-T$61XVytL|F()-*D&8Y05bW<< zoQZ1W<|f&}?2z-$QoJ^!c-WX=-(iD-nfr`E49B@Lvp6&=WFrRBZd+>m5})Z${6D{z z_yT|8@0QvqeVS7lF@;%#_F_|ggfn?GZ*y^8P97VHoe>O;F~w%HI+?Q~k+RdAZ>(9U zYp+GMP@$_(no~Pwu@i%-A$wF26r*zJg{L%_9&+043;Xv+bK@x(`n?-0(U-@M+=S1F zIlJq8V$k?Q-GU{IQXK5>B8zZVMu@R&M|wieWf{dmd>K*pO(vsE2wTtOjuvde$qwF= zl8Bb)rFYKFKwl*E>=Tnu$oag*W>+xCS(i~vhJIoAYrkQ)yl4wI*HSNe$T>5Eg)s$o zzQw>cSwy@tgq$;eLmhr-v4iQR6p0Kd`Rb$=>E@a*?lQkK{l7QS>bPklx0BQZPP*;& zfyvovE%xfRN7j3YyO+dQ(f5BtNjlw<_$ubr#Ca73@^uz-{Y97DwD;uC?VjB0l8|$2 z+zyt}T5(s~xjp|%y6Jhh`v)+JnUxw>cOl*Xxla;B|MTAR-n`empK|l|jXE=}oQK>R z&I(P*4Q6n-g(hR_<@Ouc58e`Z?O^86V7k+e*%um(MYG3n6TsCI5pvBkni4AIEY1iy zb%^d{M1mPkoCykyEt7zjQbL8a(8nk;L%Ab858^K^c2lN=24Ye7jKQ)g1G4IYq&=jG>=hZ<&n&sgp&Ti*gS|$D$`ID2$_n->*+bPW*sIj2 zx^*jyaLFHx#f@wIE33G;Id|GmX+J=DX58u&avAS73o9Ecf|c!v2l8`~N1C$&+epYs zbC+zhR5+idc}sRq$XVTrCA$Pmc7H6{Sz5BcPV<&*q+QqQF4=D4cl?Pj`L)C!`xAGz za>>qcsv>312rR}Z+H$j#xt(3WPRB;Zc1HJMBV(sQS3KfZl&Bu!xy{QK%r;B4X_g1E zSEV{nVjoKm4ahS!zYp6PwuRHM!=;4mS=?;%a(W`DYfr-x;H;=M4Yu2+_D-tTLfF(U zZu^x@ZELF6La0$^n}1V#(VzIbUrYQif8yKPxUD;tb{YG%pw+j{7jok*FGQ8hHjgup zWQ^dw=w_K{?mmwSJCCA8@|{0h7(L;x^C!*Zj;^KF@APQ9U73OzzFB5gs%&hFu>_mZ2F^yJ&9q5C>edJPc8ek zBxXQ#B|&$UnBHQ~jY4n12)ZwgsZqKWweGnHd#yN_Hl!H3%TeMq+*>S;I4@ZkV5!bu zPcFllccw!~8xr9cckO7jwgzXn4bk?d=2)W@ZEB3h+Ur`Ql`V_oR&;rFYg0oNP9ZB> zV^*|f>_jWxQax=pBgX3%H&)h1tJ-Rnj^7TS`hRYMWY47*jF* zkogDAkB)O$F=PJRin%RK$H%H$;}r)?pKeZgo7#{?ZF5tcS=Hh~CR*LpbV3~pHLY&3 zDP^>^A-cS#as_G?i{q5pYV(Q)PGmC1Sb{4fYia2?BUd-Ip?)?y zJri9}6StZV!r!;!V>C+TYQ0`V73f(Y6g>I~|Dy#7q?D#0<$7p_xacf|DrKPoLd3D_D`RKCB`nH&Lz@djnrk75Lme@((Zr%E)Vz901n-@#i{m;nGJ5=kk_lsvi4-+dH@EFq z-PD4&*A_L5h1|NNt)U96g}%0V+1R3Zb5Tv{cxu?rMYu%VZ%JiK4HT6v)l2rnXj(QQ zR@5+}wmDL?xMq1}OKs8UNYR`zk)qnhrXswWwyqkf>gy`wxR8aiR@bscXa;jl3msph z>z8Yri>jL%TU#otTlYgtTG8flxL`EBUDw#$)>?`#1OVBG#RdK6|y7`zurCr|9U0(E2b$wGD zBRLwcsl%0B9lF_E;#twfl?@G*W@5s}nL3p-wQIDQfnSA=Le99(tFMbAZ372?G+ZY{YxN(6& zLp0BC!Fc2+hdKstUAzW`q++W1oMuIrcxwj>;?C5m^A0F=<2S&bsc=nG8@k4d&Ym;< z;OGKWrKOHbnA`MLdpXD&Tb0@5=`ex+h_*Na+DtF@ae9sHSwnC60AI^ee(?VFpC9aD8O!u zwT5eA-HR@cwW8uNHZK~g1_h7CnF1|yeWe*rRsNA~8U$%; z8_j;AZ9+NEKVsCxt1~!`Vx$SJ0TPq3^ z&9Umb+PYYc+aEEElUi&wW;?>L!VQz^c64t%#=hYiZPsnKohs`&3>k(N!?ZGO(b!N~ zkD9nIU{^#@>!wP!LyUjan21~U{B3#cBTYUGYhAs zO&x=XmAva_*~8!sPMBGAh!x66J|qS24(pzjYvc<+Vp*!?D^!~0Rb!@(1J|KXUoXm@EG z{B@lFzzZDxBJ#uE+xrg3ye+v);owVc{=>o71^tI(<(e3*CEL3@@2Ks*$Q8Ew6^MtM zXI22;2xCbC`15mGB>9eN5-+Q<0{C<4K_ns#mwuu+S)3vAxewDFDe|kqlRCqRpM>p!{T$|TjKwSKZ+R`@XV*LSS0Qz9wHtiHi)al z3&m^1yTk>U`m|dqHi;eLh2pK^1L8B{>tYadk#_RLLE<=Zrg*p*6Whcy#7o2*#CyfR ziT@No6~7nL@IE%?-$yJGSBPhePlzvyUx@o+iDUX%;?ZK2xL8~%o+6$po+n-;UMFr6 z|17>Cen6scw~E_Il;z(Fx3G3mP7+f{lrL9uPqDA`LnV(COQkQ9JVl%-J>PUj`wPS) zrLU2^L~M}0UGhodsnVY(d5zd9UN7D)-YY&xq8@*h{EYa5^sh^PTl`%7O8k~Ydamg# ze@ILtq32HyI zyLgZEk4XND_&4calKiUphV&mx-X?x8{v_gYq-me-;s9}wI98k}9v~hp9wiHjIdCH;01@xGDFQxDot z5>rTo<&%gPkvvl2CE_^gr;~^`Tk;}>SBRC;H<74cTs%qo)gd1xmf%iiF_t2{BY@y6syEq@dOffS|zuOzb9emZ1H^YdWGL8 z-YISp?G7GDxy72hCX=R?V#i2omZZvr1hwXJipb+&iI7Fkz?|F7T zl{Dyi&wcOxzTbQA?|U0||JPc3-nDmCb)~A-Q4;0;ta!c&)XW1hQ;dq)Vy@VhM7do_ z>^EnM_!(l##p$jg4l9P3ZiZQ+xt9s`x0K#iED-q$TefeQI7;NrceL|`IOJ4unz&HB zO8kp>lgMXnnXg>DUA$Y|B5o637GD?N5kC} zZ**q5?cyuqo8sHz9&xYul~^er5q}i_DSG((5#=X|siOIv3VQ?TEkr)T%k+HrHCZ5b z7ki6?#37>jU5oVNq)!y5h||UMMLv$l@=HYXdl>o>>DP-linog9cQVrP1rE%AkNBWy zem}#$S^5@{_l`6DD=mP;wo{qc)NJF_>lOB z__X+}_>%aVXuO!9p7*8i6~7b@i$92L6GK4E6r*Cc$VaQ0uA^8W@+o%O`-&%uCy8Uk zQ^d(4U-8d;mx%MkYsBltHKMs*0QnK=kBjEI0p#bTzb5V!-xog?zZAa~4~svDzlyxD z#`c9pbKL=YUFlh3bFrnECl-pm#D1c=K7n#ZOCK*z6weZ;ix-NsMe_zxk^wOy zri%^5reaI6t(Y%%7W;_(#lhk*kuRHPeW!|3#IwcoMRR=z=}M%}7ng|FihSCZ<)w(3 zVpMD@wh-HkCy3p}-lDnwgYt$*A0>_x&k)ZP&l4{c=ZRN{SBXo-o5V74t+-zNtN4KU zl(d%N~{#W7pp`Y=aw8V+~8%HDrSfc#3o`Zv7OjW>?IBshl!_&XNc3p z^TbQUdE!FxD)9z!g}7Q=E8Z;{cM9moM(K}=&xp^7uZcUw_r;IJ&&B(aM5c`NR(Ol0%`D3M@Dozp47H5jH#LL7hMRT1GvOwiWZm z&SD?2zew)~EPsl4k$8!CmAF*ANh}j9M05QQpbkPYNvm7t!W*D(JZX&oCmU zi&--(mRUg zdLQiOdLP(N_JN|gt_S;E>GMT%oe%bFrT;}N6K@so6#ptdDsC3Hi{|Ai!zRipz3 z>UW6ui4Tg8iBF2##O>l6;%@On@e|Qp??d@tOFtxjFIJ1ci}bs|_KX!LiBrXM#S6qs z#mmJ-;??4Eah14MTrWN#J}f>iJ|(^+n(KLJ*L%`G62B0?65Z=~N2UKRdU-ty`OWn_ zFjIO%v8mWfG}rZzu8VZ{x?Yj=VsWH6R-7PC5~qviIv>iLE&Wn)k$AP}UgujOeYLn& zG}r%7j=BB^n(Kd{x&8+}t#r?d=K3G(=K3GFTXy$4;2!CFMS6?jIC*)!3rrU4i1o#W zVhgdAm?svBJ;lDFxekbOhe{tKo+2(0uNBR8KBQkQJucoUJ|I3UZV|VMZ-~3a55zs< z0r6Y$NAVZY)^#wym?~z74a6p5uGmKGBz6;v#A1%aV_?fs*G}rY|e-f|Hff-_bv5DARY$J9MJBi)I5#ku}T=4>Nj#whzB$kQv zF2r_h7PpDp#U0`<@qO`Q@pEy%_?>t}OseaYpDMN!^TaM<50RdY*q#aERB@Vkfq1c4 zBF-0=h}Vki#5=?%#b?Ar;`d?(ZaiWA^~KI&ckvW)f;dZ@BVI4wD6SXp5+4_z5_gEZ z#IMC~L|=WUJt487*i`H+b{9_(Cx|8De6d_yCvFk9iJyv}i}WDH@n|I$i-W~!;(6jy zahZ6(_>j0m+$DY|9ud=UL7Mf|6${0#BE1|ie!O_8c)7S*Tq`~$ZWZbMiuoIh?Zp$s zzTyCJw0N?3wm3taCte{g6_<%?#M{IT;zscq@i}p)_?GyYxKI3EtP+C_o&F??Sz=?c zt=LiQEf$F*#j)a4ahf<+yi8mwE)y%nxcHFxi1?iNqWF&Zf%uhJDH=~?*gkz5IsF%}$VZQ}jnL*moov*J$iE%EQ-7vd4|N70KvoNzt`#rk4Hv8~uq z>?!sYPZCFp6U8awMdBsmV(}XBW^s*pued>cT6|XAA?_0YE`A{%5q}i@aPG$bg~cqf zvDjWbL8RL_rawhILp)PFSG+)+BbJDz;u7(C@kWt8=ve-P;-lhbahteZd|iA~d{6vH z{7l>@(xDy8_cV1F79(O^F-vSF=7{aYJdxh;Sl&2sqBupIAh55zs<7vfjqVetp?SJ7(b)RQ8ni7mypVu9F2>?8IU>DG_!JyoPj zKk6mo67gE`MscNhn|QmpLEI=lEj}y0ChipJBarodCDIQd^W1 zJ?d-42gOa|Zt-1_&hnW4pja*bE;ef6#5WW3#m?d&afnEtcr0&{c(FKFoG&gE=?9PL zH;B)O&xvn|?}=ZDl_I^}F~61LFkP%C(vcnG+ljrzej@$UF@BtQj(Dy}Z*`1cAkrHh z^>yMV@iB3WxJ{&wI;Q_dr29GQX(Bz)QSU9DEzS@x6R#BMY>w$yiu5-}eXB@+a?}rs z)#C4B>y}P@dvUCIsz?uV%s*4SQd}g`j~wG46!B*j^EVaz>@{}4&?n+DywP#_%n+w- zhBzDt)d;#zUNc$c_Q zd{o>lZV|VM+r?etJK_i89`S4O8}X3%y=d9aIN`-aX1qdTis;@4(OCMwyC0&v(z*9V z43>WUeG%hipCXy5Isn;**eT8r~g)ME%DM&pUGtp4po^ zcMgjE-}vD4l$+i>U%_mh`IYd&u$fPDd^4TbQU8#Ras0GK;M)9m={g|I@%0vC{ktEZ zgaM#iHcfPOemSlgxF0vJFAVq-lU3wKoQA(`;94?%9-F6MSRUIo0>RA#(K>>O@RQrg zgt#dQGDPbD2I_6>o7|6E#zYtr>zy(U_rhg6^|C&<-isi+c_3O_`dd~u1%2GO^Pwk} zcjy}I(_v#j@TZ}g@)kpO^FXxrpuBq%46e8Uaf#(w*J6y&UzV4G;I?lSWH%2)>#Bjc zx0DI=apRUlPb{zKI%iy29+p*2dFvrFPd)-aw~xf%Zt%Be_ro}b2ShjB+o#|iO>QE^ zF&+1Rr283mYQnaL(VZ`kLQZVoV6@L2KU`X?Y2S;GF-KdUY5@~-8m1@+B+T&5Gd&5mWRui$D|vN_Py&S0^M{cbSmiHCA;=h(4}i( zewY0GE?u*;^Nrd0F38XC+7-6K&Rq)%jeSZ|>7ZdT=hakB!M4?=rd(Ri=A^~4aQfQ@ z`@*Qz@xY;xYc_szAm^^s*xaVgVku>5H#aFxs`Pmu7~o&wTi#+#WTkbaeDMN)-0Z(KrMzswj%UjoS}lSrQ_9B-DmprOvA_JHgGtF{#Ul@1 zpK4d8dY(RP)d{RDIyz&qul$zcG~`G+jK2#W8MQcA-lBL+aYe(NgI`>7XDqYK>M(6r za%D>RjjHU8pHyWnd^`49?31d_%O@XP8?+83Eean_vmQE}X7`R+EpUc*>l;;}g`=v{ zW=76^u{w}5sw!pT&KWON`*WhP)v@bmjH(Lt9#!R=Ief3bmLF}zMDd@+5gZ(}43`#xhOC4P0Yk%MFK*dLBbM{7W_^-FJt>(U1Bo>I(iM@5eb6{*$%8pm7L(|7rg_gZm9Uio^ zI%)cj>aabw%D3UID&O**)hUBssZO<@K5QqyTAeZ-rF)Qm5YpOS)Us#y8wWggc+Jn7 zQdie0_s&=qv&vsUd7m8cTsN`GlWn(sq1toZ3)M-3knXyaT^Qls)|$Gj`;UL2+P;o9 z#7)NxALLu}d7S|V2YHUx>0cGQ}sZk*rQ%;E8FyqDQV9xLv$IhDlyNAa-SfkeRHx6L+RRk-Oe3hF% zfqZIJlC`JGO50X#=P-`@n6zCJ(Wf(KV5IACh0-3_wSLA#tyt>FYd?=s>hF0HspiGF zX1R9zeLwf1k%#Q?onHl4udhr>on0JUS-vk=KA~p+lv%cE->}#`)0g=ENJV;Cll{SR zckh*17T%wXb)U5`JwE9xa@hWnhknoBu-|(2f&1^je>(rZZFavtdohHRJvgCx+!&7i z^59)vI9__}(6zk9%;WEdgdR_@K8)Urk=8RjYc%2W_eYHPW~Lh1;A~?Gc7*0lVvgxq z^JohB`{7XK2?cM)5e6;@`J}$b7aWH;?_?(KkU5Al?{D_z*TvDx^739^Z}&`|l6XQs zKKbb7ZIZqg4PJxE@7sm%KnXJ2-hOD6ze6e;vyB|&ZGeGu?C3JsLO%aJUOwL% z{v1b2|Gg>S!5E%{68-mO(rzW?Yb)@6{BEdq{=!@`v%V1%$(|}N9hEeM}YD(leQ}WNI zpt=|+-prk}2w!1TVfu!Xh87r_++erRI@lrwth-0pDZq;GuJK?`slEvN73?K76!|Oq z66`HC1utZS+DB?y2e?D>5xIB621 z8B~MccQ%wvJM9rPH58m1S_w5WoSnQhoiZ!pX=resTM8krca(_ z1s~5)hV;p^t>6>xOh}(R&kAmq7K)t5c0C#H26%E(B1>7-Q&LmYCr_Pb1)olzW@=80 zoXNynls7BFXAgoem{IcNG>+WC*cY4JkEVNavLkfP9DKRSyGG58tYfQRi~M5LHjz54 z==E?tSUou%((y(GE4Wh?5WX@qDYMDJL&C>IxrpY z9kPP&tEl2gCMpbmq`bo-eDQMdr^$Abi!_3I#K8((mWC&bZ- zUcqvwdekT@+MI(i-IIKS>4Go%E#s$q>NJ(Q>HDEb%bm%8bTqvv8i1n0T&gQH`azr<7bdy{`y^m+6-c!isORJ4@!&-a8mI2h(A zZw3#>J;B>e`teb&tKglUOfDsF&MThiYpmcdPX^bBH)n?@%G>^f_j*zS_zmgJ+2fD$ ze&^tWo;2Q9?9JKhkDkRc9`+<-eOUU z@f9qxGpJy95j}$&r@yNQq7Sm@0d@wjIAF9D})qoTdQ;8IV+GSk%Y(VN-J>pba(I9nf@=XUJ`wa^)2(Hbw&N$ zqellb!400Ym@zE1qr9y?c%#z-Z_auPrmJlw@kq^9nK5nP=xmhHgN}ZRt4FN{hk|Q7 z!9_4cIUj>-J&mYv%=sdN;BB5Pb0c&PymN7{PQ?_}#7g4E;X;z$@KA7p$NLftjkwnd z-t0-{#%=T%$7-D?nYB9gzvpJkvI5)!w%Ox+7cDXR&?!c3U(l zwAd5i%Lu`){AS0_dKWD{ zF#*D>>`Y$T!AT-ae%~kfZeiC&jNK!}W`+FlEQ%jHhp*qZd#3Yk2%}(#A>?$Utye}I z@?8k4X#0q^-X>idTEX+ToFYWneN4I-^xm{xf>zmm)Bl0;c=B}}ZR2R`XVPtg{vd69 zyvQyxws)cLM#y~$Uv?~wZQ&{05462b+lj`OgHAL;$YrEGIE{7O3Y|~3wVYLA*+Wb+ zJ}C7o#>Z28E|d){;3Mq2x%EY|uV!jlLsFPVFRWe=-xM^?8^C8va=&ZqSiqQzUe`C4BvuNY}o|6%B`9O|6ycum5q~Y(W z2)W!=_VCuUHN^#~UupY}^^Ztr)Bs#4Mmm{gegi>7A`yTPOO$^F=Hc|hC@9O0VSr}EmJd-y{U~-PY$HpW9&2x zg(ufaPVNgM_IULzZ)(rvUdcU@hoC_|#o(%~zYY@7hP&{*sl8LM*_77rqzy&wKP->1pVX!@cCk9}v=BjeDDP?O3Tg{-!)+*74iJO>>Z89HBaO^Ix zG?$7|HsxG$D<-Vhx^k&a;dul`klc-#2$TH}U!7rr-x{LGh!Y8}8J~639u=oFg)7J! zML4CcSXzoi|MJrUG4K&Z6dLgqqR5CR6I(oN6PyjRff*>)C=?o+s>Tqk+1M$tUizv1 z!)E|2^a={NjUHnf?c^BqhYZGm`?QdYw~JXtMm&{JvzD1=srqH5wbkS5`mrBpoL89f zW_|Fxdu#$|O5=041=4UE9`jL}P(m91d8X!51WAqCkl45lf7lF6NlzLWxTPj#HujQ6 z;ppZe7=>QB)xp|LN%w~QV4Gk+if@ScW-t~G8B&;itVyZ#*zsC7GBJ8ju0#mqP+XY1 zf}UdUf%-fG{C5#NGNKI&OM61#r3Bas2Cr2zKTctaV_y#3Z|p0Ums0r1*vAo{8vC62 zaSHs61P?yM_pY4+hXQtj&upVAg27Zpf#b@i0XrP=9e__#qm|1`bFr~}7%e0r7)(|Q z98%bc4n`bJaF9c$`xnFUEH#cc((&nBo~mGJ5W^5^(^1nFS)MTEc+JXu@Y+4+1I;55 zy+Ud5qKgI_(WoX8Qer9|7LnRxY?PgkYk}rLx7amjQ*xW3`&;s0;R4aSHVj;NOVgn+CnsJYSqbzN3WV6gU|WlM=ri!eRuh zPC{FMi`n{*8v7{15l0ixBcQU7nFxDLlF^?7-y3lh;Y@?kK8#ai1lyWObT;B7VgLfl zm=mWk%27(<6ec*zeB-Qn3KZ@LffC0)D^6j7v7bs@Z|vwIh1HG{ic`45QBvZYAv}cu z-+r8Nnrd50DfC4MVD}yoJWu1p8%k=^I5z0GzJMg|zAVYvmn|(lW@k3(c_d+g$NIE51!tXHoRY9k zE)FHElZ$<3o&1WV*aZ;IIzjf@buzAYonYVA0_}6w$()jebuwp8!d`L`?<(P6*WqfL z;F7_ilHl_2!kuEgcAZ>W66b>1>BP*5?}fmC9PXkqIo!2^oq7>h2!rWq?Q%g+YnKap zTDx4(Q?47nMgu)1O5E%eoaHjEcDbOZwaW!PU5!M}azRg@hvMv+YnBUo%EfUhg4ddz z5~tv-l-XHvzLb#x6KG>8g+~zJ*nVSapmXCml^r#P?v3MI8xs)N(F;Ka(@_e};y_1h z7Y908yExF%8y`+&qUxhvqt4_K#_`6iV4D09dX z)3`^+L>t#VhtsW#@;wQ;Ieg%O)YREkaag_Hej{GJejxvuc z%t!KFsBW2*oh^B#IUVB(SYjJ6Z03XJ^W)4+95FBq{09Ft#z~DcB}^35p!5*9?e0hL z!#{Un%Q(g75pcLA4jFMAQH9{O=GbP3Ul-LeN2i8yio7n5B~4@_c;Tke?Emu|JCTpz zhyUV&yqbf7$0~@sn;GXd?v5S>?L}f|Ntm;pY;;NOqsYyP_7M|}IF2|Q!L*NCcRqsJ zNAW5I6iX~cFzw@B`xeJetVU4#C~_Ch_Hk;wgn;@8?#$H^?!|dM&$doCm-Qfett)J^ z58r6)qY3V`u}?0o*?Y58PNbCxIKL;#5lquLiFO+M>F&7)lXLYJBA^ijr-T}TZDKxX z7K-5etTA#%A}BM4!QD?`pt;EhAPyqIy^`0OUz%`Sp2*!3H;u>2k8?vbMiDp;Eh`Na zG>%ib9|8G^%?QYEC+uP;x+@Av-19^h#RFEM>EBqQHv-NCOKT1vUhMZ1es)ZB_f^L3 z?w(l?dSE_i+A$v#h|ltx)~_gj2d#S#!EepB3R=b~euscV9`U0Q#}eFyV)r?WZRFnv z0@lUWWme-jWo|FqI*r(Xz;(;h!88P~by;bgP2&rSP%6P6Lpa%WTXuXSU3)EyAYOxj zOvD`s0i3zb!H+P?++Y}eUw{TG6HsK(y24r!!g(E)DF`@c_63ZE8n;>yWf%jME$Cxy z5_bdDl;Uotnmq0yr8W-hH>tT%$c)VX|s^+r6M;Nal!y}Gn1if5ycniaE##Cd~cfAZlPVF_p=!4boZ zDCSr>yW|zc?07pV!=0BuA_}5X^LZ z`-Z_V4uRcZYqAh1lf32>!061z{GiOo!3YFg=V0&G zIUF58;m7LYKc>2QU7)pPz90hI=WI z<$v1|>;D&SQU9;Y)jx4W`!8Lt&N_4UoO9s^23}g=%?9)256)JxT^&z6^q-2^Lbof9 zRO4(F)*5H4m@}@kRhZ>o6|;p8YSg-3#h*#7T4$>PxI*&=&NmKMy>zfjPpfdX>i5?7 zcL-$rGqe4HJh(194{ksM-ul^e4VDBiX90V>KP9K1KLp2`v}NUG`X>Zz%BT6~!V{Sv zch&g&eW-sJXwUH%P@V4YM>tLtec6)L7owodb#xzRN|GbJKl7v4<4=6+nX2GguPI7P>Edr{ zJglLCaH!TP+n?SZ%`C`-Us$-Ri=jOj-dEsuwFy#(dLyo{zdf5lH*KTp`7ViFI<&#N)mkAW=Nn{k!UoA@DeZFI4Djbi zkCd=={}UVHPN%QKV>if1ZjjE$ZID6OWZr(+SQ1^bF%`DX@6CB++!}t4jnv5WY8Wem zOFVB%Z*Pw|c|$|=rs&;T+MC`k=^Zn<(4XS;DwST2J9diR3ZSE#iVyG z2FMr+9Z#by!{~62Y1q)QdrRDe`AXe#DhcZQMsn>zI3S>Nob=Jn}zvgul-?{&?+sQw;nyjg0?8yTM z4jMbwI%~!`XTizWe?t$HwXP?5E{a%`ZImQ*_pL)EUcJAy;<_x*;>~l)~=Q+RpmrgJLufI#< zDwvl{QV#P#9^@hS0Haku!s z_=Wfn5m#%R{)oKioc-Y)-sCCbRIxyJ-A^Al~=`0hh?WM%*R-UHnZ< z!SrXjjl_0h4{@+~mB=gLOutFoCcY_tDt;^eDt5)(Wxhe;$>KTUT=8o0X7O(EG4Vz5 zU2&iIgXqUZXFc`AmSPuika)5o?<`Qhe{tIj+K3q^r_->*=I|? zRJ=m=YouQ}BZiN-%B?B+fBXs3BkKKKOVVSirfUJ_rI{XOX)i3h}Q#a~4p z0N8)?etndeCcUoMfP_6)dKS`)27|#OGw+A$^zluI!(S-^zYi{84rr$2v0}qIr)#`eELmkN!1~y^YvG z>?NA_0`t*#dAa)uFU(gusbwF^@ez)#*pVIe6N}L6BpQ0dRwtT>>`d5&G8rM zPnSMfoF<+p&JjyQ-onZHmWX$W_lggTe-q7d8R@r5e^Go@d`mPB{36}orGFtF6u%RH z601f0k;1fxx8JZ`jl^bRTd|{Pj_*h}RQhPqJkkjJMCnt+b45Np%^tZ$h#ZScj;z9AS_=EUQ(Zll! zlou8wVtvt^zaYN3^p;|t$Ui_ce-E*bSS*^i03d#}^pnN^s-LuFDrdR)@BE}as&uY@ zv}dKiAo9s-_G72GN8BqO5Wf{&e`)9OdX2Y;RCZ7LWJ4#y2W3U3;;I zX#Bv#UMzjE==xhT=fQ}dB>PnHeDNZYuWw=b^Tj3Nwc>Jdl~^Ih#e2mK;$tEo&u6*M zi!X_9h`Ys)#81V2;sNo9_@n6hGrNT6+bI8dKV~<|zEZ3ZdXCms-wh(C(Ii(a0mqg>a&TAFm%zgi>du79;w(#`J&(z*WEilw{$*G`u1`d>4@qfp;DvR^397OxOX z#iimh@n&(2xL&+Vd{EpZZWgzQFN&{MEWA}YH^vkTr|HIk^VO6cZv6kd={SV2<|MVl&bFUPQU=q!)_jcO&e_`%N37_~GI>alANLJWD)Z zbp5N9N?#(H-;Jo}M(O7FBJ?|?^SOWa`!n&d_=9-7Up3dCT0Q;_LcZo=OR+%gA|CHI z?PS?c6VDYd5U&&$i8qKV#M{K%#ZBU4;)~*|;=AI9;%DMM@v!)V_?u{c-=Tkal-~5y z^^azL*TL@kM?2mxS{J47A@bb`9H-mFd&Ldn-^3@xt>W|I>*AZ@N8+dA@qW&Z$nN?( z`%Suy-==IwikK#5iH*e^v9*{dy8h34Nbe&K7Ke#r#Z$#e;#Bc`@gnhZae;WXc%8UX zyhXfCyj|QNZWK3*Tf`T{m&Lcl_e9rU+Go-airO#N+*{EtB2#uXd~S3h^%SUeWch_BZKIi_eNX#9iY1;>Y5b z;@9Hwe%5}G{hwk07bZ9kNn*NKPjvmQwUFLkJVER#_7n$-CyIQ>2+O}%yiB}OTq-UT z%fws7b>bc3{o+I7Q{q8Fd6#S6rX#RcMGak=RFPrF_E-QpwS@2ho$^^e-Sr#B|a1 zkJel|-~Gbzh>63+(c*Y;``!$ z@t}BE{6YLpKw+`6I+UH#pC^^4Uj!1juBmdYLlg(C0-<6BF+~VifhI7 z;$OuF#7D%(Mc1F&bJF=zAGUvw_=WhD_?>t}{8{`>>8oITnvS?)6^y6Zp^i6-fO1Zo;en&%JQk zMXo!5|2Yl@_&0f68a02X299~hI&}=6`83Bj)8Vq2`E(XtFpi(r2-qC|HeCm#IlkV+ zM@YE+_&Eu|Et~pU%#HJLPUe2xxD#Q(Pb#ZO5#RK&tcCb(k7>e7W4QakX%}B$6Glro7uAyLni~ zXDF|l9ni;(<10fG%bSVvn2hbiDPB!^_d#Z!d<1^>bb^mnY!COtIEF_>H{GqhFwSlw z#WCG;lHI7Z-nh2rDxf=Go`Ia$zBvi~#i6FAeLEpzF3$qYXB^5)oYSn6A2MNjSWA&E zAIAEyyXA4*S*N=;AX=L-|Ip={k6RuN`^Tia3hn!}CROb=IH6NvevjW{={H=_~9W&0@)AsVh#)N`{AlzYO@Ks${QcxgQ<| z&b{j40f7(FWB%nOO;eY9RwUmXxHY*vd5!B`;Iu(Oco6v8!a%ua^+gAh?R0n-ILUKu zmeqE4aq?k|!b!}a^eiwzo&~&Zn#b^hyCeBmSskoH4==&+adji43xKjpi-G6n7fAteTTSXgxMn7^I#&FHDOyj@66t?c&yptc?h%3Rfo?f^ zTR(KR%aih4^|r#4!yfzN|p@DB7C0ztFF542jF6Le5>9^u5zLEVC^d+;{DhpIR zQ0YzPh;2JkZ;7}3?S_7MJQ(OrD+{dgl-q|bcpuYSMP&g%Ea<9+da_f&a`AltC@ zI<3k#|GvYaF!WZ?5$`M7Qx({oayXO%-G;r_Q-|%OJ-dCY?0CxB*2UhnHfB)oMV<~t zhcXt0*1nH7)59Oc4zysFZ|(N#J*|pkJFEAMTOWJ1dXN2b^`2halHW=$I@rJH<75ji zuopfu;9zXPx5;=#zh~gVlLoGQgxjF#pts1X7<6#(Apg-i{s9O50~$`T%g0X%71}G4 z%0r#X2UulGcV|?jl~-69Wtn(Gf74icMJBetb?DZ`fr^ZBYxT&3Wl7#c-cVYF=dhjX ztsIeBr{cBBq4T_zF9$=t-Z80^TJg4sOY_XY3$C* zK+3vUaE+BW80*KgmMf@B3~OioJ6b=xuzujXV@oJM)Z46|KL6PLQe|vbxN@5ntb8fZ z^pMwAZ`b2LTcfbv*S}c(8dg{Yx@T1W&z=oN@8E~-E6V@bhxxFrF!k{7eLqg#Z`Kd? z89{D4>_ZCLpa)pRZD;Hnd2n68%6oiwr&wWZaI9}^$5-ACrQiSdP-tyr73K-&%X-X} zZJa9~w(_myZ2559YtKe(cQELf5Jw`uT4(0g03a-hFc?8Z%2 zPFC!**ydR0m?zfbXU~D|KYNn5RqsTv(_%mD{wR3>_F0~8&kSI%0*8O^+8n+5e7BWd z&v@DRGP(HRpkm+AIzH^vikyAgqD5AP4|~$v4|~GNhrJfoTdI|39qO{kzmEGPjBOhC zZP+IkreiPaEpHrqYZFGe2z#he*n<|>?Ha?AM%pg!RXNhMS>@b+_8&MsW?B*(yYTzi z#C=vpZ3`wYbn5TF$i|-BDhnU}y?d-N=1&S7-W*C>XKw0N zmln+dUwc2kx@Gb77S2I7(zFz^Z+O;hntcA>ncxK4M>e?Hn1V0kN3HJ_+NWo&rYYp- zYk+*;qfXzs4can4?`!dAXO1;8()&APPNRGl?fG>tqr493{oON{QRd&D{k`kPA>-ZD z{HwU{Q+x$lH24K3yx<-A0vTwA?fVel!49cxAI1^#Y$FH1LJ=YO3h9Q3kS}~IUo#CsYM>gXtcz3Wb%pSOV;GHVL`~B@< z_2l?43}{yH0WY)qX0q^y8-0hQ^c8Y9)7YUdu-2jM<4?PAeKT%pongodpAh05JrUkM z6E4U!clS8HLc)cr(HFS^%?uYNI}Hd$c#CSdu&$$~MEWsnVIxO1zCyyClIdy%o(C{c zya6eRcO~_J$@C3BydFXkx#4ah-pv!ahXwQqyZw6!X~R9G`XV!__L3Tk^h966y``o^ zo@IynNKK3IZh>%LsdXcKb#}O))U3#3tf)w8;|OoH2=|woZDnL()IxT6Xs9tpIC3+# zYWSoi${cl@>aZ|XFWxL4d4c)}(=q6tNL~D>3y+qL7ak?uhPpc-wdpc^g?x+JmfPVo zLM1HSjQ6Ar$}D|5TQ)i141q7go6Evyh8LLFP=pN&Pi@M;y7V3pI(pO0M@eF04uaNK) z?o6Psknm<{p~xb(>&dWLtMC=llH>W5RL56H`04apOwDPL5+>fFyjhV3?BWY%l;|tu zNyfg|#N0grUm^Qh)XPo$Xf6B(M7ncuUyHOeYMaO%?9=PvK}L0ag@kviBF9%q_)T@d z@f8x@rFwfuMzW~4(@!#aiz0i$@H^?J8`bd@5`JGr6-RheNcbb=9Tqu{Tj^swxyn|J ziu7Xary1r>9{39R8`aNKR+!lFk&W!pm#JLA^cBMUB*ObN+2|{T+nQPHnJ>ImYsmF5GQ|Hw1hf*h5U$L|B z|FG!Q97gyGang^9Hemhm6~e)xuaJd|hp&*`roH2%TvuWE3gJ>RzC!5VA`D+4TqDL; zNHGoY719+o7+)dhu}Js|DFMCo6_U>~;VWc-N%0MRg>Wf28|imMCTt|5vT;bX0d4a8 z_98)Dyw4kdbVq>+NojJoXELIk@;Gg46Cr;-3})}oS!fnBb{|}q=es&~>b!q43|}Fy zpjTOA5s?yxuaGAoM9sbgzCx&AjYrv@FnonLBj}4>!T!Tnh-L(8WXJtJ7N3Q;_*$u9 z_zK}g;b>z{mLfZY3XA%MS>Y?h(F4&FktGaYA?EH~`U;_tfy8QdgI!_x3ONOvCc2+V z;VXnkGZrLqaxFd#d9^+di3|}G6f}0U7Wqt4!;^?!Y#Y_)hA&y=Wy_xmFSI9Kf&pmpS zT?xZi$fd>rUm-nN0(^zA1z!3Jd6p^QD}+TDUm+vdM)(SG4Dc251v>>_A&vpQLU8x9S4eZJ@D(z}sCW;|HW+w5hHOpg)yQuTVw2!2~u7=G&_XURyNyeXP?aJWHsprQxbfIEI=yThOZE2^TJoiQ5dq=j1lpEAD{PVVUIv5cCQqhwe!O#-uSUsHNzFUg=h$zg7DTI&hi+7<4~ke z#tV?2M!1`{YnZODNjC}w@)q-)QxO5DAWXL$`h40V7%00ay#uR8ljk+;!|+*g@yXkFU)s0JV3$mNNRJ+vWhze3+n+uO#LP1|eu^TlR_+z*Vc z6>TNBc0LWkI4C*EG-W&fT2&XpI4BurOd(ulpIH|<&HNc|Y^e<#C&{_IlNruM*t2j$ z+%O5d@z*h;P6kX-Jm3&PXjuY(9V0SnnhJHIF~MKQh$u}fp#H^}I>FS4rtMIlqUkKS z@EFmIrpzXo2MD=~SmnrcPL97p{|jx)jI9Z6+nQR|T?o0i8e3c1F2jVl7@;Nnq>M6~ zW-GKuX@S3#QT1Lxnp?7QI6%lXt7cRdZ5?y*H;EkBKIDcT)r_{>RydtN$h{wmJ*qWr zcSFApp;g-eY@_RPMwYhbuc%}UZ|-xnZf(ex+};{@ry}HT<}`6^=h1b(;2B82lCpbkXOu(d%irrUW%{6K7 zcha7MbmMB$%4l`ila1wq200)5i8`MmV@H2;%eoec&qe51mF@gNt*jlCN+{Q~$DP#( zdCYV|FQmm^ZGOij<11us^Ib^k?+u#Zk2f7NvT*}{2W(t~0w!T(VKZ1a!}2%+vhPNA z+P&txtI6JDBC~&qm^YBYUB2Z1z=1v>3rO ze;tIiRM`B#LD+;)z|73%HlLew26T)q3p-NhK^Df%`5KbH#QfZxRS=F);pS|O?bsY4 zk6E-iJ9k9HM9hDzXnfl}?bLlNsR-sVNIQz@8B;hMmUE#^N5CKXn9m&OtSsj1ZKv`c z8RRmgxzbtuVUUIcG?-t%L(uhQf)veU>e4nk$eS~mz?|@ zN!oqpo2%O%W@kLi{2ak$f=oB1@9U05P@%mjS%uxF3N zd3&ZxY>qt55KM`^AoQSeAu^4EFan{#&F7ZLv0*u0^SzuU!YxyOmdJ5E2YJq7KBi%; z8KcW#DM7#vllf`)n(tN2f3lsn$jyHfQr*D(Ov6}{{~lQGa`LlBw0q6>YUUqrXT0t9 z=xL;S62bK7T?lVexe%ESLiie?fVr8^?Ga0)?ls?QS>ow-2JgZ#qy9Vc{DxpkY>R$7G7fYOEr=7zRIS&RRPk-iP8pfJ=a0V==BVdf!BHF#? z`(EZh)6RIpZP9F`nuTCmv<$-aR4zoO+abge3YeSu+!nD!>R$7`fhC@8XM}OGVEXtt z@;u5yu0Xn75Oz{wiTfaYfl$EQ%;%QK?MU5gzBjVO>2}%>mdJVV3-VMkAJZ__Y{&Eh z?6D9u4`}zA*hiWFJUi_=H-9Un%0(z(8pfLZePHS3X^ z4(kPk0_J8um1y=OdsvQ@&+k>311yc>^AXa2fRM)+)3<*>`xZg_A3oLRwFWcat#;aN zZa!Zj_GJipj4}BdK#L-1Oqnli@te;B+U0iICvM(+r0RfB;KrK#XTWm0lb<8NTt4%C zi22vq87D+F0<)277J@VHAY4zy%sU8igaYPfzQi%5?lo5P4(zy{vB)iPGx9vnLO7;x zLD)rwC4L2AA3_0hGhbqfRnTpV-@j5?kM-}C_$%`K!a`VL{Z2SPMldC|htL+Gz|EIf zBFpib(g4f89qS*LAkB6!LY}@Xge6XZFrEtAcoBpP5DJ)^`P}W!pETxaNz+FARXaQZ zrFGf}bH_XJbrmu#M!?_ek?9#&u+f>RI|@m%ve<;z?C?#;WLk#|Ynh4B%G8BNdgqnl z{GN?q&+s&OlWosH3pXSE;|K+AtU2Vr1x`kHXZ@P#vbs=ORNcCE>0 z_OaI>pU2|&^$4i5PNRmXlgHY1NVOKhZ1v3$9;d>s{sx5C5enRVZV!0caxcoU%+E%9 zzNgMPERE+aUn2cp7EpyW8C`I|Mlk0s{UP*1$eV&T>b%7qBLn=&Vevba(qHYgyIC6d z9W#;sJcI%_)~w@2u#_TbKfqjGlb6qT+V|UO``rAuAk`}7XBx(u{13o#Uu}Ncy(X3y zbnFN1w3dxj|2CxB%KS{jSd;&KSl%`HJD-k5(vG7Ix5-93<09texPF5a2NBG;2D)Nj zgJ8zB5rhT^dCcREDNAZ>O4`PfHrW|Zx+N7NZ9X$!fi%M)45h*?bS8w!2zkt-lFatb zH6`)84TAlMoso>6t)^XNGtO{J zd_VyV&{brWNZT?TB{}myRF=o7* zcEivhAPYySC-Pz6%Y4t-8GmF6ofqHar?wM%y-Fq&G!IE z_Vac|K@;TRJf4U2b6EiA@d^kxQQ`UbJrM3fC}3{pbLTSKR?KqD_h3pd*cnS$BIm=? z$nzu%;V8We;cY5x-$4jpBNQ+<^SNzgiPW*;@jU{;-fm~S>z4RC^8Cg^SYm_jI5;Ah z67wK*KqzqYC64=el;go4Em7LFc3K42B+R%EMEd>+d5kgRJ|5aB2pD&c)+FS!tZe4{ zi=A;Q^KqmuK#KDb%t&1e;c6-zskIQw5%QSF9VM1D6(xDi_YC%FnVoT;TiPb1f0zYu z++TBk?yDO3Q3TCcC{H+jfro!HCfN(!T9@DF*R<{s--+6zu8`<91(U|V^w(R}M zPBF@C9@wkw6ke3-ap{>eE$=UOn2P21@ycCKtSQU8&u)x;0R$d}oC5Yc1vq)WR-T@} zv$%KN)LgGl>h}^;f8eI(6YJiW+|=A6PU@HKWY+DJjk5#Oo}P4o<=GGK=pVC5JCM59 zMYHhU;{Cx+FTet&kV=1}oOu>rN4`Hel4*PMN$rs5>tJ{*GWD6)3F!_5Q&~cvd0jhO zo`bUt1ikkE+p*BZ>QzQ-qOsA}!SPTvZHF-=Oey5Hu zHCB}*d)FGfn;JXMJos96wruN^Y}3T<8cTJlhkPGP?U|TiNT!nof5kOEla;1-)OAD+ z1IMC|98oL2@9|}DZQ_G{5e|oc^q{<*yEN;{DvQD^2uPG`7*>SI{wH5J{l&q^_)x}i z2Zg|IEQQ{VvbL1MuOU`Vm&%mzLzYNAPKSGwX+jjcqE~Z(9XE3or@M2B_G0aS6KyNud93qfekguD6pBR5cM7R;m#HA zRtUF`V@w~N9Al12{wLjPZ1RsKoKBsZ(5dyNQ|ih3(uAI@PwdJ1(uAI@FHPvl`qG4+ ztS_zY$*DE%`a_#Ipzt1KaXeWyWw&O^?hsOT>!s{gOPRHD04Udd{#8xBgqnN_HTe>1 z@+H*dOQ^}0P*ZLBwUR1VpF#;Wg%WBCCDep_k)2tAwucgG3MJHp6#5)fQ^J;8o4DoH zCT_X4iCb=M;+9*RxaHO+Zn?FkZhc(8-WsJ=NT_;wV%5t_i;$xnApnO^fx^ad%Di_D zUdI;1`D&gLSE2Acf}7GEAhSH(5i*K9L`HGP$S4OfG#n_m49Z$a%WFDeTy4X15gOw2 z(StJt`DQjf!lZLPezeB<_>kD9-EmKcT-5p2ea8-&#qnd}9FgC4U3^`Sz`01SLI}h2 zS%KrAo9aJJ^py@#qVYkTjpMjTHtz;*Y6I0bHhxT+$|%b8H3I}>2$JlJYdj3yZ1esDpY!Zydw zsqq#9+d_Vd;0_w)A8T}9oUa%99D!;1N5yOeTvqbLDYQX=^W6c!{Rm7$K7!zuM|rE_ z$ZZL6oQS+D4C6}_A=GXNYQ+dFlpKNJ7D{8L*;*>9}(S32svk2gTD?|svT!N7pTsy<=4yEfA<^d=^*smy3r z-zVsle@xK1s`!`I#4`9-P5!CSlmU0IlqV$Uymgj0fVlCLmnGz^b5S}A(b*1^)3ERo>uCYK5W$oQ|9F(UCg^-8*)oL0 zJk(d3G{}H@DVH1F=|7&Qv3M7>J3f>*Cg@!JUn3-z`3>}65rS|y_*37X+QzAPu(C6( z66>e@pV}@k-%WoAw{3wtBynNYta`_3FXc3o)=4!tAua6;u7h9hU>FiBr_SS9qK$fY zgn;FAawufpTbP)J`T~>2aV|*t8lz(%knMWNqH=ZqRR{ZT zM@OS5^Cg>ZJo}VuTIA%XJiyhFz8La|1fB8>S4aK4Fz56L`B}a`Jfl&c#DCSB)uy%1 zR;IiqL8ts{f==0ETJNN1>)V*tI6CFQ2|8t7=yP3bQg&La{A#WLKit~2rZreQria^FziN^m|a?0h%y>_O?zX7?O-H=@pwx;lG$V%EF7b>0jE|a(waeu<-bf z^GkvOe-15)Q=ofPD3`}6Y;%TAm!s`t#vs&Z?;_aY0r|hQ`LF5?+JaZHLgDg(u3Foh$vwU$1 zD;+z}JJuWV6k;QSIhUre%~5=D3OwOJOu(G)=VS7te4;bL|3lrIz(-M~VZT*f-JK>I zSx5rN(vYBlB#^L(h_ZzU$i4_F5<&o&8kR>8_5iI?9}f;;Swgp=JUc zs-A;pt?`a0HX82)g4ZABmcqLb!M($i&^=?KjDH8ERU$yQO!ff(GCP z%l9Tuoj*bkFG8UAu0>$TAMq|k%xzd6BJj!rkvanWDg?X)uPyNKs6Q|n&YYH>MR3tF zP~aOT<+A$Fs(YEbM(WxRKzV&Y&Rngi|a9^PF#B(4lR_}5INAVzN7oa*_} zc@>xOO)S@A{$eeR-t8kE{88CW1s%@M5EF_-4Xk-j0TSJ(04q6#@Wy5)kA#=2h4a}6Ga@sWgp& zq(d}USPB8pJ&4stj|Wrq-02ESBJ{X(-qJ;p*qjGjadTcVr!05c8qW!e4$ruJ5$}0Q zd>`$LnP3ncT9=?RMW$zl(N84kOg8D^yn<}T9+RL(p}NUc6OX`|Q@#w(E+Z_#WduC# zBNCK1ZssZWW*)D@c+*dOM$rQChd25SF#ybQ)TIfRW3B=0kNnCt%1F4+&Cr8m&&|fO z1F^d>I=LAR(Fv}9ritSg!noQV6pq&R$haCA6j#3Znbj);vt#>h%kN$?dTNiciO%&= z?@oNN5Nf>m(Z`_iRmKUB(-{gvL}#`;A^eGH3(4Xpt)z+H}!a4!7`)lRyw$SfHS*e0e`*45~t#?dsW` zC!3xLc__c7>%8dM<=RBu?y48t(*RCmik- z>Lc{H(>nGdy#9&&qBP#&)qy8R>0P(sqQjf5(94Iuh!VeQN zLFNUq(=UjVy(JS-J!@DFI0ziak1lVXaftLg@G}C9(*yTMv10b37TpxaCTwuYa?ccF zG!Z>)%ID!Qovf{=XCItxokM&97vNQTfq9bg14N%y7%@bySf9-k0HcYVKA17Y?T;5Cz`RyfnVjc+VtO81EQjt*a$&H{P)XFO_jpJMs}c+>&st z#l8qVd2ldD91j=3KtK-YErMeXNG{rJYu@K?g2UYu!Mpqb-s6ZA^xhB06y)>9-z5^e zqaXD>Rc4MG>s|9QHvR4m`Y7IluP`yrBzObPeggCKu7_g+lDFZ^5bv`?X8eyM65#?? z9aGSo4aXE@N8@*=)MEHCsSv~AOvk5((%a z!+{G+Wk_kPBGbR39vCVR}0!G)$y@$z5=` zavix z{w;Cg^t&B%F+RJ4hdP{*d369=1pA_A%Uk~wV9UhyE&`$oUI_JuLt=t0;w7e^mjltb z-Zeo~;nlR4RpiV)@Rloh8ah|PU-LN>H^2N;1$!H6tuHzcyB9Jt7I5!g#y$q`ldiTe zW+C^!WR&;e3B>h2D}l+9FB~}@4qA3Nb})FS0qjzk+gAWA5aO-}*ty`{2C#1-!X99+ z@kT!b=kx2Ixm=`8_Hb4WjnePk=hM$=i?--zU!^hny?P-xq3HL!#b;CPcfGL~{2{xr z>2T4@BdilpuxB>-bRIt+!y9^((o61`M^02GTR-|c^!cg7@jspPlNFZ%emKQ_5)w_s z#CwtC->$9LToV`L5wy~F(^4@da*pE<{%%FkGjQ?SseH^B{~3ydkbi(P+gI3MgU3pw zvo@mQ+@m?)II<<7TijGFNsp$2`%BW$-$5`9|JvJYwDI`80Hlvof(HrC= z7!8TbhaG*Df;Zs29NIRG@U|sBdYm$vL#9}Oc)T(3tnjT5yesi!&nk@JAK$sa+Z*&K zFCn~M8g%SGias(HePk?p^j{1V&Gai8 z+K5+1pKCcbW4VvOqED|Zn+jJM7n2G;&N7e6y@FUaRdn%{XB6=t?(m{JCOSjnDkEMQ zJ74rI2&R+ZBNH(jOn=kSHe$+H4cUx!JKQmiVsBDNd_GLnyG(SfE%*#i?36UZkof3! zOc|GL#=6hga6eTOv*Cp_un|+nWt-_Y!=bAEas7@ey7;QLso3Ji4aUW#iY~5?#$Hk2 zeI~}sn{97J)NLkuw2#IsV|k0dl;GHAVfyV2Z8&yJ8LcDR+Jjiy+4Hhs*?fvg7xx_1 zNr)+<`3lAwjEPOYb5p>fn!^WmQhU&^AS@< ztJ=1Cx!MyB11Kqe*=l68{J8hgA-0bXefWV8gdDXpQcD-VBKfG`*6A^0)JH8{+!Eun zsaW*K%ILb|_!#RFxMTCNR3Y*Cuo;!Rwnyh97!8TbhaLU8{?TigZPSSR&?~y2$19^b zWQW;`xO|@FS>YBiA7**7Iu+{x|L#JF`*7@RFCmKHr8#D0j71+8i#{$EJvyr6zTh9* zd$4S7CeX!gNH|8x{foGPW7$-=%4q2vqs&Ht8IQ4oP(>HlfgPiW|9qtv-LV;!Aq_I& zDUTX?jF$&@?8x&%8d!-bqa)8T>DwC{4L>L7*tE=$1~y{KSjnSb#6NcAF@2|_ZN!w( zHP{#IhFEm*6Ig692t>o<+rjMjoQ6b4PhfcI6toP9%Y3{tt^yb<{$rrArtm`IY&dpI z8O?m`JNCy;U&XLKs9`>AJEn}Ls2Kk67qtll!$PF#JxJnAdDWj96 z`~CSTh^p$*55DdXy6BVyeOckD#ug~VN1SawVqy*h7!j>C0EdxgfwFWGsA zcVp?@DtmX2IHkE?^llNo`$OIwUIw=uj(3LM&7gND$lJhbxLP>g1A4c8-aQ|0_`ZQV z2*3U(8asaEpU&(JqE`o zbaXx7`oi%U1l>ls+u`nny9e$exh>$6aD47S*A$LV!urDTF&H0J(M^Hlv#<;0mVtaA z#>ZE5*TeCt*duaVK|UILM{YOB=VRW%8%Xa~k#~pQ5wGLTo_Bb+XWq@0ccgJT!R?eMMW4Yn@J78{gMd!hD%4gM0t&rA}%6m<$s-8Q&x@>lM zTIH;YnsECCJ$rPRIDJlCxOVQ`SvBFZ>e=Cn*;6W}POX?av1hobOJUFa^SkBGE}J>G zdLjbz=ggf`kzY|ZrE+4WdxnX#%gSd|&Z)5epRirCu;zc$?ySlw6Q`G#AC>o>1w{pg zUJ3p;&+xmof)^}R&n_*WJ7->L^mi@`yBCzRCCg{mRMwOtQw1})1~KC7vf3GtFrZ4O zR!l3an^jv{yRfRF20C>1(wf?-m2+w#py$k*TYjGFi$;MKF^~{?%agyG6Rh=GXqX0{=h?TR-jWb9LNj@f&~HFnF~7ULjw4lSP%#W z?Lcy$g4{sJSrn$OX+dV-Y$)s61kP?9s5^sy1Hm?dI_Lrx-pd{A9O!81$!7)dN*3sQ z2Zn<7vH;%Q;`g5s=tC3)(ugqsw81aj15W1x6VvaEz!|9tw&CAQH)`}ePKrt8q}dG3 zivG!@&q=afYlz;gpm!j}Y1BK=D0oYtG3vqZ3$zY88&eAcPLu4cbA$M7AR@eVzKs}# zfs~-Lh`wQr>qSM?A!=7eef@m9FpMa<(a432T;Roa4ZE=$1)XpyLZs3L1*w%XSVeUc}(hq$Tlitz8&t( zOr;LVZUWgZFa?hl_g^VT6?b*DNw>&$tLV?fgvt0C{9Ti74F(c}S%Ky!qGBe51I?ZG z;XrbCaA85PfE63|DmE$T3}>q*QiI^EZ06mo&#>DUotx{!fjaaTyEp%^gBJ!05v>pU zC8aijG!_{BJ|&EfmX(!hI#$p`b@F;Q38V*|t@RL-ob0fZ9Cqe}os4ieY|?yY4GFY_ zwGiuXXy8P6QCETB$gDsH^AZkZAR-V5o|@$}LPT^aNBgK>5>ThcB$LeSGxKxp8nucoGF+cNOkH8^7Hd)CUpo)n{5V&ZLCqo zFaM$Y(8sZa@BQOX=cvz^-?vuaCw5?oY(O3h}*?T=Qo$^?6)LuKKfy_Q#dv@;|8PAZIc= zcuc8&h^y~Q|Lh45#^rL^pG|ZqE|(wwiTb-auD6`A_zw z|HPH-$Ny=fMyB)pR&DAQueJ8ZdhmoMfn`%zbesl4FZto%{8{u&JKjJreucG!W1jte^Z z$WV3@s+D)g=~@tM<4qL9j5U6)5gL=Alb0Yl=uDu_!F;O($yLqJLh{ETz!PQLEz-v*qLA8r1j?N(yNK0=Zcjemv6KsH76G`O;l%MAwy6#$_})! z?FlfKX_kGH_cQH46Q?5$x5+|CiZi-^le6?fTe*L!MdpLfJgwY~|6t{Q z50@Mbt`}~qGwF_9x&JsO$``+K|87LB+{wXaW~D~ejOW_jAsk37#9HpI+)kqH%wx~t zbrI{B!YS`K73$vx1?MrbDz_!uwZEfn=T^C{HT(=@y7;SWv zPIk4;8fwek5&B4j5egemXcYcU0l{!M7#*TdDsW4KA&OK_Dd6Fw1D?i+Pc?(g!Bs;T zBQn*Q$pRF)OFOOv&{LxG%=u)0~gv z=9t?Wgdx!`CAu{hz&s)3s<@24Y=sNV*|%U0k7l(`!>m4D@8$JP<@F9PuWuZk*SmGv z7j#;8qD*t3hkbWGd@q(IH%IH0Xm^7E^n#l)A70N2mX z#SXhl5o!(9_;@0#v9a@99ZF>C@u3C-A;sBNhllIByvIC+*$e|8m+$7{Gs&6B-kTXV z{WiH-Ae|##*Yl{fa@;XFZNj*f>SnGz-&ow6X*t!zuKSxY-jLqx$BlStXJ#umGaFOg zn~k{pl9st%Zp@vDnZ|ziW+TPHtw}D+8oMl_oe3^v?Lc#ksKy0=DOzJ) zPv`PR1=H$0)&xRP4~iVSnK5zPLa|88e!oblcCHZT4`D+%_oRk{?ab=q-FzLD>HoDN z{%&maj93}bJJO@2Gi?zonrW(cd_&Bdg$7Km4Rkmk{jhhS11cs1m+7XBu(sr$o(n;X zN-l2E%%apNIGhU#Z$dI-3(5?0ebKDItS(c{m`WZ4&yoHxm76vn;kP7BjolC!!V*G@y75xCrP@USG=xvw6J6|SZ5%m+W5 zi4Pjvc4_IDVMF^3Ew)Nar%lCUyV<1+=2lhAu}bI8DXmygSzB6GJ-x>2H+optF*dXPphW7y#G*|si~Yk zr)*Z~l)7nF-5d%PQ^RE6QtYCZ0ZEfO*n4w+?5XRyDVVIhckAyLgN^_q(A8$1RrIAD-fI;Ubm z?KBISD(u0+R+r70iWXB5O3%Zy&NGE33gX@7WcmElW#lN(K)dh^C)fV^s~F zQ^-F>$cL--`V#81a)E`8!V}G%Hm#rkx~vn#5nSIjA2XjP3s-A6M!cHo$? zr6v6a4;?ppAT!yc8`H9UH5KL7`8~RN;zCpLcpi>I&zWlBwbNbrr;vY&_@}E|RMTau zYv;}{ukm_lDVxL?j_b&k=*XpR=1w0zEe zo+Ib?%%6g~E1waru9#O@gWZ5|QIC_loYd{yaQ^J_s=8Cl=T_HNEXbeT4RY;_y4h2} zY0yurn%6DArYe7GVGnB9fcbc|f9i~~>ZwqaRhQ2=6)ipQq>B96Cr+yh=TDzHzpQ#% zeo;7oMAvZsv^jJ0Yig@2%aLkUWmyfjBcPn79f^F@lG&MnZfaR=S-d>0Dj(0rYpcu3 zYfnXESfy3n3l^oY?M(lw|v3^uRMW>1NYvvOoreau#+pLi7|aBPF>g`Ki$*M;HMa&GrnF{i zB_7CEvNyPM)&xDH#~3Y}J-f`zHSlrr>Bq?@){)WNR_PQp9rAz&^|LB#AkXHAEiD~4 z6#X64^j9;l64T23a#MP*9Ne}+l<1g2o+`@b)Kz)OO6OtLK@Tu}jk6#M>5fm9ywI9c zH+$qfAcCmsL7+#DFtO$D%ydm7JR0_ONPZplh0G*hFUSmskVkWuRP+eGII*6*YvZ4a#Mmv|yicKJObLwg; zP}6fN=A(({)uMNy_R1D;LMffqqg$Cf&rF$ho>?Z&?^>vVZ!BS!npIsfy|fPJA3bo4 z+tdxFDf*?g1{>8Djz*VGQ4Gqqv?rxtg)nOZZqbOz=?R996o`vr4~g$8+Q zuxhE($7b{C6}6~=3N{F8b}GtJTEi4rF*w0_9V*&2N^9Hz4Bpzg=atSXGo5fs{CF{S zgtXJXWCqjPb|e4r`RYfUx22qsbC9nfiR1PTQy~~*t;2qO2Q79DgK<&2 zT6PC`11Am4A7%wp5{5PMB?dG6P3$Z?$7yOevzy~L9q{|QzP53nUT{wqukc&n{T7!6 z>@>!Qa?jc94MwBHzPsqE9PC3jjfT<_w+Ro);nrl_;ozg`@rPr@eW(Kg4!+?Me>kSb zVjBD^PfUQ%vC@u`GmetekCK~M$3eqVvc5Bz-#@sP$@_z=C2XZyK4hD1>BD>Wc?L2| zY)0ZID%z2V#5QI)n~v-y4iZO*{7@Fdr-;+VI&qP>T)bM`AZ`-x6Zu&s+S?)S68DJv z#cxG^gPidb#7wcZ*j?-=P8a8imx=uR4DH+{J|sRVz9fDj{v-y`)tIiAc)EC|SRvMm z7mKUKTg1&Gf4ZLbUK9Dl=ajz^`PpI0$=F^e^TkudA>vu$4Dkl>cJX2H1(98f_8N=% zVsG&b@oceDTp;olOHBW)_)qbm_?wuDp~ZMDMSet+@-(qdyi~kSyhHq(_?-B*_^J4# z7(j=o-7K-4*j*eb@<$*TuR^R7FBPvB{~~S`Ul3;^pEE;$Ora;v3>8B0nF; z^er(q$$artahQ0nI9t3xyjr|j{Hyqc_^SA^$hT4OJT~SLGDFN2yNLtERpKq;9`Q>t z0aG9Cj1i}ZHR2+%UR*7%6E}*ti}#8zh_8uniyw&p6h9Zg7Jm?J%w^11rWh7`i6tcZ z$`Elli84)4c)8^1;wm&ILg^v)&N-*xrr2m#g`yLX1mfqjk)rZ7X66rI<<4BbE1cjd{c9H%x z68Sq_@)(7W7bi+TlSI54$@L1qSX?gsdJ^Z~L?ZrXg>Mm`5T6!b6kiqJB$4i4Bmzs5nv_N5aloVx>5j#ChvUocCgJg}73@QM_5al|;ISNZ8#f`2~f)BEBL0 z2a-P)_mfC>P~kRiEqMNbm`K8YrsN#4Es1pP#ZKa>3hyVDNIygzBmH=Biu5zYS>go> zzev1Nyhgl1+#qfuk)PYeE#hP1lj3V6%J-(YN8BrZDSj<}Pr~lM#bBl@CyQxf8xnTg zi5;ac5Kof+6tP75q2frfOyL#cOzG!{^QB)bUMBqtaiw^R!tW687atNI7oQS$kSOO) zaku!9_=$LkL^*#FEqrF1vR_OQ)5UBOcAJYG#V%quaUcmhgT>*}j~367zEqqkeU(@% zUaIgb#MR>UVnn=6yo*Hs?i06(&xp^9?~=&h2jV{Q3-LSgNAVXDcK<7;;>MYB6S1k- zfrQhHPWvY*NJy4{IB98;$z~o;y=Wf zNtA1sxL5p4+%Fy>QO@7QP_`>4i&B)uK0=cUx;6c|53P|?oG`fcKK(!U_SCH?#2N8+~%KP3Jv{jXvG57u~|Mq(3^?aNshmc4&T%06MB~edxB+j!?Tq^zLlCKi4Ct>F%h5uFh2gOIEe@gPR;;SUm zy(R7zzf}0w;=jdTM5no%uLLofgq<`oEFMpy94C<|$0=g5I7l2NjuX!&k!~glyH#SX zcqs{cSBTe0zgpZNeMG!R`px1N@i~RRAigU78{!Aje=P2o{-F4S7{G&E(;viC68X*$ zkCVQ&*irf}B+A)O`hntbakO}jSSn5>k*=1+c@{~&O5xXv>%^PHJH)%i`$^b&l7yWd z;!g2B67~F{_?ft0JS6@k{z}4*g)gs?X=1k6Ts)D4-Ogf9v9~x-94rneVQ;iJMVvt* z{|iajyFgqf{Z*2$71xunvq|9(O8+O1w^7Pr}Yd@qTfOxK(_Cgxy!fcf|L_e~F)qUy-nTP_$aRa!^bZ zk0W8Xwb)+lBz6~17EdE#x4$@AoIs*pDoEI?6syH~V!e2=xST|~>qtC5xm|ovd_(+H zw8Cz@OtC=hCr%Wv7e5p;+qmg09Lztq4-D~G&k(owhFE3|F`NwBi58i^!jBWPO53^9e&rG+#p88JH>m%hs8(5?cxsc z74dbEuZE@FkHpW#1L6GQMYDg0c>In$ z?ee?xJY{~5o;+UUcjYPbd+{W{8&94l_7^9MQ^nch`QjpRsd%|~mAF=1 zC*C67A>J=OBz_=%EPf&KM`M`3AH~CBfcuKjHxe_%Y_YYND|QyUie`Tk>HA6^EDjUT z6wSUT;+0FDF4l@D^c2aCf*exINA`5k`J?4yEw zT?u8rgM^$XULam1ULjsB-YDKI-YMQAJ}f>eJ}EvUz9_ybzAJtpejZl%Elw7vB)y5kD0FDSj&+5|4<#iAmgFhTX>Eabj!n zM6t7Yir7aSBn}nFiD!vrVud(cJYT#(yhyxKwpb!PCX@;yL1U@jP+9xLCYgyh_|4M#Ou?2gJw4r^J`U*TfG*v)_(<9gzI3 z_?zh9nv40)6mvwg4-fqbl1~y(5lh||UM#QEZ4@pADhaf28U9}piFpAw%H zUlZRHKNkNbek&dl9qz}YJmzx(EU)AoF;_f6JV`u7JY76P950?DP8ZJ;=ZlNQtHf)? zo5W4xR&krSQ+!$6Cw?KC&ljK^KT8hbTA1Za7F&qs^9Im&lH5h?D;A3*#j)aKajIA) z){5ry2C#dH^vj+Rq+k+R}sI( zWAdFQHW9;Op4dg~CYt?!*e{lB_WvQ9{eN(>^k)Aba+Ty-@j~$uaizFc+$7#Ez9_yb zek6V(ntgqo$L#Ba|CQeC>qAcE{x_H*wi4Tl1!9qSn%G|)E{+x#h)cv3;!5!*ag%tT zxLMpLZWmt`cZqw%z2aBmLGf47(mwYNai{pY__p|o_?dV}{7Lk4Ul{ch64S*jv4t2G zJBayWH?gPKM;ssy6-SC^iRX&b#F=7^IA2^UE)%a5uMuw$H;A{2cZv^)4~vh9Pm0fp zWt#8INRuRclg z6!ARK?61S#0?A9nE5&QX>qN89j`*7--!9%OJ|LR?cEsBz`C0KF;;W+Be@8sC{|=h{ zckl~^eI9se07l`%Z#p2QX^fyay_Un;9vriA2eR|OB&x6k@-pk@H z@jdZFaliPDctre7OxAvMn%GQiDIPC+`}AEUpCtAbi^ZYhNO8Pq_Un=F5chk*WU+-9 z7EcgQ6uXH%#eU*I(cAwXE%_X=RGcQx6l=u!;!<&$c!hYic(Ztmc#n9$_^9}}xI^42 zz9zmYejt7<9=$JqNcx{dOZ&rqF-dGJ=7`6Md18C9Q0y+ACiWN45J!k-if4=E;&gG2 zSS>CV>&4~b3h_GeM)3~uZgI1?MKt^A=pSZ39o#AX%c9v&hu-X`gL|dlCw?t{C;lS- zS4`l(GSVf98Dh5BQfwo36br;2qPNf9Px3%u~6(M4itxqBgM1CbH%CR4Do!iPFx~hC@vRQh-<_f#7*Mu;$OuF#mB@a#plHr z#dkz+Uq6-m)~JUJv6%85gTbAIz?7WPe~2%M-hTZ%lFfcS%JDDB-oE`el7AA9 zh<@!`hs4HWrr1IZizkRDirvJXVqdXXJVP8IP7o)Gv&1TKzPMPtL|iVK{e6^gjbyXG z4|$X1zlisW4~vhA-hTfxl3x;E6L*Vy#81U9#qY!)#T@N_A1AgIj~DaBLa~>4ns~Z+ zhUo3@Pm?@bJYQTOE)iFW*NHcYW}hGR@)ybXiaW%eqS@a^yf-DkFMcF`Dt;**6n_vi zxzCOCIbti(+u!dXIbZB1_7wYw1H_TySaG^&_W5z1YRU7&hs8(5C&g#P7sOY@x5VAz zKgCbQuf&7mPvQ~Lr~T}p*jUUIn~SZ)cB0wmNB#>XcNcq$eMPg+k9cQD9xF}|%ft$C zmRKd4{ePr4`~RTX{|C+fKWO&` zxKBJFek=Yg{wg|c-25bn8Dh5BQfwo36br=e;>lvMI7l2Rjup=lOT}s8O!0iNPFyN3 z6R!}j7T1dF#9PEW#QVg};#P5+_^kL3@m28+@dNQ=@iTG1_@j7OwA#A$=@(PPbg`+} zLOek{QS2(7B%UVr7YB>O#IfQ8u~aMl7dMJ`i+>gWCjMP~ zT6|7?S==RlAbu=wZH7S9yV z70bj~VwJc+Tq0f~E*GyA*N8WXo5Z`s`^3MAe;1z?pA%mZUl;T9+ z;xO@SagunRI9I$yyhFTC+$=sSJ}y2ZJ}m6m!H}@dWWC@f7iN@eFaic#e3UI9FUO){75{e-pQf+r@u~FNtr6?}#6Y z{}jIvzY-6LKZ*YpeJ8r*ZX~9NO~j^RYcW^sC>Ds_#goOpVzGFJI6}Nkyi!~xUMJou z-XlIJ{!QE_ZWsR{z9jAu_llp32gL8ie~bSS?M`leWQf^fOR>-{i_7g{oXNr~LY;mc$OuSLNS-f9-Nc=mAdf6%YW${DtpW;vA5iz;5 zTdp**jo3~+MeHMv6vv7cVx_o9Tq<5Gt`YAP?-3stpAz2|-xK$X--y47P8T=d&BT^s zfmkFC5Kk9}lc=Y2C6|fS;yiJMxKg}DyhD6Md`#RWz9oJtekuMU{#Q&dbn~Aj9xrwj zPZj%#qs24DSz?uVk$96JHSD7e5le6%UF2A~(Mwv6>_p(PZj%# z=Za-wwKz{)A+8i}5$_PUird6D#COEc#RKB6qSe*ScedDEJW=c{_7#i8v&Bi`T(L&H zL|iUjOQK(GlzgjrxAa>jZxf%D{te0Rh@XoG#P3PiwY$0H2#DEYbMZv6v)ETG7SAAI z=WNN7#JOUPxQIl&Dr zibKVb;&|~Kah6ymUL;;BUN5c}?-d^qw~IT(cf}9Huf&65u!mcoMDaMWwOAzf5QmB* z#WJx%oF^_4SBh)JJH)%i$HXVax5VAzm*Usre?{L(ZoXTIZN;wQN#ZbZlsHA4Ce9ZZ zi>t)z#5=`%#K*;_#J9!w#Qowo;%}nU)6H))v87lb7KsDI)5QtmL~*uwzIeHKm3Wi5 zNqkWJoA{FWnz&coC;liN78{@J<~vi&6Wfa?i>HcX#PQ+`ah7<2c#(L6xIw&6+$;ty zoFC&ljSS$A=odp`vgpNYBDtxE?In{wEaLHwk#W0bh|4}hEOUk!?uMua!`@Rh%Kt605{oae=r*yimMETrRE<*NHcYo5b72yTtp%&EghutGG?v zF76O_iZ6@1#J9xV;vR9YxKI2-{7O71{viG={wi9wTmODBBqobTf4{G(^ex1&m?yRu zJBeMyZemZdx7b%K76*w##gXDzae_EeoGeZiXNa@JDzR2vATAM?iz~#H;#zT&c)NI) zc%Qgc+$L@pcZfU1m&M)U9&xX@Py9msN<1k3AX+}PmlzV0#in8lF)ZeZUBqr;PqDW+ zNE|AT6vv8_MgER2=ZhKQEU`+g6&Hw0#O2}&aizFcTqoWnZW6ukF>aQ;McgWG6Ss>y z#GT^H;%;$|xL4dKej$D({w)3~T8`>p42kA_sHl&ol3R#jk-s0z`syNf6MKsM{a=O; z5{HT-#j)aK(fdB+49T;^DzR3)P`pH3F0K$)ifhGn;!WaR;(g*~af`TJ+#&81Ulw6iA}_?m?yRuJBdBTqrYcaEd5AvtT;iOD9#XPiKXfX zO*nt1qP@L&w4i3;?Ao#^Rsr7wZaBm9;cfY~R)Kk~dcl+${J1a`1;6(KWvc+cMNlxc zVoKd~_ubv{mra?1Un7VQ^U+ zLU8}Hc%2aE==1s;L8$}HXO1)Q*RxGUPsAD0#srx^UfAi7n7psi;?D{^^TKDavf#xq zwP=s|8V~2Cf!A7w=ban8%*KUP#`zhqC7!c9g=;YH@N85-5r5vTcj7auxF+X$c|PyF z3*h(Cz-#T9ZdqY^ba-L4kmK#G`_R4CqrF5p&)!w=duiaceucdSUZur_T@HV|y}Mv9 zoZ#j!8DXBio8!{JYt_!OtRoyWI=pk;2sz%~&V6nJmy}6cZ{$? zbTEu=i|EDMaRt76tT==h?`iqHpx#%;wKbGp(Vu`nK7YHAzclEWzYN7=HeQ88vsVG; zSORw-5Vt#5Pln*J|8wZ6I4Hnciv z{XPBr9x7edW_@to8v}gBZPr;G?c%~+?GKw|Q`i~C#Ok6sp9-?q48 z@rLHP`~Ovwxu$IiUL}8U!?Jr1*hyD4edT9s^M^lo+w82lqQu(J=zx=4y8otB>)?Q8 zN#FUc5&N$R;R~|~_k8E~TW!-0`+KiF>`zNO?95tw*crLup(`F5us=AU-~K?q+#@!^ zeF*m<+(x*4Ot`~R& zwyC>X9kyGnJ8VQdfV{++N+hb>N^AXuSIUR=!ixHa1yvUaN#P&IbRQ^P3)O8Ccus zy2Mo(t9@&H8w2aI4+me)KAiAX_F?>VaNE|uTytc^{^TL8e_3&O#D05_wYo`3R>{i4 z{w^yIJ5?JVI%9ug(t!O515P~Rj2pZ^)TqM|r#Snte}xsf;-P-~L;czuapq?qcD`!; z%krNG?N1%l{)m&i@~|(w^02)!`>^lj)erUG->83^BffF%kNAqcv%#tj-TBt4Y}A@} zZrD#a;fSxu-r(*3_P%ugp#=ZbLyg;fU|O*JP)@%$(tU>#d{Yj! zF7vPVZRr2A|2Y5Z#P$BJ>-+oG)c-K-0cU;IhV+uO_05W%Rqr&-+>m+DNwN-hy(nva za6|fyzVGbRwDlwQuW3|W>>PBQ5&N$QU0>p?x7Ik{{nqP+16M2zp&uu;UQ=uzxT2B0 zGO%VX##LyOy&2E1t=#m({!VD2zUhaZ`_M`wS3h(+YB{lg@%}(@+avz2>4$v? z_aWRyxP45xzwp}rn{bZzU$<@y9tipFelYuRDDB3>nAL7dJ7Ra8^gr4m7-{!@k4XaA56DxMTU$UV%dBd3E zSH84P`S9oB&DMt74kVhfTDhxH+(^Cm|IkR?8aGmtFj9B^Z;jMMl+WI_)e| zZiRC;Kk>!EYeVZc9S9_yT^w4y{?pL9wBq)~$7zn*{AqQ`&XSKxc6?r4vb*G+k^`Sw zC!V~^xhc1}b4g{Z4J99bnHFfd_d4|8jKlVM=y8WCAIv&zzl`>oY`Tr*VyTw>$i>8gX(fGr82*5-#OnOf>-}4tQu5vBDI3z(9Qf2%5?bf1@*S{}Zaa{a zbmIO4m@D7<^uwQ%H~08FZR0bajX3yQms>w~R=xPC^_2NemzmrB_9IxllDpu~BT!6^ ztqCUBHw>3XPKTWCkQ_UhhwB2z4&8-oLEkPcY|cqdM=-<};9EZ&U&0tfz(9t7Skp?v zA6SDBA74u0jA*vRs1o>U3?~%0h!#Q#_u`y>e}F%3}+nZbMT+m;mlmhT4|yw_n;-*NOmaNIkHn(7buuZ9j4%6q5A z^!x5WcqrRcR9YewO+%eSNwAl41O9{xGwH`U(o4^?LPa{GKZWls2^A%|83?63hFph= znz&+e%Db==Dmu;;)6z>9SfQ>->BdkKRMZ^^PP`F++CXK>h6|QcVKFasQi#1HWg7m3 zPHyCtZ#?bwlITzAM)4Ghp_DICmQZhr$tmYDFQ-aOOW8~DG>J`8GMKiH#HJ~8d7{1& zTcq&SHlcnJ!{$xvR>%$w3Hfo3lon{!&>4yJv(}fh4u&?O=;U5#r<}*&;ih1aeJR^0 zkCJ?e&q}-$=Wc@7rpT?W48Fi-r5!pqG?~^-eNW1upVpT$XQe^63j8VmLHmWu8cj2y zp_IlHr?g^aIk|WM74Xw=;ynDJ(-{K(B@i<0v^Sa6P+jOAh$+{y#pk8d&lA-$oAbRB z!4i92+H1(`jL_dgxyWOBX_XavBtr?(ORKHWqh3!)FP(3Nwn_@6%w)d)-iTw=mz$jO zB2V?0#MJcCDbuXb>k%}d$KT)&u-0r+y;r;Or>UTTzY#7^n>u_-I`s!r4eA`0-D3eXcGO0Y}k z?Va)yO}&}k)uip4vYg^u=>v>7ARRwPX@%aEsp6CZ*5vz2J2b_|R{9|E8&lqqDchOJ zk23lLzTB}X{Tca_+2Ro6u~}ewUmkl;`-ee=yk?DKqv_K(3bv{iceRFQ1JkN_?oO3gJVrae>J}BopreEM|l5Els z&EboZLW{llBXc%UUgB%S%0V^fG^QN!CH&pwXF?9gRp>TfCWn%fyVIA$CqJRveHk1h zPVURToI^b0UB2X2ID?bBCy?_UP5jlDHW@{8a`y&u{ze-Q_!2vs7+(cY{~QW#BYlq8 zagAg|H4-2C2K+k_p^5zq>YW`lE-F=Cd-8opu03|!SR|xx3Wb^d*$d5J#`M8)$>mNn zX2NHz#@2RoK2K}=gY(#}q&fH9sk9igG)ZS@d;PDfVA3ATDj2xnx$ z1Adxsx*B#U`}zaX-*-E3Fr zLSMpZXqp_pFe$Xm*OaRnO&w;^i+vexJNk2;VSz63r7^NEH(ale@{zxr;Hbbxk%Gn>mD@+NU?p-^r(jIAv=Z4k z97vLz9}F$^IUhlB9A}--b-pAv?r{mMiH*J_p4C17H(sKqR`6{^u>*dpTG*ThOz%bq z`vsbSpVt)ljXdf#Z1Ug__%rY~k$tciJSGD^t0k`xLj_I_XFl6*`3ftiv(s{r5gosO z6vA;mwg|~u?M1EvHm@BUE%OEWLrtysBVK*@uc&k@3}@NluaN+D_d(U@YG3X&#Io%+ zZnDG$w!`0N3NK^a*8FL&`qsCiik7yXg=81BZVC00);B@FxOH&^EQXe?TY~W zR16wxY@&+QujQrpffTJ9vcy!%<65lz^%OCT?zj=!R3k2ZOaKwd>1 zced=&Su9WYCMX|V-ql8T9ChzN=8r$*tv0$g)bXVfli>2UI!HUl*yD>E-lpy;qsw7D zemVZf9N4U!Q)t;^8~=j5eAvvg`0{k(YBt%P_b z+zCU`hepGl#ikm>X8EcatC8Qw+Xk0+Caclay$ktuIII0i{J9hY$cHR835#+A})zZr2qjKlHxbbTc_xxylDXkOu z_Re47Zi&Xf$7iZ>IpSUh*TK|@l(#^!0nR#+)66sQVEo~*cQpPU20Gd3Zf}Jx>kYV0 zKOoAN@O)0;a|l^&aCZU6h14oYMcjUn`oPKHC-5{f8(j7qjZaCF!7~woUk)?|&x5Cu z0u9~(&vkHoMT6Cu2Jy(6IZH;5cmJlb?+>*z_-jms%$~8r@AN(GS=kNGJ8(rz#rP&` zze4j19DWd#7O4-K=i&A^JLBC3*3#Rem%^Dm9S=_)Tz(fMHI_;s6~oCACqV4F!r7DT z48A=omalUV?JPKBsR|x`DKDRKjipN=T@0sEcJtB8zdhmXnRZ4^18X-S>N+@M?M--I zhb!{p8;f5+^BJ5h4)M{;zr*3|i|mZ&V9_+|e-P^koTMbnz`g zJ3(V@G%a3fXXIeoGZuRz4Zmz>ERKR_1O>M1G(;nX`gFJlPMlI2V1 zl3?oUcEq?9&gALu@H|R^dHNKdf5GK5O?;lXf1F@-p{0v(3F=u&Z->qbXDl5L55M1L zERBX|BwRkzn7l28v;+>FjALL0EH<(R(c-nf#wK6!3aQTd{ zd|BPQV7~A@m(bdN7Dk;ObE^s|7E*#xM4^v_t`vq*=(rvxeE&#Drht>D+wD>_lbqD! zQpW|;?a{V*LvFU^r1nZWCF$g(!8p5?Dk1!rM2>-9H%9*Dv?vAZ`~g8TBKN3*mzLtHh%l) zNNo%3KFMA?u|(;1hTS)KLw|EB+%bD$gEM`>NBd(@&(rBmyGqv%x@fgYcYM4KR|iSx zB^fpg&_2l?haD5FWbq|YvX1dOtU@jA!pzb3*8YKU!3jxcC5<;#i_7{#FF*OThT+jI zrosoE3t_%XG%e4J)B!hjAyZ>6b901Y9*t+tp;+CH(PGvpKs~!P%(@DrPJ5t=Saj1G zW;AdLcdkGAnu6E>z4Su zZi%)UGPvcK47z2#4-+tgFEI%V+$OlB9-Yy8#1po`qvFRpf=T0L!f_mW@z;lcIQTTw z$oQ+x{-|CudNBg8gk#N+E8!C057t?2BX>bKlk1Un7BR_Wb76gip2@DB+cR$%{i+r9 zCCI@waLCt+dV0dBNgLPE0Jl{fYe{{C9zOAco}baOP%zs%n+Tc0E~<~vlj!PM3Nfpz{K2*nN~|&1B2F{jvxw1fCP(yKX7po;D~-OkK0?oWSHB6^0>^WZ ztpC_KD5()v#Pz{ZULTBB9ExR*0Ct~z4jzj@^5GK~=72w7Lyv*%cbq_g?dDS`Z|fP> zFbzwEgMW?*Gj-2Ulg@2&BeFGbg+tM|)IS3conuv95TWN2S6CXMM?$?3{IH0bhsZX@ ztCmFQX<_se2>$kmV=b^F^z?NFUxXgsH6p}`EP!Vb97Z(3E`mDkOMV20np$2T?9n1Z zA*Sf=Dt?K^=++`afzGk!EipoSpAjyI(8Eh}ge;BFGu0L9BlIkT!|X*|;_8<~=vfPw zXsy~-A7mEVMksHEYhNnO|?!cNZ%RGf>TbFA~1 zMB;=CjIh-WSsI~7LcI~*hXT_zvCoaPB=QA3`;C4y@r%({+Yx#a(VrZv+83dRKTrX| ziO|FQ*$_S-wZLkd>zJX&&rjOcB*GnaXZC`3xY3R#cp-}cPSBYiLeC0USQ?>6LcJ00 zhXOr>*zQJJ5~1gLqn|+RHhT0BdiJ}5FG3IRh)oaSAm=iKb9Y7+!io+%$joC9uS? zi)N3F$0~o^;H+|t(9@^Jphtpj2ImqekeqPGBa&YUfesC@wVs}b;4n9Atq)>kQFte+ zC~6U*z(MH7=<1F=t}|%N;@EhD;W)vG8+_;_vB6hm8(}ZfBVPo^9D0&J!V%{VzO!P3 z4+~#x@GV?w1|P?pV=cTO;teY1grkSfv|60tL@2CqLws@L3av)%7C5vT;f^b`T5McR zij6C@T5MdQ)nelct>z6T%x9Nij^o-GTM*Aa4IPdSB_=qkm}PHtIaVE(cPQOKRkt)k z&k{ItqO+}W-uN;pyb%_6POg<4Yqai-Ih@oRa$NF%=Ro6PU1_j%aMps6zFrOE zN|V!;rj7!fg2lru5?7wST;G{dOpJEKTefM%J11^3q6e($@O(#&#>uAV#}5LI1vU*! zN4i%l=Mc;o)xXmYvCN)xRFjNEBGeASNsH7J0t{1 zfB+2%$d*6?0%C-)HTw>Vh=vftq9lPVvdAW`I4(dyAuxtf$I)?j9Cchq+#LnQeMK3@ zaYS6eZKCM-Ue~Fsx*LSYdA{d;zVG?o-&?<&{-66kYn`>K(p@*6ahOj^I?RQi8{(ipqMCad^76K{G|Np|70rM%j}EbT8OfQ&ig+^&Rpper-Ncwou$!Qb z_SR%}2L}z)c@uzsj{j9~$eLrw?T}uP8yAjIv;aTYnl|z^*G$Li8O0pjCM>q{?Qj8W zg;mh0f!-(Jur;$uTf;G=ck2dvyD(pCCeZ^9*Uj#=)<9QJ6u~h?eqLnJ_F4H2{J##@ zO{}QfS9|Lv1K1B-zPK%*#%wyO*>=<6R4sbhgs2u9>M4bwTJ*kRLS_LBSrb*8s+!;HWD0H<1`vN`Wb%kx6!Jeov+DTqdK#OKG2a4js{nYIW zAfkbX!=FcVHlM{_U<0FZiPPcYtYx^n$0|wT9JmB2umgG99!CYId=E5WlDTxUCWfgM7vy1>O*tEkIrpujaO4wq#{L4hk6b}?K^q7?Q4n-`TL(0&L* zm6lss4HS5#lpsa69a-RmxKRy4X4|?=H|DZK8uaT17~Uu zkG#pd5-wm>bL`T~Z&qM_5cP0au%?o1Bos0hSIFkVcq|&s$QVKNuQ4O=EP_qv1$p&B zjw(7*2Tvw>lf4!W(TE%1(1`wE4ceUomtORQKe!+s@Y>roy>l4RIM@*b+U;*m0(pc1c+PU(y)HV z)QWw;8a;1!>>MwqdDBHHBaWFfs`4ZfUr=jcGKFpD&^2Ij3QLV$c$|IT%E>+Z>Uhg-0%^ zL7e%-8U&G#U|g;H`2@oE!)02FR=B5=_|s3V7p-*tML8WB7|Kl_F;>OISRIYQQ10xA zu{hor$Pq&mg{@o@h{oWkV9%kR zF{LbuDTSdc+!!&XEQ%?Gp;x*wVoF&QQ%bboPE-o}ZJ+6tMJFhQp}fLJO;1otwBJtD zV(d5G@1D5D7|Ki06So)|-5fR_r@IsK&#V9!6QJ#9%O!Q2s;xMsH915J{aad4| zg43HFo)DSH4HP+tk&jorH>G1@c{4duyf=v>WpND9B}C?KWID%Gk>h|4vApxA$j*@zWJw^6AWxL0vE*!H+ckt0N+F$MD4 zPRC@#o(>nAjS1p^sm8+vaQD%#a|6AMi+IGWXo!~+h%@(dG)1rbvDZVvfB)c$JQ}k( z6rGJSQhD6nK#^mVk;_o`i-(*RG4*r5U3j&*7m7*FuMql?d<040b zk0TZ0)i2I0eET8B+-$|!Pe4H>cG;M#4sRy%N-vT@Ok8ha=QWJClE%ihZ031PVF^Z| zCyQRL2_`0$C%zImUR-a}Fg1v|ru5=kcCydC%8qU1i1O!`-qD0yq3L3JJZMvqX_S%P zi7Jo2T#x3&1a6|}FtKx>bl0OuPF9REa+74)jOE6RJo!T2w)aItoEWD99j?S8*NNUW z23scDd$GwP>zQSH8N@bH^m~diL*5>ZVz|M?j2?VpJfe(LJLXG?(a90Cy}c2UY_RbSu!yhm1iSD4hxR&j0z%kvFV0PrUj$UsPOiU_KgA-i6d%4EO^{()E z&fXRuJD=msrp-M#rvKvXg-}rW?<^kCxWBx3Fi*Oe!V-+)_G6SbV^R6gcX%sGb02C7=N(z_w}bPR1W(T?Kz9xt zr-FBIa-S==mFwEU2OcYPYZHul69Cxe8K|dV#Ifi=&fN;;SEWlxeFGSRfoDP?ccZS%y|{Hp_VrSth(rvHw-tCv;(7xP`XVD`*; zrKQKzy?K1`&CIR3gNW4km(sfb!`;T{=IU6x$%xpauQr!vwYpBvFC4 z9N@DsFvFR+HWY{pI=u@sng>#Xc3vRKS$2IO0VfhNXW!EA3$%AGY+?tT=FRD9G&pnca)fz&p=5yNrTHOUM14BCi+v_CGkV-kOr5|emM)o~IZ!7sWaiGNjv zz6hi^C80vrEPJk#0FhNo2xikWA|Jkd_?+b|?SwjnEeOQ5479TCU?`Y}Ow(-Sm>);*A|iES^U62cUGnl0YexGsp6fK5L&4^))xqN zXyI0~6~dP>)83{%8MDdg!u8JA$Tit%RReim4Ql3GxOz0lR{(FE=$Q*e&vbg>$qzIM zI!o`MpOc_qrtLJd3s+$lNr_*mh=6IDc|`-tB(Vfo7@D zxZ3rLed2Y3bMuMHe)WW9-|@3iXQq|&rhA5_PKCjo=7FXhbHPEFe$Cr;YzJ>IcZMNU|8qyIEU;9kK0r`5|*t4OFKkO3Tc1mKS=7ywuFPV{BCtS_azKSnp71 zn^4DgX7Ni1rc0R?Xwx%Th_I+CHPEKlF{-A4Hu*-C*0eCh#kX?{R0^x^Ypb}7I(OU8 zX=O%zhB?`5vA#8}S&N9ys2aR3f@}D)(WsfXm6!qOyprVY1}%cl4K>&e3b2)Qz*f>s zTglr=-fn=jx7WB^iJSQ8*u-}oFY&I}#DA*cR?^fd4HY`wLLpXdNggZhc6By6A{$lA zXXjxzVV6Od*Znw3o(gsz)3R*5bhB8S7I_3aN3!!2miPp01m?^iTx~7~ezHO>0_~tl z8to+IIkmhV=+GiP6M128j|&dcw#$8DnQ6PD_T8rvy~e`6dsppow$5FNUSr|p9;%Jq zckho){OIu#|2a1CbG0YlcXPP!h6`|dX5U@LQ$L{&VJF;o(Nf%Z*;J8z_m8IaUV_SY zPS$mgv;Km@KrPpjLVmE>@&oy3$3d7RrV%;ZO%tbtoK(9-i}Y4(WoM@o3Z$F_&-Rs} zkh5bor92MTZ+s!MBcr35OdlQS*cM%|pecI0X|_8ATtBtQh^L1c#EXWQe#RvrTDeu8 z>GU}qF6dN5Y1%dqgZ=fDyi9PuT~!zu1ZASrBrhLVSj87Z=Z+gDd#*;-!^~$||hl%8KH$r3-3`ORDBoTX@53 z@wmZLM;4DCJbu*puvNUIw5GCrHZGS-YRatQsy_X#>Z;NqW0|me!Muu+g~hXL=UTND z6w2m=_yR7xUT1Fgg5`)lcVP+gEXGS~YkC(HBc!aVs-iMl$dqYAhYp`I#VVa&R(hUQ zTt3??rmSQR#j1s66)Jk@fSJ>(%c`npmM$zQFRAL4KXYzn)p@;V4jngT)Rf|rUCtaf zW#Y_YC`$PPw9A6>MYUCB#f$JR z-AHpz88u^g@wib_(6&QITE!K3)$d#jndkRq?szHh9JH(oS0(Uvu7#Bq^Frq1=msvS z#vN&SnQ8js;_C3IvBS|*bE>UHqwp#Kd=#K^uGZ^poc@BP*5dq=SzhJbxz%N0S$SF2 zyt0bYW!9nzXrxGOrw*SowKzO@)Yxg0hwHBEgm=X~kAE9xTCBRP)NQ(Drg3q1i`J=_ zW0jQR^#S1xo8IS00BC_?m1ST zyC}D`vZAJ{q_pNV^omuy=;WA5ICl8>5txg^Cr_R*8KY%UZB4!l^e>tS4TUM=HB|ZR z=xixP#od-KH!Y9ZSNyK=Q@sEK%iLXC#q&za%S+5U0UsBR!CW|^quNZq+2}r$ zj9cu53#yT}oD;CPc-mMDeo%{5_4y01BrGX4=j_#<&sz{BGLKM`vXTnC8BEEF&&P^^ zQDBA@S1_EKJ7;;m`Bp`3`NT@3=3K@EUr;><6=2X{^Eo6sBL+_%F>T!N@l(|o#q+h4 znZn%_0#Wkae9BRxImtPdwdfS9c08)Fm1SjS0I2a6l$D`a^kd1w z=(?<}RqJt{GJ^r)()#J$EyhQ(aj+A1fbPXwfkCJZp%2 zQJ16k6bIez=nSkd zb#}YKYynm=vRG7Bx?t{tvN>*dmANl`cXv`uP(0TvU5ehXE@Rhm-!OZL+jb=jIlvi) zR>TxE?Nd=+vJhv7yjh%uO>sb|3s=*r=HVoE(a>N#pd79Tlp$=NrDfICl~vWD{<%jz ztL*y!bn)dk!7S@19Ju3O(Ih$LsCQQL;p~tmITt5f5`SsjWx>k>>-<+Zzw%ve4{5T- zb}sTIHpv-+UsYR!d*h>ok4Y`NE4+bz!*j=3!IZdh33xAEGk+nym*8Suc9AgjMYsQLrY8dkr8X*oI9cCOAuE22F9%r<&B=8fR7am!A=VC|x8v^kr_Ht{bae-FZV{}A~N1cnZ z1LC9Nlj2{*m&Dh__rwF@5iuTX8SB?k%p);23dFu7&ZS7A$~3WPm&$1={(ar4U#vD_0s=V@~z^X()0C!tnZ`Z z6VmUN{Id9l^naE7ckvVHzmfc%_%G@4@*$HyUMl3a3kla&atE=q^!buc76(W_T=FP! zy!2;EK3kkEeYxbt;`!2FDESg`v$$2fRlGxdMBFL9B)%%{7e5le5x*1TaY@4VO%~gT z?Zq4t^QDWJPaCYt*zd~Fh{Y50=UnX8D{T9jF#hXc_zn#SSJR<#0@h{?T@eT1E@dFa+K9>Bc z_)ik~{;2SjRLH1Ln%G)wC!QpB7kiP&w}?bOVR5uLi$s2N#By=5cs_}A%f*YNzf9aH z{T34C+$sIN;=|%&;!`Bz?Uwwq_#TOJ_A9(m`X9sqE`V9j1hEN;d@>}r5j&H}r-#@} z3@d!JI7K`|oJk_xEOCMK<>FH5SBY!II)z^+?htPh?-1`1?~{zCkoL_Su!8=gkuyjqCu#ExQjv8ULF zM83mFs!<2E^)>tUtFFWVp}xC^f1g6&6nU%ekaLY#eDH(ak9v-v$MWuizVWGaiMs=$X~`X z{)OTt;??3t@jlVqA0qx^lAjcx7he=#7vC25iyw)fiHF7SMf0US?RV64#2q60Z@rh}*>*#ovjKh&#pS#9iV(@k8-b z@sQ}}{Uy#XUgVb*Df7#UWH&KS>?fWo4iiU;eDO5X%@Y@i{L&)zE5!@NE5xhC>%?v1 ze(@vmbMZ^@Cy_rNC8j*jp?Vi^LJ)7;&mNT`U$$#dF09 zafx_=xK_MWyh_|4ZWU>cf%Ushyi2@ad`Ns;d|G@_d_{a)+$(-0ej*+gzY%{F`FabM z-&9N&v&4{ilGt5*MBFKw=L5)Rw`9IRg89-s1^GA8JU4)RNb=X>5s_~VXMDaCf#h%g z$#gM842d~nu88+Vn)m}mzA}O7hl``cN#Zndwm4U;7MF+@i%{9s^PC0w+$8x9(L8s7{xQiV9X^8l=8 zg=n5jL0%?#jd-zmmAFBy7q1t8C*CIBCq5`XCO#?d68DI2itmaaiXV%I#c#xaiM-Y` z{Vt}6&BaWygV;&T6AQ#s#X;goajZB+JVTr%&JoMS#o{V)t$2-CC+-k$5^opp7HKtv z=k=)gjQG6xs`#e3PyA3kD4OSe$fr^A52C~8Y|zJvsbX`nt=K`N=^n<<6Z?uZE<*iK zafCQgoGP9zmWbzy6=JQpOk69P=Z(n!D#;tfdhvSkcj9g0ed2@Sv*HWlE8-jCUh%J@ zc^-*!Ka>2eNV5(+UkBIZrv1cJkp?=bZzHxByNEr+Q^i5z2+=&pMEc2+PZw#rgZVBK z*N7L3SBmC&CE{Ht**v#|e1qhh#XH1%#6O9TiqDA8i!>9$@_!J`^GL{Xd>#ij5zX^S z$gL!|70q)>=*@FVu$T0GM7}wj`4ov0#3|wo@f^`SuSEO>k{5|J;tFw%c#T*mZW9~C zo5kOY<~bztKOp(AXr4zx|AS-;_hhVhoR}mw6I+Vrxg_G5=aOJo>2t+CVt;XvI8>Y= zo+H+Z%fvO}#o{)xLA+V~y?C#9zxb&5xcHp7OEk|VQSUb;zb~5Sl+b@7`E&7G@q5wc zb34StSEmhWMuzeP(L8U2e2(NYae-JPn&*y)w_5T=;+5ih@jB5wk3{^NCI4PD&m*C~ zU-Dz(lcISpiSU;szahRO?iW824~yT3<~b$OTY6rXBsLXWimgTS+!FE4b4xH!`U3GZ zaj-Z_94Af{r;Ej6sd()3%v$M}iEG4*#b1fnh&1uT{(4?~S$ti5PuwSdCLR{~FLS2% zi^*cD*g@!v0TFGn0OU2FNR`Ivut>WF{ec~hHPVqT$ zm-v?GJ-7T&^2Z|0A@Tf^#Fk=fk(N#v-bu_A^TpG|!Qwb^k~m%To?FhByila+CFXCQ zPlEN5uNQ9YH5#JX-7rzw06Mq!(n=O-nyx3Gs z7ip`6i|>j1 z#D9uM#AbZXh;%JQn$V(ria1ytE{+u^if4#tiB;nH;#J}Xaf`TJ{Db&__=fn7xL^E8 z{7gJ7Hi|!p`0bpjf4mqHbHpNXm^en9Aks7#&%Z)EUtBI;C|)97DXtfPC*CGLAwDD0 z%oy`OBDR7d1$Amuf$u$JH!{nmqeOaV|i&}PqDW+Nt`BDi%Z1K;#Tni@nP|8aj$qp z{7Gz!FI2Jo4&oqjs8}MFi5H2Ni8Ket^nVo(iC>Ejz7WRnII*SJTI?$3iiKj4I8K}- z&JyQ{i^W=Tt$3-pS==h#BHk`OEIuag68DIE#lMP&#IHrCjm}SODYh27in(H;SR_sm zr--w~xnixjOuSsYQl#lUw(q;*C*tSgkD`r#kT71V*j&sOPZIlz1H=*H7;%Ppj(DC} zDXtRNir0vB;tk@>;vdC7iO-17i*JhWiXV%gibuqs#3ryg$n$I_b`U#>eZ>Ca2yu)! zU7RVNCsvB9#I@oEakF@nc#B9oh^)^`;v3>S;(qZX@iXzT*eL!WI_=#2;zSx%Wd5DS zTrpofMLbO$CXN&*h*QKF;yEHMG&27S#I@q3;#J}Xaf`TJyixp}Nb`=&?*;Ky@lEjq z@o(ZM;^*Qw;&&o#Lo&Z?vAft)>?fWo4i!g;ZU5GBjsByJaX zh_{Hhi?mD0_)mzmNlE!#@gwmQ@v!)fm>6>7Hxb*5*NwMZL@4BsUFR=ibwTKtRnp14o^ zhj>s-&vEn15c`RzilyQ_@fxvCq=`e;=N9o#;-li<#RFnmCpUfzk+uw(zMDvMhLlei zY0QxFTCq;NPNelhhTksIfFb3#MEo1Z^5K6AxZO2+z|b$^alMi8*vt@@S%%o23_~KS zZ{%KLAF;n!D2^1ziW9}D;w*8FIA2^SE)`dZYs8Di_2MRRi@06fA>Jh3E#4z#IHsEn1Jo?7vsfbF;k?i7{&{UIbtudkJw)<6i13<#fjon zah5noW96A2RprgD##?@<$UDvt zBdk39*f4KS+3ebR?yqv>FPS|XKR1jGmarQB112c*zhV;a6gLB{lfH;q2NPWc!~uaJk7Yvp7$9^l=gSMDv-W13nqgamAm- zV;GN<;5es#DP9l6Ikwzg=qK;+%QG7E@-`||v@JVRhZh!xjDI0nMbdwL7Un$q8@H|I zS2xU$^*SBSO9QXf7WW0oUS(s#I4@)4b;b4EzdA96dw5}UAjX#KKNs)847ug9Jg?j( z@Ox?CwN4spSs{9Kcwy|k*!(tK;jUdg5B!TKk{{GZxliYe>7-T#n_YNrHHao33=*mHDB$Bl+C|KhyMr1K*AF1d!*!gX>ys{kEfisnD^0cqA67-){KP?TY|& zEJA*nAiX(2`6k2*L5ar?=C@8Pm-(~Im|x3TeN<{roq=usGqQDEjIz7Zq*2A~U$Lyxw=%ZZfI9Ziw~e zZ5NHHFW*wIx!W+`ux+igKlxkr>2+4Fb?CA+1>35Jb*t;WEmT+h$@NZloptE-HQnoX zAMma79Zt1^_1nWY98R^Z94p)2WYz6GV6B_jm^w3g!I1En@KZ+u*=@t^!!IB3^_ke1 z+~d}87&;$f#E-o@{Nxe;I;*2^5?q2UZc#$)? zZg73kR^Q<@L+w-TgBRIOw}K6)ZyWZO)!jPO_PQ6t_4mx0e@3G}>z43N$ac3E!-;$PY~J1Y8rr7Mx|(hvOaeYB0w>qwc(Rqw9LN8ecbg z+qliiy}Q++C!9Xlp0#Np+GTHJ5gY5nW4C43 zJsvI!4-Px~-fK*~JMl2SMUai2%g6Yb_kLq)uicGVYXae%Ex~I?hx5aChyR4pV6BS} zr-gm>p@#TtpE%;!yAOoyy$6EL`e3Bztbg{1GkouX_;nq&zu%Z_C2fA;h|{d;ruPrn zS;%wv&LeT_60dD?ZR=~_Y4p#^xwi9$HXD;SrEY4zDQna21HpBB4>Vc2_dw!s-?q^D zokxu@@Q$NU)%Zm zy$3Q8!?95k&Y@lQvqys2?ZbNyG|PVGND|v+cvd()jC%ITM%((=+o$e6(AmE8aB7qI z@PpwF;n%|1b*sOgao45caa+(L**s&b%gQ|`ZL!x++}>@=ws6rl>&)!!t>#;sZVl)B z`qc0Z$laQ^C;a%4z-^&lTkFAjr-gkDkE5L?gm;9uBE(w9If_!VN7tVjz7u`0C2Vz@ zyr=)BqWV)dpNjd>f8Jz_NZ+pqY-0K;Te{Wv-Bh^gv~V_ZA22U&``YQd8{fP8v`yBQ z(DuCt`l4kDZ^P)FH+swC7^#?3x7l6T`lC$lZ-sOA45=Gd7p@ywSG4VnEf_ml-L?(i zymNZowxL)#hV(%{-{brB2$VeXw!H_2%|oeu_8thYv$i4E+nz+uPhf8R87=ZwxX<

    tZ(6#f2#guACp-^fdavD|B7Vs`%o3tcNo(Hu_*5C1!_%+b5fq z6YJs3(etyyQ^HT69a@Jwq1}Dk@xC17%yrSX>7|!3cCwpnORi5o=mdR#nAzw|e7_Of ziKrhCyhQ~&-6`aLOXQbR+i((;oigv_}9s|G(89Th$`IZT6{q!fcIBW}ooY zz4UTH{jP(_)#%;y-3NNCi$^~ubC2-n?6EqxnvXpqbSqXHjv~8oT)5SqylZziK7x6g zw+`!9GWLj&-Qx+&jB(+lJ-rb26vBGh+$Att)kcYEA+}CpT|D-Q__}256F&{Se)vT% zTcOgsAN}~yHDl_VwebxbvvJ^u*j2ash9yS!)H6OT3m0IHhj#wqAKkZ2uKU}EdmDGH znfQFsR(oUy-=q|`f&PtBG~EGd^-K7pngvO^z%%5{|uJG zuh#lIwt60_fPW7@gO?$(?TkmQ0zI0rLgttLfhyyVn~Bh1nVo?vGuRRg-0bkT-wFId zbKsWb&!J3s2ss9BO{d;U?1c}0Yd?wc@e}>{z>NvhAg7GON8q<{mq6{ywous< z95JHbaz4ko1#WYg)cKs5-__>N2y5aG_-mo_+3^oR+mwFiR>X~KX&NfE1r(WaJ>$Ou zQ}~|VxcqebQAQfx5ENIS68$NuIFY!5B)0fH2EHPv?!#6ps zcsp)%{HLr{B6>A$Od|bk_4C;VV-qMk*=y{S{tO;(P7JayWgX>7k}vjIiRCDpZ#Xum z+}>(di_+HHac9Sm#2L8leNHp_nR_uJ#uW!Iar-od4?E&Y62_a*_!L$wZgx91mXm$C zjYeh0iRU1gP9+5Vb0DPKsgI+o@o}~B8zH9DvB%F(qn`y0W;K_11tBMny40so-u$>f z#wVeUX~m1Ixci$aL0WN@759KQ64Hv7SaA$70;e) z#XX!h*OZ)^Qo_iOC~am+3QzG#(@MVVtdu(#`gGghqw2owP)Y^6=GnI9OVimoDR;2e z&!>EELc65!9RP7JB(#9mm)#=`?;o+^UQ|K7AmRjG(h2m3h%?xuatl+QVpgxFwJ~Xn zQl?RSEv>r|ho<2LV^-Xo%4%3jM|S!&Uo~@H{0rQ>hQ>Cnod2Eb%zND+nDflxQ89vX~+?C@q{=kCg`P#X1a>fh} zwFSO-mgCD#%}A$wt}otv0XMsO#(c&v_ww(R!H1r46~315;m*{T-6vx!^IznJ_s@8Z zoSKupFOYF7^SH~G*v!QEG=TQ!RB$`#CB%;DBqOr%5NQSK z6!71T2+fUw2oBJgsQVGg>(6&hB&OrAjYdLxzP-h){v3s7GGqDRygb#DQM-59jP32# zTW~U&&mptqxNJNAGQ`L*Yj-C*jRNL)#x#V+b+$D^{2BbIOx#JfMo2tL~Y>#@qn6EjW)<1Y8Lt}|7gp7DF0 zW~GcA=gOyha)#CFP~28u+=WnNT*fxt?rTGVZT>LZ?AN}`4Mv6mKCbE%Ojd2JM0O4* zlH}Hh;#T>bXP{`qRVQw#KP){6G)p}(MgHoA5>2S2W4*4Tk{NEg=~ zHAuL|POn3}rhBNNsgZANFY`UO(t^;j-7FR`$TOFOVO9 zwaGULW%K7y_8>Pu$k$WHSKin~M)wTlC*X2k#)my5m38?9-jAqzgSw$c$6s60Vogpv zeAvTMSq6U*$t$Z)i9lB>WrvOGQk-roTn>LAXOA#Cem8$JT+YX6 zb9+Q4OXd4H_|A?_)wSi8J<_ylCGH#e9*fTBTJ|VY-%jVj*MhCX?>Cb`@_?{(%lOglP_(W~%qcRpNB6QgTO9e=xh zA9byat}AsHrsKB?a3|fsRvgou-MTtw4x44XsWiWU_y}Ci0;6lev2b^Dd@&U+r^4vk zP&X1!ln21&R2y9f>i!J*dbmzYds+4blihWAP`nbZ)6#sX(iv+UzDjl~T&JZ4P-RfX zZC~iCl1AZN{0c!o2AU!gb-{E*;jbIw6gS|;jnA-?lH8;=q9vppl~bZ^ zk4mRLse?5ty(b1ia{5v6@!peY$^B7jya*!+(VBKfd<>;@+i4P;e;VS)do^YJW+p}; zT7&c!)=8*l^A`3=$!^�w%APk(j7D>y)9g&6zN-%t&d9(Mpw-*jnc*u}y4xEPgDJ z`L^xjo|DOUP%;~>9o})@WMC4T5;ax&_FWJ!3j;o6JUHtPe*4%+9rNr#ctx;#emtWz zyO~`SypAuz$qvLco-g>o5cFz}3O8LTT_@-wjV4{^SRKZ9Y%a^tb|QMh|~(jFCd@GT!OLeQrZGuAt|B zBOpFKJK=C9jVpL26nLMDtQ%Lb-`wFniTDVPyT-DRprPqGFY z*#yp5W>+gy*4Wq{GjJ!N@y)^Q9cC_RJ`%EzhLLzM%<~z+L^dCR*l-%1^tq|fdeNMu zi{$jP5||arHjabj2IJrG!^)lT&^gwkMGY}RO{}mqR#;(#=BOst38F8YNlp*HRf0u} zm}>MZ{0;O}xI%mbJ!@SdxnU85@?Kgw5F9bv)1{m+uLSUGyB{(v%{t@F{E#Z#Usk7kK@Z7SRp8MfAs8$C1XEjiG zB%;75qwp3Shs#QO_8DP$Y6Cr=!`aphA`e~QSj+tl^i;V*d;>kaGe<~r13i4I10l76 zo-iCn7>eGoel_MX<$71QeRYufjt!Lg`bNaN-P3Vay}>IoYbHTwIw?k|X^0V)#tJKp zkZ0!GM1uRKNlwo&qd%RPVf5$w8|dL11+X08jNsvG1Rx|g+zAhF(_zn*_{iut99lt- zD`4cs2sN?7(pX`I5ehK{G4hBRW?CXSJ+q8{CUL&eW8~4Z(G}tw==r@XBsV++&m(Xc zB!m_T)Cz)@>>pOftOJKuc+(xd{KLwadA?;e2Bsd2IsZA-yk{X?<_cT=Jas#qKxRI zT;)zmTF!H`YwcH#4y%CKbjl;Z8~Veg<9izCVe zbVM$4-D{SeQ2VT24J{EN3l27a2`)_7&Bp`h8}Agtz0BC~=}LO&5QVD^#|ASYxun?E zncjjzHT{zn#cLSqIcYgX>FH3KO3vjC|=g-Wwp^ z3>UCgSp}UM=-mm2Ga-^qw3!6k*s)gFX4xMAfhl^oZlHG}95!KMG8`@qY_kh2boB%; z^a9wE^7A6sd_F6`!Rr8Am+-W>tmF1E+Wz^G_D2k_`B6D<35Rzd((tWTXy*4;(!;eG z`bz<>zsS#9by*_&jQxe^Z>^xG8yuG7w^ju6vl=LH2}OTQ2Y4NW3E^GAFg<&351bl| zUUnv`N3cIl&h(5mT{wkc9~(VA=fJ7;=&gc7c?91cgiBl7ERE}3J;95WfK|iR^R8Q1 z7Y>d?Ce}>iOXHn}elrK!MMDMG4)RmytrghHZh**L7+!A==0J-!^f|MTg7cp0n7!)3 z)m-)17HGQHR2s@45}E07O0zMjix*G`jkh)n3yf!&_DdF}c`&Yv5c3<_?AJaJDs_;F1yv^Gc7T zR@pI_1^*g2Og(~^eOLhrwh`)pD+-(+&l*v9s?0RDu@UXK2iti)98QVgh%xuIRaO>T zopQY!OlVKIW%WK3@u4Yg3c+Czo6H*)$kpo!(@<>rL^$XPj*{49-l##a*C-|#N4%zqx`Lj6!Qm;NpDR+>EJKrs8OD1C;Vw>R5xix?Vo%&>yi`Y4pGL82Pg4dU*#-7O2C{&!=1JB1hL)$*?IkEO;4PApmj6jcD(P_k; zrtm2Q|8;~Y_pPGGt>3g0*Duel)Q7N;=GG9)gxA1mDKwS(;JEcd1G61R!@;{YQs95k zAm(3VR^%BWlAyMcBiasB;Q`DEdN{hDoZ;PmqwT}UZLX=y8N^cKokCn}yk`=0XrFy6 z>4|B#r%aUT#6IIahu9BiV$;KyC}Ok|S!gaS4}_ZV>zF1yD{?|V_vj|_e)RrBa2V|b zN3SU-W*F~-j^C*{&^V2IX5T=%M3d z^5YynbNKlX=WO4~D*k^WmSW;iI#>Us;mwA~2a?w#UiRWX^!n_FS}xJ)2`V6|}#VD6FW=g3Bo zw=}px{j%-qA=rhA0i0xxR=+d1xaRkNFORQHSOGKAoShb|snVi6?0O$#QC{}sD`-!?ne53|(4Ks=kZVuAA_NbE z@cB#j|?R(iH448UZe(Y)s4#HrC{KTQ$eECO@%7pc%4Cf)#TZR|a5K z9&}(g`Z&hqomcFL_1dO2v@eZTNiTJ2%aRH-~nNQS+WKV_Zrb#-5@} zcA#frVW26E7_*spHna{6gTAm=43oq>o;~$m6kEnd>1GDA z-Okl@W_UYS)lD|o$5LnPwaaL`G0GlHp?ZLu48z+^1N+TXk9F1E=#Pd~8%yHsMH5h< z%AJokWkgsLH~L^^Brh*_&n|rPkTgs36bB~3O(Jt*9hptXW3w%C6+zh1Q|by+NhiS| zhl$$pBS(3j7p;(cs^+|VFp9CYY>I(paVmnQV7Fl?H+S=JTSs-{2r(Jay0zOTP2Hw& zYXH0EOzNZ=xK*K|W3)adRgo)4&(~C`52G5NQ>}LDWU^BkXd$E9x zIr;^I4~aVly20SQ$tBnk(<0a$Cy^EC)|sk&g!Y2iD<^AUXkZ|9u4jQhfth*McpP7po>iHPv-K1Kchwz-vrf5t)v}!Lzr{tR18Ie)VUM{AcEvk5hpjy97|xY2^_~WS z%Vp2>^vH6V?plIhi?~=O*V@l%KPn6)4ZGb*pN?e`mcf&pMP|dB{~Wf$q+n_wr7Peh zj&6>MbfH!Hfq|awW_Am7=@sZ1n$g2BZ^nR*T+DmAjfh3R+Rnq_v^IGyDU3C8-;)b& zmpoW04{#g6?txMxI|EJLcflFRf;wAE!^| z&FmlOoC6ufEiMdn#?~K5VM=f3&nsk8XVk>({5kFhk0gt77?T^_Qf_<-C=8^`#-&Bf z&VN+sTrc21-us7g?>{ZF_ZLxo3fq_6*}dX&Hms06d$Tfdlb1bvjMh+K5azzw_>XHO zKFRsc7lMg+p7t%iP@ePZ%8>JsZLH02gW-5un@^?G;ke1;o!2oolbv^Am>$;UuXe4= z`}hz)VtMy}oMrhK)71Y1jm-b|SeN&#%KtZ-llKhC|LkQc-tE%AX<{Bf_3PV*ri*EX zn?~ao_wDV8|JQUp447B{*G$L%&odV9-fvH-tgR|7>lt3Ku%@hPLB+f|r`R6L)ohf;qxKLa!UMOB8ZW4Eh zw~G&nkBKjfZ;F2tzYvXWKa`(_hGKpB%Pul3o-WQ7mx}zd593`eZWA9ApB4F!e8x-U ze-6M5v9oxx$ZrfYe2O?*Tr92;`9=c9YY^`c`OhutcZu(bKZ;3sM9uKlVpp-hI8Uq* z`O`ecH@4?M{``_MfALEin{Z$#n*LHw;~Y&IeOiEPL}rFbuke-nQc6YvW#AI3t8m`36pGf3py zQF3RoyY!w7`2o@!TTF;QTJm^tisGLmdA2xD`YOriix)_LspKofYoxE2e7$(1^mj_W zSA0PFCnOu2OgOI>q<=&Dcfm_dzw@QDLKIBjV%I?~=Snd|mqe;%Cwu z+fAtdx6<={i>5uqL=vur5Z)>q&K#jz(R!=i4(*r;%srQXlykhow3yfUM~HW zB6`S-Uo4x3sHS16m?@h7e`B0?lH66y7f%-X1t`u3vrmKkb_nHSajtl-SR*bK`O^i) zzev16yji?MyhnUctEAJ2v_zjjI)|CTi5uMa4< z6V3h)`Bce6L~}g={W!^!#2Ml_;ym#@k-t-5{^oiCyh5_MZh(A)k5#+9H;!b_)qbO$X}5&JX7o-b`tYMenFk_JR81)BwsCV6zfI4AcyhI^#^#5 zWPTrr`ag@$iZ6)#nh3+q^$GZQ$p=L9Jr(G`m29qGAoC|GOqVD&5nG6@#A9vw=1QM0 z4iE>5zhuj|MDfbRh2kRdSX;gqOMkiO+3?*g`3CW3(X-+E2g&>fl4(Ej8S#1XZE>&o zk@$)DmB?3LF`u7A{_LJ|x|kt`M1J{(;e4F{`LOtu_?-B%__}DW*ASmyF=M)e;um70 zXs+WB?!Yl#oR}&$7u$&K#V%qG@nrE7aflce$BC1~8R9u&nYci#63-XS+t1*?Q1TVx z)#7#HHt`1WX7LX39`ToK`M#)luZVApd&Q5$PsC$w`^NJ+6Jg1sxo(BrN^(b$-%4k^ zT#;`DqdY(yD2@=vh*L#=bDi-^#4@o~Tqdp)uM&SP{zkk-yj}dG_$ToR@fne?0AjhX zitma0M84{V;hs%jzKVvjXVdp5$quiZp-&c5#a5zc)3>waZeqUZ+4LPKnLkEieq%(> zrtfsgGsQA-fmkK-cS=mZQsg_UC|@C7Ep8UKist?R@otuUm&jL7F+G23NbVG$6<-iv z6WMfzBK{=u-6E!*;udkc_*?N-@m}$M@t17(zO8tB#b2`B`-9@)>x!mc z38H7ax25FPVzzja_)E5X`7$7$?`ZKqYrA*3(s?#~FOj@X+$dfvHi$QhzZdTm9}piF zpAw%FUlv~%-xv3b2gJ|BZ$-W#i0A3>J_w8xJsZB6k~@iA#sA&5dzUC*bDxKL9BaGx z8im)1|5@9;k1O5N;)|kZ!}nduABZ1|pNf2M4%_ED(Z~BE$U*U_`$p(nOW#iHBz6@G zM05X$_?`{lq0)~PCyKMgIbylESX?Wb`$gpE+2sAB^pA);#lMKV#n;5Q#1F*3iJyp{ zi{FUfi9X&Ju|32TF->eOwi7#vo-N-3$$iB^;!ts{I8o#~j9A`<;x(dYn|Hh99pdlA z+r;}sb6<#j9+Ui}_`LX{_@?--XzmY@j^7VvJ-!gX5*^-`LGRi0O_khSJl2+Pf%JVv zzK@CNtHle%)#9b%72*bQv$$Q{A>Jz9A>JoGDDD)W5?>Hs5&mKOGJ1+iDH`ALTo2?6uXMK;>qGEVv#sZJk}QQ>C$^Pfjt|&4@v*D_!n`H_?q~x z_<{Jb_^J3$@rdZd3q*N-LD93(n=aY2(c4aPS20&SSv*B75{HRn#0laV;#uNsajsY{ zE*6)HE5u90b>ez)lekT65Pv7$Cf+ALC_XLzMcgC4CcZ0vApS!Td}j)O*~mVMJy6M8^GfvPZFn#GsSu0d1AG=L|i4V6+N53cS!bZ{yr%A zG4V<91@R^E4e=duzxa{(h4__7gBENbzv$TnZYnub%o4N3lf>R)KauZlV}56gb41Su zaINHJ;$`Bm#Es&$;*H|(#6OCE5_gJEi7$(@4;c`-#We z2A&}O6p`Ul6Tg5xXV{HR} zEd8hASE6S#_+OHJ&E5JXiA}`}v5nYK>@4Pr`C@;uP#h|b5XXy?#WTgT#W~`9u~MuS zmy4^!OT={|Uqi@tzE6Ba+$sJ=+$|n!oA|HN|6Tl4JS2W6{wU%{7N$JUHgQwQcq51r;Ej6sd%g{<67yLiEG4*#b1fnhWF+sHZ6cM*Gvy~P3IKyidPMw~33E*@)J`CREM zM80d1_1h-iAl@wACH_HtNc^+-toVZXiui`OSNyB^iTJtb*<}7sGRz8@`uN2ZF->eO zwi8bhyNi5LCeLS*I9;469&5{ak@Pj<1>$P)Qt=A0PP|UsA>Jh3F5WGAHlSaX{Eqm( z_z&@*_@(%*_><`1A16GoM6rq3Qfw`D5Ic!{B`DL47AK3Ri)V`^;sUW;tPz)re4i-u zyGy)Zd`Ns;d|KQk?h)S<-xc?ZABmrdhs8$m2hnNemLDfJ5u1rwVn{qm>@M~bPZfuV zVG)n({zKc3-v1@A-2Lyi4H)^hON_0)1r>8EJ$rutzp)V525p0X|CsOW07uzKql|y8 zn4<$e84v#=Fh?KJ1H*Wn1c%3LzZkCv;v8FU78B~gzXHrL5uaY(R7^yijkrJb4lish z6nHFU6)9lHNcU|vSlaRC68;X@t=CM@O9QX99})PzNbm5%DxmQE4CCCLfpO;@Uf8)% z#Fje}72eqz|I>w@r{k5&ADeq=;I$UzTULl39bVWn$g%mwpNIcHLdX2@7%7t9dicFG z@LKDUALDt47j`8SvH4}j>(?vh zd~ul^so$&cV=ONM%#k|c=&{c-d5|%~!y1NoAt*#G2E^oZC8?0tOufG79udrDsu{g>?nKKQmN@Mrb`uerNP z*aw?Ut?mgP{%L@7Fwx&W9IQ(^XgfC!$^3O-J>J9e$rEbl46~_+$)TcjP~af9M^w68zT|eRak~Q-)h# z)~#{2#1ET3EUR_SCm&Wjd5PhKI_t}8F0#57eYJH>!eP8(bc28Ely-54eaT6OeL<_M zb!f;%*478U!!yh8Fzjyv6{V--l?%o$m(9U_bls=@o{yqaTO2iX#b14_W+ElO5gwQojWth zkPt!wh=>q+O(29WLTC{X5CRA)8bS(*k_3`aR0Kp+Tv0(-ML>fc*M^FUE-JFv8`!(7 zf}rTGhy?}p|2*eDcjhMO?tb_C`?rBJpYy)wJ-ytTIlHmn)P|1^TPp_c?3Xhtr)!SY zCb?wSVQWL$k!D%rO0d`8J@Gx_`%$t79NhKHf#H>L2e!vW4m=ZT@{JQ{yz^m{=uza2 zGG*EQ>q8Dewp_V$2r|nMXx{pWot1bn5cnW<$ncEAfs?{$p&2OWD;GZ;zdC2zt}Z!a za^BkKti9y`+t0an%0B0Y+2jC5x?;ue*U$Sy(;_L z(2~g7)$#SPi{GnDmSGpa>`Ldr_Q2n)U{-L&ZtRT^Ie;If?ty)@4ySFxE?kRk>{a&4 z;hq~3R;H@-im4r`ec;a+V)>znRN z0&D86TY_EN96NqZ=vq5#`+*?~tOG+6-nLF{vGHJh;FT}p{}g}V<;1v^kpshm*XFFr z3Edc69d|Guzs_Q{>5hHl9ylDo`{iXRN0PF-9}Ytb?oK%pgg-dC`{6*>M$nI5W}l2b z5iRO(J{WI*wkz(2;QGgpzxjd3&f1DLOU4MhbRc2tF6?3Wr|`Of*-On@oA>3~#K3`}an?7VU+iE{wd_M{7vGT+ zcVKkbSKxX; z*++Negbxf&oS4%(XXXRh*c-A9_V&#DDR5Tzp91H%I}+F0KIz9@Lk_*xBhb5;v$6}z zx__6I*1+t%X0MA|i}Al9b=VC#v03)i4`c4L*2S+H_xT>KDcM$+LEoKpU*upA>(;6k zeNRj{=-AjS_M7h(TQ^~4$bRG}E6r+$GUf(vY?Slx1CKz56=Gc5Bcay88}0N)If*;5 zLQH++r(ia9ucyw)xeKE^DQ9WU9eekr!f*13+-I*pvxS9KF?cW#8QYxe;#-TYnoU1h zOs~7uuFa9)1iN4JoWVPpFX}iI>1ElSn&X`YpHXrH}qPiphUR_8(A-FL6Ms!wQv6)OKthQL8hu8y?vCAsfPip|ybFAg9?Tq9cuBbt1g4Co<&)Jr`6|IA_ zkDTLjj@!Ept%IW*df=8(+e z1lI7@Zri+`T5s|GJ{fyH-PH!^dq?MV`Mi~Bi;nlU#(s!_lj2NVyZwcTZJF4|Bh|!%LBtM5 z0`2WqHTxPaPTm_|bNAkXIoE&guKNi&fkEr{a3{ZeKTl}sovQ@xhjG%9cpOf+cAz!3 z`Oi2YV;{c)1YrxhyKxQWyoi&hV4tQ#84?Ixg41Q}>9-ID4&TTNj%mt2)WDv8S0TjV z%NN1Zj^~LJ_UaoC3H$g}A_eT@_cG32V*B__hlz7HRH3xgKJ;G#<51Vs@$`?TzI&rW zCKDf=#*}B`D_mh@l{FTNZHyfex(S7{lw2xn76eUjk_`QY{ zL{)Z*&w;}@rW{P+fY+%fz3y@lp=_wlPic%+GGoa7!zwrNEB z_$@=Cky`usMPmE-@xAd#Y#+bBq12JsK7NOhPNdd8evyB>k6#W_Y#Y%&ev_GZY#+b* zOfR;NA9wDF#P;!fA9abu_VJs{vc&fB`+{O@A3y%~W+b+c-!x`admq2ZG5h#Mw2vS6 zp^C)z@w<|3;M>QKJ6=V6`}loI`CskhcOi8_ zB-ZEab&%&fu?c>L-oFcJ({9a%oWBd5=Ewe~$ zAHO?Uqu4%v?=z$SY9BxTRYk{OWSaKzyMpQZ_VJs@#_;XqcZA`-ef;?AkdUMM_?^p2 z`1bM3r0m%8GZZs-AdWFk6%;DzJ2^SuOj|^{P@>A5&u4Zd#Ld5YB zj@{(#Z6BmRB-DiMzJu?@(w#b+p$ zyCGjaZy&!yuwRsRCmP*KgR|_kB=m^(@vB#NA3yv~io1{B3fi{hpXDuTc{4g_VauzK zkGGE>|LpF+;??Y;cYMK$dHDR;x@7P!@LZQ9Z9BxA=@&0nY+i!XbCvFit2H@G&} zqa60hW-q_RkQY!lpSpp@jss-_bs?rV$msY}|2yE?{(>)iu-R$vD|q))$Dhg6{(jBi zO@wPZfV!b(FTYRVy$H_TeQ#KUPjM^wTO`dl&f8YgZdfDgCSyPjhiiMj(KVy)Ey#bP zj+XYGo`vty%cWtuZ{QCudiRbVy!?g{w zMcw@Zf51bR4RB_wyb-3rnRq_!Iv#?yOB<~3a2-E~@H0I7DZB^a$F@if zt`nnlwosmHJK)b7;qaiPJq+AU2M$BD-)q_y_uo7AgLZI7yc-JFi2@2l+3)o|i_sEbG#dsLjK-x8_W-KZU_=Mq_{}_EAVb zyU|$e3=?gNiPo3ff}3JDMC&ww>%;(4>@Ji{n{{QeyF-s3&c=676SYABqq6APFd7JF zsxS$j2^3g`bKxn0OZTE>uo@^nyKxkg!5#zn{;I)kOpM)lG0ZQ5>%wj{-FG*n8n{k0 z&0zOo^_YmzY|Of_wUG(*w39w$3NxT?&>8Iu*NGvWtD$KNsWqJ9UpG2c8Rw@2H_BbYMV zc>t{XGd^t?YT9f(G^fSlQ}3A2a>hT+PG084FNReiKzk0mnl!OQwHG4mT9xk zVYLU&qbene?qDLfAdx5F`6~sc_&Pj0;nEqK@w^l{E+{+Zdl^&Ax09za zMUIPoh_jdRXv0v`ufIZb6i(xcddGw=XZ%7td4m@}H670c;nHctP!qp1G#%m8dsj1- z*_`)U`bzASZ@n4~g4M~iW{oDolS_d$DurhTTsmVjo>wEbI%UUvU&j>Bvr~rQz-!uQ zA>u4xB1~}=JS!3R;($BTyMXYZaZ?&ELofj`91LGI26GKeA zPLMjlsZE(*vMJ3L`0O=yN)Db!n-&-ZtCQi}Hiajbf@xEDX27L0Hsg6Mz&54qnD4Dj z@di6(jhEs=#96>ZOq;^9l7eYdc)ruI5K zJ1H==eemps>%=(zl(w6c(wNdZJEbe0M4Oua0^1{u%#>2Pp+(?KN*&;72iJ*lyp(ua z{37I_)t4##&5q1wO7B2@GHg#`V~AOqobE7zLp-)Vjwk;5Skg;UA7|Fq-IkfK1-H7o&3ekLrYFdpZHDS0)dN;e)$-o(Uvo+T&> z^xf%|{0dlH&Ug$lCBGHY%_g2%0h=OTz~Z<075t(=gVs2wH9fusR*%4$9)AU%mnd-T zd4CItvn!-MH_%`vQ{(x|Pq6=<3Gn=-O(xm|&YZ`rgy&MYPPeoQ{y`EJ?sy`rF)@f-q!1ZTc>bnORh7F z35yfqIx)n=>j|lciD&XK*gF zp7H-;rz~WAp3lsMRW+Px(<|Y*f&$xg13Wjur873;nbGkuG!MaPC8FLjp&OX;-FC{m zUdk`R>UlVm@+a_oM1d)P2hX=~>5R>ICgn&LhB}-^F!k6}fNgb;ozfYv7@6|6fJJjS zlWG<`nG~4n2zYYfIx&t(@f=7~;Z)W;Op5&e3!HtgowC$RwF*|V;Y_N_;JJ(fQ@s(M zb#UokJd^T+&}@QJzjC*cfHi_;ebjEam8o(}JO_(s;5sqH^vlPPJ~Z*nSl@(rNC@AX zS)#w%DM@%g&D8TdSbYm;N)+jdrhzjhY5`AkxO6X`#(H;-b*AH(?=4JmtDQ29DRR7L zAx%=%-N}NyT z5AUt{OzC1fxhJl3O}ih2?LTSH5Yz7AURV<0FcR2Gd;sWvzsfpYYNuSrxNN0Xuxbfs zTB$cYJt?r2PK9SATsmVjp4UoDk+NgH%_c&ZVIFuXPD7k?m3zl8yu${;oA3f*h&$OJM z?Fa?j0{bV>i)T>IUc0$XrPCgnxCwmjCg8@|uQ zXU%qVt)H_Kn75nu3!e32v_#;QxR&4KrqSGFal8sEv6<>B z@dST-th~&T>7LlrZ3C0;phPxW3;b$-(!c~ZB}%IJEjz-ld40=DGal5s6?S5%W7Ims z9+c>H4r|oVPO-DY*AFpSwF&u}I}m=98z#0@_NFtXYX@Dl*`#alw_`CnoM>mJ=Gt3^ zgeHZjB%F~j*|ZXVN+dH?Q932q`~|npJ!2|N3jWbl*JxapFBUsJ0b?%(13H6oa8Qie znLI*n9^Io_#g;xZs`spM@{@t4bQ`flVwx#pmRi9yI3}VhE3ub9!pKxN3huz029Zr4 zwS~mKb)#@5;)5xTqxnUKXb1Y+lC8NiSQqU!p7szJK=RhR34qb>d~hVfYB`P=V!Ts{ zClM)V9kR#O(6=29HiVnn%FT;l^ameIW>}9W+!RkI)}RBhW!9EO^ze>65+u@0xuIuS znVB)7hgo48sbg~)W-`bnymIE6a=I~ckBvbMRzD;+fpCj8nNao{{n>9^6w7`xY-)Yn zrd?@yO&hRQ)(WQ}o1o8z-B#-(n|PlM*1FioD;)cpHY^hTu@4Sd(GRUV2TbE_Ui2|S zmLWsOn!m7yKl9^O5&{#N<+kzWMciJLZv>#hH!q@xzg%eI(8K&ph?j?h{m6LXX4&jK z?k)=p6iFXy-H+>&Os$E=*o^1KHVGjl77JlGGd256vPoCK|1Dg^y3opOyArP=)lfVP zmk?F83Dnd>2KNn28VlI3v1}%NQ0hu(0C^ikHf{AB)EAcrRU+o)*Q1PB(I;p zG7WitVhufEo<~?`YyqBxbFA|NHS}hx42&7c{pQF4;@U1S3P}Oi~|1jjxnOACmc2&C3?ffib-h%oWGcq z$JWvXYbfW|(uHd%pHoX0tf4#|4msDWp{K+Zf@Z(mbQ1<=96H1JuIvN^N%a0pg+h+n8=9>txk4kG1wgZk^ zjgs%v)*4T6I>1YOXS}(b3w$a>V?NX|4_K@T#4tE4e*8_`V%JN|b-jeVE8yjPVG=_y zp2xz`Px1%OkOucu4)0v!9ZzuITpE+hj5?QC?|O-wT<>3iM_e!QF&yKOUm5iT;#b#8gw61t zz#rbqfTJm^+8M548;<=o=%XFQUNJmPVQ|BKWZBj$s@-_XG2Fyp^$EOUI| z#K@$1tYl3hmcU_<5nGIR67jC@)7!AnMHiH}{cmphIkUhc5?z1(@T z5r=)kJY}$Q3Er@UmU!RwGWQK8@zV)j%fo;$7rEBygqwTx9D>Ii_aBXaFZW85_+*0j z;<2wMvEB6&uex65&YLbUAhx<*!dwtrlLmC7a|-vaPcS^K8nRNbr#n_H>W0p=To; zjyMD#d*Fr1Rd<>n?-u6D_l@RPl+omsG*0y z4-T`1HS{ciLw3Y+S3kdoo~w;Mm$=F3D+4w3+~*3x8hSRnLb!$=o*2bj^YCYat=oia zwnO465sLOPU{3k0$%N}2Pc(tUX7Irpdfa2ic%la!_LwDxz&X}}Kn*>)t`MxD=NwlE z*Ob7+d4Q~l`;2!Su>%e@4cE}~ywOkOWcbv0Clg1F_jJNC2Y~Se4>~B=!kXC8XFSiy zS{RelM*}>kV#kvU;Ji^u|B9#_tfBw5s2r}Lp9dty-2}cUKe-#uONV~GOXSMI8v5gL zAn-;v{XBIhaoQ=`gz{y%HbOC9FpnqywN?9U1XKR z&m$T2u|wHK=8(oSHddVEDI11?cjiWO?}O%ZS0G$}n7cacaIR$d@Y@8UfiSx~I}_vz z7#_S6|4&TZp4=UCtIP z^ety7(|rix3WhRWP~)vw<{FrNMTaRuG=;+~T2MoeyJn5!LPdvGB-}Nta-na{s$5{! ztTPdccSJ6Tu307ru3BqM^r<@l_i#PcTd0f)mn!!naSE5JAV)LG!!-d8)5HENkF#FC`a*&84J! z^@w)hDK^(3MD~`WTK7@>WyCD?f3y@qWqgbs%i6-|vc}|U zFKS$zP}^}NTR+ZPdD|kMhEi~wdya>hW&J*`1T`%K4Y2xNG?z^tn zM8KDA)yHk1b78u~m{0P~=L1-(xz;ldx-MoP=fs7>I1ws`y?eQPx-X7-tAeMrh;Pnt z86W=O^B{*>9B%oo+=`P1FU0_ow|Qwth54R_lzHeyxAUNTlk4>|!R5zlq~o4FPb4;( zWUH-uzx~#%h63}9SQpG)9WW|pO^28SpEt)@GN-^|!TbW5dj-RoH52G4ItDEeTRozU zf#R~jjuS)?&BdrlKTptTz{vE#{gIW)(ZqM{Oqy;SqjgiMt2MFA7uT8{aJc)uX%RiU z;cz8K?12mMHfu%=z2CwGtjy@GY2HDphm?8Vh5H|bdlPOV(Hjoeev4}883uLotcKpxO-L>=1r8?;i)!d`Z`|b)ydDi%l`MvLY06^o?%j28$eLJVyc2jn=H5*> zhgi#YvlcF@q31R@++H4w7Ut^+h)67EgIja#nlm5+3YBsdj<-ez!&LGo@r zWAL;o8xApuu|}O~?!)s(@lD&%<6f3!)+~gdXGKisI*{i<^kXuZ4+oeN#IV7!AAW>! zRjTztco2?u3^&sqlav44k9S>!%x!Z)6oy@p|G5VBDKwu5&eg5&)N-o)TAM=l%D=grNScSqZqAEV41akh2l9}hhD zp20+(1Z2bEyvsZ8n=$1b`J=U_f3E6}YItWfp?2N5@jdwn5YReww zNiTYo@b{>D@{7^#o&2)ryz^Z8S0IAdqp|b7?lt#8&tq=1MZ5#B$X`)5Cr@Q4ilf?f*!`A zJsZ#a=;yj<4xI70*ru=v4z|SW{xAw@XzX}vWiY&w*6hx{aM9=#*s(DaN~}ZFgaT)C z%!CprU(|#`4>%NpVE1_irk|(aQCshPJeC|!qu5eW6AJ8|n2Fa{UaDvX{|AHFT{2+S!e=J$!Wk2Kc>4)a*{EziZ;5j!L@tpH2Mb~doXM0P z_hN8D?7VaWX9m|hRufnPXY!%Py)s1Y=;5@15pf-yIcn3xsbtcpXCoZ)CD=zMC9iAH zdT258K|}q)=W6J=G-5({DbD z$W;U}y~PA+vjsWzX~CjCZY(AcJo~1)Zds8RKDlsw@WSTjB)bWYesTj`80RmuFeB;b z@Id3uM5$)MnUf@X7Q>-9EUkMT8(Ri&3dr+Co~`@7rLk<@INPq=c?0czIJEE{fG2J6 z7NhEO;aDc#7FhNhKSu3a(O6AoKss&PcwS+1l zl~-9`T3)4nX?c~8ppz8QYXhjf9KE)H%F7W&G9Pp)T9F+a^~L0vuC_%?@3Up)x5CxK zeciCiLYe)GjwI;(!R+$4;Sw38jaPGO+<`ETO~n<;H3%wIYTV(GOVHIeU~|rb^XEmG z0|~uN(D{Se+>7CA7lj&k#7$)5uZbFXMWMzWhZETqZ^HRgrOdI3K}gW~gV|Mk;A&?| zjXQ`Zvg3Y;8hDvf!_!l=Du?#faQ;*&bGW0X1f4&aGvFq;+L==0&WmxJ7n`C6UZ&LW z1Qr*l1YPY$=N$S5&Yu@$&MOp!pz{ZFs^NH8rzq686L1_SU`o`$D+)F4T#T;8$l+i7 z^Tr+;i~~!nj5l_CBLZG_w-y<8tlPP{UhknJ*)>{Y*a>b&Oz>J7DXQ!A%IsZt`-;y1&y9j-EL;Tdm1%LI=w928XFA+>5~1GO zMA1!pJd-YWL%o4XaV{MC*sD(1&JMVDxNvX6Q(AUTR2dz@j#2V{mbrw8*-}O4OVtT@ zk8kR>sTG(8Q#xN41Z^q`jWYUjlwTQbKHpy~$4+$c7n{-OzT#5p-g=9^x#1W~R~b#y zF*&=+XuDW86?K%3QS!zdPA6gwK!vM}7T&R`;O#h^g#@D4w3ba39j@fO1blx{9J>kb z7|Tjy87rwz8O_SFY2{i*@1f&d5z4tHdTe4COIPVjGiDhrl7+t_`<>`i^6uX;ooahe z<$Rs$*fe$TVETF`ri>LK_UFY`v|5hMsF%U{$CXd%iypI#*1)kDbr~EwAn5A=s_3xR zMmxZ!g12X38}`{!MdvGl@6UW=on_ls!|GaN87-Dy8Otj6H@&gd!@&;>dNHqiKetO5O?fK9TyKsd+%W%&sF-OdrE&*9b@*QiSL^h zjO!|W@ja!#_CaIzF3gj$A`fcMTiJ8L?6$3=tw~YOkK4o;|@VLuI>tl`W1n*|B zulPJJdX5j``@=uq8z@N%Q*<~EMG<+!2VQJ$ik+c@TSx*O^px@uYi(|Xlkt+RJh96xQ~k| zed~s&^bd`QO)Z~C)mk?!n<_eAUXD?&H%i|UPb*g$D?sdTcw;NHWz)*Fj8@9`H@Uup zsj=K(GK!_?Q$|OGWz)*Fj4ee*afgZSTVQDADt&2sN`ISJHqGkBH;TWQM189ctz4xq z(U{WrM2l8+q6fnFK}mJ*B_$fiNF1()mtKLQ$o; z-RXb!={}5n)!0Xes%5_jg{zF_=U4hhC9PgJ(PP8Pjwz$j9iP(I){OeLiS8SKF{Lkh zOzDfxs2`f>zQ&3vebGJTF)d)5M_=){c&xKv9Ywl9sBxdhTZ$;s5-M-~i4Ho%XAH{( z&-Ru|if)YA-umdpXbumKeE2Y$`{7?>d7lU2q1y_#9gg>Byn8gfXx=0D5Aa(!-e>Xd zweW@tZ=%pGh2u3e@0ob_O?V;ATO{6X5?)dB{s-NDI9^iob_dw@kUI9_4%P6gd&I9_J+76hGl+ky8N=z_Z7=IsQ!CUCs+_CDSPG}!{q`*?clTK|ro zI$jHVANsv3;0&MMuj7TR_u=IyT`nB2IeEcJHyw^wnY_fLtAyiqrT583C(;dpf9($(N_A_d9y(l6-ply)&OCKD}Sp)Ti$OKb?23!9%}yvN0C^TsiN2!YeP2 z!*o0%-2&%*D0?~{SiH}D@Y8X*eA1_72{o>p0cO=(5F8NKb^NYc=?k4 z`TR~J9=;}_6sj!CE2t=+n>Q=J zvbr>XW}ds5R%Wk^0vtrFg0ia8syvh|ql61Qt;_POOCaHCZC+tfasHf{)p^zD&nl{d z4kIV8s=BbWycz!0c?65sxRH&%8ZZ`?v@&gq^5?PRD8ihZ{tvE*baq_Nm?k3UkM1|yIw{pK5S13C1!@=Pobh| zT59M_7|v-GI*^2s9*EE`sQ{TjLl5K`Ij((+@L=tQ_HJBftF(6dm zi3|uu!mEOTP)lcZk{xmyH456H24QFaY#U0)S(7v+d~z7CUcz?YY#YXHLiNMW1@w*i z*U`Eu+Md~VX03RczZ-9W^2-Rj5hG#eOJo?=B-8?>ZI~8{3umS_ZX607-zb!T+ps85 zy|hq*Gj0?@oK6{yo4~C8D5}n9rJRJcpc88D9JNuc#*I=NA-H+CndfI2!p?3q2`z zF=x$M%`8BTeclaiL^v}bH* zo0Snd5y{1~Wk-j)z+0bFb6n$43Ja4KNYii763w8ohCO-!F(>-IUuep1-kyO0CHan{*s;qGQ+!}<%OZ0@XZEu;D` zUE{E`nr|&5lW!Jggp!=wRte>9O|5lz+`43|F_o-SOovHKuR&{s-l|!B?M8|CN2jB)P82 zv|~mn(TQ+f>)*&M6d2@wWUvzWhM(zy3%pT@0tG$dCOEYIl*g3`3_Nc8L zVK?S*aUN!I8Z~m4S6Dyi7S-8YNB_L^54n0S?mt)AT-q;7v~_er^cQ6IU@bFaRthYu_uDs_wQ4{pp{J8Fz$qU9i)PhRu$Iin zfg7>UE@ zFr3LehLQNE=L2SpINKJc)tb-kOn*e@ z^JKSyTN`b3KA-7oTh_Kc+pOl!t#zjDdzz28)X~2${msYDQ*Vx;8Xw4NL!H=@v?mT7<~sk%4jn&GZ28NXXI z)~ovenR@*<4T8a-ig86j#ad*zb!)>*wP@X(w*wjGaE9JZst&d4HwvAd*#HI&+VpD^ z^TT%*(ust7m=(%9sFaw)&7V=nS!?Z{mW^Mz}VIM|7OVlA0Ha14=&;!!ZqR`c$0bM_PZB^ z2t*HKrCX8_}Fd)yXWw zOViDbagbWPgB?S$KHe9|aQ0x09POOO6PHXJDV=*3@s5(S7x!}Nh3x>IHQRZ4#f7*V zSC%)wVpdVPl~+-oS2Vx0IxoL+MwK-|swxYHjAk-br8CNLcWwHdVrx!0g`&bV+$Xd0W==1z zD!l;a#WVAfLtY-VSv~R)QdC)4UJ=W3!la=?hfkPb6_gYeoM+{gP4}`v87NlHEGk#l zL;FviR8>@2HML-7ep!BH_sprq6_w{@O&vOB!pI4Ey9DVh(aHo>fuB5)|Wp?H}GCv~b_B;=EFnd`RgGQA91jREe@{t)$%1Y5xrDe0`R2JpUs;=}^e&m_M^Tv#vfW{v> z!pbWznqOUPA@$7OEN5kYc_A8GxhnU(^Kk#Md`6o2s@>-KRk#^lR%Ci3FRvWt0*q6Dyp{d>#uWA{i3p>${9uF1?O9{PDATO z$H>It6DH>63?4apQZABb^{R>rT+jKYm2hhswJk5S@(T*O^DC2IJ@}R7*3ooxWp%~8 zf+}^bZ^V^i#O1kVIA!dlw4s@O(##EGb2~hC@3t z1tn>fMRQB5a5p}!NAEt}`}90JExoK@)|`_IDk`gs=BJnSgj`)Rr))Y{41MvexjoaX zW~CQq_NIp2m5y8MCzs?`7DAC3thDsv z@{07T>dMjr#F|-}Uxmj3P!{WnKsp-5JQ;wlFuywAFBi{B$Gz$5%KU=rlhNi@-mG4} zIXHUw*i$eShv(*=mdm+Ug@(ec@TOnc^w@+bKvCV6FEcHV37E$Mn0dqI^&(;7VzPI) zW=*I>M_^9k4mNun$(Nw7DyCOi)2W+)DVrJd_K11Wa|JUisxU6{stQYSFT51d%}sGD zZ$^GuS-x2c;N#jbm}^69l)AHM!kE#6hfT5arlaRj1l%H@Sz3ie$~dL+@+OVOs0Ou6 zRn0BM^q*H?D(_W;PfcJFoggSuQGWTHSzfffxmX=A0L=K}YK1zwlaUqAw94m{jjKRx zPEw59(yBrfVAlA|UZ!CNo9`jM)h{;a2j`wLY0U7k6TNOJ(K6;vZ{%odTUap%y<_E# zK5gi!c@t6m%2KYFZtGiBB^Zcibu`9o6=R^47UMoT$0m#%d&;EIgLCmvL2F7Ch6&eK zJe|O3Liy2i)6w)ZE2d-p^{p+YMCTWofuXi6Eh<7O(7*XJW9!45@;OySXyWpsdFa}? z)fiQ1w*2{AFY;#g?wRi{BhzP|XV&rAS(#?QRF|2QvzaE6D6Fc;E5X`^rkXX3Lx5$&+K*DyI*@31$Cld}Mb)T%5!)WET8Pr; zRWSydfh(3bcA}#ougVR;G_9^UFK=eP8E?~lGvnVp*6a3%hY37Ka$6Mn7MGi&s1AQB zwHfX_WZ+4Vy1rIxA(nZ*#BRlL(i=Kh57^G-rdnu1At-III>FRaI3~R;Be#ul01Y(|@~0^ARlH!T${(+|65%lvv;D zN~J!0JUb+*?b67l@t4J29$pr@BKRlg%D~n3;G}8J)q#3RZHFWb&Vq41AB$Qxw!*SP zeTJuxvBLG^#zX@3!YRQT9s-3&i|-rQ~x@V}hkX5@QY0MGjl{-*2=qQ504 zC2o29gYnD|PYrz^2PxnO)_os5LG*nbK1B3=9R3A|?}IH|d=ei?*Q+D5#bO`F;;$0N zJ`Uan^?w{I#V;bghIQmdRvI*H1GaYxpLqVOk>9rZkAsm09)MZ_RDq=o;ODQI8`)UI zZWUGlFQT?1VZ{DsIJ=STE9Qt}#9VQjSR_`77l;>&*NCgd4dOlGr;D@2#o{$0 ze~h2$ao2H@ud0wQiyw-=hzS_Z3~wfO68nlX#A@*p@dk0H_=(8fe3@P%h84-pY{|}I zKXHV(R9q!KAZ`<16F(Ne7Ws+?)9sDvMGhAyiACZZ@lx^6;_c$Y;xpn~;$HE4F@%B6 zd>V_~W1Vs@ak$7|cBj5roF^_5Zx9Dy?$K_fI9Z$_az9swuNH3+`3J1jZx_E7e-Z0r zE;5|^W|QgS$>JFCY_UwdNW4nCNxWa&ChihH6%UEQh?`$yF<+c5-XlIHz9Y85a>sJ^ z5QmDR#M8v-Vu@HTR*M&kH;6Uj?c&|y1LC9N6XFhWm-w0Zix|Ng7Qk4jFE%7mhZ9JY zzrEznB6n$^zQ5#w;!x?wO3oE0OFvz5v3Q>Jb0uFOE|UIFlCKt5Nq>{%Tf{r1e^Bxx z;$NkIR`QGDYtp|j`D5`P;6Tc;q?qP+;<8+1Xk|;JL5wDr#7Gft7@wzE|kn}^v5z=#02BtSj zoJJyEvBEEuev!CLTrRF8k^frBH;H$VNaucqKPCO&#OI~oCHXCJH;H(kEBpuPe-?j} zKE46$*bd@xB;uVYwh}WH-b)-P4iQfkPZKASNN0*zB9@b==Ry+sE)iFVtHm2g*xg04 z{*t#Te24gg^sh^PTl_nTc>5H7So)))jnh-6UynpNlEmXl#A_+G5qm1UuXwWbgT+zO zj}_05K2IzVs}(+9yjZ+cyjr|gyq-jP)`_=CzfpWh`p3j4#8(ymy7+HSt~PKNR;#|Fw8f4B&Ex?GhFnh^b<8F->eoBA-rT z59xc0gQY)3JXM^k@M&U^^rd2@^mE0FrN3OfQe3a_4dPwmz2YO{qk zBk><3+TmOAi1?crpX!DuiVaDm+gNNTb`iUY*(A~(CUUDP+4OMka`zqn1|JH%JSUE=%V$Kq!s%DYeeQT#>3>un}Hg+x7@h%Lo7 zVpp-d*o#EE{lt;tY2pO2kVLvAVwv=_#S5fgC|)7`H6+$W?rG2Xw~2R2|DfbY#HUG= z=Q)MHEB%M!-=+Uj@;}6%NW}Y1bZ}u#xe(pYeDMiZ&LUz;@#r?;udkM_%w-po)KS_{&n#q=|3aU zp5IA-SmYL7Y@d*rB&LYRk%*TjxvkiZM83Vme&Q&Fj}<42XNiSkiC9J=o!R0A(k~RR zkp3DH<=7zoZQ@;uqrA;t%4_;%_9l{nJOMHo+xIJ zXvZGnN#Y=Jgg9CpPa?fZVv%^BSRpPZk?vCQDsiQ_R=i2Pl|;ICijRs9> z_<{I|xL^EAJV+v*jlUOVx^X1rrXtQ6;w zNasTFN^zz5XYmda<@$^Gkoc&$P23^AKqB2&#E-6IU=TrO~eyO zq}x*LCiWuHemNxKj}j+{lf`Lbp;$^H-uWcbT_kzA!dHklh&PINh<_39Cy~xp689`# z65kbn5)-lOBEvg~{l!UQiFk?lg!qzZw{+v<@q#HYZeJVX_K_hj0}ZiE8=_ea+ligT zOtF_ZPMj#7CFY66;<;kAIA2^OULxKi-XY#AJ|J!pw~Eh*FNizEH^q;{zl&dr{}AzG z)5kC_Ti2oFS6$5;ZgLG5HO#R=kMu|PD>nULQs$>w=6NB~A1!&DI9WVPoGzN@iLfu1Tq#~4E)*{nuMk&?e-_t^8^k-syTu2^N5m(@ zr$zG{?I_2~lHU~H6?cn!!~^0##UI3>>6OPZo!Z z<~b|!87Fz7c$Sza7K`VKmEv6SBJpDJ3h^q@Jg-GQ+-isQsu6D$?-uVD9}yoHpBA4H zUlw4sbVv+h1g!~EM|(m#L41WVu3hA zEEg-q^F{N#8Tl`jyiB}CTqUj*>s3-!Azsag(@Nd`o;!{JXeU{7U>r{82n2@*I@y z5*F)=4aKHnbFq!sLCg?)h!e!gVxCwao-3A%bHww-#o|)&O7R-;I&rOdvv|8`p1Y$y zn#I`mUzB+k$9PCp2MSl*Gj%lyivSa zyi2@S+$?SppA!EjzAWw(-w{6$KNUY0|0y04kBWRji~SWRn&0+s9p4%gQuH*~EOT^1X^V}YGt0mte-XY#A zJ|J!pw~BugpA&bAZ;Bs?pNOA}Uy6ssA4QALwNaj+SYK=?n&)9Vpp-d*hf4`93tk3r->6p^Iibj&%74^dhY|2Dcrmd0R07$FA=@>0#-;~ zEv^%5#Es%T;=|%&;&$;_@iozVPvCvYAB%g%FGTac0Lu4+Wb?iNWJk}(&HDn7lO?B# zZN<9p3-pzKfH+hdQ8e!hp#6GEK1m!T=7^(2@4bP^lFt#Ri|2~v;vDgO z@nZ2(@hWkp_=EVfSWnNvlf=g2@nUPSy_ha$ii5@B;%IT4c!qekSSXf=6{2|$0PS?4 zD+ zE1LHYP@Xc$v&H$MdH(?6mq@-`H18ikZ{9xu@09*-@j>ws@kw#JSoeK{&!zuT{8s!y z{8bF-`MY`l0Qs8t55Qj1_Yh zua$0HnYdhBC0;MyB;F$4E#5Dh_W_X4|;*;XD;)|kruK?}vw&ah*zl-Mm0)(6Q3&2Ct z|0w<{2KbyE;q}Fa;_>2%Vmq;u*j?-?)_w2bROwF>CyQr^)5T)ZyoZ2tnD-Ds@BM>C z3cp+TD;z!~haliPTcvuXjx%G>P$B8G1 z9mTFiwDKS;!&|n8@K(siG9SA z#35piI7S>Vo*|ws7K$Zeg;*tCC@vB&6aOTx6#p#VDBdh?6z>rq5+4?~%8+2SzqRPi)1Un~-5inGMU;!^QS@fxv4yj6Tyd`#RX?hxM=-xvQb z?iGI&kBA8!R9~@)*i7s!W{BD1F!5CJG%;T+60a4n6K@o67B`Cbh!2U6icgB$#TUd^ z#5cuv#ZSb~#4p8vh~JApiB?Cq{y{N8Y#=rfn~AN&c4AktyEs@JE{-PSEbA=EdE#tw zj<|q?-IbEB5pNc67atY>D!wA_5I`K~NZgH!)P245EC4Me`DIO7j6O+5T^=Krv6FZ6h#ew2*674)u z@)WUDEE5-sOT<;;_2NeH9`OnBY4LUOZE>G?K>Sq$L*qznB6bqf#X;gwaiTayEEUVdh2j!% zm3Y0lQM^ZdLVQ|$U3^>ICms-g5wT-}xsFT`n}{96F5=1JU@>1T5@(VaR~JfNB-V(x zihm(t_n71-#2wPVA^9Eg3-N35I}-7o?ryo`#N)*i#cpDjI9wblo++Lq7LiD|TJn7H z3h^p&H3_?0CEqD-5x0u3h`Yp3#m~i`#9zc@D^e2aChSiQ*J7Pb?5C z#kt~2@z3II;zsd)@gZ@$_^kMfxJ%qE?h(Hie-i8UaO;;OwiMflJ;lD_C~>TqFBXY& z#S6qM#cRY3;%(x?;$z~A;;Z5(;%DM_;$bn8<(9v`*g|YAW{G{o5#ng^9C5l>CC(F< ziOaF#Fxa6#ZSfW#KU5wr^+w35L=5`VjppYI9fbg%oi)gx#H#GmEwAF zgZO~>u=uR_qWFRMiFi=_UJUng%U@4yCAJfLi~Yq@#nZ%TVxc%kJYW2ic(qs~-YRYu zw}>x@uZSOupNfaXAI13IZut|%Hev^{zc^4FBaRnminGK;;w56(Li$*jlF1Oh#Gn{2 zCW@Y2BguFyX5!&?wqcrx%TpucwAK)ZZ9^+ixIw&4+$3%mw}@NC=f#)Bo#LC~ZgG#eU;Ik^M*L1ZEFKl{gP&&n z2E}+WQEVzU7t_SHVt28pXnqG0?J+>|2ywJHPMj!C6AQ%>ai%z5Tp%tMmx?RI)#4g) zy|_`lN8BWC7PpBz#6q=8BhL3E{GGNp?=z~-FRRXA++;r>dm{Q1+T<5$Z4q5S<_pK(5Zw|7Pn(vQVIRx^`3 zekw&2(8?&NC@bUd4EtggW1CSJ;U}dt@~iPP<BiaA>gGbC3rl-YYAwNA`M8DC5 z=F-2%Tqy|)VSz85EsK3>>Okp1ax#X*?$WO|rl(e&XiLpY|#^qHrx`K{fT;P*eF^FCgB zjN`X^6XpBNGXg!kZdqBGJ=0>J%wD~Fbnn%@d#|jtwC+ajerI;?{(rIeCh%2N=idL` zXPRhdR``T8q{? zPgPO0))}Q%tAM1SwoOIb|L?cWAoPn$$n zwawb*-&CK~GU}^MJM4EJ8f1O-`npF4**6B?4M%;^eo?z_??F2}x~*@QukN8iuRXb~ zwbj0DblFg6(}1t**4f(@9ZE~OYKVW^*hAN*lni<7nAK!`bimg?TX*-M%ZH>LvlFbZ zYS(?;D(BE2D+9H+M6JAw_9Y!oNPar{MCjuql`E{Hx32XaOSkVimhSY4Ha+5B@w+4b z{!NcK^J+e`` zE7E%JjTa6FD^m_T8NS287U83g-Fjc`5o^WUN340B>pQKm&sJs*CIpSL}0XZ`qHTD_BLl1swuShxOPr3Dt(BZ2>_O|;D+m6-kwkJ`;G`Q33V{1p< z^Q7*B_(=N|$38EO zwuoN!d0^Z6P;jGl^zfx)57j1(J(SeiIqEpc$3nJ$)A?;f$I=rlJNcO3AKJ9{VDhzS zb^GPRNy`&9?vD1$3hhk2e(%A==TiJy48>TfIRTYts8>ycOI`t~a->wnV! zjQZe;NPXvNz3X%P_o?q#G_(E=q;to#H;*`7XV$K8{iXe@ z>o1?yq26B6zP`ge`%LzSiu&9l=C%yE^{wwbFFktK8^Oa^6}$VOeedB|pl>kMc{A%f zqojANn1!BIg%UIM>iR29oY3K*GyS3Sah!gKUgY1=0bvlf|Lpq9`>5;N?hPV(M^{^x&tIB^+|bDL;JH05wYIQiH=`%jC84qxuSI=UlT zd}QGYfqxXVn@fL?{N-khW^Jn zWV~sAUr{r(Dd&*#`diWde#{*|n>QPC$Qc;r<@Eu~AsFdrVlMJw4w>f8Ax|B)%p4Lt zY^66p>iAmk!;xIE5j)4Njed5=w5Izephg?98(mlG687ywt{K>=qsBh_H-kR?(w-JP z<`3TXh81b@z;C`ddY!ZF=EG^hV=bLcGg_VhS=!+wf1lR5hd#wjIsdcLXhHP3&xb@W z`~3F9X?|Dx%x6oZ{?ErA{b#{PpIc9wZvxHq?zex26Bp0%))AvP@yBNeKgLC$&kmIm zzQ8zK75ID!UqN#2L|EVGtn&zefa@waiy3NcOI#K}m0*@e2nA;1^ydpDa6x;&KR`<- z@cSu(IA<}Lyo{lAUjT2XAag3ChWy=`+L`$AcWC(wr~>{y_zg}(1lwti%ez2c8Z&nC z5G}C8xD!r;Z?Mb`uZ2g*AGqD&8vTh}U?Xs6%G*#TUV{_^cV$p-CGl#aIb6wW;c%>! zP~g@?t{RiN96y1dCGaZCmt&>ggcb_?JirsMFUM~=uQ0*89Y%G&!)ZEjf9u=fm*x-n zFN6+_#kE43(Cu7-un8?pgQO3HA}gUs=mRkI3M87)GlOpA(G-T95_%~|f9fAm%!FRa zZUI86ml`qC6;o1ujM}TUE2cLsuCWq&C;!1Dl!=C_hAWAy*c`)d>V}ICu3C|sa7KvP zrcPo4XC`{}+k|il{U!QS`Jf@;EQz7imr<95LWwDhN%+wK#d#=Q+ z)EUfZfW++7FWDFaB}S}fQM6jfPACfT-Zu3e9KD2*N#;Hmtv;CIs6>iR&RRQ_>pvun zF%^UCOTC!#d6F;pSxJ+SH*bnfmD^d(hNEa3?Su(X!AdS| zN;fk~V=*jt)U;ScpVE^Xk|gkCMUB1sp2!bQFiTPMuvCt;>fg|fm!*ch{Y$6-E|wX<8TMP;(MI8I7JjvZQr5MeWSceI;Qz!(pAfNw%4TRp@dPG$>t zw$(#I$dMHf_?djxbEraE!nt;c3%Z0W@slvXZe~_@K~ifOb)Y8)!(62&VUXSI9Fz`2 z-b$k5Wkgc3TkcC(>q|&OGlsh`sdc`rwI-+)ewa}&^EGpiqaRmKkT3V8Gq5iw6n>J& z;3vK?PZPeJ-0(0#qdA%+T`JjKIycqeOdy{CBG4&T8jwVvWRJKUP(*zAr+bXVI- z;+dMIGHu$@m02hwC%E!Co*cGX9!=QhOPC8q_&03Roxau-*b{DIo89EgGK;h1)L2QJ z)hU>y+E__zQ6ml{$*qnitoAwgLD8DCPQneoWFFksud$4~e96q!&Ho86QkE6G96{`W zpQ>z|(}3yS=wL6y9q{v-BHON~Uc=@aqyGfIN$i73ct&Ij;IrCnXASb5FlRp7ZnK#g z_i)-|8PVtWUkZO*k7XiS+Z`xkz&;H{3a#@6X>g_8g9x`KaxEI&itw~#N3w84knXRc z3SHyN>5EXd-QJCsSYtc1vl4j}L9KQUBe&axCR*L@cI30F-9)HYwkw7Hl6L1Jp%s`3 z;gPu34lG8zgexg*vzvB-&}0vOa9wDApT}akF#&hT_=gHQxu1 zaZp6D=S-t+e6w1(@4|iqb>CAr!G!CHygFmgSq2Y#q6xPOawTQi<}V{X4(O+- zE1+(&3HJr$PpSKa=}j@Z6x1h#JvRYA_Jx@&OMf`?sH3Mn!{}~?vz9t~+Qpg7qYK*T zuMj&{)L8aKCK&Aajg4_?8>rA8Tl#J;Hd+uM6ggrBxxxNMY zCF~t5s~1>yX$G6{T-*b+!`^A0WzRC@?RYU<&DlC-sqn*|`!>^^l|>!RPPE0I+nTkW z)sDJwI*tzZ+?Uy6vpQ3^8S+Z%nlf%#(<`Cl(gWvX&&@WvHq`wJ@~zZ$HoDWO8{7=b ziDU0vjpJySXY#PF$z8%`nQIDt6+BmC&s}D8Em@H-A@f`J+?7VxjykSQKMH&9rAF70 zx|bk7hP@+RNU`Uc9}O%SWGqpVHsj%gXmPFm} z=G{DC(rVEd5=Cd3!phs!glT0p=B5xWRal9wR9A_uO`o_HIyZ%l*4B@D zoRiF^L`fCDT^EGo8axr>K&{*R?UMs_$hXghop85)tWi_DnLQwQBW(}m1mYUc7yQ*A z9MxQ9ZVsh%9ieM%H0e6U>(IaBqp?h8!#Kc1y2?B}M%r}el2>3bIM%8I#&Hz{dXSv$ zjE9N-gP(k8Y-=3BKT+7$c;YEU@>^fqjuj_bIS2wNk2y%)o8#>#XK)4C;brG-Zx0$l5V7IM_73{o|Q*sZ_Cd)fKK5Ns- zL5v^t{EBuE(|}5^J$LR@KTn zIyfYtXFJ`7ot=c_L5iyk#e1+LB*CUce#B$g8HwbOiHqcoAcXW9oFTmp#!TG}3bcNs z8)~21=nNU4o(^gqY_6BBqoZgD;q%g9(WFMSm=^7XYV(Nk(4gCG2VOAB#Z`55yyglu zb#%P#3M=dA_z*j$8R9EfUr|R#gV9eWQcwoRTI#Q(BjO67IywqmA*F5x9G7E9-o(|$ zIf38{F}5{>aGeu~JFz>~>X7LWFPI<`UIO;HPQvXbGuSuchFf2>4$4wfM+YzEAgrvT zV>))*noP_z`ik^AI?9cHJaLQBFY(vW@q{ac>gf2BE2PxXk%IPgtR?AnbnwLsOj*Qy z>_MvrevrHi?52t6V84Y>RYymb>8O(l?vAy%qK*ze?|@KMN5?2vsHvl4 zqARSdqr+THTjvqwuD+s<4ql_8w!~_q$Kj!a>k1?9P#qn&xk5@^Y{X1{4mw`sA~KPL zj*Yrj)zQJb6$mwTbhL7Xm34GPu;bVgwET%c6?JqJ8vQt8oY7bK>*$!}3ZXhWs$3x@ zZd6Y8Mj{f8jljtqY8+6|qTiVf6690$dUOnoCLe}`8`6vuYGN_`ac+(^pO+F2%qh}j zUfem7)?yEtIj;hTo8yXu%C@Ex+#Rbjy^aodpjD>C4YbNo+(4`Jn}PPJi9Ufiaz5gxFX@M~ICjbOdhz#rkOM^fjI1i07!7Cna}eO-JW58;Xt% z2T2=c?kljb#U6{y-tV5+r^ik7Jh5x)j-AV=pEO^4mq%>3%TWeQJ3lP>Ni)EYmAr9I zKyk3SCFdw`PZcKXxNfYhhs3g;9?NL@DH;SRxrxF-H+OGiX5J(aw05zb%q+kW?6WqG zCD}xDd!x|{#{tPPNIy0ho5=HHw`M2yWV-iYXIS<#_AAfN>tpa6>2)!WXEE7a-G~>D|qR$F5J`=bWwr{l1;#A()GqKu8vV2*XNX>;mKB7k3C>5vwC%` zqm#2F4m|O$aZV%-V8_LpZ7w(d3V|_tx2mHvX!1UfNWzX2rEMm~wyvItU=LV}t)BUf zGo;VzS?4uAE|$HC5SKS>cDI+9OX&AaGLs1&3>B4A9N+Uqc*1XHB4o^WFgZ`*649HX zm=h1xWbDX^n1S7~D(t!%I940|H18zL;5?eIVGmf^KkGW{#NY>WNv{1J)9@3!OaqGJ78MpJPXU1SboX1kG(Wb3lDQ zbpxC#sg+DWZ(hKiB9Cz|(}q)sLhO#UY)#zRX^MAt@>vCSvFTxoH$70z0m}Z5X?@Qc zc6v5Z0&i}EJ+n=FEj0z6M6AW`Sk<<2a5C@6^+XM|q@Z@L;%+l|}?gqs1p%6k1&`rEN z8AlsaIn~w|$|~$QBM@t`2XWa^g^Lcl$C;w6wl;-u<3)jO8Nz*S&}h7tO+XZ*VDT?U zlf;5t1?d*-$bevbHHN0ZTb)>FN_(&)G{K5AhW2U|3ylJvv`vJ(1iNibBi0({M1p+= zT0WFuws0~prWt=^5aSE0;Siw~;0T{BT&gCn7)Gr^-z^jEc))40GTtj@-tQ=B0XT<0$4f&()8L z%ZLsW|VriON&$u)busM$Z9HjHIo90kfS!oXS(o{OJWKB9=vOcRa zmLxh5HdNfZ_V?j6-SWmXmzcDfP+Xe44Gy@s#dI>=6Vo&)Ldhaxk8N?eY#hW~u3!*c z(U5Fzq?1nm+|`dE-2+{jLcZqe$C7_C?#d9EY09v15XnFCAkDGlAmd(cI8}O*<@Vtb z7I}rMA49rzSh)nXvYnsb1OF#1 zs$NoB)+0K1epT6$xeI4Us~475&0Vyx(kksgy<*9t+4#aBQa*QnS!JY4O~1aUO`pB6 zI#RW0(frB?zKe*IEtpw0YgXB;>HQ+T3VQbIzPL~K1ts$qEtw9_?h6+!EbCrYGIQ?q zxeH6@SI;V&zM!OZ4nJ%7uSmOc`G2&`^XJZ-KD)H^q_X$R@0H)vtHFOo$u0LtjBwk? zvVQozN$+0yr5qT=v&za#s^?b~S1qq7tIVInu25WAH4E?FK|puGcP1CRuErqHA_O8r zk3O@c44;s=K^Bx$&4CNOhdD|Lq9@@sx`63q&O4SJv+Kt|AM zYQyDJU zQO`hXH)wi7)BF_9)Sy#kN1PP2ORy)>NOczH7c$k1A}0}I(56og(+i}Q=9rWaXNCQ* zwB;sfLW@935ao78L;_8mf(TOX8Aw7}3BexCn+KAEPSlRDnP0+aA@`XSPc&UUOgb~&XsC$m)6*#V(^#ZrTN$}QIXdiK zN*{%AlU{UU(kG>A@?-b6O{Oi}*rw+rsWf_=eu_+}M{}M~Xhn6BO+ytZdvu_onQO0nudL)CkAJh3-7%EJtN740a4;1?`a|M-J-| zXwn@;=>a+86i(EBg&paG5S*Txa6Uj2vf&%3$q zygM@&X=5S}vh5Os|EBh&d3QMH-JYkIcZagN=kgqRdc-|ZIbU5;7^r49E#wa?e{SGh zR5hKGElyWF7htMRjo|duym>}Twu$pQ{GlV&xy2WWIFGF{4feBD=#ucm1bxalA!i@r zq&Npw=kt{O4=0~z1pZOtUtQt#_>l{Z;^OjIxD;AYT(hX6Y@t=WXkl?#&D^Tuk|nb% zEqrQPJbK{7;l*PHju|l~Y85Xlty;8TCaywCs>-b5C4Kr?l}kzojbg;gxw99R%rBl< zU2at`q);|1!p{Woa&UR&+!Y93KEDKM7US#Ls@}bd;ZwF`$-+gkOeRbkJb37Y30CQx zveJvK;srCkY|2VzQCu>=Y@xCq+<*F{%CaSu(@W=p zPj@+e$b@mz$1PbjudKAHa{92rgU#jBqH5$^Ua_c>B`C+GZ*l3OMHkOS`3B9MZ3C(5%Y6mqn1?S z!hJ!RY3}0U%IJtuLveIwRazAz7WU*%FOQVzwq$nM!qVkd z#aJ{+W5Fg4oiMRDI&j3ON#l_u>rh!%>N=L2M#1Ghs zc1x-jEi0|`x=QiVlKItT*03>?B7=LL5iyt9<|d+Nub#alUGQmiSxIHtX^{(XN#4C* z_nByj(m4@)SUtBA_a~8Fea|R3qtAtr?h8sQs?RQ6v;^O3cVEy4a@Cyb1v9~N=*ugX z_UT?((S26WzSQt|bjJg&k%z~n1N$H%kF$|WTQPzDyxAKZe_t~?Sl`JXm-Ye35 zZ0|_-@`a1KC>kf1ErJyLfxgSl6NjvtN3%jFf_OBXGyT2fM4bvD}9 zDy}#^Zt#p6I%XKg(9rSY$ByR^szlSEb9+s*U}mgem!ha{TQ4wejd4`W0+{a42K6Fg z{9%+9SQQhNpy@HRa4*0PjpXOx=q#F9Y0ac=0!CiXn6p>RiDOkde^Dj+eR1WixwxyC zi|FR|!YZC!vS2}p8PRZYh!5ltkM%_}OlIPMA!poU%%59{xC=N`ii;)p(*2p*#dzEb0%JB`o%I-1ua`XcS&W{h=sGtYAh(+8EaPMqT)H2g3u}z zLwHPCDon-5|Acv6-842Y&MvD$z026lXuw%0cX1_SpaC%I8#_be0WPj|J-8ObqKk{? zmzWMTGrotL_CVb7h2~VGGm4wDxv$j`I-#ZrZSIzNFmTH8jxfd~2ggEFB)4VFRC~(1 zZ>tzdR+N>_EuUL9%RMY*?urlY84Sa1Ze?+44UTeU84nRBZ8L$p?Nu_L9hZJ+ISeS% zCJPso%twuoHp^h)WYj;>g|p#A^K=DgugE|=VHv6?ED@ZxO3NxM7cHrb^y_}Y!C#uYk;TE~Yj{bN%^z(cNNC(kMH8 zAQHDZ`13>j=HPD?@tb2-W{7F#8i%1F(6)U786YPrYFgnR$FM;3OpXo z_!Q?yuH15~tX!Og@iYhLo~6YVB}=O2Vy-Fg-HQ+U@eDA@J>EXN;LTh}zROIuB=L@F zM>5TQ3y^vqUb4S9P>hQFdkg)~7iWtL#cJ^~k$;Y5_|4)i;vFJCA)x=0;w$1i;t}!h zVmmYp!{>|Vh(+Q>;yiJwc$v6cykF!?1x)WN5d*`>Y3MK1w-Nbwe#&QwMdJA)KM$in zUtuS&6mJl36CW0z6F(Eb7Jca6jNep@h-1a+;>F^nB0u9{ycfmK#BW4=C2stiiS5M# zalUwoxJ|rM{FV5E_;vngb9cj4FlYX-FC6dd;dD2%)Hg=@pUM>9w z>8}xu9ch%)*pG(pX6bJyp?^^FFU99Xe)z+B8avUTu@em*pdRrKlh}=&Xz&~9|0%tL z(-!?R#IV>y>@D^qk=|g*!^Bb2Pmz3qc#-rMOI{>aNxw$&W#W42YbD<(?v(xx$#;tn zNdFu0CFx%k-;n-8$p^&Gq(3V88}aYb8#~Wvj}Xp@Y!`gkVu%k^47-Z?;@RRrahy0& zEEQ*qIDNV6wTZ~q$mt@lVc5UTU;Mz1l1~$Ril>Ww&x7I3`53%Fa?}_F*7Vb|ae<2XPsQuREuy*afd9>sed`)~)d{5jj z{z*I}el7k@#2cHYJ^W&_*hI_{v&9^-v)DuIEf$IcL~~z-_8cvFvN%mF6=#bJ#Uli{G)hCtQY?(ekz2dv#hvKK=7vi7Auf=c0e~5U^$kZoMOcyi7 zc4Cg$Rm>O95YG|^iBWNkI9@zoyihC`=ZTBOYH^i#sd%-xQM^&yA>Jb1F5WLbBt9WN zBmP$0E50qhFaAONOgt)nBYr1Zc=p16ksv0ET)2h$LE;E;v^Y_mDwc?4;(W0}tPxj= zmx))3*NL^_PI0$*ulS(2M|@m-Ui_`NPkc+M#pYs;*jdaMdx__YgT+#DwzyDSA}$wKiIe7_c-5nm90FTN)p z5I+@&w#PpAf--%X+s}G4OVy2iSM#Nk(Pb?7oiG?E9PGWvD z#ChUEajCdMTqj;3UMpTNZWninw~Id)xh@m)dsTc_{80Q<{6ah`ej|P-TA6AOF-6Q2 zvqUcX#Qge-=ZJ&EB5{m3S)3-$6w5`f7{&Ci6t5F&#T{auc!zkm_=xzJ$mOP(9@p6? z|0sSg{#pE5{DK+AOFXg4l(ak;8C@C zuK+l~egb7Y#x+}e{4yLKTbiwp=z)IRI%CJJ`o9d9hcGAS`x5%8xAFLK8;RXZn=+rD zEx@&?w|RcUpg=dU2FN1|j*WPRg6?MC1YvqC7Z<1U;=pOm#eCGqt7M$t+&DMGaoh|< zpYt{^jWQ_W^Su)VSsQlqWqw}1{QHa-hiQD&&9WkNX!HE4AjhZI1%LQq-)22<%h{OT zPvQ3Bz-j#h=`ozQd45+y5uaYaxb$$#(wH7ho}7?g8V(Sj5qO)I-Zm)W(;JTTSWlJ@ zm$r@R-32$}6kz9;+!udq!13@l`f-0)^uqn>>{Htgd0OEBvlU>a)d6x7UVr%w-0|fb z7gt}LiW|%K8ru(rifXN+ z8!pRe6Rh2P&^LR|j!5nPhC83KbGp@9x!q{Nz{%OyK59iiY_JA2pA(EWi9UBcFxx(> zFdE+1VPnpX`ww=QJ-)#|>ca;AIJ?{P$NjSlqe=TZZR~vG_=Zs7hYcZX|G`epo;_|g z%Zx_0ciYi%+bqlOJ*dGya@(ND_1$WN+lTHeK2)1#9UXsJS6E3%YnI+S9CZ%+Qi9v9 z-1Poddwa9BY5zei8QPFOJ#+3_=5KF6iQYWu%k*uW(2$ZcG&%-aYqGOt|3Tm62@Ro9 z(!+oW9*TEn~=>+5ul(dFj|4+d`8!Sx3KG*KKQ`o$Er+9QIZEVYg(|_08Lfw3CO7glqK1^xmh}cHJ>$Q%di=+S_3NU_fo& zj{ObRA5iAJ4%efcd6DZ;#t_Pw_qzt`0pIo8qoa0otbIBFLhF6X|&6;ff=%AgAG>1NQJYhr9mb5Lcw!Giq zzo^5OPMca^pRzf9bLQsk&3g|9H|#%{RQfp;Lwl}}wh2uWE zjX63A+f%P^v9a04tc`6q?mw7f`?l|G7_#iiy`te8>|MSaTW;Fhuo7vsurs!F+O_{+7D6~SazY*2=Dc`3 znA0x0|6sG67mg?AAl;$au$_T&_UVYW^>4J#+Iz5*ec!S4v`}auEI=dJd}F+20N?uho?VV&P`XUjR(=DVUDZaOP^3sSdc?~6WtJaBj9 zCTk-&`|PN%?rF5s*y!%)HuzW@21Q3Q*PMad&yU`RW3V-9bsfL2|K`5i&${7kjEepo z71_R<3O6(U_^o-{`)xjF^V!iHq+U2XVduK3dmBD|;M~pD*2vEN2m7IA&bj-km!|KgB`6wT|vxdwT8eKaDlka+YCKbltwc zVc%1`tT{XIS@hvxn$@>bma2PajRxnbPY=5zocqtt7ziBjHs3W-WzA24E{?p+EDkGH@fby zcJ&_8wYCUlSha6&L*&5zhAw|7KC~-k`M$0@_BMo`LP@PYJFJed4q{`(++fxEIc9Rk zHKfl^oqP41;O6JicLLD)`;5Z~d~MFShR}5Mt3I43a-zYV<2kn=ynlMpoNOHD3DIZJ zim+^Q*1o8P)H_CRM%upG*Wc)~^+#jq3aIka7uPtSbNFcXLa(;K?@Yz zg^~H}ao+~JaCEfgzJe`#8=ga*3pOD2Y|NDr8}+s~jE*Mn>jl48;n%AVX3KPxi9UTg zMngLmSc4n<7lbf}JON8a4y*}vt^LUx#l|{GS+vhq&eYF-J_Sc(&ZZ2^VUu_4uqM}z z<*beQbjRAsnB}@{w|m=%FH4+*Hi~QJ9K+kBf-Pa=ctS%CL9y3X5^!^9OZ9Wh4 z%{Y4o=FG}Db`P{M^ojc>Zk`1FMEe(WX5hTzYUk`o+U~aDoZ8Tiol$@95a#9DL7U&$ z62-X&GgRb&b9fzEm3`^mKe0WFKi}W5`wxHqoPB-GH&@*^%*bAUd*M%2QHJ{b({K5# z*qnm>c1Ji;!nks{Iqo9BbHcvMF#f&M4!wfQUf6ee8<#n-@4`RkI+X|&v+r^MK92cg zbfbNjm5Afq#Tc`*mN9TBz{?fbdYOT%41c4om&x#RZe?KEdT9c0*?Mtaq`P0n#U{T0 zA?ETVeqi_IWvBxFefSM>r4!q^45jkyz8s*Z?7r-TFYUfu4V|(3(gtZJ^2H0-eW`~s zkuMv-?hEzqO8?#AN@jT3eW5vsRK9QyyDvY1+6U7ee1jKuUyd6Qc3rCLx zL^lB|wSZ!OiT+f+Fa^6Wu5T!n@4vwAiz}w2?q*remYAN(w=-b(#r4fh{T@|>-4|EP zO8tmQ4Um|fx|VSVN{m>|@Fdo?`|>4A#TN@;_l0h@`rS-JuI~`qR2g<(xL%d9`@)ql-S(c*jBciWge5Bux&`&8e!+5=B#tq@ zp;Q(Oc3;?7virh>lem@*cjXZ9&w>EEFMmZ*Y4_!Nh^c9;CAKHB>H#w)LmNM|;>cv^9M<_mP zT8VaFuA%sRo1de2wEOZRlX|hu?~Ryi48Fkb%eO}ClFEgmVE3gtZmWDbjdow$j2i8} zxD{x$`{I_lFqQ97!0roeHPP;j8hx6^5lp);k1(Up)Y)kFg^4n1bMwRA z(tHtrsK;?R9bQf7)nWo-x^`dKI^k7J7j|D54o5Wn2^#};U#>A#@Q2@}KkUA^awtrz zB9Pmc%$7HjuB(`rG^UF zeF@?@g0cIO$tuC_%WyQAL%S~rnFj2>G&3Q-q}>+|1@|D)@J-x7G9n9yKr2zEfd2sm z$h1F!h8;96C{^C^{J;caJa*eyAjIbvI>ycmd!ZT3viowDC!=)R*o?6I!uR;H__2Vo z`*I~hgw5OyyDt>jBW{2%?Y=NGSOyE<#rnhUi+TidWW@u1CZ9D5=^DE)Z!)PDP)gc; zp}?ftvSDEN#g&6$zSZ>uyDy(0u!`;4ed&Zl8Q#dGVE2V*GbWWy`7&QK_c;2)JRi~S z3j@>c3tyb0-4~uFX!qqHOAWg(ZY_p~UuAsQeOYbN8yCiNAB%QhYE4n6hWQ~0?Y_7J zZcdn1*J$^}l`Fz+7#?TKH44~$;VW&l`@#|!yDzm2 z0lP0u!q|P`OP93!;woVGB?X12-4|B@yDxk_k#=8P1?;}?eNWnbaTT!paw9{)?u(nt ztFZf0jpSJ>)26WdLYaj!GVH!kp6tn<-Iq(D2oHr1?Y>Z8oAc!{+I`t%WY~S-q)5Re z1-maiI2=flUAr$YK+&4B4(-11;I=-CEdjeP%+<~RZ7&k+zPy8=u=_%l?7MK@LI3_t@M8});f}$%pSoYMhC`a(iS({SR=keLxeh;eG@W@o z3g<)AZKiIR(R~LeXY-tAs2iTnxR0U(UWPrF7FkA^U^k%zVeGlI$Wmlfi}B>r!Jbpa z(v38_A<1}|346{8qswBh{HWtf?77Aw%P7-Qd?Ds>hT|7z_NYuY)fsp&%?}K6{$_No zs7uCE(Z5i~V%no3)ZGf*4cK$IM!P+#6Ll?db@O-Va%u2nw8`QtsNTh%OM@q)GZ^Yl z+)Hi2o=bx#qr+5n#UsU5*mG-O@MLsrs&0mOBUPnLs~uHAJp4QaRSsWpw#S%8{|$7% z#Gb>Kob54fdBA9-F{zKe~LKp zj@vN4kOE&>Q0@~M{}xOTNbH+cbXwW_ zkorlRsWfzG%wGUp0T>B1tfZqab}k&=C$|!-pi&x+9U%#|RKrR(3>REC(c;>nVWn3I z#9*~q4-?3%5cFPY^eMV$H^UT&Sv78Eu}RF-Cv2Egt#R1dGP^<606833MaLsXShBK? z4(>Qu2UZ39WE%y)VKPDK;C%u50>NrAIo4_>cBqMU*r|R3dzF+#3uSJCml5wI{k9p(a$J}e-GKN(*rIM{e>O+1(ww_0Hj zqAbB2tU(WVTkI$%k%yhdB+oJG83d1tiS8X9hT+lSk)Ych|kb({Uem^s0@kgZ;AWC_LP#z)_^YPt{QJjjQS4bsbE*q}S2$C+t`^ndpR8fZkt6 z$2?aE)zQIqQQ?zf>@sBI>~5mdaSrw*ll7*pYp|R&WnNK3cjuZQi-dKHA@iFj=*#QY$aqd*f5MJ@i6pnHuU}1vD^ye%D-04`^Cl8%;(b;c;UdJtL`zhd zv=DtY9G4sYbYi>Fquf(f| zc%dd#E&@jf>?k0?nIB~$ zILM*(#=1Gu-YE$|ym4>z7#U{s$HqD$H;zd9VH&{Ajyp4ZHdk<*5Xv3(m>tl^;^H)p z@0iYu$B@{(F^ygk8`0xqBN~%-Y(&F^O>9KNxDBUrcSPef6&v0#@e?P+5Bw#ecptwJ zx|q>7p5S>6eKNgn2pn-IIF5F-QNzmE&|U2gUEW1tIr@}3I^6LJ>qoKiy4r8XYZ{xy znnAcj7t#3%CU+#fXEhz>ww(g!eF`68$D9HM<`fED(Ach`Fxy;(X!t&`IyQV^DJC{% zVJRjyX5qsz>kd=+#Kz|I*nmVJjzXTHP_PH$hTh`zxB<4h>Jjuh6frh^j*24vic zeEn)K8|Y(+V750G9-3_)Xbknk!o(uM)p)XO)M8L#%()^UmvPL4b~__k=MlTGBl+)E z(Xksls<#K=VB%u9YtwaNeAasw1jtT850#Z8*0k!hmGs%{k#I;+`u^A9D$@J<0x{Sb67_r zeu16syONH-V#f`XpKF=(jE&&Lc;lQxa0;-k3kaUR5rDYII42Uc6o5JroE^~U1W)q_ zOZZIVP9oBca|*#(1jRVONA_kzNjQbm?bQ%hbEm2kOTUUG=EG|v(BT$z5^+0r6p7#` z*a-6KYC7EVP5SZjb#e>!&1yPWLQI#YaQH!dG?k9QDa(ZhW~l~Yhm&Tc|7C-?dGP&1 zvmr;5kHlCzP=V{+Q?&+KnYnUCN85XsVmgpBTrE*yoD+zZ#(6%$9qseQDmvoY?Qs)i zD)Fvy&LG~$ZbH-Xh0#wS_;(77A3{xd`I=Z0a=D5h+uU=upVz9tz>cv_u=kpL;<_=f zQKN3({bCgz_h82)KzwVQ6NqfDh;*D|ifFoYTuZF>g3$4yD;!uwhdSjKE9v0QClIID zXb27$A-te|96L%)a2Y9-`oJnWrkNs5;UMGkPbetysd0`cREh(u;!5$wO0N{m*ek>j z=XZyN#^!$p*|Loggm?kzvfWnFameH~h45;;l8&9&aXm^fH|FH!ie$V@6JyutUISnb zrxT-+HwlNZ`(Q8SoD-A0Pf3#QBru*}vZqMWBpr8??PUe}W5<4+cT<8v-3is@ZA196G;%_`a&qQDDG6yCeeZ1m&#oR1=K%^m+#iQ(oO^`@O` z;5M6Sd_M}oc8}W_m=i-|q7-;rg`Ti}4IR7|X!MP{uv)){XSR>bd20sYUM0ZZk#`cq z{Ks?u0Jkjb*U-UB_r}z`>v)sb3AOPaEHwu8ifrn^TX-~yD&ja?^1{#g9~&O67`>VP z;zOGhOgzSQZ^I`;i7c*O9fXx63iGj}sfmTyaieUTi}&@ep5Wzs0Dp#n6)W#bo>r`Q zmGQW|V4I0fUUZ-hVqI|pry=$t=c&1G6Eq#x34WB_G0ZH6heyr!mw;VLf&nJc1=L zIkG5outV6nhK_mI(H#gD(db#m6zpzlI2shXVn@vhmcP+&fQA@yVik(8BN)L-u-hVm z*hoXR-m^?(>s5%ek~_9g25s{ZJ${Rq@4_Fg9IFeW{6AYV|I+@=|1?`N2wuKw2TJ$s{^$B1Si>&`HAz`mK;bVx$np7=F2?2)?ga`OcDjr>R+Gza31Az|H_| zvE&4D5waW1LM+aKmisYqljxjBYb($MkY7@;MIe;TRsUh61?CopaW(&(<}Fwv)?@iDTt`x5OA`ankZ#-(D)-QZx-C!H$Ru-2kIInlHilaU7;zVCX!gX-u?D@j3z9|ynlXtE-y@h6@Kh^ctffnCCzEyC zK#yGJo8oYEU`Ff`wEG}t_MklE56eG2kbj>Oih{DCj{l-4IY=n0LkElzj8r6oera5Z z!2*nI7AD)|Y-)}MLY}6fFf=-J&Fhty+ZD!s^4c<+%uHoy>Iy4aG-cDSefL0<_Ge+b z>XE@Ye#08*oWEK5Jup?SUsDK6E)eK#g2R-SYk()&`N!&f=Xtvb=aQgv`)V3w`NUoq z=rRUbbw{By0;y4&?#h)3neI85>xac_I^_hqVpOsU=a&K zDVxekj*TtVwvM=JH z=D8y>9j6zbL#Fo&!jf^2|WvvgGF)yJLyY=m<=b^=6)Dn=|DI8vS?t z9Cwe?q7Wys#B~S)TSln!>~&~`#9&$=nTFb&q#{^w3UuNmcut^uTU5MLL7;nNTApG4 zwEi6esYOsAtT~>Qu$q&f?_{zS`nx93Xt1q2&xD+(A=Y4jib$y1f4^x z=)cP@%y-Z#NzS#ac^aQsg;w%m$$Y!fz{07F_`np!$wqq`7mfEW6#o;<`25ed*K?wg z9@h@YNv3)J`)%;R4oBZUv>oAD-C5kXwfcqtk zmj6uqJpcDv=5cNE@D~PAPHm5;_y=}(jPWni$N%>%@W8Chf3u+-+*NBx{;!$a`Twtt zo&Q_S>7?M%S-dTsg1AR%e3JGfwsdwo&N0`R4#E%Yji3Kv_H?*LM{J8dEu`*$qP?6f zlnW1E&7Vh3w3ib%t;1N(4=;N7*BlEUNZ?s4iP!J(>boJ^fO1O`PeMDA2$Uy14;%ga zivz`|I8i)boGs25SBRI2*NL0O-QqpsW8#zI8{#|SAH_e5FzW2qM?6D}ihOv@^3N1& z#C77e;tp|-$nSg^?`<)O&xaw0MgA?0^6BCbae_EgTr92?uM_LUd&S4aSH%y-@5N;N zVTJj%5>FHRiL=Ej@iK9n$ZsPV|6}ocF$LY8`qpAs@l0{Jc)3_BJ}5pVzAl>e)RCT9 zKOOu|`o8$P3G*2$P7=*}=FnG5{)xzs)foO~;xEPL#ovpciGL9T=;(~sTGE)EqZ ziRI!l(X8){_+~wCun_Yb(;Fd95oe2LU2FJnmVAr&3-KB8i1@vjim}La+lbx8v>k zh2jEnm3WP~OT1rvN_<27L^SJ0BR{iFG}s(pSuy_-aj|%h_^9}fn3Lp&?5Ma+P?Ac$K(QH0u!~{1cRMET0iyAW;UhE;0Pyk^F&pfQ0_AD*JpDXgSD5f)3@&s|J^rez#i%Z27qOp&I z@)-L#ps|mG^o)HR$i_YnXzb%aZ|vhhHtQ9G&nunZim#Cf_nzea;wRD{k$g-v>lP!t zS+5xB;fbSZpCl6c=8{{AUBo=`EYYlIjQC?Dj~7eCGSS$@LAV;pt4QQy?BYOwwe*{$ zH+FHL-!1*mq&IePpnq6;V-E-NKFPmVIAae7`cI`lD7~?V13eb+G4;i1#Pl~zQ-)9* zri(o1vOk)?DuNv)pCO!F>5yHu+=rXgbROG_jZ1R~#%36UT}CeuL?jh-Kn@ zu|niWjSTlwu~zi#(bP%4RpbYc4F4PP1@UF^cj7zZcOw5J%ycGlOgAK^h1jP63)KtoU znYdQGT=eYH+#q?Ec#C+q=-H+Dwd5zo7ev03$$Gvi@~tMy|H>ZCUls0Kk*{ttUQpy$ zvy^WZe=go9{!)BYd`5ghG}lRp|2xU%JzK~JBy-6DrvG1Mf97hiABp-uiATg^qFGA? z{{N7i!0T1W$zrCMCAJfD#5}P;JVWFM{Y+dJ}JH=zAFA+^z6!*`vH{0vn%sw`FnO{zLoqBF#*>~=J<=v z#1>*Z(X%U)C%Hg8Q#@Pbf)z}!NSq)}5od@q#f!y7VvV>`+#p^fZWnincZ>In|Jn9q z{-$(~i+`A^~@@oVvKqQ(0Y zg!hZ7VpGxBHHCj$$>x3yvbkRa&3zd-T>j?%46?aD1E))Wk!bGEpubphl~^O1`!o1& zlDu8qCEg+4EqZogzLNZR@q01I`wpaM?z6zAlFj`V7T&(4goV+#2f z3ipU;?3qIUwB+B4dqs2q2LJaYoBKG(<~|NQEd8HFa~}u&cak04Q?h+MyE9yZgz{P9 zU~!l@MjS7mFJ35?i}S=K;!<&yc&WHvyjrXkZxnZlw}^L%_lggTd&DQjXT_Jr*Tmn8 z?}-OQ&yEe3TVeg1h+(m{m@9S>dy1!vh2j8lm^f0LC{7iN#Zu9;OS4e2XP0KV=Oue~X!c2dOZ-6mSp1WCNaQjz%&(2uQ9Mm75c`N{iRX$@ zu}C~moFq;cFA`^q7mHP*XP0J;WX~?mRg$k2ZxFYMw}`ik|EuXXDYvANh%>>zd$yNf-=eqy0GR2(6W6DNunh{fU@alTkBE*IB{SBP8?h~>UV^z799 zO7c^pXRqcJ$*+r^-J16$|3UmrtQWr$kBk2l6Yz%>=ASHbH6qHM-I~)SpD7L!qvB}s zJaL*hLo5^Lii^c+aizFc zAB&%hhefW1#`a1PGsP@1BIb&DVu5(3c(yoH93hSuCyQKXjrm<6)`~ZZyTn_>yT$v( zJ>uiyv*L^5KJhK_58`Lym*P?Jd(jTNbqN3gbr<<-(tw|>3xU{*sqx$9uG98w;paU4xCn6z8j8iZl2%e zaL1?jWn6k}Mz4I^xa+w{4&664IYB~9Q5eJdho+%fx+^HN>lBJ)01TR zUWFfHxe73!6|ff^(|%s0qd3H7#EV0T;b4A0#C+L5%+sG6@LKN<#q%?I^zrTC6!MUG zc_`lpek9P3hrNFK42Y*b|8B3J-hKM_=wYJ&`@McTKVULEVy~ayW3Qi3BD~tZrr8bQ zH``#ppYYYkB-$tJYwWt{J`4N(oMYKVue5S@yXk3HJ+{wIyJw$cyV%d>?B(HGHvM3Y ze)I=4Mu&C>!$ZP}S8|U&;IwkOJJ(u!^OyHaFl^Hg&S->=c=QJcerrm*gOM?>(Z}o=<(y%K==VjanXejmpdd^Mj6}kFND}@cB7MrTYHNx-n`FgGAN@jeULk1S7gLVyWC-q@3YfiJz$M~ z^+2dcY+qU|V_#avhHbH%oEy*B^<3uE;m+0A@#nJejW=0qhNs=w1Us8pdyl`^zA?Pk z?sZ+7y?a=cdxxOiuD)kqnvEV=Vh>E;{dzWbthvnHJv?;At`{?$tJWs2PB?3A>>iS4 z^+B8Tz}_Yg9Y|ZYbybstX}x+Jh(HQ0Yl2?ufnAz<9B{hkK|gAheY}Mf)c*n2|F$i( z)?SynJHxsAp+N^Sa-Kr_<)9}Y-)A+-tUuv^lR0J;>eGn2Q2kY_PQcC}jSo8L>0{8- ze;Dy3dfJITz74zoTo%45?Z)C=H)NuxqiIhcpO{!5-90M&RN^G;>XEtZNmx9wesE%L zq8z17pHY9nTHXF&i(VtKQ%q=GT2WemO7;o+wr$-#syco5vrhKzt(h2y7=us#fcu7+ zA@PHeUiN@2$d1+X2WPgCj|oE#<@Ed^)U_Q-mc7r({vh}M5gkyz=)Pb2O{zcX;WKt! zpUM26-d36zo7kUt>x<2a1&Q!YEbVc_k4oILtxaMx!gK3KV~z|8fn@4?Uu2+P^0xf>b7x&UlgFBRXZ5RJ z9EF`@=6+#4y`ZhX*5gkwvFK;=9kVxMt>pXjgCFd{as!TK*gm8+;GTwqK&W5yVTgkL zSones?8ovjLn@&Po!0zZhJ?Zm2yyub|DiKl@WA7QqHB=@_F(xtGQb`zeE)lD50Vjd$4c^iP#Z)u_Gh(SdSYnSh;mdj)?#5GX#UArV0{38v zZI+alHG{?cQ*0RE6l7+d#H=2dnBBN|YPl7AqOtjLPC-sqF(aq;VEKw-Y7ds*QcUf^ z@>iNl?ZLta`?1s>EPPFR?9e?}Vy`PBZx5E(8>)b}2TQD8Wge6@mZnmBu>6hfap)c_ zv3F!@c-B&OdTI}rE$pS#9xRO+n%aZq8j7hsSeCIysXbU4G2j2AJyw5--$`Pc@@(?YG0a?d`+T4KjZYU9cWs+J|Kvyr)rjJ9XYZESJH%jJo%z^Y&rM#UOkG zqPKI(DUEKzeXZRn)>gB%JnPVFuqp+-+259~P>* z3O2BFPB)EyBW@~P4X3?X+Oi|wg}j}*$4$IrsmsR=rGG%z!R*6A&5zK057)u$$3o3) z-1uq^SJ0X1&S*~E3f%Xc4Oeh4S`+)RP&W`a@mj(i-4_=^gP}lQ@cXtb{vxDfF|^Ha z-zy!i<5&ol@RU**0U?T;qhCSj#3Y?(L(>7bL7T(D;MEw8AHic=JSVeXZMK>QZ-=%D z5$3>kVnF9j&|C&-m6vRql0~g$CRyK?m}~*G>k;7=CSyS770^5mX|tECLCLbrUkuo< zX62xxj%kG=b3FRMN*hO~EV&C%hh;=QTvAhwUdnnNIGw?hO*M+H>&RBjM zn(c6~%r>UpHQz7Oa&J5PNm^z*??$Yzn4WPMYTAr{lJn10dg?Lg@Vynz?q_HJTQ#sb);&nzZ#yKhVxO6AOuHvmuCeBAlt&nedFKz?z*8&rG;3OwDwr zX3L;i0w>GVyC!ryEgx^^Jm_1#7O}2@GnVgx=PnAg{4_j&hU>!AOlK@_hvrQlW#dUCNn2vE6YWnp)XzqnW9hshb*L?G>z4jjat8qU&R7X7Sk~fLronohGr?8)+y>;Z@+~_c6JXO8ol;Kj5TnbPDVLRx_cqreQ3IvHHEdf z$j+YOr+Wr5o@P3Rm~`(#dfTKkqlEe8n9}giuI!8LoX45gv?*eJ4d=D#Q3!?e+7zB< za9x<1>HHR8n^JbocWYW)Zs%m;VD7ak)6j@%Q+NhbFl`FY1h_6t&2+NZjTR}p)%=s^C7#vtkJ3WcU9@zc9sP`!hC%%`;_hPNz7TTa7!Por7_IYYrh?QN4g;D- z5~eu(9tmgPZ%5nX)a4i&G6qgZ)KPF<{3u;%1S5qfGE;dLWo=;zMmo(VA)z@Xn1T4^ zaGe-pP6?JnS_X%7T&b8YYBt?Ly1rL49apIv5aT+yPVX|^3TQS#dJqoj*b7XT<;}d2 zPSy?b;`}gc<$g%t!l~r5Vac`9Smo24W_dVcGbN9;L&4xW zF~pR-08%?Rm7IT2?^+MoA~@ukbqmw7 z^wSZm49@iYVt5u&V9#F#&y{dp{B(Zr^Q?3=?O6R;lJlIbFKLaZrFS9z1{&b`%$xAM zNP*`wgWKb|E?g(3@y};y$>Hg}#Xm)~mpfTKal&UTZ9v>x;f$px;CYM!E$xBlE4WTf z<6Gj&)5BO=1+9IVojr?|xH7jXz#9eNIx)no06ih~fJ3V?-9V&^S?if@wVi#dpY9~Y z7{PQ5G3m~OH2KhUuCL@29IljJZt55R+~dq?IO}=?&)B$mDtgOMH!;)0<~~ z?2TIxYaN{FjfdfRhyr`#Wq4kM>%!DbXU5fs(0l-=;{)}s2^~tyYwVmWe9PY=)?PSc zIobgiuW-h4Yj|41bzy3zGnR{>=?RA7Oo3Z zGo3$^xvEii&42qYJ7<$`?LEYQhX!b^0iLfZ(3;y38N+pAGT##C(HvNE%pddGv+V3$ zw8VCAfw=jM-yHExyB9+03Ws)QD^($#_gxF0J;%-&gp)x zPZeAjre-?7m1vPNcjCjJ_`}(im;d8(b&GmldnWKWO56yOr&p2ZKd?9g6!8JJSd++Yk=enY^#jbAHKe z%l*-gQNUfRyMSIuVY#2#t!*k@9#1_3pL+(pG+!!BFa9aI`&U0Ud)tfsb};t4e(Vh_ z$%}q$*4B&tlAXc4J=?GNvGF4W%XtkOhx6Wt%l_+KSye<;Pii3Gm9?)$2TSNh;dBap z&O;@gH=>yotiBr}kY4cZcs5>$7Nu;w5Ir$vDp(YUA8a8TJGWw9dU#s$&?8bK7KE?#G)- z-6aE~stJZ_SEj*4PR28NguOfplUk*gzI#&d$HvJ^A$BPC_9yO?88=156K!903i9ZQ zEq}SaFLp4d*ejUelw2=KZzKuC>7!kOm89?CNjS&w!DPiMf8>V19XRK$i{7>9>C7pO z4S@~A3NXo!_`;15od5ApZ>&+qJD%XK8{Q7V^!)^f{VNFGS^w8t2lKWSHf$iUjKDjN zIM&k=UE%)4*1=fMkzg#rMA$LnNpo51=Xm7S!MFlo7KE4E1o#g5cgbte^b?3hMt{|V zOX*o|gsM;-J!{~w0UNQ&=n;vYEk>w{)X~HGp{m3QrhU#M5^&gWaY-FLQ$0O#i_yal zJ-l+n#%aV@IM=!`R7cM&Pfu(xdc<#!#^Sws*Sf%|qo*$%_7EdpHs0|BA8q6GVo4o6 zpLlxWbK@ODwDv|U5r;Fe>1prjIWATh?>WR3o|aexhdzIBX+1pKjWE}#qvw4%jP1_> z_N9rG>eSKxWar zMDG!cjd#ptzzuMWL2fYW@dUdS)0lX~c*n3qKZ0Xq-r)bQ|E&4sTuj<^gCme&CrJumU3=OyIb4llcvCLFYQHXH^a zk>`2u05-uf2FX5yW%d-iiE7lue9Y#j2xR%a9^l~QjdR8#c|#gaN$fPmEvuJI466-0Mx2XA!(-f(?oY-mHR`=I zaK@YH{?t!K_vgP9*d`iLpG~EY)KTCfVAA`m0Sn!2~IFxcIaJuoHMR3`~R#$}Q9Yc8c9_NPY=<$}&F~n*(*dW%!xz=K*j-CfS zAyh{XS5$;V>UjA41P=E10z5mx93vbvh0OM(5#t?0aIrNq-qGjgoa zjwWWnp{XNv^vp8)@tlta4knO6LjW;hMp~+5ZtDG z^bY7g@gvdmDIAwi;B#M3PlFLK&FJ|S4y{HUah8YWlAn-a2p>enc1HLCNCti02d9C? z!_xUW%nRR-G>q-b7G!>~!Jp?r=E;Qsg&hnnXFkTzlE4yx(KQ8H&U!@hC%=i5n)sNN z{=_%q(Vz54u>lFUz?l^EJZpq`82%E_2K0JUeFEWm#}MDbq4O8l(c_@R=zJm*&b8(_ zb@Xt$;{chO_4AgPS*(3x3AJ_fcx!)P`eIjW z&SP)-&c(U~!JEFA5vl2m<%iRE7aYn;G{B(_X?2{l-t;{$HGOgJnwq{#7T0n5wui%6 z?V>}^)}kp)AOJwEH<-ovnMPv7YN@P0apw3 zc$07vkq(Em+}aLyL|~eRxpQ zXDBis4Tr-$vBh}LBe-Iill*_ZbhI})PGA{W0IV&<6`t150nLvO^I_3Z6h{Bt^ZrT! zaa2WAoW7!rJS9VSex4i{V`#!V2OE>B{TRmQ$3G(9g#_Mt)mR=w+M)>P8>XFV@*T^x zOFXZak`c1-+8Exw+X;s;n}<{!jt;J>1|lxgprupsqi!@3u_ET@0^X_HnSnIsIm1|_ zL3*=PGClmEIUt)LVqIWeH9XSZH^{w}&82|XJLcP;EEo@*9Y2|pB@cQy6tZBa!@;B%Dh;3-HteUC5692@YB)k{_ND4TM7sf-5qv)KB)qk%{?4_>Hzk z;2|F-KO%E4$BD#L7=XROBrjKzg-nh5i5&Hxz+nOqd*PDNC^YvhSCX>eU#K>c5yyJFq5Smk0ZiI}2 znGcgva!^}O3*szIE+Q&036Qyme$eZnDUP&B5+}A z0rvo z-GG-M<2J#|lPipVw6pm*{z$_7MvapnPBsoa=11~GgndgsYy7>ER~3%cyN-Q4 z35^NU1kd%^<+EUO5gZCdtb{X#;taV1j&XQ&Xpo=eWI=qwTOv}I_pr)ONc5z@H>Z9% z9CoWdIf8A3>1R>U&csktl1YSjlWLJ|O2|jtCJDwF{kNES;|VS#evrQqU?i~oYgj;J zL|zAnG8104t~%MT7V>7T_L>;u3D%5b6uHrBRs`7bR|eSetHe`Io}Y$L<-t&TGc`Cn z54k^-nvnnMrqB_FVcs_!Ly^`vgF6iFn4JAkIZ|;k;N%a)^0R{~q*(r0X&~VSB;qO% zNC?S%&?RU#_79pN<&!iRs*!LR=Au~{P{CF}s}gjFginE@{BR`|-r4mSq8bhdI&&p1 zvsAHmFiX%K7K4>t4R=UxRItiOMy!K7EE!d70mLBgNyYG+j4HMdVi0t);m3f+`|ylM z|NP1$6|3ac&fFkWHCP_6Xy&G%R|a!aP?^c5Wk_P630#MYy>N#Y&~kPu1gA{!nU7;L>bG!+ zen|Nu$q?MB_98PQM)i(Gfq9owrefMDWimIfJ9ve}qY_Hp8t{%s~tZ2gRY7H{TB+YRTghs2iw;nOue84_%pOq=m%!~HAmT))H6e2hmIY)6L* z-UmOtfR-~yA%U6X*o?{>b%&QPk_-tPlkC(FbyF*vZ8N=hEtfoc1(nH>!{h#X#N7yo zGW(Zjf#P#c`ffF1-2fLj2d3y<0-i}bcX^@y!JMLJ`b?VUtwf|1xL84D#H`YCl_4JXwo6#{(=ytg?KE^xTD?36NDfS@wjQh^@{2OFC9 zCL5c{brJI8OYsN1}pDG<{&Ly;H)T| zR33hZIq+NG)REP)*_gG)Ml!pgGB79^YoUpm8dY{mnN02ml!2yZ(#0luVEm<&f#fM= zAUTsRH^~ESl~M+h`^v)`pf$z}j(hmPj6S@fit|6Wz)!axj@NAdhyJ_dHU{+m*&a`j+IkIclK6U__;d{D z8PAW)F#kipAD5>*{)c|Lp>RA6@<0CR2ssVT|M+_9X8ektI-XhhANu|CiQ0fZsN-pY z|KZ`4&Od_lfJ)~dvv~-m^N-SgItRm$&OadfdLGew!ttoaLyrFm>VkUzu*9`|cpyGy zU&qzg|M=@G*OaLNJ!M}vBcS(J8P2OE0X=13w>+R{KEZkAo-(x0E zpEECBTUj}~CXT&u<7E|7%ce~$n>M+Byl0Q1{@v#G?p9GUtFn4B0=vzroKx1VtYqrU z$uqqiCRdb{&X_r;%=*8>cFhGf|3ka8XHK0wy|nbOviC3SSy<%P;D4CIueOSH_^!f5 zeXxf-y0NsPW@b$>N>n(53oQ2@t|+OU0STkNcv@L`$-LRM#kChymDNCpky2b!I}Lk; zL%{MoyR!6r&zFn>En*-c^by>jEi3aQ%Wf3oCv01M3kJs4^SEbeha+yIL1EjS8xOmY z?z!PuZrF}A3dbTn!)|UaWqi5$;RvFpyBUKJe_kBE>^OYYOystU=Z3Q*6XO()ceCxL zP2Eg8oFBn34M!tx=Ae)hKFYl{+YY;Vc_BNT6>;C6YeVU}cVthDN4iIF_na|z%*78! znuXJmRqJ@TQ9PXQRuqOCxw-LhI8u)1pSUG;Z%)eg0K$&AKZbsX1tUXFz5ij%`&TWy0K4lkHl!r~EaHOay z8XYYj=>TSjV*}U+8S#)CZtY&?ptqXl<>s+3A}xJC8#3bV%<#GregE59+s%oG9QTWi zK${;#_tMHL&q_OtF?&$Nt>Jj{t+hw52dyPX!9OtyG9vB*J3a_ybF&MZDp@B>&e|&ff8I_ZHz3kxlP>|=AY?;)4Vz&LgPX1fI|1Aa(BQ+_Q&R>i-~qL!kV(A6XvL zs1e=`up>v5?d?F>F8dGi+8-#}Z~lY${|J=rXX}U#Kca1a3AF8xN5)T<-_*ukwiH9$ zYi@6Jd9#rk_h%d?{@qBqxF$7He*E9Xj~bJg)R`-yB%5JR<0>nGcF5lO}Pr& z6&}?+oZ)`Dq!8h*yUPxwL%B_&msy);dEJpJJ>our+C(EKVNK%Niy_CQ_W}EHvn&k? z$9fNPn+zHhPM=aci0egZVbf-4%nbK}csO=qIHL{QDLsxuyM5|W@OP)Ld$%Kf?xJ|S zH`H7Vv)l!RICyY{MmHe=^abKf&|O5$iPQ|>qFR*HnOGk3tD>$H`@Ml7D zkEPtMsVU>wLaw-z?N=?A373kcI`a>aF`zG^y}vxc{u!U zq+;88hr|CY5e|oGk*49+UC@eW;Y`jwhD9&J;A(^(2}gRc(NDLr(+`#b2A$Zn8ISQ^ zqi1v~H0PD2gg8Qmx7J)gx44s zc zt&yJ1%mR3Hsx0PoCDxQD6$?#~u!Loz3j#~pc3H)bm=Do^DE%FW>ED+A_Cv}VSnA^5 z+Il6*l^H=##3H@Ca_u-|mA%ERvcZyld|1hDS59vqR)RaE|L`zfZgW zn(ES_qnNB_=JYuwvx}$BE4Sv&p-?t0j!Q|ac=putnwg6by?k~FEEX3-+pA|WLdvSE z=Tut76;pkC$c$q3?6Nt^W7xpS6Kcw;YbKY@E~zM~?ol+kyt4ZIUXzENHtv*h#eFcQiFM@Tv(i(L{U?9xIKq&TdJL&WZ@nJ>%;^r2I zxq(yEv#3|Rb9LG5vXYvzW8&xF=0mss-KL^7N@v8Y%jVClnOQj}-m`DN9{qZs8}C+8 zS~c(Z(#q=EvW49$dPAkQX`TfeeRdgw@ig%knZ9z$OdAFYNZfEq0cPpP$*{!CwdS)q7&7N6OGZPKpt-O5R z95i(0oNj0ovIe?oCAB3%xxA`dY2}>S>XOph?9}4%C|vbSE>T{qS~W8;#LRMJBD2mWf|fQjqHEC4T(@vz z48sA%LGw>V`^~PLighhG)0y!FWu{-%AT!I#kQq9uWOiy2&zm!^rVQ;gr)&ZGXMQaP z1?pb1kdwN2cHiD5-dvwL`+T!L&h1rXdcC&7Skg*y$RdHL!?>i*F@s_Os(}>v_LkFW zHI>CPu0s)n=kSfKMw)?AhU%`M&TM~rOTLrmtbVVqhZrok08Gf*%JYk7mzdEtH8=xI^C4~d9CPT=F+@3=0m_9McO2E7$-=Qa zk;>f1WFO*S;|~YSUN-6+Q#7wb%*t#PBXw0->CEz(Wz)QlE5pz&$Kl8vrZ60F=d^So z#z9RPJCVz|S>nBBEt$>X%P=%BW}0b+ITa)b`}mq1LK{!M22x+dPg+aY(qkNH1cQ7!JB^$R|@NL`$rnPpz^z><%kp zm!_?Z{wA_2{M*oF?(du{>>=3`-9}D&c88%ELwX@%3GcaE_A&5=`;F*!nia{4o)&Y` zBTYhic2hgwZEm-)TjE7Kt?jl>`@j<>=3*WocpiL*tbM;E1$gk+c|j4fxmBFhd9QOw ziU<#xJ-kwyLmz0kyi*f~79@UKbTo-bU8QHYFQ8#Hr$3ahZ6fSSQ{mJ}GV$cZffW z8F;e7{91~~i2cRsBA;I}-X-E%v0nUG{8`MzFk<{x;<4fYk0xWMVZ%=WUI8r=AoGQ)`=ZLl9 zh2mx6I`L8QDH478toR~{GSn;l1IZtYpGyCY>-{g4im?UXNqOwOmU&OSiG1-K9@^g zEnX}AddVBayQP0b@@DZx@h{@L;tuh@NaXXi7Y~R(lPGs28^m}>7n_o>(~3lR7wNl;y`?{1@(^(piF9KXK2`d1@qFoP zB`*{&A(8I4;_th(s2t7@_O+ug>MuelKzk4 zQ_?>xz9#)!;ydD(3jbRCyZD31-}11XB4P%Kax@Z~OW#`TBz-rrNF1v0gm{KHPMj=G z5z9#AGgGXVe!h6I^uG~*C$3ZYdhvGY?-n;n|ETzk^e>68iaQj(Q~XT&uf%Vq|6a6l zLe26<#SF1EiS~<&$B5m;zT!afL=tv}iKC<+EuJHNiC8AiSNJ0F67e_UYH^LYmP9@` zi+4zWkN8LFpAerG>lMCTd{6oh#m}YRCH`IdgW@k@4lZ}tE_q@bv7LCVSSa=)QQm&y zN#beZ7;!2IyX9h~SR*bLmx-5>u=`tatym}CCO$&K?q>1N(mx~qMf%sp_oV+={F}I6 z;RnQ@rRVD}S&noP`DBYNq(4e55PK`Uzc@r3A)YRd70)7J{~YmrajrN|TuCDT%fxHM z>&5lr2JvnZcJCAaEIuc`B)&_+?hf(4r2kB8kp5foXX)KMq{F(KMt+JN!Yoagq?dOKdJC7;w$27;+rJWeIWT`aTf_Yd&T`CH(_G^vc+5y@$$t^VmA_Y zPaqM0sCbg}qa}|Qi%HliQ}}%87l})yUnTi+@p=;JZdUli(my6{5uX=dAyKY3CBH5H z7YRFGDExr*KZ$m}moA-T{lyj}(jBGn9@6&~2S`6uazY$KBHdZyIpS=ESBV#h7l|vy z%fu^5*ttf$O}v{#Js&4g-lxQu#8<`b;=AI9B+~66VfQ=9q2`{QG_kSRRBS7@7dw%# z(~pFm<0YT2@Uh}q(oc~*O{^r5Zl1zdO3z)oSf4AUzd`ak@lF!y?o;?v(myM{Bt19d zqMhyH$0X8yCVnMyM=r+urx?WzI?5Shp4eP$L&8ow@mT2##R1ZvC=L_HE1Y|B(SC_o zCe9J7#RVktxlrWJTuir0yheI%(#3wbNBaB4$HXVZ=f#)B*GQy$Tk`wjXC(67Eq)_f zExr6hVwTugY$>)C3rN`MB=(TLw|JuTBS@6vOz9_y#nR7^JX>5q!tO=l#p2ZpzfPcN=5)rzF~)`-+kK#J`LG6di02!0;%EbQxkRv7LCd*q227 zfg<+~qkNJ$S{yH)O~UTEB6k#{TtlM$R**=)O1w(su3^;QBHk+ANg~~2B<%cI^6LtJ zQ+!AIosvHlzaf$C@8S<)I{p}l`DKgwVk@zO*jemG!cLLM{lF-nB%UfxCSiAq$eqC` zSBUe)MdDHtb}kXQ6By;S;?3gyByOx#VPJr9sb_mddL zW&xCAViS@3e^K9xM7qu-?hW)4hl^$6Lh%~$4)GaryZDWGOk3F#D@5GRH|59eVnf`X zF~sGSA(lZy6yNY@@ffj4>?4jA$BXBP#bUWQORNbc3Jt8+wW_jKa-w{6$KM_9{_lWz%1L9Aj z%jbdcN5yQhiP%DHBX$rwi`=xC=}!~Q^GC>MOP(T56VDeb#rYz)QKy}Y#Y@G@#ns~V z;!WbM;vFJ4jHaDe#ka(F#E-;JL~b9?_+qe#f!v?#Z}_v;Av&1~Hx!6uTTI?$J5C@3IiwSY0I7XZx zzAnBgz9)Vt^1XuW?_J_|;y=WHiu^4V<7J4A#O7ja@o4cF(L85Iy55qH7l()=#nZ(J z;@RR9ahiC(SSgz4@vv{6$Agzh{~OUfkB5GZjjLQFSZgph@HjmVlQ!!I9NPMJXIVoP83VT zGI5SrEnX-t70q*el+!%N2d|O-dhr(VR`G7}KJiiUaq&6vC9z)IE`BKfm-walwfLR* z50O7dWIKk$46%{eOl&E(6OR_Viao@B;&I|6@jS6ioGDg`=J`L$agpSU#Z}_v;x*#+ z;w|E>;@#qX;8e2Y~YYQ?kS7;E-dY`5ge{Jju<)?qV--pm>5f zLOewrEshswiWOq5xKLast`Kh){~(&*1E5^y_W<`Jxi;)X z#cZ*O*g|Y0b`U#@-NjzwU~#y3mUxahRV){4#0BDw;w|F6;sc_2o{#cAF4=#s|AORq zMe|%A@%|?H3o&2MrCW)e#jav6v7dPOb9(c99(Kno+<#7AEV*2qB`y#z6qk!D#Vf^Y z#P#9^@m}!(@lo+{@fq<2@lEk<(SKh5Uy^?m|0#y`TskJs7OTXCqIsTE}G~0upiZP>kP5A7#BNlsSS4O8UMgNE-Y9Mq9~7SvUl89G-xt3Y_lh}jul#vpD-z@CSjmOr>Ec-N zY!dNiNS-a$NWWb2O7RA9op>9G^qV9iHpT$;+5hx;s)_9@d@#1@pbV{agVr9v;=|%&;>+Sz@k8;y#Bas##b^hw{25|vF)kK~eZ+(~ zQand27OTWsaiw^fc#~KsJ}5pSz97CLzAt_xej|P-MvnH%pDwl*<6@E6M@)z##dE}B zu}Z8JFBN|)-YDK8J|I3UJ}qu+QT&Vef%vhwSKKd#J9*`gi7mypVt28Z7_ksP%55pUbbxoBBH}Tk zk#Sqz(2s}9TO;Fi+7PD)hH(+Y!N{G(u3`_dx7c4CBn}pbizkbt#L?n-aiTa`oFUE@ ztHfGynYcn+C0;JxAg&YFiyOoT#Ye==;*;Xb;#RR<+%E1EKNY_ezZUn3`^5v|Poiae z?HUr(M85x<=QVu)H_7*ZlX0fs=#8lf_ZuXmPwaMf87PHbe4k(fr*# z>@AkOOk5$Z7T1V3i0j0=#Es&E;v?b~@pQxI^42ek$%2_lpO_pTsoBYmZDZ zN8~%sO?!$R#Li+@vA;M-94rnOPZmdsqecJsZWAR>7N>~Q#452?TqrIUSBaO4tHm|q zdU1nzm$*^fEIui25uX?9#qHv|;tugk@oRCfxL>qfuN^~TnwTjz7h8*Qv4hw{>@Ax2 zB5?dlK3N1-WkF~z4;aRpv%ms9ljY4 zO=>=e$72{jIHZ`jrTn{iT@ml_d_(9%{}YnuWYD)wRe!{}5Z6Ke#}6A01%94k4OT#h z^YMEIbTn=`S~N?0X>jA={50@dJXdS$7d8-99`G~XHXK_|V&(MlZA^t6%=h_Aa6kHJ zFJI>8=Q|I6KMhSZKi#t8^yuS<&4nDaH~wz#xXgOsXA((!tKj$3z-#q~J^r54|M+1m zpa|NV27C1=6zyfg`Q^J2em@Po*6K0d-vQIlj~{j&{6TxY@Aul3_As@Q_U=%c9w0y0 zm7sh$$M8S2NB5BE$7`73?ZI()yr&e;*H4?7>TBv)4}Knp3zlyX%9jHj%ZJB7$@0Al zKborwFrN*u7aY@meMx@~Fygz27l#tJgw1<(m@n-!&p`8A2WH`V7CQgq+iMI(Fy1JX z?*l&)=*LT~G`)HjR(6jU_37KQN1q-&`V__EJ>vX$-$gxo^zGX>9`D(!XaIoEl=P(| zMkTy$7(Bza)j4UGnjL2veb}pSXRL?$R=2PAp7FZ}*AC6QIs9fMk(tOzv`F+!6eQez z%TBe6UTK-J@0a7w*!8;%`>M0sI=eHX*4_onKi>1eB4=MHc28ni!tRi_*NwEQzj}|g z=-oZmtWFIb7uhE)X!y;d#`R71*wERYu8_KD{SAAZMPv6kMn{d^`?jIGzP1;QObo0q z-nAy%+B<5wwJ*mxV^?k#QcUk7u^9n?{9m3clMIl?(8PZhR0Bc zx-Z-==MEqI?N`g}n{G^VuEuWR%g@-gChd$}X}L}85bEY$ecQgA^xO7jI%&s+t`1)l z+4swU*S<=ta&NTuwa$F)tH_X1i4VUDt$ulT+LAl><+#z^*=@tSos6RrIeqH(l+9|r zC)#rIo=D5qd&0*)*pQgCw;?eSZqmR+X<|s?%{`%6xqCwCSMPBby@|GYbB~?guHlY> zQyV%CENSR?Z0;VnWqHH0S?wBrGqR?k!^mC@mriQm5FI#fkJGZc;r3(uHmsaA1#+hb zdr_~34g>o&L>ARHv_E!AL#L7L;c6N#9hkevKDJ#$r%BTr{(!JcMzY;|H?$u)r6E44 zT|<0epN0Z({i1lo@>%wPThaRS8dgkVZv7gjr@kZ+!l;tdpG>&R&K0}JK5qXL9`t}K{%Z_cudvcAg zeH&``Z|gDKI_B*9-=`JtX)$SHJ;yOeMAyVv^zvKY=taw!(Th4dBQZl}U4zkE-f$c8 z2w~LTK5IHgZ$IQ$-Vny<#S9tbzz)XmB#cA%y=^b-4%b9?ySdixaMQ+nU8hw&T5Hj@ zaIA|xknPmCejI9ZEu7IEOI@`7uc%Ef9CgHS&+o@DI{S+{S?c<|3(?!EH3L^!ei z3+JW}F}`oIoNHY8B17Ea=O%7R*f-_wbu;JHJ2zo|q+@1;LRcHzeKzJwdhTmqIaPnz zoqmC}dsQ0h>@-iDlZft)wfJ2ky!-OZc8UB%>qPOM;zijAJ1%i%g7aA|f)?=RGh2l7 znJx0ao6q(MYLP`=i>w^J?V+`(KgMOUr!Ie}1#171`qS>}_2(_9{n=Dr5b=2@z8-KJGp^-8>zZSZ*Q1}ja4?HoRM1=3k)o@ebT*PvscODnv!1Ju|!l zq-AYIhS8pRo|u_+F_ZRe<%v0six*naUKy_#LwRVZbKy%LgRl4COxN6u%&%W3iUTEvvceRPlbDuOz#0san3*+|WjS7AP8R zKHXFdvXgZM2Y(|GmewfA{V=x3ku&3Mt`h}Q(6 ztiQ6{B{BA!Q;?R$f<>pcWn;MotFUuVh=$V(5lp8X!XaL-<=QzfqNr)nd1>6bE2|z~ z(fN((XGRGYbAg``EOFH3T!8FnME{uf0m|68xXOw?+C&K&7gt-+$NZ7dxOjmT-7G0B ztCZ#XQ>-806l7*)ust7_nBBN|YPl7CqH$l7b57PIMt)Lhn`gaG@j25z{)0S*J7dCz(Zveqn#<@88$9jh^}d7hk>znK|NciMV#X8ty05}oO!d1Ean|9;A|oV4q3hV2yOSz{KL1E3 zI>%{dUS?O&JO6U#SLKKI&u`3DsCLqyGU*59?`Qt=94#e-^G~Jy`F{N2`G3dIjV|!R zPtJdv_7*yM&ztn4@;kB_FZAP&&cBB8VkgGNaSF!gx1(I=M9oX~3MS@rUPW(naygaU zf|s5A1PyL*nsAP|1zVl`ZdBamWWJ3Y+=3n9{7-4(J}0L+n#?WO8P0!+HXd-&`G*Q_ z!PjB5Kc|A%Np)y|Kqnbdox~e>;m|Tf$g?-0-W;HTs8sp=d9R7YbR4#+NJw7~g<1VM z3e9B3^1*qDs{nt+jPjmd^eDUK3{y=I;Z=9Z-zmE2P<8&=I_D1LT2BWK-mZhes6Z0E0{%@UT z-h`Wx{{!t^=F3(29U1?3zPvD>FVT!%?&L&FpD(lXhcLqLot$PyvC7VWgfXu0O5hf( zxAT`V#+9B4w_t;v-;a5&_7xlL{J*nOSNV!Z?EIe?<7!{=B;G(m#WlX-c{~4Xj=eSB ze8h0It#lr#St`?}Ej*cpGIG?DJNk0I)nadStrHysMgAaWzs_kzfo;BpZFaNM+`O2w zV4;=HRh@z{)y7I^=WrrPZn-zQ#BsS2wBo80z1GQK=eBCWmbk^qV6I;Ncle2#Tah~v z)eeWKYHf2FFrym-Y!m$95YH)E+njvOh*8gD=?tvIY&cKmuK zu-ddjK-%w}g0_fd+tD`A#@5=6`IkkF&c;_bL!<#Ntuv2H?vsH}MX@`z3Y1VWp-wJsc8C=2cjBO)i_I7_J{& z0XG4)YfUXK$Uv@e1(inEmMw4>u`S1FpluUQikP(;*g9RZ3e0jP*3c+u=~w#`e+KxfyPDtLzDp#`ah{2R-0)ure}E zfD*@=W|o^hFypw40U4*{;^IOfSU$sz5Q#ecw%W}eghq-gZrF>PmTzZdcu8$Ui)9^R zDc!bD$)!G{opnks-@lrfdq{k|nlqJie-t{K8DcVYM0}hP=Gty{(0*gYPxDL4_)ScV zaH<5kO|4ESW?oafQ>K@9)3CACEEy9;XPNNlMJ8`k6WVH?%uO*`sIU@Ss;(08XGy8_ zSX-DQ?Y8M1(4UyeMr(`x#j;PxU{j)`N`F*m#A}^}CBk@6>vo0qiJ5+TbjoaOH?apt zt{(~m?Zci;(?d?=v7wwo$|tDn09~?u6z}Muj>7>TOf)P<7a777{ru}@vyH85T~wdk z&z1rFJAE!cCIFER`*4V1^J;=u2)1=5!2}`eJ9~5;gd;wA&|tT3!b`*7j9P6yEfI%v zt+`8oB{gr!+W(8aHvz1wy4J_fx#!-S+$1*y61a>S3@9iG1W-{ynT(1|GKm%qAtaCr zNle0|2-LX_6~z(MU>$3n>O5=Jszt3ct;0|G{K5A zmB5@KI)gaXN-#An0oh^hX!lIsQ`35VXxQ$c{?l=yN^t~B(GMpC2BjNg8g$uVp8JC!f@D0y;xP;c|GI-+ za4b$X(i)&E@R5Wwa0cFSE87{!vr-*N;3f0DnJge*LJ=ek#Tj@@qU{Wfb$kLJ%8k#! zWXC5&aCLld4k3;+@K&yDXCT+{dGXl%5Mdvng9T(1`dKiA5!AYiHNZ>)n+DPZwg;p$ z&2l7aU=eZD(MOBMREDL*PXtTH4wfc+C;Z+ZlMr5i8pn_$^L! z2Ld});I%Zj^I0aVm-FJWI}>@L-RIjNj!)Rvf-?yGS=y2^;QHD$4&{2B$ck_tPGr^A&cJ#{EN^Gv`;J)I&cJmz zkuTvv$8T&RdRASX8MqfG3P^a|@tfNjc+&Vs6J9a?s%Sd{A2=enodFJ`z*~g^ zVxaK#%lBpzx?AvQ0w-ED8G#cGN=k48D?RH))1!$UPX~ff&QXAogNw^u%y=MAaKVQ% zA1&m#HbT-PCc_I;Q4&XH1Wg+Y(v6^LnGw{oGHV32EYBK2xYV4#IEsAl2m;T*TUwMg zvX&NPjjW})StDy{wEZ2(e`v{P5&jw`M@>AAE?kB+0G_yTMK(;hfCfZCI|E!D10uJb z0XKlq*BR)B6Uhl2H=gn7nawX&Uo^Bl3foq>BD(PsBdH<}J7aIgg4vXwS~ z+^AW$yqy8g(}-zn=eXhNdxvMn4N`EhxV!J+94tIB*o)dTBd4_>Yvi=%W{sTIsEwRk zOzm{Soni9K$eErQIjt+RMo#PUtdY~&)}9#_$UQSGkb7oWAot9$K<*qCkKn|NL~z3b z$vGC>us9+!ELN<{8Wt;-XAO%LZS5QY?sjr`rq>^yxt*l%vgisp*lM|!@zl(1YidSG zdc1HjxLMH63WsN8vNJNJ_=8~)1`V?*Dhlbb2%m*B;;o%RWCxFXm!m{3%pS`)c33z6 zubsjfn9mgChn*%&!w$sW!8jsk(lCy_gS{c7!=3@zL>*;Ys0)ituDks5juGJ|epV z<%w)JhQo#n^)3RR*FB^e=3SmT!iOM+!;2EivCceP+wc)=5KeUB)$I(hsqhq>xvGbO zkv=%fPzn+R_XK|K?W;q9u)$FZ94L{^OC2&``yx4kO^jRZMB?92Rj>(s$gxM?u*%@G zJMgAJ@yzUN#bhBM(V+-@4guFnfrwm|#Z8^AWQen(N=|7ljcbA`uwq`DH>_tngR^kr zC4#^wB}|UKO{a~HPiV#&^Oky*73sM(;#Ibv1@>BtYV(HnZ)cFb4|CTVl%NYrh_Vy7 z(~s49E&`m&d~ZfLiBVD52Qhfr{Wx18WoFW9U1gJ&yQxoSFPw!l<{isy8DvMqGaun9 z3(g?0yWxqzx10APAeaKRX7G8On0yH@;l$+Y+l;i?@d><}$GjHSn!&%~WMO&by5K~9 z1YSLrgx&N`iT(UT#w12w?IsE9)~NvcvA_pYJ9)9!5hP zEly%5oM=A+3uS7*|}_;51YYHmv+|qF{5VA*?;`x3&P`we1bxFJdtP2JI-6_?UGR##BoF-QN9Mv8jkk zh*CH{R464Goh!D}nS&z;qK(k=JEwCzt1q47L!Hu-QEPfawGnju4hO1@ABaOOqj#W% zZ)Gvhv@l3b+iBs2i;#^ob3{)D`#M+BNklej1W&p|{A_{n+Q~$=4EP1a4;_CBk+lOq zmpH=0YsU~Ly6_ZYy@gj99w$DLC5?EiRuZpw{K-UD`c=!rV)jM=Y#iufloDs@hsQVEKr>2F_W~xTLhrwvxmO z!_qo!BROY;ZM<84>~L&}`|YNdIfyK8Y-+44=Pr(Ou-WgTCG+d%EUu|t$R)}D9lBdr zV0+yERGF~>^&D&!yj|ICTj8(<|H&M7*eco-^$^!a*&8)tDxUZ6GlDagS9ON{fJtEkThGeDoFDv($+!u4!9{5PA*Qh>D7%2gR`R!a7&* zp66rd?jSyH~RB0?P$RCN&5{3%NYq4GJ`<52R z3gZ>n`8$Xo5fu7eyW$V_1oulP#Y%$fR%37R;1}51eo-lQpbwr$2s_&6$NdWICteoA zj`Fem+A{7f4rXv1w-*1q+aU>R^w0W;;tNvp#k6=+EZp{`lFU6Ta)z6!fSMYoE4b2j*rpD9() z@-^8MQ)s(-*wwMdEL9!KR$CFCdAO&&;*@Ow@$HcWw9itiVk!=$yiP|Wmt(p91j*U@1RG85%bw3(2D{k`^54G zGOANWM|qYxOCIBT2u2xF1o6IIi&GYi#Vfl7eQYYhh^%Ir`(h@@iO=~*XA>5!)h`WD zr*JlDt{BN#qw9p8oHfYr=cdGY{V2l}D_EJo%S}&-sORmNQ9UGX@-bT}k9YbJwbtQsoL%v`rFqo!EWT|X0tu$b;5vp?g0 zkmm02Qr}{8=yRx54lWfm<_9;dM%{1;&t{$M8jiv>L?9k~zLK^7vtLmfyzZ59j^4C# z0yqOI@Pz35>D}7X8;UP)YUVcTO^wxc%NyFNZKrVT)ZW&#cwV>>ear9>+~8Ht#uCe0Jq15rX}2>yt%2B zyN1^{VgvZvrlw;Wkk8nL1-5@VHmS7=q{i3EC z{dHTvQ(|!gs++w{eIu;iupv8lE=P+YaKR3XJCa@4v(WK zW#fFWrWUIj@TZc0hVsua?9)!mJv4eNHi=(W+ZtZc>ZLW@Ri0a^kE`7KpWPe1w0v=G z^O8}uO)anoEMGhvblbuui{}CB!LM&#I=sBKxqN=*UgWTe%kcm`YGF;wd@yQSY8Q^e zQ`^$L>&h4JQQurzzF_{cnwI+Vp{3oiP?00b9rr3V_Qp2ZQCfcq*vX%CmyHmLZfH1DbOHcQ!JjB>5sK2nrqv| z*0!w;3#yr+bz3%Im->iK4UG**j>lW}wgokd7uVPjLx^K;498rif3aipK^N6qT3tU3{bybcHPz#h zcu_+uFEx95b@j}NO^pkH_4Dx}fIhRd0b_4jtyMj&1mA=pQoE?GrV-05u zy@n$fwQHWE*g3(<8-S*dS$fg7A%X}m|E>2O(bc~DF_-CViAt9%sR}b>V=u*klbobB~W z*QP_YAZ;&gZ29Bryzts$h_QN&RwUPqHb;8ZNZnjl+fd(7H{UgPowEyew+Qs5hSuuZ zXNRE|i$)(`w=r#-BS!3*Y>IPfgJvald&KR|?EE%?P^Y+=8X z6Q|^!nsZwG^w@W!X9QJP=8qW$=^B1b@N7wBZ0`fhCwcK?&ZI;n zFWx0u;&=5^L3h80-_!5q_x5*+?1DGvjz=~l>V5QOc5J{G?W`lvcb1UlJ~D z1>2P_FzeOqcr5+PIs&i6Y*N_@ydGWn)nL0Rq+grY4>!&1$rPWN@og#3U0?b?rdA^D zWr=Vp=W$P{{zNPZ93(z3C*$`Oju9R#oFx2~aGtP1xJ++ScO&uMz!<@I4_{xKfT^T8Je=`$h+P zsOT}msY2Vk2=Ps#PY~K?WAHB(eS`2B;j6;U!oLXl^Aq#u5^v&o;dEhxaHH^M;WNV5 zgtj*i(r*==K)0d3?!pJp27o#Glg}+CBjpL z7YMHw-XZ*n@E5{&g`Wyz=-`&Wu)lCG;X%UL!UkahhBMRI9wxxuMDHy;NH|~EB0N!e zp6~(TGs4$}e-wTpOk%oVetm@H!coFW!lQ(?7YXE7i(V_dLTG!6Al~*60lp~yyTVF* zS!RA?ge!&L6<#a+Sjaho^2NfQLfhj4{Gp<`UY2tE3&#r&6&@*EA^Z*z*Xk7EcZpc? zdXD1Pi@scVrT90AzEyaa_>YKwT=YO^ns?UgP2oGj_leN^iRdlDFT~HqZHws&gq?|y?=8Ai*k63x+XC{ow*_z? z@yAQrEpK-MB!B7;X=FbA^kkj^};p6lZ9sr&kT4Hg%1fI z6>bv#O!y1ouY_+3Z50*r`KG-HV|)&PTtZkRED>(M7vTW$2MLD>?YRVc_7^=?c!+S4 zkc(oN-;u%^VV!W1uvxfFc)XC0xlGR$(L@^g5<3aI3401*k#6z33Aw0)^23Frgkyvg zgp-Ab3%@0tFI*^W5{7#Qt`xmSc$)A`;X2_(!i_>MAY{326#htfuaIkY82^OuDdCGk zF6Ci7E!2o_3;!VeQ24oUn~>fJD4#3rEbJ=Wes92m;+G3)w#fAR3daZ!6w(Tr@zaFg zw0GdKl3OBNDO@9@ks9@#DLh|zvG59^JvSnJljvK8_Xr;lJ}%rO{JGGcFA;u2^lyZ} z7ye1OMfi1l37Ul!WJ>s)3G5}@Ss3miI7sxK!hM7^@L@U{$`hvu>EwYl4aSK_3l|8F z5w-}I3ReqH5^le@;3eW;CcH{`o$zMiZNhtn4+?)Gq+L79MLR!Ym2i^qFd=}+$Q`|n9JvH=qV6(74{I83i}D|Jpl5RqDKfv3J(+>BK(i;Ww=b~ju)ORJY5*> zVR(V)a1X;hDm9!i$9MLVJ&co|{GACcIDhkkH=WAor~3SB1Y8z9;;>(B9u5 z|GDTdg#q3LSZ*4T5<3Y~LVJ$`zfAOQ!ePR_h2w+=38x6B3%@0-7Saxx`JEsQ8^ZU5zZd>l_?d9~y$KV14?_B+u$!=_u&>bG-yl~m zx>7hoNb6PVp^Y@r-ot>Giry%^R`^5V?ZUf-4+$R?{!IA1@D<@3!f?;PKZ*|b4BR66 zOJRU-mMj-ORT~xwVcctUxOZTg=-q@B!lA-_grkI2!U@8|gfoS6h4Y2S2%CgUg~tg` z5}qbJPk5p5GT{}%>xDN7?-1T2d`$SHaQnRjUlsq?!p*`Dgr5rkBIGw;wqsnF6m}N& z5cUz$KA!TUg$D~K3TFss3+D>w3l|HI6&@#CB|KGlhH(460%?oS{C^^RUigymb>UmW z&B70a;huooMDyE*)nC|2SS&0R_7mxJJJUL(9oc&qSU;e*1*g`0%W3ttkxA^eSyJ`1e=!f;Q(ZlZS*?jqb>SRvd?xUX=m zuu3>tI8At@@Mt0ZBQXCHh2ImNCtNSQTzHM}df~0YJB1Gl9}#X6{!I9i@D<@!;opRL z_<@AwDHL`S_7v_S+*Md194g#bxWBMUI6*i~I7>*!56rJkxKg-Ac)IW`;rYUgg&T!e z3F$S0`og^epAr3Y;je_@o`LU*eqZ>BaEp*GC#bK7u&=Pcuv}Ov94QUsC76RB38_C{SS(Bl zcNUfj_Ye*i?k(I;I8GSuDL6%RxThdqo4g2~-O&9kUw|QA*A4CWCX|OB6Cw}_zhAlEf;XTQG!R!V;y94v3e&!jD4FtVh^uIC&bcFhFJLn)6orP~Dp%5^X8$4{-h#{q! zLOFRuOe7f>_B&IO@gJSZ% zJl3WwLiuYDkWW{-dQ3J_=hZnYz=or?7X_;ht-=+pHrQ$(MxOAyLyz@LwBTHTQMDCA9_uBQT%@1QjB>FN}C$s1Ud zeMLr-#YhI9u3_fC#Q26!*D!M~v4BrkWuE*D`ry;mktNAG7VQ9$-IKK2g-=%(+dFw7 zRgDo@>UH5FC-dq0B1^?ZCh+OXFk2mE^x)H#WI&&;FR_%9tzw`f$*B}SOf>8+^Jap< zA9}3H@aZ}SnVV17AqcqkKDrCT)IN~fs^hL?QRnfsCb5^r<|bJ%_;h7s$)_t7=T#w^ zr*eozCxU=aS1u=^PuJssN!WG3rDkV_nGvUB_;gi9xIFB2McWWdpROOH81m_=1oG)B zdHHm8RBrMR>b@s24l3x=bvX(JpRSHf`*fxKb)>8)$zhXozj|@^I1w$y<2go=SXSWZI{z%P8&B)m0$v)76!E zWRkzN!l!GH!;D5JS5eiAor{f3`*d}x#wQn3_!X6TVzL-jflt>5t-e!}gIS|Dx|ojv z_;h`XW&TY88-+ey1D5%nLXKeibbXJp@2a!Wrz;D@q+RU~drQ~D`G5Ec5 zSqu1dy$N@h2zU^#aPt9i|z^AK=ACcON@$l(Nr;U-ak*UX+ zAAGvHsbq9&7-{%)b@Jm=&$Gqh)78ZvoI0EO;M0|k9wTKFQ%6%CK3$#s)YJ*AAAGv9 zap=?aUdqF#t9{IcPgjmB`gG+`GM}#BrvmtNkt`g9<|AD!dNBk_{7vAngJy}66<*IrO^E5( zZ8Jhh|2r^j_Gd4&!HnsH}eqlacn;?<0xf?!RNnnhpRFQcAntGc_;nP(;0y(ncu_)Dd=ktpBbiJ3V_{%AMx{{!(J4nN)tE1y7^RWq^t`m^T ze7Z8Q3BoG2^XXcMW=u^-8FS#%b&ZL7sUK6-Ns%t@I!04>v6S%XN?|yzPF;akpifuc zCg{_ZKmOCFtEp`pRQD4K3#u-82WT| z4ES{A$_M&%bqx4)-IEgV>FOBp={lYa_;hs)_;h`UR|h^_T`n++&N~W9SSo8%_;e-B zLKzL8uB7)5>CmTZ0~jgZ0O-?|1TSA6Y4~(qVKjWYa#AE=s^HUg4NAj-B-;6Oy$Ot7 zoOS5al^3_y$!tsbbY-qC{|CcF@acLVnDFUJmVCEz-a-fC?;`MyjNcBUD_u;{rz<_2m`~T!PyzUK<;sSg-VP7OV71{DofrWKEy0dqE05UHQu@eY*0Ol}>bJ8jHHWs}Sx{khr!me-lFH zfj9Ak!s64Y1r2%|vQJ!J*zF`l(t-B<)bqo_ZnjdcEEmI!0yh-KxMZ%c&q>^WFwWxG z!#vSH98bHuO!xeUhA`9*tWun1d}8+>?#!GH#yOTes`r1~mD*1Ly@Wg#!GEMHOK>mf zJ8|~oAU+Dp`ukIZkNxTW{lk1b#Nq-#Xjk8#h+-^7GEo2aGKv?fe_=19^j*3O{ETkz zKeTKIzDN6g_e3ApyAnzIpK&6L1@g`v%MMZD(c$T7qYIrEQ}i7knEh~`VA#!t`Oe+p z;L{^qyb&k@*EAiXjo=G9{O}O?9vXqqAR^`IYV@#n1io^hSV%ODK;;pynQI$E1-aP@ zzUn)av2X&EEi^ryOK($$KlT<)%nU_Gb)@;Q5O@dT@4vk~G%ac^g@wY`d#3nbp)+9Y1B+6aslj3kQ}F+c=ZBH=mNYDCD{pAr-+C8b?fFiQ zKJ|zXW9O2XA1{g(_Ky|yfdOqVMFQW?w%2k7Pif1~j9F%N zHO;g}n0Xhh5Wiw$x4pUHKWXuru>kC7kQLhZ$!s)jf}3SN6^h8t7xuT=c3?D)qd{pV z16t#CFb6Y3E7=)RT!ynW!0Tu<92(%t{LEBRTWAoRHuiG1j$y%^ZDMFw7aEnp0*?k> z|A<}SH}t%(TEBL%K@LseoDs2IPG1{RKma{r-bSJxHE3~c@EvR;U1z`8xSX<}JRAo9% z<%?-sDg)4L6IhuM!psumx1q6maou9tKs(dyEDP5Tw(05iFw@0m6qx3vX2Tg8q-Kmv zv#h3NKxy`wp$)by)j5_!W9^Lbdd4&{+h7j=`nt~%ydZC>%Zopl5r-WRiuz;pxKj zh2IxmE4)YeknkztFNJ>;{zYhZK+s=-MrA(x3(ejK^jy(q=L6d8dw?g2zfpLz@Im39 zh5TWMdilwi*he@>xS!DMY7lRBG{A-8FB6_7yg+!B@OB|T5mW!W!jFX!e4`+r+cObM zh1{u-G(Ytcj}d-Hc(?Eg;k&|5g!~lGbo9JR>?<^T6VQu9A1}N_c%ASr;p4(z2>ELo z_0h{H(d;gOqeM><9wl5XJVD4$kW6=(@J8VS!e@l93;!tmLYPEHXZk+Ea^Wc9WMQ?i zS@<1czZ{poQh0!Him+O^QfTY>k>7gJ*9(6kv~~B0|5S7gW02*ub@jmhqW2WqdU^0? zimnqb5uPf%NO+y_9^odTty_m4Tc-~ELi|H8}Y{| zh&DS~(A>|6@e_nog|mcngtjglaxJ3GUKaHAqVE;jI%@ELCHgHQuIanN_lYRuUxl2i zNymstS0uVb*hBn&q6Y}e#UCMhq;L!o`OQ_l*}Fn75AxBi4SBC5&AFP`PdGq0SU600 zuyCSqx-hiEtQK7>)`}Z&UwX$HfbP1GgDFcEeu`RXkg` zW4JJcP!8X+Ee)?H56bacg$J)E58lTyOuW%Jd7O{mHmTozdvyJpH0^;y-3WT@ug734 zghv?1ew(fDQs^6j{z82$3-hJE1vtYr2zs;+;OdI-2;)|O5r!G}49486p-@&FpChvK zeQ{^(iUJ<c4-l8F@3GR%b>mZLsE^M})W`n7qXrLl zZ-t!#G~;+aCJg1qqO&XoFFZoIpM$}0c-#%S0U-fozC516nO(l8OEdMw$Mtmi-ar_A zxfx)`o6witr^CF6S;^gx}!Oo7j5Rp!ffXP)8MK+qeH{x^jI9icv^$(DPq6uY;C zLcmaN@UY?Vg_b$KX}wqFUc-mG^}{QVyOsI(whn_M@fWlzhNHI>t@JNlvn?olY+Fv* zrfspZpKgnnJ-N*<3oh|53%2?n?Xorh&z;9j+)~s#vi|5T1rtx(7AgD5wkTvh$U^So zCy^r9>U~DZZsQ^sPuxWUP38dHr-KO_a zr#Jdpbc56E?>BKvbP;xFFD&?|s35wo{pYa_Me84{Djxs(mho$1>rSn@zN*s(Z;$%t zVjChC@4V38a2o3M@V3ITT$CcOEP=oAvZqnzf=i(BLzLo^`_Rs#H%GnM4~;`zlN)9~ zlsoRpEx3An98N8lys#y@(ce&T=^4=UW7Hz|k{?4~0)IVdV!flELPwP8qn|)4bd1>? z^JhQQcbvb+lUt%iBcR8>^o1?CZ$>sy%VR9hrEKj4{`%13l@(l!l%JsuSst%yb2L5& z`mmrDWyzfz-;lF@9Io!T_aik$!{Y1mH^kQEZ73P)@0W94-n!MFd~#FqEf4(e!*eRD z{#+HWda&xZ@4Zx2h^y;Yz4hMfTL!IZd(V4lI3^=E&fxYHfdV?_x!w9{$3IvOcq|49 z)(AEr0;>$`FslUPG1X(0;RIvl+Cz9G#*Lh@Tl{hgoXVI<-H#zeV{aiQFcah{Jysbj zhX&EX)l9LV`?+N0#(sw)XxU-F_ZF--%Fk{kSiU6R~Q~qe2S%x z-po9>-UI6pe*+d4kKk|o2_*IduAsm=L>4Fbn2{|O&e@1qu0!N>XzLL7gwDhb$Qw6$V`IOf>L@tC%G8*d;F9sXGg(r7Ki((xj*XP;Z^0czYIz%Q7 zuB7std%Xlvu0uSVGJfs>;C5m-uti1PteJ{(!QeW?eCSK^#}ceVWEgp99iq!In*0_j zg1zM(nVb9*GQ>JWM;0V6gC49ybY!>=v9l@SI>f6Hop%ZT^aac6hDnwd>|BRkwVZqRDNnWKE*pVsn!$7}g=O zv9u16iu1U%fTwbZMOT8rIz*b)a~xhTm80jxuGX}iOXKgdU| zmADRZBV&Kk=MfZ->kuEMswevV(a3(uT)a$R9by+iq-;R)Vby$n-iyrwZ#3dC^}{nI|S6VVPge<1Ic?HZ}Pv z3;9Nuu@J%nx#V{!{F{Om5aK#SKCEFKB1bUSA->3r-c@JgIz$$TNxRw~_Li=v@eld9 zE|U<|iBa8-MM}30k*$+jOTAc!=qlu;Y;i5tAzp1&h^Btec&tNoG}a-q!dQps=z`QX zWWsfbE`3pI6KSkNd;?ECT!(lc3yO7!E`CUACTXlg`Jq(pZP+kys%)D)dg za2+BWhwBjOJcH{H@3HdCPH|ju9U_O4twUVT46qK7W5m`W@^cl}A?}16Y#riIRtf76 z=b~wB9U|_@whnQ3ldyG&9189ty$9*6i)17Vhl_MR$`p$}34s!SD>&?+S)ycx*Yjf& zVmfx)j1baur+1tE*$ZtjWBQl?$>|}D(%ryj#5%-VP?_#@m|^P>+aZy%xdiJFNnnhp zE@2B{9inT&XzEthAL|g+BakC29*a_acdps8b%>j(>JL!Nb%-RWY5*Gs>ku6sPX&y} zI>gy1ovlM;U@L@GY_|@P%hgghQ55SCc{ih~eMw^-qPvdK6rBxn9U_If4zZl2#yUja zCb$mqS1dKwA-Y-|occ4FCW8OU{rKeVFGP7S3z)*-q9w=i`O<*^RY(aovR zl*c+mM=wv+GC!zb=*gC{BnJ3mE zItJDuvQu*%qGMnk;&?V7)*(6u)*<#~60AdX46H+3M+vM$bh&UH;@MEoQdyf~9U^HK z%4n=ZB;6R&;X1@iz;J7lu?~?0+q@gvhU*Z2U^Lbta#AE=s;~}`7l#8$v|ESx1{l3K z>u?<+FK(}qYzeGGWUem%55h!PhscGsScgbfZ=chE^=@=9F6)g&*(UI1N2w8nIlqTo;(WjO zQE*~WvSLyC*XvP~SRBhw<)d}KPm!ir$z2d(>wbpDOf<*3JPa`|N_+=7CXS7DdEDsS zRBu!~(Gn|eH~9iDrwoBaYb^FO1UgY=Uq6X*`TMz*id;X;!>`2iGgm5(9Kg^7u&QvD zy++wlovHp<(8rMX2peYq&Md-}pqW+KcPV#37Z&pgoUBnlcpdlrF-1(v%=q-${}%}O zV~d#fV+3hB(w}wm#~E)ain9o3f7Z(%Z)sl#{d1iC;AY(O59~yb71c;Wk5>KW4e|Uc zYt3OO!5%pK&BIRZRmE&ge&gqpYQK5dsl6&i7Tq`9NmdP|dXe>4ke?WfQah8y4?jb3 z_L~jo>Ha~ce;Mc+$AjEKC6p^dDd~8q-w`I)gS=b8yA&sQl-r5ClhNZEaYCQxA8hJU zx#$2m`~M8-{X?wfR)D5onEpN4A`^^v9_a6pcOT^rHQpnjZy^sY3SLjP`eEqz{082? zkS#aa^0)}}IppOUuN#ZHt|Bns z7;X(y%c2ab;@7Q?kM7-0VmwZ?1Q;WGx09HdW(@D$&emXEodl9Vg&mkrgTP&ApEb>7 zlgl7aq`6^re0=YA60_0_C?PQ~%|N~+_`${{8PU6)L|dAHf*{=SU&jN&Vz6_oMAj|n8s$&ybwIYc!ueZGvE6(GVpls^C6!P+_jw-h-WCo za30#GgAgwq&rm45kR62Bs_aD_m?&?uT%6Vexen<;@M=&N+gB6VgMIHvf=Y2qR_enc(c$2A{2orsSOk~) zh^*ANXQiGRCWUewOuH5*b}A*zvz%uW*ek&W(~da*VwW5ZLdUe^=OK(4gYcRKr+xz9 zst;@@OK=66O1Qn4rD{UO6ZuaO^>V&}P9S39eYYV0M6mgR1N>iho!y z*P=%f?!<}GYyu3od}m||HZxPOBQpg%I#aO2GX*=61>@r$%1Cf!JTjanP~5P$pgzdV z4h&@;Q5*yeCmt-}J2{$fY z)Q5#-gm9){{I=HdP$ORoZlPs(_$~nT#5M%)cU(f$GC7jKy#H?ZW1bKQGt0HR5c?#i zic8ZsD?Y7;lQzZ>=V#Y%`P;4?C?DGnx)8F$hCMcpd&zX{NX%}_P71{vS2Hl%N<5vw zdKjO9Mx2%i`v$Wq|B92_2xE_D23>Pjrf;)~3L7uX&J_!t$cp8P&-*sAxqCGOvvA_} zarf$YC2lYv*m3ZjLQn(Too)bbP|Sa~LhXZA&1r7}c+0@_mxp5UZh_zk0B;molOpt4 zI<6mseuC-8;Ee)RcY!kyWaDqRqDlNy(cNZYq4}P-> z+n~mG;SQ^|zbdu?ErzoE;6xuO3W7^lj|B0KXFEE62YaRlU1PDXvD~=7|KL5aQD0vK zyY3N743Fgo$8qPrzEIbF@L(juZi2bNF^&g$#&sZS2RD^6%}Z?pa|8s?GPb#fNjaTbD3+lvRDu1 zInvq;7i%Od!VM-nl?KbOiDGH26ZWBmYVL@M?CM=jxvOiaqS934LsOry@EsHd%ho~< zHl;;DZO7S;%21FF%B&4`RGwI;2ht_MM!DFEb1>@0JvobkL%VXD!~}O*4faA;o``FA z*vMGtpn#h{E-OWU>CEad>_Yj$hSe2V{p$NLT3L{_r`C>kN9?%HY(7lgDq#oG+QxB9 z1F-G4PRy*hw;jv=q0JMau+6RacUB%WV)|FvM$y%m#wgiVEB|GiCuZ3t{f9PBM2qe< z+>Co*azdN8WA_>slG|;i_%+)m!pg2~`oe~K8VLR0+dy%Vs=mERBf92xJ1G8BMtk9H zFJtir#T{%F)7EZjo4l+|7t@A9|KQ$=9St5s!?AfCcT?;*(rcYvs}(dfwE8dJXwim_ zv+hanBDsUD6{|TtSZB_*#QVlg7P()ev-C8x%>TYU6f;J#|KM(lm^n2RzjjZ>j+-f_ zr^l>K6yKa{4VE;zTIQ*_rz0m$H!f5~h*LI6(>#%>Z zZ5PcoLALD}*Bgfi--W(r-^J#j-2Y#@@8V8j1q?IqdL;ih?yJ}r<-+@_y%4AORs4z# zSvZ@2o%NWTMES+-pRp4g#&q~abYI~C!b!pzLVk;&++1O!uvPdS;iPi}~iDp@@Bi1BFwBM+^CVgL20S`2mUadf_!f`wbiX=S2Tn_*x$KMaCkW3LUM9Rz_<-;k;p@Ub3cnD3lfBp^3<&1OC5ObtLORJKeU5OW z@JGTK_!*n=H9~Vl270yVbA&et&6^nFH;H~l_@A{GI|aXgvm6%)uNK}Zd_wrL@O|M{ zq3vIS^tN9KupD0*sc(hwyFzn?2ma4R|4FzXeoLo(Xeah9(R58k{sQ4~!ZpHEg=Y!Z z3BNDAUHD6(?Xv-Wwyy>-2S3_Ve|O;?!tM9V*pGaab+T}pkbbC`exB%hA#GyFUn=@I z;cD@1-wf#cp7@swzc0L2a<_`UQ+S{FkBiG!*9x-8w zu)A?8hN0Fb%$sZ{^P-w0^!JjI6hL8^UC|@J|w$SdQ;2$q~ zweT#V-B%IMmFi4?h46aeO~U(x4+)+2K}Pwmxc7@Nx44?|03iXdGZVSd;m0ib)Y?W0QVMuf1y2x zfInIEG~u^|)k3a$qrTNby3-|nhVVk+df}Bq`i-VsxWC~eqV2f`{AWaOzt15pVVLe+ zAy?Cp=Ff1%9AUnY&K}9{Cgkc#(p>vYbXgHt8n{$3Lg{yN#V1?7lf|}!~F{175%=DO9q+G*X={N ztKxSTRtm%Y2uF$@E##78>N`|8O*l(v&v%Hg5xr2jNZ2Y|CbZ{2$e$?syTY@DT;9n1 z?i4;C{IQS=(;5G?kTwXUUl#sa__lDf@B<-!6*c*&(EJu4{Q%MX3ilTtC_F^?En&5g zOD~!K=|X!x1-(x6dg0~5YlPPex8JAme(@g`J|TQc_=514!Z(D!5xy_{qwo{q79rP# zvb?>7y9jp`e$&2$<0N;GaI!GmpYRCLwx2ojnJ;>wkZVwx{|Q2_KP7#k@G_z8cMd++ zqB8z*VYt8GOQOU51>Y9ES@?nQbKy2&4xW9eFWg_So9LdxU4**|Z9jF$?F{1kk>j{^5G!hi;ldCY z$745~=ziZQHwZG@=es7%3~{*i*}(-gp>8s6hs+2(pNB^nHwg@M3vaX{UfdmvI?zG7 zf<{*{eJmHPM8Y%(dVheSeAlde!?>pHy2=j7yFplTF z!cgw40Xz0N@Py<5c0>net~D89e|Z$)?DCzQRbO1fbopLH7=5`JV8?jq%kI-G8xLYu z_wbfOt`y8};CIH!eA({IGaMTTdKaVrjbuPasE=u~<<3X>-U)?(p&Wb;4F8Y#92h!e z#Lyx5iM+J*n|%(P&%uIW;p&_5IdJAJ2QFOumx6~Q7n}k_IWL$4uLFMY%=^(ueBDN` zxGI3Jfli5>^K;kw=O)$_eAKxhxGb_^(87faf3Wa{E#58PT3E1Wa6!&xM^>$`^2!^Z zdwomEn%B2P-#mItbdP@9B3oxweV*FC>fvoqUGw8@k6shsTJYKKTN7KWHs{4Jx;6fB zr}&+>R&5T(9ke-J1Ap|8Y|gOWF2YciwvH)!32NQ!CRuoOs`s3_4v>I4Y`-?F+Opbzb?LEkK6nWxBbN%(r;Vv$$OUnBUL}% zwyA2vtt>&mt%*;@ZH|nECA}Zn;D6l7Kj+qiHs>8Qa832xo^x}DMbj|fvB1yW1rS-xn7zACfn!Tb#GuyG-lsDhag3CN{^Ms z%6S^Xkr$YLLHBdW%8k*ne}u1~(S{!1H&zbKxI-iQXpVh$*c+@^Nf-2LFS4BB(&BLp z!-x__@x`1jBNgNiDdAX&9@+St>QEAOZHa~QI)x?xhe4J!I2 z_Rjq+^DbiE`y|5p&7r=1MMjfciI~_=WNz{r)Fm-eWI>V^wuw<9i;}ZgwEabvBzrUM z0V2C6cVSi{TAf5)=wOjyO!Fmy^rp~Ft2F^OI96sO%P3f zf|4X^5*J!*ZjuE{%-e~LB^!Gx&SO*XR1UEy-8aC-ejQ4ln^=)f~JqeC!+So5( zR`-f@Huj18I^SeD7bWW{e819mPhtx85|3Id(Z>D~l0WG~Lt5I{e?(PJ^y!1r!rnH? zm#f64g&FoIE=Gmu1*w~L|>>FKL0JO2co8)f_egGlb*so=c z-YMh=rj7jx%;;TpHrm+pS~F=^`@`PS^)CJ)AJ^psM0H|Rw=d8p1EPt!kzBS;Y7L?j zu(8*0N%?Fl*w~xHJz9D)9ya!l&Q0CLjA3K%=z`Qhb~V`8yYxk=Eyy$h8++S$95(jz zDGwWa7e6HR7BWr1#@;p_hmHLQY<$?*yZ8~QWy~Ko_S{8-Huk$xA8hR1R5Chs4r$of zJNfacWlRqndl!FjYADmg#(t!wpO`v>%?KNNCqFgSlljBOo{d8r`%@SX8~gVY*3K!8 zs|0N9Ih4%C{-?|UHufANW@CQ~8L+XRj2z6yp1)BgU}L`)RSme;&z{tYy?%}~3A3^1 zP;eJ11*xoyWF!lRi$r6ZSab{2mH4|O%nq6*N>+G1%Mj)CvD;>Zkp5sWY;Pa-LL1E5 z>*u79#-#otbR}S8|0XKaohHTwi84R;SxDG!N(tE5lfW2H@sm;lHukOsqp7!8f7sZo zM<7R5JQk(;?rWg8FmZsN+Y?W^sSChLz{Z{gRgGlh!p7dw@f2O$Bw%Ad3)MFpdj@ug zu!`N|xx|`C4o$IBhf@`7?0Gk%s>hiWHumm1MpL)2La?!?Fm3D`S!&qW^EN>n`&?!X z8+%uagHs!*4>tDSH+@r62LltZv40hOjJMSJtR-yh-GEz|dV%@D#@^A*DgH2@fQ`MQ zm#5Ym*=f&x_lOlTiXT_RQ7gPm_5|1RHyP3WJS3S-pKu1J=9I!RWFg7Ue+i?Q`&j zV_}Bzx$j6G`{1_`FkP^Pw?`z{*mLHCjlItb!Nz{MkwG*%3k*DujYG1X_>*(Y-;+gx zjr}9gvh!TXtuCE_CiO}?;g4U+ora+IJ7DF(#{NP`!N&eza?fxU^__kWUe1k38G+UP zvq+WGgMAPN_wRv-MHwH9zJb3ziX!u3`7`j-qq!!D%#WF!HJiFWGKkd0x_kjK8r+|a z5=QE=BAvfeqI+{KP-H1Kg3uYq2yAWW?MhOSPz4I zkSrR~Pbg->UxIuAXMYybKh(tdv(2aEoxnOA+Jka4!8;UZe|}T;Cz{-P&>ZRgPcvRO z%5lPf6sI%%pVa9?@cst+&y?eJ@h4lomLgb>vp=tmKgH_LpCLXZkN%1LshxTGXQOHP zAlaWEj{L){?OH(}Lmo$fe^^hp=L4YmAltu~a?>nr3_&^~*>yPt>XL|j91{L%Nh;>8 ztUJ#Bk0M9$_}#u7r?)E~7%obu_@SkkgP0@JDIAYq;+rhRlSuK?bc)|vipvp0w*oE? z$GZbG?|I&CZ=nl~KmaX`!#_Na-!%q&0`8lLe*@=0M(oZlg|>p?txd@$A`rFDjQ-rB zy~AXk(3DA>1Nr^Yk_`m48&3SB%G~z1Wc)iCr+;ML(l9B%%#Xx5D2%k^v%#5V$*r(V z6m?0D%DXX4x)=h-;2g+kOLiJ4K7u3f+mI^@oA1rWU%$5VJ52UCxR*kJ-|+`BV)qxo zxf9gwmdpyvQRM8*<}uV-P=-mwnunk5e~NPuMHp$hz6;LVF8NbvG4iAKx1PzDCYzZ2 zJ+>u;_~m}UDyN=@P%M0rZ?{t3AKz~M)Hv|A^T-)6}EHUs??$-AMed?aE9aI5lt zAh|cr0lR?UxBH1W2Qd-FD_X#nBGQ3z+Ys`PPbP|xjEZWJq=q`Ekl*o-Cqae$n7>m47d`+{RrGk9h9f!?hk))I+3}3beoCodkp42@MD~VC{Ic24=;nm{WH~4 zn;G)>_d}fi%gKkK%UY_Om(MEnM~MHPibApM7Gko%5`RJkuOt&Fu(ePm4-A|cMZH1w z#5stGC@w{V*)sg{5qNKci;an5`-4-?rm-d&hD3vL4rFu%n*?7;nTQ`7VtBhoqA2X3 z(g~^|%q39+8Knfc+1B9JRJki=&d6teFF&{u8isP;zsTo)ff44Oev4ng`F|J;AH2v` zKS2VCc@G;t2*Jp^es7=5fHRR(@LQ+ArTLxG44)Z+^e;kbb|@$PQnvKVp)_k1`~n`Y zK4xGIr1xxUt|V(H?+YM?k{E3Sz0rV}Oxe92L>+R2U*;q@K=)oY4012$6jH<9%l3lT zjbG&yQqCK;Xi*FNJm$pcb;Qe~A`U%!O7gwoeV`_I00m$~z^>*B@IZC}9&iO1aXPQp zLpcSM_4eVqg5ZuYsY`Z8cCtINlij6cU*rCzo9DKR+b5sp4ElNb`TOSwm~NvA=HhyE z0+-S8Vn~lHz~hyY#ay!7l%JpPJd5zQgN01lO7ndGkYe)l`+A2I4@SQzDDEJi%$6U4 zi(SYJG0W}>c?|zzKPb%B-x>1ho$@H(#Ux^x5)@;X3KX-XtG`=;%e!mLbp6}?O9%Ha zyXN~dYy8P*=@M4kOEekR$V zeC$uiZ>;4^k4b@PFsr1+EsvPXW5`#ym^UhL#c?&!y>=@owW18wPKfGp!{pyaW={r7~r&+h==~9D6wM+=qMT35I;MqE8$mAGhHX z=Q#`T(Vr3EcQ{Hw!2q8?ksbTT8DT<)5kjG_I>d28(?X$$ckXz|cQ|^3f*m*^)YH)) z4&z~Lj_G75f?3(}2?_S=x33N#mGDHxCmo*V@P>g`aDx8^fVT#ixZe)9Hj(z>AV%Oc z1&Fi*v}G1VGg+DUkWJ)!vk5%mFJ@&s15W#FIzgcJz*`dGySp6`q~O6)+>aAB@GJ%I zz4=y(^CP4Cjo!7LjL$57I)QpR#DixC43&Xs39j5GIy#3BcFo2)vJJ2tX8}Bpuk`vI z=dJMi_ibMT&Z#)zih^*u3!V?yXu%^1SK%!1mND5{M{cX)nErtez@XQ$lA;^;*F+^F{dJA2b1wpo64ar zlPs;+9$+X72}-h0_};e&yZ~r?!cC6*GeE>tO(U?$AscpyEN2Bp;3E>*Q|DQhdiq+x z(=JFw&$}SODLOKvXgZj71n3)qJ>jkd4eucv0oPe@7TfV}7My{|5_$}ly@JxBB6GK;u3 z!_tS@g*2kcr0`C=~w=#mPo8j}i>K*KA=5C|1e>=mEALm?}pTOL4+A(P+BmV3=RM(M$vm9EuTLxzgRu&6AEfN16dy!#`y5r84XyUpsAt z!frx%7-UxGqlS$*|LzQecz5J*ZeRz}Fp(nS=@=k?_LCy+1!&5VDC8US*zH z(@8YJtIQMP_hpOcq+>Al5pPG-bc{y$tJ=xsiCZK7+7XS621@&Og&C`utcvCreO+M+ z(=oWXNN9&2VLzIOlZC;fX6A^H%QI`Tiuz>Ke?4;sqTJzA%1Is>@;v|B2y*(!YL9GY zy4IPu{BTkUbp$@svp;23Bb%9?uOt3iNS$wz)9}}hY-UzrDdi-y3VSh_oXa{CHp9#+ z?DjLBWraV1AI5YjY=)UGY+yIShmocLo_F%T{Icg#Z*)JnWzrG&w<5#`0$ixKvoBQa z8&Z1yJ4og3hUx2`^(vpW$+b@@-8T_(hrb#4ADJt z95S4h(^nPY(Ksm+#v^D)b{fVpO}d96+@|wH;HfynVkh)@k=;g z!5JQGPM-X*z{xE<_^d)6+l%gy*k)|wux&#*#%Iff?HR@sIg_W4IBzDiB4}NITOoYN zyL%rb{BLkRpdEz|X{=qeWPY6}q#4)LQa3o{*6ur}xut1AOU>d^ZpPbMI$-&Ty#~%% z(72?ut?3(`3&CqZd1F&!U3p#2yoNd0A(lDKSzJ@Qu%WTe`|r@*x}xrNl~iiS-;5>(w{bbC+1J zL2#+lyEIl3yy=xVd!$(B zIQ=UPfe)l;1TL5U7Qrs$T}wul#QDt*etN!G>087$7tuEzvE~F9u|*N_&OuSd$av5S z-%T#*Ns{=~Nff7(o~now1IsKE@wb(JH@Nhn;vo2aq!eC)pejE&zFY1;$vN^S1eVxuEWBJ zOON%tb}fk|(SAd)N4xW{R2(3EGH5G})1eZS7x=N_crpA=<-`Z~u&KvcGft>>u87_9dmrzOh2tcSB3`3Z7s~bSps%?Gz7gI{_sMI-x{61uYc}!rfHx zqtzAGmS+d0@pQvH4AIW<;+;|UzCGwc>H5_^#S+2yf{F@v?S2Ls`nZDYrEZy4d^WAN2)73Z?E9bxMpY&S5frc(^s)4^$I?6{9-?@+MT%y zg7K2l(vj@qZ597m`uIrej32MWH}GJKUojFx)Ay^Zr%#$VX5x77A8^^!QdcvdbIS6e z)$?n1=%XoX2lcd<5c86ZoZPdPF7fw)6xffHkU{7@HH63m- z@38t9=V4|C``UNdm_FQLotuFFqaK}{&!y_R#dR$U>KbcTc+FGr3pvX3pY-eG9Ko29 ztd7!9^LK7e-oJf8(GAu&`-1A|{H(fuNn^eQ}yB{i|EB`=ESDP1;G0GcmRS|u%!+2St*om@jN_8z~dCgJ)QvF zuy@@a1*)rQT+$pSOYc=5P5|NP`a6D{(t~i!w1eO?&PH1krjUQquhU_bd!nWtojX|@ z&GweHG_=)e>O+r)E2DZeT*CrnHovBgjAgY8=XsnSGNWikT}=yO)G7^ib!Y%QO4TgN zY&O57aY<_(8tb2S@U*CF%O+oOc@=n&!27%TO+~C;mD=P5(9Sp1$E7 zVer@a{j!JBYPyGVvpyH-{1c9%IyjqZZ9{K6rg~9LD>~%jd2LP0YQvsqP0k+JSktng z)#FvGn_pVHkQc|ETfNqWO)YJu9U87<*|WV9qLVg!XafgiB}$bDM|DAJw5vf@WFhiYzFA;v^e1(uXl_A9{TB(Z7v3VgQ+U7dQQ`B#cZ44aOYk|J`nWk1 zaky~2aHepfu$hRy(I#9@L|x7lo+CV;2z~9MuM}P<{%xYUpE}duFa8svpAx<*{I&2M zBJ}=A^vA*oZno4D7j_f&6b=-Y3%P)a@}q@QgwutyiO8o`^a9}`@t27{Ubsg5Gew^x zJYW2F(N_v@6W%4fpNRaP5dDLiI8&l~2}{M_ zL-b&w?XQfs9i{k##h)lVO#C^b=L+kINY|wJ$B1_7K01aDey~!lA;kimwt*5l$D*CPMEVVV(F5!Zz`b6Rr}j zQ~X83jl!#hKOjQyjlu_nj|!g<{*s96`>OCA;qQbW2|pEXB|`7tgoQ?&y3BC8+>MMOi$ z0ui#9ghgaiajjYe+(5;;S8b)%y=rY;tDv-6we9CpmnybUts51W|MQ&t+?kswqE`Q3 zzwhJxa`T+`J^Q)m-nnzCo6r0@J!*k!XFV)?|R`i!k-9#D!iYF z{{33`gzzch^TIz1Um>F2*M;v3KPFQY>^&T!9DV(bG z8NxDQg>XI*UmWcZDAaKN0e4FUv)RF(H2kc~&xCZwXL`1&&^mqpi{|Iy)q|X=j6b=@W1cT*A z2*(KNJV^a)Asq)Pd;Ei^OFm0@fpDF0lW?=peBVa=*OGrLG~d4w|D$B{Jsk1ZCBG$n zM@aq(_Ja5oX+;}LAl8%U2trq2=58ATKJ0ab>ZKL_>N9*MCSiYNXJ9US;7N}IOu*zeWB3f|D$U@_2Y;*=x0cIwvaA` zlur^aCE}oCA@x5L(ua`pRl*yHIOs`8{k=ku=g&ChL;sxe(PfbNb_mV;2gsjErgI?E zvxIaDq+B4R;~(YW!q&Wfbn0XJJfX+WcdF#pJbgDvf3uKodo2H;kPds4&3g=>d5;0~ z`1w3OzR#79?sm+dEi~^nAQwrd(;d@C3F%Qsd8Uv~b(EJ1R}nEcbgiR)osb@Mly4K# ziH`DPLb}gU{x2bY<0!u?q|+Pa6d_&SD945LWTQMpcsLRL7$x~gA^qB^rz0ElR|x6U zPJO-PCZTyR13i|pN%x+cAe!>HJsHGw8uXs8T0d9Cm7XUo5cU!F6Al!X2uBOY3ccs9 znUZG<=Ljo>^MwnAONGmYtA%TXYlRzxmkKWz-YC39xJ7uo@NVIK!pDVMh1-SC3SSYv zE__S)ci}t2_l3KKp9pCZ$n!^2L1Kom_4A!E0!Mm*()$Rj^gNNx`tTjOgX;b6_!#kH z!hSwR%qpJQ%zwNi2S#wiv(j{8APom$S}(5tS_zJ7iYeEv3SnH{lW`g9SflF zx4U`-zE?oOcG(`sL0pN$D}$&tBGGIleR+a{KGMbfP;x)`v?hQQxg9 z(+|jSMK3)6;U4P+w#DOKp_gw#|F6f#_&V|p^C|;+>*XQD{r$TN{qyDzU#}DWdlqrW zwc$t1vf=~WHE0C<^X7tx+ejiDgM4u)4}hi}4z|ns*(T~sgl4QifB(GtSjL}k3;OqZ zqExb7@G%Y<98ZSgL4*7E8`KYf@wm&o=>9M6*KhD(WISYumwn%SjAIWr4JP;)JL1lm zaYwN93b^uLJ*V58R6E{eb?Z?2`A469K4(tG{boN1QzU5L!TT{M@*-cSy=Z`j+<^qw zp!uF%g~UMb4r2kJz2i@7;2I=h6}SfP=MDNbOkp6wHFyqd2vDEk8r%R0{DOm#;zYt* zQBjgpuz@-A&?iTng5(5uI%IL`10*1E#3{(VUL2QG5L`7QkP_f|2p-(=Rb&kX-@^Zt zYmvzgG(aB`ci^MYgv1>ffj$M?ftMm{BpABh8H651KSmEiH>PvsQU0JA`bie`Rw_q4 z2C+2eCwE}znrJO#!*Lh7F3c-90Q$ES^f+`=C<{r3JMaKDd9%Z!fh<;dYbV;#lRNNy z=rD@Hh5M_;V2u3o;r?lE2O_Z; zGKKqRyJC8bzcz;ZcXCC;9T*;v*3MK!?!fENZYqf#yFq2fh6`W;;(6gAkvoC0LL`O{ ziF)Jv6I(k}VlXzFsfS67#6G}1COk}Hdh8g?ad^1Ij2M5(4IeHsJH{_+;Ugq=i0x)- ziNwyan^@HdiQo?8>zari9v|WF!?6$8?u1mvIqR5FD?Bku(E-y`tPQI^$_xy0AjT1f zkCwa!k%!5^5-kii{zJmPEZ@bQs3h`958LMG#^eKN;fmf}u9F!m`cE00#2)JTjS z3(xJ!$r5)UD^BHW1|Di56eRx*xC8mMKN4OPxd~!y2FosP$2c2G=P;Id4dL`~)n#-; ziTU9>BDok8xdX#@W~umG8h3=j9q8ttlJh9X2kt;l4!HwgVSaE2njg`@ z8OQ4?4DLW)N`^adJ1YQpAg>X_9rz0>z#T|(Gs7KtDysx{;2cbuL+-$8D!?7s%j7WJ zfxHyllk_G!>^n(DWan^_HlSQ6$ZZg^?T?}10`+C3$~&L$nM^FlWt+@|@*SWscYm%z zb1~!g!RvCGC!=?5InCe>f1LL$f9yTKi3%q2i$b_>S~?m%}2gE>(a z1$UrU1X|?4LqS&G;Q}PK34=S3#uPahGi!;RX)G&H)lSOb4s_*|99o`)TXP5U^@qCM zaeH`m05@P%brQ3JJCL7dxbx)Dh$Rf}K=(WbbKYPt!5zrVBv<20r7*Yy`7uH6z&=a| zcc428mt!&v?!a?ReN%Gy(kTq?z?;!JxdVr@esBl67u@`u7nlz2Kv!~X!5w%$Dq*k8oPs-$GCO5t za0gPZ^JH=dhQS?p85B8_SQoehDR9pDB0CK3Kx2543+_PP)hU>&z#Yhw!wX6Bf$xOD z9rzLyop{#?gFBEXw-aCdg~1)jR^9e@d4<3oxCcsb2U6A9=54^NZY;2mp$P?fp~FUz zdX5nq(vXINnfRZ|HFzi@rUT&kBl&a~+=0CFfje*pN?nIS z>2e1~z#T~An1lGnc2)dFq=GvT|Lyo|h@#&0NQi(tuo}6*9asi!6ik740o(o120iMt1%W?t@u4&Q=&I*cm+oYQP905bJ-Kle1- z3Zz~*66zjB7W;NqNgFpi783)OGL97nxt0-+Q11^^zxZ5aD=MR3FZ0(LU8vnns zTk!Ycmb>5O_e&h1TRC9w&78ZYuBN#R+kzKWV0nDe(HEyU>FA4Fq8xn@OE~%>o^bTV z^6?yfp_ZdB?xsHPV%$H6&0SQpu(`0N?r^ifLJ23}C-JfAWQXjOjCiQc=un2UjJ~_M zDIF5g_9^j{Bj~Rgvb)96Ik+eKTvc3ei*M<5;+qMd>zlV@dSc&u*PEx6?^0|3tWk%~ zp59c|*fhIhVR>zNW543r)%A@F2FxBcY1+7HWrJLtJ$l-d*;5+pPpqnFZkm1Ms8K$j zsur#$2@fGS!__Q>i;(9k>A8x~#VXXO!akTRZFp6jGIhZMScB(8fI#mw{TIFTP17rJUHdD;;tWLYvKGg zcj1B-t})s|ru4MI!i4vz zm2lT=>B6=b4+n1{(D|nvu2%_%OHPN?>dY9gF1AA-r80~Hoph(7Wk%P#&2_e7FI^A4 zFYzlXgEJiFxS#7iR=%*zoQ@Vgot`HsUCOMoiIYc7C_BdU;Np^4kaQa|ZfWj$G|px| z7tp%e@`cFkcGmMys;gSs4Bw=Lqnz6rD4Hs3;O<|8G0KSv{lZ0DQ&(17Rm(GmIWKSR zG~)M)8UX*hYTO(a*3bcKNrlh#&+|G<%$RY#@>~jy=iB@;c>xryTQAZoCl_K8Wbs zmpf?HmM^7mtsKQXXI)%m^xDHULTBGH_pJDqX;l?YQcZ2cqQIInU^d1G~9|9Ii#0rA4>y81%QZA}GAEvzYTs;Qd?B|U1J(T76ZK8a1x@w31$ zS2q+^)YmmPmRB?n$7Rye(+_6@)8sm=f_@If8XsnHoshwK|`i;ssK4B`Vnwshxo8m(YIn{+H4a6jzSl`(5 z+s;2fw)x`J@6VS_r2?N7N3@Bo3BVERKhbwD*XyXkIcC3;I}9Q@MQ9TLAIb6)AYSDHw5e>?jc z4|jWa=u3Ru>H0?9JeR5X3W8@fD}XO6JlC|tZ71Y!m6SUYG5mZYGWC*vsLf()$Vz7fuq+7V_61<}>?D1C6~X@KWi`zS5BI zlKhD9S>fx#_l11d&iZnN{e|XNJm{xLHv2(CK2P!{;m?I{2|p6H$ECx1^MnJ0BZWr` z=Ljzs^0!2mGy5w8Uy%H!@IxWlN14yqF9MH}e7vw$xI)O+z|4Pz@TbE2h1-NL3U>-W z6~?gOS-y*~P&iyTNqD@lR=865BjHs-?oYt_j^Qg=V7ahfxJvjV;VnXAZ-@L(NdA*B zglm!Yv=`=LrjheT4&rrNZ&TqlMFjwZfBxONGmYYlLSD`QDW6UM>8I@TWp7>#wx) zo5uSN%JXyNTicD{S+MA<_VP`9Zv788Aj2GW!hw&7#FNKB#Qg!&X+k&rXFlA1O=z8u zX$(DZ;F8^EKD_k)Lc9L=d|ZzVeQ;oTTO~M5K!;gBZFrc62jy8fygndm=n(J4TK9sN zHUkQOeG$|*AM1tnacz0^RU__|LDWjch0(*C3||`8vp*mG6Mw}53SL?>WPiI2am(5Q z9owbeYxgX~y)uYe@1VXoBMM&H>5%>P#k;xJEbHU2z54hYgjWVp<4?$I+Y4UW#ZdU` z>*uSFw+XL4KKFQKSO>R-;?Klh@X~IC!e3tr>hsPUpGv*@`255&Tn`NN6Z@PeLV;;K z9uj)_Ztn2qwr1Ov4`4zb9ux~a0myb4w&L*jZ!G%9dExx=so3iu{hF}m8vrIuM1B6X z&%QAbebZpAM!tSf@~t<9Wa?x6Y}31j5Vf`(XjzjOQSjpNgj zadA8u_GxQ2wBJBC_r7h-Di1ad?# zqOIAZ(0aCJ;~3wkt=S6JnY1~l6RTeJ1JV!mi=MxP$n)+`I7^=!@Psg|%c zdmCByYHK#1iAh^CZvE!7HCx0wzoD(!5DYwFYsTg5vo-rATT9xS<*~KB+M1CL#Aj>v z4(j#Unk{43lD1}lVdlNtnhiipNn5jr*zVqK&G@~*Z);Z0>|bSTMu)Vdt(lqcq^;Rd zjyY*-_9QDy+M2Or-@w-FZ)hoDYi7(L_GN39isrwCt=TO0>z*jD%K-MNZRF(NE79Gj z)@N&W8_#mm)@%gJCT-35k?ONG+d(mDYjzQ*=ew~rqd)1_wl!PH%t>3b%PA&p&G-oH zvo)h9q|eqYlYLIwn*D{T-^$jk0Tuad&2DAAK3lUIcFJdKHiZrOY|Z}WrYCI8_yyT- zYlhFA7Pe-_?9pdyW^8zTwq{Mdh~hxUvo)K^{61SV z+H?7B&FFaPw>9H+)xy^7a#rBCHCsi6-_~p#tMuEN6;bh@ZEI%iWIbE6HMsdCZOzQR z#Aj=^l;ic;nsL9zz1o`L6`Rl2jGGSoZOvY%?6Wm97Phc8n~PGoA4Yd-)Z%W_x%}e70ttSpF+)&AK!FD{RfK=PdYa&8}wu{I+J-u|s}avxAw# zZ)H>0(OnS4U%>(ZtVN8 zJll#7(SP6aEMfhTq)vB@lZ^Gn{|?JBoDjp$ZHVX1KWP3tEy!G6eb0dDJGCRD-Hl5| z{!I+Y{8mrog8n~eMfPtQV7lDj|E?X{-b~H@H<*}xm!@T3X#&Z`yWimKf0V&l!t&M6 zG5^2H@+=+Cru*&A@J0MT-tKH4MDp(M_qfM=|8{3n_}vCSpnCRZRgxD9PZF*Yo+&(E zxJh`Gkl*!LAAdI`J}lgCcjnH=e!DYw9`@Uvx%05!?#!Ks|7~_>d^buvuZhBG!XF6B zgcU-*H)Vcvp9PxxEbv_E*9mC{!+hpG3)~|4E+JofGaWy;|EJiY{m&;d!(4X4!Pobk zR|db04Q0HOF`*m&Gap{dn9w>O(-^*QJG69kID&R)FNC-I345V$YloJN`o3#Bv~B2@ z7rc3CZHKlzZdnf^6URZ@B#wpSYHf%1+1Io~8-^1^J15rnRd#4yVFbo}Uhw+I>(6hO zHPKfe9(NM`4z1tUv_q@(jrXhU z&}M#3JGAq@rXAXSU(*h)8U5SI30LsW0qoEQek0Da!NvW*t{vL7XcM889olJg>^Z^G zRJ%i|)y-o&vwk%Xi_X1Q1nmj9Pp6N^9py`H&}>7N;pC%c*qsd{*pXSduLJ_26$Zk` zpr$}DRDwY|_uwCR%_^BM81BuKNQg5LXklxHv@p_~L(n$t%laXMLoR37l+84mgD)`o z68wWr*=^Uf- z*^K`ri+U@SqiK&=+G<3^Up5?aESGg&7d{zkaA?HH77d%S*Nhmnoa@;9%?^t?+$jn+ zW!EE({AI^O!~~IIs4e5pWr)G1tP<%NG!3Io88K#lLN3l?9Bqid%xy6kYr|6g(_AqU zdl;EuQ|5~4vG+}CCs*|N%ZwRdF8RwAA$KYbU*5%G#)h^@I7geZGl8+!(Hq#5xfNKk za@KdK#9%CotsN#Y65EEQ0sb&W%cd~<(UQquHXRB& z)|erKzwCX)jZIlU^unF*6EYcR?Ju!sWhrjYg0b6KS$TA@NsYwVG1!!GvczA;ic?FG z%tI}Nf)gQtzwAN)ZOTZW9*eQ;;&z5g9Sx;(7)!i{aC*4vGPWQmZOX`mB>plL5Pz9E zCjK&4io}d<&OOmlsDd_S!_g_&l(}NUrtB!x9mvgy@v?zUnOn9)tRMUJkeMa&m;ICC zBVE?vl#svdc2@ORm-~&F7dwoT{Y30lBNoK2=ZSkV`l%5U{AF%K3H~y7015swx7}ee z`f$Of%n7rhl30IM^=!K=BPRIE+^R;$YMJ>@>hr|d85IAV`hXellvrPm=%vg|+%?Ew zX6V~qP3NSLzwB;|8#ZOUg2`WY3rF;Z7907?*dZ2eZ~k$$wEqGBQIGS|1xan0bO8AY zU7Iq_PR?}B1#HUP0a-aSQHVBWi_8#$Ii1)LY|30YlJkt4-qn@U4FwNv%G~l9Ii5|~ z&+rLO{<06)Z`hQ%>HTtEqYRre)rvQJn)Y|7m9p*gf*q)pj#ru?uR+WOL_%)OPA zgE^P7 zDEP~?BG4iS9tyJh4w-1j@R!kvET;<>7x>GJM;WR*kuq$`Tsb9&I}?zjj*Opw2fn;g=n z%pJwpoL_SkuqkUa^-an7Df5HB>=d+4{<5u1hfSG#!OhRPm+9aybLEB{-W+LD=E_TR zxM=}x%DS3!4*oJyo6@GN$SA;H_G9)KHf8LAL;kWW*(KPNu?oXq_6MZUrp#4Z? zOifh>VEZ+K&BCUPcRui!{fZ)N%D5ASZ3luuv!zHRxR_J)GbD!Wo~V-iWpoNW==V^q zikBhPia&~f37fJgDxgi-VB`XSSqTOdz07V`0I}^!_!kPg|5qa3F+I98ltw4P9D2$| zmxZ#|qb^S9e9T|;l+XdEBa!@Nx3Qk(p##n_a>NR^VTKi<(2t<#W_M(_#aG5JR}A(K z@U-jll`)nFRUAhyn*v|iS%{b77)c$gx5u?-?e&o7QO7RW8-0FFKnp&M)PU`SX(`tPLB)>FJLA zct%N3hADqLOnI=cbRk5Y4_ErycGn;f_Zrklcrmp`hMq^1nvV0#OS@(VO zk#Vhl86O#+9>GUOV3sf8Bf}Dc`e*`k?9D37tVLv;iu2~u1y~IcR*P@&Xt_B;^eXrw zI~h~KPUg?_)$C-f${+ml8eDk$*~#YBEs8fAMiBhQAFmP{$QLZQ7S_z24X%||mRyFH zWj6S57A~r+vc3n-wr^r1Rz0Bqe*`<(6A2r!P@DWvMi)|(wFg<5vlO;t1$d8=QoIjl zvj3U(VfzWiz-ach2*v*InR*!-t*=EG*3#0*XCsHp8wM(0$|knoitB3M7UXK!&lk3+3G8u(xXjSL{W}Jg?x*L!%{}H)0{%BLj`3k~ zZ+2gN`rFSp<~|R9mwaQK*Kf=><}SE>@Qv{@PuhL)+r_ux8|#B|w7)7A9wFrSZR#fp zj}aa#ZD!+{3~*gzpIhco)I+cEY%DvT(L=f$&rzU#YX)V?t8@Q+{9Q;5`Rrx^ok|3Hu2b z3QrO8*D&V0QFxc|QQ;qi^sHsRu6Uh8EEEnGP7)q3tQD>ho-e#Y_*3Ei!fnDAg*%0x z3S)Q;#CE#~3x&glM+wV>4Z>4}d11GFvG54tWMP?bx$s=!M&V7uKM3Ctejp6t^$`2l zUYIW&Bpf50F02wR5}ql%M0lg{9^n(hKMVgZ{8Ts&ZxY%5vBC|)9}9maOvBp-<~vZ> zTi9P{_PIp*c*#?QGla8+W`9fMYm~fEc$4s6;giBY3jadHIekO8gNVL;BBb#JV$|Okh5k<|G2wCj&pXaamX;I2e}WH%r#f=MCoJL3tJquMdbCJHrK7 z`(E(UW0>W+<$Weevq6M%*idsC5_WIsl(xUhvYELgB@kwhhBD zyZ0UR_3XGd;(;grCH0-&sy^C<@fzkhIBahm8xi;S?_Si$d|vRf`n4l|j^c0`+l^2QPSOH$vgB@A7!^ytPG|S08O@ScdC?VJcqiKJP6G$V}t$kkHH5 z6N_arbYAfCZHIz!FIRAyi4_kXIK(yN z+BcurrTifpA4%?b3vhkrScN;@nf&CI&5`Xp?5f}?*8Bl$op&7P$o2MN!`D}I9%_fy zhu+P0hOO(rJ}^4v-3+Jnl5uMbE*!hA=laR-SZVz?m0mh+cXpp?yE87IwmZ1hUN>!r zb7RjF%sRbK*tPQ-IVGrAAU6|3op)|1WsnXw-zFPWl zsdI(3aog?=TTpMQ)#Ir>p?Tp;rtS#Ne{n}jrhUb>-SI60OCQ-2%xw3rHG1T`RxrBZ z#T}8%;N{zP7i{^hPoD;TYUb8GRwC!N9kB_hb%b^BBYPs5+jjTc(std8JJK_|U;M-# zC-cP}ZN{L^QQbFf+g-BdsXfk^oYHQkN4{%0Y-tQyYKIy##yFd|?H-Gk!ehFXdMTmJ zSsMbE|FUHC?u=nC?#LXo6{UNXTIlVREpD#qyCV~~?VhuxM=ATfZAbeF!Apjf+MByy z5xR2Q?)e-o`t=z4pMySSXFh>`=dk{g7k3**;$6ou2;Ujsp{;wyv-@Pv0G!y=`~H7Ps9lnt{hq_8_#>87(=iWmHb-i#xhz1~)ku zVeD+pjN6pjy?RSGv=|@r+dUEAsJHDtdrR&H_J8e`7k3;y<`*R#cXC$pQ6_H;MlvQF z;((l~Ax?r=taoGHAyKm%dl~~;#-V?BUUl>3uy~a3~ZQH#CXT@e) zBhf~n5Tom3b6woM<%vB(I|KR=(D#MD$bNiJn}nu#-L~BiVg&tc^xtShms*>UH@K#x z^PJ(Etlri;m#jVoEpOj)2+moMYkrK?{jojHj6oN_xMSdq0M^V4TOQgIozWhxlw$6N ztbcLG;2929@+)XPkkB6j{m>bY?+GR}hppeX`z^G7=!~s<+8FKdjn);cX!GzHLDX&i{I|)v10&Ws7rwZoBr|a7w%w7RKe#6~Gg8{F)EoCG zjC*9}<2bi|?Y7++KOcjX(O5IVL<+{g5#w*u=40!#-|UXO(sQG8=}26={Wp!=osphB z0Cxf01A49>wy9wKfK9!2y{cpYVBWGi9U0|cLuBr6;(wE=7 zvJ~fjle0d!F1PfBH*w9c%YM`P)j!j{duz~Mh?{IWHz~Wx+?!hd3)m^g;j_aj#0PrP zM)YM$fzU5;3l0RrbFU^7bc!U*p8MV&AAULp6%!s7VMLCH1*^#gB@w5iKE}n(5xk8q{Ft90Q=bRn*2b)sH!{;FNi#&z2-}871`DHc1Q^=e581%qw59i+#w>OkNp2AA> z%*Rvc&|*|Ph0YDEyyc#_uqoxnsfMS}$w6M&lycHCKEuBRPoc3x+S{JEqcIR4Pa!G2 zeLRJip?lwyr?3h&CU^?t7?6*r@CeqI>5#$x}EDXVu43csJ+3wf2@$RtnUx$LHYPh76Lj0-VO--4%b5&M<2DILb9 zzF<@8?TNdPnUg$)A5u*66!LM_$5VIvA*>46q19h1y5lC zhveree1>)W_wp3-Ivj;lrOiQ&O({1FH8OhlHmA|!DQt%UBzX$Wy~M{;cp7KO$5VJG z$G^8dagRg2$vtst6zk_HY{!Z5@f3!b-rA=0W3QV5%eN=)wan_<6Sp5_*p!kYj^=o4 zI3OQS;Q{QmZ%^D8*=rw9AuVtHJcUPbo%{C0tzmv2Pa$8p`uD^wVSXP^;Y7CQ=P8`V z41S)%-OSm#cWpTSquQk^!amF$9!F>dkVTcaiBiSo?xnL#0A0)!t)Qo;O&Wq6>rD=b34h*;{kYO z`5AQ>2y_Q>ZhsHmRvcI^e96DxT$iT5|5wa)v72$ipjrD4=WB;!W8^Gd_ZIoE22H^F z#iQg3^Ntbgk?}ktZ&Hr6Vtas*DL9xwJY!012kN1h1l`DQ_ZYAYi)z_X!gQ3%9Ri zgpM33n2MB=&YKx0*STXg&)Lj~AzWr+B;I*5>8JUlwJFNT!MK}*Sx-uCa5II=lZwb@ z3SBWJ%8|aA0_PItuUf?jZ!eCuB)FN8g+@3jvY8Q0!1k4<`}h|KnP8(%1oor@qCADf zi*cASpdXAMh$>t;vYBzV?8bJQwbfq}38m|XD zYNAuJF;}HHxJEIEJRC54-vD^rM5obFhI3?FC$QNQO!OE+rHM`>a0LXcMfl$`a2W2d zR#ORFy(yXm##szwxP1j9TtQwU(o8@f5m?KaIBe@!0@o6HLtq(bq4Wh#6>GPxnS_f? z_SpnC`%EvdTYED5Y-YdIWS>QFv(NUj8{|3Wxn^+7Tg)&A2i6CHm0%oZburF~#vt!o z!3Zx;2oJ7c#2v_V@7ge#yo&?E-7CB+!<6tY3zN+|6($=`2KU7<*?d!Jx_}-egS$e_ zt;SPUBSN1u^q!FH{jkoAm%6=wa0MgmG-j2+ewy}t9lp=s;k#G(I{e@Yufw>hvb#F- zcbhX`XU^hOf))XKKCClZHvtVZaNdI^xHA5;?`v>iH4wP}Anxp(=eee*QwZ!W&d1#= zP-Sw~r+BlDvfdD|@Vyzw<-qQ<*I#Sld$W$r=tzs;F!(elBA#k`I*oJ6VWBkwuS2(| zC7l`1bg#f<_fAN5?-+Kkz;tgKfjtdajmwFAyNQkv+{<;EH{}>%vZws=W&(PV3`St< zTAeo``XCMzCGZAe79ArcZU+gxTbT902z?cCq6uBm3Fz-jEC5rO{Yk7?ukDDrU2z2< z&%-M`wdM#FBJlQVB9_H@bXV(p_O$-_n;GZ%Md7V08R2%3xaDqLnNr+&GX-}<#}N2o zn1WA)X#);4pM&mwZyI4E4%Bh&Dn|7Ac zm`izfQ7D>na8}643PrO_Ks8~fM-j3)#}$P_?L!f0(wv-lDB{$_`xf^Kg;Kg@L7Rn0 z-}WeO52K2azJ+cgqKG(YMcJXW6np&Icqp7woRSkt?Gy?Z^ga&NwS~$#spyE_OD6TM zS?{zdavEnk?TVcGxU;0liN;O52>)|?JN3XgQc#7{#-22(H_F#HqkMK8gKLaKT*emQ z(-dRxQwFq0NNEdwbSAPbi?c*@7@}>85Nj+#Y)QNr(nyH)>`FG3XDc-&S!=G_ODqFaff^T~u-C*g8y!94 z)==85U((6JzD^d0LOJbCkBbk%B=k+Ov5uXShlLz0x=`EBAtx`?whL3RjbBj~Tt2S~K0PfR$Lj0Ks+PjTqr7omQ>zWD zecnL0_N}rd70vavb3y-J-i&&t}$tT{h~&6x1xR#hGBd?tfu)j)u@fBwKa8CSxs%y|3{42 zjpcQfoDa9kvIXG9ubUS)|60yVc@ws&udOmOR#w(jI&R_^Ol)P7Rkx^i8c$G@d@!e> z9~D)7OKTQ3S2bd<`%-Om-_&<6emcH;bXl2OuXn039W_g>vij=krYa01NrT@o8PkPX z89b2F#Q`=|Rahqt9^i>5n~8$QDMnp~)5PJLbJy5hzoeo`=L_{WPtznVE?>B)%HqcN zql$-o+nwy=g|!t8i-uR!H)5;V!rFn5o98d8oeQjnzPe%Yz`~}6!ph>o)GVwoZ!RpK zTQhuqd1ECM<&72dhhvr&52-4w?OojvFPvAoq`a}Zuz$R8@_=|@bzOa7Q*&cY1xhWf zDR08;LRqZ|F2ocx*VNZFLC3uT{Bm_eVMTpib7Of$^Ki_jRn{;FD-08X>A-^aE{)o` z$+cX8PHF9!xx^Jy#-_}Y=OlWCa8cnp?8hrcUX7@DKIXlCZd20ts$yY%6Bct>Q)LY{ zVW`2$FuO5WW%J5wYs<~`h?sBram_biW$}`oTh6l8ja5|(Ynpf-x%|t@rccCT1?tAo zw73RmdP#*Dlh?cInuTn(VqsNz-J%9BbJ=2CrI;(TB-n-xQ=;Uy0@juruwq^xWV8I zG?mvj02)T~^s(y;OxNZvsX~of9&n@4=pRl|VC%3GLB`{04R1@btaW2c6+yq=B z&Gie)7UJQLC)mGO&7`4hb)EU#;2Ef@jJqvkdEwN!r!3JabGEAMnon-P9S&y<9}V6q z$A!d+^HZZ6k8G<9r5ma$YN~6hD&5mmg+)`14-fO90{_&Srm~8qbc znwshxo8m(Y`}_Bx>G^GMa)yw>?>pDe_f3jlq(-*MTN6Daa%T9fl(R$U1kZJT7`VV5 z(Pn$V$ql5o$s5UEE=CN%zw#>F{VcmDqM;#U3MW}9vGAm5AT=d3m~FSWb6_3S(LT`b zWOuf^2FP;OGWZoi>)p@&sgCzGS4u};0lhp9zT)|VgD;1CVWA- zL-?^U4Gsw`-&t5FG_+yRlOc@hh5``yJIVhL9)?>X(>=er<0O-ki~4!OWy00MGlk~~ z*9)%}-Y$Gz_@?k9VHo!)*55(cTR4D-b3a6Q7!iFvN;p;c10u@Lm0T^P&k*&CB`*`M zlKx!D7YMHuUM;+Vi1N2dzEk*1=^vH+gz#zU|0MY(;V$7ng*NWR#y?P)E$kp1C>$z0 zQaC|)oUlw-FKiN?E<8(kiExwfCgIP7zaV0q4@mxv@GC2+fOLoY#EGJ%#3T3Hm{j#|vrB#dR=U$lt*z@5?`NgYsP}E)JDc&>20@DkxwLhg{u`e?~Rd`$SX@EM``JVZJv8=3DP!uN!q3mtxL zAw6A~A?z%S3uz_9d?SPtg;Rvb3(JLdLjJzba@<6kc)IXh;RQlk95MY4;e*15g})R2 zLHMfhuR`O;j`AN#4)SvoaztqS+98|IXW*gIA1*8vju##+oGzR#oFkkkH2(0YuTk=1 zp<%v;{#40l3(e;}^y?*GBBV7d`+K$UUf~16M}*wIoB94A{G;$y;a`P(G-bY^FiqH2 z$e+lW&Y$Fnw96uz=L+DVk`EVhn{uX)6Y|$E%KQ?<4~JXCnNko51&XLt>O(j+bZGgUyWYYFB-w@$p!jZyK;UwYFLRuuU++yJh;iS$ts?WTv1o1+Ue;4lw69lr`?(7+#U|hp#e^RCkJE(rFK!qp z^uWv42MWe{E*Y4QpF>{oqBEfI$}sIlBz(vRTm>(U?@sU)#VV2h{od~ViSJ~vw9MNo z_G>Nf}qTr>ig6yxa`7qb#o%P{sTcW;;5%f=U=Pdc!|E{ zVV#G3aVQUfp6~rwALpHIdTSn0>lUoPQbrWK`dFq#KJ;&gmkH?Q>pNgDegsQ~eQ^@> z?>BJZP?LS%oCNWSrok_85}dPTc4Y0p(jN?N05icE&O5fV_Fw4H+R*x|tgKRJbl@Uq zUCP?<`mOJ_O%H5*VYhYF3%i3`f>-3spD};K{Pg})N{<7#fK~W|?Jw?5Uwc963A=-7 zJ@#1db>EXZAa76FfKeZ(zjxYg&UuzI?@~6l8y(&lx+4Fc$9Ln5?+*4m;FX{M z%gX4n$Ns4M9&1V79;bQq$La5%b6fDew!!Oe8}qg^YQ)=CN%m^yWf^;ueOTn(NW@<6 zYQKX!VCauX3G|0PIJx6;qYD24mz)y`@tc7Y z37?KO1?Hez;hP;6 z4g8puxAc?7gf>8H{G8w11l0 zfkCz47tQLNw_o&7WkVNk8dD7)x}RGN;E#pB5c1F(WpQT}%2&^G*;wLa7~M+?FI- zBC&I90n2{DPdYk2!tc_tt8s3l6H?9hYRo#{<3@dc(jPGSC^Im#_YR+XqhIAGeLq@T zYe$cd%wg?jzLS2^z1Xv|6n6@OvA^NeM9ZVq$cb$!V*Ff)&h5&{(%w7SNJ-^aZysh+ z55iP0hk(6z_!T7*T@>L;i|xU`Xwpxb9>>uy_(|V@d72-+Ba(|ja_^n!otZ3*)yBPd zqIY>KfqU;n@0JvaRkL6BM0t&J?;RTCNAH#B?!6QJWxJK8qKp`?s%X+r`W=c%Kk2m; zAL;TNbT5FtckX0WNk3_Rd59+cr0?XITKY*xpHf5a-aFB!H2`<-o#=M;d06ZmR`pD~ z0e}GZ-pQoc(oZ`2ys8=Cmo>d z^OMeJe(b&DuEl;i8_{Ug=O=wX+w=KJm-19$@0}DpSp{;3<hqK4d_;YI(vw); z=O;}^{;1DSdK0J7=O^8n?fd+sFJ`*WPny?N6npRRvNC(`T*?Oge$xEuDT=*!x}t|> z@0}&A((flt-|Xmrwx9G%oJP-2nlB&Hqq%luGfq~HxtI9-r1>f&>hqH(Ge>l9e$pqR z-Zs%A?8w`!Y6ed}_THg@t3QWt(V{*-X}%SS!cUstD9qkFjI{8Rj;;=Xr~*}WU{yXp z=~XOxdeTptKX68Ue$uPhYoDL=^X#?HPkJ`%!`?gRnx?1Z@CV?i&riC7`F(!Ue8CdM z-aGsV4dgcD6f?iiPx@xI=l7Ey%?y4&>EW!w?Kj}fdn6UQ_8+CHA z_f8K^px;k=DvS92q*pV?zvm|%y(|#EjC0PH?@^zh^lHx8H}aE?t_(OYp{h>2>qN2l z4o_~U3piJM^^=~5EZ>!%^kj}8=_h>*8&3F1JHg64IuRlFmn)bo>m0|l_B4~_OyvG-0j?g7|)$NZ{suHR4k0hA2DbDAEoE&Zeeb3D(NSE6gm~CPWnk7gT)Y-=jDf=^b6>4V15ffY0~1_!}u_W z&usG_a&LUeqM!8e0>*|T=@1;bd?jojZv3R@LZ%Z-ZU(Bfk1&4HXF)!ly2Z>_lKBwg zH{rM*hwCRj()c>_1L8>>`7!j*9%X!@C!y&haO87L@TaElG>3aVbsQJ`sUL;zAQWkf z!}XIcZTk!8XgP2mbuj<5k2I>cAihc!El%N1&20Ioxg!p_Q&ZIhkz1+d%{6||RPkqm z3#p<9_4q8R_#|>Yj(j>>z`vQgXCc#xC4VxB&GxbwEBOJU({bdlLn-O%Ad?uy z>V7umZi$ObiS~cxVpbWew8J9T#jYX z4-t$QJ(!w$CQ29F3S}CG#i8|NLa+Ov$%mASL#4(e66}C~_Hh~ad8PQSo7-uTyU;Cl z45X=UsXA1`QfWh3>V$UxWT{i3tU)^26M8bC*9Fj=4vFuzv9l98#G%?X)`|RgER5Zo|#(hm3$28{L38`7`!N`8nudJxlz><7(De3|INW+FNz)67NtKzLM8Id#ZmA!gp(0jLg7US z7a+pd-F>`by@IIs8fbouL-n#chyN;Z*h^xYy?Xh=`%WCD-ff6HNrCmgipVQC`gp}m zy&pkCvSieoiDs4}65zk(IP42zZ?oS1NJz(-RwH7sjg8DeX%2k?@{Ge_x;O`s6DY8YWL<8;(T8PO%yjWwX!ssn^-}Nf-x?hD zy4Xgq-p$B!1rAd$UxeRAf%X0t5n7t`@rs#xUxMbpaNwFKMkaoYJ6GYKeOdTL);S5v z_mKWBj)D>hS@;BOhodKR^_m3@%~5*eP!)F~;yj3d_CG=y?U2kWOwq~6G=W8#TEwC% zaxWszEBI%>6B^Z`$SKIaghiODB4&9$4A~f-Jr1-Vid}$WW_ezR+}GeR%ky4D?#9uF z*_qQU&!?f;hC_2ny~BUz9pG9c8i)V3XOWoIm#qUhX?_3vnI+K@mSC99}pB>l=!xDy9ZPe+oxP7(ihXg+Yzz zw)0pxoq{#sRgB2F->ZlB9=D$R!~K)>+#fDU7X6iq4(8{abB9;dEp~^$*d6|2cd3~5 z<-6>)+*;2`Zn_uTzssJxXJAKd35Xp9xq;t-+EGwqC+!fZ{RTU8Uq5E+B9aWFKO&u5 z6Lt;SPMgEixM3mo1628g3b1iuXMCi_O(YE$Op$#=y3@wpGO$N_J3G@ZNx5XCsrBFx z9(KL`1x3AqcQjt^aaq#kwV>ljxoad=?U&Maq}kI`*xepo?BcAc_T3}Xrl-tIJ2veH zW~>DvtJtfuC$r*SGBBy?ohZakCX4k+!&>9}QrHj_qw*q_!F}ROvg0wP2(#kON00Ql zX%;32o{Cf}{WTa(@c@5;aanGWftncQ8RVaR+;LhL;U$QGYY^WBzQ|7!kavwX+=q5Lxs=}2b`)2UM3$UNsCNVy-We?!qF`24+lVi!#TmL zrxha!>T+!3m~Qn#F7q5@9qm2rz_XkWD?A))i0O$t^=2Z>#33sYt>JGf zfo-!kY8hPe5B$d{=RmGBx@m;@Zge$ZjT8u@aV= z=q$pSCOVaHE{=3-nN^b4V5NTk`GMUw-vo`jG^ZpRm;$8<8TgM=gI}B61~?}eIicA^ zk7ENjy3u4+)3}y73F*kjc1}Ty-F%nQG^8o?1G)oettMphKVQWmUHak%*o+{`%pLGlByKctoMhUwLZEGD?51MbTI5E@V&+_#Dm z7Qmpraz@WPg4=7~P<+e8)QEpU9F;h@lvA+(#&WCsX2zKnb>hE*Z!vi)mR*B`3*IZs zIJ5f8hQDOVu`Jikvp7<464)-|%!;*y|0XyAPXFOJQmlVIg%99l2vExdE7sEnqdXZr zko{hN_HZHv>(9%cma(_&Z4xQIfdoyHC2sAlIzufF+nRy@CIkZ|Ky{{7_K`~Q4b={C z)Vws%_jUfhTLEf$`1&5Ssc_eOVnBXnVp1%dx!jzI6Y3bn98+gfX>z*CSx7R$@hKBy zv+OxY2g6XUP=%PL#XXEo&|c?{3rjBB2W$^F8Rx%e&-< zJ{eIr*bf8UPmIKahwlq;@}jhC=5li;&X!{o{EYNnzK+T1Dt+gGiZA4(f;SL1;V*5iFhJ&{lFHkoa$7md-IK0~jq9!oyP#pd==J7%a zA}rgwTqSh8>z;^%cU~{7L4?NzI4<^-ic{u-xgN(B9Jk@{!kvilME+IB+d!U3FL)=J z>0X*YozwL!j^}Xv35P%MQ^gDS;)SPU9fzs>#>6--an3mH0PRZnKdQd5s;{U09`=Ra zPoC3QTUb|LS5-()+r$psU+pMbJP3}WIPEkJtu1e!Uo@XrPepALyq2-IH$*(&l~q<% zm%|Oe%y>pa7lh8Z^fyDmLZOeh8%tz?7CBH5`V_b+(BIn4qGtFCG?ZY^dC+p%b9xR7 z^>XHtIj3t;sFQOXW4o-P(1FgzRYl~?`76j+IyviBjSt!27$NBmsBn_pIa#50DRB_t zfORAr)H%UGsIzmrgH5*EXQwzB!-6EzIc-G|^p3MD5Krj_E*U66m9u-fZE~-6b0-t_ zDB;t9sis@XK~6@zD8*?)kKLl5DaXfdj;utTr>=18Jj<;!negdy+Ys}Rcc#QN`-WS# zuUj^p;#`cfPUs-#H*L^tb~XrB&=~Z;JjvB>Z>9gK^iQ?YZ#l^h#cUgdLs?EbqE2%> zrO5EiP|QlniWj2Vz8y_tx3(($lq$WWmHu(*f6+?+q}v#(bu#TxS5gCIk@6=7>YXAr zdjQ7U$$63EJs=xnLf%_eF!MyEi7u!^WVui%WcZ72?_6+v(m{q)77VNRbXNtT45hR`XWw5 ziu2DH2$+1+{-Z{B+CPc4JRPS>|8Xn*nnrKhGeMbTSdujU_8c*$KJzeeLM`G7aMI#g z9Sxt3zrPc_<<+XcS(p$kS4>AJWvn6BNpn702`VDnIoFO4!{uv#9U7fRP}-E8R6J;D zf3Q-JO5?lZ%`v1oU_nSQZjf`P9Ha;T2?RPIc^E1V43|d-b716e#-@X6iU+ftSarnH z^PQ0Ee5Iv+@gT5ad=+($OK#JeKqo<*VYCvGIpFrn(CeQ(MO>5$uvT2j1 zj~J~_+y7q#I*GOYT~O&HuD20Wj|4xLN3HYC2z8Fes&AOq*n(BZ%*;&7knre6hE?i5 zZhlK*D)Th-J@WN@Tb7=(vZ-UHxr{3GEUbN3W@U+#eXuD2KNp0R;dZSwYW_O$WM z7QYK;w30Jh$@nGT7yO((oa=pa_L!T`zBqfZ%=w}S-^wHI`6cH9TPD&zo!F6xH%a+K zEP`Ir4;9j6llevqrwWf1o*-N(JW04pc&6}t;U?i#!drxQ3m+E#UiiFlhwvZ5J;ME* zJ?{D0&)MV7!+y>lcOLe0_Fx|H!{h%J&Yt$TH*-84g$2Ss!o!3|2#*p@75;#T`}kbR z)xrhRFP6MaxJvqSC0`(1Fa4F0uNK}Q{cV!(6#kNk&zFal{*mzE0RA{c_2x zg+C;s+*+kyCH=L+pGbe3LW7k)%Uxle?2KBk;O#QMk< zc9g!0u)FlVgoC6%l!)<;m;NZ>H0ftco+Dg9M0*XwX5kv8pDjFJ`U{2Ji=O?vQuq_; ze`aJsNc={3Se;bP$`;pxJ&iD>6M;YHG4CcIYqp9p^{ykF_R7Cs?-O85*B z^*%3rMf%r;|B(KD;cj6BkFK1jbYXj8N8!Q3?!w+gw9{8ORQh4UBc-1x7Pi? z2WQSph=_9SiO6@LW6pOyXv;cL>rCH%W^x6(fmrs69N``<>GMMS+h!npK#!u~|u zvqlJy64nb(6J8|jMuQ!M=C@z;H(zp3 zAw73EjuFDK!imDU!fIiy@Fd|`!XFCP3HduM>%B?%GvOV=dxU=$zAXH!kiXBe{JX*r zgr5m%>BID>Fec0v(v6?#9#>qhWREMZpJaL!G2hX`nZnt^3gJ9qgRoh6ig1sosnU#Jm@A|gH}yqA zv%L%CLnRy2bI9W*&k)WMdR%ft8N3oUM>Amwb)TaJWMMGs(9J?-AZF z^tk38m;AKw86n-c*xuiTtvTmX@Ea}DQ-yT#qTEy1PdHF`nD7W;sc^h-UmSGw7i0ZP zgvPZT@@bM=bIj3mjQM{iyhC`8kX~d=e?j=N@HOGv!d=1-g#QxKJC^15#xX~aG^QUS zED??tP7qEO&JfNLmJ6$dON6Hg>D|Wq*9z&`M)~JLx<*s}weWG_R^cCne-yqU+#!5d z_<_*lma|bO>!sHmv74}$ut+#ac!+SMuvAFLI+j09NT)i=jlz|}(}Z-ZWBMh+)*N!Q z9bvlh6%74LrCv5%K1Y2rBOaqNdGg+9yc3Z&?r|5>4ir5WFh^} zC|@9?pBd$AgsnN(=xxUIZ9@8)QGQiOpEAlH3F%fwIY-!)h_TVRjQV0BeaI+J6V4(c zUzy|z;fd1IfsFZA3D1=NhmwCJyjXg=k1_vGg!CYz{D6?YW0ao}(npN)TS9t>QT|j& z-!RIVLi&MG?jfWX80BF?`hQVAT8L%pu1`IG08Bb=I|ea*2EFI6*3VsWrRNC?gnfkO z{WIH_Tp}DT94qvm%VtWREu15)6gCK(g-eCYg=Y)T6Rs6*5MCv`R(PZE7U34*?ZO9z z4+|d`ZWV49(!P%K`ik&%;akGL3*QmGFQg$B%hCOX$lnc!=|b;$kGqpnf1;iTvRNMA ziM{jj9diTXH;4V)fS6(vF!d(%!2bviJc5`oQ0Re|uMZTA^V(uyKAu-E1QnS9^r@|3 z5YE8&A1`=mQ=!1+Zj~q@djL54(%s*Fuq0@jXZkf4=#^pCUt^K9^*ZZIYxc#NZ+i~D z$K!tB1+R_f?7TuMDEr6x3JXQ+QE+C-c|09Q9p=MAnDtNz`{E;$9g>s{fC;InC#Btgi046L&eO!ZH@Wx9FcuL?c$QOt50L0tjV7siJZTgmx zwYC4(;|3gv{_Q|nFL>>O8*or@JQ?=I4Ol#I$RYhr_I+~$Mh2VKT5|&)2}ZyfliyyS z?!4o)nf!Ko$MF2X-=e8)-u--N_TY>`2kZ=uKVWCD*NmM`uLE`l4xO>nK6Lud;H>sL z9UOsW(|6j-?t9m2YrXUAYWv*`EAVcHQ(2m^GkD_MUHRiHccq+o@UAmvE#7tQi50uT z;}`Eb%9XM)daM_fd4)W(Ay$8}yMgFs94c_%*q~{$t zWLF6J&pdI+uKZ;cyKY$K>~xl8>&LU^?g|~aXxEv*YsW9zb^WZ| zU1u#@guM2!QRwHCo%XD}UHPcB$BBdgAA4^CUsZLk5AS{UK4aQnb*k5@rPc{h z3QCm{tN-U&>)pvtoO*k2@9=%@Usj&=zUy7{aQ4|}t!E$TccFo@jzn%2$~*GF0O%Z~ z8eDwqZzmSbh&_TDox1zC9~qPSBMwT{a}G+5cu3W`aKwQD$n~d-N1%2ik=|t=85eFx zjM2N-AQzN(arproG48lybO8#WbtLFgL%q$w0saPAA~d>@k58wLcv4H!LG68hX?=s zS05bw(ZK_!F5Y^e{M@YvVv7$RC_DF^_qQIH3*Y#24??pQn%}>l8oTa&R=XOLp>XQ|X1@mOGtzriKY9^c=~_d>pJ+8?4Ug!G0`Y# z&~~BU`d9dz?y3=zKZa4dGt}i%p74JBbMjNw6CbkIU1T@~lA|4tq9RT~f-Zm?CiS{g zkfz1NFrOwl1--PWcnqCk2~R_*c?{2oFP=}b{vA%$4GYtWNHNPf&L#VQ_yq(w$H#f~ zJC5QBBHH0@6i*b<4fkLT3Pnr|_hMO25-~aa4#ks2ObZ`H6`fN=Ob_$9l`~qzjPT!> z)EE(?Mhcf=*K{ViJ6I|cz3QA6Pd^yF!WC?T$#E2|%oS#sJm}68RWZnc@CwRjhj*ojHBj zSi)n-gyVA&OeZ-6Z9XpokKuL{)ph2(b0CKK-T-GoSNfUJC>C>}ml4J>M_uwNWMApr z=l&jLB#)tUe~LsPkD>E`HxkHW=xi6s4RbCz55^q_AdlgT%<3T#HIJe5aMzJ4=j8BI z8t;&}>EV48cd1qiWM+hGDL&qNF^U%ekKrix_!%V*3ZKi2o{dvq z+cSrB#p~7#=LN|~^B6k6kqT%YLua?-TNvKOq+aT}UnMm zq>91??DW?q?&R?O?4{qw->K?5E&Lb@`Bn-^S_7G9hDX!*?ZkW-1;Ari!5Y1j#2FmO zoE2WgjNX;OR%WD`>}y8trv7oXbUTIrs7Jr>Jxg5})SYChgKP&phHRZkG1CQ)p-h)Z zH5&swhUeoZ2J1oO6^4VyP|I$F4?`gL(Q;zskI2LUkD-pA93hjI10F;5B{wrIQcQdB z80zr6$X{74@EC5vokSpWc%+2+fyYpXkBaaipaUL5^(7cQhWs+*fX7fTC8HI$ngbp~ zZC?~QgrVzz$54k)h}_Kh;4xG$D9W51NoRiGG1T_cB78xD10F**4w^Z_7cw~DF}zrn zXJ&-+$^nldr;_3^EM$V9Dt zawh8!9zz)s$dMHf+Dtxu2GUJ(z+-qDlj2(y9Pk)YU{XJ2RPY#TITZONlLn6=PvR*a zLwbGzV<~oz-Oh@D^C`YyM5Z$-@EG#bj7h!4sNgZw{b)y)utMN5q%p`^BcHPmz+=dd zi9lvngb%G9@EGb^Oo-gb^uS|Sq0*bCcnKZw7?!G{&Wt#;2alniaFr3h(82+ap_c0+ znTY3r$56|QA|UNB9Pk*1RG+UfBfR-^z+>25DXuajchUkphAe@Vxyg*orv-QnnS_;j zyBW!0p5QUmiY;d35Gw^9L#+Uh;VxQ$$51PFn2}F8{J~?W6_1&b6xJI&hB_Dg)Dk}) ziLg|vO?zmWg;KJkh}Ia-YYc44TKFNG^B``2w@P2VlQE%HJzI9>bq9g3mv11{Xrng-P@?dBW2?1&7ao#!>YjinX}6C0F5Sa}d2*2#dmHUWWwCF=jWW zI1!5RR9?dBk2Sk7+d3#Nq|&A3I5UN1yBTghoaQSWZ>BN&8&L2zGn+SKX3R`u^nZoF z87`YuF;CUXJPgYIaM`SnIYCFi4T{xpnzL}CnaUO#fLJ}@6dU0rty=_{e9D@R(2UTI zsq+;^S#t^ubCTJMx^0lRQl~fy&A!y})8l2OQ+AoueGd5ubu()~W_X&;Bp0>KfP)g2 zrf$jaajL@~RRO+#{ox0L0)Zx-2$9548=c`d@)07nrN*yLAj=`VsJv$o zm@FxDI$b)=8U8fe$&nPR4#|BGDL^#MApQE{QzhQ*ga3wb4V-1vHMY>RLko*q=-H=* zB`x%P0f(9r_$VAP>RRaO1Ba9d)0F;VyM>;WT5wzFxkn3$Ej!`)`g(HT0f?9E7J5F_ zg4;rmZhVwXmp#o&qf_X`$yamHpWS zjysiB`v5!}7VQ_-SYBQe2aMH|y%vUls@K5qPhk>lK-v%wYX4LsdpCgY(W&u2%gf5c zdP2Ka*Fo)gF;*9Og@R3y--b0>tK*LM*^Kwwu%a8ZP0VK#^V^JsaGSO{)n{|6&n6(3 zs7?TGffZr>WSXWWM0Uo z<7KO>O*a<4+u>k4WgBph_=&ug!Wd{ICTV{eQQB>auiYm5$~)Cp-oI;%`N}&5*><=< z&|+ae%f-R41P-O0dO2{r_=)c*e?uMdWL4VLQ(3|~?VsW+;bdP4r?N%g5*wnl=u}^e zPWF|M&sRELGUH}JyA=*)n|uJs^$z~i`UB6@{)xmZwSN+k<)97AAo+e}bV;wajV_pC z2>?R`Zj@2 z6!_c7QZOVuvJ|L=ECmz5$IueOc*4z8Pz^O}7k;fU!HhCslJ%@&N?8YT6f0yc0uM^6 zj~fL>Ve2Xrv=$-j=(0&*M+v&n1;Lf_?U)Zf6>azR2!anqW-7Uu=yVe5qQgS~-W zbAy9(gOS|eak;^)++a~|Fh3VWAIZ5O`luuGMSgH_$O3al7pp-LVZ37nfD!7gr1`P*YnSjIRJc2KhiLY8s5< z(%RaKs>+Sxu~l<%Dqpi6EG#Rzgh$&Oz@%i%Z#%3{LWIiN`SmdJGmunN*Otg}enpu; zHkGP*b@S`Xi|ZO;T!UA7R~!^cA zhul~>f8HEm1@skl3x?-3)a8`nrGwD0A#=cpby8(XeHj!b^`(_3p+^@SSDrKP*owMn z&fKzvCG{0K1<{xq z6?HkKwKa|PC8dog)mET)>PBEJEG%uP|L-RbQS@B@U4$W}=(d{qbr`}GWz|)4iWijE zv%lKrqQ|#W)lk;ZXw2a!;Ebxpm>-qJGHL$~T9AK~*+YFW7nfkDR5cn6l^8Tp&dH8+ zA{}SAk61#@@!|$_W<%9n)JVNmw-}vTIR~vMc>H+Qe4(hTU=REQ&wGWG?dJ%1Jo6v z)r(n#i?B2;Xk-c6ctlDuEfCngAk8grL?z4FGe&Vq84CGN<^1?Yu8;5OJUT3TxaY%j z{SJH{QOMrKuN7mHqL;f@I9G;#6uin_WnCS(&NTiv@_6*|3azmHs}e;^f7xrZu=w!Y zcUfw;VY|Xoy9NC+TdDoB)NVb$oZK$JXQ|zC?J7&{cJs?=Mn8!B7RNUJRvr(v)O-tt z2ksYm@BSa*?ifP*FwQ&+@;Q$>b0^40RFqE_JWp_rV3puPLG@Gt_E(GiW5HVme=7J( zLGD{*`rHOU{G*_QwxHZyaDZTe-~_?xf)@y0BzTqJO@em{zApH_pn58ReE4OD`K1Y} zvtE!3L>?nJO|V$7R&c4{HG=A_7UFLa`FX+L3+@yAtDuW7W6b|J!6LyKf>nZ>1b;60 zyx<#x`vs2*#$os~-E_e-1xp1l6;x-7V8=IR(Vj2CC91PUKy{V~7{XUY>iHHeVz!_< z0|a@z$Y%+b3(gn3LhuH`I|T0&d|dDq!FL7!A{fK~SNRKO3yu^#RdA-DI-7%XC1RR0 zUJt>6g2xG-DyYuBz^-0o{*1Z}X!S0bx3Es)<7`6I!<35K~%0O7p_a|BNkJYDd7 z!5YEkf~y5@738arnBFeImj&My%*VqdhK~_kBDhNMr-Gjd2I94Ss$fsSzJdjU>P!dH zJz3-;!P5lK6f9)krxRr75yrauN6eg ztA4^Vpb%<>{B&dgWeE-v94e?jM-Vz#LBqj;+F)!sFg1rUR=MVIQMONG9AoHEx zv{z5cfn!BJO^`3TWcWjgWXiB_LyNaq>}=e`K0d#@mWYNO0w*@$Yp z8t_SxcMHBO_@>|=1@{Ra5d4eaUj_Nxnd#bse5oYmu7cc>L3y}fq2Or2iGrsKc0Lnb zD*CyCb%Kq8KNMUp$lV^y?@qzaXP_Sz{jUYRv(MaR$9S&@{=4AYg6|3bS1S{6M`=Yz9{&* z;9G+43Gycsrt`7jr-EMyGK?->FiEhxU{AsRf&&D(%ZKr%3!W=@fnbH;g@WGM=mjEk z>ptVJ6uesSI>8$SHwfM)c&Fe!g1-=aNbnKCCj_4nd{OXK!OsQx1%u^q1rr6+1k(kh zf?0w?1oH$(2^I<#2~H54Cg`2Do+a{Z!AikuL3QRDRhLTE;J%jekRW2fR-3g>mbXKfS~e zx_&GlnzAjupG%xPAg`bIMq7J>3^MbgQ#*Hop53CXuRjC&q}T)0br5#`G3XU_7ef8z zOGEj*_Dew+?bshL!(lAf0o0Y1-7!6{Er`D1Va$YG6iV)Z__i~ki!lBQb<*m;mmcGI zbBF<1DBnBELjUvZa0YZ#ezg7a&VUX-J{rwaYW+VyFK^_?kZ{`58l+o=t!J zP}In2n$hQ&rswxY4d+mrHK55p6tyx|AG@~u>g=YU#RfFbIFdFbW$lb3$wOuwaWiHd zu@h4vB@W4MP6I}VbYs{xGmfMq+}@J4X2xFY*}=`3tKGH6vBtrFxvc+&K23J)@knyP z^Lvf);kAje=OcqQ^j`Pok-9z4A4y;R{NBL$A5a^!=#wg8u-lKFeYZSnhS43n#UIv$G(j8+HWL`fo<}J(E48cEsOE2 zqk)f|qvpZPqe)*lvF;m_$Bo{X6ky3SkJ^Xrwf{0YX+v_;z;Sl-Sd{XtBZ-Mq_x))Z z^8PHjS(O5%cN5*!_J;JPqS$S%w)yj&WrQh)8-kzH? z*7dk)OKaTt#MZ#a&+m;NA8L*3AK4#oPu=(af)%lDEvf5LZoaD3Fj@1*TP>3{PiT&` zu=c4%2~Fq5;+ubp+B>ar+hh9!fvohg`_0hUSo(g;O=zCF@9p}rs98_Qw#)F)Eq7v+ z1dfJ2caItepEwjnI|haiI%*!8yw6CSyw6N@kA@CK*0}2vTkX#x8`(>%Vxd-R;i}f4 z+4siVTdnctEq1fj8fs0y<=$B8El;$9_v@CQw1zgI{2NxrGS*!hOIw%J8hYekVmn*o zHV4*iLHQG6Cl)2NEG&9{uWcsW6j^Vz1e?rO=N!A)Tz^vRgUFZZ!JCtt$Kz`@QW|fy znls+q8-F%h!Wq3k!9W`?KCj25{h|0j^a$P3y?GM9j-#9dk6MTAHG_^?NBWKX#ptAs zWB0j%B8+C#(XuxbVT3zJtxtN63pd+qQC9a#mMV;);D_hO+u*kI6-`W~jWwZtsPKb>{Es|Hc>$|Q_N9(6; zcmg(7tFb-(mdN_iv7f~@#U5=9twIlF_Pr&s)%s#fYXJQkIFP(y>b^ZoR;C;4PK`Yk zyR{YDE7zH=#+_Z)Pu_1P?(Q+aX!3qH@sr5N9^=tx1?iz%y0wIF9=AU+G4W{VVE5+U zxAaGC(07L{j7l>xx-JBbarmz&InEk8NjHaY8h^wtgx^YPg54**H@LS%nv&PPdF1jv zeOjjOdvB3>%H(}^;)s|PON_;0eQsKQc=$b-v%`mM=->P%=I@)Bt#4wszNuzz-JVp` zHOcJXl+zsFbZj%%fb%Zx-<-9fSLG{_zOl3z#>d5pt-(*wuj2!)=CHd^*W@**aSBpR zu{H$PWo``L)Uzn1*;?zi8fT1(t!T9}yRCC#sq3;aKAg<=BG2y)Wnwis+r2r^Y++V} z=H3%ayZQ0fq`7Fr@d%xpc}r;Hv*}a!{qbUqZWF6ZU3_csa~_9y1ixP!SzLm!*5 z_>Jk~a*qZ-={hcb+?#uo&JL~aH#@xXnDw`zcJKT!>1f;+sLN*K7~|kySG>8`-rWCY zqc!1BO=Z%Jk4LiBMQ*sK)yOnjgI(=dXkE&NO|AC$a8XigLViN*waAsNfz0qNzf|)i zA+tHwtr@M>yf(J0)!Cff9EYC9@tqj!nc4jOUU##*;jUI|v)dZnwkrK6vHr2RjcDCZ zNAI_7jLV8>YzyY!h@zLUcG&@rk~7kKZ^*c%`^I>T6V8daqvp}TC(~m6j@lnj+GoY1 zmaY9T5|Y*@k3;({s+=8;9kbp%hGDUoaqz|!SsVJVPuaMtGI`DB*1#gvbP?*f$XXxY z>VCqOPH1(z23n20yAe8?^LJ5jb<(=zX7=D^t#&5+FmqjKBU%Bm-9_d)yTxub4zG(n z6-jG;x<@1y-mptjHd`VaGMjhA;#!hg6PE>Buv+gq73B`JTpxS7ht--`WVQ5+g_^1R z30iJpEE7E#U=KEqLmTwo&}YAyRD{qZ)DpG*y!*!4vB~?a#Ej-#%#B>sno|762p}*sfU>2ujH;>!vri|MgI(r;G<;LL?ZX7<}qQkPA1~m`Z(7$P5b6SCU z;()aSo0cE0+A?%2&h7trSM2TB!5HSo&Nts@8m}?MvtN#dW1mpFseA0V?{{nN5qmx2 zHusLb6&Zw?f;pqcfBAc_;|5IMtJr2PJc(tv;kpMs#Rn?>E8sd8<3_`>gZ$MW$MH)M ziY;?I@@4aO**Z3zH{Lkcem^7}_E(QCZ~~47D-dFxo?Z{Y!T+0aM`b_8I8%FEp;XRn zNOlSI*4*@URJlPO7qhS6zx34cP}wVJGbFWw{tT4G&P%(5e*V^Fk4n7;ew;zOh>4S0 zF4(`v+fW7V5AZ*<36V|vS13$qND|9oe?)b?@;f}q1-gL<&rG{^=uV5zJL4`v=ApY1 zL-ap@6hl8tr5@+z@ozkQ3A86CKV_NPvyftzdz^be^M0EN93SV^Zyd!FM6|=%6i*b<4fD4>w@}2y@JyEFBoULtJVWT7 zEMi(Xo^ekRF+F^U;%E^w!hG!JjuEkq6TqG1+Q=i!AI03$;^}9rU&S_<97oY2C%{h` zJVjLuav*$!@);tN6W|JDmIiB8WpD!U;oEA{J>Q+p)Kz<5kU~FG=X7z4L%Ip<@L$k> zZb_VaewnE`0o*x#*jT~|z=Y#@4v$W92--^^fD_;&7S)~alG-u+4F0(by3)^#_~^!6 z=w*cN;iyZ#0cEXp?{hN|lbitV{V5WGoB-|v-bf%PfV*8JH_VCRJ{UI>Ku&-l+w&n2 zH79`ka92e@nVB4}qwx-jo37{@++C`b$O*84p^x`|6vZPaz;Y(_WbcoZm=)%OANQGX z3LuaqT&assfg8MT}G$I;U5NBl=U`sH*4bzxBVNr*Yfc4r4%woZgU>bT$p z&|}4jw6HP232=w1f*pC6;ot<&vKtx93WF0s%ZZUzWa5GoK*vvxJVP0r0B_;jDp))s zzhgnc382ICBDs{o32<1250CJnxeHDJ9X=|Oz*Yb!K!`s&f)gN(>46hKFD0WR{E@~5 zCxEsuigaUqa02M?36b5D!3mJ4;!lorL7iQ20%-eb5k7o%!3n^|AtyjQWpDyKsLC@l z!g=L_6M$1maRSU`g5U(;98sJA{F%T7Cjid_D^37%Si0Z@n2n~f$O&*K(*P&HU}d2= z0XP+OC%q4AUneP%g+nJ@k1_>qKJH92k3z!%>NBOv>(5V=5#w>#wi_WnPw1=FpQBJs zW-K3^mwaw1E2guB%?M5a9;!`0jKU?l-~?!aMMSM7-~^z6IUeETZx@^Zx&`gXa@HT5 z05T$wBP$-XnS6RN(oJ%~39yezx%lUfHd81tsn;15oB&!5Mc!c2-~=c}=@cgbJx5_I z#qP1&1t-AC=$Z)m5pY&JT{DIlkyOgy1knA6 z1)Km=kUv-S$T>(D$HtQ{PzrDYkQ&tmCjd*JH~}`%0-OL$LU97jWS-yz&GNa4nK&sZ^VS6M!-crDSjdP_FT0 zass&E1XvG6gg=zJ-~^z+?kixMffGQHSZ0C~fU7zMl@vGu*g2d?BKJJ#f)n5^D0*?# zalr||&h2%CWdtVxbJh7D@FIZ|fZIaA2|!hb$z?!|ZVa%a(13aZZIWSf@_BP13;v*; zg8%UxgD1eF3V^fwWHoTX3BZ*PoB)q7V{igYP$D=1NEn3svHMZFK1ZPpnmp7N2TlNP zp6E*^kL6MR4(D+K{E`uj-rW!o2TlN<`3EP!R74H@*i79F!!EZ%=a5(m5(0Ty1S4~U}aJY14$5Ipe}*Sl2X)m4UFgvj^xWd z`$Qzj4IK{84+gGC3O)y+OK-&OXCA}q{hYUiIA@7ec$xR&E}EB%PJlKWRdJpnF)Tx8~52;2aNAPDT znm)(>P#Rm6zX7rL^fCU2RooYl^h0p^6#v6%Opkkb7Q-p>fgLKjG7P6#aEg0iM=Dbz zQO)g2h2#G_B2@8n>O;5zWFFYji>d)74DCy=;sp4WN^UyD;c(gH<1ruUx*4sJh8ics zWna%0{k3YnX^=-zhj8e6vPB&{vbNx|->2P9mEKUu$58i2rR&b@_;#0>)cusYe^cpI zhH=6YE}Ps6=A%l-x0zf6H}C;;bsv_8nHlDRr1PL1^jl~L@eLi?V5~BjK!Za`mwN`s z(15Q!*$QV2W=iSkIMY}`!>(r1Jsm7}LwcdjlJx7Q!7nvtnwi8fU#2Rp6Hr=PJ#scj z;Jc+~p>jO{i7!mixzf@#7O{|{%%lvKy}be|t+!ZngWD?1bIhceXQ9%HhvdTPw77nn z#vqpNTr;WCv($~D(&CTNmNA|!J&OiaaBv{b`ND#W;O#6Xb?pxzNPA>o9C6BCY4Fku!KhM5)_E8a9G zrc$5K&zP7x6eUhf?O-4F+jH|-5;MdqGXVA&*r}$K|HN?+NUUsV0#HtyBPyf z%(QOiz(k#Qx1dU^dz&SS&N4+LZ&eefmEM+{Sp3fsLZCUnfe->A6H_}8LilwaA%tJ& z5kmNN1BUxr60@|onV&k{+&(sVR%m9z4-(E%O#~LAe6$o6`+P6Y!5s~Q+VI$~XfZf* z(Rt_?G$y+uif+vb>P%IWb7bPe2*$_VQiT|n^k)&d71J`7?lI}P5{>~xe%z=47pv9i7oafuG{4 z5cKfF2BCK?4`tdd6e>`3QMfG>rl1Ezk=Q~(cj21RL~gHbi%#M0b_LihAm~m;2B@*R zOgu4DR}i7NqHxj`EFCwboJpufDK-ku0j zRTuiLjXEO=O?%ERy>w{Y?aM<&87&mfZBrm03YBdN3?T}2Z3<*e;qo>G1`7ONxy(So zQlBkeh-wEB;9b*@+Q>UE5PS9Ap;?3MEWb0e1Vdmf}dZqy~yqf{px5+-Q z$)-OIQvr$XTt?3TxR8OAP|pJRxi!m^?}YzuCF_#V{~{dc|1x^MfJ??M-p`IhV{b*n z0{gU3n}IRxB}4xpC8LbU#v2~!YtsycNI624`bW<-a9rXrdiA`az;z4x9$rSz6x|#< zm(jx}P$BfN3J_jiM$g%BAz7a2KNk*^J_MEtoHX7l1iA;#@J(7v;Oc{fUR&lZLv5u& zVZM6l6zdo`={P#xz1tv;;mk2pqSFqE>nO zrQ$1=(^KiS0zF*)P$7ae$j)WH205%6gtbI; zBbR2W`V0J*@%}*5TskL^T}J zA+)D6I>VRFhn>I`YlV1D!Tj|0_3MQ(j;*5VFkJ#cUsZ5Phw6od|87HF17~#c(sq;Ps|x0 zwPEAR%CSzZ9NdqM)YdHzwV-;BCC9p?x?^waUpfkS-4BX9wuzK+OTP{G%h zg+^!4pNCi&HvIS*t-S;mKwA}N(9a)@&{~9(RYNj?Q5p2J2LiY!C(hFTCB&=YbP`1w z-fgSRl_oSBZG0shJ{Jgj0c1d?Z$VVD>n(^nqPL7AA}h}e1yT+CU1N&2Q{c4SG;i#o zPi}AT28;J@bpBP0F?pF5pWe{7~Vm0!6@u=9P=%$-6iwUW0ob?g-o$aA;_C^t30C&$8(H!}04Cj{*&b8wFPg z=UrcCQ-JW{V#`*F!A*dxg!8Ve;lB=UBit=;cfxIh+X43o+)lU`;a-M&18xu8J8#Q`|}+Aew3KoqVUVQPe ze9d`A_7q_%L+^ft0S$AlodFFKNf^-JYhyrzzl{M6L)2qHgIdzX*z$3n{Sx0s&0v-l zUl=s41t2;LofPZ|;x01^Ca#Pqlt0LY?D@;5^D9c63jN*H1}6_Aea}j_FHC-Z3g45 z8<*r#14T60GdGx*n=^Ex1QdetYZz(LU@*dZ*NQ@)U^Ooxb=fJ@({s8Q6k30<3YEdF zOB8h(BK5IevrvNWC`O(cEX<7p`UMO72J>`Mw=bEb@_qw(7v`$Sx2wpfsK~FV$S7^9 z3VKaSdKaum-0VfTd&wjafsx>id~O9+TtyJAm|!i8s-%CX3Kg|}fpnon5yDm?!yBXE zXp5s!PwNF$wXk)csv4}i;gWjww4Sn5v*;o}sLGd(K&zLjTMp&XVLO+wrShzuR`k+- zCl1XG7Iswye?$uYs1-%+FAa{+RfT$hwK$sDTT0*U*tTk*I;sWkYiqvLz9$6>bI?7( z!bvL8Cw&d|3*As7&;W&Kn?kQ`o>{^!^m-`I+Ged*ai3Fht5hAWg{IZ5P?fvIisl4+ z_ERQ*lrlrtNzUy%RB7Ik&f93sRPy^vW~x-yTe^VnOA70)!qt6;_C=Y{?WjA8$ZF{S z+IGLP9bw&IP4dcq0A(+*Dx&i(^iUx76%8cZ7q;SvtV{O-Xt zGy?`Mx=^*@8film5{!EXR3G)RuIr#Zv;-p?(bB9$PR&Np@>yNz12diH%e7LY);v9` zR$CRS&IeUPW^%Z6M`l7RNK?mxsqXi~Qn+h;<{v8apdL~x^VLh)A(%U1_KI3*IO_^RjFl;cX_nXO~Hb>4k5wNh;|CZ(}jcZd{h?Q@CaHcFE@AM&~jDwT}$;;g<8pvN~=NE z?F|Ez<>a(9)mFchwoRpc1X{m zD9$-5y{Dzs5hyZ;GX{9un)S0llxuT>^|a~`=H17-S9b^&LoT44Mmn$8mgZUwY{==F zk`aAj#Z3wpgp#Ua7J{wL_W=||7%crh;hyHk4<_g+Rx4_d<9NpSp!?DQLc4_0M#AJKG>mb&v zf9HlBaUzx_mB6!0Cs}xV7@AVraW0#9q}Rmwn3*IWGr5y6L@y%YXCDsMIZ?E2KaP26 z+o;uBO~Q`Ns#MafzmjHs1Pzmr9gOd#ivDN-x1u@y)Ms*zUU45=y0TCIA#4?Cyu6OX zm7lJCPg8BE7jZo{$`s?L|R`1-XRZ3u|$(Z+M1(qXtb8|UaURYKbaPSDRp|NBxIQ2Y+y+yTk z<)G%PttlqQUvWwOTt&M`(nZ{Ng3As(nZrkQx|dZ9p87tvs-}VWvYO%#e10AH@f3e& z^_+?ZMOau-UBbkR+vq$0d8DJfW&UR{i#AkNRR|^Ny#IBqqG(rqv5?|5l$RP8j~wQS zmnZ_&s+v+Tq1Gtw#6>WiH;43^Ala0z1`TWD45{M(|JX*WrRx6;q@!ev9L2sVt*&k0 zY-}j2Dyymi$)^6Y_rHjIbRH;o)l^3*!O!{KG^A>RtASWu3;I{g!#Uv5ES@}d+-b#U zg3`6Vii^s3aEhWu{#mr4imp>N{AX2y61>G< zajzn7MUDDsAdzc%SyU6Bek1+pKS($0e=_ntgK0+wQ#}9cz+ajN*}M3laBNc6<#AWw z2a+F!t_rTQueSaL45nj}_L$ZqR(w*{SnNmpU&&{h}=W3qP;V{(KK6+Br`@v}icOXQ0L7YnWuaP)O7Q9!GKe#abGeI7XpqwQ*OmM8=8G^F~`Qk&`^B^ekX~EY7 z-xpN;UkK-K>a;5@;lg4YV(Ecma2zY=_2@J+#w1pg)&#(-yjy#;dwPZB&` z@O;5}g3APdEVxPVUcoalCz)=EV6EVC!5<555#*T$+CL-sx?m8y4XE!Xm@PO$aJ=AI zg5`qq1+NgiLGTX2`vspAd`)n#;8DQ@9FJiB8G<>2mk4^ir|LDmu=}m(|15YS_9`+y zU&Bc}PjHUlT*1YHD+I3;yhgA|(BnJZCbHr+MY`{c{F$JG4;kj?@s;L_d^{0-f0E!B zBFg$rJf)QqUM+Yr5$P@wd4=E=qF*iY^@6tx-X-|2M8w}N@(#g&6a8}{?-qPT^m{~p zNAR%V5kVIp%B+XSXPO~$R4`9)xL}ds1i^Cz&l9{*utrevmm>X3MZQz;Zo!`uQLl$Y zenfDW=wA@|MZw>R{%w)p6WlNQPenc|_@(IMkq7IUB$!Hs>mzc1!GWSL5P78FDMa-D zcp}Yh=}z5BKW0*2a|OE{fH>f zK#@-(!hVe4X%c>hgwGSXLF83L*k3DnlZ4+a;oFJGlNa;Ba;p%{sW4eET~KY}fL*r8 z#|Y*Ng8E6tn7JkKNH+4xJ~e3!Cwo$B&a^` zk^WmEzb(i!Ys^1GFjH`#V4fg1jnHn4;CR6)g3|@h6XY3K+E)wK2`&}9RFIoZXvYmF zM8%H|OKbgr$qL6Vt*&{?*;b? zek6EQ(Bp;m_+Y#6z69xI2u1~Y?vVPJ;2DBv3C5t8+*nEd+kyuKJ^s}%M5YZLH^~rF1p5f~7d%#QsNji$rwE=Vs7}wqf1b$2f)@$a z3N8{{B6yYHHG`nV`Y@NyxS!U$9QOi(q%bo`M4e2MZ1pR6PEOH(KN(!P5k%3i6l@ z)1M_+E?6a4FStN(so=FO2Jye2EpZmmkC}YxLS~>ty!L}f)5Bj zEcm40vw|-Rz9y(BL=gXo$X^Qb>=V=NBA61e7kpQ6ui!yJ^}Ys_r&Z)H z1$i2s^-UM-E0`(Blj#gs-*bSoMJ^Lm?_q#meZK*!_b>ogO86?lYX#Q}-YlrT=fGZl z&jD@~{Wig!f{zKR?>Vqj-*bS!7yTauL29VV`)5I(qG$ON1k(i51$m;L;ll*g`x+ph zEb@54iGnAotm`rZRs zeeVGt5dFu3>U$6LUx=)}_dr(Pdw}WkJt9LeQ&4^HLHIC{j}sgxc&gwTf@cYmX@Kof zE!ZHqP>`$x48LBmS+GTrWC9GoUy!r_lwTI)v46@R3-ahb8wFPgUM_f*;5CA)1+N!eC%92?li=-wcL{D0+$y+DaJ%3R!JUGS z2|gwGoZxQ3mjz!Fd_(X9!4Cxw3LX|bBKWx=A7rz=Z9!KsQ7~CBO)x5$B{)cMh+yaM zcRWPE^a}+?3l<4Z5S%PHP4G;?nS!$fXA71IRti=NE)rZKxI*x9!K(zX5nL^Jz2G{* zje?s5Zx_5vaEstp!EJ)u1$PMU6nso@x8TcyuL-^(xJU3E!4CvK6g((+Sn!D8=YocO zU$X^WK^`$?KO_sL38o8X2o4e)BA6#QTyT_Nq2Or2BEboQJYd26rU{-YI9ssu_u6XF z*9kTXE)rZKxI*x9!K(zX5nL^Jy`XxIk8*4jd6VGnf_DjS5!@=cO>n#54#Ay*j|n~{ z_?+Nw!IuSJ6MRE(kKj9k9|(RZcu?@L;1R*k1zq``n<$tp$b%wm?{vY=-^;T^KS*$h zV4mP`!BK*Rf};hC1Sbei7F54yAm1}Zo+&s>aJFEXV5MNSV4Yy2;3B~#f-3|&KNq-0 z^s5E07hET}QE-#s?Sgj+ZV}urxI@r;9+SrP5ubtS-a47vaLK&Jk~w%E1b!%2Sn2uj zYScy}SH0OZcTPitkxNDHx9%PIKmH~N@QtBeu;lP8jJk#kdVt}ou73DWJ2bDlI@>Xf z*FZQI?z`-Uz@~G){2kW2Z1KzhdTCR21U7G>KfTKfn+gTK;uxbP;HokBjt|>zkTI;) zb6b|H7|x3WukmVkyj#Mnq%VxmU;TEqJuo-ECf|9m^XEHzqG9Yz)cG<$)`PeL&Y#{c zG*lEi@AATyK;cg>dN%nAbb9!z(w1Hm{9YV*jXxp1r@Th@h5ZVlL8Rv&(<~D& zqHlN@S)+}=>s=5*`4ORp=^^L3Lk2<3YZI`8uAh7LOpF9vVFzUy5O$B!DRUj-5U z?sq|K?5}cbdly6xtd7a|*|D3CxW;X>`_)Y{qYXyC^w^i5eevb&*~!1!#qW?RifulP z$&|>4rssJj_95t`6HoyQW5);_n_fsT-DRjR=%jB|;8Y_e>kT9jIGue1a-85a#`!J& z1*Z03hk%@V9IgJ1{<-Ow5!~S46gX=Eb{mOxU)nu@GFj=V9BS4A&<2HLdI?$T!MEvYoHE*CiqK=?HtqA)68CTOj~aw ze() ziQzh?Ss=lD3Ue*ePUP7u)!^M@qoL=oL^9M%M< zP{hP=7Ao(YBw}*-C8P_AQ=L>=cs`4Eiiqjq%`_e@Vn+B8bg?r=#Hf+NGtI8)2*)&U z+?{rgX%^e@aZEc*+Q%_Ho9183G0iH2V>$`Gxa7=UGjnmFC%@x{N=w$?QJ&wBMml31VY3G=BI&e%o4|pSi z9MjHrk=*bPnD&El(hq8}jdIaNxV_JugigaPPk7N2)=I`T}PNocwX>DH=;fZI*$1!~Y)AMmm z^M_Ig9Mjr!qF)gP2eMoou*Kj_KtX z9Epy{F|F1TAIJ20tS>mGbqm@Ne#LRViDNn)`6M|W$MmV}OdrSedz5_~)5%=*z%f0E zh0IJe;^{f+6*FM;*zI^6)1@>8$F!;s7pymX>y@E;F#96 zm=JlFwE)NT)hg?0kw4Jh$1#17;XaOOp0;;<9Mk*)>i9UOf6emwIi~qU!SQoU_of9n zrda~TF?|n<oO%r(a} zcP}oF)*{r1@{Zk%{tW+-?iC0Cfw;#pJqFptb>Nuhy?$I9$Fydbjsv@NSKP}+-b6db z`PilT5F!rj(hMZKG#~oKfn8et=md7@FVS9cUuBoJ7!B;wks z%wHl!5=+O1(3b^O6fTnmFi-8;0{;ZKvD7hBbAlq4{vqV~)UjaZ#I7vY7RYzOWw9{k zBo#NX#>h^G?m>hPFsI?@{)_?U876LogEk4J2b$(Ale=%ATA+UgGxT`VN8}e}#%F z4|=U%u6atLM@IaQlIeo4wvEm>fX>fewbH}@ASv#Et5<@PG=9xks0Zd6EZdJpCuwsG zCSDkxa7z_(EW^()`5i7Qz}7^d2}r^^1S^5F5ZqFP2wVXCX++wS{)ir)%Jj|f{%&F?q}^Pglk z>Bwk;!+q8B%gVoJW9h*2BCTR{WWnilp0%{3tlW1dg9q{230l5F$%5|Ir}P?gEBRbT zC|TfZqhx`WL`;qUjD3#+WL!z z%^G+5jEOUfM`)Z?G-KMVY4x=imX|g*%sO@4IJ8mC+^G6DzediG;UHZ5ku;nR@ z`Sm;_hogoa4?vgJ)?QS_6Lb22oJvxaSI#h3H58XFDrq~c=^da+{!`tO0C{lfS1CDXxtzkUFX>{s>g{75qR8`c8X_OX)(XH6g zu%fCOO;S@;I|l_qDT*uR<2-RgWo><9w4SHS_1q;2CxlqGn!6HH>v(z2>gL4=@#-CU}R* zEeF<_;JjKir5r^?XSW@~MOUc-rzT}pP4T?)dF(ngdI`!`f%#lr#j}zNOMP?2>!G%` zP^Tp8P*@&#RfkP0i}jgz-Ds-6RK3*cY&ol`+qXD2aq@U|LYvW5VH!H9(5aZrNLC-@ zZXZCHI^HR7J$2B^rPbvnHS_C?VwA0}ytJyKs=SQNTvA;Q^NLzzRI+Gc8Jbj|>6BBg z4dvw+JjJE8^VM8c{o)&l<>lz6s(E$u>&uJl8ZibdFpXJMT}gdNR5dfs%74d4;n0ph znSJw$?BfsM(PTC(TcE=c)?$5lz5NVnNg3;L)?};jD4H*h($@vXvM0Ntk0h^9BU8s7}f84g%J8j#sf*nSr{}MAb(hNP<=T%w4wZ%=y`KXOLIo$%t0|qE2H)03p$({ zjpocNt($*RDQ0N-qMUidAvadepEn0s0ewZ?g5fz0bvb4EBdOuw&MBEwby8(XeHj!b z^`(_3q0|eGE6n7C=sn40~G1|Ut$Z>fxQeg7v z4~UNEmFq?{7=9W9PIC5%flr|mqJ!9=XV%tMH$?HV6&+JQFFJnSobs|VoN31ARcU!c zLv4LSbW{$TI_KiyXoL%E>yP|yrA`?c}Dra*t*WOlgx3fnmJ zr9aT({iyG<)O~up0;JIG0(=&3e)+Y!{c67%rp{{n^;cV1>KDCsYfJs2=9lp;#dleF zsiOa~j4pl=>38iU<6DUDvT*v=e_8l7aR?NwCEJx}bEo(WlIia_1;2TX`L+YQ-p!%6 z5FlChX*`O9+c-R!(0$JHKdb?fzjG4tbFe!9lug9IV0o#}7sStrN{$JhE;wCqwqUtn zgWw{;D+R9=Y!=)kxJ7Wg;A4U>3jR)Tui*FRcy)h#e~wqT!}sTSbvyij{QRV$rMf zywIzC@4)Ls@9lS2=XQ~<+Sd-`#q#iziHIdtA=i4!S%QNEhYIqemf;fwCkxIHJV&rt zuvCzbSQ&4*pjvMsUoG-l!5anDdW-O_B0nJbu%P<9zz-*0d7)P6d-eGNzRWW}e!l#} z`_XW#_#J!F+CI_#uWwB2g?8fSKiiepa1Cw$(VXh)hyS$m?sz)eF^tzhI6kWUF1tL~ zbk5iRfRO#kYX}^MwJ{owS0M__^t;2+hK}+qIIj%wDt7xPF&Dhc3!4drKfNNP$DJ5V zk8R+kR|&rt2VNtBi89b@3||=eK>T(mLd zYb4+nFG`PGUf30o{pmIK({qC9vD#jG8{zljz-t_f^f-6C%L`ivg+IN^ed%%8@Y1^n zelHHwI1%ab46S#0VRu8}Pw#r9=k*(+w59hD{EWl#!0UP30H$Jodl$p#9vAfN_N0IP z{x#m0(cZge;s$b%CjeOwUN6A;%eS##d;9UO*{km#;Kx|51E^~S(({jfFE6668H{bP z%Y%}S%Xv@B^w{pq)0-Rc8t?QpjI-#G%S(@O{B~RV8OEPIBcNx8{c9sewQpaGe%JoB z{9y%odIQ^c?_b+JRAtz-O2gJp=iK46txz_&Nz}h zYxzyk&Qtdl+2g1=lxzl2Vhbg{^S4v?O-W7MpOlea)VHYTK`Z{a z-ESPh8@DP~>hfCW87IyjSNYH(Gk#^Om1%v_$C|otob|)mnXt2?mwR^RMB~BPyJ*)% z>;hBwjSU=~-34}T)UNWSS27NgPU}45hb6!I;NXuw$J(ODj%^+fPvQ#n?vK#+T!j1= z_Wh}Iz@~c>mMrY`TYzB|2si_5MtdytEoN8l*-}O7;7S9%uQcN zl^ay-Ij%!eq4vFgg$T16X*?u#JpF&+zq~Xqoz}ZB#s0pF;K%RDGnh*;{$YRLGf)NX z-S`hSEeud=DoTa@eJqgm1Ow}p-I<>!#d#&P@Vzgs_-vKD&HXudp@1x#` z=Zxn@lLXq!{=Tyyhg0zn`}?kdn*00m(Q??|*Q!L@uzE6)%@(6t+%1p&eUBh4$qw4{ zp~HsBanN?5-+Bc;?C&c>c=GS@kNf+$&o8WY;pC^%k372KX)yNp=^X8FS5yT1`?TnW zuS15|->1dI@DC9O`}?%$?eF`mN+=BtbuE1Hm*O9p4^-WdH(#s3{e8DU7ygI|93Q6> zFv9&Po*<$f=37ayzfXs{;R&okp@@m$(JaeJA|{7VYwc6juGZ$gLXde6f=x3|*96a{-QMB;J@$m5so}wxSIS{^@@);su zjtx5VkQw(|s48QBUk!3o`} zc@=*Bv6*l@cSg}k4ndn|DN@bkM^RMn?^_Eo{A>Kf{yzGd(O4F9p_dU-;;2h*Kv}uJ zF99*T7S|cr-zO2e7S|it-zNo={e4<;!+iFD{e8y)u-PX}ss-%t(_-8HK1Jw|nH-)- z;~kPxdiW)ZyHqO$GBd&r6d&)+S7Zb-qv5&inkRd|qQtE5JuLMzVQvizWDW|iVn)x# zb;HMJAah99;`wt7?C;YVQ5zfXscitrPk`}_C``9Nl2=7mfyhNn5c~T$N36`}0+H!dV1HjIo{Beukv&WT`}-!K$*jyh!N@A6 zf&G1at-Y1`VG!-lsh~UQH)sG~Cn@m?R1!u@P^O^GJ)&vm+t6@;`b??v`t$e7i19dV z+l>$(d$#oI&rzr*GnNm|%M(2rrQ>cM?(gGvuynO)p8NZL1dE7TyRpBI0!KsztB3u4 z%#6E_E@S<%zfVR4a%9DWHj__33F)f+eI#m#tVJogzfZ9?AgSLlD)#qjITRs_8~69| zhiFWBBc7hO5mSn-_xF+0ATo7|bfo;BnZHE1QYm~gmi07(KK_!L#ee4`gB$4(0 zz9*pQ#Z`y<``Ed?K4%%RzmK`<{9pAVVSnFGV2b^HRArc42Gr=r0DBw$pv{S%VRG_$ zb0HD_pnVjf@f?HwA*upkAKqZr0Q>v6@|kAuTbVKT_vI-O?>+8?aNLhgK$d+-Dbv2c zkA!u7{{Z{t(Kk^`BMN7j(OryS^d{{O_xDYKm1#Od5S9D;nqbpq6?D$0u;c!|&CmpG zs)F{7_}|Zb1W`@A83F;und(2}{>QOIBfD}VU=aeMaQ$DU<#9?EgCV~b_2+kKb5z&6 zVD~=cSEzIG&pbY*1#!v{d;wf$G1EIy>28C(8ZHaJjGBe2c>PhMo^aXBX9!#!zWZjL z$~dQWVx}GkVOarpw9Wc#WqlJYNzSCx);c4*4wg&c1|@oFU!bgc-16==YppY~SHki- zxU<`=io-o;J%$Wyx8(x6M-P zjDh&(ZM@cIdAYK*(Y#-@S!$gzXcR1Ui(R3tNWz%|r*qain0&usG8OkTso1ob5NzMD z81Zj-9EEw3t}J{zBzvTq2|n?EY{Mj`Zij7j*woE%ol!Z-0yBxY~Jj z)#Zy$FKMid$#$au>{}qQ^~3k}$M5$_tBp;a-ii4wd!QY2R1x2xoCD9n;SYk;;qsB!4##pe| zU}B4!Xe^0}D8>?SP4YkI-g9T(EQ?@CV)End=k2-Q@9p>9_vV%FxnEk8&i!{=N8=g5 z*+cK|M+@P1GMs`*boc}abZF(%w^A5>+tSn?Z?zQ_bR*f$c$tjCuUiw}p8+H35q`8W zU9EMgtLUYaUF$|{m$K)#loIYN!^c!an}pk?W5d)mwi!<%XnSG!aMP)-OXw61o-eoS z&iFugTC>$G5dNl`U`#4v6@d~vGG+mNXXcH^w_iZ4U$$Njaz`AGCZQ01P_mYmyXbMs zm@xkjI+UXM@?>7#XfbLnYh_mKEM@a-PpvhxF*Bv%e%6pXXXTzXH#X+Pc~;idG8v|M zYM%XVeHU0`fm{E1UM*{6X9z26eP_^~V-sYJGTE1}=Ynb=uQXLOu9g+={}mfpTCT#N zoZJBT<#Mcsd2pWOr~v_kYGY=cwZSKYAn3HmTC~IdKFboYcJ|h^{A>A~s&%^B@X0_&~4(ZVKm*4WsTf1Z)E!GY~`z~`;R#U4(811L3{lyH^iI+ z&g_3@{-tspj<4fdik74GoEzT4u{Bf2;0F<{k|DV<60d8w>@1tV+~ZW1ITCOx#R|+R z;b;-nV+M__hn)e^$v_(ETY83=6gV9%XC%l6620Q9JC^znIg`p+@f#+SJKmyb1TDv9 zjK4#UgJYCr**k{b5TH>wN(A`?hTH%WmthGwq6t1jEyWYUcf^)F?e43Ayv-g^oL&<@ zz2J=4+US{)v%+V8SMADSrWDw6k0?}r7kxgpLc91B!!geKe5&VaP%+h$<#;`j$RET0 zb?n1?Fdqz;`U?9C2MhTi%Xnio0h}qBFFUATAzUrIK*;wWjK4~_UU;|gKH;;%7lm&M zKNRBT+?3NuxSxxI@oXIT-(hi zQ%AYKlzcA{$8v*^YgN$B`zgg6|4)!#k^Xh*H%b0bXx2?fxn{j|qz~gW63dAbp)Zxp zWhba_A$X8Z|u#1W}S8Dot?Q^Umf*d zq;fJuq`OwQUiv$UNcStDvqOJc>7Et7Ohox_E8V-o52UXpqWpgfjUOqbFHP9;X`gGx zg9!cJM5OO5>@9tNBHCltSqF0MMW#Pe>5N|~U-AzW|0Cfw z(*KNzbazQMex^{bS$7@yl=Qz>x<5*Omx%byLbKjF+R2Um!sW>zq79Y^tAs;@qlA1d z%6t=qlZ3N{^MuQU=JyZjPm{b>$hWsF$NUZgeq5UK{hLB#hluoBB>zoVD~$1e0r5pbS`1Kb zFYGMrCN%dYi0>zPppa|(Fdq#Hh%|8_(qw?RNJygq%4Z1q*`KoUR|({Yeag2A`RSfA z&Ao{HI8S_8$WQQ;KNRvqJLR~L%g9kK71HXJaw{P}xl`Uxc#v>_(AWbbeuQM)K6oMg z*1PKoM3W!U2Jv%j&|P<$Nj9HPP)=HMTVY3GCt)99KVhY?O6aaz!zGUvn)`K>KVGuC zj?I!hS9q|Fdl}_od>@h?>rj7<^{DH6Ci!n?{NSD$V}i?udA0)N@fj#%2+h_S|CtU` z&ul$~4j9L+19r}fou%U(s9SIFQy1qLw~^Rg*_6+upx-{qE^ZjY_=)r?v2*)z8_ZkG zU2=ypRm^WB+jTT{mj^-bOw5bDT_*!^oI}BMx8Wq<+O}?Uah!9(dhgiV^Clr3>t%h+ zLOc<>%Y&eoM1nK}+Fac6kb~uwRoL^7<>9t4Ti*EyyF3VbosnQU1KM2N*^qx!M*)!@K9$qR}$ z#&PF8K``Cibp2eOhm;OrwztyxbCvaSyB~Y7eXpW@ICQ3cje)Lxd?rWt76Q!HtaW~Q zY!f$PV0w7NkuD7-jS(7QXL&52bq0pZn~V9^8#=eS@|Y)>?tQfHPc9MAr306zPp@=t z+bNf4zx}%RG|6|)gspEs@D_mj<~&1-vq7X7$k^sUmHZ;yQ3F!JNuN4@u6-_J^mK5keP z`?z6j(0fILs@{uLJ+;*v{nXY-8( z%tU4JNAcoAC)A?;3+KgH$CpBtJ+kRZV88bZMF2b9bBfD<*#gM??;i9ggc)?7}pgR1W z5mcp1_hUhKBXLA)b^jBJh+V52_M%6!|@prbO#Mln`JF#mEdADs=sE+0MJEa(`Sb)D1Vq&ReJ`p2y#b=lDBEq9gGfe~0VA#&i6gixCnK;Ma`2)oqe}_NM@f?4L%e2OG{GDxVb&kJ7)8lwP ze_8->G4J0shYWlmq;ozp?%Rf9F`1AK>qVm_ESYxq)(kzcY%% z7~t>lMQ}X8-x)?Zz~A9{6%X=vMzFvjf2SuELH-VDpz$Do=PxYdyUpLZjKk>oI}Oo+ zMBMRr%(W!I-&xNQ3h;NPv;RBd@9-C+pBt0samN6Y;wI9Z)=S{GHF3BFNvNnPxo5-#LhN2KhVhu~R|*&eKd0*nK7bP8{oV8~zTjI&sI}8NiX)A%EusB>lGd zJAK)M9Dj$tNa8{M&c2Ap{n*8*vK2o8S^iET*5@|-opxyGDQQwXyfk*tPn-9NUdzv* zD$MbB%v;a1gZ!Nu}`xa?*5H$LOcoCow1kmTNpSz)XjiA277?R^AW_&Og0qpe*cC) z#3OGhxstj&JA6$%*x=OdI|RnG5EZr;V;T z+f{~QO0bu=GrHE)^@n^Q_V!)T*5P>OE!d(gHte+@f)sS>YI}0BN%1nuc_~|#)p_kZB4t;kwCy@2P?imQ?Pnpy(b=+A znG_$Q9DaPYJ+L~jJwI!on@xFB3yxnLL&;Z~cKoc4w6kv5z4k95$GzDc>rIXyAcjv& zHiy+c2AMa%UWbwr$A^IAAC~w8xjXI!C4W!pXMJzzy?r`CQwfQl)s>4z4iUa#^bb$a zF|5hOFSKKsixDQ*0!Z^ru6CU*y(onw$G zd?RztiT)5dJAVje$2air=SXxL_PrTf@dY$k?uA**(E*DR&GVFUZqJpET z)N>GsY{5T&eqy0Z-4!V-n3@r$j$x2U&_ynGigl3m@A;=juZ5f&hiW7`mRT9A&UA5E z_P&Z)PK)M}pMa$N8g62g-0OM;ref$bEE^dvLQA`~p!hdGVT50zh|pF)!85%(mQD3S zpZkRraD^qIu}2h_v(WQcagxfg&HRGRY}3D_^xkgjTPfbF{r6Je$WCkXO~`NgjJNiV z@z$XwTnLQu?;6lxTx@)UqZ%C9!0_OrUN=Xj+uL&D_UV~Z?VHU+LR~IfC(E$IIl}xn zCzuDH{<6tk9k^~+fQ4u|h#eAXQzJw#otUNR znQyM%No^HH$P&G_C+G2vEy#HUUI#(*9PAL{83uSEfRM;Aun{|Q5MDOH z(S&!fgFhF_Fo1XpmN>@G#Smf{2HIO8o?)P;6^ep1yFAibJdU5DxMS6^;2^7x&GfyA zguAhay^|vu25f6jUKwcZM7H(??BLW9zQ7I^UMRyr8`F$MkqiU;WkpPkzk+V#NOtG| zX?qTx9mz3-iP%B%BbZA%sd)_8=75^Vzy|E#=_N7@*pZw-_%n8J@d#V7gWwp-FhI%^ zgoxoNwz5Jj!$5Z{#4`+3TA?VzzyK@cjUCP;nM zTkLgjmtoL$_$b0HCgFI3?bdQX!@jV5<^c1K!S}JFR>J4l!`@=w413ztFqXi9XAUs$ z7-R?PFzGwp6j@ZHGdeq2BuPU#!#Mv9>O<&-J&0gct5wp>|9=TfvbcM&s8iX(CB{jdi{3wPHhG5cDC zPiU3xnW0sN@-UM$(9FJ29AuQ){_~bDjh)RY$#46??G3S)nF6i1-y1bth|)F&s1b6i zrsj09M3}lOGUV}j!i0QN8BZ0S3#gZ1XUJi$U>^UFxnR8mRbzaix+KIgN6+!U z721uA##y-(0 zfjko2dA@Qm-R5-nLc!f_Oyh<&s9y#Bso2+GKNEZ1e8ISL>xsVvy34R%j{VAd;)8M5 z)DwRTbhp=|59&4`-fb@5s#hxsw)3C+uk+js)Mhn+ufJokCh^89a%ofiO}sFm1* zTX0@*&8e@=JmI|F|iAGKCkCYFuK7#?_Hf zv_*JL819;ylpR_Y^CP6&hCf~Dn~2kFM3-#D-xRUhMwDhFYFGNvPT=lFW35X|N&PJY zv9~A|UgAf~yF`mBxP|vf3VW;0&O^aVYnjJ#dQQ)lk^;$G^^jDe!LSh zJx67^K3;f|?fhSCTo;tzDHgu;B=jep>r7!qn^s+;t-GN|i_!XUaYeMOc~`2scERu- zQehf%d$^)vSVb&68C|eLdyz{2vn@S0g5NvI$1&QI;}PiZmj%mA*FIrEP0LDM1!tHF znukAj`U+d|<>&zT)IUE3$z$PXz4{2+U85~5-@MEmNlMJKJRNP(F-9J`(U()Vlqno9 z+vI~sFH*B}Sz~Do#B%>@zzK#Fob&$VTtnr18(TQg5v+MEs?qP|-K%HA zm)UN*HN15F57Di&)AB14uNNNHt(RBr*w^(EpOFA(9XZ+g)aSxgW9>uD*? zXtQ^G&1^X5%FfHLxo&~EN3gE_tiwF|phAPKv%C77eBnx9{LAg8bUTk_&i!G&bG3Yb zTXHdn-vPMln=yZK&CJF5J{PS+x%#{W&X{lR)aWH}#dPmG!0X162HiaT>&|~Y_^;=8 zhU?un@La>kngPXa*A$)}KciqRRwzF!a(4I}vc0|Uq#rTb=;t=vTnD!AGT)oyykow% zxx(y-?~N-YUtQo;MV#*mf%p(h+i7AGAxz5a^#|5N@qL7Yg(HM~ZNPFS38xDe3s(qN z3oj7zk)HXk60R5CExb?otnfwQo5Bx;yZPRB9B1PFF2{2>-`kD@jeR&CyZPRB9RAz+ z-W!W-KVBiiUhp;HThcq8_s7z2mEQ5Z3-AGz`4U9T3&-@TCR!KfrX!zgIUnBWuBHDSI@R!mX{x{M&-uFw= zzfFYx1IgQn$p3dC+r+&g5$T#qZY%62eP79gh{!)wI8yp!h{!)p@&dA}|mG|6j) z=Mj`s;*0mHro!|DW(dB3=_dMnwLXq<>ZTC+Xjl{DE*A5&8b1_~K&7=ucx| ziiq;klG_Tq5RtE^u#a$v;)e?llYX3VqV!XQ^Q5mKqMo(VpCeo+{Z&NNcb)Jj!h4Bm z?*`$c(myGDMff@qP({U^e0(uZK$M14%yh=}@{5|OXH^!o_ANPjR9>8d0juK4l7 zW2K)Vd5&-?5&2dq{sQSQ7G5U(jYOooS@OM#-ynQc`sau^hHnbD2pg4HeOidyBvT&m zbXhK@y+K49>?=G-I7m2DI9hnP@L1tw;T++7;qgLpG+7@%?GVopo+rFec)5_Db(ro3 z;Z4Fjgm(!a5I!t?M)+Idr^0PQzME&c5n%&iLm};I8PBC-iS2}Y3%MvT_57qmJV1D` zaEOpg%`)DtcW{(s8t_t2n>peILb9MJUoN~-c!TgJ;T=L6Y%=`=!iR-V3CUGr{ENa@ zgf#Z2{vF{*!cT?&5Qgy8g6ZfPh}clrOxQw5<738~b&h~_*EOIaGUMk6mkLi1t`e>h zo+C8tAR*snlCKcnAiPO| zpTEj zNZ%8b|0JX(HDwyG6KO?FY$i18IYF+FOp9v94-$?O9wnqvHRIPv+wVJl%9Aq|w7?f~IfAvuWDFAy#k z(qx(X9|?afyixcw;m?IMXJ-1Rgl`Go5%R&B@ev_yn_&tYY^CHXA+4F2?kM3T zBGS>Onfk>-+AdQz>reqNP&!&KQ-6(+M#_}$6y8fjd9*^N{#oHm($m(M`c1;WN>7Vp z>Z3wh7gOF-*qVr)cEr^86wy9)94%;YogF_4aC60E;cSS76cdpBPC3BpOjX~KoV zCBo&xmBLlRHNthmON5sRuMplSTra#;=za(9m;8|MG2v6fmxQkhUl+b5+#>u$xK;Rt zFs|PN8dh<9Xx2b16W0B`>?nOFVcp-$KGOFS4iUQF%h8e#7mgRY^@3(eo-14^Tq0a9 zTq!(Lc&>1r@Dkxw!XFE76s{NECA>#?zwja9W5TC|F9}~2zAmi$yZgTMTZEqow+g=y z)?H`lU%c)L-VN?vcLh`5Y&ZmF>wy2f&fq81Y(0ezT)IwBFwAQfH>MlnA`y;IiESkI zfZF3+J)p!ynSU;B7$iKBm}?Rv9zz9Nq2N1OoPwr2w(Dr@E)RmSu-^M&cSa|3te5q%A4J~MyF3VbEn9eAngMMtj?VzW@)jOQ zlTlk9Udv?5J0D?}2SM*Zl*ju`x4F2pp$L|@3gz+Ouzd;au6=H|=& zkb~_zvobe+jS=VC$9LlxhJ^sL^+S2Vx$62$3=FHc5b4rT(ku~E$CSt8!#drZN6=e` z`9~8(x4H6|Cz$TC${nq{(x+SZ+_Eb>_o3XaYu7%zxb8|NPg0x~w!a;*9#zW2nk$Jd zcMRVMU&JwZPmYE@N=If6K4NoZPLs{?6&*fkzrsH_g3!3l1uJHLaQ%uH(p4dR#O4B| zh?x{oL2y*cYPd$vUfoQlxK&A!R80oW4pKH@_*e&16O+PFEa`0$D(;zNj! znD|qH8#hN48(p#Go`r{)cb;Z=BK~m9|HRu6CK^TlzmOk01P2xCrjW#mwNlLLu%QC8 zcw8jP-_Wq(T#edeJaUF2@J0xTNB3v0c)|Ce%&m`d9OA+wF*)JWcsP^CBV3g>%q8RC z$Cyw0(a2T!A2W2zFqeFTALBvLgl8ig{1`J_5Qd(9jF&(#evCIGP{;>1_%Xhh;pGhf zq?CH=x$^G_G+=u9G3HZz@?e&EUBNu4LvTgQClvTGe$t5WV@wVz{1`K9xG4+#S#w^H z=*M^vyXVK3BS%Aq!@ocXevCN?CG@aIKgRU*mpqpd-AawuzpNi)TVo{2XD#?Kwqo4+ z;O$;!#YECL9_`-Tiq4PmC#OTMEVwir6Z(u7&nvOvZC9h!e!zAOSK+%Cv zaM5GaW%w~3gvyN{V-oi5cu#E1FiZcOEvt^%hDMUS%E6DZd1fz&k1-1_ zsz4_0sv#QTf)DUxd^3Q4jHdvTe18K!#tgF}{>;FSu`0sh;cr68Q;4M><5$or`7u@o z`7u^{`7yRqJo!DAo%3USHCw%%ALHJp=91*ESo1xa#m$nucYq&bjuQPCAH=*5w_Jfk z5`rINjtl%4UuVR&NiIVKKgLfOv14*N58RW5q?iW$7~6`nevEAgvVM$hoBJilvfke{ zGLMVpmB}6~>bXX>rl_nRV_Q^J^8YdM%WCuRNaFl)9(0Z z{TOp}Qi~wckFo8Lm*N8e{TP$cO0Tu2a3rw~ik0K3y{z2I%8AscYzWptvH43<fSV;kQmRlxLE2jyOqAAXEkAJ##! zmy*g<6=kf0V$)Zp&ft7P;C0qDPBqF$Jo56gdgK` zm>%n(n1!9;zn13}{TOq~7(d2OvH+}u!gIvTZ!(FPkJC1n z2>CZcVf+?z7Mhb;evBKSeY#>6+|6!c9Tcuy(5x9IM}mHgxoUUHT)VLjidn)N-fQ`) zk$#Nr2u4zOFe}zU(TqTi>^NLC<9{>WhZ#S{*RUwAj!r+u6mYpnok1DvpjbJU;#;xp z{1|gda5dZdG5!oU*{Ls>6ziby*NjD7L>cR#*y9*Uz0Ou*9TX-G!H===D2{bd_%jiL zALA~J$2uss7ei8fK}bKwGfa7-Q*$v`^kZyZ$Y374!+5NNVo$hPsS_EGbx^FlFtvd3 zSO>+*%Ts*eMnA?ebIjq#m@CQBk8x9@fFI*uv&C2kg)K0CjJe7Q{TQ7`>yPAJu(w%+!r@BzIHY?5 z^4-+Y$-O_kF`qp9qVV3>%O7Iikw&)w@-f)WvL~ZT*_O{Ceuf=s8u{&tOB;lXn-`CZ zHS)*!cq;HhZM_B!4uTR>v8iVW*v4rpZc!D3^D5d9iO9l^l_E(${P-6rt=QS|l=Tpc ztmKau%B8GID)RlIrPMcQ?F}uZB|$;xzzp_`ksl0Gt8l%?#P{IPk^;D8eP2o^kBd z2R8D(eW)$s|Mt9ZJ}-koPvHCwdrK!}80ct)X&DCkSz%U&fgx6yn_*zM6^3URm}G^~ z83yKB;c(*;cBK`@XBars3KKHdAg~@g>L=W7^dQ?a@RSwe83taqLc;h%ecuWt83y>O z7o7Yu!!eJbs}O=-T3zQ|$C2E;A^?4!UFK;FN2^OR4DhuDglQQDCRkxshJoc)m}^>m zBLrk8JZAJD+%xcw72;;$0Na#BLF&3|f;|{WtcHxq4a1oA(Ar@DQ$9BgHNj!12@XR| za2RTW!%!0(2G-^rr;fcIK~9!@+B~k7+&Ep>KQnC@q+Yan2JL*AKxm5{>n9K{!H#tm zd^12SU$l7!e~BHmdBP*u4Q-y|^=GRmaOgyvXOM$emo~pA^c<*=w{8SS$);JypHQ>4 zz<+avG!3>ob~3mH<)!%X_}X;E-2}zX(!Klcq;?Vh1=PsQ# zy?(mlj2_)BU2!{tBIZMmporrwf+9j$f+E6Mf+D83BPc>Gf+Bva12o7Orc*TQD)lMc z>KI?C;nsc`h-NQ^Q!te>hqK!L1-vtyvxJaFWU{@sxr~<({ zvBPqC8O+6|SzMjiZsfhqHuSmXOTtB@#^t#;1^2JMMzIu=wGL(OD<|H*Jy~j8&{v*e zCOBSKju;YPU>RCTz)4>n*N1ieIetyD+m5__I;Vqj$mw`^&KY39pPfr-y{~>fQjML- zWbXx?O_D-K4qC2_Wbu%6Gksdxx~w!_^W;I2$qnPql5-Z!ub#eq_L6Et9DzU71;@<> z4Xb+b%(+Xa=Qu%dWH}kc61aw}p1K?~9z*LzGWlGzUMJD(JSK@e99BCwrEoK88XoYi zS(9_F>BuWUdS+dUPFRYdr4MC2X`*W563~$gXHK3sZ?bV#i;yEYX5F;bN1wtlqJky! zynN5Cq9!>;BU+Ef*&)bJXx(XAM~|$ydIo%Cd-XAFCNJUG!Vf6>AYZ!Gc^+a#h%~$? zuUbAd+slvX|V{^5D*+k4{@NQZJr18w~8(U`JYqjq-Jy^CNov zRQfx`5k;2Vh}d~!++{i@n(ZLxR)FnTy_gOetF2>Gd8rM$6O{v8sVqga+7TlI2S3M} z6rl;edFM`_Jb&pzuX>06BBx_AlZ?Qzv}CkMRZ=DcD~p2k|o4PP*SrdK_4 z`Vw4`rn5{ab$Vp^T=mi3^4ykMKc(`cY5K+n9dC%G=8ROCIp3{W&zN(2_nchKgAw4+ z{$Fw38+1bInHipA7t5QinN~|?&zo+>2$O5UVqE8HKo`yta&cu1URaGoU^5{&{{JDT zqY2zm{1cn+g;o|Pl3qG+!^->BfyE_jBBzJX2(9%)s~&yi;fL^$-@gYEP39e#=kJYR zbiYBJM|iPh!HB|8QLJ&K%x~hS!p;0W{5`QKVGF-is7;+aVcwDFwutx9KXVfAi-WP0 z?VYtt6NVlc_Jg5lVgH!!o=AdzmcgR7rKgc`apz&u$Pvdd>&7QW){EkfIcX#5> zIB0#9uD@`IkPkM@e~fU7aJJCcBqN>=)J%7_@B-o0!W)D?7dj5w^OFB0EWkLhoTkF| zLM{b#_Y2hov_k`PoaZF*Bv!Bq|xB8>`uM_@4_^|MK;oHJbg;6~6nEHk7guR7_2*(R&3ln&m%Y1tXI|%m^9wMA3tP!3n zyh!+K;nTuD2*0VX(fK%M*}hYR>x5SeZx=o&d`|ebup3@fGk<^KO5s_;8-yPVLwLi< z^rgZ*g?kB|&r!Y!Wx9ieRl-AsM+;97t|sDGoi5}G)#QL&p!mxrUn#s+`dcL5F1%BE zGk)IifqlNsYPno6_#2Lal!o|Ylg{y>X zgy#qyhvPEIv|(U**9m_jO!We%ykdGDvL|i_<)K>gp5tpon!vY)-{<;Q~H=F)Y7l3^Z0ZcNAfOSkbF$c@*yfZFQ^fm~jF*VY3zk=f^4LGN4?~nKZ#}{+k9Jbr zqDXL=JJ^sJ$Nf&BOZOu@94&*+Z7$tIP%!MaGW-Yz=a!o<_ai~DeZvF&rOk%x@3RP_ zdkX<(8&an{R~HeNk?gh->C#a0qYj41l*e&roq^%42 z>ALjj(_{a1ZriEP!X90Fb~VX&?z6CK7gJ%L?QG|Fw~ShQ>luSDgR_)#2Zt|;t~+UC z+2HcQ#UG{p#7F5+y2qGz!Zry#azdTijk@nvJ)jUi7N@-*AUJTc^nAWs5$N_H_%1bITp6G5K%4)QE3 zVe4Gm{5}KU4K0IxaL7mh!XKr>7d#vNVfgZ6{5`9#th%Bqd{N|w^m;gIJx>bga@DotM zunYfVJ(1ZD_d%;*Bg_VcA7NyT2^Z8NJ#B=~h0fRrw?vtRd_aYb@CQ&9lE4TXVd|}w zSZ9Qc+bP)ylc}35#Xr~xpN>Q{^V~!+;46{Fh_Df6)-X**VIxcfWZDQXg${%GcU&B- zufz)w4;$fWh%b2s|7au3BawU#|6n7`FzRSjeH@H}RbwRiGc*%6!nOhNB;7?9d=OxOs!%0uiy&R3$bV9fbST+F8B zd?migyg6Tq_p{`juf*3_)ONlS3*;;D6C7LE2)~aOa@5Ny27D#9!9jc_zc^f?<)~D!W=Bw2(#d# zi71G>YKTUrL4b|$O=v1@gfC)6{C$LtFvIM|zHH`pz7iLsdfEs#Ku*~RD}!u=Pe+4b zfGQhdE5(z1rVH2z8(YNfY=mc+noE*HnK!OE#`r$qE0JzhX(PM<<-im>bq$9(;46{m z6>WrhS{WPRb}TUHD=|Su&{yK)EHdaTaR|%!Zu?4H#bI>55^qNbjE(SG9Q2gAb_aYV ze!|`ad?g;p{_n_FB8}6Hjqq<-lrgM@jW7jVE>dSPYrt3H^&C0)N<0V$IaHqTiWqnU ziOn@A(>Ic#;nSK?`?7EO5ROdDWqfFb{6?%Q;p%^p$unl73sh68B*ba=sELvErbw#O8>{{TNp)XmuBk zPtHbo1)e ziC@b1hS3P$x<(`4$N$zo-{Lr5iT5HEH^0q$C{TV9`6_dN>}|GCXZ> zK8@%a>;MCvk-FTmb*vgh|Rt?Ph-li1r%fu=DV z_c|o@sV(lw`x!Tf*P#GAX<9y~WZ`V=rTLz| zS=OdmDfW;_w8TASQ7y4~Fu&)upj|V|Z7IKArrd)QG|g@mforXU8qi?dI@n^my*k2h zy9M64r%eDaj9ORt2Pd4pcZUQ$c~!XN%xxo zr#B;@&u&>;Eh7&yWTvoZ`!vBKO817}-dVTOV4 zTVY9t0p7}>faS(P)e}}&nPK1y?6BD-l$Z`Inv`Ln8FqNyBD6Jnc-~@wUpe81E1qFs zq7@Pu2F|uZNrnO5;2~LAhJm}RkZ*Pimu0ZJHhVaX1UT%rDFoa132X=}h0iTQN9^#d z70EDQ>xR!Q2Bz4UM1}!d_sSAew}fCrR_>r7kq8b98X%u$EWSN(5AME(J}b!VwlZFv4qjsVSIc_h5Do*~mJ^$Ecvbjni}pb~vOWaH591MUyy3S6VfJvlQxCoS?T_HGy*#>V=%0 zf3|7@I|KD{PK3eOF=+{Gf5rHSBf#Zu5CCG0!h{#<3&W86kaYqu= z@M&!L9IGa%;d9yWE3KNKhA&~m`4J2j-~=^%B^%xoI|hZIhDSJkml^eF0>>S#O|TO` zHtNF(>O>jJGaHUJlI3=*wK6+Vi5*9gU^`J`Mt_M_6Kp4H%;?`})dbs#8Z-K@S~cMl z>>;mac}KK`FXb`A2(}X|&HP_s)ME&?6D#BF#EnKhnqWJzGJ7OwEyF)VnLX^Y>Gqxd zIF9-GCSn}Nd4mmdY$d@#F-?lt&R}Yk~h9L;G6S z1k4#`L)*(=;4UF-{4t08S~&6LWgMwk=uWL#y?=oT_-@ZV^?L5f_n2gC)B}EeY;aMJ zZvP?6`2A%VpP~<+6a0QKe=khKI{x@H9l9_WqjMc-;c}(|M(6FK1+lWuooV7;T3Qx8 zIOcb$h_>q-t?IH@v|X2IRYkPhUR|O|ChZzbTKaED+9e8m{%)P=DrZtfG#O6Qy1!e@ z9|py-73@%lQ|U$sCieZ*l_s5RSI|`Yp6Swr&16Rou83B3j;WFX-S*uoS$zGjrK%Qq!Y|JZzw$J%?)XrMo8JGV%yw=ci9qul2#=l?N zVNJly*4Z4(wmNG=95gnTf%d=JMNM^%8Uah~-aTpG%=VBVu&8$rC+?c7n%ypGU=sho zKuuph zV)Bw%gTWtJGJC=N#a(t(G=8SpA)5DRuc0C=u#OJacD zkZ%I-$Qb|Sj%B_hw)-6e_tbodt=ET4|KiHf%f)TKi#GgxRLE_71C-moi#Ggwp?Q2Z z;aJya!=F8KaeB2~vcr31ypzBqQvBPq;UCQM@Sg5)p|L=KJX7*q;R@kup|jn;MDkU_ z^}@S_&W8V4$uA1u6n-cKQ`NM?*p{OH{Uq~^0^4_lkPnlTmkUo7@=XKvKNOl*Bak1J z{DQCuH;zn~61Eri5^~ue#*Yp0 zd?NinrFZ^h;`pS%@hByt9OqA_h4dYycm8Ddmwce`P~j-yvBJqh<2MH7E|!eTl(Bg> z-x~1Yi7$5f^^C91h|adzyuyOqPWrut{E)_UlZCT{=K2c#V#&s+3-T(-YlPl0zTl<)J>f?}+L2NJ4`GPcRmcs54Ta5w zErjiadkeb@dkgDw1ExtoOK40aP!G*{SRY?%5>FPIZ=sMKN8l3aFB4uZbR2v99OO8d`DqVVIQIS-9i2#k`EV-7xH5&%U>cq zQFw~b{0<@hTFE~ZauGS^yHn^m0gp=Ns&kD0t?&imYr;2$hLeVLA4oRbG|1+64am>9 zEN5R~ccEF55c-284-gI&ju6t+hxwh~hDnlX_eK3&;X>i@!V`t33D*kG7aChHTmrG0%Ckm$s>-vpYD*XvUeo|+?p9r}^9%bh@;vUKO3m+9eDg2%A zMWOR2@rLC0gk0H-<$fyMCiJ1BJ}OKION3l1knt^qv{9toK}g#J$~}aAg$D^~Ai(%( z!sCPsgv*30gsX+83(pm<6J9F(q3~Ma4Z>T5G+$!9cMI2h;MT&cRK$cfc%H#LA%_EC%455Z z!S3=P=*`3ZPJLXNd3DmwZ3w?3EJ&LxV>aYqz0Y9)D$yy{%lg<4;!5l;4}#wQNRVbg zn~PfxIapp9J{EF*vpn3cWy|BUqRWGzcN7w2KRE{C&Ota>UfV!2uL2ouI zbO#|2_alUZ<@H2)>>rck6w8)(Gs0|NSM1zo?}6)}JJ^sJ$DQ|5!E`Ot^>bw&Ryu&$ zE=k*E=_F>G`T!Kc_Vo+&w=v>ee|e9FxxCQj-Zzv7Hr2|){_kQWzmgUOyNvAC*#{S3h^1XZaPN%zd->-L1lYHk~ znHH!M+jd+TtTi9^wya*|VGVh#H;=XEOCpa9?zOG>p5EJvSN7UgvcC7Wk}C>o8+=hz zTkyA2$_i_XJ|Feo+~I|_4YobCY0mJ1O|yr#-CFWg+pWb{^x9U0Tt�K(542b0v_g z2)Sa&6+^B#a>aL=D~?>TD|&AWAxG$*UfUwb70KqZZ7cemEzPy?-jDp^wp$~}8M-2h zUUJ3!2zq)pR<(~etE}o@HK2+-nL{_;y3M=)wr!!xTepQ4-nPw~6sb*o8mTS#WL{Z8 zZR~H;%3`&N&!U@V4gzN^~+v1hC zZ7Ujm>$W&nmydoFsSSTTw9KoGd~yu_N4Gq%XI{Dpj`NKN-H)8sN8$-fz z9d67(sKV*e{g6C79*Mz|IgH^?`LAo)G!_$&jAF^h;9ovBW)U)ExiM^ne%~^=JG2{Sk&yDE|t>wmWp>%L#I5_#-m_{gc zhuj$6n+3Qr*P_AzH|8uf@2hfS+M~oQH-;7%-83}4CFad zo=ASgs_rhdVsWGDDKor+Up4w#+!(GrvSV({DpvIG;KrnQ&~x0FKXLx#xG{WW3UFig zW#WH7H--?EI+`FNilzb8*>lk05|6E zEbmLWFmC#-uSF$d(~FC7&Bp zgRFkf7;?ZE+Wd#yrW>`r8gWUYN<^fwx7m-n-bU932^(W?GZ*E8FGFt3m5_PI+ol-* z{63BOioO^VhMywK2Qpn>qZI=+cXMNQb7OcOSZ)kwaXtmc@?Nt4F=YY-7|tNG&^}Dd_e5|X z>{xTYCd0sJD=f({Fv$wbG7Owyh2|pD1kZ=$}lj*3Xu#0TxJR}u?zz%tq{*JaIO`KcyepY_Ae9)^K#*O zco?foV+V_Y(AH#K6fzW>!>tg>FfiT# z>C-0kNq6tstxxAgJv+~vJZC}8gt@b)Oqe-!>I5X}Jb%Ib>E8`!4f<%-trx8EFdhEw z-WvKiPD)vTeL_OX_YB*jOD8fY9QlNdlXiQV|6L6C!*Vo4mmmeDNhg=Xa!~#iIZC^B zR;yechC5PKmyxm;y8%jv;d10NQ)Y;n;z%}zj)LZwnSv1zKgE(u$VoXkZ73?ByyWO5 ziS%Bmp>;mL*cB-ZZ}V*I51Lt3@NE2 zH?AYo!XvkZy)w`7R5;FG!c#FngFED@;1WagnQy{V;d3bMy9WzL2*(H~38xE<{WQ|A zki1$*+as29iSR1ndg0x|-8>aLPP=(3b{xK`&xu|*0XXltR2*@faE9=B;hDl82>ZcC zl<9{GjdN_sGbJA{yhM17@OI$_;Wza;F%Pf$*p8Eg=LxSA{!Dnk@LAz*o(jedMt$E^ zo=PRJclhR1C8RAXW!kP1#|tM2&Gi-f*^+C7e7DNwuWH-&!@ZV`SW{JYS{?-}do2RdSVA(s}W+)c=Ll$84k2MLD? z#|RA{5$UQWPZiD;E)N__pv}A=h zRsJg3@l|M^#C#F##JI4buvEx3*BQT;kQR@W_Yrm%_7>u2|4V(SRBAq#F&%F2o9TM? zZSg{ItNvf_MCH503kiN2!jv%^e_L_+&2Dc&*cD#LORaZ}7ji7_({_ayGNGa84Z^&0 zn`;w)+i}a{RVre12RvsZT@%Q-tur6Kh%2$XJP3MMV^XFW(B|TnLk^bbb>1~z$O9-Z z_{8eUtIG>136#fo1srF#?`rHW4}#vaC~psU5CU<$7YVj6jq;eE{pAz1EAM86SzcG{ z+}^{~>Y_{PrP>*_bDot`FMxhT;e=9e5%8_e$rsUEqc6 zvJaI=g{d%)7XnU5V#^(iH+mnz&G<)Ya6;0NnS;k|E;#y#&G8jYuphCxU`~e**3N1F z!P*rwKe%qij1R7xb3DS!KA175YIDJgs?G5^<2FZ;K8Ex$q>p|{`Y6)JkUos`5u}eG zefUe#hmk%q=ZMWAqzxghkG%fTJ8F-AaMk7zTIH{Zp+8adCxZT53g*Y~vUFAJsy1SN zY~1V}{p@CM#YU8OAyRihpJsk=J^I%kZE0uv#yOt_CC8g zyyG_Py8&(3usOUUg**}Di6BoDd7?Yavte^|#Rl|q%RLJZ@$T!>0KZ%2P(}PU2qgA} zz?Uv{H*h~*;BTTIKbjDVF2=M3-{W0Mktpv6!m}72wTF2|i4>Th+<5foykm(MoQqkP z<9M8a;=>)G0+(Yr!mu42%@QWyAGjQsLluo&h5xZbQKlbmjNf7SIT-{^cpD>YOt^sb zQgS(#Kxh1%Y(}7v>-vMs!Dp4iOHm@Y9MoGsCw$^)!1VHS(hjXi((VOZj(JdH?fK-M z7zuDWo-|^_3%6h)H-(us%sWSLInGCzeoh7!zladH92|ra8adF<$%DXT z7=?n%!7%EOpA%bSB*`_n!R4@GJV`PQxExkYB>A)fE{7FM8dWd%;OFFVQ&1TOiu{?P z!|?C-*iGM1H}8PR<(Q9ZlYd48xE!_sFFBE7Ux|?8|CLj8RX|g>E-9d9g7RtuK!m^9u&D8y!{84 z!-`ohhavHomn6?%;(IiUo8c2a#0SkNh00qbuV?JTEmxpY@7Qf`OXY}PBxjm zmB~FQKG&$$hyxo{&qYx$s;H{uKiQ0zm3MgZcWm=3Mc14Dj!s_4*grP@8~_I#Nn;%T zMuPJ-R6ah*8wL0|;Taq%pO75Hir&^_n+D@VHi%i9n17rtO%CQi>Tz7ipK8dcrf(o* z{hV-gQr~B}@N;52zykY<$<$Bb?~-LrvG4_@1eYSReeH*!VuF5Jv%Aj(bgfzZ7o{ z=;y> z>x>7NW06TeKE?BjTn?T}#?Q&&ED(N9c#ee2p9-Z8paOnQUOyyT`>!O&0z$WV-`Bo>|Auf_&MPl-jum^gUexF z_rf_zCw3294m*O8)amR$xEz`hsF59yMp%3^8c-T82VVxK_@=o4eoiRha*=wLS;6J7 zaxArqMc4In!q>-Yw)J!J8E%MEd$B0^IpMDvi@J$f;pfC2$4Kg0b_iS!CZ?a0$9W9E z<>1dmsJv~8FEPmFu)P?PI)>%J&&do^-ssdUApM+7HBB9#+KcJI<*+B*tQ5Uq(9emL z7p7V=J^Y+ld3lP9N|4JDGsk?DpJGMybJEl(;OAs9OMssfMi@UQ{O&_PCoCdd{$oGI z7dYf{SjBojRfsu9E{9dX&&g({0GGom?(tK_RDjE26%YBTgV+vmIczOY`Cic=6wg+f zG2O$;Y?P4;tW57PMoxKqY@wf%!=OlUfg5r;C~(YA;h4eC$z&rh_lkH?q+qhP^on?J zcp^#Oa|`{P@Ji5}R~`B};lXXr7a!zuuvT0D^)6F0FUHRj@N+^{3!j$(GrKXtZbvv8 z;fdbD=gH^J1-eX%MxMa`BF@3TB48Q-&c#gj09+1U`Fy{nAz6XT;h{C~FA#~0L_F@t z8lcKn7eN{I_ePWAr-ov~itys(SIBls`Ze^@OJn!^^h33v)!=vyo8nORpAl%wN76tf+@F&XiE;9cix9QF{4Qa9nNk$@~6ZSTImE{jLI$py0 zM!3yjHg;H(=GinY&k#ru2f_Kw5{;$(FaE@T=pJYC# zufzO9xP-_VO?_?yiNnzgh|HJebuf-8`M?i41)&vo&@8597#M7YSs4a+ULa;}hJj^P zSeRkpWGgJmFmSyUmS-6FsTEdc7@+kx$Q*<%RzE4jz-LB3n((>NFN|au*awXTeMzD1+s#AAvumg3EVcon2f!RTzH9Ghk)^ST;E5tJljJHC<&^+c_ zp(MkAt*)jl!+?Zf-KYWEC)mNIAaHJc3A4k;#gmf<8?HOJDlhiBx63ft6gwCXgpDS6 zB;h6OVefd~97C2bW(R|5l!RId=3yJlvzenf!RiS-hGKRw$PVm`*@1$wabkAI9`e?W zA`UR&Ws^89r$|q%vHDq@lov@)yvFJma!PKHp7@;AFXz;&Fs)g4C~>e2k0SDDfLsxu z0_5El+dw?q>PwJyr(1iZ=#3qDM-T^?@Um$~0B1-~RQu4|Fp zN>1O#wrwMboLgvfgtK^<^hEU~!8v@g^hEWg3`Lp^DjduD_x8|NU`Jm@5^Z0WPGVms zN>8+XSvre-IbV9B?aR`I?908<6K!9XE@xkgv2&b>wl9m!89Bh}M-pvc7RA|@WzrLE zUlwJL3)oBeGh2vlABG)eAIkQwP?&ApqA<_RrYeu9`Xf9u&$s$Rk<@H0@ZXlrbH;8w z<$_yKZi-~P2_gRzgpe6My8nj=Ay4A&JX%^B4Ttyj%jmrW4oVKIfJcokbf&SE91lZE zK%msR^C*ipMyeKFqKzw}EjmY2AV?&!gL_d{PwLWdF}34bs3DHGv3(7N;mPy|vKPA$ zV1%$+#||^TN@j$MjIWZqjF9}IyQ%2T(Z*e(DdYTPNzT!TqnhOT8>zpIuAsn}<@qf6 zW<_cEo6vtr=qoZpz9wD4PS~&L`(%1e&HM%QHL-ZfWICOwnLc?M#hSU(=fh5zx`BNs zj9WatX7Plnb0^Q6T+_ANgc%EJj_WaD;E1t9$5!{UIH79n=n1217R;GGb;;rhhYTEO ztc?G~9#4$l6YKeazDDNFp6^xvXMLaS=77wgPmRuS`(hkRq&v@;v9R;h1@o8GOrE;r zK#*p<>VE+Tq+ap^&Ih>Lp#u!#ZR7ZQ=gpgJe1jll`4TzO#FWX*G^1wv^trR?TVvkRxpZE+ zEG}6SIX!$vXssW5_|ZomeyG^n&GRr;D!GCBCOi+0@s4>O_WofZ7G5PZ_NUN4E%{a9CgJD8LOks< ze>36XLayvb{c54HhB3viDT6nwgLE&@4w}svC!H4<#3s(xy65b&ESQsj@=}U!s3ilFr z7t&Wb%RNX~B|KDkwD1JsY9fx+=|Vb(C;#FC#a}M@O5wHAa{(`=yIpvv^cy5UB79Q% z7bL$dd`-%3FQ|H8w=CIw!-eh-a=fCOn)%_4br}m{o|`GB1{ksnzvAp zM@k+eJW6=1aE5S>(D3At&s;x&tE68eJWqI`@N(gm!W)D)3GWczB{bJpl>4CMr-U1Y zFA84~z9oD|NYe-Q^HbqJgnUCteFNc+{EYAm9@F&~n(H=Xe&(m1%Tf}L6iyOO6V4MZ z5}LQaNN?Vp0@q4^j*x5Yu)NEJ{8~tv-};FU2_F;wMo2pp#=k0jUHGnWv(WrrAl>JZ zX(+&a1;P@c`5l3tUnUvfS=dwP{EYA`CF7?E=LwB}E9jR?UMW0HxK_AMc!}_<`W@Mz ze2)m96+SQIH&eDR%-<7W17Snq&iEQ#l&*)6h9fNJVBsOcLxtw|4)I4yt`<%e9w%HN zJYIOB@HF9C;RV8rh5X{n`X3ZNDg2G_Md2&LH-&!@eklA{SS$ReumBedGfu)%VM@4{ zuw1yWu#0d%;Q_*dLK@|lKdY6}ZUYY@IE^ayGV0rIg zpm_hne&F^fTOOa)Tpk3yyHOs~xy{9$14XdBt%33qh;!|`8ex}*WjulM_H+j!5J$7l zV0rP*wts9NUN2Hn=a~RkNvy% zNawbl^FR9RvR{x@6{f;G{zvC`xAd=m@1o*$gAX7FBn-bGp-%>neK$V%jM~`DHMNmJ zCzr%FO^*%OS~7R+yRq%G31}nRY2(m_jP~RbmcbJ4`N&TU*czD|MlJ9>5_;-cZ_~&U ze^YUzW?RDX@{Jqc^#(BQ+>%pkVbHs2YUHku{CHwgQ^bU}k7+o3QXyg@ZJB45$>VLB z>YX_W-ZNHv_szz&!XCefKMsKeZ*tcL2HXWfgE$XS;YgHg`@juGKg57oK~p<$2+qbi zopYqo3d)FiTo}=82Gd2Nmt$r{E@P@udyqka5@?AQnFxJoX0vmtibwehATkAd_{=yO zstE7Z!LyjhFb$2ueM(m$3>&{$EN}_`wb|nds9-3I|1tg;`Vl@lgLA>UBabk$#)J!w zK`c2J`$1OWaM46Wb5{+~2*(DT z3%YD0=YrPpN#2hK{AcuKGmm!_p`<~ms^m7b^-KL{sA1wiEyFd7CAF$Gi`kQ6lGpkMrPM{1nX#fpf8vMLpW`c_X$>Ue8uPk^J0<9h29w zPhZi0hOM_>^4Bctca56!^;3CeawNs)8trSuEa$?uxhmP32mNK8dBc+*aAxNGXYf^D zz<)+BCf=d{4DuzwxvV>8n!xm_Oh@<4=?W{xkS+Le7Ov zKRR_PWpFMyIOJTAz#jCU!SgE5e+Hjm^ZaMbrvjXd81C5&=i((63C_h344L6v@Zqjr z{~2t=Z!jQ%gJeYNagbJ`P0`4$NKod#0SzZ;ASqSuc)ns1F<%qZnoETI9u!4`5W`t$ zPG(#_C?DWtwC*Jiqw}Bf06Jhe7i*CsWv(Rw{~3p~d*EEy5saiV?EjAZXPk&~bN(~V zMk~p=_$|uCRWG%PSp)tve!-%_xfqMq;gt7^7+s{rSMuQl@gXY^;5p#O~FOaab?t%aP6r6``QGE)JZ3(9Pi zk-@p3e1wx7=VCP!sosbQ`p+QAo1BXa5g956=Yl^86iiXzT=3vros%u+;t?pC^QuG6 z1rKg>!%x}Xe+F}dbMZqY1?PgSiWdF{_-|%6CN?Qd(a6VWR12RcpF0;42uCBIBesZB zybVN6`itZ^bhOzHElT*P1zrN zIk{neU*jF)1;|`Fro0pW$*TtMBu~L!-p%MtIyQm4V7uRIpus^6!gwH#H1)#8 zeH$FmVE+a~OVRy?h+!aB3Vpu>4uKLxZGw2pZ_vP|_mQkHnU}rD_lK5J-=MWOw6qKE z`4gpi>65|q{7zEL3UMIXBR%d$O8szgu>3|yA9u}T`o<q zO%0%|A}X?p2o(jiY(+s7P+8;yEkzIz6w&|lob#M}Cusu({S^OSC%?JRdEax+dzLvf zcXH=_=8a$+lR9uJ(Nop$I|Su=C9q&j0;BFX(my)aP5P+4RhIronb*GwOlIK(L)b zbtWz_`h|q+up4d#6Zcvn*20AStz!NDAt|u@kPW+pZ6>*#@C)o@F)RuW3CU6W;H{T0< z$fy_L(`=lC;4Zb%u`7K{{xX8PQpv9H$0jgy24->8=meqz-;&SneYGq}3}h0N;gkKCl!jyKhGB)ZxV?z+I!DDpe``KV7k6aJ%UaSoZ z0UP%s`ypea!5kO+87P1}v++hExQ8Hfr_QaxA#`np8w_^fVd2^k|6~X^N&v&ol$QAVs>sB|EuSwCVwlOuNdBV7Z z=9{z*Jc5_=*KMe*TCt|QqNa9j)&Gj^##0*qNxL7vpeg06%No~jC~v5$EL%Ui_&-FF z8E>MdfFzS-)RbmO;hd2m%4{4-GD%K~yqV?Tnhc2M*ia&jpi-EXHzGQ0R5ZVTG(nn4 zQ6{r1GCSMMejgz-I&5ULux~WK2>qxcAEhVlBjgDQE~`wR`Y#WJJYl!Gk_ywc8yfCt zs`rcL7o#*rklp~TnroYi{;T;aWi@3w)y;s{fltGWfLUH2img(=xS`@>5Ud1L zxH_+FRo%&rwVSIveADT?_;Bo%^kwj)vRG=@l!IQhx~d7psw&Q~S5{sLicwkPstsUM zt!DV3H2Y{HczU&F<{NEBV-wcd$z^rrhOx9NxaPo&Dkm+edTn{b>P8Q1b8S^+$}U-u zobXWD5{NdeRThTA(oLt-SAj%jW~Fl71}t~448$(Z&RWx@4Qn?v;@*G}NW3!CuCJ=7 zt*(W}wunVh4a#A4UHR%pFtlnL%PN}7|J$f6UM_BIgKmX$ zw&k(3{sP2JX=@@&>ul7|!v0aXEJv~)ew&;uoGGN=7xl}8j>}Rjd984Z@Ju27qFC>X z!YhRQ51sluh4%;_6Fw!WV?q6 z4;M}lt`;^4KP}_~0oL0i{H^dkAzwVj{GP(0!Xtz;g=Y)DAmp1YS#Ou{QQ>cdd?zRK z|0W!V(~I(S;Zk9haD(t1;YGr$g|`at6Fwn)QTUdyJxE}ycEL<*qh2+&jT&~Qx za5@;|w*|+UC*&`-lqU+O3Xc&k5H1m(C@dGABsAAu*x4lcRN>jeZ9>O^xk&O?g;xo$ z7k*QCo6uaJVgHAc?-RZvd`AmzJ-PYZu5{JSuO8%vhs>r{z_LOz(LJVRI^TrE6T zNbe$+yH?2e&{Ezld_=fc_(x$!+@7;s7vU)3Xd#NdFZaZ7kWrsc>_Qzg+{1q=_DGw% z?*Df3Nl(lTE>o>IAQ00VPF=J0!zasO$(xN2sDc~wxDCc0!~Q|#hNDc|c7F+-+pxsV z#_vRDn~GcrYw&&RHkUUC3Vd~YrOIgPkNa^PdvYQGcoc8@wF2nsAnBcgFX_Djg-h}~ z)}>jl66@y#tUI^4Jbot!+kF!gP_K4553b$Qkal%w<8E{;#e_DOM_;p`y~+{x{(RBdl-7!-c?AuIyCVr?Co#|F_6c5h@ic*VUOcv z|1d>qdp99Xdqvo}ZSDaMAx~Is%;Ww&p(}S(>cFu_?pHa0*=|W?Y*XRZ%e_bk`?n)7 z-YzP~{{9?0hF1?T+wW2b$2}?N=N%OHWCGS7|F3o%$I7iU_Q14yUq=64Fgf_%= zY)LA!eIWN_Ov#uDrufR7Gp5g(AvYgm)c1z8I<_y5HtJT~lhBz(vYVyX|QvRfY?}R2sQTO@B{Jr?EdT(}Km)F9f zE_=c%?;qJ=Yll5koiy~=t&u&SmURABM%tK(#S=2!ium-3&pio8^hzj7jWY8AItZB` zpf_BF(=7aFOlD+!!Bi9gHG~ue#N42he)xE(B6ADOO>`uBJ95I`Mvch)9z5uvh8QYj zEP5?0fOtZJbSC}=Z_&diLKRJQrMqL8-=WdrT^BOliTa}aN}7p9j-h4JOS4*WM81Fu ze)t6RBzt&Ab|U;NKC&B3I-BqHj)5b>(=!&yz9wuqBD^8VzApDwDC3X8V)pf2skd)p zHyja`Cr2dvYw@MXNsPuv_SMRBf?k~ zh9eSw5UF@~GdX#0!CpapRE&4D2~xM?#a+$at&PhOFHwt;1o@`%k`A^5vBZ67FkX^x z#oWXVtXk63iiRT+AKjrnjtIwwi`Yz991tHLBkdtU_viQ#acjU!Os06G#7Lrm;wL1= z61*>rPn4LO;9Je(M@h^}kZBvABr!kn9@>f@EwLc+98Hxsysw$qQF7@LU^*!j+IL|$Xh%ChVf zL=rEv->o?!@l}1=<%rl8(j1Y8(bZU79Fbc&UmH8qIhc!w;X~q^Tto1NHrl5`RPu*|;3>M>PN&mm|JM?M_TE z2tqu=5g{WY-kKv4e^REVC63@he@b=dB=|pLJi`$o{X71fF7!8MT#mUc+?pd2|6NC( z!HmoCSvK^d78^Mt=U~K!9%4Q+91-eqTzG$PIU++*b4Vn$ogCoLn^u7N) zCnLZS;SCn#G)LqfHXPuH@J1*Oj)<+FmwcEq;&RY4oN+mtSRNb^n_radNIAd}Ii2l+ zBVzL>B>AlzM_dj%hldI$CbMY|aXIXzq%_$?85|K?ewqnP5D#!fzE67rjtGMi#=#M> zGU;Av&zavV>Ch|9tMNKIUhQYwNRk-an#g1fJ9p^3}EQ^6jj193#ou?Oj3I3g-)IU*De%n{*vXgDG~nH87Aa764CGn75i!^907s+_xp8nr*ccm2CD`*A{TK$0ggzR z`2mi|C2SfT5j%>R$*<8KI3lN;rY%P#9^i-!VEF(?g#Yct+i*nUh|6J5$mZlIw%3*; z5)X1jzRwcih_DCY!Ylmb7m$btIU=*!W{@Mo+nachBf_5%;)u(^R>Ose%fa74;z5qc zSgt*AL~JXqI3k?7AV-99kRw8w9FaKUau|-tGR`UDa!}y4;Q`LU0XZV93XTYYCsGG1 zANE=taXAb}gjb!opO}gSZ^?aE2o; zhxv7KdypeC1;#>PjnI?3HAke8c1CBxj^}OV2R8rN1bnG)hEab^XTGMX6w2Y)`(MDG zjx{_HUWxCeZV2l7Wtxug zXF1-asw1ov;YSL)zbJP(YqKM#pbWp}O-GzC*p)OLxd7SrzgIIOgJ^*tLzq~a^Cj1j zuc6$P*ay2z(~%!Q!>=B7gq0%v;6e14A=O17-9@faBVC{B9g*~e}1lM_~grO{98s#a+7u#SP-Wdxo^n~Bb=Nb-ogtZYx$O`?!&!sSOBRo?=zx3nG##u%( z)u{6@BjH;?f8^;AE?QS#OtFL#gc1s+6pDH3gm2HzrGVaj5Cy6=?;0)k>B;7 zra+Nc)&C$#Py;}WN|VGyj2hV6FYda?zhg=VvZ|JMIKIPih6FY!>J@iYnZX^fO1fa# z3>lMA9-gkaG%HhWXa}D$$%gHhiB&xkTrWFgWT2%?Gb7Y>!wJL6Ru3hPYFh83az+Oq;YXWmZ5Zo z!{+j1`?Zk3@0+lLlod9&Fv06Ca<&*w8n1m2PH$mi26o?DN?`9ybtYCA{X)V? zM!!DP!bGzbA}vhVZm!R2P0&Kd66_#!5w>D)&Emp$GdDBCC`B|Q;bkrg3WQ?O*nu5K zn8f1VGQt$>h)v|Tu#>dU8lZJCxe_~CC9J}ZFgt!rB@*@6p(iw8XARK0nB)M0v@RPp z#5aq?9_M_N0ROHRAZ3&8+X-6t{eUEoCnpO@9!*Xal1%_k6q5Kf8wMQsqxtUGQ6L5A zZ<9P+BW;q$XrfKh{HJV^=Id;d<~Q3UKF#LyQH@!pS>B%>&5_nXC{H@H|CS+xN8TCdYUAN|GS^sBKt|GTW}&erceKSy z+>vB??tvaea0W$8(G@m>McZFusER)pRdE(oaV{6`0qZbi!iQBHe^4m6^wd{ym= z2_s8J7OxPY>7OJV9grl2Fq92z$|}~>*EN^HAvr?;Djo}8OI*~My{5dWW@HUlSjCz~ z`1P)?sDOyCv9ijl>T-ljC^Npp&|zKJmp?mZHth==DJ`q9`R{b-;W)q}F0o{^hQ zvomr-8|#m!t#6|BxUrr~j#c<%PUXkLoH<@$bn7F;-1%3ro7z1~KAxd<))$Y3-~QSS zYZjN|)TUd1S;e{y@bfpJbs)7LRtIc=;&F8Pr=S0r2{=I;O+XZjWhV#1r?h4els6(a z%$lk)!xboNv_z#%m2CSUNlT_%BrBQ3foMwYFq9bGs0?FnE-9-8<=_xs>EFdyDqB2v z>Evm;=Krt9*-0%6Gp5bGh$8oN$VO8PnkQ#6qUs##iLV08mj855ZLPQ)F*MbHe$kvRk)m2 z)TA1!HrA3!mMR%HzG(cI6Zhjgr2@D4TalieiQRMh12%NeA8A3e|CY z?QO;Wew-(BA!(oUgbN%0SH(YKF+B1l;)iVdR}txtMugj$7wUi?(1|F-|FEeaEu0{n zA)G5*BwQ)167q=;>u(mGDLlk^vh#9?^JM3N&+xcTHVDrVUL?F)c&qR};S<6ag>MND zah~jaK8ACh^ZLB-4dH()=V=dq;N*B5*U7}?!Bh9&N$T`*( zla$<3I8-=NIGTuZlO#_O9!tbpTOeE_tWRxLg7`)zee~i z;dh015MlQ&;eFEoRQR~`zY_jhxKH`73;!(rUxi^@^Ep4+!Y)L#lN9z84paUp;RGSy z=*Rk#iKsVSI8XXT!V{%mC9D>1RQ_h+8Pb1RxI_A#!po(~9LY z;UR=MPlWiIH|^k8K07}`K9OMi1w!+4G~`mr(}c$g4W}CU{8^gyP7qcIR}1;LhxzvTUBnz=M`2Rf zQ|LH;gCskSA03ui-*NmVNp>8+V7h}Q_eBfM33mvEO5 zUh1a&gTlv!bU3D+7lbbfUlsmI_^yy~OISXO4+MaQLk{dFxrdNmJIw!taEfq-kZ<>A z{zBn$;R<1eaJ6u)utC_C>qn0u+M{DI@oM4q!fy+25q@8IkMMrsZsB9XCxnK(4!h4v zrf(73c}r+GfA~3@-bK_qu3t(rUGk`>%MkGhAzgzgn|I&?mr{lu$Jwh!s7;7ycahrT`3|4>M`9m>BD(qV`4ULhTGDD&riB46xGJ9N#VOb>e^ zy>5u3gr&l1Li*M)|3qOW5q2CGaE_my%dq51y{{c_hq%#-A9V%|YK8H>K+Fafo$hbxEN~M1Vi>3x0;s5$r zjyy$8zxX)U)j<-A6>sy$I&quJTMLCtGw)ISc+iK2w7I;KAP3uBG6L%i<=8Ig!L`fp zXjcbGZ(n!MOEIC%<(&dKXs@osoBJ7>POl>ajtB`~CUV%N1llFL6oV}ZnW*wfR+@1lM^cU`6LuMZL zwj95k`yU*~Z%AQlPM+)Py|5YV-w-Mjzn>$GHOi?l+ln^!+<1wB<>Bo_xfGN* zeCGEg+RMYvHeoNleS3g)tZ)ivkH0|$%SG^G(+jQ;(3JznZ$fb@vwa}PuXybE5>xzx zIetxtn+98P{OWJ{Qf!ioEEO3$WAVP&=C1p)H?My6+RcMs&ED)EwdvK*Y-UWTY5O9Z z7w_wc+(bGz@_Jr``O{Ei@xEN-bx7w~eHQdN(8t^8qnm$<_);?vUn;9Jd4YrX?A+&V z-m}j)t+I9hNLu(Iv_1Ch*%#Wpb6+@Z!yjt%{LLMZ7eQV$oo91Go9n?KL5*$Lh{((cts3hPGnl}W55S|25Bzhe3!scZU^Ls2u9dHHbF$dg8 z){13+8OjV-kgshB&%z=J7v=L31t0X6sk##%h#PeoRME&4_{`!90sL?hZ6a>ebZEl- z`bXR-rnB!wdB%-uf?(oC?L#8Y8#Kg?x|?afU>0$ssJEOz-j#P?dBu$yi2fyxq|K|d z*FX(N|3nML8=?;y5u88xy3aigs0;zs?{ z7-HNgk}h)=;^SA?&De1Ar7&>DjpAKzg6ziZBjRp+yhB3VC@V%1Ls1QJqpTQ9oQLZX z;zn69H}NhEAa0Zu^Af+II7woDf-h7++$ft{kT8tNQi;71$I{efiQohtftF%^_UzbQ z?A30zdu$HVoOSe(aib`P88_-$_Hv#X801i5HH$Bl%(ziULBSV8nIVG{7{OsOaia>5 zu=D+?E=2!!2Wjh*4{EWuRO4i(JNydK!ZwCoucAE~-FIVD{~9B`9u` ztsP6Or0ws;$)_bJa3wm0xKUP2$Bi;C_bALu+{>2llBI$K|35_BD9#e&MlozK;zlvL z65~caN%4W+R~vCaVi6~Mcf!11qHsv!Bp$d2<1d=r;hpiw$;*DEvu((70<$0004ygk zdym?knBY5W5I4%angVg7M$^>eo!>R4(s84#scDJxS@m37|0R* zrpsT^IdTGj%054zTWm(OJh2;dn*FVQvE=JEzmJu3Z73jc z0&V@g&7Y8bk1{xccbobX zlQ*(`a02b6q%_Hw;xKNMEk7-JHfJ21K$|}^$$uOfH|ocx{+uNLfo9w&TYf?Ea`qpb zKu!+hM)4m?#*H#BzXB(a=N02d@l-OL!0j{uP9V<_!wKYTbQm{^fo)9OsQEMrPGAA1 zEL`|(G&zO}Z~~tbQ{&_0cgVcf!2M&@E**O%NgL=`(RusthZ-#~oG*FZ(cRcxy z6l;&mHd6@oNmI??dB|00PG)feJD`8MVrHMsE`k%t|CbARvuff-9fuN0bL|EvkOI!} zB>#nC+$cMPkz^xh2%JEz2(-w7My8pDGRP9O!EI+rpyfmY5+ew#8l zf%JVgaif^H8HLqt8#n6DxVcR7C31`##cwm3x{xwBf%Z5eniYEqP9O{8B9~l-!82|Y zza~P31Cl=T!3ngZn3*Kei*ci>jlBiQ^(+rgV1?=G^5k!r4^E&x;cAi_nGa5&mFttd zQf7k_XyxYQc+4T=MrD~}z7>o=HV95&cca+mCx5^mgA>Re7)~I6b7I^mnlN#rUO^7y zMp?y;e)1bE0ZyP*+~OyvvjjMSRsl}n5-Pw6w2B}5$@%OTIDxhmassEr2zzDb6r4cH z?39tg38YNgrIB6SsD)4@-{cU$38cU|AIUL-6IgC!#Es%ror0+fP9P5sPbA4UZWONs zJ$cn(+$bL0o=0#l!3kumw*6~dC2#_N1|>LwRQ2+C88E9G3+!g3qY<9yy?ma0?p$C9 zx@crKK6AJR|Ad6;0JwY0*(^ALyz=>eZ=QvW8^wPI4JXiiCB`COgv~zu3B+;&88?bA zwd?yTRA;0%BG*g(n%zo$7oV`pe*+mest-zm6F3i%1H4|HZ;HQe_mHMd`gA$_fQRN)HEz7H~PR!-U|*xsc=JFNWYf)weJ)&I(P2_cX-{%_id2A}iFi zFmaL<>dXKxgy4G%2{#%2`bY~CyR8swVZ!$80P&-?Artf-0uNYgvJuX1ZX5thnSn4# zeSmCakJ>Uqf9zmH5jJB7BPtj}%8-rN6#s)otAwwcVjvrFo_Aq~p1{c!*@#IFAV@ZX z_&yugOfT#qZ|8jCP?K(4NgQd@r6s^4O?u~i;%uv*IS*(akD)GcmDMk(2Cg;fo%4wt zAL2_bzX13ptDi^YfDpdPteKmwem-%R)yM7!K4Q{4=M(M7>N$G{v2m58uw!KNh#FaC zU}V$ALC-rKmLY0na~2_eg7idVZbJGttDi^QWzzMz zyMaG5>7Db4Pgy+=hS}^9VUi2TZd`Q1EhwLluaiSzZ4NpV&&N8fP4(y!%WBz=xDpBy zS8&8dTtO;LTtPZbT*1`^dRo`;$2B&8Et7Sv&i5W zpCaSpBp0nFjorZS7{~}Sn@2`_4~iycldzJ`Rp6VbErk*YEYm9LO}eD)9CQJMsWHqC zMB3@GJe-3rGSE#R*p4h0t8MhK8SM|T?VH*gTv!_ur{eOC z$O1x8Ol9Z=7e9eXm26&DUxhduZK8>gwLyA>aa=ba4BgNe4Det)iOW{O^VgCnYSwLF zq>@HNlvua6jKN6COjHQaLDrpI%R)AwMB18--w+7j&{T=nZlpWbxUrToDlDPH#n5ok zA}TgE8S)3BMl@DoH2VdT!FV!3R9t`xAUPr%FqY9JB%W|Ufru$M>5RAZl-kuCZrSSc zHEYUEA*3ArCe2PEb;N5;Ou^BvS>+iQe3H}FZGaJU6+N*t*}62tk0Ihk?YdPa7={A7 z94KT)xeM;X4wu(i;!7(QjN{I*2VU8n`BRTATjFiPC^$@BVlv?}HZ{~X>6o2Th3GP^ z$O&t!nwxM04Qq!{Ky1rUG*;H)@YKSZjnpA}Pc<%1b+wI9Z>k8a^YlO~O#GU)Rhu%b zhzwUDK)z8d5;GScl?q|6xm*iP=r#xLxIt1`rcs*N6IdYW5JfseP_+VH?Q1vGw;z9` zej10pro7oOk8HdXoHSKjwUz>9&bO1jzw?olS5iVfXp_3g4F- z$5)M5GpxEkHDYz;rt*gB5hbY+^GByfRIgn(0yA4%fm(I7<&Cv#S3}7tOHJS}jKFn} z*a#gj_CdM2eniE(wM`A>6-`Isv}hf^#xmgSg@#A7wy}~61}9^AU7EgTLj+aSt>b01 z0VFsq-(ZNH`mwxXkweF+|IZLNa969Wg7J z?VsUoaDLy1w_&e(?eaEw6M`QsvHvr?jU!nto$Hwm{0w+kJA z<4Vcb3eE3A$(EzmN1G1ZrT?P6pj-fBU~=573T8s z1p3`WI9NDdc#N=8*dRPhc%kqI!iR;w7VZwC%Rd|@Nuh7M+nIL(RaGLN~;R(W1gl7_Q ztj-ahM?{;SQ~qU=zbgEi^n9To%iS!zUHW?^yI3|4O8*P#pAs5=2gd&g$*&3xzXSTe zOQw%H+u>&XFNOTxqs(8ci2ONB6&w=L^mC z5%n*T{AJx6Cn%I}hXm+&V-K5eI+$A!NXJ}dm4 z@D<@}!gqv!6Y_CB?U?T+V4mcBVJ~4yI7B#HNFNy1pCBw1n(sB}`BaVh8-=F}&k}AI zULgFE@G{|5!fS*#32zqODZE>FzmV=AY`3j{Iv-n8|Ge-I!dHcV7Mkx>lne3u5SS(G zDC{CUOxQ<=uOZ`q?yfHoO?_k=H1`*<$KRCyH)5*r?(mSmHD{dp;7+@YE zuwN^%yE;gEz3?TqH=uCIwQb5}<6n}Iu2X@$laLO!`*ISHn;Y*sc5ZK?z!%)XhRi(fZT+o3gPVhm(7Vl* zyB`Xs(_8P1ZR*^ixfkhR|F#Ckiy@`^*Vf;<2=;<&)wM;$rIPQE`#+pSB+#=x<#zcJw$?^n?Aa^G28k z)Be^yaA!8+_pcpO_J<4OJ7;9g=rp60p4XAxGZHhF{63c2`mX1n^=_zeW}dgV!aID% zKi>ZPKbHJHtF6Ab)koUs5o^V_IU$oXGmo~SujeB6N`=RqJ74#6B4{uAdS3MY$Fla$ z>Ylwfo-BAR9LwJm8<)LzTWs0ygLNnNK4ONeJ8k;l8CkE#vi3dpgO^|XjCap7ycadY zi}<6F$Q=gZ2S(BQ1Fq5MV6wxJD1WVn+jIl+;cWe9TrJ>NynzskZp86Lkd`=BZp7SH z&Ml~Bxk&UJj@|o8OAn?jDvB6 zo-*MHUAM9}-UUvBW&CIro243+{YVKq06%QD9r+tR;D^n0_6+3G4|_ZWcFHsgHb zH2kn%g)(kjs$FcB>ClWoi4H6;KWx6zJuwR(@WbZW3g@cCFw7kMu-`Qz-iXK-J7X-Y z8d*!@`^9EC3R)AJCGsdz@WbYuGQ8qyb*^VwrhL}M=()hZlaWZIZ9$);(HV)Nz705VBMo779{xFM|P>iUWvXe zJXs?AusdN^j2|}d6%((bi}1rX_l=nKr4$3PS$g51!w;JS3)2sK4dnyIX5rz4ANE?b zX8f>cVgz=+GqG9tYYhCb?I0rw(gWa!Jr5=6hs}<`51W%EKWyH$=6nj-+|8u+#Z*^9 zfFCx0VxS-Pg%A_p!w3AZndai*&j;|sRzs*WolAlLRL~Ebq&)dytAhNnRbGDB?pSPN zzrGje*E{{N-(*vFN=*A7kW3yyuVzcD(pg*NP&q=^Zl785~ zFymd2xRjmD#AZpca3(g(6&z6}HcJ)TeNl^ze%S2Lfnu{zkK-~H)@*E+5NcXK>>H3u zUP`<0!?pwRk{59@0v03(UR^f+j z%P&Z-Vf%sDEH5)Z5SxYP75%VzS{Xm=DjE#NW|>1pFgDANXfha^7p*=-q9c zMi-mqMhw9CVVl@2=Gq;I&2lt{2S02!M$i1yIR5rxv+#EbJnM%|cirUCGzC9wGai_FkX7M_P2K=|#UD24 zht0zD!zQ7ae%Sn)pda>^*);sH?I>m@Po+KhVIOXqUXUyY(hvI!rmM@7MJykP&GJjO z*CsX#{jm9!8Y*l~zQ^{0v018VFc_PKk=N*l%^ny(>~FC|FgD9Fwi%4gau`ppU~Cq~ zY@i=DTQ#v+7?YNM*j52Q?4j%j{IG2+^uykOvg0r-W=?~#SvZx!*esNtANHA?^E%X| zA2tOZzVC3(4j7w-RpEzCxY9M%+p~Vy_e0T>R~`Cc^WgS;mVMkmHVbRR51Zjx4=y$f z$A}Z=K(Se93;xn8If6`VmTTB>FgD9V16J^QN0323Y{h2jhN^KyV)+8fbmC98*(N&L7yYi^fTne9mWw&OG1e*j ze&llV_uy8x|5g}992WkR%U-0g_b-QKf1HWU(iKhn*!xdnVtf}mlkPzBT)`TP{D$U!ax>tm#Mbne95 z&y;p_!7Z?8xM9KIq&&?aPbs8R0Bv%wb^tBbHXW~(&qoz-^d{g33H+A3CdhFsHE-iX6PJFkTab`sSI_J^M12dbZFmvkOW1vHIe|x|wF^1(cm%lP zFq;QPzIQz9@mk?~ClIz`4||)>Xko(kS55NvDa>6L= zA+KpAXJn#P6OOU!8qN&|hth;{tFGrP)mt^;RI6_0A-d733AY>d#%6%o+%SX4?xe6| z;StoGN_J<0RTI>mI(BD)RTI=5_@7yqe;7FlNp)unyK@b8s0r%M79`EaCDL|hcQ`Fc z_V9 zuu*SqSP0l~2dP~f?$E(Tv$bI%V8b2Jc5S%h+ym#Uu^|Z9Fq4fB-aWM4-QiDSIdL}a zXP|NlmAEL-$4c8r3xOhTt+Z>ytsvN_vo76fcyw#>%4<@&bY3npQ%KQ^_$+!F^U>3ODO4EhYy_GZbhxJFcN9|t~52B1A z2j~_WaA^OCtbw#ox^p--{_xH}-+8^$+tfPx%Bei#zsxM-=O1wGb7jSf$OosL2MmzC9;U3B>DvII0YrL%YBNH5o z@&M=LHLEiI@&Olh;}H&8LK*#~%`y$TFQ{wB8CZO z!1}odC{vamA?}IzI_a}q3n+bMu{?;?RZZ})ui|urc~VItMWdnl1Q`cwGKWiyqSmyC z*8cOx+a9a8daWTNwPG+?%Ep2CHq~oQm?;v3HdlG>kXqtP*;>=3Rs;!*tG=qDwz{^e zQUnq#it2S4&J99YRWu`BjHQP#-i@v`t~kjZB!_T~WnyHRh2~gEX@bSaG={_dxCfom zF?DwAoa}S6J`>#*IWN3DglNhiM=k(;Ju+J)lSC?<_UN(du<;Jb6bTzoiJ*)h{{mas zzK$xb3G;=Bfh}yjE;5R+hu?+*TNvK{!7U8WlmaODe>UfsT!5j00(ngDw{CFXxF08g z%c<2x%)BKd2hB}`3F4=O&B9xRS-_9NAE5t;@jn*wmnF*ch0BDW6xIsY3bzQ)6n;+l zMd1}f{@+TwcM2VU;4#Th3SSWZQ3%?ssmG`MtUq2jL%2-1O4uyK4|%3MgN3smUxP&C z57fj5guf8-w`l55Z!fC?A!d1fc!mYy33Hf>++WV%^_G?0sjoL zJRd6(4;LCgOvtMxHwpRdnB^`NGVV6z-wOF!DayGxb%;HMd`v_62;oejd7m!ybc$g9 zcZ9oyj|zVy@B-n*!pntU7hWg)mhij6yM()h4+tL=J}&&F@Hyd&!dHZ^3Hh**{Y?t{ z2>S~U7t&3P<;Dr!`|};I;TY)`2$u*Quc2IWjgXI=X^(yc#7#mz=%l<;c(KrYpFn?= z{=uyGC*hxke2p9RhUW(4169hyh4eq9JYLwA z&oEnh^TJk?TPFDgVY#qM$d~=mp7~w_HcQ?j#H%??{x+fczC$^_{f+hbaF^)bpU;=L zQodjKi125^UkQILd{Ov&q2oEcDfw?g{<2NG*+TRE3AwA}q_B^$zmN}_S#P$`e6K=2 zSu)*%n16wg&Xtr6Zx8s0eZ7z?`bX=Nwekc6DUJ(hEu%i9J;uzxX3yt9Yf zgS0*SgxS^hys5B9-z&E{dwh-`v{wLoJWlK%rYLRi2BcYs>w()U{NuW-&HOR{R_wuY z{reu6GjXrV0nBy@$_3XT=Y`wd*n|B`1;)$&uHF1SiZq5-4=~$9ZS1-65(CS_9JC@R zlhD5(XQHSduEo~0`E>T$awdw0A8*?Y6o;NzQ=mAs;8YLy$H9$^FPMsApgUX*33P{% zC=fmws>s}e6PXi<-h!O)H&G)pzXulp=ne}Y;XU(wc`e8k8*#KU@0p*6B4PR;MpIpR zNW+^@I6A!RLZ-8+FUqf^nOLNeme0UPRx94aPE_#2$Dt?L!#lDQVcw=@H<)yGJ#u5< zJ?wxk7RkOQYIg$4`tI z-h-L%4DaD(_N*++PC+E`Ec>0|J+Nc(_u)O*7Sg;2-g?F2;ypaa`O5GfX0w}{Tto2i zGSMeb4fmEP) zkoPd1iXiXdWts@`9{948_@b`?4c)5Sf@E$JX z!4B{qUT4(+?}5Lr#=(1-ZA^prz{K;}xP`Ud?y)DnHI!|550x|p-h;`&I(>~*Kb_${ zkPjCR@E+h6>BR%Q2Xay3;62z;%uHTEd*D5sZkk?@JPH^O@E-VscRav*c#rl1yoXUN zAK*OVmun%0b=(W%3^4mxi(p?_nP2G{AfKG3V@nya!eV?}1==4^}?x zwfO0wu;D%MsuOp-2L`8$@6UT+CGZ{?TH)Y$4;&*-n*;G4Xbb#=DI7tD_rR!n@gVPE zH1csjwg64`c@n*{@1M_cyoW!b{28f#V2-^MpRxI=n^?i?Jq{T;8Q#NT)NT**9*%~w z5SS1xsMVVH0EOp|w!DY!6tMYAa4XyYTQKU6F}w%<%aX$0|9sd17vj1c`|t5B)TPjx zKd#F+ke-7iA3YVWVz~)M$5)^5vC{xJMu5(6IjZv4JrdFi_u<2zXmo?Iwt8b9$hP@! zna>aW`{ns_a`?0Hpw-BzL5XVYgI(s3CTP!sW-E5o-UgACBK+uu-JhHLC~IGbjEhm` zBJ6`M4+w)@$sxBwdn2-Mu%_6N0kpu6K};;nVT2pgksqSWJ=h1kOw$p*28%!0sUxfu z;m1(y{-WIFtj&(_XS-Lin~pePuq$ag62(yt^GMqnDWL^^@KE?mbH3y{!Y5)p>jt|_ z(-FR>goF`wgq0%vn1J11miwIR$SjmO2D|Bq69&7IrX&2qSz%3aMoMXcA2XOZKBq7K z9XB)5h%)Q34|bWRBcFxleC+B7D@FJ*8@qo(?n$i88R3ghuE1_O;)KDjr0K}*$iCH@ zVn^1}0zVpKe+reM%P2+1{Z3Eb{M|(xJ28#b4gx_zuT)AQNa%)GKyn26q5K zs0&ujkTDtM;f@}}(nABhpvW{=2t$K&XLU^(%Oj$mQ_e!wk?K^Gox;*ZF8e64 z2)P|IV)4Nck+x%*w{M%_OjsK-&?jxSPYVg=tIbXU_rjQA?!3#WuNDC9Qt&nBnYw!^$a$+q^*gh>GG-C&eiEyS#E+(97wfJna**+{H z)L{3$;|LtU`xA+5z2gasOuZ8b%di_F5fipkClF{e>TM#Ch{?6s(Got*7Q&p^zXHg1 zDi-jFa4JBrao=A^@&IrekmN*fv`KuL4KXtGM_wcJ}7rh+2~C_SHw zHcCHK0wrf^f5X&r57>wp1?MB6^n5DXDE&|=lrymJZx6)Q_H=TVJg}jaL=crjgnJtPqGM7cH8a}2atco?^ka=s(b`yN^8D^mGC)rT|?C< z$D%mIUio*iSK9g=7LT=j6+T&2tO^|FiZzXJfL&ctF|q~+9x)TDs>|_K^K`rmEE`f2 z;6;oA_|J#F;x?5o0xe3QBJ^2Ut5sF5u$sZI4ET4?I5J>$jU#=f8-rlPeNt5#NL9%r zfu-IMNAe7TrQT0b&Bz$@BcW)o@OfcB8t#_gFF(tVFselOwJm-m9PJx^xg#?2^G7-T zMeBXUtH>%cwa#u^>n+uKp-rtzgSED{t@Rhx`fZz9UkTRwTgdbpv2624_a`IC|#Oa~v;;chMgH4MZCA z@_7K*6(GtL#DGGQL^I#vCLPHKy8782)q^uTh@P`OB|1LsJ+2XlNCr{Jm)%(y) zHgi4ym-BDZ%lShxaq1Uxg*iHo4T}H<&inChS~H1UIFpYZ4X5ls&cG=z}xHb^XzsKa*@PA|C zL?Qnxrp!lIMBLuuAqF1d5ivaa4iUQvdk{O|$0Z^P4VQkjkpEAzJpWN7&J`{at`t@Y z8-<&N{P}|QJ}3O5@CxCL!aIfc2p>WafoYU=izyr z^E~g~5Juq8NV%J^T*!#v)ZZxlp72RwVUEpru{x$oW(aQ9n=f1?tP!piHVID^ZWn%8 zc$@HUBK|MGSLkAK>{0&HMD)qT-~j$k`aeoXX*bc4C9*5@n;LW5YY~vHyP|H9H#tH!U@8O!pTI`n=YIu{UYIs(ytO$ z3pXl%v+xY*KP}uL{Z8TK(qAF`y6_g|-y!^=@IK*gBKr4;@JZ>P7XFX)dxd`#{zLg; ztO?Fjj0iiq!fw*{5Dt+3aN!8yQOchzoGqLuTug-B8 zk?^b1UnTse^fwD{6W*`<-NK&>pACa47w#3B`yAxIBl&MabKe6! z-{s8y@mU|SyO4grl=}&X2!{)eQw#FPOQw?u%P$ZfC;X&vm9Sb!2NIUwCUmiLz95V&}D@B&kN}dLirjY{Xi&xUr2us%7)_&e3CNk(Bp&pKM3i}L7DzjM7nVh z`DT5h`M(AA+W@#DsFJ50)c@c3~XjvZg8UMY5NR}>x`cWW2Q{v5~KZLZy!Pz3G$1on2J z!+a9VzOY^Pe>rwn2TAV>o!~Qswd6LJcM=pX&Aes!U%JqBK9E<9bgl747A>VDTE#qn8t()Ku~t`3skr6|C1ZgY9tpa}MFXTTo5 zhST=GinOak8`s0$uie285K*9FE4pOtj~9z`0%t9SMy{af2}Z4m>@ z!<&F|MNlT8=Wi)&HxE183{00-Q+ROPtvk@a-=ePDT)W_IjV(!Kwh!cPjXR>qvbjE( zyVYxwX{{}HYx0PFq4O_}o&D`id*;7}gNg_=J|fUenvuURma}AE_U6>9Ue4-Quiaeq z>foGPU)`1S`m1?=-SwyYw%+<`sY!q5)m_`Y*B{&(-51%Ozb^}QqV3eVu1%fmP$!H! z5!4B{Q|J6Pb*@L95bA_b$3I}5wNJP1*=JD0-|kO}D7Mapk9m8K$@BMSckc39IJ9Wb z&V63ao`5Z{aQv%V(<8m(o(?Nxtt_7M_?i2>?f#KtQ8R>^nVz?;d2E}Si%}Cj8Crmv z5!B4glUEp=-5#yln~hqb?U8T);FZw%i0*Ud^migVE`DkHJFy+7;xl*0r|_A#WAaPq zuYBdDhkqaH;_oEm?$=CRGH*Z4u>Caa_S4Lz#`iC@cKlTM(yR8S!L|Dwm652Adw_5l>G1p> zyk>)6cN0|L*JZO@Ec-&(&G75yph!5Es-k?R;kV7Vz=TOfkM{4ut5!5}1wOMFTf-0E z0n1s#J5Glt{A;QkOgj4!X=#0ObyW^A~~eGMiC#Ky<&q>#41kM_u}ILarOOjNl7<2(b@c&$)2na9^H>k{W-}~IgQ}a+42jL`zV7)$H@s5 zE=g{r3?7~NvAJ-0lIK+nJUX6ACVtQl*#LNSJV(NX4~3G~Q2`#^FVI4`@R?|G7Ka2L zT>+*hT=;A>N$y?@Ji6yiiC3bSf1V2VAhn=$;2;^1okJo1;1P{%MS*<(W@xxT14XHF z$CD?XwZ~UNJkv8|!(KjS7oc^`{{N5^k7np#L1JUV+EBgyMI zAn@o|nDK+k*lY0U_%*@!LHx%j1|FRq#muCSR$}1MRU3N?lAi#^z@w`$U0t5s!SdkI z*%PiNNrr3;JUT1aCr7Y6cyv~7PLl8x1CK7t9P_PyvXlkDqw8)I+x#S%)G_er*n@E4 z6@GFjOMpj56XC+I`^lTxCU|sKaigDH$&(2@I;*(FPfq3pf=6c+clpUvSp_^gt3dpq zZ?FV-bhed;z@wWE^X!$GQ}F00vr|R}kB%~_ibf`nE(RXmLMW1_ASVVM9R+jvIA`F| znFln5&0Y?#>J&^>@aTAOcp^zY?6nwpbi5Muw&f!&OBG{TkJ%je1G&V^@;em6dIxCZ}(gy{hIZp%0V@aTBu^Znjq z*f4l>^u6@`P$a_ZB<{x;7^zPQJ}i$8e9bIAMC!W`<<3a)-9ugqyXU8NvjXB0K?Raz zVIP$8{eHGusM!yH0g6;T%l7>O%AC=+3R84?U;b2iTHoGKZ|R!@qo?-ekAIsP!VC7c z`qAT2FMBG5Oa0Dy5IS9fk7&exeiP~bKIyssOv}LIy$3h{G~Cn{^6i2CtZsLp7#GzF z?1j&9jI+BjpnMk;{vX&b9EuPB*e<6ce**f&FZcnwSZ;1Eb!S38p1O;uo0nkYTu-NB zAJ7rgC{gJD93CdmQDn5+F1FXomePt?M!iqCl@uKM8T*ZH&++SS9F}Mhf#6CC= zBhOTPh!tyC@zUs6^uu(u8s%1EH(k9PiHoog{<~{&2**gCq_>R~Z;qNu52MTj*iEG< z7Tnvc)L*R)9^(>IT>IYPoW#(ty7%+BM8fRUP!JtMPjxrbJdAZiPj~OcebC3oJ$%~?;u-<5sPqf zh`{os4jn))vNR%=>pKMXdnItfn*>&3zlh(qQ2&ws(Yc0v1isYZTr!|avo4-u8Y&cr zDafQ6pvHr`47+M+Ry*7(u%$ePU&0xcree9mpc)>CL4~(21UXW}S`(^<9}Gtdiyl|Q z(+Y@~C8krv8*#oMT}1r0O{a*r*mMDrS1^`Aac$sMg~OR0TKs?SlX&xf8%Y_yw}6ns z4(3v23lj^hP}9Q15-ZfTFmbjO>RXuDW`!mbE9nj^G`BEumld|OF!368#7iRl-Rf7i zFu~hXv~KQFkqjfCcuNe4aaM@6OhKaF3VAIY_np{biLlG)5p9Zz`>jyl!UVpzIg*-| zJxK6*6NLH}Cf;;8Ok`mWVT(|J9fg`(nCNGO`n(nP^foUf>}#wJ^bpHiYIDCLXfFmKG-7#17gU!A>oz zGr^0l?=2+Q*<2rKSpvb%=K5G*HkW2*6I{B?Y@)f$Y@#EX*+foeHj$H=&83;ygsseM zqQSsyuE;8k1!fan3(O`mBm2#!oux$tF8$UdxCpdf7+<{@G3UwbCdqW`jb9K^keEsa zwlHb!9!K~Cb};k^uV6=*u`^nj;A}!q2*D^TgD=MAZ9oT8oJ4=bTSbhCnz#mIb{2!}t z=1HDs2D-D9ILM^yy(z%i(i2x&eT?r&F%PKGAL2DupLYxJ4wG(b<|^jTUkGegzYF+d zo37y+-fhz>Gm~AP$B8!o-{4BY)ofmViU40+%6OwGx0-ZQ-45UvO?u~iqUN<}7t%kGo~U`jLvy8JO2Cfq88T z%xgY|VmI`~UJn-l%{7tDu^A)KF6|k?)^MLiNZ4uJS?cO=8E3k(v(%OKV8VKeoDGDr zrr_nT)fKO)&AC*G3R|($G-riPF`XHG+h%y_z5_d&X>JKza+_N?8$8EN4oU8-WwXdPWGefg~&0HMFyo$DU2GnanW@G-IkBh7$Jr zw=i=ZS{S$v@$wMdP@bEsN9#+Vt5-`G0IyLxvzm66x@#ZHyM~y~teQ;Edci)%hb>}0 z`7y&PjLfIYcv@+`XSuH2@^~5T{uR61cx=zc?vCp(kjFA^b4QZ1#4@>Pqfek6cL>}} z(l*PuEgy1s?3{}uvGa^vfSvQvgq>&NcI=#!8?d|iU>m{l&|XmH6O4}>%dItI_7FGr zKg5l#9$j)EZtQ+!SlroU$go)MBEuq;Cc`3~Cc|Q7I5I5MBE#Yzu*;(Pv)zMB_v!jXG5Q-f~_N$BiHdaQpweph>wsO@6Tlw(^Te;?gt?X)T zW%&U{^bJ@6-?i3HjWiV6p3B2I)G#bvyHjRn_Z!1Ul29CeVlihM^LK5gwM4jJHV#0| zNHdcu+wR2RO#axmyTK<@xxGX4uWSd+q=V_TSpgr|43~o@FEa=~{J>%#Rgw9F;me~5 zvus9z#oYNrr2Dy*br0sl&+5jh>=eFj_{5R3m#6}Z9Axmt)~@r?CKoTAI(7Qu#SDbj*i_yGn&-zce4imEp?ez|+vg*jcz!mj z7sLLoVO+M_HT4@Bs>xl+0@w3v<~YZUt{JB_`el7FirZylCw+6h7nB9*5pOUES)=j z-V!%o`|+7uze0g#-jCsoDQ>Q9^4g;`r<+|oYu+(S=S;={Dr>|E%1C&46GwRy>G+7r zxC&7h>(;F*uM3{!mh)d#j&OV~u3~Lf6)tKftX@;?nyRuuFg%|8o4hi_`a`5hTmj3Q zO~}r=abwC&vDUE$Y13u6uPAJBu~KihBC{rJzkY}r$Y|74Tb%zw0r{HK}7f1HW@=a*O{oFwEw zG5-t?`bgHtW2ni(nZmh3!zV)iD#^9NO~Nh0?ZVFquM}P@{I2jGAzg#m?sG!M3ZTp% z28e@%CBm7)MZ!-BPZsh=1J=7(XnstA{FLOEgnt(DEyFCIFDw)q9u4&7r%oVUlvu7z zxK4PQaEI{A!W)GT3k~lD_5UFGFTxo9gQeZ^!fC?A!dl@KLKFK4zY(}c$gYlZ8C8-$JreWv8k2tOtypcfYOS@}R+JR$irDu5edm5J^FXQHYkz+q z+?yVdy zFNRPX@|zOv6$|ZUHsnr{y9)VzgZcUjhX{uX#|Xy@HwZTgFBkHA2JKug+#n?dup6gKQM+%P= zP7=-(&JtD%7YOTx%Y>_irwh*&ZV=l2747kTFJ3ME^}_E8?-2e__^|M4;ZKE}UdC~; zC8&WNCG$%!_5A2T>?Ir^JVZEB=<{2rNaiedmYXGqZN!V`p?;>i5;V?ex9c(3q5;iE#bcbM;4;Y-3_34bSiOZcwvL*ZY95!j%eJR#jn zP^N1aqVJOu)5J_BL4bNJZf$t5@DQQ-Za|!@73MoqI8FE!A*V(&eXj5XVXbhvkW=TG z?{wjr!V82Og_jE(h1Ush65b}fQ}_engF;RxWj%3W3n3>=Q{P^=pRkMYK;gl{0m8$D zoIc6&M+zqi>8OnQV})~t^M$p-2H{tQtA%F@&k=4EeqG2Z{j`6TkaP7Ze@A$y@Lu7A z!bgQa5k4z?N%$+_?}Tp&-xYo+{EINc=UmjwNzud>LegI-w-<7)MfH85XTC~PO}DCF#5<{Ky+DjX>sFPtpo3}NP9C~Oce7p@Vm6><_W^EV2w6W%1e zO?an}lZlz%e31iRko>anH^ScuIp3K1lfsrlTR#c8-axM(px##m>SLu5Q_k14Ydoh;tp9{xG_MZnQ zOP(&ADV!y&7S;&sgiC}ggsX&S3C|U75c6Fwk( zNVrw_oN$ny4~i)Ni`S3f+o~_ukHElU!{e)MUGO)7fX5Zv`U-vU^OZrtIL`-e%*SU| zf8+VUtp@^5q0mqSZZCItYXET_0_I_0ed7^)+lYo%!PY(bjJeHE8v`+DujoL`szxJd zk8Sbo@jUR$AR6iq2I^UX_W5ZG_sI8sEEYf(kH7i(s-Otg`%rJpgNB0jQt#Kh=lT)* zwGV|dNcT72-cl%n_HI7}Qz)UMJ^Wm4ws$V#ei=kVhr`~hjA--I&Vn4Y_YmyOMk4Lu z=WDaQD-rk0AR5}Q0|+X(zWAG;b{P~wdz}t-`-%2Q=Joq~BjPN>_}|<<{=UVrTnDgiOgDF|`ZC+Z zjTksQLaUIk49d@2KVl1xXTR^h9U|A9@XsO2L(sloF`~_{7wbn1I5?BtK6m|yegpny z-@oq-vdWs*k0?fOdcL`1()wFAC1Mvn^=8D&*%;px+HuLLsnMYltRvxd9sRY@tw(Pf zohb`%n*3&B=9G^zHB&z7Fn-;x*iDnRT{hr|ZRZ>@Y1>VM*6m7A?!T*e^tN+Gk9{jY zAKC$D?TW6ywfKm)3JNA|y99aHA2IpOoO{mL6&>|b`$^kw7%=6d;+mSb;`!H)?lSu7 zyrH(v+tsg}j>vrYNf2$bf`c3($X#6PDaYx>$ zZD)=;8@1dB{dEJ7D~?i!or4-CZd*Tb@|)3nZhNaBGUcPf8k9S1^XMB!PujMrFKSxv z*HrUXLB3xbYeJ2OO?)f9TW$G&V{Kv8me{Q}*2EfFQ?PG-ZBssqj^DjT_Km%|BM&{f ziG4(``nx`k-nJfnxU4TnWaPGUMqbX5>|gU%4tf#BnBBxtDDZ}0?}a?Av0h?iWJC0l#K`D|*rhFZ;E8a@rE8+!h+NXGI;Xm(dT8~jyK=Y}`>oxTGk?^! zb4GErZyGdd+t>PWkFp(Wc116{v3Sic&%=24pS11LzN4)jXOAoxy(X_c+H&Kdq1)CC zt$8b%|J~N76%Rw|UGI2_d0Sb}4b|(a->!b(-&aqIGS+ix*9G|t7B3jPVC}BZdLDV` z&rLk~*6s3++QlPiAV-kB7=wOs6mJ=QbKceLZNJgm&cgU^=ral}AHMC>;T+%V2eCiv zTeoV*{^VSmH@ns4Kl~{Az=LmwdL?hciXIn)O5Axe^>_B3(@wLf*9I4m{7Y~by2wAv z1Bi7r?3;j>I2xB*_^e)lOBvSDpySa93H;#+#Zw5;SOZcb^OyLqOH^XG762usW_ zwog@wn7zSB#81SPB)h)G5M+rsrSksK*2;_Wc<1mgo+pFop|D1Agnrs7X@ zH~-b+P}qyKL@#1J3fQ2?Gx!s$w|JaCw{x2PSI6YP`UG6*V)9>o9xTT8>c2WB|J7V~ zBbN1Fox;e)0{*KLG$Q}i5i|*#XI{vx-tD_j2PI39KewGHZ{;Nr5jc5H=XDDXdt1m|N)$y$V>iBN{tK+-*ua0N^S5IZTvg>aAo>lF>?nXT8zj`b) zXZ=^dPciGix`ATWfAulkHCg}Fe325*`mbKjigx#39pBx5b$oaK)$y$V>WgS9>%Y2~ z;_m*d<5~aJ@3R?M|J9`1#IydZ&tz)We|3^aMAm;bAC}`;|J5T|(LdzBntbf8(fDln zubxZ00sqzOIT!)|)jwu>z<>3rtT^Dm`fYY1;J^9-$^rk?2Qq)ae>FeS#smJVxrkys z;J>Yp<`;J=#Z zRXpgwns2w`LI2fUn#YKd{7u{;NM>r-J^g zx#mec=)c;dBIv)mJKOQk`LB-q{;T=HFCOq;y`E$Ccloc5`~ItW)rtH5tDj~Y_v*j8 z4z>KN{8x`>53>HNH?iWN|7xwfk&7z#y%0@w3us_{mz(;flm<# zFy7MZT+li%QqaC&Movp_s#l1@Vfo_4i^j;8%Se1NmXX-Ynh`j@K4Zm*($82if~!dE z>7$oNfW0HastbnL`8cOe?nE4pV=odq`7w)(hQI_O4@yg5X@BFg3|<(kGq?b?t<+#@ z{&D#-0IZEb=#Btp_ef$Ngh=Sbd5w(R=!EJ zN#k>{*a72nFh+2mOsGPDQ{~l-j6Cl21n%G%JRM`P14cQ5T!ervW=mlh)!PQ?QyWTT zH&n=t?ad8cY1dz0=7{8krfrPQ+8E_qiWLEQE#kKXWPUVyJs?M6cVFw6E6*F#)PTGg zaZdE{?O%fUj{@@Jh;wlKbjCR`*_XQ`J~1G3HMn&FnUiR~7m$C1I48LH<--`55(HoF zj<`DzU3>kZ42}u9XWKtBrgLB+Cp2|q^!Sa@D#R}d$TuSXSU}#&xQzkwe`RBoSC{_2 zjPi#eP8PG-LprZ9TYMSm_aXjdK>j)6ZcJVMjQ6!Maq>vSj}OQ^0KqixIRGNFAaPUV|A~=BHt zBC2Pzc%dF>?VL>DHQKc^%IId7Lg3ZerQ|c(10BLWfRODQzxdk5Iu$TW3^8uh_-Ore zAGT%?T>t836JJH}LdOzZ|LUrV6KODXEW!1!&h{J+R;byJSqNwofp)A45=|ZJ)Y69~0=a?Nj~=_d>@IUPcIq>Q)iAxw!4qp{N)~13~)~ z?X-P*y-Oiv`)2zz*Y@dAglylM_bI+QvNzaV&luxPCAbA;{?d+w4nmQCzTBT+_~72X=Hg)bv_Ej{+w2kuI25!50%FZeARykn z1Okp5e+dMrwFCl=67ncNb3uf|LE3NK8s5RvTn}Ldmp#ZGg7pxVWnz(>NN$GOWgzuK zor!gftQeOW5^IscVhR00j4#2W2W<{ScuLp;J>n>f=X*ihn#lJ zeX@%D9+zPcaNt_+-f}9?><%Tdk{%p3H1Hr`4|Qvg-0VRzGBXn^iFD1lKJ?}i4Kuhz z!#LZW2UXDrJQisf0uyD}XGQy#?2G9B7G)%`|1ferX$F*zkR{11vpM( zIo5~jua;dJ@->LFOfB9p=0%JZ6e!z*g*ND8i9Tu!=jc}4yFhJSA1g>vwO-SPx(35GpZ zTp-zasx3aiwHWHbNERJ^#Nb&o8Y=4>X3edsSX5D8)_Yb}ZT$%c&l)jd+SqC3{T$93 zIc@T+$@R4hE9Wk0n03U65q3eU#gYN#RduxuaK)Y_X$LQ8NM4M7&8@9HVF75;!xzja zo7rg8%jZ>`#ML0U9ztkobK|+TLUrxZ`n@m2;QUPF z`7)eo3*e*OKRf*c#;u7^H?4l|un_+a{|vwG=otzyd!s>1OBDGp|WzGTWv&yJjf z)e?pkjEP+7)`DhF2Te3?psh14ZZW1U~2OZaw#MFS?A}8;AdNKi{J+zU$SPm><>WdBKYMT z+#(@-zzJ*-n=PDGMC^TNQ09nbw}`!94$95HuT2@jY6rnBVly|hnn zM%c?^0FIK~7DNahL3n+JpRRcE$<~oi+EUm?*p7&aznzK5#Qn^C+uW$j?_xEcdAJ=fYh6^oO1J z=}&pA&>XRFyd^IeZW4Y=Xgn(9`;p{-c720IICt5OlZEFA`7wj~?+70d8h;7;|1198 zZ9N0@=lNXp7jt2JKku(nhW;(-eLwH-N&gq=Be=G)T!M)FttF?09i;Cf`9NWr^oK}3 zTsTttNs^}tXG%X;@_gYkq3`G2{JWz)=ShEsaIo}12T&DLH_7mFm8TvZOHmMi#S0$e=JX5$qXxDAz`-bFi3U3th69wzLQ+TiN zA>m^}yRIYO&m_Mhd`a!r?-@PavJ2 z?U>*07r;4^tAw0vC#1J7%H4$hgg*a%l;p9(8N#E5l|q~K4?9aGpCmj(xL)|M@W;Ym2!APj zQ@CBYQ}`z#XYR7SDPcQdM`1T17nx?hLBd0YV}%ohMp{7pILQlyi-ac$PZq8ho+rFi z_zmF=!fy-j7Tz!XvG6J3FND7oat0XNofdLxCgl=gcVRD~J%1p5kmO-Pdme$FbKO~f zve4FFf;>y|-^+_%r*dZtHwwQlyi!PCm#p{OLVDk#e3$S(A*Z)d|Bmn@;U~fS~){=dG`+kxS5Ox>#5%w1zDjX)X=P%fwAbE!HXyI(3tv`i)wUQfzD}_EEe!b-L zg!cS~ay~zvbNAREpZETP< z`w0gLhYEe3`~=BUgfoS+g!6?b2<`oZiC>ie zVO}^EQC-q&FYomK$BE(XF)ny?vG)#u-F&c9#_-v;KmIZwZiBY<75cz5Ze0*?sC;g| z9>}w2y}=LpxINi6LHQ(x)}jG-tjENe81wCK{Ryl zKA}*C5p8}N=iLPDy*$wIm1z$@k(%wDhqzw`(a=k<7kp#or>#d?(B9htd;D$Uw~vz@ z{W6G#-hw?k==L{1?Q$rB_CA3<_K)o=K=AF|ggDETA#l4igSCHnvT9=*!}o-Kz8V}r z90Pyz^F0U!=)5Xd_Ha|6-Pif*56k7a`SiqO7SSwNd#FZkYr24%9_=kmS#_8vIU zvd_+4J!<^u<_X2H>xH`RHg;S1vJj_*JBPdCH>uC}K7Dj-=kPGK_oPGRD*(NBHU;g(;%87dvLvvAeGorP}?+F9`Az?}uN2JOrrKX7M$ z&7-@{FMV{^8D4Bx{`*tg589c#YVKQaGz{FCJL~CP=XwwAT37mzrN-ZDh13Mf<)D1x z?YVEgj$Aq8AK7)L_b_Zcylbr&-IZ^-qNpiaGiYacmdh0$Pg{?|)}xjy_TH^;Me~rh z>YjJJ+$7qHHsALM>Peu@*FE#gH**f@;6*Mk9eLHr$j0d9t#?GC6ShV!zjtTof!lV5 zX5Y3mJo(<8;X3x~VOV}-*SV$fU9tCXeJhqg>re8Akg1LOygpVcic(RO%0a1|y5Xab z9L*9exm&3oeyOyT%AI`M&IC&34!w70!b$~uz}B{Dk3K9zsiV-6qhgnDNsipMZeEAk zrzKlm4%YFUeP)YSti5vS?_T742-}@ekH0PR`GWBVQ|$gHoQT^Rcj4H5I0wKo?#d@Z zFR=wDd1L@p1B!VPf@*vSQX)JvKsBC6h{hg4hR8k03aYWaf{4cFu;2wOIKTL8=1RoK zg3NM^r$HI1!~q@2IF2!&^}#ouNxk^Syv#=EjthL_Q_M*8QdV^h{(x`%8dS09@9{T> zKM1_YJTwh_<9RGbHTcGi$4^5l`No$(NJPOmCUH1CYCQ{GQNS`7n z=BI9gVepNeSlF_BMF@Q3mS(6319c6Ob1%i8{h_kHp>D2VM!qp8Ag6v!1A~&zKqxhq z;$Vr<6fbPx8~c^>H#zvme&y@fmO~{Lraq>4n8cz~jAaj(Se)Yf5b%v%*$$~HW*#On z6KZt;M#cEXQPh#jV6TF2%s5A#`x*fF{-*`5y+jt+}ig8-!-5z{n*Rp782U-HYah0VeQfwIb#vH6jDR_FZ zC=KT>!yg9K5R0yY(Aq0}9!(|Rn9BmDKENOFjTvV}Utu$s`xU{`VLTMBLiOYubAh^+ z<#i$Oja8s!d3^|cV>PU0`SK9>#!gD47O-7+C+!R^%}@2_c-|wipk?`-su1|b}g_;mgP(5gupj;6_r6m2Y#Xs41|atY*oEOQg6`Ivn>y{vO`lRP<*cC2op!N zEU$s7=VfYSY7BS!iz+)l^$7RUOSw&GYq)fB>P0s4l~%)%2@dE}vzYm{{F9I=Tskv# zDtq*L0ngxY>8uogJA-fRhHf4_<1xmfZR`(^mNsYd5B1nD6Ohz`Np1V0q~jZNbkcli zBj4Cr3Z;L_!2sXb7GndC^HrvUZ|vkm`Z-n%zOj?@(_GA)d}CL>F#R-T@Qq)=(?Ynk zD18d^gKzB8%hJZk2H*HSOYfV0l=Xpc?9vCCCv)E*+Bg`Nr;2GBi!r9r?yC z|Hw2a)sk=Q(#NDfp$xupzLg)J?!{pQ-`M4!oW7be_{JO@40F00W$=yfw)V_S^SmP8 zn5R;t^s#Vy1`UF5%yT4C`eZmggbMJD>Ek<6`f@By_8s}g{M{cZeKnTmLXhMecefmG z$1wgp72HnZDt&>SWFi}fOniYGi#~=7Mc&8I@Bj^DrOMx*?^-67<6)c4g!08un=jU(Dmv_{Q64>Q?Ujp^ZpO{7~f9eiWnCc>qi(tP`hJ&2a<10k|fTzbcXrCH+Cmnb()k^@{OHbm*#^d`NmFOk+uaS zz&GZPdtTAgM=%5U#>boDEH7=X}q>64iQd}CJ&UhU_e2lH%|jcGe4vr#6;oxIqW z)1h`d$Tz+eiZmDEC*PO?$NXiE0rH8T2@pH6R0-zY*i) z50HHPAcR=-W~9fWx8d*p9)6jJyg__;bD#T(Udf5D?hS7F6tXOaVl+a@a_SB--CAT{ zj8IaBKi-g5{JwP{Mx`@C$p%_DwB@rX%kL@two-B(NAxh$t%AG)p>zp{V5pV71@aZt zeG9wO8`k0hl%0iWUxd=*P1lh+u6N5daE*LC-1<2RR=C`(k&lPBV%NEPD_3?k^6~IC zRPjY~X9Oc34=<+bd5Cu-pu#W7$G9t-hx%C7hkQEdgZ}?l^6`y0zKvtd$jt~O9}_t< z=I-~D)`PP};BbKA#J2LvM1D5Wf|2mT zjf@YW&g7{12G7blCbL;CJz-7E%GoBnbl2)zksmD}*vu!GMho`XT-&A++yQan82^9( zH+hfDHZ#EsP2)>InH;}o7FjWC%CmbG5A9*Yh#0K`2(A&+2v1ttF@zToBB7O@?b|;> zKrbSr6O%4~$Tp_A%1 zg+HCnv}FjswRMPJ5s zFtZamp~)MgQ#M8!FFC{wSu?@+tMjYPZY^}#+#uIk7BKT zSvYhQfmbS{88fob=?QFwNV<%k>rx18kV{GUZ32>t>IaBy6+#5ZMtC^nqY%&`0$Ugk zt*9ribZP=y3-vPMWu~4^V9TLiNqhhS7YM@32vDCwmoF?+^&MyQ9t4!L%Q86EFZ z2-&{bV4r3w(+SzWHIH`(vyMN_-yGZplp25I#nRtuF%Xe2DXFvOFJ78iVpHPrB{fs2 z>F~1#+I08kIqztjD5;>>#gdDS?pFYEXrddUq@=bs+G1JmgaJuVt@TX(rZ^T`X~mj45y!>`xx@O{;s6 zSc#=XKE6gKNiT+|#+W z*p(oW_3lq55jZ*X`VREjoA{iQ<;^wou#9n5(J(jb6}P-$^w{xmCv9GE%U#@eqYD!0 zf)&_5RaFg@s37Z?+NZpI$+86dsUg#|iY|(Kf^ND*a#dZ=xwVUz)K|=1a_GOEW%-ZM z#OyBe1tn-UAJd?Seo55~eM!}{>sHm`B`4MK+SssQWo2ky?b10lU=QQ;;?-|)z{j^; z3Pa_%>eW@wT~M{4a-L7PT(G#RmSp6L`3>-UzM!Fe?uv@gzk;gyMdVxZ>3?s0%kWQ) zZuy1uMZJ&zlf@7}TLRk`nQzJQ-YehIF1LH(TjC*zui5{be9P6WA3P_{=OgmF7jd(2 zi|{VtL&Bd5pBKI<^!b*%B*!r}v}b-bf!!oe67uC5(-#Z*LWr`xWdL3#`C8#^!mYwz z37do^{GpF>wgeN<=HCJ*NIy$>f^em9z3>v@bwcweiSou%0X`@F>%#YhZTMmV>7_#B zlRzFOnR82-zFK&$(EL0?|6R$P!o++Z3XR_Znd{q9&qeo%!-Z3XvxQd(%|9aY87~9) zg7o~##_}HsWB3|Gxkxxsc${#N@MPh6LQaQbxo->a7d|EYrEt6OPr?)qc$VuZ>?u4{ zI6=s-e$2N>$f*jHFA#1P8V>>b>HIVdtPt9~e#omOUm)Bfyhr%B@I_$^?~rJxjj*%O z=G8+#O7aY0rEsb64B^GXYlPnuJ}R_%@UZu$WSi#>IS=1aS$_wi`G13alH~QmhlI}v z{~$aB?}=D`obXuT9N~N+muzOfHNthmbA=m)-xA&~{Grfzl_>uk%GkHR6Z-thca-lF zBHBi0QN$P#*>@DmkTr8{?o+Lb3 zxK?2@Cj_Ln?ZI9xbd=<_p=lRQtzr66gCa|?)Tgg!s>T*;hg!1UXN_X>X?Y(TXJIbypRiXT{5*fiz8~cN%5V2?lpigb4vuK= zDB&C-C$3UoFI*-(O}I{YzVIU9<-$fG=ZDbFqr&HfbooKOJr@9d|HmInze^ZL8uR4| z)57*bPBvlsSm9*hbRlOfAcuWK7X@X za)Z#;*+6-pzj>PUX!d`Rr-vVUU-I;@2ly@2ZCwC(^bO&1YFl5S4}QKLP%zH@$Bp@d zUpH}ivTXwX`emqi8^SAi7V|ehZ7dXc3=IucLXXb)ZG_{6{4s!iQ)RpM%z~Xz%KPJwCho?c*#;zYJ}h4|@&% zP6(v&Jwnjl?XbuGv3&&yzCAvN(q0(?HxCcQ^pWmwOk?<-(9idF$=}A)n^&6M*R<(3 z^#_Ot+jn1}zpa#y?cIuiW3&!n+tsiaJXZa&AmS0Hd3yo*GElaKrX>RFEkt0Qu-CkO z)akSBu}m=ElW5iETHY-j3UQZjYYR zxPAU*iN^A67vDKL$adVokL!K@uvleC6qg9O zV;R51>Dxo&&fFfl?Ebf-=j^zz?uZZ%?NB|geeQUSdi*VsKL!WmSxnhu0~2o>E_|Sl zEhdCxw&F)PZZB-2vDG+mBdeG)sU4@Fg`@E{loGK!aCm~$cQNc{Id?;lCGr9PlogF< z_C%CVwvprU2YfnCpov8{<8Mwmtayl-d2xfmMq=@z5f)E|%l zKAkfVO7);PSYkBw7c>)mI=^zRZ38}?U-?+JI?Em|u{iY+Ef1C0 zA=QnUhe-sVj&tRWPj??%^%|N8J{{v6^=TBxCn*}AjvlPQr(?&APgg;CisZE*#L&~& zlgMpd2A^&bYBN3^SMhPs2)M6Slh|xi4~pYLa5Zz^CJ2iBCtv zxm@;#K{dppoKFuv9e+-cPd5i*>OuSgpN?^MqaB;M+^-0`heuuE-DoTMbo?PDKAj4P zPp5{7Pv`H8sccu)et$CYRv`E>ln z2tM64CU#0~V5=WbJ#J#x)OoDvi6p6U;nHS4ovWysPv<(&%%^j09+Dze0em{%p2MX> zQ+#y`KHV-8oB4Fk)X0>_o&KWQJU;a@kDr%vuSHwQr`yOzzS4>uPV(vKHW+-m-pE8g z-E8*g^#Y#3qboQeHd^%n^$)|I2BKB+a36qA$J+$?bl0+K@abGH#-w@hlTTM=_9mzC+ap9i-CS$x z%yd`g2cOQJaMkH2Ss(axPOeLLWPb4JoV+5fGid>Q zI<~<0bo^aIJ{?UMpKc=S1fR|+z^7})lM8%0rvRVs56l5Rol}5Mm!<-II;Q}iZYbLU zKAo%ON$}}L!8}`KV+uYUWj4xW@aZViMXJd@pKb~i>0wAApN;~@oC{x(PiG7Nl!8yk ziy{Rp3O*fo4o@V>j!(xcL3>_x$fx7ZZT}+M2tFNab@gBC7XqK|4AcTX9aSAXUIy&w z#sPLK;;|@C^bQ_RKL1>J+4PU&Z!V9)KO$lc0Pl@U3y@F8D%B=rRek|JWe&k=B`89eO${>Wi%u_H3yL`n-J{@U&;M0{ro4nL(SqQPk z(fAXKy1(Sx?GHy5$TcAcnJ|&v{z5M4%Qj7Hb0V_vARLKMGMKtarkjC`+%+Xh{P8BY z`YO^NMwHJ-rL_>eDQ!+bS#MeiUx;~AP2#(CzGv^$g>_E1Qv34mj?k$V9r0$gX4CF~ zd<}IZ*?TiOQFjEQe8=3m0zNm7vTT#lo`DFR=TOy_x%h_b_f*kY=TYsbx(h0fUS~S% zJgNg#e5cm~0mi@N%i(S+rSbauQA%mEKMcw*Ixu=5*zK=PEX(v zvjoU%jIxs?uc5GQxC#a~9ux( zX&ukaR@Q(G6N!B+US~Mk=_e7ZoIXKZDLs*$fdjrmnDICMHu8h7L+i^BUx9!Yk0Y+J z_|kdAODw)&JaMzdm(~#PviOFHM74Mc@dc+JMdT$Y99p`{zZ4-pi)Z~p*UGWPde_Q) z;@M6=im28X!GvvlFxYUhWvka9pw&}|n_YY|(Y0v9Frp5U5xKBh;%b;gIb)=T#jsCa@4y0?{n0u4({_`;;8*J>nZ>xy!wH=tR#3P$dPZbj_)Kp&oa|0c#HPe!Q*&a|V&Nxqrshn`nVd7Fpm5luk39TP z0gL`G`1IqajjNk~nPh*hu>D^|&RGWSVsp7a_QpALciT=&u%_GIPF;J|Kt2ZdIsFoF zz7di0vxx18NbF2Z$e-dz*!|c3O5LCUODpLESX=ASpG?2PRz+RSqS>hk~y)5`E0&8 zaE9bc;Zorl!i$C12=5R+Ec}`94dMI37~Z9^9-EKN`X%=l9wD45w0YLZm(Ne4z;;5L zw+z|lDFcs?-sT@eu9tk8@FL;;Lh}!Ue7}^uUHB(qD&gugzb?qvQ}Urg^Vb6XagrAc zR}0PW3evwR`BveB!smo<2z%q4Xa9x?R|$<*2K{xC-xY>)UH;a>eT4f7`v|!VBJCa~ z94S0fc#QBQ;i*LIt22b_i3k@EVdpZ*R|>C^o(ps`->t$srT>xSM}$vE{|n*k(*It# zUHXqC8&3^!kMrhGe?Aei@zj8Aq|ZoiJT>SKmOMZ>S~yO4wD34#jj&FL%b1M=P8&nJ z9%EbzB^L|rjT-cwBzG0^O(n;%udqtEPPv-Pgk?f5 zCB}4qStcGWoGqLuwEFBJ8_1mOApz)T0 z&q=>c*d(<34AMWA%@6H993mVcJVI#qA(Wpk+3rV>=Sp5EwWN7ldp( zgFRmW3nX(%aq9OG?khY%*j?C1NIw_M&!xeM!-eC76NN_!j}guhRtas=G~)G=R||TZPXFUlzV9^!aL-cxQIr6MiJ*gFfv?h515GL7<*X z{u4V0eSX?_$O{CDRcK%hd?$ge!!rglmO9KW&5LO~NaLn}yd4w+L?+-X(lM z_>k~P;a1@bLN15S_Ps9ry%2y&>Dl`$M9YW6%h1+~KskQO3b(-cNFVCeaMGeB6?1?~ z>K#`5F}i09_2N=cp<;|ab{n5#f*Wpww)MbY z#<~BvF&}>e`y2NkH~#(%s6(80OrOgB=BJH?0*|<%p-T9q6kpJ>-}(C&5TZS{Yfm27 zRQwh$#68O2e0wKA;m4Ua2glAweq#e^^AQi$yS5w1MffeidRd=e@5(?KL_^1bNR(kj zn_t&5$U%GW;en9PjvZy#rm_+@D0 zY}n&(MSt_tE{7s$uL$Av zJa}K@>MaDaPXCxkH1rUTzX6PB^X;{S9L(1P?R(YF1oZQP2iC85CcAwu53J9C{sS%h z=kvfay{y9Bcwppy?YMmanO{*bzasNThdNLHC{r^6VfsfMYSw*x%?BfZ(?2SPt{7M( zT@m7i&=msnrOQV=0bK$ZHJx|(2*k+Aiop6ayK%AFZjDsu%^q1DDqZ{WRquI&$Inh} zU0Z$b?1!pN?*8QL*w*lZ+=}4~PW$+(caN+fE9x2?yl%fly>~Ha`Ft=r6a5+(7)(aN zhx!#R0HFTNC4^)9AtRiU{Si`xSA)oe;wj7*jrBrGI=9G&9jB&ov;Cnq*>;6Z2F2 z^_A$;-igMON*tW`YcoWi)KbK97vRr32-Y`Tw2~N_PKf~t{&GptHArGm((hkaii0Ia z&39Ph5Q&LYm^~OGF+ase@Wi1K3sdCBB@UBVl-hIkxI~G%;~xF5?{a5fsNKDRNeQitn%z6Rl&A!>OYvPmxTX6o1@uAu8)Kcv5`$ z-{2*VOO&BnH{Qp$Vw~20!j_fixFLw9o@To%l8&z9cv6Wu`*N_vlcM3=(J0KI8bI5C z0G`zOY-(a@VkN}XN%)gk){=2nRKR8~_bbBgDMM9-r=t4m#2txu(MIy565ng30^~_0 z?(~lY@}v@XNlK)qvYA<))a|V5o+Pi7;Zo;!EOBp3atY{nY%DY1r?SPVXDL2tqePxm z1I33sUWDe6CsoM(_-M!bP3)8+MbUdlV^D;Hk+}I^vRN3(2?_;N;W{ zHu9BLtuWl=N%7ZC;ptDJ&uD9o|H=;XkM)n z;7O4PLBC_~v3~HR+@)k_dK&8kPs-&VnSK$6ZUQ_hmp&%Fn)bkxB6%VVp46)xRq&)- z{>kZMSwDDE931kbNMK5UCuJ{1;ctrPRRTOIo=V1(>P&;+N%0&po>V>+;7QRjlJTUr z&?I$C*6qw3G5^j**NSZzNm^tFF}SP?{R2&fCjQs z-dw!zSOK>H%v|YQw zld@&iz>ew3?tv%eMlhN_l>G-!N=F20WXIuJ4S$PA!frw0a4*3{*V0_!Bmth3t-uCT z>sb^$DJSQo>7_HVCr^sYw5i$cwkFnu;{_PTbXS@JPihSY0au>%?JNqOl-rNd^b&Rm zJSk=-Pm1i@1b9-sO^_$WMTKyGXyJM>Ce0tU3Gk%q&7R{)CBT#VDr%?Su^l|Fz>{(( zTy^?~tPeaXCp(^00z4@vuSoA;ec(y$Yx`V0DNtz&dzk_}DKe`Q;7PFs#*<}iDF+YoA2A-5HP)D8=uj&-c6nIi= z&?BBmlK0t>fZws3p=i&mP69kB?%ei#VUz$*inY4>zwZ|UPpTHRfG0(j_)xrV;Q%8O zDi-C5-oa}^+&>rS!Y~#kDKVGFU~aA&06r60rU~$*XaPK_Ijk5wsbUl1cg!a8CZa{C za^K6LbUdjf{Ep3mmHo(wU!CFmz)%JuhpeaBXd8xxXo;1N5dzgRt5baHA!A0}TOeyk^U1eql zA;Krp?tV@)H3^yt2r@Mikud*^NAQkr@mt^2Jmewu&P?&xB2T}&pVLfnjj!_&WXhhW z`DZqQSJ9$3T57H0iE#5#d!}Dh3 z%*;DF?<;wweqsXy653=YK7zLz~&6TRUDzcyhwrb zYS$%yY-@hm#BJRg6k~&MXsXQ;?f68^xNJDC%FQlbNW4XQfHttUf*Z8EYnZJF0kky& zuSambHLsD8u1=_KWQ5lZq|`JrGQ1Q`G!jGY-oxn34OtokuBO9EMXk=uQ6Y?7w+3bYEMny>pn49_ld!}L0j95s$AWmt!3-}4BFZ%) z^`fLP>e@VuFvl`}g;0eM2`%?*9BE&aG)B)wK&^!H5sZ??k-XCB37Zi_Nn@0Q7o?=2 zHGzM&D3l!%VH_W2$UDUHFR2*`ob2LDxTD!Bx zYq~I3pK_nrQ4ylH1+`^-@98$L6OaLptE9pK&ejb?Kr3oKOB*!6dBvOjsw89u$R>a4a`O=!)^w`UfAORo{iuS;AJju19+p0^MJ68 z`GY0O>`ZYb%Ix@bC4v>BMvwLxaAq^e_P(4uSH9CG#-v83GQsn%cQ1xL9)*XpsX2p~vHPePyMec~QlZYAA7wnJmg75b|FhF=ipCe`>4fk*-o$f>})%B&vwpUvi&}oEg5+im8K#Y zda1&17dHKvUL+TF_nls`y`5c~m}!64^rv>WaxE%Lbw%<47=%bY8@Sgphgx@&k-xu8 zDsr=R>Hu)T+JxZ{^54h-D#rois576*1}a}Pr@p3gF^;T?C6%EOgJ;cXsH|_8HMgc> zQAK@O?^#u~^(P!WYs7?UW2cq(b2w|{w8^t3*VitDbD@S=M~oO@$7StO%+0TYeaGX=YLRGj{)+}g1nMHQ&l+PGnyLdi~Rn5a~V^Mj-vIXq=0{(qH_03Hx6~e?;>a;}*h+A2vpFFbXxbb1G`e7c8nAMGba8Tvc)Bd{KNzW%z`m zjnBm+vV5QLbg_EAh@2kIt;lZK-w4!w5ji~V&@TSc<{0n6;qfmpIHSSe`Sh7?^Pm2c z{-PG6jpY9<6`n3UOUU0=O#hbfI^o?yn;(w!CnVc^aLC&w?-cHb0im5Uj`45zAydB5`B>VoNCQCj_I7>KJSTDR#cqtM4>>I*w5>fX}O8=hZ zdxSrb{&C4q3!jz#70Is&&94;N`A5kg2+fZa>Ph0QHS23dL_5+%gf7w_DC{fr{YV{3 z8Nv8EC~tfnp!tu2onx2|JYKk%h;&<58~9bptA%To&-_TC+=bF#EZnU0YlJrl?^gQ# z!bgOU3x7g{y=R3lOaH3yE$Md%-xEgjU3(M4mcll|eTcBTuds{s2MYU3e+UsakC6UI z;dJ3l;c-OdtCGA>SWm?MyIhFNz154$iy_p8g~DQ?z4Jr+CQ9Z!Ah!2t;c>z$;X+}9 zaJg`eaINq>;e|qbO$od9h8TFA^fw7_7v3eb`x){*DEUd@R-xVBkiIv*(>u!dzVOe& zFz-(&mnY=MUCPBmTf7r8zy4A`OlbU8$o3Ht$f+<)w z@EqYL;Uz+TX{P<}3hxr$C*)UWrvFxGQ!OCBFZmN8U%oLPSMMg~35$fq!ct)uVK1Ta zZBfqd+rY!6A1$=|IP^0l+x;9eKY_D87Pr*lm1-{KiiC6CuB_Q|407M1Dypb`kPpI%Q6{A=>i;aGGR(E~lPr9TRPi z9q<&%{8mo=CLzCxQ@%my^Ok-fnIFWN{xjj8ez87~{$nB5+OhmOLVhD>`HZluu!pd( zaG;Q1(3ziJ1Bgcpj}y)lRts_a4~210_OBlhtsIgKal171uQPjIUouMXBL__D{K1V*k zzxiqNq448O>xP4Mx!fbj2T9>`E_v`ThQKp z7$}}6w1>y2W_#-q_sbv}dI0vuFrv**I|Fji-jlF58#>zKF#7Ey=ff|9XefaUzxH=x zAnogj2krIf>H0}~IJKJX@t#b3WeD8f#7Rg0X8y)BhFgVxzBT)OHaCR#@L>BsLcZX! zAABbiiM-n)a^#vK=%Z!lK%Z0Qb@%m8 ztVuwhD9bzbmYum}#}2o=r{4ej9jBk%!rvcJZxnV+{%_EeGZCuUrN9PGh^-&tC2qj^ zAIZm#iVi3qfgIq6Tm}jJkbyWLjUN)7P;3vU(bx@0iQI`2(Mj!iaKLwt(MS`q`?1@= z54jwBXb*k}pT}aE)&r0|aw>|(dbFOxcn|8!issQwBFd{r$#V@z zr1R6mM`NKB-rvj;;Y=BF03Er&`hOubFwB8ySljS*X2pm@=S&?)!3&#~n&e@lPC9Vh! z=N^y345|TB*CBu_@*J9)NG?rW1Tpml{v?;RWSkWp%VsY3E5hz6!%&4k>tZ2Z$$IR6*-5d9_{!u6Fa3IWvd@geQaXa)Wz)66UjDlW_CVxl25B5 z#}!HbL>+Kkk>pm@J0$fAO+DMPy_FrB;ymZ%b1e@v(Q!qR&&$-v)L`!P7gctAiodmz zFXjH+`a3!GBpdlkD`UEYD?$c)^0oX5Wb(Np$=3^b29qmtIV*ZY2OGH}XTS=Jwy{4v zTH4g|5B1nD{gBjxNo{+hWY=hNb~wS&F|J4wToLBO9!+1z!2nm}JnMqvia;)Maw7c{ zD+X7@$@yu%kWGRs;>s7Mcc9WFxFV0>E=aD(Y0M9jPKB zr4LMVLT(aV5l#jtSELi|fh*!JB}3B}QU+JVP(B2OaYc9(+Q}@g$RWOri#kXIp(MB>m!LDnFQIYyNpMBZ zM2@swyTKKqz$1dLeUspdu(B|`EM36g>^ZJT5?qmu*3_Bl;mi-N zh&$n`({bhpSH#JVE0P3P#K|ktWvmZek^ZQkS9J5K13E$BXj6bI@+0N|SA;ES=87c2 z6`={^ittB&5?m3d09S;o$0WfOaSCunK4cDXMVta$k=|5*E8-O3iqKPE5?m2i3wCqv zQkZ9}Y)ruwq0B~^46X>}qkNfMktDbxr$Ui#KuQu^5egi0UO$uIid<+ixFWo&Q!rED zig4%fM3TJEjwHAuk3i9$SDhrdBHX#{TXQ796=AKe{-67Wz!kXH z22Cu=6TO4Slg~dF@)3_kNzBUSF<1i88URkmeD(lb5n2FOd1o6M2RQI@>WDg@~IguFvd zcMiIBIs$YDLs!InT-JuScn~+zMkCMHRuo`(zMmW$<>~;vWbOQMGY-tvX^3OgjJuz>#U;1X`*}~F( zqLqFOnn$vwSt!ase5376%Dd7p%`acPa31IoISWPkCxhTk&U@J}osT0f z7vVrZ(Mr>uW+w!c=FoLQB*H%&8E<-Cmz0L@5agkUavQ$Mi12gTfqqUK!YXLUhm$E< zi11Gj1aC%Oy>IHP$a4~cnc9HJ`3ML4InC6y&|HlmQ?wA_A07|hQF-_KrtU?ayAjOP zRz#jgIMB~&rhW^}>j*eDc*xU2+;-~R7+)E5`51ple%y)BWjlm!IH9?QUsvYp7RR8B zf;0>Pt)YoAh(!2j9D+A5cBF6SMC2je(afwvWG%vheoiyB8Ja5*WQrCd{4*ZGtBifk zH+2W{+=gJL$aZ@S;Xps9nR*=>UfVFhY!xj;_=n#;ysDUWY$wt`L@+Z23EXoL4)k-G znXb?rfPk&%|6}h<;G?SU@88SJNnjwXYC;mWpdeutkbP0AXbg}*6q1mH zMO?tOYHdZWR@>UR)ZJRO?pmp}wr*8wwYKhBZC!Dzt(I2*=iGbVwjecc0XyD*-@6vW;C81ts@ z3hUNAn1v4v zwZd(5m}SptjkfuV8bWf~xCYuPEN-vD0#<=?MRi%LN)|6kb_Q(aD;+&X)*NjdLl1 zwFx{xrg|)WXjV8a?}hm z@?`{b3wD+fM&Xm|9PL!~?AgCKH7GH7KpRE2;g_w3a}7RO7%*SYs2Wr?q>bKYd@!;I z?1He<;`BG2!QuyWx59g(6=f%!PC!90P^;?1c}^ zrwBHk0|?{s$wiX{8j~WM&H-?l3qvQ94>KuzY~&?`fU^qTTx`Azq(hNSX9-;Gm&*>| zw^6hRoA6xg^qT`x2+U=krZKp9+5hZa_F;Cqcl)>beTs-onH?Go-U>ha4Knpo|2DrL zRf27ug4v7gD@0Mx^l$U~4pID)27{q(u8?UXj#$@J-U{6mkirZnXk11~C)JGf2QUwxp7^Bj;jr*8zcZ#nz}E1u z)o}2``wZvyR((zea_Qhi<>%Y@a8?GdV7`qg&i}E&q&2ks!h8~2ze^e#8){2xYnIn9 zt1PW3Enimu`5Bd3i^UbNHrWJ=G8#;lkM7c7l3UVc*oa%lZswC15bfrZxJAl*60WrQ zB;0B9N!8=>}uLtWdnP)YwZtlRK-_+Dl&5?1n>;!q6!p7(e#v zIRdAa*?@PBwgF$Z0Rz$j?<(Nr&H?W!;3NeM^ppA{0%(W%P_8ks9O28aL*A4>*hzl9 z(AmtqcTdz|U}osWqumiBcnDiGn?t3U>D+&B zidzsm%f=Ysm+BSC&+H_BRq}1VTrK#~(L5Y3v_JCA42|o;oRgNF1A0cfxzx)GZ7z*; z8&;ZGN+VSoaPDTx`OoP`x|OAZiT^K{aLRV`Q*F(6vj8)5)!3PRn#m`oHLQ{T<`Hlv zjlXg58!W)e$Iz6i87DrCs>H=zepTq^6XQO_^miRZ&)6 zSzb{-GBvEZc1b;asbbM1!umioqqRK=LFWn)Jjk}6rdqG|nv z6|fep-Bhx66#T8L*RNd;tb@F+X~U?JmZp-GYC=25Y#lUSUmyD z=!UViC2RMrYf6=@TDh^Nxvr!lRWffR&S`6CECI80{R+fdQ(x0k->`~@x5@mk1P#!N zva~=(!^5EeUva?Ozn4*HdQ8GBwYH{VeG|Ia*jQF?fPFQZ$&3gZU1Q*Owx%i{ZAVgl z%SzZWHZ7pP-E4Hy!u`r^_}YKYdeqpM2FGB_=VUqh51W8iS1+8l$eO!;`dM)QMTVf& z3nndEN;7&x{y=ly&9#niBHUP4$HlI}SkGG9T(k1QX0xHCsdhzuU489JYr|WM6{xNe z39YGF)q-R3{u}K<`Pe@>UU;H+Qs&8#FNaSFoti-&k%lHc%kqb;qAih!e0oV5dK#9mXLharar>4!s)^Tgv*7Sgxo*EcpRKW zZm}d9I~5>z2h#s5VK%;3)1MFy5sns46)qAk7p@a-6`mn%6B_#vqYp#%Atcc><$o1&k1GBA@twGbaGa1Vg_NHtJX?6Z@JGT& zgwG1!6#hkM&QU=+)A0R`=`9h~3fBuy5^_HR^)40OB)nJnxbS7+`$BSIGak2p5zT&F z;Ar`$36}`@^ELH03Q1E+|M|l4cq>K!OyPmTRl<$JuM000-XQ$3@J*pP&kgD2VlFaW zbDkTpM1FIg8~k(RH|M#*zgGTZgkKeYNBDi=kA%Mvz9@W87{=Q%=G#kHBU~rEMtGa> z31M-zjpy5gPLbcY2c0MXa^Y%WgRoV2l<+j+w}r<36Xm*#e)Q#!h31?#lwpVTo+85k zobV;d-;)15p*gP&>4mVSQQs4q^V%Rc_Mea!NbcKzj*x$%aEfq|@Ic`z;SoY}P8-}u z(vS3wohQ;acAmhmN`9X7zb(9si27bl#ODslw+rtRJ|z4F5uYdJe^&S^5$Ws{zANNf z&iZExV?^k66DB1u6dL6Pqe94yxza*?z_*℞b!3$BGNrUc)H}lrjWn8u{@UxuNK}Yyj6I&@Lu7=!bgSNRLFGr8#pm4 z%n{}b6T*~`+p?)oGZA9BaBrdE|A3r(6&Y@hJOI-8g#N|CLxg6VJLHGU-yqy5JW6t;r_k_>KyD08fPa;oHXhWE3cCw?2~)yB!aarD zf5mu}!tuf>LjQcnh4LRD4C?@r0NftB%|5I!q>QOLc#41ZI|ub1?5UjflPZv)M#LBJuBo9A!% z%jF*}G|%CX&z8SNSSws3Y!cG)i}@TSE~u_;wwbxabGR{yM)|7OMjj)L4@8A`S%cVr!4g*3g-*` za}mw=41^ypIk&@7e~WON&_D0+GWlscLp|v(n!~*oO!mZfK=^FCnULUK5VtY7lA${rhfG ze)AJL(n-lbNXVbanf@rDc^?A*c=@Y@Q-w2xvxS}S*GnZ|CR{CCBmDgM1Mo8Fi?b!s z%9tDGKlYCTIUcZ7n~QxMynMaAAf%gPix>5-FfRL#V~ZD`(fl~{KaJ0Ec<%ErKWrKV zcvN<(6ma2iY-odkcI_Bi=8YuF#qA(|95|grFsR?eebm4FuvHNFZidam{?mP!fG$65 z1^mH$%kYwq^PBlno%JAc%ZDEaPUoZo$4Swl%MWXYKbYP&JiKz=F+F@8Pp5Y(+KOz%RZcO7I*kMq?p-?!lQ4oe&872He5)=I>+c$Mo>H zo=)#_#VG^w+LrQ-2#nX{#r$r-hv@6IVgRwN{EK1y@Es=6zutgeaBTTSy#ort@-0RA z{PydCFu%SJ!HqH6lL5EIDC% z`drC3z0L3JT(x-$FnzA%n-R$(km+2>H$#$zAk(>$Z@Qb^2{yL7x&2(pEpFx1afVf( zz?>?%gL->Y?{2ud?>J%gR}R~O^xQqHEVS9%5vq^X>`=aU19`sW(|kW=suFg`VUp+Y z3*I??O9l{J0+Z3OFoUl}+k-#gI0N2=h>bHP$-fk0N*VL|n0rasGt`68$SB5&dK@h6 zoB?y88QKROA1doP8zHboBg0_mw~&Vi_Tjg^Ncckh&m_@~8>&KJWUn|^sL%nBM4FA; zdmZ|j;09<#Kr|e=Ec7NESUO4l!zo--IIHFZdeV`E@2e*HjGtjNETfeS!Ss2ABW=f1of`1~&k|jBRth zL!wDIYZyNzkLpCfrH3gvY?N7B2ayFCmuFZW&Me5c|jbNLRzyT`N=xdFy8?!84k zFp}H=TtdB{6`u^-5Nz<7t{l9$1IFzaRGwcG&S!^+5V19*?90+t)V+o62N z=gwumzwG|HiCdMMVp5NF-(|d(8^C))NlneYk;+dh?(AIJXM0a&Uxu1w6wlA)W3BgW zk3XYuJV)|fR^i1Q^U?+9Nb<|C_fniQnA`y5B=cU@U?VpG`*&1YgCBzztyi(L`VC?`Qov z2_DGdfg8Za&r6iB7T^Xr7k4;v1ANGEa0A%zvc&J{2RDHEv7>lYVl@5W2C(6kiMQwn zHvo^3BR2qFYIxuVuuDl*f+TVtxB;yG)WjOLIJg09_>9CH#s@cmJ*RSZqLKRG2C(|` z6F*`7zzx90AvZt^^}!8beuM!x0OyqlZU9at!wtZpE^f+wWl@Om_PYpK!N1>U_;s%JJd|ENRi&;%@1MuBUl7l1112+JFVM~~`8{7cq z=Qdb`^Jh~J+yJ%(!-mbl12=$11af4>BVi_=9E>u?VJjWIm`U-?iU)20dazt1_=M4>|1vdciW=x7l{CVI8u>BZL+{aRa8-U8> z2AG1%d*BA(ZGzkYdoUc_0Jau068EwJzztAm(wm?767|6iu)-8|X@Wo6df*1I6K=IR z64L`Wfb};e4rDmE0jz&hVi4NU12;gX>2q)caB26z4ba;NzzuK}OAKxRmcVcWyv$(& zZU81>xB*BY>46)-3cwBU7zN-4umW%ctVdiA+yGVpZh#Xh05^aYfE!>F%LQ%#n+v%C zrXdlQ%CsrC0qAF;j33+p^bhg<hHvm0sbMk0-;07>1T=E=AuIlud zq`(cp&f!Fozwg@~xB<8l6mZq?zzx98E#M0r58MFE)#iVh9|_z5G}!_-07Zo^mjN@n zF~DwsI}+wZ*ZGpHBP665v8POCa}2%-#e*X7Ay5zIFT-?K5$5AaX)B*8=w>w$~xce zo(FHYFX3M#Z2#B6J;3D`33o;&lW}h3KV0rWZc}h)_Tqt)b0OFZpMgDC&RM;VfQ(Bx z-@Ffm<)h>7-{UBRe-HjE@hRTL6y_M&i|{{;4+LMB>i$QY>Y}ed7w z=4&zBdAvn%gi+ppS%c5?e}<<$bWoFDN^#B}A&C!+I#;&QG01vWx6#2dijXyJbntlv zo~AZBs;sBAjgHyYv&ooC%un;zHbKsxN8|JC)dBY;LJ#QGHvJe;I z1C!QZ-a6&a=H109fA)ROLIV4zqpd0yAzrp40=BAH46sr)I~9Z5=***zb0Fa$<6J^m zj!(#0@1~6bWvj}pjyGxx38xvgX4lk)zbwLrm2e?GvQ?#%6$sj@78*bPnKu{2_9e{v zI{GK0E+NPKLiYEc&$eRkWlhbEtD0-prg)-EOKRAr$}z*2t!h}GYHe&>(~`pW;8g9} z<+V83Yvr;^vn#x0-6-tWKD@Dc83F_5I5Ncf;v}}NT16+=_$FMPw_VqbtSDW90kXU8 zP)5*p2wg4PA-K}ELvW{UhcIe=+aZW$JA~UAw|UElJ16eCP6R1q>0MJ>{eCM~mI(o*)%NV7ugU?CIgma=EKmD|(O8q8^Fy=R58X+?tr z)H( z4A7ibr!%R#=p}oySA#uQ3`MD?k&8~@>X>egIiRbITl7~o;CL-l_nH=1!mO>e9^V?t z9#y9Ey*8qKxrv`EN&EJE9r|UAhTt@`+U4y>3&Ik? zH;6)|F~(7qv}p_q)urKrJ;%#GGt4ZiXlZkp6^udG`!nWu|tY2dfQp9vTZ|P2|iR+|5`heJ)q};Ix3L-2aNzSkUCfF~i)RY{|y6wo;vsuG5)- z&9Dl@!bAHze*tY8jg`*~1Dfmoe>&(a2Y3IEak);$(ea#IC&kABU3_4k6gcN>=@;jm znU)EeUr_y4;&V5@8nj;_SgHiCkog6&T@nHz0c}tC{f}+jm0gQ{G}zs)g%2Qnbo*!Q zTJY1d*{3;4I72u`c(8D}uwH2PQ|8)lirnYPuQtRpgck`f7ydx#+qFC{{|iD74Z!%l zg+qiDLUVo#!WYU_-9eRW{=tBRpOBZQ(USbDjzGo|50}|AYTS`J;FiXF6krQ-$Vy63FZ2zfkyn z;m?In3tt!hS(t^#eWsffE*7p39w*!;R_H+CV1yo|O`2dMD#^+ZC{8rFx7b z|MK-#KoHEgY=Glzg&y-|JFp%^`@S0vU4>X2Q@#i2r^grY!St>xw(q%_9;@xAcWNLG zoX&Wp7kt|F(>n=a!SsF?ssA!tn>cG9Y~M$WBD+((&=5U zIAuUyXJP**_nG?_^Wx_Qp|6+Q_p|L^JP~@qvBi4ux&xnJeSaOOFQ5MX`aT3Vs@DWC z*R7q>^V@FiwybMzt;XT! zrHvy}pSpi>Ol3u7ir1&_U;N7ilVOMbi_WmM&+rVS>;Am;j~n~pM2mRe?LX*uUe&Et z-p*~=f8P20=8F9jJGafc_UOOy@vJ-cOPo4MLubU^oHZ$Y&T^VWj zkKd_Uc>J#Lv=_Tger;OD+0F^OLJVu2`r6F!>1nyu3XOUaT2nLTy>@)`lwHx{$GS~@ zZOU$1QE8p!9KXwvd!cjJJ5IOgj*NXXU;ovH4S5xlvJZ1oJS%BS-ri}qQye>N-rFCS zHSOnYf9^|TtH&k$ehs^P4$etp^z!Fq-W-BgMmT&S20$nr;fqfkhx8Oeu_5ve%$_ix zfI@pF7Z_2LJn`XKm<^$^$(0mkL`c~m{u%~aXj~ujH7&!#mw6{V3^|47Bu}GOIKrRF z!*?NeXkMQSjL72|uHjQKl0&PK*HILW{DzOaQIFqJ!cB08llffr!nqWr@|V*6Fk*xU z^*jRZ$ge0kmg(%3e=OaLQIBw0&ok*J(RR2p|GRMG_x?*6?Wgz`8Q7;Eik2B3g#X@I zi0p>fp}?7Y#aY&H97$w08+UXgLOtxi9E*UgaOPzpK7V8%gpy@mk;DC>*~g$>nOEjh z?!?$g$HA3D{Sb`KGcU>FZ};)@nC7J(R{(6Ph;Ku0WL_1Shal{?a>85DpqW>P7&SbZ ziGRPK2i)Dlnc@4X<3``dx)Px~OiPStZ_|c(Wk@y|9TBC~Sv-zJqviR=0?qEfj8-Ve zaGdtp(TbQYKr}wbczarJPJ9KLH(F6(y=MPqbYyG}62)#VG}H^oH}*LG9RiW58x~?( zY7dHzjdIUg{B|^TbX=BSzn?-D-CN#pyqVs8&^A@Z{>#@<(rs?^km$FWx@qr2d(h3) zUtr0qGi?)ujR*KguC9d@DTIe@XN3Xmow_ zcksslf)Nqj(4B5(w35Z#=x2oP;i$_y7@@19H$|&43b_9=dUFp&;Qq_#E&fR0{>$jC z@cWHN~UtjHKX6%UF}$J!HpAa^e6l2JS?ek$wqU{<~H+WnW&hn11te;Iv5 z6|nm+qdS!E`1m1A>X+Sl2tY=0Rs1Bj$79{M7_Z%b8GS-YO^x$_>FAS+J3D?qsuF!F zdk<6Q`SFb$Y|r*M7LA6Df$C z%fdlv2iiI_%=CM@W8mfh4X9G&_vZ+s#CROG?MjHh7y`5Ua}=7%jOBy#@(kaP(vce` ziv5>w0F%Y2Ku#3(5O5nMq^+rMXq36fru+KuN{!vm=WAmz&Wg ziLWpz?7!sQj7gC+B8vT&wjaZZxvUWOUs9R-FYjR=VE-j=6Wo7Eqr)inU)ow=oNydt z|K%+vz4?iofKlwf{5|wI4xZz#&l zKUeg`BUHft%WoP1_Fuk94eY;U3C#Y>Hcl<#T9Nbn93#r{ir*yfAbX4rrEvhiYJQ&i}388D+818fZ3nPE=!LYI@zp9_Z>Igd$- zaSU#N!=#0Ml8>+k*ni2D5Bo1qL{Jp_FHbaHJcu2RQPpoa$`*0=MOkq8SLV;4)Bhs; z+mh;w!aAuc{Bu*ZDL{fv5aGnFVjg+ox&v&q>`iVc551deLQgvVd!bre`tvlKWBc zqI@fz{dG70V@RTxF*Y`Q4rlOO1ZRe+6nhbVJ|_-jPkam_vpRT+`ygs;Z~+5cH+C@K zoA{VE>hDBOqsnn8d2DzgVPBRdAa2+k*BxfI8n|oeoVhKssDKZ5wAekuc=rBm<=Lr?d_l=Xcb(9up$gkYoUK z_CU^kF~|M(BaKY)SyX9GQZAJVz6#o}geos_{B1~5E|tT46|^78V~USr6K_sZE){aZ zn2gYVEmXOXD#s=%m&)aErrVF_F%@&ScI@~h1Elkyuk$h5?{@0^jyfkN86cgv(mH5A z9?(?W9~F+BmSli*@?i>W`vL8j0Z;MmY~!yb86cgpX&toR5bE%r6gw-)0M{+%SH0M| znySUaSdMRMRu+>wA@&_jz~U#E|HYbX#Y-{pVwY)F6+eZAEOwRVPw`7^m1{Lqiu-YF z+~Cg%t|<>7YtxMRs6LCdo{8O7Ksky{l{bAA^w%>~*@HE^tAKK;sS`e2-ujKiM+WBuJELlEaYwo)qX9mP@% zay3bcB2*siY6caJVWEb*nkGg3MLxENt2tCOkNsTgYN8a8rzAGQ4c>1;7{0a!6P?Jr zEKN@;jYNJ3L1`ATlSid%&9!k1Ld;zI7}Fo_qO&-~E8Qdm(ALyB$k*B8L}=%{V>^0 zGDJ!{(@N<6XQ*@_%RR+SGDJ%GJ^eDFJ$T+q5r4do?dK*Lg7)}68+?Y}J7yG2M~L4Z zV;JQl_WEo$$pECw`|;tv4%*`&>d>w%HpfjeKssl@nQo6`sg%tEE^w0!kjT{+L!?xU_xS1Y(F2~M zA#8wy-6TWM9`CTBmvtE72Oz|>2byp?qg=#ltaOtMP`aA~I)_uIio<-hn`8iV_zc(v zr^y@7wUMt;>0?gnwQeCpl+aItN~y_;l+>ke`^ zA$zwX$K_KpueU8YZvO=KRbcy{J2Hz8u%jT~3!fqDP$zd(>@djO1w&_{$K5eTqZy$M z_zZm&t?7<6vTNbLm@?XuyJNdECB97hh_V_K#T}cZtQ4{oK0|Q~8)W?`I~{&*pc%^D zDel(uA6^Op%@l^?1M1Zy5STG0+|RuWzR;cyDhF@Ldkp+^ z!>U0}EVgefgqntXJE8dAv3+9WVly%AB10TPW;ZC%;pHQEJi0k5J)K{dm2hJ*8;vK| zWy4}QkV?#TXXaC$GXTl4!nye!^y5K&ZlmbN4Dlu~-wnls33rEL)GrK8^m_KmR(QBuY4KMajjh(Q1@4meQV0b#eZ(m>N<7;eQ%)pU$abx^50F~@Ib z)|O`!R%L!;vMI)39TjLIWMtkl8KY`Q2m35kd1x?IDGf^>X}BbFY3xg}15vW!fnyT) z*!@_-J(VtM#!+G}3??iL$CzImpSSKpBByRg^DYQ<@y8q(aS@)!hgL@O+vs`)9|RB> z-v+>8E*ghd!o^QMej@x+*`J30VK`??S-%g*{>d>0UgP0~h+vX9EH{wO71Gq@J&Qij4 z_!zsYL2Y#2Y(f^^33%Q*@jrdV;o?tAu)HEXk59>G2rW>LcoLFV%%Ge?=3Rm}ui>DzuFkg@sU z2xHXX71a9yZmJ>YP$ZS{iMCwRu}yqVP3!9EI{%_Y=0&hWnbO!?JHj_J`og^HUv*Mc z#}m4YxmEhdbz|7IVr>gfK)?wqrK>SlcDM6F&(k;rKLJAlV?}meaHZ|M;7;3lVSV-O zydZA3>-jl#)BIA1A0*(;Kn>843cLI@((uSX;kpb!$s?MHx&7x=3hL*|;%I zbq71DNekyx&zZD%M)llDb7#(-?zC>KU%7Hk?Ucsay6W<>ic#F;;lK(gV2o2u!-Sw7 zv*U>@9qftHCOh1l5Y%R>?KWgG*Xp9M)phloa3qK=GYoNBjoCz?#Y}SrQ*N%SYprIh z$Y>_exHzYYjhn9Rq9s$NOk1?5W5LiiIPi$a+t4hF##w8ZH@6!D{ewnz!4jehwwvQ}B`Mk`%((-?H7u}Gm|Qow?#y{Ts&G_88h%taVw zQ)bwMrRtp3HEZe|4OfnQ4smpGhZC{T2RsrBgj4}VGql_72Rn?i>JBDszKs_xl>(#2 z&n;N}F&O3?zQ&Z#mciPL1(i@lX~`ZlKguhZ1!D)RiwsPL)zwpGALKO6Ti@C~3l>jXw77cuq?xmqES%=F z)~;0xGYVBk6H#*FmkM|M0+tW)t!D+Xm1 zqsQ2mH5P6DB4(O}6SBhzWVBes`q)z5)%vC-g9Y!Deh0tl1u6yF$!{cUK-WI$Q04y> zLp2(g1)Ght0^>J5k!MevyB}^8(-tnAx3GhvnHgMLI-4P*_u7|FjxU^rxxon-Gn#Rd zHdW`S!=9){b^-<&WJ-Sm~S%HO*Y}(>AN0c${13=Z?+`mDZ88 z-C`Ga1AhjN>CnV>!tuTzY(c*}12VJbqz4?%j9W5i+T6t&a_Q6L0uk5^TBmj^{pc~D zutv1k#n>gY^~|~!92sa%tnM8QnuEc%CpqqAA5BAWd-t$5(e1rPB|DnagK-j9Q@h%< zTQHkp!x58igGDpv?zd$2q=lbQ74sa};-7*SXdF90gGFYISQf)QV5Z1&jNCPi%V7i_ zxObby{YV;frynruYinye_nvJ-V;J3TIc}|l5s|IIxn|DMgWd1)S|lgybudb7G8V*X z!{A^kaSQAE&S{?oedB%9L^m9nqzBXBpfIi3@d?3N$IFl%1+=EPK?(<1w~G-V9osBg z{z8O7$J?x}qe+5`8<(P*)-G>M_L;YX{WUGK|MmnjPgT~2J!o3JHhmD|-;TXz=>vSa ziL}-IdU7EA|1lEhyQ-j#_^`l>E55gy+WG9mj5TrRC-?sJXZPLz@T8GYsNq4~jyoLA z$k=HmbDYdvZ%$T5c4m)oPq&ww2qoP+Ep+>33=F>BG&uzYVdoug1WI2aynqW{ zh95W}2;ogy@CxCrN?uR^Ki~Ymk(S{_O5nmzhyfqp%kj-g`xP>8^MZc7oeo?e01o&V zpYJu>uYbgL9KWxaTC?rbw&Q^z1gr5uW<6@37S?7QzhJR6+yaPSrVZkEDuc8~&p_Z{ zBHr!qCHdaMNy6zuzK~`*#-cBr(ev%S1e5`Pa@Jqs4;a7y;6q>Vc5btLBv7ykU^DE(t!ncGud|L~B z?#CvQ_L6Ac;sTG5f3uJzy9}pM0`YR;&BA+yj|qP(d{5|NSTkOpFeNM#E)Z4=8-&LQ zPZ!=HyiaJ(c0syt%0CFxf%%LSE)X6jY!n_V{HoBLy@GhZmjCxc{N!QM<8}b1TP)-+ zlk`s#&KH_9Par>E{wsyI3GWyFM)<1mLtz$vFk!lVgu{j7gfoStA*G(NB?lfU|Ea?B zg;xr>9gX@A3ZE9fDdhHUhF>7OT6l->L7_SG1A2dyKNCL=FkWxrB;f)ff7NC9I^l7` zGldrkuNU4e{DtrZ;k&{R)&!>4Q#e@2eHE1NCtND57v3biS7?5?g?=uUKgQ!G9wImQ z6HgY>vV?wf1|pDq1L(g=c!%(A;eEp23EvRDE2K>g<9{R!<3~UGvxVJ-+}cHXnQ*dj zp70pqg~EG;zY}I*ZDjls;Q}G|gHe9I@Q1?Zg(0k^3?CviXXC-YR{k@EHwk|u{Hrhp zUB;gxtP`Fp{GRX^!uN%Ju=|YhCJ6Tzeo44WxL$aI@JwNw@O#1?!uN!|aT8_w zS@M(QKUMfO$@MV%A<7LG4{)6PWJjia znsBCYzL4h>F#KR)wXpNqgX<+fQpoK{j7M`X;x~lmjB5C~HHq>Ygxr=y|NX*eh32^o za&ACk_=iHn`2&BF&rd+ZlnNXnKW^JFP{s3<+6Q3t{PBPw0lZ=+~4en z|6|+_{=@u#I_m?ThtVGBf)4x(@TM;`o4E$yKlSj~X)eyM;KeXrL-Ao>e45@~(CM7- z+mQJe`;`~xtDiRgv`3zRHNn69FwSp0>Nr&jxTf53QV?LdHQx}K9?LZkA3qM9P7Maa zI=_;Eu$q9IdXHky&c0pf9fGi6z7Lr%WHw*s=jYo5cQD^P?B7g5=3jo;8VEY1hpjCf z^Q;G!$8>rp!0pF@(dZK)O`{B_cUA~{fjp{Y|2@FC3f@9jxix}v3XDRf`AjECVu*flArq4VB z&E=ee@mCC)fBETkhajjo2<78F!M}XH_LpYmqdybx!`RBQvJ|gR=Y6`! zy%*-?Pb#>-c22;hbdlBv-Ie*0614bFUUEp-M z3X0%o=*_PuVee(AfYTuh5BH(hAZq7yxE|j#LWg5UgVO;+zzLm)UIdv#6Jum}!x@A3 zVvsqUKv6i7V*H00ZC;;qjmT@@mz8M5oF5tWCLsl#h85!1QSms05|mpWhtNwHSKx72 ziTIHR@GtZ=Bmo|Wjdb(f1$Z1zW8%^99Z(IKBOeC#;Zs9qI0yf|ixI&MeGTOUcLR$S z;w={34RlApjL;6;4SesCy&0tecLNQ;v%iXJfV+WmYpq)km)Yhm?uIkrk6+9*FZHfw zQDA<5I$9mv4d$f|xEn$jqT#^Zz^I|+O#J%=e}*c#8?J{8+zs!biz0M~DxeGQ1~yq9 z8Jo!6z^8zCHWCGQgLxuIb2r!=!|^C80`3Oujm8f_siPG=tv4sW7EKE72J7{?8%85h z%iX|-lo-#tm95TZf!UOJxy>Ra#cf-T*#tT`= z4c+NxM#r((8~uzhju&t!@WeTCH|&Q|Anpc55O;$LChi97i^e$zz}>(pn^Bw-U&*X) zmp9GbUo9xz~6?MmOh8=gj6gM|; zH_$ML+znR(!QHUHc+=bsHls9mgRMZCyTO)ue4OXbgS)|=GgK8nhwbrL_f;mTG0~*{7JxrPB$G^uU24a`ekO1VtFsyBA_w?gq9_;xMKQ?gm>SC-GZ02DlsU zH&qBHTsADY8>~N?7{v;MyTST%5_~C1?gkq_FEO2da5wM^BDou`U_rs%V8hE2A96H- zyCG@9M{w?gpzrKXGLY;oxpy$0C&S=Xd3Q@V^}3{H=Kw7!`-lyX@I+d=H%jT;8d`k#N&Meon*W$96IS% zlqoYz(~q7mDSbFV1F97Dl4=4$Ha!m8b|u6g4}sxo;3zbcS=y5@sy{cLP0`p69XP&0E6>@SnXha}KRy;GzqiZn%O`Psr$D z`!SqY$_jzIfy(4=_$B)Q+zq@)({1RT8-ynvuWZZukunCU?W}MgZ=HzfuF-4J?7-Zr~&( zcLS3!+zq8HBe)x^0Nf2l7&YW>umW&5EMWtJyTJ;;-N573$lYKC;BJ_M?8x0&l#(41{_GJ{S-#Bz_ zJ9h)$qW8ZZ|F)#|Mqz#KhPzNzBuJiFayOg+g$~>ee0iQCi>K3nG^(|w|Apw8WBb31 z0{Gkw!=Z9i|E*Xc!QJo;1dzMoE(oJPN8;pepy5^|!f`SO|H$1y=CVkF652VZ=^BPZ zk{PCEjNeEW!jU#hoCHrXp5#c^zyKK7jRCC3$23cSCsIol{!9nD2Fj&!p05I{z*DG_ zg*-vmK)F=z@Ks#Kb1MEFcyd?@~bu7Pr?@GYV(FDxYAq0Ry5 z5zsX-KsrOxI{4kV7d*xMy$o~>43N&Ov<~be*^R~TqBTI*zyRqqq;+6uc?fmRW09v7 zGC(?KrFGCa$5H2G)_i6m1E4bqMdSit+7GtXmr|t_JqNl5%BAvaUu6VLI;rv$`W18y zluKoouTt$qUZ=`eF-$<$K)F=N;43N%gX&ulF97&zC*nV|M21w`Hv<~dfFQCpUw$0&521w`8 zv<@2QZtDCDa{zP=41i7#}H8voo!O_Irjp{9PV&4GfS@k8b{aK>NAy6nj`_K-a(k z81BzzJDjVjT3o?$d{eWsm`fYz8teot{yp=*SaYp-HAWTa8tkkp-o-Sp()=mj$yT{m zGo`qcW8(&YPH;`R6j__j0A0g5EE4Ae=o%E)3he(8XDm#;&Ms428Kwfoznr!ui^ZNY`N7rD!9|0=fpftQMWjMGJHdfmOB; zFaAu~KJM>CV(=8Tve`h_z!2QROE`W&*I>P7Wtkt0Gm&w!*p8rUU45GxoDQp4N6`wgc<4a*I>28O6i?VJv155wsYrV{8HET=;epSVfaU^~m)YX{(`AHO}i z!(9~RVg2#<4aWP$-F_=AWjD+)XwRE_As0d z7}>aOr#T&{)XwRE_As0d<;)Ir4dQg5Qah&u+QV=ym)ZH0m6}VGg8R!~Fd<(h;KKeEyv>uB(h zT>~Gm*TTOFA4AvhQSL8x@_Quiz04bPeBy(#?o*9X`WYPw0S+ z7ynQqL)nmv_uU~Xk(!s8*YFvwC6CSPs)bhGw{8{d`RT~m zP-z((7_cusuCs_R6`z=s!yk>-JLN+P+u%2snMu9}B}wPn4^EpaU02uumi|`jybG{< z$*@?MGVQL9fKR-t5V{y26qvwALUK3|o2;0y37=6;wo`W2Jf~_<)eu3yi9_hyU}W$V z`tq#b56b$(kgUJ-ZDY*SZ9;@?_}u!BB!s;Gf$aZ*D7)3EUwdU(`mfu{5YEGA`+sU> z);p+a#h^A;;xc?5{SU7Q2V#>Qh*>Xl^py{4W4$S~{A zj3fO}XMODtdGue8r>ifhSN@sPz}M6-Uj}}YPN#xbmR6LOFVorJ&gVc#)78n^b{8G? zxBN#_uaGB&Y%Bf6w!+h@Lk(^u8tOr^5=*+07;i~e;)cy+kk7o5b0pYWaMm`6P6Dhe zmJY?IT}hEVrKFI|Dlb(AP8G#kS(Pc6fkaNG;=5iD@-X0IK(Gh$xm5E z6>_cgjKun}RIE#uYe`p9hIA#r)aPB6aK~qf{Qh!0gGKNOgv`Xdi!(ULa)Nc59qhQ&cdd1r7e?hv^*pR9iGq!B(s6$dE zYgaU_pRl5_8AsihtQ`e^>uPWi0P7&HYuYfXq@}53W%(FNXt!Sid*cbKYnoR=P}96( z^#p8p-7vPcWbK}HO{tPqD>v3O*OgSHO6HABmDDvfmcU%Teg$H!sjq<<`zi?Q#Hm*T zTAbGU#)cNiNVE|2*EN-Z1Em!v;H?ut8RS&|OG#HO*W70?D>n~7Fq~gi%}N;_tS^XJ zmdtK!Sk=ym@dYuImWCx%YSIN8mZm;KXwe-d{l#r89Zut_8F?>~TJB@UC1A1DEGNmYUOVc@;4TSpDg@}@O5(5YlvndaXk4 zQ>Xtr;dbHU!W{m9j_?BEIN=N-&ktdEozVQ?4*!Yr|48_V@J-=ggfaY*&-mOkKpZaQ z#w+@pg~tic6w;QB;nxfA7XCu`g76)oi}(1{?=Bo5EEi4^E)doT*9ngko+-Ro_ygfj zgpUh(WEt~2NqDyK65$VoJA}^)cM3le4#!UgOlO>MrtnL`df}16Q-$XXuN2-UykGdF z@O9x|gt^#?!uA&*3%pH@J`qlDiP-YtAd7{yJGdNkG|&KI@{ z&lBDud{#)aH0lo$&JeBq8F7?w zvT(leP~jTkX5lHqtA!5>-x2oAv*}g}mkGBDzbm{?__{ET9gr+fp>U#bx$tCRXHJ#p zB;P6gtI+3EDaYPFrt5R6)XLu~JVAJt@FL-L!tFwzQ{_GR6ZtmXeT1KtQzg{X#v3Z! zU-(%$RdB?Lsn1y9!NR}Asq&=4e@Dcc_nL4gk#nH8#Y~~$TtR#Fp&vL%@?pXf$t&d_ zFPtR#Z29L4mq>n?{40g^lDEpgNqCIpr^tW0@Jz|SE&qkWYbC#3_%q?73jdYRaIK*J zFVPQtMfeAWe<1vrh@O0re;Wvce67n~5mhZ>H`-MLjJ|Uz%3-w+U{!aL&@Esxd@=-4)G)9u}_m-dg z`WSAWlYlei=T3RbeeRT{@>dI22#r}K^e&SB3gI=v!};8T@CM;};gQ09`TT+K$-=&T zUVy)!aIla^&`|E;Lo}RiK=V8S>?iqPp?SW5+iuH6s}#aH5>w+6r4tg6MKF75Gmm#nF8sCASg-eNnYD{#<9 zE$CJQu|QI~7D}KYF0E7ZfZLA)r}JRS>e0>1 z58DEFFunV#+SAKH7~7fUI|m;>4xG+YDOi|cE%7fu>`VxP>HWIO#%K9>TkzAn2yVvV zI?rp{AjjEX_YL|P#?LiEU+<}k&&J`hc;si}aCyF}y}o!vNtf@ZaHD$c7ISSwdb}6; z7t6+r7#JSTPoVc%I9&dK#EMM{_Me{~9>bV#`g*(S6F6Mz8~9e26fUXq(PJvgMwgY1 z8k0(ufvLs+UtU%=W(;KIqsEq18u_PlxST%PWS{16=>tZq6LMp-e)L{1=j|J-G8TSN zT;-1Z(K{eF|DgCs7wrnKdO6|linKTbAKK*7K>32KAf;cjOid ze!-OX%I91TtwtR}Wj#4CLT6$$hbr?=fE%{C0~l>G{)Gqj`4}SDyP}BR%ZTiTZbgwJ zd&TP+?LCMi&Bh&l0HK++ZsNNL$O=a;3oS%oHn-bFuE;5-`vs&JxiX(}C&p>89IhPd zlO!c_N!Drb$H^fZxzxJ=Vpu-Mm!Y{MS4B7yVFK@jQkcV$t3!+$dJD@`8CcP2SVZiuHsIFI@PdD=Dj`Li+3gsA%?~jUj6){_Y zXq?AidlfycHz&^5C0<2=^%{~CZ)B|0B-9fP^<(54Bi$}(uuR=BE6+uWgS@fPUo!9W znfJIXzkZKH=It$SI8N(VZy$N1@yk&cZ@j!Y@i@yeLEgOhE_(Nsx2Iv^@FvQej9!Uw|H+~U&d_#A-S&ge%?2Ud#=pK%` zytxQn?cEfu!q6f~ig$AlMIcFvcZ)v~NRr~+Dql4IF5-H(Wlb>yGbjEkv$|bgOOoQ< z(fwN{=e+o18?13bu*o2Qy>|*{PNwG^wRf0^`9!OHG z{?x=$PGFFv*zg&N%b6ZXQpiY(5M(&%pypin&>nB!!Ly zlvV6LJG`wK-oa?j#JwChAW8WyG?>(*j0%zz+mGSIBvuF{DO4s&%21XXBq_X2kR+v% zS%W0S)?!A22b+5!NjcY~H$QPH&^slg?|slCNy<6wWss!U3AZ}&9PcCEB;^R?A1dDJCit_72a=Sdi~uAlqnH9nQdj~*l5!&Y(*sEglQbkLcQ8+o zq*wt+QvSrr1dLlECrOHTeuj551c}$UsDdPg9=7>Xwi!rLero(6N#Uwak4Xw7DeN3h zB>DTk?H!vD+66%YR~-)|DeT;WF>EW4q%c>Te+&{62_z{KkqbytC@OTh44Bc40hWL} zGt7xz=yLM;b77K^kHG&J$KZi*n6$uY@+@lrk`%6duutZzat|aawZ;qHz3+2$M8nsk zbp4vpKM{90iUcyAOv9BDK~h^%umE>_u9WYg#z;30)c^yIxKg4QAsIYe|Fl>#nEt@+VzL6G*#-*ec8hcDVGXgtQ!@W)Xt#FOH?T-q+BX|=WbNCIFTc$ z@&U$Cc6lM?QsL`(qw+D1Kc~t?$US>>A>~r}F`Tx%FfS%G;lLqi*z9qI43G|)(bIK$ zoH}z@rwN4&kWMz5-|E1)_(SUa8jX-WsgMEEDNXCZO1TK0fko(+>}iDzkj}!i4jN|? zb@=@`duAa6pz{oBupUlREznWaQsq93iR`&a%B8|*F{3g9TrpJPX$RR0laxz^zcm<@ zYA3>Hpn-?5{SHV{E*1U^VN|w*D~2jfR5>U~xm0+9hN<@!wBI|_sbZZDO)@|_d=Rv4 z1G{EY4GkozVD|DP1Ej;}8LI=Xj&amEp6yqcWPo%U(mEh*p#Ahf{tlXbc#;9qIV-J$ z#yO5UC2X9ABmX=?C)p-4#Yw5PWHu`YXjRbC9*HmtQvSc)}HLEG=B!Z##Xsj zGiBg9j*T1qIdKn4Sc_kcOf!P(WC`2@?_^@P6;O_1Q-wb``TeztDtoYIcNI`B75)}w zRKRueEvjti;JK%Oa;flVDx>lUmO!fHGnM-aD3{8+aGJij1>^k%>in8@`FQ~Yq{9;f zjLvrGMBo{i!@hX5fC19k+t(r2$#ClMc=_xn3K$@rLwy}`oy?)mp3Lj%0tQIucwdKH zC+n!QjAeeIfC19E6i!nubo)6}Ih4t~T0pr}_(PjfL9gFRl`}YNb{0^MUZ2jgy%%h% z5B&&@PUKZah_drPD4<+v@<%$8=37oA2kwDnRLcHq0p(Jug449rb7-j%@Dv@#oWOO$ z5GmEBm2gX0Or*PVENVeH*aGfv&Ddutffa}D1&B~I8muhyVBF@K*)5vxN*9k)q zXC+$+Tqp7##ZrLl#NLpKu3?eEbz*N}MZe{03$7D;n<*N`sRynTduK9SC)uU0CQ8x% zOc`7!f&0yO(xsUQt{ixZUgLZP*9k*Vnp;>naGj{uTpNFZ5YuTNWBN17Iz|E42?Nm9 z)Op|6+2TZArp~=AH@Hq1Af3LLI<_UyX*^=0D1)5_t`mkxX<}Ll-Cs(jMXV#ZP8cGk zm1!l6@I_Rb!tB6x!VoE)npQ&hZ=%v6EH}7L7$T)>(@JQM3#h~wpxNL$VF=n|F*_Js zC$@LYz4ir!`0eovMtO(54z3dhAYI;%BR!>q_IRH;Y%GJ$PhBQ6BRK z*9k+UG%u}$_Slz77__);yGe#fsWq*H_ECk&C&`DrDz$0=0emWpg}oiId7 zccqok9^a$VFFE4Cb;1y|$9ZgMaGeB3_&W$O?SUvSFv?a|16(HzP`bVF`rFruz+LoZ z4s&pwFaSDy2HYD?(;j#fjqnJNqUlru*9k+EP<2pgE|m`Ahy~XPL!iXbcw$hgg-SnX zH-hVgAs}jUm!Zqta?j;6EU!@(9Cy$r$F0bsxD2Ab@ELp*s_c$3vLQ(fMt5}VKFANm zX8}G#Ye;*-7(btmSS{2&~fGc%vu z9aWj%n2h8HMVwF+2^;l{%v&a-dj|)Tz`zK4r7{$1qs2p1q1g zr(5B{0*IgVkFc(^3Z&3LM948x%;Bk4Wo=FCYPc}#cshf8m_YRLXZ^;8>ed<@!p)2z z#+w8u!XeF*0V1J%T)iR*m|urrh8@Z59f=o4+|Y*7NLDC2MPYs~C=AbxM>7cyZlIPynp0-qhGs+mJrr z)toNeMGSigFe+BNslK(krg>GzQ_Jl+u{;WPnlT9B3!gNWs#WQ)1Z`wav{9jU5hJ)?vdzZ5oEGUEb1)Bc*AgTeH$w=(QiU zK4tG^OIm81Tb8X@Qv+khvhrnhjm<}lTsCFSqM3`TM_XJrbCikl)tF~rb7VHI?|2e#&`jFe2lLq7798%}*my*JZTf`k$ruez_2l|hJj&OYsBWZ* z>L;&M_H5hqgyA@bd8M&J;(^lku;q>QD_5?mozhraS8cnI8PNoOHBQX!Pz^I!P!V%b z^oqvyD2cK5wEsI!L1!egYpcH2Ao@Ny2_lmZA(%;edg?G9U1}!m6j%3Q)5g0rj9B)mmYShEw!Dy zylXo!Ge-lbVpo=rs|Yp^&w)<2@Bf({bs)pt4}r#@MTeNP+|!2A>&A@KN#WH;etuTc z>59(e#5c9|kIBX;3HBJziVphC>}OSiON43L>S}9&4QuLKuokby^9M@s ze`?TNUA+RMuVH-?5;jXr`lx#UR)s0p#T4nhglO1f^{sDNiNbaf#h+DU9NZcXs9DpY z)^;xOT>4-eV%aop7?7E@yLxrkcU-M2lj~a-)^2E@&z!h_yFl$l$8#5&!C!|=@8C9y z5!s=rwu3l&XV06mfAwOAceww@-j~2vQQd9NP43O^H7xO7y@`g4vI!wTWKoo`BcLLn zMMYx*VGRTmcB?ERDsHIMA}(mf4RJ$Tu_7v3#kx_@x)c{&>IzEHS8yrc^PKaX$%N9D z_Wk<4`hA(-Z|-xJ=j`Xq%$=EM{`LSqqh>tL?P#7ojNo-GuME=~S3LgdwI>e+`%om1O~$C(o%faOp68DwZo|X8Ft+qj4!w)w!hH z(1Mlv3CfZ8F&Ml+MPF71ipJ;X;R(1^=_EV`_g;SY722qU)Zx|Qeodo6_xmNIJyuQ z^P?(jYq97GySC$HLA!HG@G+AK)itgE-D?H@RpjlApw76Ef!cU?qHi>JLHNSdg((+> zhCVBS@sCkojOR*$Eo^S<@OGu$>h8eMpX$H4Zevr;+sxK&<8l8qu%+Ugt-%fNSO&ew zuYT#N9-e6gwp0%{;R0K#sa;(_D&G9YO<3OQG53?GFK$*BZR|aA@wq=sMWeic+*p60 z>YYyPt=be6%liT;Xb#7j8XVS)$nuB>6A^g?5zXQ~Erxdzb`|y$4iY-;@mca$3C|JE z5iSs3Ep!^>JLF#_TqAr=_^NQL@C)HrLSv^G^~^!1vA(vw5Em>3axi;*0(>ghqPkw~2_2gdK&Y!jpt&2`33}5Z)zRBc#ONAG2u(XbMW+p<(Rj}fqec?{|&-bLStYI;jhX6k?_O*^~-&V-CV(FhMTq=B2__i!A$(Byn(#Ye zAP#I!buVKfLSn?a|!EtbDT zc#N=zkdJs--!p_2!ZE^XVXg2|;gv%37B12+lOKmuyq9V9R?L?h(bcy<&wucvTRpA? zS6{EFcGje+Vr2aC$R9Xo-2`HWxP<0nW|1n=rW^a-=}q*>Kk@x0C1Hj4+nVa91wp zd@#SExVSDvnA=<&*GMqGndm&ON9Kpqm7m{2xLq1Jy&B|4p4(j9d;|pZyEu>^PDg%z zOW}5Dn8$qNckMpCvLdToadf$4@ zwc-KHwhKHI?QiU7Zfmdy>vwaYy*PaP^?MF(T;@&zn5}J_`uVxOAO^a@I~%-G1jZ1K z(}>BB{mwFxpTFIV`B&uo>iQO^wtBq#QNK6#!Sjzs_=42_={1i!s^fm@HNUhSS5L1w zKQrfe@5>%uX-bFPjf-<13Uz$qYp+l0cj29hoDRDh7oNE*JSY*){Vt`rbmz;(g*qOs6s zGHL2V%>2H@pFpKHlVVx)@K}b@o%(Zdoi?)>vZXeYZ(T<3!h(S|lWvqDZKf?T9PNaL zK$~g38PV%dYiKjAHz(Q};{n?_qRZ4Y_l(Mc?* zRNnk(oN0T?TNu!0W}-#WCKy#{GwEipKgm8AoJlX0Jkhy~J~4|8gFhvTw{WP$c z7a`_guuYSp%{&QJGuljk^2_%3S&hx-zmWUSS+lY<*XDHAyF7EEDcjd(va_VkWX9R& z;)lCRNDI${2inX*I5AM0c^|ydF&y#fjp$}Gu3@!jxPmY|JkaJgLoBtKtuVEu%~S$u zGgUEZGp#Qp`d6e4Xfy9+QGcV&yug&48~vK(wVK88XbzkB6pR3~Uin7C2yN!G7+q>J zkKs5zTksd-Jv`cxo%{O(Vkm$H?00ewJfGRocztcAEy&kq+6MUAOk3yf(c_ub=0;sj z+S2G9?2lI(4KQ9`n`yJ^6RqZ;zo|M8j?%6@w3$26k`!n&pJFB7ZcJ0>)Mj2l@_RYw zn--0T&I3Z5$rVg(CY2n}X4+~{n@Jaw=9wS%L*8ZlVK~NRC|5b74r+;%R-4J*iH%^s z&}Q14yjVL_o!ZQmrU~KL$Bc(I)A}=FUD;r0Gp#=-HiJ_Q+Dw~1H4!FRw}~%_eap^=Hq*v;jXlruq0P)j^J&1o69*RBOnWFPjlEAlw3(LQ zCsx4p&}Q2B0kJBkhc?q{KL^K-WH&;aY57B9{K6Qund}^DGh5IPZRR>tpAj*xD{3>j zl#Dj>N)`ZZCfA73W=>}Sw3(ER8ExhbSRmA9R-$O5&0NAfpv|OQOa|<^6zm|;K7C-2 zjF*+eAYF$#rG;Mvp=oFjLO4MKR0g^6q?XF&$7x$fLV9YJj24r#&@5(YGeM7;WYXFkwV9NG8*S$E$e7y9Q6>P|OzKCd&14OXHghqT7POhn z!e}$+vP@_*Z2+{Hlo3&zX#=3mT+UWNn`r}}%{-n-pv|-a&}PzjBej{floz1Qyc*fF zR;Ev(&7_}|GJa??>92Kur_Hq=b%mZlT%2}vH6S;=R=?05i&E<-?IGD9 zg+|XI$7HxD*E&j>7gQhu0=HALz<>-cI&m-%N-zLYzrH z2c0vLoIG~UCaqd#~CilZbw1?eL_kVDd)!-E=mDzMEd=g15ff7oLlqbj1Y$()AakVn4Ed!EQ~Wk zoJyaA{u@rtiRfs^F&QDwB|ZoJHXrd>bD$Ji_PYNaGk7-C4068YZ zMY+pSUiKo_k-}RbkYh4jlo#PNV?jCQT5@h=TV6~sLL7c{)Nm-re3zWBSm8|xMu?M# zyC8-`Ic6B1WSE@S5{wY1o8wT9*@~PmITl+Ij1cEc$Dtf^FgYVx=dB4wh%*;X(|;KD zDWo)Kl|M-^T$EcK1*3iqDKofgwkH^lQ7>ZMb_ToZ6_=pei#*K)FLLmAB^a(ezj2f= zyvRqSZ03ykA;EA_5{*3D3zTDK!BfD)H079#5y@yac}jT)hhL-Fq$HklOldYb0gPso zB+4<3X7eF75^_wd*(~74qA16-{ZeoV>jF8ZJ**bI&I23dn1Q40!>(?WW8TiXtz+*) zj>#CDe4BFqK#pm>=E(9{FwL7x^E37%>8h+1_a!h%7Xr>&~o{$R8VU;1rw5PCw zJ6S2nG3_!bC}9gA$Fyt6mt)$Khp{S8IcDH|GYfaz>~W)q7a0dn!F?Pg$T1m%+AL?~ zAjedzd2C#T7&BM)VEHpiA0~kulMxsYayB~7953<&Ig40t$T1lq4wad%n7rgY1^da^tsIlFEsY%0@QN^!kYmz41Dt8t5zrvV#LXEawv5!t zA!9)~Wmj}qgB%n8hcI0zyCfcN-C-i<=|7QUlJd85OdJo)(-s&Z#*x=6#17-cbNFvg z8+zVrgB{XK7nBbN6EZ`$xs|dn|8*cYh%6^hE1YWHGQ|_9!b-hiIfVwi2S`GWRsnNnnKFr}3MOwhTE(Mm67H#Ng3IGKrMh(r8MX+|9#!%zo5624Ob&BX^>A^$!1Vh(jcD<>L#f9rKkrsOs%6q zF!_@=CL5gX4T4Fd#%mBv`U?6VjbL(rKMY_l@)|UixQ>#pu0d1TpsB2dfU-eT`IFUD z#@(F=Aa70#h=v!02Et}5ww|5v^CPp>iU&S{&1xx2{E)gEEe!fGYbn{+|5!`8x9L`U zo1spwjC&5qgKhsYXek%69+)+k3$GX6ELKil^r$-7kd8g?9_r2>BSA_5MIeTPO7MoqS@6u(xoiuv|DrI7fJe@J8V( zp|j)qd->lGIy!|mS#B#~7hyl)DZ&N9tAsZTe5HS^2Db2#F`!ePP+p|j&UU;e9wzY?w%t`}|+z9;;PFa-}( zSWaUh-?5;-qp+87sIWpX#Pfw$ z2>C`h!}-B{;#a~_+|Z`~B;naYr=_ft-)Si?l>buURl=phJA{1Yo%ud5+$lT=PoNpz zO*m3GM|i7{Z`qOeneae7~m+uC@%osA#EXOP!(EZ;nQ0v5|(B0NUeLwJht zG~wC8(Lz3dWq#)hahSyWkb1<1aBhspX~5urNE3-`oq&-R9zY zAt0FFROI(D&X3HGb#eI(h1;cp(>oP}{n138hsnN(3ADL9&W1l&?nwNPnTs%%%Wzk2 zE!-{*oL)LKhlO-#b8*%12lLy4{J7qjA5KGlehcAtY2fr)B0uun=HlifAei6hf&6fK z@$*{>w@br3x*$JZSGvu`EkQsqzwePB$BFgBX~EBL1>8)-`M~X!1kUd)P#fd8-zRju z=B@Wn6L|x8oI`G7KXY4yJy^dmCZOxTCWv$6@f_Tk%ToYm+kpInbK13+80ZG?d+(wut2k+Z>q)k||>nGrdIIb@`Nj3Q(TGrW$)6*lRM9Kwf#42k6k zxFfeS;BFKPiRDCQpAr5J%Oaf5Vv`5|5kYBT{_jlZhdn~!Yfv_1l`J;Qzk!fd(w(sa zv6NL_1CNnawnk*u2WUTJmER&T>rvzgStY~0Y<5{UxN^vstg;;bXeH_iStVB$v=Y%A z^de-H#t=7TmEkbz23aMOhK*+PzQpfArL2QWq^xo!!lEa!>~5Jh11SFx23e)`hNFD59I{I5&4~UCZGo)PdUK+GLE|B- zwBFq4tE}2_@-~eYFl`Tca^pI6r{{rZuW+8_5DeR%v~{$xE{;o99Gnd;zjb>-9}u)|irglb1GaJj#Ot zWR>itfXPeqZyK^nT5f`@aw`U#CNC*HfUGi&YZ$W1Y!>u{#S@nsQbI{+^${QTL98H0&@;$QYziA z(#k5?JHE+Fo0Avo%g%tT@;cLmI+K^ypAq99Rmv)@KPOhfsRmi4O`jX%S&y>HO=t~e zmG`iskX73F;@Dp?n<%TK^*NfnY|Qc?tF-Z5W1rFwS>?ATzI%)pV3bwbLrH1uCHf(& zwERA?3@%{EDsB9L7;lhJR!JKOG>iKkS@l6rG?jm&@{B2A;>U5Wsn=sj|_?FIBn}lNS}iMbM)sdG>aLB53bAp z&X4sxgmVwF$`!zPUo^nTDz5<}W{%yERnmhs9=nk}1X-o+!Eo$TwjZ)e%?OmphNp#@ zef${=kC9cr&8#vxSs<&Vhgn?#q^#2V)2z}ECND>$b}7wa@{*42AgS6`R>^xtF@9`- zvPz!KnAJV(bjT|0IEG_;I4>ZpG&h(as|>N$kX7SUG6O;tz4`m&XfRoVqN&dN9;tF-<)S*7*QjJ0EVkX7>klOran5)EaQ&!0=jI44Z%Y>}b20&JM2Nx4$l{Nsf%7@ts$SQ3BWR)dM0$HUE zfUNRno`oQ*w53p1IS<*hR;EuOtE8WmGJeP^>925pC#$?10WtGM0>~=qVV`$mpFvi6 zqwzyl$%7(2CM(D)IXGNM@>^NuCIlpS)S;}BgPX`@UqM#MQf>L~xkQjv9)eOJt7K4q zh=&0)yD`DG!wqpIs+%9;;&W?(OE@i@hTm+?!6GjQvGD<PKArORya+I}|N&b%eVMdA6|P@rO<-Y5Ag<_z?d3>T%`QTBL| zlSw%jB|uNfa8WLV)7BS~j;ZAQ5t9>oN=Artm(M|)mXecA&awH75a&go13|}Ha$ZO6 zp{HboI6Hg}lp*huL-9TIl#CE34RrXa9|fGeVpW zJ_o|ELU@wx**6p7j1cD(pM%cnLryw7XL6ho;9QTAXTs_FZyYJJ**P_FhKq8&qoDsT zB}L{f87|5?M?wGHOG-!PGCR(2QMNh?`tJ{<{EU?I;|v!if}50n|9wTyT+XfeaYl&K z+Hu%_xF&=ylbnTdMu>BQ&q4onC#NSm5qe5Sh;xq5LI0gi&Pw+26>&z0^9!GY{#!uK zcpMs_r({H(c}u%glb^Fa%ku52O!5Pu&{Nt4nEagO|4M5uIU7?PdP=*hl4Ec*hn~`| zpX8m)S&SO* z4$cO0K4OJ8B^V*j4~~Ar?2BsPgz3F zNY;64f)V13gVXdMhJ6Gny_n4>35JVusiR=j&n0C%SIzbW!!hd3SpS{Du3GC7RC|$C zOt6N7zbnCT<@t`IeBni2CgmBk1gP!^e!VCCdih4@Mh}6m_;qV)S zr+{Dhq@I#7BAwt!)KhjRiJuapo{}**NA6~~Ku>A=rQqkR3-pxsuv+jX4{Xp=29C1) zjHNvy9fortb9{>{0eVWtAjb^OALuEq*Bn_k2h*%)n&a7z&{Hx7X`12;O+BT&e4Iu- zr9B}PEM}FVr?e}m;0aa=dP=)YeDjue4f%RXd-5nSVrJ+m1LqrlIMcSEhZh+FPr)({ z67-aeL2a&L<)Eijt9fi(f*3Pb_F(xlNqZ)No{|yhYjV~&&KxgtCpmYq-q2GrLY%kY zv}I$^ULc8Qdg>_|BNE@Nup|us4w8o9Du{YY#)#C?Ct-#k1W!Rr76&~gV?-M4lQ8_p zkd$D(p{HbwNay$@^vBsGt>cjgdP>HiKRR%Lp{KN?W6rfJ5aaq|36s#8IQ5i_K)yU5 zZ*Uy+#~N}DW46#!GD4hfaQgkRg(QB4nR-gbh}5{LBcVS+@c4R4#)#C#C!s%Dkn}pM z1U)5VL>lRn&>w?H+QzYlo{}*l&GSjE{ zlH=IV&{Hx(`Mw_DY#^tC(;RwAMu5X>z#rf={ee3ikLL zVJo1gWDH20js1h9&Lr`}IMh=zhUP6_0xQ%%JH(4rZkJ(CInOh4$^i#36m2lu5oKs` zXrKu@f*%|T4a{SF3mA+F4a}#r2*g&{Tk?Z#p+Pyf!#x4}XzVRu{Bp2Kd@X!S7y{Mh z;9RC#1>Z`BAg2?|Hvrbd_XPHq&!E1c6HU4|;pd%G1pG5SrYvQm!r}UsG9xWuun~V9 z4)kc+5&sODc&X9u=-mwQA~fKLi+5R$gn>p{h|H4I(b#Lm)qE&)d=rM}82gVn;vOKw zlj7qGY0mQF@lCp-g$J@g+$Qr4R*DEa*L4;hNo?$^EX8P&=kfbAO=+ys7Md3^ZTNpu zkD2wan8)-@VFt`&(!Qq|C54&!!XL~9ET_e#L{4%Tu}uBCv~``1GK4v6ScO0`iHBp) z@xZ(KB=4KzZ(8RsZ;Oy(>|_AkhSW#HeIj<4&72P4E+@-N@rvup^7xd1gcPq9zi#8@ zi4CoBK|ri|Nl6!<6bLr8V0o+wQ`u7LYGt0on*?qNTTUK!1`VP(Bv? zQCZsD;K|fxlY=5@#@6Nuz`O`P^Ou^|!30Ipl8PFc7das9z(^LtkK}J^TKh<*Npyx7 zD`1iniPKVNg(8g)k3`zEk0d%oS{6kb7x6byMBON&r*v-;$w>Zu&FuDSpB1w z-2Jnuxu5brd-`@JUY*@WXXwoslY<4{Q4?XgEqIhNM)F{$5cYbjD{6g{Z@ub~tR2Fi zt^v+5GATV~JS<5X`;x|5q%#iN(^$Q0u)}GGnP)57;cQTf{y(P_4ZH#9`9>m*F-dpa zkkNDy|Hiy!gZa${spwC}{ALbrNCa(f((g9julT8GL+83m`?pYSz>irQ%KrU_+E9C` zQs2%d!s@i4^uVqoc0Q-TJ@bFd&L;1rQKQmR*iSfIc$#pmuu3>vI8SKmfqbr%|5~Bb zh~6PT-xFtf&j_Cvz9oEL_=WI0VI$l$WV!-jZ{bj3g>bTv@Bfg0g>aeh4&l?n&BFJD z#>NQJHODYGJ}zu2>@4gn94=feTrPY}_=50H!cT>}g&BCJ z$Z~oKPZpL7&k@cOUM0Lm_<-<9;U9!sg*${HOmvphNZ3r+LD*AxvanqE&$OY&SO@Yw z1&=|P|0rRt@B-n@LfR!EZ=LWZ;cj6jZhtfWU}0-vH{tQZ(}d%NvxJujuM_@vwV{*n z%!>6nPq;?-J0ZW%&v;s^ARZ@l+R)+hJ8kGB`D=xk$&aG0<{c#d$c@HXK?!Z(B;3%?PjHMaTY2@e-`67~{~6;2l} z6Rs1!FU-I>j`eIO94ee4Tqs;Ad`Y-d7{|jMrax9#A-qUxb&i{-ymDgGg+En&6H(V;2ttEar zuW+ehwi2NO$16qv-5fh^Oc`C}@ZD|_b8)@k59arCt&rcwee}x`#0B$Pfc)IJ;WXvvw*qd~f%AdeE<8Bz z#R9c4j{AK=$2+>s{%KS12d@xm-Nt_A#{V3_`dt=iFHR4B{hosxb9oBDY#WhZa89#s z+=zj0@WMx8&LS{|aGb78ez`!F>DC6EULVXq9&g>|^1~^!9`6R!?+r%+Iv(##@mcFR zojUBNHnmH!RjZzzHK*_3ej)Sbh0QpG_lI1*4B?nztEWxP-Qf)z@VK|5u=lb9a*n_C zv-!i?eKIBWjFgjiB}+pcpW5N|gRAiN@4}aS7)$#ua+O!O{=3xB0PnGnr=(8l?@^@T zWn+@sz6yti<2;bl0yATun$l33`MyUeY-8n1=K~j;9M?op! z2&F-(jd+3R+wOdTd71B|jE!GORz{?pIqz-9^LfP8v*X#DdC86^i)OMFUGf6k`ojR=OKB-#Vr4e@C)qEcwnGZj4#@hOw0Zer&5 zC3b>J@##u(LKzn_l=0<7Q0pe5Z^=*1uZ#;S~3o2D?esmZ*4&qZATNn_Z(!^!- zNQ^4Pr*yN|-(VjM&ZO6fPnRwk{7W91PK;!kr zr?wzpd}gV-4mpRPAesI%#5{TZ<#Y%s*9)}Ir*kW&rfQ=7idrYDyU z#iyItBM_h3_~IBOhDLna2+gDTG|uuMKDF^(W1r9u@hL5425oxULrI-YPs{HUJBAAw z;!_(xAhw9MBAW-;UN!F4&s`LUjz zP0tt6s`vynz=%)Rf)O*v5{OUf!5WV}#U6tA)b?OFM*RWBruh?GOq-r9S!;+-d77a3bSP>^@u_XafLIBu2Jz{&CcirI=?2s45wV$UCB&z8 z!HtW(!}1_Lwf;KssrAo{QH@CP=|q&D3MdFk{0Gd&ku3&xwX*K zg!7hUHs|2a;4pawYK7iUCItAlXXVddOzo4>hP87_yNe(=e8qOF~WFMTl?UlV2E!e1V_r zrx4s2HE6~@q#!i}k2CPe2uKLN2k|I4P3sQxB1e!SK`O&Vp>a|}f$m`dDKhZMa8b^6 zlsR5xA}Q3sLy*dFQEqaSJ&+WU!h5t3q%vHT^>EtyLId&uIhp8K2vQj#&Yyh_+C<}W z&cG)l#K}VU+kBt^*-g&t=mZE-86gfo2V*&qk`%y`^e_exq%uOBp*{zlLrtMG@W}{p z-a-qe!D%`N>aj{vHegObkjijTcr9iq?Y+pwq{zT0!$o=2QOdjsuYr=K?7vgv3>W2X zM|s?fyhO?{QcjOET$B{dbkimZQfZ|-*_>@UE6xaUcp+%p4e?1HJjpXT4i#}mh{Nj{ z%YmS>8#(jYe`Df|5NEQ_fwJyQa`+h*2vQj#&ec8#oimS|7VMnKaYlgiJWBpGoUZ?F zBSi*287|7}j)MN%K#B}}GF+7J90mRN87cj-t{_NdxG0C>Hl-;D{TGGX8Te$lD81nH z`>z8z4`Pu)kje;g#yAcIsi%;`XI2oTGD4h1J_r3bi<~hS3gWKlFP9qAV{^V zDtRsrp%A3n_2UeD+Le+#hjU}KTN6B{RN~f(=|%`rPk}p0!8Zh{3`ey|x!6%KUNcE) z!!FFDG~I0TZydnOR1GF+6uz-h*dg4C_#{DEzGF~JCN z4#F)F!=WHG0#7oBW3eg02yu>f912oflatRzy_R5vIA=Ky1*s>H6J=Rj5{wXMzT;4k zdJZ`fq%uOB+u$_)hhhH(DQ7X8PZA6lWrL$&)Yp)5C0EV%1j8}vG@uMYYM`rjy9Cv+ zUCRWrDsj}T^h97*> zoiy-iYyVFd7MUF&4>MVE)K4v2!NM#Jpo4Yxb5Tx3EDY%7ofgsf$Rtx@% z2Q~;&14r2{E=L;pe4aUO;YxrYl`+WC8Thnbb7aZIO)*ndrrEi=^N-RvCg+yMhXyVWl8Qwadg8q}ny)3sUXLqo9a6Ly#Ic-`wQariT}~ z9G(JWg%yHS#-KJ2vvLrms?|I;{sA#&(Dq>YGf5vFY9L5u1V)Vo~IbP&La@Mil z5Twd>CppG;Cr6go0hw4w1t}af2vTLclO$ui(~vOy#&)L@q{?2njtFXt{fIdz00ur8*1||mkILSF@Jj6E*jqw!+S$amGzLBm zPX<2ez6hKPu_KdzCMd11B85fA?Cj&R&7I2zL1~>u&_kq}g@~5w*hJ7kDE>rI!piW1 z6043iTH78ul;0j24y8tq%cdx|F1y28ftQaflS1RbA*q?s+v4DvR2D|+X|rfv6zY-V zRJYX1HVQQkm8ShGg3`Ukqb*U2FETX~#Xc>gAx}I&@VaA%yD5?Ll;QrChUMvRvdtMr zK)N?&F18e27MkZW5Q+LcIM5s3q1a*Ylh6YDUIst$e9sgYNQg&PD4iQ~wHs>`+=BjF zKyJ`_{^Yct?lIesO6%ECQqR05(sdR`@{D@3G!iq|9Ma5#BGG(n@-s8FQJo>s)-VJb zIWkh%JkqXxq;gMhP6rdl>;{LISHWhKSkI(t&Yl;JD4#<*pm zpUNl}3TlLmr8A0ID{E>dS9<~K$%r(e&0-RZcFmVZDzY zc}i_%P3_20Rppb)Yl=IJ98+C0vD3)jCk#7&SlLk)NA?*uWaN;V>Is#jWb8BWgt%Vi zPc8Ivb<53id0OotetP zu#QJ{w$poZ<;zj9^^8%qT3GuK?P$gCJ%Y%!-iTULh8X6+(k_!4 zYf9E?BT+V;LCiPXFM*V7zR{taVPPFXQ@+zw(cuISgoZu0;hEq4v}}Wx`t1q(E;@e9`cL-z-_?KCokr{Q zp9-tffAZ+=d8OF@JNnN~Opk|{U4{LGgM_CE&k|M%&k@cME)ZTVyiRzBaFvknVza#G zgs%#>3cnD3B}~IzYVw_JP~Lr}|8U{a!hXUkq4{(@c$domOW{32Jg7AJJSE&H+$Q{9 zn2q~)EU$-fu<#7w1mP^<#ll|-Zx{Yr$Ok3N?-k*D!X3g8o_{dDk&xeWroU8plJG3y zB;gIhyM$|m{JEd4~ww2#*#H6rL`eAe=2+B)nd@O8A)YCE+=E zYQl2P7hWdh=j$21O8A`cHQ`6XZ-hxaG$OyFkY7Khf2goRSR;`_ocg>gKDVE8e@vxIyS&hQmNeubI-&xN@-+0kDj93kX0Wrp7* zd{X#!l6Qb6q>v#LT4*a0J=GL+{o)=T=oa2db72~FHR3$ zsquN<>qpxB`J|Q{?kuk#c9%Dt-c0NVlBCVW^@2Z`-@C|<8Ia1lxcoR5T^cyOi$K^P z8>07O@-JfoZ7z?q;jdRNE`}E)jO8-im0Jt9O9Q7j;9$=yq(hsFtA;B-M;A>1wvoZdL(N1oeU+UHJK}fSYMJAGj6ZpfQ#OYGWMt`-G0Sp!NRgG-=DTtMVeSpSi8U9<1NeKznhx z_Urc?+?dN#0A?#`vwu3xap0Ar;{Qyic_-#yk;@#&wsONM&0j+3SD7lorO&}CXLw15~B=rXN0H%dVYbeY!c z>oTo39-YL3N)?+QrIsJMOdAVb=3MkzMksw?20x}0<@=$~WttBwq1TtN4+dw_OBGL) z`eEoY*)aH1qFd=dS^fnORxLsdtuL4+LzkIA)r>Ba3M<>+XEmmqWBPN}tSrq|#n)vT zyJj#7%8I2|9Lmm;E|VE&pNk*vDgicN;ejsmP}H2d%=_Stj^T(;Z$vi>;`{5+WvU>| zV;+2cU1lpxE$K3qK)OuvrOULwjObrkuSYU_10d3h@|#9~tINE=l$;y=n&h?VHm$GA zWG_*dNlgD;!Lt}$>N1Vo_Su5J81LcH2o569WyVkdje_pv9C$vnqw)H>Ok0qz%d`#f zb(yx@?&dW$=rX&Sw58G6?2lI(na?*h_jQ>zt3J_Q9P~F;XJ41O)3kR;l>dF9%jDa~ z)McJZ@_RYwn--0T(sWN1~ZK_68FkRN z7*4CpWbedAFyD$4RmzLCW3NM(xze<#PM2x@8L@2k9dw!2pA(zGsRmu9?T|WMrul*s zbeWg4qR?g9_~O{xTn8`;x*M&fF7sPAMHJb!oW+jSFZT@Z~HkNrnmr1FZjDm70*g^Un$peFA zysR7si3X3;!Y_i*G(@>RCuo4mAUB@742kJDZR~xvG zMyuk~cNtyg3NT{k*bQAKJy_$h^Vwt2W!fGL$0*jPE>klCC9>gZVP;>a%lv{_(U=`| zne;HL=|CCZ1}(*$*yB`g}cOxub9F@AxIy39o;zag;)faw>f9K!dKQ=re~ojU3=?SdN@TgLLB z%e4L}v0KT%)cI$|qHGFunSA+~NA%e9BtVxr$^<}{N%^%$ zStfLuHUPTJwOm}#W!eDfGHJ4ux=b4YUFPvj0$rvJfG%@3&qB~;+EQMCF7s++&sv#2 zg)WnRR?7IH%cQ^7`JFEFCItApOnTVo{8|}xnfDq$beTLT(qpoME|Y`9g(Sb#WxkJq z1dlq@WpZ#6I}k!$CQG&D?{tZv%lsB216?MA@v(HQ7dlP=ak$ zo7tR$J>WGJ2j6~^>VlrHm8{xF|g&O2Ca*U>^TRtPidD7>gP4|;ihK3!$rB)QOdl?LQ;~f%&BpPi}Hx0JdVq7 zQjQ|!^f<#sc?(X{CQ311ASZ&U1SuvX#0g=U*>*!L@g+HNjzdM95#rFUx#d7g*c6`R z73{w;aYl%9yw8EAtSdQvFb5&UWP~`Ad=5HiBsp7g0D%;f5#aDciHqTM{Wq7CE3pV* z86qDhi{LxX+f6tI2DJH{3+3hIkzfVZ1VnOG}87@izZesfVmjh4o z7o1!3wLH`XWrx`jLQcOmObBWJE|IH-lH|*mp;*1dI z9-o8$yMdgOIi6R?839pVA1>8vwN#xH)2_;-F;94t7GRQ-0a8r6){>`Vxl< zW3p1~$4N2mN=dfm+*s|_1V0W`in}LfydcFahC4ZfnLUzVII2y`C`Z9~4I`y9TedF2 za8VXIN*6COofJti87|6Qj`Fe>xsDXx7J(F#;i9|G3D*dT0n|v7fHbc zRvA)EdkQPKla+!L)1GDuO4x!nA+4c;GdRvgAuW`GT;>cZX5f4?3lDMZF|~&m83#|n zeLQYJipdz%riPV+6jQC{v2hh*%v{-n<X)YEp{6?=?#x}w>sPvj78NH?s3v(J|-RwKxR0{#XUKFU4d8 z+RF3syN-kY*hr3(VlqM;sxtll_==?Wc`kqyQ+iEiWb~S@Ka5@zV{D|D(rc1r^qQ_e zj9$}8F&U%cj9%0AhtX@k#Ic4HQ+iG2Wb~S@Ka5^;DQ6s{m{zY@a4I_*Qp~^%e*tBf z{y-P5h1-{6GD3xa8Q{E2PA^V#NHG}!4v%zHWt#rL)n_COPeF(zNHL|?WCe|0lNBVX zHAzvn0#Z!rH94wAujxoeuX#0x5mHR6*K8hYgA6Fe}r-D<19SIwxn7BFPTLG1nG8U9lc14H9 zeM_QZ94rf@^8WuI#XKC-g_28RSL+TFIZx|JG2!QiRf&ftLkMx>9EM+i!x}SUOXx0J zz*&NQFWn{On8#uNC%Q|wOu#f-(Ek`Nyc=|vKTX{w9-I9*b(fKJ$Sj)_Mk3TzHuH^Z zQiPe_9YKftI?O17A{`^e`H{>*L^N*#yPAq-7JGX3tle z7}<^a@hxx}`DuCWs5<#cS#7`L2lw^LW{j@&#?+LLn!2}WWp71agC=t?O=g3o%?8zF zgX$6r{4q6^l~v=RRVUj4P;M(>7hyl)DZ&N9tAsZTe`AtpwPs5`SB42YQP8ISMAo^)ofcStAPfv~iW#K!*EZl4+ z?+{@d;nBi@!qbI(l1V<_-Xbm%E)%X4J}TsU%H+Kz+%DWBG&Y71-wcmu$m=LPUwDP^ zIUzr$Pu^F;Qaoy)|0LnrLZ`PhFUBL@=`Al*{H4OHgiD2d>yr6BB79!BQ+N=bP&2-p zaHMdK@KzyT3?T0_;ej}z(cejUs&JO@1|jXGkoUeY9dDG-f28mvVXg35;UmH=!ac&~ zNXzv7g%gEW3Lg|cDSTP@mhdy-Zecp!bYOmY!sfz$!tuh(g!c(I3%?O2@U8&!=^-2? zTqwLt_^|Lz;Sa)QcF|g?|+8ufFmoJTYeZ>xF+7?ytV`UOW|I`c1 zmkMtX-a-Wb9^o2=uNA(k@OS0^K#0?#$sdPZgP6_+F?>(T~ zJXLt6uv|D*I8%tjB$P0CB~gBWDaY04|GvFTqoc%yPlJwxF<|e$=sjjPoP&V_jT+oP#b6oZbWw_D4r~6(;*dOrXu>aW?$Hau;{9b!52=cjeZ? z?b5*M#rIQ3nTrnO{AYeR4f**kggcmD*ZtH{76$Ue>BY})>0bF!=lLYA6W!*@T7rOJ zdyA1D$BFgBX~EBL1>8)-`M@m`2MM0{+{QTW_X!DC6E-W1HgB099W z{BY{3#~Xk`|B;Ro)_3dcC?S@#b}j91hvMSSojVs6b|~p~6ad?P*t_g(DpgNM`Odax zvkSMk%=&t}H@g`4>+Mfu?bx3C?GM|Zm>qsKwtex@p<~kVyKDPLvzKp+fipI%aC>^z z_lRfg^{XHJ+M9F8Cd(N+`?P#Aq65D{ekq?_kec$@yp(IUd9ycd^Crwdn!@cZvc_(| zXm*$FbF-%OFW%liE7Z(u{^yS_*q!9t4}Dm}C?=Kd`*4WD!JMDtskrT?`f13#1;j!RCetACPbMugGJiUF!9z;Z!VC_MENjJ)n{L+>f zj_yJ=A-}ZVjOba$+thk*SXa_Op>+QlgZ7Ieu84X&cJ!jjo~mawWo| zC$a2qnKlD2dJV$TkCrzaJ(S+(QjZ5l0L+8*-8 zqa#>Qsl55oET-)#FXWd~(JMxNxr?<*!>B@jNjH0)iVVmv={538zUL45B^zesmweM6 z@=NQd{BjmzGSD@q$&gj(m$uyQ z(eBJ@bEB3fZE18F`{R{HU5wY4U)rqtL`yj6Z))WYj$V$Yr2i@FJ#-n(VqVP2_I6{c z%qhPdK=OMzlT3?zvzT1Llwa~YJ&<48YEXVj7nA0hANE5YzxkENaEwb&u5v~lbO=&f z`6YYDH;ZX=@~oLk$Sx%MAE+r$s4tKz`X6IT`uom248^m%~xCkzbz1JRrY3)G&-$ zOfCgGNHjnf7$oCma~7J# zjKc@lWq;?#dLF{LcUb6<6~K63G{DF&uK^=wj@^)7(t|Y~>%!(ierbC!9HVTD@=MJK zl*opsg_(W)84OP}y+&G-_weV$!i4BvsqW zFM01Mb~EP@WElhwi5D7yWqyfe#`P8zqI~3vzXRDGsgKw`DHJZYvh-Y zBV)=hhnfJ$FEf|}{LYV(^zu?1XOkY6$jBfp%;G9kaT0gzwb!Nmmmr44}mauHhr z`K1kj{IY~eAiuN$kY85uPzU*?Ers&SdB~o%GJOj9CH<_F@k4$|e}(fq`Q_yZh~3FP zy&)w*5Bt0m`wa5S8;u|GOCA*IFgI>I_}p5cI4v!lhTm+?!6G z`-{3uUic;7LT6?jkzfSgx#tJrc40RyIn0ZEOo~ikGF+4d>TW1_y+0f7Bp)PXwaaI? zC_H}~3e*loq!^h>hkS;MQtl{wyvWICjy=LYzE|oUIQ!Ck#*W zMD%mk@%fAZ=N`16E1ag~5J|NnWg3PRx=V(Oa)zU{_acKx`2|N|Xq@4qobM=QUSu*U z2e2}y#u+ZkEspZI7rBa*LQ+nTGh7s!^)>aKgZ_Jn9GVw~?vfGWP_1s;1o_14mZBV{%_rzXyDQLc9s^xvhV(2Q2r^f<#sS?4I|zk5mP$XsT}87|6JM?wGn zfs~(-a(aaubLb(gp%gnpBpg>goRbAr!7|8*y)CprQMu_tZpM(BeKu&iY8lbymM4bstyHt~(vpvhSDwF(JC`@45 z1(^Jt<^M`+Ejb%g9J))ps*)W!CM&gml6Nwfd$m%Myt;tyQfq?8lvcRgV#W))%Q)Q0 zUox{t5)4PRNg3oQ7_VbUX~UMSOE6rN$&S*+i=0Kud7L~?B^WNsRgUtq7nw&&6XvoZ z!EjN24W}6|>MmE1b1~cUVuBIkyx};HgR_C0k67VN2}X$XgX5&*c=0(o{3IrHmy8gn zS+2^W?lKpi8EeS@5)7NpRyDTARBMrHwV>Rk7?Fp%1B&!VFrCmV<*RWF1UE0%(ZvxYRb1 zT_^=c^bFl);C#c6Y}yv|@FGLtDOkoqg6@(rsLg0r4!TRVn#aZ^h%s|z50*cZv}Y3N zE*XKoCTES~%<&?3k~59u0NJA$$cDkn80KN^5yw>gX5q-){t`;vxNyvMu@WwPQO34ki<_mQ+LT2 zks3F3B=koJo&ro-qq}5`NL_pq`lAI&ud_<0hT@D7X{1j=e+(k&363>%my8izXEH6sbSOU5XpB%Xfwq(<-*@a8jhmy7|4v$21W)S0C7IE>I;GKMBF z&jKsdKRd*WRBlVKr<~^*+2w!(7>YKS?TEI>KQz#U9l;M1g$Cv^zQy>-aOTrl1Y#@f zE%{-$(4d^#;hunfH1-xSkU7{Sz7{?f(*lMv2j?=~D)?411Ua2xz7?<@z9+D^zB6>>qCXt-9P*F-I&To8?V+>?*vQS8amHV(P z^>@r=HK;~=S67ZH`%zf+{GU;c21}tn#hMQ*n>wj%T=le?dZrMKaa0%-HTD}vRZqhM z=P^~)<@zrRL=w%%{Gn+YCt(B@e~^-%%H`hou!hlw36B&7M*Hr zjn-Sq=H>KyqhsbQJG*jHWzE>i$)je~i)QNJp}`5u0zxw#6NXlf8b8J44->X_>}a^t zs7CiP*%_QX4JJA#jhQm-*fCS4m$a*$(r$Ez&V}tJnf1}Gykh*Z5L}K%KzYrmamQkn zOz%?JZqkusrWCdtJ9Y!mfDmZ2sal77ODb?s2 zoxM~TP_45{JgPw~`hP<#I!1P-|6`Uq153FS0 zp1pLRfe}Dq_%)XfWut4W%f{iXZ|vBb!plZYpIR|(jOUkOjzocJUhkCn-;|b49$#Gn zJLqM#EDfyrzXb!r-i|%N z*i_uQ32v#nlj6cs>%G0p`zB%Y-m{D6Jr~@w_b&DW>h8fX=*O%RW&i#|ov1xz)z^vg z80hOn>A|at*!ipicji3&8#g*&>QC^r$LLUS2ihQBG51n1z()}Al-Jzr0`F+W_Z0RM z4i}y#94o96&KAxSatv7Rl|tTsrr+sB?~s3u@EPIr!ncI)3%?M4Cv1eN!u$$^y@f-C z6~f6vz5_)56~bl0JA_XQHw)hr8ha#2*Btlhn7*U1r*MdnFQ_nnvXIYm>Ay^Pz3^_~ zBfMO#W@cEyB-)nOG8xj|*E0I}7^? zhYJ@AmkS>gz99UQ@KfP#VFsQnvYcMRlZEBNbAKNl`*@AeS(CI{n%kOleljN@z z&JxZQUMajq_@MAl!oLce;Ym8n>mwX1yi|CfaI^3mVFJf8Q%_;JaDng+;qyXTg&@BP zj(x-~!ZU>D3vUrVE&NEBjWkTxUN}rRLwLRLF5$z%-w8Jhw+g=y{vgc8TNli~NO-bv zs_>V>M}_YQQ}NCM)3p>15>6IgC0s6CFZ@uLi4%n>S2#>qAv{MoS9qK7A>kXskA>d| z({N&DzInpKg`I@Ggky!%h0BENgzpP8aE@bs?Sw;xGlUC;D}^r!cM9W8ZTe${6~c>z z*9w0td|Q}`6DZ4VB|JfRrf@tF$EHcbIYi9u3xpRFk$#EL*yTjLv&;FQ!qC zits(5v73hUU&+5q_yZB;WE^D6&k^GAZ0d)@h(QdyK{U@`k+7rCTo0f<$H_lLI9xbE zI9WJNI7>KJxIk#G1CZY``Bw?=7p@mRBYac%w(!rwPlY&~L+E3lA+q1O5nVg~GdfjX zYc=RpZEy2|tKC`xIInQ2VYU*X1IH^y0NorrZsaX7F8jl=e?ROlZ#caT*c+3i&BgVCKbYUe$d9(%NM&7Iena7QY2ftU1feai&)nwXMkBzv z8JC8O>Tew>5O+4*!E$d#gEu0KDC6E-Vn?`9&g>|^1~^!9`8=n z?+r%+Iv#I@)lRG6ea8LMsdntpWq)<58_@=A5!>EY_?~vmYxl{QJRg0ngwt+Mr3H`7w*QB{H-WFJy1vKXeM8=TNgfFhcu@u)GYY{lBcg%~ zf`Wj6LmLT62qa1dk}zmdaUQCzQwOa!4z;yvwY9Ylb)LUk6!{j`_|d}oU_kx&mD5_Ugx0rf=i1ZgEGZcAq&3Wlln*@&zfEc6>UTy z7Af`%E>7(RIbDLEf=iNirydkZKS%Mh#BY&`{M6XHGkjJQ9`rJNr)|B26!Ke{@fVL2MyE)gPl0R=r>~)@sS^99 zqf9(aVm8u)mptF|_x2xQtscP9!=hmfqes%aP@J2hNH$aY&y@GIhLN9|o{K@?FO&>^ zYT*(T_5xB{lfh42fYMI){Db{U90S+iOM5U(>wK%>R~NW0h^HT9O=?mTEY?q3#cKPr zvy7jbh|_Q(r=a4l5)$#b5Wr78j#cy5_#`K!oAKkX?anX@inE&Qf`V{(IO_Biyu*44{M0mWss3I4&P4UFJZO3j56wOO$gBfbE#1mm-I zcv5-irb)H-pDMiB+PfgVma)(F=z;DAKQ;Xx#pjFXAQ6@;OdrA)z0i$kF!-tI87$~U z4L0&qd90bWm;G?G^g4h))Z@7HLsSW)dh<=n@VLJ$>a%w;b+n7+L3O%h_GV{*pSs4H z5YMo7kjtFxXV$V{@Kc>!oB_2U;)9>+@|R{Vqzr!QmALDXpE`o+!B2JZm6^Lxybpfr zofbbXvj@uqKh?!g%8;eygP&>>Rt=hxd5h(PpXx3pQ!}$^AN*98eny6lbUyg0E`D~V zgZaTvecJ5L&D_Us1V7cKUyxbI^1)AK=Wuz@yBH6C>dBV=zzokTAN*9FO2$v!o(92B zJ2ot7*+AXPo+RpM=~q;sZK7)97WUMr`ms+gNm`z5vq9~606$VZSprplikpbnf^2d ze(FY~psCB4_1I_+cO2sx-V%K9Q<<2{gI>vF0DdZO6Xd5ZWYOTKx>n4#BWqIJII=MANk9Z%;gF1PA=1GR~3Y2gwZ8psCImlFwDL7Dymxxo<*W+ctMmGl7eF!JwJkk4luTjr7Lc=-j62@mOQJ@-{8V1~z#}-81%sbjZX%{I$siujV}&TP{~1uaj1>28P2C&Pg=S>Z|Dk43tkFvH122Bw*AmmX&!o`at= zWDe@fbi104UpT&oeJ~56d$Px$;SB6mauEJs9KwYy2Vnf{fPKix5GEop9{bQB<*mzXEp=-l>8|$ zburRhh}}%_lgYK%hXyIl6tDXaV3(=6w7{PO8JJfxxmXS4W&3&TW@-xpoDyVckkU+* z;$U{;F^&vpUu~cTN?vV=_0f)q8-(3Vd=UXo(zzp3Sawb`aUynXJ3WP;=p0;FITB(c zT3Sa_+?f)DF%)*AFmf77i0F49L6fW6*luoSxJd4T#L?xik8|Sj$Z*Jy@^#^pi0By0Jiv za>wl`&8=3Y^xcs@M-^cD9=R2-l%i*^$S_p1td}>e*p=NYfwJ*rl1us7T^nnZw?}c% zAH#~fdp*3V1z=II2L~oXJtdOFply&O2KVzu_uS9BZqFiSKd|Vaq66&63`s;r_f)>2 zMHmr1Fhszz$SH^CGA=1_*)R%=yd}7H?KH}>TA}0EsaYJL5vUFigoeRL)kLC=I$S^S z{^AIGPr=I)!sQlWKc3sD&j;OwB(k6{)FZLSA{`x_4Dj59u)dRlxlY*7$v`c3FS3}h z*6CY28E~iB0>W2J-x}{^-~uQ3oeW&zgyImJ`z#VJr-H(Szppz0&JGC+jlZ}5_T`LlyEBcSma30y7t>nPq+X(bBrF< z$sqeV8X29diI=-sfF9F|NZZ2Nj+{2)@utGvi!5;o*@}?}@)iLD9oy1&(SdzD8Az&Sq6pOWSv(v)>f^otE=i-_erD1j2a!Z;GZm^t7Y|y z`akG*bB_$(2^%@7uBpATy&5$e)xaTBy}W)!4Hv)aIIOk49XcF&`1>t~6C?zTCi*?P zP%a6yNP&#dXL@bl=3Sx&NJONA5 zt>-#+!>L&h&F}-UGF`!tcr>v??3hvzlgi3g7I<+lk&eCJg5~TADlKYb*Qh^-qW)6S zCD(_cs1L$Xsn}bHO2>+_usRxir9>*$Mv_#l$BI}ARiP@V%1bWiK30`f?5nNFIhOg5 zjP?Gf(xqc(!yb)!1-+tCoNzf;Pq$WHbxU(K9fzyUi4v>+bhI?p$}zLLjl7ih#+A)A ztE#)Wr_!akdR6TTbEU0bv8o0RnAO!e2iN+xw&oVBHB{T)0k>pQTWXe5Y|FdaPoG@1 zq#e$tRduUsz!j(*U4;cJ4jo%Hecqxui>k*vteUZCK^4}mI0R&X_A0D!VMC~84GLe; z3icPV870@Xv>e(oMFXmQV?G|$kmU_j&I zWbWbX>Kef1GJom1RW0otW9`cuaTSBBy}O*jgSw`vsm4wdghHdi#$as?GyP5LZ+*%g zaA#in@|WC?S)i+KReeqKnpV`)miDR+9J+&(QBLpGZiTH{HgpmF;aeBA)lIWsoInlL zI)izdG{GG_yslOC-1*b@sa}i~!rB^na*KG7=NedIcLKJFU8j01bCXB1G>(s}4`G@+@H7e(E&kBPaFr8O6=OO=*8}c1Kal9uddEt zY*yBHp!xOeRCL#JRR0rw?*m7AjIWP#nRng7f%Wmu@5cS;(mbTLyD^Um4*BwyHQ+wk zb%&#(+2{bSgY8-usYdQraO74r)-P9yxW=!*mEErRaQVj_zivH_YkNHp3Ym<$Dh0`5 z7jcK;w_~|AzqzSq6^#1pLP6jg)?@aI$ckaF%ef@F3wz zVY6_J@L1tV!n1`J3BM=2UU-Y}e&OT7SB38jcR(kw9k$*OaCgaj3zrEG5%SX})ARcY z@dDvh!kdL}2>&YVhNoht=M=|8`V|p(749uONZ24;Cp=O3HQ{%JKM~$3ZyNL^7F!% zq<=&5JHkIpUw~^J?H3Ar5>cOWVPD}$#a9Y#{UhYtP4b>fH%mBQ`bEN}($@*iFCOKr zQ~Z~N#|cjoo<>BvGlb_#|7{_sa%23J!mEY1EB1PmObAj}Wg$E03ge!iw_PP=2&Xs(z@O#4Bg?9@d5I!t?Lin`sMd2TWZwTKJ^6MhoZ68K~wnhWc*5w24 zsQ3!uIN>Creb+*|nUePv(mjrL`K6L*)2;(MB(E19CA9l1;*F;Tv~~S}S1bOf!kdJ* z3GWj=DEyW18Q}{;`USEc<{kiiTk;1&zB6Ndk+4L_@1@ia5l$4^eH?mzEM@#cAwP;z zULoXnQOX;H{31&EOd-E~QvROM_+pT6lFZMZjHmxCk)Jn-#vcRn3n%5j2>ET3a+#3d zGAUOGjaLSF7s=Cvwp<7F{M^a()xwoRdtQLvcxb?N((_{|)7!d*z;8-EPk6ELdqUhc zBT?Mjg7XccWuTh)317pZoly8*RhsVcRhL^4Q=o+Q#c-cni{vgpy$%XKqZ#|2cw< z$C=xn*n>QjU%-Af54yG>Zg`Xba*Fg&ekb z`cCc~pglZd^MupAhx$DlBmxHMa#tBF2i&qV)|47QVNB)t%F1!$K5osaal1^& za{Kf(r=D{S-P)IbFZlAO`fchxD?KYd>%m!%ycfB3Wy7QIMJ{;sz4%6doIn2QE!%%^ zH?)s$DSwxK_v@AwyzUpg4B!0!OU<4!XU5($dTx%z$~XP+{m9fGy&qZd$d+DjdApWv zEP*BpP1I>dEZ$fEO}z3)@5f7jxuyG?XKjRc{)v%WR$u_RzK(l65GdXS1Lh2L$~QwD z#320h?f){*-+*&F_B=W?KCyf{W1@+691{5Imm+Vh4yyRPa(n2CCyqf(>=fjP&)<#* z9t%iSK*Fk0XTbt|^&8Opd0+i$ND|u%szkOYeUD>{kvK83=R$_#)K``*rx`y^=g?Rc zehLO|cOO)V_$K@oG$Df*TZx(^M|NW+Vm#EzHVY@`A=ZcA{;AOU@#J@7{a`c28*1{> z;@6-|T@H)M@AstMd1~_Ms)*_7x1YQ?MR(pbqm!2;kB1u0cTR7<`Z5xgr*`(=L`3>U{G>+rWEf@8 zZ$C9gCC1Yp8j>1Q#?xtvyGr!aJFx{*Bo?RlVqJEVSem9&Z)$gm zWobU-ruL9no_?67rb_IaroUZkn#62`GaSQjKef02N7m|XR57(rA;awTDvEPc6wPmc z5Dt23Uu&58?O#NBq2%M>c-w@+K0s<~GW_=G8+^K#I@q6$7P$Ui+Jj+Qe~vY)E^u8C zPd~$Y*QA`wyPsyoQnmfrS@PSb;licJ%v~kGjTi#__P>X!`l&VknGn+#;wQDXJHsq! zB&)eDCf3Ht4G z>Veb^5}n_E>Sx_oSjnYn`ZA<$RNnIR^Azu}UZUUr5ftz0cNwZjzy0MrH23s-)WpH* zyIJe|(pyX%p5`-X>i$$OJU&JTIlukXgDS}R?WZ161DxM}YLm*Hl75D!e%ZZ`<(-;t zruazr5hgmn{nXF29>9>C_3wlw5jeh&bBc54%*$+ocuNMALkK-~PQ6-G(okGsx@zk=Y&)&&2 z(JuV!3mEwdFDfsQX^b0Z_EFXUR>>T>-zr}d? z?c0l|K?i1dUZvo-&r`|#_UF+c{PuZ{nBV?5D&V)zg>1}kpHzet{PsELgZb@qR{9kD z_Ip?gtSgm>^HgvL=^=DT=pdQM$|2DP)F~1FArh2%9MBw~p`=s=$CJxZIeQ$o`9#Ri zuL9<$&rxV6v;6jV4P;!@$r(w(Z=e5Hm0yX<6{q00ee)#QcM4&`AJQ1h)^7*jaEd{^*U(ggsSPFjo6lm&4%nHAKCl_QcqG|Z;?`@{x zx6i=yNUUmaw?LWg~0Ka|S zCg`_MidhPN`>qwUGwkIQ{PvGDdkf6XJ_Wyhx0=?0nR2Fw-@ZHH8Zu9^JoxQ9xivEo z`BL!Pck=p7it+Hr?RCccsv8e+`VVR@SHR+o#M* znGC;u%KHa0{q|Gv+dmqL%v2T+zkLeq^GDcc@Y_GbWccm#s!qX7!Ec`jhbNNc?Kh|3 zw|_SjeR$PL!Ec`jx6dD0NBHftR9F6EK_>X^{|rgtw@;P)^LgFE0DB%9Fkn!rz8+7$ z;9Mw1I1wjFrjTQBAVjMG{Py`;DFwfMT7cjF)hrl(`;{ibZ+{5l@jNyLMfU#*l+JIz z5PtiI!^#d1A^lO=ThPi#7JJ0YUce0a`hti;`0aE3CHU>zTP`dwbr#Z;&DQ&U`LfS-zHV;{7c z>86%Y$7zTTrtV%C@}^n34#@nMmrKn!A55cHV{{G7~C~ock7YHWtfCkNo?w@5l(t^%5k0lv1vN2*k_r z<1HwzC{`|BqWR)#M@Cq#-so(;vI^z0^-R5m#dSfh5s2sOtR30umWwZ~rdzJTV^G7v z(8u^Q9J{x;FL}X3_C>@Okmf+_L#9D!L7)ly&>-coFG9=9&N0|wg~yl{qWl?&-CLY^ zpQe6`h;xwU8`y_D2H{EsuE0JtNI7gXwB+pEjUA>~D_V&0ht>9$^yS)6Rx2{!p2BXm zdIN#Y*o{A74P>p7=y2R9unlLesE^JzGl>&vhBfMo`0cSJt3Y@5)^D6#MUIpnK0kdKoq>B+@ zwnf&+8zV*j5WS)TY>N>2VpKQ-=@~3w=dG0(%3V1dqd$eSaSTQ{I2&1xbZs7ne;2-n zUE?DQf(to_7`$!|#16Jbypw@h*r6xb)gZEfuoQbN(i-h#pw$WSP6qhog_wdISpc%{ z<44R4gmiC-EM&PX18((%!PsMwHStacT)9i~ev3y=7kArQDBc?|v+I zBzBM`2=qPySt8!afGc-@!hzU9_aGdCJ%;;bCj%Rt5btEbwYRNHxlrRqj2+JTgk!LG z<#M=dB>Ds~NX3d;kR6r4LL_5`a9uF@;T**J@@*Yh8w6Khur^pp+Gh@sI~e=|c9cq} z!XAsXdv=VPou0tnVh)fyf&&&NcSP;pJ>1gMgl$nfPL&9IkprZ|+s^y|VS%=Jb{JhR zvge#K8Vs?5$Qut825MrIBhDT%til!*HzkdKGZFKA#a2qsly0=;x-+jt72XZkIKHjq zF{8`4-p}=E%!cq*ha}=rv6a#@#biW;IxVmKNENo7+znC=RGx^7v8O*tlXT@=Wp~e5Y!gJ1xS$EOP<&6o#+zQFLW4CU6hM zvKqBc6;y+wtHxpicVq}+S+fqO3Tj5t)oc-gJ2C{ZklcpzH%t-A8OLQa$c9rgNZl8K zs0r~vWfzD*;JHwaor9Enuu;dnTkFF*j?`eQM1cD^>^%0t#-0q0Ap49R6&y2m3HyQj zdhD!zcsnK}c&PqA#SRMCDW7wNnraSdX{-8AafR}}ocPLQ>>z%25^X0MiG;aA_@Cn= zTp^4D=Uh*&5N>SrQg@*oR|wi1SEwM*6@vN`*+D&fmyr(C4h~K%J&Gipr6B$Ejhz$& zv!_?t&Sl2J!Ae7~Z}2SQL>Dojp!aV{Ls>`%t^V7ymc%|p zsVwqi_(_e;d&1BBA0{a^Hc!La2>%JD5-N_8F-AY0uJrftl(w}R(I>H$KxgQ(ywJa! zwd6=g|0H*bJh5uDbp4p>MzTfz2boMpVdHuU|G%I#eGEw{7@Q$z1RU+p0ClOAtES}m zOGa=CkH_}U8lB0i+J)ouUq@lW6&e@#e*ur_Z>G=LGYQ$2|68ml=a&`cJ!M1B-h2+< zvs?B!|M=ty1t%s>ik}=i<#X;6{~y6i>(CbKGP5n?`5q#_eG>PHecYA%WJ58`eZu93 zFA?znobQeoeaGqBMeHTqj#z|O=EP$6;)(HN6+cNhOE^!spKzJ5Uf3=?TzItbtHQH| z7YMHq-XILPPY+8DxKF>8{3l@o|9)G0gcF6cg!>C^O%1fie6)ebNdFb#w}jUT?-4#G zq^A~TKJ)`82=YBo-4c)cM|R*oGm;~c$V--!dr#>TFLzU+Ct=P zV#E)G6YyUYWljP{Tq3L&t`QzDZXnl3ruKH1tDXiu&5 z4Z>z&hww|nQ-tRUjq8N`H&e#3yj^%V5p~$4bWchCweSV$|0MZM;d|1@a7|F!8n+4g4w4*jn;Ix1Uz2dP@MxtwUicN^nZj=nk?&hV z<36Dtmn#0p(qAXMQTTJkZxa4W_>Ay*BJBQ7_$TS#6#hl}7{&(EC50Ix%I_l_EF3PZ zAR_%};biG|7tWD>Un2Txsr0qNLxnBE4kFSWA^B+GsYH}>hT_kc-qwCW{VtPyrSQi} zccbK6h4&J%KQ4Shn82e7_2t5`!YUzd!&W{n^M>dy!%`vN?XrG+zf0Uz7;w;LN#0w? z7tl<{&o@NA^Ci{_8--26wL*K&K)PckpD4Ukc!luC!fS;$3vUN~yOF+K@;V_M za%kst;Wvc#yaPR*a~OY@aFg&6AzdsP|7+pzgf9!t^%3#!N{;e*1#*EfE$lAbUf5q4 zaL{&?JWe=CNJk;s+gE67l|inPOa~#x2b?rI2T?vvNH-wL7YV;l#66gfK-AlF7m!Xr zlphv8p>%Zpq5c&i-FztHA>EKZaI{BfAL{M-3`oZw$~y}uC|$rwn87G6(8edw@5{m+GT%%S`nA$@Zwzaykq4&@>tJ#Z*z zg>=H9%vt}5Q-~;st~iwE3+Z}8xmjrbFp!Uye3I}~;kSggMjO(7SMp`T>xDN7?fDYv zo|pW(@NJE%T4-^g+RtQH6rwV5X7YPp#E)~`a=}Sbr#|lpoenn`{ zu?U|d8IP6LZ^88uqUA^R4e^*}7+gpBJ&pG5dmJz;d9ZNn>#O~rhICUDKU+9gxInmA zxJT41|N{gSfT^TM)MliXhCm&3JKfDGg~0;;JBr%e}S2T#>9? zmKT)Uf^d+BCcc@8M6wKM3*rui9JaT444hq|V>|G#Mb6$a2nTr(j9dqMmolI&h&vK; z*dAZ3Y=(~Zim?avI~(C34}y_p<>uS6GwiXQw8z5|*t-B>+N;FQt-fz0 z^4s8GLuMTJ%Y{L@*@ONzZsV;;7am(dReu6|;rhLY`jtY*`tj{nP`|qn#u#k{*!I>| z_JY13hK5IE_~3{+Akz&`~ z+00px-hO!Xj5cF1_S+QBZzdz9tv#Uip!KGDBLeM$)+Dsi$}`@N zmVR;j*qh1NS*@FII&RieFIDnc->MS#dLd9uBK!qV%r<5ICt8aF;yW6>Am$Ztewmo( zUx?E&%C%X+Yn+e7v1sDkkYdqfB@#rJLj_)ABV*zTn>*(!MP4Qj$(e?X6!i;l>o=_ zd8n|U1bz$7L30wdj-$=&kmESI665JCnhB1h6aDnf zC=eV+Cl;qKVb(EyoEUH%?eTmNIgX4jBtvHa%CWYg>}jw_jw4;?)4!sDT~f|KBt3=V zWQp-KC))tWF(`a6TQEgpak`Cl*-c`pEhYnwqf1ciG9%@=;)I5Ny$Kbn0oH$^eVwTWgkdS7c8zr`|97k7`c={#QyC&u6fqt451ILk_C5|Hv7p}z* zca;Fj6$Ee`e~zk><9HdwG@skSab%bUap_-h990kw4@X_;`6!+o$3e&`j-xV&{ybIgaCzR&r^2F%#dYQCyz>BgH$cm&kGC;~hATx1)OG zIDVC;?&NEsxUFfadZXcIF7CXIgX>N^OW>&XzG{U z$6DU0X|AgQj^lI_a~wx!YDRht5Big;^W5~UJW5X$zGm%RkiL_Ze747)NJNgKQOlk$ z=Jkdg$79)|7rOBbCdcs%7WAS98##`w5VQ8OAC8t@C-R4S9G7{BDq&Rb9g)*<9N9aW zX4(bE(KRTN`3?^-IF6TC6XKc284r%5ll{yl77UJ~lZ!KdL?Prjy8NY?2PuQ&_-u+5 zEz7KDdT<cQZh9|P8&In zF8z!Q|KTOa(Z$csJV<-sIFk4j1;>%gkdWi((l5yHA02WW**WAm8t)VwM|+_Rjw8=2 zavXUo8OL!i8U)9Y=ZJ9}M^OQeV}F!j9LJYw5*){6=(5-e6X69Nlq@XZQk%97iT5$C3YNljF$S1UZhEvuJP}T`Rzar9E&QPceH7 zG82I0I9_g5JuuUQ>A`VyCtO43uPhH7M<=&thBG}lj!s^m8P0fc9QQ@}yrO6LCXpP+ zrKSMK@dl;<$B{LNac!bAnF1U~nlO$dKbDc>=oH{MlE6cbqf>z6_!d)u z_e}=Jkrzb@W(pif9vq%Xk{!qKSt$DOszZ(=4{je4e#voUsjmFjf=u8zUX7&SI8r4p zBd=Q+U}Q0ZEsO)&*W<|-oC|{yPQ*zlF60=TjDS@DT*R4d0XUAd0FL9s>>O|$XPX#{ z$N72_&tnIm$o{{AGU1J9mB4X46IOP34e5`{{tm5-WU)uQ?2nKEcKacM9LE(%1&-r% zAts9L{uLJ@WsSZ`O~KVe+H!phIcI>3#zF0_>3?529*i2zdNqc5n8e zdtqVdZxGRme&Tz-VL{~Z*P!JaKhA}r+{_f?Phafb>=^|}V!3(Y=G(wwL8RsWJv7$; zks%)-B{RkNleOG^7BY7^{y*UN;y+^_S_Fa9bd+Kr7Ni_L1lnQH48e|%)9hhdV4F~h z#Lyo=!B>Wpu@Aif!a@Z2&TuED7=8mZ?2kt5*hZ|uPjo^Qth{>>GqQEz#7J~vw1`5* zz3AEKq-fEtI3lBrl{Yz>qJV>LN9hg@mR`}m9+fe+${FbG47fby%2W9x6dC&pSb2BA zLTse5^1f0~NeKd2d0#2mox z+D=O|fn-Jk+4fr5Ng}?c1#19tHKo2>Ux~^3g;`{K6i>l1?H|W-LAw`m;V8F45Yz22 z9QpfVEM_f$6KBA`VznbKP(<@XazwhW%O2rna&CpAVZpLT!$Zp+?U>7$U-oDxx9ri! z5b;9HJG`O}cgm=)yu6Q4@L18xkMi=iMa1Lj$;Fe1ygDMxOG~hMUQ`=~J~z7{MHUda zgFv^TlYx=gJzEkwg4bjSRuTC2AQsu+buzHj362uSXJW*}jM>G4kr}`F&GRrVl5Ntl zT43G~?79|NLf{T6-iA&FTqTweTqPFfE3rCU3Gwn)SmxE?N-Tsbzp)aY+nmx>Vn4!A z?BL}QxPzCsp_2hu3FGU{uq68tzFq`yV3M`Fsq!N zz~d^K9)oNTX?pp}QJdd9cE?=oIO0KPAh-$|W(^UL?ABo;lNQ~^13DFZ4}5+&+nYUj z_E1o}4EuIc@49>ef%V;1GFG1t!HDx@LfE&HdR9txWAnC^j4fK>;-WGk?Au9w1NKr( zjv3UD_3Yb8Et`oZ2Ce;QBE;L~MR{O&YJv9l7VmAjEgGDC;B5uUs44qGL~@CMu0niU$yp3c;Vo=;Pn;sL$Sf2c{l^xI`kW3nrgHS8iq+#P zJ}Y#viJvVtm~p{uX{b?CKtftzjIRgsRIo%}TY)JchJnBZVwi6{svLvs;&qUFmpNwE z31Vh#iDgBr0yFDu$IM!dbOo`VQ^E^CC3<^gZOu&d9x|$6Q~~%`Bts3#ul&RW1z0|6 z$4^eNcQ%|GR4UN94$8v6<0I=m<-d{q6RfIFB~*zyF>(DkBl7%zz7W)>Gpj&BnG~#r z)6lY}E%HA>u=<~*RQ*SoRDUxYg_lG}cKz3_B=sq@tA9DwDt9tX+ix$B9{<@@qqvG2 z7M`pA%+al?tM{9^=znkBsMQmBrTot=9_47E!Oi5ew33wj|18X@;=^*V@nLpax3c3B z$Hz~Iok%tnYa&J3tdrWkNce~Mn z%+_TKE8>yY>AsrVVtD!wZ?W7zWKJ8yBXxL-;Xl-FVTE~TKL=|eq9xQCGcz);VBUWf+?`A-aG{v$(NEj&tig77rqw}cl6uMl1* zyi@oKAwN0N?jMAI5}NNa^htCCZ343AKvfM$! zF~Vs=dS@{HDB-EXZwWc0DC7AKo%pV>7yhTEJXknZxTlcsz8Swvc%JZb;r|Jr5WXaQ zN0{K}4&*Nr?khZ4*d#nc$WItdf4=Ys!kdH-2%izYD*RB$Ps+?se;;Cna5v#R;laWt z;gQ0x3NH};NVu4v0%5O4*djbi_*LN*!W)G537-@ud}rq$T~F$G<^P)S65&sU_XwX5 z{z14!ScLCpY)4;Vh43)p$-+B@4-5Y!+!Zf)m_OiBeNl42rCKSO(}FVHM&SvE9F@cMAQ$7pm;9A|mQjDl8KYR{U_`XyJI_WFqqIF5H?+wZHUV zB%Qa4)N^BfaJex=v}>1;uZ9^v zPRK9uls}j(-%fJ()|ElmT;ibYWgm(W$`fDZMCcI1ddm&woSWdv@`LpD$IXwZF zhrXgrpA`-kju6`Y9PyJRPZ3TR?j_t$7;poYO0E_1lR3-zlJFSe3BrKubB1JoPG|an znu&O~+%nb-5kT z1sjHtZPV}@*rwuA?BjILp&Z2RhA?lfQ?YY8F!D5P z-4--56jvPzGu`>6m=rarR4DF?2#3qPZaBsj(y?5Y$1FtmwGshseUKm<2*99Dhaeob zw+S7EqRk#2w{rH54&^~GvMcNz$bh!M-Vu<)_MU^ijnJ`v#n^-TorQ3a2f@f$NH8ln z*rB+uA{@52tirXA_V_=1V6Rhoc#d-W6;3v~Rt6i(;?8?BF-Ujo4%_CD&=o3Nze(AA z9zwIUfO4w zq3(*@IKX{Ih1#~j9`l6Ltw;SHQ5r&!F8D^WV(gf|ZH=tT(Up_3+&-O0a^oN?unUg_ zERy2QKN-6z@_K23_j+j}`g&=6<*Z(>#t+{g`?}ZeIo#W02131FjX@JLO##x*K)Bbd zQRoUxmq6YbCMTdzm@W=mGZ20pt7#RNWoHbSG0?aueKu`+HFEeF*vt2ytHsgeF$0qLWjFY^$71BPT&J2QBQ|mp1u^f~w{TxlK z$05KvT3kIK8c*zoPLJJ=pXmJUcn)FhtZ|I-6E9Qplg9w^YiE@rE;a@SK2}*a*Am3( z^c*7{Ek1C&bD>JaFTigBZ=ha`)ZWC%ZZn~Y(TgzAX5r*xNM8W{2rqknJn`Mws|cj- zg*I_%@y!hPWBB_$sduZS@X4}>>B%2ST$~z$N~b{*i6kybHbD)i(DbnsFH78SBG$;d zfW==PW7gO&kv?%%pRXWH{)jzjqEnEggyGmZ2qk-4CzNv4(DLNY{v9l%l@X(RGK?~~ zMpkl+N{pwwF>*|itAL+=0Ev=g%A8o7e%E6AIMMhc$+1QMXNJfh;lpep9b12e-P(o| ziaw=-lN0@BVEQ+xZE}}X(7qbln=CP&E=9KFt`hz9N?c=-QzRCrOVIe_ZW2q=Z@^x1 zcZuMS(9|9h%hO!@AURcHU(8Agahk+zq{j{@$@h|b`!}*y*Rb4u3K?dvqmGf}+!RH6 z8>hca)B9S(AV<^ln0%pR@<%x6IC+mX8T^rQ6n?swJlJQz_4iU!(mJ2ylGO#S3*zaU zXsjk>&zXb#G%J>@?a$5x@*HV6Rjb95)^M8}%+U^XqAl?#^ z>wZI@~g{JQ5cZrFE)4Q^> z?@Qlj;&9{cB=1kXXrkkfBp*~kjz5xoNDXlOk>n68S2 zglPN`&hU@~e}w0V@kclXR}%aYF5+YS5%Tqt;E#~F5hH(Odn&*mdEQd|k!xh}RB#8W z6BP~}BokRVB$|tSiTFk&DD$p{h66N|l&au(UT%q)kHa>f2>HqIu{E+d3hiXp8d*iC zpRSn6bJ$GqM;d_T1sEK~Nvx5@*{3pg?FN6urlJBuZb__>brDU`%{~eK2nAd&GMv333I2$a3o>U@27hFC8y$sgf*nMv?Rc$*-9gfAbG;E%Xg z%+B1%R)9aU!t5=`%x8M=N9wGq2WIYJJoqE-glotwW<2;KPHxTY$$0QboV-3W1bvtU zf26>UIrt;|T95>Pq_-)+AGwe<27iP#F#gE*SS9dBXu|j-zd%e9{1K-Bf8^^-0se?n zfIl*VDZn3b3h+nhtd<0S#3{fZ;RGK^@JC!JKL>wgCXBFF)~Dc)P-dk}27iR|&_E`C zB#AY$7DAEnX$$-j3hZ+({FDTL#3uC`1pWxG>J-cr_#-?xJdq@Czd4CDvUnxv!>djb z{1G19K7HAj;E%9WSN?Z{OyG}P2POC;RQ2_E8L-if0d_UQi8xR6z8+7$;9THxdx`jc z_$}lZd;yz+rRatlT9NBA!uypQ8?`y}JX+hMc+m56j}WclEa@MZZ9 zPeXN7whFP4>>aFD_8k1eZZQn_;E#~T0{+NgG$?hB*S!>C$wBx@#N99XB?CNu=<#+V z6Aq)BKiIs1r$F|0@3k69IPCF{R%9SQad~@~?l#E$FJ>UA&)(Ethaw#xUT9|EFQ}W= z<4cG?2r@6)gMI|Tn{GOOw&jHmif!@;^2C8yS4zR>JOVKVJ}W!|9BaAf7wrNnLbTx8 zJu%h>iLVgW@o3v?8G76!jV&RLaOn>b=BT4SzrpbwqXQ>_^FX)3!hcfXoJ<&w9bV@h zoeWHJ!un1I__ho&4V?@uaKb8c$X*Kp*$JnZzBS&-z_*>?cQSCL6N>o{zqXH7VPPwx zoVkU0b6DdhZ*Fzi-0Dv@w_o1eetC0kVRLO^b8TUBu9Cd6!L^#ezU;b=4Nh-v>`|t& zo@EdxDXuiOjtzsov4gun7;M1<2+Og@BI~@IPrDrCS=4csY!TrkONMo9*ahb~J%N2H z2l=3T!|T}eMKo?i*y8rfpWqS{D8e$|UB@E!#r*GeV6K~7)!NpwvaO~myP|PbeS3EJ z`biUZtXkQ;Cfm`{vZ_6ccNE$BrrP@D%j=g{P0Dt4^hIPvb4zo51^rB_8k_4@tyx}Q z)l^g0(AZob`FGfEKdk+qwELf0tHL?z1+L<`l`Ht}$5yWR$l??@sQJYyFj}=Z1wy&S zDG<&rPJyA)R$t%Dl`Npv;uN^!@guE8fJwudHFlSmJNRB2NBn2!yPrYA8LSb*bkj}@^(`Wky&^kPUCGnNW&(4VGH zuRxN~`IQ=$x3^R`)HE+&RgWHNJRHAmkjBAvufD0iZDoCP-C`LC;M>u71J zMaR{2Al=q3nbRj%EorZBYp<$XRnt_{Ryn$AMN8YEW2>gmTQp};^>~L>GZrnVTF};V zNPS&Ld(~dkr#nx)kIsQ!UAdpOEDc85O);CA0 zn`%+bb#*~C>B!h#Ul%F|o{o|B#+A+W%d>S2HEogVHMMInDST~BJ6gr$=1c5c7rQQ6 zQPJ_VMR<=i~8{4bv)}yB|a2ipQpb7138<)fWsza@Vv6w_H zd%JFJhn0&-%-icbBCU(s>ZaN6o@_(AHKILe1sb)gzB!OI(>mPwP-yiURAKBG_5@qS z%3!G#6FZjIx1oK3C-usjrluN8gb)riR%+mH`F>J1z}ZVJ3{N~LT5$jwR65N-6(6WUl*xvsKya# zZc*3R*kO@}Ew908R^4vxbG=wSYtG!6HWGNc**I_SqH1;%1C4z4>% zU^%xg1CB;(eO=><#`@*KDb(1!q9xKggKcT5S-);M4xwG`(ChW}Fj8IDvWA1)b!TX_ z)z_nU8=G3!wAEL)c3_~bz{$#*x;DCITaWT=Xu>eV7_sWMcVKuQTD_` zX-A`ZdBZ_tD_OO5*7J5c%X)Rrcym+DDp*4|P8e5X!)>p9mt?1po|v69YRst7cEcV$ zX7t$X@V5F@^|*ZOnEm3)y1I%<6}2d(t|8l2zqXO}%#N8bv2xP)b**c5tHWtg zzrLbr9ORCMHBGg^70|C}T|2I#y|rTb=n2$tpjF`JzZ))6%b}=gt83T|18nWY`iiCz zD_XM^E0?dUXQI4;Ah8`fUeCkw ziq?v{mgbJOn!1kNFv@Y1Y#_QGi&#b61%^G=*uI=c&4yO~Jgi&Q!pmnH?;K6F;R|r< zcy)CXyE=kv{^aa%cI0Av2*OPwI}Hy)GxZ>p#oeK*kcQ7uQM|I^@uF`OzxNUOeU!Kzu?W;~A`Xn3Z~=tTH=Mm?+N*xl=@qQj|zVy419Wfqw!2PR5(UBTWG#X zh!1>x50(BT;Wvce6+S6^N%)SC51uTiOgKn5MmSBlKxp&&B7KYGBZQ|4&l6rDwE23G z-h6q0FH8TvkgvvA{zTyn;UZz9@B-mg!Uu#;3ttg#5%OgZ?b0WJxL8;xJX(0V(B`#8 zI=;MOdYi`<$Q7w6^VKe~myoY1DUTP<6fP0g3)cvb7k*86iSQcXUBX9&FAColCNRLQ zeBlt`1mRx71BH#kV!nn&J+~7M6HXNFC0s6S6CNWxQ+Si`0pT;kSA`!6(>MoNUO!=l za5v#R;laXY;ZefVg%=917TzIzMEIg`G+t7&ylKJ>!oZjJdy?N2Mhji~p2F>gI|zey z6DCRCT{uIykMIk^!-Pi@ajcFPo=ilUUse3MlD{pySb9!>!*o{*ua*9G$#)Cym;N!y zPYP{)1+@QV$*&1Hxge!%7GsO1u zZ3~gF$cRS^PZFLg{F>0-10&ra72K4ro_ zLVm-g-mbI2og|MHP83cR&Jgl#G4t^=I&rzMLC819)SoFlUwEPLQsEWCt$jalmHtlQ zLqd8I(5_w2fzL{|>pJ9DB)=iF>pb-Q+{b)&y$9m*@QFTxqm{ml>F`VwjF*4hXOH*k z&*y(eciM)-W7{zN;!?);T$AW`9Be^c z6%^rePt8WmFPY`CJhp>KAM+p&f{~~30Gnk%TM&0BfEim<((!yenm`r)+7*}DK? z=BdQa?G-!#uMQ42WX5s7To|OQ!h-E z1=R1+AQ3P~XD?718dr2wuO2%Zo_nLmPZ(1_)k=cviE8URX z;=MC#i}(KZGs|x|>E)N!&U~+Q)#CSxx1leF-p}dh=hFMo$5$0>@!s7FcJ`fl(#yX) z{Gd%YzwULL`Cj}Adic@v?_PTN^<6fj*8KbS+7xfN@bzqR{>v{M7T=QmAhpGN`?lA! z1v6hRP7K~s@B#7Esn@*n!cl#1K}}~I_wtJ!-mYcKMr@kV5YF?7=|?PH)^pRb4bNl} zTfEJ&Ey;HWZ7FzX()7ydu`S-~KYZmkN5wY5_Ozp4es1*{%WnGp<`Y%t4MClcdaL=W zi(g{T4cRn*PxPJnKK^dj67IWXvuE)%w(3^2${R6bi}%*zWjCP4(^0=OmR<8wQkk;wU;7Qyu7FBIk$FPb8G(<3FB^V?I@oc;*)wF zYj)#%v-JJ(lNh+&7N`<&o;aFk`ygCq3N+95-H0p*&9j|^pX7I-^Wz2IjnS7bwI2#E zxU{%G!*|1C!S{PoA1P!{@M)-s>FFm~aB=E*$m#9yQ*cT0e5mQ_#uaA@E=$+~J8+?l zl8sq#dCVT9xY|m=RefGVQu;|=f}H4Fx)7Bx9K9MLU-N9gh(zW7&OZNRP5%k8{^*|e z->dVJ^v9^gczP)M$RAVWD&VJYK&|~TWlk(kAI+>|`Z&@2B>k~Pw#>~S`bpk|=)xc2 zXBU)XZNmj@FIXJxPxR?}nuc#k#NQj-6WQ# zpQE_D#Ip3OXrjM|#Pal0G&NOX-*l9Tr%8mLB<^VNll1rY`=Sh+XWQSWkYV;Z=h^n> zrYOefC&`&Q{e7)rkfZ6dDKC^vKS@5Yjznr}GW;a#QQGOAf3Uxv)~&yn_F$OSUuMm! z3tSh((@(G_HK`*l)=yi-YWuUZQF+VL&rrO>dWn9L?G*3o_av$pg`eb79-4dlCHPPApuy?uSnK=J zJDE5U&^@=ammXN%n*J zNlv9f_(}2{F+a&+RKQPi0!qluv+cuAay^c^`AJ?w8}O6d(^8n9Bu@o*kp7Ae2^}O8 zSvede{_~lLKZgWmUJryhKtoBX3XUfo!kj%0+k7JAuY|&`{v3sNGUM{W^YYL@hO^iS zu;s%~@?JE?&9m*pPx4x%$k??6ev%Y$j@vxjKKvwI55_YGviHSbp^A+PtwV5o^5~YdA55Xv8uh@CLey1`{U4LxZo)K*UG5gMOvx*IZpCl90Px3t;1NceuHbFm0k_dhHNxD{GoX{TpB)@L<7MKU3 z4?oE}tknl*ikKdLlJ10a^KAR@lXP-xrXTY8@RM}%`phWS2Y!+(P(H8d8U9BASGv-* zrqDdwKKvwE1M`zSj49wJNfYKLIhtj{PtqyiC;2uT1wTorfS)7}mk&Qlr+}a277l;- zNje4mBr|L`{3Kl|xEB^)0wb)I^(p)$DYH^0!%vd(34u&MNgsZaKY}7Ng~h{9k^=ku zZuS}cByTerev-VZQ!rETljOnSi6nXZ%|84j-+{vB+4kWl$%ES`$-aW0BujPW7vM~> zOz@NZ0ZM_NBvqPEo7XK2FwUf%i1S46>+$3Z&V?za=cM+99E1BIV7B1TSjiT^Pm&hk zC;0$72Y!;vOvF6f0}zjSw)aDkp?S73pL@Y&u(AW4bC1e$g_TGad&JA0h77R#5>%K( zebA9e1wToy^TCO!C|N%5-OYJ^4N?5vM8<=exrJUKTdJS-j|DwO0Fu{8K#o z4qV5Wy}Cb(WOEUj#Xj&s{CKlV`EMp)W%0F^n_7EL_a~5!*ZGsFOEd4@Jsv{3Vd$V8 zu)C?X=bG-zkZY*B1&O_R-RXeI={UZDeK5Z2dJ9vm<9!hCq>6q5-oi9>WXZmXeF*D# zJM!7)o!@=vT~MI7t6(zv?P!0Gsbj;}N1~n46yJ}cq-}a>c6H5+<()R;pU?LEUp(8h z=2s5;ZssR`&d=YBr~lDCF>F3M)iRbUh=t~F<^Xc{uEXG~;2!W-CQ5qP08!2e4j_?--lazb&a<@@EUzF)rT$egb_GUuzl z4Hs6F5_TMAZ#y?uhQ5s*{;hDjnA4}#oW8TqyUhd5VG?(hB5V=`p|2MlHbXCv7l1fd8vjjf#^yDa+?xJM&v))U*X z7vU}I{Gr8g1vzS1Cl$`-0ePDTKxtcF{IY%=7Qx242HWijY{LEq70~y`J~9+fbvQkz zcZfyEANwcgLjHF+|9fkUf2 zd2VJ;0U~x=eWFU|5rR$&D(TqYC;$H z=#X2o`TpkI)sdYbCh`Db%@*|3u1YsgPr-v3>_?ehc2oW32|An!!( zoTCGu=U}in;=oqC3+HQ}_vm(s^Ipq38G}*d+;u}<(SZwkmoKdtQbB|4e4uYNH8%RJ z?t!DcTuJ;?_9#dgnnO zFh6n^S&hit6|1YyyYq&3)PS&`dQ<+8i;se9X2`9+s~5I)3LLaW9bpgG2mBZ3?Y|AS zM&2dA3v=JKC&!Z()A zf69IQ6aB~ekUza!_Bj9eT{w(^B(+?xR;gK`6eHQ)4%TPc5PsKjY z`;UjN7=Z_Qph8-_l#Tp7KIHtDk-n#sgu4m%5$-3XCjiqe6|NGl79J%$PI#v99O3tb zR|u~Y-YMiileGV|@MYnjg!~Ve@qur7Psuw7#|x(kR|?k(PY|9dGm!efPJ3NIA?PxFBC#|ytMoA~t)(euFab9U|&t^F_l>5x%2PE)m*%(a`T8d63ZNi-vxz6b~lRLGB6 zlots3W{&a~h0BEvLc0zlevRZKg~td_7M>>jy6{}#g~CgOR|>Bd{!Dm_@Lu81g})R& zE__b-g76igUC&X^_auKHOz=7jeM;Cv*jw07I6xTqxZBHLElP_2TS4zp>drcPmnxSI77IPaK4ZqH<|yd!mkU@725p@@s~)xQh2rSCgE*D zPCZC_KNmhK{FU%I;S0h)3Evb3^CACLaslsGuvaMTDa;6M{yM}Dl)R(R?vv2l)NsIH z{^Xg8r*|IhavC1uV&TEU8ll}!5x+|EI$3B< zg^vnto@MBtll+2^UyzyJTyN8W?LwFrVOh?@!pZ?{Bl{y^NrFb?SR53u_d z>&5$1kO#rYeYm%AO_g8^;%cD?!i@8AquVQ}R49)BUxds3Av%DQ(6L;W$1FtN@51)x zV<2Xs3$`Gx35u}2EINw!SlYuQMb6%F2nTr(jI_XBB?H=mxQ&p*_9|g-Ds;5Rb0?@D z@2^1~1S6fW$GOdeEr{d)Nnv}fu*de%9!{&Ay^9cLo}fWD>WxI~mpsGJbY`A{wL;cqSaY1|UK^SAS6=2)x*{=42_7X$GBXTFwWufd1 zeRu4%$K%5?gE5a_CSP=2naiSQT4wE5?tX ztVNyKV9Q z((TQXZZlr)He=kf@$bhG8|@N%$wb5O5SXKX2c zYxb7n_r7!WjF|$qB-C$uyWCN@B{7w!^x8o`%&%! zeQX2n!sD>`>D&cA`i8g*Bhk}g?!tH)5qE(TMt+pLusgJlyYM@Nz+GUcmG*+!9Cv{< zxsT;8OhiLM+=cs5V2Haw@4CO2yKo>Z=C}*Ig@w2a2UE;*7xti-=PpcV3-a8BX4WOo zU3i^hp1Z(*Izrq9K8uIA3saf+W4Q|>aa2Rxg>SMCLfnNfFgnCt;2f@>$Xz%SrRBK` z*57&V0;d%ZaTj?0{Nvn(-?FL!cVQFzE6-i1V>Lg*UEn`K|2TKS{-wnn&qeId8&Xbm zb3A`McOlIt=D76y3ty(GJa@qe2YK$oxop!v$X)myJ0Qm} z{|5|l7anFM^W24lnfPP53m3DXe~7y<6*-5;KbE^-?&Trw!fWiw5O;wO8DZ{15rzd8+y(wGkmD}Aj6NvN zaTn}b65=i#!yXE87f6BnSnk5nu$$*D{Fprx;x0VLtRe2gvosCvLM;ZF&GF2@wz&&O z{6F@-1hA^&djHErQkm_syKin-^A>wzfYm%=_k?IkVom zH+Pxu9u{SB7m_Gj+yySmv$+dNEZX8O@WHpuU3ifB55QeeJOYcmz^}I-h`Vqs>pLKK z;b~gf+=V-NXxZF_)7eIwyU>LPm(5-Hgcde;Ax4GGUEnv{zbfuR1IN_jF1*4q_+s1z zo^@Ke3t1eA{c;yJ!St)*E>y7xaqhya92}dwa5~a)J;pD~bl;9v1>IrTDXrXvJ+NOE zdk4L-$>J3?_6Cc=0ELa*CUwp*mQ3#3xiQpfi+?vWi{g85mPG^ZkD zf0K4cDIFirT}#~#7`vksci|^!2;GQ+yHMb`qZN697j&;`T_JR7q$Bh}(cKYxqipAC zJR8U^XThg-XWwQafmh?%bMPa&a}aGraC&Fq$B)}!I|r$%8xZUq&q5}z#OXa5KlDwg zbCjt%=xekCg3h6JxsdxJIKAiMhh7Qo9P^P<(OG0veQ$=c-<9}z0CwvU`ZIOF-OxxDcE-0FKW>@# zSwa?mhyN*NVXB?wUda9zm}R*)h83`ut+0FxLDkk3Z;p;Y=ufMGtZg`?p$J%V%Z5IV zNN_uT+*O{+J{M_K2rByxh+K!zpB5_ndPw&pV9Wg}c7pFCcxv`Ph?4SdqxcUuRSBiBlKsidV0UQ|}&_;$ORqY?~|M{}5|ay&R0oibd1T1s$a%2D#Q@My&Gr)lx{41R(s zOIf7EExs<_6L-=4UWfQa@tl1zRZ`qjLoB3EH@6^Tio0P zGY1ZUp(Xs;qLJ8im4EQMu)F&H0QOiO7MhMxOEZ73g46*T*W=Uc?HBnja9 ze134)sPL(c=f}9tB5Lr7lzaf4QE*AlZDE8@Y8A1B5fPTQF!BuquuKS52rz1HVWdXs zClmNu4qOsn3nM%iKnS!ja-$YPEo%_rSpjtu)Cq!hGx9iss+$oJmbNhRR|M2e_z*$W z&4~JY;!Gy+Pmrpc5q?8T)y)Wp2|}n11A$}5QWe96HhVE#Tqt4DI%>Ae6#2~g6fnN#JYv2!f1msn@Ug*n;d)=ekp{@wVuG~B|H@~ z)5ud<12qQ@^%1tH=uE;^1Vx?Ups`C*AERtEI!YiHNAY4fhJ0ZQJ%OVr^)X6r2+O!BXV1ar|I|-_JX^gdgAM%2dK@5{l#GAKiA5?)XIOZm7k+2 zTMn=f0$6EArA{TP$QV?qsQM~jaZYic1x`*2HOvBY0_#dNfI_xB;3x!;myC)BpUyu3 zh>YjPOQwcdU`~*dEdwZJ8v`ssu-Y6_Nz8N%0!m&IFPR!c(f!MEQMyJ*81Yvs9^)79hdKAz+>tftqsJpQNzZfp{C8K%`!lm+FaM{!I1M| zU+YyIvT~d_AKIq))q%@7+P!tcEphrJfA-lCW|lxK>2D67#$F!kRhSmKFTmWd&6^ zuj|@n>X_PPcebfr=iq6jZSCIYE~_g_(K}lodJtRhs~GQua0Ehk1Rix}vvt(>LEy-n zjd6xTgrP<$abD>2=p19|Z5{PI#yG`!!sdQ68{-Vq5V$YR#z|U_z%%!`2%LT2LRf*o z`L-H?GskS)e+-)txF5~NIKvhMj%LM}LIT|)j_{P5q=DH8-X z5ZYc`LapC_hd(a_x*L?BnQd9(W^`1!Pl!o&klm`0!5_5>y4o)2O)2PmsvywWR7pFQ zkWT0ShVmHlypu?;Ywt3#f3SUTRcNpsv)D8;7=VA45;?HND0aO5WaizsjNGhoAw^*S|17bkS>W+s`g4V0cK-dqRr z=0@$8H`jrDy8dL>?Zum8(h+$^57M8{hYQhGO3A;EJoh=MGU_-G{~cd*vfYA$VTwef zeMlUfatHEE!EomIS5xosFb6JNECQY;9g+P+qMc?JDT3Hxid~{}h<`W5E@9aU{N`v+ z6aRL?UF*#J^3*$vY&Uw!aRqv^)q->P`IvU66bw@igW_~M<>ICk$6Rw^X*C=Xl{SLJ z`ZZFrQA3!@rwPcLC0&)Fc&*^~ z1lJG|?j+*;wO;fa1b;62Cq#ZykQ@i*dx?mAe--^!!S_YKTjWm#130HMUxbK!Swyt2 zt6)#j4-z?Fa5xe9j+OKiM1Qj2RMF2AdA8tOBJwSe^d+KSE_k8nSBrd=;LSv=UAUEq z{2N67u;3%2f0_up=S6-;(%%={Df$5VO1mT?%Ii!-zq<+c5gZ^mmO9nJY>F?Bl1J`L@sS6_7OCE${`|;5ac2x z+D#VZ0xHU93UWabW%bEz;B_MNJKfaZDtL$BeS+%+ex8f?O$0S^0_sa>X5Ge*Bf#M{t0k;kk_vxmeKfD!KTI`N{<6 z3f2fN5R_y*LxJ7V(Jj&gY{;8mc#a(P4Kg~?+AlON;r(kbE!=L1G zNZJ<(juPbhdFqc7Y|Eo86@9tjJi+;bZF!X668%MjR|;M&c#|NP4YOV@Vk15%_?V#j zz5(=H(8lzwf*%TgB>1VI4<`)TB@3nra`7AW0|W~NhYKDfI7U!;rGWj(BF_@65ail8 zmUo`u6@uRtBuj@L9VN#yjk#%f-ecaF8EhLuDPRqieNXv zo`U@ZNvELQF@j?RrwJ;bfk-bExm<9e;5mYq3SJ?ozWacDH;Bx&eXQpp!AFQ5`Xlml zf-i}lOZ8~~o*-B2QH}{JUxkQs%^vk51-V9#vihzBkjwNa-z@k8A_5odQNKYD)hNCB z`vy^^WA`h>t*S!vcQ8w2K3`xtF~J05jlY%b@zAU&! z@D0K3f;$Cw34S6-stv~>RnYvs$YeSmS!9Xb7xX!2-u?a8d!6foaljC%=P7`MH|&)0 z=Spoo@k=|Lrqwo7&;Zl8^+gCH9L$dMx^2BVrVykB5V(~fSZZfFgpIhyG@D5)h60zt z4w2g@Xvi8In|vOGX`squyCx%;Jcv43?QrdCI%%cNw&JwA3lEsyKzU{}W$<~CUGI&9 z9cMdE2CSF$u^&WUx0*bNI+x=CRg4kYOd79q?ebO)KQvzSy(lls6oN8Lba|WdZbW&j zk;wL?BAE8^I@#nw)Oq{}EKN2$!Aj$GwcWl!MY?}1k52+kdEb{j`9N;(cgHuBc#@Qj zburu{XzX6Luk*0mWMjUgr9-y`rD9@hLW-N%- z^l&!7E(T>M==sc%<)tIAPBZ5bbzZ>y>&1v{rab1c?Ml$TgYcq9fEFEV^*J|Wf4t}s z!wO^E4$g~y;z-q~y?N1N!HW)@{1O~kZ@+T+q^&Dbeea}tp>CZ%4$SEEvH#spAG@nM zee9cfSuy$1!5v;OZHJe(?fywy)AGW*-CaF)U;b%$hZkN|JZ@{aGO)u7AaE*p0aZjpp3?AT&P3 zkoNpPs|Q2+f@{W)`mwYvZPFOkx`}8VTISw}*3B3-dctmR*BkdAzuWtG($;Xlqequ) zO{(azd*!a&09ew2;Lc@1-I{C0u{EzsYc``MCwBapWO#PFe3uh@LfSG0t-E}e8{4Q_ zLZ0;HyL{Tm5yShZLV|&79w2fZ?N#a{JilyG@2{@C}M^yy#q~crPX-Hxzg{kWpO`m ze`UMBu%9>H_Ox=P@8NjGxze-P%)PkMSEKqb&y{|QRUIl<`W<#L&Xqo&V%*Q$T<)4U zSNch|I?k2m{rVT>O8x8< ztzku9h$~H!=>fRX-{xRgTxs4!*j(vnSh3~jjUV^2xzc>NWpkx3roF|L-o|cOe%=)G z*5XR@wUuJkFa zz~)NxaZv(S`Zp}n=1TJc$k&`J{e2Fj@$>d$bRf=^R_79nD}5rnXK|&g+5i3dc`HS^ zajx`z-1!z)`sd7Qai#BI(TB#BK9@yVT5F-2*<9%{tkdR7^NXwrTxotvErBbo+|k)w zX+F&Rs<_g8AZ~M||HLu-Vq9rOZ8v`2USk{g%a!KisIQ7EUBVv3xzcyAVw)??Pbz{d zU4<&UKZyO)hAX`Z_RC_w#h^Pe1jmiti45@b#z(6bS2`Q{eHXeN?uL!_^Ttm+81}T+ z1tssBIIXD5BgienV`%k@N=DrdyFDZUyD9|7eN!J$A(Fg zrpLF9S_k6vSVf%XA7y^O4|YSK%cLE@*T--7K{ph-BdE)VJP4sTn(Tydcbq+l4Vd1I zFMp;WVKPE?34TO(Hlp;g>GY1_r>ISibx64j!Op?Y^ZpV+)1~LN$?+ai-ffe^V-paZ z-o^O2u}zK%NEwe{*TD~#oT+lGMUJOhb6lInew>dK64G@Jt$P^qUChykyYVzcf~)c4 zPWN2Meb2&AzsdMH8&if9ea)7h2Mwsp%<>Skyud6Ay?!*m3|1E)sBA7CfPCf&Q+g1y zWkb`Mk45kxd>(#$!+oGSHzOsl{*)1pZ-g&}!r+bA*}fuQ3Te&xit0Slm!vq(!2oB^ zVXE_Cs`HnlI`4ztJjkLy?}zGadG^D1ZEWUq{y~_}JYjAk1g1Za@~W z&j<|Q>YmqP2}^BZnG$MLj?)Ny)`c8PS{PZR^pgoImA>9>VdMra_!Oo0b}jf@?m~pe zIO--asJbm-X^SN+Q^IbQ<21sjI>(Y0Mv{37cP10aLj}XxRSaJ~|5Ze2Muuv^-@*t- zO|$NhJ-*@Z0n~~HO^bcfpc6^Zt&C_EQl+v_Auxc}yhJg1IX>|JM_8evrxUJ0@H>m$ z7DjHOjwkL~l1Q)nODW>@u{6U2vu=ON%ui38N;Lkh=7Y|gW6xLj0i zessXHS!&rVH8uh4BFko(WwXrK;Eg4sqY&^_0iz752(#uPq@tNuxf60GD6TU#%mQ-) z+n8tog=`~%#RzS9!_3Acs0mWSdGRWslYKRaTP>`X{SIV3ChGuc|p_^6#%}3!VM+h}n5)e-)#HV$>FNIp!?2 z?Owt4uxy9-3MSmYb+7PDsSosk*$J(8vQ#iVhA;?$=g&ff;Rt4nA(De&r;Rj;lGYDc zj8K9w0bwEnk5C4)(S~&}F9U6OPMm^Z+nIc`p|3(P+ag5HMOcEc0)c0qRS1_OT!U}} z!fgm3V5 zXIEBKR94I=iWTM;6y+`$np;~oudZRn*MX8g;y=VlKkASe=_@lbz$)(sPWS523HZo{ zqNT&VsT=GD{x>er4MF|YR$h6xkpD(7$h{a$f*xI@`u%VCW1+!@seXs%m(O)a(R=C0 zyae~HS;8;R5`H;|;fefm7-)X^0WCDYTrwMe`7f5`kziiKJ}KJxBX*-7T;i^V6V~af z*`ut+|JrW+ri8|Klg96lLS8_&xwx2ZLm_XQWGLhXLHdnN@!zs6@83)$7w+eX=AnxE z`QPP}^?!*bZt;~zIO5(AdqepaZG>M#xXc7ISM$#gyJej(BO*>PLBFs4Z+6T2^<#-A z_+vfH2><$dSzR!K-@B-q-*irWWux;sJ_EvQ53u{st#piY-v4`^SyOQx{TVjb@hwS9 zji_4*b7{@X?6GNGS9lkOE(%^8Sn2;ZS>(>w(l2YeX|%#Xg7kIt%bI}}ax6KWYy#FRrzFn5ie#qzjg@jA>wK8XM%n_1tvE*LWEtG$Xx|{ zihhvD`GUhlUo3Ko;PIlLCh~N_vqV2v3PtR|(!GsC==ay@oUXu;>j} ze6z@ZAR@dp#3kE{}J6pQne?C83V^)45r zA3e%kUq>`Pbng)PZb7cKWBL<<^hrkfIYF+wqx`PmPC+i0rk-o?i0Oh^f?Wl<9*^lm z1xE=M3vx*w(@zuRay-gh4o&28MB;^ls{~gIa)BPx?-NwlX^?*{@>7CbmP

    &m(>) z$fbFdQv|yS_7sGN1(nWKgtX&gJ>o<`F4Uu3Cdj3ElrI!qB}o5;)L$$3JwYzpqkf|x zmlsohUhoyc*93P6{zH)KTWKE=%oNNL93Yq{SS(l~c%tAWK`swud3Az|h-T|1rTF!G3~+1oH)l3Kk2N2u={3C^%Vgn&5Q78G>^KYXs{Bn*^H$ z+x{J0A^O#VR|%TGqc@7YRsir%DGv9D|9T3y^L65I+pm!W*gxFHBH&V_b*q7}4A+ciGik>{fkV$JmV|!& zvE&-ZHJ``e@N`&S7-15E$%Cl#4(7rw_*-i>lU4?Wi8E~#9`Ibv3S={BXF;~>ZO+%< zm0-QB&(zD~$>c%Q>4|}lF(R8u z+-vcqC>zrlcs{W0lKSqO!_Dh$+L>)R?1mZvXy(gL5Vza61?@|Rj_vCpcHA$IBcOZS zEoxieraV&@(V8C4Td<2k*$H|+^JBd%pLJTp<%Ijg4mz`$@|efA+m7};xBG75la`9Ka6;Nyt@*-83#hc;z3s5vo$gH~DE-uNDEFJkZFY|--W7P*k5-^1 z&M%$@KRatv$>SxRxBHWZZGL%|Q!MS-F?P3a`-Nk={u1pRd%@N>8z20@O?qmVliv$g zfdg5!dumr8za6Z?&iQ-r)%4vymi6H!t!2H|_|&d&zW+WjxUW#{nP}RxZ0DjM{^V~Q zsoc${jY-c>A9CFI$udUcc87M3MSQZ1i#@*s7_#m^W%t;zkl0h!@M1!5f1!Fi zWeoc}4sA63yT7%6qE-F5qqRSy(HFEorrYoQ^82_i*K<4I79o;45EJk*YciUsPkkAw ze{>iWemC?fPN;r2OeP3?a`Q?VJoEOvAiEX@zLT zZ16c*7f=-r-iN~hobxL%^W&Uzu1xZcg32%cxu>$SK^dn|&+nP}^D`?LC-c`|l(ATq z6`&VG-#q*TdUbvss$k$P{Dx|f+4YS?3xk8w*f?JR*@6u!?(vd3ROv>qLjoxNxBGeT zoU{bZ3a(8hRVj%~oZy`q)H}(e@G}mv6x#d2BMjb}R0}zB5`Ka|@OXywWjm34jA-z# zU%Yug6bMs8ru@V&mONjyEFw0CbU$Siq45)woj}b95(vx|Q6)`Kqdws81#IBJX8jlt+=5%O>Q471?3E=?hhahMU5)q54ve#Oeqqil4e22WMEHRquPmubrG_JHm^ZsS2g{!ger7Phf|D2Fhe2ux z1~|1c-1K|U)UdZOd>6#XFYx0nYR@<;%4IVbn~G2pXI=V_QQuteC*f@5Y+qXMcn@@t z4DCxB9Pg)QCbTbI?06eQ3P)D6T@NOW1;9aX~w{1$yiCoWC|0dGGV`{(1N>=pSq+BHq zYG1l=w&Oh|73D)j2YxRdD1wL{Y?gXQMaZP}o^3xwhkruba@u}U1=}_-R`jM!whC}exUZSDqx#`&>3A`JsK zKa%EwXRg!pqwld>;F<4K=|iJeus-n2b$U_sGs@tZhxmX$dsK8F%Y#pDeJUxAvS;2R zV_y>OL3{Abb^3%TAJ}-{nWw7!6Qksrd+^Dv%by%=Wc~2T&B4JiN69nyz%zePwP$*i z$CY=hFN24YKl=$^bRG)?&z#4IKl@2vl*DrnKDoQ227mU;!RT*UBzWetu-EjSAj;1sdf=JMj6jX-crd`?v(7`gY2LAJcq@ydBW({na|$f#DP{%FT+5;8Ei4*5 z^ApfI<&&F{-7uDBci!wR_u&MLqK;!x;Fa`a4~x6*fndJvO6Jvxl`@X4(YxVh0S ztPebME!Ri8(f(2+H%G}c_rNnh8TIpw9-U8v%Y5lGm13nEy^0p#nX?7{>@{xmr?ddi zoJIPxZ*!w(vQF^KwPKwc<=1vR_~h1#^=@=4E#Q+|D;{>EIaGjWt`(cy=#lLARr+|u zbcJij%TPR9rN*?gmf0vJds?1v<@B91A1a#P@#-@!2h&-_j$H#^BZ zt5Z-#b#s!rb9f+$e8hHdsn7o^6kT}M@xU|Z&h7FJ+X$XHYt{9?XEJ3uq031HG%ugU=ibIfw@X9q^mXIXDs#)d29p=dlOine)u&y4`-niorAI zQ%cu`FIG~u!80F%D!V@frRJIAdj_HJpp+hbI=U?OGJ5I65F9u5Yh*yVNk|A^=F6^v zmFp@Zc@jKu-wm5~w?OA%VT_Y>mG;sd3{Vve+>76y?ktuwTvN+GgcUcp*QF>BzPBHT z$#N(rBV_Ya2yT%o&poBrnXm=PoG*OtNAzBVUUS%wk?9+e>mA6?Qa6|-9o2!8ix2(z z0wCuY+8wQQPeZ-~p?CFsaLiTV9g*V|^s#r{!Y1f4*ji53nFu+zGwZRc+8_q^Gqfp( z-xhI;m2L!d1qe{IcYCL0r1;aiq@5aS?@n>m7o9q3=4gs`lIzcLQc{kA4X%78iksYE zJ7`Jr4Q0T36mIuD$tJ#a!%;VdK8#Tc9r5D3(29;Kg(kc1@fp;o^mLBT7>t{R)QklC zh;2`=$Z4z)d#VrYak?8=thjQ4)dgHBonc3nToF z2bxEirlKQTJz+H}Hg%I-A6S_E*#T{S&^0U_v|;|w{Xh0!etu5$+A z4Ftb)j;m%1nbFV_IA55fAg^`mkmAc$4^>vD5%|ky{$VrKwmAuz)tr%wyxb9E9yk8xu?u^z#gG2V=T5(pe?Ora*?as*?>_(}wr5%fN2 zY$mQoFlLOeMSvN1#KV%*fc7xXy?|B|p0Sb`=bk_k;VqT403*_;g>k)uNNcnnR~RJt)ReWa)gkUwEPHl7NEV6O#zmXFMrr3 zd$Z-OF#Cc&dCN!6sBfs7(@^$>Jlf)wLGJvz`IWhqWwWbiz{_LJ!ivfnwPodVtLIlb z|BA93&uRRU<^HEAkD8TmydER0qG*7Z%yRR#Mfv0{t*ERjTUgUns%Q*(b2$ezM- z$FV`TTQI#Km=x*>FTHTmn;CTd3uAE7n?xtQ`Ov@vZ2t6M#GeF~U}!)_FsWnb&Ygo< zA^%)*6i)=zk2pBk37DK0jP!(bbg-S$=4Zh0Utrb|wYF2WM?x9FPCcaJvbZDUtq6R_MQH*(lat#>OOeEzjRKHl3Y~H!1_B?St(GL#fA~tsnfkwf=b+ z2!GTX$SO_=e~;;U7}2!6U{)WLeUuqXU5Wo3WE>8?8nK0mBc_^ha0}ghMG75-Y5Tbx z3m*~_$T|p18}I?{gd2f|f~IaFFzQ#Pj&d_)|lLkdYms%&VO zU+0wm8~CH(JfY_Dy1KKg!H67FJ%{c;mE+yTiUQbB*@zR0)5_RFa*=W-43gm7Iz0a_ zMdpRbqumNO(oulUUyFwdrPa0d3mYm+>ziOWzp}Xru2BEgPKDdL6Gn@N4>e7uTj2%6 zhZymk!_I|stE%dA|1-{o|6^{1%WEpj=Hpe4co;8TRN2s24cEWsfHTvhy0M~>&T#Qp zb1Er*rE|@Z$wRgEIH1>Hb?~Zr_WAq=|GSu>^D7tQFkjSEQ^{_YH7~BfVP7+RXqh@M zmBQh#Iu&8zhIAgO==OimH}Kh0s(NR^`5F6c48yhE|>4;5ks4K5*Y^-Z&j1}c3e6gc{tSGNA zuRwjqqoA;0NUUE&B@Tzi%Kou4=aiS{7Uj;y8M=IKtf6vIHIIr|;qVdpBZguLLMpEP zY@R2de3*@Q6JyeHRwP{*zR0^cv@-bZz$N}m!Sx)SmhZbNIW1>Qif?9G&exLn+1_+Q zVf>DX;@6S)nTdAsW{zVX=Y3jNA%^&ARIufB`BthQeQa?+uQm|35 zS@0sk%LKnCxJGcD;0D1>g3k#4QSfa+#X&*6dqnmy7HkJy2N3%UP7<6cIA8EwLEiq; zo{vt6w+nLF0_Dwue-?aCuotc*nLb$X7{QYSX9%7xsQm81{@Ws7C&{JG%o1YZ%{ zCiqXm2qrwsQ-0ilT%1DrXu*>N&l2Ps3Z^d=RDRhYuMzo2g46JRi*{v#b%M(TuMk`( z_>kal1pg$c*7BpAj$vJ1Z^2=L;{;C?tQ1@*c%k6cfvreeH?RcN9EA^u0yyFPJC#BSk)1aE$0r68RLt zS%MXUO@hsW=Mho=N|9FyUMcz;MP4I_)0pZf4i|;|Tg!f@3uXzbCwtK6h}=(*e~W29 zRB)7FvEXvS6@r%vULnZm=FESC;H`pp2;L{SUhwCFj|e^?$VbI2=MRD}3T_d6LvWkm z2ZFl=)k9?DSLbtJ3eUH|4uYKo4TmsWGAYm*;<^8%|-W$c9tM zg*r^{CU`LavFh&?>zc*&>!enCG?#f?UEw{gHxgxr7r%ul|0* zt}U0aLel37(w`K|zF&}DIB55Xpz$mF zJCW7jYovF^34?Y$1$zq)5;UB`B9RTJaIDD32~HB6D)o`>OMS{l)8b7ym(87F^1i7Y$@^ykOg0~8; z7u+EDOTkA4>CcAwpA!6&;H!df3cf8!*H*OuSdcdalmmh(g6#x52_7NXN6>I23q&3! zsIIF}9v8i`Ty=c~JVoT`f-?jw1m_CUDHHQG3oaAn(md)f6;#({kiRD~m!LBJcEP&@ zxn7F;hXj@XT*!}!{IuX71YZ{1B1qqj%)ecb>zybk38o8X3U(3fA;`5*v_DGlIKdMI zPZvB>5Y-%zd-)anb8Wpd%){M(UPa~Xg>&#otE$eCc-idPxc|4Qf_REzi)DC7Fo&PY zis#>3Q^S{dQX(GEIC<4iHg2{uZb8^&iVvNXU(rO_mls80Q!?HYFnzxp>0&$ZEQD;8N z9VqPbVknROWBd5J-IVuz#F>ZJ z)!b@u;mvc1*_g&~kD#&3&E7W`P_Lvgxv^phb|rC9)l2aK1iO9xtp0XDnrYv!5yxDv z2dM2WlxNRr(_f-BJ)EvN*l$pFf}YR4SRTinb)vl1Z4~BTuU09(ub9WSD?cMWy1w8JRU9siA`kR=eDnAf=mux@$?Ukt{d?vfcc;6@`$xyo?w-&`!5!^_nWOKyKd_@+;I{jtqdSfEcC_tNQ*APMcEzb5gj3T#2&X*_{rG~1LvZ@Jz;3lN_`0)hz zQeC1{-a<;@;7?E~cx?^Xi*a7t2{7@IQ)7IoPG>xpF_!upkrDn=6+tabeSRkAB-T;a zv6gS*2mVuEhe~*DKS2i9w-T*_|5P@}$6G}BPi5S@8maW3dL4vtASArDS!fpgr-o2| z(l(R`|Ec@owS|P&)(@uepL!+B7Y-Esr)EH_cx`mP1^=nzD4)*4_u{qj{z3EFUPKK3 zQ#nxS@8O63Q@QRu!do@?Ph}i+kk=ND^V)db2mh(M0pZANs1W{BwU`>YnOPHfZQ+CR z+A2^Y{iiBk+cPX6&TAV*G0tntq8R734P+1Eyf$9S!+)x7OL~M?zVM%_#mvY@9Qin} z?Iji!=e6;%ApECltaGcjRgT`@Q+g~Zhd2JU_jPu$q z;I4`D+Wy8?$9ZivtSFJ!7Ea`~g%f#g;W)4DQx+BHweb=h{!?vUTR6^ZJC!3D=e0e^ zy%guQ@v$)cr;dRUd2Q7+j`P~iV~^szwx6-0FT`u(-G=s`s(5XSSgyruQ~pdXUfa`5 zw|H&aSh2-xdy}28cx@zp(0?k~EabI)pY|57Z3JbD*T#ngVT;$6#!;|%ZM>48|5SY{ zDUQyiZ1LLs%y049_%I-B@!F2!Fj~Aeekh0jQ!hq2XY}pW4c6@w6J+?VJd81+XVLW%kkR6 zhSzoqtG9S zm#IHRu0&oNZZ=zaZNEUAo7;k0)n0T4D%>_+#m5kO1#n*~+_oDb^V+Z1aMUIYw?`oV zoVxqiLCtXc5Hc?+vyWkUM|F45kQUemcz^+fmv4M8&%>-luwgf#a4W zkuAr&@ic_K)$`$zwIq!?q{9ec~T;^sb^cXp(rH(Q=`y#zJLLL)TE9d+y&JM=S>tQ;d=1dWDr%*j_{>X*b*5^^c z5cOF4A8x7=)H|GAZYpQOQ029Cx2vWOj*5-Y4O1V8{)5}qrG;N-eqLwR_AiM2VdCWf zs(;r*rB1feDRI)+2a~d|t-~oJ#ntX$`?vaaZSQt)r>C5ea=N0&4hT908N$pQm;zcZ z-=hw)9lo|^JT(;0mdA2&3^6wj0@~x4*~=7!%{DKP7YFh7GYAI zB%P@Qwiezd3G)#YqmdEagP8<%nsTNRZdWFaz7|F{Xd%$T$U|C)_duOS$-`p#97C7S z5OvMpAk0)LXApGFU?j3SKJ5sieh?QKU4h^_(+PZl>IeTy@x%D%0eS*QkU2nHWRy)I zVGtl2YhI6lK{6_zI@b?S%2SQ9of-}{0!&7u>})A{{j9b$OWA6fWhq-NmAT8oy9NPN zFEeyxeL=(4CbWw#PM1Q--e%w_>s7wuoMQMFTht4|lx*}xh>Y5Yz8Jcaedtes?&N*wspH&eTmDSwX7599 z>)0Q&Ek$HG0;enYIrkO!`wa-(@pmC`uiM)%EMXn~`hP(-Tp~y7U%_8H%#GUzV=#dY zhxZMN4QH{|Fst|C#$hMNxpA2AT<)$paIM@pXj{2)xGp!`IH(W6h6B?oJulcbKbYii zmlsU;FCfz?CnKYCCYW(xx&*U^gsMp@qg*!@}|1l*@hZGwiXun&zZk3epdDT(FI^Z{4bES_T}2|;8ZPe zTndJh4)U+2Y-vAy7I8}v(8$$Nkwar?HB^>Wl%k`}h06EhVds9JywuJH-$y39CcKn> zN#}n18TUz=Fc%aE%2QeRaZDT zhQalTAH-GFHONXvmY%I>;#WoQ!bgyB3Md^tN_7epb@@EKthC2196by6f6F6YvLNq>)8$o{JDGGnV%9_g1jK$@1XOjN&yPNvYLsw*ooG>QP#R9#!Cxn2wBFKn#DFn&==SZV2$aZ~??h+#O-7anGZ zX@AaNf*rOuKP+ZlQ}gM3_(JcZ(8a-(fp7aS0Xyt4A55(}iVu`OVHFhbLwMgD z-~4LTjxA?8nGku8&oOSx2UF+TL_Qc!IlTA7yV^v4NK5&da`XNtZ`6Z(BSM+O$2tO2jSnw6W zcLnk1PL+peND9#%h3SI%f$V0*`g0+H+1kV+` zK=5M08wJ-0-XVCm;3I;M2|g*fS@1)_j|BfI$d?an57&qiQw2K;b{32Y^22eo8z?wf zut<fJBw z9}`*e#UVc@GFKe1Jg!zGa%hNObyH6yYOVQ|i%<%3yQAYiIKTqUZQ(~dm@hv@N zUtJ-e1F0ECkRdyoGi!}D@>mySRpu9utu<1aEah@!4-n51^G^b>g* zdr;Qjag3YIq|JuH#F@6eJvi;AQ&t-P?%4IdJOJwkV8?n{ANxV%eV|=lGYn$Tna!l} z@0DF%YMwp^usmGSwU)O6agzs8=QDSysjv(7>O(|6~VMmzaNG|w&k7R zFLNLL{SMOY@@5Ry{bPCDEvCHhBhEJDBXG;dOW$_bA7*13!##q=?%1A(#v|GQJ9}=i zUTzN{*zK!8`_iFf`}jn`wC~r5qkHuLwY}S>JhqJ+(V8Akte100Jfh-k{mxhwBIPiS zY1DdbP;Nr|{>X@Ire5o1&Ir(mVgMk&mTG@7R!%u)4v7z`NM|~kHrdx3>yN# zc5oh1tUy(^7mp}>^RGVez#_UPb;|u`ZJxAsRjU7;R4>@AXN&bJmGJ8x#B>5d7`avr0N`_lLS~Uj4C?k5BOLap}=( zhku9XKdL?hS~uU#v$fx>4@2wAhfa7!p6{W0@``$lfAMe5FV!`y>T1B{^+xJNI1}&> z&UP7W1HK$gi#WGv5KcW=*2 z7V)eBZV^AE5a$++MP?sqIfh%r6`O`zL}w$0Ta-+FE4Szb)uEpCxo^&RIHtzp*B$t{XtXj-{NymYm=MaNK#bBm6k80Qx8 zdkYq~Xf&G^=N56fti>(bg)Um$qE}c{oLdy4vBfRoBH}o=h`s_WZqZ3-vCSQZTbx^@#yid}dY3JWbBq4Mmc+S5s$qxDEqaMfHQXY82g2eO&0;h6;uc+p z>c0TDh|gXvZqd`MYQNl~$uy30i}*Lw;ufu>80Qx8D-ag9=t;IZ&Mlh7ioPJX=r1fP z&Mo3+0QS!<`jpLxbBlh)y%gsbt!8SRTf{FoSll8$c(%AjYgo}2;uaMlr^PLr$8s%h zQ3D6V;uby2bcNqik`DE~dT3EmE8ii(52@^;z7a*C<=uBCh_k zxkd9RTil|5;Php4i*96oi(B*tN7dpMRdQG@Zqc8aZgGovTqSUe=pitHThyNln_I+h zQY3JTE@T;BZ*I{KIE;o{^g22a=N74RiN!4%!R}eyBHsG$ms>O&<;J;1^eAU@i*9FD zi(B+77JX>kqH|f4#Vv9vTil{c*&&Nt^aS^T#VtCARa@L5eqh7q78P=yTil`u?JaIm z8tpA^ks@eX+#*F=vAIPfSfI@*FBaVeWy^e2wN7vmQ3tkcRZ`Xk%8UvAMOF#W2yMaQuRac4Ap^KY??7d7i>4sI??Sgj3v9H{EcN_P*hZfE zIL|(bM*RGZaiH}KYry7?#Ix33i%~U*M$h7AaX6GQgkE&!>=r3T&Tk<Hu??Z4b=UbI?XnkfVowIkfYc^ zW5Zn{5wdgHmJ(IouOR<| zx<-HDh3w0xuPL;>gJn!#&^8-+Bi7KxT`l`4@*;#D#X^Q`oianEzkUbEIqU#Bn z7kW;ge)w5}`(>Tubd_TQQpUID(7LlApQ&;zM~-`2b4*t`Rv?9*19cr*cRl25RSsU6 zynr0NRjbZWIkcsYZ-f*lM8a$F z`#}3y08MWFDI*-;2ww_?yhpLSeMP<$ zQhWw0+RsQ|5(UtHICTz_dHz?)JfO6+@^pk;Lsw|6e&Q@wXsvdbu7<4BcOOI=d{2xV zoBkGGXMiT*4AktKK{jzlGi`Fgv|*h>tpVfIaB(>BgA<82n2)%FMldWJo-PwvHm=X- zhaW`h^@a(~tt$f9GXw^|v+%qYOIT_P%argfmE%;xMLNfl7DiSn{ba)TmA>9>VT4b$ z6)A_2-)O<#@)RO$CF;g+n{6Xxka7sL)1;huj#HpZ*wg{(Od+t$y_}i3=)J|x(G(cC z_gMmC1~_V4qPQ^Z2lRxSRrGYidIaTei;*X^;A>$-cW1HP9lo?n*w}75A~Wr`os#iP zr*=fEOR{um@K_Ss83gW%ARH(a_EuwjiHM-?F!~(?*Ex-_20?iZG>3 zVua}kph^++j^ItN+Fa#8Y#QQVB#92ud5G31C6i<;21-dr6>6{TQ zzK=0;_Ek$jHI2PR-t!KScOQ)jr~)PL(*5QQsE&x)vi+K=X1bh^wPh zMRd}~!AlF8n)3;Y56F5~eNs>~T`hlO1OAt@j4 z@LRX8i20Pnlak(e@S2V3F@!+~`3OT1iV#L26eE}|hDZ*Au_;Ep1YrWgLZSCAh-uvj_n*KD$Sk&cLy`@e!+4;rd%T!H)LPZ zO;}>d;@T{Ms5Ihhz*Fkd3#_43@|2p$Q|g`3Nzs%>ft54Hu!TZ{^K%Cc&Mg?I*f&9V z$pUXE*d;V1nAyLLsxX*2FfZ7pBOo^z%n4==unjcrNVAImq}fBD4s{9n*DL`IC>HDj zvXCY)ZSm)Y1{=cBTBL$1ROyZ)v#3WNeMYr1i=v8I)IS*Qy>Dg_(nEP<79G%FFJ=)& z<)l2HZ*O+d0r^D26gVKQ=%9=uVE~M19;%2e{|!!{{x9&0N)I!N{=JN%(nK=Ne-B}( z4aw(_h(miZg%VjorKSJJX+Q_Lo*A65P5`{YIh9SIOI6Ze7id@&6^^)*vhBc=`j7aQ zS}=m7%EJz(+B%p@#kH&LUn*u@_wus$zlA@PZnaxKbBQayj{cbXc;{t&NG z6X`=EaGQqPvant^#Wl}d%R}VaBI050kRFHIF{m7m9}B9r!H^I8lG5Wc3wQM#pBn`a z`;yY*aoCrX9*3{Wm((N4y1bVJ|3btYFMf1~_zn?^CI2qz4xT|#4hSX@F;6o^&Jye< z`hFr05-bq?D3OZ=$BBNj$kPPR5WVpwHCObtqBlOJmWbZ?l3FdY@ga4a$m<0+2tFbB zq~Oy;^yg)fw+Ox|`t2g`6#Q890sMjHxG1g>FhUvSbSA>4m&mzdS0FfC^rJ-{CwQpb zqeih`EO;If^<6|n{a1?qYQY;s{{xZl6jYofCXzjNQB+%lD! zS#XNrnS!N)a|LSz8wD2&E*D%Oc&XqOg4YS&DEI@xI|c6-A z0n`5~$h8NQ_Xu){0p)Z-E-#?W?|Txtpny10kc$Z@^Kmzk%Lj;DQB3600pd-98wEEB za!CNw`C(z=M}oTrU0#1c9~9(r0m?DKBL$BZc1Tu;OKOE}kN-^3X9;!{>?b%#Fkg_bL0Es0;3&aj!4kpAf_%+E`{{x+ z1ZN3W2(~?s)Qi4JaJk?L!Igrm1Xl}QCD``7vR3r#1n(1EFSt=~li(AAPYP}pd`|EM z!IuTM2)-e>U2vyhq0G-r%4t}QEqW)f@toSGve`g*nN~R0#PER^xHD2;X33k~2!BXa z#3Lj?^mjay%YFv7v?IIr8*%YAFM zfJDXuP1#hDW7>?rt!6W6$3lTW!%ndzOwYz^I~6@*wIw0)rSMvY9s3K(@qO7z2Qro1bmu*=KO z*ZpL97|Pc2Zb6)RkgT@x;70A_Nm4eZF{~3bb|ZW4n;Z3@*a6gbAMEToXm-s{kZQND z2nDA@$M$tVF#UZTadfX9ptd*Kl*hJlBU;nL$?D}C5;v+S8+I%}Hd7v-r&z=4OhEg1 z4P`cC7eC8X4JkYXA4^9bIYLvT4uKoRwqZ-)M%AysCfs|o^FeyR{UF^xZ2Yusfph1) zxBOi9=&^`R+vZnN0O?~9pSCTeWIt@jB0g9F1J>$rLIHb<8; z@)5)$kXx1{x)B7{loRgZRdTOYF@zQ($LhAm^7y-MdA-UB84%K zJ~!mYnEBjrA4n>v!=R9F#T@8h;d1E7+jo-a6Qa z;Ogj`NC*dlxBGV@l5{h)!L_N6F-|{F!8@kzc}%|B&#ZoW4GR9S%hgCr3j_lbA#zZVqaEY^a>Tq&Y7o-@ z0!5ZLILwRN$Ves>WT*>W?dr%Ylo|t(7f^#&n4%jHjy#DBUSXydQzO4;*1|4YOmAP> z?07>`)RVC6Obk>7tdpnXXA6Sr8;-?fbUeo!0onrUeiyCvj!ZKB8_4oTiWrD=VQoi= z7>>-tOz=jDm>PK#1$ak`m>zk8;xQs-MxJ9)$BLL0;pL`REMnJ4h((PSG3Im_fSSUt zcS874wrV}=Ju#Vajyl@tcoUN-`m>k2kyBap$*NZif3W1y4=I* z@E+o;UGJPr|RGQ*?FY zJCqUf^FT+s34bu@ z>gXY+gN~%r^P_7igO2oLl|D2|?+za5NIJbJO764=I?`h*eN^-sro+{dK9v+lc_Q~f zN7D8sY6-UoS4TR1LX>`hA{z%IK7R-XNZ`tJd2PZ8YMD}H_UHY|i1|2e<3`B;M<~?U zpR-UM%s74Uxa?qLw62`p1|5lRsk2^1<5InBH#`#-QFZPH9f<;t@#tjs7jz^&f`KUS zu06Oqk{N*-+3{e2#b@yrD9t<84d2P4{zlVcw*v(hHI$PLbR;c@qNE9Wpd*b#F6HWo zkq2Qc&F;L}gR7%|;+i-5E1H6i#J^@Ns+cn9NP0g8qTgmKK}VvoFFPD7XNNxjFhzwg+^ih}!4N-ROC25a>wVlwzeDJ)0JAb;K6>mh-ZQ>JnMLHb;O<9Whc%<9_UD{Ro8!y$&}@U9)%KgB&xc)JPoMXjS2Q3 z;=uq9^sX)sK65PmMd_c$Z!+iL$B3u~fHsuE7K4t&Gap-$33uF+Gnn~ji2js1ItFtm zWu6V)+mQcE-CZnka))mrPAXL%LiWQD+$pKlvBf-#K+)dqotBZ}PwSF)YN)+C#ZAWq z_T}JvX2(E@3D?QuB;ZO>QgHMH+rfy0fKUcZMxkY%*a~kT9CcGtKqE*wQu*&liX@bj z?7GKixX7N;(>XqapG8Z}NU)FC_C@Gi8Y{&3^?^OE9x~t|#4f)*>|2=z$1 zhKDNm*i;T$_W=5FObUlmQ!Z%NqaVhqE3W=xDuQ13%yW-THSCbSsdTtf9J+Q43h0&K z0w(m+G1!6G`(ToAZ>!rI5;ZWj)H-*>Q!hfCvyS@srk4ET$0jfEW)`FgLU#ne)6~?$ z$N()gw=j~Yg}E(^aN@$Orez8u(-DxJFjwj811*d+Yay&Wgsjj)Di5TDZ8;>Lv$~kb z=7yXd{=XOZx9s+A>M8MRPl;E%z^-VP!jkwI=dAaO81QtD|8>R7Vw# zK0NtpAa#OKJ#MEF@F)T%rxH#;0O!S3W5e>91MCV$XCt6iLKTAFX>iq0Ez)`dM~yka zu3(hoW;;gds$~4A#}35!xkXEf@{5=fU(h+lVRsa{m1VQ5XZ-6|c_*%}cM>1eDCZP= zxud{tjk}}3d=+;Th_$+-K)lr*1*WTUM*+3CqrhJ;R<%#(6r1r!*q`B#xtVZK;Xey2 zsQuZo7?ydT9qbIB3Q6OFk=~HSU3%C@!LHT&-aDqSCT8V8JqpZZY!-4b> zT_jvN_|#hKipILqxn=V!@J08=@-lwcy|MaS{2C7gm9>=(b1LVTpJTp;-sW5Ii_06; zx8WP*qxWM+&N#KPvY~NCc}-buSwnuojHgH9J zH#N>UZtPh7adWlcbm4q{d%dzEroK{dzN=ne*I3WUoKBUdbhX z#=N<%z7pSWubqvyEiO0CC-}K``Z!2j*eccOuk|mSy%1l2*Wbpc`P@3(uIja*iEb^* z>*~&~#yFKW&Z${gsf$!CuBs`U)992|H(Spjg{yIR-mhfn?Yqq;(i6NkWstVsG5(8N*AKqA%*O{{%Cy_C$bWoD%4`k zG1YTa%Mw@jmePF#_H$(;KKu_?+FUg2v>AN$;d`|%mi@pgTh&ywME5t*T6+bUUtKpF ztwK{us}{~LmoM=rTI!{@`MSa42&A;Eu{{38eBCOv2`z9+Cr%oBV(BzzF?zv%v42?2 z$#KSK2yu4^32sYT zo3AH{`i}oxu5_JWXSo_s)o9llvdmSFMd|qCCyrA)wTTO4QB7%Mf=VB4a1VetTL~T{ z;9>zQYpdsDKcUm==#2YXK%?p_%d4xZD=W+qpgsgxU!vSOlr=A|z>ZMoER1wzB?>7m zuUlx2n6n*g;#5{*L~YLoRXE_-Qr$=0Z8eIV%(co@gl;Zh%hjD-T2sbKWx;-Yr7hP1 zxB8T@R|qGZpkX5J6BgmjQOzB-x3h)W-0f4SMWcDi)VDROJ@NawiRmHJ+Y=n+)MQypNKDWGXep5qPdDGFD=kP$GPBY?9_!Aem-v}o+&s_aHSw0Q88Vu0Rqx#H04c#&kFJjeAIUp z93(hOaH8N0!5YCOf~y2?6kI3xu;Bk^?@i$IsOt6ccituMOqyxaCheqqXu7XyTG|3_ zNolDqv@}40f-PyArVDgQlWrhjDijbw*%T3_0vBYFMNn2*l+9ZZiXd~@Iv8z!Y70;3f~rHu@ADGa$$erSm89`T;USo zdf}Uo5;#`s*a$D7;1bA4+~e_>lBZN`6N8-_pM#`86R9 zBUT>_TSK15SU)~9Ayx?Ou?A#5SfYME;Y{IdAs?bJ{wQICaGB7KgNV21{6IeXV*1U( z(}iaW`EHx>7YZ*GULoYuSjOKid{Fq1@MYnv!ncL*2;UbPp#XMDc$@>43cCyK_zFFr z>N1|+vnNgxP7&_PMcp9%@xskQzUN~8Glk^mP`*(34dIo-Zwqe{-Xgq5c%Seg;iJN5 zgwG4Hn;UmA-o6m6+<5zs;qeyrD5oCJq2ulUQ8;rv^ZrjK&GkfopbI}1oH_0z@xtxK zWg1r2FJ8Wnz}wiz<0X!(g#w406p_ndG^`Zco7X>p0#~XI;W!V1sT*)j#CLS@5(gJU z5r-Lf5srntW{8(Kcr+Brawk+`x?)7KTpXGU<*r3I&Vyj;^PN(uN(QvVajPIF?G5hd zj#;$FX0u;t_Y|yg9t2ZY!5+tcyu@*>P$cb5NZ8{sF}BC+v^WofsoP-hXK9Aq633kj zF==lG?6E$qA9kyPy-N{ho@%UIzS0H9M((6q7{~QmVVtfQ7pi<39WQY@UN15nFRe%y z=b?`6;Bqt8Wc}(A?L`#|_2cmrmr6|lTW)~8v9SP*%OWPaA@w5CRYKVfdR}9*+)}J8 z6ZQ&A7UK^^7nax_^CZ(PM53n(soKgNHMRyf)@@5+KJl7(Ch=;EEX*ffQ$22iX+C^D z@g>8oz?^IEU>pmhRQ)UGmAwAlfn?3)(qP6dn||0kr7Jh@JoWd}fQP+PqHqbqzQR7j zSqppnPD3b%ykyn=;;}iel=NCSZSl0S*E5+;+q26z?>yygZ=dpo!S-n`JZ$d5%=VKJ zKKYGv7QPOy9H-uM{hamaZ&1<=J$oAJS()e@20@bJM8)8P)f3V=zRU+njue>8kw}0! zz7J-)Y|du?UPb+!?n_LS=OF=vInob6n4`l*8)0rDGjkGD%;mj5!&ydGm(OEXKg%oZ z%%@No=JLJ~s$BL~{1??BgO`agv@w@A3(owM>Shb)s}ak&yj!93vqe{Aa|x zQHj~`XQ(FT@^%&Q!_Syl?!=PtRA#N|=|m&X`C~f#!VHl-M*>pu3jA@(S!)~0<|N6S z%llMp_V5lwU@q^teFG@&EioI06!($nhed3`M2RI~$hu6DSQ=hJak9kn@J%!kb9p<< z6(O%DFqgLzdxdnhz+B!=1bGfeJvWy(@7Kb|vGp*Qx81v;*Y~A3E1+oPIh&gHAZwVB z=Qukk=JIAkGgTzd9fr`0NNr69d5#VlHkWrbigo>cbQgxXO&@2?>Wf@e(BZ7fqF|iG z`k_^9aUXV;$a6GYJRQ+oRRXw@5I~+ggH^>`-p4~U4j1O~W|##Pvzi;@g0Oiw>PksT z;9TBsp^hZa`8Rh_29oFeTjG&G@|=IGBtJZa)x0er&xho>TTuq)@^+#l&-r(BKFCTg z4QDd(_m#II+(GeP>m`!sS}5M%`&?9y(+t?J9R-cot1P-Z_(JLA7BYicfU5J4BJ^{HJ7UTKHR5;~C|h z6<)%v^lb56*50~sGh?6c!a2N2o-1az?5o7}f2U_;Yi4vv;Bf+68&ejg?e%Bs&A-x%JkfZ1iKsgFNSC zKRSU0V=iwemqd@C5YFZ8@|Q+eQ3iR=ZW2MB8_o0}&$;;O=phvEgFJU1&T{Fhu@Sc? z=kj*(6C%!X%DKFswD^h9pIAP~bM8=58`aT1$a60JG$Z(ME^ikE}hYS`ykJCL^nqEEd-F~T9JaLZeUiB=iGM8 zMr+w1kms0~gVtF9X^|5UZ@*I1db9s+61;}%oXaVFo*1*Vf z3~(-QnlSQQ57rUnIi~=5j(4P-%iAeHp1X=EK%R37kmp`tH9?+p3XtcrtOv+*u9SyC zo?8GTtd;dC$a9ogDU(5-qdYm5NuKjTo?8J$v^R?fd5!}6{1o;X$aBY;4DuY0>J-cr z$aAe|5qBiXJzn=gp1Tf;o;>PsE^lt!o;J@q$a5^!m48>93FNtBQ3}X&RQ2+B7_iZe z0k#d{T$Vd}FYh(#*+yvIHvJC#7jq027pnr`x{YKDK%V1~59GNovU5P5vssosxJvXz zJg&z`EbDUt(&W4$Fd2YDM@Rg=oSosbl^3CvsY^us}{=PSo@J??~OMz zKZ1N8bqBKk6FQ%abZViZb|9UVm zqZ8fl2Ydw)JCWiYtOGs|fo>il)`4-#L6<>G*V`(rGS!C`_&1P&gF4Xz-%RndeRLu* zQ*#iQjdft0(o8i%(|}c`hSCE6Y8aT?>9?_|Q^gZ@uX!GV<{Av0`E(`bsLC_$*9Fp0u&JFQRkJ5WGLpD-P9 zW%56l=}2BAcD|V-9zAKoTp7C%JGbvDJm~A1~lqa)FrS zG1@^TRY%}n4!&TLa=G47F1e>6=7g;b%)knUA>nYRZ!$`u+vVyA%S|u#ZZj;K+6ZKY>Y`)<{@omHaqI2E3-LSX7dNjJPO7!)i9wIE6Y5z zK=*V91EX9r6+6xjC|RV;rCMU@rR%@>gj%d#>IlL#tTwAQdx-X#1Jp|fmtaMygr!(9 zKewY^Hak6m)n^V+FXK*2QZK!>vp}2sV4D&XSU16dTf81Xu9!1hDzt^0+7A86{IL@G zS*lw+CUZ#>`QxKFwpbxy;Us|kn__Lst3i-!yYk0DG1-)f{IN1Q0e8w{GM6+_zKvs# zn|-mf!V$OH1zGpwU68=F{b;h?ppZF@XMS;RgtKvWgneXn3$}mCV^OZSxh%>RH#aUL z(G|TAo3@M`EN*Fy1Hic6aj|ici6p6HdVZQIlcFEmKR8`7NG4O)G&hc#xw>KH`X!D3 ziV1?}uUgcwe8uX2jqR4>T0UZ(SFZT?Oq;wLLak#b)~_8i8gw2UQW{pZfaM5c)X3!= zH6I|@V&gmd<2oe3fFgm*g$e{)XbS{eT)e~tTd3P8wF!c49s>=}7jrg7GkbvwTb9d2 zHh*%?%WT4|!-GMXU71bi`expRw_c{a{6L%2ILv&m2@@U{jkTz^+DDz9h|Mut zeS~yj=31-dK(LI(>5chuV!^g2uC^mKI$jrfqoQFJn2yF6UAcIvV*`uS3M!(grj8d# zqAEF!q#2S-+K#6B4>Ezdx!XpXjUXeQ#*9QGy~ga@nA+OL_!D!qjoZj5v3MQ(QB+Ur zSCP$_q&7pwH70jDDxxEL##=-*X4gKjD+}c6Si@S8qMYE8 zwsAmXg6J;f;7_JW#sFLeBK2w!y%Tg*V}TaP$Q+;v3Zv-2AR=Q-IL@>q96R2wsE-M* zu*lr)iPUX_!uA=*9d9ENJF;y3VYAk(Ue-o*bv*E0xb%)e-Nx{Bqo$3ws=W=o+;${q zju}VZOmJjldUApL{I~Em+x9yWHbuLR8P<-qo!~ovoF`1KKX}TtX`+f-XSLg5W6uFc zRu`|laBNGsL^v+B80TW?7c6O*wH<1b1ZSH98ANX*+$L$rtJ=1wdGB70fBZbR^ybGe;^}>^drwh*)UMl>S@HV0G*^vJs$>cuJ z-mAiQh4zpadOi#`9-{C7;X>gtLgS+${mGKQDZE~Im+(#D`@)XA%R;{1!r{VwgmxE( z_#-7R7j6`uCj7GSKZM^E-Y4YqN|y7MFpbN6%AJLk!a2hE!efP-g?z!vd=Cow2|>zl z3o{tzl)DJ`5LOFU3i$$`>G&x@;+4W%gbxV$Dvt3l3i*+A%J`<6;UwW~;Q}FP7fg4e z@GRjsgx3o16#iKFGvTYk_k>}Qv)5ZVLO4nImw3OM72h8>L9EYc;l9E-!g}Ee!ZU`?5| z#k}8Pl4IWQc*&fOfcENyhYRNm8-&fmbA%TXvCY0A^OAQ6Z7yW!-<14&;U9_67vWgP@`{CJMAXOTLI(Dd9M6GVt#o?{Ckgjcy6M6> z(jO{3TKWdzGT}zWe@1wU@O0r>MAYLP;n$?USa_B6*9mVF{!sA`2p<(bE_|8@yEa!c z(B?=+KfJ7XnXg$Vk^2=LYs$4`Cl6UhtY-PIN%~)zXg@?koK?B5c-4 zKUcUwxJbB^h;(Zt$8#oshBCI_e+Y3Ju<~%&F@)N%R2cJj?b#dZRV)28;eo*R<3c!PoIZv2NIfC`RQO-Q7lpqP@*OAB{aMJ@oRrIi1B63_e38lc$wI!% zqHZTOD4yfuB~Et-6b#2pZJ+jh_;|eB zf&|I>osj51-fze4<@pZHYl`iy+r?g77BMkAQdc5fC6wKu=e;cLm11R?iSA1M2;;9m zbnz0~W1eKXGf}^%<3zwX9r*QQ_N;7M3jF#pe}P{=X3U#YyLw^n4L|oL81#>HY?{_= z4EiqHZ+JIVd;ZSOSNZIQ1c6NT_oYvRxOx=Am_BYp`S&#RwCA`6Z z5Nj*eLv%Yh^>p-V#K7Uz2+HH6c{_>aSw?GZjT(}>4E`N3Ik0yd& zzbB1clVR2j&!qY5d)|dO^6Tva%Jb(!+lk@K|3fI~W}Q>o6N-vpl>Zhm7V>-NRhRCl!3!&o8OoJk< zZP;lh!(#tnyniutA;(0pSKth!!ud?Qx5R8Xnc_YY{gBrb!9;E08d#FLGUw z4Lh>livmYY_d`}JSlox5C4M~(7axtxTvY<-z7W8#r<<}LtoP4_7;eX3u%R=&kQeF@*55DJjKu+@OgPXf31NrsAE%8VozdpECk{_PSdfgUG1(09Qi3Nk( zB|3h6a7X8*R&r_hc_#k8@>YapY~sDvOXSzz#Mt|LUybUe!LR2Npy0vYKQ*y`_yB9Y zE!=71;P7i~(?da5KHjKu{QBS#73BE!!J}$`w&=x< z+=I!l{~8N=NrR32`YniO)~@!)(b9Dd|ER}y*%MKn7}aeEat_W03)4P(C%TMw!LMgJ zY|-f3>8C}bnIHUm7e6C+RuD)x3!N zRRDfHcO~Q3pFo4)*K;2+etiQK;MW%wQ-R58U!e)`>t~?LGUV6aOdH_Wcd-=4ujj7d zHqxW$fW$^JaSJ*b8|ehpDVMzg3Cg`4&~Shzl2R3K&u1+W^Ksa=B|`ob6vn6LD72kf z{Q7-j83%RVqXyvD^E$MGzCR@aCZ|0ODIz;|gI`a9BVsXP158fK!Z3Y#bUxb;e!WHn zN@T+^mo@$?T4A?ifXQipLQ@=J0r>S4XzJ(83Vywli=qc<8vObL%ryA*4D3K+RlEE4 z0Q~xa*p$&yngYL`XEU05lUc#9ciS-=-M|KcU(dwk*T2hc0De6W(&X3Q#G=8kcdeKa zv6lnz>rXO!bsbTi*Wbnz;MdcH@#|NyOz`WS0{r?aR6YQ|-YLMZ z=N$I|`1MW!em#Ar0`Tjd0{r^J*lzIaT`A<(uZMZo%K8-iddjSn$>7&hK0KDmuMfbl z-wcKMECk@!Q(&Jz!9D}O{v4CRujf&nf|&xpo*RcdlH?w*2jJH~07Xw8bpr6~xp8~? z>-jC`1MqYN6+IH1{fLi@Kix{dwJaX;(eh6;arx^EX5py{UBNe zz=Ll@;sE@5S^&TP5q1vv_0=YVUw=5_aXm(Fwm$y_rQ_EZgI|9TcOEismf))g8w~` z5?MsHUrGUshe=aY{rG+YWc%xojHl5`to?Z51F}60d>!&vsXL3cpV0YA=za|OPU;S1 z-o3h9gYaI+vM1K6Pcz*!<*CV9_G3j%3+8ff_1<-5NZ*ajCCMW4Y~%J z!y(PZin9<~Z4Wj1$Ey-=POd`wtj}S`j!2>yS9*pjv3Z2F+Ko!W7#; z3mN|P!|K%ym`PJ?$Mr~aE!H7%q_yQgp?MH1aZnt@Y}9ozL8C&+|z099C=3 zTL^GIn<4#_(%R%>gcNaw2gKHpDSzGALcmP(M z#aWxl%sqpDD*-|#Tj_g8E|=?R-RGx8Oq#U z)Ys#{%T&{!0ODv$5NaswOJVfs7)F^N6qQgwqdxH`z%KWH&7UB43!pc`F5U!(;jpxO zUxM~d2=FIxjt4_`<7_Z2>19x9P7A~3^k9=lW5mPDfb(2S9GT2Ow*=N~)UHYl<@UY` zqj%%0fV~Fi1vfeLQWxgq;dsemKWXQi;EuO-1Q(o3;6VjbK4-TwFafKVnoF>wL8^{0 z3u`9Tl-|m~QBKGf$oGgT;wh)yvKSI5+yqvwJ!714Jn$#I5L}H8A@GO^j|jp@tnie` z+T_%(a)%M7TarTvb1g}8dMg7g50fuvw=%HA2_LN7L`1-4fDl)%%~63BL(TXvHw8Wy zbk#eWFxX;_Ah_yn^tQ52G$+3V2JJwaI+Sn#R`W|>|INdS!U^n3`6V#O`X>Dn+!IOG z(6jey2q0L*I&dvYz4<7PmxU!;h)J8rgNrEgn6?+zgpoF7GHJ?VGMDslmm9fE={Cu3 zl&HiX+ErqA$ul1F_rtntol{;Vw2W!z&p^dMQ_jb~EuN)v%0fL-9u>PNJyUSgByARy zAEfS2)?w3?$1f#E@97*l5*`*9lu5S^Z1xYhbzsD{xpm;oC$|oS z3T_<;7u-6E+T1#zmRkpIQkj0GM~mx>za;E^k;gEvL5%&8eT zc62Q-D~CHpCfBzpvm-E1k8HXqbHN7aGA{>}MWYa#&h;$H+_(X;-OBec=ZjoX=J694 z(F;$%&CDMCb}_SS#w;gX&-~bOWimHqDvS0g8VMy#J$Hh|!Tkb$ALZ@+K2WpF<0YSoyEJGINrHZH7??J95l_mn>c=#na(vUI;P>@Soq8VzU<+q(J#ytUmt(F0dA1C zzpq>M54xF{i^}M6sDIlhIR0<=o9OzZX;H(mjqnhj4m+ZW}p3<@Wl-!o=shQK#U*tW_ zlri{Q#82j=ydk_q8o&RD*{Py1KRZYl7j?;&dtJRKQ{i>@df)+IFRxF!pWO-}X<=5|)@6_)xn%G-fn1ojrR{cwx{tH(3H$d0z9)7WvWxEt4mG$& z#ft*Bz0!CnO70DjTqR<6Vh23eB9?s6_hf?7O&87<9wJ;QY!tQ#j~8wheo1(~@SDPK z3vU}-|H$NIGUec{7GKCq|$J)v<@AsYu3I0VC(@e_p0 zgzJPS3ojIs_rUc3EqqT{g5gd*Ut1H03ilGu5S}7DPxu|-Jwkqxnfad=zAF5aa2)Q8 z7{9;pFkz!`y>N^0%ficr-xJ<1{HgFI;qQbw40M)5x(acCa8Kd>LO!r%JYUNaHwsS| zUMQT%*Qtn~DLg{BOt?{azVK4vjlv%aUlqP546!fLZg1fT;UwW~;R4|*;fcbtgcl31 z7v3X$Ot?e%mN1LAj4ZdSaFKAW@Y}-Mgii^p@L-PlV&9Xgl4IYKIg&Z87t<{lt`@En zenxnP@asbJH9@|+C}UgxP#DiCzg_8`C8AC?mpt%A>3=KzTf%pw&)}HG^m$aZ zdkQ(F5B0+&^P`l^H&*(6B~KO3BBGuL6R|FmzEOCL^evKOUz5*KM!wS&e}UpJ5^}aL zmV2e}S|Zk)CEqT*p9nkKgpUZHSNsm)uZ5iYi*{q*l6NR0zlUQz^*LcF5&Eve?!qC8 zA0e!few@&JOJHZJ;t!JkP~j26Wr{ymxK6l9cp?$yZx)^*{TGE7N`EmCZLqnBQ7(DV zY{wnKyM^~D-H#!XW1*d&k^gDQ&k0`;{!;k5@NJ>dHIa`OZ>%SYqQqh$`EZmYVWqIY zkR$=dPZCZO8j}Hf5(XIGB-|+cjL^>ih(A>_X<1Bvp73Jfr9w`-%J^%AvG2_7l7Ap1 z`;+Om3!e~@tU&!MLQ)ebn{O+yi065n8%R)~zPpfQ1j?g?wL-hzfSzmw#vdgl>wxka zpE)kM7 zKsolAA#s2*c|Sz+ok2OI4^XZXk}g1*6aNvLgm!%c`7@F~DdL8K|Dt?A=matC9S0uDIPdHz=P`E_6T)0x$BwQzK6`mse*Z3IW zM&=VABlIv|7`kN;0GD=!yIP(vl1rR!IFt-?+;L$#ZqsV@15gaSc$!VaD~x4JxUC z@e;??Ly;`^t3#ncI+n|Rh|6t8IL?D$>Nq5*WI#(Cw;FOgdwADd3LWj?60%@#3&L?8 z1XC9x!PyLGiQ_gyPTIQ?_O?SudpyU-^}7J!I1hrUA$S-1ERHqt633kfMbh4;QLde| zhpsHxy9{CGsm97B+XHj1#v2ZJ4lfiML=))~^-yD}|2r z<8zg`y+1-2&1(YKayING$13Z_g_sx~sr!(w5=y=*#*i?3w9hgV-IaQ=AI1!H@e3_V%s&?T^qO9&_L6 z=(_!achOh-_|sBvrX1vSb%$x0xAK|un)uC*{PZ2aglmcVHtY38 zCzo`^*7-8(HY4s0VY&ek*&)%MkTYIU6~!}eRRUG6yvqZGhWhGqj-!m9J%Od1jz9Pz?SKlCv*W+$tH|J`m!MYgLt=%}Pv8%J zNDSx6`J*4wS0R`m63M1P1F8i-BwmLGoUcI5!L!x_vdDFlT=^Us* zE)Mx*2!2R*;aZhVrHg6gnhdk1kD~GGdp?Pz^g}ueI&>(X;dEj+eFsADLt;mjzKlQm zA$5Q~=L9&#(qeh%@F;NE=P3n zh4|Y8Dr+0c{uC_I59wx>{Q?c_6*vQ_a5TleC1#z&%03ePa3otWQDR9*-!S+gsqpX> zijyUlhi{;X@I!L372$7axmIGYaDOJAA`yN_osio6km#Qs_QY0&ACmcMqt{PkAIu6U zX24nxIkyP>kk~ND>F`?02TP_O(iX&&BegXden=OfH1k7RNbB4`f}^`I%x%i6boe2; zie|&-SnoxFbK!B{`G6l1J4=2@G+azqQLZWhZV?dRhx8MUJNO}84KchNfAB+Mm<1id zYHo}R!sg+qD?Jy*(+{Z%Ipv3>4Dv%##pH+NB=?;U_#ts0r61DIS=8+k3w}r^S;_7@ zAMitpx5Y2m#Cxrm=!dkK;{CmUi0Y-`hjcbK&4ayPHL-vA7;C*P?1J-tx@vGpzjpW` zjWDs`hvW(>_#wFl6#S4}xf8?R(bVIe$5`IlkaN_-4{5521wSNbYFapf8~qv8c~*EY zx6-r4uUUKR!fmYN^Ii5sBKjfCV&WYo#~~5@kT$VJFLvY}Oh2T{SOOS zb;|HVqN4%*ka)vQKO}c3sg0Jan>OHwG}Ka<9};&3w~>B{4oGYy6InTIr1MdyT=qvuQ10!7h66N_l&W}p zzGaD+kHfYt5%O0+VMl+CLfe^f_~3qdXe{HPel5EZen>Zq zu#ZP;**y3mxgN|$ytSntl12ndWW#e=ny)wvcFhmz6`J}UH#Yo`D9{w|YUzjM1b2H59uDJfFBZTkg58n7oCOx{g7zF{E+rznean$ z3iu)M=?eXjoC1DGk1+-OkemX3NPNFSKP0DsAJS1Ad+oBzpGHRH?EX(RPi!*0@kYMn0kCi8t@M8 zcODxtq4dX)eu&r`u=cBCuD!b4i|{^3%qzkE$1vSKrsK(E8FeSIk86W_koR54Z($u! zflOb;qvHODFvBt3Slj*4+52Mc&pF+sYlXZTYib}LW)DWd~jf7MvMIX(A)ZqTprcQn$>$2#a)2%KZiEzyQX`2Op#%$oPlo6 zfXh>%Jfm+xM`jklbLU=^nHgc8I}3`cDM5he&Vr)J6lxZr+)RB@2?aE2x1KxQQf;4> zK39rj4gEaU5?lCpN`!(@7X(zzoG#C|Xk>2Wb=-ZlyQospitASiBT8Pj(u_~WPs zWnEL83aq@VH>kvw-8E;n{x^E=wEH>;dZWLbT&#Qag^vOJng_SRz=HQpd-t3{iEo4q zj$L(zB)$={Teltejga9U@GoroU4Nh$~%rss`wRh&JPUerDc}DN5#DM+~@14~c zrP>0pNq`|;K zC#1JBu+j;ct#QFH3RT8%X7N;D@cLAJ^+3w;ORLPKC>-G@fns(omjoIPZ{L`Ja%dqLCBwDSq9IvsFo z25e;&X;2^x$c$3tO02SUxv0TutI_-6yp+ zRomZxzqWsmwW%5X_gI_q-|vC{3H^)TM<8K~7l>_($DW*v727H9M+D@6G5xW8m6Uzpd2JD6A0J=JpBL_<2t2wPmA*6;M6cEy$Kgun?N1 zPMdDaMhz>AipF(DwnPHN+2WrV39)MyR0T;b1xe_PTX71dZ1{yb?*<&=e# zDUXU>l%6TwcrK)DQ=$spaDXo?+1(}QR(2hY6P}iJaR3+>TZ1r5ikDghreWoXn}xLw zE9<}w&mLZgm3@_5l6E<1T_!aXMgM~zHu=OKrlxxIgb{1Uj##zmm^IDwKNkKl<3Gmk zFr6pn%0}io!!Kr_^NZ=+<{C2*4jucMQ_BO+sby5bH|8GSTu=&5ElHpf-P5zk%DfyVR@J ztZx5Nl@E1MIkdUK<$yKV;P*x*06%taDfRV-?0=}MX}gbv{4f6o%G&WfbpD+mLiv|D zrZ|VW_+0a`@=__mHEz;JrGMg@mzTU#+P;ypq1b&SWeTs$KaRdCofCEE-D-0AIQpuT zqk_C`W!uy0j5k4h+S@>I_ab8hw9v#B+?b$YPh~zoK zqlKhMFx~OOvxR)KPyH3bn}o(Wh5o-Kzb5R*n>gr=LkgTMdA4xA@L1vT!p{piMHTaZ zOL&X$e&G|s7lm&NyW$p-`KpA*{e(P4a-GmPoY0>snGc(p?>oX@3I8A@ZH4jug=2*K z2@e)76nbO63!O#?F!Sa67uB(bRevxpE@Uy}%3BN78UARs7 zjPRp=FJ%k%W!B@%!pns>3m+6dEqqzHQ`iCTtC+u+aD?zU;pc_-2_F;wR=7{G%OCry zd|GnstFlZor_5tHt-@1q@CQQkO+o$_C}Z2&_fLSori{A$PU%uOxlqmu z10wR7PYSS~^aF+FlLGxX$$JaUCk6TgBp)QS@18(!-#tM&i>0^ko*>*r8S(LVPd=-7 z`~C^^Uy^*D@Eb(5<5J-j!kZNz`=s10{k_766~A5htn@z@z9=-G6x7pvQh*)~{Oq6D zC#9G&%I_$Q6yH-gQ2Jp+*c>nYK0^E63GB^~JX`4wmwc3PF%j)QNw`&Lz9Z28UNR2n zRv#QL452nG6;=rC(H-jDU-Dq#4B;#xAFi@}M+g@Rmk5s)t`Tk!9xpsuc$)BR;rYUE z2rm)-Q22oG$HK>iPYa(Dz9f8E_`2|I;jX?MKF>R75BYq=uEOrZe!_u5zF}p$eT95o zPWb@gT;V*SQF#!5qU2MAoTHEV&J$iBjD0xle2MsLrT>obcHv#Z`-T50jD0wsmi%+! zi$cEnWx4MOvpoMn_JzZR)k3}uX1qOI1=dOCtdi7!T39b^6~;asUy&U9a9kq!a-p4{ zVdoCXvG2xXlAjiuk15iF%HEOA+seP3n#|8&=fR8RB+c9C{I2oMVky3Lk7@XvJEytc64 zlMCax48rPT{jhZ0j=Pq-4!U^Zah%IEtg&s%S7OcLxF0WZTrCthour6d>h?&bc^hv zpNaDzm|B2=Sjm8vIBpf>q`lT*pcz0%d$?37*gFN`I1hrU6Jc*216ty^R>(8 zIIhVq$otN-9%-lkdauJ=}}v*ko*v_sxlJHQEpFP2(j_hwrQGiBG8%mJjoN*lVu| zV_o78_kF0XveMf5J~VyzEB=7(sW(cq-W#QvJ*UroHGBNV*IJMFCQU_X?yDJ-vWTCG z@Z496OwJ(fRD|cgnlpJS@E4Db^Qxzfp4R2{OuFm#?XRYsoxOj6Pzc#`^3We3l!Kf; ze*9~##hYJE7dOEt;&on+TlKQup4f3qR%44D823&BG10co!{8OY18v&#d!k$M>6P&Y zdGo={<|d&(Gv*gMr+YoqW%DCo9-muzg_58D9H8xUE4)hJ>?5g6b-7&u`dQBAoVgHx z*?!$GLE>EYTlg<}7sYs)-$S1p-f!LGd_JTa)3=@B+eTd-(-^U(~|&_t9M#ruA>JX7xp` z3$h`vfAfoi0T%0rtXO_=A9j}98ECk8PegN73HVL|1h_LC2=MdkebSi2V&>h@nPC>h zqkVp3To5)7M_uVLh+Urlp1%W)qB}$W<}S)WcZU2e@kpRML;hAte#qMa(8?#n1l<`( zqs-qf(YZ6^@91oP#8su?l`Q%D%3BeRVBUMJm*~#$TZ;Gh-i%F>hC2g2H}Vhm{=gyFSR1I+M4EgOUcVfuhB>#BlH!W{%*o&r~ z=*)}Pbd_^w$Uh}h)52qz_!;G$71A|5|70RcjP49qvd%k7CLj^r z8Jf|j`4>BK52icAb&P#UgN^PC+}6z6)&4kIy0SmJQjhIYf+)P=hC9QHFf=%uUzqmU zI}vty42HBSm5Rtm&%>Qzi8Uc>AK8Fh?qomWo(Q>*lS?A{Vdvq_;Ko{M)Pt>nJHt0{ z!lXOHU5tl2gNv`W&$i^@&Tx~(kBxrKhQOV{#ZQR7%k*$(xZmO@Mqgk&+!@@Vq&E5; z%ZEFIOFu1I&K`$5gNvULWtboC3=diUSs)u!0J>GjJaa zcLweXZX;cR3MV#_iL4wp(xJ$g%btb=<=$=3(CsFXl&W}p-e`%KkHfYt5%QB>Ye#>M zLfe^f_~3p??+6_+^YhqjxHHg|r-Fl{B#+Ok9E}u_9lPPqKmq%B#Jku$+!tQ6orh3JA;!q zMZ?gCdAKu#w$0(rzz;0u;m*+86mVzY*ADVv%loq?)e9uEUHx-r1$D3Qx@NAKlv z=Zp7+7fjEG!NnYd?;>CofZIVQ_Bq@cc;tgS!~GQD&X6||-&1LUu|D60HfNMPAASsc zc-)t}>t`$ZMYdGsy{u2=h4_cTF39P_kAdzK@M9Q?mIN1iorfT{(~;2SvhJUL4tscH z+k5*K(M;-e{$cU@RiInF+OBJngy%ZkOr-kpRfadEjG6C%d<%6?G53C5kA?1K$p1|p zUuAexyL=Ae8kil4wdy+%y!}l_Uj-gTpx7<{y^ZjmX-|d!g#Qk*HW}mHMb?+tLtKA} zJ;mJ@v%41=_srEh$<^MsgiZr}vRqz#tjv?OPH% zB@8MdO})10g8g6sdt0oZSteq8)o#e{+}d_~6Mxp>RFh9EA#&7F-?o5^jnM%{xMOA8 zVByUyn7D*KSn*|tbz2!2>V!>O85rq=<@Q+x4qPN#x%ChP=3zy4!gA9$Ww$c0$qD{e z22OE8$yQ*yr4>>-b#^V0)h$ZBmHA!mkVLu9Li; z#aK})VJTL8cEYo++TipAb{2Dt9$DzO9I<-M>c$bA1a$t2)eS4xFKL{=YEi@T6{{Ol{|ehJ$F+P!yZUATRV>rZ<*W+wP9;BwS z$H@#Q!c-2HF=pp&!uBjHMF!HferWedtVb(s!fTCgvQ*EXv1&T&QWt6BC5j zFIlt>vwLrBXkNEw)natpB9ag{Hnf=BBE{6b=O5P6*xWL|VdbJ#i<+xP&tJNx`Peb@ zr_Mff=Ard_I-Ec4(7O3`&1;TnY*^Pa|5H<^IzpOF3f+#CR^b0Ot!Y`Y2{S7%UTW2g z*=mUyf8)uV#S~t(7}eU?5LdH)-73rpEQ+3$L!KTdjBZ>~*|40mLEGHG^@|s^pjAx1 ze9d~!5lsf)n$`7z1s*eAIEp zS~je}?8fnY(U@j_@k$tJ*syN#dKR&CX-gw0Y9Jn4#pC{jqIqTG>bM7CqAl*n(T%P-HKI>PH?qColt{Ry?B=!(F(SU?E{T(<)URRH5hx%D>wwXv5w<}-t8t8 zU){KA9r~4#WOLTLlA&l>vI5&>1+1aZVN`STFU6j{azzW&8ygY>yik2NNNhIn<@K0V zdi5GL&^p-auw>D3v~O*4eIZ7)*yL^H(R>)Hq_b=l9m**pHF58k^1L zDQB}ARyHnLy}s!$&zS9|50B?8w<8xi-e%3#cM0lUk0!>E&6~YqRnz+B#`>mp*a4Pe z*JH(9lU*-Zr*dqs!T`dCM_0q}It<)n>sKy9AI76up8{wjUM^a)B=vXjcioY@zW%UT zYgRAAZ0?Qga1d%_UC@5b-o61xn-$!`%T}&gj3Je%{9=xmL+yALr*?C_yUE?{AcyU} zg!>Z4$wu3Nwo}V`eZhEP3h~0!@1Hv8u*#{U$5&1mSu=99owrBVj2=@txVaJArKNF5 z<)@c5G>n)qVlfV-4a+N=8#kd~bH-GTSh{-62yBoQ4al`}#iEuKtCvB^-Etl3Fan1{VheOUswd^8O(PoC ztX|i=sA1hCY({Kd8_${!-zwq`IqWev(Z3s#ZM$&8$~8QQHjf1Zde!3OVYq2eb@eKC z^}lN(c0O@Ua$I>i7%#kzozk)7l+2d&sa|@&2kyVGW zC&2#QmD}p}^7iCb9szkR_4jaF`4oVhq%lH1*r7Z{I74WY{Xjog@?zl%VUzGA;mN{t zgkKR}DZEa2yYK;_ae`3JuOxRw2e3Xdmz59PDeonWIju)ZZWJ~PZQfO+xA|6q*Gm5j zVa#DQZVlo~c*6qhDI6-?OE^P#gm9^FgU~oM$bX*X%Y-)xV=k-BZ;EtpNY9I7mTO!X z;AF{s3qn0-_#!q5`KpDoaaVv(NPa>1rqIJMXSz~hU*V^P#|Sye8PjoE9pV+j?+Nb{ zJ}wM#3D0!Bgu{gsg|me7g)4<82+tILUHEO`_k|A&pA-H@_$Ofr2D+6m94?GGt$ew{ z_ zQ-v1@uN2-U+$MZh_#5E_JcVTYW(ZFfo-Mpi$T?b=F2GYhVh>?oVLT5zCw^f3WZ^X7 zfx@GN#|bwRv5mF}`C(>qEx)AruSvdGc$xH^W`*f)6y75J4<$b!d`S8yB|jsy`Pxy> zS0ukC#9_qhgJEmP^BC*LXD7r8p*`M!%m+-=?45SSA)oY8K32Fv$oE^+Zx(J5o+&(Ac%kqc!YhT}7TzShMRf^r^}{EYB%GDdo<1O-+Gu=OnJI536C-VlQN8R-baS&D(m$o)GGGu=fv#_*aUUgBUq6v=XHD^sc05y^5{9@{}|#v12A zF!lLPsZ=EcTH?6XkdyYR`?+Hl?cvZ?u(t)_I1hrUt6-1Ews?u-HbarLSDUcMV`5yt z3lNU;(8g`B_jBws@e;?K2Sw6e9qh4vtRHr(g1yTSW}a%STrR{#_{Ml+LuMRTUJoYI zm3H4fcaFzHri+);kuJ7PT|8d+CM#LLd5QM&J|J%Ij}XQf! z2I(rH>;^q~aJ0vMXPNPsM=(`_@zV>p1Sk$-%kb3eWyg> z5`=w)eT1_X_V%5M5V>{a)BWPHIj@xTS~zWyG3ZLSr>e5cPuY3d+uq(K3xn;`TzKfL zg_-T2TmHG7m%a6cg`7+Hatuh<*IDlm=!lXL=-ty$(+O7Jw!gGj^aOTlaKq*i(z&CN zFrCi-5>nJH#qcf~-jM}o9-z9}!ucVH&4WnS z3Z0)Vx*~&T-l>3Wr=lxMo`f8Dx*GC%u(GHp$@GGkVsc_S-`V#*a?3{m*MJI{8y1f=GuWABc4R0Y2~9Lf(-02Nv7? z8+x5n#QL)WibkZ{N%pu(1Q6*?X4U-l{_zmQ z6Y=M7=*%z+%CMRnm?HDS}5M%`&?9yM7loQjt};} z)5QMa8rFJSxWmN3A?GRd9}3~@j;|>`AefqD1%66H;N$Ak!s?D zNay0Kqx(?240JB-Bi{KS(mjbYA?F2to8^N@=ME*c5kH{ggGlGn zPmB1$7av4A7e6C9nf5@Wd(QIDihjyo1(D9BuZ!wfK8SSe9L@{8o$(;jnUf~w1?GO` zgGk3+$%u4h+W8>TaUU@vT`3hH(sANaBhp<$lOWPnqsxp)w}Cc5q~lF;rV5W9a#`*Q zZX?}-4oPez6InSVT7o*|vR_4la&H?n9H5D$RK?r#UQ5J$9JXzVkpEXu*wLS(&~|1V zKDb|2#WKz#C$k$tq-#ZED$YOyN_-IM=z$yAu^U7>bH^2Z$_J6o^FBH*9g3>>AkvxVE=--ptRT`kxhOh`JqIG4-8ENXUSJ03-m7YN z-|mA**Ad+q^`f zR?LWwq&*PnctH&st5MW^5a~XH(y_lqZ*yFMNauFA<dAksMnh;;8T1&DO6l!rm2TL2@hmGvozbd*^slR>1TJUNz0r1L?f zTLDGHn|U8ZItuLb6WM1V(wSp(6^L{^s#7piAkwv>Mck1j_juh0k?uMudh)2_gGk4X z+w({4D-h{esw@AlI1`9;{4N5BbX4{7co?wJjRCd|;arwGdN1!a>e)tUIK_A_y958l z9D~KhssMOz1K9!)>3HM=k?xBu7(}`X6X7-yAs*Lb0gCK%Hk3JU2ux!B>7vE3(w83j zpRK$ItxQ#7O?j21Hp1?Ypu(ijRpXEfe7bj#t{4;lo`y7?NRZ2A-Tz4l@8SI?GI?Vi zpY9ae!Q!pORcgQG$ms3anNPWDq2vX1ziF)8xXvd-#}oH`)V+rCyzyOl*TgE9VXf-P zbbFa@7GyH6`{ML?un_AY zrW*V;Xf{FOQ)$fqKogY+r1>`(t2d_;KL}`M&O#cpoy`m%SJUBRXq?ha-3ASvK4oe+ z0ydi=ZydbCJN>`d6hFN4Fjh0g<1L?Z4`p(uG*dgFc?YXZ@rpjpzgn!`f=;7RQ>zu9 zgNInn6g>#4unvt=nkim6?}ZhU1+#%iBap73nT?&y#9YMj>|`cRMW7YyAf~YFyga!P zE0*EU;x9cD$5RdfH`y=5QIu@5UkH;ZjGTfkl0MMyKmjFvLUzOjNnu)GkrksPS&`3= zD+*H!E5*l!>_}>4zrT_0$oYN?(;>(6{T8PAJ*;S6ha)>2VN_0hHf3~7oE+rl?j4+% z;&(_PQ~SArhsN^(4=W^ytzv|JaGu@~yG;I@q=MS$#H}BYEKK6(T)33TV_183rl^k8 zC-|8>?0{fNsKjdgOa{0|L)c_<_i~?vaKcsw4#0}}O$qayzG*81+&N*1u+sFPYBI3N z363+_>Vza`GC6&)tBvt4owWJm&gqCEu@2XrnTc66p9 zT9En#1=Ce#K4Cvgcm!cOR-3VyZKi!uFd1Bq6{Ql6!D@F6a#^bKIWQ4OUw$cEqn-Uryi z^vN96Hb7mDYGc^C9La)FqDT8&u@^BhR|J`sYhtEk*Y(h00LRNIaRAr_Yq?gYjhCYl zU;!Kfw9fvd>Ex2Ma|X_l8N1N#ITIr_LeRqvl4praG z=2DxD_duI#H_Yr@!&!63xVWA0G|ZHj$8npR5^-;}k2^gX_nTx~ka-I>!%Qy{j&aS; z>Kx69f-?i>C1>(=MgF9H)=ObF9E6MmNj+|{8GYL&oMiP5GJj*jFmshvbRdY(q8-Pi zynp%ZzNFPUzOtjfwjUfWTZO+~#`@Va|Fyq+GuTbAZ5a_yI-BAa@H)T+Xg!KHa}$?$3_v1D)!om@CG z3$M`I7F;hSmX9+ZnSET~Bey$#h>zT+`=|4fr=x805$6hz6fP647OoebEIeI!zVK4v zw}iI|?-o8Jd`f8iI+XjaWKL$nde9Tv_>sZ`gbRho2#qI)^n7o_^xqU-FT6|mrtp1X zM+_sT?=2iI+(*aGgqxLmkVc$)Cb!v7F{S9qWBCE;7bG=?kfb{19&=Lq@DH^v_; z+$`i%Rq7uUz9f8Gn87e-d>7#!!fGMEU&nZo3Wyg9uN3mLY}7v>*&X`Y{8 z$6mk!drIb26ZL#?OXQnPVx92Q!g}FSp`9m@Zmnd}#F&q4GUDfiX9>>{epUE&;pM`s zgf|H7d$6!Wx(n^yE97fd%D)u;R`{0ik3u^iBVC^7M_>nGnJ^Oe6;=s{32knC?Ik9XaFD;3{gI9NDbI6*j3 zXxCk^$0zL{-Jc+F;rxj|0eX}#Jlrw}z-@=kY|B_-3~@ScCx$r=xG>!*7IJ@Ch4%-> zd8oP->s1^STH?4Vka2oR)k=R#Wh!+KjFab%&2H~rSTC}D<2(qa7U3N7b?j5|62~<_ z5r-M~UZ+&*7jdH!al85xOhX6UfOIUE<*^+^o-dO2p2sWgO6cMxj^lk%vK?;^b$oT& z!zD_=-WG)8JP4-#40|&e&=SXOhMcsQ9hOQhgpT&ujdA^U^(UB)9p#I=Y43T+leD)4 z_Sin!>zJ^28N#ds`EXpGh%mo*ys;rOj_Y;8INicN?wks>EpfVC{Ry5%y5!i3$IC6q zm8{=N)Q{HytRL^=)*{xFPXk{ zdTLPbt&n~?M_Sk;IyQ%83-=*gCxck%l z^}O*@zkk2Q+q*++SLoBb>W3cK8bF`jMgN6X`V!D$zrSFu+h4F&yjyEcpKAJ4>h5Oj z*KWIIy{QP4G@#8qc+|x`Erf4EH;hZr?Z1ZOM5YWIG&{axDq`WMa3&=9DGWgZ^Ha#q zu2{gBZ0?(g$y|vX**V=gh%m|Tfso**a36*N{1iw!-o;O06I8j%vhhfsX-4AQ@G>5b zGQ0-MRhKWJ89&QO4>RlWSJbcjHmGvh?f5VH0y21+Lr|0a@Q$oR<`4MGH(NM=EMk55 zESw3QpUq#9=?$B~*{DkX%97Wh4EV8|{8eStJC-Uvv^y|8eHQYU1*9^E`{FNud43Dj zAR>mm`pI9N`=g2QSr|_v*JPMAa~h3b-}5fS(PzOf1U>(7Xge{S;n#YCZq_-aB~VlZ zqkLYih23B@7+q#pZq8>Rs8Na8urC@C)O2ta@WVS%U{F);#FFrSKGG+QuH zVu{Vc8%&Z|8ot1)O_o?5mNW0Z5-Y+q8(Ax{SGXS&Pmx#|`z!{iO$1Jbd&!EPs!A@a5OjiGs-(F{5glyv&BzZd+Wk`S;^5FzQ09lvf{ULKJxv)t3nVh9t7b(}4l;ZeT>84`T*~lS zVCT?hfo$dgJ`48n3tV;XR{?w$xGR~@!bvm;p9StC=Cja91$-8YaII!O3op9|V4v7S_W& zYh`^3p9RXSl*#Z}pnP~N(`O-o&%$OXB0c~L;Ilx1eSSCl3_c6zm<*o<9@QzBDfldK z<8Vik+~f5CJ_`>(Ve|b4@LAx-?ODv8fX@O;b>%-9XM)cHr^ANN0#))&;BgBBYzH*| zAA45%BH{D#x2rn=dEG&l!0;4Oxw+5eqTLt6s5`jLPm!$(%DxEQ zPGL)jw7C|#_aVPZ-2~>_x9#~wk#UKt(^CD&m3B|?u05S~HgX@s84)oVU9Z$kPL z0!-w|L?{Kxosh%T;d&H7$?^IzLQf|2DubpFjVD_dud%q(e8vj#Pa%RkF~arVdc1=_ zrO4A4p~q_wMjKv3C$4*FvSMYg2z96|Lac9;SzAB5e>*w&(eOPX$bH8 z&#Ya;8_)3%4P{xuW~{IZaPI0nK9wcm>XVqJ_{9{Bfs5 z%)a~qX}?D>`|>^_?;`YM4znM5ICiZNu=V{hQoQ%^+1txT-6iK!{J_mM!k=+ay&Y~Y zk6tO(BX_)yTyrQfwm3lgaS0OdIeal^4v%|f4LolR*fKAwOj$o1m(V-WyZ0+O^gh(dV;xNIFkvJ5j>|p)WpaFE7*Ch*H|Iiv=)(55MZBhDS|1%$Zb{# zH!<>r6{7qh@;4V361Ld<^_4{1%qfII1US1BdLe*S5^iF|ws<;W7=r6eA!c8_)sELtBtq^Wv#I_hE5Z`61fChXB!de8&7h&vV1SAl6 zjG7Zk?8Ox?fRKXCr;_+RK(uj`!!I@7VHbvADMs5F0 z9fIh11T={-5y7xbCL=P>>In-F#4=%&okf<(S|Ee#%p`E9R0X3yM1WnwB?!hYkNYiF zPvDW4T}B^6pj{%nH{=AU4v=@Z@vv4QVAvA42jp5z2hOx=0(S!H&?4Y6t0t_m>hKxB zA6PZv600^dYh7p61h$w)?gZX%)daQ{>M+1;F|>t8q7WhEG@3Ihg*fJ1$6vE$xy;ZW zff@WQs15A6%X|z01EClVFhrfd{w5pfZ;^CL(6noeutfnQ86}MTF=!;byX>CJ@|_S` z*6Fx=DJ5Xt+ue?PhU}9wx= zu`L37+TU8H`T7(h4E|Y$XnG6U=b|28DG|oH=lb-FJ+v4*W51aj*q^umADmYoPWHR5 z1%Qup0pI)bfx9Kb1PCj*W!+^Gd<=yQEe2P5(P9uw(_#=$(_*3-S`5^p#o)0qK!n-X zC&IKhOqfzoVH#85o+K<4=7z*DQDI(caKm1tlXsd2woAK$`~pKMiA23^Yg|K-xh!F5 zFkw(u{$SLk&aRC#1%+wU(nSr^$beU+&XKnYd1gPU75SonrmqQyc|$m z9yg^u?^Z7r?HVn$WS!U7n6!DQDC%`dS=LNxshxU14wg?O+Aorby5q2WtA|ArJ)kI} zwUvf26ZwK!hMD3Z$gsL&N`oYwFKX&@G|1EzbyN6Vcir@a+W$N@&KL3FH)C0|j{ocF zJ70viv$TAmnb|$a-f4bTTGGrXka^(MUp|Ni{zar7JosYOg3n9skr#bSE)Qu`)!6Y> z71ax|D8zpwv!|L2ukt}$FQEAn82?EWpY-7T*OGk#+?^@q16vSy%(4%`!N(;!>;f2^ z%pRlBEMBpj^#Ck)jY~zOFLri407GKQOkl6c?lJaPniV>@>;)EhS!Eb==>-7NYk7cx zYAyg+MZ*$t_V9V^;wE;1jbfWd(P#_;?}zNxbZ(Rr*WQ7O?{{2e0Re zxtfy#`u<8EA{--}Ae<_kC9DX3&KAN`Kg)t zz(_aPMmShFMtG=jwvawIENA?Zf!~vSvG8``Bf{r}*?59wIpZ%3>>+ueuu3>hX#9bZ zZ>i+9!n1`HQ{z)7+>y8{|IY@ zONBQG?-0HqEW(>9ma7ns68e0eNs>8z8}ls?E*35mep`5k@Dicn@1We>lyNNY7d}ix z8#XH6%aYBy0nooL{X5cc7w(YW!!?cNW5Qe_>M{Hs=sQZ^M_4KxE*vR5n22_97B^le zXGuR-SSMU6TtP%QUh+x8?-60=93sLM(qALILHb)I`@Ee8DWlx4g-;59r+j}9ZWg{R z+)hNf4}^5`WqPGFVvV}+B1(}af$j}p!o9wTfJt`L3}kLUvBqstfD zbEWWF;f=zd3-1!%EBv+aN#Xm#kA(cxLA&O67D&%c%6Y;LLi&+XUo7k;>?iCm944$3 znrU`Xj-C!IZ+@?VhfA&z(m8|ai-irsZwrqX(#e7Od|uHNlCKf|On9sCF5$gGIz+Ji z$HJDpp|<>8Mmimzh=$(_>?+x;I|R8@^1j0Th2}m1>1I75;3VnIeFNl~l4l9$3y%?U zW=Ph%T6m)H6k$uA(IwJv5c+(h>m?gLG3?zg`5xf|!j?Rwm!#+PzibD+MTpr#!#jrD zPI6~qS79$zS$LX| zo-NdG5MC?1K}f$Arr#%|YYSyAwoRmC3vr8(PArr|yzc>K5%HT(R~E{hgmhVTm?sB4(yN@107 zvT(ZapTq0I1JoW~7kbz}cM^Ld@YrIwn{9y52V6eQ#^cC1#|by)+h}6;5620&(FlGS z%3%mA@Eh!Je%c5q@bm9fDj|%4GX&$3&#@RL<`W~^MIwb?22p1*|P z<4l{02je0d(&ndCLk`wEY#+x-As_2yecTTsf4}`Qh&spPOJ<4@ZGPHf$U%EE%j`!` z+QY4D+TJ?E{W6F;O|UnM5p90j36O*K7QxS0K(ZNH$yBj(9KOA8crt#_&_2pKnvw&&TVU(XBZT%Wvv0U@zFd zcVRdWI<}7=kp2CA6mg8vdVtx^Y+;XW<35_h*$?L+hGJ{gwKAYF|R*9*;8Lw;WEf>VQZ@kBOs6*};r^nf^-+yNa$c3nsD#rK!~0j{Xd*To*O@r5Q?lt zniq<-;luY~$RK`|7ml2bl+b$Q62Hm|$NIBOJaRfJ^5U`i=y~z0kY;`^@}Y_pwCxQ; zp~I0`{Hjnk^_E}d#lz+omL#j@{HjJ2a6<>6CE{0wo`oHsUo{P>yYj0JK~sEw6>jB;_X6!Uv&@T;b? zEg62*;}kResvX$H0KbYe_6PV?CCvPZ{Hpi4(;0r%Y>EMX73qCJe${HqpT@6Rh1xRw zD%0N?e$^JXEW@vQh3)>*{HmXzscC-I1?;a3zp8@G4Dzcu>hive>i=_c{HmoqG#P%?rEGPEUsc0>`jY&r`)Mk}uNp(~6Zusgc+fNas-N;GW%yNG zfFQuHf-7l|U$u&Rl;Kx3u%a);ugXTr0KaMu?FRT&jqHp7zv>C52l!Qnn-<_#(dj$L zuj0dPkY8mOX90fI+uW@HziI*N3-GJr?1cco3ceG~_*F+z4)CkEKtPaR^&{E~@T>k# zdjWoxAvOm1Reab8@~e1WHRD(DsjwNp$}qZu{Hn*fOF@3s2HN;~`Bgj*gZwJWL4FnA zS)}<@w_pb{{3>%T3Gl1NbN2%LDnm*AB!1OI*v;^(PUI-9^!Zdy@*4JKfL}%O^5^7N zji;#qzv>wl4e+Zt`Ad*rWvH(*4u;Rjrsmz^~fG`aXqU)tc#_%CEYZ zIfDGEQ+a9y`Bi)|(TrckH$%<%RSz&nkYB}bHO=@{BRTfIB7POwM?rqo9qh9&$FJg5 zC(W<=E8F;q{Hk-1^{e7n?Z-XH@T+cT#c6((7Y_GDI_}4Ypvo?H;`l^d-Xo^@Rh%*I z_!OymP71+sQ%xuUepOo}1o&0ODDSOv&H5~sU)2r9cF(WkS3ZA%m_un4n>!BAOWnx! zaR=s+Uo{p=zJ}W>4MZp!&3u+~#n+R(GqnrEv?8~Q zB-k*5Cuw(s#A6ueL6H_RS< zG5=#ku0ZI?9KBwH=4D9FAz22ssZ%8PIq@{j_ z)-*H}q&1aY$)n#cBw7=jVhyyn25gx^l_`4@Rhji;$RF_7`B*jv)F!MULrr=O84Bg* z)ilUj^-oxFtjzMVq&z!lWtCqwL&gSmX>po(QMZ}D4+VAuFgUE z{V*VM^PA;Q1oLzGmsYG0PZvFqA2*We#b98NcJSpSv#<*Dw@ve$lq0{L!|C1%+POV* zZQbo6#?~H2)a_pzBZ_O`_>8FL1gU<_2~xXop?J{Co70~vcI8X)r>zky~OT*gM1FK05ZhzwvYt!ZK;g#b1afma%E69|J4JZHJv#7LDD zLQRZJw1U^f2C!lj#^225x*+_Bm1VTNK7xHj=wzbP2@Gb<97a+IU_BAaOmqriI0D#B zZWANptq^Kr#5Q7Sun|+BZm|_Z24RQ5##(MtrrC^{4Zktia5>~3G~Y&90GEmkDG3)2 zq9jQt7ruE-IT-S*U4|H56h8F#9gd znGm%Mf$A(T#~%A>NHSYSxeN2fkab#Q=kUi%B>%7Jj=qqx&>iQxV~fZ3Fe@?H(KDIA z5J(*aai~?fDnOA#3nQ4ofC7FhJC^q=P=!>0B8OkFf6W>)K;4KkudN{6PwWS?+h#aIz;>tw^EVfN{iDId3ZP`*RHsC{5hC0`wX%e=Kq5bP;zx z0C9&o$h`5IEOBR{A?|c+#-wRys6{W@ebl?M-cplZXDB1uBLS_*fI;? zG#Eb5Zi|wtXs}9-*fT&)Tb}L z6X4@aYnWq8zzo_$64Vgj9uAIKROV}3Q)lU5UJk#$g>@_?(Es81Cato=JL|t=!}IK# zR(Nq(9Ju@Co$!bZCue@PCFP93OP+7!Iy>~C$ZX+E6tQpOIy(hu7az#k&%5w)cu8wP z%NdM(QG_qT%jv`Xc;U+z(!>LVV}uigQ-!mHwZcZ>YT*gOJ-i&-pL=*YwjXNoeu?92 zxp1BEJmFQsTZIn^pA)_zd{4NCmt*^L4==~|!#A3jgE4yneiTDMpOgQy ze?6W1l>UVDPZJS*Ud|gz_jx&gm27x9h<_?C2k9yNu(SSRVTsW2a-cWs=pf$#(vK3F zb#!nZ&!-GLO=x&CkbOSPHtF|*j`_H8|M{y+M6$s=A>YtZZ{G9)d7nXqs0g zxJhEebXcKCdlc9MNQOgG7#%bof7ahS*n)rp3m3LGbSx^RY&AC8&N z=e3+6+3;1NKTq;S!YhT>3V$yAh460S{ldqEzY!XqE9|}``3>Ql!fnF$g#3!l_T>o+ zg`I@O!d}8M;Q%4Oc(c5D7YpR~ZOTUp`H7oyqmUoCDW5LnhiuB6n4EYO5q{t;`7Hcw z&GaXQK5vD-;MBjVa{PWx`C}o!S5w|wSSqX#?kn71NbgMMpDe5v&Ji9hTrBkYC?`nf z)ch=eu8^O|DbuTyNWTZ-9m4yB4+;4Jo#}?(3;bWnn}yqi?+ML)C;H1jpE0aWdH;Nm zOZLzEmgjp)>Hc|NCfR)LLH*|b6gW)!N@10-<@I5*^wWhigfoQ;gp2%i9j5}y_>|zc z&nay@wr*L?Y~Zp6iwpeNvf5S4oKiDyM(OOvMyHgD(&jI!{>^C~4&3j}GYF3_Hy)4R zhHf)kSNz4PjOQr3wamvfZger>Soo}beUXP{g7xwk`Wwd;Hy(fAHsv!Bdg=FuvY%Fo zIDXa~BDV*-!f^%0+aZo&Wqy~~E{+?&45H30u*GxR-~6=MQ224CosWSZ_8S#QI|}h& zy)%0`&L-?U>t%f`LR^XvwD&^{#1wS?=BL#`5wtf99fhimJ@`zd?VXIcUj|XQo@ZmHt5tr2PQ#puLY_kNZb^{6gp3yBu-a zD?{M+JWe>SXW(y4WB7^C&v)tGyXSe_seAyl6{PGnL!zmd@!JrB?F*M=`j201{q{YA zICifdV7Bq8=40RQ3u0h+IBStF1!a5a`M!bn@(@^Opu3z6UE%BnoxjlzHDy{FG~RecB*ga3^7n5R?G2R}PK;pceiGve&bbjACNVd`DNSPgOUz4f?)lho zi3N$BGV~|4$x-G}1NIn@0VeAhDCuA|ZjCFL1Q2BZ{c4WK|5!>HKwPl>vNqCA? zM{O5`6R*)&O;#6^8c(ocvDsbNSz1SjhO>EF$)Fk{VY(e-9i8t2;<4p%(wh@}c8INL zW2nxkh?n`;O1~l;9$stnu0zfRv0LLWW2d-|PVBa}D!_GgV!!Z50@u-r-7YDfSV`M= zWbsub*U_m*qhfbTwCm`^e%Xd+2iMWzqNB09RJJg26w5wfdWq}kq*(T$&ScAku#V23 zC_d8pDkByrhO)CCOFU-8UWo&F;2zIV$gZOk`;B(MuA>v%sCtJb2D08~ z+Wf_otxRyLm)Nsyb{f&HqZ4~Urm7MbGxJL-J3hhZqS(vXSDXEvoaoLydbO=#Ib$82 z|6!Y7%PmJHuA_4^_B-}^E1tnzN9XrUeM5td>*(-UvuHc>hohw(pYPgHkK+=-^{zFO z+PA}>Ug6lRP@KJ!B(o_7o`)SPPVy8Kih<{GByPyLYRW`b1fGYL;n!*9E>_M>l7t?^ zIy$y|UUDz)1=i6yAHP~$N9P@;gXdw>%aXsN44#LX+@)whav#dzdD!$JNiOys1JC1b zQ+`;IXGjd|=-5k1Ws;K}#lZ8h`KyvO>~XB4W7EebN3lG39uJ!G9%(OJm+SVzZ9I)im|cwWV@jt);HvyKj*?qXO+hv$e{N9Q|Kfak%5KFm5g z^Jo%0k3w{rSF|aTJeUgbJYF+7-io0Ac`De0)Px2H4w4bsIAj`+a*^;_WGHZNhK2() zkd-R`cwTQZu^fkOCKJkUgu<+&!%=8XX04->gZAl)8M~0XiFI^Hvnk}@$cn@8c#g`6jc1=fPhyn&K*S zG4MR>aSSJKWGk_b4l{Ed9lGwv!1LhG1lQ3a5j2K%bnIS?P5zR5fpv7|8GDnH6PX|D z=*%%qosoQ)>ELk^uyTEJ0@JaMj+Iv>i_wQM@I0dCm}4ECD_9}c(P?iK zSVw0ATMV8DTVU4Fd4j_PJP(>M>*#n?U>zN+z&bj=qyp>cSOwP6*#~7~;CWaD*3sd+ zsupqlI|jO^AU{am)6|V<`)$ONFhM49(Q6RgQAWp$#t>tA z&k85`7};she|VPDO*|NR6Ixk&~^EYbYy-W81YgQ)t(k zo02iNG-z&V(A?6XIb%~U^-~Xp#GYurpa!m2++2IU7&K9wVz?%>SU%%Wb`75q;nPnT ziC}#C*+|-#%Q~ZcR|BtR!aM}yvd+F(Vf6%df?U@9{-Db`v}WTm;2~v`{f#>i+=B97 zklAy(z1_s|Q>jL12X4VD3fYrJHh^5yBKs>!J z07gqgZSCS^r3)||{B;5F^Tc<_S|uQgF%)r~h#6kqefV|F%7^D{SJyZP&xGg|r&92^ zJtoo`Q|l+jAzJn+(JXIyX{5E6lZqrbA%A%kuT!$ThEh(R-*%jr&8hpLibT5`BU!y8 zt-C8Lr|4g0r|4%@pOR!+Q4a6rb|K@6JGXI3^@5tka~EL}^~Qy(@mCYK2d7lG6H%|6 z)39tw-E8z?&9YkO3po4PgR;xa;-iMnJfyL

    gJ%MKyIb4Q1ss=PhYCrvJ=Q6Q&(B zt$LuvnN`y!&z#(_hv7g^-CHTuENySv*(%pnZ4+kQO38= z%!*xWoNVXKU9@m^UA2}5sGE)bS~*AiWoFf;AFHXt{Go3kXXLJ(o0_wr2GeaXpS>KD zbkDA7M0Zs$tMff}={2}yadqvgh0CgI8s;}*w(TWLj#}yhSxkU)WeZ zXBFo7#;{w6Nx7@lu*MY&=feJ?W6U1-&Wv+bEHm|D9_q$gILEb|#U6?V%3zy7Bt6-*j-txtB9P5$U+%5(g zI zi)vV@R$IvUdRnj3L&n3A*QuUgy9`&KTG~WbogXW3)mX?wGk?*N*%%suM$G1MpJpy( zer`J{zMTbM6SkYF@7c7KrsvJcDeKi~I!l=n~dYN$p3HrDn|9Ra3H$&ixSxQ5PIkZP!1v5@UdRSX(jHh931sgk-m^~?94 zv!nq-yQFRa*v%q zHZEysObsbv7ndv@fSo^jNki{1+wbZwg-&rpBOiX~!B*c$ zUs=8b%50gtS?a!tzOwwj$fp4IZ%bcUdq>dRS(evf-co%LUs*og)0e5gkk1p8M+nCX zCkT%a&K52dt`zdK70aI?^nGS8lYEWv=fZo0&k6q^jA6%Vr@gR;utGRiI915^?96|R z@HF8C!mEYGcL({*XENaX((@jak>9ACb&{F%Z_gf|F{Zw=C4 zmb_W`p)ihnWR@Q+tP)NW@^vuNHwbSOJ}G=f_!r?vLNm82$`xX`vpip`6Xys|5Slqr zq36oHO#i9yS3)xvD)dp@!85&`u)A=eaJ29cVXbhvaGmfx;Z?$0g%1gz6TTsQPZ+@f zH}wm<3kM1L&4lSQgbRhae0>Ui2Vqa)VBvwnxxxnFiNYTUeLs*WNi`>5v!ZpIvh1UqT3qyF}#Qgcfy@Y!U{W{-)GH1exCAOB)nXB zweUuvxh}#U-?Gx~Z-xA zq}rIq@Kd3m?@gSTyk`2FpYNAYFz#=&I%I59$Nk{;3xr_%;%FcHh3!KV((QW`aohsc z1I)G__V}s5-~76Wfo^afM7|W1?VF@ z(6+n~z2qKydeY{2VP(~bst2pOZ1q}o+nBw;TX6R_x7CR|y&`XW7jM$$QQi|foU(Qs zM=m&+DXp8Qgv;U^Ph9Zb1-|wO=ZPKhvS0mq>j`F!7PH%7mwxpe`_4587aC>e4}9o2 zr6=6Q8VK;A!_W$aVlD=+cP#RSCKOH~gd@B+_SQ1jqz-e9D#mHgy>TotztBAL#3N>P zgm|nGBOv2j$J+*P95eULAI&%?F@~Sr4958k;tk2?Cvy1Q@s8Y^g+K7QdkiW#O5ksF z4hp+oAG8WScWjXNzf5c}@z^M&(&z3>=#0-@XV}c5(*%6(-i9*kVpxRF9rf1hqS@Ta z@VPq#DT%@O1E0Hf$b=8+iB9M__}uL@B7E*5G-Bsg_UNq-pS!z}MxQ(L!|%rFm}TZx z_U=UtK6i7Go|g@?^ts#4I{0V>pF74;hkWjAjp4*L)BvA5E5;L?!WuqzR?JN_p$vTP ztmymPeP|5P=Z-fS*(cx+ef-S4(Wtv^#QNNk^DkW)94)+z-8CeD2<2tNs^FgwGx0?DeS> z19K}E;Go0jjyvYj=dPCWr_HTQ&lux#Hx_$f`#UqYGB0oNxwAVNPSAf6K6ew56YeMp zHVi&@>@4}*eT-=KQAlPmow_%=dM*U`-2DhmrOzFGZ4z{+gU=n~+>Op`W^it0Ui0(# z08XDfdM3!{P6gz1r-sSr&PwqFe@_EGcgFi_7oR(`pb32L7Bcf)8pVYP-t)ret`0z- zJN~4>=k7W*k3M$`cxW7&9=D}S5y1?E=f%MAM5y=}@5OLn3?_}tk`No8^& z<-pv^Im{2AJDWZ>c@yQp+{(sRD=@e6(X2l(xAN=kb@<#}X6l<^J0NYgES z?p{M?a}5eP*5{6{S;@gP6_{K30TvC+txO^yeeRf<N!tS>mX@?>U! z&)pa_h?m*qcWEIwxAH~I5u983K-LMLJKFS$;B%M5>o|PwtO7oF&of7GZsj~G;B#kl zz~_$6{q(uxeqy-7=WaQy4MHPKpTg&kG8<)N_}o!G)R%pqyAz;D9*z|H+)?1+yMTT6 zh2~bK&)vf)-H}%v`rPs0c6^0x{KUDHk3%hA)!fRQ>YF}yyr{zG?s8U~o?96{cgABg z9;VM+m+O!x<8!wfXZPOsAph~HN72Vlig#FUiY~kGxg%YWK6ew53qE(bD4KP)o6nye zJGU~QKeNtt^RI^{66PDRNcepG?dm>>6n9`0fALhwKiJ%E-BFV}s109<@sTBk&}|>; z1{>Y|kZ-5%DDKFRHk@lYA13(9yjw@++qW&fcX)N2gHSY(`SvrqYapM8P|T0a?l9B7 z5)7=p5xS#{!!;Ux(~TBH|1WVnEY_^NL081?Iqo4*`Z@Lp`YD2}Nj*jfHwr$;LUdwe8+JkuQ+p zQ%I;lFy4ubaQH%4)x^kAR#?--$QlHAClc0MeSH%n=NtWG!c9gG??gr(vqHRykyoq` zbSDgYC$brsf;VGsO2!<#6Eo)EotQD#!aFhKnGKf(``!cof_(j9ZO^3bs}WphCgENL z&sh_0V&r)%#G4qgOgZsZ@b3u5D__ z47O(h)15;Is}PLWBO6F_5$8Ck|6WauUW(v4M-lh}%5#o$O{47fvGG)}+a^B(WI97H1UA;+IN%wEBd|mKZ7d=T(-GKYf8%Mu zun2*z_P6s9VYnQDjlN0YF5tZgJV*?`MPLsGw@m@zbo>N+j`?Qm?rfF7&@qFE1L!ln z?3_J5r(dJbDP5Y(8_=)E<8)s-oWkQY$+>8crMqcXX~gwb8i&!W6t$RF7TVMd<29Ne z$#LCC=V+Tq&irU8+(aYM{761MQ|Y8y_EjZkc}vDcI(uzWk(_?bs|k3u9zBj;t$WS$ zvd}_#wPqRs|JBa@cVC>It}BeE>zB@+b8z!!aqlx8v7d3q^=tO(8_r?P9X^|R09tn_ z`bx@uG3^p)94CDbRo@vDo_KQ6v<`H1@HDQra>8up-uWe+XVV^?_MlFW#1)P-o+V@V3XNgAijCi&{kJZ9X)L~Zr#3U5u1<|%8s@T7r5=*q*v&6aQAXMx}DrEA$s;S--3#;v+eJ}R1Z%% z!Ohe2fUom#Ume^$JSpS_6@e!Qs=tYTw0H?%_Hq+2?MEB9^^_N_ud%*Har+IKzHj`d zPo$3l5iSB|-a@`G3+37;BkFmmh(m=Vgkyw!Dq{L!!udiz6;Z!hc!Kb3A)jcOzCn0{ z@J``9!l#8V2>&R2M;O7OrkyrIe*C38MtG=jws4j3M4_2i5BV>ae7o=w;q$_5JW|qb zQpl+hD09LYVwG^3aJF!%aINrc;hy%vgm$|N2MR|E`M!+loRfyQQphDKDPJTUhWGiD4-%S*8X(V?yi$0s@N(hJ!uy5) zs4s0D&Rw?SJHoSsmkMtb-Yfi1n{W1sY`gz25b?p~Wg-3Q*e`#P{EqNl>HjX-pLaHn zxADxMPlTPMu#@yXCGR8LPk4Z^iij|Q2s<;RpDC=7elZbYrQ{QdsP7cvccs6Oh;W(Y z8;Hnf=9>lHD*gRLgvTX6Pel4l!rx2(77<~aFHVDcig!IOt%nx%! z!{q?-!xd%YzyVw)+58?sK3?)kLVna@e)ByJc(df&gufErCwxr!l+aAYf^xr;{JQYZ zLi+a5{(HiYg}hawo?m8(t%dxcM!8%#L^w=1N_e1G@}~*;C64lsg#6w{nah_F`Bja`rAmqXen#9Rb;gRminVDdTegslM2_ zteSlOc~U5uZ<1L)B`g+}30s~=!=xW8YI)CGJo7*S^-!|m}2>H2;+09Sm^_xEfl~(P{+8cgs81%gV z$6+_W18mnM1iuWTPEY(+bn$mGkX93jGvDaeu;cGkAdSBV!Fubvqh91=y{wP>LF9N2 z);q4P0+V4cd7Am@~)3#ymP^*n(GfI2(?` z-|$TZJG0;0Yv+KE+V9MHcT4{3`H}6dBjN3>!#}yX*(ms*`upAN2_k%=Ek4e;Y@yNN4PS!Egs9=7SC<9E#B&B_>})TYi!j)RpYAiw|ZXZ zjk%{qPILDw*co|u(&pC(&~m}rwj0NvHu^MopP+X7+StaEPCNay{GIOhm-D^tt-W*B z!jt@L=bpJ3eD*knUH-P`a<)|t);zyQ%|0WOi#bLJ@tbg6@LUWWZ*bu#q{6TK2aw=b zPM=3_4piQRLZ0C8E5C{P?q-Qe9XMz(PiqaNP&{%oD#ARiHK-@!OFn{y52PxUKbY~; zkU88pe+uJa>dOk|(o8%|M_}*U_!DX7OMV#&xE`lfjP`BCMtINRPqe|rV<#Xrmi8r& zUhNrQ@=0h)RKDc@1B=m5^d*nVmz>3-8DDY_Jr@o5lGCdxDqr$3G`@>3c{^yWFF9S? z;_Xf6%LsBksn>#f>j{ZyeQl#+Q6O`yk*;K9|V>U-DZif0{2j{Z-ey@gw8Lm)!Js z#+RIT%JGaZ`R~}0j4!!q*yr~pf0<2<%a{CK_E*N2oX(>0U3|&cq51{!j4yfowzdIZ z^7t?Okw9Pa`0bM7iJ5HX9a*CQoWFG^tGZL7oxe5yOZjEzC8jZR#+UpxiWy(>?@-M6 zlApvwlkp}0AGSKts?Ea^TWKoeOMU{y=Dy_dj4$~J z_GHGFoa~y@(*bu=u7@6ZG5wR$$!9Z^nJ-+!w%%eF@LM^B{$cSfG_!K?q0x`{1EQ{C;5_3 zg56ee%-?E!$$!Oz9q=XJ$f5yX^5-Izb%OFo#p z67(e>$P7VW@?SGY(3kuq<_P+dlcW_7`jYbvM?C0D{uXlteaS!I@DKWuPvO}6$9&1- zn7`Hdl2@|&fG_!<*au(8mptzKlJlw)_kGFtVo!XcFZol*`c?Uo^OY93Z@w@2CU#EH zm%KaDaX&_4L6<+HRo0h03-h-cU-G{p|M96;(dkYK!EsX;v4GQ=)6r&Se96rlwljjh zcTQTdZ|G^P-`9Za3|C+DLcUvYH11h(Z* zog~?^?{;{2Ejofbbz}ki_2)49 zGa9a@VXL#A?1PcB*yKFQhce7#oURx+hL*ScqEY4)_~B< zPwagdwBLi~Ocu7KSt!gud|~HK&Mn9L3{#rdxXW1DPc)@}1r2AbcAP$}n}yI{C^`gVe{XKVc7&2lNiK1?m?4GleaRivvKg|(4Pc2arAGCNb0-RXA+G@45j zlh;%Hz|A#+nW$oio6AvKjupL~&_}KrZa5vu#HcWDiJ!x#c;@hI;pc5(oBu`S-$PJ1 z2rq{Ijps!sy8yR&{*1{7<$ub|$fPK=!sN?_qJU4WX?8+qw>*EUd;7>7PPaTG=dhe_ znc1Onds*(=>y-m43;D*q2V|6e(ghERW{T}&*$sVJ8Uvd7G5&YS>Nx#MF(tH}47z7- z%2ZjVT`?0e7Vlr!1C z4!O>^cu|>);5jS9O^mEUfS$llUtn7h&PDK?`jBz(zs?HbCPwH7fs`n(k^UB}*XYcp z(V0Rpmm6m$ffo|PW?;nDJ2O-7luW%#gY|-0!Fqpc3NLL|@7{Yu8DwbKdZ!Xt2UrP& zMF?Oegqs+#^&UmwPYCE2gsTxSU2~|3k=v~hZeqmlZ$quST72TT{we3BOFayDLW)N(9SGi`!Y}#iDkS!QJ*<_nW_yL0FG`i*( zU2F9O_7+QkY~dfUAlV{hey{qN{L}H*Y$0=;dLZr^mW5HerW02g?ONJ2zBWT-l>u z*yVs8={`YfNU1`m`U9%KsSn%Kr9!6q^|&D(m;!{T^Vi>G`)Xo{S_ZU`GPkf%79xi1 ze{7zeT82RHhC@{F6x_wSvlq0(O!jmig0Y?Qd)^TgHYk_#1Uy5c~%E`aX#CMJPq6K=50HsM&&PgP>`d zJ{-D{2vrDUcat7W8^4?M8PLt#jh;Hct?UPXI}VW(5l%+nU_2M$LWCb8a712*a63Y9 z3--?gxQqId#2D+wf6(GNi^_0&i8SjLQD~Q0JUdSoOSHywcKfQLo1JtNTD!Pq0?=%lw3o*0}lk z`RyVFV1S9B^BK|hsG+0x0~%^y05Xr=pFf)lI(pyt^`%z-{uh){JzKJA3 z4$6x5jwHKB=b`S_?3g0v*2MBikESA79X~ZgX>>-WYX)m^0|ny4jg&+5^+08}3nhE__boADlqj5=1Z$KB!f8 z%6>cFy_qNe^Rv~=)ff}On|ZneQ`wtKFJ@A2Htm0gk!6S|cBO;NJoj|^!6DTY?f%(q zS1oA1N<_7t@1INm$cigNR z5FEr@;emWU{EA@?b<}LuKG@AP^!7xl17DVHYFV%?c4g#}F1>c5HpESyTe6nD}I? zuaTmIlce0ip9=oz&p!jcuIcZ0;q4R$?znlwJ+f8t$yw{-r^HT;o)$She1`X3vUi+4 z{2k-TmFX<61$)RdFC2pD^lHj%9v*4&3JXuE_Q9_Of5%*toAGyW_2HY2e`F5)AuNx# z%438Rgj0pHgtfv(;cDRt!n1{ZXrsLi!W)El3hxm%C74ky>^(PCt3Ml2D3GWsDM)<05i|}LNAUt8Q z+-M;^E-2RumkZYk&l6rHyjA#+@Hycd!uNy`40PJv!{4#}@LJsBc3~Lb_f7u@YlK`0 zlzOw&FYpe@F9?h9Zi?yt9QdOobLma$CkbZ@7YG*%mkGZuJVSVi@HXMyL>x;q$35_2 z%4owzrN1os_rlku_jxY{(l<&rJRa=F8tG4!-tc&!UoZV7!fTX%z0mM^(7wBr{;2R-;U=Na-+526 z&)W&-+J4L;!cKc4^6V{nAK?(`M@Sw|MEfQS50QR05#^7Oyi$0w^k+%Fkcje^2rrZV z2FW)G?9tD5WXV)CgGdXZxQa0{%=AT`%1fQh-gPU;a<{r5zH7!= zNxvTv`+2bRlZ4ZyKT>jya1jypEmisn(ytSqA^ka$FA!c%M7e8}ewXz33LldGIU@4C zB>68&e@FPP^e#Tq@;K)SI}3*kCkXNLYV6@MZ4ljNFi%(}#9gM*?<$UMsvo_;cYeguKsWefJ9=7yd^0yznLAAB1lR z-xmH=xKsFdVG1`{v|lWwhb!fN!a>5J!cju{CNp149@k;gA1Q3PhD4+ED}{70p`G=@ z3xtMm3_YDqnEsG(qmZtG)W0nJz3_j9n}udtSmgUaatJR|SuQF}2)QIT^?M1)>7d+Q z*jwnYIpOoW==j2XKA+315d?XT^mKAz`YItETqvI{Y2p*(wpZ3r2FSPhP}y$WP`YEFz8W|dZwa>w-xcl=$E02$A1BSgZ<4<;QqbNSeEH`7(H;+rZ|^e1X%E$z?UasaKdzVl z#x#Z-gnqvD-98`BE?(p~LwsXE*30cygkbwlM*H%hWBYIj)9rg0aqM0_z-*PU7aXf> z8#iKLcsR?DF9jtI->0tWa&9s5A&?!!b5mx_^*>Tzt%RiJr+7+hm$Hqnu|2I(%q+d znw!erxcGZHmc3JLYI4V2| z_`?$1LUdO5dM5`$>A6w*A$x9|?#-bcC<2ZiFDaho=y{8?}3j2zFr;VL=pagug9xH2+MbH@dohq%;XM5 zVJFmyMy~f*G&G#XZ|ulH&$VC9f({*;fVMT`p(ez@*JDTJy@@~M>ybH`Fhqm$d^1CW zUHb)mJzHZq(GfcWzMd8133}avuV=;F#5phwzMd7$+ArYinOpNBuKjWqlC$YG-xc+k zeM8+`o`8J4+gSG_G_Y@$HQ*%5DGrqwPH;cL*YhiH%RLw-F*hN;o+?lLo=qFB)Plq| z>>~JjHnlLp=MeDqtk@~hlbJ_IOgU}wYi0R*VbqZ@Jf(xP8E3DrVIPdoqUaT^brX|t z(81T^jzJEYHATSJvoa=n$XqI&Z6icpekzksi&0$lqAd_CnCU(ZVM#8fu(jx3&|#LRceQeol`6dy3X#I;{ep!iVd`+0(6?U$2yXddaj#fZg;2ifY!5^eDt7b@zN z;99HT>y;R>ZyPL9?|`poE3#|9fUjqFAkEjaZ620*nWmm;)8CY>Oe~`KY@1O=9MuNS z77qA&)>KuZggyC^+B`n-Qy!(4v(4jq(d5KEY~-tLM#cYOhl*wWhyl(c+3_D*sR?Sijo zcgRWBvNOQfyUOfBIQazA!Pm2LJoy+a24Bz0xk)Z+MZTUbpO?IgGWdG0X0f3K$>W(H zd_9|9mgFKwG?0}l|9EaUnOKg)Hj@eE3!yMqe~vp4J@EBx4~CNyxc}hmX+)q# z?sz0j^M!}NuHox#rm1Uruq)lR6ljWHYRK2Kax{5AO@ps@C|YOudW?L8%xZRrjpXYM z$52T&&=mN3{57MgEi4MYo;{A?Wn0QG7VqPo^T72T)c#QJuBBIJ2OA{dRAVQ#+r1(FQkpDszCZM-yJrm2R>J>jYoVDzNqo-(ZoiXBAlc zJUBd&B=5DAe7#qp=*X)M`FcFK z9l4k^`FgC?*8jF&sL+Ytfvn)`QPs)iWx$MX46u)&iG+EgW4=r3xsT8kBOVF2#oug> z!J&wl27p(`SC-`K@yds_U$~kz`FdlG=!L_4)rtGDqflj+XQ7O^ymusD?+385Hy4gN zKE?N2P71+sQ%xuUyL>f8zTQ0K!rCw6P(HNIHA}6uz6`n;Cq)Q>!FN4M#mt96koWjP zHxg!gB+OM_y1H@htH^u&9pL8v77u&fhM@*`P~J1hb~uz(2;D|fH`wUjgZw6SoD{+x zlJ_L?@!aEWTek}4+qdllNPhtGuMmo=nQuR%`#a<<)EUxUWtYcJe{!+Aw!{Qeg147k(aV;wx^9qD2u|@@{287uG0~J5hZIg*U`tqCHRK~riODEY zpDr=UlsFYB>(V8xj!g9*ni7wq#O3J{b?tfFxB$@o=@M4=0px8g(Vd5k_xACd@W-7R z>G3ucJ^z3|N1#6sL+Hhn-aDbe*5_#a2@MK?X_keDn|02Zuh z7{*zUyk*&5`+)7mF4qAEW6bA+@d$xA7EHxp!}vk)nO-o>IG?PY|F!Wl;%4cI=6=@s zP8p)wu*eoSNI^!JWpIGywHFe`BY+6@ohC-6Tj97SMtE8w<@hE>PDTJljPO0HU(>|M z`9^Qn)VbN{>)j?sp0YxyiILZ>;5GTJMBPwn+g;P9WNe!ScC78CLE9jRWo$1E+MeQD z2D)x2NDlJ}Zc~p#8UqMlYnm8gg&=|vZZOfq3A`YA&T6-bkxf6Y1T{vHO%POcdu4Mv&Xm#9&) zl~}(Bf3=MV@|Xu~hRklU?+cujYtD7Y7LV<*LfB<+hJs~>WsADQrj;uE9TgTfFU--~ zqK#p*H!6Ib3JZgUBfHy|uu-b;@hU6~7Dlz$-5c=dHb$JO9750A=q3OU0S*rSn#~g0 zcslVA8bX`t5fIu8(zJg}k?LA)y^yK?aRs3*WK%(VOP95^;D^#>hp_pees#i6M0)Fl z81D`2g~vq9CB??!1FBQUX!l5d#}=xJNPg!? z$MQ)2J|&SzaU{P_Fx@h;+8M&t>y}srR#nHScRpBEkyNB3780_AugzX6+Rx`=U1~X3 z$Dl|FfK#7GV2(jJEjeTdx-0% z$p>2A=byJ&k*E@bR}C<9pMS;DMPHD31wzLVe?1qoWYK>%|7s88YS}-9arHG(s6Ic@ zi`Qhc^w2+paAgehH2TV!S9_K{!Ud{-1+P$F{jx`aZ~KNgR41{DnxmIA^iB;attc%|QCVJ5-apl=p>|PiO=E5E)DgI^Dj8BT8%*0d3sMcWD;72` zT(US-F=%kv-~sp&o{Kx!;5tZs19!B%yWK6HYDBBDP;Z^a8ihkKcgvO5=GM})hpDHx#VL;~77WI5` zA}$ruAByrR!n1@I3pWV)^u&C(3m+8zR``OD@5`C*9U(t0QjVcBh~}L=(5zztg(0z~RCP!kNNjgnTd0e8z7Wc%kHL zgvL)8`iCSxD|}t}uCN`R7-^?SX#9U6kC1Hqe<2%xU*MV2Uo8BY@XtcN{-!-nUPvq! z_7{#6(kqAQvxNM_K-u`(0Dmp{Md6=>?+YXNn!x-8!imBog>;Nz`geq934bK~iSSp# zCxyQgZV~=Xn81Liz0SfCA?KW=euD5wVV&?e;n~6s!k-DJ_!bsfOX(#M194H(uJVaP4TrONEJWqI)@HXKi!WV^a3O^F&;5!`mqm!^ic&zYr z;e*1bh3^RW%eLixUeytjeO}dk$*YBHg{KJ56rLlzTzHG{KB3`Jp`DzfD1>ACC!xO% z(tFD1;Pn%EF=1gA5#DLHPkp4``hDU|`=Sjao`YVM$CL-KS#D4rr`ul_rOaHXw=Y%g45nd;v+&j{57w(YW z!;d)oD<(`3k!JW-DA!f`?!rDq=m$#PS9kys<;E&~n)Kfi&Xj(>WW&Qky-O*h+-jw- zQ~K$`?@51=@53=3gT`NoZU_pf|tEK)TZ~-;acs39l2<|BC7SMoxT0_>}OsLb^CHofBCT`Td+o zUsPhYu$8cbu(QzT4f*Rswd4<-dHpz7`U{1Z2sa3?6y7AfMR>c=zn(lQ`3d1h;j_XQ zg|7%V311ifS@@Q4hwx)zxyEAw)*s|JH%bZd(=S=DB z#zv=a%7e+w%z5{OG?dMk#Ir{7g7{j}kTU4bN{>AZ;e%&FbxqwGnY`VZE%6 zMTkofg7(@XLkc>7^V5!jB4}?-3HBE{+QThp+TMwX`(+SyDv%)_Q25c~kQTIeChToM zBJJfO`0e9)?3Y2*8QLEA7}yVg^V8Nt5wzF0pWQ#&LszElZ9tr5$`H6+*a35q^P;JZ zX$;p3{d~u!cFzmCUHJfJ+nUN8YbyLh!|O}1eFM-wzyJ8|!r$MA5XbJ-1I$*|_4Dz9 z<|1DT4M+EUDlh0{jK40jP2j$AYl9HzR;LQ>d(NcTKYqUSRc2oQiqEzFR#|y@1!+N_ zgBNsfk*TX0F9?jF+^x6t-{@@1i@MwLBB5=0;rV0QZ3(YF6k-0`r>=Gns6wpW77rTF zXrjnlg?PIyA?Tt;7eU!7BS)Z*7+n~)st|tx>u%*1q^i1Bbu;U3b=>&$7H9Q(1Y>`{ z`w?riapM+u_4g5sZlC)Ri$NEHE@X7~1GnB)f1q>ERz8E7T?xD8ILUJ(IJz?eo#{uh z=2iq9i#4|fq3^NI)>H$rr6`THwZAmZ>!PJc#}{p(qQ7TyO2K$PR=qU z#KV!Ry)B4japBF#wYhgQ&L6GFkMpT_vU!I54Izj5$;pXak;S{?1gENrTotQ>8jiM! zb*$pL$m2!~JKkz0U+=M~_b23!+}QDZh?A2u8X`L7D3oZ;xOXvPvG%4D@^(N`80#13 z9d4q53FZ0bZr5^hVil?}oZvg1SVfL)Ks@mW6o^$6STQ&8A&XXYw4&kU#QNv_8hPO1 zkB&MLvFs`M^FIh?-*Ce2jU6wJ4Ti5j>V6xojqRJ|@82BS8!9oJ;ET7|eiGw}g}BDV zhDpp#yaxlZ{UzolUZgl&VnO2nXzBoog^8Kmk4lN15_CI`jgXjf+V(|Faro=TdEgS< zgV@2@jI-C#Mkh8ti=yG=oJG?U&5jvP&f&~HMKU=#`$IuezS(7Pa{dqT^=|CQcp+M0 z`}?T2jMMth*|O@W?SgRPX&S4^>S9vk2{tS?y9+x@oE#d?CRLw7HAKP#Ab^uYDo;GN zJU$zkNV4pTHjJ|({v^a!`W4~uaMb0|+jT+g*7(cVDROdRx3yIPa<7@J9kUIkDR% z#S_zL`;IKW1|}!xa5O4*r$o!iiT$#TIU|em61TGEyHvI?F_dK=Fug=hPHUEZs56(N zBPZu+ijQ=@%812@{n^=%B}gwJCx;%@vB$ICFrww;#GX<`mXj0vjds9ta$*}*@32H0 z*85DGznHR>i9(uswhdPW2^CpRPV5Dls!FV6=9g4<06HCr>O zJ!e4Z6^_jc#o0T_Z?P}H$+2U_NzO*07&tjc@&#Z~ILV18AQxCUp4@8FyI46l$%zf95W^_a?a^kiZSH7}-UZ5LOW|tfGSKiWUqZ1c+=Q z35%90E{OW6b#LuwjT`P&YwOZhTkG0tt=PI%t+iHK#bULsmSX+-f1dX|bMGY3THCMx z>hE)4<~i?s_A_TDb7!9SJsl~-CdZ|plv%VeFo89+jzNly z-Me9vLjl)#W)b@fn;bWSvCJxFg-woT1Zrf*VJv}T8K0So5?Dj)8WzQ0&k5M%P+(Cj zIoV*74hx$zkA5Bv!LKZ%@D`=Y2d7XMW41u*uIknc*`I)O3 zk2SR11-CqNG~;2D*yJ2W1#EJh0ya5^ zvt6*sakbDUXEF+5t87eRlS7$}G8r~Gl(|fq$+XEyz$RxF6q&c#1=!?J;Fx!3A7PVY zPR@G5CWm)*3YHZ%IXpSMkRppYvE^-id z?oiWxAM!oa{R%_pS9M&0bj65fF+HAPf5vzCJmUE#lW#S9@)6LVSVSFfawlPjqP^d{ zs06kdU5e)AwfATH#b|0IXRr}%ZORe*%zoowTd1b9j7?y=KqHj>WUC^vi)>G1*wB?0 zBTUv!EAW{9&_Wu$bcY{-qHzT@g>jY;Ot*hOSVDA7V^&!J-vJI7Wx-$4VK*xW z4#5>pPvDr!${`ru@Uk~u5skYzwwN7xUK&|CF z@Hf-mGPy-Uc!!DmUfd>E^!xaW9WTKu8om5d^14CuJ{FAVXkW0c^R~wKgC6Y}gr4Rx#P8kg0ru065UfCf(F+jz|1P}>Cm{~%CfSZlyxoj7{Iyr#OwrUkVt zYgW}XRt#AHj@yc%3nosVbNHO<;SLu}nlp0&sBS0J)iyUR04dHnu{ToXy4CWhPM7vs zMtH-TruvP!bu<>QTrtt2%|U$~$$o+3dU40wEK3k93DJ6~fL5N{*DYQLfBB2Ss6$~` zLBd$q)zwW zno}?9`Mq|1vsDid@J)5iUc;Qm+VOUrz;zfn#29D|F_&D(t;`S*BY~*9dR>;6={)~u zmtjC_>KftTe?t8-8`;)NC{%L+3`~K#CM=dvO;7#JtGqU+!mS>Fa=@m|y8qwDIdh9B zthN;&xc)%((siqAy?waEuf~MgSl^7rBG}fNmDM%`HBGh6^{eWf;2MPHpmMKz+Kh=u zR?qb|paVSRHiB4a0;3LZ{Ko0GhF71+r3|cPfoJ{I_yUC!$@98u4HiUjHAB&~q#ld; z)T1=#d>`Xg10lD1#D-c88&5G)kHEf*LS;;YVYnHHeTB@TJvpBen*5l>^ zb}M+tE7vT>oC!5zF(4wpJm~e4_sB-ux@Pannuj|fvbi=ZeG4_)nedM=$AIEA2zV5Vc?P> zBdFmd99Xlse(ds^#wAeHG}bO3i$6N+N7fBobuZ|oS1*H-*IhHlY9JQFAvQtBud-ozX~V$UHLIH&YigUv;tIf7vI(n| zKCB^*=FJhSZ(72$W>YYCjcS#a#$ls4X~T=bGz`~Jui{YuhuF`1^PkH@4}E;*n^;tQ zMr=#;%*a+hGVifRA9)xbfuweXD*>0v(|LPg_=HMhmQcmJA`_-q-DrR<(ggEUcS!dn#2t;JzQ=sA|^Pa@|T zKk%%V9OKrUXLmmdlb)e*KicrxiZ9d20pmA6BEOLm@hQ}}VtkDdL81ZD^Hec@v~av| zs&KmSbHc^Kdf^7)CLw=WusnXgB3>=LLHG^f_k{co$#lOICU9ygcM|py8V3vdsgh?4 z1FrK5$z1rG`M)F#IL^k2g8nzszc1voC)1Y-dkW2`EA+;70vfjoXq+bC8m0S!@Lb^) z!drz;3SSb^{S)i^voMLNN_nJ^uaYU##}~0)c$M&W;giCbg>MP>2vd0cX8tnaTw$&7 zRN)1}7U6Be`-SvC!*b{XhX`*LhP{Qug_DKzgmuDo!Y#r}h1-O82_F$YE8HP`PZ;Mb zC)O|QEgT^{Oh^ZBOvi6>#6rBxBX$<{6^;}hCR`$H6rLu$NO-^SN#W0hyM!MK)3^p% zUpL`E;aK5x;X>hR;VHrkgjWmi6h0(;Mz}*b1TQLC-+19BVZdp=LGmAjk$jiFM7W=D ze_^ne1f83(+;PH5!Xt&p2~QNBO2oO^BIF|Xa+L{w+=T6CQ3voNK_F($%lM`1ay}jE&yT?hMAUs?+U3j$cIAN`DnUHUX z*nhrpA@VgD@l@ei!gGa}3NII4BfMVtec>a*9|^Y$pBKI)d|mj4@Ll11LcaB7djg-; zT_o=>wEHaL`%4}w94V|4P7(&(SAI%oxl4r0g?xKV{YApB3a=L4D7;l@HYiAckK_l0 z4-20X{#0o9bEFSAu6AFC{FdT>FSPqS^gi#mK)c@qaeMf?T*`lgPjCL2{?wEAx?tQe zv^IW#R(_2sW0-9_07s_7pCj9b2?Jmpx4zhMEBnZFd|qi=?>C_fHeTo4CSniDrp)W% zkGLlUTM&0B6u9kpRf^b*jum5G@OcSfPl#;S4D3N31ihE>o}F_n*n(gU6hWAAkKvxg z&&z`^te5q%A4J|yf;xoXp!XM)$8^CK#GL{~xV#5KDDP5)gFGyw5QV+EkN#eWxNv#fQ6Brp_Ti^O zw!EtmW_cCZx&5{SUM2D()y6pPw+e%F)p)Sw>-b;`(tQgGhJ)<|qzli%V7}ai1mX6* z5b7_QkZs?i2xBfc1mzWiqYy4HsEZgH2CoX~%Aw>7dp?u1UJRAh8C)9>y+xRRJ-n zUAS`g?!v+?AH*g<`KCAd%n!V?{V&hjom_cc!K9s=C(YiSEPTB)w9EW2&)E6paWi&a zRdLkLvyZBJD;n+oR;*~&?pWdM-LYw#k$=X{n<}Wkqo8W%)~e#Sii&3JyrE*o&Pzrf zwsXs2jLE!Jl$fz|o29z%UB3|ALLc11$URU0{LR>)4*q46E}Ddo$pwSAzp~pae{r|x zZT=wQpH?to=cyCES2knk)s+)a%6H!N3%Vmk3@KuND@D8X_7`_2%U{`@+-HjDS2By{ zEJ~PfaIfznQy%)wc-%kS{D}DraHA=F7c*j3=!6DA@CTDPxuD9;$N2|;u-O1~1Wbr! z$P}4g#(dxsPDi@vP9~nwd5NhK3z+J=3@VW9!kl?S%4g`kj$JY?I@!IN+u&F zIv6E`V>qAT4Y>ZIqe@m-#@PEz%B5YvH+&o_kVJ6I>xT?}v^Rt2)-dLG{84x)+qghgKx;rlW({VA_kEz4cjpsy$T`l4VNIkxDb_-Z}DFTF_z{H1bjm$CexSWynt`$#KLq6od@60iN)#P zqCD^oomiSaFb?rhiDl`NnYc<~*R(NK#!Cd>kV_~T-;kxGf6jW3%x9RRju9i@kYbcR zz%ODekFt(Ij-(ed`7Fug8?J)lFGy`&2H%j*%Z+b16#+Ni$9G_ur9aD-Rp+^O$I?4k zSWW6Ei%q84Fz^jISmGP9;C#}>xvPeFYzYML4bK9QZ+HWndKY0in4q| z*MThG(A7I8&EEjv8+Nh0Rq2T=>Y4TjnV97px}qkfNdW=h(B++$=JP!GhWry0fe-M5 z*rQiE^p8`Vn|_{ceyy+uiO4tP%L?!fc?FYi_;beY&}1XukcBd9M>}w~bX>y&^*ArX z5!H@Sozm#M;~R2xGP5}r;2Sa>&S<6%naDRh&$3UB%uiShWk+l-_XU6%DhGyd_%ebrVsFM zvp(<*-L0f5b0B5#4PE+4ne#Z};2XO5shLXV2j9^77@wAz%kE@)|L|;peFU-!Ko)gvK|V%p$=zoQfecz9E13 zk#9)1#L=F{H{_+@PSR6oaOfnN$j0F$(Wo&Vy8{VI{nw!31PvvnDmb6?J@3lnw9O?# zewxh~zmT)gE@tr!4+&(n?oxIWe8VpT%Z8$H#y8xG6dAjBgKtQIGoqRO1>ew(V9dO% zlW(XQfg0KIc#OrD@m+xN4S&L-_T%IN-;e@}T1y#xLnr5DjIZ97Z}=J#tJ#ikNLpHE zJI54!L;f{mQD0zD;2XO07|VQ(tpwkYiODxyfB_=kkbfq~H{?r6@(o=traIm$_=YE2 zc{9z&IQfPbTT|y}9^wFjZ|E+#<>t$td_yNUWX3Qad_yO1%*@6Zl5aQy_4AINxtbM% zZ#cyi;2Yk^7K3ld78u{~L3RmzLl$9t!`Bc)zM)fqZ}@el0N>Clz&9Mi6yO^=1^9+l zRDf^j6yO`KV7tIKbhVIgxDJJ|RW_#J8&YPYOa|YO^3j1D@C{FeA`@X*;2Tolm>1CErbxkx0^g7)hZmA$$2WWwiY~nCkZ;J7+vRYc8}JQTtE>OHAQSk8KY$W^ zL#n#^ybajw#snjMHy-1KF5lqnBQ$jP?>vO(a}M@^Xbk`_a2%@z-;j4c@C_fO2)<#3 ziQpR!KnEhp*y$*<`(234@eNNxDf|Bls#D5WBGxPaDVtT^f+Na37zMz=d(Weg3Vg#- zq)Wlc_r-{9$JccU{@zJl;(UO|W0ye{kNr1}2l!t>Y5u`v4T8vJN60;BN9&Jne{l{1J7h~^9rlNnSrQ?-z zH}+ml>sEPwRXa9=uDwshjzpgk67fed>v~#*!c3S@$oIEpS@+dS@#!NZ_L6_+FmaJH zzUku6Y+h0O5`_vtKP#@Oo{M3KdVP`QV>|NwjNUnrw1@@fj&6Yns{bN^6x5cGQ{bS?eb76XtZA+WxpqnQ z+Mz@KLln=kAYzt);+dg0-xHmm+*CP*4Rr0xU~~hV`bJZO;_ad*j)|xGj$vRBDWFlf z`|Y0RPn#O=KPcY4BHn*MynC;B|NimrRq+EGpN5l;;;S|}N$-7Ak^0+dG1Xn!(D z#~?S-OwFc2VHPjS=pgef+~G7i?{%b6R2%QV)H0)W)QKYc5z$CEo^9SMbF@>u0BV0M zdN*s#pa==y)qBxO*NzxUrWm?=b-$pfc6kyCpqu+h1 zh^K8hr?^$~GHS&mguTpzrp!IQON?!lYlCy|euLAx;2_LC^f zM{RR)ijx}F;s*$RCg5ig&ms9_?S=gQPZ^)(KNc@_it^1B9xGfXTq!(Bc&aeqqh2EU zD&eidZwmun>eG^qXN7kDO7ic7aSVp_M`%1Lq?;m{--Q^zSh!Jmn$Y-Bi2rZN_X-~q zJ|{F^eMpz#&n;jd;c($3;T+*&;acHlAzz*`e~XZ>o+;la{E_fw;fF#lY{zu`t!@zUrX< zcHslUr-iQx{~(OvJvh^M6xIl7=}*16@&Ix*PRh>PSe3?V;iFu&d3f!9dB zUdRs|jDJS>3*oPXJB4ox-xC_C1o>cyYWeeoX<>U|S7Eu(Ue_VtL6V0FNdRIy4i!!m z9wnSDq$4G!J6>2PtQXqf7sOvI`C8!(!fy!8_dC)(B>6GnPlaRZ@K3@h z|BfJCLRccq2zv_q3Wo~K&I0*xoBg}|-w~>Z&uRa<@6J|_M4xehF{a!wrETkrBmPX_ zxz}yOgaHKU20+0u&mA|WM&rr6!tq2Es5cKxP2VegE2(}>ZbST2*#c+a{ zj^*+1PS8Hy^MgDHdV^6O$%?@i#9azSxV%!7$NsTA3{kecZ3r_@1$J&*k>J|kWJ6{g z_dA3^y8ifr!H+A!7Nol$3WkI2Dx|9l1Yj^}&Vf0#Oa($q;E-ib!qZBL&SJIf#a$OmUE zOKqQg*0i(y{tQRAZ$9gsvmW^1v}F&y=`Fkejd#AtdUpKA``$fxo^sm z1!!k5F@gaCmzJ))Km+|AuIuOkocP$tvWbWWuhuNwB8j7rAi5Z;*z~f6jETkRZ!P*H za>QnI=1GT-&UMUBTe;Y>veT(b#($1Vqx`cQtM7c7sS;$TI7Q^)Y7q2K?!thfJk1E-~Fn_Cfy%hP23!}2dSRm-qx^?TcXSwUB$w0@A5X1l6$)i zIt)5#N9`Dn`beAVWP@4!CnPFM4Nmq%dFeffO${kw7j63J+^L|9Ua67EAG7Y~S-`=m zpnv>}k{T^BX5`V-Arh16@#srxjKsn;ozJDlN-R#t+0trTNk$Rg)rD7__uB8j_vwZY9fHXKKpPyzb(=E`b>SNJ$>|% zdpnzn?^E8gG=Ep59*y_jA{Y~tbzKeZ& zA~o4W$GuJcSQR<$ZR#m?z;SO=+g0zF^ez_l)AmPN-l{a0;7L8x{&OZe?rrLM6*Vb6 zhbR3-<(-zkk7wzn{5$};x4&Z}U+Hih5|MkmjEP?>ywGCjr<>TL*Nb=slY2|vY-)!l z8@abU*UZ|{4xB9=TX>)z=cNu&?HJXGmbLw2sYQ__M<=tA<$`;w%O&#|2Ls&O`>hMH z%wvoP_tweD%*(8JS){v@3(fau3fxU z2KTm?<)4-zOD+ZOtxG>Ma}Q;3Z#g*R-VUP-?(Ngo-uW3`S1E9Bc_|t9mJIY1xVOAU zjC*?|72w{EKn=#dO|nbi-fqN@8Ta;emI3bV1WRGuTV4w8B>fesLnp~ZHV!9=#*^{b zt4L4^UvJ=2qrgy7s)F-Lr-rUPPTO1}UV=~<_m;EJE@p9WR|GO{>ipfB0{8X@=uFwW zXk1|mzCQ0kij3V$z`dn_Ydmv4M+n?oH-fRuCiWlPTg?d6$d1QjEWV7tvy0$JHOZI6 znQwDsz`dowqPSv43fx;K=VkcTEd}oF5$L}8`edL3606yrx2HBo5~OHm&R|jC-d<-( zy$pR8rog>*=P{N!mmLE4mWj!|?Z%?Pz2%W=y_lMLfce3_wLkGaXJ+`| zmjd_pA?x-0%wVPm_tsr-%QIYzD+TVYlN&O9m>%3)CvP-fY6{%jrKq2G^vuCb0PgL2 zQ-FK>0$T*`En8sR+tZi=+*=l5+}nAq6Wm*;0QZ)ULn&}?odVq33}+U&w@v}>ZFgn? z_tq)Ey*-a9z`b>~{0Q9JZ780tvM~ksmNFY9_?EWVx9rrdLzCLe8Df_pB>XdT&UhvAEu-nv2I6ACK{cWIXl)jtBT7 zP?|rAe+P0)wEHPM4fmj12mj#qd@EUr$a3sGwo*6RbS!-vb>z$Yhje%d;R+PPN4%a( zaPY^pe;0ZEIlZ=`LH;;P!FOG}PJ0^}_t181L@`E{W)*!{Z7GWJdEk?RKdtmZ{MhbG z*OaFr#b)gNg2)38g!T$(zJgu3nJLNxeoi6xNdCsO++RnU+nGCvwA@cX^Fx<=EDB?$ zC=b0Xcfm~NJ^>N0BF!t<`!0mA2Z7xbW4%^TTFl&##kSJmaLpO{7VfSZ=BBt{yR<3OHqAw=m8xZ9UV?lPEah`p~;QmxI zxaokl$G)7(w$fpmk-%L9r?p`Mckg|Wy8CqVhm_3r@10OUx3%*Njx9LGoaVwM_K*^J ztnF8TX~Tz_1Bd05{Tar!o6SEjFPD2jfzJ&MVPq%O3;U(o(-(Yn> zUU@6jREa|nn{-(YN2Qe+lu%HR^T|6D6#P*9FyCh~+i*GJ55X7gWzxwm%v(*c`REpY zE88X=@0p;26L0u=dnm&8}8d~cqOwPVKz2pPKZ43 z=!;_@eKS1DyB9XxtVi$lbxBHZ@9WA>RmRAn^6{1w>uZec&g_;y09?1;~#!(8%K zEzHZt_}(#=76;#wjz+c}U5VZyWoF2MBC2JMzFQDA?HkprveFu!VK3 zE4+pC^Tm18qvh(yX4SXmdOHcniEA3`1|RO6Apbi!=ASuM-Y4_kJpblC_zf8j+9K{q zA-Bgk$F-}P;Ocf+ZSA1tIP35aT(`7_-ea3jY^ZC34s*=;z-@+r$1Qs2bfIh#XyH#5 z8KKADxWLyk)bh2ApEme?5_nf06HxCmOv;K;69$Ure%yEYqW!{?C4jFEQedpa) zu6!B0ie6|#o?^`x?NSe;Fk}RC$T}h5iaNv#{G7Y!)+5)-M{%{B_&Ue3&Y^E`j^wvm zZk@d9175dW~7=NY^=^%B_5o2TreZ9<^DeO~zJ!x8<=raLz5a+s+p_yV@`dZL%EJ zar3s$`&Hm=o_@a0BK+W0!>j zu03;ZjO%`7W8Jdqb*^QtF8#psymN0ZPvmHxbCMjkesUHL)iT4$7NWVByL+|ra_#(I zJE!4c&(y1Or%7(-F=a!Jv|IDuo$V5wa<8swghzS~Xx)->SF`g2zAta=OIO=pZhB+K zasYuDk#mdQ$}O}UX`@T~^gEvQ$ewkCZ$8I)kChMbz)iWc3V|naTomSO=oY^cl?`O}Q=i*iYRjnWN8f-UmnD?y7rn^l=Zt(<5GL zJ8lm-s^psx$S!2)`$MN=Sc7jHg2`;$MV? z_(ef^pzsi(t$Ppsv67byza+d)_zmF?h5R+b^4bXp3dabK6dot67jk($=KH4bA>l8D z?+E`YT@;TGX# z!W)G53V$eE$xnmGccRdo6G8rx6;O75K@}Gr1?p5Rl$Au{(+GN~&)Yn~d5211Ip|6xYLTDU(=%+|NLO6p6 z{X*e#=~oIj2{#MRCZav(3ojC0qxkEEw@81x@LuWf6Fw&WkA&NWuPXj^;hWO$6233} z9$_5!aJDC3SS0LD#5na39wZzr93|wEbWAs%h;k+i=LwG^qOKE&NVi(pB>g7In}z>H zL^&5I{wnFO6W%2Kos#bsexHbZj|v|bKBxE>g})O1M);2KkHS9_QO<|Le4JaJ-)_Qj z!i_@wnX&Y^Z5bk)VX=^3URmA<;aK5#;Z)%?;XEPV6*J!=;S%8r;Toa+-9)-glD7!Y z7G5O0OvtakEcZLY2ZfIcpAA*eEIzQ2P_h1gn`d- zesN}eV1sdp8{h3^Uj8x4LNXFj@bBlZ&Z6SlRzFdIIkvjyORbCqts zaEWlakYCkV?wP{#i1=H<@9NZFCFJ*W%6AFxBO)EYpi^(p5x`d^zb@p*a>oCUkl)KG z2R0V`8cw;Nkkl8J%WvY;PZ09^H|1l5#}ko`U%{zgE94h%%4Z7s(VOyBLVowAOx_(4 ze_pMe;Ch2-`rvxRpD~kz>#|I;y~0QSa>>1f6+*tAXZfE~zxn+CziIn{NA1sSKQN}; zaLL%#7e}5ioLbv>4#HcIZUB@F^W1Y|y3Gt|*?H-l<5iU?2Ux6mjA53J1FWu{;cAw!Cc!vpiml z+cZd)*4z6B}VzEZTW7&^AE1NNZ5k0Xrk zH2`eeT<+$e#OzqGjiKq`eG}=*q3i@be^;|Smd`pv!{t45fctz1wQVei8}o$I^+Nmj z_c_>tbg=yx@v&?_hE*P1S-R(N*0|vWyU*RYUb|P ziUqr4N6y$eqW9oETizSI=gjwK>>Sp2@Sd%I8ocL>Klc70acQ3qV#hX2e)H+^X7$l= z`-Ok@s;>Mq&hF^a54_9MkbTJblHZ?leEXGuh8MX%N6L#oh+O{AZtntEfSi8jl$)mf z;y2yf1!EoaM`F+mIVm2(z9<+SVWb(u9y>5I9CFmp>yLRA^^=$5I*-u)9JU}c7!!$` zokb*J#@d%c1zV7M#>C>^K)T2c$N^grK6gc9i5ZZh$@q_OdZNk1)i@Kf`9Pe#;^6a4 zytKoCNFLeDaCyl@hSwt_>^~MVJc9a)QqHSrGIl0wp<8X(dAtTyJoW~TdFLR5AK`Kc zu=8MpB7CI*I}e5vYYJCDerEaa9bvqrwi!f)^L9Fo$`<2>jvp!|g0j^W5V z2*J*S16AA=3fg%TpuBV$4zTlJ7^z(pOHZMAh{R-i zA$u@JVquz|dtv9H%G1B0I8I_|nsiRsdAQiJbc~&>lGrs(fB3NTaIxiHhf<7+*?GiJ zN4f{jD(pNM=BS^{F_@O37^R)ZLPj5D9fKT6-$r?s09z^pZu=Dr|i+ZdZjWTHG z@e{WC@pK0~2Sj@IOJB!6J&_t{V%E;XRg|^!a2?3ndAK%@Nx#pce%gMh<*iDeMDdyS z6HUz8dAOn`rHAvRzo<4(OY=P<>^$DK{?1H4#zwx^z)Ym?`2^gPn)VU+nBYVCV5liVZC_ALz96aPbwH zj?51`59b4YSmqYi2RjcJKPuCkqX0V((!6QsLI19_^KiG4stkYh(ayuApX7+{u=8;7 zQ!}r!JlJ_SJCbRcE*wVKdARg5GZ#{Zod*Ypb{?H5!_LDTQuLgk;dMnj4_-=U=dqau z!p?)&h}n726$Jowj) zMeSi$*m=0~7|YPH4(&Xcn06j~*-SeR{+Xbi$Nj7tb{?)5Q#1FmJlJ`hW97}vEC$lf z;}&b`{ES)iz|O;6aLY3ZriYz}lN&NUm>zZ>PTrU~i0y%$$5E)Ccl69MCV-vC@uq;C z$DK?8I}f%X+Vd(ua~D&<&Vxmmodb2oC09uzp{X4D2d zkDE+}od<7<6s#!NdGO@$LXzz4JYIpK3-3C#^We$t!Vdtn^I)y6{T$;DL8oIZpyh#rqUfa3u^t(5~ik26>gHh(&PHub1R zJ^sPPKSeS=^p<1qQAgcq)7=c2W8PyPbS4?QLR7O(s8ZSh1Ag&%Aeeh z>6#%oQpcN?Ke;1yXG7jf9iHc*>q6a?koi8V54+1BPd*R(F)*u$FR1%2Lc}+af^WI{ z1(64?g7!&hp1`i$%oO9HJ9d9g(V`&tYe@4da|e-@n_toR1`Jj)e?no*gh52kqYL?h zx^D?u*&ZF|Td}@*5a?or>mPajf2j1SGMAn&ru)7OWfh`%MIOY61K)(^bV#Q%lh=p2 z`XCVHp+9zieqju+EG#D<<7vX$FNn0r>&tsUiI1amGZyfMgmIMUDzvtJNt zxw(eX0+;(#^pKgNJd9@U>H_}y?|T~#O-REvHu_!-;VcCBBdG5s5Wb24SKH_pWIOOX z(B28n9oX@Gkma(tC=cVX`-=*!Og=I_g5An|8G#omuuNXLG@R`hWEsdZu?>0wlQhyX z($(kmi+!40!UdXY|%0t(KCrYvGJ8&~L)NHu5#@LA-#9w}Y0(3wb3-%`ZL)Ws@mHGUJ=& z0}MN8377vaO*GuNiE(jPW>pJX*2pGH&xWhzdQwsx=oStxm1@18hC7W-XZ-0+nUD;;&_P5zpb#yKz|K>Sm$lQeGIc2WQ z2;09Oc38OV$p>b)2({cp?TVSQJCsOXgd1aSi%`qmw{f?KSTayXyiwU6=d_`clg!{V zc@OMq%;r(0rTh0R@0IC&KnqoU81Ky^aBq_W8n^jD0;COeQOnV0h&`W*Hp*xsP=*_v z(}wznM|U)c$p>LiUMTm?jnf=D!Z-&A(#@uxo)cu zPIjOV&PXuSZS}!e2YTWeA%Q+#qu!Bd(q|@2OX?Oho!Im*nq6V(gaxn>TF`olkAMH- zA#F^UMt;I9m`XaC4O1hR3@O6WAnl^fOJVvG?ci*f9?sb?IU}XJH#sAv2irz`3lXqQ zir$c*SyM?T7%suc>1vZohVMVGsaiwDr)|_7FZMNmpMxe7+P#F zW0|(*R)`)I*ob`Etgg&lh1OPX?GEeTN84G!^TfJ3@BfrJRrQ?tb0-WL0Smc?b)~t4>MS+pcN0~`|q=i)VJ}f8Al<@z9 zt<;*;%gVFnO}u&hdu^mzo3xGes{dDQrf_q{Jl~h$l-b|H{Pu4eP^}%w+v0!Dipp7m zj@&rRj6gqGCRN6}3a@`s9(v~H^Y?_Ju4g2+j3<$kkJ z`AM{=>V$T2EIG#eu&3hF%3kJFBat=_`^T}T;_of;%|{6j6;2Y)7V>8&(;Y8dDO@W& zMR=z0JmG%}uM*xWyjS?J@F&9Og>MRfC;UK|z@QjEUU;C8-;S((!qvi)gvQTC`@bUj zdZF>Lq2Dg~7s9uNJ@|_f@nj?s#|ftk7YJ7fPZILG64QTKc!SV<&_n--E9Q|`B@QisqiS_LLvQkG5!m}^Mqd&eoc74@JZp%g}a0w3e%YIERUc0 zhy#UVh0}%PGBJLYkj_sje^Gdq@aw|4c=N;f8sQq@DZ(!bZxw!9__**zVH~f#SWZV_ zZ{cv^WZ^tvop7CSi||t6HsRgE$Am8k-xTf<7U26d>+dQYC_GVkw(wygJt8vw?}Ufs zJNXFV=Y)Yh)iTL}J=JE(X9~|1UM##u_)X#Wg})TONyNF`C8S3{+VOm#_&mIhq?|8o zM?`z~lN{Jr^^|^)^nrcVNa^X5pZR7gey(tdFtDpyrF0vm5A3T>mHu4mFA!cT{Z*2$ z6W%2KHzf!5RrgE(1L@7a3jKRp`j@2-?5qO&s<)}fIQ?Eo+gOfEp0I$3_;$iF>AMQ~ zxr*@vgcZUn#ZM9*F8y@j(bAip73!;#-t4W=mXj2JvT&==?5vRfQlE9LZk^X;#bhF5EiioJcI}z>bAv{PpSa>iI>CFxc z>5r0rw(uAt^ot}f5w0O3U$fBcw;-RT_;ZC9D*jU8mC|1${F?N43hx#^s`$r+KNUVN zd{y|m@J%A>-z9us`aQxpKEX0RUsxpEkBITfgfBBGAdg!c&_ z7w#197UIvm<;R~BL!36lVj-CZEPt5r5TQM{KtEOTG~pZ}-;gt(J-+}KOI{&dBitw? zeVFOD2+tPYEWAy4myle3rhh>Au<%LY)4~^oFAIMq{EhG(;U9$`W#2|-4eRYIBsGz8 zrErX}N=Tj!xmE^}D@6TKLh^(t*9yrI zqP$UP&vB5=&J9Rz5aX{Ak_ANBp6h_$rHsG*x!oa@mbCMSejaQ9)<{xnMZF~YX@r4gP`{!%6c*AWGIevC!Fq^9Z&`f(iX%mf*h{5co2-t(0JC%`q&R*6ZRkv zg5JFu&nss@TM);;q2cm2SAt9h9m~Vxd$znY5f1Vo=)HjQ8W_+P#GM8?T;2sJ?*iyp z9J}m2&A|4>)RAd2Y+D1yxaAj{n%) zaY#kQh!G>o%ZF499rBOb1D=IGU~6R$_|7-Kl>Ei61CJZH-Fvqq-8&ILcZ7_6^6yP}a|$KGYvI>0q-M?6UpoUEWC-U|+^`qt_u#d+2=V ze5dPAU1Ixo)OR6vrlaPeUEXo;+}Cgz8~;E2Ez5ux^SPu);TX(-BTdozfVHD`LxW|E z$acnhQ8Nq@tC1UPM2*FXiT)Ia$c)bOnJ$)?%$Q_+C#7WKG(c`GC|VtWUXDXWsXZPi zW51w^B<5I;&R;>|c7H_n0;#)|c2b;fUL?mPJ>!Z66 zNZkT${KmrXGCYXkn@Xs6t9$S%wt(qr^B2E1)fWSz>VVAz*qPBZibP zj5=uZm#9>YvGl8`AyHZ28jwuCf<%eRQYRLs|H7=5U7Tn(e~F<5KeU2q^S2P8{8>1V zeQ$lk#o84e@0A#t9$;GE3Fo4>@}9h8AKe~Ej7nLwMr#J!S|W{wHl ztC1*zHh;&UQHgI$bT)s9@3bF*vbna?jjZ`Tz*!=yN z;$z*mnb<3x=3qabe%!=G1mLj z_HS9I?LxzKF(60rGm z`HM6Au@|uUy9|F(Y4i6O+YOsP7hjRNi!yBfZ1HET?G&X9n?Dyn%51X|u=)G0{lv&0Rhs~dhpPK2y@?i64FIIa_%Zz1u*!;QlGc*6i_QU3n zgF~A?zSvK|=5MXlH$TJcDgm26UP@;3cPbUI`QtTWHh)W~fX&}?$YC~r!&xM3{%C9$ z?fGgvvmX_(`FqV${5Fp9=cV9IQVSX!I!Pw7aY!@``Qow7NKoqE2@NM`C@EFJ`Mkvv zF(0RGE)nu?hr-r&;w-d_8MhB!mj!5_?wE-Nb{jT-%YkJDm>h)(tnG9RQe^Dj4Vym- zxS3>V&Xa)6pBuqg<^*Pi&7WojYGlV@jD=$vpO=afSlj6u7WF$Ot@1liU{Py0*r`0h>RkfX&|xOaYrer-04hK}-RgKc}G09~H3qa|+n}O<}uW^XF=z z&EI4c!dBUs!sd@M8)Y(V{wVheWZL{Cu(s1IC^B!c3$Xd4z%f67eT2{PDxf{=bCklya_vrS5sGI zx*tP+n7ZfD2!DKs&m){cbP4vJG*a{@bXdQw=gi(2^(7&nCXN~ zEew#%4)Qx;sna*KFtF0}GYOlq!&WEO!oVd?NVYI=of8VP1`p^#u3^F2HM!zu<%+{v zG@Fsz6}L8A+}dz)NP_JI>@aU3a3q`+4Fa~|isa_Ii^|Y~)XR8=K{qtV5N0#EcQoNR z>`^$jvp%zY8Pza&5_Z%|I2pSc)oe!KBJ9u;*nAn)Fv#(sQ4PR0+|aTcPpNA~p2weR zE?fnSco!T=qK8mM^ZA5qmkz>j9L=FYR0Nd}tGstaY8FM$>*-0~%uFTwI9P;2=T{8i=aa!GlZ zMe*!nCJ*AFAXQQVYW_gK6W24DPFsMX}(08-IL(Eedia6~kpym}Y`#PfQyxOl3jHxrR;kHt|wLQAWJ zAvrF61gm!Y)nPyPZV3^spb=W(qS`(jfHDj>^{Ws~ap{w-g2pOP4m)VL^pCjkV+LIKkuk zEw;QxQ!x6iR&WVeuD~V`;&Uq!xCI!pwCsRM8kh#OUb;eS!(^9CA+z3Vb5d*(hpgQJ zRzz4?CjxZqgl_Q)x3mIQAy`(ublvJ&Z(nN_U@mQ}Z?5241abqiz)jTbLqPL?gExM#wCo+ARWME00uHyH#bvD|BelncNaRx#bmBEynl;r#xrg z5UdK3TLA=(+V=_$t7g)Fj*jr?CRA6adeq84DWYr-v! z!t?KzlyNuV=K582?y}VyIkr|+>vc@HvQPFp<^@QDo&U_LAo!`$YE6*x&=Vma2*(!{ zpAp*fM^{OYWhUs!t-HeLu8|KTSC1d-K`d{Q`vc zUQ70R%)?6~Md8)L8-(8weoy$U@Rvg4uA|;g7znnzkI=YUkf%zXEuSULm|yXdEY`e@XIA zA)KaKy-7S!v;L7n<19fo-`v1@>8}#rE__mGoFk;8XCRidN0`ENr(7nSE36fsD&)5; zrfU)2CcIzxBVisM_n8hpTMT;(=^Byx$-;TUI^jCu7U8ABZNj^Rj|iU??hw8wjAMdZ z{leZtdibIKFrj($f?O}Tkgtd#cNX>)juajyTq0}~o+i9Vc)##T;m?J;gdYmiNmpMt z;XvV7;dJ3b;cDS2!V82~3-1&@Bz#7=LpTK2Jo`6ZxJhW7b?9%9{0Ctq-=!}R?kC(| zSSjSIHI_S0I7xV<@HpX#!c&PjS6hT<6S04hh;qIn`AXrn($k$9)7>e&NBRdPKPu$P z=q%@F!q=sLL%3V`7a?vZ)*eh>L%T1ceZ`W?g!WPd`YOqjgnVnl{>%^>cL4GN$#ued zVWV)p@C(9Ih35#*7hWo~cho5N8p+oS$(v#QcE1GvSn^MVKNJ33_`2{7;k&~3g#ROq z@V z?+|`d_&uS0Iz)YZPtJOG2;UWw*+4x%ArXDvXMt@wu^pxFEF|%R>3RzX3Wo@BJHf|? z-28!P>4W(-Lh1PaFwze9UB&;497O&M{?wBYyI?GEIzAB`#PADFo;z-bVQ2e-&8{W9 z*$=iLZXy)8je1pzD8_`DHp zL0k@_66nIJ2F+*9CbH^p>Hp_xI7?OA!|??-G>9{A?fo1Z2zG zhA_*kz|L)932f$gp=x6s_dA3^x)<><%=>h(1?ldGg5hAJC$eFI01W2Kw-64u?}|`= zJ18C7`#AP!h=X`WoAQFXh@oNd?nSx^C_6zPl!u|RI#FJBdjl8NL0Ku+_O=|vThYE3 z_mPe--0)JN8cT!@S~D0N!{H+;D~4B8466v(hX`QHau6$rj06=C+efcSu-!GR6$f$P zo9~RT-g$BI$|;vj8A={v3_Qe0;k(7rDO2X|E?zKuck!mJSe0NR!gF^QLN1hC2ssHk zDLDx_203Q3KW-u<@(?2^FN*S>e|pBwWLedu@sl2&)cu`kQD%E|dH(X#_MHBQ@4o97 z{b;vWQM7&H@*@IGyC3b2Rm8WSzWf~1{AhQw0;?FDYW7w(ZZW?dPEaBLNb#a54-F=R z;2_#_tDig;_W^Ja7h-==8E#Oc#qULrioT^)oszF;ya;d6IFnK1e2x zL>)Ok;uvNgf&{SvC6gI`4~JMqsXdM)V`TS5N8=Fh(fLlq#AEm3n0Ev+_|f*b6!HcX zvEt~XR5w~UVeAKR6E{PbjOAS)jibsGe{kg8Soj>2DgHRfyQzeF$42RhPyy4Eo0xZP zij<{v5{JBPi4&m);UJyB2<6=z|CNd0CceW0Z;3K%^azG;?{Yoj$W2@b9k_{|p>4-- z^cIAYooqmgUqYg?h)BPKLvlz7!>EJY#AKyvjHUUpJy}`c8jv(zU9z&&iG}G6 z%v#ySiN;M#4lVel6+~_#A5`+|ap04K^$j<--6*kFa%7S#H>LR*K6!8|=pTQPCPzz* zrTIXWJVatLO}<`ojKsopZ#HeL#NzaSQyeF;H2o{)Jyc>@`el|}C9!Mz0~R%2BDjfo zngBO3c|`IVwu;8S$s_X_=BOV`aaxLEl-$G*C?91VgB(du!z4(~l1y&mJXA(QYU?t% ziSy933;g85WCf~q<9&PwhFLl-j*``RZV13lWJ_vNj@FkRL zK$U_3ZsHkiT5?_TB#7xtaY(Lj&oC>Bv6&l!ig0>(uP$DL>X#?)O8x%xrryRN3R$03MMyk5-ZxF$wqD>&o#4lv;${L$76V)9_OVS zqS`U4(=T!87fUXRBsn^nT9ylLqAr)rS`G%diR-Kju?$-Wxzx$Y%z9Rg^$46?nE5p- zNrIc`@)u|5gdhoS;%)d#OK##pOb>3Ni?7J=g#kFkog8;?SY|2f12@sdkIK-SauVD` zl8?9^!7kPhZlb%DRAt7qd~g$8`bil+h$O*Hbn#O&bP|vRH_;Z&1UK<1jw-l`F8$2R zEY=ThA_s@u#K##AZleA0#(D(2u9Dy;@=`KxBFT$Ma1(ir7&oyW72qb)VY+b>uVInk zCUTuC<0jJ3BnfUJ9jI$P0$vL4B;A7n37sSp**KgeE}asOeHjT#eLjS6f`*b(6`aq9 zED`f@+U61={~J&k7m>5jE@p8Pdj>KHTAMhG;3jTHXUhHy9VkqKn@CRpwxUE5+(dH= z07e>@Qb>ZE=teM>AtgHrZlY!cYGlXbF&1CO_kBf4a1-e?zzBaya1+gg0E*hitl%a( zIWKbxi*CzJq?-XXyYu!WxQRs=#!Pqg3Y@XB&FC`jJeixB_4G&wcOGMz#q1EciA+px zBAI4Ma1-qZCb)?kSv9zct`}1?$FV$c6C16(na27{f}8kx)Q;;dQ^@q-Cb|o5dFCG0 z2X3O18#3LHF9~j~7~A+(h09L0>B#WD0N-8(9LliEM#!6B$T?o5&)J zn@C3(NpKUL0^CHt?M#B3=oH{4exE78O>_!y6G^2_f}7|R;3jruJHSnJwUC>*5QVT+ zHm2YvQf8w}1~-xNxIiX1F$r#BJrtRPSUtFj6gcK|ERh5^(Ht!F1UHd)bqZD#xQUz5 zBVI_7_j@M^ZsKiFbm3hm32q`!ZkGqyMsO2ZtE>OJK_+k$>re~0iByS$$om#17}{kIVgt_3b_5|5DxoXe#us( zX-BeQJm!ukBYc2=IHLXGdC2O1)DV4o6X;RQm=W#y){Vbd%CYz8MBPZ!JqVdkhCL>; z!K2!rj&$TE@@;#MJf=Ii!^Mc_^H44Jo?V&l5Yv&@dMWl^tO&n&J)ehu3>?<(Sp2l@ zeHkM7{)BeLz0Zcg#lFZz?-Qi#do8rnp`r6p6*Yh*@Gy#j!`smdgcY?IX%=C(qG)5h z9($i4r4@BPG<@T(qQg(G?u^v zpRoPu?M4@>RlIG}K-r4o`UAVM_X$#3QN=i!Gzh}zaI7}51WNwmcGj^25!VyD6+vU< zdDstR3d?>TB>o7%*8fAClgN17SUD4-2hnLg#KDvxR8kmAVZdnA5Sf@Ppn#e_FZs}e%XwHt9Z;p z=P17a-k#jCK29{`34TDBCu?)gy%!1myx##G!exr$oOB!YxuCm|cr&{~Jpg;uYi@2~ zfY&C3jV%oD>VmMTg@MJ`;dPq8mp9Niv@qZMD-KN5TybrfsNn)Tp+0ax30*C?AXoN+T-lq#Wp4_Xy(!#Olwcd)3!&6G zgp(|IJb^<_%IlmguM`T7yB!UE-0#(p`E1W|jQ5Tv9FN@?u52KSi-XNNbiWn`&%*9| z#}m%QZr=7e7FRkw;VSIRF=S8+gB<5D!`09Jv50t$4T!WYtZmL}J)eJ6xQD!L``JGc zD1a|GZ3}Cgvs(ORL#+Kd$+?nYz z&Ne^$M*;<8wOASkvD{k~z;hj;GJ+Sri@p+stF`ccsU0@80U8{ zDlyJH*^iD&jM*eAF+y1?F~V6YF`g>}DlybK@^FYsoWLx@t4A_3Fslv*rx!%x3|Yh{ zAv_}PM>mrF+m9M>d{h1A8~ryHfv502?ab--GIIu=j-J{;4seAwdysHCZF`O6IEF*gs=hpGu9OseLTSs`NS5`7{8*`k@ zf0FZ@CC~=+O5^PY?Bal(OP<}n9d{eKR4ipjaEkXTUU$I4%hG&v#ON%u zl?>_XRvg@FkyIUJ(s5V=9;O)DqAiDb{ zS>4=NQ`nuCm@v9w8Sxn9l zHQMfa;M&%#T2*6QZG@cb>l_V!aZMB0*E!y_WBXQ%#2d^PM~81?P2dRQIYP5boTK4} z3Da5rX^!UGiYyd0FYd8pe*as& zbyv?CKMDS;`Nzkdf>u{mNI7zND-O0} zXFFnhm^ZyDcgAESf%%4cx1xGw4J&KS3J!Se`*PC#H=T3mDB@ZNVi_Hy$6PTmE_xn-xdB|_*Y>Oe`6tiH{k%` zAwu)ri1=eAFBfhQZWUfCyiWK{;lsim!aoQjc+O|N=6exXF4?>-L0%wvh4572y+XPc zVg4P$KMJFm;?#E#9w4j`t`zd4CezUi1@T7VJ;FzY&kA1`cE=A6rXMIAE1WJ|C|o7{ zg77@ySA|~_-Yc(w3*!UDXxVmjj~0}qmHJY~ouB?rE@XZ}C-z64IH;@rM(FVo#K(=fn5 z4~y6i!=@}V>>}bQi>Roe;)?9UBHOSDDk`F=G5QoWMvcj!iA&sLT+kTB-RBnE6SpL& zF)=QNT6hT& z$Lxo~%ZaG_I;Gz(`7YtT(my8oDIr&SW;~_adU)Na2CfA1s_8{Z!!$;ZmiaAUsWYrtlmh?5-AGD*cayHfJ}|Z&dm% z!uyr}u<%#HXNA8eqMXg$4SZ92o4XtP`LWVJ7k(+^ELQA?7Q%MIj>1kv*zHc z(U9r<7)o3%yjbYxWd5<_tA+U6j70I@=Fc~XR^FeF_}ekL>3LZ$eNI>CJFG zmj3Jc^ZWbX|Mjl?->Uh9`OM)r9%pWQA>h=@Z*L%W3lF+BpEeXS{uUy&(htgEj$I5Q zK8Ik~<$cT#K-`x>G;$HH`3o^N{N~dpLE+;}OJN}1j=`U19IHH+L!-#ZbzH?^6w2_{`3y(+liY`zxne>?aw}sjJa@A z>yLxo%2zapCJIf|X?8heMG-Xd>YsfcFS}qk{Qls#e>QZfc=D>)4zQW7 zLsOF1l)eXL`e(41{Anxdo#!U+u1c7ne*4KEr|Hg{>4Bf*mC035!x=Br7Co1|Ht|;z z;kQr5aPm4#+=Ehls!!h3{vM>!Z+{7N=)_&1ZO(Y?mx!g?Sm%^|j!YHl-l>m}kog!t z>6%uIqYnD*r~9bJc%}<>Gu@}eH6WFtb6mPlxf4q>KW5QB?VV_T`{}+VpPM22?Vp2K z@hQxMcH6$;gxVVxtI`AE3y8X3Wa6%AXCRWHhg5p7#CWCy#oZ*PGIY;P50O}!;gSpK z-6fV~xI#jDs6@;u%(8n(tjPS1Vy(munNG~Sr^H;OC9a6@+fVPCdWWs*gz=T$ub6T6 z`dMgkdUTqi`R$Ko@&UGE=C^+Z<*|}agX1l4biY7u+hzFeFF7NK{ddQ7y|tENo`4`m!!^z znBo0a`q&nXvm$!GrkDDPaCoX=yX*(3erEc%6z3|X-+ub`mMTEM{q!AvB+zd^y;f2x zWB+A$riZ}<=M;XARox}g%_*GzMGN|Qb57wY+=;tYwj%QZ#RsgH=(o=?pMGeEYtcOV z?H|KK^T-a*n^={3n5}*+v&qD68M>;cA5XXDs}ap9oPJ6bIluk%ue1ZsZ$G_W^$y9r zN>k6aXm4d}GxI1u*J2kFo!@@?MVT6&8N`GBlFE+G@Eu?J<>D7?f5&9Fd|djqmZay< zZ+|p1Zz!FNO!V77m3#C?GoHcp+rN|*y{W-Qzx`E6XVKR7!_m^3^oiEgh9cj=?DH&BM(KAm}^@Z0ALz%=~!UH&oI zD=5QnpPfU${kD|hw{I_=;IGZ|Dhub~b2?YFcXHm5L81$U5sg$@WEBokMmlW~yfOrMC~j11+$252}yLs_Zv z$Ma>&#Bvc$!O!JW~4ZnSj2-L_OPsC}yVgl?o!-UPLXK0EeEDgVX3N&>Gi^6Z; z$wk@qG!4J~ea&=fq?nNn$gF0!U7v>EKBu0|E~Y8??eom0DH5I1@Y{FCF`mWuoJbme z`^-$geO`#t@Y^@yH~jWFCwCft`))5rW!cMV`0bx$_QquSLM9Er{R^zAhi6IXO2cp8 zop3X=DdvaYzLV>-mCO&neJ3x=_F{YBw?6>&^NOAw&J6I|A888s?LWXA@Y`n#%y0jE z=78TmO_<+4C;v#pZ{I24x4(%y1;2f#fZzVJ%mKfBr-0vnh6?!YI|cmqhjZ+~Z{O8I zzx^dJ!d6+I!f&548)Y*5_9-9gW%})>;kSPZ6xjn=J^c15u+N`kAHZ*awaM_?=T)78 znS$Rw4-QWx$?Z0#;kW-V6zzG{NyBfS2e*9-_5}R)S*xr61z!k$`@cX|`0Z0A|9oDz zFu>@UpNR8B?-20h^XEb-;)ys(GQ}K&l@P4~@UI`nJ%HanEx>PoEjtH(`_(4GZ{J=! zrQ(xNWycLrI=}s5`0XDLD?9RQ!pXUZu$Pe>LL|uD1cR`fLP9b8_76ZV`0d-Q31Ai}b4m=3-W)>Z zQ0fMn?i$Fvv#q>{tsm6l8sy8NIpiKxk_ieYem)+Z4Vly6behI|yP57j$Tv{OyUL(8 z{R5Qcr=n2^ok)oZYMWEX>1{ZNcqe}63ih;oiy`xow-dij276jQF8RezNmX&&gY!8l z;13^ig8fVHE5Y}>EE0H!aT!7vpV+ku+O^Q!j=;Ymh%AK0qvQdlpZb#Y$bTH6I}@zb zTafrsN~J0hiC5q!7*pD_RQ2%^%@bptJePDpab3eH)A|o$5>Rc9yTRx--E_ z@uk%;D^=A8Ev$k*#-DC1c}NHHf;)53z9W(6aD>iW$!|U)a}m1uoL!HC_B3c#BESld zF)c*-(*q$mB=I>-y^aJvQG6ev^9vAeMC5veEc;vmYe#QE=D6){JK9N&H!mwN~(!iwl=oD_%o{GYNHP4(k^(w)lL6ZI{(ZiT)*M zAH@EKdV8Eo@zbExgoiO`qn`z(9GpFmojfNJ-4xiUMEiLH^s*PL&j%d>=7?Fxn1L6Z z0axbND%1NER2jRsXvcsjO01f^3Wzn7AoQWI2ZfsHs5f?BQ7HxN)OKD4PSowZ3QwWf zMqUN!7@k?N1=7VXVYWrirZ?{)@`p`tju8*GMTmUSD_mfoR<20zrb-Ou#+;3sui$K~ z#0UpxBgc`hjZeCG)OQYWg8V1##GNGal9q~B60#8j{8T)krntOIWKgen9~ULJ2?#ML{lQ1946y$izig2};p zms#Njjq2UX{vO17dmw-;L7?{u$P)1eMqIsz5)MZI-Ggup0;U3wHZa16D+uuhM%?}` zY*a7Q_#;Mub3S1uLSrt6yGEiC@d&ZVqQH*PJf|nHw^#z?4u8PHL=!#@w>Z9~>@lOuxZcnAY0QRjlS2{-sA!@LOfeVHFBe8@t7^M6P-M$+Ci99g-K9pAO7R$%S`S#}QsYXc$TKO3@SUn{?z9O1vd%FG zX$)VLqv+~9guoC=WizHYm2U<`*Nj653@G4J*|Nn>R^5 zjpMTEi+u%4XQej<TJQz7m7E1W{ zbA@c)S^JiauS~`c3ek3Oc*9&FJacTu6~Z{6!?5ED;g3yRA;j`rA;gixEjv(D;0i%4 zt`HvZ@s!?_9n`8#Iq5))KnIFtdXWz_0pywvu`^@f1GO&iU2ZI#L{aR6<$)!f;SzQ# zYH@f`YoGX$5?8szR{2sNE8#RHRQeL1A|VFe(Vt6=chnpDXrg^l?3QC8w<)Jg22$+T z%J=q`^C1&RL62K4vDj^~UPU_<^>QVDzueMh!Cq0UeVAs{#cF=aSw!Y+QS8P=K`&@y zv1dwq6}igOv8&N5&AXr#U0BItw&&kow0Z0X)XFNi!cUqtZ!gSF-*_>BMw7}nok`oK z&<@RrpLfeAHD}hmJ!|0oKV`aGu;G7@xP<*c%^0%tm%u0f8?%=d)byusy{4o8Y7P^2 zzGeVR{10)N@C3dDgqFIwbqiuzT((-0Jll)N=|h@l$8!7SV@3-1!%D|}kWZ$fP6>%#Yi zoF~-wM>tS8Qb?aDrgLgFqWNe8S4!rmTk7dHLR>3+MEHWRm`{*M&kDN;In@;P!-WS6 z&1V|=1(H_?&lNTZZxG%sd_wq&@JnF{o@rQ5JE8eNLmnjAe3~IImVBzvyv3kjFZs7Z zE+J2QrFbqPwioU!+*LSAc$)A6;m?HYgq)&~cKEf0_^yzvv{N2{rzj#P0V9qR)(Mvg zR|&r-yi$0Z@FC&z!Z(GV2oo6SwBK6TS=e7VLO4!1UARpPU7@YjfbzCh1JKrL0NPp&KwGN;Xlpe9ZLJ32T%5aX$BDvogg+AA zBwQzaTDU>@kuZ)g)z&}4$wIEiOT8_(4ZKtGi^5LDF5PpVhDr9^rvoKV5zZ9O6D}5> zAUsQWnb5dSsP`VqIF|PdZ4CyrVZHLbOoaSfp{>P$a_>w2NN8&^Kp(?3jro(pQX=$O z$?b(X>35ObTi8$fJtPkkj*{MUoDP$Iy!6I#LcO!4ub19)olchCxK7yLrd+4Xm42o0 zS|aj!uG1aT|3YY7C!{}48R2E=e=B@L`gbLNApC-easjUSEa$mRttq4Z#&Lq)xJ{6a z+XU>xbd(#Ya(gTPenR6mq1+LYJ-2BlWt5vMTp&C}`Bn-4OL)HU`$UxcfzY^5XvZ~5 z|GD&Qg?9^|Q2Kh|Z-lQ3HxOa>55o7Q|48^Z>0=l(%$F2mEnw>(tm$i5CF~~bNksk{ z;b7^93ipxz03!Nng7i~_vxW18i;2j0qU2MAXA@D+YNh{B`pbpa3U3ttoCrI2OI{~@ zl!)-6@C{)Cw<^?E2>S}h3-LE>_2V*ci0(2h6Y||I+sF62#NC8+d7?a0xUcYFAwSyb16bkry-{AEo{m?J3{)Sh4d9*e&con7fGgjIQ4YM zA)Y7vzR>P>pubP@L&EjK=Y*W8l;wXb{DY9Lm(-it;UJ-L%3=Qi$+iX-DWWLw{U>+c~06s($kHH`RM#iq$dy2 zbJFO;L-|ah-OoY(p=7%2F#Q(cokX;U4m;F8A*5pt<=+eGn?w08LVD#;E)miLhjLCx zCmhQCg+qv_hpsr(A1I{j4dr>l6NRS;$!lQx*+R}vPubQ0170QhTH&2STN4cFc7F-n zApHlzPlR^AiFABBHoMJ*t%Q|A@&H(GPhpL)RybUEu<$V91mP4ReTiu2RN+~|{}S4L zEaI0)#%-nbo4-CnwDM@aA#T$Q{dJVz(`cXH&xko;m9Xjc)t=LkZ-~-I2}cXZ2oDiX z5>6A&6wVRW3l|Idy^ZbQH#g!6;c3D%g=Y&d7G5U&H*g#Ae7l|7i0-uwmtotw;+JCy zr?+kV{|#?GUk@l5=eXp?d_0zZiz~7h(3hcVEy6Ll2k@Iu8wv$(%ObT(nAsWMywMQ8 zXTWfY&>q`$0D>=rXrvMjo=@T0>NlS@2?`%)+D5#%xQ2$b`Lywn!}YG~X|70CFYEL5 z&PUvrp^1yLkw}gaZ9Z)_z7?B%yn7=In}QlW2ICY&#Yop^o=`SS102O708zfMu#UAMMQ z(V*%J-ANclvHH-YYSt%KgV?K-TH}13e38!t!emrT! zNJyVNy)AHP`rD#KjN{Vh;z%t zg4E?W6{An1Bf)7rkSWmw-w?&3$!cVX9sw0NjkA~%Py7%m(VI{LoJRhC#2lwFmP*h| zIhIP!!%-He5otq^C0YtqqP%5y#`kAD*J>E!;x`&wGDdxMImb{e73abg(dGC7zi|Up zSWE)HMdzd5AUXl9O7>{R21TF45BQCY=lPBNyE1-bf7mqA8u*Pxj6Vj8;5SkqDQ43+ zJ46Zdi{D6cP^J@pz;9d)HAo8?-VKA_*a}*(S0d3*u%F;JvS^fdg5Wpu0fYR;bD%?q z(qX(g zH~Pxkau0?`EX{DODDWFqdFBm@LnW3w65SpWD;$xsR$_+?&u{P>UD=#pmk9jEIO@po zWgqyBjI-D2XbpZN#TeHm8pY%TY{wu+GkmuPej|4@)`|SaRfw_UZI{7s{4Q!Ue&Zxs z|1)w;2{e`b z#%m#F&chG*jf}G*qh&7j72)u3)Rmo&>d9~Hgp%Sns(|>7YMA(qPIBuKrSDAh93{W; zaaMJg#5}+8B&*r2O9XzSD_fEIJ$LZ|>m~9VPoenG4)>!M$#3MFVelK@HL)u5OLp#K znU;7qh<56h;qwjnjXh0t>k@(A=qk$d8{H1%`HimLA(`LP)Uz%6TG`r69mVHb3^Os$ zZ*-=HXZrA?Ig{FSM@h$TWbb6B(k}RoZigb-IqVGZ z8?Uroh-aT*I{1xFPG#4#V(=TCT$=qoDj~nol`qRaKpFhT*V1fgd3G7|gWu@VtFxT= zi~L5%KkS#C%=*A@bm@b#WM+`xNCFf2jeJ=_extjT)MmMM5BZHQ|M2Vw7{%l_y7W=m zi&!4~Mv|V$Z{!jrDYA zjNjOa3h)~{q6XtPzD*P0H%>yA#X9{ik>vv+`HeeU4&yiSRB#9BEp$NWAeqR<;UHaz zHYMVZB13tw2^tR2P*$q^@%+d#u^fkOArs11Kw(#ZjzT+`arxkRd9aspQEy;3g5P*E zcBbN4G|u>q4akwTYYF&`6mX8``HijzFJV)a5+b z;5SmBsWmJLexs9%vX8Lmz;8Sht-~oFDQ097GOO8+-^k@_va@Ll{6_wp(bR`53Vx$I zj`1uz2$XS!fZ*&Uq8}DWg@Ee^1{Kmg<_=Df*6yP`R#Qg@p(bYnJ z<2f+GR#~5d-$VMA{0>AMVWCg#GD)AV3-NFDPgE0~3iQXaL z$>-07D#R0Ul8K8s1_vWz4FC_(CN}`Tkru#je43pDe&Z+;WAQj&b>e>PFjU#`H&7-5 z-aC@tcs{J`_#X0~oa6heNDd(qF<*h;$&S=98<=Z~; znpK*GV*KfV5R4j8ge+G2Ddgdsz^*>gO8*g>Ke*CgASVmO_>;5J?Z>io1)dN1t@y79 zT}mKuvP`b{)Ya$g)*0Ha&~!!s=ZHN_3*09(BGKgrDEPXN_kUg1Kp2Y%-xu!89Nq4M zW;Uc*2-tQx20zgOQ84lzMM{tQu>&K~fzc8QJ%5RwjSh;ItiuuMWsJPR(KH1dbUR89 zaImzFb_l49aj%?#HqL-6Q=u}|KSPzVqru2~02X3BjFESAQ8gt9VB{TLG?YRO-?qml z7L`)KPHmBq*CrBcHn?OrTP6p&t0E;OLrY?K7LO~6$MZyUX!mJ_$B|aZJp|25s+dSu zsccYE;;fLsmCiIWS{wxXw4%Obr^r67_=&Q#RipfwaQ;E)f@Z7`=S>&n$8j?jUC4e5 zYqT{MYhnE~ta+q}x zUL@yNH|pw_Jn9x&@~C^hU}4Flo!yd0TOr|vSa*0mZKF!VqgP{2-e&YWHne(kPTrPC zcsxD1a1xPMN5pw)@mml?wPEOUvkOvW41odUx#bOv^gswAV+eRfhUj?0NQ78qxg&oa z>4azlBgZ%))-VSVR*b^Lmr=OVi*11Zk`G0wgpih7@k_7ynT#o za$$>7%K*-n*G5grlK|OMxYif8D76eBLS57r#mY5NS}v!|8;%52FobFg0xCG#x2QxD zI)s}L-%@tA$Q|1_Vs7JL_FE1ShDrq1;}lqr!U1}^JoRGn|(%1@wj3=%J5qAdXRA3>qoPMTT_deQ%(WuE?RM5+Aw zvFAa1gQ;liq0OHsV)eoEmn@uG*L$zYi)KyTfAZp)BbUr`OKlanO1!-PgVmxoXIbS} zh$?)xMYUX?X%O%mldPKZLcb}CYU0F$MjZT~w`SCWfxKu=pSSq9`Z}zj_CLOGl;eQ< z{}u3Ov9@4j;Aj=-LqNwX^BttekOCh&PdQ5(Zs+J zJ@=0kWs>`+@tvn-ygXGb^ut?Bx9(mS z!!31qi{S|s@4P}=;U=HTZ{s>rEzmCRCHuEAmx>plFqLZHKh2}s88+!ZJxFMN&ya^p z=5r_0=_x_vBQuc?(ZmJ9lZB@X&k_DWxJG!raINq`;WNS)g?|#hFEqbp)R#m@uwHw| z4z#s0fSiue+9#x|2Ib?0=3fk%9tPCgyL{l!C7WL{Wb-2iz9)SpAIBi~77i8eFB~tN zEj(Ume!eJovE-|TcL*O6J|}!b__44xhAr#uB{~C;V^WuZ3?3{~}EAa|gP5- z4Z>dvpA^0-d{_9Tke`%Up8h_>p2FRQ`wNd2&J~^{JXg3z_%q=l{1ga#lZEqzCkxLN zUN5{$_?Yk|VIt-1eBHIAR;m2=gjWi07d|5VweU~EO~Mjf3(po_AiP3&tMERd@upDzb;>xlwl);-&y>-Y zPn0i$*Ef{o!ZZ=($|c*{P)OfF`fk$uHKJ;yA0mCNaD?<@Bp)I?f`~AMh@Dy4T5)(HCx2NO|lsIV!I>QL#ABBJgYMASE1xLCMMcp?$`PM3U^(0Ekn zU(O%Oe*Ts4OJNu2sOQG^;BsS#WVc_!YGFU&ZbJKCL%C6sM+^CWn)VJ8+W#BmDUxRk z>6goV%Y@5?tAyVXUMsv&c$@G};X2`i!Y74K3x6$qMfke#E#XGt$HFg#{0_kO6$_gQ zJ&&iaWPTK9zM;Yq!hM8(4JqR#BOkvkGXG@ZOyL~i5}~;&A)oPI^!#Gae9s7f zLqtBi-+=xd>G^G*`8dxR(blpAwvo&a^VIJm3Eeh9S2ge z{PHQI%WT^Tzs!fBV;isK;f-nBx+35<=PUE^7&fh!&r*KF5VCDg{Ce9|`~;z&{&Oh% zwA~TsUu!J_x94_>M1F?>*cx#R1^aJeyY@%$We|=08n*89I~huw7>YCBC1scp)i)}X zb`;{_dT+%b<%%?{m-Vp-aUMdr-YhcYp!1tgI|hody(iF7sM_q|b}Mi16vTZQL?Z)X z?{G%6`Lq)uhwZ%rdn=%0`$`df`z}D-mq9dgE;5Yt2RoE@F5+Q(<9oXOqdh*udwUHk z!*i6|^Elb)TIn~|#lZh&qR)5tj$7uC&=o4&zJ9qv86;V~#GfOC+cypE^ZnOS`FK1Y zM8NLV18kd?YdrRSUBuAvh+K?(IVjse&vyXaU)pD#q3(*T-N}7Mh1xc6k7dI77NdR7 zDG$Nt^DiT(_wCbYeXOl=NUCeLnL~1SC#$d#hXf3g(v7$FT_5?NtSI=PED`;nEIwmo z>v!YFABwQ_y)%vv_85*>>vv<t9!yu%T1{caSxBGV;McDTt2=o6-k!`5)bU&KmU zrRBNdI}NWC59R51BgdbIVD@*rAF&qe*S{MazZ$`GyWEdh61pgKQPbTI+<15W-jRDZ z;)HO=CLZ+0NnT17!Ur>odf$6ciVT!Wvr343ghP>1aH$JBr0N;wO4wTb@H$ zH_L7%Qi-=IrIITFg>|#|x*^sF2R>F^KH4(GQ?M5!6)j%b_EM-4@iq7@;vZ-b8;Hb2 zk7gsFiE+KA#6pWFUqJpMtdF%A38{GEs@S`Tq#uPgaZTwxjPJ+zPg_y%R!HHUWeM|> zKa%)yx-%MW>o_H@OwNTGPN5mjCZD)A@wkatA8QS(zb?k2v493|YX4t|lRsiNn&=di zXwG=-62y{itP{#wB5y^qcZv?=84_fYHLVy&9b6wP*+(_TGtHRTr^GcNmEmn*vQN1a zOEaHZYI`RdeK0 zdu*4%AE`p+=LN~5Qx%A~{+`g1aa!k{TykQO>w>tkOOlh*cAwcPm0`n@Q#!J<#2=yI z;$A4kpc)eKeh|PP;cKZ>a!G0mFvDk)Wl9DtVVg#~(@lqQwBKxh!)HYrb1$ zD>6M<_5tf9@<&MZPd>E6@i-(=@JDzDo_u77D^0A*?8eT1Ec2L&-Hf}Fd_4W8iH<*# zd`cBL{z&py+5yKONv>DDLo#vJ`)rFpTiMzSSAR-A*W#}xI{rxVMVT6&Ifj{EQrXcN zK4&FgF22h4cTA=;_vp2jo6tD&M_y%{H3pzNx`R{s@mX zi?+5Oj+WMY@P~RF7rxVL&ZIWHYws3MPKu`3J6Yb8n0-HZmRj5tm+_eT_2sBQ^<8r+(QU zl))cy>4UO#7EXdca*vfCl3mC8z#nm!lG-dE`jX&}xctMjQ`qC+kGS+v+2Je?{)oK{ z1ApX5<_CYo0UzU!^ruPiM@Za=kw4Oo3h+lZSdMoR=zpFH?jSXw!J&g>A{&QHqfssqUx5te z!7b2mfQGVC<&WoemWky!YzvuCo(vybAB&^VPG+r-Rf6{EikZBGy9xftOkhP321jWU z>tk`|sjOYQ!5^_{sK6TF>u{_9q#lfCFJMvdM>HZ(BX=B*{rIimJyWwJ*2lVnrgq@q z0)K=8E*DwO+>iu+#K}e33n_y?LgzZ;k1)b%t<>zc>ys;@$-m$REc-UIf_=2wPzMk*hgOz#pLrWgmM=zlRuKg`dDM3$d=O<_#+h9=N-6@ z;E&jZUY)=n;Z>c2nF4==2Ztw;uYjyQsUY#TUV5#~YF8*2hYLKf;&gJH7(d$+_`JjpQC+vvQZ<7j{cw zAO-#iX)NH6RAGnGmjo@!AT~b&KZ&^eCBI~+;B^dzVD}=LiSQ)m7F3=EIT+e{0kUw| z<3TG@$xmFt9;UkwGM{29(`)FW1n-`j?e1^I`Tb_XQBOvpl-RWl#f?=lPXIozA zpx7dhpg00~0nckG7pU>rws7Ae6X=@slz>d75lOX>e#TlD?CV4za&`Np4!7TvKI##$%U z6V~x)+iMwm+#^rqW(35`h#Ym)7dG=c$4}S=oe!ySP9}6ifYhY_YB#3D-r>q6R>gFK_BA)r>mnF!_}&o*D?^aS>)9OQlXhS#v^fMi^K zu*L0{KmHQr6=9k0u49o({QlDp%-_t>7cVe+&YM54t|$FW#?P8Jb^&j zb>Gm5c+0l`_c|xLiMai$A^BA+`0mG6t=Mc~3LMVD!W0;-T9^W{{K6E7=NG2HP+3@4 zH*ayTnHURxVG8`?@gs-PT>z(FF29RUyESl1jJg3m~_ zgC;#Wk?9Pnw@I0mTaDJxlX!_a9ygyJE2gh;zy&WlH!@?nf%M?_Z~LPdE%K5VWSlu@-ENy z^B2upR#@u+v!f5gWbPB4TVS1e0#Ba?ulTtW|7Tcds(Xq3p!Ty}tjlAxr9=q7;oj-m0qPoSA`hyov-P3;eqN6MO7Cr3u0y~B2 z;=QDK)3C&GI7S_xpOC5Cd9Dd z1Qv1N@1iAh7UT659ZMrkj@Z(vGpE?j+u9h|KhAK!g+uGs3Ya%*{uJ{>oH21a+)yKK z-u}iWG0>LHT3qegI(g1S>#)g-;Ilfn&IztTXbvimOdNgSu>B?;5?P8J;4X33!dCnlJ*Hred`!^4Y%vCecb)YvuQ=?}X5qljf@K^uRG{@b zrsLu;XVxO98?9)P-xW8?Y})^s6XEwbZ@zZc`kB=nH*GSP)>vfw=lW&h$bCkSu#v#i zje9e3Q6rUG1H>BJ*fSc7FkrQTS@UqX&;gUVM}^fG(5U*lsk5ffs+;Cdp;_~$&)32L zel-HS+M(C$>R?2Rlh`RYI}#c{b#)jAv*y+>Sy(r*elboYzZ{C&N4MM7i#!|VV&J&G zez2k>Qp}#*BQ)-kJLHyr(j%! z8Zm_j{oq;0bFYz~*tU{^{`@(M za`=#S`PmXQ|lHjn!j*SZcxuY)ir~9F6h^D?&M?UFYKPPC9nSF zYbNl1Z&cFKjFgnfj23daa-PG97oFZo2_*}}_&*9&c~UgS4l9^l*3 ze=g(~Jl4;Tbws{)CLS!DC0rxCN%*Aj72%(Sn}mGXLp$^dARZ!|Dm+Dap3vsBMLxc~ zVt$*$7Rc48Df87X5i=?n@--#p{=yN$al$&`65%T0_k>ppZxcQwd|vpb@DpJI1KjEt zb`}m0?kzlAI7?W{*RW`3TVYq>K;hoPX~KoVmBRCdzZ5K+*3^a7UqEGl3Iq(C$#- zaN&N!BZbEaPa)!1trC8Rh&sb`Toc@OSZV}!g{r!?37CtWh3zA@ND7tg!Ud7`L2+BmGC~{L&7J7>xC~0UlzV0{G;##;U_}A@nw6;h3$p>hD*I& zXMsCQ_CBHmCD#gv3;DK~<@gz$$m!UKGlhI}Oqo*v5`QSXTzHLeYrdcBl>VUbSHfq7 zc0GsP*Cg9@9Wo~^V|^bA?K%&c9thOi^&W`J!$0&9tWo}Q=EFUWA1`0uXOI8W+vk2p zciM)-V_R4J;!?)u3dhq#pzrr|=8#m^=)ne|4=Q%f?zrGA*o)6)PDSR5wcU*QN zwFumnx5u>sf3iA;=T-Rl)@POl>O$@&VwRs?+MuB{;_>Ht@8HPAkH$?2;BaR z8{h^0U_)ja!*xQRZ#-^n`6}LTKHpj>828(A$QK@4e!OrDh1>UBXn%PR?)Ud0#4$$e zy}cCt6T3Z;IW#c0~gI88< zy84shh#&k}X-F=GoC?V)$nm@!3>^+B25a=%`wczzI!qcqd3ei>v1rTnv6+!wTD%$z zE}2xiei-7-Uk!HNZ&K0vQxT885~)0O(-j|mcanMMRh_!&Cm;Rkt%xCWz4P>kZ$<7s z2ZPrgmw50oI<53!oaJYr1J{H)lTrBW{TxZ~*&9fRCU(ami$;@4KMvEZiK~<2_o9U_8a->hi-`G!<`0YhCb@ zsBFupzC@g3xQO#f2C-tC3PnAdvEtY>R4=r6GKJJ6eEC*Dmx>o%6~nvqNO};eFS@4m z1t`{wk!=m(Okhf)qX6nlm0d59z5k)*)r@AyY-Fcj{#%WS+-Qs-_j=sDr+I zsXnSPp1B*%O!X;o4M=5i= zdle?CQUgYjG+BZdxN9H;lz0`ii#`i$4XDN_siRZXsMhuOgqDo+n678bCKkCa zh-Y46OD3nC8=RX9IyI#uJ4?QNG+azqYzEZ;*CGh;<(tB$rIw_QhnV3{>ev3H2yLVG-e`%ugQ~wU=gXH`uX=}MR?yV5En<8m>{Od+LGig3txR;j ze5n^@YIx=;Hsd9g9i6$7N9pC_d(hTsr!kpHOnt3oOLQrH`8H78P-+A%`0^dYJ$j=V z&tUrUk>{FvQ-h7Zd_2}H+S-0NT3R2*AL?;jc0f{dCbhX2Ki%S~NzoL0Cp(pP;mfDf zB}?K^3ch?xY!~9$$CwUZJ}0NL^I0)``J7yueVjW1Up`m9EPDfG`10L|e?9v0(aj|V zUp|*!o&7PYhtF*r=WEw5yC3U=FP}>vl>G%|`0~+NhjT&mUoQn;K6fdp%^pG-zI-nK z@GM`pq~Ocv(nn=iusnSE=-|V-pl@Y2!k5qGACsjMcM86I>>T>?-NbbG^4UW)eEE1@ zrQplQQ^|b!y3ine`FM_)FJFcV`0{bGTJz;wL6h+1t45cZFCYCQQ}E^E^9NWFi}fgTx1`MEqi8C=b~09H61BRQcn{2}PYf4%Z|X=F7)XXeYCL z`8s(S|0Cq*rQplQ?y8uD9Vkt~myc}ctX;d|%V*SQcyI;WJ^1pu9*k${|CE9+pGE{~ zU}u@a0>9PQaBXdnSvX8g1#0V?4|Mg%o`Gn3=wO7xNgvmydrF^yNF6Rl}Fh?Zv3< z!L$cozJ+Gb%>|u;FW(8M9loBfK7%ixk;v)G$E!L8GX-D171$%5NRr!aOu?7$Mkw0zs*{2* z9}jN(tJzoZOWbfu|vuiSHnC20~ZnG82AsXqn*N1@?1j7xLMy6}O|r zE#Ab7i17ZiD|4BNcOh}-WnvUfu&08fyR=0k%|sj>!G|qt1!sHigwU0_%mh96xoj{d z4PjrL&DczYU}+aC&il^;5UltOh;VpzU4a}{{I`&PgMe-4x9}6)2iHv==-4itm>FVk zN)Y-`*quTTQZb_YrAjEErtJ=u7;5<`oaNA%4Ld~g9dt#08ffMCwm4MMO|x`|kvM@)ppK6&FyELAmnJYhk<^0T>&!M~v+7+6ZxkuQW)CM1(;DFx2^CA~7BVH^$ z@kZ$Z+T>vgDeP;>#Bv1qY!a#v;9O5Q-oOaoq{AnXz%vh->TRmw zd8QvjINtQ|{$%8IC!`t}xzGuv4Q%HcC&U{VVWTnOb1Li?3YBevUGLP^v8;75LJ%2C zSb-3Wz&Df;R~dXmy?ta_1N~J9mWdHp6*3{-Xqy8mh#W*<9y)m*l+P4*SzTMalc!q7 zv_xcKq)%slk5fa(mm_)*0w!`M9Et$P*}!^>b+AO=b~cysv6ju8Q6PzEI(l+PuXVWyY`1bDwoO|Fa^(<$$T&h3LKFwJ8<6)sP!sw&_2NOmS_G&G z!x4~s*(ji0%Om3m+*hcV*8>+L$aR+c7RAfByc!9x#@(@a|BLBKM#2+>H`8Z`_}tTpN9G04Gw2G|w^wLqs0Tcd^{WX&XM z5coeDItYwz;UMrpG&u-777S3w0dB*|Q83B9@&}XgHOS*igxkjwtW}L*O*;C%hR_l3 zfK=QKVJp_or$UgPeu znSKlF*Feb-PKRjcDUsWy*o|1kW-AH)+AM>cP`j*fD1L>@qo%n;u3_^R*7f!t!P`Bt zofo;ePkCSRe}@mb`rr4v^S#vDeDlPfI(HGAWM@pB3Rh|j+07iYaX0L|XX$H=VL)d- z7t1?lLz{QZP81xop)R;$ha9t$7*Kd=%lS5-V$9TNlerV8g##Yulqkn7O*yt(s-pJOCezY~C-;vQzn;1QF8;riQ zHKXUr=*GO!wC&nQ*nQU#9pL3|d)3c=v8+Qpj&8PG6M7|LMX@f2H=04)b#)~=7l$Wy zT(3l?E4sc59p4x6AavHj*v1?@WJR%Onxm@na?s4s%dTNR&F^;?dceDU|DDg5L$OSu zOgeT2@`sxe{hytTn{MFF*WNi_H*y01n(p?Y?`w9ZnX9(<+cgjIyp#LbgU7)Y-MfPq zoMq*5U2p_ul6>Z;&R+uGars4?(w>2=eZIHgcQ4=M{}jJp^VMxi?D)Sl z?e^3;b(7~UsrSC&1z&HSYUXF3cXAH-l6%MfJS$)ebcIGF0#Ok>)4(wqLVo|`dxRJy z-@b{mH$MqI_r@_dM6$@!NkUAb`r+o+&p+?TMDbjjupvS`ltv!@&iCIDA;Mnya|?$` z?3>0Ug2q1Q=9~_9bP;75v3(r3;VW(=-F)czJC_1Cp%I10u|OtC5$G4_zi;nM*ry$nbLYNcsiv{&I z2^Vm-2rlA3eOS#P!vpxOVr^JSl|^4}L;BfL}inDAxc zJHju8`{3&#_wNYdg~H2)_XOu8%cW}Bp5~HU2|E&D2MbtRdT;6b z3OS7j%hw7=5Mk#4$p;CKB;t6SD#Yd6?Ba4^2(@9Eknbj0uf5L%R!QzA6#&v^!m1JAj0`hs1FBBRF4*E5cIfE7L zT_@xeTa@n*-XpwU_?Yl1;q$`Z2!AJhL->wxqwrJVUxhLLkE6b%kWLPiI|@4sy9?>} z!1O(Y^m?E?PDl?2%I4(@TqJp^kWLRwKS$Vf9&NfeF#Rs!eL^~rP*0Bs;>$w%J5c^W zNZ$s^DPePAD|FG2fU zvYL3O&^U#VACmmvLV8m$-|Iq7(MI__;U~h+g}D9rhuj_feOvja*GYcMq1~LYO6aeX zJtXt{4fFB)4Y5`@T-fw_dbsrCg-x%g_0lgEt`MFkJX3hK@I0a2_oMzbl7Axf^UvG< z;PJ>`|Gy?TNzXmoxk>0=+i+R6tt);xmT=nH)=%ic=i|6xoa2%k^WAJQ_Y+rqFQ6|& z)f)(_IY_nnw4so3n_%OPNoAdIjfL^nh+{a|*GjhQ00dtK(Z~|qGn{~Hp5J`hBq)5G zX&akkzi3FCPviIv*Sn@W>P9}+%lfz<#Q6xm45E?GFc5Q$X!B{aA&2eV+za-gqdnYW z=IyOS+?PQ#Qh^NN{_|-kAuVig9qes{j`rA%zI_)W?#mz=c@!Cb$Z9gyQTsrcj(qer^W*v@ExFYewhHREeczXfhmA8?aW z;3lPvo7DGna*v{~ytt|LCp~Ye0u!n4=S7V)MbMCsRLB#DCTa{NmI{VeeHH~nDFud7 zD*gf(N>7w}hEkjLH-C=du}e8QN-LT}ib85hmePt8Bv2rBiGio|%%)Z!wZG-ND;!hl zIg{Q5SINbg`;Sj=d@IaV+7Sn=^cn2&cd(yl+P)Tkz*Sn0^AlX9LjbY&anND|D~2Hh zcuO;JIKf+bof+bZrI2D%m@Cg!$}lCBSc6jFDjkJ73S6a8un`+fRj$=Q#y`bRfvYrv z*0>x;W3CdpP(iE|r-tV$J&IzUtJD*zn{$LhWvu9Ha+OxnRDrA1isDweO1uFNah0y%Q7UkiIQ4vptCVEd z7Pv}txJL!9(jKhnYjKrcf!z>Ssg8C-TqUEEgt$uUm>%LPkyIS!D)C`F%vHLUa)_(c zh518VrFGn`5LfABc7BMf^f~1aSLuD$AL1&FrTq|BsfhVQT%}tnhqy|7I0|!>Mzj79 zSLr3Dhqy{SuNrZcj-_*R3IvqPu;40a*B*ayM zPjw@%(n9Y4*0@T0!ES-8#L2wFT%~(hG{jXpo~FT7+7}1e<{f8b%Uq?lG!^11UCE*$ zuF^v8P>8Ga0FOb4tF)R`hqy{~4G(jb_%9viD)FU8n5%RP>kDy}x-)->tMoqW3v-qD z^xKH5G?x~_T%{A3Bg|FWk9CH*N=5t|4Re)VVvaCZiBp3&;wtrJJN`vnB~D@z<|-Y> zKKpuHC0=#%TqVw$y>+hAB-HY+;wp9J9u&ArMqmqbl`4=9u2KS3c03zRY{FH#4Gldx z_XPSllH(Inkh_2dB0KPtR*0)q3~ljQTjeUDWS*TCSE&+G4nZdDk$nv9gt$t( zBE3I?nV5kHU&s}>N+&|%r$up7>6zo>?i<0`#hvxr<^^!3pOM$U6Wyn&G`oKV!j_TKD-XaghboDeTiNqFzlXe);V?hz|n?xKXV5I{qU z+Qjp&G7y)%edMS0wLTLg>zoj-3L0z+5x`XlZO(!vNFAH!&RvDwWunh2)EbctdRU5M*Y5=1o&zfa&F%neL~=#-@FdCZ_$N z$(!Z@Vu0zBHZwg^iH%MBA|cbrhlaawF(N#ANi5A^9ZZ2C4HlEC@JBSChsTuxc_PZ= z4{tsX4>AMtL^o?H>JEI(Y_6|?ac`;dZm@)J8itT>fkqQ6LKMHYb-=G1S#fFH3Fd{C zh?FB#C@_Bx!EYQb480I|)cwXo%}|TLL*_RgCx(L%*x!EhyXbe%@0w31t_uk<+~RB} zKMfvVzi|GHg_GyzI9dFnT(@O|26P`kW8RY7Vw*J@ui|rcnlXC(Ae#|7KTY&_tOhV1 z6r=IT6k0;#{~!4Yp9{YIFSIpKV^zy&o4BdQY4CHe6Gv%A{O`p_E{Mt+5l#*1<^T64ioKu>>vtrn4| z9oSk6bEZr;2Y$a`hg+!N-@&t@+y2(MRsRgBYC%nZW2I~>wF*00Gk_(&WfZGzW?b0i zGQX}xlZ8xC~0Ulwi<{z3Sj@I&F}!Y_q*?Pcvx3(JJ`@!@{aVT0I1$hl=H?=GYd2W5J!5$VA} ztQXQ-gEA+SC0;1xT)dR&z(M3B@kHZu10R=6R}Jbn28L?@jj$NY4=J=~75MSa_Ilf^dq^?$?u!Bf$LJh^XE$CFC<0^<_eSE~1IIl^AUU* zL?a83A;*X|pVpLDb#{msRE)gd-b%!M8JbuPdlxgJ&8M9NIo!U>U~fHiY+osYw|61p zz6_#~?rrexdkgz}9@4`0=2W}=qdmT5@b=aqPJ2kUts0K~XZnK;4bvE!@~YPEv~9eq z>dI~7Rbip*ZQ@nUguU=sW!tzBqZV^NmmyycN_5XZh%Y{eRgSVhuEJ>lchUEy0j8&YSpHzKAC$<9IH6B`aEVlDzAw_LmpKWD?_A`)GgnwfBUT~F__(PiU;J>m)2k;o`H@%Gt{|^;>#+IK=*8a z#A89x3mD_EAax`mn&5&;v1sy7kfMCUg!Q2K;xQIaEI~?iCUYIww%%095=yDW3>?l_ zD#7u5@2C1$?XbpiG|&i{M*PA1P*YdLmZB z{8}4|OU7h4tpfN~tDufzc^|H{2)@-{O^ipP>uK=17>h=CX8fl1_aKdHLvj5LbR6#! zn=>B$F4DobV&{}?zz_LWoYlZBPE^y1anzx;ppwj za|OPYuRO!H>@Kk^^HYjLC6;I2#x8RL39YeVhKzam95Qmr1)HmT};fc4dqM?&wR>eyreU4 zbY>05&&$Ox*#3^me21y8wcI(uW*m}90KvDKj7(Uo#;*;R1NckZ{^afvk#+s@~zz3P5rVXSs(aT zE`3mzlWCA|#l>H^HWY9E$hUHrlG^Nnv=6?O%RfB(0){U6RxW*1_5_v(---*yaBZkp z*{fI^%Hg}xP0)u+|A4QA32NN2)-4cwJXRp zF}~Fq$dR>$<-oV1z!6b}RIUxh%A%d(Sw7~IZ>14|8oA?%IL%ko!mjbHo}sBD(Ms~I zDA3d@76sqR$wk=}G~JYMwE>ycY_~R47aU5r#u)fk{5PYi>sSTp&KzLndHQQ1js8rFv5%`#SI%kBas-|7Nu>fu>lnaQ_uC)~{J zTGj`?m6Ho=Lpga__FdKozSRKK&ntR ztPS-7cM5zfr@-1!moo?WR!)Jnq4;ixd@HBG+E5#r1AHr23#KG0UIHU*mGvpshN8?y znT)leC?D!&zc$n)BUW8;Z5M`d{#cur?Igu;5!!r8S^<-NFFd08Jv!6TL&glh2LOMQzE!n}v3Q(hY}}8Pp~{ZuLzxJ8kI1#5j)#>U ze~$bo=PtlrMsf&|Ah#L?V0Rr<L1jOHjx%C?N!=f4Vb_*?a+(7jXRzwD z1M}@>x~n1c#>m!&8q$n)b8@G{5IVCSOmGoFGJf{$JhKGe@tl%iDr`4@hd zbY-q?mqK$jq$?3*q6Z>Djz42NU*}ESgY>%)%)~p0yp7P6xy(cqduLCFt`$RBn!6Yr z-uXRmqAl{YMlch5BQgTP@vYd3qahuIpjM1wY5SSjxdzF$Ba4yFjx-ZjAhHIbD|1;Z z)IuQZe&M)J~)`lX(qp&s< zrTp4Z6ncz8Z*y%Z3TW{b`BrTrv1WrycC$rRIGWKixN&p0R1Yk1(aOP;9~j8ke^ju?=vyt>P05R8*TF-fyP8whp;93mAeq* zZ-Y7Q*EDvaB<)FyMU|SR@dUP7DQr27Q^Xokj2@4GDhbOGjCaK@Jj>|`XCsJF#VGre zyesbE%?Kz>;7%zQqxT>%7jd1%Lo4$@-s0wVMM>>|l?dS55I91}vg!fs=hTG3PJQA~ z;7F$?jCSgi#sCj@YQm9DeKK*9i=VI<=nm(>1oi@HRx5$rU5vZ)0NiUtF9ob|Q34Mw zGZU{xKn?=?1L}YsahFpQT%YhmpWAp0+ab!`BQt4K)u=8F6c~*36qpK>bU}k)HK)a;pf*c4rwVd4f&z*IsH8j>pLA3^+be2iJq~UT;O;=%{#&qod=!<9dy*GUM}D_y3RlM|C!WgF5?GXU+Gr ze(^;_ei0cNnU$6Kef8N*0-i}!ZAYr0n&ZV4s!zJGvuej3s>05y?Izo(wxeB8%`xX{ z{HeB8Jx+z4RohLrQEiV{K{byXSExSaOTC_@!p^GgCIQu`$Ju38dl2bjWd?X1O1K&~ zEWh{mh!*PbxN=1uSKY9Ow@`-%nX7Tt+IAGswrg8vcWnzyTTPvJgIlbFIpZ63}zMB@OPhYJAK~5aIaJFzAg_TF$EtA_;W5HaxoUmgH~4WY%6c=sFj}tT6wQ?E8IU0y6>;GwRuPWTAjmOP25hH ztDSVj`pQ69MhAy)b2eT*&bT|oE1Oa+ZIe>Xxz==hWz!hQtqpBWwO~E+>sywM zsm!-j)>VyTPGfVjwK7?onbeTX)gdF9OEpZwE97P4)0Ito)wjee7uPLM=ISe})W!aR`j6~5y8kj^6HYU$)H@{QkiPbw&s$l)=3EU z<0O6vj|I0vMo-J+>k#2-JK?c9Uge`=@C0aT&ic`=;1yZhh|o-(<74f#b0EK<6W{q@ zT3_FHt8iKS-urMZ9nXtieYW-ZmUJHBt1>Injy>rA{{m)};m5$m!A{AO%B>ZRF0aeG@+}+8^;(^F3HQ`*HCq5_IDl z?-ZlX*YV-nll5UwH$j{%@^>cltq&L9Zcsi}OpAGOg?O5Ho_L|SPP|6EUA$X-LbS26 zUX%PM5utBQ`#nSxGX(uPK=NT?t=KNE6wehe6>k+E68WZ%``3lPg29-$yEs;?5$B7w z;!^Qc@jP*@Xl%ft_YTRw5nm9E%{I!-Kf-~1@gj!(FflN|36g2K#QawAba9PH>mQcC zBz`U$TWaL@!=nk7)1rbjHq_uO$!CZrh6M6&kbIB$xcCQ=uT81vGjSYFAIdYtg<@K4 z6VDVc64#42iJQe|#5csPBL88L?erFhiDShXBL9|?_3FjtBJCQPzeb#h)12~w;^E?A zak+S*_zQ89c%S&L__-J@@%0W6E5%9TT=8hJNjypXvG{ZGI`JOy3Gr3&LotlEsb+k{ zq_|YPM!ZdYRvd!M8Mmtzr;9dL)*+H>#Rf4ewu&c+tHrCu8%P|(o5b5lw0*zItg^^D5C@5SlIREDsWIl$WaUp6=ZNz}6C(@h zVNUSTBf0lTjc!6kQWFdXI@9EtgK zsff$D(TmH4A+in2#R}0pOGW!bB@Y+P_Ym?AlWeRkAtxmtC-TJ#`@dW~K|DiTC7SOk z)Vo0PW#T&VN^zseXQ|YCt9Y-tS$s@^9R{9!0KU-^fNv_7DIn%j`e#S=tYA~1iWc(ZuBc(1rw+#)_L zz9haTz9qgV{zd#$EaLYc+A9`&h`q%D;vjLjxVJc7+)tb?&J<}zLH(zRtHg6e8zbuy z$>#eS^{F`~JDK>ifTHR5dX5RpbD)MM^5Ky#k~wkw}@CM>^5q?HNf zjUp{dDBmYOE+?T;N&bm4IYgwT5@p6`AZedM zE) z?DxgDh_yBT`|c9f4`YGLsrl^(bb5D48AE24LHJ}noO)&%BU-SG%N|%uu>Q4rd!x>_ z?cRetyWkWt%T#(%_?*J8^iLB=hJGe!BchT_F5CN%w&Fcr)%b@pp6R=W+7 z&d+dvL0?_F*s=sNY?@^ixXHMNinQ3WqaX*{eREI8ITrQUF5BaNki4g`+aT#YfC_OY zwAeD8buceUmtEy3;Iq&+HQlS^E&ih!h{xEb`s>Ez9XP-3-Z`M4x{ZK?_umV zNIECtWix$G?PAM#&lA))yvpA{>cc5j(6<(8ZiD8`axo^_1-!s$VHww7iniW}!Q1x- zyG8W?v#dkC3045@eEAj9!Tyax|H_fa{`FKn9*+mGVve=|X89fT1?RNgUotQ~oU$Q~ z6GtZB#q-$;+ogWCY3DqW&fY`)7_LlnvHG}8u-+8(?`c!R|FHG!L*)9=)jJhuYo7`G zRL9No*Zsj>$G&3e(nB)^usB8+WA*!Gnt#<`xI2a=tYdIwt8yy(VPC_&RzxoA_nq5hI435bvxa8$;YQ#HUb^>-wFG zH2t(@K;)oci|$N^nvn8#HG@$8J7iRN|4?#27_DJJ)hq4;SnAtXVmMlks@{GQOQOf(y5UWfSQdQ^3cN`Y%cFNv++Sj^=oYG)EU_ZW z{~_?ENbDcogQ})Vj5|GdLrW#DcTfqRtwkC1*PGqNJZHnGqmPa^r<5YC`lAV|KG^IS z&j0-X@hrD32#>Er{&$;Qyb7v%e%$S1o~-tw@NCB@;9P)TPY*d&`)bJI_2Fi(T|Je z{dj=A+bPlRRP}U^PmSpN zX?f2|RZa9bR(@XF&WZ9Fu=o2e8_fRBiw@%+{h{Y4=p6mDu412GEvrH$`e~hw{q|n( z#xt0HTGz7l4NW%sY4KQd)86KTv!(ZBelQ=$C4%c+cNXnRQ~Kdy@7SUej!tX@#{zy@ z{#&v}>pVr0r)}o&l zL+5$$)AGwl#WqofpO$&hH)KqVKQKM`Y5C<7Vl?~r;HPz$*?wY-e`?~vPs_iQOo?q} z|KO+P*RP2k#Sw>}mR~+AR>tk&r}co@eokx{w}+pWUw>X~1-FNv76*rZTKls;{Itvi zNcd^-yz=0u#Z$@nX=RuJKP{dk#!qVwGvKF1M-tgkDB3~GlTmJKP`U* z!!iB@_u!|c8G#nL<8Vd8X9e$rx_Oh`5l)1rXOMQndgHu!1za&e5YCq4LS z(TdQ-#bSbwuGQ^6Tf9??yg%cnDs~sE!cU9eW>m#LRq^1b}2*5ep;+dKdox) zyazumeofF%>t!Aj_-XljF)MaHy9Ph4dZTY%Y!>UoPb+1*dPM9}mcviWKj9i;b6E~Q zEnjYl@j-`&xLCg29vg@g%!8j+u{q}O(_&O~@5e>uyP6F6Y0>T5gP#_AVEnZB&c{Ps zEUGYmT2G?HgP)e40Y9zPtN}kQKLdVRd$9)mwEPVCY3<7l_-XkW@Y9;ke!)-6Z-stZ zGoXaMGGhuqEz0bak>RIBd3P(*Ps>|VRq57F+e(-(WX_pVqC&gr63(`n$Xg znAwd9wh8G-m?wIFmnWY+7wGaC2|tX_E}Vn^g@ow<{Hf>x6<>o-=zSRl2zoYTAZo!+ zYXEkrbdB4i9Afu>#789Tf7T;C$Yt~?ce3xNwF(NjxPvP&n(ma|OHpMCGWNzg_(j&7 z+ItD|9)tV<^Y}=}o!0XNq+{sGE?9@$0Ku&>dAw*$U=MfT4%FfQ6YA_46#l^-$ag;K zBi|*sKG7GcuUwxb_LD1<9HaWv0g2THjDhDAT$W7!x2c21k6I#to{d_?BsyS3}fJFpo#u{FH&q zjp12FKBHTE5(yLp#(R+My0Hi#pUT4XRrj zROf5u8yGmA5Ua3u_LRZt#l?&TYLR9vaEjrYQ1FrQhvqPX7g#t85Yw=RoHp0&Gxf_^ zhRI{FqE(_Et8tcLpO^Xh1P4KGFm^oX27_F)aOiPGz{1Y>3wI#61m!nTIphq+=hwE5 zPkpQKA9#Ea2>X%ArW)Jo(uVh0KZ+4>L+iM?|_0Q&p6N+TEQgGQFsx(KTMg!QMGwwdY&B z+2{+2bW=LFIGs%$?<8nn%0KbXwKg}^Vic3Du!G$8KmDigyJ%rPoy#vuH6~%(I;v_> zeRFQf=ta}#&OdN|Vyw?aHS^~!nwM)n4#unbMKh;Q_iZb`{6FypL+qC3e5M_LC$9h) zwT(-rXKBodw>`&>G^Vpws?R2Ki(!^npT$R_tzdS^Jz)nhojDk2 z8usNKR^E$~O-)H0*~M9;5LzRhL|1a@JWq`!W_O*=kw$P_8)}`F`8k-YLYWB#g07+` z{{D8Z%^*ikBAaQhH5QYL6EshDw)Y45m^1Ae{Lz=`i(;H4l6lxLH>DG1ApBmTPv}9x z%yv0;l>5c~(>PaS?&UI^f;?Eqr+EmoP02=7@w;e^HnZvWRvbgtq7|>TzQy6I%iuzg zfm+|L)0k#MJI?sV4D5r^gTPD=Jk{+OD}Ux>)61PiL&CS{_xIY&2h*{-BuWt{D}|Esm63N+tz~lo6WbRQ!nQVQt(^A8IX-c*)ufx$Xmop51It?WWKPZbijg~lp*_2LWm@`c+ZMk%!r4=Jv zj}wqR_4m==Z8M@7jA#?45e6UQ%*lf3yCl(=WTT39(qT=TtYfPS=QL**JBh{VR$Nlj z)QL=;CChN_fIT}(8=Gq}K?0o!*lXL`nRFTxpe@^$$4)a~3=SIil3iPFM&6vF(q0I~ zv9spd{`W|taom`snVd5ZUKpQVH9l@)aha%HRn=9aJO`9PK(jiW}aeLecO3|hIO2^sm5krH*;eqaAF6qyvFIkOcfpv2N(N&>Y z8KEFLgFZV>h zI0hWwPWH?GX%#SFMh5EePU`E}F!L8ZZOnM6NdAT(r;4-0xgy{9vbn#ow$BHvV zW21w5X~}Kknc_v_dhsT4v-phohPYLXV1k?W#bM$&ai(~Lm=VkP$Q1qQBkm!N7iWrf zVoqEs{zSY}d{lf<{I<5s*%H5hr-?`gjS{r8m&kgJCFV={&#UsVz#nVU}t20IZ9TRP1&r|uoO8&Wch4QbJyh*%8 z`S(eFP<%xBzm@#Fh|7j)7t_>`-&O1fACHg~qIrS=d5Yv3k+0ZU?+}p>b|^0r(_%)< ziF|0ndVG{co+hpq`C6L!7m4QCEaYEE-XLBln(HFU`DB&bJt;mXz9_yfzA1hnZWaGq zEaLSIdiYe9>?iV@ma@67f_y?td7gNbm=Nnlz8++~r6T`8jq=IjN|FD_#r%H}FA*;j z*Nc4R%zD?0H;Q+Q=9L-BaTnwS1`@v#)b7(nUw#*^OVaptacm9cVK-P=d@jH8DF~LGGfkKmVMS2 zcKT34yCxiV^E{IMIvA_n21(~KJj;GNkYSU@Zd31UT;rayg@H1j|G{=Y+710fJ+{mC zxF2LQ*1+b@k=-39jy${AvL(m}>U(;Se~qF(?zYvp5^1{)lFka~nAc3Z*m}1jgK4`Q(WgT<^SB>eZp0ew-)Dn5#t&U6^lvlLxCLqf%(4pl yf^*fjMFxh!xdZj$$lMkAv{hrfjFGn_#`N!Q218^Zx;s@nSgu literal 0 HcmV?d00001 diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/apollo3.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/apollo3.h new file mode 100644 index 0000000000..a6aab007b1 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/apollo3.h @@ -0,0 +1,23505 @@ +/* + * Copyright (c) 2019, Ambiq Micro + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * Third party software included in this distribution is subject to the + * additional license terms as defined in the /docs/licenses directory. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file apollo3.h + * @brief CMSIS HeaderFile + * @version 1.0 + * @date 13. January 2020 + * @note Generated by SVDConv V3.3.27 on Monday, 13.01.2020 14:44:43 + * from File './apollo3.svd', + * last modified on Monday, 13.01.2020 20:44:43 + */ +// SPDX-License-Identifier: BSD-3-Clause + + +/** @addtogroup Ambiq Micro + * @{ + */ + + +/** @addtogroup apollo3 + * @{ + */ + + +#ifndef APOLLO3_H +#define APOLLO3_H + +#ifdef OVERFLOW +#define OVERFLOW_RESTORE OVERFLOW +#undef OVERFLOW +#endif // OVERFLOW + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== apollo3 Specific Interrupt Numbers =========================================== */ + BROWNOUT_IRQn = 0, /*!< 0 BROWNOUT */ + WDT_IRQn = 1, /*!< 1 WDT */ + RTC_IRQn = 2, /*!< 2 RTC */ + VCOMP_IRQn = 3, /*!< 3 VCOMP */ + IOSLAVE_IRQn = 4, /*!< 4 IOSLAVE */ + IOSLAVEACC_IRQn = 5, /*!< 5 IOSLAVEACC */ + IOMSTR0_IRQn = 6, /*!< 6 IOMSTR0 */ + IOMSTR1_IRQn = 7, /*!< 7 IOMSTR1 */ + IOMSTR2_IRQn = 8, /*!< 8 IOMSTR2 */ + IOMSTR3_IRQn = 9, /*!< 9 IOMSTR3 */ + IOMSTR4_IRQn = 10, /*!< 10 IOMSTR4 */ + IOMSTR5_IRQn = 11, /*!< 11 IOMSTR5 */ + BLE_IRQn = 12, /*!< 12 BLE */ + GPIO_IRQn = 13, /*!< 13 GPIO */ + CTIMER_IRQn = 14, /*!< 14 CTIMER */ + UART0_IRQn = 15, /*!< 15 UART0 */ + UART1_IRQn = 16, /*!< 16 UART1 */ + SCARD_IRQn = 17, /*!< 17 SCARD */ + ADC_IRQn = 18, /*!< 18 ADC */ + PDM_IRQn = 19, /*!< 19 PDM */ + MSPI0_IRQn = 20, /*!< 20 MSPI0 */ + STIMER_IRQn = 22, /*!< 22 STIMER */ + STIMER_CMPR0_IRQn = 23, /*!< 23 STIMER_CMPR0 */ + STIMER_CMPR1_IRQn = 24, /*!< 24 STIMER_CMPR1 */ + STIMER_CMPR2_IRQn = 25, /*!< 25 STIMER_CMPR2 */ + STIMER_CMPR3_IRQn = 26, /*!< 26 STIMER_CMPR3 */ + STIMER_CMPR4_IRQn = 27, /*!< 27 STIMER_CMPR4 */ + STIMER_CMPR5_IRQn = 28, /*!< 28 STIMER_CMPR5 */ + STIMER_CMPR6_IRQn = 29, /*!< 29 STIMER_CMPR6 */ + STIMER_CMPR7_IRQn = 30, /*!< 30 STIMER_CMPR7 */ + CLKGEN_IRQn = 31 /*!< 31 CLKGEN */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0100U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_apollo3.h" /*!< apollo3 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog Digital Converter Control (ADC) + */ + +typedef struct { /*!< (@ 0x50010000) ADC Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t ADCEN : 1; /*!< [0..0] This bit enables the ADC module. While the ADC is enabled, + the ADCCFG and SLOT Configuration regsiter settings must + remain stable and unchanged. All configuration register + settings, slot configuration settings and window comparison + settings should be written prior to setting the ADCEN bit + to '1'. */ + uint32_t : 1; + __IOM uint32_t RPTEN : 1; /*!< [2..2] This bit enables Repeating Scan Mode. */ + __IOM uint32_t LPMODE : 1; /*!< [3..3] Select power mode to enter between active scans. */ + __IOM uint32_t CKMODE : 1; /*!< [4..4] Clock mode register */ + uint32_t : 3; + __IOM uint32_t REFSEL : 2; /*!< [9..8] Select the ADC reference voltage. */ + uint32_t : 2; + __IOM uint32_t DFIFORDEN : 1; /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable + FIFO pop upon reading the FIFOPR register. */ + uint32_t : 3; + __IOM uint32_t TRIGSEL : 3; /*!< [18..16] Select the ADC trigger source. */ + __IOM uint32_t TRIGPOL : 1; /*!< [19..19] This bit selects the ADC trigger polarity for external + off chip triggers. */ + uint32_t : 4; + __IOM uint32_t CLKSEL : 2; /*!< [25..24] Select the source and frequency for the ADC clock. + All values not enumerated below are undefined. */ + } CFG_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) ADC Power Status */ + + struct { + __IOM uint32_t PWDSTAT : 1; /*!< [0..0] Indicates the power-status of the ADC. */ + } STAT_b; + } ; + + union { + __IOM uint32_t SWT; /*!< (@ 0x00000008) Software trigger */ + + struct { + __IOM uint32_t SWT : 8; /*!< [7..0] Writing 0x37 to this register generates a software trigger. */ + } SWT_b; + } ; + + union { + __IOM uint32_t SL0CFG; /*!< (@ 0x0000000C) Slot 0 Configuration Register */ + + struct { + __IOM uint32_t SLEN0 : 1; /*!< [0..0] This bit enables slot 0 for ADC conversions. */ + __IOM uint32_t WCEN0 : 1; /*!< [1..1] This bit enables the window compare function for slot + 0. */ + uint32_t : 6; + __IOM uint32_t CHSEL0 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE0 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL0 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL0CFG_b; + } ; + + union { + __IOM uint32_t SL1CFG; /*!< (@ 0x00000010) Slot 1 Configuration Register */ + + struct { + __IOM uint32_t SLEN1 : 1; /*!< [0..0] This bit enables slot 1 for ADC conversions. */ + __IOM uint32_t WCEN1 : 1; /*!< [1..1] This bit enables the window compare function for slot + 1. */ + uint32_t : 6; + __IOM uint32_t CHSEL1 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE1 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL1 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL1CFG_b; + } ; + + union { + __IOM uint32_t SL2CFG; /*!< (@ 0x00000014) Slot 2 Configuration Register */ + + struct { + __IOM uint32_t SLEN2 : 1; /*!< [0..0] This bit enables slot 2 for ADC conversions. */ + __IOM uint32_t WCEN2 : 1; /*!< [1..1] This bit enables the window compare function for slot + 2. */ + uint32_t : 6; + __IOM uint32_t CHSEL2 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE2 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL2 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL2CFG_b; + } ; + + union { + __IOM uint32_t SL3CFG; /*!< (@ 0x00000018) Slot 3 Configuration Register */ + + struct { + __IOM uint32_t SLEN3 : 1; /*!< [0..0] This bit enables slot 3 for ADC conversions. */ + __IOM uint32_t WCEN3 : 1; /*!< [1..1] This bit enables the window compare function for slot + 3. */ + uint32_t : 6; + __IOM uint32_t CHSEL3 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE3 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL3 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL3CFG_b; + } ; + + union { + __IOM uint32_t SL4CFG; /*!< (@ 0x0000001C) Slot 4 Configuration Register */ + + struct { + __IOM uint32_t SLEN4 : 1; /*!< [0..0] This bit enables slot 4 for ADC conversions. */ + __IOM uint32_t WCEN4 : 1; /*!< [1..1] This bit enables the window compare function for slot + 4. */ + uint32_t : 6; + __IOM uint32_t CHSEL4 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE4 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL4 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL4CFG_b; + } ; + + union { + __IOM uint32_t SL5CFG; /*!< (@ 0x00000020) Slot 5 Configuration Register */ + + struct { + __IOM uint32_t SLEN5 : 1; /*!< [0..0] This bit enables slot 5 for ADC conversions. */ + __IOM uint32_t WCEN5 : 1; /*!< [1..1] This bit enables the window compare function for slot + 5. */ + uint32_t : 6; + __IOM uint32_t CHSEL5 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE5 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL5 : 3; /*!< [26..24] Select number of measurements to average in the accumulate + divide module for this slot. */ + } SL5CFG_b; + } ; + + union { + __IOM uint32_t SL6CFG; /*!< (@ 0x00000024) Slot 6 Configuration Register */ + + struct { + __IOM uint32_t SLEN6 : 1; /*!< [0..0] This bit enables slot 6 for ADC conversions. */ + __IOM uint32_t WCEN6 : 1; /*!< [1..1] This bit enables the window compare function for slot + 6. */ + uint32_t : 6; + __IOM uint32_t CHSEL6 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE6 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL6 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL6CFG_b; + } ; + + union { + __IOM uint32_t SL7CFG; /*!< (@ 0x00000028) Slot 7 Configuration Register */ + + struct { + __IOM uint32_t SLEN7 : 1; /*!< [0..0] This bit enables slot 7 for ADC conversions. */ + __IOM uint32_t WCEN7 : 1; /*!< [1..1] This bit enables the window compare function for slot + 7. */ + uint32_t : 6; + __IOM uint32_t CHSEL7 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ + uint32_t : 4; + __IOM uint32_t PRMODE7 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ + uint32_t : 6; + __IOM uint32_t ADSEL7 : 3; /*!< [26..24] Select the number of measurements to average in the + accumulate divide module for this slot. */ + } SL7CFG_b; + } ; + + union { + __IOM uint32_t WULIM; /*!< (@ 0x0000002C) Window Comparator Upper Limits Register */ + + struct { + __IOM uint32_t ULIM : 20; /*!< [19..0] Sets the upper limit for the window comparator. */ + } WULIM_b; + } ; + + union { + __IOM uint32_t WLLIM; /*!< (@ 0x00000030) Window Comparator Lower Limits Register */ + + struct { + __IOM uint32_t LLIM : 20; /*!< [19..0] Sets the lower limit for the window comparator. */ + } WLLIM_b; + } ; + + union { + __IOM uint32_t SCWLIM; /*!< (@ 0x00000034) Scale Window Comparator Limits */ + + struct { + __IOM uint32_t SCWLIMEN : 1; /*!< [0..0] Scale the window limits compare values per precision + mode. When set to 0x0 (default), the values in the 20-bit + limits registers will compare directly with the FIFO values + regardless of the precision mode the slot is configured + to. When set to 0x1, the compare values will be divided + by the difference in precision bits while performing the + window limit comparisons. */ + } SCWLIM_b; + } ; + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000038) FIFO Data and Valid Count Register */ + + struct { + __IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */ + __IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */ + __IOM uint32_t SLOTNUM : 3; /*!< [30..28] Slot number associated with this FIFO data. */ + __IOM uint32_t RSVD : 1; /*!< [31..31] RESERVED. */ + } FIFO_b; + } ; + + union { + __IOM uint32_t FIFOPR; /*!< (@ 0x0000003C) FIFO Data and Valid Count Register */ + + struct { + __IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */ + __IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */ + __IOM uint32_t SLOTNUMPR : 3; /*!< [30..28] Slot number associated with this FIFO data. */ + __IOM uint32_t RSVDPR : 1; /*!< [31..31] RESERVED. */ + } FIFOPR_b; + } ; + __IM uint32_t RESERVED[112]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) ADC Interrupt registers: Enable */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) ADC Interrupt registers: Status */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) ADC Interrupt registers: Clear */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) ADC Interrupt registers: Set */ + + struct { + __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ + __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ + __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ + __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ + __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ + __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ + } INTSET_b; + } ; + __IM uint32_t RESERVED1[12]; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DFIFO75 : 1; /*!< [0..0] Trigger DMA upon FIFO 75 percent Full */ + __IOM uint32_t DFIFOFULL : 1; /*!< [1..1] Trigger DMA upon FIFO 100 percent Full */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ + + struct { + __IOM uint32_t D75STAT : 1; /*!< [0..0] Triggered DMA from FIFO 75 percent Full */ + __IOM uint32_t DFULLSTAT : 1; /*!< [1..1] Triggered DMA from FIFO 100 percent Full */ + } DMATRIGSTAT_b; + } ; + __IM uint32_t RESERVED2[14]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */ + uint32_t : 1; + __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ + uint32_t : 5; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DMADYNPRI : 1; /*!< [9..9] Enables dynamic priority based on FIFO fullness. When + FIFO is full, priority is automatically set to HIGH. Otherwise, + DMAPRI is used. */ + uint32_t : 6; + __IOM uint32_t DMAHONSTAT : 1; /*!< [16..16] Halt New ADC conversions until DMA Status DMAERR and + DMACPL Cleared. */ + __IOM uint32_t DMAMSK : 1; /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO + contents to memory */ + __IOM uint32_t DPWROFF : 1; /*!< [18..18] Power Off the ADC System upon DMACPL. */ + } DMACFG_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ + + struct { + uint32_t : 2; + __IOM uint32_t TOTCOUNT : 16; /*!< [17..2] Total Transfer Count */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ + + struct { + __IOM uint32_t LTARGADDR : 19; /*!< [18..0] DMA Target Address */ + __IOM uint32_t UTARGADDR : 13; /*!< [31..19] SRAM Target */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */ + } DMASTAT_b; + } ; +} ADC_Type; /*!< Size = 660 (0x294) */ + + + +/* =========================================================================================================================== */ +/* ================ APBDMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief APB DMA Register Interfaces (APBDMA) + */ + +typedef struct { /*!< (@ 0x40011000) APBDMA Structure */ + + union { + __IOM uint32_t BBVALUE; /*!< (@ 0x00000000) Control Register */ + + struct { + __IOM uint32_t DATAOUT : 8; /*!< [7..0] Data Output Values */ + uint32_t : 8; + __IOM uint32_t PIN : 8; /*!< [23..16] PIO values */ + } BBVALUE_b; + } ; + + union { + __IOM uint32_t BBSETCLEAR; /*!< (@ 0x00000004) Set/Clear Register */ + + struct { + __IOM uint32_t SET : 8; /*!< [7..0] Write 1 to Set PIO value (set hier priority than clear + if both bit set) */ + uint32_t : 8; + __IOM uint32_t CLEAR : 8; /*!< [23..16] Write 1 to Clear PIO value */ + } BBSETCLEAR_b; + } ; + + union { + __IOM uint32_t BBINPUT; /*!< (@ 0x00000008) PIO Input Values */ + + struct { + __IOM uint32_t DATAIN : 8; /*!< [7..0] PIO values */ + } BBINPUT_b; + } ; + __IM uint32_t RESERVED[5]; + + union { + __IOM uint32_t DEBUGDATA; /*!< (@ 0x00000020) PIO Input Values */ + + struct { + __IOM uint32_t DEBUGDATA : 32; /*!< [31..0] Debug Data */ + } DEBUGDATA_b; + } ; + __IM uint32_t RESERVED1[7]; + + union { + __IOM uint32_t DEBUG; /*!< (@ 0x00000040) PIO Input Values */ + + struct { + __IOM uint32_t DEBUGEN : 4; /*!< [3..0] Debug Enable */ + } DEBUG_b; + } ; +} APBDMA_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ BLEIF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief BLE Interface (BLEIF) + */ + +typedef struct { /*!< (@ 0x5000C000) BLEIF Structure */ + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */ + + struct { + __IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return + valid information. */ + } FIFO_b; + } ; + __IM uint32_t RESERVED[63]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) FIFO size and remaining slots open values */ + + struct { + __IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO + 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in + FIFO 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1 + (written by interface, read by MCU) */ + __IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently + in FIFO 1 (written by interface, read by MCU) */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable + the read FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the read fifo contains FIFORTHR valid bytes + of data, as indicated by the FIFO1SIZ field. This is intended + to signal when a data transfer of FIFORTHR bytes can be + done from the IOM module to the host via the read fifo + to support large IOM read operations. */ + uint32_t : 2; + __IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable + the write FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the write fifo contains FIFOWTHR free bytes, + as indicated by the FIFO0REM field. This is intended to + signal when a transfer of FIFOWTHR bytes can be done from + the host to the IOM write fifo to support large IOM write + operations. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) FIFO POP register */ + + struct { + __IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by + the current read pointer on reads. If the POPWR control + bit in the FIFOCTRL register is reset (0), the fifo read + pointer will be advanced by one word as a result of the + read.If the POPWR bit is set (1), the fifo read pointer + will only be advanced after a write operation to this register. + The write data is ignored for this register.If less than + a even word multiple is available, and the command is completed, + the module will return the word containing */ + } FIFOPOP_b; + } ; + + union { + __IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) FIFO PUSH register */ + + struct { + __IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode + and will cause a push event to occur to the next open slot + within the FIFORAM. Writing to this register will cause + the write point to increment by 1 word(4 bytes). */ + } FIFOPUSH_b; + } ; + + union { + __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) FIFO Control Register */ + + struct { + __IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the + fifo read operations. A value of '1' will prevent a pop + event on a read operation, and will require a write to + the FIFOPOP register to create a pop event.A value of '0' + in this register will allow a pop event to occur on the + read of the FIFOPOP register, and may cause inadvertant + fifo pops when used in a debugging mode. */ + __IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset + fifo, and then write to 1 to remove the reset. */ + } FIFOCTRL_b; + } ; + + union { + __IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) FIFO Pointers */ + + struct { + __IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the + outgoing FIFO (FIFO0), which is used during write operations + to external devices. */ + uint32_t : 4; + __IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming + FIFO (FIFO1), which is used to store read data returned + from external devices during a read operation. */ + } FIFOLOC_b; + } ; + __IM uint32_t RESERVED1[58]; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x00000200) I/O Clock Configuration */ + + struct { + __IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior + to executing any IO operations. */ + uint32_t : 7; + __IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */ + __IOM uint32_t CLK32KEN : 1; /*!< [11..11] Enable for the 32Khz clock to the BLE module */ + __IOM uint32_t DIV3 : 1; /*!< [12..12] Enable of the divide by 3 of the source IOCLK. */ + } CLKCFG_b; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t CMD; /*!< (@ 0x0000020C) Command and offset Register */ + + struct { + __IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */ + __IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1, + 2, 3 are valid selections. The second (byte 1) and third + byte (byte 2) are read from the OFFSETHI register, and + the low order byte is pulled from this register in the + OFFSETLO field.Offset bytes are transmitted highest byte + first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted + first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt == + 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If + offsetcnt == 1, only OFFSETLO will be transmitted. */ + __IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction + if set to a 1 with a new command issued. */ + __IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer + is not included in this size. */ + __IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information */ + uint32_t : 2; + __IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to + be used in the transaction. The number of offset bytes + to use is set with bits 1:0 of the command. Offset bytes + are transferred starting from the highest byte first. */ + } CMD_b; + } ; + + union { + __IOM uint32_t CMDRPT; /*!< (@ 0x00000210) Command Repeat Register */ + + struct { + __IOM uint32_t CMDRPT : 5; /*!< [4..0] Count of number of times to repeat the next command. */ + } CMDRPT_b; + } ; + + union { + __IOM uint32_t OFFSETHI; /*!< (@ 0x00000214) High order offset bytes */ + + struct { + __IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order bytes of the 2 or 3 byte offset + phase of a transaction. */ + } OFFSETHI_b; + } ; + + union { + __IOM uint32_t CMDSTAT; /*!< (@ 0x00000218) Command status */ + + struct { + __IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */ + __IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */ + __IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred + with this command. This field will count down to zero. */ + } CMDSTAT_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000220) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000224) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000228) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000022C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation + is done to a empty read FIFO. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in + the B2M_STATE signal from the BLE Core. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal + from the BLE Core is asserted, indicating the availability + of read data from the BLE Core. */ + __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS + signal from the BLE Core is asserted, indicating that SPI + writes can be done to the BLE Core.Transfers to the BLE + Core should only be done when this signal is high. */ + __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write + with the register address bit 0 set to 1. The low address + bits in the CQ address fields are unused and bit 0 can + be used to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error + occurs, the system will stop processing and halt operations + to allow software to take recovery actions */ + __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the + sleep state */ + __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned + into the active state Revision B: Falling BLE Core IRQ + signal. Asserted when the BLE_IRQ signal from the BLE Core + is de-asserted (1 -> 0) */ + __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned + into shutdown state Revision B: Falling BLE Core Status + signal. Asserted when the BLE_STATUS signal from the BLE + Core is de-asserted (1 -> 0) */ + } INTSET_b; + } ; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000230) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger + of the DMA when a command is completed. When this event + is triggered, the number of words transferred will be the + lesser of the remaining TOTCOUNT bytes, or the number of + bytes in the FIFO when the command completed. If this is + disabled, and the number of bytes in the FIFO is equal + or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT + bytes will be done to ensure read data is stored when the + DMA is completed. */ + __IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations + (IOM writes), the trigger will assert when the write FIFO + has (WTHR/4) number of words free in the write FIFO, and + will transfer (WTHR/4) number of wordsor, if the number + of words left to transfer is less than the WTHR value, + will transfer the remaining byte count.For P2M DMA operations, + the trigger will assert when the read FIFO has (RTHR/4) + words available in the read FIFO, and will transfer (RTHR/4) + words to SRAM. This trigger will NOT asser */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000234) DMA Trigger Status Register */ + + struct { + __IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read + only and can be cleared by disabling the DCMDCMP trigger + enable or by disabling DMA. */ + __IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can + be cleared by disabling the DTHR trigger enable or by disabling + DMA. */ + __IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data + in the FIFO was enough to complete the DMA operation (greater + than or equal to current TOTCOUNT) when the command completed. + This trigger is default active when the DCMDCMP trigger + isdisabled and there is enough data in the FIFO to complete + the DMA operation. */ + } DMATRIGSTAT_b; + } ; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000238) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA + operation. This should be the last DMA related register + set prior to issuing the command */ + __IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */ + uint32_t : 6; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DPWROFF : 1; /*!< [9..9] Power off module after DMA is complete. If this bit is + active, the module will request to power off the supply + it is attached to. If there are other units still requiring + power from the same domain, power down will not be performed. */ + } DMACFG_b; + } ; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x0000023C) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit + is read only and can be cleared by disabling the DTHR trigger + enable or by disabling DMA. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x00000240) DMA Target Address Register */ + + struct { + __IOM uint32_t TARGADDR : 20; /*!< [19..0] Bits [19:0] of the target byte address for source of + DMA (either read or write). The address can be any byte + alignment, and does not have to be word aligned. In cases + of non-word aligned addresses, the DMA logic will take + care for ensuring only the target bytes are read/written. */ + uint32_t : 8; + __IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA + (either read or write). In cases of non-word aligned addresses, + the DMA logic will take care for ensuring only the target + bytes are read/written.Setting to '1' will select the SRAM. + Setting to '0' will select the flash */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000244) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that + a DMA transfer is active. The DMA transfer may be waiting + on data, transferring data, or waiting for priority.All + of these will be indicated with a 1. A 0 will indicate + that the DMA is fully complete and no further transactions + will be done. This bit is read only. */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA + operation. This bit can be cleared by writing to 0. */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error + was encountered during the DMA operation. */ + } DMASTAT_b; + } ; + + union { + __IOM uint32_t CQCFG; /*!< (@ 0x00000248) Command Queue Configuration Register */ + + struct { + __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing + of the command queue and fetches of address/data pairs + will proceed from the word address within the CQADDR register. + Can be disabledusing a CQ executed write to this bit as + well. */ + __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request. */ + } CQCFG_b; + } ; + + union { + __IOM uint32_t CQADDR; /*!< (@ 0x0000024C) CQ Target Read Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source of CQ (read + only). The buffer must be aligned on a word boundary */ + uint32_t : 8; + __IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ (read + only). Used to denote Flash (0) or SRAM (1) access */ + } CQADDR_b; + } ; + + union { + __IOM uint32_t CQSTAT; /*!< (@ 0x00000250) Command Queue Status Register */ + + struct { + __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will + indicate that a CQ transfer is active and this will remain + active even when paused waiting for external event. */ + __IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */ + __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit + signals that an error was encountered during the CQ operation. */ + } CQSTAT_b; + } ; + + union { + __IOM uint32_t CQFLAGS; /*!< (@ 0x00000254) Command Queue Flag Register */ + + struct { + __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software + controllable and bits [15:8] are hardware status. */ + __IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Provides for a per-bit mask of the flags used to invoke + an interrupt. A '1' in the bit position will enable the + pause event to trigger the interrupt, if the CQWT_int interrupt + is enabled.Bits definitions are the same as CQPAUSE */ + } CQFLAGS_b; + } ; + + union { + __IOM uint32_t CQSETCLEAR; /*!< (@ 0x00000258) Command Queue Flag Set/Clear Register */ + + struct { + __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG + with a '1' in the corresponding bit position of this field */ + } CQSETCLEAR_b; + } ; + + union { + __IOM uint32_t CQPAUSEEN; /*!< (@ 0x0000025C) Command Queue Pause Enable Register */ + + struct { + __IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing + when active */ + } CQPAUSEEN_b; + } ; + + union { + __IOM uint32_t CQCURIDX; /*!< (@ 0x00000260) IOM Command Queue current index value . Compared + to the CQENDIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQCURIDX_b; + } ; + + union { + __IOM uint32_t CQENDIDX; /*!< (@ 0x00000264) IOM Command Queue current index value . Compared + to the CQCURIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQENDIDX_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000268) IOM Module Status Register */ + + struct { + __IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error + indicators. This will always return 0. */ + __IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing + a transaction, or command is complete, but the FIFO pointers + are still syncronizing internally. This bit will go high + atthe start of the transaction, and will go low when the + command is complete, and the data and pointers within the + FIFO have been syncronized. */ + __IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note + - The state machine could be in idle state due to holdoffs + from data availability, or as the command gets propagated + into the logic from the registers. */ + } STATUS_b; + } ; + __IM uint32_t RESERVED4[37]; + + union { + __IOM uint32_t MSPICFG; /*!< (@ 0x00000300) SPI module master configuration */ + + struct { + __IOM uint32_t SPOL : 1; /*!< [0..0] This bit selects SPI polarity. */ + __IOM uint32_t SPHA : 1; /*!< [1..1] Selects the SPI phase; When 1, will shift the sampling + edge by 1/2 clock. */ + __IOM uint32_t FULLDUP : 1; /*!< [2..2] Full Duplex mode. Capture read data during writes operations */ + uint32_t : 13; + __IOM uint32_t WTFC : 1; /*!< [16..16] Enables flow control of new write transactions based + on the SPI_STATUS signal from the BLE Core. */ + __IOM uint32_t RDFC : 1; /*!< [17..17] Enables flow control of new read transactions based + on the SPI_STATUS signal from the BLE Core. */ + uint32_t : 3; + __IOM uint32_t WTFCPOL : 1; /*!< [21..21] Selects the write flow control signal polarity. The + transfers are halted when the selected flow control signal + is OPPOSITE polarity of this bit. (For example: WTFCPOL + = 0 will allow a SPI_STATUS=1 to pause transfers). */ + __IOM uint32_t RDFCPOL : 1; /*!< [22..22] Selects the read flow control signal polarity. When + set, the clock will be held low until the flow control + is de-asserted. */ + __IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first + (1) for the data portion of the SPI transaction. The offset + bytes are always transmitted MSB first. */ + __IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This + gives more hold time on the input data. */ + __IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This + give more hold time on the output data. */ + __IOM uint32_t MSPIRST : 1; /*!< [30..30] Bit is deprecated. setting it will have no effect. */ + } MSPICFG_b; + } ; + + union { + __IOM uint32_t BLECFG; /*!< (@ 0x00000304) BLE Core Control */ + + struct { + __IOM uint32_t PWRSMEN : 1; /*!< [0..0] Enable the power state machine for automatic sequencing + and control of power states of the BLE Core module. */ + __IOM uint32_t BLERSTN : 1; /*!< [1..1] Reset line to the BLE Core. This will reset the BLE core + when asserted ('0') and must be written to '1' prior to + performing any BTLE related operations to the core. */ + __IOM uint32_t WAKEUPCTL : 2; /*!< [3..2] WAKE signal override. Controls the source of the WAKE + signal to the BLE Core. */ + __IOM uint32_t DCDCFLGCTL : 2; /*!< [5..4] DCDCFLG signal override. The value of this field will + be sent to the BLE Core when the PWRSM is off. Otherwise, + the value is supplied from internal logic. */ + __IOM uint32_t BLEHREQCTL : 2; /*!< [7..6] BLEH power on request override. The value of this field + will be sent to the BLE Core when the PWRSM is off. Otherwise, + the value is supplied from internal logic. */ + __IOM uint32_t WT4ACTOFF : 1; /*!< [8..8] Debug control of BLEIF power state machine. Allows transition + into the active state in the BLEIF state without waiting + for dcdc req from BLE Core. */ + __IOM uint32_t MCUFRCSLP : 1; /*!< [9..9] Force power state machine to go to the sleep state. Intended + for debug only. Has no effect on the actual BLE Core state, + only the state of the BLEIF interface state machine. */ + __IOM uint32_t FRCCLK : 1; /*!< [10..10] Force the clock in the BLEIF to be always running */ + __IOM uint32_t STAYASLEEP : 1; /*!< [11..11] Set to prevent the BLE power control module from waking + up the BLE Core after going into power down. To be used + for graceful shutdown, set by software prior to powering + off and will allow assertion of reset from sleep state. */ + __IOM uint32_t PWRISOCTL : 2; /*!< [13..12] Configuration of BLEH isolation control for power related + signals. */ + __IOM uint32_t SPIISOCTL : 2; /*!< [15..14] Configuration of BLEH isolation controls for SPI related + signals. */ + } BLECFG_b; + } ; + + union { + __IOM uint32_t PWRCMD; /*!< (@ 0x00000308) BLE Power command interface */ + + struct { + __IOM uint32_t WAKEREQ : 1; /*!< [0..0] Wake request from the MCU. When asserted (1), the BLE + Interface logic will assert the wakeup request signal to + the BLE Core. Only recognized when in the sleep state */ + __IOM uint32_t RESTART : 1; /*!< [1..1] Restart the BLE Core after going into the shutdown state. + Only valid when in the shutdown state. */ + } PWRCMD_b; + } ; + + union { + __IOM uint32_t BSTATUS; /*!< (@ 0x0000030C) BLE Core status */ + + struct { + __IOM uint32_t B2MSTATE : 3; /*!< [2..0] State of the BLE Core logic. */ + __IOM uint32_t SPISTATUS : 1; /*!< [3..3] Value of the SPISTATUS signal from the BLE Core. The + signal is asserted when the BLE Core is able to accept + write data via the SPI interface. Data should be transmitted + to theBLE core only when this signal is 1. The hardware + will automatically wait for this signal prior to performing + a write operation if flow control is active. */ + __IOM uint32_t DCDCREQ : 1; /*!< [4..4] Value of the DCDCREQ signal from the BLE Core. The DCDCREQ + signal is sent from the core to the BLEIF module when the + BLE core requires BLEH power to be active. When activated, + this isindicated by DCDCFLAG going to 1. */ + __IOM uint32_t DCDCFLAG : 1; /*!< [5..5] Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG + is a signal to the BLE Core indicating that the BLEH ppower + is active. */ + __IOM uint32_t WAKEUP : 1; /*!< [6..6] Value of the WAKEUP signal to the BLE Core . The WAKEUP + signals is sent from the BLEIF to the BLECORE to request + the BLE Core transition from sleep state to active state. */ + __IOM uint32_t BLEIRQ : 1; /*!< [7..7] Status of the BLEIRQ signal from the BLE Core. A value + of 1 idicates that read data is available in the core and + a read operation needs to be performed. */ + __IOM uint32_t PWRST : 3; /*!< [10..8] Current status of the power state machine */ + __IOM uint32_t BLEHACK : 1; /*!< [11..11] Value of the BLEHACK signal from the power control + unit. If the signal is '1', the BLEH power is active and + ready for use. */ + __IOM uint32_t BLEHREQ : 1; /*!< [12..12] Value of the BLEHREQ signal to the power control unit. + The BLEHREQ signal is sent from the BLEIF module to the + power control module to request the BLEH power up. When + the BLEHACK signal is asserted,BLEH power is stable and + ready for use. */ + } BSTATUS_b; + } ; + __IM uint32_t RESERVED5[64]; + + union { + __IOM uint32_t BLEDBG; /*!< (@ 0x00000410) BLEIF Master Debug Register */ + + struct { + __IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting this bit will enable the update + of data within this register, otherwise it is clock gated + for power savings */ + __IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug data */ + } BLEDBG_b; + } ; +} BLEIF_Type; /*!< Size = 1044 (0x414) */ + + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Flash Cache Controller (CACHECTRL) + */ + +typedef struct { /*!< (@ 0x40018000) CACHECTRL Structure */ + + union { + __IOM uint32_t CACHECFG; /*!< (@ 0x00000000) Flash Cache Control Register */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Enables the flash cache controller and enables power + to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE + should be set to enable caching for each type of access. */ + __IOM uint32_t LRU : 1; /*!< [1..1] Sets the cache repleacment policy. 0=LRR (least recently + replaced), 1=LRU (least recently used). LRR minimizes writes + to the TAG SRAM. */ + __IOM uint32_t ENABLE_NC0 : 1; /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to + define the region. */ + __IOM uint32_t ENABLE_NC1 : 1; /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to + define the region. */ + __IOM uint32_t CONFIG : 4; /*!< [7..4] Sets the cache configuration */ + __IOM uint32_t ICACHE_ENABLE : 1; /*!< [8..8] Enable Flash Instruction Caching */ + __IOM uint32_t DCACHE_ENABLE : 1; /*!< [9..9] Enable Flash Data Caching. */ + __IOM uint32_t CACHE_CLKGATE : 1; /*!< [10..10] Enable clock gating of cache TAG RAM. Software should + enable this bit for optimal power efficiency. */ + __IOM uint32_t CACHE_LS : 1; /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should + DISABLE this bit since cache activity is too high to benefit + from LS usage. */ + uint32_t : 8; + __IOM uint32_t DATA_CLKGATE : 1; /*!< [20..20] Enable aggressive clock gating of entire data array. + This bit should be set to 1 for optimal power efficiency. */ + uint32_t : 3; + __IOM uint32_t ENABLE_MONITOR : 1; /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes + additional power and should only be enabled when profiling + code and counters will increment when this bit is set. + Counter values will be retained when this is set to 0, + allowing software to enable/disable counting for multiple + code segments. */ + } CACHECFG_b; + } ; + + union { + __IOM uint32_t FLASHCFG; /*!< (@ 0x00000004) Flash Control Register */ + + struct { + __IOM uint32_t RD_WAIT : 4; /*!< [3..0] Sets read waitstates for normal (fast) operation. A value + of 1 is recommended. */ + __IOM uint32_t SEDELAY : 3; /*!< [6..4] Sets SE delay (flash address setup). A value of 5 is + recommended. */ + uint32_t : 1; + __IOM uint32_t LPM_RD_WAIT : 4; /*!< [11..8] Sets flash waitstates when in LPM Mode 2 (RD_WAIT in + LPM mode 2 only) */ + __IOM uint32_t LPMMODE : 2; /*!< [13..12] Controls flash low power modes (control of LPM pin). */ + } FLASHCFG_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Cache Control */ + + struct { + __IOM uint32_t INVALIDATE : 1; /*!< [0..0] Writing a 1 to this bitfield invalidates the flash cache + contents. */ + __IOM uint32_t RESET_STAT : 1; /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache + monitor counters will be cleared. The monitor counters + can be reset only when the CACHECFG.ENABLE_MONITOR bit + is set. */ + __IOM uint32_t CACHE_READY : 1; /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate + operation) */ + uint32_t : 1; + __IOM uint32_t FLASH0_SLM_STATUS : 1; /*!< [4..4] Flash Sleep Mode Status. 1 indicates that flash0 is in + sleep mode, 0 indicates flash0 is in normal mode. */ + __IOM uint32_t FLASH0_SLM_DISABLE : 1; /*!< [5..5] Disable Flash Sleep Mode. Write 1 to wake flash0 from + sleep mode (reading the array will also automatically wake + it). */ + __IOM uint32_t FLASH0_SLM_ENABLE : 1; /*!< [6..6] Enable Flash Sleep Mode. Write to 1 to put flash 0 into + sleep mode. NOTE: there is a 5us latency after waking flash + until the first access will be returned. */ + uint32_t : 1; + __IOM uint32_t FLASH1_SLM_STATUS : 1; /*!< [8..8] Flash Sleep Mode Status. 1 indicates that flash1 is in + sleep mode, 0 indicates flash1 is in normal mode. */ + __IOM uint32_t FLASH1_SLM_DISABLE : 1; /*!< [9..9] Disable Flash Sleep Mode. Write 1 to wake flash1 from + sleep mode (reading the array will also automatically wake + it). */ + __IOM uint32_t FLASH1_SLM_ENABLE : 1; /*!< [10..10] Enable Flash Sleep Mode. Write to 1 to put flash 1 + into sleep mode. NOTE: there is a 5us latency after waking + flash until the first access will be returned. */ + } CTRL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t NCR0START; /*!< (@ 0x00000010) Flash Cache Noncachable Region 0 Start */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 0 */ + } NCR0START_b; + } ; + + union { + __IOM uint32_t NCR0END; /*!< (@ 0x00000014) Flash Cache Noncachable Region 0 End */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 0 */ + } NCR0END_b; + } ; + + union { + __IOM uint32_t NCR1START; /*!< (@ 0x00000018) Flash Cache Noncachable Region 1 Start */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 1 */ + } NCR1START_b; + } ; + + union { + __IOM uint32_t NCR1END; /*!< (@ 0x0000001C) Flash Cache Noncachable Region 1 End */ + + struct { + uint32_t : 4; + __IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 1 */ + } NCR1END_b; + } ; + __IM uint32_t RESERVED1[8]; + + union { + __IOM uint32_t DMON0; /*!< (@ 0x00000040) Data Cache Total Accesses */ + + struct { + __IOM uint32_t DACCESS_COUNT : 32; /*!< [31..0] Total accesses to data cache. All performance metrics + should be relative to the number of accesses performed. */ + } DMON0_b; + } ; + + union { + __IOM uint32_t DMON1; /*!< (@ 0x00000044) Data Cache Tag Lookups */ + + struct { + __IOM uint32_t DLOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from data cache. */ + } DMON1_b; + } ; + + union { + __IOM uint32_t DMON2; /*!< (@ 0x00000048) Data Cache Hits */ + + struct { + __IOM uint32_t DHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations. */ + } DMON2_b; + } ; + + union { + __IOM uint32_t DMON3; /*!< (@ 0x0000004C) Data Cache Line Hits */ + + struct { + __IOM uint32_t DLINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ + } DMON3_b; + } ; + + union { + __IOM uint32_t IMON0; /*!< (@ 0x00000050) Instruction Cache Total Accesses */ + + struct { + __IOM uint32_t IACCESS_COUNT : 32; /*!< [31..0] Total accesses to Instruction cache */ + } IMON0_b; + } ; + + union { + __IOM uint32_t IMON1; /*!< (@ 0x00000054) Instruction Cache Tag Lookups */ + + struct { + __IOM uint32_t ILOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from Instruction cache */ + } IMON1_b; + } ; + + union { + __IOM uint32_t IMON2; /*!< (@ 0x00000058) Instruction Cache Hits */ + + struct { + __IOM uint32_t IHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations */ + } IMON2_b; + } ; + + union { + __IOM uint32_t IMON3; /*!< (@ 0x0000005C) Instruction Cache Line Hits */ + + struct { + __IOM uint32_t ILINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ + } IMON3_b; + } ; +} CACHECTRL_Type; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock Generator (CLKGEN) + */ + +typedef struct { /*!< (@ 0x40004000) CLKGEN Structure */ + + union { + __IOM uint32_t CALXT; /*!< (@ 0x00000000) XT Oscillator Control */ + + struct { + __IOM uint32_t CALXT : 11; /*!< [10..0] XT Oscillator calibration value. This register will + enable the hardware to increase or decrease the number + of cycles in a 16KHz clock derived from the original 32KHz + version. The most significant bit is the sign. A '1' is + a reduction, and a '0' is an addition. This calibration + value will add or reduce the number of cycles programmed + here across a 32 second interval. The maximum value that + is effective is from -1024 to 1023. */ + } CALXT_b; + } ; + + union { + __IOM uint32_t CALRC; /*!< (@ 0x00000004) RC Oscillator Control */ + + struct { + __IOM uint32_t CALRC : 18; /*!< [17..0] LFRC Oscillator calibration value. This register will + enable the hardware to increase or decrease the number + of cycles in a 512 Hz clock derived from the original 1024 + version. The most significant bit is the sign. A '1' is + a reduction, and a '0' is an addition. This calibration + value will add or reduce the number of cycles programmed + here across a 32 second interval. The range is from -131072 + (decimal) to 131071 (decimal). This register is normally + used in conjuction with ACALCTR register. The CAL */ + } CALRC_b; + } ; + + union { + __IOM uint32_t ACALCTR; /*!< (@ 0x00000008) Autocalibration Counter */ + + struct { + __IOM uint32_t ACALCTR : 24; /*!< [23..0] Autocalibration Counter result. Bits 17 down to 0 of + this is feed directly to the CALRC register if ACAL register + in OCTRL register is set to 1024SEC or 512SEC. */ + } ACALCTR_b; + } ; + + union { + __IOM uint32_t OCTRL; /*!< (@ 0x0000000C) Oscillator Control */ + + struct { + __IOM uint32_t STOPXT : 1; /*!< [0..0] Stop the XT Oscillator to the RTC */ + __IOM uint32_t STOPRC : 1; /*!< [1..1] Stop the LFRC Oscillator to the RTC */ + uint32_t : 4; + __IOM uint32_t FOS : 1; /*!< [6..6] Oscillator switch on failure function. If this is set, + then LFRC clock source will switch from XT to RC. */ + __IOM uint32_t OSEL : 1; /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT) */ + __IOM uint32_t ACAL : 3; /*!< [10..8] Autocalibration control. This selects the source to + be used in the autocalibration flow. This flow can also + be used to measure an internal clock against an external + clock source, with the external clock normally used as + the reference. */ + } OCTRL_b; + } ; + + union { + __IOM uint32_t CLKOUT; /*!< (@ 0x00000010) CLKOUT Frequency Select */ + + struct { + __IOM uint32_t CKSEL : 6; /*!< [5..0] CLKOUT signal select */ + uint32_t : 1; + __IOM uint32_t CKEN : 1; /*!< [7..7] Enable the CLKOUT signal */ + } CLKOUT_b; + } ; + + union { + __IOM uint32_t CLKKEY; /*!< (@ 0x00000014) Key Register for Clock Control Register */ + + struct { + __IOM uint32_t CLKKEY : 32; /*!< [31..0] Key register value. */ + } CLKKEY_b; + } ; + + union { + __IOM uint32_t CCTRL; /*!< (@ 0x00000018) HFRC Clock Control */ + + struct { + __IOM uint32_t CORESEL : 1; /*!< [0..0] Core Clock divisor */ + } CCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x0000001C) Clock Generator Status */ + + struct { + __IOM uint32_t OMODE : 1; /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT). After an + RTC oscillator change, it may take up to 2 seconds for + this field to reflect the new oscillator. */ + __IOM uint32_t OSCF : 1; /*!< [1..1] XT Oscillator is enabled but not oscillating */ + } STATUS_b; + } ; + + union { + __IOM uint32_t HFADJ; /*!< (@ 0x00000020) HFRC Adjustment */ + + struct { + __IOM uint32_t HFADJEN : 1; /*!< [0..0] HFRC adjustment control */ + __IOM uint32_t HFADJCK : 3; /*!< [3..1] Repeat period for HFRC adjustment */ + uint32_t : 4; + __IOM uint32_t HFXTADJ : 12; /*!< [19..8] Target HFRC adjustment value. */ + __IOM uint32_t HFWARMUP : 1; /*!< [20..20] XT warmup period for HFRC adjustment */ + __IOM uint32_t HFADJGAIN : 3; /*!< [23..21] Gain control for HFRC adjustment */ + } HFADJ_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CLOCKENSTAT; /*!< (@ 0x00000028) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKENSTAT : 32; /*!< [31..0] Clock enable status */ + } CLOCKENSTAT_b; + } ; + + union { + __IOM uint32_t CLOCKEN2STAT; /*!< (@ 0x0000002C) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKEN2STAT : 32; /*!< [31..0] Clock enable status 2 */ + } CLOCKEN2STAT_b; + } ; + + union { + __IOM uint32_t CLOCKEN3STAT; /*!< (@ 0x00000030) Clock Enable Status */ + + struct { + __IOM uint32_t CLOCKEN3STAT : 32; /*!< [31..0] Clock enable status 3 */ + } CLOCKEN3STAT_b; + } ; + + union { + __IOM uint32_t FREQCTRL; /*!< (@ 0x00000034) HFRC Frequency Control register */ + + struct { + __IOM uint32_t BURSTREQ : 1; /*!< [0..0] Frequency Burst Enable Request */ + __IOM uint32_t BURSTACK : 1; /*!< [1..1] Frequency Burst Request Acknowledge. Frequency burst + requested is always acknowledged whether burst is granted + or not depending on feature enable. */ + __IOM uint32_t BURSTSTATUS : 1; /*!< [2..2] This represents frequency burst status. */ + } FREQCTRL_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t BLEBUCKTONADJ; /*!< (@ 0x0000003C) BLE BUCK TON ADJUST */ + + struct { + __IOM uint32_t TONLOWTHRESHOLD : 10; /*!< [9..0] TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) + #15(47KHz) #53(12Khz) #14D(3Khz) */ + __IOM uint32_t TONHIGHTHRESHOLD : 10; /*!< [19..10] TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) + #2A(47Khz) #A6(12Khz) #29A(3Khz) */ + __IOM uint32_t TONADJUSTPERIOD : 2; /*!< [21..20] TON ADJUST PERIOD */ + __IOM uint32_t TONADJUSTEN : 1; /*!< [22..22] TON ADJUST ENABLE */ + __IOM uint32_t ZEROLENDETECTTRIM : 4; /*!< [26..23] BLEBUCK ZERO LENGTH DETECT TRIM */ + __IOM uint32_t ZEROLENDETECTEN : 1; /*!< [27..27] BLEBUCK ZERO LENGTH DETECT ENABLE */ + } BLEBUCKTONADJ_b; + } ; + __IM uint32_t RESERVED2[48]; + + union { + __IOM uint32_t INTRPTEN; /*!< (@ 0x00000100) CLKGEN Interrupt Register: Enable */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTEN_b; + } ; + + union { + __IOM uint32_t INTRPTSTAT; /*!< (@ 0x00000104) CLKGEN Interrupt Register: Status */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTSTAT_b; + } ; + + union { + __IOM uint32_t INTRPTCLR; /*!< (@ 0x00000108) CLKGEN Interrupt Register: Clear */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTCLR_b; + } ; + + union { + __IOM uint32_t INTRPTSET; /*!< (@ 0x0000010C) CLKGEN Interrupt Register: Set */ + + struct { + __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ + __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ + __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ + } INTRPTSET_b; + } ; +} CLKGEN_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Counter/Timer (CTIMER) + */ + +typedef struct { /*!< (@ 0x40008000) CTIMER Structure */ + + union { + __IOM uint32_t TMR0; /*!< (@ 0x00000000) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA0 : 16; /*!< [15..0] Counter/Timer A0. */ + __IOM uint32_t CTTMRB0 : 16; /*!< [31..16] Counter/Timer B0. */ + } TMR0_b; + } ; + + union { + __IOM uint32_t CMPRA0; /*!< (@ 0x00000004) Counter/Timer A0 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR1A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper + limit for timer half A. */ + } CMPRA0_b; + } ; + + union { + __IOM uint32_t CMPRB0; /*!< (@ 0x00000008) Counter/Timer B0 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR1B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper + limit for timer half B. */ + } CMPRB0_b; + } ; + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x0000000C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA0EN : 1; /*!< [0..0] Counter/Timer A0 Enable bit. */ + __IOM uint32_t TMRA0CLK : 5; /*!< [5..1] Counter/Timer A0 Clock Select. */ + __IOM uint32_t TMRA0FN : 3; /*!< [8..6] Counter/Timer A0 Function Select. */ + __IOM uint32_t TMRA0IE0 : 1; /*!< [9..9] Counter/Timer A0 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA0IE1 : 1; /*!< [10..10] Counter/Timer A0 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA0CLR : 1; /*!< [11..11] Counter/Timer A0 Clear bit. */ + __IOM uint32_t TMRA0POL : 1; /*!< [12..12] Counter/Timer A0 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB0EN : 1; /*!< [16..16] Counter/Timer B0 Enable bit. */ + __IOM uint32_t TMRB0CLK : 5; /*!< [21..17] Counter/Timer B0 Clock Select. */ + __IOM uint32_t TMRB0FN : 3; /*!< [24..22] Counter/Timer B0 Function Select. */ + __IOM uint32_t TMRB0IE0 : 1; /*!< [25..25] Counter/Timer B0 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB0IE1 : 1; /*!< [26..26] Counter/Timer B0 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB0CLR : 1; /*!< [27..27] Counter/Timer B0 Clear bit. */ + __IOM uint32_t TMRB0POL : 1; /*!< [28..28] Counter/Timer B0 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK0 : 1; /*!< [31..31] Counter/Timer A0/B0 Link bit. */ + } CTRL0_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CMPRAUXA0; /*!< (@ 0x00000014) Counter/Timer A0 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA0_b; + } ; + + union { + __IOM uint32_t CMPRAUXB0; /*!< (@ 0x00000018) Counter/Timer B0 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB0_b; + } ; + + union { + __IOM uint32_t AUX0; /*!< (@ 0x0000001C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA0LMT : 7; /*!< [6..0] Counter/Timer A0 Pattern Limit Count. */ + __IOM uint32_t TMRA0TRIG : 4; /*!< [10..7] Counter/Timer A0 Trigger Select. */ + __IOM uint32_t TMRA0NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA0TINV : 1; /*!< [12..12] Counter/Timer A0 Invert on trigger. */ + __IOM uint32_t TMRA0POL23 : 1; /*!< [13..13] Counter/Timer A0 Upper output polarity */ + __IOM uint32_t TMRA0EN23 : 1; /*!< [14..14] Counter/Timer A0 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB0LMT : 6; /*!< [21..16] Counter/Timer B0 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB0TRIG : 4; /*!< [26..23] Counter/Timer B0 Trigger Select. */ + __IOM uint32_t TMRB0NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB0TINV : 1; /*!< [28..28] Counter/Timer B0 Invert on trigger. */ + __IOM uint32_t TMRB0POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB0EN23 : 1; /*!< [30..30] Counter/Timer B0 Upper compare enable. */ + } AUX0_b; + } ; + + union { + __IOM uint32_t TMR1; /*!< (@ 0x00000020) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA1 : 16; /*!< [15..0] Counter/Timer A1. */ + __IOM uint32_t CTTMRB1 : 16; /*!< [31..16] Counter/Timer B1. */ + } TMR1_b; + } ; + + union { + __IOM uint32_t CMPRA1; /*!< (@ 0x00000024) Counter/Timer A1 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 0. */ + __IOM uint32_t CMPR1A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 1. */ + } CMPRA1_b; + } ; + + union { + __IOM uint32_t CMPRB1; /*!< (@ 0x00000028) Counter/Timer B1 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 0. */ + __IOM uint32_t CMPR1B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 1. */ + } CMPRB1_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x0000002C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA1EN : 1; /*!< [0..0] Counter/Timer A1 Enable bit. */ + __IOM uint32_t TMRA1CLK : 5; /*!< [5..1] Counter/Timer A1 Clock Select. */ + __IOM uint32_t TMRA1FN : 3; /*!< [8..6] Counter/Timer A1 Function Select. */ + __IOM uint32_t TMRA1IE0 : 1; /*!< [9..9] Counter/Timer A1 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA1IE1 : 1; /*!< [10..10] Counter/Timer A1 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA1CLR : 1; /*!< [11..11] Counter/Timer A1 Clear bit. */ + __IOM uint32_t TMRA1POL : 1; /*!< [12..12] Counter/Timer A1 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB1EN : 1; /*!< [16..16] Counter/Timer B1 Enable bit. */ + __IOM uint32_t TMRB1CLK : 5; /*!< [21..17] Counter/Timer B1 Clock Select. */ + __IOM uint32_t TMRB1FN : 3; /*!< [24..22] Counter/Timer B1 Function Select. */ + __IOM uint32_t TMRB1IE0 : 1; /*!< [25..25] Counter/Timer B1 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB1IE1 : 1; /*!< [26..26] Counter/Timer B1 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB1CLR : 1; /*!< [27..27] Counter/Timer B1 Clear bit. */ + __IOM uint32_t TMRB1POL : 1; /*!< [28..28] Counter/Timer B1 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK1 : 1; /*!< [31..31] Counter/Timer A1/B1 Link bit. */ + } CTRL1_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t CMPRAUXA1; /*!< (@ 0x00000034) Counter/Timer A1 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA1_b; + } ; + + union { + __IOM uint32_t CMPRAUXB1; /*!< (@ 0x00000038) Counter/Timer B1 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB1_b; + } ; + + union { + __IOM uint32_t AUX1; /*!< (@ 0x0000003C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA1LMT : 7; /*!< [6..0] Counter/Timer A1 Pattern Limit Count. */ + __IOM uint32_t TMRA1TRIG : 4; /*!< [10..7] Counter/Timer A1 Trigger Select. */ + __IOM uint32_t TMRA1NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA1TINV : 1; /*!< [12..12] Counter/Timer A1 Invert on trigger. */ + __IOM uint32_t TMRA1POL23 : 1; /*!< [13..13] Counter/Timer A1 Upper output polarity */ + __IOM uint32_t TMRA1EN23 : 1; /*!< [14..14] Counter/Timer A1 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB1LMT : 6; /*!< [21..16] Counter/Timer B1 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB1TRIG : 4; /*!< [26..23] Counter/Timer B1 Trigger Select. */ + __IOM uint32_t TMRB1NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB1TINV : 1; /*!< [28..28] Counter/Timer B1 Invert on trigger. */ + __IOM uint32_t TMRB1POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB1EN23 : 1; /*!< [30..30] Counter/Timer B1 Upper compare enable. */ + } AUX1_b; + } ; + + union { + __IOM uint32_t TMR2; /*!< (@ 0x00000040) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA2 : 16; /*!< [15..0] Counter/Timer A2. */ + __IOM uint32_t CTTMRB2 : 16; /*!< [31..16] Counter/Timer B2. */ + } TMR2_b; + } ; + + union { + __IOM uint32_t CMPRA2; /*!< (@ 0x00000044) Counter/Timer A2 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 0. */ + __IOM uint32_t CMPR1A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 1. */ + } CMPRA2_b; + } ; + + union { + __IOM uint32_t CMPRB2; /*!< (@ 0x00000048) Counter/Timer B2 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 0. */ + __IOM uint32_t CMPR1B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 1. */ + } CMPRB2_b; + } ; + + union { + __IOM uint32_t CTRL2; /*!< (@ 0x0000004C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA2EN : 1; /*!< [0..0] Counter/Timer A2 Enable bit. */ + __IOM uint32_t TMRA2CLK : 5; /*!< [5..1] Counter/Timer A2 Clock Select. */ + __IOM uint32_t TMRA2FN : 3; /*!< [8..6] Counter/Timer A2 Function Select. */ + __IOM uint32_t TMRA2IE0 : 1; /*!< [9..9] Counter/Timer A2 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA2IE1 : 1; /*!< [10..10] Counter/Timer A2 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA2CLR : 1; /*!< [11..11] Counter/Timer A2 Clear bit. */ + __IOM uint32_t TMRA2POL : 1; /*!< [12..12] Counter/Timer A2 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB2EN : 1; /*!< [16..16] Counter/Timer B2 Enable bit. */ + __IOM uint32_t TMRB2CLK : 5; /*!< [21..17] Counter/Timer B2 Clock Select. */ + __IOM uint32_t TMRB2FN : 3; /*!< [24..22] Counter/Timer B2 Function Select. */ + __IOM uint32_t TMRB2IE0 : 1; /*!< [25..25] Counter/Timer B2 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB2IE1 : 1; /*!< [26..26] Counter/Timer B2 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB2CLR : 1; /*!< [27..27] Counter/Timer B2 Clear bit. */ + __IOM uint32_t TMRB2POL : 1; /*!< [28..28] Counter/Timer B2 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK2 : 1; /*!< [31..31] Counter/Timer A2/B2 Link bit. */ + } CTRL2_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t CMPRAUXA2; /*!< (@ 0x00000054) Counter/Timer A2 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA2_b; + } ; + + union { + __IOM uint32_t CMPRAUXB2; /*!< (@ 0x00000058) Counter/Timer B2 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB2_b; + } ; + + union { + __IOM uint32_t AUX2; /*!< (@ 0x0000005C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA2LMT : 7; /*!< [6..0] Counter/Timer A2 Pattern Limit Count. */ + __IOM uint32_t TMRA2TRIG : 4; /*!< [10..7] Counter/Timer A2 Trigger Select. */ + __IOM uint32_t TMRA2NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA2TINV : 1; /*!< [12..12] Counter/Timer A2 Invert on trigger. */ + __IOM uint32_t TMRA2POL23 : 1; /*!< [13..13] Counter/Timer A2 Upper output polarity */ + __IOM uint32_t TMRA2EN23 : 1; /*!< [14..14] Counter/Timer A2 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB2LMT : 6; /*!< [21..16] Counter/Timer B2 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB2TRIG : 4; /*!< [26..23] Counter/Timer B2 Trigger Select. */ + __IOM uint32_t TMRB2NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB2TINV : 1; /*!< [28..28] Counter/Timer B2 Invert on trigger. */ + __IOM uint32_t TMRB2POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB2EN23 : 1; /*!< [30..30] Counter/Timer B2 Upper compare enable. */ + } AUX2_b; + } ; + + union { + __IOM uint32_t TMR3; /*!< (@ 0x00000060) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA3 : 16; /*!< [15..0] Counter/Timer A3. */ + __IOM uint32_t CTTMRB3 : 16; /*!< [31..16] Counter/Timer B3. */ + } TMR3_b; + } ; + + union { + __IOM uint32_t CMPRA3; /*!< (@ 0x00000064) Counter/Timer A3 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 0. */ + __IOM uint32_t CMPR1A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 1. */ + } CMPRA3_b; + } ; + + union { + __IOM uint32_t CMPRB3; /*!< (@ 0x00000068) Counter/Timer B3 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */ + __IOM uint32_t CMPR1B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */ + } CMPRB3_b; + } ; + + union { + __IOM uint32_t CTRL3; /*!< (@ 0x0000006C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA3EN : 1; /*!< [0..0] Counter/Timer A3 Enable bit. */ + __IOM uint32_t TMRA3CLK : 5; /*!< [5..1] Counter/Timer A3 Clock Select. */ + __IOM uint32_t TMRA3FN : 3; /*!< [8..6] Counter/Timer A3 Function Select. */ + __IOM uint32_t TMRA3IE0 : 1; /*!< [9..9] Counter/Timer A3 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA3IE1 : 1; /*!< [10..10] Counter/Timer A3 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA3CLR : 1; /*!< [11..11] Counter/Timer A3 Clear bit. */ + __IOM uint32_t TMRA3POL : 1; /*!< [12..12] Counter/Timer A3 output polarity. */ + uint32_t : 2; + __IOM uint32_t ADCEN : 1; /*!< [15..15] Special Timer A3 enable for ADC function. */ + __IOM uint32_t TMRB3EN : 1; /*!< [16..16] Counter/Timer B3 Enable bit. */ + __IOM uint32_t TMRB3CLK : 5; /*!< [21..17] Counter/Timer B3 Clock Select. */ + __IOM uint32_t TMRB3FN : 3; /*!< [24..22] Counter/Timer B3 Function Select. */ + __IOM uint32_t TMRB3IE0 : 1; /*!< [25..25] Counter/Timer B3 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB3IE1 : 1; /*!< [26..26] Counter/Timer B3 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB3CLR : 1; /*!< [27..27] Counter/Timer B3 Clear bit. */ + __IOM uint32_t TMRB3POL : 1; /*!< [28..28] Counter/Timer B3 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK3 : 1; /*!< [31..31] Counter/Timer A3/B3 Link bit. */ + } CTRL3_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CMPRAUXA3; /*!< (@ 0x00000074) Counter/Timer A3 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA3_b; + } ; + + union { + __IOM uint32_t CMPRAUXB3; /*!< (@ 0x00000078) Counter/Timer B3 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB3_b; + } ; + + union { + __IOM uint32_t AUX3; /*!< (@ 0x0000007C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA3LMT : 7; /*!< [6..0] Counter/Timer A3 Pattern Limit Count. */ + __IOM uint32_t TMRA3TRIG : 4; /*!< [10..7] Counter/Timer A3 Trigger Select. */ + __IOM uint32_t TMRA3NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA3TINV : 1; /*!< [12..12] Counter/Timer A3 Invert on trigger. */ + __IOM uint32_t TMRA3POL23 : 1; /*!< [13..13] Counter/Timer A3 Upper output polarity */ + __IOM uint32_t TMRA3EN23 : 1; /*!< [14..14] Counter/Timer A3 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB3LMT : 6; /*!< [21..16] Counter/Timer B3 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB3TRIG : 4; /*!< [26..23] Counter/Timer B3 Trigger Select. */ + __IOM uint32_t TMRB3NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB3TINV : 1; /*!< [28..28] Counter/Timer B3 Invert on trigger. */ + __IOM uint32_t TMRB3POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB3EN23 : 1; /*!< [30..30] Counter/Timer B3 Upper compare enable. */ + } AUX3_b; + } ; + + union { + __IOM uint32_t TMR4; /*!< (@ 0x00000080) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA4 : 16; /*!< [15..0] Counter/Timer A4. */ + __IOM uint32_t CTTMRB4 : 16; /*!< [31..16] Counter/Timer B4. */ + } TMR4_b; + } ; + + union { + __IOM uint32_t CMPRA4; /*!< (@ 0x00000084) Counter/Timer A4 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 0. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR1A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 1. Holds the upper + limit for timer half A. */ + } CMPRA4_b; + } ; + + union { + __IOM uint32_t CMPRB4; /*!< (@ 0x00000088) Counter/Timer B4 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 0. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR1B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 1. Holds the upper + limit for timer half B. */ + } CMPRB4_b; + } ; + + union { + __IOM uint32_t CTRL4; /*!< (@ 0x0000008C) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA4EN : 1; /*!< [0..0] Counter/Timer A4 Enable bit. */ + __IOM uint32_t TMRA4CLK : 5; /*!< [5..1] Counter/Timer A4 Clock Select. */ + __IOM uint32_t TMRA4FN : 3; /*!< [8..6] Counter/Timer A4 Function Select. */ + __IOM uint32_t TMRA4IE0 : 1; /*!< [9..9] Counter/Timer A4 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA4IE1 : 1; /*!< [10..10] Counter/Timer A4 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA4CLR : 1; /*!< [11..11] Counter/Timer A4 Clear bit. */ + __IOM uint32_t TMRA4POL : 1; /*!< [12..12] Counter/Timer A4 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB4EN : 1; /*!< [16..16] Counter/Timer B4 Enable bit. */ + __IOM uint32_t TMRB4CLK : 5; /*!< [21..17] Counter/Timer B4 Clock Select. */ + __IOM uint32_t TMRB4FN : 3; /*!< [24..22] Counter/Timer B4 Function Select. */ + __IOM uint32_t TMRB4IE0 : 1; /*!< [25..25] Counter/Timer B4 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB4IE1 : 1; /*!< [26..26] Counter/Timer B4 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB4CLR : 1; /*!< [27..27] Counter/Timer B4 Clear bit. */ + __IOM uint32_t TMRB4POL : 1; /*!< [28..28] Counter/Timer B4 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK4 : 1; /*!< [31..31] Counter/Timer A4/B4 Link bit. */ + } CTRL4_b; + } ; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t CMPRAUXA4; /*!< (@ 0x00000094) Counter/Timer A4 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA4_b; + } ; + + union { + __IOM uint32_t CMPRAUXB4; /*!< (@ 0x00000098) Counter/Timer B4 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB4_b; + } ; + + union { + __IOM uint32_t AUX4; /*!< (@ 0x0000009C) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA4LMT : 7; /*!< [6..0] Counter/Timer A4 Pattern Limit Count. */ + __IOM uint32_t TMRA4TRIG : 4; /*!< [10..7] Counter/Timer A4 Trigger Select. */ + __IOM uint32_t TMRA4NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA4TINV : 1; /*!< [12..12] Counter/Timer A4 Invert on trigger. */ + __IOM uint32_t TMRA4POL23 : 1; /*!< [13..13] Counter/Timer A4 Upper output polarity */ + __IOM uint32_t TMRA4EN23 : 1; /*!< [14..14] Counter/Timer A4 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB4LMT : 6; /*!< [21..16] Counter/Timer B4 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB4TRIG : 4; /*!< [26..23] Counter/Timer B4 Trigger Select. */ + __IOM uint32_t TMRB4NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB4TINV : 1; /*!< [28..28] Counter/Timer B4 Invert on trigger. */ + __IOM uint32_t TMRB4POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB4EN23 : 1; /*!< [30..30] Counter/Timer B4 Upper compare enable. */ + } AUX4_b; + } ; + + union { + __IOM uint32_t TMR5; /*!< (@ 0x000000A0) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA5 : 16; /*!< [15..0] Counter/Timer A5. */ + __IOM uint32_t CTTMRB5 : 16; /*!< [31..16] Counter/Timer B5. */ + } TMR5_b; + } ; + + union { + __IOM uint32_t CMPRA5; /*!< (@ 0x000000A4) Counter/Timer A5 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 0. */ + __IOM uint32_t CMPR1A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 1. */ + } CMPRA5_b; + } ; + + union { + __IOM uint32_t CMPRB5; /*!< (@ 0x000000A8) Counter/Timer B5 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 0. */ + __IOM uint32_t CMPR1B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 1. */ + } CMPRB5_b; + } ; + + union { + __IOM uint32_t CTRL5; /*!< (@ 0x000000AC) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA5EN : 1; /*!< [0..0] Counter/Timer A5 Enable bit. */ + __IOM uint32_t TMRA5CLK : 5; /*!< [5..1] Counter/Timer A5 Clock Select. */ + __IOM uint32_t TMRA5FN : 3; /*!< [8..6] Counter/Timer A5 Function Select. */ + __IOM uint32_t TMRA5IE0 : 1; /*!< [9..9] Counter/Timer A5 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA5IE1 : 1; /*!< [10..10] Counter/Timer A5 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA5CLR : 1; /*!< [11..11] Counter/Timer A5 Clear bit. */ + __IOM uint32_t TMRA5POL : 1; /*!< [12..12] Counter/Timer A5 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB5EN : 1; /*!< [16..16] Counter/Timer B5 Enable bit. */ + __IOM uint32_t TMRB5CLK : 5; /*!< [21..17] Counter/Timer B5 Clock Select. */ + __IOM uint32_t TMRB5FN : 3; /*!< [24..22] Counter/Timer B5 Function Select. */ + __IOM uint32_t TMRB5IE0 : 1; /*!< [25..25] Counter/Timer B5 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB5IE1 : 1; /*!< [26..26] Counter/Timer B5 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB5CLR : 1; /*!< [27..27] Counter/Timer B5 Clear bit. */ + __IOM uint32_t TMRB5POL : 1; /*!< [28..28] Counter/Timer B5 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK5 : 1; /*!< [31..31] Counter/Timer A5/B5 Link bit. */ + } CTRL5_b; + } ; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t CMPRAUXA5; /*!< (@ 0x000000B4) Counter/Timer A5 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA5_b; + } ; + + union { + __IOM uint32_t CMPRAUXB5; /*!< (@ 0x000000B8) Counter/Timer B5 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB5_b; + } ; + + union { + __IOM uint32_t AUX5; /*!< (@ 0x000000BC) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA5LMT : 7; /*!< [6..0] Counter/Timer A5 Pattern Limit Count. */ + __IOM uint32_t TMRA5TRIG : 4; /*!< [10..7] Counter/Timer A5 Trigger Select. */ + __IOM uint32_t TMRA5NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA5TINV : 1; /*!< [12..12] Counter/Timer A5 Invert on trigger. */ + __IOM uint32_t TMRA5POL23 : 1; /*!< [13..13] Counter/Timer A5 Upper output polarity */ + __IOM uint32_t TMRA5EN23 : 1; /*!< [14..14] Counter/Timer A5 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB5LMT : 6; /*!< [21..16] Counter/Timer B5 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB5TRIG : 4; /*!< [26..23] Counter/Timer B5 Trigger Select. */ + __IOM uint32_t TMRB5NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB5TINV : 1; /*!< [28..28] Counter/Timer B5 Invert on trigger. */ + __IOM uint32_t TMRB5POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB5EN23 : 1; /*!< [30..30] Counter/Timer B5 Upper compare enable. */ + } AUX5_b; + } ; + + union { + __IOM uint32_t TMR6; /*!< (@ 0x000000C0) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA6 : 16; /*!< [15..0] Counter/Timer A6. */ + __IOM uint32_t CTTMRB6 : 16; /*!< [31..16] Counter/Timer B6. */ + } TMR6_b; + } ; + + union { + __IOM uint32_t CMPRA6; /*!< (@ 0x000000C4) Counter/Timer A6 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 0. */ + __IOM uint32_t CMPR1A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 1. */ + } CMPRA6_b; + } ; + + union { + __IOM uint32_t CMPRB6; /*!< (@ 0x000000C8) Counter/Timer B6 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 0. */ + __IOM uint32_t CMPR1B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 1. */ + } CMPRB6_b; + } ; + + union { + __IOM uint32_t CTRL6; /*!< (@ 0x000000CC) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA6EN : 1; /*!< [0..0] Counter/Timer A6 Enable bit. */ + __IOM uint32_t TMRA6CLK : 5; /*!< [5..1] Counter/Timer A6 Clock Select. */ + __IOM uint32_t TMRA6FN : 3; /*!< [8..6] Counter/Timer A6 Function Select. */ + __IOM uint32_t TMRA6IE0 : 1; /*!< [9..9] Counter/Timer A6 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA6IE1 : 1; /*!< [10..10] Counter/Timer A6 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA6CLR : 1; /*!< [11..11] Counter/Timer A6 Clear bit. */ + __IOM uint32_t TMRA6POL : 1; /*!< [12..12] Counter/Timer A6 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB6EN : 1; /*!< [16..16] Counter/Timer B6 Enable bit. */ + __IOM uint32_t TMRB6CLK : 5; /*!< [21..17] Counter/Timer B6 Clock Select. */ + __IOM uint32_t TMRB6FN : 3; /*!< [24..22] Counter/Timer B6 Function Select. */ + __IOM uint32_t TMRB6IE0 : 1; /*!< [25..25] Counter/Timer B6 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB6IE1 : 1; /*!< [26..26] Counter/Timer B6 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB6CLR : 1; /*!< [27..27] Counter/Timer B6 Clear bit. */ + __IOM uint32_t TMRB6POL : 1; /*!< [28..28] Counter/Timer B6 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK6 : 1; /*!< [31..31] Counter/Timer A6/B6 Link bit. */ + } CTRL6_b; + } ; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t CMPRAUXA6; /*!< (@ 0x000000D4) Counter/Timer A6 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA6_b; + } ; + + union { + __IOM uint32_t CMPRAUXB6; /*!< (@ 0x000000D8) Counter/Timer B6 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB6_b; + } ; + + union { + __IOM uint32_t AUX6; /*!< (@ 0x000000DC) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA6LMT : 7; /*!< [6..0] Counter/Timer A6 Pattern Limit Count. */ + __IOM uint32_t TMRA6TRIG : 4; /*!< [10..7] Counter/Timer A6 Trigger Select. */ + __IOM uint32_t TMRA6NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA6TINV : 1; /*!< [12..12] Counter/Timer A6 Invert on trigger. */ + __IOM uint32_t TMRA6POL23 : 1; /*!< [13..13] Counter/Timer A6 Upper output polarity */ + __IOM uint32_t TMRA6EN23 : 1; /*!< [14..14] Counter/Timer A6 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB6LMT : 6; /*!< [21..16] Counter/Timer B6 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB6TRIG : 4; /*!< [26..23] Counter/Timer B6 Trigger Select. */ + __IOM uint32_t TMRB6NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB6TINV : 1; /*!< [28..28] Counter/Timer B6 Invert on trigger. */ + __IOM uint32_t TMRB6POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB6EN23 : 1; /*!< [30..30] Counter/Timer B6 Upper compare enable. */ + } AUX6_b; + } ; + + union { + __IOM uint32_t TMR7; /*!< (@ 0x000000E0) Counter/Timer Register */ + + struct { + __IOM uint32_t CTTMRA7 : 16; /*!< [15..0] Counter/Timer A7. */ + __IOM uint32_t CTTMRB7 : 16; /*!< [31..16] Counter/Timer B7. */ + } TMR7_b; + } ; + + union { + __IOM uint32_t CMPRA7; /*!< (@ 0x000000E4) Counter/Timer A7 Compare Registers */ + + struct { + __IOM uint32_t CMPR0A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 0. */ + __IOM uint32_t CMPR1A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 1. */ + } CMPRA7_b; + } ; + + union { + __IOM uint32_t CMPRB7; /*!< (@ 0x000000E8) Counter/Timer B7 Compare Registers */ + + struct { + __IOM uint32_t CMPR0B7 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */ + __IOM uint32_t CMPR1B7 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */ + } CMPRB7_b; + } ; + + union { + __IOM uint32_t CTRL7; /*!< (@ 0x000000EC) Counter/Timer Control */ + + struct { + __IOM uint32_t TMRA7EN : 1; /*!< [0..0] Counter/Timer A7 Enable bit. */ + __IOM uint32_t TMRA7CLK : 5; /*!< [5..1] Counter/Timer A7 Clock Select. */ + __IOM uint32_t TMRA7FN : 3; /*!< [8..6] Counter/Timer A7 Function Select. */ + __IOM uint32_t TMRA7IE0 : 1; /*!< [9..9] Counter/Timer A7 Interrupt Enable bit based on COMPR0. */ + __IOM uint32_t TMRA7IE1 : 1; /*!< [10..10] Counter/Timer A7 Interrupt Enable bit based on COMPR1. */ + __IOM uint32_t TMRA7CLR : 1; /*!< [11..11] Counter/Timer A7 Clear bit. */ + __IOM uint32_t TMRA7POL : 1; /*!< [12..12] Counter/Timer A7 output polarity. */ + uint32_t : 3; + __IOM uint32_t TMRB7EN : 1; /*!< [16..16] Counter/Timer B7 Enable bit. */ + __IOM uint32_t TMRB7CLK : 5; /*!< [21..17] Counter/Timer B7 Clock Select. */ + __IOM uint32_t TMRB7FN : 3; /*!< [24..22] Counter/Timer B7 Function Select. */ + __IOM uint32_t TMRB7IE0 : 1; /*!< [25..25] Counter/Timer B7 Interrupt Enable bit for COMPR0. */ + __IOM uint32_t TMRB7IE1 : 1; /*!< [26..26] Counter/Timer B7 Interrupt Enable bit for COMPR1. */ + __IOM uint32_t TMRB7CLR : 1; /*!< [27..27] Counter/Timer B7 Clear bit. */ + __IOM uint32_t TMRB7POL : 1; /*!< [28..28] Counter/Timer B7 output polarity. */ + uint32_t : 2; + __IOM uint32_t CTLINK7 : 1; /*!< [31..31] Counter/Timer A7/B7 Link bit. */ + } CTRL7_b; + } ; + __IM uint32_t RESERVED7; + + union { + __IOM uint32_t CMPRAUXA7; /*!< (@ 0x000000F4) Counter/Timer A7 Compare Registers */ + + struct { + __IOM uint32_t CMPR2A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 2. Holds the lower + limit for timer half A. */ + __IOM uint32_t CMPR3A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 3. Holds the upper + limit for timer half A. */ + } CMPRAUXA7_b; + } ; + + union { + __IOM uint32_t CMPRAUXB7; /*!< (@ 0x000000F8) Counter/Timer B7 Compare Registers */ + + struct { + __IOM uint32_t CMPR2B7 : 16; /*!< [15..0] Counter/Timer B7 Compare Register 2. Holds the lower + limit for timer half B. */ + __IOM uint32_t CMPR3B7 : 16; /*!< [31..16] Counter/Timer B7 Compare Register 3. Holds the upper + limit for timer half B. */ + } CMPRAUXB7_b; + } ; + + union { + __IOM uint32_t AUX7; /*!< (@ 0x000000FC) Counter/Timer Auxiliary */ + + struct { + __IOM uint32_t TMRA7LMT : 7; /*!< [6..0] Counter/Timer A7 Pattern Limit Count. */ + __IOM uint32_t TMRA7TRIG : 4; /*!< [10..7] Counter/Timer A7 Trigger Select. */ + __IOM uint32_t TMRA7NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ + __IOM uint32_t TMRA7TINV : 1; /*!< [12..12] Counter/Timer A7 Invert on trigger. */ + __IOM uint32_t TMRA7POL23 : 1; /*!< [13..13] Counter/Timer A7 Upper output polarity */ + __IOM uint32_t TMRA7EN23 : 1; /*!< [14..14] Counter/Timer A7 Upper compare enable. */ + uint32_t : 1; + __IOM uint32_t TMRB7LMT : 6; /*!< [21..16] Counter/Timer B7 Pattern Limit Count. */ + uint32_t : 1; + __IOM uint32_t TMRB7TRIG : 4; /*!< [26..23] Counter/Timer B7 Trigger Select. */ + __IOM uint32_t TMRB7NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ + __IOM uint32_t TMRB7TINV : 1; /*!< [28..28] Counter/Timer B7 Invert on trigger. */ + __IOM uint32_t TMRB7POL23 : 1; /*!< [29..29] Upper output polarity */ + __IOM uint32_t TMRB7EN23 : 1; /*!< [30..30] Counter/Timer B7 Upper compare enable. */ + } AUX7_b; + } ; + + union { + __IOM uint32_t GLOBEN; /*!< (@ 0x00000100) Counter/Timer Global Enable */ + + struct { + __IOM uint32_t ENA0 : 1; /*!< [0..0] Alternate enable for A0 */ + __IOM uint32_t ENB0 : 1; /*!< [1..1] Alternate enable for B0 */ + __IOM uint32_t ENA1 : 1; /*!< [2..2] Alternate enable for A1 */ + __IOM uint32_t ENB1 : 1; /*!< [3..3] Alternate enable for B1 */ + __IOM uint32_t ENA2 : 1; /*!< [4..4] Alternate enable for A2 */ + __IOM uint32_t ENB2 : 1; /*!< [5..5] Alternate enable for B2 */ + __IOM uint32_t ENA3 : 1; /*!< [6..6] Alternate enable for A3 */ + __IOM uint32_t ENB3 : 1; /*!< [7..7] Alternate enable for B3. */ + __IOM uint32_t ENA4 : 1; /*!< [8..8] Alternate enable for A4 */ + __IOM uint32_t ENB4 : 1; /*!< [9..9] Alternate enable for B4 */ + __IOM uint32_t ENA5 : 1; /*!< [10..10] Alternate enable for A5 */ + __IOM uint32_t ENB5 : 1; /*!< [11..11] Alternate enable for B5 */ + __IOM uint32_t ENA6 : 1; /*!< [12..12] Alternate enable for A6 */ + __IOM uint32_t ENB6 : 1; /*!< [13..13] Alternate enable for B6 */ + __IOM uint32_t ENA7 : 1; /*!< [14..14] Alternate enable for A7 */ + __IOM uint32_t ENB7 : 1; /*!< [15..15] Alternate enable for B7. */ + } GLOBEN_b; + } ; + + union { + __IOM uint32_t OUTCFG0; /*!< (@ 0x00000104) Counter/Timer Output Config 0 */ + + struct { + __IOM uint32_t CFG0 : 3; /*!< [2..0] Pad output 0 configuration */ + __IOM uint32_t CFG1 : 3; /*!< [5..3] Pad output 1 configuration */ + __IOM uint32_t CFG2 : 3; /*!< [8..6] Pad output 2 configuration */ + __IOM uint32_t CFG3 : 3; /*!< [11..9] Pad output 3 configuration */ + __IOM uint32_t CFG4 : 3; /*!< [14..12] Pad output 4 configuration */ + uint32_t : 1; + __IOM uint32_t CFG5 : 3; /*!< [18..16] Pad output 5 configuration */ + __IOM uint32_t CFG6 : 3; /*!< [21..19] Pad output 6 configuration */ + __IOM uint32_t CFG7 : 3; /*!< [24..22] Pad output 7 configuration */ + __IOM uint32_t CFG8 : 3; /*!< [27..25] Pad output 8 configuration */ + __IOM uint32_t CFG9 : 3; /*!< [30..28] Pad output 9 configuration */ + } OUTCFG0_b; + } ; + + union { + __IOM uint32_t OUTCFG1; /*!< (@ 0x00000108) Counter/Timer Output Config 1 */ + + struct { + __IOM uint32_t CFG10 : 3; /*!< [2..0] Pad output 10 configuration */ + __IOM uint32_t CFG11 : 3; /*!< [5..3] Pad output 11 configuration */ + __IOM uint32_t CFG12 : 3; /*!< [8..6] Pad output 12 configuration */ + __IOM uint32_t CFG13 : 3; /*!< [11..9] Pad output 13 configuration */ + __IOM uint32_t CFG14 : 3; /*!< [14..12] Pad output 14 configuration */ + uint32_t : 1; + __IOM uint32_t CFG15 : 3; /*!< [18..16] Pad output 15 configuration */ + __IOM uint32_t CFG16 : 3; /*!< [21..19] Pad output 16 configuration */ + __IOM uint32_t CFG17 : 3; /*!< [24..22] Pad output 17 configuration */ + __IOM uint32_t CFG18 : 3; /*!< [27..25] Pad output 18 configuration */ + __IOM uint32_t CFG19 : 3; /*!< [30..28] Pad output 19 configuration */ + } OUTCFG1_b; + } ; + + union { + __IOM uint32_t OUTCFG2; /*!< (@ 0x0000010C) Counter/Timer Output Config 2 */ + + struct { + __IOM uint32_t CFG20 : 3; /*!< [2..0] Pad output 20 configuration */ + __IOM uint32_t CFG21 : 3; /*!< [5..3] Pad output 21 configuration */ + __IOM uint32_t CFG22 : 3; /*!< [8..6] Pad output 22 configuration */ + __IOM uint32_t CFG23 : 3; /*!< [11..9] Pad output 23 configuration */ + __IOM uint32_t CFG24 : 3; /*!< [14..12] Pad output 24 configuration */ + uint32_t : 1; + __IOM uint32_t CFG25 : 3; /*!< [18..16] Pad output 25 configuration */ + __IOM uint32_t CFG26 : 3; /*!< [21..19] Pad output 26 configuration */ + __IOM uint32_t CFG27 : 3; /*!< [24..22] Pad output 27 configuration */ + __IOM uint32_t CFG28 : 3; /*!< [27..25] Pad output 28 configuration */ + __IOM uint32_t CFG29 : 3; /*!< [30..28] Pad output 29 configuration */ + } OUTCFG2_b; + } ; + __IM uint32_t RESERVED8; + + union { + __IOM uint32_t OUTCFG3; /*!< (@ 0x00000114) Counter/Timer Output Config 3 */ + + struct { + __IOM uint32_t CFG30 : 3; /*!< [2..0] Pad output 30 configuration */ + __IOM uint32_t CFG31 : 3; /*!< [5..3] Pad output 31 configuration */ + } OUTCFG3_b; + } ; + + union { + __IOM uint32_t INCFG; /*!< (@ 0x00000118) Counter/Timer Input Config */ + + struct { + __IOM uint32_t CFGA0 : 1; /*!< [0..0] CTIMER A0 input configuration */ + __IOM uint32_t CFGB0 : 1; /*!< [1..1] CTIMER B0 input configuration */ + __IOM uint32_t CFGA1 : 1; /*!< [2..2] CTIMER A1 input configuration */ + __IOM uint32_t CFGB1 : 1; /*!< [3..3] CTIMER B1 input configuration */ + __IOM uint32_t CFGA2 : 1; /*!< [4..4] CTIMER A2 input configuration */ + __IOM uint32_t CFGB2 : 1; /*!< [5..5] CTIMER B2 input configuration */ + __IOM uint32_t CFGA3 : 1; /*!< [6..6] CTIMER A3 input configuration */ + __IOM uint32_t CFGB3 : 1; /*!< [7..7] CTIMER B3 input configuration */ + __IOM uint32_t CFGA4 : 1; /*!< [8..8] CTIMER A4 input configuration */ + __IOM uint32_t CFGB4 : 1; /*!< [9..9] CTIMER B4 input configuration */ + __IOM uint32_t CFGA5 : 1; /*!< [10..10] CTIMER A5 input configuration */ + __IOM uint32_t CFGB5 : 1; /*!< [11..11] CTIMER B5 input configuration */ + __IOM uint32_t CFGA6 : 1; /*!< [12..12] CTIMER A6 input configuration */ + __IOM uint32_t CFGB6 : 1; /*!< [13..13] CTIMER B6 input configuration */ + __IOM uint32_t CFGA7 : 1; /*!< [14..14] CTIMER A7 input configuration */ + __IOM uint32_t CFGB7 : 1; /*!< [15..15] CTIMER B7 input configuration */ + } INCFG_b; + } ; + __IM uint32_t RESERVED9[9]; + + union { + __IOM uint32_t STCFG; /*!< (@ 0x00000140) Configuration Register */ + + struct { + __IOM uint32_t CLKSEL : 4; /*!< [3..0] Selects an appropriate clock source and divider to use + for the System Timer clock. */ + uint32_t : 4; + __IOM uint32_t COMPARE_A_EN : 1; /*!< [8..8] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_B_EN : 1; /*!< [9..9] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_C_EN : 1; /*!< [10..10] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_D_EN : 1; /*!< [11..11] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_E_EN : 1; /*!< [12..12] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_F_EN : 1; /*!< [13..13] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_G_EN : 1; /*!< [14..14] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + __IOM uint32_t COMPARE_H_EN : 1; /*!< [15..15] Selects whether compare is enabled for the corresponding + SCMPR register. If compare is enabled, the interrupt status + is set once the comparision is met. */ + uint32_t : 14; + __IOM uint32_t CLEAR : 1; /*!< [30..30] Set this bit to one to clear the System Timer register. + If this bit is set to '1', the system timer register will + stay cleared. It needs to be set to '0' for the system + timer to start running. */ + __IOM uint32_t FREEZE : 1; /*!< [31..31] Set this bit to one to freeze the clock input to the + COUNTER register. Once frozen, the value can be safely + written from the MCU. Unfreeze to resume. */ + } STCFG_b; + } ; + + union { + __IOM uint32_t STTMR; /*!< (@ 0x00000144) System Timer Count Register (Real Time Counter) */ + + struct { + __IOM uint32_t STTMR : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } STTMR_b; + } ; + + union { + __IOM uint32_t CAPTURECONTROL; /*!< (@ 0x00000148) Capture Control Register */ + + struct { + __IOM uint32_t CAPTURE0 : 1; /*!< [0..0] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE1 : 1; /*!< [1..1] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE2 : 1; /*!< [2..2] Selects whether capture is enabled for the specified + capture register. */ + __IOM uint32_t CAPTURE3 : 1; /*!< [3..3] Selects whether capture is enabled for the specified + capture register. */ + } CAPTURECONTROL_b; + } ; + __IM uint32_t RESERVED10; + + union { + __IOM uint32_t SCMPR0; /*!< (@ 0x00000150) Compare Register A */ + + struct { + __IOM uint32_t SCMPR0 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_A_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR0_b; + } ; + + union { + __IOM uint32_t SCMPR1; /*!< (@ 0x00000154) Compare Register B */ + + struct { + __IOM uint32_t SCMPR1 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_B_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR1_b; + } ; + + union { + __IOM uint32_t SCMPR2; /*!< (@ 0x00000158) Compare Register C */ + + struct { + __IOM uint32_t SCMPR2 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_C_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR2_b; + } ; + + union { + __IOM uint32_t SCMPR3; /*!< (@ 0x0000015C) Compare Register D */ + + struct { + __IOM uint32_t SCMPR3 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_D_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR3_b; + } ; + + union { + __IOM uint32_t SCMPR4; /*!< (@ 0x00000160) Compare Register E */ + + struct { + __IOM uint32_t SCMPR4 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_E_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR4_b; + } ; + + union { + __IOM uint32_t SCMPR5; /*!< (@ 0x00000164) Compare Register F */ + + struct { + __IOM uint32_t SCMPR5 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_F_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR5_b; + } ; + + union { + __IOM uint32_t SCMPR6; /*!< (@ 0x00000168) Compare Register G */ + + struct { + __IOM uint32_t SCMPR6 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_G_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR6_b; + } ; + + union { + __IOM uint32_t SCMPR7; /*!< (@ 0x0000016C) Compare Register H */ + + struct { + __IOM uint32_t SCMPR7 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register + according to the match criterion, as selected in the COMPARE_H_EN + bit in the REG_CTIMER_STCGF register. */ + } SCMPR7_b; + } ; + __IM uint32_t RESERVED11[28]; + + union { + __IOM uint32_t SCAPT0; /*!< (@ 0x000001E0) Capture Register A */ + + struct { + __IOM uint32_t SCAPT0 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT0_b; + } ; + + union { + __IOM uint32_t SCAPT1; /*!< (@ 0x000001E4) Capture Register B */ + + struct { + __IOM uint32_t SCAPT1 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT1_b; + } ; + + union { + __IOM uint32_t SCAPT2; /*!< (@ 0x000001E8) Capture Register C */ + + struct { + __IOM uint32_t SCAPT2 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT2_b; + } ; + + union { + __IOM uint32_t SCAPT3; /*!< (@ 0x000001EC) Capture Register D */ + + struct { + __IOM uint32_t SCAPT3 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER + is copied into this register and the corresponding interrupt + status bit is set. */ + } SCAPT3_b; + } ; + + union { + __IOM uint32_t SNVR0; /*!< (@ 0x000001F0) System Timer NVRAM_A Register */ + + struct { + __IOM uint32_t SNVR0 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR0_b; + } ; + + union { + __IOM uint32_t SNVR1; /*!< (@ 0x000001F4) System Timer NVRAM_B Register */ + + struct { + __IOM uint32_t SNVR1 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR1_b; + } ; + + union { + __IOM uint32_t SNVR2; /*!< (@ 0x000001F8) System Timer NVRAM_C Register */ + + struct { + __IOM uint32_t SNVR2 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR2_b; + } ; + + union { + __IOM uint32_t SNVR3; /*!< (@ 0x000001FC) System Timer NVRAM_D Register */ + + struct { + __IOM uint32_t SNVR3 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ + } SNVR3_b; + } ; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Counter/Timer Interrupts: Enable */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Counter/Timer Interrupts: Status */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Counter/Timer Interrupts: Clear */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Counter/Timer Interrupts: Set */ + + struct { + __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ + __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ + __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ + __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ + } INTSET_b; + } ; + __IM uint32_t RESERVED12[60]; + + union { + __IOM uint32_t STMINTEN; /*!< (@ 0x00000300) STIMER Interrupt registers: Enable */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTEN_b; + } ; + + union { + __IOM uint32_t STMINTSTAT; /*!< (@ 0x00000304) STIMER Interrupt registers: Status */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTSTAT_b; + } ; + + union { + __IOM uint32_t STMINTCLR; /*!< (@ 0x00000308) STIMER Interrupt registers: Clear */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTCLR_b; + } ; + + union { + __IOM uint32_t STMINTSET; /*!< (@ 0x0000030C) STIMER Interrupt registers: Set */ + + struct { + __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register + A. */ + __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register + B. */ + __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register + C. */ + __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register + D. */ + __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register + E. */ + __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register + F. */ + __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register + G. */ + __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register + H. */ + __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ + __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ + __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ + __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ + __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ + } STMINTSET_b; + } ; +} CTIMER_Type; /*!< Size = 784 (0x310) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose IO (GPIO) + */ + +typedef struct { /*!< (@ 0x40010000) GPIO Structure */ + + union { + __IOM uint32_t PADREGA; /*!< (@ 0x00000000) Pad Configuration Register A (Pads 3-0) */ + + struct { + __IOM uint32_t PAD0PULL : 1; /*!< [0..0] Pad 0 pullup enable */ + __IOM uint32_t PAD0INPEN : 1; /*!< [1..1] Pad 0 input enable */ + __IOM uint32_t PAD0STRNG : 1; /*!< [2..2] Pad 0 drive strength */ + __IOM uint32_t PAD0FNCSEL : 3; /*!< [5..3] Pad 0 function select */ + __IOM uint32_t PAD0RSEL : 2; /*!< [7..6] Pad 0 pullup resistor selection. */ + __IOM uint32_t PAD1PULL : 1; /*!< [8..8] Pad 1 pullup enable */ + __IOM uint32_t PAD1INPEN : 1; /*!< [9..9] Pad 1 input enable */ + __IOM uint32_t PAD1STRNG : 1; /*!< [10..10] Pad 1 drive strength */ + __IOM uint32_t PAD1FNCSEL : 3; /*!< [13..11] Pad 1 function select */ + __IOM uint32_t PAD1RSEL : 2; /*!< [15..14] Pad 1 pullup resistor selection. */ + __IOM uint32_t PAD2PULL : 1; /*!< [16..16] Pad 2 pullup enable */ + __IOM uint32_t PAD2INPEN : 1; /*!< [17..17] Pad 2 input enable */ + __IOM uint32_t PAD2STRNG : 1; /*!< [18..18] Pad 2 drive strength */ + __IOM uint32_t PAD2FNCSEL : 3; /*!< [21..19] Pad 2 function select */ + uint32_t : 2; + __IOM uint32_t PAD3PULL : 1; /*!< [24..24] Pad 3 pullup enable */ + __IOM uint32_t PAD3INPEN : 1; /*!< [25..25] Pad 3 input enable. */ + __IOM uint32_t PAD3STRNG : 1; /*!< [26..26] Pad 3 drive strength. */ + __IOM uint32_t PAD3FNCSEL : 3; /*!< [29..27] Pad 3 function select */ + __IOM uint32_t PAD3PWRUP : 1; /*!< [30..30] Pad 3 VDD power switch enable */ + } PADREGA_b; + } ; + + union { + __IOM uint32_t PADREGB; /*!< (@ 0x00000004) Pad Configuration Register B (Pads 7-4) */ + + struct { + __IOM uint32_t PAD4PULL : 1; /*!< [0..0] Pad 4 pullup enable */ + __IOM uint32_t PAD4INPEN : 1; /*!< [1..1] Pad 4 input enable */ + __IOM uint32_t PAD4STRNG : 1; /*!< [2..2] Pad 4 drive strength */ + __IOM uint32_t PAD4FNCSEL : 3; /*!< [5..3] Pad 4 function select */ + uint32_t : 2; + __IOM uint32_t PAD5PULL : 1; /*!< [8..8] Pad 5 pullup enable */ + __IOM uint32_t PAD5INPEN : 1; /*!< [9..9] Pad 5 input enable */ + __IOM uint32_t PAD5STRNG : 1; /*!< [10..10] Pad 5 drive strength */ + __IOM uint32_t PAD5FNCSEL : 3; /*!< [13..11] Pad 5 function select */ + __IOM uint32_t PAD5RSEL : 2; /*!< [15..14] Pad 5 pullup resistor selection. */ + __IOM uint32_t PAD6PULL : 1; /*!< [16..16] Pad 6 pullup enable */ + __IOM uint32_t PAD6INPEN : 1; /*!< [17..17] Pad 6 input enable */ + __IOM uint32_t PAD6STRNG : 1; /*!< [18..18] Pad 6 drive strength */ + __IOM uint32_t PAD6FNCSEL : 3; /*!< [21..19] Pad 6 function select */ + __IOM uint32_t PAD6RSEL : 2; /*!< [23..22] Pad 6 pullup resistor selection. */ + __IOM uint32_t PAD7PULL : 1; /*!< [24..24] Pad 7 pullup enable */ + __IOM uint32_t PAD7INPEN : 1; /*!< [25..25] Pad 7 input enable */ + __IOM uint32_t PAD7STRNG : 1; /*!< [26..26] Pad 7 drive strength */ + __IOM uint32_t PAD7FNCSEL : 3; /*!< [29..27] Pad 7 function select */ + } PADREGB_b; + } ; + + union { + __IOM uint32_t PADREGC; /*!< (@ 0x00000008) Pad Configuration Register C (Pads 11-8) */ + + struct { + __IOM uint32_t PAD8PULL : 1; /*!< [0..0] Pad 8 pullup enable */ + __IOM uint32_t PAD8INPEN : 1; /*!< [1..1] Pad 8 input enable */ + __IOM uint32_t PAD8STRNG : 1; /*!< [2..2] Pad 8 drive strength */ + __IOM uint32_t PAD8FNCSEL : 3; /*!< [5..3] Pad 8 function select */ + __IOM uint32_t PAD8RSEL : 2; /*!< [7..6] Pad 8 pullup resistor selection. */ + __IOM uint32_t PAD9PULL : 1; /*!< [8..8] Pad 9 pullup enable */ + __IOM uint32_t PAD9INPEN : 1; /*!< [9..9] Pad 9 input enable */ + __IOM uint32_t PAD9STRNG : 1; /*!< [10..10] Pad 9 drive strength */ + __IOM uint32_t PAD9FNCSEL : 3; /*!< [13..11] Pad 9 function select */ + __IOM uint32_t PAD9RSEL : 2; /*!< [15..14] Pad 9 pullup resistor selection */ + __IOM uint32_t PAD10PULL : 1; /*!< [16..16] Pad 10 pullup enable */ + __IOM uint32_t PAD10INPEN : 1; /*!< [17..17] Pad 10 input enable */ + __IOM uint32_t PAD10STRNG : 1; /*!< [18..18] Pad 10 drive strength */ + __IOM uint32_t PAD10FNCSEL : 3; /*!< [21..19] Pad 10 function select */ + uint32_t : 2; + __IOM uint32_t PAD11PULL : 1; /*!< [24..24] Pad 11 pullup enable */ + __IOM uint32_t PAD11INPEN : 1; /*!< [25..25] Pad 11 input enable */ + __IOM uint32_t PAD11STRNG : 1; /*!< [26..26] Pad 11 drive strength */ + __IOM uint32_t PAD11FNCSEL : 3; /*!< [29..27] Pad 11 function select */ + } PADREGC_b; + } ; + + union { + __IOM uint32_t PADREGD; /*!< (@ 0x0000000C) Pad Configuration Register D (Pads 15-12) */ + + struct { + __IOM uint32_t PAD12PULL : 1; /*!< [0..0] Pad 12 pullup enable */ + __IOM uint32_t PAD12INPEN : 1; /*!< [1..1] Pad 12 input enable */ + __IOM uint32_t PAD12STRNG : 1; /*!< [2..2] Pad 12 drive strength */ + __IOM uint32_t PAD12FNCSEL : 3; /*!< [5..3] Pad 12 function select */ + uint32_t : 2; + __IOM uint32_t PAD13PULL : 1; /*!< [8..8] Pad 13 pullup enable */ + __IOM uint32_t PAD13INPEN : 1; /*!< [9..9] Pad 13 input enable */ + __IOM uint32_t PAD13STRNG : 1; /*!< [10..10] Pad 13 drive strength */ + __IOM uint32_t PAD13FNCSEL : 3; /*!< [13..11] Pad 13 function select */ + uint32_t : 2; + __IOM uint32_t PAD14PULL : 1; /*!< [16..16] Pad 14 pullup enable */ + __IOM uint32_t PAD14INPEN : 1; /*!< [17..17] Pad 14 input enable */ + __IOM uint32_t PAD14STRNG : 1; /*!< [18..18] Pad 14 drive strength */ + __IOM uint32_t PAD14FNCSEL : 3; /*!< [21..19] Pad 14 function select */ + uint32_t : 2; + __IOM uint32_t PAD15PULL : 1; /*!< [24..24] Pad 15 pullup enable */ + __IOM uint32_t PAD15INPEN : 1; /*!< [25..25] Pad 15 input enable */ + __IOM uint32_t PAD15STRNG : 1; /*!< [26..26] Pad 15 drive strength */ + __IOM uint32_t PAD15FNCSEL : 3; /*!< [29..27] Pad 15 function select */ + } PADREGD_b; + } ; + + union { + __IOM uint32_t PADREGE; /*!< (@ 0x00000010) Pad Configuration Register E (Pads 19-16) */ + + struct { + __IOM uint32_t PAD16PULL : 1; /*!< [0..0] Pad 16 pullup enable */ + __IOM uint32_t PAD16INPEN : 1; /*!< [1..1] Pad 16 input enable */ + __IOM uint32_t PAD16STRNG : 1; /*!< [2..2] Pad 16 drive strength */ + __IOM uint32_t PAD16FNCSEL : 3; /*!< [5..3] Pad 16 function select */ + uint32_t : 2; + __IOM uint32_t PAD17PULL : 1; /*!< [8..8] Pad 17 pullup enable */ + __IOM uint32_t PAD17INPEN : 1; /*!< [9..9] Pad 17 input enable */ + __IOM uint32_t PAD17STRNG : 1; /*!< [10..10] Pad 17 drive strength */ + __IOM uint32_t PAD17FNCSEL : 3; /*!< [13..11] Pad 17 function select */ + uint32_t : 2; + __IOM uint32_t PAD18PULL : 1; /*!< [16..16] Pad 18 pullup enable */ + __IOM uint32_t PAD18INPEN : 1; /*!< [17..17] Pad 18 input enable */ + __IOM uint32_t PAD18STRNG : 1; /*!< [18..18] Pad 18 drive strength */ + __IOM uint32_t PAD18FNCSEL : 3; /*!< [21..19] Pad 18 function select */ + uint32_t : 2; + __IOM uint32_t PAD19PULL : 1; /*!< [24..24] Pad 19 pullup enable */ + __IOM uint32_t PAD19INPEN : 1; /*!< [25..25] Pad 19 input enable */ + __IOM uint32_t PAD19STRNG : 1; /*!< [26..26] Pad 19 drive strength */ + __IOM uint32_t PAD19FNCSEL : 3; /*!< [29..27] Pad 19 function select */ + } PADREGE_b; + } ; + + union { + __IOM uint32_t PADREGF; /*!< (@ 0x00000014) Pad Configuration Register F (Pads 23-20) */ + + struct { + __IOM uint32_t PAD20PULL : 1; /*!< [0..0] Pad 20 pulldown enable */ + __IOM uint32_t PAD20INPEN : 1; /*!< [1..1] Pad 20 input enable */ + __IOM uint32_t PAD20STRNG : 1; /*!< [2..2] Pad 20 drive strength */ + __IOM uint32_t PAD20FNCSEL : 3; /*!< [5..3] Pad 20 function select */ + uint32_t : 2; + __IOM uint32_t PAD21PULL : 1; /*!< [8..8] Pad 21 pullup enable */ + __IOM uint32_t PAD21INPEN : 1; /*!< [9..9] Pad 21 input enable */ + __IOM uint32_t PAD21STRNG : 1; /*!< [10..10] Pad 21 drive strength */ + __IOM uint32_t PAD21FNCSEL : 3; /*!< [13..11] Pad 21 function select */ + uint32_t : 2; + __IOM uint32_t PAD22PULL : 1; /*!< [16..16] Pad 22 pullup enable */ + __IOM uint32_t PAD22INPEN : 1; /*!< [17..17] Pad 22 input enable */ + __IOM uint32_t PAD22STRNG : 1; /*!< [18..18] Pad 22 drive strength */ + __IOM uint32_t PAD22FNCSEL : 3; /*!< [21..19] Pad 22 function select */ + uint32_t : 2; + __IOM uint32_t PAD23PULL : 1; /*!< [24..24] Pad 23 pullup enable */ + __IOM uint32_t PAD23INPEN : 1; /*!< [25..25] Pad 23 input enable */ + __IOM uint32_t PAD23STRNG : 1; /*!< [26..26] Pad 23 drive strength */ + __IOM uint32_t PAD23FNCSEL : 3; /*!< [29..27] Pad 23 function select */ + } PADREGF_b; + } ; + + union { + __IOM uint32_t PADREGG; /*!< (@ 0x00000018) Pad Configuration Register G (Pads 27-24) */ + + struct { + __IOM uint32_t PAD24PULL : 1; /*!< [0..0] Pad 24 pullup enable */ + __IOM uint32_t PAD24INPEN : 1; /*!< [1..1] Pad 24 input enable */ + __IOM uint32_t PAD24STRNG : 1; /*!< [2..2] Pad 24 drive strength */ + __IOM uint32_t PAD24FNCSEL : 3; /*!< [5..3] Pad 24 function select */ + uint32_t : 2; + __IOM uint32_t PAD25PULL : 1; /*!< [8..8] Pad 25 pullup enable */ + __IOM uint32_t PAD25INPEN : 1; /*!< [9..9] Pad 25 input enable */ + __IOM uint32_t PAD25STRNG : 1; /*!< [10..10] Pad 25 drive strength */ + __IOM uint32_t PAD25FNCSEL : 3; /*!< [13..11] Pad 25 function select */ + __IOM uint32_t PAD25RSEL : 2; /*!< [15..14] Pad 25 pullup resistor selection. */ + __IOM uint32_t PAD26PULL : 1; /*!< [16..16] Pad 26 pullup enable */ + __IOM uint32_t PAD26INPEN : 1; /*!< [17..17] Pad 26 input enable */ + __IOM uint32_t PAD26STRNG : 1; /*!< [18..18] Pad 26 drive strength */ + __IOM uint32_t PAD26FNCSEL : 3; /*!< [21..19] Pad 26 function select */ + uint32_t : 2; + __IOM uint32_t PAD27PULL : 1; /*!< [24..24] Pad 27 pullup enable */ + __IOM uint32_t PAD27INPEN : 1; /*!< [25..25] Pad 27 input enable */ + __IOM uint32_t PAD27STRNG : 1; /*!< [26..26] Pad 27 drive strength */ + __IOM uint32_t PAD27FNCSEL : 3; /*!< [29..27] Pad 27 function select */ + __IOM uint32_t PAD27RSEL : 2; /*!< [31..30] Pad 27 pullup resistor selection. */ + } PADREGG_b; + } ; + + union { + __IOM uint32_t PADREGH; /*!< (@ 0x0000001C) Pad Configuration Register H (Pads 31-28) */ + + struct { + __IOM uint32_t PAD28PULL : 1; /*!< [0..0] Pad 28 pullup enable */ + __IOM uint32_t PAD28INPEN : 1; /*!< [1..1] Pad 28 input enable */ + __IOM uint32_t PAD28STRNG : 1; /*!< [2..2] Pad 28 drive strength */ + __IOM uint32_t PAD28FNCSEL : 3; /*!< [5..3] Pad 28 function select */ + uint32_t : 2; + __IOM uint32_t PAD29PULL : 1; /*!< [8..8] Pad 29 pullup enable */ + __IOM uint32_t PAD29INPEN : 1; /*!< [9..9] Pad 29 input enable */ + __IOM uint32_t PAD29STRNG : 1; /*!< [10..10] Pad 29 drive strength */ + __IOM uint32_t PAD29FNCSEL : 3; /*!< [13..11] Pad 29 function select */ + uint32_t : 2; + __IOM uint32_t PAD30PULL : 1; /*!< [16..16] Pad 30 pullup enable */ + __IOM uint32_t PAD30INPEN : 1; /*!< [17..17] Pad 30 input enable */ + __IOM uint32_t PAD30STRNG : 1; /*!< [18..18] Pad 30 drive strength */ + __IOM uint32_t PAD30FNCSEL : 3; /*!< [21..19] Pad 30 function select */ + uint32_t : 2; + __IOM uint32_t PAD31PULL : 1; /*!< [24..24] Pad 31 pullup enable */ + __IOM uint32_t PAD31INPEN : 1; /*!< [25..25] Pad 31 input enable */ + __IOM uint32_t PAD31STRNG : 1; /*!< [26..26] Pad 31 drive strength */ + __IOM uint32_t PAD31FNCSEL : 3; /*!< [29..27] Pad 31 function select */ + } PADREGH_b; + } ; + + union { + __IOM uint32_t PADREGI; /*!< (@ 0x00000020) Pad Configuration Register I (Pads 35-32) */ + + struct { + __IOM uint32_t PAD32PULL : 1; /*!< [0..0] Pad 32 pullup enable */ + __IOM uint32_t PAD32INPEN : 1; /*!< [1..1] Pad 32 input enable */ + __IOM uint32_t PAD32STRNG : 1; /*!< [2..2] Pad 32 drive strength */ + __IOM uint32_t PAD32FNCSEL : 3; /*!< [5..3] Pad 32 function select */ + uint32_t : 2; + __IOM uint32_t PAD33PULL : 1; /*!< [8..8] Pad 33 pullup enable */ + __IOM uint32_t PAD33INPEN : 1; /*!< [9..9] Pad 33 input enable */ + __IOM uint32_t PAD33STRNG : 1; /*!< [10..10] Pad 33 drive strength */ + __IOM uint32_t PAD33FNCSEL : 3; /*!< [13..11] Pad 33 function select */ + uint32_t : 2; + __IOM uint32_t PAD34PULL : 1; /*!< [16..16] Pad 34 pullup enable */ + __IOM uint32_t PAD34INPEN : 1; /*!< [17..17] Pad 34 input enable */ + __IOM uint32_t PAD34STRNG : 1; /*!< [18..18] Pad 34 drive strength */ + __IOM uint32_t PAD34FNCSEL : 3; /*!< [21..19] Pad 34 function select */ + uint32_t : 2; + __IOM uint32_t PAD35PULL : 1; /*!< [24..24] Pad 35 pullup enable */ + __IOM uint32_t PAD35INPEN : 1; /*!< [25..25] Pad 35 input enable */ + __IOM uint32_t PAD35STRNG : 1; /*!< [26..26] Pad 35 drive strength */ + __IOM uint32_t PAD35FNCSEL : 3; /*!< [29..27] Pad 35 function select */ + } PADREGI_b; + } ; + + union { + __IOM uint32_t PADREGJ; /*!< (@ 0x00000024) Pad Configuration Register J (Pads 39-36) */ + + struct { + __IOM uint32_t PAD36PULL : 1; /*!< [0..0] Pad 36 pullup enable */ + __IOM uint32_t PAD36INPEN : 1; /*!< [1..1] Pad 36 input enable */ + __IOM uint32_t PAD36STRNG : 1; /*!< [2..2] Pad 36 drive strength */ + __IOM uint32_t PAD36FNCSEL : 3; /*!< [5..3] Pad 36 function select */ + __IOM uint32_t PAD36PWRUP : 1; /*!< [6..6] Pad 36 VDD power switch enable */ + uint32_t : 1; + __IOM uint32_t PAD37PULL : 1; /*!< [8..8] Pad 37 pullup enable */ + __IOM uint32_t PAD37INPEN : 1; /*!< [9..9] Pad 37 input enable */ + __IOM uint32_t PAD37STRNG : 1; /*!< [10..10] Pad 37 drive strength */ + __IOM uint32_t PAD37FNCSEL : 3; /*!< [13..11] Pad 37 function select */ + uint32_t : 1; + __IOM uint32_t PAD37PWRDN : 1; /*!< [15..15] Pad 37 VSS power switch enable */ + __IOM uint32_t PAD38PULL : 1; /*!< [16..16] Pad 38 pullup enable */ + __IOM uint32_t PAD38INPEN : 1; /*!< [17..17] Pad 38 input enable */ + __IOM uint32_t PAD38STRNG : 1; /*!< [18..18] Pad 38 drive strength */ + __IOM uint32_t PAD38FNCSEL : 3; /*!< [21..19] Pad 38 function select */ + uint32_t : 2; + __IOM uint32_t PAD39PULL : 1; /*!< [24..24] Pad 39 pullup enable */ + __IOM uint32_t PAD39INPEN : 1; /*!< [25..25] Pad 39 input enable */ + __IOM uint32_t PAD39STRNG : 1; /*!< [26..26] Pad 39 drive strength */ + __IOM uint32_t PAD39FNCSEL : 3; /*!< [29..27] Pad 39 function select */ + __IOM uint32_t PAD39RSEL : 2; /*!< [31..30] Pad 39 pullup resistor selection. */ + } PADREGJ_b; + } ; + + union { + __IOM uint32_t PADREGK; /*!< (@ 0x00000028) Pad Configuration Register K (Pads 43-40) */ + + struct { + __IOM uint32_t PAD40PULL : 1; /*!< [0..0] Pad 40 pullup enable */ + __IOM uint32_t PAD40INPEN : 1; /*!< [1..1] Pad 40 input enable */ + __IOM uint32_t PAD40STRNG : 1; /*!< [2..2] Pad 40 drive strength */ + __IOM uint32_t PAD40FNCSEL : 3; /*!< [5..3] Pad 40 function select */ + __IOM uint32_t PAD40RSEL : 2; /*!< [7..6] Pad 40 pullup resistor selection. */ + __IOM uint32_t PAD41PULL : 1; /*!< [8..8] Pad 41 pullup enable */ + __IOM uint32_t PAD41INPEN : 1; /*!< [9..9] Pad 41 input enable */ + __IOM uint32_t PAD41STRNG : 1; /*!< [10..10] Pad 41 drive strength */ + __IOM uint32_t PAD41FNCSEL : 3; /*!< [13..11] Pad 41 function select */ + uint32_t : 1; + __IOM uint32_t PAD41PWRDN : 1; /*!< [15..15] Pad 41 power switch enable */ + __IOM uint32_t PAD42PULL : 1; /*!< [16..16] Pad 42 pullup enable */ + __IOM uint32_t PAD42INPEN : 1; /*!< [17..17] Pad 42 input enable */ + __IOM uint32_t PAD42STRNG : 1; /*!< [18..18] Pad 42 drive strength */ + __IOM uint32_t PAD42FNCSEL : 3; /*!< [21..19] Pad 42 function select */ + __IOM uint32_t PAD42RSEL : 2; /*!< [23..22] Pad 42 pullup resistor selection. */ + __IOM uint32_t PAD43PULL : 1; /*!< [24..24] Pad 43 pullup enable */ + __IOM uint32_t PAD43INPEN : 1; /*!< [25..25] Pad 43 input enable */ + __IOM uint32_t PAD43STRNG : 1; /*!< [26..26] Pad 43 drive strength */ + __IOM uint32_t PAD43FNCSEL : 3; /*!< [29..27] Pad 43 function select */ + __IOM uint32_t PAD43RSEL : 2; /*!< [31..30] Pad 43 pullup resistor selection. */ + } PADREGK_b; + } ; + + union { + __IOM uint32_t PADREGL; /*!< (@ 0x0000002C) Pad Configuration Register L (Pads 47-44) */ + + struct { + __IOM uint32_t PAD44PULL : 1; /*!< [0..0] Pad 44 pullup enable */ + __IOM uint32_t PAD44INPEN : 1; /*!< [1..1] Pad 44 input enable */ + __IOM uint32_t PAD44STRNG : 1; /*!< [2..2] Pad 44 drive strength */ + __IOM uint32_t PAD44FNCSEL : 3; /*!< [5..3] Pad 44 function select */ + uint32_t : 2; + __IOM uint32_t PAD45PULL : 1; /*!< [8..8] Pad 45 pullup enable */ + __IOM uint32_t PAD45INPEN : 1; /*!< [9..9] Pad 45 input enable */ + __IOM uint32_t PAD45STRNG : 1; /*!< [10..10] Pad 45 drive strength */ + __IOM uint32_t PAD45FNCSEL : 3; /*!< [13..11] Pad 45 function select */ + uint32_t : 2; + __IOM uint32_t PAD46PULL : 1; /*!< [16..16] Pad 46 pullup enable */ + __IOM uint32_t PAD46INPEN : 1; /*!< [17..17] Pad 46 input enable */ + __IOM uint32_t PAD46STRNG : 1; /*!< [18..18] Pad 46 drive strength */ + __IOM uint32_t PAD46FNCSEL : 3; /*!< [21..19] Pad 46 function select */ + uint32_t : 2; + __IOM uint32_t PAD47PULL : 1; /*!< [24..24] Pad 47 pullup enable */ + __IOM uint32_t PAD47INPEN : 1; /*!< [25..25] Pad 47 input enable */ + __IOM uint32_t PAD47STRNG : 1; /*!< [26..26] Pad 47 drive strength */ + __IOM uint32_t PAD47FNCSEL : 3; /*!< [29..27] Pad 47 function select */ + } PADREGL_b; + } ; + + union { + __IOM uint32_t PADREGM; /*!< (@ 0x00000030) Pad Configuration Register M (Pads 49-48) */ + + struct { + __IOM uint32_t PAD48PULL : 1; /*!< [0..0] Pad 48 pullup enable */ + __IOM uint32_t PAD48INPEN : 1; /*!< [1..1] Pad 48 input enable */ + __IOM uint32_t PAD48STRNG : 1; /*!< [2..2] Pad 48 drive strength */ + __IOM uint32_t PAD48FNCSEL : 3; /*!< [5..3] Pad 48 function select */ + __IOM uint32_t PAD48RSEL : 2; /*!< [7..6] Pad 48 pullup resistor selection. */ + __IOM uint32_t PAD49PULL : 1; /*!< [8..8] Pad 49 pullup enable */ + __IOM uint32_t PAD49INPEN : 1; /*!< [9..9] Pad 49 input enable */ + __IOM uint32_t PAD49STRNG : 1; /*!< [10..10] Pad 49 drive strength */ + __IOM uint32_t PAD49FNCSEL : 3; /*!< [13..11] Pad 49 function select */ + __IOM uint32_t PAD49RSEL : 2; /*!< [15..14] Pad 49 pullup resistor selection. */ + } PADREGM_b; + } ; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t CFGA; /*!< (@ 0x00000040) GPIO Configuration Register A (Pads 7-0) */ + + struct { + __IOM uint32_t GPIO0INCFG : 1; /*!< [0..0] GPIO0 input enable. */ + __IOM uint32_t GPIO0OUTCFG : 2; /*!< [2..1] GPIO0 output configuration. */ + __IOM uint32_t GPIO0INTD : 1; /*!< [3..3] GPIO0 interrupt direction. */ + __IOM uint32_t GPIO1INCFG : 1; /*!< [4..4] GPIO1 input enable. */ + __IOM uint32_t GPIO1OUTCFG : 2; /*!< [6..5] GPIO1 output configuration. */ + __IOM uint32_t GPIO1INTD : 1; /*!< [7..7] GPIO1 interrupt direction. */ + __IOM uint32_t GPIO2INCFG : 1; /*!< [8..8] GPIO2 input enable. */ + __IOM uint32_t GPIO2OUTCFG : 2; /*!< [10..9] GPIO2 output configuration. */ + __IOM uint32_t GPIO2INTD : 1; /*!< [11..11] GPIO2 interrupt direction. */ + __IOM uint32_t GPIO3INCFG : 1; /*!< [12..12] GPIO3 input enable. */ + __IOM uint32_t GPIO3OUTCFG : 2; /*!< [14..13] GPIO3 output configuration. */ + __IOM uint32_t GPIO3INTD : 1; /*!< [15..15] GPIO3 interrupt direction. */ + __IOM uint32_t GPIO4INCFG : 1; /*!< [16..16] GPIO4 input enable. */ + __IOM uint32_t GPIO4OUTCFG : 2; /*!< [18..17] GPIO4 output configuration. */ + __IOM uint32_t GPIO4INTD : 1; /*!< [19..19] GPIO4 interrupt direction. */ + __IOM uint32_t GPIO5INCFG : 1; /*!< [20..20] GPIO5 input enable. */ + __IOM uint32_t GPIO5OUTCFG : 2; /*!< [22..21] GPIO5 output configuration. */ + __IOM uint32_t GPIO5INTD : 1; /*!< [23..23] GPIO5 interrupt direction. */ + __IOM uint32_t GPIO6INCFG : 1; /*!< [24..24] GPIO6 input enable. */ + __IOM uint32_t GPIO6OUTCFG : 2; /*!< [26..25] GPIO6 output configuration. */ + __IOM uint32_t GPIO6INTD : 1; /*!< [27..27] GPIO6 interrupt direction. */ + __IOM uint32_t GPIO7INCFG : 1; /*!< [28..28] GPIO7 input enable. */ + __IOM uint32_t GPIO7OUTCFG : 2; /*!< [30..29] GPIO7 output configuration. */ + __IOM uint32_t GPIO7INTD : 1; /*!< [31..31] GPIO7 interrupt direction, nCE polarity. */ + } CFGA_b; + } ; + + union { + __IOM uint32_t CFGB; /*!< (@ 0x00000044) GPIO Configuration Register B (Pads 15-8) */ + + struct { + __IOM uint32_t GPIO8INCFG : 1; /*!< [0..0] GPIO8 input enable. */ + __IOM uint32_t GPIO8OUTCFG : 2; /*!< [2..1] GPIO8 output configuration. */ + __IOM uint32_t GPIO8INTD : 1; /*!< [3..3] GPIO8 interrupt direction. */ + __IOM uint32_t GPIO9INCFG : 1; /*!< [4..4] GPIO9 input enable. */ + __IOM uint32_t GPIO9OUTCFG : 2; /*!< [6..5] GPIO9 output configuration. */ + __IOM uint32_t GPIO9INTD : 1; /*!< [7..7] GPIO9 interrupt direction. */ + __IOM uint32_t GPIO10INCFG : 1; /*!< [8..8] GPIO10 input enable. */ + __IOM uint32_t GPIO10OUTCFG : 2; /*!< [10..9] GPIO10 output configuration. */ + __IOM uint32_t GPIO10INTD : 1; /*!< [11..11] GPIO10 interrupt direction. */ + __IOM uint32_t GPIO11INCFG : 1; /*!< [12..12] GPIO11 input enable. */ + __IOM uint32_t GPIO11OUTCFG : 2; /*!< [14..13] GPIO11 output configuration. */ + __IOM uint32_t GPIO11INTD : 1; /*!< [15..15] GPIO11 interrupt direction. */ + __IOM uint32_t GPIO12INCFG : 1; /*!< [16..16] GPIO12 input enable. */ + __IOM uint32_t GPIO12OUTCFG : 2; /*!< [18..17] GPIO12 output configuration. */ + __IOM uint32_t GPIO12INTD : 1; /*!< [19..19] GPIO12 interrupt direction. */ + __IOM uint32_t GPIO13INCFG : 1; /*!< [20..20] GPIO13 input enable. */ + __IOM uint32_t GPIO13OUTCFG : 2; /*!< [22..21] GPIO13 output configuration. */ + __IOM uint32_t GPIO13INTD : 1; /*!< [23..23] GPIO13 interrupt direction. */ + __IOM uint32_t GPIO14INCFG : 1; /*!< [24..24] GPIO14 input enable. */ + __IOM uint32_t GPIO14OUTCFG : 2; /*!< [26..25] GPIO14 output configuration. */ + __IOM uint32_t GPIO14INTD : 1; /*!< [27..27] GPIO14 interrupt direction. */ + __IOM uint32_t GPIO15INCFG : 1; /*!< [28..28] GPIO15 input enable. */ + __IOM uint32_t GPIO15OUTCFG : 2; /*!< [30..29] GPIO15 output configuration. */ + __IOM uint32_t GPIO15INTD : 1; /*!< [31..31] GPIO15 interrupt direction. */ + } CFGB_b; + } ; + + union { + __IOM uint32_t CFGC; /*!< (@ 0x00000048) GPIO Configuration Register C (Pads 23-16) */ + + struct { + __IOM uint32_t GPIO16INCFG : 1; /*!< [0..0] GPIO16 input enable. */ + __IOM uint32_t GPIO16OUTCFG : 2; /*!< [2..1] GPIO16 output configuration. */ + __IOM uint32_t GPIO16INTD : 1; /*!< [3..3] GPIO16 interrupt direction. */ + __IOM uint32_t GPIO17INCFG : 1; /*!< [4..4] GPIO17 input enable. */ + __IOM uint32_t GPIO17OUTCFG : 2; /*!< [6..5] GPIO17 output configuration. */ + __IOM uint32_t GPIO17INTD : 1; /*!< [7..7] GPIO17 interrupt direction. */ + __IOM uint32_t GPIO18INCFG : 1; /*!< [8..8] GPIO18 input enable. */ + __IOM uint32_t GPIO18OUTCFG : 2; /*!< [10..9] GPIO18 output configuration. */ + __IOM uint32_t GPIO18INTD : 1; /*!< [11..11] GPIO18 interrupt direction. */ + __IOM uint32_t GPIO19INCFG : 1; /*!< [12..12] GPIO19 input enable. */ + __IOM uint32_t GPIO19OUTCFG : 2; /*!< [14..13] GPIO19 output configuration. */ + __IOM uint32_t GPIO19INTD : 1; /*!< [15..15] GPIO19 interrupt direction. */ + __IOM uint32_t GPIO20INCFG : 1; /*!< [16..16] GPIO20 input enable. */ + __IOM uint32_t GPIO20OUTCFG : 2; /*!< [18..17] GPIO20 output configuration. */ + __IOM uint32_t GPIO20INTD : 1; /*!< [19..19] GPIO20 interrupt direction. */ + __IOM uint32_t GPIO21INCFG : 1; /*!< [20..20] GPIO21 input enable. */ + __IOM uint32_t GPIO21OUTCFG : 2; /*!< [22..21] GPIO21 output configuration. */ + __IOM uint32_t GPIO21INTD : 1; /*!< [23..23] GPIO21 interrupt direction. */ + __IOM uint32_t GPIO22INCFG : 1; /*!< [24..24] GPIO22 input enable. */ + __IOM uint32_t GPIO22OUTCFG : 2; /*!< [26..25] GPIO22 output configuration. */ + __IOM uint32_t GPIO22INTD : 1; /*!< [27..27] GPIO22 interrupt direction. */ + __IOM uint32_t GPIO23INCFG : 1; /*!< [28..28] GPIO23 input enable. */ + __IOM uint32_t GPIO23OUTCFG : 2; /*!< [30..29] GPIO23 output configuration. */ + __IOM uint32_t GPIO23INTD : 1; /*!< [31..31] GPIO23 interrupt direction. */ + } CFGC_b; + } ; + + union { + __IOM uint32_t CFGD; /*!< (@ 0x0000004C) GPIO Configuration Register D (Pads 31-24) */ + + struct { + __IOM uint32_t GPIO24INCFG : 1; /*!< [0..0] GPIO24 input enable. */ + __IOM uint32_t GPIO24OUTCFG : 2; /*!< [2..1] GPIO24 output configuration. */ + __IOM uint32_t GPIO24INTD : 1; /*!< [3..3] GPIO24 interrupt direction. */ + __IOM uint32_t GPIO25INCFG : 1; /*!< [4..4] GPIO25 input enable. */ + __IOM uint32_t GPIO25OUTCFG : 2; /*!< [6..5] GPIO25 output configuration. */ + __IOM uint32_t GPIO25INTD : 1; /*!< [7..7] GPIO25 interrupt direction. */ + __IOM uint32_t GPIO26INCFG : 1; /*!< [8..8] GPIO26 input enable. */ + __IOM uint32_t GPIO26OUTCFG : 2; /*!< [10..9] GPIO26 output configuration. */ + __IOM uint32_t GPIO26INTD : 1; /*!< [11..11] GPIO26 interrupt direction. */ + __IOM uint32_t GPIO27INCFG : 1; /*!< [12..12] GPIO27 input enable. */ + __IOM uint32_t GPIO27OUTCFG : 2; /*!< [14..13] GPIO27 output configuration. */ + __IOM uint32_t GPIO27INTD : 1; /*!< [15..15] GPIO27 interrupt direction. */ + __IOM uint32_t GPIO28INCFG : 1; /*!< [16..16] GPIO28 input enable. */ + __IOM uint32_t GPIO28OUTCFG : 2; /*!< [18..17] GPIO28 output configuration. */ + __IOM uint32_t GPIO28INTD : 1; /*!< [19..19] GPIO28 interrupt direction. */ + __IOM uint32_t GPIO29INCFG : 1; /*!< [20..20] GPIO29 input enable. */ + __IOM uint32_t GPIO29OUTCFG : 2; /*!< [22..21] GPIO29 output configuration. */ + __IOM uint32_t GPIO29INTD : 1; /*!< [23..23] GPIO29 interrupt direction. */ + __IOM uint32_t GPIO30INCFG : 1; /*!< [24..24] GPIO30 input enable. */ + __IOM uint32_t GPIO30OUTCFG : 2; /*!< [26..25] GPIO30 output configuration. */ + __IOM uint32_t GPIO30INTD : 1; /*!< [27..27] GPIO30 interrupt direction. */ + __IOM uint32_t GPIO31INCFG : 1; /*!< [28..28] GPIO31 input enable. */ + __IOM uint32_t GPIO31OUTCFG : 2; /*!< [30..29] GPIO31 output configuration. */ + __IOM uint32_t GPIO31INTD : 1; /*!< [31..31] GPIO31 interrupt direction. */ + } CFGD_b; + } ; + + union { + __IOM uint32_t CFGE; /*!< (@ 0x00000050) GPIO Configuration Register E (Pads 39-32) */ + + struct { + __IOM uint32_t GPIO32INCFG : 1; /*!< [0..0] GPIO32 input enable. */ + __IOM uint32_t GPIO32OUTCFG : 2; /*!< [2..1] GPIO32 output configuration. */ + __IOM uint32_t GPIO32INTD : 1; /*!< [3..3] GPIO32 interrupt direction. */ + __IOM uint32_t GPIO33INCFG : 1; /*!< [4..4] GPIO33 input enable. */ + __IOM uint32_t GPIO33OUTCFG : 2; /*!< [6..5] GPIO33 output configuration. */ + __IOM uint32_t GPIO33INTD : 1; /*!< [7..7] GPIO33 interrupt direction. */ + __IOM uint32_t GPIO34INCFG : 1; /*!< [8..8] GPIO34 input enable. */ + __IOM uint32_t GPIO34OUTCFG : 2; /*!< [10..9] GPIO34 output configuration. */ + __IOM uint32_t GPIO34INTD : 1; /*!< [11..11] GPIO34 interrupt direction. */ + __IOM uint32_t GPIO35INCFG : 1; /*!< [12..12] GPIO35 input enable. */ + __IOM uint32_t GPIO35OUTCFG : 2; /*!< [14..13] GPIO35 output configuration. */ + __IOM uint32_t GPIO35INTD : 1; /*!< [15..15] GPIO35 interrupt direction. */ + __IOM uint32_t GPIO36INCFG : 1; /*!< [16..16] GPIO36 input enable. */ + __IOM uint32_t GPIO36OUTCFG : 2; /*!< [18..17] GPIO36 output configuration. */ + __IOM uint32_t GPIO36INTD : 1; /*!< [19..19] GPIO36 interrupt direction. */ + __IOM uint32_t GPIO37INCFG : 1; /*!< [20..20] GPIO37 input enable. */ + __IOM uint32_t GPIO37OUTCFG : 2; /*!< [22..21] GPIO37 output configuration. */ + __IOM uint32_t GPIO37INTD : 1; /*!< [23..23] GPIO37 interrupt direction. */ + __IOM uint32_t GPIO38INCFG : 1; /*!< [24..24] GPIO38 input enable. */ + __IOM uint32_t GPIO38OUTCFG : 2; /*!< [26..25] GPIO38 output configuration. */ + __IOM uint32_t GPIO38INTD : 1; /*!< [27..27] GPIO38 interrupt direction. */ + __IOM uint32_t GPIO39INCFG : 1; /*!< [28..28] GPIO39 input enable. */ + __IOM uint32_t GPIO39OUTCFG : 2; /*!< [30..29] GPIO39 output configuration. */ + __IOM uint32_t GPIO39INTD : 1; /*!< [31..31] GPIO39 interrupt direction. */ + } CFGE_b; + } ; + + union { + __IOM uint32_t CFGF; /*!< (@ 0x00000054) GPIO Configuration Register F (Pads 47-40) */ + + struct { + __IOM uint32_t GPIO40INCFG : 1; /*!< [0..0] GPIO40 input enable. */ + __IOM uint32_t GPIO40OUTCFG : 2; /*!< [2..1] GPIO40 output configuration. */ + __IOM uint32_t GPIO40INTD : 1; /*!< [3..3] GPIO40 interrupt direction. */ + __IOM uint32_t GPIO41INCFG : 1; /*!< [4..4] GPIO41 input enable. */ + __IOM uint32_t GPIO41OUTCFG : 2; /*!< [6..5] GPIO41 output configuration. */ + __IOM uint32_t GPIO41INTD : 1; /*!< [7..7] GPIO41 interrupt direction. */ + __IOM uint32_t GPIO42INCFG : 1; /*!< [8..8] GPIO42 input enable. */ + __IOM uint32_t GPIO42OUTCFG : 2; /*!< [10..9] GPIO42 output configuration. */ + __IOM uint32_t GPIO42INTD : 1; /*!< [11..11] GPIO42 interrupt direction. */ + __IOM uint32_t GPIO43INCFG : 1; /*!< [12..12] GPIO43 input enable. */ + __IOM uint32_t GPIO43OUTCFG : 2; /*!< [14..13] GPIO43 output configuration. */ + __IOM uint32_t GPIO43INTD : 1; /*!< [15..15] GPIO43 interrupt direction. */ + __IOM uint32_t GPIO44INCFG : 1; /*!< [16..16] GPIO44 input enable. */ + __IOM uint32_t GPIO44OUTCFG : 2; /*!< [18..17] GPIO44 output configuration. */ + __IOM uint32_t GPIO44INTD : 1; /*!< [19..19] GPIO44 interrupt direction. */ + __IOM uint32_t GPIO45INCFG : 1; /*!< [20..20] GPIO45 input enable. */ + __IOM uint32_t GPIO45OUTCFG : 2; /*!< [22..21] GPIO45 output configuration. */ + __IOM uint32_t GPIO45INTD : 1; /*!< [23..23] GPIO45 interrupt direction. */ + __IOM uint32_t GPIO46INCFG : 1; /*!< [24..24] GPIO46 input enable. */ + __IOM uint32_t GPIO46OUTCFG : 2; /*!< [26..25] GPIO46 output configuration. */ + __IOM uint32_t GPIO46INTD : 1; /*!< [27..27] GPIO46 interrupt direction. */ + __IOM uint32_t GPIO47INCFG : 1; /*!< [28..28] GPIO47 input enable. */ + __IOM uint32_t GPIO47OUTCFG : 2; /*!< [30..29] GPIO47 output configuration. */ + __IOM uint32_t GPIO47INTD : 1; /*!< [31..31] GPIO47 interrupt direction. */ + } CFGF_b; + } ; + + union { + __IOM uint32_t CFGG; /*!< (@ 0x00000058) GPIO Configuration Register G (Pads 49-48) */ + + struct { + __IOM uint32_t GPIO48INCFG : 1; /*!< [0..0] GPIO48 input enable. */ + __IOM uint32_t GPIO48OUTCFG : 2; /*!< [2..1] GPIO48 output configuration. */ + __IOM uint32_t GPIO48INTD : 1; /*!< [3..3] GPIO48 interrupt direction. */ + __IOM uint32_t GPIO49INCFG : 1; /*!< [4..4] GPIO49 input enable. */ + __IOM uint32_t GPIO49OUTCFG : 2; /*!< [6..5] GPIO49 output configuration. */ + __IOM uint32_t GPIO49INTD : 1; /*!< [7..7] GPIO49 interrupt direction. */ + } CFGG_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t PADKEY; /*!< (@ 0x00000060) Key Register for all pad configuration registers */ + + struct { + __IOM uint32_t PADKEY : 32; /*!< [31..0] Key register value. */ + } PADKEY_b; + } ; + __IM uint32_t RESERVED2[7]; + + union { + __IOM uint32_t RDA; /*!< (@ 0x00000080) GPIO Input Register A */ + + struct { + __IOM uint32_t RDA : 32; /*!< [31..0] GPIO31-0 read data. */ + } RDA_b; + } ; + + union { + __IOM uint32_t RDB; /*!< (@ 0x00000084) GPIO Input Register B */ + + struct { + __IOM uint32_t RDB : 18; /*!< [17..0] GPIO49-32 read data. */ + } RDB_b; + } ; + + union { + __IOM uint32_t WTA; /*!< (@ 0x00000088) GPIO Output Register A */ + + struct { + __IOM uint32_t WTA : 32; /*!< [31..0] GPIO31-0 write data. */ + } WTA_b; + } ; + + union { + __IOM uint32_t WTB; /*!< (@ 0x0000008C) GPIO Output Register B */ + + struct { + __IOM uint32_t WTB : 18; /*!< [17..0] GPIO49-32 write data. */ + } WTB_b; + } ; + + union { + __IOM uint32_t WTSA; /*!< (@ 0x00000090) GPIO Output Register A Set */ + + struct { + __IOM uint32_t WTSA : 32; /*!< [31..0] Set the GPIO31-0 write data. */ + } WTSA_b; + } ; + + union { + __IOM uint32_t WTSB; /*!< (@ 0x00000094) GPIO Output Register B Set */ + + struct { + __IOM uint32_t WTSB : 18; /*!< [17..0] Set the GPIO49-32 write data. */ + } WTSB_b; + } ; + + union { + __IOM uint32_t WTCA; /*!< (@ 0x00000098) GPIO Output Register A Clear */ + + struct { + __IOM uint32_t WTCA : 32; /*!< [31..0] Clear the GPIO31-0 write data. */ + } WTCA_b; + } ; + + union { + __IOM uint32_t WTCB; /*!< (@ 0x0000009C) GPIO Output Register B Clear */ + + struct { + __IOM uint32_t WTCB : 18; /*!< [17..0] Clear the GPIO49-32 write data. */ + } WTCB_b; + } ; + + union { + __IOM uint32_t ENA; /*!< (@ 0x000000A0) GPIO Enable Register A */ + + struct { + __IOM uint32_t ENA : 32; /*!< [31..0] GPIO31-0 output enables */ + } ENA_b; + } ; + + union { + __IOM uint32_t ENB; /*!< (@ 0x000000A4) GPIO Enable Register B */ + + struct { + __IOM uint32_t ENB : 18; /*!< [17..0] GPIO49-32 output enables */ + } ENB_b; + } ; + + union { + __IOM uint32_t ENSA; /*!< (@ 0x000000A8) GPIO Enable Register A Set */ + + struct { + __IOM uint32_t ENSA : 32; /*!< [31..0] Set the GPIO31-0 output enables */ + } ENSA_b; + } ; + + union { + __IOM uint32_t ENSB; /*!< (@ 0x000000AC) GPIO Enable Register B Set */ + + struct { + __IOM uint32_t ENSB : 18; /*!< [17..0] Set the GPIO49-32 output enables */ + } ENSB_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t ENCA; /*!< (@ 0x000000B4) GPIO Enable Register A Clear */ + + struct { + __IOM uint32_t ENCA : 32; /*!< [31..0] Clear the GPIO31-0 output enables */ + } ENCA_b; + } ; + + union { + __IOM uint32_t ENCB; /*!< (@ 0x000000B8) GPIO Enable Register B Clear */ + + struct { + __IOM uint32_t ENCB : 18; /*!< [17..0] Clear the GPIO49-32 output enables */ + } ENCB_b; + } ; + + union { + __IOM uint32_t STMRCAP; /*!< (@ 0x000000BC) STIMER Capture Control */ + + struct { + __IOM uint32_t STSEL0 : 6; /*!< [5..0] STIMER Capture 0 Select. */ + __IOM uint32_t STPOL0 : 1; /*!< [6..6] STIMER Capture 0 Polarity. */ + uint32_t : 1; + __IOM uint32_t STSEL1 : 6; /*!< [13..8] STIMER Capture 1 Select. */ + __IOM uint32_t STPOL1 : 1; /*!< [14..14] STIMER Capture 1 Polarity. */ + uint32_t : 1; + __IOM uint32_t STSEL2 : 6; /*!< [21..16] STIMER Capture 2 Select. */ + __IOM uint32_t STPOL2 : 1; /*!< [22..22] STIMER Capture 2 Polarity. */ + uint32_t : 1; + __IOM uint32_t STSEL3 : 6; /*!< [29..24] STIMER Capture 3 Select. */ + __IOM uint32_t STPOL3 : 1; /*!< [30..30] STIMER Capture 3 Polarity. */ + } STMRCAP_b; + } ; + + union { + __IOM uint32_t IOM0IRQ; /*!< (@ 0x000000C0) IOM0 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM0IRQ : 6; /*!< [5..0] IOMSTR0 IRQ pad select. */ + } IOM0IRQ_b; + } ; + + union { + __IOM uint32_t IOM1IRQ; /*!< (@ 0x000000C4) IOM1 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM1IRQ : 6; /*!< [5..0] IOMSTR1 IRQ pad select. */ + } IOM1IRQ_b; + } ; + + union { + __IOM uint32_t IOM2IRQ; /*!< (@ 0x000000C8) IOM2 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM2IRQ : 6; /*!< [5..0] IOMSTR2 IRQ pad select. */ + } IOM2IRQ_b; + } ; + + union { + __IOM uint32_t IOM3IRQ; /*!< (@ 0x000000CC) IOM3 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM3IRQ : 6; /*!< [5..0] IOMSTR3 IRQ pad select. */ + } IOM3IRQ_b; + } ; + + union { + __IOM uint32_t IOM4IRQ; /*!< (@ 0x000000D0) IOM4 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM4IRQ : 6; /*!< [5..0] IOMSTR4 IRQ pad select. */ + } IOM4IRQ_b; + } ; + + union { + __IOM uint32_t IOM5IRQ; /*!< (@ 0x000000D4) IOM5 Flow Control IRQ Select */ + + struct { + __IOM uint32_t IOM5IRQ : 6; /*!< [5..0] IOMSTR5 IRQ pad select. */ + } IOM5IRQ_b; + } ; + + union { + __IOM uint32_t BLEIFIRQ; /*!< (@ 0x000000D8) BLEIF Flow Control IRQ Select */ + + struct { + __IOM uint32_t BLEIFIRQ : 6; /*!< [5..0] BLEIF IRQ pad select. */ + } BLEIFIRQ_b; + } ; + + union { + __IOM uint32_t GPIOOBS; /*!< (@ 0x000000DC) GPIO Observation Mode Sample register */ + + struct { + __IOM uint32_t OBS_DATA : 16; /*!< [15..0] Sample of the data output on the GPIO observation port. + May have async sampling issues, as the data is not synronized + to the read operation. Intended for debug purposes only */ + } GPIOOBS_b; + } ; + + union { + __IOM uint32_t ALTPADCFGA; /*!< (@ 0x000000E0) Alternate Pad Configuration reg0 (Pads 0-3) */ + + struct { + __IOM uint32_t PAD0_DS1 : 1; /*!< [0..0] Pad 0 high order drive strength selection. Used in conjunction + with PAD0STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD0_SR : 1; /*!< [4..4] Pad 0 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD1_DS1 : 1; /*!< [8..8] Pad 1 high order drive strength selection. Used in conjunction + with PAD1STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD1_SR : 1; /*!< [12..12] Pad 1 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD2_DS1 : 1; /*!< [16..16] Pad 2 high order drive strength selection. Used in + conjunction with PAD2STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD2_SR : 1; /*!< [20..20] Pad 2 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD3_DS1 : 1; /*!< [24..24] Pad 3 high order drive strength selection. Used in + conjunction with PAD3STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD3_SR : 1; /*!< [28..28] Pad 3 slew rate selection. */ + } ALTPADCFGA_b; + } ; + + union { + __IOM uint32_t ALTPADCFGB; /*!< (@ 0x000000E4) Alternate Pad Configuration reg1 (Pads 4-7) */ + + struct { + __IOM uint32_t PAD4_DS1 : 1; /*!< [0..0] Pad 4 high order drive strength selection. Used in conjunction + with PAD4STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD4_SR : 1; /*!< [4..4] Pad 4 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD5_DS1 : 1; /*!< [8..8] Pad 5 high order drive strength selection. Used in conjunction + with PAD5STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD5_SR : 1; /*!< [12..12] Pad 5 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD6_DS1 : 1; /*!< [16..16] Pad 6 high order drive strength selection. Used in + conjunction with PAD6STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD6_SR : 1; /*!< [20..20] Pad 6 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD7_DS1 : 1; /*!< [24..24] Pad 7 high order drive strength selection. Used in + conjunction with PAD7STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD7_SR : 1; /*!< [28..28] Pad 7 slew rate selection. */ + } ALTPADCFGB_b; + } ; + + union { + __IOM uint32_t ALTPADCFGC; /*!< (@ 0x000000E8) Alternate Pad Configuration reg2 (Pads 8-11) */ + + struct { + __IOM uint32_t PAD8_DS1 : 1; /*!< [0..0] Pad 8 high order drive strength selection. Used in conjunction + with PAD8STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD8_SR : 1; /*!< [4..4] Pad 8 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD9_DS1 : 1; /*!< [8..8] Pad 9 high order drive strength selection. Used in conjunction + with PAD9STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD9_SR : 1; /*!< [12..12] Pad 9 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD10_DS1 : 1; /*!< [16..16] Pad 10 high order drive strength selection. Used in + conjunction with PAD10STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD10_SR : 1; /*!< [20..20] Pad 10 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD11_DS1 : 1; /*!< [24..24] Pad 11 high order drive strength selection. Used in + conjunction with PAD11STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD11_SR : 1; /*!< [28..28] Pad 11 slew rate selection. */ + } ALTPADCFGC_b; + } ; + + union { + __IOM uint32_t ALTPADCFGD; /*!< (@ 0x000000EC) Alternate Pad Configuration reg3 (Pads 12-15) */ + + struct { + __IOM uint32_t PAD12_DS1 : 1; /*!< [0..0] Pad 12 high order drive strength selection. Used in conjunction + with PAD12STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD12_SR : 1; /*!< [4..4] Pad 12 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD13_DS1 : 1; /*!< [8..8] Pad 13 high order drive strength selection. Used in conjunction + with PAD13STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD13_SR : 1; /*!< [12..12] Pad 13 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD14_DS1 : 1; /*!< [16..16] Pad 14 high order drive strength selection. Used in + conjunction with PAD14STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD14_SR : 1; /*!< [20..20] Pad 14 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD15_DS1 : 1; /*!< [24..24] Pad 15 high order drive strength selection. Used in + conjunction with PAD15STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD15_SR : 1; /*!< [28..28] Pad 15 slew rate selection. */ + } ALTPADCFGD_b; + } ; + + union { + __IOM uint32_t ALTPADCFGE; /*!< (@ 0x000000F0) Alternate Pad Configuration reg4 (Pads 16-19) */ + + struct { + __IOM uint32_t PAD16_DS1 : 1; /*!< [0..0] Pad 16 high order drive strength selection. Used in conjunction + with PAD16STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD16_SR : 1; /*!< [4..4] Pad 16 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD17_DS1 : 1; /*!< [8..8] Pad 17 high order drive strength selection. Used in conjunction + with PAD17STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD17_SR : 1; /*!< [12..12] Pad 17 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD18_DS1 : 1; /*!< [16..16] Pad 18 high order drive strength selection. Used in + conjunction with PAD18STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD18_SR : 1; /*!< [20..20] Pad 18 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD19_DS1 : 1; /*!< [24..24] Pad 19 high order drive strength selection. Used in + conjunction with PAD19STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD19_SR : 1; /*!< [28..28] Pad 19 slew rate selection. */ + } ALTPADCFGE_b; + } ; + + union { + __IOM uint32_t ALTPADCFGF; /*!< (@ 0x000000F4) Alternate Pad Configuration reg5 (Pads 20-23) */ + + struct { + __IOM uint32_t PAD20_DS1 : 1; /*!< [0..0] Pad 20 high order drive strength selection. Used in conjunction + with PAD20STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD20_SR : 1; /*!< [4..4] Pad 20 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD21_DS1 : 1; /*!< [8..8] Pad 21 high order drive strength selection. Used in conjunction + with PAD21STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD21_SR : 1; /*!< [12..12] Pad 21 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD22_DS1 : 1; /*!< [16..16] Pad 22 high order drive strength selection. Used in + conjunction with PAD22STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD22_SR : 1; /*!< [20..20] Pad 22 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD23_DS1 : 1; /*!< [24..24] Pad 23 high order drive strength selection. Used in + conjunction with PAD23STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD23_SR : 1; /*!< [28..28] Pad 23 slew rate selection. */ + } ALTPADCFGF_b; + } ; + + union { + __IOM uint32_t ALTPADCFGG; /*!< (@ 0x000000F8) Alternate Pad Configuration reg6 (Pads 24-27) */ + + struct { + __IOM uint32_t PAD24_DS1 : 1; /*!< [0..0] Pad 24 high order drive strength selection. Used in conjunction + with PAD24STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD24_SR : 1; /*!< [4..4] Pad 24 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD25_DS1 : 1; /*!< [8..8] Pad 25 high order drive strength selection. Used in conjunction + with PAD25STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD25_SR : 1; /*!< [12..12] Pad 25 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD26_DS1 : 1; /*!< [16..16] Pad 26 high order drive strength selection. Used in + conjunction with PAD26STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD26_SR : 1; /*!< [20..20] Pad 26 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD27_DS1 : 1; /*!< [24..24] Pad 27 high order drive strength selection. Used in + conjunction with PAD27STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD27_SR : 1; /*!< [28..28] Pad 27 slew rate selection. */ + } ALTPADCFGG_b; + } ; + + union { + __IOM uint32_t ALTPADCFGH; /*!< (@ 0x000000FC) Alternate Pad Configuration reg7 (Pads 28-31) */ + + struct { + __IOM uint32_t PAD28_DS1 : 1; /*!< [0..0] Pad 28 high order drive strength selection. Used in conjunction + with PAD28STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD28_SR : 1; /*!< [4..4] Pad 28 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD29_DS1 : 1; /*!< [8..8] Pad 29 high order drive strength selection. Used in conjunction + with PAD29STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD29_SR : 1; /*!< [12..12] Pad 29 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD30_DS1 : 1; /*!< [16..16] Pad 30 high order drive strength selection. Used in + conjunction with PAD30STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD30_SR : 1; /*!< [20..20] Pad 30 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD31_DS1 : 1; /*!< [24..24] Pad 31 high order drive strength selection. Used in + conjunction with PAD31STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD31_SR : 1; /*!< [28..28] Pad 31 slew rate selection. */ + } ALTPADCFGH_b; + } ; + + union { + __IOM uint32_t ALTPADCFGI; /*!< (@ 0x00000100) Alternate Pad Configuration reg8 (Pads 32-35) */ + + struct { + __IOM uint32_t PAD32_DS1 : 1; /*!< [0..0] Pad 32 high order drive strength selection. Used in conjunction + with PAD32STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD32_SR : 1; /*!< [4..4] Pad 32 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD33_DS1 : 1; /*!< [8..8] Pad 33 high order drive strength selection. Used in conjunction + with PAD33STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD33_SR : 1; /*!< [12..12] Pad 33 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD34_DS1 : 1; /*!< [16..16] Pad 34 high order drive strength selection. Used in + conjunction with PAD34STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD34_SR : 1; /*!< [20..20] Pad 34 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD35_DS1 : 1; /*!< [24..24] Pad 35 high order drive strength selection. Used in + conjunction with PAD35STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD35_SR : 1; /*!< [28..28] Pad 35 slew rate selection. */ + } ALTPADCFGI_b; + } ; + + union { + __IOM uint32_t ALTPADCFGJ; /*!< (@ 0x00000104) Alternate Pad Configuration reg9 (Pads 36-39) */ + + struct { + __IOM uint32_t PAD36_DS1 : 1; /*!< [0..0] Pad 36 high order drive strength selection. Used in conjunction + with PAD36STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD36_SR : 1; /*!< [4..4] Pad 36 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD37_DS1 : 1; /*!< [8..8] Pad 37 high order drive strength selection. Used in conjunction + with PAD37STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD37_SR : 1; /*!< [12..12] Pad 37 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD38_DS1 : 1; /*!< [16..16] Pad 38 high order drive strength selection. Used in + conjunction with PAD38STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD38_SR : 1; /*!< [20..20] Pad 38 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD39_DS1 : 1; /*!< [24..24] Pad 39 high order drive strength selection. Used in + conjunction with PAD39STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD39_SR : 1; /*!< [28..28] Pad 39 slew rate selection. */ + } ALTPADCFGJ_b; + } ; + + union { + __IOM uint32_t ALTPADCFGK; /*!< (@ 0x00000108) Alternate Pad Configuration reg10 (Pads 40-43) */ + + struct { + __IOM uint32_t PAD40_DS1 : 1; /*!< [0..0] Pad 40 high order drive strength selection. Used in conjunction + with PAD40STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD40_SR : 1; /*!< [4..4] Pad 40 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD41_DS1 : 1; /*!< [8..8] Pad 41 high order drive strength selection. Used in conjunction + with PAD41STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD41_SR : 1; /*!< [12..12] Pad 41 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD42_DS1 : 1; /*!< [16..16] Pad 42 high order drive strength selection. Used in + conjunction with PAD42STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD42_SR : 1; /*!< [20..20] Pad 42 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD43_DS1 : 1; /*!< [24..24] Pad 43 high order drive strength selection. Used in + conjunction with PAD43STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD43_SR : 1; /*!< [28..28] Pad 43 slew rate selection. */ + } ALTPADCFGK_b; + } ; + + union { + __IOM uint32_t ALTPADCFGL; /*!< (@ 0x0000010C) Alternate Pad Configuration reg11 (Pads 44-47) */ + + struct { + __IOM uint32_t PAD44_DS1 : 1; /*!< [0..0] Pad 44 high order drive strength selection. Used in conjunction + with PAD44STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD44_SR : 1; /*!< [4..4] Pad 44 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD45_DS1 : 1; /*!< [8..8] Pad 45 high order drive strength selection. Used in conjunction + with PAD45STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD45_SR : 1; /*!< [12..12] Pad 45 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD46_DS1 : 1; /*!< [16..16] Pad 46 high order drive strength selection. Used in + conjunction with PAD46STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD46_SR : 1; /*!< [20..20] Pad 46 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD47_DS1 : 1; /*!< [24..24] Pad 47 high order drive strength selection. Used in + conjunction with PAD47STRNG field to set the pad drive + strength. */ + uint32_t : 3; + __IOM uint32_t PAD47_SR : 1; /*!< [28..28] Pad 47 slew rate selection. */ + } ALTPADCFGL_b; + } ; + + union { + __IOM uint32_t ALTPADCFGM; /*!< (@ 0x00000110) Alternate Pad Configuration reg12 (Pads 48-49) */ + + struct { + __IOM uint32_t PAD48_DS1 : 1; /*!< [0..0] Pad 48 high order drive strength selection. Used in conjunction + with PAD48STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD48_SR : 1; /*!< [4..4] Pad 48 slew rate selection. */ + uint32_t : 3; + __IOM uint32_t PAD49_DS1 : 1; /*!< [8..8] Pad 49 high order drive strength selection. Used in conjunction + with PAD49STRNG field to set the pad drive strength. */ + uint32_t : 3; + __IOM uint32_t PAD49_SR : 1; /*!< [12..12] Pad 49 slew rate selection. */ + } ALTPADCFGM_b; + } ; + + union { + __IOM uint32_t SCDET; /*!< (@ 0x00000114) SCARD Card Detect select */ + + struct { + __IOM uint32_t SCDET : 6; /*!< [5..0] SCARD card detect pad select. */ + } SCDET_b; + } ; + + union { + __IOM uint32_t CTENCFG; /*!< (@ 0x00000118) Counter/Timer Enable Config */ + + struct { + __IOM uint32_t EN0 : 1; /*!< [0..0] CT0 Enable */ + __IOM uint32_t EN1 : 1; /*!< [1..1] CT1 Enable */ + __IOM uint32_t EN2 : 1; /*!< [2..2] CT2 Enable */ + __IOM uint32_t EN3 : 1; /*!< [3..3] CT3 Enable */ + __IOM uint32_t EN4 : 1; /*!< [4..4] CT4 Enable */ + __IOM uint32_t EN5 : 1; /*!< [5..5] CT5 Enable */ + __IOM uint32_t EN6 : 1; /*!< [6..6] CT6 Enable */ + __IOM uint32_t EN7 : 1; /*!< [7..7] CT7 Enable */ + __IOM uint32_t EN8 : 1; /*!< [8..8] CT8 Enable */ + __IOM uint32_t EN9 : 1; /*!< [9..9] CT9 Enable */ + __IOM uint32_t EN10 : 1; /*!< [10..10] CT10 Enable */ + __IOM uint32_t EN11 : 1; /*!< [11..11] CT11 Enable */ + __IOM uint32_t EN12 : 1; /*!< [12..12] CT12 Enable */ + __IOM uint32_t EN13 : 1; /*!< [13..13] CT13 Enable */ + __IOM uint32_t EN14 : 1; /*!< [14..14] CT14 Enable */ + __IOM uint32_t EN15 : 1; /*!< [15..15] CT15 Enable */ + __IOM uint32_t EN16 : 1; /*!< [16..16] CT16 Enable */ + __IOM uint32_t EN17 : 1; /*!< [17..17] CT17 Enable */ + __IOM uint32_t EN18 : 1; /*!< [18..18] CT18 Enable */ + __IOM uint32_t EN19 : 1; /*!< [19..19] CT19 Enable */ + __IOM uint32_t EN20 : 1; /*!< [20..20] CT20 Enable */ + __IOM uint32_t EN21 : 1; /*!< [21..21] CT21 Enable */ + __IOM uint32_t EN22 : 1; /*!< [22..22] CT22 Enable */ + __IOM uint32_t EN23 : 1; /*!< [23..23] CT23 Enable */ + __IOM uint32_t EN24 : 1; /*!< [24..24] CT24 Enable */ + __IOM uint32_t EN25 : 1; /*!< [25..25] CT25 Enable */ + __IOM uint32_t EN26 : 1; /*!< [26..26] CT26 Enable */ + __IOM uint32_t EN27 : 1; /*!< [27..27] CT27 Enable */ + __IOM uint32_t EN28 : 1; /*!< [28..28] CT28 Enable */ + __IOM uint32_t EN29 : 1; /*!< [29..29] CT29 Enable */ + __IOM uint32_t EN30 : 1; /*!< [30..30] CT30 Enable */ + __IOM uint32_t EN31 : 1; /*!< [31..31] CT31 Enable */ + } CTENCFG_b; + } ; + __IM uint32_t RESERVED4[57]; + + union { + __IOM uint32_t INT0EN; /*!< (@ 0x00000200) GPIO Interrupt Registers 31-0: Enable */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0EN_b; + } ; + + union { + __IOM uint32_t INT0STAT; /*!< (@ 0x00000204) GPIO Interrupt Registers 31-0: Status */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0STAT_b; + } ; + + union { + __IOM uint32_t INT0CLR; /*!< (@ 0x00000208) GPIO Interrupt Registers 31-0: Clear */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0CLR_b; + } ; + + union { + __IOM uint32_t INT0SET; /*!< (@ 0x0000020C) GPIO Interrupt Registers 31-0: Set */ + + struct { + __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ + __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ + __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ + __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ + __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ + __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ + __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ + __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ + __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ + __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ + __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ + __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ + __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ + __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ + __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ + __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ + __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ + __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ + __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ + __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ + __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ + __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ + __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ + __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ + __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ + __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ + __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ + __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ + __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ + __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ + __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ + __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ + } INT0SET_b; + } ; + + union { + __IOM uint32_t INT1EN; /*!< (@ 0x00000210) GPIO Interrupt Registers 49-32: Enable */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1EN_b; + } ; + + union { + __IOM uint32_t INT1STAT; /*!< (@ 0x00000214) GPIO Interrupt Registers 49-32: Status */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1STAT_b; + } ; + + union { + __IOM uint32_t INT1CLR; /*!< (@ 0x00000218) GPIO Interrupt Registers 49-32: Clear */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1CLR_b; + } ; + + union { + __IOM uint32_t INT1SET; /*!< (@ 0x0000021C) GPIO Interrupt Registers 49-32: Set */ + + struct { + __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ + __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ + __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ + __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ + __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ + __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ + __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ + __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ + __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ + __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ + __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ + __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ + __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ + __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ + __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ + __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ + __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ + __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ + } INT1SET_b; + } ; +} GPIO_Type; /*!< Size = 544 (0x220) */ + + + +/* =========================================================================================================================== */ +/* ================ IOM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO Peripheral Master (IOM0) + */ + +typedef struct { /*!< (@ 0x50004000) IOM0 Structure */ + + union { + __IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */ + + struct { + __IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return + valid information. */ + } FIFO_b; + } ; + __IM uint32_t RESERVED[63]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) FIFO size and remaining slots open values */ + + struct { + __IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO + 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in + FIFO 0 (written by MCU, read by interface) */ + __IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1 + (written by interface, read by MCU) */ + __IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently + in FIFO 1 (written by interface, read by MCU) */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable + the read FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the read fifo contains FIFORTHR valid bytes + of data, as indicated by the FIFO1SIZ field. This is intended + to signal when a data transfer of FIFORTHR bytes can be + done from the IOM module to the host via the read fifo + to support large IOM read operations. */ + uint32_t : 2; + __IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable + the write FIFO level from activating the threshold interrupt. + If this field is non-zero, it will trigger a threshold + interrupt when the write fifo contains FIFOWTHR free bytes, + as indicated by the FIFO0REM field. This is intended to + signal when a transfer of FIFOWTHR bytes can be done from + the host to the IOM write fifo to support large IOM write + operations. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) FIFO POP register */ + + struct { + __IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by + the current read pointer on reads. If the POPWR control + bit in the FIFOCTRL register is reset (0), the fifo read + pointer will be advanced by one word as a result of the + read.If the POPWR bit is set (1), the fifo read pointer + will only be advanced after a write operation to this register. + The write data is ignored for this register.If less than + a even word multiple is available, and the command is completed, + the module will return the word containing */ + } FIFOPOP_b; + } ; + + union { + __IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) FIFO PUSH register */ + + struct { + __IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode + and will cause a push event to occur to the next open slot + within the FIFORAM. Writing to this register will cause + the write point to increment by 1 word(4 bytes). */ + } FIFOPUSH_b; + } ; + + union { + __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) FIFO Control Register */ + + struct { + __IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the + fifo read operations. A value of '1' will prevent a pop + event on a read operation, and will require a write to + the FIFOPOP register to create a pop event.A value of '0' + in this register will allow a pop event to occur on the + read of the FIFOPOP register, and may cause inadvertant + fifo pops when used in a debugging mode. */ + __IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset + fifo, and then write to 1 to remove the reset. */ + } FIFOCTRL_b; + } ; + + union { + __IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) FIFO Pointers */ + + struct { + __IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the + outgoing FIFO (FIFO0), which is used during write operations + to external devices. */ + uint32_t : 4; + __IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming + FIFO (FIFO1), which is used to store read data returned + from external devices during a read operation. */ + } FIFOLOC_b; + } ; + __IM uint32_t RESERVED1[58]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current + operation has completed. For repeated commands, this will + only be asserted when the final repeated command is completed. */ + __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted + when the number of free bytes in the write FIFO equals + or exceeds the WTHR field.For read operations, asserted + when the number of valid bytes in the read FIFO equals + of exceeds the value set in the RTHR field. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software + tries to pop from an empty fifo. */ + __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software + tries to write to a full fifo. The current operation does + not stop. */ + __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has + been received on the I2C bus. */ + __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is + a overflow or underflow event */ + __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is + written when an active command is in progress. */ + __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master + on the bus has signaled a START command. */ + __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master + on the bus has signaled a STOP command. */ + __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration + is enabled and has been lost to another master on the bus. */ + __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed + and the DMA submodule is returned into the idle state */ + __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the + DMA command. The DMA error could occur when the memory + access specified in the DMA operation is not available + or incorrectly specified. */ + __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled + in the PAUSEEN register. The interrupt is posted when the + event is enabled within the PAUSEEN register, the mask + is active in the CQIRQMASK field and the event occurs. */ + __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with + the register address bit 0 set to 1. The low address bits + in the CQ address fields are unused and bit 0 can be used + to trigger an interrupt to indicate when this register + write is performed by the CQ operation. */ + __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ + } INTSET_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x00000210) I/O Clock Configuration */ + + struct { + __IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior + to executing any IO operations. */ + uint32_t : 7; + __IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */ + __IOM uint32_t DIV3 : 1; /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by + 3 is done before the DIVEN programmable divider, and if + enabledwill provide the divided by 3 clock as the source + to the programmable divider. */ + __IOM uint32_t DIVEN : 1; /*!< [12..12] Enable clock division by TOTPER and LOWPER */ + uint32_t : 3; + __IOM uint32_t LOWPER : 8; /*!< [23..16] Clock low clock count minus 1. This provides the number + of clocks the divided clock will be low when the DIVEN + = 1.Only applicable when DIVEN = 1. */ + __IOM uint32_t TOTPER : 8; /*!< [31..24] Clock total clock count minus 1. This provides the + total period of the divided clock -1 when the DIVEN is + active. Thesource clock is selected by FSEL. Only applicable + when DIVEN = 1. */ + } CLKCFG_b; + } ; + + union { + __IOM uint32_t SUBMODCTRL; /*!< (@ 0x00000214) Submodule control */ + + struct { + __IOM uint32_t SMOD0EN : 1; /*!< [0..0] Submodule 0 enable (1) or disable (0) */ + __IOM uint32_t SMOD0TYPE : 3; /*!< [3..1] Submodule 0 module type. This is the SPI Master interface. */ + __IOM uint32_t SMOD1EN : 1; /*!< [4..4] Submodule 1 enable (1) or disable (0) */ + __IOM uint32_t SMOD1TYPE : 3; /*!< [7..5] Submodule 0 module type. This is the I2C Master interface */ + } SUBMODCTRL_b; + } ; + + union { + __IOM uint32_t CMD; /*!< (@ 0x00000218) Command and offset Register */ + + struct { + __IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */ + __IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1, + 2, 3 are valid selections. The second (byte 1) and third + byte (byte 2) are read from the OFFSETHI register, and + the low order byte is pulled from this register in the + OFFSETLO field.Offset bytes are transmitted highest byte + first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted + first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt == + 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If + offsetcnt == 1, only OFFSETLO will be transmitted. */ + __IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction + if set to a 1 with a new command issued. */ + __IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer + is not included in this size. */ + __IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information. Not used in + Master I2C. Used as CEn select for Master SPI transactions */ + uint32_t : 2; + __IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to + be used in the transaction. The number of offset bytes + to use is set with bits 1:0 of the command. */ + } CMD_b; + } ; + + union { + __IOM uint32_t DCX; /*!< (@ 0x0000021C) DCX Control Register */ + + struct { + __IOM uint32_t CE0OUT : 1; /*!< [0..0] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE0 output. */ + __IOM uint32_t CE1OUT : 1; /*!< [1..1] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE1 output. */ + __IOM uint32_t CE2OUT : 1; /*!< [2..2] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE2 output. */ + __IOM uint32_t CE3OUT : 1; /*!< [3..3] Revision A: MUST NOT be programmed! Revision B: Enable + DCX output for CE3 output. */ + __IOM uint32_t DCXEN : 1; /*!< [4..4] Revision A: MUST NOT be programmed! Revision B: Bit 4: + DCX Signaling Enable via other CE signals. The selected + DCX signal (unused CE pin) will be driven low during write + of offset byte, and high during transmission of data bytes. */ + } DCX_b; + } ; + + union { + __IOM uint32_t OFFSETHI; /*!< (@ 0x00000220) High order 2 bytes of 3 byte offset for IO transaction */ + + struct { + __IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order 2 bytes of the 3 byte addressing/offset + field to use with IO commands. The number of offset bytes + to use is specified in the command register */ + } OFFSETHI_b; + } ; + + union { + __IOM uint32_t CMDSTAT; /*!< (@ 0x00000224) Command status */ + + struct { + __IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */ + __IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */ + __IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred + with this command. This field will count down to zero. */ + } CMDSTAT_b; + } ; + __IM uint32_t RESERVED2[6]; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger + of the DMA when a command is completed. When this event + is triggered, the number of words transferred will be the + lesser of the remaining TOTCOUNT bytes, or */ + __IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations + (IOM writes), the trigger will assert when the write FIFO + has (WTHR/4) number of words free in the write FIFO, and + will transfer (WTHR/4) number of wordsor, if the number + of words left to transfer is less than the WTHR value, + will transfer the remaining byte count.For P2M DMA operations, + the trigger will assert when the read FIFO has (RTHR/4) + words available in the read FIFO, and will transfer (RTHR/4) + words to SRAM. This trigger will NOT asser */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ + + struct { + __IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read + only and can be cleared by disabling the DCMDCMP trigger + enable or by disabling DMA. */ + __IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can + be cleared by disabling the DTHR trigger enable or by disabling + DMA. */ + __IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data + in the FIFO was enough to complete the DMA operation (greater + than or equal to current TOTCOUNT) when the command completed. + This trigger is default active when the DCMDCMP trigger + isdisabled and there is enough data in the FIFO to complete + the DMA operation. */ + } DMATRIGSTAT_b; + } ; + __IM uint32_t RESERVED3[14]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA + operation. This should be the last DMA related register + set prior to issuing the command */ + __IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */ + uint32_t : 6; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DPWROFF : 1; /*!< [9..9] Power off module after DMA is complete. If this bit is + active, the module will request to power off the supply + it is attached to. If there are other units still requiring + power from the same domain, power down will not be performed. */ + } DMACFG_b; + } ; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit + is read only and can be cleared by disabling the DTHR trigger + enable or by disabling DMA. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ + + struct { + __IOM uint32_t TARGADDR : 20; /*!< [19..0] Bits [19:0] of the target byte address for source of + DMA (either read or write). The address can be any byte + alignment, and does not have to be word aligned. In cases + of non-word aligned addresses, the DMA logic will take + care for ensuring only the target bytes are read/written. */ + uint32_t : 8; + __IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA + (either read or write). In cases of non-word aligned addresses, + the DMA logic will take care for ensuring only the target + bytes are read/written.Setting to '1' will select the SRAM. + Setting to '0' will select the flash */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that + a DMA transfer is active. The DMA transfer may be waiting + on data, transferring data, or waiting for priority.All + of these will be indicated with a 1. A 0 will indicate + that the DMA is fully complete and no further transactions + will be done. This bit is read only. */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA + operation. This bit can be cleared by writing to 0, and + will also be cleared when a new DMA is started. */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals an error was + encountered during the DMA operation. The bit can be cleared + by writing to 0. Once set, this bit will remain set until + cleared by software. */ + } DMASTAT_b; + } ; + + union { + __IOM uint32_t CQCFG; /*!< (@ 0x00000294) Command Queue Configuration Register */ + + struct { + __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing + of the command queue and fetches of address/data pairs + will proceed from the word address within the CQADDR register. + Can be disabled using a CQ executed write to this bit as + well. */ + __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request */ + } CQCFG_b; + } ; + + union { + __IOM uint32_t CQADDR; /*!< (@ 0x00000298) CQ Target Read Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source of CQ. The + buffer must be aligned on a word boundary */ + uint32_t : 8; + __IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ. Used + to denote Flash (0) or SRAM (1) access */ + } CQADDR_b; + } ; + + union { + __IOM uint32_t CQSTAT; /*!< (@ 0x0000029C) Command Queue Status Register */ + + struct { + __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will + indicate that a CQ transfer is active and this will remain + active even when paused waiting for external event. */ + __IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */ + __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit + signals that an error was encountered during the CQ operation. */ + } CQSTAT_b; + } ; + + union { + __IOM uint32_t CQFLAGS; /*!< (@ 0x000002A0) Command Queue Flag Register */ + + struct { + __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software + controllable and bits [15:8] are hardware status. */ + __IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Mask the bits used to generate the command queue interrupt. + A '1' in the bit position will enable the pause event to + trigger the interrupt, if the CQWT_int interrupt is enabled. + Bits definitions are the same as CQPAUSE */ + } CQFLAGS_b; + } ; + + union { + __IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002A4) Command Queue Flag Set/Clear Register */ + + struct { + __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any + SWFLAG with a '1' in the corresponding bit position of + this field */ + __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG + with a '1' in the corresponding bit position of this field */ + } CQSETCLEAR_b; + } ; + + union { + __IOM uint32_t CQPAUSEEN; /*!< (@ 0x000002A8) Command Queue Pause Enable Register */ + + struct { + __IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing + when active */ + } CQPAUSEEN_b; + } ; + + union { + __IOM uint32_t CQCURIDX; /*!< (@ 0x000002AC) IOM Command Queue current index value . Compared + to the CQENDIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQCURIDX_b; + } ; + + union { + __IOM uint32_t CQENDIDX; /*!< (@ 0x000002B0) IOM Command Queue current index value . Compared + to the CQCURIDX reg contents to generate + the IDXEQ Pause event for command queue */ + + struct { + __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX + register field. If the values match, the IDXEQ pause event + will be activated, which will cause the pausing of command + quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ + } CQENDIDX_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x000002B4) IOM Module Status Register */ + + struct { + __IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error + indicators. This will always return 0. */ + __IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing + a transaction, or command is complete, but the FIFO pointers + are still syncronizing internally. This bit will go high + atthe start of the transaction, and will go low when the + command is complete, and the data and pointers within the + FIFO have been syncronized. */ + __IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note + - The state machine could be in idle state due to holdoffs + from data availability, or as the command gets propagated + into the logic from the registers. */ + } STATUS_b; + } ; + __IM uint32_t RESERVED5[18]; + + union { + __IOM uint32_t MSPICFG; /*!< (@ 0x00000300) SPI module master configuration */ + + struct { + __IOM uint32_t SPOL : 1; /*!< [0..0] selects SPI polarity. */ + __IOM uint32_t SPHA : 1; /*!< [1..1] selects SPI phase. */ + __IOM uint32_t FULLDUP : 1; /*!< [2..2] Enables full duplex mode for Master SPI write operations. + Data will be captured simultaneously into the read fifo */ + uint32_t : 13; + __IOM uint32_t WTFC : 1; /*!< [16..16] enables write mode flow control. */ + __IOM uint32_t RDFC : 1; /*!< [17..17] enables read mode flow control. */ + __IOM uint32_t MOSIINV : 1; /*!< [18..18] inverts MOSI when flow control is enabled. */ + uint32_t : 1; + __IOM uint32_t WTFCIRQ : 1; /*!< [20..20] selects the write mode flow control signal. */ + __IOM uint32_t WTFCPOL : 1; /*!< [21..21] selects the write flow control signal polarity. The + transfers are halted when the selected flow control signal + is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 + will allow a IRQ=1 to pause transfers). */ + __IOM uint32_t RDFCPOL : 1; /*!< [22..22] selects the read flow control signal polarity. */ + __IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first + (1) for the data portion of the SPI transaction. The offset + bytes are always transmitted MSB first. */ + __IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This + gives more hold time on the input data. */ + __IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This + give more hold time on the output data */ + __IOM uint32_t MSPIRST : 1; /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for + the module */ + } MSPICFG_b; + } ; + __IM uint32_t RESERVED6[63]; + + union { + __IOM uint32_t MI2CCFG; /*!< (@ 0x00000400) I2C Master configuration */ + + struct { + __IOM uint32_t ADDRSZ : 1; /*!< [0..0] Sets the I2C master device address size to either 7b + (0) or 10b (1). */ + __IOM uint32_t I2CLSB : 1; /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1) + first. Default per I2C specification is MSB first. This + applies to both read and write data, and read data will + be bit */ + __IOM uint32_t ARBEN : 1; /*!< [2..2] Enables multi-master arbitration for the I2C master. + If the bus is known to have only a single master, this + function can be disabled to save clock cycles on I2C transactions */ + uint32_t : 1; + __IOM uint32_t SDADLY : 2; /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3. */ + __IOM uint32_t MI2CRST : 1; /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for + the module */ + uint32_t : 1; + __IOM uint32_t SCLENDLY : 4; /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the + SCL output en (clock will go low on this edge). Used to + allow clock shaping. */ + __IOM uint32_t SDAENDLY : 4; /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all + transitions affected). Used to delay data relative to clock */ + __IOM uint32_t SMPCNT : 8; /*!< [23..16] Number of Base clk cycles to wait before sampling the + SCL clock to determine if a clock stretch event has occured */ + __IOM uint32_t STRDIS : 1; /*!< [24..24] Disable detection of clock stretch events smaller than + 1 cycle */ + } MI2CCFG_b; + } ; + + union { + __IOM uint32_t DEVCFG; /*!< (@ 0x00000404) I2C Device Configuration register */ + + struct { + __IOM uint32_t DEVADDR : 10; /*!< [9..0] I2C address of the device that the Master will use to + target for read/write operations. This can be either a + 7b or 10b address. */ + } DEVCFG_b; + } ; + __IM uint32_t RESERVED7[2]; + + union { + __IOM uint32_t IOMDBG; /*!< (@ 0x00000410) IOM Debug Register */ + + struct { + __IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting bit will enable the update of data + within this register, otherwise it is clock gated for power + savings */ + __IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active + when this bit is '1'. Otherwise, the clock is controlled + with gating from the logic as needed. */ + __IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used + to select between different debug data available in the + DBG0 and DBG1 registers. */ + } IOMDBG_b; + } ; +} IOM0_Type; /*!< Size = 1044 (0x414) */ + + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C/SPI Slave (IOSLAVE) + */ + +typedef struct { /*!< (@ 0x50000000) IOSLAVE Structure */ + __IM uint32_t RESERVED[64]; + + union { + __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointer */ + + struct { + __IOM uint32_t FIFOPTR : 8; /*!< [7..0] Current FIFO pointer. */ + __IOM uint32_t FIFOSIZ : 8; /*!< [15..8] The number of bytes currently in the hardware FIFO. */ + } FIFOPTR_b; + } ; + + union { + __IOM uint32_t FIFOCFG; /*!< (@ 0x00000104) FIFO Configuration */ + + struct { + __IOM uint32_t FIFOBASE : 5; /*!< [4..0] These bits hold the base address of the I/O FIFO in 8 + byte segments. The IO Slave FIFO is situated in LRAM at + (FIFOBASE*8) to (FIFOMAX*8-1). */ + uint32_t : 3; + __IOM uint32_t FIFOMAX : 6; /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments. + It is also the beginning of the RAM area of the LRAM. Note + that no RAM area is configured if FIFOMAX is set to 0x1F. */ + uint32_t : 10; + __IOM uint32_t ROBASE : 6; /*!< [29..24] Defines the read-only area. The IO Slave read-only + area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1) */ + } FIFOCFG_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */ + + struct { + __IOM uint32_t FIFOTHR : 8; /*!< [7..0] FIFO size interrupt threshold. */ + } FIFOTHR_b; + } ; + + union { + __IOM uint32_t FUPD; /*!< (@ 0x0000010C) FIFO Update Status */ + + struct { + __IOM uint32_t FIFOUPD : 1; /*!< [0..0] This bit indicates that a FIFO update is underway. */ + __IOM uint32_t IOREAD : 1; /*!< [1..1] This bitfield indicates an IO read is active. */ + } FUPD_b; + } ; + + union { + __IOM uint32_t FIFOCTR; /*!< (@ 0x00000110) Overall FIFO Counter */ + + struct { + __IOM uint32_t FIFOCTR : 10; /*!< [9..0] Virtual FIFO byte count */ + } FIFOCTR_b; + } ; + + union { + __IOM uint32_t FIFOINC; /*!< (@ 0x00000114) Overall FIFO Counter Increment */ + + struct { + __IOM uint32_t FIFOINC : 10; /*!< [9..0] Increment the Overall FIFO Counter by this value on a + write */ + } FIFOINC_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000118) I/O Slave Configuration */ + + struct { + __IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */ + __IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */ + __IOM uint32_t LSB : 1; /*!< [2..2] This bit selects the transfer bit ordering. */ + uint32_t : 1; + __IOM uint32_t STARTRD : 1; /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read. */ + uint32_t : 3; + __IOM uint32_t I2CADDR : 12; /*!< [19..8] 7-bit or 10-bit I2C device address. */ + uint32_t : 11; + __IOM uint32_t IFCEN : 1; /*!< [31..31] IOSLAVE interface enable. */ + } CFG_b; + } ; + + union { + __IOM uint32_t PRENC; /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode */ + + struct { + __IOM uint32_t PRENC : 5; /*!< [4..0] These bits hold the priority encode of the REGACC interrupts. */ + } PRENC_b; + } ; + + union { + __IOM uint32_t IOINTCTL; /*!< (@ 0x00000120) I/O Interrupt Control */ + + struct { + __IOM uint32_t IOINTEN : 8; /*!< [7..0] These read-only bits indicate whether the IOINT interrupts + are enabled. */ + __IOM uint32_t IOINT : 8; /*!< [15..8] These bits read the IOINT interrupts. */ + __IOM uint32_t IOINTCLR : 1; /*!< [16..16] This bit clears all of the IOINT interrupts when written + with a 1. */ + uint32_t : 7; + __IOM uint32_t IOINTSET : 8; /*!< [31..24] These bits set the IOINT interrupts when written with + a 1. */ + } IOINTCTL_b; + } ; + + union { + __IOM uint32_t GENADD; /*!< (@ 0x00000124) General Address Data */ + + struct { + __IOM uint32_t GADATA : 8; /*!< [7..0] The data supplied on the last General Address reference. */ + } GENADD_b; + } ; + __IM uint32_t RESERVED1[54]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Slave Interrupts: Enable */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Slave Interrupts: Status */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Slave Interrupts: Clear */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Slave Interrupts: Set */ + + struct { + __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ + __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ + __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ + __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ + __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ + __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ + __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ + __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ + __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ + __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ + } INTSET_b; + } ; + + union { + __IOM uint32_t REGACCINTEN; /*!< (@ 0x00000210) Register Access Interrupts: Enable */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTEN_b; + } ; + + union { + __IOM uint32_t REGACCINTSTAT; /*!< (@ 0x00000214) Register Access Interrupts: Status */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTSTAT_b; + } ; + + union { + __IOM uint32_t REGACCINTCLR; /*!< (@ 0x00000218) Register Access Interrupts: Clear */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTCLR_b; + } ; + + union { + __IOM uint32_t REGACCINTSET; /*!< (@ 0x0000021C) Register Access Interrupts: Set */ + + struct { + __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ + } REGACCINTSET_b; + } ; +} IOSLAVE_Type; /*!< Size = 544 (0x220) */ + + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU Miscellaneous Control Logic (MCUCTRL) + */ + +typedef struct { /*!< (@ 0x40020000) MCUCTRL Structure */ + + union { + __IOM uint32_t CHIPPN; /*!< (@ 0x00000000) Chip Information Register */ + + struct { + __IOM uint32_t PARTNUM : 32; /*!< [31..0] BCD part number. */ + } CHIPPN_b; + } ; + + union { + __IOM uint32_t CHIPID0; /*!< (@ 0x00000004) Unique Chip ID 0 */ + + struct { + __IOM uint32_t CHIPID0 : 32; /*!< [31..0] Unique chip ID 0. */ + } CHIPID0_b; + } ; + + union { + __IOM uint32_t CHIPID1; /*!< (@ 0x00000008) Unique Chip ID 1 */ + + struct { + __IOM uint32_t CHIPID1 : 32; /*!< [31..0] Unique chip ID 1. */ + } CHIPID1_b; + } ; + + union { + __IOM uint32_t CHIPREV; /*!< (@ 0x0000000C) Chip Revision */ + + struct { + __IOM uint32_t REVMIN : 4; /*!< [3..0] Minor Revision ID. */ + __IOM uint32_t REVMAJ : 4; /*!< [7..4] Major Revision ID. */ + __IOM uint32_t SIPART : 12; /*!< [19..8] Silicon Part ID */ + } CHIPREV_b; + } ; + + union { + __IOM uint32_t VENDORID; /*!< (@ 0x00000010) Unique Vendor ID */ + + struct { + __IOM uint32_t VENDORID : 32; /*!< [31..0] Unique Vendor ID */ + } VENDORID_b; + } ; + + union { + __IOM uint32_t SKU; /*!< (@ 0x00000014) Unique Chip SKU */ + + struct { + __IOM uint32_t ALLOWBURST : 1; /*!< [0..0] Allow Burst feature */ + __IOM uint32_t ALLOWBLE : 1; /*!< [1..1] Allow BLE feature */ + __IOM uint32_t SECBOOT : 1; /*!< [2..2] Secure boot feature allowed */ + } SKU_b; + } ; + + union { + __IOM uint32_t FEATUREENABLE; /*!< (@ 0x00000018) Feature Enable on Burst and BLE */ + + struct { + __IOM uint32_t BLEREQ : 1; /*!< [0..0] Controls the BLE functionality */ + __IOM uint32_t BLEACK : 1; /*!< [1..1] ACK for BLEREQ */ + __IOM uint32_t BLEAVAIL : 1; /*!< [2..2] AVAILABILITY of the BLE functionality */ + uint32_t : 1; + __IOM uint32_t BURSTREQ : 1; /*!< [4..4] Controls the Burst functionality */ + __IOM uint32_t BURSTACK : 1; /*!< [5..5] ACK for BURSTREQ */ + __IOM uint32_t BURSTAVAIL : 1; /*!< [6..6] Availability of Burst functionality */ + } FEATUREENABLE_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t DEBUGGER; /*!< (@ 0x00000020) Debugger Control */ + + struct { + __IOM uint32_t LOCKOUT : 1; /*!< [0..0] Lockout of debugger (SWD). */ + } DEBUGGER_b; + } ; + __IM uint32_t RESERVED1[55]; + + union { + __IOM uint32_t BODCTRL; /*!< (@ 0x00000100) BOD control Register */ + + struct { + __IOM uint32_t BODLPWD : 1; /*!< [0..0] BODL Power Down. */ + __IOM uint32_t BODHPWD : 1; /*!< [1..1] BODH Power Down. */ + __IOM uint32_t BODCPWD : 1; /*!< [2..2] BODC Power Down. */ + __IOM uint32_t BODFPWD : 1; /*!< [3..3] BODF Power Down. */ + __IOM uint32_t BODLVREFSEL : 1; /*!< [4..4] BODL External Reference Select. Note: the SWE mux select + in PWRSEQ2SWE must be set for this to take effect. */ + __IOM uint32_t BODHVREFSEL : 1; /*!< [5..5] BODH External Reference Select. Note: the SWE mux select + in PWRSEQ2SWE must be set for this to take effect. */ + } BODCTRL_b; + } ; + + union { + __IOM uint32_t ADCPWRDLY; /*!< (@ 0x00000104) ADC Power Up Delay Control */ + + struct { + __IOM uint32_t ADCPWR0 : 8; /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK + increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments + for ADC_CLKSEL = 0x2. */ + __IOM uint32_t ADCPWR1 : 8; /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments + for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL + = 0x2. */ + } ADCPWRDLY_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t ADCCAL; /*!< (@ 0x0000010C) ADC Calibration Control */ + + struct { + __IOM uint32_t CALONPWRUP : 1; /*!< [0..0] Run ADC Calibration on initial power up sequence */ + __IOM uint32_t ADCCALIBRATED : 1; /*!< [1..1] Status for ADC Calibration */ + } ADCCAL_b; + } ; + + union { + __IOM uint32_t ADCBATTLOAD; /*!< (@ 0x00000110) ADC Battery Load Enable */ + + struct { + __IOM uint32_t BATTLOAD : 1; /*!< [0..0] Enable the ADC battery load resistor */ + } ADCBATTLOAD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t ADCTRIM; /*!< (@ 0x00000118) ADC Trims */ + + struct { + __IOM uint32_t ADCREFKEEPIBTRIM : 2; /*!< [1..0] ADC Reference Ibias trim */ + uint32_t : 4; + __IOM uint32_t ADCREFBUFTRIM : 5; /*!< [10..6] ADC Reference buffer trim */ + __IOM uint32_t ADCRFBUFIBTRIM : 2; /*!< [12..11] ADC reference buffer input bias trim */ + } ADCTRIM_b; + } ; + + union { + __IOM uint32_t ADCREFCOMP; /*!< (@ 0x0000011C) ADC Reference Keeper and Comparator Control */ + + struct { + __IOM uint32_t ADC_REFCOMP_OUT : 1; /*!< [0..0] Output of the ADC reference comparator */ + uint32_t : 7; + __IOM uint32_t ADCREFKEEPTRIM : 5; /*!< [12..8] ADC Reference Keeper Trim */ + uint32_t : 3; + __IOM uint32_t ADCRFCMPEN : 1; /*!< [16..16] ADC Reference comparator power down */ + } ADCREFCOMP_b; + } ; + + union { + __IOM uint32_t XTALCTRL; /*!< (@ 0x00000120) XTAL Oscillator Control */ + + struct { + __IOM uint32_t XTALSWE : 1; /*!< [0..0] XTAL Software Override Enable. */ + __IOM uint32_t FDBKDSBLXTAL : 1; /*!< [1..1] XTAL Oscillator Disable Feedback. */ + __IOM uint32_t BYPCMPRXTAL : 1; /*!< [2..2] XTAL Oscillator Bypass Comparator. */ + __IOM uint32_t PDNBCOREXTAL : 1; /*!< [3..3] XTAL Oscillator Power Down Core. */ + __IOM uint32_t PDNBCMPRXTAL : 1; /*!< [4..4] XTAL Oscillator Power Down Comparator. */ + __IOM uint32_t PWDBODXTAL : 1; /*!< [5..5] XTAL Power down on brown out. */ + __IOM uint32_t XTALIBUFTRIM : 2; /*!< [7..6] XTAL IBUFF trim */ + __IOM uint32_t XTALICOMPTRIM : 2; /*!< [9..8] XTAL ICOMP trim */ + } XTALCTRL_b; + } ; + + union { + __IOM uint32_t XTALGENCTRL; /*!< (@ 0x00000124) XTAL Oscillator General Control */ + + struct { + __IOM uint32_t ACWARMUP : 2; /*!< [1..0] Auto-calibration delay control */ + __IOM uint32_t XTALBIASTRIM : 6; /*!< [7..2] XTAL BIAS trim */ + __IOM uint32_t XTALKSBIASTRIM : 6; /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used + during the startup process to enable a faster lock. */ + } XTALGENCTRL_b; + } ; + __IM uint32_t RESERVED4[28]; + + union { + __IOM uint32_t MISCCTRL; /*!< (@ 0x00000198) Miscellaneous control register. */ + + struct { + __IOM uint32_t RESERVED_RW_0 : 5; /*!< [4..0] Reserved bits, always leave unchanged. The MISCCTRL register + must be modified via atomic RMW, leaving this bit field + completely unmodified. Failure to do so will result in + unpredictable behavior. */ + __IOM uint32_t BLE_RESETN : 1; /*!< [5..5] BLE reset signal. */ + } MISCCTRL_b; + } ; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t BOOTLOADER; /*!< (@ 0x000001A0) Bootloader and secure boot functions */ + + struct { + __IOM uint32_t BOOTLOADERLOW : 1; /*!< [0..0] Determines whether the bootloader code is visible at + address 0x00000000 or not. Resets to 1, write 1 to clear. */ + __IOM uint32_t SBLOCK : 1; /*!< [1..1] Secure boot lock. Always resets to 1, write 1 to clear. + Enables system visibility to bootloader until set. */ + __IOM uint32_t PROTLOCK : 1; /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to + clear. Enables writes to flash protection register set. */ + uint32_t : 23; + __IOM uint32_t SECBOOTFEATURE : 2; /*!< [27..26] Indicates whether the secure boot feature is enabled. */ + __IOM uint32_t SECBOOT : 2; /*!< [29..28] Indicates whether the secure boot on cold reset is + enabled */ + __IOM uint32_t SECBOOTONRST : 2; /*!< [31..30] Indicates whether the secure boot on warm reset is + enabled */ + } BOOTLOADER_b; + } ; + + union { + __IOM uint32_t SHADOWVALID; /*!< (@ 0x000001A4) Register to indicate whether the shadow registers + have been successfully loaded from the Flash + Information Space. */ + + struct { + __IOM uint32_t VALID : 1; /*!< [0..0] Indicates whether the shadow registers contain valid + data from the Flash Information Space. */ + __IOM uint32_t BLDSLEEP : 1; /*!< [1..1] Indicates whether the bootloader should sleep or deep + sleep if no image loaded. */ + __IOM uint32_t INFO0_VALID : 1; /*!< [2..2] Indicates whether INFO0 contains valid data */ + } SHADOWVALID_b; + } ; + __IM uint32_t RESERVED6[2]; + + union { + __IOM uint32_t SCRATCH0; /*!< (@ 0x000001B0) Scratch register that is not reset by any reset */ + + struct { + __IOM uint32_t SCRATCH0 : 32; /*!< [31..0] Scratch register 0. */ + } SCRATCH0_b; + } ; + + union { + __IOM uint32_t SCRATCH1; /*!< (@ 0x000001B4) Scratch register that is not reset by any reset */ + + struct { + __IOM uint32_t SCRATCH1 : 32; /*!< [31..0] Scratch register 1. */ + } SCRATCH1_b; + } ; + __IM uint32_t RESERVED7[2]; + + union { + __IOM uint32_t ICODEFAULTADDR; /*!< (@ 0x000001C0) ICODE bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t ICODEFAULTADDR : 32; /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } ICODEFAULTADDR_b; + } ; + + union { + __IOM uint32_t DCODEFAULTADDR; /*!< (@ 0x000001C4) DCODE bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t DCODEFAULTADDR : 32; /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } DCODEFAULTADDR_b; + } ; + + union { + __IOM uint32_t SYSFAULTADDR; /*!< (@ 0x000001C8) System bus address which was present when a bus + fault occurred. */ + + struct { + __IOM uint32_t SYSFAULTADDR : 32; /*!< [31..0] SYS bus address observed when a Bus Fault occurred. + Once an address is captured in this field, it is held until + the corresponding Fault Observed bit is cleared in the + FAULTSTATUS register. */ + } SYSFAULTADDR_b; + } ; + + union { + __IOM uint32_t FAULTSTATUS; /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault + detection. Any write to this register will + clear all of the status bits within the + register. */ + + struct { + __IOM uint32_t ICODEFAULT : 1; /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a + fault has been detected, and the ICODEFAULTADDR register + will contain the bus address which generated the fault. */ + __IOM uint32_t DCODEFAULT : 1; /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault + has been detected, and the DCODEFAULTADDR register will + contain the bus address which generated the fault. */ + __IOM uint32_t SYSFAULT : 1; /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault + has been detected, and the SYSFAULTADDR register will contain + the bus address which generated the fault. */ + } FAULTSTATUS_b; + } ; + + union { + __IOM uint32_t FAULTCAPTUREEN; /*!< (@ 0x000001D0) Enable the fault capture registers */ + + struct { + __IOM uint32_t FAULTCAPTUREEN : 1; /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture + monitors are enabled and addresses which generate a hard + fault are captured into the FAULTADDR registers. */ + } FAULTCAPTUREEN_b; + } ; + __IM uint32_t RESERVED8[11]; + + union { + __IOM uint32_t DBGR1; /*!< (@ 0x00000200) Read-only debug register 1 */ + + struct { + __IOM uint32_t ONETO8 : 32; /*!< [31..0] Read-only register for communication validation */ + } DBGR1_b; + } ; + + union { + __IOM uint32_t DBGR2; /*!< (@ 0x00000204) Read-only debug register 2 */ + + struct { + __IOM uint32_t COOLCODE : 32; /*!< [31..0] Read-only register for communication validation */ + } DBGR2_b; + } ; + __IM uint32_t RESERVED9[6]; + + union { + __IOM uint32_t PMUENABLE; /*!< (@ 0x00000220) Control bit to enable/disable the PMU */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will + place the MCU into the lowest power consuming Deep Sleep + mode upon execution of a WFI instruction (dependent on + the setting of the SLEEPDEEP bit in the ARM SCR register). + When cleared, regardless of the requested sleep mode, the + PMU will not enter the lowest power Deep Sleep mode, instead + entering the Sleep mode. */ + } PMUENABLE_b; + } ; + __IM uint32_t RESERVED10[11]; + + union { + __IOM uint32_t TPIUCTRL; /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable + and frequency for the M4's TPIU interface. */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled + and data can be streamed out of the MCU's SWO port using + the ARM ITM and TPIU modules. */ + uint32_t : 7; + __IOM uint32_t CLKSEL : 3; /*!< [10..8] This field selects the frequency of the ARM M4 TPIU + port. */ + } TPIUCTRL_b; + } ; + __IM uint32_t RESERVED11[4]; + + union { + __IOM uint32_t OTAPOINTER; /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset + only by POA */ + + struct { + __IOM uint32_t OTAVALID : 1; /*!< [0..0] Indicates that an OTA update is valid */ + __IOM uint32_t OTASBLUPDATE : 1; /*!< [1..1] Indicates that the sbl_init has been updated */ + __IOM uint32_t OTAPOINTER : 30; /*!< [31..2] Flash page pointer with updated OTA image */ + } OTAPOINTER_b; + } ; + __IM uint32_t RESERVED12[6]; + + union { + __IOM uint32_t APBDMACTRL; /*!< (@ 0x00000280) DMA Control Register. Determines misc settings + for DMA operation */ + + struct { + __IOM uint32_t DMA_ENABLE : 1; /*!< [0..0] Enable the DMA controller. When disabled, DMA requests + will be ignored by the controller */ + __IOM uint32_t DECODEABORT : 1; /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue + a data abort (bus fault) on transactions to peripherals + that are powered down. When set to 0, writes are quietly + discarded and reads return 0. */ + uint32_t : 6; + __IOM uint32_t HYSTERESIS : 8; /*!< [15..8] This field determines how long the DMA will remain active + during deep sleep before shutting down and returning the + system to full deep sleep. Values are based on a 94KHz + clock and are roughly 10 us increments for a range of ~10 + us to 2.55 ms */ + } APBDMACTRL_b; + } ; + + union { + __IOM uint32_t SRAMMODE; /*!< (@ 0x00000284) SRAM Controller mode bits */ + + struct { + __IOM uint32_t IPREFETCH : 1; /*!< [0..0] When set, instruction accesses to the SRAM banks will + be pre-fetched (normally 2 cycle read access). Generally, + this mode bit should be set for improved performance when + executing instructions from SRAM. */ + __IOM uint32_t IPREFETCH_CACHE : 1; /*!< [1..1] Secondary pre-fetch feature that will cache pre-fetched + data across bus wait states (requires IPREFETCH to be set). */ + uint32_t : 2; + __IOM uint32_t DPREFETCH : 1; /*!< [4..4] When set, data bus accesses to the SRAM banks will be + pre-fetched (normally 2 cycle read access). Use of this + mode bit is only recommended if the work flow has a large + number of sequential accesses. */ + __IOM uint32_t DPREFETCH_CACHE : 1; /*!< [5..5] Secondary pre-fetch feature that will cache pre-fetched + data across bus wait states (requires DPREFETCH to be set). */ + } SRAMMODE_b; + } ; + __IM uint32_t RESERVED13[48]; + + union { + __IOM uint32_t KEXTCLKSEL; /*!< (@ 0x00000348) Key Register to enable the use of external clock + selects via the EXTCLKSEL reg */ + + struct { + __IOM uint32_t KEXTCLKSEL : 32; /*!< [31..0] Key register value. */ + } KEXTCLKSEL_b; + } ; + __IM uint32_t RESERVED14[2]; + + union { + __IOM uint32_t SIMOBUCK2; /*!< (@ 0x00000354) SIMO Buck Control Reg 2 */ + + struct { + __IOM uint32_t RESERVED_RW_0 : 16; /*!< [15..0] Reserved bits, always leave unchanged. The SIMOBUCK2 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + __IOM uint32_t SIMOBUCKCORELPHIGHTONTRIM : 4;/*!< [19..16] simobuck_core_lp_high_ton_trim */ + __IOM uint32_t SIMOBUCKCORELPLOWTONTRIM : 4;/*!< [23..20] simobuck_core_lp_low_ton_trim */ + __IOM uint32_t RESERVED_RW_24 : 8; /*!< [31..24] Reserved bits, always leave unchanged. The SIMOBUCK2 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + } SIMOBUCK2_b; + } ; + + union { + __IOM uint32_t SIMOBUCK3; /*!< (@ 0x00000358) SIMO Buck Control Reg 3 */ + + struct { + __IOM uint32_t SIMOBUCKCORELPHIGHTOFFTRIM : 4;/*!< [3..0] simobuck_core_lp_high_toff_trim */ + __IOM uint32_t SIMOBUCKCORELPLOWTOFFTRIM : 4;/*!< [7..4] simobuck_core_lp_low_toff_trim */ + __IOM uint32_t SIMOBUCKMEMLPHIGHTOFFTRIM : 4;/*!< [11..8] simobuck_mem_lp_high_toff_trim */ + __IOM uint32_t SIMOBUCKMEMLPLOWTOFFTRIM : 4;/*!< [15..12] simobuck_mem_lp_low_toff_trim */ + __IOM uint32_t RESERVED_RW_16 : 11; /*!< [26..16] Reserved bits, always leave unchanged. The SIMOBUCK3 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + __IOM uint32_t SIMOBUCKMEMLPHIGHTONTRIM : 4;/*!< [30..27] simobuck_mem_lp_high_ton_trim */ + __IOM uint32_t RESERVED_RW_31 : 1; /*!< [31..31] Reserved bits, always leave unchanged. The SIMOBUCK2 + register must be modified via atomic RMW, leaving this + bit field completely unmodified. Failure to do so will + result in unpredictable behavior. */ + } SIMOBUCK3_b; + } ; + + union { + __IOM uint32_t SIMOBUCK4; /*!< (@ 0x0000035C) SIMO Buck Control Reg 4 */ + + struct { + __IOM uint32_t SIMOBUCKMEMLPLOWTONTRIM : 4;/*!< [3..0] simobuck_mem_lp_low_ton_trim */ + uint32_t : 17; + __IOM uint32_t SIMOBUCKCLKDIVSEL : 2; /*!< [22..21] simobuck_clkdiv_sel */ + uint32_t : 1; + __IOM uint32_t SIMOBUCKCOMP2TIMEOUTEN : 1;/*!< [24..24] simobuck_comp2_timeout_en */ + } SIMOBUCK4_b; + } ; + __IM uint32_t RESERVED15[2]; + + union { + __IOM uint32_t BLEBUCK2; /*!< (@ 0x00000368) BLEBUCK2 Control Reg */ + + struct { + __IOM uint32_t BLEBUCKTONLOWTRIM : 6; /*!< [5..0] blebuck_ton_low_trim */ + __IOM uint32_t BLEBUCKTONHITRIM : 6; /*!< [11..6] blebuck_ton_hi_trim */ + __IOM uint32_t BLEBUCKTOND2ATRIM : 6; /*!< [17..12] blebuck_ton_trim */ + } BLEBUCK2_b; + } ; + __IM uint32_t RESERVED16[13]; + + union { + __IOM uint32_t FLASHWPROT0; /*!< (@ 0x000003A0) Flash Write Protection Bits */ + + struct { + __IOM uint32_t FW0BITS : 32; /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit + provides write protection for 16KB chunks of flash data + space. Bits are cleared by writing a 1 to the bit. When + read, 0 indicates the region is protected. Bits are sticky + (can be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHWPROT0_b; + } ; + + union { + __IOM uint32_t FLASHWPROT1; /*!< (@ 0x000003A4) Flash Write Protection Bits */ + + struct { + __IOM uint32_t FW1BITS : 32; /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit + provides write protection for 16KB chunks of flash data + space. Bits are cleared by writing a 1 to the bit. When + read, 0 indicates the region is protected. Bits are sticky + (can be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHWPROT1_b; + } ; + __IM uint32_t RESERVED17[2]; + + union { + __IOM uint32_t FLASHRPROT0; /*!< (@ 0x000003B0) Flash Read Protection Bits */ + + struct { + __IOM uint32_t FR0BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each + bit provides read protection for 16KB chunks of flash. + Bits are cleared by writing a 1 to the bit. When read, + 0 indicates the region is protected. Bits are sticky (can + be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHRPROT0_b; + } ; + + union { + __IOM uint32_t FLASHRPROT1; /*!< (@ 0x000003B4) Flash Read Protection Bits */ + + struct { + __IOM uint32_t FR1BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each + bit provides read protection for 16KB chunks of flash. + Bits are cleared by writing a 1 to the bit. When read, + 0 indicates the region is protected. Bits are sticky (can + be set when PROTLOCK is 1, but only cleared by reset) */ + } FLASHRPROT1_b; + } ; + __IM uint32_t RESERVED18[2]; + + union { + __IOM uint32_t DMASRAMWRITEPROTECT0; /*!< (@ 0x000003C0) SRAM write-protection bits. */ + + struct { + __IOM uint32_t DMA_WPROT0 : 32; /*!< [31..0] Write protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA writes, when set + to 0, DMA may write the region. */ + } DMASRAMWRITEPROTECT0_b; + } ; + + union { + __IOM uint32_t DMASRAMWRITEPROTECT1; /*!< (@ 0x000003C4) SRAM write-protection bits. */ + + struct { + __IOM uint32_t DMA_WPROT1 : 16; /*!< [15..0] Write protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA writes, when set + to 0, DMA may write the region. */ + } DMASRAMWRITEPROTECT1_b; + } ; + __IM uint32_t RESERVED19[2]; + + union { + __IOM uint32_t DMASRAMREADPROTECT0; /*!< (@ 0x000003D0) SRAM read-protection bits. */ + + struct { + __IOM uint32_t DMA_RPROT0 : 32; /*!< [31..0] Read protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA reads, when set to + 0, DMA may read the region. */ + } DMASRAMREADPROTECT0_b; + } ; + + union { + __IOM uint32_t DMASRAMREADPROTECT1; /*!< (@ 0x000003D4) SRAM read-protection bits. */ + + struct { + __IOM uint32_t DMA_RPROT1 : 16; /*!< [15..0] Read protect SRAM from DMA. Each bit provides write + protection for an 8KB region of memory. When set to 1, + the region will be protected from DMA reads, when set to + 0, DMA may read the region. */ + } DMASRAMREADPROTECT1_b; + } ; +} MCUCTRL_Type; /*!< Size = 984 (0x3d8) */ + + + +/* =========================================================================================================================== */ +/* ================ MSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Multi-bit SPI Master (MSPI) + */ + +typedef struct { /*!< (@ 0x50014000) MSPI Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) MSPI PIO Transfer Control/Status */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically + the entire register should be written at once with this + bit set). */ + __IOM uint32_t STATUS : 1; /*!< [1..1] Command status: 1 indicates command has completed. Cleared + by writing 1 to this bit or starting a new transfer. */ + __IOM uint32_t BUSY : 1; /*!< [2..2] Command status: 1 indicates controller is busy (command + in progress) */ + __IOM uint32_t QUADCMD : 1; /*!< [3..3] Flag indicating that the operation is a command that + should be replicated to both devices in paired QUAD mode. + This is typically only used when reading/writing configuration + registers in paired flash devices (do not set for memory + transfers). */ + uint32_t : 2; + __IOM uint32_t BIGENDIAN : 1; /*!< [6..6] 1 indicates data in FIFO is in big endian format (MSB + first); 0 indicates little endian data (default, LSB first). */ + __IOM uint32_t ENTURN : 1; /*!< [7..7] Indicates whether TX->RX turnaround cycles should be + enabled for this operation (see TURNAROUND field in CFG + register). */ + __IOM uint32_t SENDA : 1; /*!< [8..8] Indicates whether an address phase should be sent (see + ADDR register and ASIZE field in CFG register) */ + __IOM uint32_t SENDI : 1; /*!< [9..9] Indicates whether an instruction phase should be sent + (see INSTR field and ISIZE field in CFG register) */ + __IOM uint32_t TXRX : 1; /*!< [10..10] 1 Indicates a TX operation, 0 indicates an RX operation + of XFERBYTES */ + __IOM uint32_t PIOSCRAMBLE : 1; /*!< [11..11] Enables data scrambling for PIO operations. This should + only be used for data operations and never for commands + to a device. */ + uint32_t : 4; + __IOM uint32_t XFERBYTES : 16; /*!< [31..16] Number of bytes to transmit or receive (based on TXRX + bit) */ + } CTRL_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000004) MSPI Transfer Configuration */ + + struct { + __IOM uint32_t DEVCFG : 4; /*!< [3..0] Flash configuration for XIP and AUTO DMA operations. + Controls value for SER (Slave Enable) for XIP operations + and address generation for DMA/XIP modes. Also used to + configure SPIFRF (frame format). */ + __IOM uint32_t ASIZE : 2; /*!< [5..4] Address Size. Address bytes to send from ADDR register */ + __IOM uint32_t ISIZE : 1; /*!< [6..6] Instruction Sizeenum name = I8 value = 0x0 desc = Instruction + is 1 byteenum name = I16 value = 0x1 desc = Instruction + is 2 bytes */ + __IOM uint32_t SEPIO : 1; /*!< [7..7] Separate IO configuration. This bit should be set when + the target device has separate MOSI and MISO pins. Respective + IN/OUT bits below should be set to map pins. */ + __IOM uint32_t TURNAROUND : 6; /*!< [13..8] Number of turnaround cycles (for TX->RX transitions). + Qualified by ENTURN or XIPENTURN bit field. */ + uint32_t : 2; + __IOM uint32_t CPHA : 1; /*!< [16..16] Serial clock phase. */ + __IOM uint32_t CPOL : 1; /*!< [17..17] Serial clock polarity. */ + } CFG_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x00000008) MSPI Transfer Address */ + + struct { + __IOM uint32_t ADDR : 32; /*!< [31..0] Optional Address field to send (after optional instruction + field) - qualified by ASIZE in CMD register. NOTE: This + register is aliased to DMADEVADDR. */ + } ADDR_b; + } ; + + union { + __IOM uint32_t INSTR; /*!< (@ 0x0000000C) MSPI Transfer Instruction */ + + struct { + __IOM uint32_t INSTR : 16; /*!< [15..0] Optional Instruction field to send (1st byte) - qualified + by ISEND/ISIZE */ + } INSTR_b; + } ; + + union { + __IOM uint32_t TXFIFO; /*!< (@ 0x00000010) TX Data FIFO */ + + struct { + __IOM uint32_t TXFIFO : 32; /*!< [31..0] Data to be transmitted. Data should normally be aligned + to the LSB (pad the upper bits with zeros) unless BIGENDIAN + is set. */ + } TXFIFO_b; + } ; + + union { + __IOM uint32_t RXFIFO; /*!< (@ 0x00000014) RX Data FIFO */ + + struct { + __IOM uint32_t RXFIFO : 32; /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros + on upper bits) unless BIGENDIAN is set. */ + } RXFIFO_b; + } ; + + union { + __IOM uint32_t TXENTRIES; /*!< (@ 0x00000018) TX FIFO Entries */ + + struct { + __IOM uint32_t TXENTRIES : 5; /*!< [4..0] Number of 32-bit words/entries in TX FIFO */ + } TXENTRIES_b; + } ; + + union { + __IOM uint32_t RXENTRIES; /*!< (@ 0x0000001C) RX FIFO Entries */ + + struct { + __IOM uint32_t RXENTRIES : 5; /*!< [4..0] Number of 32-bit words/entries in RX FIFO */ + } RXENTRIES_b; + } ; + + union { + __IOM uint32_t THRESHOLD; /*!< (@ 0x00000020) TX/RX FIFO Threshold Levels */ + + struct { + __IOM uint32_t TXTHRESH : 5; /*!< [4..0] Number of entries in TX FIFO that cause TXF interrupt */ + uint32_t : 3; + __IOM uint32_t RXTHRESH : 5; /*!< [12..8] Number of entries in TX FIFO that cause RXE interrupt */ + } THRESHOLD_b; + } ; + __IM uint32_t RESERVED[55]; + + union { + __IOM uint32_t MSPICFG; /*!< (@ 0x00000100) MSPI Module Configuration */ + + struct { + __IOM uint32_t APBCLK : 1; /*!< [0..0] Enable continuous APB clock. For power-efficient operation, + APBCLK should be set to 0. */ + __IOM uint32_t RXCAP : 1; /*!< [1..1] Controls RX data capture phase. A setting of 0 (NORMAL) + captures read data at the normal capture point relative + to the internal clock launch point. However, to accommodate + chip/pad/board delays, a setting of RXCAP of 1 is expected + to be used to align the capture point with the return data + window. This bit is used in conjunction with RXNEG to provide + 4 unique capture points, all about 10 ns apart. */ + __IOM uint32_t RXNEG : 1; /*!< [2..2] Adjusts the RX capture phase to the negedge of the 48MHz + internal clock (~10 ns early). For normal operation, it + is expected that RXNEG will be set to 0. */ + __IOM uint32_t TXNEG : 1; /*!< [3..3] Launches TX data a half clock cycle (~10 ns) early. This + should normally be programmed to zero (NORMAL). */ + __IOM uint32_t IOMSEL : 3; /*!< [6..4] Selects which IOM is selected for CQ handshake status. */ + uint32_t : 1; + __IOM uint32_t CLKDIV : 6; /*!< [13..8] Clock Divider. Allows dividing 48 MHz base clock by + integer multiples. Enumerations are provided for common + frequency, but any integer divide from 48 MHz is allowed. + Odd divide ratios will result in a 33/66 percent duty cycle + with a long low clock pulse (to allow longer round-trip + for read data). */ + uint32_t : 15; + __IOM uint32_t FIFORESET : 1; /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal + operation. May be used to manually flush the FIFO in error + handling. */ + __IOM uint32_t IPRSTN : 1; /*!< [30..30] IP block reset. Write to 0 to put the transfer module + in reset or 1 for normal operation. This may be required + after error conditions to clear the transfer on the bus. */ + __IOM uint32_t PRSTN : 1; /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module + (DMA, XIP, and transfer state machines). 1=normal operation, + 0=in reset. */ + } MSPICFG_b; + } ; + + union { + __IOM uint32_t PADCFG; /*!< (@ 0x00000104) MSPI Output Pad Configuration */ + + struct { + __IOM uint32_t OUT3 : 1; /*!< [0..0] Output pad 3 configuration. 0=data[3] 1=CLK */ + __IOM uint32_t OUT4 : 1; /*!< [1..1] Output pad 4 configuration. 0=data[4] 1=data[0] */ + __IOM uint32_t OUT5 : 1; /*!< [2..2] Output pad 5 configuration. 0=data[5] 1=data[1] */ + __IOM uint32_t OUT6 : 1; /*!< [3..3] Output pad 6 configuration. 0=data[6] 1=data[2] */ + __IOM uint32_t OUT7 : 1; /*!< [4..4] Output pad 7 configuration. 0=data[7] 1=data[3] */ + uint32_t : 11; + __IOM uint32_t IN0 : 2; /*!< [17..16] Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] + 3=pad[5] */ + __IOM uint32_t IN1 : 1; /*!< [18..18] Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5] */ + __IOM uint32_t IN2 : 1; /*!< [19..19] Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6] */ + __IOM uint32_t IN3 : 1; /*!< [20..20] Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7] */ + __IOM uint32_t REVCS : 1; /*!< [21..21] Reverse CS connections. Allows CS1 to be associated + with lower data lanes and CS0 to be associated with upper + data lines */ + } PADCFG_b; + } ; + + union { + __IOM uint32_t PADOUTEN; /*!< (@ 0x00000108) MSPI Output Enable Pad Configuration */ + + struct { + __IOM uint32_t OUTEN : 9; /*!< [8..0] Output pad enable configuration. Indicates which pads + should be driven. Bits [3:0] are Quad0 data, [7:4] are + Quad1 data, and [8] is clock. */ + } PADOUTEN_b; + } ; + + union { + __IOM uint32_t FLASH; /*!< (@ 0x0000010C) Configuration for XIP/DMA support of SPI flash + modules. */ + + struct { + __IOM uint32_t XIPEN : 1; /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively + enables the address decoding of the MSPI device in the + flash/cache address space at address 0x04000000-0x07FFFFFF. */ + uint32_t : 1; + __IOM uint32_t XIPACK : 2; /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles + (Micron Flash devices only) */ + __IOM uint32_t XIPBIGENDIAN : 1; /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in + big or little endian format */ + __IOM uint32_t XIPENTURN : 1; /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable + TX->RX turnaround cycles */ + __IOM uint32_t XIPSENDA : 1; /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send + an an address phase (see DMADEVADDR register and ASIZE + field in CFG) */ + __IOM uint32_t XIPSENDI : 1; /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send + an instruction (see READINSTR field and ISIZE field in + CFG) */ + __IOM uint32_t XIPMIXED : 3; /*!< [10..8] Reserved. Set to 0x0 */ + uint32_t : 5; + __IOM uint32_t WRITEINSTR : 8; /*!< [23..16] Write command sent for DMA operations */ + __IOM uint32_t READINSTR : 8; /*!< [31..24] Read command sent to flash for DMA/XIP operations */ + } FLASH_b; + } ; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t SCRAMBLING; /*!< (@ 0x00000120) External Flash Scrambling Controls */ + + struct { + __IOM uint32_t SCRSTART : 10; /*!< [9..0] Scrambling region start address [25:16] (64K block granularity). + The START block is the FIRST block included in the scrambled + address range. */ + uint32_t : 6; + __IOM uint32_t SCREND : 10; /*!< [25..16] Scrambling region end address [25:16] (64K block granularity). + The END block is the LAST block included in the scrambled + address range. */ + uint32_t : 5; + __IOM uint32_t SCRENABLE : 1; /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes + to the range will be scrambled. When 0, data will be read/written + unmodified. Address range is specified in 64K granularity + and the START/END ranges are included within the range. */ + } SCRAMBLING_b; + } ; + __IM uint32_t RESERVED2[55]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) MSPI Master Interrupts: Enable */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) MSPI Master Interrupts: Status */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) MSPI Master Interrupts: Clear */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) MSPI Master Interrupts: Set */ + + struct { + __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are + layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */ + __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ + __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to + a full FIFO). */ + __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from + an empty FIFO) */ + __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- + MSPI bus pins will stall) */ + __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ + __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ + __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ + __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ + __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ + performs an operation where address bit[0] is set. Useful + for triggering CURIDX interrupts. */ + __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ + __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ + __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must + be aligned to word (4-byte) start address. */ + } INTSET_b; + } ; + __IM uint32_t RESERVED3[16]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000250) DMA Configuration */ + + struct { + __IOM uint32_t DMAEN : 2; /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA + operation */ + __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ + __IOM uint32_t DMAPRI : 2; /*!< [4..3] Sets the Priority of the DMA request */ + uint32_t : 13; + __IOM uint32_t DMAPWROFF : 1; /*!< [18..18] Power off MSPI domain upon completion of DMA operation. */ + } DMACFG_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000254) DMA Status */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that + a DMA transfer is active. The DMA transfer may be waiting + on data, transferring data, or waiting for priority. All + of these will be indicated with a 1. A 0 will indicate + that the DMA is fully complete and no further transactions + will be done. */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA + operation. */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error + was encountered during the DMA operation. */ + __IOM uint32_t SCRERR : 1; /*!< [3..3] Scrambling Access Alignment Error. This active high bit + signals that a scrambling operation was specified for a + non-word aligned DEVADDR. */ + } DMASTAT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x00000258) DMA Target Address */ + + struct { + __IOM uint32_t TARGADDR : 32; /*!< [31..0] Target byte address for source of DMA (either read or + write). In cases of non-word aligned addresses, the DMA + logic will take care for ensuring only the target bytes + are read/written. */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMADEVADDR; /*!< (@ 0x0000025C) DMA Device Address */ + + struct { + __IOM uint32_t DEVADDR : 32; /*!< [31..0] SPI Device address for automated DMA transactions (both + read and write). */ + } DMADEVADDR_b; + } ; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000260) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 16; /*!< [15..0] Total Transfer Count in bytes. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMABCOUNT; /*!< (@ 0x00000264) DMA BYTE Transfer Count */ + + struct { + __IOM uint32_t BCOUNT : 8; /*!< [7..0] Burst transfer size in bytes. This is the number of bytes + transferred when a FIFO trigger event occurs. Recommended + values are 16 or 32. */ + } DMABCOUNT_b; + } ; + __IM uint32_t RESERVED4[4]; + + union { + __IOM uint32_t DMATHRESH; /*!< (@ 0x00000278) DMA Transmit Trigger Threshold */ + + struct { + __IOM uint32_t DMATHRESH : 4; /*!< [3..0] DMA transfer FIFO level trigger. For read operations, + DMA is triggered when the FIFO level is greater than this + value. For write operations, DMA is triggered when the + FIFO level is less than this level. Each DMA operation + will consist of BCOUNT bytes. */ + } DMATHRESH_b; + } ; + __IM uint32_t RESERVED5[9]; + + union { + __IOM uint32_t CQCFG; /*!< (@ 0x000002A0) Command Queue Configuration */ + + struct { + __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing + of the command queue */ + __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue DMA request */ + __IOM uint32_t CQPWROFF : 1; /*!< [2..2] Power off MSPI domain upon completion of DMA operation. */ + __IOM uint32_t CQAUTOCLEARMASK : 1; /*!< [3..3] Enable clear of CQMASK after each pause operation. This + may be useful when using software flags to pause CQ. */ + } CQCFG_b; + } ; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t CQADDR; /*!< (@ 0x000002A8) CQ Target Read Address */ + + struct { + __IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or flash. The + buffer address must be aligned to a word boundary. */ + } CQADDR_b; + } ; + + union { + __IOM uint32_t CQSTAT; /*!< (@ 0x000002AC) Command Queue Status */ + + struct { + __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will + indicate that a CQ transfer is active and this will remain + active even when paused waiting for external event. */ + __IOM uint32_t CQCPL : 1; /*!< [1..1] Command queue operation Complete. This signals the end + of the command queue operation. */ + __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit + signals that an error was encountered during the CQ operation. */ + __IOM uint32_t CQPAUSED : 1; /*!< [3..3] Command queue is currently paused status. */ + } CQSTAT_b; + } ; + + union { + __IOM uint32_t CQFLAGS; /*!< (@ 0x000002B0) Command Queue Flags */ + + struct { + __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software + controllable and bits [15:8] are hardware status. */ + } CQFLAGS_b; + } ; + + union { + __IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002B4) Command Queue Flag Set/Clear */ + + struct { + __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Set has priority over clear if + both are high. */ + __IOM uint32_t CQFTOGGLE : 8; /*!< [15..8] Toggle CQFlag status bits */ + __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. */ + } CQSETCLEAR_b; + } ; + + union { + __IOM uint32_t CQPAUSE; /*!< (@ 0x000002B8) Command Queue Pause Mask */ + + struct { + __IOM uint32_t CQMASK : 16; /*!< [15..0] CQ will pause processing when ALL specified events are + satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK. */ + } CQPAUSE_b; + } ; + __IM uint32_t RESERVED7; + + union { + __IOM uint32_t CQCURIDX; /*!< (@ 0x000002C0) Command Queue Current Index */ + + struct { + __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Can be used to indicate the current position of the command + queue by having CQ operations write this field. A CQ hardware + status flag indicates when CURIDX and ENDIDX are not equal, + allowing SW to pause the CQ processing until the end index + is updated. */ + } CQCURIDX_b; + } ; + + union { + __IOM uint32_t CQENDIDX; /*!< (@ 0x000002C4) Command Queue End Index */ + + struct { + __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Can be used to indicate the end position of the command + queue. A CQ hardware status bit indices when CURIDX != + ENDIDX so that the CQ can be paused when it reaches the + end pointer. */ + } CQENDIDX_b; + } ; +} MSPI_Type; /*!< Size = 712 (0x2c8) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PDM Audio (PDM) + */ + +typedef struct { /*!< (@ 0x50011000) PDM Structure */ + + union { + __IOM uint32_t PCFG; /*!< (@ 0x00000000) PDM Configuration Register */ + + struct { + __IOM uint32_t PDMCOREEN : 1; /*!< [0..0] Data Streaming Control. */ + __IOM uint32_t SOFTMUTE : 1; /*!< [1..1] Soft mute control. */ + __IOM uint32_t CYCLES : 3; /*!< [4..2] Number of clocks during gain-setting changes. */ + __IOM uint32_t HPCUTOFF : 4; /*!< [8..5] High pass filter coefficients. */ + __IOM uint32_t ADCHPD : 1; /*!< [9..9] High pass filter control. */ + __IOM uint32_t SINCRATE : 7; /*!< [16..10] SINC decimation rate. */ + __IOM uint32_t MCLKDIV : 2; /*!< [18..17] PDM_CLK frequency divisor. */ + uint32_t : 2; + __IOM uint32_t PGALEFT : 5; /*!< [25..21] Left channel PGA gain. */ + __IOM uint32_t PGARIGHT : 5; /*!< [30..26] Right channel PGA gain. */ + __IOM uint32_t LRSWAP : 1; /*!< [31..31] Left/right channel swap. */ + } PCFG_b; + } ; + + union { + __IOM uint32_t VCFG; /*!< (@ 0x00000004) Voice Configuration Register */ + + struct { + uint32_t : 3; + __IOM uint32_t CHSET : 2; /*!< [4..3] Set PCM channels. */ + uint32_t : 3; + __IOM uint32_t PCMPACK : 1; /*!< [8..8] PCM data packing enable. */ + uint32_t : 7; + __IOM uint32_t SELAP : 1; /*!< [16..16] Select PDM input clock source. */ + __IOM uint32_t DMICKDEL : 1; /*!< [17..17] PDM clock sampling delay. */ + uint32_t : 1; + __IOM uint32_t BCLKINV : 1; /*!< [19..19] I2S BCLK input inversion. */ + __IOM uint32_t I2SEN : 1; /*!< [20..20] I2S interface enable. */ + uint32_t : 5; + __IOM uint32_t PDMCLKEN : 1; /*!< [26..26] Enable the serial clock. */ + __IOM uint32_t PDMCLKSEL : 3; /*!< [29..27] Select the PDM input clock. */ + __IOM uint32_t RSTB : 1; /*!< [30..30] Reset the IP core. */ + __IOM uint32_t IOCLKEN : 1; /*!< [31..31] Enable the IO clock. */ + } VCFG_b; + } ; + + union { + __IOM uint32_t VOICESTAT; /*!< (@ 0x00000008) Voice Status Register */ + + struct { + __IOM uint32_t FIFOCNT : 6; /*!< [5..0] Valid 32-bit entries currently in the FIFO. */ + } VOICESTAT_b; + } ; + + union { + __IOM uint32_t FIFOREAD; /*!< (@ 0x0000000C) FIFO Read */ + + struct { + __IOM uint32_t FIFOREAD : 32; /*!< [31..0] FIFO read data. */ + } FIFOREAD_b; + } ; + + union { + __IOM uint32_t FIFOFLUSH; /*!< (@ 0x00000010) FIFO Flush */ + + struct { + __IOM uint32_t FIFOFLUSH : 1; /*!< [0..0] FIFO FLUSH. */ + } FIFOFLUSH_b; + } ; + + union { + __IOM uint32_t FIFOTHR; /*!< (@ 0x00000014) FIFO Threshold */ + + struct { + __IOM uint32_t FIFOTHR : 5; /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to, + or larger than this value (in words), a THR interrupt is + generated (if enabled) */ + } FIFOTHR_b; + } ; + __IM uint32_t RESERVED[122]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ + + struct { + __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ + __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ + __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ + __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ + } INTSET_b; + } ; + __IM uint32_t RESERVED1[12]; + + union { + __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ + + struct { + __IOM uint32_t DTHR : 1; /*!< [0..0] Trigger DMA upon when FIFO iss filled to level indicated + by the FIFO THRESHOLD,at granularity of 16 bytes only */ + __IOM uint32_t DTHR90 : 1; /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also + used internally for AUTOHIP function */ + } DMATRIGEN_b; + } ; + + union { + __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ + + struct { + __IOM uint32_t DTHRSTAT : 1; /*!< [0..0] Triggered DMA from FIFO reaching threshold */ + __IOM uint32_t DTHR90STAT : 1; /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full */ + } DMATRIGSTAT_b; + } ; + __IM uint32_t RESERVED2[14]; + + union { + __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */ + uint32_t : 1; + __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ + uint32_t : 5; + __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ + __IOM uint32_t DAUTOHIP : 1; /*!< [9..9] Raise priority to high on fifo full, and DMAPRI set to + low */ + __IOM uint32_t DPWROFF : 1; /*!< [10..10] Power Off the ADC System upon DMACPL. */ + } DMACFG_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ + + struct { + __IOM uint32_t TOTCOUNT : 20; /*!< [19..0] Total Transfer Count. The transfer count must be a multiple + of the THR setting to avoid DMA overruns. */ + } DMATOTCOUNT_b; + } ; + + union { + __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ + + struct { + __IOM uint32_t LTARGADDR : 20; /*!< [19..0] DMA Target Address. This register is not updated with + the current address of the DMA, but will remain static + with the original address during the DMA transfer. */ + __IOM uint32_t UTARGADDR : 12; /*!< [31..20] SRAM Target */ + } DMATARGADDR_b; + } ; + + union { + __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ + + struct { + __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */ + __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */ + __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */ + } DMASTAT_b; + } ; +} PDM_Type; /*!< Size = 660 (0x294) */ + + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PWR Controller Register Bank (PWRCTRL) + */ + +typedef struct { /*!< (@ 0x40021000) PWRCTRL Structure */ + + union { + __IOM uint32_t SUPPLYSRC; /*!< (@ 0x00000000) Voltage Regulator Select Register */ + + struct { + __IOM uint32_t BLEBUCKEN : 1; /*!< [0..0] Enables and Selects the BLE Buck as the supply for the + BLE power domain or for Burst LDO. It takes the initial + value from Customer INFO space. Buck will be powered up + only if there is an active request for BLEH domain or Burst + mode and appropriate feature is allowed. */ + } SUPPLYSRC_b; + } ; + + union { + __IOM uint32_t SUPPLYSTATUS; /*!< (@ 0x00000004) Voltage Regulators status */ + + struct { + __IOM uint32_t SIMOBUCKON : 1; /*!< [0..0] Indicates whether the Core/Mem low-voltage domains are + supplied from the LDO or the Buck. */ + __IOM uint32_t BLEBUCKON : 1; /*!< [1..1] Indicates whether the BLE (if supported) domain and burst + (if supported) domain is supplied from the LDO or the Buck. + Buck will be powered up only if there is an active request + for BLEH domain or Burst mode and appropriate reature is + allowed. */ + } SUPPLYSTATUS_b; + } ; + + union { + __IOM uint32_t DEVPWREN; /*!< (@ 0x00000008) Device Power Enables */ + + struct { + __IOM uint32_t PWRIOS : 1; /*!< [0..0] Power up IO Slave */ + __IOM uint32_t PWRIOM0 : 1; /*!< [1..1] Power up IO Master 0 */ + __IOM uint32_t PWRIOM1 : 1; /*!< [2..2] Power up IO Master 1 */ + __IOM uint32_t PWRIOM2 : 1; /*!< [3..3] Power up IO Master 2 */ + __IOM uint32_t PWRIOM3 : 1; /*!< [4..4] Power up IO Master 3 */ + __IOM uint32_t PWRIOM4 : 1; /*!< [5..5] Power up IO Master 4 */ + __IOM uint32_t PWRIOM5 : 1; /*!< [6..6] Power up IO Master 5 */ + __IOM uint32_t PWRUART0 : 1; /*!< [7..7] Power up UART Controller 0 */ + __IOM uint32_t PWRUART1 : 1; /*!< [8..8] Power up UART Controller 1 */ + __IOM uint32_t PWRADC : 1; /*!< [9..9] Power up ADC Digital Controller */ + __IOM uint32_t PWRSCARD : 1; /*!< [10..10] Power up SCARD Controller */ + __IOM uint32_t PWRMSPI : 1; /*!< [11..11] Power up MSPI Controller */ + __IOM uint32_t PWRPDM : 1; /*!< [12..12] Power up PDM block */ + __IOM uint32_t PWRBLEL : 1; /*!< [13..13] Power up BLE controller */ + } DEVPWREN_b; + } ; + + union { + __IOM uint32_t MEMPWDINSLEEP; /*!< (@ 0x0000000C) Powerdown SRAM banks in Deep Sleep mode */ + + struct { + __IOM uint32_t DTCMPWDSLP : 3; /*!< [2..0] power down DTCM in deep sleep */ + __IOM uint32_t SRAMPWDSLP : 10; /*!< [12..3] Selects which SRAM banks are powered down in deep sleep + mode, causing the contents of the bank to be lost. */ + __IOM uint32_t FLASH0PWDSLP : 1; /*!< [13..13] Powerdown flash0 in deep sleep */ + __IOM uint32_t FLASH1PWDSLP : 1; /*!< [14..14] Powerdown flash1 in deep sleep */ + uint32_t : 16; + __IOM uint32_t CACHEPWDSLP : 1; /*!< [31..31] power down cache in deep sleep */ + } MEMPWDINSLEEP_b; + } ; + + union { + __IOM uint32_t MEMPWREN; /*!< (@ 0x00000010) Enables individual banks of the MEMORY array */ + + struct { + __IOM uint32_t DTCM : 3; /*!< [2..0] Power up DTCM */ + __IOM uint32_t SRAM : 10; /*!< [12..3] Power up SRAM groups */ + __IOM uint32_t FLASH0 : 1; /*!< [13..13] Power up Flash0 */ + __IOM uint32_t FLASH1 : 1; /*!< [14..14] Power up Flash1 */ + uint32_t : 15; + __IOM uint32_t CACHEB0 : 1; /*!< [30..30] Power up Cache Bank 0. This works in conjunction with + Cache enable from flash_cache module. To power up cache + bank0, cache has to be enabled and this bit has to be set. */ + __IOM uint32_t CACHEB2 : 1; /*!< [31..31] Power up Cache Bank 2. This works in conjunction with + Cache enable from flash_cache module. To power up cache + bank2, cache has to be enabled and this bit has to be set. */ + } MEMPWREN_b; + } ; + + union { + __IOM uint32_t MEMPWRSTATUS; /*!< (@ 0x00000014) Mem Power ON Status */ + + struct { + __IOM uint32_t DTCM00 : 1; /*!< [0..0] This bit is 1 if power is supplied to DTCM GROUP0_0 */ + __IOM uint32_t DTCM01 : 1; /*!< [1..1] This bit is 1 if power is supplied to DTCM GROUP0_1 */ + __IOM uint32_t DTCM1 : 1; /*!< [2..2] This bit is 1 if power is supplied to DTCM GROUP1 */ + __IOM uint32_t SRAM0 : 1; /*!< [3..3] This bit is 1 if power is supplied to SRAM GROUP0 */ + __IOM uint32_t SRAM1 : 1; /*!< [4..4] This bit is 1 if power is supplied to SRAM GROUP1 */ + __IOM uint32_t SRAM2 : 1; /*!< [5..5] This bit is 1 if power is supplied to SRAM GROUP2 */ + __IOM uint32_t SRAM3 : 1; /*!< [6..6] This bit is 1 if power is supplied to SRAM GROUP3 */ + __IOM uint32_t SRAM4 : 1; /*!< [7..7] This bit is 1 if power is supplied to SRAM GROUP4 */ + __IOM uint32_t SRAM5 : 1; /*!< [8..8] This bit is 1 if power is supplied to SRAM GROUP5 */ + __IOM uint32_t SRAM6 : 1; /*!< [9..9] This bit is 1 if power is supplied to SRAM GROUP6 */ + __IOM uint32_t SRAM7 : 1; /*!< [10..10] This bit is 1 if power is supplied to SRAM GROUP7 */ + __IOM uint32_t SRAM8 : 1; /*!< [11..11] This bit is 1 if power is supplied to SRAM GROUP8 */ + __IOM uint32_t SRAM9 : 1; /*!< [12..12] This bit is 1 if power is supplied to SRAM GROUP9 */ + __IOM uint32_t FLASH0 : 1; /*!< [13..13] This bit is 1 if power is supplied to FLASH 0 */ + __IOM uint32_t FLASH1 : 1; /*!< [14..14] This bit is 1 if power is supplied to FLASH 1 */ + __IOM uint32_t CACHEB0 : 1; /*!< [15..15] This bit is 1 if power is supplied to Cache Bank 0 */ + __IOM uint32_t CACHEB2 : 1; /*!< [16..16] This bit is 1 if power is supplied to Cache Bank 2 */ + } MEMPWRSTATUS_b; + } ; + + union { + __IOM uint32_t DEVPWRSTATUS; /*!< (@ 0x00000018) Device Power ON Status */ + + struct { + __IOM uint32_t MCUL : 1; /*!< [0..0] This bit is 1 if power is supplied to MCUL */ + __IOM uint32_t MCUH : 1; /*!< [1..1] This bit is 1 if power is supplied to MCUH */ + __IOM uint32_t HCPA : 1; /*!< [2..2] This bit is 1 if power is supplied to HCPA domain (IO + SLAVE, UART0, UART1, SCARD) */ + __IOM uint32_t HCPB : 1; /*!< [3..3] This bit is 1 if power is supplied to HCPB domain (IO + MASTER 0, 1, 2) */ + __IOM uint32_t HCPC : 1; /*!< [4..4] This bit is 1 if power is supplied to HCPC domain (IO + MASTER4, 5, 6) */ + __IOM uint32_t PWRADC : 1; /*!< [5..5] This bit is 1 if power is supplied to ADC */ + __IOM uint32_t PWRMSPI : 1; /*!< [6..6] This bit is 1 if power is supplied to MSPI */ + __IOM uint32_t PWRPDM : 1; /*!< [7..7] This bit is 1 if power is supplied to PDM */ + __IOM uint32_t BLEL : 1; /*!< [8..8] This bit is 1 if power is supplied to BLEL */ + __IOM uint32_t BLEH : 1; /*!< [9..9] This bit is 1 if power is supplied to BLEH */ + } DEVPWRSTATUS_b; + } ; + + union { + __IOM uint32_t SRAMCTRL; /*!< (@ 0x0000001C) SRAM Control register */ + + struct { + uint32_t : 1; + __IOM uint32_t SRAMCLKGATE : 1; /*!< [1..1] This bit is 1 if clock gating is allowed for individual + system SRAMs */ + __IOM uint32_t SRAMMASTERCLKGATE : 1; /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level + clock gate for entire SRAM block) */ + uint32_t : 5; + __IOM uint32_t SRAMLIGHTSLEEP : 12; /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding + bank will be put into light sleep. For optimal power, banks + should be put into light sleep while the system is active + but the bank has minimal or no accesses. */ + } SRAMCTRL_b; + } ; + + union { + __IOM uint32_t ADCSTATUS; /*!< (@ 0x00000020) Power Status Register for ADC Block */ + + struct { + __IOM uint32_t ADCPWD : 1; /*!< [0..0] This bit indicates that the ADC is powered down */ + __IOM uint32_t BGTPWD : 1; /*!< [1..1] This bit indicates that the ADC Band Gap is powered down */ + __IOM uint32_t VPTATPWD : 1; /*!< [2..2] This bit indicates that the ADC temperature sensor input + buffer is powered down */ + __IOM uint32_t VBATPWD : 1; /*!< [3..3] This bit indicates that the ADC VBAT resistor divider + is powered down */ + __IOM uint32_t REFKEEPPWD : 1; /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down */ + __IOM uint32_t REFBUFPWD : 1; /*!< [5..5] This bit indicates that the ADC REFBUF is powered down */ + } ADCSTATUS_b; + } ; + + union { + __IOM uint32_t MISC; /*!< (@ 0x00000024) Power Optimization Control Bits */ + + struct { + uint32_t : 3; + __IOM uint32_t FORCEMEMVRLPTIMERS : 1; /*!< [3..3] Control Bit to force Mem VR to LP mode in deep sleep + even when hfrc based ctimer or stimer is running. */ + uint32_t : 2; + __IOM uint32_t MEMVRLPBLE : 1; /*!< [6..6] Control Bit to let Mem VR go to lp mode in deep sleep + even when BLEL or BLEH is powered on given none of the + other domains require it. */ + } MISC_b; + } ; + + union { + __IOM uint32_t DEVPWREVENTEN; /*!< (@ 0x00000028) Event enable register to control which DEVPWRSTATUS + bits are routed to event input of CPU. */ + + struct { + __IOM uint32_t MCULEVEN : 1; /*!< [0..0] Control MCUL power-on status event */ + __IOM uint32_t MCUHEVEN : 1; /*!< [1..1] Control MCUH power-on status event */ + __IOM uint32_t HCPAEVEN : 1; /*!< [2..2] Control HCPA power-on status event */ + __IOM uint32_t HCPBEVEN : 1; /*!< [3..3] Control HCPB power-on status event */ + __IOM uint32_t HCPCEVEN : 1; /*!< [4..4] Control HCPC power-on status event */ + __IOM uint32_t ADCEVEN : 1; /*!< [5..5] Control ADC power-on status event */ + __IOM uint32_t MSPIEVEN : 1; /*!< [6..6] Control MSPI power-on status event */ + __IOM uint32_t PDMEVEN : 1; /*!< [7..7] Control PDM power-on status event */ + __IOM uint32_t BLELEVEN : 1; /*!< [8..8] Control BLE power-on status event */ + uint32_t : 20; + __IOM uint32_t BLEFEATUREEVEN : 1; /*!< [29..29] Control BLEFEATURE status event */ + __IOM uint32_t BURSTFEATUREEVEN : 1; /*!< [30..30] Control BURSTFEATURE status event */ + __IOM uint32_t BURSTEVEN : 1; /*!< [31..31] Control BURST status event */ + } DEVPWREVENTEN_b; + } ; + + union { + __IOM uint32_t MEMPWREVENTEN; /*!< (@ 0x0000002C) Event enable register to control which MEMPWRSTATUS + bits are routed to event input of CPU. */ + + struct { + __IOM uint32_t DTCMEN : 3; /*!< [2..0] Enable DTCM power-on status event */ + __IOM uint32_t SRAMEN : 10; /*!< [12..3] Control SRAM power-on status event */ + __IOM uint32_t FLASH0EN : 1; /*!< [13..13] Control Flash power-on status event */ + __IOM uint32_t FLASH1EN : 1; /*!< [14..14] Control Flash power-on status event */ + uint32_t : 15; + __IOM uint32_t CACHEB0EN : 1; /*!< [30..30] Control CACHE BANK 0 power-on status event */ + __IOM uint32_t CACHEB2EN : 1; /*!< [31..31] Control CACHEB2 power-on status event */ + } MEMPWREVENTEN_b; + } ; +} PWRCTRL_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU Reset Generator (RSTGEN) + */ + +typedef struct { /*!< (@ 0x40000000) RSTGEN Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t BODHREN : 1; /*!< [0..0] Brown out high (2.1v) reset enable. */ + __IOM uint32_t WDREN : 1; /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must + also be configured for WDT reset. This includes enabling + the RESEN bit in WDTCFG register in Watch dog timer block. */ + } CFG_b; + } ; + + union { + __IOM uint32_t SWPOI; /*!< (@ 0x00000004) Software POI Reset */ + + struct { + __IOM uint32_t SWPOIKEY : 8; /*!< [7..0] 0x1B generates a software POI reset. This is a write-only + register. Reading from this register will yield only all + 0s. */ + } SWPOI_b; + } ; + + union { + __IOM uint32_t SWPOR; /*!< (@ 0x00000008) Software POR Reset */ + + struct { + __IOM uint32_t SWPORKEY : 8; /*!< [7..0] 0xD4 generates a software POR reset. */ + } SWPOR_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t TPIURST; /*!< (@ 0x00000014) TPIU reset */ + + struct { + __IOM uint32_t TPIURST : 1; /*!< [0..0] Static reset for the TPIU. Write to '1' to assert reset + to TPIU. Write to '0' to clear the reset. */ + } TPIURST_b; + } ; + __IM uint32_t RESERVED1[122]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Reset Interrupt register: Enable */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Reset Interrupt register: Status */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Reset Interrupt register: Clear */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Reset Interrupt register: Set */ + + struct { + __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below + BODH level. */ + } INTSET_b; + } ; + __IM uint32_t RESERVED2[67107708]; + + union { + __IOM uint32_t STAT; /*!< (@ 0x0FFFF000) Status Register (SBL) */ + + struct { + __IOM uint32_t EXRSTAT : 1; /*!< [0..0] Reset was initiated by an External Reset (SBL). */ + __IOM uint32_t PORSTAT : 1; /*!< [1..1] Reset was initiated by a Power-On Reset (SBL). */ + __IOM uint32_t BORSTAT : 1; /*!< [2..2] Reset was initiated by a Brown-Out Reset (SBL). */ + __IOM uint32_t SWRSTAT : 1; /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset (SBL). */ + __IOM uint32_t POIRSTAT : 1; /*!< [4..4] Reset was a initiated by Software POI Reset (SBL). */ + __IOM uint32_t DBGRSTAT : 1; /*!< [5..5] Reset was a initiated by Debugger Reset (SBL). */ + __IOM uint32_t WDRSTAT : 1; /*!< [6..6] Reset was initiated by a Watchdog Timer Reset (SBL). */ + __IOM uint32_t BOUSTAT : 1; /*!< [7..7] An Unregulated Supply Brownout Event occurred (SBL). */ + __IOM uint32_t BOCSTAT : 1; /*!< [8..8] A Core Regulator Brownout Event occurred (SBL). */ + __IOM uint32_t BOFSTAT : 1; /*!< [9..9] A Memory Regulator Brownout Event occurred (SBL). */ + __IOM uint32_t BOBSTAT : 1; /*!< [10..10] A BLE/Burst Regulator Brownout Event occurred (SBL). */ + uint32_t : 19; + __IOM uint32_t FBOOT : 1; /*!< [30..30] Set if current boot was initiated by soft reset and + resulted in Fast Boot (SBL). */ + __IOM uint32_t SBOOT : 1; /*!< [31..31] Set when booting securely (SBL). */ + } STAT_b; + } ; +} RSTGEN_Type; /*!< Size = 268431364 (0xffff004) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real Time Clock (RTC) + */ + +typedef struct { /*!< (@ 0x40004200) RTC Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t CTRLOW; /*!< (@ 0x00000040) RTC Counters Lower */ + + struct { + __IOM uint32_t CTR100 : 8; /*!< [7..0] 100ths of a second Counter */ + __IOM uint32_t CTRSEC : 7; /*!< [14..8] Seconds Counter */ + uint32_t : 1; + __IOM uint32_t CTRMIN : 7; /*!< [22..16] Minutes Counter */ + uint32_t : 1; + __IOM uint32_t CTRHR : 6; /*!< [29..24] Hours Counter */ + } CTRLOW_b; + } ; + + union { + __IOM uint32_t CTRUP; /*!< (@ 0x00000044) RTC Counters Upper */ + + struct { + __IOM uint32_t CTRDATE : 6; /*!< [5..0] Date Counter */ + uint32_t : 2; + __IOM uint32_t CTRMO : 5; /*!< [12..8] Months Counter */ + uint32_t : 3; + __IOM uint32_t CTRYR : 8; /*!< [23..16] Years Counter */ + __IOM uint32_t CTRWKDY : 3; /*!< [26..24] Weekdays Counter */ + __IOM uint32_t CB : 1; /*!< [27..27] Century */ + __IOM uint32_t CEB : 1; /*!< [28..28] Century enable */ + uint32_t : 2; + __IOM uint32_t CTERR : 1; /*!< [31..31] Counter read error status. Error is triggered when + software reads the lower word of the counters, and fails + to read the upper counter within 1/100 second. This is + because when the lower counter is read, the upper counter + is held off from incrementing until it is read so that + the full time stamp can be read. */ + } CTRUP_b; + } ; + + union { + __IOM uint32_t ALMLOW; /*!< (@ 0x00000048) RTC Alarms Lower */ + + struct { + __IOM uint32_t ALM100 : 8; /*!< [7..0] 100ths of a second Alarm */ + __IOM uint32_t ALMSEC : 7; /*!< [14..8] Seconds Alarm */ + uint32_t : 1; + __IOM uint32_t ALMMIN : 7; /*!< [22..16] Minutes Alarm */ + uint32_t : 1; + __IOM uint32_t ALMHR : 6; /*!< [29..24] Hours Alarm */ + } ALMLOW_b; + } ; + + union { + __IOM uint32_t ALMUP; /*!< (@ 0x0000004C) RTC Alarms Upper */ + + struct { + __IOM uint32_t ALMDATE : 6; /*!< [5..0] Date Alarm */ + uint32_t : 2; + __IOM uint32_t ALMMO : 5; /*!< [12..8] Months Alarm */ + uint32_t : 3; + __IOM uint32_t ALMWKDY : 3; /*!< [18..16] Weekdays Alarm */ + } ALMUP_b; + } ; + + union { + __IOM uint32_t RTCCTL; /*!< (@ 0x00000050) RTC Control Register */ + + struct { + __IOM uint32_t WRTC : 1; /*!< [0..0] Counter write control */ + __IOM uint32_t RPT : 3; /*!< [3..1] Alarm repeat interval */ + __IOM uint32_t RSTOP : 1; /*!< [4..4] RTC input clock control */ + __IOM uint32_t HR1224 : 1; /*!< [5..5] Hours Counter mode */ + } RTCCTL_b; + } ; + __IM uint32_t RESERVED1[43]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000100) RTC Interrupt Register: Enable */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000104) RTC Interrupt Register: Status */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000108) RTC Interrupt Register: Clear */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000010C) RTC Interrupt Register: Set */ + + struct { + __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ + } INTSET_b; + } ; +} RTC_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ SCARD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial ISO7816 (SCARD) + */ + +typedef struct { /*!< (@ 0x40080000) SCARD Structure */ + + union { + __IOM uint32_t SR; /*!< (@ 0x00000000) ISO7816 interrupt status */ + + struct { + __IOM uint32_t FNE : 1; /*!< [0..0] RX FIFO not empty. */ + __IOM uint32_t TBERBF : 1; /*!< [1..1] FIFO empty (transmit) or full (receive). */ + __IOM uint32_t FER : 1; /*!< [2..2] Framing error. */ + __IOM uint32_t OVR : 1; /*!< [3..3] RX FIFO overflow. */ + __IOM uint32_t PE : 1; /*!< [4..4] Parity Error. */ + __IOM uint32_t FT2REND : 1; /*!< [5..5] TX to RX finished. */ + __IOM uint32_t FHF : 1; /*!< [6..6] FIFO Half Full. */ + } SR_b; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000004) ISO7816 interrupt enable */ + + struct { + __IOM uint32_t FNEEN : 1; /*!< [0..0] RX FIFO not empty interrupt enable. */ + __IOM uint32_t TBERBFEN : 1; /*!< [1..1] FIFO empty (transmit) or full (receive) interrupt enable. */ + __IOM uint32_t FEREN : 1; /*!< [2..2] Framing error interrupt enable. */ + __IOM uint32_t OVREN : 1; /*!< [3..3] RX FIFOI overflow interrupt enable. */ + __IOM uint32_t PEEN : 1; /*!< [4..4] Parity Error interrupt enable. */ + __IOM uint32_t FT2RENDEN : 1; /*!< [5..5] TX to RX finished interrupt enable. */ + __IOM uint32_t FHFEN : 1; /*!< [6..6] FIFO Half Full interrupt enable. */ + } IER_b; + } ; + + union { + __IOM uint32_t TCR; /*!< (@ 0x00000008) ISO7816 transmit control */ + + struct { + __IOM uint32_t CONV : 1; /*!< [0..0] Conversion inversion control. */ + __IOM uint32_t SS : 1; /*!< [1..1] Use first byte to configure conversion. */ + __IOM uint32_t LCT : 1; /*!< [2..2] Fast TX to RX. */ + __IOM uint32_t TR : 1; /*!< [3..3] Transmit/receive mode. */ + __IOM uint32_t PROT : 1; /*!< [4..4] PROT control. */ + __IOM uint32_t AUTOCONV : 1; /*!< [5..5] Automatic conversion. */ + __IOM uint32_t FIP : 1; /*!< [6..6] Parity select. */ + __IOM uint32_t DMAMD : 1; /*!< [7..7] DMA direction. */ + } TCR_b; + } ; + + union { + __IOM uint32_t UCR; /*!< (@ 0x0000000C) ISO7816 user control */ + + struct { + __IOM uint32_t CST : 1; /*!< [0..0] Clock control. */ + __IOM uint32_t RIU : 1; /*!< [1..1] ISO7816 reset. This bit is write-only. */ + __IOM uint32_t RSTIN : 1; /*!< [2..2] Reset polarity. */ + __IOM uint32_t RETXEN : 1; /*!< [3..3] Enable TX/RX time configuration. */ + } UCR_b; + } ; + + union { + __IOM uint32_t DR; /*!< (@ 0x00000010) ISO7816 data */ + + struct { + __IOM uint32_t DR : 8; /*!< [7..0] Data register. */ + } DR_b; + } ; + + union { + __IOM uint32_t BPRL; /*!< (@ 0x00000014) ISO7816 baud rate low */ + + struct { + __IOM uint32_t BPRL : 8; /*!< [7..0] Baud rate low */ + } BPRL_b; + } ; + + union { + __IOM uint32_t BPRH; /*!< (@ 0x00000018) ISO7816 baud rate high */ + + struct { + __IOM uint32_t BPRH : 4; /*!< [3..0] Baud rate high */ + } BPRH_b; + } ; + + union { + __IOM uint32_t UCR1; /*!< (@ 0x0000001C) ISO7816 user control 1 */ + + struct { + __IOM uint32_t PR : 1; /*!< [0..0] Query Card Detect. */ + uint32_t : 1; + __IOM uint32_t STSP : 1; /*!< [2..2] ETU counter control. This bit is write-only. */ + __IOM uint32_t T1PAREN : 1; /*!< [3..3] Parity check control. */ + __IOM uint32_t CLKIOV : 1; /*!< [4..4] Output clock level. */ + __IOM uint32_t ENLASTB : 1; /*!< [5..5] Enable last byte function. */ + } UCR1_b; + } ; + + union { + __IOM uint32_t SR1; /*!< (@ 0x00000020) ISO7816 interrupt status 1 */ + + struct { + __IOM uint32_t ECNTOVER : 1; /*!< [0..0] ETU counter overflow. */ + __IOM uint32_t PRL : 1; /*!< [1..1] Card insert/remove. */ + __IOM uint32_t SYNCEND : 1; /*!< [2..2] Write complete synchronization. */ + __IOM uint32_t IDLE : 1; /*!< [3..3] ISO7816 idle. */ + } SR1_b; + } ; + + union { + __IOM uint32_t IER1; /*!< (@ 0x00000024) ISO7816 interrupt enable 1 */ + + struct { + __IOM uint32_t ECNTOVEREN : 1; /*!< [0..0] ETU counter overflow interrupt enable. */ + __IOM uint32_t PRLEN : 1; /*!< [1..1] Card insert/remove interrupt enable. */ + __IOM uint32_t SYNCENDEN : 1; /*!< [2..2] Write complete synchronization interrupt enable. */ + } IER1_b; + } ; + + union { + __IOM uint32_t ECNTL; /*!< (@ 0x00000028) ETU counter low */ + + struct { + __IOM uint32_t ECNTL : 8; /*!< [7..0] ETU counter low register. */ + } ECNTL_b; + } ; + + union { + __IOM uint32_t ECNTH; /*!< (@ 0x0000002C) ETU counter high */ + + struct { + __IOM uint32_t ECNTH : 8; /*!< [7..0] ETU counter high register. */ + } ECNTH_b; + } ; + + union { + __IOM uint32_t GTR; /*!< (@ 0x00000030) ISO7816 guard time configuration */ + + struct { + __IOM uint32_t GTR : 8; /*!< [7..0] Guard time configuration register. */ + } GTR_b; + } ; + + union { + __IOM uint32_t RETXCNT; /*!< (@ 0x00000034) ISO7816 resend count */ + + struct { + __IOM uint32_t RETXCNT : 4; /*!< [3..0] Resend count register. */ + } RETXCNT_b; + } ; + + union { + __IOM uint32_t RETXCNTRMI; /*!< (@ 0x00000038) ISO7816 resent count inquiry */ + + struct { + __IOM uint32_t RETXCNTRMI : 4; /*!< [3..0] Resent count inquiry register. */ + } RETXCNTRMI_b; + } ; + __IM uint32_t RESERVED[49]; + + union { + __IOM uint32_t CLKCTRL; /*!< (@ 0x00000100) Clock Control */ + + struct { + __IOM uint32_t CLKEN : 1; /*!< [0..0] Enable the serial source clock for SCARD. */ + __IOM uint32_t APBCLKEN : 1; /*!< [1..1] Enable the SCARD APB clock to run continuously. */ + } CLKCTRL_b; + } ; +} SCARD_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ SECURITY ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Security Interfaces (SECURITY) + */ + +typedef struct { /*!< (@ 0x40030000) SECURITY Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control Register */ + + struct { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Function Enable. Software should set the ENABLE bit to + initiate a CRC operation. Hardware will clear the ENABLE + bit upon completion. */ + uint32_t : 3; + __IOM uint32_t FUNCTION : 4; /*!< [7..4] Function Select */ + uint32_t : 23; + __IOM uint32_t CRCERROR : 1; /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during + a CRC operation. Cleared when CTRL register is written + (with any value). Usually indicates an invalid address + range. */ + } CTRL_b; + } ; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t SRCADDR; /*!< (@ 0x00000010) Source Addresss */ + + struct { + __IOM uint32_t ADDR : 32; /*!< [31..0] Source Buffer Address. Address may be byte aligned, + but the length must be a multiple of 4 bits. */ + } SRCADDR_b; + } ; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t LEN; /*!< (@ 0x00000020) Length */ + + struct { + uint32_t : 2; + __IOM uint32_t LEN : 18; /*!< [19..2] Buffer size (bottom two bits assumed to be zero to ensure + a multiple of 4 bytes) */ + } LEN_b; + } ; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t RESULT; /*!< (@ 0x00000030) CRC Seed/Result Register */ + + struct { + __IOM uint32_t CRC : 32; /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF + before starting a CRC operation (unless the CRC is continued + from a previous operation). */ + } RESULT_b; + } ; + __IM uint32_t RESERVED3[17]; + + union { + __IOM uint32_t LOCKCTRL; /*!< (@ 0x00000078) LOCK Control Register */ + + struct { + __IOM uint32_t SELECT : 8; /*!< [7..0] LOCK Function Select register. */ + } LOCKCTRL_b; + } ; + + union { + __IOM uint32_t LOCKSTAT; /*!< (@ 0x0000007C) LOCK Status Register */ + + struct { + __IOM uint32_t STATUS : 32; /*!< [31..0] LOCK Status register. This register is a bitmask for + which resources are currently unlocked. These bits are + one-hot per resource. */ + } LOCKSTAT_b; + } ; + + union { + __IOM uint32_t KEY0; /*!< (@ 0x00000080) Key0 Register */ + + struct { + __IOM uint32_t KEY0 : 32; /*!< [31..0] Bits [31:0] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY0_b; + } ; + + union { + __IOM uint32_t KEY1; /*!< (@ 0x00000084) Key1 Register */ + + struct { + __IOM uint32_t KEY1 : 32; /*!< [31..0] Bits [63:32] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY1_b; + } ; + + union { + __IOM uint32_t KEY2; /*!< (@ 0x00000088) Key2 Register */ + + struct { + __IOM uint32_t KEY2 : 32; /*!< [31..0] Bits [95:64] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY2_b; + } ; + + union { + __IOM uint32_t KEY3; /*!< (@ 0x0000008C) Key3 Register */ + + struct { + __IOM uint32_t KEY3 : 32; /*!< [31..0] Bits [127:96] of the 128-bit key should be written to + this register. To protect key values, the register always + returns 0x00000000. */ + } KEY3_b; + } ; +} SECURITY_Type; /*!< Size = 144 (0x90) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial UART (UART0) + */ + +typedef struct { /*!< (@ 0x4001C000) UART0 Structure */ + + union { + __IOM uint32_t DR; /*!< (@ 0x00000000) UART Data Register */ + + struct { + __IOM uint32_t DATA : 8; /*!< [7..0] This is the UART data port. */ + __IOM uint32_t FEDATA : 1; /*!< [8..8] This is the framing error indicator. */ + __IOM uint32_t PEDATA : 1; /*!< [9..9] This is the parity error indicator. */ + __IOM uint32_t BEDATA : 1; /*!< [10..10] This is the break error indicator. */ + __IOM uint32_t OEDATA : 1; /*!< [11..11] This is the overrun error indicator. */ + } DR_b; + } ; + + union { + __IOM uint32_t RSR; /*!< (@ 0x00000004) UART Status Register */ + + struct { + __IOM uint32_t FESTAT : 1; /*!< [0..0] This is the framing error indicator. */ + __IOM uint32_t PESTAT : 1; /*!< [1..1] This is the parity error indicator. */ + __IOM uint32_t BESTAT : 1; /*!< [2..2] This is the break error indicator. */ + __IOM uint32_t OESTAT : 1; /*!< [3..3] This is the overrun error indicator. */ + } RSR_b; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IOM uint32_t FR; /*!< (@ 0x00000018) Flag Register */ + + struct { + __IOM uint32_t CTS : 1; /*!< [0..0] This bit holds the clear to send indicator. */ + __IOM uint32_t DSR : 1; /*!< [1..1] This bit holds the data set ready indicator. */ + __IOM uint32_t DCD : 1; /*!< [2..2] This bit holds the data carrier detect indicator. */ + __IOM uint32_t BUSY : 1; /*!< [3..3] This bit holds the busy indicator. */ + __IOM uint32_t RXFE : 1; /*!< [4..4] This bit holds the receive FIFO empty indicator. */ + __IOM uint32_t TXFF : 1; /*!< [5..5] This bit holds the transmit FIFO full indicator. */ + __IOM uint32_t RXFF : 1; /*!< [6..6] This bit holds the receive FIFO full indicator. */ + __IOM uint32_t TXFE : 1; /*!< [7..7] This bit holds the transmit FIFO empty indicator. */ + __IOM uint32_t TXBUSY : 1; /*!< [8..8] This bit holds the transmit BUSY indicator. */ + } FR_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t ILPR; /*!< (@ 0x00000020) IrDA Counter */ + + struct { + __IOM uint32_t ILPDVSR : 8; /*!< [7..0] These bits hold the IrDA counter divisor. */ + } ILPR_b; + } ; + + union { + __IOM uint32_t IBRD; /*!< (@ 0x00000024) Integer Baud Rate Divisor */ + + struct { + __IOM uint32_t DIVINT : 16; /*!< [15..0] These bits hold the baud integer divisor. */ + } IBRD_b; + } ; + + union { + __IOM uint32_t FBRD; /*!< (@ 0x00000028) Fractional Baud Rate Divisor */ + + struct { + __IOM uint32_t DIVFRAC : 6; /*!< [5..0] These bits hold the baud fractional divisor. */ + } FBRD_b; + } ; + + union { + __IOM uint32_t LCRH; /*!< (@ 0x0000002C) Line Control High */ + + struct { + __IOM uint32_t BRK : 1; /*!< [0..0] This bit holds the break set. */ + __IOM uint32_t PEN : 1; /*!< [1..1] This bit holds the parity enable. */ + __IOM uint32_t EPS : 1; /*!< [2..2] This bit holds the even parity select. */ + __IOM uint32_t STP2 : 1; /*!< [3..3] This bit holds the two stop bits select. */ + __IOM uint32_t FEN : 1; /*!< [4..4] This bit holds the FIFO enable. */ + __IOM uint32_t WLEN : 2; /*!< [6..5] These bits hold the write length. */ + __IOM uint32_t SPS : 1; /*!< [7..7] This bit holds the stick parity select. */ + } LCRH_b; + } ; + + union { + __IOM uint32_t CR; /*!< (@ 0x00000030) Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] This bit is the UART enable. */ + __IOM uint32_t SIREN : 1; /*!< [1..1] This bit is the SIR ENDEC enable. */ + __IOM uint32_t SIRLP : 1; /*!< [2..2] This bit is the SIR low power select. */ + __IOM uint32_t CLKEN : 1; /*!< [3..3] This bit is the UART clock enable. */ + __IOM uint32_t CLKSEL : 3; /*!< [6..4] This bitfield is the UART clock select. */ + __IOM uint32_t LBE : 1; /*!< [7..7] This bit is the loopback enable. */ + __IOM uint32_t TXE : 1; /*!< [8..8] This bit is the transmit enable. */ + __IOM uint32_t RXE : 1; /*!< [9..9] This bit is the receive enable. */ + __IOM uint32_t DTR : 1; /*!< [10..10] This bit enables data transmit ready. */ + __IOM uint32_t RTS : 1; /*!< [11..11] This bit enables request to send. */ + __IOM uint32_t OUT1 : 1; /*!< [12..12] This bit holds modem Out1. */ + __IOM uint32_t OUT2 : 1; /*!< [13..13] This bit holds modem Out2. */ + __IOM uint32_t RTSEN : 1; /*!< [14..14] This bit enables RTS hardware flow control. */ + __IOM uint32_t CTSEN : 1; /*!< [15..15] This bit enables CTS hardware flow control. */ + } CR_b; + } ; + + union { + __IOM uint32_t IFLS; /*!< (@ 0x00000034) FIFO Interrupt Level Select */ + + struct { + __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] These bits hold the transmit FIFO interrupt level. */ + __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] These bits hold the receive FIFO interrupt level. */ + } IFLS_b; + } ; + + union { + __IOM uint32_t IER; /*!< (@ 0x00000038) Interrupt Enable */ + + struct { + __IOM uint32_t TXCMPMIM : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt enable. */ + __IOM uint32_t CTSMIM : 1; /*!< [1..1] This bit holds the modem CTS interrupt enable. */ + __IOM uint32_t DCDMIM : 1; /*!< [2..2] This bit holds the modem DCD interrupt enable. */ + __IOM uint32_t DSRMIM : 1; /*!< [3..3] This bit holds the modem DSR interrupt enable. */ + __IOM uint32_t RXIM : 1; /*!< [4..4] This bit holds the receive interrupt enable. */ + __IOM uint32_t TXIM : 1; /*!< [5..5] This bit holds the transmit interrupt enable. */ + __IOM uint32_t RTIM : 1; /*!< [6..6] This bit holds the receive timeout interrupt enable. */ + __IOM uint32_t FEIM : 1; /*!< [7..7] This bit holds the framing error interrupt enable. */ + __IOM uint32_t PEIM : 1; /*!< [8..8] This bit holds the parity error interrupt enable. */ + __IOM uint32_t BEIM : 1; /*!< [9..9] This bit holds the break error interrupt enable. */ + __IOM uint32_t OEIM : 1; /*!< [10..10] This bit holds the overflow interrupt enable. */ + } IER_b; + } ; + + union { + __IOM uint32_t IES; /*!< (@ 0x0000003C) Interrupt Status */ + + struct { + __IOM uint32_t TXCMPMRIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status. */ + __IOM uint32_t CTSMRIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status. */ + __IOM uint32_t DCDMRIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status. */ + __IOM uint32_t DSRMRIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status. */ + __IOM uint32_t RXRIS : 1; /*!< [4..4] This bit holds the receive interrupt status. */ + __IOM uint32_t TXRIS : 1; /*!< [5..5] This bit holds the transmit interrupt status. */ + __IOM uint32_t RTRIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status. */ + __IOM uint32_t FERIS : 1; /*!< [7..7] This bit holds the framing error interrupt status. */ + __IOM uint32_t PERIS : 1; /*!< [8..8] This bit holds the parity error interrupt status. */ + __IOM uint32_t BERIS : 1; /*!< [9..9] This bit holds the break error interrupt status. */ + __IOM uint32_t OERIS : 1; /*!< [10..10] This bit holds the overflow interrupt status. */ + } IES_b; + } ; + + union { + __IOM uint32_t MIS; /*!< (@ 0x00000040) Masked Interrupt Status */ + + struct { + __IOM uint32_t TXCMPMMIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status masked. */ + __IOM uint32_t CTSMMIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status masked. */ + __IOM uint32_t DCDMMIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status masked. */ + __IOM uint32_t DSRMMIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status masked. */ + __IOM uint32_t RXMIS : 1; /*!< [4..4] This bit holds the receive interrupt status masked. */ + __IOM uint32_t TXMIS : 1; /*!< [5..5] This bit holds the transmit interrupt status masked. */ + __IOM uint32_t RTMIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status masked. */ + __IOM uint32_t FEMIS : 1; /*!< [7..7] This bit holds the framing error interrupt status masked. */ + __IOM uint32_t PEMIS : 1; /*!< [8..8] This bit holds the parity error interrupt status masked. */ + __IOM uint32_t BEMIS : 1; /*!< [9..9] This bit holds the break error interrupt status masked. */ + __IOM uint32_t OEMIS : 1; /*!< [10..10] This bit holds the overflow interrupt status masked. */ + } MIS_b; + } ; + + union { + __IOM uint32_t IEC; /*!< (@ 0x00000044) Interrupt Clear */ + + struct { + __IOM uint32_t TXCMPMIC : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt clear. */ + __IOM uint32_t CTSMIC : 1; /*!< [1..1] This bit holds the modem CTS interrupt clear. */ + __IOM uint32_t DCDMIC : 1; /*!< [2..2] This bit holds the modem DCD interrupt clear. */ + __IOM uint32_t DSRMIC : 1; /*!< [3..3] This bit holds the modem DSR interrupt clear. */ + __IOM uint32_t RXIC : 1; /*!< [4..4] This bit holds the receive interrupt clear. */ + __IOM uint32_t TXIC : 1; /*!< [5..5] This bit holds the transmit interrupt clear. */ + __IOM uint32_t RTIC : 1; /*!< [6..6] This bit holds the receive timeout interrupt clear. */ + __IOM uint32_t FEIC : 1; /*!< [7..7] This bit holds the framing error interrupt clear. */ + __IOM uint32_t PEIC : 1; /*!< [8..8] This bit holds the parity error interrupt clear. */ + __IOM uint32_t BEIC : 1; /*!< [9..9] This bit holds the break error interrupt clear. */ + __IOM uint32_t OEIC : 1; /*!< [10..10] This bit holds the overflow interrupt clear. */ + } IEC_b; + } ; +} UART0_Type; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Voltage Comparator (VCOMP) + */ + +typedef struct { /*!< (@ 0x4000C000) VCOMP Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t PSEL : 2; /*!< [1..0] This bitfield selects the positive input to the comparator. */ + uint32_t : 6; + __IOM uint32_t NSEL : 2; /*!< [9..8] This bitfield selects the negative input to the comparator. */ + uint32_t : 6; + __IOM uint32_t LVLSEL : 4; /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this + bitfield selects the voltage level for the negative input + to the comparator. */ + } CFG_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Status Register */ + + struct { + __IOM uint32_t CMPOUT : 1; /*!< [0..0] This bit is 1 if the positive input of the comparator + is greater than the negative input. */ + __IOM uint32_t PWDSTAT : 1; /*!< [1..1] This bit indicates the power down state of the voltage + comparator. */ + } STAT_b; + } ; + + union { + __IOM uint32_t PWDKEY; /*!< (@ 0x00000008) Key Register for Powering Down the Voltage Comparator */ + + struct { + __IOM uint32_t PWDKEY : 32; /*!< [31..0] Key register value. */ + } PWDKEY_b; + } ; + __IM uint32_t RESERVED[125]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) Voltage Comparator Interrupt registers: Enable */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Voltage Comparator Interrupt registers: Status */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Voltage Comparator Interrupt registers: Clear */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Voltage Comparator Interrupt registers: Set */ + + struct { + __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ + __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ + } INTSET_b; + } ; +} VCOMP_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40024000) WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] This bitfield enables the WDT. */ + __IOM uint32_t INTEN : 1; /*!< [1..1] This bitfield enables the WDT interrupt. Note : This + bit must be set before the interrupt status bit will reflect + a watchdog timer expiration. The IER interrupt register + must also be enabled for a WDT interrupt to be sent to + the NVIC. */ + __IOM uint32_t RESEN : 1; /*!< [2..2] This bitfield enables the WDT reset. This needs to be + set together with the WDREN bit in REG_RSTGEN_CFG register + (in reset gen) to trigger the reset. */ + uint32_t : 5; + __IOM uint32_t RESVAL : 8; /*!< [15..8] This bitfield is the compare value for counter bits + 7:0 to generate a watchdog reset. This will cause a software + reset. */ + __IOM uint32_t INTVAL : 8; /*!< [23..16] This bitfield is the compare value for counter bits + 7:0 to generate a watchdog interrupt. */ + __IOM uint32_t CLKSEL : 3; /*!< [26..24] Select the frequency for the WDT. All values not enumerated + below are undefined. */ + } CFG_b; + } ; + + union { + __IOM uint32_t RSTRT; /*!< (@ 0x00000004) Restart the watchdog timer. */ + + struct { + __IOM uint32_t RSTRT : 8; /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer. + This is a write only register. Reading this register will + only provide all 0. */ + } RSTRT_b; + } ; + + union { + __IOM uint32_t LOCK; /*!< (@ 0x00000008) Locks the WDT */ + + struct { + __IOM uint32_t LOCK : 8; /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the + WDTCFG reg cannot be written and WDTEN is set. */ + } LOCK_b; + } ; + + union { + __IOM uint32_t COUNT; /*!< (@ 0x0000000C) Current Counter Value for WDT */ + + struct { + __IOM uint32_t COUNT : 8; /*!< [7..0] Read-Only current value of the WDT counter */ + } COUNT_b; + } ; + __IM uint32_t RESERVED[124]; + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000200) WDT Interrupt register: Enable */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTEN_b; + } ; + + union { + __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) WDT Interrupt register: Status */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTSTAT_b; + } ; + + union { + __IOM uint32_t INTCLR; /*!< (@ 0x00000208) WDT Interrupt register: Clear */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTCLR_b; + } ; + + union { + __IOM uint32_t INTSET; /*!< (@ 0x0000020C) WDT Interrupt register: Set */ + + struct { + __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ + } INTSET_b; + } ; +} WDT_Type; /*!< Size = 528 (0x210) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC_BASE 0x50010000UL +#define APBDMA_BASE 0x40011000UL +#define BLEIF_BASE 0x5000C000UL +#define CACHECTRL_BASE 0x40018000UL +#define CLKGEN_BASE 0x40004000UL +#define CTIMER_BASE 0x40008000UL +#define GPIO_BASE 0x40010000UL +#define IOM0_BASE 0x50004000UL +#define IOM1_BASE 0x50005000UL +#define IOM2_BASE 0x50006000UL +#define IOM3_BASE 0x50007000UL +#define IOM4_BASE 0x50008000UL +#define IOM5_BASE 0x50009000UL +#define IOSLAVE_BASE 0x50000000UL +#define MCUCTRL_BASE 0x40020000UL +#define MSPI_BASE 0x50014000UL +#define PDM_BASE 0x50011000UL +#define PWRCTRL_BASE 0x40021000UL +#define RSTGEN_BASE 0x40000000UL +#define RTC_BASE 0x40004200UL +#define SCARD_BASE 0x40080000UL +#define SECURITY_BASE 0x40030000UL +#define UART0_BASE 0x4001C000UL +#define UART1_BASE 0x4001D000UL +#define VCOMP_BASE 0x4000C000UL +#define WDT_BASE 0x40024000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define ADC ((ADC_Type*) ADC_BASE) +#define APBDMA ((APBDMA_Type*) APBDMA_BASE) +#define BLEIF ((BLEIF_Type*) BLEIF_BASE) +#define CACHECTRL ((CACHECTRL_Type*) CACHECTRL_BASE) +#define CLKGEN ((CLKGEN_Type*) CLKGEN_BASE) +#define CTIMER ((CTIMER_Type*) CTIMER_BASE) +#define GPIO ((GPIO_Type*) GPIO_BASE) +#define IOM0 ((IOM0_Type*) IOM0_BASE) +#define IOM1 ((IOM0_Type*) IOM1_BASE) +#define IOM2 ((IOM0_Type*) IOM2_BASE) +#define IOM3 ((IOM0_Type*) IOM3_BASE) +#define IOM4 ((IOM0_Type*) IOM4_BASE) +#define IOM5 ((IOM0_Type*) IOM5_BASE) +#define IOSLAVE ((IOSLAVE_Type*) IOSLAVE_BASE) +#define MCUCTRL ((MCUCTRL_Type*) MCUCTRL_BASE) +#define MSPI ((MSPI_Type*) MSPI_BASE) +#define PDM ((PDM_Type*) PDM_BASE) +#define PWRCTRL ((PWRCTRL_Type*) PWRCTRL_BASE) +#define RSTGEN ((RSTGEN_Type*) RSTGEN_BASE) +#define RTC ((RTC_Type*) RTC_BASE) +#define SCARD ((SCARD_Type*) SCARD_BASE) +#define SECURITY ((SECURITY_Type*) SECURITY_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define VCOMP ((VCOMP_Type*) VCOMP_BASE) +#define WDT ((WDT_Type*) WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define ADC_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */ +#define ADC_CFG_CLKSEL_Msk (0x3000000UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ +#define ADC_CFG_TRIGPOL_Pos (19UL) /*!< TRIGPOL (Bit 19) */ +#define ADC_CFG_TRIGPOL_Msk (0x80000UL) /*!< TRIGPOL (Bitfield-Mask: 0x01) */ +#define ADC_CFG_TRIGSEL_Pos (16UL) /*!< TRIGSEL (Bit 16) */ +#define ADC_CFG_TRIGSEL_Msk (0x70000UL) /*!< TRIGSEL (Bitfield-Mask: 0x07) */ +#define ADC_CFG_DFIFORDEN_Pos (12UL) /*!< DFIFORDEN (Bit 12) */ +#define ADC_CFG_DFIFORDEN_Msk (0x1000UL) /*!< DFIFORDEN (Bitfield-Mask: 0x01) */ +#define ADC_CFG_REFSEL_Pos (8UL) /*!< REFSEL (Bit 8) */ +#define ADC_CFG_REFSEL_Msk (0x300UL) /*!< REFSEL (Bitfield-Mask: 0x03) */ +#define ADC_CFG_CKMODE_Pos (4UL) /*!< CKMODE (Bit 4) */ +#define ADC_CFG_CKMODE_Msk (0x10UL) /*!< CKMODE (Bitfield-Mask: 0x01) */ +#define ADC_CFG_LPMODE_Pos (3UL) /*!< LPMODE (Bit 3) */ +#define ADC_CFG_LPMODE_Msk (0x8UL) /*!< LPMODE (Bitfield-Mask: 0x01) */ +#define ADC_CFG_RPTEN_Pos (2UL) /*!< RPTEN (Bit 2) */ +#define ADC_CFG_RPTEN_Msk (0x4UL) /*!< RPTEN (Bitfield-Mask: 0x01) */ +#define ADC_CFG_ADCEN_Pos (0UL) /*!< ADCEN (Bit 0) */ +#define ADC_CFG_ADCEN_Msk (0x1UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define ADC_STAT_PWDSTAT_Pos (0UL) /*!< PWDSTAT (Bit 0) */ +#define ADC_STAT_PWDSTAT_Msk (0x1UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== SWT ========================================================== */ +#define ADC_SWT_SWT_Pos (0UL) /*!< SWT (Bit 0) */ +#define ADC_SWT_SWT_Msk (0xffUL) /*!< SWT (Bitfield-Mask: 0xff) */ +/* ======================================================== SL0CFG ========================================================= */ +#define ADC_SL0CFG_ADSEL0_Pos (24UL) /*!< ADSEL0 (Bit 24) */ +#define ADC_SL0CFG_ADSEL0_Msk (0x7000000UL) /*!< ADSEL0 (Bitfield-Mask: 0x07) */ +#define ADC_SL0CFG_PRMODE0_Pos (16UL) /*!< PRMODE0 (Bit 16) */ +#define ADC_SL0CFG_PRMODE0_Msk (0x30000UL) /*!< PRMODE0 (Bitfield-Mask: 0x03) */ +#define ADC_SL0CFG_CHSEL0_Pos (8UL) /*!< CHSEL0 (Bit 8) */ +#define ADC_SL0CFG_CHSEL0_Msk (0xf00UL) /*!< CHSEL0 (Bitfield-Mask: 0x0f) */ +#define ADC_SL0CFG_WCEN0_Pos (1UL) /*!< WCEN0 (Bit 1) */ +#define ADC_SL0CFG_WCEN0_Msk (0x2UL) /*!< WCEN0 (Bitfield-Mask: 0x01) */ +#define ADC_SL0CFG_SLEN0_Pos (0UL) /*!< SLEN0 (Bit 0) */ +#define ADC_SL0CFG_SLEN0_Msk (0x1UL) /*!< SLEN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL1CFG ========================================================= */ +#define ADC_SL1CFG_ADSEL1_Pos (24UL) /*!< ADSEL1 (Bit 24) */ +#define ADC_SL1CFG_ADSEL1_Msk (0x7000000UL) /*!< ADSEL1 (Bitfield-Mask: 0x07) */ +#define ADC_SL1CFG_PRMODE1_Pos (16UL) /*!< PRMODE1 (Bit 16) */ +#define ADC_SL1CFG_PRMODE1_Msk (0x30000UL) /*!< PRMODE1 (Bitfield-Mask: 0x03) */ +#define ADC_SL1CFG_CHSEL1_Pos (8UL) /*!< CHSEL1 (Bit 8) */ +#define ADC_SL1CFG_CHSEL1_Msk (0xf00UL) /*!< CHSEL1 (Bitfield-Mask: 0x0f) */ +#define ADC_SL1CFG_WCEN1_Pos (1UL) /*!< WCEN1 (Bit 1) */ +#define ADC_SL1CFG_WCEN1_Msk (0x2UL) /*!< WCEN1 (Bitfield-Mask: 0x01) */ +#define ADC_SL1CFG_SLEN1_Pos (0UL) /*!< SLEN1 (Bit 0) */ +#define ADC_SL1CFG_SLEN1_Msk (0x1UL) /*!< SLEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL2CFG ========================================================= */ +#define ADC_SL2CFG_ADSEL2_Pos (24UL) /*!< ADSEL2 (Bit 24) */ +#define ADC_SL2CFG_ADSEL2_Msk (0x7000000UL) /*!< ADSEL2 (Bitfield-Mask: 0x07) */ +#define ADC_SL2CFG_PRMODE2_Pos (16UL) /*!< PRMODE2 (Bit 16) */ +#define ADC_SL2CFG_PRMODE2_Msk (0x30000UL) /*!< PRMODE2 (Bitfield-Mask: 0x03) */ +#define ADC_SL2CFG_CHSEL2_Pos (8UL) /*!< CHSEL2 (Bit 8) */ +#define ADC_SL2CFG_CHSEL2_Msk (0xf00UL) /*!< CHSEL2 (Bitfield-Mask: 0x0f) */ +#define ADC_SL2CFG_WCEN2_Pos (1UL) /*!< WCEN2 (Bit 1) */ +#define ADC_SL2CFG_WCEN2_Msk (0x2UL) /*!< WCEN2 (Bitfield-Mask: 0x01) */ +#define ADC_SL2CFG_SLEN2_Pos (0UL) /*!< SLEN2 (Bit 0) */ +#define ADC_SL2CFG_SLEN2_Msk (0x1UL) /*!< SLEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL3CFG ========================================================= */ +#define ADC_SL3CFG_ADSEL3_Pos (24UL) /*!< ADSEL3 (Bit 24) */ +#define ADC_SL3CFG_ADSEL3_Msk (0x7000000UL) /*!< ADSEL3 (Bitfield-Mask: 0x07) */ +#define ADC_SL3CFG_PRMODE3_Pos (16UL) /*!< PRMODE3 (Bit 16) */ +#define ADC_SL3CFG_PRMODE3_Msk (0x30000UL) /*!< PRMODE3 (Bitfield-Mask: 0x03) */ +#define ADC_SL3CFG_CHSEL3_Pos (8UL) /*!< CHSEL3 (Bit 8) */ +#define ADC_SL3CFG_CHSEL3_Msk (0xf00UL) /*!< CHSEL3 (Bitfield-Mask: 0x0f) */ +#define ADC_SL3CFG_WCEN3_Pos (1UL) /*!< WCEN3 (Bit 1) */ +#define ADC_SL3CFG_WCEN3_Msk (0x2UL) /*!< WCEN3 (Bitfield-Mask: 0x01) */ +#define ADC_SL3CFG_SLEN3_Pos (0UL) /*!< SLEN3 (Bit 0) */ +#define ADC_SL3CFG_SLEN3_Msk (0x1UL) /*!< SLEN3 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL4CFG ========================================================= */ +#define ADC_SL4CFG_ADSEL4_Pos (24UL) /*!< ADSEL4 (Bit 24) */ +#define ADC_SL4CFG_ADSEL4_Msk (0x7000000UL) /*!< ADSEL4 (Bitfield-Mask: 0x07) */ +#define ADC_SL4CFG_PRMODE4_Pos (16UL) /*!< PRMODE4 (Bit 16) */ +#define ADC_SL4CFG_PRMODE4_Msk (0x30000UL) /*!< PRMODE4 (Bitfield-Mask: 0x03) */ +#define ADC_SL4CFG_CHSEL4_Pos (8UL) /*!< CHSEL4 (Bit 8) */ +#define ADC_SL4CFG_CHSEL4_Msk (0xf00UL) /*!< CHSEL4 (Bitfield-Mask: 0x0f) */ +#define ADC_SL4CFG_WCEN4_Pos (1UL) /*!< WCEN4 (Bit 1) */ +#define ADC_SL4CFG_WCEN4_Msk (0x2UL) /*!< WCEN4 (Bitfield-Mask: 0x01) */ +#define ADC_SL4CFG_SLEN4_Pos (0UL) /*!< SLEN4 (Bit 0) */ +#define ADC_SL4CFG_SLEN4_Msk (0x1UL) /*!< SLEN4 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL5CFG ========================================================= */ +#define ADC_SL5CFG_ADSEL5_Pos (24UL) /*!< ADSEL5 (Bit 24) */ +#define ADC_SL5CFG_ADSEL5_Msk (0x7000000UL) /*!< ADSEL5 (Bitfield-Mask: 0x07) */ +#define ADC_SL5CFG_PRMODE5_Pos (16UL) /*!< PRMODE5 (Bit 16) */ +#define ADC_SL5CFG_PRMODE5_Msk (0x30000UL) /*!< PRMODE5 (Bitfield-Mask: 0x03) */ +#define ADC_SL5CFG_CHSEL5_Pos (8UL) /*!< CHSEL5 (Bit 8) */ +#define ADC_SL5CFG_CHSEL5_Msk (0xf00UL) /*!< CHSEL5 (Bitfield-Mask: 0x0f) */ +#define ADC_SL5CFG_WCEN5_Pos (1UL) /*!< WCEN5 (Bit 1) */ +#define ADC_SL5CFG_WCEN5_Msk (0x2UL) /*!< WCEN5 (Bitfield-Mask: 0x01) */ +#define ADC_SL5CFG_SLEN5_Pos (0UL) /*!< SLEN5 (Bit 0) */ +#define ADC_SL5CFG_SLEN5_Msk (0x1UL) /*!< SLEN5 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL6CFG ========================================================= */ +#define ADC_SL6CFG_ADSEL6_Pos (24UL) /*!< ADSEL6 (Bit 24) */ +#define ADC_SL6CFG_ADSEL6_Msk (0x7000000UL) /*!< ADSEL6 (Bitfield-Mask: 0x07) */ +#define ADC_SL6CFG_PRMODE6_Pos (16UL) /*!< PRMODE6 (Bit 16) */ +#define ADC_SL6CFG_PRMODE6_Msk (0x30000UL) /*!< PRMODE6 (Bitfield-Mask: 0x03) */ +#define ADC_SL6CFG_CHSEL6_Pos (8UL) /*!< CHSEL6 (Bit 8) */ +#define ADC_SL6CFG_CHSEL6_Msk (0xf00UL) /*!< CHSEL6 (Bitfield-Mask: 0x0f) */ +#define ADC_SL6CFG_WCEN6_Pos (1UL) /*!< WCEN6 (Bit 1) */ +#define ADC_SL6CFG_WCEN6_Msk (0x2UL) /*!< WCEN6 (Bitfield-Mask: 0x01) */ +#define ADC_SL6CFG_SLEN6_Pos (0UL) /*!< SLEN6 (Bit 0) */ +#define ADC_SL6CFG_SLEN6_Msk (0x1UL) /*!< SLEN6 (Bitfield-Mask: 0x01) */ +/* ======================================================== SL7CFG ========================================================= */ +#define ADC_SL7CFG_ADSEL7_Pos (24UL) /*!< ADSEL7 (Bit 24) */ +#define ADC_SL7CFG_ADSEL7_Msk (0x7000000UL) /*!< ADSEL7 (Bitfield-Mask: 0x07) */ +#define ADC_SL7CFG_PRMODE7_Pos (16UL) /*!< PRMODE7 (Bit 16) */ +#define ADC_SL7CFG_PRMODE7_Msk (0x30000UL) /*!< PRMODE7 (Bitfield-Mask: 0x03) */ +#define ADC_SL7CFG_CHSEL7_Pos (8UL) /*!< CHSEL7 (Bit 8) */ +#define ADC_SL7CFG_CHSEL7_Msk (0xf00UL) /*!< CHSEL7 (Bitfield-Mask: 0x0f) */ +#define ADC_SL7CFG_WCEN7_Pos (1UL) /*!< WCEN7 (Bit 1) */ +#define ADC_SL7CFG_WCEN7_Msk (0x2UL) /*!< WCEN7 (Bitfield-Mask: 0x01) */ +#define ADC_SL7CFG_SLEN7_Pos (0UL) /*!< SLEN7 (Bit 0) */ +#define ADC_SL7CFG_SLEN7_Msk (0x1UL) /*!< SLEN7 (Bitfield-Mask: 0x01) */ +/* ========================================================= WULIM ========================================================= */ +#define ADC_WULIM_ULIM_Pos (0UL) /*!< ULIM (Bit 0) */ +#define ADC_WULIM_ULIM_Msk (0xfffffUL) /*!< ULIM (Bitfield-Mask: 0xfffff) */ +/* ========================================================= WLLIM ========================================================= */ +#define ADC_WLLIM_LLIM_Pos (0UL) /*!< LLIM (Bit 0) */ +#define ADC_WLLIM_LLIM_Msk (0xfffffUL) /*!< LLIM (Bitfield-Mask: 0xfffff) */ +/* ======================================================== SCWLIM ========================================================= */ +#define ADC_SCWLIM_SCWLIMEN_Pos (0UL) /*!< SCWLIMEN (Bit 0) */ +#define ADC_SCWLIM_SCWLIMEN_Msk (0x1UL) /*!< SCWLIMEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FIFO ========================================================== */ +#define ADC_FIFO_RSVD_Pos (31UL) /*!< RSVD (Bit 31) */ +#define ADC_FIFO_RSVD_Msk (0x80000000UL) /*!< RSVD (Bitfield-Mask: 0x01) */ +#define ADC_FIFO_SLOTNUM_Pos (28UL) /*!< SLOTNUM (Bit 28) */ +#define ADC_FIFO_SLOTNUM_Msk (0x70000000UL) /*!< SLOTNUM (Bitfield-Mask: 0x07) */ +#define ADC_FIFO_COUNT_Pos (20UL) /*!< COUNT (Bit 20) */ +#define ADC_FIFO_COUNT_Msk (0xff00000UL) /*!< COUNT (Bitfield-Mask: 0xff) */ +#define ADC_FIFO_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define ADC_FIFO_DATA_Msk (0xfffffUL) /*!< DATA (Bitfield-Mask: 0xfffff) */ +/* ======================================================== FIFOPR ========================================================= */ +#define ADC_FIFOPR_RSVDPR_Pos (31UL) /*!< RSVDPR (Bit 31) */ +#define ADC_FIFOPR_RSVDPR_Msk (0x80000000UL) /*!< RSVDPR (Bitfield-Mask: 0x01) */ +#define ADC_FIFOPR_SLOTNUMPR_Pos (28UL) /*!< SLOTNUMPR (Bit 28) */ +#define ADC_FIFOPR_SLOTNUMPR_Msk (0x70000000UL) /*!< SLOTNUMPR (Bitfield-Mask: 0x07) */ +#define ADC_FIFOPR_COUNT_Pos (20UL) /*!< COUNT (Bit 20) */ +#define ADC_FIFOPR_COUNT_Msk (0xff00000UL) /*!< COUNT (Bitfield-Mask: 0xff) */ +#define ADC_FIFOPR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define ADC_FIFOPR_DATA_Msk (0xfffffUL) /*!< DATA (Bitfield-Mask: 0xfffff) */ +/* ========================================================= INTEN ========================================================= */ +#define ADC_INTEN_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTEN_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTEN_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTEN_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTEN_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTEN_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTEN_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTEN_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTEN_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define ADC_INTSTAT_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTSTAT_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTSTAT_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTSTAT_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTSTAT_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTSTAT_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTSTAT_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTSTAT_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSTAT_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTSTAT_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define ADC_INTCLR_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTCLR_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTCLR_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTCLR_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTCLR_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTCLR_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTCLR_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTCLR_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTCLR_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTCLR_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define ADC_INTSET_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define ADC_INTSET_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define ADC_INTSET_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */ +#define ADC_INTSET_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */ +#define ADC_INTSET_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */ +#define ADC_INTSET_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */ +#define ADC_INTSET_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */ +#define ADC_INTSET_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */ +#define ADC_INTSET_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */ +#define ADC_INTSET_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define ADC_DMATRIGEN_DFIFOFULL_Pos (1UL) /*!< DFIFOFULL (Bit 1) */ +#define ADC_DMATRIGEN_DFIFOFULL_Msk (0x2UL) /*!< DFIFOFULL (Bitfield-Mask: 0x01) */ +#define ADC_DMATRIGEN_DFIFO75_Pos (0UL) /*!< DFIFO75 (Bit 0) */ +#define ADC_DMATRIGEN_DFIFO75_Msk (0x1UL) /*!< DFIFO75 (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define ADC_DMATRIGSTAT_DFULLSTAT_Pos (1UL) /*!< DFULLSTAT (Bit 1) */ +#define ADC_DMATRIGSTAT_DFULLSTAT_Msk (0x2UL) /*!< DFULLSTAT (Bitfield-Mask: 0x01) */ +#define ADC_DMATRIGSTAT_D75STAT_Pos (0UL) /*!< D75STAT (Bit 0) */ +#define ADC_DMATRIGSTAT_D75STAT_Msk (0x1UL) /*!< D75STAT (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define ADC_DMACFG_DPWROFF_Pos (18UL) /*!< DPWROFF (Bit 18) */ +#define ADC_DMACFG_DPWROFF_Msk (0x40000UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAMSK_Pos (17UL) /*!< DMAMSK (Bit 17) */ +#define ADC_DMACFG_DMAMSK_Msk (0x20000UL) /*!< DMAMSK (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAHONSTAT_Pos (16UL) /*!< DMAHONSTAT (Bit 16) */ +#define ADC_DMACFG_DMAHONSTAT_Msk (0x10000UL) /*!< DMAHONSTAT (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMADYNPRI_Pos (9UL) /*!< DMADYNPRI (Bit 9) */ +#define ADC_DMACFG_DMADYNPRI_Msk (0x200UL) /*!< DMADYNPRI (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define ADC_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */ +#define ADC_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define ADC_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define ADC_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define ADC_DMATOTCOUNT_TOTCOUNT_Pos (2UL) /*!< TOTCOUNT (Bit 2) */ +#define ADC_DMATOTCOUNT_TOTCOUNT_Msk (0x3fffcUL) /*!< TOTCOUNT (Bitfield-Mask: 0xffff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define ADC_DMATARGADDR_UTARGADDR_Pos (19UL) /*!< UTARGADDR (Bit 19) */ +#define ADC_DMATARGADDR_UTARGADDR_Msk (0xfff80000UL) /*!< UTARGADDR (Bitfield-Mask: 0x1fff) */ +#define ADC_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< LTARGADDR (Bit 0) */ +#define ADC_DMATARGADDR_LTARGADDR_Msk (0x7ffffUL) /*!< LTARGADDR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define ADC_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define ADC_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define ADC_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define ADC_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define ADC_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define ADC_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ APBDMA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BBVALUE ======================================================== */ +#define APBDMA_BBVALUE_PIN_Pos (16UL) /*!< PIN (Bit 16) */ +#define APBDMA_BBVALUE_PIN_Msk (0xff0000UL) /*!< PIN (Bitfield-Mask: 0xff) */ +#define APBDMA_BBVALUE_DATAOUT_Pos (0UL) /*!< DATAOUT (Bit 0) */ +#define APBDMA_BBVALUE_DATAOUT_Msk (0xffUL) /*!< DATAOUT (Bitfield-Mask: 0xff) */ +/* ====================================================== BBSETCLEAR ======================================================= */ +#define APBDMA_BBSETCLEAR_CLEAR_Pos (16UL) /*!< CLEAR (Bit 16) */ +#define APBDMA_BBSETCLEAR_CLEAR_Msk (0xff0000UL) /*!< CLEAR (Bitfield-Mask: 0xff) */ +#define APBDMA_BBSETCLEAR_SET_Pos (0UL) /*!< SET (Bit 0) */ +#define APBDMA_BBSETCLEAR_SET_Msk (0xffUL) /*!< SET (Bitfield-Mask: 0xff) */ +/* ======================================================== BBINPUT ======================================================== */ +#define APBDMA_BBINPUT_DATAIN_Pos (0UL) /*!< DATAIN (Bit 0) */ +#define APBDMA_BBINPUT_DATAIN_Msk (0xffUL) /*!< DATAIN (Bitfield-Mask: 0xff) */ +/* ======================================================= DEBUGDATA ======================================================= */ +#define APBDMA_DEBUGDATA_DEBUGDATA_Pos (0UL) /*!< DEBUGDATA (Bit 0) */ +#define APBDMA_DEBUGDATA_DEBUGDATA_Msk (0xffffffffUL) /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DEBUG ========================================================= */ +#define APBDMA_DEBUG_DEBUGEN_Pos (0UL) /*!< DEBUGEN (Bit 0) */ +#define APBDMA_DEBUG_DEBUGEN_Msk (0xfUL) /*!< DEBUGEN (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ BLEIF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +#define BLEIF_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define BLEIF_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FIFOPTR ======================================================== */ +#define BLEIF_FIFOPTR_FIFO1REM_Pos (24UL) /*!< FIFO1REM (Bit 24) */ +#define BLEIF_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< FIFO1REM (Bitfield-Mask: 0xff) */ +#define BLEIF_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< FIFO1SIZ (Bit 16) */ +#define BLEIF_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< FIFO1SIZ (Bitfield-Mask: 0xff) */ +#define BLEIF_FIFOPTR_FIFO0REM_Pos (8UL) /*!< FIFO0REM (Bit 8) */ +#define BLEIF_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< FIFO0REM (Bitfield-Mask: 0xff) */ +#define BLEIF_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< FIFO0SIZ (Bit 0) */ +#define BLEIF_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< FIFO0SIZ (Bitfield-Mask: 0xff) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define BLEIF_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */ +#define BLEIF_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x3f) */ +#define BLEIF_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */ +#define BLEIF_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< FIFORTHR (Bitfield-Mask: 0x3f) */ +/* ======================================================== FIFOPOP ======================================================== */ +#define BLEIF_FIFOPOP_FIFODOUT_Pos (0UL) /*!< FIFODOUT (Bit 0) */ +#define BLEIF_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< FIFODOUT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOPUSH ======================================================== */ +#define BLEIF_FIFOPUSH_FIFODIN_Pos (0UL) /*!< FIFODIN (Bit 0) */ +#define BLEIF_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< FIFODIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOCTRL ======================================================== */ +#define BLEIF_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< FIFORSTN (Bit 1) */ +#define BLEIF_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< FIFORSTN (Bitfield-Mask: 0x01) */ +#define BLEIF_FIFOCTRL_POPWR_Pos (0UL) /*!< POPWR (Bit 0) */ +#define BLEIF_FIFOCTRL_POPWR_Msk (0x1UL) /*!< POPWR (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOLOC ======================================================== */ +#define BLEIF_FIFOLOC_FIFORPTR_Pos (8UL) /*!< FIFORPTR (Bit 8) */ +#define BLEIF_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< FIFORPTR (Bitfield-Mask: 0x0f) */ +#define BLEIF_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< FIFOWPTR (Bit 0) */ +#define BLEIF_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< FIFOWPTR (Bitfield-Mask: 0x0f) */ +/* ======================================================== CLKCFG ========================================================= */ +#define BLEIF_CLKCFG_DIV3_Pos (12UL) /*!< DIV3 (Bit 12) */ +#define BLEIF_CLKCFG_DIV3_Msk (0x1000UL) /*!< DIV3 (Bitfield-Mask: 0x01) */ +#define BLEIF_CLKCFG_CLK32KEN_Pos (11UL) /*!< CLK32KEN (Bit 11) */ +#define BLEIF_CLKCFG_CLK32KEN_Msk (0x800UL) /*!< CLK32KEN (Bitfield-Mask: 0x01) */ +#define BLEIF_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */ +#define BLEIF_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */ +#define BLEIF_CLKCFG_IOCLKEN_Pos (0UL) /*!< IOCLKEN (Bit 0) */ +#define BLEIF_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ +#define BLEIF_CMD_OFFSETLO_Pos (24UL) /*!< OFFSETLO (Bit 24) */ +#define BLEIF_CMD_OFFSETLO_Msk (0xff000000UL) /*!< OFFSETLO (Bitfield-Mask: 0xff) */ +#define BLEIF_CMD_CMDSEL_Pos (20UL) /*!< CMDSEL (Bit 20) */ +#define BLEIF_CMD_CMDSEL_Msk (0x300000UL) /*!< CMDSEL (Bitfield-Mask: 0x03) */ +#define BLEIF_CMD_TSIZE_Pos (8UL) /*!< TSIZE (Bit 8) */ +#define BLEIF_CMD_TSIZE_Msk (0xfff00UL) /*!< TSIZE (Bitfield-Mask: 0xfff) */ +#define BLEIF_CMD_CONT_Pos (7UL) /*!< CONT (Bit 7) */ +#define BLEIF_CMD_CONT_Msk (0x80UL) /*!< CONT (Bitfield-Mask: 0x01) */ +#define BLEIF_CMD_OFFSETCNT_Pos (5UL) /*!< OFFSETCNT (Bit 5) */ +#define BLEIF_CMD_OFFSETCNT_Msk (0x60UL) /*!< OFFSETCNT (Bitfield-Mask: 0x03) */ +#define BLEIF_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */ +#define BLEIF_CMD_CMD_Msk (0x1fUL) /*!< CMD (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMDRPT ========================================================= */ +#define BLEIF_CMDRPT_CMDRPT_Pos (0UL) /*!< CMDRPT (Bit 0) */ +#define BLEIF_CMDRPT_CMDRPT_Msk (0x1fUL) /*!< CMDRPT (Bitfield-Mask: 0x1f) */ +/* ======================================================= OFFSETHI ======================================================== */ +#define BLEIF_OFFSETHI_OFFSETHI_Pos (0UL) /*!< OFFSETHI (Bit 0) */ +#define BLEIF_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< OFFSETHI (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMDSTAT ======================================================== */ +#define BLEIF_CMDSTAT_CTSIZE_Pos (8UL) /*!< CTSIZE (Bit 8) */ +#define BLEIF_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< CTSIZE (Bitfield-Mask: 0xfff) */ +#define BLEIF_CMDSTAT_CMDSTAT_Pos (5UL) /*!< CMDSTAT (Bit 5) */ +#define BLEIF_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< CMDSTAT (Bitfield-Mask: 0x07) */ +#define BLEIF_CMDSTAT_CCMD_Pos (0UL) /*!< CCMD (Bit 0) */ +#define BLEIF_CMDSTAT_CCMD_Msk (0x1fUL) /*!< CCMD (Bitfield-Mask: 0x1f) */ +/* ========================================================= INTEN ========================================================= */ +#define BLEIF_INTEN_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTEN_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTEN_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTEN_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTEN_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTEN_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTEN_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTEN_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTEN_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTEN_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTEN_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTEN_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTEN_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTEN_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define BLEIF_INTSTAT_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTSTAT_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTSTAT_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTSTAT_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTSTAT_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTSTAT_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTSTAT_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTSTAT_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTSTAT_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTSTAT_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTSTAT_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTSTAT_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTSTAT_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTSTAT_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define BLEIF_INTCLR_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTCLR_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTCLR_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTCLR_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTCLR_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTCLR_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTCLR_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTCLR_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTCLR_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTCLR_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTCLR_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTCLR_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTCLR_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTCLR_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define BLEIF_INTSET_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */ +#define BLEIF_INTSET_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */ +#define BLEIF_INTSET_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */ +#define BLEIF_INTSET_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */ +#define BLEIF_INTSET_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */ +#define BLEIF_INTSET_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */ +#define BLEIF_INTSET_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_DERR_Pos (10UL) /*!< DERR (Bit 10) */ +#define BLEIF_INTSET_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */ +#define BLEIF_INTSET_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */ +#define BLEIF_INTSET_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */ +#define BLEIF_INTSET_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define BLEIF_INTSET_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define BLEIF_INTSET_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */ +#define BLEIF_INTSET_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define BLEIF_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define BLEIF_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define BLEIF_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define BLEIF_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define BLEIF_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define BLEIF_DMATRIGEN_DTHREN_Pos (1UL) /*!< DTHREN (Bit 1) */ +#define BLEIF_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< DTHREN (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< DCMDCMPEN (Bit 0) */ +#define BLEIF_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< DCMDCMPEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define BLEIF_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< DTOTCMP (Bit 2) */ +#define BLEIF_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< DTOTCMP (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATRIGSTAT_DTHR_Pos (1UL) /*!< DTHR (Bit 1) */ +#define BLEIF_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< DTHR (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< DCMDCMP (Bit 0) */ +#define BLEIF_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< DCMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define BLEIF_DMACFG_DPWROFF_Pos (9UL) /*!< DPWROFF (Bit 9) */ +#define BLEIF_DMACFG_DPWROFF_Msk (0x200UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define BLEIF_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define BLEIF_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define BLEIF_DMACFG_DMADIR_Pos (1UL) /*!< DMADIR (Bit 1) */ +#define BLEIF_DMACFG_DMADIR_Msk (0x2UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define BLEIF_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define BLEIF_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define BLEIF_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define BLEIF_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define BLEIF_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< TARGADDR28 (Bit 28) */ +#define BLEIF_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< TARGADDR28 (Bitfield-Mask: 0x01) */ +#define BLEIF_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */ +#define BLEIF_DMATARGADDR_TARGADDR_Msk (0xfffffUL) /*!< TARGADDR (Bitfield-Mask: 0xfffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define BLEIF_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define BLEIF_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define BLEIF_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define BLEIF_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define BLEIF_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define BLEIF_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ +/* ========================================================= CQCFG ========================================================= */ +#define BLEIF_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */ +#define BLEIF_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */ +#define BLEIF_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */ +#define BLEIF_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CQADDR ========================================================= */ +#define BLEIF_CQADDR_CQADDR28_Pos (28UL) /*!< CQADDR28 (Bit 28) */ +#define BLEIF_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< CQADDR28 (Bitfield-Mask: 0x01) */ +#define BLEIF_CQADDR_CQADDR_Pos (2UL) /*!< CQADDR (Bit 2) */ +#define BLEIF_CQADDR_CQADDR_Msk (0xffffcUL) /*!< CQADDR (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== CQSTAT ========================================================= */ +#define BLEIF_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */ +#define BLEIF_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define BLEIF_CQSTAT_CQPAUSED_Pos (1UL) /*!< CQPAUSED (Bit 1) */ +#define BLEIF_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define BLEIF_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */ +#define BLEIF_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */ +/* ======================================================== CQFLAGS ======================================================== */ +#define BLEIF_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< CQIRQMASK (Bit 16) */ +#define BLEIF_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< CQIRQMASK (Bitfield-Mask: 0xffff) */ +#define BLEIF_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */ +#define BLEIF_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CQSETCLEAR ======================================================= */ +#define BLEIF_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */ +#define BLEIF_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */ +#define BLEIF_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< CQFTGL (Bit 8) */ +#define BLEIF_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< CQFTGL (Bitfield-Mask: 0xff) */ +#define BLEIF_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */ +#define BLEIF_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */ +/* ======================================================= CQPAUSEEN ======================================================= */ +#define BLEIF_CQPAUSEEN_CQPEN_Pos (0UL) /*!< CQPEN (Bit 0) */ +#define BLEIF_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< CQPEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= CQCURIDX ======================================================== */ +#define BLEIF_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */ +#define BLEIF_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */ +/* ======================================================= CQENDIDX ======================================================== */ +#define BLEIF_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */ +#define BLEIF_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */ +/* ======================================================== STATUS ========================================================= */ +#define BLEIF_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */ +#define BLEIF_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */ +#define BLEIF_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */ +#define BLEIF_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */ +#define BLEIF_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */ +#define BLEIF_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MSPICFG ======================================================== */ +#define BLEIF_MSPICFG_MSPIRST_Pos (30UL) /*!< MSPIRST (Bit 30) */ +#define BLEIF_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< MSPIRST (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_DOUTDLY_Pos (27UL) /*!< DOUTDLY (Bit 27) */ +#define BLEIF_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< DOUTDLY (Bitfield-Mask: 0x07) */ +#define BLEIF_MSPICFG_DINDLY_Pos (24UL) /*!< DINDLY (Bit 24) */ +#define BLEIF_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< DINDLY (Bitfield-Mask: 0x07) */ +#define BLEIF_MSPICFG_SPILSB_Pos (23UL) /*!< SPILSB (Bit 23) */ +#define BLEIF_MSPICFG_SPILSB_Msk (0x800000UL) /*!< SPILSB (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_RDFCPOL_Pos (22UL) /*!< RDFCPOL (Bit 22) */ +#define BLEIF_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< RDFCPOL (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_WTFCPOL_Pos (21UL) /*!< WTFCPOL (Bit 21) */ +#define BLEIF_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< WTFCPOL (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_RDFC_Pos (17UL) /*!< RDFC (Bit 17) */ +#define BLEIF_MSPICFG_RDFC_Msk (0x20000UL) /*!< RDFC (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_WTFC_Pos (16UL) /*!< WTFC (Bit 16) */ +#define BLEIF_MSPICFG_WTFC_Msk (0x10000UL) /*!< WTFC (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_FULLDUP_Pos (2UL) /*!< FULLDUP (Bit 2) */ +#define BLEIF_MSPICFG_FULLDUP_Msk (0x4UL) /*!< FULLDUP (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_SPHA_Pos (1UL) /*!< SPHA (Bit 1) */ +#define BLEIF_MSPICFG_SPHA_Msk (0x2UL) /*!< SPHA (Bitfield-Mask: 0x01) */ +#define BLEIF_MSPICFG_SPOL_Pos (0UL) /*!< SPOL (Bit 0) */ +#define BLEIF_MSPICFG_SPOL_Msk (0x1UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +/* ======================================================== BLECFG ========================================================= */ +#define BLEIF_BLECFG_SPIISOCTL_Pos (14UL) /*!< SPIISOCTL (Bit 14) */ +#define BLEIF_BLECFG_SPIISOCTL_Msk (0xc000UL) /*!< SPIISOCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_PWRISOCTL_Pos (12UL) /*!< PWRISOCTL (Bit 12) */ +#define BLEIF_BLECFG_PWRISOCTL_Msk (0x3000UL) /*!< PWRISOCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_STAYASLEEP_Pos (11UL) /*!< STAYASLEEP (Bit 11) */ +#define BLEIF_BLECFG_STAYASLEEP_Msk (0x800UL) /*!< STAYASLEEP (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_FRCCLK_Pos (10UL) /*!< FRCCLK (Bit 10) */ +#define BLEIF_BLECFG_FRCCLK_Msk (0x400UL) /*!< FRCCLK (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_MCUFRCSLP_Pos (9UL) /*!< MCUFRCSLP (Bit 9) */ +#define BLEIF_BLECFG_MCUFRCSLP_Msk (0x200UL) /*!< MCUFRCSLP (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_WT4ACTOFF_Pos (8UL) /*!< WT4ACTOFF (Bit 8) */ +#define BLEIF_BLECFG_WT4ACTOFF_Msk (0x100UL) /*!< WT4ACTOFF (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_BLEHREQCTL_Pos (6UL) /*!< BLEHREQCTL (Bit 6) */ +#define BLEIF_BLECFG_BLEHREQCTL_Msk (0xc0UL) /*!< BLEHREQCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_DCDCFLGCTL_Pos (4UL) /*!< DCDCFLGCTL (Bit 4) */ +#define BLEIF_BLECFG_DCDCFLGCTL_Msk (0x30UL) /*!< DCDCFLGCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_WAKEUPCTL_Pos (2UL) /*!< WAKEUPCTL (Bit 2) */ +#define BLEIF_BLECFG_WAKEUPCTL_Msk (0xcUL) /*!< WAKEUPCTL (Bitfield-Mask: 0x03) */ +#define BLEIF_BLECFG_BLERSTN_Pos (1UL) /*!< BLERSTN (Bit 1) */ +#define BLEIF_BLECFG_BLERSTN_Msk (0x2UL) /*!< BLERSTN (Bitfield-Mask: 0x01) */ +#define BLEIF_BLECFG_PWRSMEN_Pos (0UL) /*!< PWRSMEN (Bit 0) */ +#define BLEIF_BLECFG_PWRSMEN_Msk (0x1UL) /*!< PWRSMEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PWRCMD ========================================================= */ +#define BLEIF_PWRCMD_RESTART_Pos (1UL) /*!< RESTART (Bit 1) */ +#define BLEIF_PWRCMD_RESTART_Msk (0x2UL) /*!< RESTART (Bitfield-Mask: 0x01) */ +#define BLEIF_PWRCMD_WAKEREQ_Pos (0UL) /*!< WAKEREQ (Bit 0) */ +#define BLEIF_PWRCMD_WAKEREQ_Msk (0x1UL) /*!< WAKEREQ (Bitfield-Mask: 0x01) */ +/* ======================================================== BSTATUS ======================================================== */ +#define BLEIF_BSTATUS_BLEHREQ_Pos (12UL) /*!< BLEHREQ (Bit 12) */ +#define BLEIF_BSTATUS_BLEHREQ_Msk (0x1000UL) /*!< BLEHREQ (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_BLEHACK_Pos (11UL) /*!< BLEHACK (Bit 11) */ +#define BLEIF_BSTATUS_BLEHACK_Msk (0x800UL) /*!< BLEHACK (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_PWRST_Pos (8UL) /*!< PWRST (Bit 8) */ +#define BLEIF_BSTATUS_PWRST_Msk (0x700UL) /*!< PWRST (Bitfield-Mask: 0x07) */ +#define BLEIF_BSTATUS_BLEIRQ_Pos (7UL) /*!< BLEIRQ (Bit 7) */ +#define BLEIF_BSTATUS_BLEIRQ_Msk (0x80UL) /*!< BLEIRQ (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_WAKEUP_Pos (6UL) /*!< WAKEUP (Bit 6) */ +#define BLEIF_BSTATUS_WAKEUP_Msk (0x40UL) /*!< WAKEUP (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_DCDCFLAG_Pos (5UL) /*!< DCDCFLAG (Bit 5) */ +#define BLEIF_BSTATUS_DCDCFLAG_Msk (0x20UL) /*!< DCDCFLAG (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_DCDCREQ_Pos (4UL) /*!< DCDCREQ (Bit 4) */ +#define BLEIF_BSTATUS_DCDCREQ_Msk (0x10UL) /*!< DCDCREQ (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_SPISTATUS_Pos (3UL) /*!< SPISTATUS (Bit 3) */ +#define BLEIF_BSTATUS_SPISTATUS_Msk (0x8UL) /*!< SPISTATUS (Bitfield-Mask: 0x01) */ +#define BLEIF_BSTATUS_B2MSTATE_Pos (0UL) /*!< B2MSTATE (Bit 0) */ +#define BLEIF_BSTATUS_B2MSTATE_Msk (0x7UL) /*!< B2MSTATE (Bitfield-Mask: 0x07) */ +/* ======================================================== BLEDBG ========================================================= */ +#define BLEIF_BLEDBG_DBGDATA_Pos (3UL) /*!< DBGDATA (Bit 3) */ +#define BLEIF_BLEDBG_DBGDATA_Msk (0xfffffff8UL) /*!< DBGDATA (Bitfield-Mask: 0x1fffffff) */ +#define BLEIF_BLEDBG_APBCLKON_Pos (2UL) /*!< APBCLKON (Bit 2) */ +#define BLEIF_BLEDBG_APBCLKON_Msk (0x4UL) /*!< APBCLKON (Bitfield-Mask: 0x01) */ +#define BLEIF_BLEDBG_IOCLKON_Pos (1UL) /*!< IOCLKON (Bit 1) */ +#define BLEIF_BLEDBG_IOCLKON_Msk (0x2UL) /*!< IOCLKON (Bitfield-Mask: 0x01) */ +#define BLEIF_BLEDBG_DBGEN_Pos (0UL) /*!< DBGEN (Bit 0) */ +#define BLEIF_BLEDBG_DBGEN_Msk (0x1UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CACHECFG ======================================================== */ +#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Pos (24UL) /*!< ENABLE_MONITOR (Bit 24) */ +#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk (0x1000000UL) /*!< ENABLE_MONITOR (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_DATA_CLKGATE_Pos (20UL) /*!< DATA_CLKGATE (Bit 20) */ +#define CACHECTRL_CACHECFG_DATA_CLKGATE_Msk (0x100000UL) /*!< DATA_CLKGATE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CACHE_LS_Pos (11UL) /*!< CACHE_LS (Bit 11) */ +#define CACHECTRL_CACHECFG_CACHE_LS_Msk (0x800UL) /*!< CACHE_LS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Pos (10UL) /*!< CACHE_CLKGATE (Bit 10) */ +#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Msk (0x400UL) /*!< CACHE_CLKGATE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Pos (9UL) /*!< DCACHE_ENABLE (Bit 9) */ +#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk (0x200UL) /*!< DCACHE_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos (8UL) /*!< ICACHE_ENABLE (Bit 8) */ +#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk (0x100UL) /*!< ICACHE_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_CONFIG_Pos (4UL) /*!< CONFIG (Bit 4) */ +#define CACHECTRL_CACHECFG_CONFIG_Msk (0xf0UL) /*!< CONFIG (Bitfield-Mask: 0x0f) */ +#define CACHECTRL_CACHECFG_ENABLE_NC1_Pos (3UL) /*!< ENABLE_NC1 (Bit 3) */ +#define CACHECTRL_CACHECFG_ENABLE_NC1_Msk (0x8UL) /*!< ENABLE_NC1 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ENABLE_NC0_Pos (2UL) /*!< ENABLE_NC0 (Bit 2) */ +#define CACHECTRL_CACHECFG_ENABLE_NC0_Msk (0x4UL) /*!< ENABLE_NC0 (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_LRU_Pos (1UL) /*!< LRU (Bit 1) */ +#define CACHECTRL_CACHECFG_LRU_Msk (0x2UL) /*!< LRU (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CACHECFG_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define CACHECTRL_CACHECFG_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= FLASHCFG ======================================================== */ +#define CACHECTRL_FLASHCFG_LPMMODE_Pos (12UL) /*!< LPMMODE (Bit 12) */ +#define CACHECTRL_FLASHCFG_LPMMODE_Msk (0x3000UL) /*!< LPMMODE (Bitfield-Mask: 0x03) */ +#define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Pos (8UL) /*!< LPM_RD_WAIT (Bit 8) */ +#define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk (0xf00UL) /*!< LPM_RD_WAIT (Bitfield-Mask: 0x0f) */ +#define CACHECTRL_FLASHCFG_SEDELAY_Pos (4UL) /*!< SEDELAY (Bit 4) */ +#define CACHECTRL_FLASHCFG_SEDELAY_Msk (0x70UL) /*!< SEDELAY (Bitfield-Mask: 0x07) */ +#define CACHECTRL_FLASHCFG_RD_WAIT_Pos (0UL) /*!< RD_WAIT (Bit 0) */ +#define CACHECTRL_FLASHCFG_RD_WAIT_Msk (0xfUL) /*!< RD_WAIT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CTRL ========================================================== */ +#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Pos (10UL) /*!< FLASH1_SLM_ENABLE (Bit 10) */ +#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk (0x400UL) /*!< FLASH1_SLM_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Pos (9UL) /*!< FLASH1_SLM_DISABLE (Bit 9) */ +#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk (0x200UL) /*!< FLASH1_SLM_DISABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Pos (8UL) /*!< FLASH1_SLM_STATUS (Bit 8) */ +#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Msk (0x100UL) /*!< FLASH1_SLM_STATUS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Pos (6UL) /*!< FLASH0_SLM_ENABLE (Bit 6) */ +#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk (0x40UL) /*!< FLASH0_SLM_ENABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Pos (5UL) /*!< FLASH0_SLM_DISABLE (Bit 5) */ +#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk (0x20UL) /*!< FLASH0_SLM_DISABLE (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Pos (4UL) /*!< FLASH0_SLM_STATUS (Bit 4) */ +#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Msk (0x10UL) /*!< FLASH0_SLM_STATUS (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_CACHE_READY_Pos (2UL) /*!< CACHE_READY (Bit 2) */ +#define CACHECTRL_CTRL_CACHE_READY_Msk (0x4UL) /*!< CACHE_READY (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_RESET_STAT_Pos (1UL) /*!< RESET_STAT (Bit 1) */ +#define CACHECTRL_CTRL_RESET_STAT_Msk (0x2UL) /*!< RESET_STAT (Bitfield-Mask: 0x01) */ +#define CACHECTRL_CTRL_INVALIDATE_Pos (0UL) /*!< INVALIDATE (Bit 0) */ +#define CACHECTRL_CTRL_INVALIDATE_Msk (0x1UL) /*!< INVALIDATE (Bitfield-Mask: 0x01) */ +/* ======================================================= NCR0START ======================================================= */ +#define CACHECTRL_NCR0START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR0START_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== NCR0END ======================================================== */ +#define CACHECTRL_NCR0END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR0END_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= NCR1START ======================================================= */ +#define CACHECTRL_NCR1START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR1START_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== NCR1END ======================================================== */ +#define CACHECTRL_NCR1END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */ +#define CACHECTRL_NCR1END_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= DMON0 ========================================================= */ +#define CACHECTRL_DMON0_DACCESS_COUNT_Pos (0UL) /*!< DACCESS_COUNT (Bit 0) */ +#define CACHECTRL_DMON0_DACCESS_COUNT_Msk (0xffffffffUL) /*!< DACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON1 ========================================================= */ +#define CACHECTRL_DMON1_DLOOKUP_COUNT_Pos (0UL) /*!< DLOOKUP_COUNT (Bit 0) */ +#define CACHECTRL_DMON1_DLOOKUP_COUNT_Msk (0xffffffffUL) /*!< DLOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON2 ========================================================= */ +#define CACHECTRL_DMON2_DHIT_COUNT_Pos (0UL) /*!< DHIT_COUNT (Bit 0) */ +#define CACHECTRL_DMON2_DHIT_COUNT_Msk (0xffffffffUL) /*!< DHIT_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMON3 ========================================================= */ +#define CACHECTRL_DMON3_DLINE_COUNT_Pos (0UL) /*!< DLINE_COUNT (Bit 0) */ +#define CACHECTRL_DMON3_DLINE_COUNT_Msk (0xffffffffUL) /*!< DLINE_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON0 ========================================================= */ +#define CACHECTRL_IMON0_IACCESS_COUNT_Pos (0UL) /*!< IACCESS_COUNT (Bit 0) */ +#define CACHECTRL_IMON0_IACCESS_COUNT_Msk (0xffffffffUL) /*!< IACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON1 ========================================================= */ +#define CACHECTRL_IMON1_ILOOKUP_COUNT_Pos (0UL) /*!< ILOOKUP_COUNT (Bit 0) */ +#define CACHECTRL_IMON1_ILOOKUP_COUNT_Msk (0xffffffffUL) /*!< ILOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON2 ========================================================= */ +#define CACHECTRL_IMON2_IHIT_COUNT_Pos (0UL) /*!< IHIT_COUNT (Bit 0) */ +#define CACHECTRL_IMON2_IHIT_COUNT_Msk (0xffffffffUL) /*!< IHIT_COUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= IMON3 ========================================================= */ +#define CACHECTRL_IMON3_ILINE_COUNT_Pos (0UL) /*!< ILINE_COUNT (Bit 0) */ +#define CACHECTRL_IMON3_ILINE_COUNT_Msk (0xffffffffUL) /*!< ILINE_COUNT (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CALXT ========================================================= */ +#define CLKGEN_CALXT_CALXT_Pos (0UL) /*!< CALXT (Bit 0) */ +#define CLKGEN_CALXT_CALXT_Msk (0x7ffUL) /*!< CALXT (Bitfield-Mask: 0x7ff) */ +/* ========================================================= CALRC ========================================================= */ +#define CLKGEN_CALRC_CALRC_Pos (0UL) /*!< CALRC (Bit 0) */ +#define CLKGEN_CALRC_CALRC_Msk (0x3ffffUL) /*!< CALRC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== ACALCTR ======================================================== */ +#define CLKGEN_ACALCTR_ACALCTR_Pos (0UL) /*!< ACALCTR (Bit 0) */ +#define CLKGEN_ACALCTR_ACALCTR_Msk (0xffffffUL) /*!< ACALCTR (Bitfield-Mask: 0xffffff) */ +/* ========================================================= OCTRL ========================================================= */ +#define CLKGEN_OCTRL_ACAL_Pos (8UL) /*!< ACAL (Bit 8) */ +#define CLKGEN_OCTRL_ACAL_Msk (0x700UL) /*!< ACAL (Bitfield-Mask: 0x07) */ +#define CLKGEN_OCTRL_OSEL_Pos (7UL) /*!< OSEL (Bit 7) */ +#define CLKGEN_OCTRL_OSEL_Msk (0x80UL) /*!< OSEL (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_FOS_Pos (6UL) /*!< FOS (Bit 6) */ +#define CLKGEN_OCTRL_FOS_Msk (0x40UL) /*!< FOS (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_STOPRC_Pos (1UL) /*!< STOPRC (Bit 1) */ +#define CLKGEN_OCTRL_STOPRC_Msk (0x2UL) /*!< STOPRC (Bitfield-Mask: 0x01) */ +#define CLKGEN_OCTRL_STOPXT_Pos (0UL) /*!< STOPXT (Bit 0) */ +#define CLKGEN_OCTRL_STOPXT_Msk (0x1UL) /*!< STOPXT (Bitfield-Mask: 0x01) */ +/* ======================================================== CLKOUT ========================================================= */ +#define CLKGEN_CLKOUT_CKEN_Pos (7UL) /*!< CKEN (Bit 7) */ +#define CLKGEN_CLKOUT_CKEN_Msk (0x80UL) /*!< CKEN (Bitfield-Mask: 0x01) */ +#define CLKGEN_CLKOUT_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ +#define CLKGEN_CLKOUT_CKSEL_Msk (0x3fUL) /*!< CKSEL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CLKKEY ========================================================= */ +#define CLKGEN_CLKKEY_CLKKEY_Pos (0UL) /*!< CLKKEY (Bit 0) */ +#define CLKGEN_CLKKEY_CLKKEY_Msk (0xffffffffUL) /*!< CLKKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CCTRL ========================================================= */ +#define CLKGEN_CCTRL_CORESEL_Pos (0UL) /*!< CORESEL (Bit 0) */ +#define CLKGEN_CCTRL_CORESEL_Msk (0x1UL) /*!< CORESEL (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ +#define CLKGEN_STATUS_OSCF_Pos (1UL) /*!< OSCF (Bit 1) */ +#define CLKGEN_STATUS_OSCF_Msk (0x2UL) /*!< OSCF (Bitfield-Mask: 0x01) */ +#define CLKGEN_STATUS_OMODE_Pos (0UL) /*!< OMODE (Bit 0) */ +#define CLKGEN_STATUS_OMODE_Msk (0x1UL) /*!< OMODE (Bitfield-Mask: 0x01) */ +/* ========================================================= HFADJ ========================================================= */ +#define CLKGEN_HFADJ_HFADJGAIN_Pos (21UL) /*!< HFADJGAIN (Bit 21) */ +#define CLKGEN_HFADJ_HFADJGAIN_Msk (0xe00000UL) /*!< HFADJGAIN (Bitfield-Mask: 0x07) */ +#define CLKGEN_HFADJ_HFWARMUP_Pos (20UL) /*!< HFWARMUP (Bit 20) */ +#define CLKGEN_HFADJ_HFWARMUP_Msk (0x100000UL) /*!< HFWARMUP (Bitfield-Mask: 0x01) */ +#define CLKGEN_HFADJ_HFXTADJ_Pos (8UL) /*!< HFXTADJ (Bit 8) */ +#define CLKGEN_HFADJ_HFXTADJ_Msk (0xfff00UL) /*!< HFXTADJ (Bitfield-Mask: 0xfff) */ +#define CLKGEN_HFADJ_HFADJCK_Pos (1UL) /*!< HFADJCK (Bit 1) */ +#define CLKGEN_HFADJ_HFADJCK_Msk (0xeUL) /*!< HFADJCK (Bitfield-Mask: 0x07) */ +#define CLKGEN_HFADJ_HFADJEN_Pos (0UL) /*!< HFADJEN (Bit 0) */ +#define CLKGEN_HFADJ_HFADJEN_Msk (0x1UL) /*!< HFADJEN (Bitfield-Mask: 0x01) */ +/* ====================================================== CLOCKENSTAT ====================================================== */ +#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL) /*!< CLOCKENSTAT (Bit 0) */ +#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL) /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CLOCKEN2STAT ====================================================== */ +#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL) /*!< CLOCKEN2STAT (Bit 0) */ +#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL) /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CLOCKEN3STAT ====================================================== */ +#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL) /*!< CLOCKEN3STAT (Bit 0) */ +#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL) /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FREQCTRL ======================================================== */ +#define CLKGEN_FREQCTRL_BURSTSTATUS_Pos (2UL) /*!< BURSTSTATUS (Bit 2) */ +#define CLKGEN_FREQCTRL_BURSTSTATUS_Msk (0x4UL) /*!< BURSTSTATUS (Bitfield-Mask: 0x01) */ +#define CLKGEN_FREQCTRL_BURSTACK_Pos (1UL) /*!< BURSTACK (Bit 1) */ +#define CLKGEN_FREQCTRL_BURSTACK_Msk (0x2UL) /*!< BURSTACK (Bitfield-Mask: 0x01) */ +#define CLKGEN_FREQCTRL_BURSTREQ_Pos (0UL) /*!< BURSTREQ (Bit 0) */ +#define CLKGEN_FREQCTRL_BURSTREQ_Msk (0x1UL) /*!< BURSTREQ (Bitfield-Mask: 0x01) */ +/* ===================================================== BLEBUCKTONADJ ===================================================== */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Pos (27UL) /*!< ZEROLENDETECTEN (Bit 27) */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Msk (0x8000000UL) /*!< ZEROLENDETECTEN (Bitfield-Mask: 0x01) */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Pos (23UL) /*!< ZEROLENDETECTTRIM (Bit 23) */ +#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Msk (0x7800000UL) /*!< ZEROLENDETECTTRIM (Bitfield-Mask: 0x0f) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Pos (22UL) /*!< TONADJUSTEN (Bit 22) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Msk (0x400000UL) /*!< TONADJUSTEN (Bitfield-Mask: 0x01) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Pos (20UL) /*!< TONADJUSTPERIOD (Bit 20) */ +#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Msk (0x300000UL) /*!< TONADJUSTPERIOD (Bitfield-Mask: 0x03) */ +#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Pos (10UL) /*!< TONHIGHTHRESHOLD (Bit 10) */ +#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Msk (0xffc00UL) /*!< TONHIGHTHRESHOLD (Bitfield-Mask: 0x3ff) */ +#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Pos (0UL) /*!< TONLOWTHRESHOLD (Bit 0) */ +#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Msk (0x3ffUL) /*!< TONLOWTHRESHOLD (Bitfield-Mask: 0x3ff) */ +/* ======================================================= INTRPTEN ======================================================== */ +#define CLKGEN_INTRPTEN_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTEN_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTEN_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTEN_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTEN_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTEN_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ====================================================== INTRPTSTAT ======================================================= */ +#define CLKGEN_INTRPTSTAT_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTSTAT_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSTAT_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTSTAT_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSTAT_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTSTAT_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================= INTRPTCLR ======================================================= */ +#define CLKGEN_INTRPTCLR_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTCLR_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTCLR_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTCLR_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTCLR_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTCLR_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ +/* ======================================================= INTRPTSET ======================================================= */ +#define CLKGEN_INTRPTSET_OF_Pos (2UL) /*!< OF (Bit 2) */ +#define CLKGEN_INTRPTSET_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSET_ACC_Pos (1UL) /*!< ACC (Bit 1) */ +#define CLKGEN_INTRPTSET_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */ +#define CLKGEN_INTRPTSET_ACF_Pos (0UL) /*!< ACF (Bit 0) */ +#define CLKGEN_INTRPTSET_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TMR0 ========================================================== */ +#define CTIMER_TMR0_CTTMRB0_Pos (16UL) /*!< CTTMRB0 (Bit 16) */ +#define CTIMER_TMR0_CTTMRB0_Msk (0xffff0000UL) /*!< CTTMRB0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR0_CTTMRA0_Pos (0UL) /*!< CTTMRA0 (Bit 0) */ +#define CTIMER_TMR0_CTTMRA0_Msk (0xffffUL) /*!< CTTMRA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA0 ========================================================= */ +#define CTIMER_CMPRA0_CMPR1A0_Pos (16UL) /*!< CMPR1A0 (Bit 16) */ +#define CTIMER_CMPRA0_CMPR1A0_Msk (0xffff0000UL) /*!< CMPR1A0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA0_CMPR0A0_Pos (0UL) /*!< CMPR0A0 (Bit 0) */ +#define CTIMER_CMPRA0_CMPR0A0_Msk (0xffffUL) /*!< CMPR0A0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB0 ========================================================= */ +#define CTIMER_CMPRB0_CMPR1B0_Pos (16UL) /*!< CMPR1B0 (Bit 16) */ +#define CTIMER_CMPRB0_CMPR1B0_Msk (0xffff0000UL) /*!< CMPR1B0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB0_CMPR0B0_Pos (0UL) /*!< CMPR0B0 (Bit 0) */ +#define CTIMER_CMPRB0_CMPR0B0_Msk (0xffffUL) /*!< CMPR0B0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL0 ========================================================= */ +#define CTIMER_CTRL0_CTLINK0_Pos (31UL) /*!< CTLINK0 (Bit 31) */ +#define CTIMER_CTRL0_CTLINK0_Msk (0x80000000UL) /*!< CTLINK0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0POL_Pos (28UL) /*!< TMRB0POL (Bit 28) */ +#define CTIMER_CTRL0_TMRB0POL_Msk (0x10000000UL) /*!< TMRB0POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0CLR_Pos (27UL) /*!< TMRB0CLR (Bit 27) */ +#define CTIMER_CTRL0_TMRB0CLR_Msk (0x8000000UL) /*!< TMRB0CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0IE1_Pos (26UL) /*!< TMRB0IE1 (Bit 26) */ +#define CTIMER_CTRL0_TMRB0IE1_Msk (0x4000000UL) /*!< TMRB0IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0IE0_Pos (25UL) /*!< TMRB0IE0 (Bit 25) */ +#define CTIMER_CTRL0_TMRB0IE0_Msk (0x2000000UL) /*!< TMRB0IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRB0FN_Pos (22UL) /*!< TMRB0FN (Bit 22) */ +#define CTIMER_CTRL0_TMRB0FN_Msk (0x1c00000UL) /*!< TMRB0FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL0_TMRB0CLK_Pos (17UL) /*!< TMRB0CLK (Bit 17) */ +#define CTIMER_CTRL0_TMRB0CLK_Msk (0x3e0000UL) /*!< TMRB0CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL0_TMRB0EN_Pos (16UL) /*!< TMRB0EN (Bit 16) */ +#define CTIMER_CTRL0_TMRB0EN_Msk (0x10000UL) /*!< TMRB0EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0POL_Pos (12UL) /*!< TMRA0POL (Bit 12) */ +#define CTIMER_CTRL0_TMRA0POL_Msk (0x1000UL) /*!< TMRA0POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0CLR_Pos (11UL) /*!< TMRA0CLR (Bit 11) */ +#define CTIMER_CTRL0_TMRA0CLR_Msk (0x800UL) /*!< TMRA0CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0IE1_Pos (10UL) /*!< TMRA0IE1 (Bit 10) */ +#define CTIMER_CTRL0_TMRA0IE1_Msk (0x400UL) /*!< TMRA0IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0IE0_Pos (9UL) /*!< TMRA0IE0 (Bit 9) */ +#define CTIMER_CTRL0_TMRA0IE0_Msk (0x200UL) /*!< TMRA0IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL0_TMRA0FN_Pos (6UL) /*!< TMRA0FN (Bit 6) */ +#define CTIMER_CTRL0_TMRA0FN_Msk (0x1c0UL) /*!< TMRA0FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL0_TMRA0CLK_Pos (1UL) /*!< TMRA0CLK (Bit 1) */ +#define CTIMER_CTRL0_TMRA0CLK_Msk (0x3eUL) /*!< TMRA0CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL0_TMRA0EN_Pos (0UL) /*!< TMRA0EN (Bit 0) */ +#define CTIMER_CTRL0_TMRA0EN_Msk (0x1UL) /*!< TMRA0EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA0 ======================================================= */ +#define CTIMER_CMPRAUXA0_CMPR3A0_Pos (16UL) /*!< CMPR3A0 (Bit 16) */ +#define CTIMER_CMPRAUXA0_CMPR3A0_Msk (0xffff0000UL) /*!< CMPR3A0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA0_CMPR2A0_Pos (0UL) /*!< CMPR2A0 (Bit 0) */ +#define CTIMER_CMPRAUXA0_CMPR2A0_Msk (0xffffUL) /*!< CMPR2A0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB0 ======================================================= */ +#define CTIMER_CMPRAUXB0_CMPR3B0_Pos (16UL) /*!< CMPR3B0 (Bit 16) */ +#define CTIMER_CMPRAUXB0_CMPR3B0_Msk (0xffff0000UL) /*!< CMPR3B0 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB0_CMPR2B0_Pos (0UL) /*!< CMPR2B0 (Bit 0) */ +#define CTIMER_CMPRAUXB0_CMPR2B0_Msk (0xffffUL) /*!< CMPR2B0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX0 ========================================================== */ +#define CTIMER_AUX0_TMRB0EN23_Pos (30UL) /*!< TMRB0EN23 (Bit 30) */ +#define CTIMER_AUX0_TMRB0EN23_Msk (0x40000000UL) /*!< TMRB0EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0POL23_Pos (29UL) /*!< TMRB0POL23 (Bit 29) */ +#define CTIMER_AUX0_TMRB0POL23_Msk (0x20000000UL) /*!< TMRB0POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0TINV_Pos (28UL) /*!< TMRB0TINV (Bit 28) */ +#define CTIMER_AUX0_TMRB0TINV_Msk (0x10000000UL) /*!< TMRB0TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0NOSYNC_Pos (27UL) /*!< TMRB0NOSYNC (Bit 27) */ +#define CTIMER_AUX0_TMRB0NOSYNC_Msk (0x8000000UL) /*!< TMRB0NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRB0TRIG_Pos (23UL) /*!< TMRB0TRIG (Bit 23) */ +#define CTIMER_AUX0_TMRB0TRIG_Msk (0x7800000UL) /*!< TMRB0TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX0_TMRB0LMT_Pos (16UL) /*!< TMRB0LMT (Bit 16) */ +#define CTIMER_AUX0_TMRB0LMT_Msk (0x3f0000UL) /*!< TMRB0LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX0_TMRA0EN23_Pos (14UL) /*!< TMRA0EN23 (Bit 14) */ +#define CTIMER_AUX0_TMRA0EN23_Msk (0x4000UL) /*!< TMRA0EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0POL23_Pos (13UL) /*!< TMRA0POL23 (Bit 13) */ +#define CTIMER_AUX0_TMRA0POL23_Msk (0x2000UL) /*!< TMRA0POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0TINV_Pos (12UL) /*!< TMRA0TINV (Bit 12) */ +#define CTIMER_AUX0_TMRA0TINV_Msk (0x1000UL) /*!< TMRA0TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0NOSYNC_Pos (11UL) /*!< TMRA0NOSYNC (Bit 11) */ +#define CTIMER_AUX0_TMRA0NOSYNC_Msk (0x800UL) /*!< TMRA0NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX0_TMRA0TRIG_Pos (7UL) /*!< TMRA0TRIG (Bit 7) */ +#define CTIMER_AUX0_TMRA0TRIG_Msk (0x780UL) /*!< TMRA0TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX0_TMRA0LMT_Pos (0UL) /*!< TMRA0LMT (Bit 0) */ +#define CTIMER_AUX0_TMRA0LMT_Msk (0x7fUL) /*!< TMRA0LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR1 ========================================================== */ +#define CTIMER_TMR1_CTTMRB1_Pos (16UL) /*!< CTTMRB1 (Bit 16) */ +#define CTIMER_TMR1_CTTMRB1_Msk (0xffff0000UL) /*!< CTTMRB1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR1_CTTMRA1_Pos (0UL) /*!< CTTMRA1 (Bit 0) */ +#define CTIMER_TMR1_CTTMRA1_Msk (0xffffUL) /*!< CTTMRA1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA1 ========================================================= */ +#define CTIMER_CMPRA1_CMPR1A1_Pos (16UL) /*!< CMPR1A1 (Bit 16) */ +#define CTIMER_CMPRA1_CMPR1A1_Msk (0xffff0000UL) /*!< CMPR1A1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA1_CMPR0A1_Pos (0UL) /*!< CMPR0A1 (Bit 0) */ +#define CTIMER_CMPRA1_CMPR0A1_Msk (0xffffUL) /*!< CMPR0A1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB1 ========================================================= */ +#define CTIMER_CMPRB1_CMPR1B1_Pos (16UL) /*!< CMPR1B1 (Bit 16) */ +#define CTIMER_CMPRB1_CMPR1B1_Msk (0xffff0000UL) /*!< CMPR1B1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB1_CMPR0B1_Pos (0UL) /*!< CMPR0B1 (Bit 0) */ +#define CTIMER_CMPRB1_CMPR0B1_Msk (0xffffUL) /*!< CMPR0B1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL1 ========================================================= */ +#define CTIMER_CTRL1_CTLINK1_Pos (31UL) /*!< CTLINK1 (Bit 31) */ +#define CTIMER_CTRL1_CTLINK1_Msk (0x80000000UL) /*!< CTLINK1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1POL_Pos (28UL) /*!< TMRB1POL (Bit 28) */ +#define CTIMER_CTRL1_TMRB1POL_Msk (0x10000000UL) /*!< TMRB1POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1CLR_Pos (27UL) /*!< TMRB1CLR (Bit 27) */ +#define CTIMER_CTRL1_TMRB1CLR_Msk (0x8000000UL) /*!< TMRB1CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1IE1_Pos (26UL) /*!< TMRB1IE1 (Bit 26) */ +#define CTIMER_CTRL1_TMRB1IE1_Msk (0x4000000UL) /*!< TMRB1IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1IE0_Pos (25UL) /*!< TMRB1IE0 (Bit 25) */ +#define CTIMER_CTRL1_TMRB1IE0_Msk (0x2000000UL) /*!< TMRB1IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRB1FN_Pos (22UL) /*!< TMRB1FN (Bit 22) */ +#define CTIMER_CTRL1_TMRB1FN_Msk (0x1c00000UL) /*!< TMRB1FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL1_TMRB1CLK_Pos (17UL) /*!< TMRB1CLK (Bit 17) */ +#define CTIMER_CTRL1_TMRB1CLK_Msk (0x3e0000UL) /*!< TMRB1CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL1_TMRB1EN_Pos (16UL) /*!< TMRB1EN (Bit 16) */ +#define CTIMER_CTRL1_TMRB1EN_Msk (0x10000UL) /*!< TMRB1EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1POL_Pos (12UL) /*!< TMRA1POL (Bit 12) */ +#define CTIMER_CTRL1_TMRA1POL_Msk (0x1000UL) /*!< TMRA1POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1CLR_Pos (11UL) /*!< TMRA1CLR (Bit 11) */ +#define CTIMER_CTRL1_TMRA1CLR_Msk (0x800UL) /*!< TMRA1CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1IE1_Pos (10UL) /*!< TMRA1IE1 (Bit 10) */ +#define CTIMER_CTRL1_TMRA1IE1_Msk (0x400UL) /*!< TMRA1IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1IE0_Pos (9UL) /*!< TMRA1IE0 (Bit 9) */ +#define CTIMER_CTRL1_TMRA1IE0_Msk (0x200UL) /*!< TMRA1IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL1_TMRA1FN_Pos (6UL) /*!< TMRA1FN (Bit 6) */ +#define CTIMER_CTRL1_TMRA1FN_Msk (0x1c0UL) /*!< TMRA1FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL1_TMRA1CLK_Pos (1UL) /*!< TMRA1CLK (Bit 1) */ +#define CTIMER_CTRL1_TMRA1CLK_Msk (0x3eUL) /*!< TMRA1CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL1_TMRA1EN_Pos (0UL) /*!< TMRA1EN (Bit 0) */ +#define CTIMER_CTRL1_TMRA1EN_Msk (0x1UL) /*!< TMRA1EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA1 ======================================================= */ +#define CTIMER_CMPRAUXA1_CMPR3A1_Pos (16UL) /*!< CMPR3A1 (Bit 16) */ +#define CTIMER_CMPRAUXA1_CMPR3A1_Msk (0xffff0000UL) /*!< CMPR3A1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA1_CMPR2A1_Pos (0UL) /*!< CMPR2A1 (Bit 0) */ +#define CTIMER_CMPRAUXA1_CMPR2A1_Msk (0xffffUL) /*!< CMPR2A1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB1 ======================================================= */ +#define CTIMER_CMPRAUXB1_CMPR3B1_Pos (16UL) /*!< CMPR3B1 (Bit 16) */ +#define CTIMER_CMPRAUXB1_CMPR3B1_Msk (0xffff0000UL) /*!< CMPR3B1 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB1_CMPR2B1_Pos (0UL) /*!< CMPR2B1 (Bit 0) */ +#define CTIMER_CMPRAUXB1_CMPR2B1_Msk (0xffffUL) /*!< CMPR2B1 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX1 ========================================================== */ +#define CTIMER_AUX1_TMRB1EN23_Pos (30UL) /*!< TMRB1EN23 (Bit 30) */ +#define CTIMER_AUX1_TMRB1EN23_Msk (0x40000000UL) /*!< TMRB1EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1POL23_Pos (29UL) /*!< TMRB1POL23 (Bit 29) */ +#define CTIMER_AUX1_TMRB1POL23_Msk (0x20000000UL) /*!< TMRB1POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1TINV_Pos (28UL) /*!< TMRB1TINV (Bit 28) */ +#define CTIMER_AUX1_TMRB1TINV_Msk (0x10000000UL) /*!< TMRB1TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1NOSYNC_Pos (27UL) /*!< TMRB1NOSYNC (Bit 27) */ +#define CTIMER_AUX1_TMRB1NOSYNC_Msk (0x8000000UL) /*!< TMRB1NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRB1TRIG_Pos (23UL) /*!< TMRB1TRIG (Bit 23) */ +#define CTIMER_AUX1_TMRB1TRIG_Msk (0x7800000UL) /*!< TMRB1TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX1_TMRB1LMT_Pos (16UL) /*!< TMRB1LMT (Bit 16) */ +#define CTIMER_AUX1_TMRB1LMT_Msk (0x3f0000UL) /*!< TMRB1LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX1_TMRA1EN23_Pos (14UL) /*!< TMRA1EN23 (Bit 14) */ +#define CTIMER_AUX1_TMRA1EN23_Msk (0x4000UL) /*!< TMRA1EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1POL23_Pos (13UL) /*!< TMRA1POL23 (Bit 13) */ +#define CTIMER_AUX1_TMRA1POL23_Msk (0x2000UL) /*!< TMRA1POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1TINV_Pos (12UL) /*!< TMRA1TINV (Bit 12) */ +#define CTIMER_AUX1_TMRA1TINV_Msk (0x1000UL) /*!< TMRA1TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1NOSYNC_Pos (11UL) /*!< TMRA1NOSYNC (Bit 11) */ +#define CTIMER_AUX1_TMRA1NOSYNC_Msk (0x800UL) /*!< TMRA1NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX1_TMRA1TRIG_Pos (7UL) /*!< TMRA1TRIG (Bit 7) */ +#define CTIMER_AUX1_TMRA1TRIG_Msk (0x780UL) /*!< TMRA1TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX1_TMRA1LMT_Pos (0UL) /*!< TMRA1LMT (Bit 0) */ +#define CTIMER_AUX1_TMRA1LMT_Msk (0x7fUL) /*!< TMRA1LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR2 ========================================================== */ +#define CTIMER_TMR2_CTTMRB2_Pos (16UL) /*!< CTTMRB2 (Bit 16) */ +#define CTIMER_TMR2_CTTMRB2_Msk (0xffff0000UL) /*!< CTTMRB2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR2_CTTMRA2_Pos (0UL) /*!< CTTMRA2 (Bit 0) */ +#define CTIMER_TMR2_CTTMRA2_Msk (0xffffUL) /*!< CTTMRA2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA2 ========================================================= */ +#define CTIMER_CMPRA2_CMPR1A2_Pos (16UL) /*!< CMPR1A2 (Bit 16) */ +#define CTIMER_CMPRA2_CMPR1A2_Msk (0xffff0000UL) /*!< CMPR1A2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA2_CMPR0A2_Pos (0UL) /*!< CMPR0A2 (Bit 0) */ +#define CTIMER_CMPRA2_CMPR0A2_Msk (0xffffUL) /*!< CMPR0A2 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB2 ========================================================= */ +#define CTIMER_CMPRB2_CMPR1B2_Pos (16UL) /*!< CMPR1B2 (Bit 16) */ +#define CTIMER_CMPRB2_CMPR1B2_Msk (0xffff0000UL) /*!< CMPR1B2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB2_CMPR0B2_Pos (0UL) /*!< CMPR0B2 (Bit 0) */ +#define CTIMER_CMPRB2_CMPR0B2_Msk (0xffffUL) /*!< CMPR0B2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL2 ========================================================= */ +#define CTIMER_CTRL2_CTLINK2_Pos (31UL) /*!< CTLINK2 (Bit 31) */ +#define CTIMER_CTRL2_CTLINK2_Msk (0x80000000UL) /*!< CTLINK2 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2POL_Pos (28UL) /*!< TMRB2POL (Bit 28) */ +#define CTIMER_CTRL2_TMRB2POL_Msk (0x10000000UL) /*!< TMRB2POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2CLR_Pos (27UL) /*!< TMRB2CLR (Bit 27) */ +#define CTIMER_CTRL2_TMRB2CLR_Msk (0x8000000UL) /*!< TMRB2CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2IE1_Pos (26UL) /*!< TMRB2IE1 (Bit 26) */ +#define CTIMER_CTRL2_TMRB2IE1_Msk (0x4000000UL) /*!< TMRB2IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2IE0_Pos (25UL) /*!< TMRB2IE0 (Bit 25) */ +#define CTIMER_CTRL2_TMRB2IE0_Msk (0x2000000UL) /*!< TMRB2IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRB2FN_Pos (22UL) /*!< TMRB2FN (Bit 22) */ +#define CTIMER_CTRL2_TMRB2FN_Msk (0x1c00000UL) /*!< TMRB2FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL2_TMRB2CLK_Pos (17UL) /*!< TMRB2CLK (Bit 17) */ +#define CTIMER_CTRL2_TMRB2CLK_Msk (0x3e0000UL) /*!< TMRB2CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL2_TMRB2EN_Pos (16UL) /*!< TMRB2EN (Bit 16) */ +#define CTIMER_CTRL2_TMRB2EN_Msk (0x10000UL) /*!< TMRB2EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2POL_Pos (12UL) /*!< TMRA2POL (Bit 12) */ +#define CTIMER_CTRL2_TMRA2POL_Msk (0x1000UL) /*!< TMRA2POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2CLR_Pos (11UL) /*!< TMRA2CLR (Bit 11) */ +#define CTIMER_CTRL2_TMRA2CLR_Msk (0x800UL) /*!< TMRA2CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2IE1_Pos (10UL) /*!< TMRA2IE1 (Bit 10) */ +#define CTIMER_CTRL2_TMRA2IE1_Msk (0x400UL) /*!< TMRA2IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2IE0_Pos (9UL) /*!< TMRA2IE0 (Bit 9) */ +#define CTIMER_CTRL2_TMRA2IE0_Msk (0x200UL) /*!< TMRA2IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL2_TMRA2FN_Pos (6UL) /*!< TMRA2FN (Bit 6) */ +#define CTIMER_CTRL2_TMRA2FN_Msk (0x1c0UL) /*!< TMRA2FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL2_TMRA2CLK_Pos (1UL) /*!< TMRA2CLK (Bit 1) */ +#define CTIMER_CTRL2_TMRA2CLK_Msk (0x3eUL) /*!< TMRA2CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL2_TMRA2EN_Pos (0UL) /*!< TMRA2EN (Bit 0) */ +#define CTIMER_CTRL2_TMRA2EN_Msk (0x1UL) /*!< TMRA2EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA2 ======================================================= */ +#define CTIMER_CMPRAUXA2_CMPR3A2_Pos (16UL) /*!< CMPR3A2 (Bit 16) */ +#define CTIMER_CMPRAUXA2_CMPR3A2_Msk (0xffff0000UL) /*!< CMPR3A2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA2_CMPR2A2_Pos (0UL) /*!< CMPR2A2 (Bit 0) */ +#define CTIMER_CMPRAUXA2_CMPR2A2_Msk (0xffffUL) /*!< CMPR2A2 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB2 ======================================================= */ +#define CTIMER_CMPRAUXB2_CMPR3B2_Pos (16UL) /*!< CMPR3B2 (Bit 16) */ +#define CTIMER_CMPRAUXB2_CMPR3B2_Msk (0xffff0000UL) /*!< CMPR3B2 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB2_CMPR2B2_Pos (0UL) /*!< CMPR2B2 (Bit 0) */ +#define CTIMER_CMPRAUXB2_CMPR2B2_Msk (0xffffUL) /*!< CMPR2B2 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX2 ========================================================== */ +#define CTIMER_AUX2_TMRB2EN23_Pos (30UL) /*!< TMRB2EN23 (Bit 30) */ +#define CTIMER_AUX2_TMRB2EN23_Msk (0x40000000UL) /*!< TMRB2EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2POL23_Pos (29UL) /*!< TMRB2POL23 (Bit 29) */ +#define CTIMER_AUX2_TMRB2POL23_Msk (0x20000000UL) /*!< TMRB2POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2TINV_Pos (28UL) /*!< TMRB2TINV (Bit 28) */ +#define CTIMER_AUX2_TMRB2TINV_Msk (0x10000000UL) /*!< TMRB2TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2NOSYNC_Pos (27UL) /*!< TMRB2NOSYNC (Bit 27) */ +#define CTIMER_AUX2_TMRB2NOSYNC_Msk (0x8000000UL) /*!< TMRB2NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRB2TRIG_Pos (23UL) /*!< TMRB2TRIG (Bit 23) */ +#define CTIMER_AUX2_TMRB2TRIG_Msk (0x7800000UL) /*!< TMRB2TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX2_TMRB2LMT_Pos (16UL) /*!< TMRB2LMT (Bit 16) */ +#define CTIMER_AUX2_TMRB2LMT_Msk (0x3f0000UL) /*!< TMRB2LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX2_TMRA2EN23_Pos (14UL) /*!< TMRA2EN23 (Bit 14) */ +#define CTIMER_AUX2_TMRA2EN23_Msk (0x4000UL) /*!< TMRA2EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2POL23_Pos (13UL) /*!< TMRA2POL23 (Bit 13) */ +#define CTIMER_AUX2_TMRA2POL23_Msk (0x2000UL) /*!< TMRA2POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2TINV_Pos (12UL) /*!< TMRA2TINV (Bit 12) */ +#define CTIMER_AUX2_TMRA2TINV_Msk (0x1000UL) /*!< TMRA2TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2NOSYNC_Pos (11UL) /*!< TMRA2NOSYNC (Bit 11) */ +#define CTIMER_AUX2_TMRA2NOSYNC_Msk (0x800UL) /*!< TMRA2NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX2_TMRA2TRIG_Pos (7UL) /*!< TMRA2TRIG (Bit 7) */ +#define CTIMER_AUX2_TMRA2TRIG_Msk (0x780UL) /*!< TMRA2TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX2_TMRA2LMT_Pos (0UL) /*!< TMRA2LMT (Bit 0) */ +#define CTIMER_AUX2_TMRA2LMT_Msk (0x7fUL) /*!< TMRA2LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR3 ========================================================== */ +#define CTIMER_TMR3_CTTMRB3_Pos (16UL) /*!< CTTMRB3 (Bit 16) */ +#define CTIMER_TMR3_CTTMRB3_Msk (0xffff0000UL) /*!< CTTMRB3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR3_CTTMRA3_Pos (0UL) /*!< CTTMRA3 (Bit 0) */ +#define CTIMER_TMR3_CTTMRA3_Msk (0xffffUL) /*!< CTTMRA3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA3 ========================================================= */ +#define CTIMER_CMPRA3_CMPR1A3_Pos (16UL) /*!< CMPR1A3 (Bit 16) */ +#define CTIMER_CMPRA3_CMPR1A3_Msk (0xffff0000UL) /*!< CMPR1A3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA3_CMPR0A3_Pos (0UL) /*!< CMPR0A3 (Bit 0) */ +#define CTIMER_CMPRA3_CMPR0A3_Msk (0xffffUL) /*!< CMPR0A3 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB3 ========================================================= */ +#define CTIMER_CMPRB3_CMPR1B3_Pos (16UL) /*!< CMPR1B3 (Bit 16) */ +#define CTIMER_CMPRB3_CMPR1B3_Msk (0xffff0000UL) /*!< CMPR1B3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB3_CMPR0B3_Pos (0UL) /*!< CMPR0B3 (Bit 0) */ +#define CTIMER_CMPRB3_CMPR0B3_Msk (0xffffUL) /*!< CMPR0B3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL3 ========================================================= */ +#define CTIMER_CTRL3_CTLINK3_Pos (31UL) /*!< CTLINK3 (Bit 31) */ +#define CTIMER_CTRL3_CTLINK3_Msk (0x80000000UL) /*!< CTLINK3 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3POL_Pos (28UL) /*!< TMRB3POL (Bit 28) */ +#define CTIMER_CTRL3_TMRB3POL_Msk (0x10000000UL) /*!< TMRB3POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3CLR_Pos (27UL) /*!< TMRB3CLR (Bit 27) */ +#define CTIMER_CTRL3_TMRB3CLR_Msk (0x8000000UL) /*!< TMRB3CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3IE1_Pos (26UL) /*!< TMRB3IE1 (Bit 26) */ +#define CTIMER_CTRL3_TMRB3IE1_Msk (0x4000000UL) /*!< TMRB3IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3IE0_Pos (25UL) /*!< TMRB3IE0 (Bit 25) */ +#define CTIMER_CTRL3_TMRB3IE0_Msk (0x2000000UL) /*!< TMRB3IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRB3FN_Pos (22UL) /*!< TMRB3FN (Bit 22) */ +#define CTIMER_CTRL3_TMRB3FN_Msk (0x1c00000UL) /*!< TMRB3FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL3_TMRB3CLK_Pos (17UL) /*!< TMRB3CLK (Bit 17) */ +#define CTIMER_CTRL3_TMRB3CLK_Msk (0x3e0000UL) /*!< TMRB3CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL3_TMRB3EN_Pos (16UL) /*!< TMRB3EN (Bit 16) */ +#define CTIMER_CTRL3_TMRB3EN_Msk (0x10000UL) /*!< TMRB3EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_ADCEN_Pos (15UL) /*!< ADCEN (Bit 15) */ +#define CTIMER_CTRL3_ADCEN_Msk (0x8000UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3POL_Pos (12UL) /*!< TMRA3POL (Bit 12) */ +#define CTIMER_CTRL3_TMRA3POL_Msk (0x1000UL) /*!< TMRA3POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3CLR_Pos (11UL) /*!< TMRA3CLR (Bit 11) */ +#define CTIMER_CTRL3_TMRA3CLR_Msk (0x800UL) /*!< TMRA3CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3IE1_Pos (10UL) /*!< TMRA3IE1 (Bit 10) */ +#define CTIMER_CTRL3_TMRA3IE1_Msk (0x400UL) /*!< TMRA3IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3IE0_Pos (9UL) /*!< TMRA3IE0 (Bit 9) */ +#define CTIMER_CTRL3_TMRA3IE0_Msk (0x200UL) /*!< TMRA3IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL3_TMRA3FN_Pos (6UL) /*!< TMRA3FN (Bit 6) */ +#define CTIMER_CTRL3_TMRA3FN_Msk (0x1c0UL) /*!< TMRA3FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL3_TMRA3CLK_Pos (1UL) /*!< TMRA3CLK (Bit 1) */ +#define CTIMER_CTRL3_TMRA3CLK_Msk (0x3eUL) /*!< TMRA3CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL3_TMRA3EN_Pos (0UL) /*!< TMRA3EN (Bit 0) */ +#define CTIMER_CTRL3_TMRA3EN_Msk (0x1UL) /*!< TMRA3EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA3 ======================================================= */ +#define CTIMER_CMPRAUXA3_CMPR3A3_Pos (16UL) /*!< CMPR3A3 (Bit 16) */ +#define CTIMER_CMPRAUXA3_CMPR3A3_Msk (0xffff0000UL) /*!< CMPR3A3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA3_CMPR2A3_Pos (0UL) /*!< CMPR2A3 (Bit 0) */ +#define CTIMER_CMPRAUXA3_CMPR2A3_Msk (0xffffUL) /*!< CMPR2A3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB3 ======================================================= */ +#define CTIMER_CMPRAUXB3_CMPR3B3_Pos (16UL) /*!< CMPR3B3 (Bit 16) */ +#define CTIMER_CMPRAUXB3_CMPR3B3_Msk (0xffff0000UL) /*!< CMPR3B3 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB3_CMPR2B3_Pos (0UL) /*!< CMPR2B3 (Bit 0) */ +#define CTIMER_CMPRAUXB3_CMPR2B3_Msk (0xffffUL) /*!< CMPR2B3 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX3 ========================================================== */ +#define CTIMER_AUX3_TMRB3EN23_Pos (30UL) /*!< TMRB3EN23 (Bit 30) */ +#define CTIMER_AUX3_TMRB3EN23_Msk (0x40000000UL) /*!< TMRB3EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3POL23_Pos (29UL) /*!< TMRB3POL23 (Bit 29) */ +#define CTIMER_AUX3_TMRB3POL23_Msk (0x20000000UL) /*!< TMRB3POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3TINV_Pos (28UL) /*!< TMRB3TINV (Bit 28) */ +#define CTIMER_AUX3_TMRB3TINV_Msk (0x10000000UL) /*!< TMRB3TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3NOSYNC_Pos (27UL) /*!< TMRB3NOSYNC (Bit 27) */ +#define CTIMER_AUX3_TMRB3NOSYNC_Msk (0x8000000UL) /*!< TMRB3NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRB3TRIG_Pos (23UL) /*!< TMRB3TRIG (Bit 23) */ +#define CTIMER_AUX3_TMRB3TRIG_Msk (0x7800000UL) /*!< TMRB3TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX3_TMRB3LMT_Pos (16UL) /*!< TMRB3LMT (Bit 16) */ +#define CTIMER_AUX3_TMRB3LMT_Msk (0x3f0000UL) /*!< TMRB3LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX3_TMRA3EN23_Pos (14UL) /*!< TMRA3EN23 (Bit 14) */ +#define CTIMER_AUX3_TMRA3EN23_Msk (0x4000UL) /*!< TMRA3EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3POL23_Pos (13UL) /*!< TMRA3POL23 (Bit 13) */ +#define CTIMER_AUX3_TMRA3POL23_Msk (0x2000UL) /*!< TMRA3POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3TINV_Pos (12UL) /*!< TMRA3TINV (Bit 12) */ +#define CTIMER_AUX3_TMRA3TINV_Msk (0x1000UL) /*!< TMRA3TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3NOSYNC_Pos (11UL) /*!< TMRA3NOSYNC (Bit 11) */ +#define CTIMER_AUX3_TMRA3NOSYNC_Msk (0x800UL) /*!< TMRA3NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX3_TMRA3TRIG_Pos (7UL) /*!< TMRA3TRIG (Bit 7) */ +#define CTIMER_AUX3_TMRA3TRIG_Msk (0x780UL) /*!< TMRA3TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX3_TMRA3LMT_Pos (0UL) /*!< TMRA3LMT (Bit 0) */ +#define CTIMER_AUX3_TMRA3LMT_Msk (0x7fUL) /*!< TMRA3LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR4 ========================================================== */ +#define CTIMER_TMR4_CTTMRB4_Pos (16UL) /*!< CTTMRB4 (Bit 16) */ +#define CTIMER_TMR4_CTTMRB4_Msk (0xffff0000UL) /*!< CTTMRB4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR4_CTTMRA4_Pos (0UL) /*!< CTTMRA4 (Bit 0) */ +#define CTIMER_TMR4_CTTMRA4_Msk (0xffffUL) /*!< CTTMRA4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA4 ========================================================= */ +#define CTIMER_CMPRA4_CMPR1A4_Pos (16UL) /*!< CMPR1A4 (Bit 16) */ +#define CTIMER_CMPRA4_CMPR1A4_Msk (0xffff0000UL) /*!< CMPR1A4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA4_CMPR0A4_Pos (0UL) /*!< CMPR0A4 (Bit 0) */ +#define CTIMER_CMPRA4_CMPR0A4_Msk (0xffffUL) /*!< CMPR0A4 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB4 ========================================================= */ +#define CTIMER_CMPRB4_CMPR1B4_Pos (16UL) /*!< CMPR1B4 (Bit 16) */ +#define CTIMER_CMPRB4_CMPR1B4_Msk (0xffff0000UL) /*!< CMPR1B4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB4_CMPR0B4_Pos (0UL) /*!< CMPR0B4 (Bit 0) */ +#define CTIMER_CMPRB4_CMPR0B4_Msk (0xffffUL) /*!< CMPR0B4 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL4 ========================================================= */ +#define CTIMER_CTRL4_CTLINK4_Pos (31UL) /*!< CTLINK4 (Bit 31) */ +#define CTIMER_CTRL4_CTLINK4_Msk (0x80000000UL) /*!< CTLINK4 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4POL_Pos (28UL) /*!< TMRB4POL (Bit 28) */ +#define CTIMER_CTRL4_TMRB4POL_Msk (0x10000000UL) /*!< TMRB4POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4CLR_Pos (27UL) /*!< TMRB4CLR (Bit 27) */ +#define CTIMER_CTRL4_TMRB4CLR_Msk (0x8000000UL) /*!< TMRB4CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4IE1_Pos (26UL) /*!< TMRB4IE1 (Bit 26) */ +#define CTIMER_CTRL4_TMRB4IE1_Msk (0x4000000UL) /*!< TMRB4IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4IE0_Pos (25UL) /*!< TMRB4IE0 (Bit 25) */ +#define CTIMER_CTRL4_TMRB4IE0_Msk (0x2000000UL) /*!< TMRB4IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRB4FN_Pos (22UL) /*!< TMRB4FN (Bit 22) */ +#define CTIMER_CTRL4_TMRB4FN_Msk (0x1c00000UL) /*!< TMRB4FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL4_TMRB4CLK_Pos (17UL) /*!< TMRB4CLK (Bit 17) */ +#define CTIMER_CTRL4_TMRB4CLK_Msk (0x3e0000UL) /*!< TMRB4CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL4_TMRB4EN_Pos (16UL) /*!< TMRB4EN (Bit 16) */ +#define CTIMER_CTRL4_TMRB4EN_Msk (0x10000UL) /*!< TMRB4EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4POL_Pos (12UL) /*!< TMRA4POL (Bit 12) */ +#define CTIMER_CTRL4_TMRA4POL_Msk (0x1000UL) /*!< TMRA4POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4CLR_Pos (11UL) /*!< TMRA4CLR (Bit 11) */ +#define CTIMER_CTRL4_TMRA4CLR_Msk (0x800UL) /*!< TMRA4CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4IE1_Pos (10UL) /*!< TMRA4IE1 (Bit 10) */ +#define CTIMER_CTRL4_TMRA4IE1_Msk (0x400UL) /*!< TMRA4IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4IE0_Pos (9UL) /*!< TMRA4IE0 (Bit 9) */ +#define CTIMER_CTRL4_TMRA4IE0_Msk (0x200UL) /*!< TMRA4IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL4_TMRA4FN_Pos (6UL) /*!< TMRA4FN (Bit 6) */ +#define CTIMER_CTRL4_TMRA4FN_Msk (0x1c0UL) /*!< TMRA4FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL4_TMRA4CLK_Pos (1UL) /*!< TMRA4CLK (Bit 1) */ +#define CTIMER_CTRL4_TMRA4CLK_Msk (0x3eUL) /*!< TMRA4CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL4_TMRA4EN_Pos (0UL) /*!< TMRA4EN (Bit 0) */ +#define CTIMER_CTRL4_TMRA4EN_Msk (0x1UL) /*!< TMRA4EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA4 ======================================================= */ +#define CTIMER_CMPRAUXA4_CMPR3A4_Pos (16UL) /*!< CMPR3A4 (Bit 16) */ +#define CTIMER_CMPRAUXA4_CMPR3A4_Msk (0xffff0000UL) /*!< CMPR3A4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA4_CMPR2A4_Pos (0UL) /*!< CMPR2A4 (Bit 0) */ +#define CTIMER_CMPRAUXA4_CMPR2A4_Msk (0xffffUL) /*!< CMPR2A4 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB4 ======================================================= */ +#define CTIMER_CMPRAUXB4_CMPR3B4_Pos (16UL) /*!< CMPR3B4 (Bit 16) */ +#define CTIMER_CMPRAUXB4_CMPR3B4_Msk (0xffff0000UL) /*!< CMPR3B4 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB4_CMPR2B4_Pos (0UL) /*!< CMPR2B4 (Bit 0) */ +#define CTIMER_CMPRAUXB4_CMPR2B4_Msk (0xffffUL) /*!< CMPR2B4 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX4 ========================================================== */ +#define CTIMER_AUX4_TMRB4EN23_Pos (30UL) /*!< TMRB4EN23 (Bit 30) */ +#define CTIMER_AUX4_TMRB4EN23_Msk (0x40000000UL) /*!< TMRB4EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4POL23_Pos (29UL) /*!< TMRB4POL23 (Bit 29) */ +#define CTIMER_AUX4_TMRB4POL23_Msk (0x20000000UL) /*!< TMRB4POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4TINV_Pos (28UL) /*!< TMRB4TINV (Bit 28) */ +#define CTIMER_AUX4_TMRB4TINV_Msk (0x10000000UL) /*!< TMRB4TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4NOSYNC_Pos (27UL) /*!< TMRB4NOSYNC (Bit 27) */ +#define CTIMER_AUX4_TMRB4NOSYNC_Msk (0x8000000UL) /*!< TMRB4NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRB4TRIG_Pos (23UL) /*!< TMRB4TRIG (Bit 23) */ +#define CTIMER_AUX4_TMRB4TRIG_Msk (0x7800000UL) /*!< TMRB4TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX4_TMRB4LMT_Pos (16UL) /*!< TMRB4LMT (Bit 16) */ +#define CTIMER_AUX4_TMRB4LMT_Msk (0x3f0000UL) /*!< TMRB4LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX4_TMRA4EN23_Pos (14UL) /*!< TMRA4EN23 (Bit 14) */ +#define CTIMER_AUX4_TMRA4EN23_Msk (0x4000UL) /*!< TMRA4EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4POL23_Pos (13UL) /*!< TMRA4POL23 (Bit 13) */ +#define CTIMER_AUX4_TMRA4POL23_Msk (0x2000UL) /*!< TMRA4POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4TINV_Pos (12UL) /*!< TMRA4TINV (Bit 12) */ +#define CTIMER_AUX4_TMRA4TINV_Msk (0x1000UL) /*!< TMRA4TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4NOSYNC_Pos (11UL) /*!< TMRA4NOSYNC (Bit 11) */ +#define CTIMER_AUX4_TMRA4NOSYNC_Msk (0x800UL) /*!< TMRA4NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX4_TMRA4TRIG_Pos (7UL) /*!< TMRA4TRIG (Bit 7) */ +#define CTIMER_AUX4_TMRA4TRIG_Msk (0x780UL) /*!< TMRA4TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX4_TMRA4LMT_Pos (0UL) /*!< TMRA4LMT (Bit 0) */ +#define CTIMER_AUX4_TMRA4LMT_Msk (0x7fUL) /*!< TMRA4LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR5 ========================================================== */ +#define CTIMER_TMR5_CTTMRB5_Pos (16UL) /*!< CTTMRB5 (Bit 16) */ +#define CTIMER_TMR5_CTTMRB5_Msk (0xffff0000UL) /*!< CTTMRB5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR5_CTTMRA5_Pos (0UL) /*!< CTTMRA5 (Bit 0) */ +#define CTIMER_TMR5_CTTMRA5_Msk (0xffffUL) /*!< CTTMRA5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA5 ========================================================= */ +#define CTIMER_CMPRA5_CMPR1A5_Pos (16UL) /*!< CMPR1A5 (Bit 16) */ +#define CTIMER_CMPRA5_CMPR1A5_Msk (0xffff0000UL) /*!< CMPR1A5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA5_CMPR0A5_Pos (0UL) /*!< CMPR0A5 (Bit 0) */ +#define CTIMER_CMPRA5_CMPR0A5_Msk (0xffffUL) /*!< CMPR0A5 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB5 ========================================================= */ +#define CTIMER_CMPRB5_CMPR1B5_Pos (16UL) /*!< CMPR1B5 (Bit 16) */ +#define CTIMER_CMPRB5_CMPR1B5_Msk (0xffff0000UL) /*!< CMPR1B5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB5_CMPR0B5_Pos (0UL) /*!< CMPR0B5 (Bit 0) */ +#define CTIMER_CMPRB5_CMPR0B5_Msk (0xffffUL) /*!< CMPR0B5 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL5 ========================================================= */ +#define CTIMER_CTRL5_CTLINK5_Pos (31UL) /*!< CTLINK5 (Bit 31) */ +#define CTIMER_CTRL5_CTLINK5_Msk (0x80000000UL) /*!< CTLINK5 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5POL_Pos (28UL) /*!< TMRB5POL (Bit 28) */ +#define CTIMER_CTRL5_TMRB5POL_Msk (0x10000000UL) /*!< TMRB5POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5CLR_Pos (27UL) /*!< TMRB5CLR (Bit 27) */ +#define CTIMER_CTRL5_TMRB5CLR_Msk (0x8000000UL) /*!< TMRB5CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5IE1_Pos (26UL) /*!< TMRB5IE1 (Bit 26) */ +#define CTIMER_CTRL5_TMRB5IE1_Msk (0x4000000UL) /*!< TMRB5IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5IE0_Pos (25UL) /*!< TMRB5IE0 (Bit 25) */ +#define CTIMER_CTRL5_TMRB5IE0_Msk (0x2000000UL) /*!< TMRB5IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRB5FN_Pos (22UL) /*!< TMRB5FN (Bit 22) */ +#define CTIMER_CTRL5_TMRB5FN_Msk (0x1c00000UL) /*!< TMRB5FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL5_TMRB5CLK_Pos (17UL) /*!< TMRB5CLK (Bit 17) */ +#define CTIMER_CTRL5_TMRB5CLK_Msk (0x3e0000UL) /*!< TMRB5CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL5_TMRB5EN_Pos (16UL) /*!< TMRB5EN (Bit 16) */ +#define CTIMER_CTRL5_TMRB5EN_Msk (0x10000UL) /*!< TMRB5EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5POL_Pos (12UL) /*!< TMRA5POL (Bit 12) */ +#define CTIMER_CTRL5_TMRA5POL_Msk (0x1000UL) /*!< TMRA5POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5CLR_Pos (11UL) /*!< TMRA5CLR (Bit 11) */ +#define CTIMER_CTRL5_TMRA5CLR_Msk (0x800UL) /*!< TMRA5CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5IE1_Pos (10UL) /*!< TMRA5IE1 (Bit 10) */ +#define CTIMER_CTRL5_TMRA5IE1_Msk (0x400UL) /*!< TMRA5IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5IE0_Pos (9UL) /*!< TMRA5IE0 (Bit 9) */ +#define CTIMER_CTRL5_TMRA5IE0_Msk (0x200UL) /*!< TMRA5IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL5_TMRA5FN_Pos (6UL) /*!< TMRA5FN (Bit 6) */ +#define CTIMER_CTRL5_TMRA5FN_Msk (0x1c0UL) /*!< TMRA5FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL5_TMRA5CLK_Pos (1UL) /*!< TMRA5CLK (Bit 1) */ +#define CTIMER_CTRL5_TMRA5CLK_Msk (0x3eUL) /*!< TMRA5CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL5_TMRA5EN_Pos (0UL) /*!< TMRA5EN (Bit 0) */ +#define CTIMER_CTRL5_TMRA5EN_Msk (0x1UL) /*!< TMRA5EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA5 ======================================================= */ +#define CTIMER_CMPRAUXA5_CMPR3A5_Pos (16UL) /*!< CMPR3A5 (Bit 16) */ +#define CTIMER_CMPRAUXA5_CMPR3A5_Msk (0xffff0000UL) /*!< CMPR3A5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA5_CMPR2A5_Pos (0UL) /*!< CMPR2A5 (Bit 0) */ +#define CTIMER_CMPRAUXA5_CMPR2A5_Msk (0xffffUL) /*!< CMPR2A5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB5 ======================================================= */ +#define CTIMER_CMPRAUXB5_CMPR3B5_Pos (16UL) /*!< CMPR3B5 (Bit 16) */ +#define CTIMER_CMPRAUXB5_CMPR3B5_Msk (0xffff0000UL) /*!< CMPR3B5 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB5_CMPR2B5_Pos (0UL) /*!< CMPR2B5 (Bit 0) */ +#define CTIMER_CMPRAUXB5_CMPR2B5_Msk (0xffffUL) /*!< CMPR2B5 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX5 ========================================================== */ +#define CTIMER_AUX5_TMRB5EN23_Pos (30UL) /*!< TMRB5EN23 (Bit 30) */ +#define CTIMER_AUX5_TMRB5EN23_Msk (0x40000000UL) /*!< TMRB5EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5POL23_Pos (29UL) /*!< TMRB5POL23 (Bit 29) */ +#define CTIMER_AUX5_TMRB5POL23_Msk (0x20000000UL) /*!< TMRB5POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5TINV_Pos (28UL) /*!< TMRB5TINV (Bit 28) */ +#define CTIMER_AUX5_TMRB5TINV_Msk (0x10000000UL) /*!< TMRB5TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5NOSYNC_Pos (27UL) /*!< TMRB5NOSYNC (Bit 27) */ +#define CTIMER_AUX5_TMRB5NOSYNC_Msk (0x8000000UL) /*!< TMRB5NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRB5TRIG_Pos (23UL) /*!< TMRB5TRIG (Bit 23) */ +#define CTIMER_AUX5_TMRB5TRIG_Msk (0x7800000UL) /*!< TMRB5TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX5_TMRB5LMT_Pos (16UL) /*!< TMRB5LMT (Bit 16) */ +#define CTIMER_AUX5_TMRB5LMT_Msk (0x3f0000UL) /*!< TMRB5LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX5_TMRA5EN23_Pos (14UL) /*!< TMRA5EN23 (Bit 14) */ +#define CTIMER_AUX5_TMRA5EN23_Msk (0x4000UL) /*!< TMRA5EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5POL23_Pos (13UL) /*!< TMRA5POL23 (Bit 13) */ +#define CTIMER_AUX5_TMRA5POL23_Msk (0x2000UL) /*!< TMRA5POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5TINV_Pos (12UL) /*!< TMRA5TINV (Bit 12) */ +#define CTIMER_AUX5_TMRA5TINV_Msk (0x1000UL) /*!< TMRA5TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5NOSYNC_Pos (11UL) /*!< TMRA5NOSYNC (Bit 11) */ +#define CTIMER_AUX5_TMRA5NOSYNC_Msk (0x800UL) /*!< TMRA5NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX5_TMRA5TRIG_Pos (7UL) /*!< TMRA5TRIG (Bit 7) */ +#define CTIMER_AUX5_TMRA5TRIG_Msk (0x780UL) /*!< TMRA5TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX5_TMRA5LMT_Pos (0UL) /*!< TMRA5LMT (Bit 0) */ +#define CTIMER_AUX5_TMRA5LMT_Msk (0x7fUL) /*!< TMRA5LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR6 ========================================================== */ +#define CTIMER_TMR6_CTTMRB6_Pos (16UL) /*!< CTTMRB6 (Bit 16) */ +#define CTIMER_TMR6_CTTMRB6_Msk (0xffff0000UL) /*!< CTTMRB6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR6_CTTMRA6_Pos (0UL) /*!< CTTMRA6 (Bit 0) */ +#define CTIMER_TMR6_CTTMRA6_Msk (0xffffUL) /*!< CTTMRA6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA6 ========================================================= */ +#define CTIMER_CMPRA6_CMPR1A6_Pos (16UL) /*!< CMPR1A6 (Bit 16) */ +#define CTIMER_CMPRA6_CMPR1A6_Msk (0xffff0000UL) /*!< CMPR1A6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA6_CMPR0A6_Pos (0UL) /*!< CMPR0A6 (Bit 0) */ +#define CTIMER_CMPRA6_CMPR0A6_Msk (0xffffUL) /*!< CMPR0A6 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB6 ========================================================= */ +#define CTIMER_CMPRB6_CMPR1B6_Pos (16UL) /*!< CMPR1B6 (Bit 16) */ +#define CTIMER_CMPRB6_CMPR1B6_Msk (0xffff0000UL) /*!< CMPR1B6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB6_CMPR0B6_Pos (0UL) /*!< CMPR0B6 (Bit 0) */ +#define CTIMER_CMPRB6_CMPR0B6_Msk (0xffffUL) /*!< CMPR0B6 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL6 ========================================================= */ +#define CTIMER_CTRL6_CTLINK6_Pos (31UL) /*!< CTLINK6 (Bit 31) */ +#define CTIMER_CTRL6_CTLINK6_Msk (0x80000000UL) /*!< CTLINK6 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6POL_Pos (28UL) /*!< TMRB6POL (Bit 28) */ +#define CTIMER_CTRL6_TMRB6POL_Msk (0x10000000UL) /*!< TMRB6POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6CLR_Pos (27UL) /*!< TMRB6CLR (Bit 27) */ +#define CTIMER_CTRL6_TMRB6CLR_Msk (0x8000000UL) /*!< TMRB6CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6IE1_Pos (26UL) /*!< TMRB6IE1 (Bit 26) */ +#define CTIMER_CTRL6_TMRB6IE1_Msk (0x4000000UL) /*!< TMRB6IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6IE0_Pos (25UL) /*!< TMRB6IE0 (Bit 25) */ +#define CTIMER_CTRL6_TMRB6IE0_Msk (0x2000000UL) /*!< TMRB6IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRB6FN_Pos (22UL) /*!< TMRB6FN (Bit 22) */ +#define CTIMER_CTRL6_TMRB6FN_Msk (0x1c00000UL) /*!< TMRB6FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL6_TMRB6CLK_Pos (17UL) /*!< TMRB6CLK (Bit 17) */ +#define CTIMER_CTRL6_TMRB6CLK_Msk (0x3e0000UL) /*!< TMRB6CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL6_TMRB6EN_Pos (16UL) /*!< TMRB6EN (Bit 16) */ +#define CTIMER_CTRL6_TMRB6EN_Msk (0x10000UL) /*!< TMRB6EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6POL_Pos (12UL) /*!< TMRA6POL (Bit 12) */ +#define CTIMER_CTRL6_TMRA6POL_Msk (0x1000UL) /*!< TMRA6POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6CLR_Pos (11UL) /*!< TMRA6CLR (Bit 11) */ +#define CTIMER_CTRL6_TMRA6CLR_Msk (0x800UL) /*!< TMRA6CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6IE1_Pos (10UL) /*!< TMRA6IE1 (Bit 10) */ +#define CTIMER_CTRL6_TMRA6IE1_Msk (0x400UL) /*!< TMRA6IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6IE0_Pos (9UL) /*!< TMRA6IE0 (Bit 9) */ +#define CTIMER_CTRL6_TMRA6IE0_Msk (0x200UL) /*!< TMRA6IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL6_TMRA6FN_Pos (6UL) /*!< TMRA6FN (Bit 6) */ +#define CTIMER_CTRL6_TMRA6FN_Msk (0x1c0UL) /*!< TMRA6FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL6_TMRA6CLK_Pos (1UL) /*!< TMRA6CLK (Bit 1) */ +#define CTIMER_CTRL6_TMRA6CLK_Msk (0x3eUL) /*!< TMRA6CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL6_TMRA6EN_Pos (0UL) /*!< TMRA6EN (Bit 0) */ +#define CTIMER_CTRL6_TMRA6EN_Msk (0x1UL) /*!< TMRA6EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA6 ======================================================= */ +#define CTIMER_CMPRAUXA6_CMPR3A6_Pos (16UL) /*!< CMPR3A6 (Bit 16) */ +#define CTIMER_CMPRAUXA6_CMPR3A6_Msk (0xffff0000UL) /*!< CMPR3A6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA6_CMPR2A6_Pos (0UL) /*!< CMPR2A6 (Bit 0) */ +#define CTIMER_CMPRAUXA6_CMPR2A6_Msk (0xffffUL) /*!< CMPR2A6 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB6 ======================================================= */ +#define CTIMER_CMPRAUXB6_CMPR3B6_Pos (16UL) /*!< CMPR3B6 (Bit 16) */ +#define CTIMER_CMPRAUXB6_CMPR3B6_Msk (0xffff0000UL) /*!< CMPR3B6 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB6_CMPR2B6_Pos (0UL) /*!< CMPR2B6 (Bit 0) */ +#define CTIMER_CMPRAUXB6_CMPR2B6_Msk (0xffffUL) /*!< CMPR2B6 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX6 ========================================================== */ +#define CTIMER_AUX6_TMRB6EN23_Pos (30UL) /*!< TMRB6EN23 (Bit 30) */ +#define CTIMER_AUX6_TMRB6EN23_Msk (0x40000000UL) /*!< TMRB6EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6POL23_Pos (29UL) /*!< TMRB6POL23 (Bit 29) */ +#define CTIMER_AUX6_TMRB6POL23_Msk (0x20000000UL) /*!< TMRB6POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6TINV_Pos (28UL) /*!< TMRB6TINV (Bit 28) */ +#define CTIMER_AUX6_TMRB6TINV_Msk (0x10000000UL) /*!< TMRB6TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6NOSYNC_Pos (27UL) /*!< TMRB6NOSYNC (Bit 27) */ +#define CTIMER_AUX6_TMRB6NOSYNC_Msk (0x8000000UL) /*!< TMRB6NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRB6TRIG_Pos (23UL) /*!< TMRB6TRIG (Bit 23) */ +#define CTIMER_AUX6_TMRB6TRIG_Msk (0x7800000UL) /*!< TMRB6TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX6_TMRB6LMT_Pos (16UL) /*!< TMRB6LMT (Bit 16) */ +#define CTIMER_AUX6_TMRB6LMT_Msk (0x3f0000UL) /*!< TMRB6LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX6_TMRA6EN23_Pos (14UL) /*!< TMRA6EN23 (Bit 14) */ +#define CTIMER_AUX6_TMRA6EN23_Msk (0x4000UL) /*!< TMRA6EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6POL23_Pos (13UL) /*!< TMRA6POL23 (Bit 13) */ +#define CTIMER_AUX6_TMRA6POL23_Msk (0x2000UL) /*!< TMRA6POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6TINV_Pos (12UL) /*!< TMRA6TINV (Bit 12) */ +#define CTIMER_AUX6_TMRA6TINV_Msk (0x1000UL) /*!< TMRA6TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6NOSYNC_Pos (11UL) /*!< TMRA6NOSYNC (Bit 11) */ +#define CTIMER_AUX6_TMRA6NOSYNC_Msk (0x800UL) /*!< TMRA6NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX6_TMRA6TRIG_Pos (7UL) /*!< TMRA6TRIG (Bit 7) */ +#define CTIMER_AUX6_TMRA6TRIG_Msk (0x780UL) /*!< TMRA6TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX6_TMRA6LMT_Pos (0UL) /*!< TMRA6LMT (Bit 0) */ +#define CTIMER_AUX6_TMRA6LMT_Msk (0x7fUL) /*!< TMRA6LMT (Bitfield-Mask: 0x7f) */ +/* ========================================================= TMR7 ========================================================== */ +#define CTIMER_TMR7_CTTMRB7_Pos (16UL) /*!< CTTMRB7 (Bit 16) */ +#define CTIMER_TMR7_CTTMRB7_Msk (0xffff0000UL) /*!< CTTMRB7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_TMR7_CTTMRA7_Pos (0UL) /*!< CTTMRA7 (Bit 0) */ +#define CTIMER_TMR7_CTTMRA7_Msk (0xffffUL) /*!< CTTMRA7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRA7 ========================================================= */ +#define CTIMER_CMPRA7_CMPR1A7_Pos (16UL) /*!< CMPR1A7 (Bit 16) */ +#define CTIMER_CMPRA7_CMPR1A7_Msk (0xffff0000UL) /*!< CMPR1A7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRA7_CMPR0A7_Pos (0UL) /*!< CMPR0A7 (Bit 0) */ +#define CTIMER_CMPRA7_CMPR0A7_Msk (0xffffUL) /*!< CMPR0A7 (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMPRB7 ========================================================= */ +#define CTIMER_CMPRB7_CMPR1B7_Pos (16UL) /*!< CMPR1B7 (Bit 16) */ +#define CTIMER_CMPRB7_CMPR1B7_Msk (0xffff0000UL) /*!< CMPR1B7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRB7_CMPR0B7_Pos (0UL) /*!< CMPR0B7 (Bit 0) */ +#define CTIMER_CMPRB7_CMPR0B7_Msk (0xffffUL) /*!< CMPR0B7 (Bitfield-Mask: 0xffff) */ +/* ========================================================= CTRL7 ========================================================= */ +#define CTIMER_CTRL7_CTLINK7_Pos (31UL) /*!< CTLINK7 (Bit 31) */ +#define CTIMER_CTRL7_CTLINK7_Msk (0x80000000UL) /*!< CTLINK7 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7POL_Pos (28UL) /*!< TMRB7POL (Bit 28) */ +#define CTIMER_CTRL7_TMRB7POL_Msk (0x10000000UL) /*!< TMRB7POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7CLR_Pos (27UL) /*!< TMRB7CLR (Bit 27) */ +#define CTIMER_CTRL7_TMRB7CLR_Msk (0x8000000UL) /*!< TMRB7CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7IE1_Pos (26UL) /*!< TMRB7IE1 (Bit 26) */ +#define CTIMER_CTRL7_TMRB7IE1_Msk (0x4000000UL) /*!< TMRB7IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7IE0_Pos (25UL) /*!< TMRB7IE0 (Bit 25) */ +#define CTIMER_CTRL7_TMRB7IE0_Msk (0x2000000UL) /*!< TMRB7IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRB7FN_Pos (22UL) /*!< TMRB7FN (Bit 22) */ +#define CTIMER_CTRL7_TMRB7FN_Msk (0x1c00000UL) /*!< TMRB7FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL7_TMRB7CLK_Pos (17UL) /*!< TMRB7CLK (Bit 17) */ +#define CTIMER_CTRL7_TMRB7CLK_Msk (0x3e0000UL) /*!< TMRB7CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL7_TMRB7EN_Pos (16UL) /*!< TMRB7EN (Bit 16) */ +#define CTIMER_CTRL7_TMRB7EN_Msk (0x10000UL) /*!< TMRB7EN (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7POL_Pos (12UL) /*!< TMRA7POL (Bit 12) */ +#define CTIMER_CTRL7_TMRA7POL_Msk (0x1000UL) /*!< TMRA7POL (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7CLR_Pos (11UL) /*!< TMRA7CLR (Bit 11) */ +#define CTIMER_CTRL7_TMRA7CLR_Msk (0x800UL) /*!< TMRA7CLR (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7IE1_Pos (10UL) /*!< TMRA7IE1 (Bit 10) */ +#define CTIMER_CTRL7_TMRA7IE1_Msk (0x400UL) /*!< TMRA7IE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7IE0_Pos (9UL) /*!< TMRA7IE0 (Bit 9) */ +#define CTIMER_CTRL7_TMRA7IE0_Msk (0x200UL) /*!< TMRA7IE0 (Bitfield-Mask: 0x01) */ +#define CTIMER_CTRL7_TMRA7FN_Pos (6UL) /*!< TMRA7FN (Bit 6) */ +#define CTIMER_CTRL7_TMRA7FN_Msk (0x1c0UL) /*!< TMRA7FN (Bitfield-Mask: 0x07) */ +#define CTIMER_CTRL7_TMRA7CLK_Pos (1UL) /*!< TMRA7CLK (Bit 1) */ +#define CTIMER_CTRL7_TMRA7CLK_Msk (0x3eUL) /*!< TMRA7CLK (Bitfield-Mask: 0x1f) */ +#define CTIMER_CTRL7_TMRA7EN_Pos (0UL) /*!< TMRA7EN (Bit 0) */ +#define CTIMER_CTRL7_TMRA7EN_Msk (0x1UL) /*!< TMRA7EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CMPRAUXA7 ======================================================= */ +#define CTIMER_CMPRAUXA7_CMPR3A7_Pos (16UL) /*!< CMPR3A7 (Bit 16) */ +#define CTIMER_CMPRAUXA7_CMPR3A7_Msk (0xffff0000UL) /*!< CMPR3A7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXA7_CMPR2A7_Pos (0UL) /*!< CMPR2A7 (Bit 0) */ +#define CTIMER_CMPRAUXA7_CMPR2A7_Msk (0xffffUL) /*!< CMPR2A7 (Bitfield-Mask: 0xffff) */ +/* ======================================================= CMPRAUXB7 ======================================================= */ +#define CTIMER_CMPRAUXB7_CMPR3B7_Pos (16UL) /*!< CMPR3B7 (Bit 16) */ +#define CTIMER_CMPRAUXB7_CMPR3B7_Msk (0xffff0000UL) /*!< CMPR3B7 (Bitfield-Mask: 0xffff) */ +#define CTIMER_CMPRAUXB7_CMPR2B7_Pos (0UL) /*!< CMPR2B7 (Bit 0) */ +#define CTIMER_CMPRAUXB7_CMPR2B7_Msk (0xffffUL) /*!< CMPR2B7 (Bitfield-Mask: 0xffff) */ +/* ========================================================= AUX7 ========================================================== */ +#define CTIMER_AUX7_TMRB7EN23_Pos (30UL) /*!< TMRB7EN23 (Bit 30) */ +#define CTIMER_AUX7_TMRB7EN23_Msk (0x40000000UL) /*!< TMRB7EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7POL23_Pos (29UL) /*!< TMRB7POL23 (Bit 29) */ +#define CTIMER_AUX7_TMRB7POL23_Msk (0x20000000UL) /*!< TMRB7POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7TINV_Pos (28UL) /*!< TMRB7TINV (Bit 28) */ +#define CTIMER_AUX7_TMRB7TINV_Msk (0x10000000UL) /*!< TMRB7TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7NOSYNC_Pos (27UL) /*!< TMRB7NOSYNC (Bit 27) */ +#define CTIMER_AUX7_TMRB7NOSYNC_Msk (0x8000000UL) /*!< TMRB7NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRB7TRIG_Pos (23UL) /*!< TMRB7TRIG (Bit 23) */ +#define CTIMER_AUX7_TMRB7TRIG_Msk (0x7800000UL) /*!< TMRB7TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX7_TMRB7LMT_Pos (16UL) /*!< TMRB7LMT (Bit 16) */ +#define CTIMER_AUX7_TMRB7LMT_Msk (0x3f0000UL) /*!< TMRB7LMT (Bitfield-Mask: 0x3f) */ +#define CTIMER_AUX7_TMRA7EN23_Pos (14UL) /*!< TMRA7EN23 (Bit 14) */ +#define CTIMER_AUX7_TMRA7EN23_Msk (0x4000UL) /*!< TMRA7EN23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7POL23_Pos (13UL) /*!< TMRA7POL23 (Bit 13) */ +#define CTIMER_AUX7_TMRA7POL23_Msk (0x2000UL) /*!< TMRA7POL23 (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7TINV_Pos (12UL) /*!< TMRA7TINV (Bit 12) */ +#define CTIMER_AUX7_TMRA7TINV_Msk (0x1000UL) /*!< TMRA7TINV (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7NOSYNC_Pos (11UL) /*!< TMRA7NOSYNC (Bit 11) */ +#define CTIMER_AUX7_TMRA7NOSYNC_Msk (0x800UL) /*!< TMRA7NOSYNC (Bitfield-Mask: 0x01) */ +#define CTIMER_AUX7_TMRA7TRIG_Pos (7UL) /*!< TMRA7TRIG (Bit 7) */ +#define CTIMER_AUX7_TMRA7TRIG_Msk (0x780UL) /*!< TMRA7TRIG (Bitfield-Mask: 0x0f) */ +#define CTIMER_AUX7_TMRA7LMT_Pos (0UL) /*!< TMRA7LMT (Bit 0) */ +#define CTIMER_AUX7_TMRA7LMT_Msk (0x7fUL) /*!< TMRA7LMT (Bitfield-Mask: 0x7f) */ +/* ======================================================== GLOBEN ========================================================= */ +#define CTIMER_GLOBEN_ENB7_Pos (15UL) /*!< ENB7 (Bit 15) */ +#define CTIMER_GLOBEN_ENB7_Msk (0x8000UL) /*!< ENB7 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA7_Pos (14UL) /*!< ENA7 (Bit 14) */ +#define CTIMER_GLOBEN_ENA7_Msk (0x4000UL) /*!< ENA7 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB6_Pos (13UL) /*!< ENB6 (Bit 13) */ +#define CTIMER_GLOBEN_ENB6_Msk (0x2000UL) /*!< ENB6 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA6_Pos (12UL) /*!< ENA6 (Bit 12) */ +#define CTIMER_GLOBEN_ENA6_Msk (0x1000UL) /*!< ENA6 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB5_Pos (11UL) /*!< ENB5 (Bit 11) */ +#define CTIMER_GLOBEN_ENB5_Msk (0x800UL) /*!< ENB5 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA5_Pos (10UL) /*!< ENA5 (Bit 10) */ +#define CTIMER_GLOBEN_ENA5_Msk (0x400UL) /*!< ENA5 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB4_Pos (9UL) /*!< ENB4 (Bit 9) */ +#define CTIMER_GLOBEN_ENB4_Msk (0x200UL) /*!< ENB4 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA4_Pos (8UL) /*!< ENA4 (Bit 8) */ +#define CTIMER_GLOBEN_ENA4_Msk (0x100UL) /*!< ENA4 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB3_Pos (7UL) /*!< ENB3 (Bit 7) */ +#define CTIMER_GLOBEN_ENB3_Msk (0x80UL) /*!< ENB3 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA3_Pos (6UL) /*!< ENA3 (Bit 6) */ +#define CTIMER_GLOBEN_ENA3_Msk (0x40UL) /*!< ENA3 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB2_Pos (5UL) /*!< ENB2 (Bit 5) */ +#define CTIMER_GLOBEN_ENB2_Msk (0x20UL) /*!< ENB2 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA2_Pos (4UL) /*!< ENA2 (Bit 4) */ +#define CTIMER_GLOBEN_ENA2_Msk (0x10UL) /*!< ENA2 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB1_Pos (3UL) /*!< ENB1 (Bit 3) */ +#define CTIMER_GLOBEN_ENB1_Msk (0x8UL) /*!< ENB1 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA1_Pos (2UL) /*!< ENA1 (Bit 2) */ +#define CTIMER_GLOBEN_ENA1_Msk (0x4UL) /*!< ENA1 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENB0_Pos (1UL) /*!< ENB0 (Bit 1) */ +#define CTIMER_GLOBEN_ENB0_Msk (0x2UL) /*!< ENB0 (Bitfield-Mask: 0x01) */ +#define CTIMER_GLOBEN_ENA0_Pos (0UL) /*!< ENA0 (Bit 0) */ +#define CTIMER_GLOBEN_ENA0_Msk (0x1UL) /*!< ENA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== OUTCFG0 ======================================================== */ +#define CTIMER_OUTCFG0_CFG9_Pos (28UL) /*!< CFG9 (Bit 28) */ +#define CTIMER_OUTCFG0_CFG9_Msk (0x70000000UL) /*!< CFG9 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG8_Pos (25UL) /*!< CFG8 (Bit 25) */ +#define CTIMER_OUTCFG0_CFG8_Msk (0xe000000UL) /*!< CFG8 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG7_Pos (22UL) /*!< CFG7 (Bit 22) */ +#define CTIMER_OUTCFG0_CFG7_Msk (0x1c00000UL) /*!< CFG7 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG6_Pos (19UL) /*!< CFG6 (Bit 19) */ +#define CTIMER_OUTCFG0_CFG6_Msk (0x380000UL) /*!< CFG6 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG5_Pos (16UL) /*!< CFG5 (Bit 16) */ +#define CTIMER_OUTCFG0_CFG5_Msk (0x70000UL) /*!< CFG5 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG4_Pos (12UL) /*!< CFG4 (Bit 12) */ +#define CTIMER_OUTCFG0_CFG4_Msk (0x7000UL) /*!< CFG4 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG3_Pos (9UL) /*!< CFG3 (Bit 9) */ +#define CTIMER_OUTCFG0_CFG3_Msk (0xe00UL) /*!< CFG3 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG2_Pos (6UL) /*!< CFG2 (Bit 6) */ +#define CTIMER_OUTCFG0_CFG2_Msk (0x1c0UL) /*!< CFG2 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG1_Pos (3UL) /*!< CFG1 (Bit 3) */ +#define CTIMER_OUTCFG0_CFG1_Msk (0x38UL) /*!< CFG1 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG0_CFG0_Pos (0UL) /*!< CFG0 (Bit 0) */ +#define CTIMER_OUTCFG0_CFG0_Msk (0x7UL) /*!< CFG0 (Bitfield-Mask: 0x07) */ +/* ======================================================== OUTCFG1 ======================================================== */ +#define CTIMER_OUTCFG1_CFG19_Pos (28UL) /*!< CFG19 (Bit 28) */ +#define CTIMER_OUTCFG1_CFG19_Msk (0x70000000UL) /*!< CFG19 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG18_Pos (25UL) /*!< CFG18 (Bit 25) */ +#define CTIMER_OUTCFG1_CFG18_Msk (0xe000000UL) /*!< CFG18 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG17_Pos (22UL) /*!< CFG17 (Bit 22) */ +#define CTIMER_OUTCFG1_CFG17_Msk (0x1c00000UL) /*!< CFG17 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG16_Pos (19UL) /*!< CFG16 (Bit 19) */ +#define CTIMER_OUTCFG1_CFG16_Msk (0x380000UL) /*!< CFG16 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG15_Pos (16UL) /*!< CFG15 (Bit 16) */ +#define CTIMER_OUTCFG1_CFG15_Msk (0x70000UL) /*!< CFG15 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG14_Pos (12UL) /*!< CFG14 (Bit 12) */ +#define CTIMER_OUTCFG1_CFG14_Msk (0x7000UL) /*!< CFG14 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG13_Pos (9UL) /*!< CFG13 (Bit 9) */ +#define CTIMER_OUTCFG1_CFG13_Msk (0xe00UL) /*!< CFG13 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG12_Pos (6UL) /*!< CFG12 (Bit 6) */ +#define CTIMER_OUTCFG1_CFG12_Msk (0x1c0UL) /*!< CFG12 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG11_Pos (3UL) /*!< CFG11 (Bit 3) */ +#define CTIMER_OUTCFG1_CFG11_Msk (0x38UL) /*!< CFG11 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG1_CFG10_Pos (0UL) /*!< CFG10 (Bit 0) */ +#define CTIMER_OUTCFG1_CFG10_Msk (0x7UL) /*!< CFG10 (Bitfield-Mask: 0x07) */ +/* ======================================================== OUTCFG2 ======================================================== */ +#define CTIMER_OUTCFG2_CFG29_Pos (28UL) /*!< CFG29 (Bit 28) */ +#define CTIMER_OUTCFG2_CFG29_Msk (0x70000000UL) /*!< CFG29 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG28_Pos (25UL) /*!< CFG28 (Bit 25) */ +#define CTIMER_OUTCFG2_CFG28_Msk (0xe000000UL) /*!< CFG28 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG27_Pos (22UL) /*!< CFG27 (Bit 22) */ +#define CTIMER_OUTCFG2_CFG27_Msk (0x1c00000UL) /*!< CFG27 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG26_Pos (19UL) /*!< CFG26 (Bit 19) */ +#define CTIMER_OUTCFG2_CFG26_Msk (0x380000UL) /*!< CFG26 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG25_Pos (16UL) /*!< CFG25 (Bit 16) */ +#define CTIMER_OUTCFG2_CFG25_Msk (0x70000UL) /*!< CFG25 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG24_Pos (12UL) /*!< CFG24 (Bit 12) */ +#define CTIMER_OUTCFG2_CFG24_Msk (0x7000UL) /*!< CFG24 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG23_Pos (9UL) /*!< CFG23 (Bit 9) */ +#define CTIMER_OUTCFG2_CFG23_Msk (0xe00UL) /*!< CFG23 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG22_Pos (6UL) /*!< CFG22 (Bit 6) */ +#define CTIMER_OUTCFG2_CFG22_Msk (0x1c0UL) /*!< CFG22 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG21_Pos (3UL) /*!< CFG21 (Bit 3) */ +#define CTIMER_OUTCFG2_CFG21_Msk (0x38UL) /*!< CFG21 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG2_CFG20_Pos (0UL) /*!< CFG20 (Bit 0) */ +#define CTIMER_OUTCFG2_CFG20_Msk (0x7UL) /*!< CFG20 (Bitfield-Mask: 0x07) */ +/* ======================================================== OUTCFG3 ======================================================== */ +#define CTIMER_OUTCFG3_CFG31_Pos (3UL) /*!< CFG31 (Bit 3) */ +#define CTIMER_OUTCFG3_CFG31_Msk (0x38UL) /*!< CFG31 (Bitfield-Mask: 0x07) */ +#define CTIMER_OUTCFG3_CFG30_Pos (0UL) /*!< CFG30 (Bit 0) */ +#define CTIMER_OUTCFG3_CFG30_Msk (0x7UL) /*!< CFG30 (Bitfield-Mask: 0x07) */ +/* ========================================================= INCFG ========================================================= */ +#define CTIMER_INCFG_CFGB7_Pos (15UL) /*!< CFGB7 (Bit 15) */ +#define CTIMER_INCFG_CFGB7_Msk (0x8000UL) /*!< CFGB7 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA7_Pos (14UL) /*!< CFGA7 (Bit 14) */ +#define CTIMER_INCFG_CFGA7_Msk (0x4000UL) /*!< CFGA7 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB6_Pos (13UL) /*!< CFGB6 (Bit 13) */ +#define CTIMER_INCFG_CFGB6_Msk (0x2000UL) /*!< CFGB6 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA6_Pos (12UL) /*!< CFGA6 (Bit 12) */ +#define CTIMER_INCFG_CFGA6_Msk (0x1000UL) /*!< CFGA6 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB5_Pos (11UL) /*!< CFGB5 (Bit 11) */ +#define CTIMER_INCFG_CFGB5_Msk (0x800UL) /*!< CFGB5 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA5_Pos (10UL) /*!< CFGA5 (Bit 10) */ +#define CTIMER_INCFG_CFGA5_Msk (0x400UL) /*!< CFGA5 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB4_Pos (9UL) /*!< CFGB4 (Bit 9) */ +#define CTIMER_INCFG_CFGB4_Msk (0x200UL) /*!< CFGB4 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA4_Pos (8UL) /*!< CFGA4 (Bit 8) */ +#define CTIMER_INCFG_CFGA4_Msk (0x100UL) /*!< CFGA4 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB3_Pos (7UL) /*!< CFGB3 (Bit 7) */ +#define CTIMER_INCFG_CFGB3_Msk (0x80UL) /*!< CFGB3 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA3_Pos (6UL) /*!< CFGA3 (Bit 6) */ +#define CTIMER_INCFG_CFGA3_Msk (0x40UL) /*!< CFGA3 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB2_Pos (5UL) /*!< CFGB2 (Bit 5) */ +#define CTIMER_INCFG_CFGB2_Msk (0x20UL) /*!< CFGB2 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA2_Pos (4UL) /*!< CFGA2 (Bit 4) */ +#define CTIMER_INCFG_CFGA2_Msk (0x10UL) /*!< CFGA2 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB1_Pos (3UL) /*!< CFGB1 (Bit 3) */ +#define CTIMER_INCFG_CFGB1_Msk (0x8UL) /*!< CFGB1 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA1_Pos (2UL) /*!< CFGA1 (Bit 2) */ +#define CTIMER_INCFG_CFGA1_Msk (0x4UL) /*!< CFGA1 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGB0_Pos (1UL) /*!< CFGB0 (Bit 1) */ +#define CTIMER_INCFG_CFGB0_Msk (0x2UL) /*!< CFGB0 (Bitfield-Mask: 0x01) */ +#define CTIMER_INCFG_CFGA0_Pos (0UL) /*!< CFGA0 (Bit 0) */ +#define CTIMER_INCFG_CFGA0_Msk (0x1UL) /*!< CFGA0 (Bitfield-Mask: 0x01) */ +/* ========================================================= STCFG ========================================================= */ +#define CTIMER_STCFG_FREEZE_Pos (31UL) /*!< FREEZE (Bit 31) */ +#define CTIMER_STCFG_FREEZE_Msk (0x80000000UL) /*!< FREEZE (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_CLEAR_Pos (30UL) /*!< CLEAR (Bit 30) */ +#define CTIMER_STCFG_CLEAR_Msk (0x40000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_H_EN_Pos (15UL) /*!< COMPARE_H_EN (Bit 15) */ +#define CTIMER_STCFG_COMPARE_H_EN_Msk (0x8000UL) /*!< COMPARE_H_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_G_EN_Pos (14UL) /*!< COMPARE_G_EN (Bit 14) */ +#define CTIMER_STCFG_COMPARE_G_EN_Msk (0x4000UL) /*!< COMPARE_G_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_F_EN_Pos (13UL) /*!< COMPARE_F_EN (Bit 13) */ +#define CTIMER_STCFG_COMPARE_F_EN_Msk (0x2000UL) /*!< COMPARE_F_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_E_EN_Pos (12UL) /*!< COMPARE_E_EN (Bit 12) */ +#define CTIMER_STCFG_COMPARE_E_EN_Msk (0x1000UL) /*!< COMPARE_E_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_D_EN_Pos (11UL) /*!< COMPARE_D_EN (Bit 11) */ +#define CTIMER_STCFG_COMPARE_D_EN_Msk (0x800UL) /*!< COMPARE_D_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_C_EN_Pos (10UL) /*!< COMPARE_C_EN (Bit 10) */ +#define CTIMER_STCFG_COMPARE_C_EN_Msk (0x400UL) /*!< COMPARE_C_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_B_EN_Pos (9UL) /*!< COMPARE_B_EN (Bit 9) */ +#define CTIMER_STCFG_COMPARE_B_EN_Msk (0x200UL) /*!< COMPARE_B_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_COMPARE_A_EN_Pos (8UL) /*!< COMPARE_A_EN (Bit 8) */ +#define CTIMER_STCFG_COMPARE_A_EN_Msk (0x100UL) /*!< COMPARE_A_EN (Bitfield-Mask: 0x01) */ +#define CTIMER_STCFG_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ +#define CTIMER_STCFG_CLKSEL_Msk (0xfUL) /*!< CLKSEL (Bitfield-Mask: 0x0f) */ +/* ========================================================= STTMR ========================================================= */ +#define CTIMER_STTMR_STTMR_Pos (0UL) /*!< STTMR (Bit 0) */ +#define CTIMER_STTMR_STTMR_Msk (0xffffffffUL) /*!< STTMR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CAPTURECONTROL ===================================================== */ +#define CTIMER_CAPTURECONTROL_CAPTURE3_Pos (3UL) /*!< CAPTURE3 (Bit 3) */ +#define CTIMER_CAPTURECONTROL_CAPTURE3_Msk (0x8UL) /*!< CAPTURE3 (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURECONTROL_CAPTURE2_Pos (2UL) /*!< CAPTURE2 (Bit 2) */ +#define CTIMER_CAPTURECONTROL_CAPTURE2_Msk (0x4UL) /*!< CAPTURE2 (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURECONTROL_CAPTURE1_Pos (1UL) /*!< CAPTURE1 (Bit 1) */ +#define CTIMER_CAPTURECONTROL_CAPTURE1_Msk (0x2UL) /*!< CAPTURE1 (Bitfield-Mask: 0x01) */ +#define CTIMER_CAPTURECONTROL_CAPTURE0_Pos (0UL) /*!< CAPTURE0 (Bit 0) */ +#define CTIMER_CAPTURECONTROL_CAPTURE0_Msk (0x1UL) /*!< CAPTURE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SCMPR0 ========================================================= */ +#define CTIMER_SCMPR0_SCMPR0_Pos (0UL) /*!< SCMPR0 (Bit 0) */ +#define CTIMER_SCMPR0_SCMPR0_Msk (0xffffffffUL) /*!< SCMPR0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR1 ========================================================= */ +#define CTIMER_SCMPR1_SCMPR1_Pos (0UL) /*!< SCMPR1 (Bit 0) */ +#define CTIMER_SCMPR1_SCMPR1_Msk (0xffffffffUL) /*!< SCMPR1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR2 ========================================================= */ +#define CTIMER_SCMPR2_SCMPR2_Pos (0UL) /*!< SCMPR2 (Bit 0) */ +#define CTIMER_SCMPR2_SCMPR2_Msk (0xffffffffUL) /*!< SCMPR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR3 ========================================================= */ +#define CTIMER_SCMPR3_SCMPR3_Pos (0UL) /*!< SCMPR3 (Bit 0) */ +#define CTIMER_SCMPR3_SCMPR3_Msk (0xffffffffUL) /*!< SCMPR3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR4 ========================================================= */ +#define CTIMER_SCMPR4_SCMPR4_Pos (0UL) /*!< SCMPR4 (Bit 0) */ +#define CTIMER_SCMPR4_SCMPR4_Msk (0xffffffffUL) /*!< SCMPR4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR5 ========================================================= */ +#define CTIMER_SCMPR5_SCMPR5_Pos (0UL) /*!< SCMPR5 (Bit 0) */ +#define CTIMER_SCMPR5_SCMPR5_Msk (0xffffffffUL) /*!< SCMPR5 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR6 ========================================================= */ +#define CTIMER_SCMPR6_SCMPR6_Pos (0UL) /*!< SCMPR6 (Bit 0) */ +#define CTIMER_SCMPR6_SCMPR6_Msk (0xffffffffUL) /*!< SCMPR6 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCMPR7 ========================================================= */ +#define CTIMER_SCMPR7_SCMPR7_Pos (0UL) /*!< SCMPR7 (Bit 0) */ +#define CTIMER_SCMPR7_SCMPR7_Msk (0xffffffffUL) /*!< SCMPR7 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT0 ========================================================= */ +#define CTIMER_SCAPT0_SCAPT0_Pos (0UL) /*!< SCAPT0 (Bit 0) */ +#define CTIMER_SCAPT0_SCAPT0_Msk (0xffffffffUL) /*!< SCAPT0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT1 ========================================================= */ +#define CTIMER_SCAPT1_SCAPT1_Pos (0UL) /*!< SCAPT1 (Bit 0) */ +#define CTIMER_SCAPT1_SCAPT1_Msk (0xffffffffUL) /*!< SCAPT1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT2 ========================================================= */ +#define CTIMER_SCAPT2_SCAPT2_Pos (0UL) /*!< SCAPT2 (Bit 0) */ +#define CTIMER_SCAPT2_SCAPT2_Msk (0xffffffffUL) /*!< SCAPT2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCAPT3 ========================================================= */ +#define CTIMER_SCAPT3_SCAPT3_Pos (0UL) /*!< SCAPT3 (Bit 0) */ +#define CTIMER_SCAPT3_SCAPT3_Msk (0xffffffffUL) /*!< SCAPT3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR0 ========================================================= */ +#define CTIMER_SNVR0_SNVR0_Pos (0UL) /*!< SNVR0 (Bit 0) */ +#define CTIMER_SNVR0_SNVR0_Msk (0xffffffffUL) /*!< SNVR0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR1 ========================================================= */ +#define CTIMER_SNVR1_SNVR1_Pos (0UL) /*!< SNVR1 (Bit 0) */ +#define CTIMER_SNVR1_SNVR1_Msk (0xffffffffUL) /*!< SNVR1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR2 ========================================================= */ +#define CTIMER_SNVR2_SNVR2_Pos (0UL) /*!< SNVR2 (Bit 0) */ +#define CTIMER_SNVR2_SNVR2_Msk (0xffffffffUL) /*!< SNVR2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SNVR3 ========================================================= */ +#define CTIMER_SNVR3_SNVR3_Pos (0UL) /*!< SNVR3 (Bit 0) */ +#define CTIMER_SNVR3_SNVR3_Msk (0xffffffffUL) /*!< SNVR3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTEN ========================================================= */ +#define CTIMER_INTEN_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTEN_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTEN_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTEN_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTEN_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTEN_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTEN_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTEN_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTEN_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTEN_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTEN_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTEN_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTEN_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTEN_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTEN_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTEN_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTEN_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTEN_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTEN_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTEN_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTEN_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTEN_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTEN_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTEN_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTEN_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTEN_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTEN_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTEN_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTEN_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTEN_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTEN_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTEN_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTEN_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTEN_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define CTIMER_INTSTAT_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTSTAT_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTSTAT_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTSTAT_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTSTAT_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTSTAT_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTSTAT_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTSTAT_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTSTAT_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTSTAT_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTSTAT_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTSTAT_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTSTAT_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTSTAT_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTSTAT_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTSTAT_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTSTAT_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTSTAT_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTSTAT_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTSTAT_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTSTAT_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTSTAT_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTSTAT_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTSTAT_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTSTAT_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTSTAT_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTSTAT_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTSTAT_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTSTAT_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTSTAT_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTSTAT_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTSTAT_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSTAT_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTSTAT_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define CTIMER_INTCLR_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTCLR_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTCLR_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTCLR_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTCLR_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTCLR_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTCLR_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTCLR_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTCLR_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTCLR_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTCLR_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTCLR_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTCLR_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTCLR_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTCLR_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTCLR_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTCLR_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTCLR_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTCLR_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTCLR_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTCLR_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTCLR_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTCLR_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTCLR_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTCLR_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTCLR_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTCLR_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTCLR_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTCLR_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTCLR_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTCLR_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTCLR_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTCLR_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTCLR_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define CTIMER_INTSET_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */ +#define CTIMER_INTSET_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */ +#define CTIMER_INTSET_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */ +#define CTIMER_INTSET_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */ +#define CTIMER_INTSET_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */ +#define CTIMER_INTSET_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */ +#define CTIMER_INTSET_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */ +#define CTIMER_INTSET_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */ +#define CTIMER_INTSET_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */ +#define CTIMER_INTSET_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */ +#define CTIMER_INTSET_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */ +#define CTIMER_INTSET_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */ +#define CTIMER_INTSET_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */ +#define CTIMER_INTSET_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */ +#define CTIMER_INTSET_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */ +#define CTIMER_INTSET_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */ +#define CTIMER_INTSET_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */ +#define CTIMER_INTSET_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */ +#define CTIMER_INTSET_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */ +#define CTIMER_INTSET_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */ +#define CTIMER_INTSET_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */ +#define CTIMER_INTSET_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */ +#define CTIMER_INTSET_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */ +#define CTIMER_INTSET_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */ +#define CTIMER_INTSET_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */ +#define CTIMER_INTSET_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */ +#define CTIMER_INTSET_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */ +#define CTIMER_INTSET_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */ +#define CTIMER_INTSET_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */ +#define CTIMER_INTSET_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */ +#define CTIMER_INTSET_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */ +#define CTIMER_INTSET_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */ +#define CTIMER_INTSET_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */ +#define CTIMER_INTSET_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTEN ======================================================== */ +#define CTIMER_STMINTEN_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTEN_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTEN_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTEN_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTEN_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTEN_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTEN_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTEN_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTEN_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTEN_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTEN_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTEN_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTEN_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTEN_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTEN_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ====================================================== STMINTSTAT ======================================================= */ +#define CTIMER_STMINTSTAT_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTSTAT_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTSTAT_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTSTAT_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTSTAT_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTSTAT_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTSTAT_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTSTAT_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTSTAT_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTSTAT_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTSTAT_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTSTAT_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTSTAT_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSTAT_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTSTAT_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTCLR ======================================================= */ +#define CTIMER_STMINTCLR_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTCLR_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTCLR_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTCLR_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTCLR_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTCLR_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTCLR_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTCLR_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTCLR_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTCLR_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTCLR_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTCLR_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTCLR_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTCLR_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTCLR_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ +/* ======================================================= STMINTSET ======================================================= */ +#define CTIMER_STMINTSET_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */ +#define CTIMER_STMINTSET_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */ +#define CTIMER_STMINTSET_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */ +#define CTIMER_STMINTSET_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */ +#define CTIMER_STMINTSET_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */ +#define CTIMER_STMINTSET_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */ +#define CTIMER_STMINTSET_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */ +#define CTIMER_STMINTSET_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */ +#define CTIMER_STMINTSET_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */ +#define CTIMER_STMINTSET_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */ +#define CTIMER_STMINTSET_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */ +#define CTIMER_STMINTSET_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */ +#define CTIMER_STMINTSET_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */ +#define CTIMER_STMINTSET_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */ +#define CTIMER_STMINTSET_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PADREGA ======================================================== */ +#define GPIO_PADREGA_PAD3PWRUP_Pos (30UL) /*!< PAD3PWRUP (Bit 30) */ +#define GPIO_PADREGA_PAD3PWRUP_Msk (0x40000000UL) /*!< PAD3PWRUP (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3FNCSEL_Pos (27UL) /*!< PAD3FNCSEL (Bit 27) */ +#define GPIO_PADREGA_PAD3FNCSEL_Msk (0x38000000UL) /*!< PAD3FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD3STRNG_Pos (26UL) /*!< PAD3STRNG (Bit 26) */ +#define GPIO_PADREGA_PAD3STRNG_Msk (0x4000000UL) /*!< PAD3STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3INPEN_Pos (25UL) /*!< PAD3INPEN (Bit 25) */ +#define GPIO_PADREGA_PAD3INPEN_Msk (0x2000000UL) /*!< PAD3INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD3PULL_Pos (24UL) /*!< PAD3PULL (Bit 24) */ +#define GPIO_PADREGA_PAD3PULL_Msk (0x1000000UL) /*!< PAD3PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2FNCSEL_Pos (19UL) /*!< PAD2FNCSEL (Bit 19) */ +#define GPIO_PADREGA_PAD2FNCSEL_Msk (0x380000UL) /*!< PAD2FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD2STRNG_Pos (18UL) /*!< PAD2STRNG (Bit 18) */ +#define GPIO_PADREGA_PAD2STRNG_Msk (0x40000UL) /*!< PAD2STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2INPEN_Pos (17UL) /*!< PAD2INPEN (Bit 17) */ +#define GPIO_PADREGA_PAD2INPEN_Msk (0x20000UL) /*!< PAD2INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD2PULL_Pos (16UL) /*!< PAD2PULL (Bit 16) */ +#define GPIO_PADREGA_PAD2PULL_Msk (0x10000UL) /*!< PAD2PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1RSEL_Pos (14UL) /*!< PAD1RSEL (Bit 14) */ +#define GPIO_PADREGA_PAD1RSEL_Msk (0xc000UL) /*!< PAD1RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGA_PAD1FNCSEL_Pos (11UL) /*!< PAD1FNCSEL (Bit 11) */ +#define GPIO_PADREGA_PAD1FNCSEL_Msk (0x3800UL) /*!< PAD1FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD1STRNG_Pos (10UL) /*!< PAD1STRNG (Bit 10) */ +#define GPIO_PADREGA_PAD1STRNG_Msk (0x400UL) /*!< PAD1STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1INPEN_Pos (9UL) /*!< PAD1INPEN (Bit 9) */ +#define GPIO_PADREGA_PAD1INPEN_Msk (0x200UL) /*!< PAD1INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD1PULL_Pos (8UL) /*!< PAD1PULL (Bit 8) */ +#define GPIO_PADREGA_PAD1PULL_Msk (0x100UL) /*!< PAD1PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0RSEL_Pos (6UL) /*!< PAD0RSEL (Bit 6) */ +#define GPIO_PADREGA_PAD0RSEL_Msk (0xc0UL) /*!< PAD0RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGA_PAD0FNCSEL_Pos (3UL) /*!< PAD0FNCSEL (Bit 3) */ +#define GPIO_PADREGA_PAD0FNCSEL_Msk (0x38UL) /*!< PAD0FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGA_PAD0STRNG_Pos (2UL) /*!< PAD0STRNG (Bit 2) */ +#define GPIO_PADREGA_PAD0STRNG_Msk (0x4UL) /*!< PAD0STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0INPEN_Pos (1UL) /*!< PAD0INPEN (Bit 1) */ +#define GPIO_PADREGA_PAD0INPEN_Msk (0x2UL) /*!< PAD0INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGA_PAD0PULL_Pos (0UL) /*!< PAD0PULL (Bit 0) */ +#define GPIO_PADREGA_PAD0PULL_Msk (0x1UL) /*!< PAD0PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGB ======================================================== */ +#define GPIO_PADREGB_PAD7FNCSEL_Pos (27UL) /*!< PAD7FNCSEL (Bit 27) */ +#define GPIO_PADREGB_PAD7FNCSEL_Msk (0x38000000UL) /*!< PAD7FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD7STRNG_Pos (26UL) /*!< PAD7STRNG (Bit 26) */ +#define GPIO_PADREGB_PAD7STRNG_Msk (0x4000000UL) /*!< PAD7STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD7INPEN_Pos (25UL) /*!< PAD7INPEN (Bit 25) */ +#define GPIO_PADREGB_PAD7INPEN_Msk (0x2000000UL) /*!< PAD7INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD7PULL_Pos (24UL) /*!< PAD7PULL (Bit 24) */ +#define GPIO_PADREGB_PAD7PULL_Msk (0x1000000UL) /*!< PAD7PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6RSEL_Pos (22UL) /*!< PAD6RSEL (Bit 22) */ +#define GPIO_PADREGB_PAD6RSEL_Msk (0xc00000UL) /*!< PAD6RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGB_PAD6FNCSEL_Pos (19UL) /*!< PAD6FNCSEL (Bit 19) */ +#define GPIO_PADREGB_PAD6FNCSEL_Msk (0x380000UL) /*!< PAD6FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD6STRNG_Pos (18UL) /*!< PAD6STRNG (Bit 18) */ +#define GPIO_PADREGB_PAD6STRNG_Msk (0x40000UL) /*!< PAD6STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6INPEN_Pos (17UL) /*!< PAD6INPEN (Bit 17) */ +#define GPIO_PADREGB_PAD6INPEN_Msk (0x20000UL) /*!< PAD6INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD6PULL_Pos (16UL) /*!< PAD6PULL (Bit 16) */ +#define GPIO_PADREGB_PAD6PULL_Msk (0x10000UL) /*!< PAD6PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5RSEL_Pos (14UL) /*!< PAD5RSEL (Bit 14) */ +#define GPIO_PADREGB_PAD5RSEL_Msk (0xc000UL) /*!< PAD5RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGB_PAD5FNCSEL_Pos (11UL) /*!< PAD5FNCSEL (Bit 11) */ +#define GPIO_PADREGB_PAD5FNCSEL_Msk (0x3800UL) /*!< PAD5FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD5STRNG_Pos (10UL) /*!< PAD5STRNG (Bit 10) */ +#define GPIO_PADREGB_PAD5STRNG_Msk (0x400UL) /*!< PAD5STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5INPEN_Pos (9UL) /*!< PAD5INPEN (Bit 9) */ +#define GPIO_PADREGB_PAD5INPEN_Msk (0x200UL) /*!< PAD5INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD5PULL_Pos (8UL) /*!< PAD5PULL (Bit 8) */ +#define GPIO_PADREGB_PAD5PULL_Msk (0x100UL) /*!< PAD5PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4FNCSEL_Pos (3UL) /*!< PAD4FNCSEL (Bit 3) */ +#define GPIO_PADREGB_PAD4FNCSEL_Msk (0x38UL) /*!< PAD4FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGB_PAD4STRNG_Pos (2UL) /*!< PAD4STRNG (Bit 2) */ +#define GPIO_PADREGB_PAD4STRNG_Msk (0x4UL) /*!< PAD4STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4INPEN_Pos (1UL) /*!< PAD4INPEN (Bit 1) */ +#define GPIO_PADREGB_PAD4INPEN_Msk (0x2UL) /*!< PAD4INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGB_PAD4PULL_Pos (0UL) /*!< PAD4PULL (Bit 0) */ +#define GPIO_PADREGB_PAD4PULL_Msk (0x1UL) /*!< PAD4PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGC ======================================================== */ +#define GPIO_PADREGC_PAD11FNCSEL_Pos (27UL) /*!< PAD11FNCSEL (Bit 27) */ +#define GPIO_PADREGC_PAD11FNCSEL_Msk (0x38000000UL) /*!< PAD11FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD11STRNG_Pos (26UL) /*!< PAD11STRNG (Bit 26) */ +#define GPIO_PADREGC_PAD11STRNG_Msk (0x4000000UL) /*!< PAD11STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD11INPEN_Pos (25UL) /*!< PAD11INPEN (Bit 25) */ +#define GPIO_PADREGC_PAD11INPEN_Msk (0x2000000UL) /*!< PAD11INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD11PULL_Pos (24UL) /*!< PAD11PULL (Bit 24) */ +#define GPIO_PADREGC_PAD11PULL_Msk (0x1000000UL) /*!< PAD11PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10FNCSEL_Pos (19UL) /*!< PAD10FNCSEL (Bit 19) */ +#define GPIO_PADREGC_PAD10FNCSEL_Msk (0x380000UL) /*!< PAD10FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD10STRNG_Pos (18UL) /*!< PAD10STRNG (Bit 18) */ +#define GPIO_PADREGC_PAD10STRNG_Msk (0x40000UL) /*!< PAD10STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10INPEN_Pos (17UL) /*!< PAD10INPEN (Bit 17) */ +#define GPIO_PADREGC_PAD10INPEN_Msk (0x20000UL) /*!< PAD10INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD10PULL_Pos (16UL) /*!< PAD10PULL (Bit 16) */ +#define GPIO_PADREGC_PAD10PULL_Msk (0x10000UL) /*!< PAD10PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9RSEL_Pos (14UL) /*!< PAD9RSEL (Bit 14) */ +#define GPIO_PADREGC_PAD9RSEL_Msk (0xc000UL) /*!< PAD9RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGC_PAD9FNCSEL_Pos (11UL) /*!< PAD9FNCSEL (Bit 11) */ +#define GPIO_PADREGC_PAD9FNCSEL_Msk (0x3800UL) /*!< PAD9FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD9STRNG_Pos (10UL) /*!< PAD9STRNG (Bit 10) */ +#define GPIO_PADREGC_PAD9STRNG_Msk (0x400UL) /*!< PAD9STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9INPEN_Pos (9UL) /*!< PAD9INPEN (Bit 9) */ +#define GPIO_PADREGC_PAD9INPEN_Msk (0x200UL) /*!< PAD9INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD9PULL_Pos (8UL) /*!< PAD9PULL (Bit 8) */ +#define GPIO_PADREGC_PAD9PULL_Msk (0x100UL) /*!< PAD9PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8RSEL_Pos (6UL) /*!< PAD8RSEL (Bit 6) */ +#define GPIO_PADREGC_PAD8RSEL_Msk (0xc0UL) /*!< PAD8RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGC_PAD8FNCSEL_Pos (3UL) /*!< PAD8FNCSEL (Bit 3) */ +#define GPIO_PADREGC_PAD8FNCSEL_Msk (0x38UL) /*!< PAD8FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGC_PAD8STRNG_Pos (2UL) /*!< PAD8STRNG (Bit 2) */ +#define GPIO_PADREGC_PAD8STRNG_Msk (0x4UL) /*!< PAD8STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8INPEN_Pos (1UL) /*!< PAD8INPEN (Bit 1) */ +#define GPIO_PADREGC_PAD8INPEN_Msk (0x2UL) /*!< PAD8INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGC_PAD8PULL_Pos (0UL) /*!< PAD8PULL (Bit 0) */ +#define GPIO_PADREGC_PAD8PULL_Msk (0x1UL) /*!< PAD8PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGD ======================================================== */ +#define GPIO_PADREGD_PAD15FNCSEL_Pos (27UL) /*!< PAD15FNCSEL (Bit 27) */ +#define GPIO_PADREGD_PAD15FNCSEL_Msk (0x38000000UL) /*!< PAD15FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD15STRNG_Pos (26UL) /*!< PAD15STRNG (Bit 26) */ +#define GPIO_PADREGD_PAD15STRNG_Msk (0x4000000UL) /*!< PAD15STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD15INPEN_Pos (25UL) /*!< PAD15INPEN (Bit 25) */ +#define GPIO_PADREGD_PAD15INPEN_Msk (0x2000000UL) /*!< PAD15INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD15PULL_Pos (24UL) /*!< PAD15PULL (Bit 24) */ +#define GPIO_PADREGD_PAD15PULL_Msk (0x1000000UL) /*!< PAD15PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14FNCSEL_Pos (19UL) /*!< PAD14FNCSEL (Bit 19) */ +#define GPIO_PADREGD_PAD14FNCSEL_Msk (0x380000UL) /*!< PAD14FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD14STRNG_Pos (18UL) /*!< PAD14STRNG (Bit 18) */ +#define GPIO_PADREGD_PAD14STRNG_Msk (0x40000UL) /*!< PAD14STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14INPEN_Pos (17UL) /*!< PAD14INPEN (Bit 17) */ +#define GPIO_PADREGD_PAD14INPEN_Msk (0x20000UL) /*!< PAD14INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD14PULL_Pos (16UL) /*!< PAD14PULL (Bit 16) */ +#define GPIO_PADREGD_PAD14PULL_Msk (0x10000UL) /*!< PAD14PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13FNCSEL_Pos (11UL) /*!< PAD13FNCSEL (Bit 11) */ +#define GPIO_PADREGD_PAD13FNCSEL_Msk (0x3800UL) /*!< PAD13FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD13STRNG_Pos (10UL) /*!< PAD13STRNG (Bit 10) */ +#define GPIO_PADREGD_PAD13STRNG_Msk (0x400UL) /*!< PAD13STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13INPEN_Pos (9UL) /*!< PAD13INPEN (Bit 9) */ +#define GPIO_PADREGD_PAD13INPEN_Msk (0x200UL) /*!< PAD13INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD13PULL_Pos (8UL) /*!< PAD13PULL (Bit 8) */ +#define GPIO_PADREGD_PAD13PULL_Msk (0x100UL) /*!< PAD13PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12FNCSEL_Pos (3UL) /*!< PAD12FNCSEL (Bit 3) */ +#define GPIO_PADREGD_PAD12FNCSEL_Msk (0x38UL) /*!< PAD12FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGD_PAD12STRNG_Pos (2UL) /*!< PAD12STRNG (Bit 2) */ +#define GPIO_PADREGD_PAD12STRNG_Msk (0x4UL) /*!< PAD12STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12INPEN_Pos (1UL) /*!< PAD12INPEN (Bit 1) */ +#define GPIO_PADREGD_PAD12INPEN_Msk (0x2UL) /*!< PAD12INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGD_PAD12PULL_Pos (0UL) /*!< PAD12PULL (Bit 0) */ +#define GPIO_PADREGD_PAD12PULL_Msk (0x1UL) /*!< PAD12PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGE ======================================================== */ +#define GPIO_PADREGE_PAD19FNCSEL_Pos (27UL) /*!< PAD19FNCSEL (Bit 27) */ +#define GPIO_PADREGE_PAD19FNCSEL_Msk (0x38000000UL) /*!< PAD19FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD19STRNG_Pos (26UL) /*!< PAD19STRNG (Bit 26) */ +#define GPIO_PADREGE_PAD19STRNG_Msk (0x4000000UL) /*!< PAD19STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD19INPEN_Pos (25UL) /*!< PAD19INPEN (Bit 25) */ +#define GPIO_PADREGE_PAD19INPEN_Msk (0x2000000UL) /*!< PAD19INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD19PULL_Pos (24UL) /*!< PAD19PULL (Bit 24) */ +#define GPIO_PADREGE_PAD19PULL_Msk (0x1000000UL) /*!< PAD19PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18FNCSEL_Pos (19UL) /*!< PAD18FNCSEL (Bit 19) */ +#define GPIO_PADREGE_PAD18FNCSEL_Msk (0x380000UL) /*!< PAD18FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD18STRNG_Pos (18UL) /*!< PAD18STRNG (Bit 18) */ +#define GPIO_PADREGE_PAD18STRNG_Msk (0x40000UL) /*!< PAD18STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18INPEN_Pos (17UL) /*!< PAD18INPEN (Bit 17) */ +#define GPIO_PADREGE_PAD18INPEN_Msk (0x20000UL) /*!< PAD18INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD18PULL_Pos (16UL) /*!< PAD18PULL (Bit 16) */ +#define GPIO_PADREGE_PAD18PULL_Msk (0x10000UL) /*!< PAD18PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17FNCSEL_Pos (11UL) /*!< PAD17FNCSEL (Bit 11) */ +#define GPIO_PADREGE_PAD17FNCSEL_Msk (0x3800UL) /*!< PAD17FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD17STRNG_Pos (10UL) /*!< PAD17STRNG (Bit 10) */ +#define GPIO_PADREGE_PAD17STRNG_Msk (0x400UL) /*!< PAD17STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17INPEN_Pos (9UL) /*!< PAD17INPEN (Bit 9) */ +#define GPIO_PADREGE_PAD17INPEN_Msk (0x200UL) /*!< PAD17INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD17PULL_Pos (8UL) /*!< PAD17PULL (Bit 8) */ +#define GPIO_PADREGE_PAD17PULL_Msk (0x100UL) /*!< PAD17PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16FNCSEL_Pos (3UL) /*!< PAD16FNCSEL (Bit 3) */ +#define GPIO_PADREGE_PAD16FNCSEL_Msk (0x38UL) /*!< PAD16FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGE_PAD16STRNG_Pos (2UL) /*!< PAD16STRNG (Bit 2) */ +#define GPIO_PADREGE_PAD16STRNG_Msk (0x4UL) /*!< PAD16STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16INPEN_Pos (1UL) /*!< PAD16INPEN (Bit 1) */ +#define GPIO_PADREGE_PAD16INPEN_Msk (0x2UL) /*!< PAD16INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGE_PAD16PULL_Pos (0UL) /*!< PAD16PULL (Bit 0) */ +#define GPIO_PADREGE_PAD16PULL_Msk (0x1UL) /*!< PAD16PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGF ======================================================== */ +#define GPIO_PADREGF_PAD23FNCSEL_Pos (27UL) /*!< PAD23FNCSEL (Bit 27) */ +#define GPIO_PADREGF_PAD23FNCSEL_Msk (0x38000000UL) /*!< PAD23FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD23STRNG_Pos (26UL) /*!< PAD23STRNG (Bit 26) */ +#define GPIO_PADREGF_PAD23STRNG_Msk (0x4000000UL) /*!< PAD23STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD23INPEN_Pos (25UL) /*!< PAD23INPEN (Bit 25) */ +#define GPIO_PADREGF_PAD23INPEN_Msk (0x2000000UL) /*!< PAD23INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD23PULL_Pos (24UL) /*!< PAD23PULL (Bit 24) */ +#define GPIO_PADREGF_PAD23PULL_Msk (0x1000000UL) /*!< PAD23PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22FNCSEL_Pos (19UL) /*!< PAD22FNCSEL (Bit 19) */ +#define GPIO_PADREGF_PAD22FNCSEL_Msk (0x380000UL) /*!< PAD22FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD22STRNG_Pos (18UL) /*!< PAD22STRNG (Bit 18) */ +#define GPIO_PADREGF_PAD22STRNG_Msk (0x40000UL) /*!< PAD22STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22INPEN_Pos (17UL) /*!< PAD22INPEN (Bit 17) */ +#define GPIO_PADREGF_PAD22INPEN_Msk (0x20000UL) /*!< PAD22INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD22PULL_Pos (16UL) /*!< PAD22PULL (Bit 16) */ +#define GPIO_PADREGF_PAD22PULL_Msk (0x10000UL) /*!< PAD22PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21FNCSEL_Pos (11UL) /*!< PAD21FNCSEL (Bit 11) */ +#define GPIO_PADREGF_PAD21FNCSEL_Msk (0x3800UL) /*!< PAD21FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD21STRNG_Pos (10UL) /*!< PAD21STRNG (Bit 10) */ +#define GPIO_PADREGF_PAD21STRNG_Msk (0x400UL) /*!< PAD21STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21INPEN_Pos (9UL) /*!< PAD21INPEN (Bit 9) */ +#define GPIO_PADREGF_PAD21INPEN_Msk (0x200UL) /*!< PAD21INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD21PULL_Pos (8UL) /*!< PAD21PULL (Bit 8) */ +#define GPIO_PADREGF_PAD21PULL_Msk (0x100UL) /*!< PAD21PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20FNCSEL_Pos (3UL) /*!< PAD20FNCSEL (Bit 3) */ +#define GPIO_PADREGF_PAD20FNCSEL_Msk (0x38UL) /*!< PAD20FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGF_PAD20STRNG_Pos (2UL) /*!< PAD20STRNG (Bit 2) */ +#define GPIO_PADREGF_PAD20STRNG_Msk (0x4UL) /*!< PAD20STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20INPEN_Pos (1UL) /*!< PAD20INPEN (Bit 1) */ +#define GPIO_PADREGF_PAD20INPEN_Msk (0x2UL) /*!< PAD20INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGF_PAD20PULL_Pos (0UL) /*!< PAD20PULL (Bit 0) */ +#define GPIO_PADREGF_PAD20PULL_Msk (0x1UL) /*!< PAD20PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGG ======================================================== */ +#define GPIO_PADREGG_PAD27RSEL_Pos (30UL) /*!< PAD27RSEL (Bit 30) */ +#define GPIO_PADREGG_PAD27RSEL_Msk (0xc0000000UL) /*!< PAD27RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGG_PAD27FNCSEL_Pos (27UL) /*!< PAD27FNCSEL (Bit 27) */ +#define GPIO_PADREGG_PAD27FNCSEL_Msk (0x38000000UL) /*!< PAD27FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD27STRNG_Pos (26UL) /*!< PAD27STRNG (Bit 26) */ +#define GPIO_PADREGG_PAD27STRNG_Msk (0x4000000UL) /*!< PAD27STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD27INPEN_Pos (25UL) /*!< PAD27INPEN (Bit 25) */ +#define GPIO_PADREGG_PAD27INPEN_Msk (0x2000000UL) /*!< PAD27INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD27PULL_Pos (24UL) /*!< PAD27PULL (Bit 24) */ +#define GPIO_PADREGG_PAD27PULL_Msk (0x1000000UL) /*!< PAD27PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26FNCSEL_Pos (19UL) /*!< PAD26FNCSEL (Bit 19) */ +#define GPIO_PADREGG_PAD26FNCSEL_Msk (0x380000UL) /*!< PAD26FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD26STRNG_Pos (18UL) /*!< PAD26STRNG (Bit 18) */ +#define GPIO_PADREGG_PAD26STRNG_Msk (0x40000UL) /*!< PAD26STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26INPEN_Pos (17UL) /*!< PAD26INPEN (Bit 17) */ +#define GPIO_PADREGG_PAD26INPEN_Msk (0x20000UL) /*!< PAD26INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD26PULL_Pos (16UL) /*!< PAD26PULL (Bit 16) */ +#define GPIO_PADREGG_PAD26PULL_Msk (0x10000UL) /*!< PAD26PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25RSEL_Pos (14UL) /*!< PAD25RSEL (Bit 14) */ +#define GPIO_PADREGG_PAD25RSEL_Msk (0xc000UL) /*!< PAD25RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGG_PAD25FNCSEL_Pos (11UL) /*!< PAD25FNCSEL (Bit 11) */ +#define GPIO_PADREGG_PAD25FNCSEL_Msk (0x3800UL) /*!< PAD25FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD25STRNG_Pos (10UL) /*!< PAD25STRNG (Bit 10) */ +#define GPIO_PADREGG_PAD25STRNG_Msk (0x400UL) /*!< PAD25STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25INPEN_Pos (9UL) /*!< PAD25INPEN (Bit 9) */ +#define GPIO_PADREGG_PAD25INPEN_Msk (0x200UL) /*!< PAD25INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD25PULL_Pos (8UL) /*!< PAD25PULL (Bit 8) */ +#define GPIO_PADREGG_PAD25PULL_Msk (0x100UL) /*!< PAD25PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24FNCSEL_Pos (3UL) /*!< PAD24FNCSEL (Bit 3) */ +#define GPIO_PADREGG_PAD24FNCSEL_Msk (0x38UL) /*!< PAD24FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGG_PAD24STRNG_Pos (2UL) /*!< PAD24STRNG (Bit 2) */ +#define GPIO_PADREGG_PAD24STRNG_Msk (0x4UL) /*!< PAD24STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24INPEN_Pos (1UL) /*!< PAD24INPEN (Bit 1) */ +#define GPIO_PADREGG_PAD24INPEN_Msk (0x2UL) /*!< PAD24INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGG_PAD24PULL_Pos (0UL) /*!< PAD24PULL (Bit 0) */ +#define GPIO_PADREGG_PAD24PULL_Msk (0x1UL) /*!< PAD24PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGH ======================================================== */ +#define GPIO_PADREGH_PAD31FNCSEL_Pos (27UL) /*!< PAD31FNCSEL (Bit 27) */ +#define GPIO_PADREGH_PAD31FNCSEL_Msk (0x38000000UL) /*!< PAD31FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD31STRNG_Pos (26UL) /*!< PAD31STRNG (Bit 26) */ +#define GPIO_PADREGH_PAD31STRNG_Msk (0x4000000UL) /*!< PAD31STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD31INPEN_Pos (25UL) /*!< PAD31INPEN (Bit 25) */ +#define GPIO_PADREGH_PAD31INPEN_Msk (0x2000000UL) /*!< PAD31INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD31PULL_Pos (24UL) /*!< PAD31PULL (Bit 24) */ +#define GPIO_PADREGH_PAD31PULL_Msk (0x1000000UL) /*!< PAD31PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30FNCSEL_Pos (19UL) /*!< PAD30FNCSEL (Bit 19) */ +#define GPIO_PADREGH_PAD30FNCSEL_Msk (0x380000UL) /*!< PAD30FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD30STRNG_Pos (18UL) /*!< PAD30STRNG (Bit 18) */ +#define GPIO_PADREGH_PAD30STRNG_Msk (0x40000UL) /*!< PAD30STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30INPEN_Pos (17UL) /*!< PAD30INPEN (Bit 17) */ +#define GPIO_PADREGH_PAD30INPEN_Msk (0x20000UL) /*!< PAD30INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD30PULL_Pos (16UL) /*!< PAD30PULL (Bit 16) */ +#define GPIO_PADREGH_PAD30PULL_Msk (0x10000UL) /*!< PAD30PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29FNCSEL_Pos (11UL) /*!< PAD29FNCSEL (Bit 11) */ +#define GPIO_PADREGH_PAD29FNCSEL_Msk (0x3800UL) /*!< PAD29FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD29STRNG_Pos (10UL) /*!< PAD29STRNG (Bit 10) */ +#define GPIO_PADREGH_PAD29STRNG_Msk (0x400UL) /*!< PAD29STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29INPEN_Pos (9UL) /*!< PAD29INPEN (Bit 9) */ +#define GPIO_PADREGH_PAD29INPEN_Msk (0x200UL) /*!< PAD29INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD29PULL_Pos (8UL) /*!< PAD29PULL (Bit 8) */ +#define GPIO_PADREGH_PAD29PULL_Msk (0x100UL) /*!< PAD29PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28FNCSEL_Pos (3UL) /*!< PAD28FNCSEL (Bit 3) */ +#define GPIO_PADREGH_PAD28FNCSEL_Msk (0x38UL) /*!< PAD28FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGH_PAD28STRNG_Pos (2UL) /*!< PAD28STRNG (Bit 2) */ +#define GPIO_PADREGH_PAD28STRNG_Msk (0x4UL) /*!< PAD28STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28INPEN_Pos (1UL) /*!< PAD28INPEN (Bit 1) */ +#define GPIO_PADREGH_PAD28INPEN_Msk (0x2UL) /*!< PAD28INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGH_PAD28PULL_Pos (0UL) /*!< PAD28PULL (Bit 0) */ +#define GPIO_PADREGH_PAD28PULL_Msk (0x1UL) /*!< PAD28PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGI ======================================================== */ +#define GPIO_PADREGI_PAD35FNCSEL_Pos (27UL) /*!< PAD35FNCSEL (Bit 27) */ +#define GPIO_PADREGI_PAD35FNCSEL_Msk (0x38000000UL) /*!< PAD35FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD35STRNG_Pos (26UL) /*!< PAD35STRNG (Bit 26) */ +#define GPIO_PADREGI_PAD35STRNG_Msk (0x4000000UL) /*!< PAD35STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD35INPEN_Pos (25UL) /*!< PAD35INPEN (Bit 25) */ +#define GPIO_PADREGI_PAD35INPEN_Msk (0x2000000UL) /*!< PAD35INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD35PULL_Pos (24UL) /*!< PAD35PULL (Bit 24) */ +#define GPIO_PADREGI_PAD35PULL_Msk (0x1000000UL) /*!< PAD35PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34FNCSEL_Pos (19UL) /*!< PAD34FNCSEL (Bit 19) */ +#define GPIO_PADREGI_PAD34FNCSEL_Msk (0x380000UL) /*!< PAD34FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD34STRNG_Pos (18UL) /*!< PAD34STRNG (Bit 18) */ +#define GPIO_PADREGI_PAD34STRNG_Msk (0x40000UL) /*!< PAD34STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34INPEN_Pos (17UL) /*!< PAD34INPEN (Bit 17) */ +#define GPIO_PADREGI_PAD34INPEN_Msk (0x20000UL) /*!< PAD34INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD34PULL_Pos (16UL) /*!< PAD34PULL (Bit 16) */ +#define GPIO_PADREGI_PAD34PULL_Msk (0x10000UL) /*!< PAD34PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33FNCSEL_Pos (11UL) /*!< PAD33FNCSEL (Bit 11) */ +#define GPIO_PADREGI_PAD33FNCSEL_Msk (0x3800UL) /*!< PAD33FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD33STRNG_Pos (10UL) /*!< PAD33STRNG (Bit 10) */ +#define GPIO_PADREGI_PAD33STRNG_Msk (0x400UL) /*!< PAD33STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33INPEN_Pos (9UL) /*!< PAD33INPEN (Bit 9) */ +#define GPIO_PADREGI_PAD33INPEN_Msk (0x200UL) /*!< PAD33INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD33PULL_Pos (8UL) /*!< PAD33PULL (Bit 8) */ +#define GPIO_PADREGI_PAD33PULL_Msk (0x100UL) /*!< PAD33PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32FNCSEL_Pos (3UL) /*!< PAD32FNCSEL (Bit 3) */ +#define GPIO_PADREGI_PAD32FNCSEL_Msk (0x38UL) /*!< PAD32FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGI_PAD32STRNG_Pos (2UL) /*!< PAD32STRNG (Bit 2) */ +#define GPIO_PADREGI_PAD32STRNG_Msk (0x4UL) /*!< PAD32STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32INPEN_Pos (1UL) /*!< PAD32INPEN (Bit 1) */ +#define GPIO_PADREGI_PAD32INPEN_Msk (0x2UL) /*!< PAD32INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGI_PAD32PULL_Pos (0UL) /*!< PAD32PULL (Bit 0) */ +#define GPIO_PADREGI_PAD32PULL_Msk (0x1UL) /*!< PAD32PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGJ ======================================================== */ +#define GPIO_PADREGJ_PAD39RSEL_Pos (30UL) /*!< PAD39RSEL (Bit 30) */ +#define GPIO_PADREGJ_PAD39RSEL_Msk (0xc0000000UL) /*!< PAD39RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGJ_PAD39FNCSEL_Pos (27UL) /*!< PAD39FNCSEL (Bit 27) */ +#define GPIO_PADREGJ_PAD39FNCSEL_Msk (0x38000000UL) /*!< PAD39FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD39STRNG_Pos (26UL) /*!< PAD39STRNG (Bit 26) */ +#define GPIO_PADREGJ_PAD39STRNG_Msk (0x4000000UL) /*!< PAD39STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD39INPEN_Pos (25UL) /*!< PAD39INPEN (Bit 25) */ +#define GPIO_PADREGJ_PAD39INPEN_Msk (0x2000000UL) /*!< PAD39INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD39PULL_Pos (24UL) /*!< PAD39PULL (Bit 24) */ +#define GPIO_PADREGJ_PAD39PULL_Msk (0x1000000UL) /*!< PAD39PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38FNCSEL_Pos (19UL) /*!< PAD38FNCSEL (Bit 19) */ +#define GPIO_PADREGJ_PAD38FNCSEL_Msk (0x380000UL) /*!< PAD38FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD38STRNG_Pos (18UL) /*!< PAD38STRNG (Bit 18) */ +#define GPIO_PADREGJ_PAD38STRNG_Msk (0x40000UL) /*!< PAD38STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38INPEN_Pos (17UL) /*!< PAD38INPEN (Bit 17) */ +#define GPIO_PADREGJ_PAD38INPEN_Msk (0x20000UL) /*!< PAD38INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD38PULL_Pos (16UL) /*!< PAD38PULL (Bit 16) */ +#define GPIO_PADREGJ_PAD38PULL_Msk (0x10000UL) /*!< PAD38PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37PWRDN_Pos (15UL) /*!< PAD37PWRDN (Bit 15) */ +#define GPIO_PADREGJ_PAD37PWRDN_Msk (0x8000UL) /*!< PAD37PWRDN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37FNCSEL_Pos (11UL) /*!< PAD37FNCSEL (Bit 11) */ +#define GPIO_PADREGJ_PAD37FNCSEL_Msk (0x3800UL) /*!< PAD37FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD37STRNG_Pos (10UL) /*!< PAD37STRNG (Bit 10) */ +#define GPIO_PADREGJ_PAD37STRNG_Msk (0x400UL) /*!< PAD37STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37INPEN_Pos (9UL) /*!< PAD37INPEN (Bit 9) */ +#define GPIO_PADREGJ_PAD37INPEN_Msk (0x200UL) /*!< PAD37INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD37PULL_Pos (8UL) /*!< PAD37PULL (Bit 8) */ +#define GPIO_PADREGJ_PAD37PULL_Msk (0x100UL) /*!< PAD37PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36PWRUP_Pos (6UL) /*!< PAD36PWRUP (Bit 6) */ +#define GPIO_PADREGJ_PAD36PWRUP_Msk (0x40UL) /*!< PAD36PWRUP (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36FNCSEL_Pos (3UL) /*!< PAD36FNCSEL (Bit 3) */ +#define GPIO_PADREGJ_PAD36FNCSEL_Msk (0x38UL) /*!< PAD36FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGJ_PAD36STRNG_Pos (2UL) /*!< PAD36STRNG (Bit 2) */ +#define GPIO_PADREGJ_PAD36STRNG_Msk (0x4UL) /*!< PAD36STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36INPEN_Pos (1UL) /*!< PAD36INPEN (Bit 1) */ +#define GPIO_PADREGJ_PAD36INPEN_Msk (0x2UL) /*!< PAD36INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGJ_PAD36PULL_Pos (0UL) /*!< PAD36PULL (Bit 0) */ +#define GPIO_PADREGJ_PAD36PULL_Msk (0x1UL) /*!< PAD36PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGK ======================================================== */ +#define GPIO_PADREGK_PAD43RSEL_Pos (30UL) /*!< PAD43RSEL (Bit 30) */ +#define GPIO_PADREGK_PAD43RSEL_Msk (0xc0000000UL) /*!< PAD43RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD43FNCSEL_Pos (27UL) /*!< PAD43FNCSEL (Bit 27) */ +#define GPIO_PADREGK_PAD43FNCSEL_Msk (0x38000000UL) /*!< PAD43FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD43STRNG_Pos (26UL) /*!< PAD43STRNG (Bit 26) */ +#define GPIO_PADREGK_PAD43STRNG_Msk (0x4000000UL) /*!< PAD43STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD43INPEN_Pos (25UL) /*!< PAD43INPEN (Bit 25) */ +#define GPIO_PADREGK_PAD43INPEN_Msk (0x2000000UL) /*!< PAD43INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD43PULL_Pos (24UL) /*!< PAD43PULL (Bit 24) */ +#define GPIO_PADREGK_PAD43PULL_Msk (0x1000000UL) /*!< PAD43PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42RSEL_Pos (22UL) /*!< PAD42RSEL (Bit 22) */ +#define GPIO_PADREGK_PAD42RSEL_Msk (0xc00000UL) /*!< PAD42RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD42FNCSEL_Pos (19UL) /*!< PAD42FNCSEL (Bit 19) */ +#define GPIO_PADREGK_PAD42FNCSEL_Msk (0x380000UL) /*!< PAD42FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD42STRNG_Pos (18UL) /*!< PAD42STRNG (Bit 18) */ +#define GPIO_PADREGK_PAD42STRNG_Msk (0x40000UL) /*!< PAD42STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42INPEN_Pos (17UL) /*!< PAD42INPEN (Bit 17) */ +#define GPIO_PADREGK_PAD42INPEN_Msk (0x20000UL) /*!< PAD42INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD42PULL_Pos (16UL) /*!< PAD42PULL (Bit 16) */ +#define GPIO_PADREGK_PAD42PULL_Msk (0x10000UL) /*!< PAD42PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41PWRDN_Pos (15UL) /*!< PAD41PWRDN (Bit 15) */ +#define GPIO_PADREGK_PAD41PWRDN_Msk (0x8000UL) /*!< PAD41PWRDN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41FNCSEL_Pos (11UL) /*!< PAD41FNCSEL (Bit 11) */ +#define GPIO_PADREGK_PAD41FNCSEL_Msk (0x3800UL) /*!< PAD41FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD41STRNG_Pos (10UL) /*!< PAD41STRNG (Bit 10) */ +#define GPIO_PADREGK_PAD41STRNG_Msk (0x400UL) /*!< PAD41STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41INPEN_Pos (9UL) /*!< PAD41INPEN (Bit 9) */ +#define GPIO_PADREGK_PAD41INPEN_Msk (0x200UL) /*!< PAD41INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD41PULL_Pos (8UL) /*!< PAD41PULL (Bit 8) */ +#define GPIO_PADREGK_PAD41PULL_Msk (0x100UL) /*!< PAD41PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40RSEL_Pos (6UL) /*!< PAD40RSEL (Bit 6) */ +#define GPIO_PADREGK_PAD40RSEL_Msk (0xc0UL) /*!< PAD40RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGK_PAD40FNCSEL_Pos (3UL) /*!< PAD40FNCSEL (Bit 3) */ +#define GPIO_PADREGK_PAD40FNCSEL_Msk (0x38UL) /*!< PAD40FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGK_PAD40STRNG_Pos (2UL) /*!< PAD40STRNG (Bit 2) */ +#define GPIO_PADREGK_PAD40STRNG_Msk (0x4UL) /*!< PAD40STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40INPEN_Pos (1UL) /*!< PAD40INPEN (Bit 1) */ +#define GPIO_PADREGK_PAD40INPEN_Msk (0x2UL) /*!< PAD40INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGK_PAD40PULL_Pos (0UL) /*!< PAD40PULL (Bit 0) */ +#define GPIO_PADREGK_PAD40PULL_Msk (0x1UL) /*!< PAD40PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGL ======================================================== */ +#define GPIO_PADREGL_PAD47FNCSEL_Pos (27UL) /*!< PAD47FNCSEL (Bit 27) */ +#define GPIO_PADREGL_PAD47FNCSEL_Msk (0x38000000UL) /*!< PAD47FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD47STRNG_Pos (26UL) /*!< PAD47STRNG (Bit 26) */ +#define GPIO_PADREGL_PAD47STRNG_Msk (0x4000000UL) /*!< PAD47STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD47INPEN_Pos (25UL) /*!< PAD47INPEN (Bit 25) */ +#define GPIO_PADREGL_PAD47INPEN_Msk (0x2000000UL) /*!< PAD47INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD47PULL_Pos (24UL) /*!< PAD47PULL (Bit 24) */ +#define GPIO_PADREGL_PAD47PULL_Msk (0x1000000UL) /*!< PAD47PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46FNCSEL_Pos (19UL) /*!< PAD46FNCSEL (Bit 19) */ +#define GPIO_PADREGL_PAD46FNCSEL_Msk (0x380000UL) /*!< PAD46FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD46STRNG_Pos (18UL) /*!< PAD46STRNG (Bit 18) */ +#define GPIO_PADREGL_PAD46STRNG_Msk (0x40000UL) /*!< PAD46STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46INPEN_Pos (17UL) /*!< PAD46INPEN (Bit 17) */ +#define GPIO_PADREGL_PAD46INPEN_Msk (0x20000UL) /*!< PAD46INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD46PULL_Pos (16UL) /*!< PAD46PULL (Bit 16) */ +#define GPIO_PADREGL_PAD46PULL_Msk (0x10000UL) /*!< PAD46PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45FNCSEL_Pos (11UL) /*!< PAD45FNCSEL (Bit 11) */ +#define GPIO_PADREGL_PAD45FNCSEL_Msk (0x3800UL) /*!< PAD45FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD45STRNG_Pos (10UL) /*!< PAD45STRNG (Bit 10) */ +#define GPIO_PADREGL_PAD45STRNG_Msk (0x400UL) /*!< PAD45STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45INPEN_Pos (9UL) /*!< PAD45INPEN (Bit 9) */ +#define GPIO_PADREGL_PAD45INPEN_Msk (0x200UL) /*!< PAD45INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD45PULL_Pos (8UL) /*!< PAD45PULL (Bit 8) */ +#define GPIO_PADREGL_PAD45PULL_Msk (0x100UL) /*!< PAD45PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44FNCSEL_Pos (3UL) /*!< PAD44FNCSEL (Bit 3) */ +#define GPIO_PADREGL_PAD44FNCSEL_Msk (0x38UL) /*!< PAD44FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGL_PAD44STRNG_Pos (2UL) /*!< PAD44STRNG (Bit 2) */ +#define GPIO_PADREGL_PAD44STRNG_Msk (0x4UL) /*!< PAD44STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44INPEN_Pos (1UL) /*!< PAD44INPEN (Bit 1) */ +#define GPIO_PADREGL_PAD44INPEN_Msk (0x2UL) /*!< PAD44INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGL_PAD44PULL_Pos (0UL) /*!< PAD44PULL (Bit 0) */ +#define GPIO_PADREGL_PAD44PULL_Msk (0x1UL) /*!< PAD44PULL (Bitfield-Mask: 0x01) */ +/* ======================================================== PADREGM ======================================================== */ +#define GPIO_PADREGM_PAD49RSEL_Pos (14UL) /*!< PAD49RSEL (Bit 14) */ +#define GPIO_PADREGM_PAD49RSEL_Msk (0xc000UL) /*!< PAD49RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGM_PAD49FNCSEL_Pos (11UL) /*!< PAD49FNCSEL (Bit 11) */ +#define GPIO_PADREGM_PAD49FNCSEL_Msk (0x3800UL) /*!< PAD49FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGM_PAD49STRNG_Pos (10UL) /*!< PAD49STRNG (Bit 10) */ +#define GPIO_PADREGM_PAD49STRNG_Msk (0x400UL) /*!< PAD49STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD49INPEN_Pos (9UL) /*!< PAD49INPEN (Bit 9) */ +#define GPIO_PADREGM_PAD49INPEN_Msk (0x200UL) /*!< PAD49INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD49PULL_Pos (8UL) /*!< PAD49PULL (Bit 8) */ +#define GPIO_PADREGM_PAD49PULL_Msk (0x100UL) /*!< PAD49PULL (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48RSEL_Pos (6UL) /*!< PAD48RSEL (Bit 6) */ +#define GPIO_PADREGM_PAD48RSEL_Msk (0xc0UL) /*!< PAD48RSEL (Bitfield-Mask: 0x03) */ +#define GPIO_PADREGM_PAD48FNCSEL_Pos (3UL) /*!< PAD48FNCSEL (Bit 3) */ +#define GPIO_PADREGM_PAD48FNCSEL_Msk (0x38UL) /*!< PAD48FNCSEL (Bitfield-Mask: 0x07) */ +#define GPIO_PADREGM_PAD48STRNG_Pos (2UL) /*!< PAD48STRNG (Bit 2) */ +#define GPIO_PADREGM_PAD48STRNG_Msk (0x4UL) /*!< PAD48STRNG (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48INPEN_Pos (1UL) /*!< PAD48INPEN (Bit 1) */ +#define GPIO_PADREGM_PAD48INPEN_Msk (0x2UL) /*!< PAD48INPEN (Bitfield-Mask: 0x01) */ +#define GPIO_PADREGM_PAD48PULL_Pos (0UL) /*!< PAD48PULL (Bit 0) */ +#define GPIO_PADREGM_PAD48PULL_Msk (0x1UL) /*!< PAD48PULL (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGA ========================================================== */ +#define GPIO_CFGA_GPIO7INTD_Pos (31UL) /*!< GPIO7INTD (Bit 31) */ +#define GPIO_CFGA_GPIO7INTD_Msk (0x80000000UL) /*!< GPIO7INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO7OUTCFG_Pos (29UL) /*!< GPIO7OUTCFG (Bit 29) */ +#define GPIO_CFGA_GPIO7OUTCFG_Msk (0x60000000UL) /*!< GPIO7OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO7INCFG_Pos (28UL) /*!< GPIO7INCFG (Bit 28) */ +#define GPIO_CFGA_GPIO7INCFG_Msk (0x10000000UL) /*!< GPIO7INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO6INTD_Pos (27UL) /*!< GPIO6INTD (Bit 27) */ +#define GPIO_CFGA_GPIO6INTD_Msk (0x8000000UL) /*!< GPIO6INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO6OUTCFG_Pos (25UL) /*!< GPIO6OUTCFG (Bit 25) */ +#define GPIO_CFGA_GPIO6OUTCFG_Msk (0x6000000UL) /*!< GPIO6OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO6INCFG_Pos (24UL) /*!< GPIO6INCFG (Bit 24) */ +#define GPIO_CFGA_GPIO6INCFG_Msk (0x1000000UL) /*!< GPIO6INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO5INTD_Pos (23UL) /*!< GPIO5INTD (Bit 23) */ +#define GPIO_CFGA_GPIO5INTD_Msk (0x800000UL) /*!< GPIO5INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO5OUTCFG_Pos (21UL) /*!< GPIO5OUTCFG (Bit 21) */ +#define GPIO_CFGA_GPIO5OUTCFG_Msk (0x600000UL) /*!< GPIO5OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO5INCFG_Pos (20UL) /*!< GPIO5INCFG (Bit 20) */ +#define GPIO_CFGA_GPIO5INCFG_Msk (0x100000UL) /*!< GPIO5INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO4INTD_Pos (19UL) /*!< GPIO4INTD (Bit 19) */ +#define GPIO_CFGA_GPIO4INTD_Msk (0x80000UL) /*!< GPIO4INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO4OUTCFG_Pos (17UL) /*!< GPIO4OUTCFG (Bit 17) */ +#define GPIO_CFGA_GPIO4OUTCFG_Msk (0x60000UL) /*!< GPIO4OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO4INCFG_Pos (16UL) /*!< GPIO4INCFG (Bit 16) */ +#define GPIO_CFGA_GPIO4INCFG_Msk (0x10000UL) /*!< GPIO4INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO3INTD_Pos (15UL) /*!< GPIO3INTD (Bit 15) */ +#define GPIO_CFGA_GPIO3INTD_Msk (0x8000UL) /*!< GPIO3INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO3OUTCFG_Pos (13UL) /*!< GPIO3OUTCFG (Bit 13) */ +#define GPIO_CFGA_GPIO3OUTCFG_Msk (0x6000UL) /*!< GPIO3OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO3INCFG_Pos (12UL) /*!< GPIO3INCFG (Bit 12) */ +#define GPIO_CFGA_GPIO3INCFG_Msk (0x1000UL) /*!< GPIO3INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO2INTD_Pos (11UL) /*!< GPIO2INTD (Bit 11) */ +#define GPIO_CFGA_GPIO2INTD_Msk (0x800UL) /*!< GPIO2INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO2OUTCFG_Pos (9UL) /*!< GPIO2OUTCFG (Bit 9) */ +#define GPIO_CFGA_GPIO2OUTCFG_Msk (0x600UL) /*!< GPIO2OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO2INCFG_Pos (8UL) /*!< GPIO2INCFG (Bit 8) */ +#define GPIO_CFGA_GPIO2INCFG_Msk (0x100UL) /*!< GPIO2INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO1INTD_Pos (7UL) /*!< GPIO1INTD (Bit 7) */ +#define GPIO_CFGA_GPIO1INTD_Msk (0x80UL) /*!< GPIO1INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO1OUTCFG_Pos (5UL) /*!< GPIO1OUTCFG (Bit 5) */ +#define GPIO_CFGA_GPIO1OUTCFG_Msk (0x60UL) /*!< GPIO1OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO1INCFG_Pos (4UL) /*!< GPIO1INCFG (Bit 4) */ +#define GPIO_CFGA_GPIO1INCFG_Msk (0x10UL) /*!< GPIO1INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO0INTD_Pos (3UL) /*!< GPIO0INTD (Bit 3) */ +#define GPIO_CFGA_GPIO0INTD_Msk (0x8UL) /*!< GPIO0INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGA_GPIO0OUTCFG_Pos (1UL) /*!< GPIO0OUTCFG (Bit 1) */ +#define GPIO_CFGA_GPIO0OUTCFG_Msk (0x6UL) /*!< GPIO0OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGA_GPIO0INCFG_Pos (0UL) /*!< GPIO0INCFG (Bit 0) */ +#define GPIO_CFGA_GPIO0INCFG_Msk (0x1UL) /*!< GPIO0INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGB ========================================================== */ +#define GPIO_CFGB_GPIO15INTD_Pos (31UL) /*!< GPIO15INTD (Bit 31) */ +#define GPIO_CFGB_GPIO15INTD_Msk (0x80000000UL) /*!< GPIO15INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO15OUTCFG_Pos (29UL) /*!< GPIO15OUTCFG (Bit 29) */ +#define GPIO_CFGB_GPIO15OUTCFG_Msk (0x60000000UL) /*!< GPIO15OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO15INCFG_Pos (28UL) /*!< GPIO15INCFG (Bit 28) */ +#define GPIO_CFGB_GPIO15INCFG_Msk (0x10000000UL) /*!< GPIO15INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO14INTD_Pos (27UL) /*!< GPIO14INTD (Bit 27) */ +#define GPIO_CFGB_GPIO14INTD_Msk (0x8000000UL) /*!< GPIO14INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO14OUTCFG_Pos (25UL) /*!< GPIO14OUTCFG (Bit 25) */ +#define GPIO_CFGB_GPIO14OUTCFG_Msk (0x6000000UL) /*!< GPIO14OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO14INCFG_Pos (24UL) /*!< GPIO14INCFG (Bit 24) */ +#define GPIO_CFGB_GPIO14INCFG_Msk (0x1000000UL) /*!< GPIO14INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO13INTD_Pos (23UL) /*!< GPIO13INTD (Bit 23) */ +#define GPIO_CFGB_GPIO13INTD_Msk (0x800000UL) /*!< GPIO13INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO13OUTCFG_Pos (21UL) /*!< GPIO13OUTCFG (Bit 21) */ +#define GPIO_CFGB_GPIO13OUTCFG_Msk (0x600000UL) /*!< GPIO13OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO13INCFG_Pos (20UL) /*!< GPIO13INCFG (Bit 20) */ +#define GPIO_CFGB_GPIO13INCFG_Msk (0x100000UL) /*!< GPIO13INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO12INTD_Pos (19UL) /*!< GPIO12INTD (Bit 19) */ +#define GPIO_CFGB_GPIO12INTD_Msk (0x80000UL) /*!< GPIO12INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO12OUTCFG_Pos (17UL) /*!< GPIO12OUTCFG (Bit 17) */ +#define GPIO_CFGB_GPIO12OUTCFG_Msk (0x60000UL) /*!< GPIO12OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO12INCFG_Pos (16UL) /*!< GPIO12INCFG (Bit 16) */ +#define GPIO_CFGB_GPIO12INCFG_Msk (0x10000UL) /*!< GPIO12INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO11INTD_Pos (15UL) /*!< GPIO11INTD (Bit 15) */ +#define GPIO_CFGB_GPIO11INTD_Msk (0x8000UL) /*!< GPIO11INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO11OUTCFG_Pos (13UL) /*!< GPIO11OUTCFG (Bit 13) */ +#define GPIO_CFGB_GPIO11OUTCFG_Msk (0x6000UL) /*!< GPIO11OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO11INCFG_Pos (12UL) /*!< GPIO11INCFG (Bit 12) */ +#define GPIO_CFGB_GPIO11INCFG_Msk (0x1000UL) /*!< GPIO11INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO10INTD_Pos (11UL) /*!< GPIO10INTD (Bit 11) */ +#define GPIO_CFGB_GPIO10INTD_Msk (0x800UL) /*!< GPIO10INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO10OUTCFG_Pos (9UL) /*!< GPIO10OUTCFG (Bit 9) */ +#define GPIO_CFGB_GPIO10OUTCFG_Msk (0x600UL) /*!< GPIO10OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO10INCFG_Pos (8UL) /*!< GPIO10INCFG (Bit 8) */ +#define GPIO_CFGB_GPIO10INCFG_Msk (0x100UL) /*!< GPIO10INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO9INTD_Pos (7UL) /*!< GPIO9INTD (Bit 7) */ +#define GPIO_CFGB_GPIO9INTD_Msk (0x80UL) /*!< GPIO9INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO9OUTCFG_Pos (5UL) /*!< GPIO9OUTCFG (Bit 5) */ +#define GPIO_CFGB_GPIO9OUTCFG_Msk (0x60UL) /*!< GPIO9OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO9INCFG_Pos (4UL) /*!< GPIO9INCFG (Bit 4) */ +#define GPIO_CFGB_GPIO9INCFG_Msk (0x10UL) /*!< GPIO9INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO8INTD_Pos (3UL) /*!< GPIO8INTD (Bit 3) */ +#define GPIO_CFGB_GPIO8INTD_Msk (0x8UL) /*!< GPIO8INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGB_GPIO8OUTCFG_Pos (1UL) /*!< GPIO8OUTCFG (Bit 1) */ +#define GPIO_CFGB_GPIO8OUTCFG_Msk (0x6UL) /*!< GPIO8OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGB_GPIO8INCFG_Pos (0UL) /*!< GPIO8INCFG (Bit 0) */ +#define GPIO_CFGB_GPIO8INCFG_Msk (0x1UL) /*!< GPIO8INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGC ========================================================== */ +#define GPIO_CFGC_GPIO23INTD_Pos (31UL) /*!< GPIO23INTD (Bit 31) */ +#define GPIO_CFGC_GPIO23INTD_Msk (0x80000000UL) /*!< GPIO23INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO23OUTCFG_Pos (29UL) /*!< GPIO23OUTCFG (Bit 29) */ +#define GPIO_CFGC_GPIO23OUTCFG_Msk (0x60000000UL) /*!< GPIO23OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO23INCFG_Pos (28UL) /*!< GPIO23INCFG (Bit 28) */ +#define GPIO_CFGC_GPIO23INCFG_Msk (0x10000000UL) /*!< GPIO23INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO22INTD_Pos (27UL) /*!< GPIO22INTD (Bit 27) */ +#define GPIO_CFGC_GPIO22INTD_Msk (0x8000000UL) /*!< GPIO22INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO22OUTCFG_Pos (25UL) /*!< GPIO22OUTCFG (Bit 25) */ +#define GPIO_CFGC_GPIO22OUTCFG_Msk (0x6000000UL) /*!< GPIO22OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO22INCFG_Pos (24UL) /*!< GPIO22INCFG (Bit 24) */ +#define GPIO_CFGC_GPIO22INCFG_Msk (0x1000000UL) /*!< GPIO22INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO21INTD_Pos (23UL) /*!< GPIO21INTD (Bit 23) */ +#define GPIO_CFGC_GPIO21INTD_Msk (0x800000UL) /*!< GPIO21INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO21OUTCFG_Pos (21UL) /*!< GPIO21OUTCFG (Bit 21) */ +#define GPIO_CFGC_GPIO21OUTCFG_Msk (0x600000UL) /*!< GPIO21OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO21INCFG_Pos (20UL) /*!< GPIO21INCFG (Bit 20) */ +#define GPIO_CFGC_GPIO21INCFG_Msk (0x100000UL) /*!< GPIO21INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO20INTD_Pos (19UL) /*!< GPIO20INTD (Bit 19) */ +#define GPIO_CFGC_GPIO20INTD_Msk (0x80000UL) /*!< GPIO20INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO20OUTCFG_Pos (17UL) /*!< GPIO20OUTCFG (Bit 17) */ +#define GPIO_CFGC_GPIO20OUTCFG_Msk (0x60000UL) /*!< GPIO20OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO20INCFG_Pos (16UL) /*!< GPIO20INCFG (Bit 16) */ +#define GPIO_CFGC_GPIO20INCFG_Msk (0x10000UL) /*!< GPIO20INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO19INTD_Pos (15UL) /*!< GPIO19INTD (Bit 15) */ +#define GPIO_CFGC_GPIO19INTD_Msk (0x8000UL) /*!< GPIO19INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO19OUTCFG_Pos (13UL) /*!< GPIO19OUTCFG (Bit 13) */ +#define GPIO_CFGC_GPIO19OUTCFG_Msk (0x6000UL) /*!< GPIO19OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO19INCFG_Pos (12UL) /*!< GPIO19INCFG (Bit 12) */ +#define GPIO_CFGC_GPIO19INCFG_Msk (0x1000UL) /*!< GPIO19INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO18INTD_Pos (11UL) /*!< GPIO18INTD (Bit 11) */ +#define GPIO_CFGC_GPIO18INTD_Msk (0x800UL) /*!< GPIO18INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO18OUTCFG_Pos (9UL) /*!< GPIO18OUTCFG (Bit 9) */ +#define GPIO_CFGC_GPIO18OUTCFG_Msk (0x600UL) /*!< GPIO18OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO18INCFG_Pos (8UL) /*!< GPIO18INCFG (Bit 8) */ +#define GPIO_CFGC_GPIO18INCFG_Msk (0x100UL) /*!< GPIO18INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO17INTD_Pos (7UL) /*!< GPIO17INTD (Bit 7) */ +#define GPIO_CFGC_GPIO17INTD_Msk (0x80UL) /*!< GPIO17INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO17OUTCFG_Pos (5UL) /*!< GPIO17OUTCFG (Bit 5) */ +#define GPIO_CFGC_GPIO17OUTCFG_Msk (0x60UL) /*!< GPIO17OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO17INCFG_Pos (4UL) /*!< GPIO17INCFG (Bit 4) */ +#define GPIO_CFGC_GPIO17INCFG_Msk (0x10UL) /*!< GPIO17INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO16INTD_Pos (3UL) /*!< GPIO16INTD (Bit 3) */ +#define GPIO_CFGC_GPIO16INTD_Msk (0x8UL) /*!< GPIO16INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGC_GPIO16OUTCFG_Pos (1UL) /*!< GPIO16OUTCFG (Bit 1) */ +#define GPIO_CFGC_GPIO16OUTCFG_Msk (0x6UL) /*!< GPIO16OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGC_GPIO16INCFG_Pos (0UL) /*!< GPIO16INCFG (Bit 0) */ +#define GPIO_CFGC_GPIO16INCFG_Msk (0x1UL) /*!< GPIO16INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGD ========================================================== */ +#define GPIO_CFGD_GPIO31INTD_Pos (31UL) /*!< GPIO31INTD (Bit 31) */ +#define GPIO_CFGD_GPIO31INTD_Msk (0x80000000UL) /*!< GPIO31INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO31OUTCFG_Pos (29UL) /*!< GPIO31OUTCFG (Bit 29) */ +#define GPIO_CFGD_GPIO31OUTCFG_Msk (0x60000000UL) /*!< GPIO31OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO31INCFG_Pos (28UL) /*!< GPIO31INCFG (Bit 28) */ +#define GPIO_CFGD_GPIO31INCFG_Msk (0x10000000UL) /*!< GPIO31INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO30INTD_Pos (27UL) /*!< GPIO30INTD (Bit 27) */ +#define GPIO_CFGD_GPIO30INTD_Msk (0x8000000UL) /*!< GPIO30INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO30OUTCFG_Pos (25UL) /*!< GPIO30OUTCFG (Bit 25) */ +#define GPIO_CFGD_GPIO30OUTCFG_Msk (0x6000000UL) /*!< GPIO30OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO30INCFG_Pos (24UL) /*!< GPIO30INCFG (Bit 24) */ +#define GPIO_CFGD_GPIO30INCFG_Msk (0x1000000UL) /*!< GPIO30INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO29INTD_Pos (23UL) /*!< GPIO29INTD (Bit 23) */ +#define GPIO_CFGD_GPIO29INTD_Msk (0x800000UL) /*!< GPIO29INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO29OUTCFG_Pos (21UL) /*!< GPIO29OUTCFG (Bit 21) */ +#define GPIO_CFGD_GPIO29OUTCFG_Msk (0x600000UL) /*!< GPIO29OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO29INCFG_Pos (20UL) /*!< GPIO29INCFG (Bit 20) */ +#define GPIO_CFGD_GPIO29INCFG_Msk (0x100000UL) /*!< GPIO29INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO28INTD_Pos (19UL) /*!< GPIO28INTD (Bit 19) */ +#define GPIO_CFGD_GPIO28INTD_Msk (0x80000UL) /*!< GPIO28INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO28OUTCFG_Pos (17UL) /*!< GPIO28OUTCFG (Bit 17) */ +#define GPIO_CFGD_GPIO28OUTCFG_Msk (0x60000UL) /*!< GPIO28OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO28INCFG_Pos (16UL) /*!< GPIO28INCFG (Bit 16) */ +#define GPIO_CFGD_GPIO28INCFG_Msk (0x10000UL) /*!< GPIO28INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO27INTD_Pos (15UL) /*!< GPIO27INTD (Bit 15) */ +#define GPIO_CFGD_GPIO27INTD_Msk (0x8000UL) /*!< GPIO27INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO27OUTCFG_Pos (13UL) /*!< GPIO27OUTCFG (Bit 13) */ +#define GPIO_CFGD_GPIO27OUTCFG_Msk (0x6000UL) /*!< GPIO27OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO27INCFG_Pos (12UL) /*!< GPIO27INCFG (Bit 12) */ +#define GPIO_CFGD_GPIO27INCFG_Msk (0x1000UL) /*!< GPIO27INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO26INTD_Pos (11UL) /*!< GPIO26INTD (Bit 11) */ +#define GPIO_CFGD_GPIO26INTD_Msk (0x800UL) /*!< GPIO26INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO26OUTCFG_Pos (9UL) /*!< GPIO26OUTCFG (Bit 9) */ +#define GPIO_CFGD_GPIO26OUTCFG_Msk (0x600UL) /*!< GPIO26OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO26INCFG_Pos (8UL) /*!< GPIO26INCFG (Bit 8) */ +#define GPIO_CFGD_GPIO26INCFG_Msk (0x100UL) /*!< GPIO26INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO25INTD_Pos (7UL) /*!< GPIO25INTD (Bit 7) */ +#define GPIO_CFGD_GPIO25INTD_Msk (0x80UL) /*!< GPIO25INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO25OUTCFG_Pos (5UL) /*!< GPIO25OUTCFG (Bit 5) */ +#define GPIO_CFGD_GPIO25OUTCFG_Msk (0x60UL) /*!< GPIO25OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO25INCFG_Pos (4UL) /*!< GPIO25INCFG (Bit 4) */ +#define GPIO_CFGD_GPIO25INCFG_Msk (0x10UL) /*!< GPIO25INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO24INTD_Pos (3UL) /*!< GPIO24INTD (Bit 3) */ +#define GPIO_CFGD_GPIO24INTD_Msk (0x8UL) /*!< GPIO24INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGD_GPIO24OUTCFG_Pos (1UL) /*!< GPIO24OUTCFG (Bit 1) */ +#define GPIO_CFGD_GPIO24OUTCFG_Msk (0x6UL) /*!< GPIO24OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGD_GPIO24INCFG_Pos (0UL) /*!< GPIO24INCFG (Bit 0) */ +#define GPIO_CFGD_GPIO24INCFG_Msk (0x1UL) /*!< GPIO24INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGE ========================================================== */ +#define GPIO_CFGE_GPIO39INTD_Pos (31UL) /*!< GPIO39INTD (Bit 31) */ +#define GPIO_CFGE_GPIO39INTD_Msk (0x80000000UL) /*!< GPIO39INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO39OUTCFG_Pos (29UL) /*!< GPIO39OUTCFG (Bit 29) */ +#define GPIO_CFGE_GPIO39OUTCFG_Msk (0x60000000UL) /*!< GPIO39OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO39INCFG_Pos (28UL) /*!< GPIO39INCFG (Bit 28) */ +#define GPIO_CFGE_GPIO39INCFG_Msk (0x10000000UL) /*!< GPIO39INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO38INTD_Pos (27UL) /*!< GPIO38INTD (Bit 27) */ +#define GPIO_CFGE_GPIO38INTD_Msk (0x8000000UL) /*!< GPIO38INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO38OUTCFG_Pos (25UL) /*!< GPIO38OUTCFG (Bit 25) */ +#define GPIO_CFGE_GPIO38OUTCFG_Msk (0x6000000UL) /*!< GPIO38OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO38INCFG_Pos (24UL) /*!< GPIO38INCFG (Bit 24) */ +#define GPIO_CFGE_GPIO38INCFG_Msk (0x1000000UL) /*!< GPIO38INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO37INTD_Pos (23UL) /*!< GPIO37INTD (Bit 23) */ +#define GPIO_CFGE_GPIO37INTD_Msk (0x800000UL) /*!< GPIO37INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO37OUTCFG_Pos (21UL) /*!< GPIO37OUTCFG (Bit 21) */ +#define GPIO_CFGE_GPIO37OUTCFG_Msk (0x600000UL) /*!< GPIO37OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO37INCFG_Pos (20UL) /*!< GPIO37INCFG (Bit 20) */ +#define GPIO_CFGE_GPIO37INCFG_Msk (0x100000UL) /*!< GPIO37INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO36INTD_Pos (19UL) /*!< GPIO36INTD (Bit 19) */ +#define GPIO_CFGE_GPIO36INTD_Msk (0x80000UL) /*!< GPIO36INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO36OUTCFG_Pos (17UL) /*!< GPIO36OUTCFG (Bit 17) */ +#define GPIO_CFGE_GPIO36OUTCFG_Msk (0x60000UL) /*!< GPIO36OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO36INCFG_Pos (16UL) /*!< GPIO36INCFG (Bit 16) */ +#define GPIO_CFGE_GPIO36INCFG_Msk (0x10000UL) /*!< GPIO36INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO35INTD_Pos (15UL) /*!< GPIO35INTD (Bit 15) */ +#define GPIO_CFGE_GPIO35INTD_Msk (0x8000UL) /*!< GPIO35INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO35OUTCFG_Pos (13UL) /*!< GPIO35OUTCFG (Bit 13) */ +#define GPIO_CFGE_GPIO35OUTCFG_Msk (0x6000UL) /*!< GPIO35OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO35INCFG_Pos (12UL) /*!< GPIO35INCFG (Bit 12) */ +#define GPIO_CFGE_GPIO35INCFG_Msk (0x1000UL) /*!< GPIO35INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO34INTD_Pos (11UL) /*!< GPIO34INTD (Bit 11) */ +#define GPIO_CFGE_GPIO34INTD_Msk (0x800UL) /*!< GPIO34INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO34OUTCFG_Pos (9UL) /*!< GPIO34OUTCFG (Bit 9) */ +#define GPIO_CFGE_GPIO34OUTCFG_Msk (0x600UL) /*!< GPIO34OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO34INCFG_Pos (8UL) /*!< GPIO34INCFG (Bit 8) */ +#define GPIO_CFGE_GPIO34INCFG_Msk (0x100UL) /*!< GPIO34INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO33INTD_Pos (7UL) /*!< GPIO33INTD (Bit 7) */ +#define GPIO_CFGE_GPIO33INTD_Msk (0x80UL) /*!< GPIO33INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO33OUTCFG_Pos (5UL) /*!< GPIO33OUTCFG (Bit 5) */ +#define GPIO_CFGE_GPIO33OUTCFG_Msk (0x60UL) /*!< GPIO33OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO33INCFG_Pos (4UL) /*!< GPIO33INCFG (Bit 4) */ +#define GPIO_CFGE_GPIO33INCFG_Msk (0x10UL) /*!< GPIO33INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO32INTD_Pos (3UL) /*!< GPIO32INTD (Bit 3) */ +#define GPIO_CFGE_GPIO32INTD_Msk (0x8UL) /*!< GPIO32INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGE_GPIO32OUTCFG_Pos (1UL) /*!< GPIO32OUTCFG (Bit 1) */ +#define GPIO_CFGE_GPIO32OUTCFG_Msk (0x6UL) /*!< GPIO32OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGE_GPIO32INCFG_Pos (0UL) /*!< GPIO32INCFG (Bit 0) */ +#define GPIO_CFGE_GPIO32INCFG_Msk (0x1UL) /*!< GPIO32INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGF ========================================================== */ +#define GPIO_CFGF_GPIO47INTD_Pos (31UL) /*!< GPIO47INTD (Bit 31) */ +#define GPIO_CFGF_GPIO47INTD_Msk (0x80000000UL) /*!< GPIO47INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO47OUTCFG_Pos (29UL) /*!< GPIO47OUTCFG (Bit 29) */ +#define GPIO_CFGF_GPIO47OUTCFG_Msk (0x60000000UL) /*!< GPIO47OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO47INCFG_Pos (28UL) /*!< GPIO47INCFG (Bit 28) */ +#define GPIO_CFGF_GPIO47INCFG_Msk (0x10000000UL) /*!< GPIO47INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO46INTD_Pos (27UL) /*!< GPIO46INTD (Bit 27) */ +#define GPIO_CFGF_GPIO46INTD_Msk (0x8000000UL) /*!< GPIO46INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO46OUTCFG_Pos (25UL) /*!< GPIO46OUTCFG (Bit 25) */ +#define GPIO_CFGF_GPIO46OUTCFG_Msk (0x6000000UL) /*!< GPIO46OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO46INCFG_Pos (24UL) /*!< GPIO46INCFG (Bit 24) */ +#define GPIO_CFGF_GPIO46INCFG_Msk (0x1000000UL) /*!< GPIO46INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO45INTD_Pos (23UL) /*!< GPIO45INTD (Bit 23) */ +#define GPIO_CFGF_GPIO45INTD_Msk (0x800000UL) /*!< GPIO45INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO45OUTCFG_Pos (21UL) /*!< GPIO45OUTCFG (Bit 21) */ +#define GPIO_CFGF_GPIO45OUTCFG_Msk (0x600000UL) /*!< GPIO45OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO45INCFG_Pos (20UL) /*!< GPIO45INCFG (Bit 20) */ +#define GPIO_CFGF_GPIO45INCFG_Msk (0x100000UL) /*!< GPIO45INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO44INTD_Pos (19UL) /*!< GPIO44INTD (Bit 19) */ +#define GPIO_CFGF_GPIO44INTD_Msk (0x80000UL) /*!< GPIO44INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO44OUTCFG_Pos (17UL) /*!< GPIO44OUTCFG (Bit 17) */ +#define GPIO_CFGF_GPIO44OUTCFG_Msk (0x60000UL) /*!< GPIO44OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO44INCFG_Pos (16UL) /*!< GPIO44INCFG (Bit 16) */ +#define GPIO_CFGF_GPIO44INCFG_Msk (0x10000UL) /*!< GPIO44INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO43INTD_Pos (15UL) /*!< GPIO43INTD (Bit 15) */ +#define GPIO_CFGF_GPIO43INTD_Msk (0x8000UL) /*!< GPIO43INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO43OUTCFG_Pos (13UL) /*!< GPIO43OUTCFG (Bit 13) */ +#define GPIO_CFGF_GPIO43OUTCFG_Msk (0x6000UL) /*!< GPIO43OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO43INCFG_Pos (12UL) /*!< GPIO43INCFG (Bit 12) */ +#define GPIO_CFGF_GPIO43INCFG_Msk (0x1000UL) /*!< GPIO43INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO42INTD_Pos (11UL) /*!< GPIO42INTD (Bit 11) */ +#define GPIO_CFGF_GPIO42INTD_Msk (0x800UL) /*!< GPIO42INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO42OUTCFG_Pos (9UL) /*!< GPIO42OUTCFG (Bit 9) */ +#define GPIO_CFGF_GPIO42OUTCFG_Msk (0x600UL) /*!< GPIO42OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO42INCFG_Pos (8UL) /*!< GPIO42INCFG (Bit 8) */ +#define GPIO_CFGF_GPIO42INCFG_Msk (0x100UL) /*!< GPIO42INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO41INTD_Pos (7UL) /*!< GPIO41INTD (Bit 7) */ +#define GPIO_CFGF_GPIO41INTD_Msk (0x80UL) /*!< GPIO41INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO41OUTCFG_Pos (5UL) /*!< GPIO41OUTCFG (Bit 5) */ +#define GPIO_CFGF_GPIO41OUTCFG_Msk (0x60UL) /*!< GPIO41OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO41INCFG_Pos (4UL) /*!< GPIO41INCFG (Bit 4) */ +#define GPIO_CFGF_GPIO41INCFG_Msk (0x10UL) /*!< GPIO41INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO40INTD_Pos (3UL) /*!< GPIO40INTD (Bit 3) */ +#define GPIO_CFGF_GPIO40INTD_Msk (0x8UL) /*!< GPIO40INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGF_GPIO40OUTCFG_Pos (1UL) /*!< GPIO40OUTCFG (Bit 1) */ +#define GPIO_CFGF_GPIO40OUTCFG_Msk (0x6UL) /*!< GPIO40OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGF_GPIO40INCFG_Pos (0UL) /*!< GPIO40INCFG (Bit 0) */ +#define GPIO_CFGF_GPIO40INCFG_Msk (0x1UL) /*!< GPIO40INCFG (Bitfield-Mask: 0x01) */ +/* ========================================================= CFGG ========================================================== */ +#define GPIO_CFGG_GPIO49INTD_Pos (7UL) /*!< GPIO49INTD (Bit 7) */ +#define GPIO_CFGG_GPIO49INTD_Msk (0x80UL) /*!< GPIO49INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO49OUTCFG_Pos (5UL) /*!< GPIO49OUTCFG (Bit 5) */ +#define GPIO_CFGG_GPIO49OUTCFG_Msk (0x60UL) /*!< GPIO49OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGG_GPIO49INCFG_Pos (4UL) /*!< GPIO49INCFG (Bit 4) */ +#define GPIO_CFGG_GPIO49INCFG_Msk (0x10UL) /*!< GPIO49INCFG (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO48INTD_Pos (3UL) /*!< GPIO48INTD (Bit 3) */ +#define GPIO_CFGG_GPIO48INTD_Msk (0x8UL) /*!< GPIO48INTD (Bitfield-Mask: 0x01) */ +#define GPIO_CFGG_GPIO48OUTCFG_Pos (1UL) /*!< GPIO48OUTCFG (Bit 1) */ +#define GPIO_CFGG_GPIO48OUTCFG_Msk (0x6UL) /*!< GPIO48OUTCFG (Bitfield-Mask: 0x03) */ +#define GPIO_CFGG_GPIO48INCFG_Pos (0UL) /*!< GPIO48INCFG (Bit 0) */ +#define GPIO_CFGG_GPIO48INCFG_Msk (0x1UL) /*!< GPIO48INCFG (Bitfield-Mask: 0x01) */ +/* ======================================================== PADKEY ========================================================= */ +#define GPIO_PADKEY_PADKEY_Pos (0UL) /*!< PADKEY (Bit 0) */ +#define GPIO_PADKEY_PADKEY_Msk (0xffffffffUL) /*!< PADKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RDA ========================================================== */ +#define GPIO_RDA_RDA_Pos (0UL) /*!< RDA (Bit 0) */ +#define GPIO_RDA_RDA_Msk (0xffffffffUL) /*!< RDA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RDB ========================================================== */ +#define GPIO_RDB_RDB_Pos (0UL) /*!< RDB (Bit 0) */ +#define GPIO_RDB_RDB_Msk (0x3ffffUL) /*!< RDB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== WTA ========================================================== */ +#define GPIO_WTA_WTA_Pos (0UL) /*!< WTA (Bit 0) */ +#define GPIO_WTA_WTA_Msk (0xffffffffUL) /*!< WTA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== WTB ========================================================== */ +#define GPIO_WTB_WTB_Pos (0UL) /*!< WTB (Bit 0) */ +#define GPIO_WTB_WTB_Msk (0x3ffffUL) /*!< WTB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= WTSA ========================================================== */ +#define GPIO_WTSA_WTSA_Pos (0UL) /*!< WTSA (Bit 0) */ +#define GPIO_WTSA_WTSA_Msk (0xffffffffUL) /*!< WTSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= WTSB ========================================================== */ +#define GPIO_WTSB_WTSB_Pos (0UL) /*!< WTSB (Bit 0) */ +#define GPIO_WTSB_WTSB_Msk (0x3ffffUL) /*!< WTSB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= WTCA ========================================================== */ +#define GPIO_WTCA_WTCA_Pos (0UL) /*!< WTCA (Bit 0) */ +#define GPIO_WTCA_WTCA_Msk (0xffffffffUL) /*!< WTCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= WTCB ========================================================== */ +#define GPIO_WTCB_WTCB_Pos (0UL) /*!< WTCB (Bit 0) */ +#define GPIO_WTCB_WTCB_Msk (0x3ffffUL) /*!< WTCB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== ENA ========================================================== */ +#define GPIO_ENA_ENA_Pos (0UL) /*!< ENA (Bit 0) */ +#define GPIO_ENA_ENA_Msk (0xffffffffUL) /*!< ENA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ENB ========================================================== */ +#define GPIO_ENB_ENB_Pos (0UL) /*!< ENB (Bit 0) */ +#define GPIO_ENB_ENB_Msk (0x3ffffUL) /*!< ENB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= ENSA ========================================================== */ +#define GPIO_ENSA_ENSA_Pos (0UL) /*!< ENSA (Bit 0) */ +#define GPIO_ENSA_ENSA_Msk (0xffffffffUL) /*!< ENSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ENSB ========================================================== */ +#define GPIO_ENSB_ENSB_Pos (0UL) /*!< ENSB (Bit 0) */ +#define GPIO_ENSB_ENSB_Msk (0x3ffffUL) /*!< ENSB (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= ENCA ========================================================== */ +#define GPIO_ENCA_ENCA_Pos (0UL) /*!< ENCA (Bit 0) */ +#define GPIO_ENCA_ENCA_Msk (0xffffffffUL) /*!< ENCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ENCB ========================================================== */ +#define GPIO_ENCB_ENCB_Pos (0UL) /*!< ENCB (Bit 0) */ +#define GPIO_ENCB_ENCB_Msk (0x3ffffUL) /*!< ENCB (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== STMRCAP ======================================================== */ +#define GPIO_STMRCAP_STPOL3_Pos (30UL) /*!< STPOL3 (Bit 30) */ +#define GPIO_STMRCAP_STPOL3_Msk (0x40000000UL) /*!< STPOL3 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL3_Pos (24UL) /*!< STSEL3 (Bit 24) */ +#define GPIO_STMRCAP_STSEL3_Msk (0x3f000000UL) /*!< STSEL3 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL2_Pos (22UL) /*!< STPOL2 (Bit 22) */ +#define GPIO_STMRCAP_STPOL2_Msk (0x400000UL) /*!< STPOL2 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL2_Pos (16UL) /*!< STSEL2 (Bit 16) */ +#define GPIO_STMRCAP_STSEL2_Msk (0x3f0000UL) /*!< STSEL2 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL1_Pos (14UL) /*!< STPOL1 (Bit 14) */ +#define GPIO_STMRCAP_STPOL1_Msk (0x4000UL) /*!< STPOL1 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL1_Pos (8UL) /*!< STSEL1 (Bit 8) */ +#define GPIO_STMRCAP_STSEL1_Msk (0x3f00UL) /*!< STSEL1 (Bitfield-Mask: 0x3f) */ +#define GPIO_STMRCAP_STPOL0_Pos (6UL) /*!< STPOL0 (Bit 6) */ +#define GPIO_STMRCAP_STPOL0_Msk (0x40UL) /*!< STPOL0 (Bitfield-Mask: 0x01) */ +#define GPIO_STMRCAP_STSEL0_Pos (0UL) /*!< STSEL0 (Bit 0) */ +#define GPIO_STMRCAP_STSEL0_Msk (0x3fUL) /*!< STSEL0 (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM0IRQ ======================================================== */ +#define GPIO_IOM0IRQ_IOM0IRQ_Pos (0UL) /*!< IOM0IRQ (Bit 0) */ +#define GPIO_IOM0IRQ_IOM0IRQ_Msk (0x3fUL) /*!< IOM0IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM1IRQ ======================================================== */ +#define GPIO_IOM1IRQ_IOM1IRQ_Pos (0UL) /*!< IOM1IRQ (Bit 0) */ +#define GPIO_IOM1IRQ_IOM1IRQ_Msk (0x3fUL) /*!< IOM1IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM2IRQ ======================================================== */ +#define GPIO_IOM2IRQ_IOM2IRQ_Pos (0UL) /*!< IOM2IRQ (Bit 0) */ +#define GPIO_IOM2IRQ_IOM2IRQ_Msk (0x3fUL) /*!< IOM2IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM3IRQ ======================================================== */ +#define GPIO_IOM3IRQ_IOM3IRQ_Pos (0UL) /*!< IOM3IRQ (Bit 0) */ +#define GPIO_IOM3IRQ_IOM3IRQ_Msk (0x3fUL) /*!< IOM3IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM4IRQ ======================================================== */ +#define GPIO_IOM4IRQ_IOM4IRQ_Pos (0UL) /*!< IOM4IRQ (Bit 0) */ +#define GPIO_IOM4IRQ_IOM4IRQ_Msk (0x3fUL) /*!< IOM4IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== IOM5IRQ ======================================================== */ +#define GPIO_IOM5IRQ_IOM5IRQ_Pos (0UL) /*!< IOM5IRQ (Bit 0) */ +#define GPIO_IOM5IRQ_IOM5IRQ_Msk (0x3fUL) /*!< IOM5IRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================= BLEIFIRQ ======================================================== */ +#define GPIO_BLEIFIRQ_BLEIFIRQ_Pos (0UL) /*!< BLEIFIRQ (Bit 0) */ +#define GPIO_BLEIFIRQ_BLEIFIRQ_Msk (0x3fUL) /*!< BLEIFIRQ (Bitfield-Mask: 0x3f) */ +/* ======================================================== GPIOOBS ======================================================== */ +#define GPIO_GPIOOBS_OBS_DATA_Pos (0UL) /*!< OBS_DATA (Bit 0) */ +#define GPIO_GPIOOBS_OBS_DATA_Msk (0xffffUL) /*!< OBS_DATA (Bitfield-Mask: 0xffff) */ +/* ====================================================== ALTPADCFGA ======================================================= */ +#define GPIO_ALTPADCFGA_PAD3_SR_Pos (28UL) /*!< PAD3_SR (Bit 28) */ +#define GPIO_ALTPADCFGA_PAD3_SR_Msk (0x10000000UL) /*!< PAD3_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD3_DS1_Pos (24UL) /*!< PAD3_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGA_PAD3_DS1_Msk (0x1000000UL) /*!< PAD3_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD2_SR_Pos (20UL) /*!< PAD2_SR (Bit 20) */ +#define GPIO_ALTPADCFGA_PAD2_SR_Msk (0x100000UL) /*!< PAD2_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD2_DS1_Pos (16UL) /*!< PAD2_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGA_PAD2_DS1_Msk (0x10000UL) /*!< PAD2_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD1_SR_Pos (12UL) /*!< PAD1_SR (Bit 12) */ +#define GPIO_ALTPADCFGA_PAD1_SR_Msk (0x1000UL) /*!< PAD1_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD1_DS1_Pos (8UL) /*!< PAD1_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGA_PAD1_DS1_Msk (0x100UL) /*!< PAD1_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD0_SR_Pos (4UL) /*!< PAD0_SR (Bit 4) */ +#define GPIO_ALTPADCFGA_PAD0_SR_Msk (0x10UL) /*!< PAD0_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGA_PAD0_DS1_Pos (0UL) /*!< PAD0_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGA_PAD0_DS1_Msk (0x1UL) /*!< PAD0_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGB ======================================================= */ +#define GPIO_ALTPADCFGB_PAD7_SR_Pos (28UL) /*!< PAD7_SR (Bit 28) */ +#define GPIO_ALTPADCFGB_PAD7_SR_Msk (0x10000000UL) /*!< PAD7_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD7_DS1_Pos (24UL) /*!< PAD7_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGB_PAD7_DS1_Msk (0x1000000UL) /*!< PAD7_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD6_SR_Pos (20UL) /*!< PAD6_SR (Bit 20) */ +#define GPIO_ALTPADCFGB_PAD6_SR_Msk (0x100000UL) /*!< PAD6_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD6_DS1_Pos (16UL) /*!< PAD6_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGB_PAD6_DS1_Msk (0x10000UL) /*!< PAD6_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD5_SR_Pos (12UL) /*!< PAD5_SR (Bit 12) */ +#define GPIO_ALTPADCFGB_PAD5_SR_Msk (0x1000UL) /*!< PAD5_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD5_DS1_Pos (8UL) /*!< PAD5_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGB_PAD5_DS1_Msk (0x100UL) /*!< PAD5_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD4_SR_Pos (4UL) /*!< PAD4_SR (Bit 4) */ +#define GPIO_ALTPADCFGB_PAD4_SR_Msk (0x10UL) /*!< PAD4_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGB_PAD4_DS1_Pos (0UL) /*!< PAD4_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGB_PAD4_DS1_Msk (0x1UL) /*!< PAD4_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGC ======================================================= */ +#define GPIO_ALTPADCFGC_PAD11_SR_Pos (28UL) /*!< PAD11_SR (Bit 28) */ +#define GPIO_ALTPADCFGC_PAD11_SR_Msk (0x10000000UL) /*!< PAD11_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD11_DS1_Pos (24UL) /*!< PAD11_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGC_PAD11_DS1_Msk (0x1000000UL) /*!< PAD11_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD10_SR_Pos (20UL) /*!< PAD10_SR (Bit 20) */ +#define GPIO_ALTPADCFGC_PAD10_SR_Msk (0x100000UL) /*!< PAD10_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD10_DS1_Pos (16UL) /*!< PAD10_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGC_PAD10_DS1_Msk (0x10000UL) /*!< PAD10_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD9_SR_Pos (12UL) /*!< PAD9_SR (Bit 12) */ +#define GPIO_ALTPADCFGC_PAD9_SR_Msk (0x1000UL) /*!< PAD9_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD9_DS1_Pos (8UL) /*!< PAD9_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGC_PAD9_DS1_Msk (0x100UL) /*!< PAD9_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD8_SR_Pos (4UL) /*!< PAD8_SR (Bit 4) */ +#define GPIO_ALTPADCFGC_PAD8_SR_Msk (0x10UL) /*!< PAD8_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGC_PAD8_DS1_Pos (0UL) /*!< PAD8_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGC_PAD8_DS1_Msk (0x1UL) /*!< PAD8_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGD ======================================================= */ +#define GPIO_ALTPADCFGD_PAD15_SR_Pos (28UL) /*!< PAD15_SR (Bit 28) */ +#define GPIO_ALTPADCFGD_PAD15_SR_Msk (0x10000000UL) /*!< PAD15_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD15_DS1_Pos (24UL) /*!< PAD15_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGD_PAD15_DS1_Msk (0x1000000UL) /*!< PAD15_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD14_SR_Pos (20UL) /*!< PAD14_SR (Bit 20) */ +#define GPIO_ALTPADCFGD_PAD14_SR_Msk (0x100000UL) /*!< PAD14_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD14_DS1_Pos (16UL) /*!< PAD14_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGD_PAD14_DS1_Msk (0x10000UL) /*!< PAD14_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD13_SR_Pos (12UL) /*!< PAD13_SR (Bit 12) */ +#define GPIO_ALTPADCFGD_PAD13_SR_Msk (0x1000UL) /*!< PAD13_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD13_DS1_Pos (8UL) /*!< PAD13_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGD_PAD13_DS1_Msk (0x100UL) /*!< PAD13_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD12_SR_Pos (4UL) /*!< PAD12_SR (Bit 4) */ +#define GPIO_ALTPADCFGD_PAD12_SR_Msk (0x10UL) /*!< PAD12_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGD_PAD12_DS1_Pos (0UL) /*!< PAD12_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGD_PAD12_DS1_Msk (0x1UL) /*!< PAD12_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGE ======================================================= */ +#define GPIO_ALTPADCFGE_PAD19_SR_Pos (28UL) /*!< PAD19_SR (Bit 28) */ +#define GPIO_ALTPADCFGE_PAD19_SR_Msk (0x10000000UL) /*!< PAD19_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD19_DS1_Pos (24UL) /*!< PAD19_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGE_PAD19_DS1_Msk (0x1000000UL) /*!< PAD19_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD18_SR_Pos (20UL) /*!< PAD18_SR (Bit 20) */ +#define GPIO_ALTPADCFGE_PAD18_SR_Msk (0x100000UL) /*!< PAD18_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD18_DS1_Pos (16UL) /*!< PAD18_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGE_PAD18_DS1_Msk (0x10000UL) /*!< PAD18_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD17_SR_Pos (12UL) /*!< PAD17_SR (Bit 12) */ +#define GPIO_ALTPADCFGE_PAD17_SR_Msk (0x1000UL) /*!< PAD17_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD17_DS1_Pos (8UL) /*!< PAD17_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGE_PAD17_DS1_Msk (0x100UL) /*!< PAD17_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD16_SR_Pos (4UL) /*!< PAD16_SR (Bit 4) */ +#define GPIO_ALTPADCFGE_PAD16_SR_Msk (0x10UL) /*!< PAD16_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGE_PAD16_DS1_Pos (0UL) /*!< PAD16_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGE_PAD16_DS1_Msk (0x1UL) /*!< PAD16_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGF ======================================================= */ +#define GPIO_ALTPADCFGF_PAD23_SR_Pos (28UL) /*!< PAD23_SR (Bit 28) */ +#define GPIO_ALTPADCFGF_PAD23_SR_Msk (0x10000000UL) /*!< PAD23_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD23_DS1_Pos (24UL) /*!< PAD23_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGF_PAD23_DS1_Msk (0x1000000UL) /*!< PAD23_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD22_SR_Pos (20UL) /*!< PAD22_SR (Bit 20) */ +#define GPIO_ALTPADCFGF_PAD22_SR_Msk (0x100000UL) /*!< PAD22_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD22_DS1_Pos (16UL) /*!< PAD22_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGF_PAD22_DS1_Msk (0x10000UL) /*!< PAD22_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD21_SR_Pos (12UL) /*!< PAD21_SR (Bit 12) */ +#define GPIO_ALTPADCFGF_PAD21_SR_Msk (0x1000UL) /*!< PAD21_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD21_DS1_Pos (8UL) /*!< PAD21_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGF_PAD21_DS1_Msk (0x100UL) /*!< PAD21_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD20_SR_Pos (4UL) /*!< PAD20_SR (Bit 4) */ +#define GPIO_ALTPADCFGF_PAD20_SR_Msk (0x10UL) /*!< PAD20_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGF_PAD20_DS1_Pos (0UL) /*!< PAD20_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGF_PAD20_DS1_Msk (0x1UL) /*!< PAD20_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGG ======================================================= */ +#define GPIO_ALTPADCFGG_PAD27_SR_Pos (28UL) /*!< PAD27_SR (Bit 28) */ +#define GPIO_ALTPADCFGG_PAD27_SR_Msk (0x10000000UL) /*!< PAD27_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD27_DS1_Pos (24UL) /*!< PAD27_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGG_PAD27_DS1_Msk (0x1000000UL) /*!< PAD27_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD26_SR_Pos (20UL) /*!< PAD26_SR (Bit 20) */ +#define GPIO_ALTPADCFGG_PAD26_SR_Msk (0x100000UL) /*!< PAD26_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD26_DS1_Pos (16UL) /*!< PAD26_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGG_PAD26_DS1_Msk (0x10000UL) /*!< PAD26_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD25_SR_Pos (12UL) /*!< PAD25_SR (Bit 12) */ +#define GPIO_ALTPADCFGG_PAD25_SR_Msk (0x1000UL) /*!< PAD25_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD25_DS1_Pos (8UL) /*!< PAD25_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGG_PAD25_DS1_Msk (0x100UL) /*!< PAD25_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD24_SR_Pos (4UL) /*!< PAD24_SR (Bit 4) */ +#define GPIO_ALTPADCFGG_PAD24_SR_Msk (0x10UL) /*!< PAD24_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGG_PAD24_DS1_Pos (0UL) /*!< PAD24_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGG_PAD24_DS1_Msk (0x1UL) /*!< PAD24_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGH ======================================================= */ +#define GPIO_ALTPADCFGH_PAD31_SR_Pos (28UL) /*!< PAD31_SR (Bit 28) */ +#define GPIO_ALTPADCFGH_PAD31_SR_Msk (0x10000000UL) /*!< PAD31_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD31_DS1_Pos (24UL) /*!< PAD31_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGH_PAD31_DS1_Msk (0x1000000UL) /*!< PAD31_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD30_SR_Pos (20UL) /*!< PAD30_SR (Bit 20) */ +#define GPIO_ALTPADCFGH_PAD30_SR_Msk (0x100000UL) /*!< PAD30_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD30_DS1_Pos (16UL) /*!< PAD30_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGH_PAD30_DS1_Msk (0x10000UL) /*!< PAD30_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD29_SR_Pos (12UL) /*!< PAD29_SR (Bit 12) */ +#define GPIO_ALTPADCFGH_PAD29_SR_Msk (0x1000UL) /*!< PAD29_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD29_DS1_Pos (8UL) /*!< PAD29_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGH_PAD29_DS1_Msk (0x100UL) /*!< PAD29_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD28_SR_Pos (4UL) /*!< PAD28_SR (Bit 4) */ +#define GPIO_ALTPADCFGH_PAD28_SR_Msk (0x10UL) /*!< PAD28_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGH_PAD28_DS1_Pos (0UL) /*!< PAD28_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGH_PAD28_DS1_Msk (0x1UL) /*!< PAD28_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGI ======================================================= */ +#define GPIO_ALTPADCFGI_PAD35_SR_Pos (28UL) /*!< PAD35_SR (Bit 28) */ +#define GPIO_ALTPADCFGI_PAD35_SR_Msk (0x10000000UL) /*!< PAD35_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD35_DS1_Pos (24UL) /*!< PAD35_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGI_PAD35_DS1_Msk (0x1000000UL) /*!< PAD35_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD34_SR_Pos (20UL) /*!< PAD34_SR (Bit 20) */ +#define GPIO_ALTPADCFGI_PAD34_SR_Msk (0x100000UL) /*!< PAD34_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD34_DS1_Pos (16UL) /*!< PAD34_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGI_PAD34_DS1_Msk (0x10000UL) /*!< PAD34_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD33_SR_Pos (12UL) /*!< PAD33_SR (Bit 12) */ +#define GPIO_ALTPADCFGI_PAD33_SR_Msk (0x1000UL) /*!< PAD33_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD33_DS1_Pos (8UL) /*!< PAD33_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGI_PAD33_DS1_Msk (0x100UL) /*!< PAD33_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD32_SR_Pos (4UL) /*!< PAD32_SR (Bit 4) */ +#define GPIO_ALTPADCFGI_PAD32_SR_Msk (0x10UL) /*!< PAD32_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGI_PAD32_DS1_Pos (0UL) /*!< PAD32_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGI_PAD32_DS1_Msk (0x1UL) /*!< PAD32_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGJ ======================================================= */ +#define GPIO_ALTPADCFGJ_PAD39_SR_Pos (28UL) /*!< PAD39_SR (Bit 28) */ +#define GPIO_ALTPADCFGJ_PAD39_SR_Msk (0x10000000UL) /*!< PAD39_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD39_DS1_Pos (24UL) /*!< PAD39_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGJ_PAD39_DS1_Msk (0x1000000UL) /*!< PAD39_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD38_SR_Pos (20UL) /*!< PAD38_SR (Bit 20) */ +#define GPIO_ALTPADCFGJ_PAD38_SR_Msk (0x100000UL) /*!< PAD38_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD38_DS1_Pos (16UL) /*!< PAD38_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGJ_PAD38_DS1_Msk (0x10000UL) /*!< PAD38_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD37_SR_Pos (12UL) /*!< PAD37_SR (Bit 12) */ +#define GPIO_ALTPADCFGJ_PAD37_SR_Msk (0x1000UL) /*!< PAD37_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD37_DS1_Pos (8UL) /*!< PAD37_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGJ_PAD37_DS1_Msk (0x100UL) /*!< PAD37_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD36_SR_Pos (4UL) /*!< PAD36_SR (Bit 4) */ +#define GPIO_ALTPADCFGJ_PAD36_SR_Msk (0x10UL) /*!< PAD36_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGJ_PAD36_DS1_Pos (0UL) /*!< PAD36_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGJ_PAD36_DS1_Msk (0x1UL) /*!< PAD36_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGK ======================================================= */ +#define GPIO_ALTPADCFGK_PAD43_SR_Pos (28UL) /*!< PAD43_SR (Bit 28) */ +#define GPIO_ALTPADCFGK_PAD43_SR_Msk (0x10000000UL) /*!< PAD43_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD43_DS1_Pos (24UL) /*!< PAD43_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGK_PAD43_DS1_Msk (0x1000000UL) /*!< PAD43_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD42_SR_Pos (20UL) /*!< PAD42_SR (Bit 20) */ +#define GPIO_ALTPADCFGK_PAD42_SR_Msk (0x100000UL) /*!< PAD42_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD42_DS1_Pos (16UL) /*!< PAD42_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGK_PAD42_DS1_Msk (0x10000UL) /*!< PAD42_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD41_SR_Pos (12UL) /*!< PAD41_SR (Bit 12) */ +#define GPIO_ALTPADCFGK_PAD41_SR_Msk (0x1000UL) /*!< PAD41_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD41_DS1_Pos (8UL) /*!< PAD41_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGK_PAD41_DS1_Msk (0x100UL) /*!< PAD41_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD40_SR_Pos (4UL) /*!< PAD40_SR (Bit 4) */ +#define GPIO_ALTPADCFGK_PAD40_SR_Msk (0x10UL) /*!< PAD40_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGK_PAD40_DS1_Pos (0UL) /*!< PAD40_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGK_PAD40_DS1_Msk (0x1UL) /*!< PAD40_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGL ======================================================= */ +#define GPIO_ALTPADCFGL_PAD47_SR_Pos (28UL) /*!< PAD47_SR (Bit 28) */ +#define GPIO_ALTPADCFGL_PAD47_SR_Msk (0x10000000UL) /*!< PAD47_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD47_DS1_Pos (24UL) /*!< PAD47_DS1 (Bit 24) */ +#define GPIO_ALTPADCFGL_PAD47_DS1_Msk (0x1000000UL) /*!< PAD47_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD46_SR_Pos (20UL) /*!< PAD46_SR (Bit 20) */ +#define GPIO_ALTPADCFGL_PAD46_SR_Msk (0x100000UL) /*!< PAD46_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD46_DS1_Pos (16UL) /*!< PAD46_DS1 (Bit 16) */ +#define GPIO_ALTPADCFGL_PAD46_DS1_Msk (0x10000UL) /*!< PAD46_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD45_SR_Pos (12UL) /*!< PAD45_SR (Bit 12) */ +#define GPIO_ALTPADCFGL_PAD45_SR_Msk (0x1000UL) /*!< PAD45_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD45_DS1_Pos (8UL) /*!< PAD45_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGL_PAD45_DS1_Msk (0x100UL) /*!< PAD45_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD44_SR_Pos (4UL) /*!< PAD44_SR (Bit 4) */ +#define GPIO_ALTPADCFGL_PAD44_SR_Msk (0x10UL) /*!< PAD44_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGL_PAD44_DS1_Pos (0UL) /*!< PAD44_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGL_PAD44_DS1_Msk (0x1UL) /*!< PAD44_DS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ALTPADCFGM ======================================================= */ +#define GPIO_ALTPADCFGM_PAD49_SR_Pos (12UL) /*!< PAD49_SR (Bit 12) */ +#define GPIO_ALTPADCFGM_PAD49_SR_Msk (0x1000UL) /*!< PAD49_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD49_DS1_Pos (8UL) /*!< PAD49_DS1 (Bit 8) */ +#define GPIO_ALTPADCFGM_PAD49_DS1_Msk (0x100UL) /*!< PAD49_DS1 (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD48_SR_Pos (4UL) /*!< PAD48_SR (Bit 4) */ +#define GPIO_ALTPADCFGM_PAD48_SR_Msk (0x10UL) /*!< PAD48_SR (Bitfield-Mask: 0x01) */ +#define GPIO_ALTPADCFGM_PAD48_DS1_Pos (0UL) /*!< PAD48_DS1 (Bit 0) */ +#define GPIO_ALTPADCFGM_PAD48_DS1_Msk (0x1UL) /*!< PAD48_DS1 (Bitfield-Mask: 0x01) */ +/* ========================================================= SCDET ========================================================= */ +#define GPIO_SCDET_SCDET_Pos (0UL) /*!< SCDET (Bit 0) */ +#define GPIO_SCDET_SCDET_Msk (0x3fUL) /*!< SCDET (Bitfield-Mask: 0x3f) */ +/* ======================================================== CTENCFG ======================================================== */ +#define GPIO_CTENCFG_EN31_Pos (31UL) /*!< EN31 (Bit 31) */ +#define GPIO_CTENCFG_EN31_Msk (0x80000000UL) /*!< EN31 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN30_Pos (30UL) /*!< EN30 (Bit 30) */ +#define GPIO_CTENCFG_EN30_Msk (0x40000000UL) /*!< EN30 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN29_Pos (29UL) /*!< EN29 (Bit 29) */ +#define GPIO_CTENCFG_EN29_Msk (0x20000000UL) /*!< EN29 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN28_Pos (28UL) /*!< EN28 (Bit 28) */ +#define GPIO_CTENCFG_EN28_Msk (0x10000000UL) /*!< EN28 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN27_Pos (27UL) /*!< EN27 (Bit 27) */ +#define GPIO_CTENCFG_EN27_Msk (0x8000000UL) /*!< EN27 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN26_Pos (26UL) /*!< EN26 (Bit 26) */ +#define GPIO_CTENCFG_EN26_Msk (0x4000000UL) /*!< EN26 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN25_Pos (25UL) /*!< EN25 (Bit 25) */ +#define GPIO_CTENCFG_EN25_Msk (0x2000000UL) /*!< EN25 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN24_Pos (24UL) /*!< EN24 (Bit 24) */ +#define GPIO_CTENCFG_EN24_Msk (0x1000000UL) /*!< EN24 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN23_Pos (23UL) /*!< EN23 (Bit 23) */ +#define GPIO_CTENCFG_EN23_Msk (0x800000UL) /*!< EN23 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN22_Pos (22UL) /*!< EN22 (Bit 22) */ +#define GPIO_CTENCFG_EN22_Msk (0x400000UL) /*!< EN22 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN21_Pos (21UL) /*!< EN21 (Bit 21) */ +#define GPIO_CTENCFG_EN21_Msk (0x200000UL) /*!< EN21 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN20_Pos (20UL) /*!< EN20 (Bit 20) */ +#define GPIO_CTENCFG_EN20_Msk (0x100000UL) /*!< EN20 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN19_Pos (19UL) /*!< EN19 (Bit 19) */ +#define GPIO_CTENCFG_EN19_Msk (0x80000UL) /*!< EN19 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN18_Pos (18UL) /*!< EN18 (Bit 18) */ +#define GPIO_CTENCFG_EN18_Msk (0x40000UL) /*!< EN18 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN17_Pos (17UL) /*!< EN17 (Bit 17) */ +#define GPIO_CTENCFG_EN17_Msk (0x20000UL) /*!< EN17 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN16_Pos (16UL) /*!< EN16 (Bit 16) */ +#define GPIO_CTENCFG_EN16_Msk (0x10000UL) /*!< EN16 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN15_Pos (15UL) /*!< EN15 (Bit 15) */ +#define GPIO_CTENCFG_EN15_Msk (0x8000UL) /*!< EN15 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN14_Pos (14UL) /*!< EN14 (Bit 14) */ +#define GPIO_CTENCFG_EN14_Msk (0x4000UL) /*!< EN14 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN13_Pos (13UL) /*!< EN13 (Bit 13) */ +#define GPIO_CTENCFG_EN13_Msk (0x2000UL) /*!< EN13 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN12_Pos (12UL) /*!< EN12 (Bit 12) */ +#define GPIO_CTENCFG_EN12_Msk (0x1000UL) /*!< EN12 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN11_Pos (11UL) /*!< EN11 (Bit 11) */ +#define GPIO_CTENCFG_EN11_Msk (0x800UL) /*!< EN11 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN10_Pos (10UL) /*!< EN10 (Bit 10) */ +#define GPIO_CTENCFG_EN10_Msk (0x400UL) /*!< EN10 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN9_Pos (9UL) /*!< EN9 (Bit 9) */ +#define GPIO_CTENCFG_EN9_Msk (0x200UL) /*!< EN9 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN8_Pos (8UL) /*!< EN8 (Bit 8) */ +#define GPIO_CTENCFG_EN8_Msk (0x100UL) /*!< EN8 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN7_Pos (7UL) /*!< EN7 (Bit 7) */ +#define GPIO_CTENCFG_EN7_Msk (0x80UL) /*!< EN7 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN6_Pos (6UL) /*!< EN6 (Bit 6) */ +#define GPIO_CTENCFG_EN6_Msk (0x40UL) /*!< EN6 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN5_Pos (5UL) /*!< EN5 (Bit 5) */ +#define GPIO_CTENCFG_EN5_Msk (0x20UL) /*!< EN5 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN4_Pos (4UL) /*!< EN4 (Bit 4) */ +#define GPIO_CTENCFG_EN4_Msk (0x10UL) /*!< EN4 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN3_Pos (3UL) /*!< EN3 (Bit 3) */ +#define GPIO_CTENCFG_EN3_Msk (0x8UL) /*!< EN3 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN2_Pos (2UL) /*!< EN2 (Bit 2) */ +#define GPIO_CTENCFG_EN2_Msk (0x4UL) /*!< EN2 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ +#define GPIO_CTENCFG_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ +#define GPIO_CTENCFG_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ +#define GPIO_CTENCFG_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0EN ========================================================= */ +#define GPIO_INT0EN_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0EN_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0EN_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0EN_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0EN_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0EN_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0EN_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0EN_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0EN_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0EN_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0EN_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0EN_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0EN_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0EN_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0EN_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0EN_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0EN_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0EN_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0EN_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0EN_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0EN_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0EN_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0EN_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0EN_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0EN_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0EN_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0EN_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0EN_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0EN_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0EN_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0EN_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0EN_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0EN_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0EN_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================= INT0STAT ======================================================== */ +#define GPIO_INT0STAT_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0STAT_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0STAT_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0STAT_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0STAT_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0STAT_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0STAT_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0STAT_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0STAT_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0STAT_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0STAT_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0STAT_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0STAT_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0STAT_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0STAT_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0STAT_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0STAT_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0STAT_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0STAT_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0STAT_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0STAT_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0STAT_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0STAT_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0STAT_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0STAT_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0STAT_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0STAT_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0STAT_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0STAT_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0STAT_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0STAT_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0STAT_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0STAT_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0STAT_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0CLR ======================================================== */ +#define GPIO_INT0CLR_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0CLR_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0CLR_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0CLR_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0CLR_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0CLR_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0CLR_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0CLR_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0CLR_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0CLR_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0CLR_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0CLR_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0CLR_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0CLR_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0CLR_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0CLR_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0CLR_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0CLR_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0CLR_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0CLR_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0CLR_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0CLR_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0CLR_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0CLR_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0CLR_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0CLR_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0CLR_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0CLR_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0CLR_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0CLR_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0CLR_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0CLR_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0CLR_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0CLR_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT0SET ======================================================== */ +#define GPIO_INT0SET_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */ +#define GPIO_INT0SET_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */ +#define GPIO_INT0SET_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */ +#define GPIO_INT0SET_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */ +#define GPIO_INT0SET_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */ +#define GPIO_INT0SET_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */ +#define GPIO_INT0SET_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */ +#define GPIO_INT0SET_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */ +#define GPIO_INT0SET_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */ +#define GPIO_INT0SET_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */ +#define GPIO_INT0SET_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */ +#define GPIO_INT0SET_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */ +#define GPIO_INT0SET_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */ +#define GPIO_INT0SET_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */ +#define GPIO_INT0SET_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */ +#define GPIO_INT0SET_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */ +#define GPIO_INT0SET_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */ +#define GPIO_INT0SET_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */ +#define GPIO_INT0SET_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */ +#define GPIO_INT0SET_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */ +#define GPIO_INT0SET_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */ +#define GPIO_INT0SET_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */ +#define GPIO_INT0SET_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */ +#define GPIO_INT0SET_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */ +#define GPIO_INT0SET_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */ +#define GPIO_INT0SET_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */ +#define GPIO_INT0SET_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */ +#define GPIO_INT0SET_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */ +#define GPIO_INT0SET_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */ +#define GPIO_INT0SET_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */ +#define GPIO_INT0SET_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */ +#define GPIO_INT0SET_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */ +#define GPIO_INT0SET_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */ +#define GPIO_INT0SET_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1EN ========================================================= */ +#define GPIO_INT1EN_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1EN_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1EN_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1EN_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1EN_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1EN_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1EN_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1EN_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1EN_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1EN_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1EN_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1EN_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1EN_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1EN_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1EN_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1EN_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1EN_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1EN_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1EN_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1EN_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================= INT1STAT ======================================================== */ +#define GPIO_INT1STAT_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1STAT_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1STAT_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1STAT_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1STAT_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1STAT_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1STAT_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1STAT_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1STAT_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1STAT_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1STAT_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1STAT_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1STAT_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1STAT_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1STAT_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1STAT_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1STAT_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1STAT_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1STAT_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1STAT_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1CLR ======================================================== */ +#define GPIO_INT1CLR_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1CLR_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1CLR_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1CLR_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1CLR_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1CLR_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1CLR_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1CLR_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1CLR_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1CLR_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1CLR_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1CLR_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1CLR_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1CLR_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1CLR_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1CLR_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1CLR_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1CLR_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1CLR_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1CLR_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ +/* ======================================================== INT1SET ======================================================== */ +#define GPIO_INT1SET_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */ +#define GPIO_INT1SET_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */ +#define GPIO_INT1SET_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */ +#define GPIO_INT1SET_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */ +#define GPIO_INT1SET_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */ +#define GPIO_INT1SET_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */ +#define GPIO_INT1SET_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */ +#define GPIO_INT1SET_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */ +#define GPIO_INT1SET_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */ +#define GPIO_INT1SET_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */ +#define GPIO_INT1SET_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */ +#define GPIO_INT1SET_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */ +#define GPIO_INT1SET_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */ +#define GPIO_INT1SET_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */ +#define GPIO_INT1SET_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */ +#define GPIO_INT1SET_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */ +#define GPIO_INT1SET_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */ +#define GPIO_INT1SET_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */ +#define GPIO_INT1SET_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */ +#define GPIO_INT1SET_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IOM0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +#define IOM0_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */ +#define IOM0_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FIFOPTR ======================================================== */ +#define IOM0_FIFOPTR_FIFO1REM_Pos (24UL) /*!< FIFO1REM (Bit 24) */ +#define IOM0_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< FIFO1REM (Bitfield-Mask: 0xff) */ +#define IOM0_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< FIFO1SIZ (Bit 16) */ +#define IOM0_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< FIFO1SIZ (Bitfield-Mask: 0xff) */ +#define IOM0_FIFOPTR_FIFO0REM_Pos (8UL) /*!< FIFO0REM (Bit 8) */ +#define IOM0_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< FIFO0REM (Bitfield-Mask: 0xff) */ +#define IOM0_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< FIFO0SIZ (Bit 0) */ +#define IOM0_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< FIFO0SIZ (Bitfield-Mask: 0xff) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define IOM0_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */ +#define IOM0_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x3f) */ +#define IOM0_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */ +#define IOM0_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< FIFORTHR (Bitfield-Mask: 0x3f) */ +/* ======================================================== FIFOPOP ======================================================== */ +#define IOM0_FIFOPOP_FIFODOUT_Pos (0UL) /*!< FIFODOUT (Bit 0) */ +#define IOM0_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< FIFODOUT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOPUSH ======================================================== */ +#define IOM0_FIFOPUSH_FIFODIN_Pos (0UL) /*!< FIFODIN (Bit 0) */ +#define IOM0_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< FIFODIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOCTRL ======================================================== */ +#define IOM0_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< FIFORSTN (Bit 1) */ +#define IOM0_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< FIFORSTN (Bitfield-Mask: 0x01) */ +#define IOM0_FIFOCTRL_POPWR_Pos (0UL) /*!< POPWR (Bit 0) */ +#define IOM0_FIFOCTRL_POPWR_Msk (0x1UL) /*!< POPWR (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOLOC ======================================================== */ +#define IOM0_FIFOLOC_FIFORPTR_Pos (8UL) /*!< FIFORPTR (Bit 8) */ +#define IOM0_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< FIFORPTR (Bitfield-Mask: 0x0f) */ +#define IOM0_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< FIFOWPTR (Bit 0) */ +#define IOM0_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< FIFOWPTR (Bitfield-Mask: 0x0f) */ +/* ========================================================= INTEN ========================================================= */ +#define IOM0_INTEN_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTEN_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTEN_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTEN_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTEN_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTEN_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTEN_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTEN_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTEN_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTEN_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTEN_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTEN_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define IOM0_INTSTAT_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTSTAT_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTSTAT_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTSTAT_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTSTAT_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTSTAT_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTSTAT_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTSTAT_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTSTAT_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTSTAT_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTSTAT_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTSTAT_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define IOM0_INTCLR_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTCLR_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTCLR_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTCLR_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTCLR_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTCLR_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTCLR_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTCLR_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTCLR_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTCLR_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTCLR_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTCLR_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define IOM0_INTSET_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */ +#define IOM0_INTSET_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */ +#define IOM0_INTSET_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */ +#define IOM0_INTSET_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_DERR_Pos (11UL) /*!< DERR (Bit 11) */ +#define IOM0_INTSET_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */ +#define IOM0_INTSET_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_ARB_Pos (9UL) /*!< ARB (Bit 9) */ +#define IOM0_INTSET_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_STOP_Pos (8UL) /*!< STOP (Bit 8) */ +#define IOM0_INTSET_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_START_Pos (7UL) /*!< START (Bit 7) */ +#define IOM0_INTSET_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */ +#define IOM0_INTSET_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_IACC_Pos (5UL) /*!< IACC (Bit 5) */ +#define IOM0_INTSET_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define IOM0_INTSET_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */ +#define IOM0_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOM0_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */ +#define IOM0_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */ +#define IOM0_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define IOM0_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== CLKCFG ========================================================= */ +#define IOM0_CLKCFG_TOTPER_Pos (24UL) /*!< TOTPER (Bit 24) */ +#define IOM0_CLKCFG_TOTPER_Msk (0xff000000UL) /*!< TOTPER (Bitfield-Mask: 0xff) */ +#define IOM0_CLKCFG_LOWPER_Pos (16UL) /*!< LOWPER (Bit 16) */ +#define IOM0_CLKCFG_LOWPER_Msk (0xff0000UL) /*!< LOWPER (Bitfield-Mask: 0xff) */ +#define IOM0_CLKCFG_DIVEN_Pos (12UL) /*!< DIVEN (Bit 12) */ +#define IOM0_CLKCFG_DIVEN_Msk (0x1000UL) /*!< DIVEN (Bitfield-Mask: 0x01) */ +#define IOM0_CLKCFG_DIV3_Pos (11UL) /*!< DIV3 (Bit 11) */ +#define IOM0_CLKCFG_DIV3_Msk (0x800UL) /*!< DIV3 (Bitfield-Mask: 0x01) */ +#define IOM0_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */ +#define IOM0_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */ +#define IOM0_CLKCFG_IOCLKEN_Pos (0UL) /*!< IOCLKEN (Bit 0) */ +#define IOM0_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SUBMODCTRL ======================================================= */ +#define IOM0_SUBMODCTRL_SMOD1TYPE_Pos (5UL) /*!< SMOD1TYPE (Bit 5) */ +#define IOM0_SUBMODCTRL_SMOD1TYPE_Msk (0xe0UL) /*!< SMOD1TYPE (Bitfield-Mask: 0x07) */ +#define IOM0_SUBMODCTRL_SMOD1EN_Pos (4UL) /*!< SMOD1EN (Bit 4) */ +#define IOM0_SUBMODCTRL_SMOD1EN_Msk (0x10UL) /*!< SMOD1EN (Bitfield-Mask: 0x01) */ +#define IOM0_SUBMODCTRL_SMOD0TYPE_Pos (1UL) /*!< SMOD0TYPE (Bit 1) */ +#define IOM0_SUBMODCTRL_SMOD0TYPE_Msk (0xeUL) /*!< SMOD0TYPE (Bitfield-Mask: 0x07) */ +#define IOM0_SUBMODCTRL_SMOD0EN_Pos (0UL) /*!< SMOD0EN (Bit 0) */ +#define IOM0_SUBMODCTRL_SMOD0EN_Msk (0x1UL) /*!< SMOD0EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ +#define IOM0_CMD_OFFSETLO_Pos (24UL) /*!< OFFSETLO (Bit 24) */ +#define IOM0_CMD_OFFSETLO_Msk (0xff000000UL) /*!< OFFSETLO (Bitfield-Mask: 0xff) */ +#define IOM0_CMD_CMDSEL_Pos (20UL) /*!< CMDSEL (Bit 20) */ +#define IOM0_CMD_CMDSEL_Msk (0x300000UL) /*!< CMDSEL (Bitfield-Mask: 0x03) */ +#define IOM0_CMD_TSIZE_Pos (8UL) /*!< TSIZE (Bit 8) */ +#define IOM0_CMD_TSIZE_Msk (0xfff00UL) /*!< TSIZE (Bitfield-Mask: 0xfff) */ +#define IOM0_CMD_CONT_Pos (7UL) /*!< CONT (Bit 7) */ +#define IOM0_CMD_CONT_Msk (0x80UL) /*!< CONT (Bitfield-Mask: 0x01) */ +#define IOM0_CMD_OFFSETCNT_Pos (5UL) /*!< OFFSETCNT (Bit 5) */ +#define IOM0_CMD_OFFSETCNT_Msk (0x60UL) /*!< OFFSETCNT (Bitfield-Mask: 0x03) */ +#define IOM0_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */ +#define IOM0_CMD_CMD_Msk (0x1fUL) /*!< CMD (Bitfield-Mask: 0x1f) */ +/* ========================================================== DCX ========================================================== */ +#define IOM0_DCX_DCXEN_Pos (4UL) /*!< DCXEN (Bit 4) */ +#define IOM0_DCX_DCXEN_Msk (0x10UL) /*!< DCXEN (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE3OUT_Pos (3UL) /*!< CE3OUT (Bit 3) */ +#define IOM0_DCX_CE3OUT_Msk (0x8UL) /*!< CE3OUT (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE2OUT_Pos (2UL) /*!< CE2OUT (Bit 2) */ +#define IOM0_DCX_CE2OUT_Msk (0x4UL) /*!< CE2OUT (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE1OUT_Pos (1UL) /*!< CE1OUT (Bit 1) */ +#define IOM0_DCX_CE1OUT_Msk (0x2UL) /*!< CE1OUT (Bitfield-Mask: 0x01) */ +#define IOM0_DCX_CE0OUT_Pos (0UL) /*!< CE0OUT (Bit 0) */ +#define IOM0_DCX_CE0OUT_Msk (0x1UL) /*!< CE0OUT (Bitfield-Mask: 0x01) */ +/* ======================================================= OFFSETHI ======================================================== */ +#define IOM0_OFFSETHI_OFFSETHI_Pos (0UL) /*!< OFFSETHI (Bit 0) */ +#define IOM0_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< OFFSETHI (Bitfield-Mask: 0xffff) */ +/* ======================================================== CMDSTAT ======================================================== */ +#define IOM0_CMDSTAT_CTSIZE_Pos (8UL) /*!< CTSIZE (Bit 8) */ +#define IOM0_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< CTSIZE (Bitfield-Mask: 0xfff) */ +#define IOM0_CMDSTAT_CMDSTAT_Pos (5UL) /*!< CMDSTAT (Bit 5) */ +#define IOM0_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< CMDSTAT (Bitfield-Mask: 0x07) */ +#define IOM0_CMDSTAT_CCMD_Pos (0UL) /*!< CCMD (Bit 0) */ +#define IOM0_CMDSTAT_CCMD_Msk (0x1fUL) /*!< CCMD (Bitfield-Mask: 0x1f) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define IOM0_DMATRIGEN_DTHREN_Pos (1UL) /*!< DTHREN (Bit 1) */ +#define IOM0_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< DTHREN (Bitfield-Mask: 0x01) */ +#define IOM0_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< DCMDCMPEN (Bit 0) */ +#define IOM0_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< DCMDCMPEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define IOM0_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< DTOTCMP (Bit 2) */ +#define IOM0_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< DTOTCMP (Bitfield-Mask: 0x01) */ +#define IOM0_DMATRIGSTAT_DTHR_Pos (1UL) /*!< DTHR (Bit 1) */ +#define IOM0_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< DTHR (Bitfield-Mask: 0x01) */ +#define IOM0_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< DCMDCMP (Bit 0) */ +#define IOM0_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< DCMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define IOM0_DMACFG_DPWROFF_Pos (9UL) /*!< DPWROFF (Bit 9) */ +#define IOM0_DMACFG_DPWROFF_Msk (0x200UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define IOM0_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define IOM0_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define IOM0_DMACFG_DMADIR_Pos (1UL) /*!< DMADIR (Bit 1) */ +#define IOM0_DMACFG_DMADIR_Msk (0x2UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define IOM0_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define IOM0_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define IOM0_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define IOM0_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define IOM0_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< TARGADDR28 (Bit 28) */ +#define IOM0_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< TARGADDR28 (Bitfield-Mask: 0x01) */ +#define IOM0_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */ +#define IOM0_DMATARGADDR_TARGADDR_Msk (0xfffffUL) /*!< TARGADDR (Bitfield-Mask: 0xfffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define IOM0_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define IOM0_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define IOM0_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define IOM0_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define IOM0_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define IOM0_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ +/* ========================================================= CQCFG ========================================================= */ +#define IOM0_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */ +#define IOM0_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */ +#define IOM0_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */ +#define IOM0_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CQADDR ========================================================= */ +#define IOM0_CQADDR_CQADDR28_Pos (28UL) /*!< CQADDR28 (Bit 28) */ +#define IOM0_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< CQADDR28 (Bitfield-Mask: 0x01) */ +#define IOM0_CQADDR_CQADDR_Pos (2UL) /*!< CQADDR (Bit 2) */ +#define IOM0_CQADDR_CQADDR_Msk (0xffffcUL) /*!< CQADDR (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== CQSTAT ========================================================= */ +#define IOM0_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */ +#define IOM0_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define IOM0_CQSTAT_CQPAUSED_Pos (1UL) /*!< CQPAUSED (Bit 1) */ +#define IOM0_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define IOM0_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */ +#define IOM0_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */ +/* ======================================================== CQFLAGS ======================================================== */ +#define IOM0_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< CQIRQMASK (Bit 16) */ +#define IOM0_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< CQIRQMASK (Bitfield-Mask: 0xffff) */ +#define IOM0_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */ +#define IOM0_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CQSETCLEAR ======================================================= */ +#define IOM0_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */ +#define IOM0_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */ +#define IOM0_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< CQFTGL (Bit 8) */ +#define IOM0_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< CQFTGL (Bitfield-Mask: 0xff) */ +#define IOM0_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */ +#define IOM0_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */ +/* ======================================================= CQPAUSEEN ======================================================= */ +#define IOM0_CQPAUSEEN_CQPEN_Pos (0UL) /*!< CQPEN (Bit 0) */ +#define IOM0_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< CQPEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= CQCURIDX ======================================================== */ +#define IOM0_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */ +#define IOM0_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */ +/* ======================================================= CQENDIDX ======================================================== */ +#define IOM0_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */ +#define IOM0_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */ +/* ======================================================== STATUS ========================================================= */ +#define IOM0_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */ +#define IOM0_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */ +#define IOM0_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */ +#define IOM0_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */ +#define IOM0_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */ +#define IOM0_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MSPICFG ======================================================== */ +#define IOM0_MSPICFG_MSPIRST_Pos (30UL) /*!< MSPIRST (Bit 30) */ +#define IOM0_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< MSPIRST (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_DOUTDLY_Pos (27UL) /*!< DOUTDLY (Bit 27) */ +#define IOM0_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< DOUTDLY (Bitfield-Mask: 0x07) */ +#define IOM0_MSPICFG_DINDLY_Pos (24UL) /*!< DINDLY (Bit 24) */ +#define IOM0_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< DINDLY (Bitfield-Mask: 0x07) */ +#define IOM0_MSPICFG_SPILSB_Pos (23UL) /*!< SPILSB (Bit 23) */ +#define IOM0_MSPICFG_SPILSB_Msk (0x800000UL) /*!< SPILSB (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_RDFCPOL_Pos (22UL) /*!< RDFCPOL (Bit 22) */ +#define IOM0_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< RDFCPOL (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_WTFCPOL_Pos (21UL) /*!< WTFCPOL (Bit 21) */ +#define IOM0_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< WTFCPOL (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_WTFCIRQ_Pos (20UL) /*!< WTFCIRQ (Bit 20) */ +#define IOM0_MSPICFG_WTFCIRQ_Msk (0x100000UL) /*!< WTFCIRQ (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_MOSIINV_Pos (18UL) /*!< MOSIINV (Bit 18) */ +#define IOM0_MSPICFG_MOSIINV_Msk (0x40000UL) /*!< MOSIINV (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_RDFC_Pos (17UL) /*!< RDFC (Bit 17) */ +#define IOM0_MSPICFG_RDFC_Msk (0x20000UL) /*!< RDFC (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_WTFC_Pos (16UL) /*!< WTFC (Bit 16) */ +#define IOM0_MSPICFG_WTFC_Msk (0x10000UL) /*!< WTFC (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_FULLDUP_Pos (2UL) /*!< FULLDUP (Bit 2) */ +#define IOM0_MSPICFG_FULLDUP_Msk (0x4UL) /*!< FULLDUP (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_SPHA_Pos (1UL) /*!< SPHA (Bit 1) */ +#define IOM0_MSPICFG_SPHA_Msk (0x2UL) /*!< SPHA (Bitfield-Mask: 0x01) */ +#define IOM0_MSPICFG_SPOL_Pos (0UL) /*!< SPOL (Bit 0) */ +#define IOM0_MSPICFG_SPOL_Msk (0x1UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +/* ======================================================== MI2CCFG ======================================================== */ +#define IOM0_MI2CCFG_STRDIS_Pos (24UL) /*!< STRDIS (Bit 24) */ +#define IOM0_MI2CCFG_STRDIS_Msk (0x1000000UL) /*!< STRDIS (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_SMPCNT_Pos (16UL) /*!< SMPCNT (Bit 16) */ +#define IOM0_MI2CCFG_SMPCNT_Msk (0xff0000UL) /*!< SMPCNT (Bitfield-Mask: 0xff) */ +#define IOM0_MI2CCFG_SDAENDLY_Pos (12UL) /*!< SDAENDLY (Bit 12) */ +#define IOM0_MI2CCFG_SDAENDLY_Msk (0xf000UL) /*!< SDAENDLY (Bitfield-Mask: 0x0f) */ +#define IOM0_MI2CCFG_SCLENDLY_Pos (8UL) /*!< SCLENDLY (Bit 8) */ +#define IOM0_MI2CCFG_SCLENDLY_Msk (0xf00UL) /*!< SCLENDLY (Bitfield-Mask: 0x0f) */ +#define IOM0_MI2CCFG_MI2CRST_Pos (6UL) /*!< MI2CRST (Bit 6) */ +#define IOM0_MI2CCFG_MI2CRST_Msk (0x40UL) /*!< MI2CRST (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_SDADLY_Pos (4UL) /*!< SDADLY (Bit 4) */ +#define IOM0_MI2CCFG_SDADLY_Msk (0x30UL) /*!< SDADLY (Bitfield-Mask: 0x03) */ +#define IOM0_MI2CCFG_ARBEN_Pos (2UL) /*!< ARBEN (Bit 2) */ +#define IOM0_MI2CCFG_ARBEN_Msk (0x4UL) /*!< ARBEN (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_I2CLSB_Pos (1UL) /*!< I2CLSB (Bit 1) */ +#define IOM0_MI2CCFG_I2CLSB_Msk (0x2UL) /*!< I2CLSB (Bitfield-Mask: 0x01) */ +#define IOM0_MI2CCFG_ADDRSZ_Pos (0UL) /*!< ADDRSZ (Bit 0) */ +#define IOM0_MI2CCFG_ADDRSZ_Msk (0x1UL) /*!< ADDRSZ (Bitfield-Mask: 0x01) */ +/* ======================================================== DEVCFG ========================================================= */ +#define IOM0_DEVCFG_DEVADDR_Pos (0UL) /*!< DEVADDR (Bit 0) */ +#define IOM0_DEVCFG_DEVADDR_Msk (0x3ffUL) /*!< DEVADDR (Bitfield-Mask: 0x3ff) */ +/* ======================================================== IOMDBG ========================================================= */ +#define IOM0_IOMDBG_DBGDATA_Pos (3UL) /*!< DBGDATA (Bit 3) */ +#define IOM0_IOMDBG_DBGDATA_Msk (0xfffffff8UL) /*!< DBGDATA (Bitfield-Mask: 0x1fffffff) */ +#define IOM0_IOMDBG_APBCLKON_Pos (2UL) /*!< APBCLKON (Bit 2) */ +#define IOM0_IOMDBG_APBCLKON_Msk (0x4UL) /*!< APBCLKON (Bitfield-Mask: 0x01) */ +#define IOM0_IOMDBG_IOCLKON_Pos (1UL) /*!< IOCLKON (Bit 1) */ +#define IOM0_IOMDBG_IOCLKON_Msk (0x2UL) /*!< IOCLKON (Bitfield-Mask: 0x01) */ +#define IOM0_IOMDBG_DBGEN_Pos (0UL) /*!< DBGEN (Bit 0) */ +#define IOM0_IOMDBG_DBGEN_Msk (0x1UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FIFOPTR ======================================================== */ +#define IOSLAVE_FIFOPTR_FIFOSIZ_Pos (8UL) /*!< FIFOSIZ (Bit 8) */ +#define IOSLAVE_FIFOPTR_FIFOSIZ_Msk (0xff00UL) /*!< FIFOSIZ (Bitfield-Mask: 0xff) */ +#define IOSLAVE_FIFOPTR_FIFOPTR_Pos (0UL) /*!< FIFOPTR (Bit 0) */ +#define IOSLAVE_FIFOPTR_FIFOPTR_Msk (0xffUL) /*!< FIFOPTR (Bitfield-Mask: 0xff) */ +/* ======================================================== FIFOCFG ======================================================== */ +#define IOSLAVE_FIFOCFG_ROBASE_Pos (24UL) /*!< ROBASE (Bit 24) */ +#define IOSLAVE_FIFOCFG_ROBASE_Msk (0x3f000000UL) /*!< ROBASE (Bitfield-Mask: 0x3f) */ +#define IOSLAVE_FIFOCFG_FIFOMAX_Pos (8UL) /*!< FIFOMAX (Bit 8) */ +#define IOSLAVE_FIFOCFG_FIFOMAX_Msk (0x3f00UL) /*!< FIFOMAX (Bitfield-Mask: 0x3f) */ +#define IOSLAVE_FIFOCFG_FIFOBASE_Pos (0UL) /*!< FIFOBASE (Bit 0) */ +#define IOSLAVE_FIFOCFG_FIFOBASE_Msk (0x1fUL) /*!< FIFOBASE (Bitfield-Mask: 0x1f) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define IOSLAVE_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */ +#define IOSLAVE_FIFOTHR_FIFOTHR_Msk (0xffUL) /*!< FIFOTHR (Bitfield-Mask: 0xff) */ +/* ========================================================= FUPD ========================================================== */ +#define IOSLAVE_FUPD_IOREAD_Pos (1UL) /*!< IOREAD (Bit 1) */ +#define IOSLAVE_FUPD_IOREAD_Msk (0x2UL) /*!< IOREAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_FUPD_FIFOUPD_Pos (0UL) /*!< FIFOUPD (Bit 0) */ +#define IOSLAVE_FUPD_FIFOUPD_Msk (0x1UL) /*!< FIFOUPD (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOCTR ======================================================== */ +#define IOSLAVE_FIFOCTR_FIFOCTR_Pos (0UL) /*!< FIFOCTR (Bit 0) */ +#define IOSLAVE_FIFOCTR_FIFOCTR_Msk (0x3ffUL) /*!< FIFOCTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FIFOINC ======================================================== */ +#define IOSLAVE_FIFOINC_FIFOINC_Pos (0UL) /*!< FIFOINC (Bit 0) */ +#define IOSLAVE_FIFOINC_FIFOINC_Msk (0x3ffUL) /*!< FIFOINC (Bitfield-Mask: 0x3ff) */ +/* ========================================================== CFG ========================================================== */ +#define IOSLAVE_CFG_IFCEN_Pos (31UL) /*!< IFCEN (Bit 31) */ +#define IOSLAVE_CFG_IFCEN_Msk (0x80000000UL) /*!< IFCEN (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_I2CADDR_Pos (8UL) /*!< I2CADDR (Bit 8) */ +#define IOSLAVE_CFG_I2CADDR_Msk (0xfff00UL) /*!< I2CADDR (Bitfield-Mask: 0xfff) */ +#define IOSLAVE_CFG_STARTRD_Pos (4UL) /*!< STARTRD (Bit 4) */ +#define IOSLAVE_CFG_STARTRD_Msk (0x10UL) /*!< STARTRD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_LSB_Pos (2UL) /*!< LSB (Bit 2) */ +#define IOSLAVE_CFG_LSB_Msk (0x4UL) /*!< LSB (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */ +#define IOSLAVE_CFG_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_CFG_IFCSEL_Pos (0UL) /*!< IFCSEL (Bit 0) */ +#define IOSLAVE_CFG_IFCSEL_Msk (0x1UL) /*!< IFCSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= PRENC ========================================================= */ +#define IOSLAVE_PRENC_PRENC_Pos (0UL) /*!< PRENC (Bit 0) */ +#define IOSLAVE_PRENC_PRENC_Msk (0x1fUL) /*!< PRENC (Bitfield-Mask: 0x1f) */ +/* ======================================================= IOINTCTL ======================================================== */ +#define IOSLAVE_IOINTCTL_IOINTSET_Pos (24UL) /*!< IOINTSET (Bit 24) */ +#define IOSLAVE_IOINTCTL_IOINTSET_Msk (0xff000000UL) /*!< IOINTSET (Bitfield-Mask: 0xff) */ +#define IOSLAVE_IOINTCTL_IOINTCLR_Pos (16UL) /*!< IOINTCLR (Bit 16) */ +#define IOSLAVE_IOINTCTL_IOINTCLR_Msk (0x10000UL) /*!< IOINTCLR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_IOINTCTL_IOINT_Pos (8UL) /*!< IOINT (Bit 8) */ +#define IOSLAVE_IOINTCTL_IOINT_Msk (0xff00UL) /*!< IOINT (Bitfield-Mask: 0xff) */ +#define IOSLAVE_IOINTCTL_IOINTEN_Pos (0UL) /*!< IOINTEN (Bit 0) */ +#define IOSLAVE_IOINTCTL_IOINTEN_Msk (0xffUL) /*!< IOINTEN (Bitfield-Mask: 0xff) */ +/* ======================================================== GENADD ========================================================= */ +#define IOSLAVE_GENADD_GADATA_Pos (0UL) /*!< GADATA (Bit 0) */ +#define IOSLAVE_GENADD_GADATA_Msk (0xffUL) /*!< GADATA (Bitfield-Mask: 0xff) */ +/* ========================================================= INTEN ========================================================= */ +#define IOSLAVE_INTEN_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTEN_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTEN_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTEN_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTEN_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTEN_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTEN_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTEN_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTEN_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTEN_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTEN_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define IOSLAVE_INTSTAT_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTSTAT_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTSTAT_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTSTAT_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTSTAT_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTSTAT_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTSTAT_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTSTAT_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTSTAT_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSTAT_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTSTAT_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define IOSLAVE_INTCLR_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTCLR_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTCLR_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTCLR_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTCLR_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTCLR_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTCLR_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTCLR_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTCLR_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTCLR_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTCLR_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define IOSLAVE_INTSET_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */ +#define IOSLAVE_INTSET_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */ +#define IOSLAVE_INTSET_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */ +#define IOSLAVE_INTSET_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */ +#define IOSLAVE_INTSET_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */ +#define IOSLAVE_INTSET_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */ +#define IOSLAVE_INTSET_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */ +#define IOSLAVE_INTSET_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */ +#define IOSLAVE_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */ +#define IOSLAVE_INTSET_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */ +#define IOSLAVE_INTSET_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */ +#define IOSLAVE_INTSET_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */ +/* ====================================================== REGACCINTEN ====================================================== */ +#define IOSLAVE_REGACCINTEN_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTEN_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTSTAT ===================================================== */ +#define IOSLAVE_REGACCINTSTAT_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTSTAT_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTCLR ====================================================== */ +#define IOSLAVE_REGACCINTCLR_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTCLR_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== REGACCINTSET ====================================================== */ +#define IOSLAVE_REGACCINTSET_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */ +#define IOSLAVE_REGACCINTSET_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPPN ========================================================= */ +#define MCUCTRL_CHIPPN_PARTNUM_Pos (0UL) /*!< PARTNUM (Bit 0) */ +#define MCUCTRL_CHIPPN_PARTNUM_Msk (0xffffffffUL) /*!< PARTNUM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPID0 ======================================================== */ +#define MCUCTRL_CHIPID0_CHIPID0_Pos (0UL) /*!< CHIPID0 (Bit 0) */ +#define MCUCTRL_CHIPID0_CHIPID0_Msk (0xffffffffUL) /*!< CHIPID0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPID1 ======================================================== */ +#define MCUCTRL_CHIPID1_CHIPID1_Pos (0UL) /*!< CHIPID1 (Bit 0) */ +#define MCUCTRL_CHIPID1_CHIPID1_Msk (0xffffffffUL) /*!< CHIPID1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHIPREV ======================================================== */ +#define MCUCTRL_CHIPREV_SIPART_Pos (8UL) /*!< SIPART (Bit 8) */ +#define MCUCTRL_CHIPREV_SIPART_Msk (0xfff00UL) /*!< SIPART (Bitfield-Mask: 0xfff) */ +#define MCUCTRL_CHIPREV_REVMAJ_Pos (4UL) /*!< REVMAJ (Bit 4) */ +#define MCUCTRL_CHIPREV_REVMAJ_Msk (0xf0UL) /*!< REVMAJ (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_CHIPREV_REVMIN_Pos (0UL) /*!< REVMIN (Bit 0) */ +#define MCUCTRL_CHIPREV_REVMIN_Msk (0xfUL) /*!< REVMIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= VENDORID ======================================================== */ +#define MCUCTRL_VENDORID_VENDORID_Pos (0UL) /*!< VENDORID (Bit 0) */ +#define MCUCTRL_VENDORID_VENDORID_Msk (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== SKU ========================================================== */ +#define MCUCTRL_SKU_SECBOOT_Pos (2UL) /*!< SECBOOT (Bit 2) */ +#define MCUCTRL_SKU_SECBOOT_Msk (0x4UL) /*!< SECBOOT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SKU_ALLOWBLE_Pos (1UL) /*!< ALLOWBLE (Bit 1) */ +#define MCUCTRL_SKU_ALLOWBLE_Msk (0x2UL) /*!< ALLOWBLE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SKU_ALLOWBURST_Pos (0UL) /*!< ALLOWBURST (Bit 0) */ +#define MCUCTRL_SKU_ALLOWBURST_Msk (0x1UL) /*!< ALLOWBURST (Bitfield-Mask: 0x01) */ +/* ===================================================== FEATUREENABLE ===================================================== */ +#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Pos (6UL) /*!< BURSTAVAIL (Bit 6) */ +#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Msk (0x40UL) /*!< BURSTAVAIL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BURSTACK_Pos (5UL) /*!< BURSTACK (Bit 5) */ +#define MCUCTRL_FEATUREENABLE_BURSTACK_Msk (0x20UL) /*!< BURSTACK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BURSTREQ_Pos (4UL) /*!< BURSTREQ (Bit 4) */ +#define MCUCTRL_FEATUREENABLE_BURSTREQ_Msk (0x10UL) /*!< BURSTREQ (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Pos (2UL) /*!< BLEAVAIL (Bit 2) */ +#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk (0x4UL) /*!< BLEAVAIL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BLEACK_Pos (1UL) /*!< BLEACK (Bit 1) */ +#define MCUCTRL_FEATUREENABLE_BLEACK_Msk (0x2UL) /*!< BLEACK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FEATUREENABLE_BLEREQ_Pos (0UL) /*!< BLEREQ (Bit 0) */ +#define MCUCTRL_FEATUREENABLE_BLEREQ_Msk (0x1UL) /*!< BLEREQ (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGGER ======================================================== */ +#define MCUCTRL_DEBUGGER_LOCKOUT_Pos (0UL) /*!< LOCKOUT (Bit 0) */ +#define MCUCTRL_DEBUGGER_LOCKOUT_Msk (0x1UL) /*!< LOCKOUT (Bitfield-Mask: 0x01) */ +/* ======================================================== BODCTRL ======================================================== */ +#define MCUCTRL_BODCTRL_BODHVREFSEL_Pos (5UL) /*!< BODHVREFSEL (Bit 5) */ +#define MCUCTRL_BODCTRL_BODHVREFSEL_Msk (0x20UL) /*!< BODHVREFSEL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODLVREFSEL_Pos (4UL) /*!< BODLVREFSEL (Bit 4) */ +#define MCUCTRL_BODCTRL_BODLVREFSEL_Msk (0x10UL) /*!< BODLVREFSEL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODFPWD_Pos (3UL) /*!< BODFPWD (Bit 3) */ +#define MCUCTRL_BODCTRL_BODFPWD_Msk (0x8UL) /*!< BODFPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODCPWD_Pos (2UL) /*!< BODCPWD (Bit 2) */ +#define MCUCTRL_BODCTRL_BODCPWD_Msk (0x4UL) /*!< BODCPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODHPWD_Pos (1UL) /*!< BODHPWD (Bit 1) */ +#define MCUCTRL_BODCTRL_BODHPWD_Msk (0x2UL) /*!< BODHPWD (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BODCTRL_BODLPWD_Pos (0UL) /*!< BODLPWD (Bit 0) */ +#define MCUCTRL_BODCTRL_BODLPWD_Msk (0x1UL) /*!< BODLPWD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCPWRDLY ======================================================= */ +#define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos (8UL) /*!< ADCPWR1 (Bit 8) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk (0xff00UL) /*!< ADCPWR1 (Bitfield-Mask: 0xff) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos (0UL) /*!< ADCPWR0 (Bit 0) */ +#define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk (0xffUL) /*!< ADCPWR0 (Bitfield-Mask: 0xff) */ +/* ======================================================== ADCCAL ========================================================= */ +#define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos (1UL) /*!< ADCCALIBRATED (Bit 1) */ +#define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk (0x2UL) /*!< ADCCALIBRATED (Bitfield-Mask: 0x01) */ +#define MCUCTRL_ADCCAL_CALONPWRUP_Pos (0UL) /*!< CALONPWRUP (Bit 0) */ +#define MCUCTRL_ADCCAL_CALONPWRUP_Msk (0x1UL) /*!< CALONPWRUP (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCBATTLOAD ====================================================== */ +#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos (0UL) /*!< BATTLOAD (Bit 0) */ +#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk (0x1UL) /*!< BATTLOAD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCTRIM ======================================================== */ +#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Pos (11UL) /*!< ADCRFBUFIBTRIM (Bit 11) */ +#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Msk (0x1800UL) /*!< ADCRFBUFIBTRIM (Bitfield-Mask: 0x03) */ +#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Pos (6UL) /*!< ADCREFBUFTRIM (Bit 6) */ +#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Msk (0x7c0UL) /*!< ADCREFBUFTRIM (Bitfield-Mask: 0x1f) */ +#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Pos (0UL) /*!< ADCREFKEEPIBTRIM (Bit 0) */ +#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Msk (0x3UL) /*!< ADCREFKEEPIBTRIM (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCREFCOMP ======================================================= */ +#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Pos (16UL) /*!< ADCRFCMPEN (Bit 16) */ +#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Msk (0x10000UL) /*!< ADCRFCMPEN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Pos (8UL) /*!< ADCREFKEEPTRIM (Bit 8) */ +#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Msk (0x1f00UL) /*!< ADCREFKEEPTRIM (Bitfield-Mask: 0x1f) */ +#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Pos (0UL) /*!< ADC_REFCOMP_OUT (Bit 0) */ +#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Msk (0x1UL) /*!< ADC_REFCOMP_OUT (Bitfield-Mask: 0x01) */ +/* ======================================================= XTALCTRL ======================================================== */ +#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (8UL) /*!< XTALICOMPTRIM (Bit 8) */ +#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x300UL) /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03) */ +#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (6UL) /*!< XTALIBUFTRIM (Bit 6) */ +#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0xc0UL) /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03) */ +#define MCUCTRL_XTALCTRL_PWDBODXTAL_Pos (5UL) /*!< PWDBODXTAL (Bit 5) */ +#define MCUCTRL_XTALCTRL_PWDBODXTAL_Msk (0x20UL) /*!< PWDBODXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Pos (4UL) /*!< PDNBCMPRXTAL (Bit 4) */ +#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk (0x10UL) /*!< PDNBCMPRXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Pos (3UL) /*!< PDNBCOREXTAL (Bit 3) */ +#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk (0x8UL) /*!< PDNBCOREXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Pos (2UL) /*!< BYPCMPRXTAL (Bit 2) */ +#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk (0x4UL) /*!< BYPCMPRXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Pos (1UL) /*!< FDBKDSBLXTAL (Bit 1) */ +#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk (0x2UL) /*!< FDBKDSBLXTAL (Bitfield-Mask: 0x01) */ +#define MCUCTRL_XTALCTRL_XTALSWE_Pos (0UL) /*!< XTALSWE (Bit 0) */ +#define MCUCTRL_XTALCTRL_XTALSWE_Msk (0x1UL) /*!< XTALSWE (Bitfield-Mask: 0x01) */ +/* ====================================================== XTALGENCTRL ====================================================== */ +#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL) /*!< XTALKSBIASTRIM (Bit 8) */ +#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL) /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL) /*!< XTALBIASTRIM (Bit 2) */ +#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL) /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos (0UL) /*!< ACWARMUP (Bit 0) */ +#define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk (0x3UL) /*!< ACWARMUP (Bitfield-Mask: 0x03) */ +/* ======================================================= MISCCTRL ======================================================== */ +#define MCUCTRL_MISCCTRL_BLE_RESETN_Pos (5UL) /*!< BLE_RESETN (Bit 5) */ +#define MCUCTRL_MISCCTRL_BLE_RESETN_Msk (0x20UL) /*!< BLE_RESETN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Pos (0UL) /*!< RESERVED_RW_0 (Bit 0) */ +#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Msk (0x1fUL) /*!< RESERVED_RW_0 (Bitfield-Mask: 0x1f) */ +/* ====================================================== BOOTLOADER ======================================================= */ +#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL) /*!< SECBOOTONRST (Bit 30) */ +#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL) /*!< SECBOOTONRST (Bitfield-Mask: 0x03) */ +#define MCUCTRL_BOOTLOADER_SECBOOT_Pos (28UL) /*!< SECBOOT (Bit 28) */ +#define MCUCTRL_BOOTLOADER_SECBOOT_Msk (0x30000000UL) /*!< SECBOOT (Bitfield-Mask: 0x03) */ +#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL) /*!< SECBOOTFEATURE (Bit 26) */ +#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL) /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03) */ +#define MCUCTRL_BOOTLOADER_PROTLOCK_Pos (2UL) /*!< PROTLOCK (Bit 2) */ +#define MCUCTRL_BOOTLOADER_PROTLOCK_Msk (0x4UL) /*!< PROTLOCK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BOOTLOADER_SBLOCK_Pos (1UL) /*!< SBLOCK (Bit 1) */ +#define MCUCTRL_BOOTLOADER_SBLOCK_Msk (0x2UL) /*!< SBLOCK (Bitfield-Mask: 0x01) */ +#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL) /*!< BOOTLOADERLOW (Bit 0) */ +#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL) /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01) */ +/* ====================================================== SHADOWVALID ====================================================== */ +#define MCUCTRL_SHADOWVALID_INFO0_VALID_Pos (2UL) /*!< INFO0_VALID (Bit 2) */ +#define MCUCTRL_SHADOWVALID_INFO0_VALID_Msk (0x4UL) /*!< INFO0_VALID (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos (1UL) /*!< BLDSLEEP (Bit 1) */ +#define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk (0x2UL) /*!< BLDSLEEP (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SHADOWVALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */ +#define MCUCTRL_SHADOWVALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ +/* ======================================================= SCRATCH0 ======================================================== */ +#define MCUCTRL_SCRATCH0_SCRATCH0_Pos (0UL) /*!< SCRATCH0 (Bit 0) */ +#define MCUCTRL_SCRATCH0_SCRATCH0_Msk (0xffffffffUL) /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SCRATCH1 ======================================================== */ +#define MCUCTRL_SCRATCH1_SCRATCH1_Pos (0UL) /*!< SCRATCH1 (Bit 0) */ +#define MCUCTRL_SCRATCH1_SCRATCH1_Msk (0xffffffffUL) /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== ICODEFAULTADDR ===================================================== */ +#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL) /*!< ICODEFAULTADDR (Bit 0) */ +#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL) /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DCODEFAULTADDR ===================================================== */ +#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL) /*!< DCODEFAULTADDR (Bit 0) */ +#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL) /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SYSFAULTADDR ====================================================== */ +#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL) /*!< SYSFAULTADDR (Bit 0) */ +#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL) /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FAULTSTATUS ====================================================== */ +#define MCUCTRL_FAULTSTATUS_SYSFAULT_Pos (2UL) /*!< SYSFAULT (Bit 2) */ +#define MCUCTRL_FAULTSTATUS_SYSFAULT_Msk (0x4UL) /*!< SYSFAULT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Pos (1UL) /*!< DCODEFAULT (Bit 1) */ +#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk (0x2UL) /*!< DCODEFAULT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Pos (0UL) /*!< ICODEFAULT (Bit 0) */ +#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk (0x1UL) /*!< ICODEFAULT (Bitfield-Mask: 0x01) */ +/* ==================================================== FAULTCAPTUREEN ===================================================== */ +#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL) /*!< FAULTCAPTUREEN (Bit 0) */ +#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL) /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01) */ +/* ========================================================= DBGR1 ========================================================= */ +#define MCUCTRL_DBGR1_ONETO8_Pos (0UL) /*!< ONETO8 (Bit 0) */ +#define MCUCTRL_DBGR1_ONETO8_Msk (0xffffffffUL) /*!< ONETO8 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBGR2 ========================================================= */ +#define MCUCTRL_DBGR2_COOLCODE_Pos (0UL) /*!< COOLCODE (Bit 0) */ +#define MCUCTRL_DBGR2_COOLCODE_Msk (0xffffffffUL) /*!< COOLCODE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMUENABLE ======================================================= */ +#define MCUCTRL_PMUENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define MCUCTRL_PMUENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= TPIUCTRL ======================================================== */ +#define MCUCTRL_TPIUCTRL_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ +#define MCUCTRL_TPIUCTRL_CLKSEL_Msk (0x700UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define MCUCTRL_TPIUCTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define MCUCTRL_TPIUCTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ====================================================== OTAPOINTER ======================================================= */ +#define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL) /*!< OTAPOINTER (Bit 2) */ +#define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL) /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff) */ +#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL) /*!< OTASBLUPDATE (Bit 1) */ +#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL) /*!< OTASBLUPDATE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_OTAPOINTER_OTAVALID_Pos (0UL) /*!< OTAVALID (Bit 0) */ +#define MCUCTRL_OTAPOINTER_OTAVALID_Msk (0x1UL) /*!< OTAVALID (Bitfield-Mask: 0x01) */ +/* ====================================================== APBDMACTRL ======================================================= */ +#define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL) /*!< HYSTERESIS (Bit 8) */ +#define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL) /*!< HYSTERESIS (Bitfield-Mask: 0xff) */ +#define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL) /*!< DECODEABORT (Bit 1) */ +#define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL) /*!< DECODEABORT (Bitfield-Mask: 0x01) */ +#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Pos (0UL) /*!< DMA_ENABLE (Bit 0) */ +#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Msk (0x1UL) /*!< DMA_ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMMODE ======================================================== */ +#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Pos (5UL) /*!< DPREFETCH_CACHE (Bit 5) */ +#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk (0x20UL) /*!< DPREFETCH_CACHE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SRAMMODE_DPREFETCH_Pos (4UL) /*!< DPREFETCH (Bit 4) */ +#define MCUCTRL_SRAMMODE_DPREFETCH_Msk (0x10UL) /*!< DPREFETCH (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Pos (1UL) /*!< IPREFETCH_CACHE (Bit 1) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk (0x2UL) /*!< IPREFETCH_CACHE (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_Pos (0UL) /*!< IPREFETCH (Bit 0) */ +#define MCUCTRL_SRAMMODE_IPREFETCH_Msk (0x1UL) /*!< IPREFETCH (Bitfield-Mask: 0x01) */ +/* ====================================================== KEXTCLKSEL ======================================================= */ +#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL) /*!< KEXTCLKSEL (Bit 0) */ +#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL) /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SIMOBUCK2 ======================================================= */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Pos (24UL) /*!< RESERVED_RW_24 (Bit 24) */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Msk (0xff000000UL) /*!< RESERVED_RW_24 (Bitfield-Mask: 0xff) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Pos (20UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bit 20) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Msk (0xf00000UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Pos (16UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bit 16) */ +#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Msk (0xf0000UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_0_Pos (0UL) /*!< RESERVED_RW_0 (Bit 0) */ +#define MCUCTRL_SIMOBUCK2_RESERVED_RW_0_Msk (0xffffUL) /*!< RESERVED_RW_0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SIMOBUCK3 ======================================================= */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Pos (31UL) /*!< RESERVED_RW_31 (Bit 31) */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Msk (0x80000000UL) /*!< RESERVED_RW_31 (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Pos (27UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bit 27) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Msk (0x78000000UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Pos (16UL) /*!< RESERVED_RW_16 (Bit 16) */ +#define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Msk (0x7ff0000UL) /*!< RESERVED_RW_16 (Bitfield-Mask: 0x7ff) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Pos (12UL) /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bit 12) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Msk (0xf000UL) /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Pos (8UL) /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bit 8) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Msk (0xf00UL) /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Pos (4UL) /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bit 4) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Msk (0xf0UL) /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bitfield-Mask: 0x0f) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Pos (0UL) /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bit 0) */ +#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Msk (0xfUL) /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bitfield-Mask: 0x0f) */ +/* ======================================================= SIMOBUCK4 ======================================================= */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Pos (24UL) /*!< SIMOBUCKCOMP2TIMEOUTEN (Bit 24) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Msk (0x1000000UL) /*!< SIMOBUCKCOMP2TIMEOUTEN (Bitfield-Mask: 0x01) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Pos (21UL) /*!< SIMOBUCKCLKDIVSEL (Bit 21) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Msk (0x600000UL) /*!< SIMOBUCKCLKDIVSEL (Bitfield-Mask: 0x03) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Pos (0UL) /*!< SIMOBUCKMEMLPLOWTONTRIM (Bit 0) */ +#define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Msk (0xfUL) /*!< SIMOBUCKMEMLPLOWTONTRIM (Bitfield-Mask: 0x0f) */ +/* ======================================================= BLEBUCK2 ======================================================== */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Pos (12UL) /*!< BLEBUCKTOND2ATRIM (Bit 12) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Msk (0x3f000UL) /*!< BLEBUCKTOND2ATRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Pos (6UL) /*!< BLEBUCKTONHITRIM (Bit 6) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Msk (0xfc0UL) /*!< BLEBUCKTONHITRIM (Bitfield-Mask: 0x3f) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Pos (0UL) /*!< BLEBUCKTONLOWTRIM (Bit 0) */ +#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Msk (0x3fUL) /*!< BLEBUCKTONLOWTRIM (Bitfield-Mask: 0x3f) */ +/* ====================================================== FLASHWPROT0 ====================================================== */ +#define MCUCTRL_FLASHWPROT0_FW0BITS_Pos (0UL) /*!< FW0BITS (Bit 0) */ +#define MCUCTRL_FLASHWPROT0_FW0BITS_Msk (0xffffffffUL) /*!< FW0BITS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FLASHWPROT1 ====================================================== */ +#define MCUCTRL_FLASHWPROT1_FW1BITS_Pos (0UL) /*!< FW1BITS (Bit 0) */ +#define MCUCTRL_FLASHWPROT1_FW1BITS_Msk (0xffffffffUL) /*!< FW1BITS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FLASHRPROT0 ====================================================== */ +#define MCUCTRL_FLASHRPROT0_FR0BITS_Pos (0UL) /*!< FR0BITS (Bit 0) */ +#define MCUCTRL_FLASHRPROT0_FR0BITS_Msk (0xffffffffUL) /*!< FR0BITS (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FLASHRPROT1 ====================================================== */ +#define MCUCTRL_FLASHRPROT1_FR1BITS_Pos (0UL) /*!< FR1BITS (Bit 0) */ +#define MCUCTRL_FLASHRPROT1_FR1BITS_Msk (0xffffffffUL) /*!< FR1BITS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */ +#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Pos (0UL) /*!< DMA_WPROT0 (Bit 0) */ +#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Msk (0xffffffffUL) /*!< DMA_WPROT0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */ +#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Pos (0UL) /*!< DMA_WPROT1 (Bit 0) */ +#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Msk (0xffffUL) /*!< DMA_WPROT1 (Bitfield-Mask: 0xffff) */ +/* ================================================== DMASRAMREADPROTECT0 ================================================== */ +#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Pos (0UL) /*!< DMA_RPROT0 (Bit 0) */ +#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Msk (0xffffffffUL) /*!< DMA_RPROT0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DMASRAMREADPROTECT1 ================================================== */ +#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Pos (0UL) /*!< DMA_RPROT1 (Bit 0) */ +#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Msk (0xffffUL) /*!< DMA_RPROT1 (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ MSPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define MSPI_CTRL_XFERBYTES_Pos (16UL) /*!< XFERBYTES (Bit 16) */ +#define MSPI_CTRL_XFERBYTES_Msk (0xffff0000UL) /*!< XFERBYTES (Bitfield-Mask: 0xffff) */ +#define MSPI_CTRL_PIOSCRAMBLE_Pos (11UL) /*!< PIOSCRAMBLE (Bit 11) */ +#define MSPI_CTRL_PIOSCRAMBLE_Msk (0x800UL) /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_TXRX_Pos (10UL) /*!< TXRX (Bit 10) */ +#define MSPI_CTRL_TXRX_Msk (0x400UL) /*!< TXRX (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_SENDI_Pos (9UL) /*!< SENDI (Bit 9) */ +#define MSPI_CTRL_SENDI_Msk (0x200UL) /*!< SENDI (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_SENDA_Pos (8UL) /*!< SENDA (Bit 8) */ +#define MSPI_CTRL_SENDA_Msk (0x100UL) /*!< SENDA (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_ENTURN_Pos (7UL) /*!< ENTURN (Bit 7) */ +#define MSPI_CTRL_ENTURN_Msk (0x80UL) /*!< ENTURN (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_BIGENDIAN_Pos (6UL) /*!< BIGENDIAN (Bit 6) */ +#define MSPI_CTRL_BIGENDIAN_Msk (0x40UL) /*!< BIGENDIAN (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_QUADCMD_Pos (3UL) /*!< QUADCMD (Bit 3) */ +#define MSPI_CTRL_QUADCMD_Msk (0x8UL) /*!< QUADCMD (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_BUSY_Pos (2UL) /*!< BUSY (Bit 2) */ +#define MSPI_CTRL_BUSY_Msk (0x4UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_STATUS_Pos (1UL) /*!< STATUS (Bit 1) */ +#define MSPI_CTRL_STATUS_Msk (0x2UL) /*!< STATUS (Bitfield-Mask: 0x01) */ +#define MSPI_CTRL_START_Pos (0UL) /*!< START (Bit 0) */ +#define MSPI_CTRL_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================== CFG ========================================================== */ +#define MSPI_CFG_CPOL_Pos (17UL) /*!< CPOL (Bit 17) */ +#define MSPI_CFG_CPOL_Msk (0x20000UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_CPHA_Pos (16UL) /*!< CPHA (Bit 16) */ +#define MSPI_CFG_CPHA_Msk (0x10000UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_TURNAROUND_Pos (8UL) /*!< TURNAROUND (Bit 8) */ +#define MSPI_CFG_TURNAROUND_Msk (0x3f00UL) /*!< TURNAROUND (Bitfield-Mask: 0x3f) */ +#define MSPI_CFG_SEPIO_Pos (7UL) /*!< SEPIO (Bit 7) */ +#define MSPI_CFG_SEPIO_Msk (0x80UL) /*!< SEPIO (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_ISIZE_Pos (6UL) /*!< ISIZE (Bit 6) */ +#define MSPI_CFG_ISIZE_Msk (0x40UL) /*!< ISIZE (Bitfield-Mask: 0x01) */ +#define MSPI_CFG_ASIZE_Pos (4UL) /*!< ASIZE (Bit 4) */ +#define MSPI_CFG_ASIZE_Msk (0x30UL) /*!< ASIZE (Bitfield-Mask: 0x03) */ +#define MSPI_CFG_DEVCFG_Pos (0UL) /*!< DEVCFG (Bit 0) */ +#define MSPI_CFG_DEVCFG_Msk (0xfUL) /*!< DEVCFG (Bitfield-Mask: 0x0f) */ +/* ========================================================= ADDR ========================================================== */ +#define MSPI_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define MSPI_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INSTR ========================================================= */ +#define MSPI_INSTR_INSTR_Pos (0UL) /*!< INSTR (Bit 0) */ +#define MSPI_INSTR_INSTR_Msk (0xffffUL) /*!< INSTR (Bitfield-Mask: 0xffff) */ +/* ======================================================== TXFIFO ========================================================= */ +#define MSPI_TXFIFO_TXFIFO_Pos (0UL) /*!< TXFIFO (Bit 0) */ +#define MSPI_TXFIFO_TXFIFO_Msk (0xffffffffUL) /*!< TXFIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== RXFIFO ========================================================= */ +#define MSPI_RXFIFO_RXFIFO_Pos (0UL) /*!< RXFIFO (Bit 0) */ +#define MSPI_RXFIFO_RXFIFO_Msk (0xffffffffUL) /*!< RXFIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TXENTRIES ======================================================= */ +#define MSPI_TXENTRIES_TXENTRIES_Pos (0UL) /*!< TXENTRIES (Bit 0) */ +#define MSPI_TXENTRIES_TXENTRIES_Msk (0x1fUL) /*!< TXENTRIES (Bitfield-Mask: 0x1f) */ +/* ======================================================= RXENTRIES ======================================================= */ +#define MSPI_RXENTRIES_RXENTRIES_Pos (0UL) /*!< RXENTRIES (Bit 0) */ +#define MSPI_RXENTRIES_RXENTRIES_Msk (0x1fUL) /*!< RXENTRIES (Bitfield-Mask: 0x1f) */ +/* ======================================================= THRESHOLD ======================================================= */ +#define MSPI_THRESHOLD_RXTHRESH_Pos (8UL) /*!< RXTHRESH (Bit 8) */ +#define MSPI_THRESHOLD_RXTHRESH_Msk (0x1f00UL) /*!< RXTHRESH (Bitfield-Mask: 0x1f) */ +#define MSPI_THRESHOLD_TXTHRESH_Pos (0UL) /*!< TXTHRESH (Bit 0) */ +#define MSPI_THRESHOLD_TXTHRESH_Msk (0x1fUL) /*!< TXTHRESH (Bitfield-Mask: 0x1f) */ +/* ======================================================== MSPICFG ======================================================== */ +#define MSPI_MSPICFG_PRSTN_Pos (31UL) /*!< PRSTN (Bit 31) */ +#define MSPI_MSPICFG_PRSTN_Msk (0x80000000UL) /*!< PRSTN (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_IPRSTN_Pos (30UL) /*!< IPRSTN (Bit 30) */ +#define MSPI_MSPICFG_IPRSTN_Msk (0x40000000UL) /*!< IPRSTN (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_FIFORESET_Pos (29UL) /*!< FIFORESET (Bit 29) */ +#define MSPI_MSPICFG_FIFORESET_Msk (0x20000000UL) /*!< FIFORESET (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_CLKDIV_Pos (8UL) /*!< CLKDIV (Bit 8) */ +#define MSPI_MSPICFG_CLKDIV_Msk (0x3f00UL) /*!< CLKDIV (Bitfield-Mask: 0x3f) */ +#define MSPI_MSPICFG_IOMSEL_Pos (4UL) /*!< IOMSEL (Bit 4) */ +#define MSPI_MSPICFG_IOMSEL_Msk (0x70UL) /*!< IOMSEL (Bitfield-Mask: 0x07) */ +#define MSPI_MSPICFG_TXNEG_Pos (3UL) /*!< TXNEG (Bit 3) */ +#define MSPI_MSPICFG_TXNEG_Msk (0x8UL) /*!< TXNEG (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_RXNEG_Pos (2UL) /*!< RXNEG (Bit 2) */ +#define MSPI_MSPICFG_RXNEG_Msk (0x4UL) /*!< RXNEG (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_RXCAP_Pos (1UL) /*!< RXCAP (Bit 1) */ +#define MSPI_MSPICFG_RXCAP_Msk (0x2UL) /*!< RXCAP (Bitfield-Mask: 0x01) */ +#define MSPI_MSPICFG_APBCLK_Pos (0UL) /*!< APBCLK (Bit 0) */ +#define MSPI_MSPICFG_APBCLK_Msk (0x1UL) /*!< APBCLK (Bitfield-Mask: 0x01) */ +/* ======================================================== PADCFG ========================================================= */ +#define MSPI_PADCFG_REVCS_Pos (21UL) /*!< REVCS (Bit 21) */ +#define MSPI_PADCFG_REVCS_Msk (0x200000UL) /*!< REVCS (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN3_Pos (20UL) /*!< IN3 (Bit 20) */ +#define MSPI_PADCFG_IN3_Msk (0x100000UL) /*!< IN3 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN2_Pos (19UL) /*!< IN2 (Bit 19) */ +#define MSPI_PADCFG_IN2_Msk (0x80000UL) /*!< IN2 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN1_Pos (18UL) /*!< IN1 (Bit 18) */ +#define MSPI_PADCFG_IN1_Msk (0x40000UL) /*!< IN1 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_IN0_Pos (16UL) /*!< IN0 (Bit 16) */ +#define MSPI_PADCFG_IN0_Msk (0x30000UL) /*!< IN0 (Bitfield-Mask: 0x03) */ +#define MSPI_PADCFG_OUT7_Pos (4UL) /*!< OUT7 (Bit 4) */ +#define MSPI_PADCFG_OUT7_Msk (0x10UL) /*!< OUT7 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT6_Pos (3UL) /*!< OUT6 (Bit 3) */ +#define MSPI_PADCFG_OUT6_Msk (0x8UL) /*!< OUT6 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT5_Pos (2UL) /*!< OUT5 (Bit 2) */ +#define MSPI_PADCFG_OUT5_Msk (0x4UL) /*!< OUT5 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT4_Pos (1UL) /*!< OUT4 (Bit 1) */ +#define MSPI_PADCFG_OUT4_Msk (0x2UL) /*!< OUT4 (Bitfield-Mask: 0x01) */ +#define MSPI_PADCFG_OUT3_Pos (0UL) /*!< OUT3 (Bit 0) */ +#define MSPI_PADCFG_OUT3_Msk (0x1UL) /*!< OUT3 (Bitfield-Mask: 0x01) */ +/* ======================================================= PADOUTEN ======================================================== */ +#define MSPI_PADOUTEN_OUTEN_Pos (0UL) /*!< OUTEN (Bit 0) */ +#define MSPI_PADOUTEN_OUTEN_Msk (0x1ffUL) /*!< OUTEN (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FLASH ========================================================= */ +#define MSPI_FLASH_READINSTR_Pos (24UL) /*!< READINSTR (Bit 24) */ +#define MSPI_FLASH_READINSTR_Msk (0xff000000UL) /*!< READINSTR (Bitfield-Mask: 0xff) */ +#define MSPI_FLASH_WRITEINSTR_Pos (16UL) /*!< WRITEINSTR (Bit 16) */ +#define MSPI_FLASH_WRITEINSTR_Msk (0xff0000UL) /*!< WRITEINSTR (Bitfield-Mask: 0xff) */ +#define MSPI_FLASH_XIPMIXED_Pos (8UL) /*!< XIPMIXED (Bit 8) */ +#define MSPI_FLASH_XIPMIXED_Msk (0x700UL) /*!< XIPMIXED (Bitfield-Mask: 0x07) */ +#define MSPI_FLASH_XIPSENDI_Pos (7UL) /*!< XIPSENDI (Bit 7) */ +#define MSPI_FLASH_XIPSENDI_Msk (0x80UL) /*!< XIPSENDI (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPSENDA_Pos (6UL) /*!< XIPSENDA (Bit 6) */ +#define MSPI_FLASH_XIPSENDA_Msk (0x40UL) /*!< XIPSENDA (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPENTURN_Pos (5UL) /*!< XIPENTURN (Bit 5) */ +#define MSPI_FLASH_XIPENTURN_Msk (0x20UL) /*!< XIPENTURN (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPBIGENDIAN_Pos (4UL) /*!< XIPBIGENDIAN (Bit 4) */ +#define MSPI_FLASH_XIPBIGENDIAN_Msk (0x10UL) /*!< XIPBIGENDIAN (Bitfield-Mask: 0x01) */ +#define MSPI_FLASH_XIPACK_Pos (2UL) /*!< XIPACK (Bit 2) */ +#define MSPI_FLASH_XIPACK_Msk (0xcUL) /*!< XIPACK (Bitfield-Mask: 0x03) */ +#define MSPI_FLASH_XIPEN_Pos (0UL) /*!< XIPEN (Bit 0) */ +#define MSPI_FLASH_XIPEN_Msk (0x1UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCRAMBLING ======================================================= */ +#define MSPI_SCRAMBLING_SCRENABLE_Pos (31UL) /*!< SCRENABLE (Bit 31) */ +#define MSPI_SCRAMBLING_SCRENABLE_Msk (0x80000000UL) /*!< SCRENABLE (Bitfield-Mask: 0x01) */ +#define MSPI_SCRAMBLING_SCREND_Pos (16UL) /*!< SCREND (Bit 16) */ +#define MSPI_SCRAMBLING_SCREND_Msk (0x3ff0000UL) /*!< SCREND (Bitfield-Mask: 0x3ff) */ +#define MSPI_SCRAMBLING_SCRSTART_Pos (0UL) /*!< SCRSTART (Bit 0) */ +#define MSPI_SCRAMBLING_SCRSTART_Msk (0x3ffUL) /*!< SCRSTART (Bitfield-Mask: 0x3ff) */ +/* ========================================================= INTEN ========================================================= */ +#define MSPI_INTEN_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTEN_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTEN_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTEN_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTEN_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTEN_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTEN_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTEN_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTEN_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTEN_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTEN_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTEN_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTEN_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define MSPI_INTSTAT_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTSTAT_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTSTAT_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTSTAT_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTSTAT_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTSTAT_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTSTAT_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTSTAT_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTSTAT_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTSTAT_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTSTAT_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTSTAT_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTSTAT_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define MSPI_INTCLR_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTCLR_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTCLR_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTCLR_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTCLR_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTCLR_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTCLR_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTCLR_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTCLR_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTCLR_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTCLR_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTCLR_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTCLR_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define MSPI_INTSET_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */ +#define MSPI_INTSET_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */ +#define MSPI_INTSET_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */ +#define MSPI_INTSET_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */ +#define MSPI_INTSET_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */ +#define MSPI_INTSET_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_DERR_Pos (7UL) /*!< DERR (Bit 7) */ +#define MSPI_INTSET_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */ +#define MSPI_INTSET_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_RXF_Pos (5UL) /*!< RXF (Bit 5) */ +#define MSPI_INTSET_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_RXO_Pos (4UL) /*!< RXO (Bit 4) */ +#define MSPI_INTSET_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_RXU_Pos (3UL) /*!< RXU (Bit 3) */ +#define MSPI_INTSET_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_TXO_Pos (2UL) /*!< TXO (Bit 2) */ +#define MSPI_INTSET_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_TXE_Pos (1UL) /*!< TXE (Bit 1) */ +#define MSPI_INTSET_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define MSPI_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ +#define MSPI_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define MSPI_DMACFG_DMAPWROFF_Pos (18UL) /*!< DMAPWROFF (Bit 18) */ +#define MSPI_DMACFG_DMAPWROFF_Msk (0x40000UL) /*!< DMAPWROFF (Bitfield-Mask: 0x01) */ +#define MSPI_DMACFG_DMAPRI_Pos (3UL) /*!< DMAPRI (Bit 3) */ +#define MSPI_DMACFG_DMAPRI_Msk (0x18UL) /*!< DMAPRI (Bitfield-Mask: 0x03) */ +#define MSPI_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */ +#define MSPI_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define MSPI_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define MSPI_DMACFG_DMAEN_Msk (0x3UL) /*!< DMAEN (Bitfield-Mask: 0x03) */ +/* ======================================================== DMASTAT ======================================================== */ +#define MSPI_DMASTAT_SCRERR_Pos (3UL) /*!< SCRERR (Bit 3) */ +#define MSPI_DMASTAT_SCRERR_Msk (0x8UL) /*!< SCRERR (Bitfield-Mask: 0x01) */ +#define MSPI_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define MSPI_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define MSPI_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define MSPI_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define MSPI_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define MSPI_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define MSPI_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */ +#define MSPI_DMATARGADDR_TARGADDR_Msk (0xffffffffUL) /*!< TARGADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DMADEVADDR ======================================================= */ +#define MSPI_DMADEVADDR_DEVADDR_Pos (0UL) /*!< DEVADDR (Bit 0) */ +#define MSPI_DMADEVADDR_DEVADDR_Msk (0xffffffffUL) /*!< DEVADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define MSPI_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define MSPI_DMATOTCOUNT_TOTCOUNT_Msk (0xffffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= DMABCOUNT ======================================================= */ +#define MSPI_DMABCOUNT_BCOUNT_Pos (0UL) /*!< BCOUNT (Bit 0) */ +#define MSPI_DMABCOUNT_BCOUNT_Msk (0xffUL) /*!< BCOUNT (Bitfield-Mask: 0xff) */ +/* ======================================================= DMATHRESH ======================================================= */ +#define MSPI_DMATHRESH_DMATHRESH_Pos (0UL) /*!< DMATHRESH (Bit 0) */ +#define MSPI_DMATHRESH_DMATHRESH_Msk (0xfUL) /*!< DMATHRESH (Bitfield-Mask: 0x0f) */ +/* ========================================================= CQCFG ========================================================= */ +#define MSPI_CQCFG_CQAUTOCLEARMASK_Pos (3UL) /*!< CQAUTOCLEARMASK (Bit 3) */ +#define MSPI_CQCFG_CQAUTOCLEARMASK_Msk (0x8UL) /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01) */ +#define MSPI_CQCFG_CQPWROFF_Pos (2UL) /*!< CQPWROFF (Bit 2) */ +#define MSPI_CQCFG_CQPWROFF_Msk (0x4UL) /*!< CQPWROFF (Bitfield-Mask: 0x01) */ +#define MSPI_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */ +#define MSPI_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */ +#define MSPI_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */ +#define MSPI_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CQADDR ========================================================= */ +#define MSPI_CQADDR_CQADDR_Pos (0UL) /*!< CQADDR (Bit 0) */ +#define MSPI_CQADDR_CQADDR_Msk (0x1fffffffUL) /*!< CQADDR (Bitfield-Mask: 0x1fffffff) */ +/* ======================================================== CQSTAT ========================================================= */ +#define MSPI_CQSTAT_CQPAUSED_Pos (3UL) /*!< CQPAUSED (Bit 3) */ +#define MSPI_CQSTAT_CQPAUSED_Msk (0x8UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */ +#define MSPI_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */ +#define MSPI_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */ +#define MSPI_CQSTAT_CQCPL_Pos (1UL) /*!< CQCPL (Bit 1) */ +#define MSPI_CQSTAT_CQCPL_Msk (0x2UL) /*!< CQCPL (Bitfield-Mask: 0x01) */ +#define MSPI_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */ +#define MSPI_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */ +/* ======================================================== CQFLAGS ======================================================== */ +#define MSPI_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */ +#define MSPI_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CQSETCLEAR ======================================================= */ +#define MSPI_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */ +#define MSPI_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */ +#define MSPI_CQSETCLEAR_CQFTOGGLE_Pos (8UL) /*!< CQFTOGGLE (Bit 8) */ +#define MSPI_CQSETCLEAR_CQFTOGGLE_Msk (0xff00UL) /*!< CQFTOGGLE (Bitfield-Mask: 0xff) */ +#define MSPI_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */ +#define MSPI_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== CQPAUSE ======================================================== */ +#define MSPI_CQPAUSE_CQMASK_Pos (0UL) /*!< CQMASK (Bit 0) */ +#define MSPI_CQPAUSE_CQMASK_Msk (0xffffUL) /*!< CQMASK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CQCURIDX ======================================================== */ +#define MSPI_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */ +#define MSPI_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */ +/* ======================================================= CQENDIDX ======================================================== */ +#define MSPI_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */ +#define MSPI_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCFG ========================================================== */ +#define PDM_PCFG_LRSWAP_Pos (31UL) /*!< LRSWAP (Bit 31) */ +#define PDM_PCFG_LRSWAP_Msk (0x80000000UL) /*!< LRSWAP (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_PGARIGHT_Pos (26UL) /*!< PGARIGHT (Bit 26) */ +#define PDM_PCFG_PGARIGHT_Msk (0x7c000000UL) /*!< PGARIGHT (Bitfield-Mask: 0x1f) */ +#define PDM_PCFG_PGALEFT_Pos (21UL) /*!< PGALEFT (Bit 21) */ +#define PDM_PCFG_PGALEFT_Msk (0x3e00000UL) /*!< PGALEFT (Bitfield-Mask: 0x1f) */ +#define PDM_PCFG_MCLKDIV_Pos (17UL) /*!< MCLKDIV (Bit 17) */ +#define PDM_PCFG_MCLKDIV_Msk (0x60000UL) /*!< MCLKDIV (Bitfield-Mask: 0x03) */ +#define PDM_PCFG_SINCRATE_Pos (10UL) /*!< SINCRATE (Bit 10) */ +#define PDM_PCFG_SINCRATE_Msk (0x1fc00UL) /*!< SINCRATE (Bitfield-Mask: 0x7f) */ +#define PDM_PCFG_ADCHPD_Pos (9UL) /*!< ADCHPD (Bit 9) */ +#define PDM_PCFG_ADCHPD_Msk (0x200UL) /*!< ADCHPD (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_HPCUTOFF_Pos (5UL) /*!< HPCUTOFF (Bit 5) */ +#define PDM_PCFG_HPCUTOFF_Msk (0x1e0UL) /*!< HPCUTOFF (Bitfield-Mask: 0x0f) */ +#define PDM_PCFG_CYCLES_Pos (2UL) /*!< CYCLES (Bit 2) */ +#define PDM_PCFG_CYCLES_Msk (0x1cUL) /*!< CYCLES (Bitfield-Mask: 0x07) */ +#define PDM_PCFG_SOFTMUTE_Pos (1UL) /*!< SOFTMUTE (Bit 1) */ +#define PDM_PCFG_SOFTMUTE_Msk (0x2UL) /*!< SOFTMUTE (Bitfield-Mask: 0x01) */ +#define PDM_PCFG_PDMCOREEN_Pos (0UL) /*!< PDMCOREEN (Bit 0) */ +#define PDM_PCFG_PDMCOREEN_Msk (0x1UL) /*!< PDMCOREEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VCFG ========================================================== */ +#define PDM_VCFG_IOCLKEN_Pos (31UL) /*!< IOCLKEN (Bit 31) */ +#define PDM_VCFG_IOCLKEN_Msk (0x80000000UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_RSTB_Pos (30UL) /*!< RSTB (Bit 30) */ +#define PDM_VCFG_RSTB_Msk (0x40000000UL) /*!< RSTB (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_PDMCLKSEL_Pos (27UL) /*!< PDMCLKSEL (Bit 27) */ +#define PDM_VCFG_PDMCLKSEL_Msk (0x38000000UL) /*!< PDMCLKSEL (Bitfield-Mask: 0x07) */ +#define PDM_VCFG_PDMCLKEN_Pos (26UL) /*!< PDMCLKEN (Bit 26) */ +#define PDM_VCFG_PDMCLKEN_Msk (0x4000000UL) /*!< PDMCLKEN (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_I2SEN_Pos (20UL) /*!< I2SEN (Bit 20) */ +#define PDM_VCFG_I2SEN_Msk (0x100000UL) /*!< I2SEN (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_BCLKINV_Pos (19UL) /*!< BCLKINV (Bit 19) */ +#define PDM_VCFG_BCLKINV_Msk (0x80000UL) /*!< BCLKINV (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_DMICKDEL_Pos (17UL) /*!< DMICKDEL (Bit 17) */ +#define PDM_VCFG_DMICKDEL_Msk (0x20000UL) /*!< DMICKDEL (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_SELAP_Pos (16UL) /*!< SELAP (Bit 16) */ +#define PDM_VCFG_SELAP_Msk (0x10000UL) /*!< SELAP (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_PCMPACK_Pos (8UL) /*!< PCMPACK (Bit 8) */ +#define PDM_VCFG_PCMPACK_Msk (0x100UL) /*!< PCMPACK (Bitfield-Mask: 0x01) */ +#define PDM_VCFG_CHSET_Pos (3UL) /*!< CHSET (Bit 3) */ +#define PDM_VCFG_CHSET_Msk (0x18UL) /*!< CHSET (Bitfield-Mask: 0x03) */ +/* ======================================================= VOICESTAT ======================================================= */ +#define PDM_VOICESTAT_FIFOCNT_Pos (0UL) /*!< FIFOCNT (Bit 0) */ +#define PDM_VOICESTAT_FIFOCNT_Msk (0x3fUL) /*!< FIFOCNT (Bitfield-Mask: 0x3f) */ +/* ======================================================= FIFOREAD ======================================================== */ +#define PDM_FIFOREAD_FIFOREAD_Pos (0UL) /*!< FIFOREAD (Bit 0) */ +#define PDM_FIFOREAD_FIFOREAD_Msk (0xffffffffUL) /*!< FIFOREAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FIFOFLUSH ======================================================= */ +#define PDM_FIFOFLUSH_FIFOFLUSH_Pos (0UL) /*!< FIFOFLUSH (Bit 0) */ +#define PDM_FIFOFLUSH_FIFOFLUSH_Msk (0x1UL) /*!< FIFOFLUSH (Bitfield-Mask: 0x01) */ +/* ======================================================== FIFOTHR ======================================================== */ +#define PDM_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */ +#define PDM_FIFOTHR_FIFOTHR_Msk (0x1fUL) /*!< FIFOTHR (Bitfield-Mask: 0x1f) */ +/* ========================================================= INTEN ========================================================= */ +#define PDM_INTEN_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTEN_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTEN_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTEN_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTEN_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTEN_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTEN_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define PDM_INTSTAT_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTSTAT_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTSTAT_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTSTAT_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTSTAT_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTSTAT_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTSTAT_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define PDM_INTCLR_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTCLR_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTCLR_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTCLR_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTCLR_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTCLR_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTCLR_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define PDM_INTSET_DERR_Pos (4UL) /*!< DERR (Bit 4) */ +#define PDM_INTSET_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */ +#define PDM_INTSET_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */ +#define PDM_INTSET_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_OVF_Pos (1UL) /*!< OVF (Bit 1) */ +#define PDM_INTSET_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ +#define PDM_INTSET_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define PDM_INTSET_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */ +/* ======================================================= DMATRIGEN ======================================================= */ +#define PDM_DMATRIGEN_DTHR90_Pos (1UL) /*!< DTHR90 (Bit 1) */ +#define PDM_DMATRIGEN_DTHR90_Msk (0x2UL) /*!< DTHR90 (Bitfield-Mask: 0x01) */ +#define PDM_DMATRIGEN_DTHR_Pos (0UL) /*!< DTHR (Bit 0) */ +#define PDM_DMATRIGEN_DTHR_Msk (0x1UL) /*!< DTHR (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +#define PDM_DMATRIGSTAT_DTHR90STAT_Pos (1UL) /*!< DTHR90STAT (Bit 1) */ +#define PDM_DMATRIGSTAT_DTHR90STAT_Msk (0x2UL) /*!< DTHR90STAT (Bitfield-Mask: 0x01) */ +#define PDM_DMATRIGSTAT_DTHRSTAT_Pos (0UL) /*!< DTHRSTAT (Bit 0) */ +#define PDM_DMATRIGSTAT_DTHRSTAT_Msk (0x1UL) /*!< DTHRSTAT (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACFG ========================================================= */ +#define PDM_DMACFG_DPWROFF_Pos (10UL) /*!< DPWROFF (Bit 10) */ +#define PDM_DMACFG_DPWROFF_Msk (0x400UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DAUTOHIP_Pos (9UL) /*!< DAUTOHIP (Bit 9) */ +#define PDM_DMACFG_DAUTOHIP_Msk (0x200UL) /*!< DAUTOHIP (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */ +#define PDM_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */ +#define PDM_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */ +#define PDM_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */ +#define PDM_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +#define PDM_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */ +#define PDM_DMATOTCOUNT_TOTCOUNT_Msk (0xfffffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfffff) */ +/* ====================================================== DMATARGADDR ====================================================== */ +#define PDM_DMATARGADDR_UTARGADDR_Pos (20UL) /*!< UTARGADDR (Bit 20) */ +#define PDM_DMATARGADDR_UTARGADDR_Msk (0xfff00000UL) /*!< UTARGADDR (Bitfield-Mask: 0xfff) */ +#define PDM_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< LTARGADDR (Bit 0) */ +#define PDM_DMATARGADDR_LTARGADDR_Msk (0xfffffUL) /*!< LTARGADDR (Bitfield-Mask: 0xfffff) */ +/* ======================================================== DMASTAT ======================================================== */ +#define PDM_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */ +#define PDM_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */ +#define PDM_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */ +#define PDM_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */ +#define PDM_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */ +#define PDM_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SUPPLYSRC ======================================================= */ +#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Pos (0UL) /*!< BLEBUCKEN (Bit 0) */ +#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Msk (0x1UL) /*!< BLEBUCKEN (Bitfield-Mask: 0x01) */ +/* ===================================================== SUPPLYSTATUS ====================================================== */ +#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Pos (1UL) /*!< BLEBUCKON (Bit 1) */ +#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Msk (0x2UL) /*!< BLEBUCKON (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Pos (0UL) /*!< SIMOBUCKON (Bit 0) */ +#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Msk (0x1UL) /*!< SIMOBUCKON (Bitfield-Mask: 0x01) */ +/* ======================================================= DEVPWREN ======================================================== */ +#define PWRCTRL_DEVPWREN_PWRBLEL_Pos (13UL) /*!< PWRBLEL (Bit 13) */ +#define PWRCTRL_DEVPWREN_PWRBLEL_Msk (0x2000UL) /*!< PWRBLEL (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRPDM_Pos (12UL) /*!< PWRPDM (Bit 12) */ +#define PWRCTRL_DEVPWREN_PWRPDM_Msk (0x1000UL) /*!< PWRPDM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRMSPI_Pos (11UL) /*!< PWRMSPI (Bit 11) */ +#define PWRCTRL_DEVPWREN_PWRMSPI_Msk (0x800UL) /*!< PWRMSPI (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRSCARD_Pos (10UL) /*!< PWRSCARD (Bit 10) */ +#define PWRCTRL_DEVPWREN_PWRSCARD_Msk (0x400UL) /*!< PWRSCARD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRADC_Pos (9UL) /*!< PWRADC (Bit 9) */ +#define PWRCTRL_DEVPWREN_PWRADC_Msk (0x200UL) /*!< PWRADC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRUART1_Pos (8UL) /*!< PWRUART1 (Bit 8) */ +#define PWRCTRL_DEVPWREN_PWRUART1_Msk (0x100UL) /*!< PWRUART1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRUART0_Pos (7UL) /*!< PWRUART0 (Bit 7) */ +#define PWRCTRL_DEVPWREN_PWRUART0_Msk (0x80UL) /*!< PWRUART0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM5_Pos (6UL) /*!< PWRIOM5 (Bit 6) */ +#define PWRCTRL_DEVPWREN_PWRIOM5_Msk (0x40UL) /*!< PWRIOM5 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM4_Pos (5UL) /*!< PWRIOM4 (Bit 5) */ +#define PWRCTRL_DEVPWREN_PWRIOM4_Msk (0x20UL) /*!< PWRIOM4 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM3_Pos (4UL) /*!< PWRIOM3 (Bit 4) */ +#define PWRCTRL_DEVPWREN_PWRIOM3_Msk (0x10UL) /*!< PWRIOM3 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM2_Pos (3UL) /*!< PWRIOM2 (Bit 3) */ +#define PWRCTRL_DEVPWREN_PWRIOM2_Msk (0x8UL) /*!< PWRIOM2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM1_Pos (2UL) /*!< PWRIOM1 (Bit 2) */ +#define PWRCTRL_DEVPWREN_PWRIOM1_Msk (0x4UL) /*!< PWRIOM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOM0_Pos (1UL) /*!< PWRIOM0 (Bit 1) */ +#define PWRCTRL_DEVPWREN_PWRIOM0_Msk (0x2UL) /*!< PWRIOM0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREN_PWRIOS_Pos (0UL) /*!< PWRIOS (Bit 0) */ +#define PWRCTRL_DEVPWREN_PWRIOS_Msk (0x1UL) /*!< PWRIOS (Bitfield-Mask: 0x01) */ +/* ===================================================== MEMPWDINSLEEP ===================================================== */ +#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Pos (31UL) /*!< CACHEPWDSLP (Bit 31) */ +#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk (0x80000000UL) /*!< CACHEPWDSLP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Pos (14UL) /*!< FLASH1PWDSLP (Bit 14) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk (0x4000UL) /*!< FLASH1PWDSLP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Pos (13UL) /*!< FLASH0PWDSLP (Bit 13) */ +#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk (0x2000UL) /*!< FLASH0PWDSLP (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Pos (3UL) /*!< SRAMPWDSLP (Bit 3) */ +#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Msk (0x1ff8UL) /*!< SRAMPWDSLP (Bitfield-Mask: 0x3ff) */ +#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Pos (0UL) /*!< DTCMPWDSLP (Bit 0) */ +#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Msk (0x7UL) /*!< DTCMPWDSLP (Bitfield-Mask: 0x07) */ +/* ======================================================= MEMPWREN ======================================================== */ +#define PWRCTRL_MEMPWREN_CACHEB2_Pos (31UL) /*!< CACHEB2 (Bit 31) */ +#define PWRCTRL_MEMPWREN_CACHEB2_Msk (0x80000000UL) /*!< CACHEB2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_CACHEB0_Pos (30UL) /*!< CACHEB0 (Bit 30) */ +#define PWRCTRL_MEMPWREN_CACHEB0_Msk (0x40000000UL) /*!< CACHEB0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_FLASH1_Pos (14UL) /*!< FLASH1 (Bit 14) */ +#define PWRCTRL_MEMPWREN_FLASH1_Msk (0x4000UL) /*!< FLASH1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_FLASH0_Pos (13UL) /*!< FLASH0 (Bit 13) */ +#define PWRCTRL_MEMPWREN_FLASH0_Msk (0x2000UL) /*!< FLASH0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREN_SRAM_Pos (3UL) /*!< SRAM (Bit 3) */ +#define PWRCTRL_MEMPWREN_SRAM_Msk (0x1ff8UL) /*!< SRAM (Bitfield-Mask: 0x3ff) */ +#define PWRCTRL_MEMPWREN_DTCM_Pos (0UL) /*!< DTCM (Bit 0) */ +#define PWRCTRL_MEMPWREN_DTCM_Msk (0x7UL) /*!< DTCM (Bitfield-Mask: 0x07) */ +/* ===================================================== MEMPWRSTATUS ====================================================== */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Pos (16UL) /*!< CACHEB2 (Bit 16) */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Msk (0x10000UL) /*!< CACHEB2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Pos (15UL) /*!< CACHEB0 (Bit 15) */ +#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Msk (0x8000UL) /*!< CACHEB0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH1_Pos (14UL) /*!< FLASH1 (Bit 14) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH1_Msk (0x4000UL) /*!< FLASH1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH0_Pos (13UL) /*!< FLASH0 (Bit 13) */ +#define PWRCTRL_MEMPWRSTATUS_FLASH0_Msk (0x2000UL) /*!< FLASH0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM9_Pos (12UL) /*!< SRAM9 (Bit 12) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM9_Msk (0x1000UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM8_Pos (11UL) /*!< SRAM8 (Bit 11) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM8_Msk (0x800UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM7_Pos (10UL) /*!< SRAM7 (Bit 10) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM7_Msk (0x400UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM6_Pos (9UL) /*!< SRAM6 (Bit 9) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM6_Msk (0x200UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM5_Pos (8UL) /*!< SRAM5 (Bit 8) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM5_Msk (0x100UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM4_Pos (7UL) /*!< SRAM4 (Bit 7) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM4_Msk (0x80UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM3_Pos (6UL) /*!< SRAM3 (Bit 6) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM3_Msk (0x40UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM2_Pos (5UL) /*!< SRAM2 (Bit 5) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM2_Msk (0x20UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM1_Pos (4UL) /*!< SRAM1 (Bit 4) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM1_Msk (0x10UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM0_Pos (3UL) /*!< SRAM0 (Bit 3) */ +#define PWRCTRL_MEMPWRSTATUS_SRAM0_Msk (0x8UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM1_Pos (2UL) /*!< DTCM1 (Bit 2) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM1_Msk (0x4UL) /*!< DTCM1 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM01_Pos (1UL) /*!< DTCM01 (Bit 1) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM01_Msk (0x2UL) /*!< DTCM01 (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM00_Pos (0UL) /*!< DTCM00 (Bit 0) */ +#define PWRCTRL_MEMPWRSTATUS_DTCM00_Msk (0x1UL) /*!< DTCM00 (Bitfield-Mask: 0x01) */ +/* ===================================================== DEVPWRSTATUS ====================================================== */ +#define PWRCTRL_DEVPWRSTATUS_BLEH_Pos (9UL) /*!< BLEH (Bit 9) */ +#define PWRCTRL_DEVPWRSTATUS_BLEH_Msk (0x200UL) /*!< BLEH (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_BLEL_Pos (8UL) /*!< BLEL (Bit 8) */ +#define PWRCTRL_DEVPWRSTATUS_BLEL_Msk (0x100UL) /*!< BLEL (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Pos (7UL) /*!< PWRPDM (Bit 7) */ +#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk (0x80UL) /*!< PWRPDM (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Pos (6UL) /*!< PWRMSPI (Bit 6) */ +#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk (0x40UL) /*!< PWRMSPI (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_PWRADC_Pos (5UL) /*!< PWRADC (Bit 5) */ +#define PWRCTRL_DEVPWRSTATUS_PWRADC_Msk (0x20UL) /*!< PWRADC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_HCPC_Pos (4UL) /*!< HCPC (Bit 4) */ +#define PWRCTRL_DEVPWRSTATUS_HCPC_Msk (0x10UL) /*!< HCPC (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_HCPB_Pos (3UL) /*!< HCPB (Bit 3) */ +#define PWRCTRL_DEVPWRSTATUS_HCPB_Msk (0x8UL) /*!< HCPB (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_HCPA_Pos (2UL) /*!< HCPA (Bit 2) */ +#define PWRCTRL_DEVPWRSTATUS_HCPA_Msk (0x4UL) /*!< HCPA (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_MCUH_Pos (1UL) /*!< MCUH (Bit 1) */ +#define PWRCTRL_DEVPWRSTATUS_MCUH_Msk (0x2UL) /*!< MCUH (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWRSTATUS_MCUL_Pos (0UL) /*!< MCUL (Bit 0) */ +#define PWRCTRL_DEVPWRSTATUS_MCUL_Msk (0x1UL) /*!< MCUL (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMCTRL ======================================================== */ +#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL) /*!< SRAMLIGHTSLEEP (Bit 8) */ +#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL) /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff) */ +#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL) /*!< SRAMMASTERCLKGATE (Bit 2) */ +#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL) /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01) */ +#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos (1UL) /*!< SRAMCLKGATE (Bit 1) */ +#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk (0x2UL) /*!< SRAMCLKGATE (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCSTATUS ======================================================= */ +#define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos (5UL) /*!< REFBUFPWD (Bit 5) */ +#define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk (0x20UL) /*!< REFBUFPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos (4UL) /*!< REFKEEPPWD (Bit 4) */ +#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk (0x10UL) /*!< REFKEEPPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_VBATPWD_Pos (3UL) /*!< VBATPWD (Bit 3) */ +#define PWRCTRL_ADCSTATUS_VBATPWD_Msk (0x8UL) /*!< VBATPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_VPTATPWD_Pos (2UL) /*!< VPTATPWD (Bit 2) */ +#define PWRCTRL_ADCSTATUS_VPTATPWD_Msk (0x4UL) /*!< VPTATPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_BGTPWD_Pos (1UL) /*!< BGTPWD (Bit 1) */ +#define PWRCTRL_ADCSTATUS_BGTPWD_Msk (0x2UL) /*!< BGTPWD (Bitfield-Mask: 0x01) */ +#define PWRCTRL_ADCSTATUS_ADCPWD_Pos (0UL) /*!< ADCPWD (Bit 0) */ +#define PWRCTRL_ADCSTATUS_ADCPWD_Msk (0x1UL) /*!< ADCPWD (Bitfield-Mask: 0x01) */ +/* ========================================================= MISC ========================================================== */ +#define PWRCTRL_MISC_MEMVRLPBLE_Pos (6UL) /*!< MEMVRLPBLE (Bit 6) */ +#define PWRCTRL_MISC_MEMVRLPBLE_Msk (0x40UL) /*!< MEMVRLPBLE (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Pos (3UL) /*!< FORCEMEMVRLPTIMERS (Bit 3) */ +#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Msk (0x8UL) /*!< FORCEMEMVRLPTIMERS (Bitfield-Mask: 0x01) */ +/* ===================================================== DEVPWREVENTEN ===================================================== */ +#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Pos (31UL) /*!< BURSTEVEN (Bit 31) */ +#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Msk (0x80000000UL) /*!< BURSTEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Pos (30UL) /*!< BURSTFEATUREEVEN (Bit 30) */ +#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Msk (0x40000000UL) /*!< BURSTFEATUREEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Pos (29UL) /*!< BLEFEATUREEVEN (Bit 29) */ +#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Msk (0x20000000UL) /*!< BLEFEATUREEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Pos (8UL) /*!< BLELEVEN (Bit 8) */ +#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Msk (0x100UL) /*!< BLELEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Pos (7UL) /*!< PDMEVEN (Bit 7) */ +#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Msk (0x80UL) /*!< PDMEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL) /*!< MSPIEVEN (Bit 6) */ +#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL) /*!< MSPIEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL) /*!< ADCEVEN (Bit 5) */ +#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL) /*!< ADCEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL) /*!< HCPCEVEN (Bit 4) */ +#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL) /*!< HCPCEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL) /*!< HCPBEVEN (Bit 3) */ +#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL) /*!< HCPBEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL) /*!< HCPAEVEN (Bit 2) */ +#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL) /*!< HCPAEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL) /*!< MCUHEVEN (Bit 1) */ +#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL) /*!< MCUHEVEN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL) /*!< MCULEVEN (Bit 0) */ +#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL) /*!< MCULEVEN (Bitfield-Mask: 0x01) */ +/* ===================================================== MEMPWREVENTEN ===================================================== */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (31UL) /*!< CACHEB2EN (Bit 31) */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x80000000UL) /*!< CACHEB2EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (30UL) /*!< CACHEB0EN (Bit 30) */ +#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x40000000UL) /*!< CACHEB0EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Pos (14UL) /*!< FLASH1EN (Bit 14) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Msk (0x4000UL) /*!< FLASH1EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Pos (13UL) /*!< FLASH0EN (Bit 13) */ +#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Msk (0x2000UL) /*!< FLASH0EN (Bitfield-Mask: 0x01) */ +#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Pos (3UL) /*!< SRAMEN (Bit 3) */ +#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Msk (0x1ff8UL) /*!< SRAMEN (Bitfield-Mask: 0x3ff) */ +#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos (0UL) /*!< DTCMEN (Bit 0) */ +#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk (0x7UL) /*!< DTCMEN (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define RSTGEN_CFG_WDREN_Pos (1UL) /*!< WDREN (Bit 1) */ +#define RSTGEN_CFG_WDREN_Msk (0x2UL) /*!< WDREN (Bitfield-Mask: 0x01) */ +#define RSTGEN_CFG_BODHREN_Pos (0UL) /*!< BODHREN (Bit 0) */ +#define RSTGEN_CFG_BODHREN_Msk (0x1UL) /*!< BODHREN (Bitfield-Mask: 0x01) */ +/* ========================================================= SWPOI ========================================================= */ +#define RSTGEN_SWPOI_SWPOIKEY_Pos (0UL) /*!< SWPOIKEY (Bit 0) */ +#define RSTGEN_SWPOI_SWPOIKEY_Msk (0xffUL) /*!< SWPOIKEY (Bitfield-Mask: 0xff) */ +/* ========================================================= SWPOR ========================================================= */ +#define RSTGEN_SWPOR_SWPORKEY_Pos (0UL) /*!< SWPORKEY (Bit 0) */ +#define RSTGEN_SWPOR_SWPORKEY_Msk (0xffUL) /*!< SWPORKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TPIURST ======================================================== */ +#define RSTGEN_TPIURST_TPIURST_Pos (0UL) /*!< TPIURST (Bit 0) */ +#define RSTGEN_TPIURST_TPIURST_Msk (0x1UL) /*!< TPIURST (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define RSTGEN_INTEN_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTEN_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define RSTGEN_INTSTAT_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTSTAT_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define RSTGEN_INTCLR_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTCLR_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define RSTGEN_INTSET_BODH_Pos (0UL) /*!< BODH (Bit 0) */ +#define RSTGEN_INTSET_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define RSTGEN_STAT_SBOOT_Pos (31UL) /*!< SBOOT (Bit 31) */ +#define RSTGEN_STAT_SBOOT_Msk (0x80000000UL) /*!< SBOOT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_FBOOT_Pos (30UL) /*!< FBOOT (Bit 30) */ +#define RSTGEN_STAT_FBOOT_Msk (0x40000000UL) /*!< FBOOT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOBSTAT_Pos (10UL) /*!< BOBSTAT (Bit 10) */ +#define RSTGEN_STAT_BOBSTAT_Msk (0x400UL) /*!< BOBSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOFSTAT_Pos (9UL) /*!< BOFSTAT (Bit 9) */ +#define RSTGEN_STAT_BOFSTAT_Msk (0x200UL) /*!< BOFSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOCSTAT_Pos (8UL) /*!< BOCSTAT (Bit 8) */ +#define RSTGEN_STAT_BOCSTAT_Msk (0x100UL) /*!< BOCSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BOUSTAT_Pos (7UL) /*!< BOUSTAT (Bit 7) */ +#define RSTGEN_STAT_BOUSTAT_Msk (0x80UL) /*!< BOUSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_WDRSTAT_Pos (6UL) /*!< WDRSTAT (Bit 6) */ +#define RSTGEN_STAT_WDRSTAT_Msk (0x40UL) /*!< WDRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_DBGRSTAT_Pos (5UL) /*!< DBGRSTAT (Bit 5) */ +#define RSTGEN_STAT_DBGRSTAT_Msk (0x20UL) /*!< DBGRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_POIRSTAT_Pos (4UL) /*!< POIRSTAT (Bit 4) */ +#define RSTGEN_STAT_POIRSTAT_Msk (0x10UL) /*!< POIRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_SWRSTAT_Pos (3UL) /*!< SWRSTAT (Bit 3) */ +#define RSTGEN_STAT_SWRSTAT_Msk (0x8UL) /*!< SWRSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_BORSTAT_Pos (2UL) /*!< BORSTAT (Bit 2) */ +#define RSTGEN_STAT_BORSTAT_Msk (0x4UL) /*!< BORSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_PORSTAT_Pos (1UL) /*!< PORSTAT (Bit 1) */ +#define RSTGEN_STAT_PORSTAT_Msk (0x2UL) /*!< PORSTAT (Bitfield-Mask: 0x01) */ +#define RSTGEN_STAT_EXRSTAT_Pos (0UL) /*!< EXRSTAT (Bit 0) */ +#define RSTGEN_STAT_EXRSTAT_Msk (0x1UL) /*!< EXRSTAT (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLOW ========================================================= */ +#define RTC_CTRLOW_CTRHR_Pos (24UL) /*!< CTRHR (Bit 24) */ +#define RTC_CTRLOW_CTRHR_Msk (0x3f000000UL) /*!< CTRHR (Bitfield-Mask: 0x3f) */ +#define RTC_CTRLOW_CTRMIN_Pos (16UL) /*!< CTRMIN (Bit 16) */ +#define RTC_CTRLOW_CTRMIN_Msk (0x7f0000UL) /*!< CTRMIN (Bitfield-Mask: 0x7f) */ +#define RTC_CTRLOW_CTRSEC_Pos (8UL) /*!< CTRSEC (Bit 8) */ +#define RTC_CTRLOW_CTRSEC_Msk (0x7f00UL) /*!< CTRSEC (Bitfield-Mask: 0x7f) */ +#define RTC_CTRLOW_CTR100_Pos (0UL) /*!< CTR100 (Bit 0) */ +#define RTC_CTRLOW_CTR100_Msk (0xffUL) /*!< CTR100 (Bitfield-Mask: 0xff) */ +/* ========================================================= CTRUP ========================================================= */ +#define RTC_CTRUP_CTERR_Pos (31UL) /*!< CTERR (Bit 31) */ +#define RTC_CTRUP_CTERR_Msk (0x80000000UL) /*!< CTERR (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CEB_Pos (28UL) /*!< CEB (Bit 28) */ +#define RTC_CTRUP_CEB_Msk (0x10000000UL) /*!< CEB (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CB_Pos (27UL) /*!< CB (Bit 27) */ +#define RTC_CTRUP_CB_Msk (0x8000000UL) /*!< CB (Bitfield-Mask: 0x01) */ +#define RTC_CTRUP_CTRWKDY_Pos (24UL) /*!< CTRWKDY (Bit 24) */ +#define RTC_CTRUP_CTRWKDY_Msk (0x7000000UL) /*!< CTRWKDY (Bitfield-Mask: 0x07) */ +#define RTC_CTRUP_CTRYR_Pos (16UL) /*!< CTRYR (Bit 16) */ +#define RTC_CTRUP_CTRYR_Msk (0xff0000UL) /*!< CTRYR (Bitfield-Mask: 0xff) */ +#define RTC_CTRUP_CTRMO_Pos (8UL) /*!< CTRMO (Bit 8) */ +#define RTC_CTRUP_CTRMO_Msk (0x1f00UL) /*!< CTRMO (Bitfield-Mask: 0x1f) */ +#define RTC_CTRUP_CTRDATE_Pos (0UL) /*!< CTRDATE (Bit 0) */ +#define RTC_CTRUP_CTRDATE_Msk (0x3fUL) /*!< CTRDATE (Bitfield-Mask: 0x3f) */ +/* ======================================================== ALMLOW ========================================================= */ +#define RTC_ALMLOW_ALMHR_Pos (24UL) /*!< ALMHR (Bit 24) */ +#define RTC_ALMLOW_ALMHR_Msk (0x3f000000UL) /*!< ALMHR (Bitfield-Mask: 0x3f) */ +#define RTC_ALMLOW_ALMMIN_Pos (16UL) /*!< ALMMIN (Bit 16) */ +#define RTC_ALMLOW_ALMMIN_Msk (0x7f0000UL) /*!< ALMMIN (Bitfield-Mask: 0x7f) */ +#define RTC_ALMLOW_ALMSEC_Pos (8UL) /*!< ALMSEC (Bit 8) */ +#define RTC_ALMLOW_ALMSEC_Msk (0x7f00UL) /*!< ALMSEC (Bitfield-Mask: 0x7f) */ +#define RTC_ALMLOW_ALM100_Pos (0UL) /*!< ALM100 (Bit 0) */ +#define RTC_ALMLOW_ALM100_Msk (0xffUL) /*!< ALM100 (Bitfield-Mask: 0xff) */ +/* ========================================================= ALMUP ========================================================= */ +#define RTC_ALMUP_ALMWKDY_Pos (16UL) /*!< ALMWKDY (Bit 16) */ +#define RTC_ALMUP_ALMWKDY_Msk (0x70000UL) /*!< ALMWKDY (Bitfield-Mask: 0x07) */ +#define RTC_ALMUP_ALMMO_Pos (8UL) /*!< ALMMO (Bit 8) */ +#define RTC_ALMUP_ALMMO_Msk (0x1f00UL) /*!< ALMMO (Bitfield-Mask: 0x1f) */ +#define RTC_ALMUP_ALMDATE_Pos (0UL) /*!< ALMDATE (Bit 0) */ +#define RTC_ALMUP_ALMDATE_Msk (0x3fUL) /*!< ALMDATE (Bitfield-Mask: 0x3f) */ +/* ======================================================== RTCCTL ========================================================= */ +#define RTC_RTCCTL_HR1224_Pos (5UL) /*!< HR1224 (Bit 5) */ +#define RTC_RTCCTL_HR1224_Msk (0x20UL) /*!< HR1224 (Bitfield-Mask: 0x01) */ +#define RTC_RTCCTL_RSTOP_Pos (4UL) /*!< RSTOP (Bit 4) */ +#define RTC_RTCCTL_RSTOP_Msk (0x10UL) /*!< RSTOP (Bitfield-Mask: 0x01) */ +#define RTC_RTCCTL_RPT_Pos (1UL) /*!< RPT (Bit 1) */ +#define RTC_RTCCTL_RPT_Msk (0xeUL) /*!< RPT (Bitfield-Mask: 0x07) */ +#define RTC_RTCCTL_WRTC_Pos (0UL) /*!< WRTC (Bit 0) */ +#define RTC_RTCCTL_WRTC_Msk (0x1UL) /*!< WRTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define RTC_INTEN_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTEN_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define RTC_INTSTAT_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTSTAT_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define RTC_INTCLR_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTCLR_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define RTC_INTSET_ALM_Pos (0UL) /*!< ALM (Bit 0) */ +#define RTC_INTSET_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SCARD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SR =========================================================== */ +#define SCARD_SR_FHF_Pos (6UL) /*!< FHF (Bit 6) */ +#define SCARD_SR_FHF_Msk (0x40UL) /*!< FHF (Bitfield-Mask: 0x01) */ +#define SCARD_SR_FT2REND_Pos (5UL) /*!< FT2REND (Bit 5) */ +#define SCARD_SR_FT2REND_Msk (0x20UL) /*!< FT2REND (Bitfield-Mask: 0x01) */ +#define SCARD_SR_PE_Pos (4UL) /*!< PE (Bit 4) */ +#define SCARD_SR_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define SCARD_SR_OVR_Pos (3UL) /*!< OVR (Bit 3) */ +#define SCARD_SR_OVR_Msk (0x8UL) /*!< OVR (Bitfield-Mask: 0x01) */ +#define SCARD_SR_FER_Pos (2UL) /*!< FER (Bit 2) */ +#define SCARD_SR_FER_Msk (0x4UL) /*!< FER (Bitfield-Mask: 0x01) */ +#define SCARD_SR_TBERBF_Pos (1UL) /*!< TBERBF (Bit 1) */ +#define SCARD_SR_TBERBF_Msk (0x2UL) /*!< TBERBF (Bitfield-Mask: 0x01) */ +#define SCARD_SR_FNE_Pos (0UL) /*!< FNE (Bit 0) */ +#define SCARD_SR_FNE_Msk (0x1UL) /*!< FNE (Bitfield-Mask: 0x01) */ +/* ========================================================== IER ========================================================== */ +#define SCARD_IER_FHFEN_Pos (6UL) /*!< FHFEN (Bit 6) */ +#define SCARD_IER_FHFEN_Msk (0x40UL) /*!< FHFEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_FT2RENDEN_Pos (5UL) /*!< FT2RENDEN (Bit 5) */ +#define SCARD_IER_FT2RENDEN_Msk (0x20UL) /*!< FT2RENDEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_PEEN_Pos (4UL) /*!< PEEN (Bit 4) */ +#define SCARD_IER_PEEN_Msk (0x10UL) /*!< PEEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_OVREN_Pos (3UL) /*!< OVREN (Bit 3) */ +#define SCARD_IER_OVREN_Msk (0x8UL) /*!< OVREN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_FEREN_Pos (2UL) /*!< FEREN (Bit 2) */ +#define SCARD_IER_FEREN_Msk (0x4UL) /*!< FEREN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_TBERBFEN_Pos (1UL) /*!< TBERBFEN (Bit 1) */ +#define SCARD_IER_TBERBFEN_Msk (0x2UL) /*!< TBERBFEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER_FNEEN_Pos (0UL) /*!< FNEEN (Bit 0) */ +#define SCARD_IER_FNEEN_Msk (0x1UL) /*!< FNEEN (Bitfield-Mask: 0x01) */ +/* ========================================================== TCR ========================================================== */ +#define SCARD_TCR_DMAMD_Pos (7UL) /*!< DMAMD (Bit 7) */ +#define SCARD_TCR_DMAMD_Msk (0x80UL) /*!< DMAMD (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_FIP_Pos (6UL) /*!< FIP (Bit 6) */ +#define SCARD_TCR_FIP_Msk (0x40UL) /*!< FIP (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_AUTOCONV_Pos (5UL) /*!< AUTOCONV (Bit 5) */ +#define SCARD_TCR_AUTOCONV_Msk (0x20UL) /*!< AUTOCONV (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_PROT_Pos (4UL) /*!< PROT (Bit 4) */ +#define SCARD_TCR_PROT_Msk (0x10UL) /*!< PROT (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_TR_Pos (3UL) /*!< TR (Bit 3) */ +#define SCARD_TCR_TR_Msk (0x8UL) /*!< TR (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_LCT_Pos (2UL) /*!< LCT (Bit 2) */ +#define SCARD_TCR_LCT_Msk (0x4UL) /*!< LCT (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_SS_Pos (1UL) /*!< SS (Bit 1) */ +#define SCARD_TCR_SS_Msk (0x2UL) /*!< SS (Bitfield-Mask: 0x01) */ +#define SCARD_TCR_CONV_Pos (0UL) /*!< CONV (Bit 0) */ +#define SCARD_TCR_CONV_Msk (0x1UL) /*!< CONV (Bitfield-Mask: 0x01) */ +/* ========================================================== UCR ========================================================== */ +#define SCARD_UCR_RETXEN_Pos (3UL) /*!< RETXEN (Bit 3) */ +#define SCARD_UCR_RETXEN_Msk (0x8UL) /*!< RETXEN (Bitfield-Mask: 0x01) */ +#define SCARD_UCR_RSTIN_Pos (2UL) /*!< RSTIN (Bit 2) */ +#define SCARD_UCR_RSTIN_Msk (0x4UL) /*!< RSTIN (Bitfield-Mask: 0x01) */ +#define SCARD_UCR_RIU_Pos (1UL) /*!< RIU (Bit 1) */ +#define SCARD_UCR_RIU_Msk (0x2UL) /*!< RIU (Bitfield-Mask: 0x01) */ +#define SCARD_UCR_CST_Pos (0UL) /*!< CST (Bit 0) */ +#define SCARD_UCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SCARD_DR_DR_Pos (0UL) /*!< DR (Bit 0) */ +#define SCARD_DR_DR_Msk (0xffUL) /*!< DR (Bitfield-Mask: 0xff) */ +/* ========================================================= BPRL ========================================================== */ +#define SCARD_BPRL_BPRL_Pos (0UL) /*!< BPRL (Bit 0) */ +#define SCARD_BPRL_BPRL_Msk (0xffUL) /*!< BPRL (Bitfield-Mask: 0xff) */ +/* ========================================================= BPRH ========================================================== */ +#define SCARD_BPRH_BPRH_Pos (0UL) /*!< BPRH (Bit 0) */ +#define SCARD_BPRH_BPRH_Msk (0xfUL) /*!< BPRH (Bitfield-Mask: 0x0f) */ +/* ========================================================= UCR1 ========================================================== */ +#define SCARD_UCR1_ENLASTB_Pos (5UL) /*!< ENLASTB (Bit 5) */ +#define SCARD_UCR1_ENLASTB_Msk (0x20UL) /*!< ENLASTB (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_CLKIOV_Pos (4UL) /*!< CLKIOV (Bit 4) */ +#define SCARD_UCR1_CLKIOV_Msk (0x10UL) /*!< CLKIOV (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_T1PAREN_Pos (3UL) /*!< T1PAREN (Bit 3) */ +#define SCARD_UCR1_T1PAREN_Msk (0x8UL) /*!< T1PAREN (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_STSP_Pos (2UL) /*!< STSP (Bit 2) */ +#define SCARD_UCR1_STSP_Msk (0x4UL) /*!< STSP (Bitfield-Mask: 0x01) */ +#define SCARD_UCR1_PR_Pos (0UL) /*!< PR (Bit 0) */ +#define SCARD_UCR1_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ +/* ========================================================== SR1 ========================================================== */ +#define SCARD_SR1_IDLE_Pos (3UL) /*!< IDLE (Bit 3) */ +#define SCARD_SR1_IDLE_Msk (0x8UL) /*!< IDLE (Bitfield-Mask: 0x01) */ +#define SCARD_SR1_SYNCEND_Pos (2UL) /*!< SYNCEND (Bit 2) */ +#define SCARD_SR1_SYNCEND_Msk (0x4UL) /*!< SYNCEND (Bitfield-Mask: 0x01) */ +#define SCARD_SR1_PRL_Pos (1UL) /*!< PRL (Bit 1) */ +#define SCARD_SR1_PRL_Msk (0x2UL) /*!< PRL (Bitfield-Mask: 0x01) */ +#define SCARD_SR1_ECNTOVER_Pos (0UL) /*!< ECNTOVER (Bit 0) */ +#define SCARD_SR1_ECNTOVER_Msk (0x1UL) /*!< ECNTOVER (Bitfield-Mask: 0x01) */ +/* ========================================================= IER1 ========================================================== */ +#define SCARD_IER1_SYNCENDEN_Pos (2UL) /*!< SYNCENDEN (Bit 2) */ +#define SCARD_IER1_SYNCENDEN_Msk (0x4UL) /*!< SYNCENDEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER1_PRLEN_Pos (1UL) /*!< PRLEN (Bit 1) */ +#define SCARD_IER1_PRLEN_Msk (0x2UL) /*!< PRLEN (Bitfield-Mask: 0x01) */ +#define SCARD_IER1_ECNTOVEREN_Pos (0UL) /*!< ECNTOVEREN (Bit 0) */ +#define SCARD_IER1_ECNTOVEREN_Msk (0x1UL) /*!< ECNTOVEREN (Bitfield-Mask: 0x01) */ +/* ========================================================= ECNTL ========================================================= */ +#define SCARD_ECNTL_ECNTL_Pos (0UL) /*!< ECNTL (Bit 0) */ +#define SCARD_ECNTL_ECNTL_Msk (0xffUL) /*!< ECNTL (Bitfield-Mask: 0xff) */ +/* ========================================================= ECNTH ========================================================= */ +#define SCARD_ECNTH_ECNTH_Pos (0UL) /*!< ECNTH (Bit 0) */ +#define SCARD_ECNTH_ECNTH_Msk (0xffUL) /*!< ECNTH (Bitfield-Mask: 0xff) */ +/* ========================================================== GTR ========================================================== */ +#define SCARD_GTR_GTR_Pos (0UL) /*!< GTR (Bit 0) */ +#define SCARD_GTR_GTR_Msk (0xffUL) /*!< GTR (Bitfield-Mask: 0xff) */ +/* ======================================================== RETXCNT ======================================================== */ +#define SCARD_RETXCNT_RETXCNT_Pos (0UL) /*!< RETXCNT (Bit 0) */ +#define SCARD_RETXCNT_RETXCNT_Msk (0xfUL) /*!< RETXCNT (Bitfield-Mask: 0x0f) */ +/* ====================================================== RETXCNTRMI ======================================================= */ +#define SCARD_RETXCNTRMI_RETXCNTRMI_Pos (0UL) /*!< RETXCNTRMI (Bit 0) */ +#define SCARD_RETXCNTRMI_RETXCNTRMI_Msk (0xfUL) /*!< RETXCNTRMI (Bitfield-Mask: 0x0f) */ +/* ======================================================== CLKCTRL ======================================================== */ +#define SCARD_CLKCTRL_APBCLKEN_Pos (1UL) /*!< APBCLKEN (Bit 1) */ +#define SCARD_CLKCTRL_APBCLKEN_Msk (0x2UL) /*!< APBCLKEN (Bitfield-Mask: 0x01) */ +#define SCARD_CLKCTRL_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ +#define SCARD_CLKCTRL_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SECURITY ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define SECURITY_CTRL_CRCERROR_Pos (31UL) /*!< CRCERROR (Bit 31) */ +#define SECURITY_CTRL_CRCERROR_Msk (0x80000000UL) /*!< CRCERROR (Bitfield-Mask: 0x01) */ +#define SECURITY_CTRL_FUNCTION_Pos (4UL) /*!< FUNCTION (Bit 4) */ +#define SECURITY_CTRL_FUNCTION_Msk (0xf0UL) /*!< FUNCTION (Bitfield-Mask: 0x0f) */ +#define SECURITY_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ +#define SECURITY_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== SRCADDR ======================================================== */ +#define SECURITY_SRCADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define SECURITY_SRCADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== LEN ========================================================== */ +#define SECURITY_LEN_LEN_Pos (2UL) /*!< LEN (Bit 2) */ +#define SECURITY_LEN_LEN_Msk (0xffffcUL) /*!< LEN (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== RESULT ========================================================= */ +#define SECURITY_RESULT_CRC_Pos (0UL) /*!< CRC (Bit 0) */ +#define SECURITY_RESULT_CRC_Msk (0xffffffffUL) /*!< CRC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LOCKCTRL ======================================================== */ +#define SECURITY_LOCKCTRL_SELECT_Pos (0UL) /*!< SELECT (Bit 0) */ +#define SECURITY_LOCKCTRL_SELECT_Msk (0xffUL) /*!< SELECT (Bitfield-Mask: 0xff) */ +/* ======================================================= LOCKSTAT ======================================================== */ +#define SECURITY_LOCKSTAT_STATUS_Pos (0UL) /*!< STATUS (Bit 0) */ +#define SECURITY_LOCKSTAT_STATUS_Msk (0xffffffffUL) /*!< STATUS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY0 ========================================================== */ +#define SECURITY_KEY0_KEY0_Pos (0UL) /*!< KEY0 (Bit 0) */ +#define SECURITY_KEY0_KEY0_Msk (0xffffffffUL) /*!< KEY0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY1 ========================================================== */ +#define SECURITY_KEY1_KEY1_Pos (0UL) /*!< KEY1 (Bit 0) */ +#define SECURITY_KEY1_KEY1_Msk (0xffffffffUL) /*!< KEY1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY2 ========================================================== */ +#define SECURITY_KEY2_KEY2_Pos (0UL) /*!< KEY2 (Bit 0) */ +#define SECURITY_KEY2_KEY2_Msk (0xffffffffUL) /*!< KEY2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= KEY3 ========================================================== */ +#define SECURITY_KEY3_KEY3_Pos (0UL) /*!< KEY3 (Bit 0) */ +#define SECURITY_KEY3_KEY3_Msk (0xffffffffUL) /*!< KEY3 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DR =========================================================== */ +#define UART0_DR_OEDATA_Pos (11UL) /*!< OEDATA (Bit 11) */ +#define UART0_DR_OEDATA_Msk (0x800UL) /*!< OEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_BEDATA_Pos (10UL) /*!< BEDATA (Bit 10) */ +#define UART0_DR_BEDATA_Msk (0x400UL) /*!< BEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_PEDATA_Pos (9UL) /*!< PEDATA (Bit 9) */ +#define UART0_DR_PEDATA_Msk (0x200UL) /*!< PEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_FEDATA_Pos (8UL) /*!< FEDATA (Bit 8) */ +#define UART0_DR_FEDATA_Msk (0x100UL) /*!< FEDATA (Bitfield-Mask: 0x01) */ +#define UART0_DR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define UART0_DR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== RSR ========================================================== */ +#define UART0_RSR_OESTAT_Pos (3UL) /*!< OESTAT (Bit 3) */ +#define UART0_RSR_OESTAT_Msk (0x8UL) /*!< OESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_BESTAT_Pos (2UL) /*!< BESTAT (Bit 2) */ +#define UART0_RSR_BESTAT_Msk (0x4UL) /*!< BESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_PESTAT_Pos (1UL) /*!< PESTAT (Bit 1) */ +#define UART0_RSR_PESTAT_Msk (0x2UL) /*!< PESTAT (Bitfield-Mask: 0x01) */ +#define UART0_RSR_FESTAT_Pos (0UL) /*!< FESTAT (Bit 0) */ +#define UART0_RSR_FESTAT_Msk (0x1UL) /*!< FESTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== FR =========================================================== */ +#define UART0_FR_TXBUSY_Pos (8UL) /*!< TXBUSY (Bit 8) */ +#define UART0_FR_TXBUSY_Msk (0x100UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */ +#define UART0_FR_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define UART0_FR_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define UART0_FR_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */ +#define UART0_FR_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */ +#define UART0_FR_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ +#define UART0_FR_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ +#define UART0_FR_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */ +#define UART0_FR_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +#define UART0_FR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */ +#define UART0_FR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define UART0_FR_DCD_Pos (2UL) /*!< DCD (Bit 2) */ +#define UART0_FR_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */ +#define UART0_FR_DSR_Pos (1UL) /*!< DSR (Bit 1) */ +#define UART0_FR_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */ +#define UART0_FR_CTS_Pos (0UL) /*!< CTS (Bit 0) */ +#define UART0_FR_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */ +/* ========================================================= ILPR ========================================================== */ +#define UART0_ILPR_ILPDVSR_Pos (0UL) /*!< ILPDVSR (Bit 0) */ +#define UART0_ILPR_ILPDVSR_Msk (0xffUL) /*!< ILPDVSR (Bitfield-Mask: 0xff) */ +/* ========================================================= IBRD ========================================================== */ +#define UART0_IBRD_DIVINT_Pos (0UL) /*!< DIVINT (Bit 0) */ +#define UART0_IBRD_DIVINT_Msk (0xffffUL) /*!< DIVINT (Bitfield-Mask: 0xffff) */ +/* ========================================================= FBRD ========================================================== */ +#define UART0_FBRD_DIVFRAC_Pos (0UL) /*!< DIVFRAC (Bit 0) */ +#define UART0_FBRD_DIVFRAC_Msk (0x3fUL) /*!< DIVFRAC (Bitfield-Mask: 0x3f) */ +/* ========================================================= LCRH ========================================================== */ +#define UART0_LCRH_SPS_Pos (7UL) /*!< SPS (Bit 7) */ +#define UART0_LCRH_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */ +#define UART0_LCRH_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */ +#define UART0_LCRH_FEN_Pos (4UL) /*!< FEN (Bit 4) */ +#define UART0_LCRH_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_STP2_Pos (3UL) /*!< STP2 (Bit 3) */ +#define UART0_LCRH_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_EPS_Pos (2UL) /*!< EPS (Bit 2) */ +#define UART0_LCRH_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_PEN_Pos (1UL) /*!< PEN (Bit 1) */ +#define UART0_LCRH_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */ +#define UART0_LCRH_BRK_Pos (0UL) /*!< BRK (Bit 0) */ +#define UART0_LCRH_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */ +/* ========================================================== CR =========================================================== */ +#define UART0_CR_CTSEN_Pos (15UL) /*!< CTSEN (Bit 15) */ +#define UART0_CR_CTSEN_Msk (0x8000UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_RTSEN_Pos (14UL) /*!< RTSEN (Bit 14) */ +#define UART0_CR_RTSEN_Msk (0x4000UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_OUT2_Pos (13UL) /*!< OUT2 (Bit 13) */ +#define UART0_CR_OUT2_Msk (0x2000UL) /*!< OUT2 (Bitfield-Mask: 0x01) */ +#define UART0_CR_OUT1_Pos (12UL) /*!< OUT1 (Bit 12) */ +#define UART0_CR_OUT1_Msk (0x1000UL) /*!< OUT1 (Bitfield-Mask: 0x01) */ +#define UART0_CR_RTS_Pos (11UL) /*!< RTS (Bit 11) */ +#define UART0_CR_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */ +#define UART0_CR_DTR_Pos (10UL) /*!< DTR (Bit 10) */ +#define UART0_CR_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */ +#define UART0_CR_RXE_Pos (9UL) /*!< RXE (Bit 9) */ +#define UART0_CR_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */ +#define UART0_CR_TXE_Pos (8UL) /*!< TXE (Bit 8) */ +#define UART0_CR_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */ +#define UART0_CR_LBE_Pos (7UL) /*!< LBE (Bit 7) */ +#define UART0_CR_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */ +#define UART0_CR_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ +#define UART0_CR_CLKSEL_Msk (0x70UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define UART0_CR_CLKEN_Pos (3UL) /*!< CLKEN (Bit 3) */ +#define UART0_CR_CLKEN_Msk (0x8UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +#define UART0_CR_SIRLP_Pos (2UL) /*!< SIRLP (Bit 2) */ +#define UART0_CR_SIRLP_Msk (0x4UL) /*!< SIRLP (Bitfield-Mask: 0x01) */ +#define UART0_CR_SIREN_Pos (1UL) /*!< SIREN (Bit 1) */ +#define UART0_CR_SIREN_Msk (0x2UL) /*!< SIREN (Bitfield-Mask: 0x01) */ +#define UART0_CR_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */ +#define UART0_CR_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IFLS ========================================================== */ +#define UART0_IFLS_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */ +#define UART0_IFLS_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */ +#define UART0_IFLS_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */ +#define UART0_IFLS_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */ +/* ========================================================== IER ========================================================== */ +#define UART0_IER_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */ +#define UART0_IER_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */ +#define UART0_IER_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */ +#define UART0_IER_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */ +#define UART0_IER_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */ +#define UART0_IER_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */ +#define UART0_IER_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */ +#define UART0_IER_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */ +#define UART0_IER_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */ +#define UART0_IER_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */ +#define UART0_IER_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */ +#define UART0_IER_TXCMPMIM_Pos (0UL) /*!< TXCMPMIM (Bit 0) */ +#define UART0_IER_TXCMPMIM_Msk (0x1UL) /*!< TXCMPMIM (Bitfield-Mask: 0x01) */ +/* ========================================================== IES ========================================================== */ +#define UART0_IES_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */ +#define UART0_IES_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */ +#define UART0_IES_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */ +#define UART0_IES_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */ +#define UART0_IES_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */ +#define UART0_IES_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */ +#define UART0_IES_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */ +#define UART0_IES_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_DSRMRIS_Pos (3UL) /*!< DSRMRIS (Bit 3) */ +#define UART0_IES_DSRMRIS_Msk (0x8UL) /*!< DSRMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_DCDMRIS_Pos (2UL) /*!< DCDMRIS (Bit 2) */ +#define UART0_IES_DCDMRIS_Msk (0x4UL) /*!< DCDMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_CTSMRIS_Pos (1UL) /*!< CTSMRIS (Bit 1) */ +#define UART0_IES_CTSMRIS_Msk (0x2UL) /*!< CTSMRIS (Bitfield-Mask: 0x01) */ +#define UART0_IES_TXCMPMRIS_Pos (0UL) /*!< TXCMPMRIS (Bit 0) */ +#define UART0_IES_TXCMPMRIS_Msk (0x1UL) /*!< TXCMPMRIS (Bitfield-Mask: 0x01) */ +/* ========================================================== MIS ========================================================== */ +#define UART0_MIS_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */ +#define UART0_MIS_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */ +#define UART0_MIS_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */ +#define UART0_MIS_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */ +#define UART0_MIS_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */ +#define UART0_MIS_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */ +#define UART0_MIS_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */ +#define UART0_MIS_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */ +#define UART0_MIS_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */ +#define UART0_MIS_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */ +#define UART0_MIS_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */ +#define UART0_MIS_TXCMPMMIS_Pos (0UL) /*!< TXCMPMMIS (Bit 0) */ +#define UART0_MIS_TXCMPMMIS_Msk (0x1UL) /*!< TXCMPMMIS (Bitfield-Mask: 0x01) */ +/* ========================================================== IEC ========================================================== */ +#define UART0_IEC_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */ +#define UART0_IEC_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */ +#define UART0_IEC_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */ +#define UART0_IEC_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */ +#define UART0_IEC_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */ +#define UART0_IEC_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */ +#define UART0_IEC_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */ +#define UART0_IEC_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */ +#define UART0_IEC_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */ +#define UART0_IEC_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */ +#define UART0_IEC_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */ +#define UART0_IEC_TXCMPMIC_Pos (0UL) /*!< TXCMPMIC (Bit 0) */ +#define UART0_IEC_TXCMPMIC_Msk (0x1UL) /*!< TXCMPMIC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define VCOMP_CFG_LVLSEL_Pos (16UL) /*!< LVLSEL (Bit 16) */ +#define VCOMP_CFG_LVLSEL_Msk (0xf0000UL) /*!< LVLSEL (Bitfield-Mask: 0x0f) */ +#define VCOMP_CFG_NSEL_Pos (8UL) /*!< NSEL (Bit 8) */ +#define VCOMP_CFG_NSEL_Msk (0x300UL) /*!< NSEL (Bitfield-Mask: 0x03) */ +#define VCOMP_CFG_PSEL_Pos (0UL) /*!< PSEL (Bit 0) */ +#define VCOMP_CFG_PSEL_Msk (0x3UL) /*!< PSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= STAT ========================================================== */ +#define VCOMP_STAT_PWDSTAT_Pos (1UL) /*!< PWDSTAT (Bit 1) */ +#define VCOMP_STAT_PWDSTAT_Msk (0x2UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */ +#define VCOMP_STAT_CMPOUT_Pos (0UL) /*!< CMPOUT (Bit 0) */ +#define VCOMP_STAT_CMPOUT_Msk (0x1UL) /*!< CMPOUT (Bitfield-Mask: 0x01) */ +/* ======================================================== PWDKEY ========================================================= */ +#define VCOMP_PWDKEY_PWDKEY_Pos (0UL) /*!< PWDKEY (Bit 0) */ +#define VCOMP_PWDKEY_PWDKEY_Msk (0xffffffffUL) /*!< PWDKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTEN ========================================================= */ +#define VCOMP_INTEN_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTEN_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTEN_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTEN_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define VCOMP_INTSTAT_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTSTAT_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTSTAT_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTSTAT_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define VCOMP_INTCLR_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTCLR_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTCLR_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTCLR_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define VCOMP_INTSET_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */ +#define VCOMP_INTSET_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */ +#define VCOMP_INTSET_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */ +#define VCOMP_INTSET_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define WDT_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */ +#define WDT_CFG_CLKSEL_Msk (0x7000000UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */ +#define WDT_CFG_INTVAL_Pos (16UL) /*!< INTVAL (Bit 16) */ +#define WDT_CFG_INTVAL_Msk (0xff0000UL) /*!< INTVAL (Bitfield-Mask: 0xff) */ +#define WDT_CFG_RESVAL_Pos (8UL) /*!< RESVAL (Bit 8) */ +#define WDT_CFG_RESVAL_Msk (0xff00UL) /*!< RESVAL (Bitfield-Mask: 0xff) */ +#define WDT_CFG_RESEN_Pos (2UL) /*!< RESEN (Bit 2) */ +#define WDT_CFG_RESEN_Msk (0x4UL) /*!< RESEN (Bitfield-Mask: 0x01) */ +#define WDT_CFG_INTEN_Pos (1UL) /*!< INTEN (Bit 1) */ +#define WDT_CFG_INTEN_Msk (0x2UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +#define WDT_CFG_WDTEN_Pos (0UL) /*!< WDTEN (Bit 0) */ +#define WDT_CFG_WDTEN_Msk (0x1UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTRT ========================================================= */ +#define WDT_RSTRT_RSTRT_Pos (0UL) /*!< RSTRT (Bit 0) */ +#define WDT_RSTRT_RSTRT_Msk (0xffUL) /*!< RSTRT (Bitfield-Mask: 0xff) */ +/* ========================================================= LOCK ========================================================== */ +#define WDT_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ +#define WDT_LOCK_LOCK_Msk (0xffUL) /*!< LOCK (Bitfield-Mask: 0xff) */ +/* ========================================================= COUNT ========================================================= */ +#define WDT_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */ +#define WDT_COUNT_COUNT_Msk (0xffUL) /*!< COUNT (Bitfield-Mask: 0xff) */ +/* ========================================================= INTEN ========================================================= */ +#define WDT_INTEN_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTEN_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTAT ======================================================== */ +#define WDT_INTSTAT_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTSTAT_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define WDT_INTCLR_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTCLR_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define WDT_INTSET_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */ +#define WDT_INTSET_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Enumerated Values Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup EnumValue_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ================================================ ADC CFG CLKSEL [24..25] ================================================ */ +typedef enum { /*!< ADC_CFG_CLKSEL */ + ADC_CFG_CLKSEL_OFF = 0, /*!< OFF : Off mode. The HFRC or HFRC_DIV2 clock must be selected + for the ADC to function. The ADC controller + automatically shuts off the clock in it's + low power modes. When setting ADCEN to '0', + the CLKSEL should remain set to one of the + two clock selects for proper power down + sequencing. */ + ADC_CFG_CLKSEL_HFRC = 1, /*!< HFRC : HFRC Core Clock divided by (CORESEL+1) */ + ADC_CFG_CLKSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : HFRC Core Clock / 2 further divided by (CORESEL+1) */ +} ADC_CFG_CLKSEL_Enum; + +/* =============================================== ADC CFG TRIGPOL [19..19] ================================================ */ +typedef enum { /*!< ADC_CFG_TRIGPOL */ + ADC_CFG_TRIGPOL_RISING_EDGE = 0, /*!< RISING_EDGE : Trigger on rising edge. */ + ADC_CFG_TRIGPOL_FALLING_EDGE = 1, /*!< FALLING_EDGE : Trigger on falling edge. */ +} ADC_CFG_TRIGPOL_Enum; + +/* =============================================== ADC CFG TRIGSEL [16..18] ================================================ */ +typedef enum { /*!< ADC_CFG_TRIGSEL */ + ADC_CFG_TRIGSEL_EXT0 = 0, /*!< EXT0 : Off chip External Trigger0 (ADC_ET0) */ + ADC_CFG_TRIGSEL_EXT1 = 1, /*!< EXT1 : Off chip External Trigger1 (ADC_ET1) */ + ADC_CFG_TRIGSEL_EXT2 = 2, /*!< EXT2 : Off chip External Trigger2 (ADC_ET2) */ + ADC_CFG_TRIGSEL_EXT3 = 3, /*!< EXT3 : Off chip External Trigger3 (ADC_ET3) */ + ADC_CFG_TRIGSEL_VCOMP = 4, /*!< VCOMP : Voltage Comparator Output */ + ADC_CFG_TRIGSEL_SWT = 7, /*!< SWT : Software Trigger */ +} ADC_CFG_TRIGSEL_Enum; + +/* ============================================== ADC CFG DFIFORDEN [12..12] =============================================== */ +typedef enum { /*!< ADC_CFG_DFIFORDEN */ + ADC_CFG_DFIFORDEN_DIS = 0, /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register + will not POP an entry off the FIFO. */ + ADC_CFG_DFIFORDEN_EN = 1, /*!< EN : Reads to the FIFOPR registger will automatically pop an + entry off the FIFO. */ +} ADC_CFG_DFIFORDEN_Enum; + +/* ================================================= ADC CFG REFSEL [8..9] ================================================= */ +typedef enum { /*!< ADC_CFG_REFSEL */ + ADC_CFG_REFSEL_INT2P0 = 0, /*!< INT2P0 : Internal 2.0V Bandgap Reference Voltage */ + ADC_CFG_REFSEL_INT1P5 = 1, /*!< INT1P5 : Internal 1.5V Bandgap Reference Voltage */ + ADC_CFG_REFSEL_EXT2P0 = 2, /*!< EXT2P0 : Off Chip 2.0V Reference */ + ADC_CFG_REFSEL_EXT1P5 = 3, /*!< EXT1P5 : Off Chip 1.5V Reference */ +} ADC_CFG_REFSEL_Enum; + +/* ================================================= ADC CFG CKMODE [4..4] ================================================= */ +typedef enum { /*!< ADC_CFG_CKMODE */ + ADC_CFG_CKMODE_LPCKMODE = 0, /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set + LPCKMODE to 0x1 while configuring the ADC. */ + ADC_CFG_CKMODE_LLCKMODE = 1, /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk + will remain on while in functioning in LPMODE0. */ +} ADC_CFG_CKMODE_Enum; + +/* ================================================= ADC CFG LPMODE [3..3] ================================================= */ +typedef enum { /*!< ADC_CFG_LPMODE */ + ADC_CFG_LPMODE_MODE0 = 0, /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between + scans with minimum latency between a trigger event and + sample data collection. */ + ADC_CFG_LPMODE_MODE1 = 1, /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks + associated with the ADC until the next trigger event. Between + scans, the reference buffer requires up to 50us of delay + from a scan trigger event before the conversion will commence + while operating in this mode. */ +} ADC_CFG_LPMODE_Enum; + +/* ================================================= ADC CFG RPTEN [2..2] ================================================== */ +typedef enum { /*!< ADC_CFG_RPTEN */ + ADC_CFG_RPTEN_SINGLE_SCAN = 0, /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single + scan upon each trigger event. */ + ADC_CFG_RPTEN_REPEATING_SCAN = 1, /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete + it's first scan upon the initial trigger event and all + subsequent scans will occur at regular intervals defined + by the configuration programmed for the CTTMRA3 internal + timer until the timer is disabled or the ADC is disabled. + When disabling the ADC (setting ADCEN to '0'), the RPTEN + bit should be cleared. */ +} ADC_CFG_RPTEN_Enum; + +/* ================================================= ADC CFG ADCEN [0..0] ================================================== */ +typedef enum { /*!< ADC_CFG_ADCEN */ + ADC_CFG_ADCEN_DIS = 0, /*!< DIS : Disable the ADC module. */ + ADC_CFG_ADCEN_EN = 1, /*!< EN : Enable the ADC module. */ +} ADC_CFG_ADCEN_Enum; + +/* ========================================================= STAT ========================================================== */ +/* ================================================ ADC STAT PWDSTAT [0..0] ================================================ */ +typedef enum { /*!< ADC_STAT_PWDSTAT */ + ADC_STAT_PWDSTAT_ON = 0, /*!< ON : Powered on. */ + ADC_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : ADC Low Power Mode 1. */ +} ADC_STAT_PWDSTAT_Enum; + +/* ========================================================== SWT ========================================================== */ +/* ================================================== ADC SWT SWT [0..7] =================================================== */ +typedef enum { /*!< ADC_SWT_SWT */ + ADC_SWT_SWT_GEN_SW_TRIGGER = 55, /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger. */ +} ADC_SWT_SWT_Enum; + +/* ======================================================== SL0CFG ========================================================= */ +/* ============================================== ADC SL0CFG ADSEL0 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL0CFG_ADSEL0 */ + ADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL0CFG_ADSEL0_Enum; + +/* ============================================== ADC SL0CFG PRMODE0 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL0CFG_PRMODE0 */ + ADC_SL0CFG_PRMODE0_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL0CFG_PRMODE0_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL0CFG_PRMODE0_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL0CFG_PRMODE0_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL0CFG_PRMODE0_Enum; + +/* =============================================== ADC SL0CFG CHSEL0 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL0CFG_CHSEL0 */ + ADC_SL0CFG_CHSEL0_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL0CFG_CHSEL0_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL0CFG_CHSEL0_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL0CFG_CHSEL0_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL0CFG_CHSEL0_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL0CFG_CHSEL0_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL0CFG_CHSEL0_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL0CFG_CHSEL0_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL0CFG_CHSEL0_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL0CFG_CHSEL0_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL0CFG_CHSEL0_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL0CFG_CHSEL0_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL0CFG_CHSEL0_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL0CFG_CHSEL0_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL0CFG_CHSEL0_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL0CFG_CHSEL0_Enum; + +/* ================================================ ADC SL0CFG WCEN0 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL0CFG_WCEN0 */ + ADC_SL0CFG_WCEN0_WCEN = 1, /*!< WCEN : Enable the window compare for slot 0. */ +} ADC_SL0CFG_WCEN0_Enum; + +/* ================================================ ADC SL0CFG SLEN0 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL0CFG_SLEN0 */ + ADC_SL0CFG_SLEN0_SLEN = 1, /*!< SLEN : Enable slot 0 for ADC conversions. */ +} ADC_SL0CFG_SLEN0_Enum; + +/* ======================================================== SL1CFG ========================================================= */ +/* ============================================== ADC SL1CFG ADSEL1 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL1CFG_ADSEL1 */ + ADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL1CFG_ADSEL1_Enum; + +/* ============================================== ADC SL1CFG PRMODE1 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL1CFG_PRMODE1 */ + ADC_SL1CFG_PRMODE1_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL1CFG_PRMODE1_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL1CFG_PRMODE1_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL1CFG_PRMODE1_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL1CFG_PRMODE1_Enum; + +/* =============================================== ADC SL1CFG CHSEL1 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL1CFG_CHSEL1 */ + ADC_SL1CFG_CHSEL1_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL1CFG_CHSEL1_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL1CFG_CHSEL1_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL1CFG_CHSEL1_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL1CFG_CHSEL1_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL1CFG_CHSEL1_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL1CFG_CHSEL1_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL1CFG_CHSEL1_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL1CFG_CHSEL1_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL1CFG_CHSEL1_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL1CFG_CHSEL1_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL1CFG_CHSEL1_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL1CFG_CHSEL1_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL1CFG_CHSEL1_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL1CFG_CHSEL1_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL1CFG_CHSEL1_Enum; + +/* ================================================ ADC SL1CFG WCEN1 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL1CFG_WCEN1 */ + ADC_SL1CFG_WCEN1_WCEN = 1, /*!< WCEN : Enable the window compare for slot 1. */ +} ADC_SL1CFG_WCEN1_Enum; + +/* ================================================ ADC SL1CFG SLEN1 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL1CFG_SLEN1 */ + ADC_SL1CFG_SLEN1_SLEN = 1, /*!< SLEN : Enable slot 1 for ADC conversions. */ +} ADC_SL1CFG_SLEN1_Enum; + +/* ======================================================== SL2CFG ========================================================= */ +/* ============================================== ADC SL2CFG ADSEL2 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL2CFG_ADSEL2 */ + ADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL2CFG_ADSEL2_Enum; + +/* ============================================== ADC SL2CFG PRMODE2 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL2CFG_PRMODE2 */ + ADC_SL2CFG_PRMODE2_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL2CFG_PRMODE2_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL2CFG_PRMODE2_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL2CFG_PRMODE2_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL2CFG_PRMODE2_Enum; + +/* =============================================== ADC SL2CFG CHSEL2 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL2CFG_CHSEL2 */ + ADC_SL2CFG_CHSEL2_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL2CFG_CHSEL2_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL2CFG_CHSEL2_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL2CFG_CHSEL2_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL2CFG_CHSEL2_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL2CFG_CHSEL2_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL2CFG_CHSEL2_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL2CFG_CHSEL2_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL2CFG_CHSEL2_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL2CFG_CHSEL2_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL2CFG_CHSEL2_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL2CFG_CHSEL2_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL2CFG_CHSEL2_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL2CFG_CHSEL2_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL2CFG_CHSEL2_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL2CFG_CHSEL2_Enum; + +/* ================================================ ADC SL2CFG WCEN2 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL2CFG_WCEN2 */ + ADC_SL2CFG_WCEN2_WCEN = 1, /*!< WCEN : Enable the window compare for slot 2. */ +} ADC_SL2CFG_WCEN2_Enum; + +/* ================================================ ADC SL2CFG SLEN2 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL2CFG_SLEN2 */ + ADC_SL2CFG_SLEN2_SLEN = 1, /*!< SLEN : Enable slot 2 for ADC conversions. */ +} ADC_SL2CFG_SLEN2_Enum; + +/* ======================================================== SL3CFG ========================================================= */ +/* ============================================== ADC SL3CFG ADSEL3 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL3CFG_ADSEL3 */ + ADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL3CFG_ADSEL3_Enum; + +/* ============================================== ADC SL3CFG PRMODE3 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL3CFG_PRMODE3 */ + ADC_SL3CFG_PRMODE3_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL3CFG_PRMODE3_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL3CFG_PRMODE3_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL3CFG_PRMODE3_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL3CFG_PRMODE3_Enum; + +/* =============================================== ADC SL3CFG CHSEL3 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL3CFG_CHSEL3 */ + ADC_SL3CFG_CHSEL3_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL3CFG_CHSEL3_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL3CFG_CHSEL3_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL3CFG_CHSEL3_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL3CFG_CHSEL3_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL3CFG_CHSEL3_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL3CFG_CHSEL3_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL3CFG_CHSEL3_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL3CFG_CHSEL3_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL3CFG_CHSEL3_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL3CFG_CHSEL3_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL3CFG_CHSEL3_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL3CFG_CHSEL3_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL3CFG_CHSEL3_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL3CFG_CHSEL3_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL3CFG_CHSEL3_Enum; + +/* ================================================ ADC SL3CFG WCEN3 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL3CFG_WCEN3 */ + ADC_SL3CFG_WCEN3_WCEN = 1, /*!< WCEN : Enable the window compare for slot 3. */ +} ADC_SL3CFG_WCEN3_Enum; + +/* ================================================ ADC SL3CFG SLEN3 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL3CFG_SLEN3 */ + ADC_SL3CFG_SLEN3_SLEN = 1, /*!< SLEN : Enable slot 3 for ADC conversions. */ +} ADC_SL3CFG_SLEN3_Enum; + +/* ======================================================== SL4CFG ========================================================= */ +/* ============================================== ADC SL4CFG ADSEL4 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL4CFG_ADSEL4 */ + ADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL4CFG_ADSEL4_Enum; + +/* ============================================== ADC SL4CFG PRMODE4 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL4CFG_PRMODE4 */ + ADC_SL4CFG_PRMODE4_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL4CFG_PRMODE4_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL4CFG_PRMODE4_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL4CFG_PRMODE4_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL4CFG_PRMODE4_Enum; + +/* =============================================== ADC SL4CFG CHSEL4 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL4CFG_CHSEL4 */ + ADC_SL4CFG_CHSEL4_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL4CFG_CHSEL4_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL4CFG_CHSEL4_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL4CFG_CHSEL4_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL4CFG_CHSEL4_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL4CFG_CHSEL4_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL4CFG_CHSEL4_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL4CFG_CHSEL4_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL4CFG_CHSEL4_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL4CFG_CHSEL4_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL4CFG_CHSEL4_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL4CFG_CHSEL4_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL4CFG_CHSEL4_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL4CFG_CHSEL4_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL4CFG_CHSEL4_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL4CFG_CHSEL4_Enum; + +/* ================================================ ADC SL4CFG WCEN4 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL4CFG_WCEN4 */ + ADC_SL4CFG_WCEN4_WCEN = 1, /*!< WCEN : Enable the window compare for slot 4. */ +} ADC_SL4CFG_WCEN4_Enum; + +/* ================================================ ADC SL4CFG SLEN4 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL4CFG_SLEN4 */ + ADC_SL4CFG_SLEN4_SLEN = 1, /*!< SLEN : Enable slot 4 for ADC conversions. */ +} ADC_SL4CFG_SLEN4_Enum; + +/* ======================================================== SL5CFG ========================================================= */ +/* ============================================== ADC SL5CFG ADSEL5 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL5CFG_ADSEL5 */ + ADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL5CFG_ADSEL5_Enum; + +/* ============================================== ADC SL5CFG PRMODE5 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL5CFG_PRMODE5 */ + ADC_SL5CFG_PRMODE5_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL5CFG_PRMODE5_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL5CFG_PRMODE5_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL5CFG_PRMODE5_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL5CFG_PRMODE5_Enum; + +/* =============================================== ADC SL5CFG CHSEL5 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL5CFG_CHSEL5 */ + ADC_SL5CFG_CHSEL5_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL5CFG_CHSEL5_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL5CFG_CHSEL5_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL5CFG_CHSEL5_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL5CFG_CHSEL5_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL5CFG_CHSEL5_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL5CFG_CHSEL5_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL5CFG_CHSEL5_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL5CFG_CHSEL5_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL5CFG_CHSEL5_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL5CFG_CHSEL5_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL5CFG_CHSEL5_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL5CFG_CHSEL5_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL5CFG_CHSEL5_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL5CFG_CHSEL5_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL5CFG_CHSEL5_Enum; + +/* ================================================ ADC SL5CFG WCEN5 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL5CFG_WCEN5 */ + ADC_SL5CFG_WCEN5_WCEN = 1, /*!< WCEN : Enable the window compare for slot 5. */ +} ADC_SL5CFG_WCEN5_Enum; + +/* ================================================ ADC SL5CFG SLEN5 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL5CFG_SLEN5 */ + ADC_SL5CFG_SLEN5_SLEN = 1, /*!< SLEN : Enable slot 5 for ADC conversions. */ +} ADC_SL5CFG_SLEN5_Enum; + +/* ======================================================== SL6CFG ========================================================= */ +/* ============================================== ADC SL6CFG ADSEL6 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL6CFG_ADSEL6 */ + ADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL6CFG_ADSEL6_Enum; + +/* ============================================== ADC SL6CFG PRMODE6 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL6CFG_PRMODE6 */ + ADC_SL6CFG_PRMODE6_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL6CFG_PRMODE6_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL6CFG_PRMODE6_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL6CFG_PRMODE6_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL6CFG_PRMODE6_Enum; + +/* =============================================== ADC SL6CFG CHSEL6 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL6CFG_CHSEL6 */ + ADC_SL6CFG_CHSEL6_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL6CFG_CHSEL6_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL6CFG_CHSEL6_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL6CFG_CHSEL6_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL6CFG_CHSEL6_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL6CFG_CHSEL6_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL6CFG_CHSEL6_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL6CFG_CHSEL6_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL6CFG_CHSEL6_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL6CFG_CHSEL6_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL6CFG_CHSEL6_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL6CFG_CHSEL6_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL6CFG_CHSEL6_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL6CFG_CHSEL6_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL6CFG_CHSEL6_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL6CFG_CHSEL6_Enum; + +/* ================================================ ADC SL6CFG WCEN6 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL6CFG_WCEN6 */ + ADC_SL6CFG_WCEN6_WCEN = 1, /*!< WCEN : Enable the window compare for slot 6. */ +} ADC_SL6CFG_WCEN6_Enum; + +/* ================================================ ADC SL6CFG SLEN6 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL6CFG_SLEN6 */ + ADC_SL6CFG_SLEN6_SLEN = 1, /*!< SLEN : Enable slot 6 for ADC conversions. */ +} ADC_SL6CFG_SLEN6_Enum; + +/* ======================================================== SL7CFG ========================================================= */ +/* ============================================== ADC SL7CFG ADSEL7 [24..26] =============================================== */ +typedef enum { /*!< ADC_SL7CFG_ADSEL7 */ + ADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide + module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate + divide module for this slot. */ + ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate + divide module for this slot. */ +} ADC_SL7CFG_ADSEL7_Enum; + +/* ============================================== ADC SL7CFG PRMODE7 [16..17] ============================================== */ +typedef enum { /*!< ADC_SL7CFG_PRMODE7 */ + ADC_SL7CFG_PRMODE7_P14B = 0, /*!< P14B : 14-bit precision mode */ + ADC_SL7CFG_PRMODE7_P12B = 1, /*!< P12B : 12-bit precision mode */ + ADC_SL7CFG_PRMODE7_P10B = 2, /*!< P10B : 10-bit precision mode */ + ADC_SL7CFG_PRMODE7_P8B = 3, /*!< P8B : 8-bit precision mode */ +} ADC_SL7CFG_PRMODE7_Enum; + +/* =============================================== ADC SL7CFG CHSEL7 [8..11] =============================================== */ +typedef enum { /*!< ADC_SL7CFG_CHSEL7 */ + ADC_SL7CFG_CHSEL7_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ + ADC_SL7CFG_CHSEL7_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ + ADC_SL7CFG_CHSEL7_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ + ADC_SL7CFG_CHSEL7_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ + ADC_SL7CFG_CHSEL7_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ + ADC_SL7CFG_CHSEL7_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ + ADC_SL7CFG_CHSEL7_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ + ADC_SL7CFG_CHSEL7_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ + ADC_SL7CFG_CHSEL7_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ + ADC_SL7CFG_CHSEL7_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ + ADC_SL7CFG_CHSEL7_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and + pad13(P). */ + ADC_SL7CFG_CHSEL7_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and + pad14(P). */ + ADC_SL7CFG_CHSEL7_TEMP = 12, /*!< TEMP : internal temperature sensor. */ + ADC_SL7CFG_CHSEL7_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ + ADC_SL7CFG_CHSEL7_VSS = 14, /*!< VSS : Input VSS */ +} ADC_SL7CFG_CHSEL7_Enum; + +/* ================================================ ADC SL7CFG WCEN7 [1..1] ================================================ */ +typedef enum { /*!< ADC_SL7CFG_WCEN7 */ + ADC_SL7CFG_WCEN7_WCEN = 1, /*!< WCEN : Enable the window compare for slot 7. */ +} ADC_SL7CFG_WCEN7_Enum; + +/* ================================================ ADC SL7CFG SLEN7 [0..0] ================================================ */ +typedef enum { /*!< ADC_SL7CFG_SLEN7 */ + ADC_SL7CFG_SLEN7_SLEN = 1, /*!< SLEN : Enable slot 7 for ADC conversions. */ +} ADC_SL7CFG_SLEN7_Enum; + +/* ========================================================= WULIM ========================================================= */ +/* ========================================================= WLLIM ========================================================= */ +/* ======================================================== SCWLIM ========================================================= */ +/* ========================================================= FIFO ========================================================== */ +/* ======================================================== FIFOPR ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ================================================= ADC INTEN DERR [7..7] ================================================= */ +typedef enum { /*!< ADC_INTEN_DERR */ + ADC_INTEN_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTEN_DERR_Enum; + +/* ================================================= ADC INTEN DCMP [6..6] ================================================= */ +typedef enum { /*!< ADC_INTEN_DCMP */ + ADC_INTEN_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTEN_DCMP_Enum; + +/* ================================================ ADC INTEN WCINC [5..5] ================================================= */ +typedef enum { /*!< ADC_INTEN_WCINC */ + ADC_INTEN_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTEN_WCINC_Enum; + +/* ================================================ ADC INTEN WCEXC [4..4] ================================================= */ +typedef enum { /*!< ADC_INTEN_WCEXC */ + ADC_INTEN_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTEN_WCEXC_Enum; + +/* =============================================== ADC INTEN FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTEN_FIFOOVR2 */ + ADC_INTEN_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTEN_FIFOOVR2_Enum; + +/* =============================================== ADC INTEN FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTEN_FIFOOVR1 */ + ADC_INTEN_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTEN_FIFOOVR1_Enum; + +/* ================================================ ADC INTEN SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTEN_SCNCMP */ + ADC_INTEN_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTEN_SCNCMP_Enum; + +/* ================================================ ADC INTEN CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTEN_CNVCMP */ + ADC_INTEN_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTEN_CNVCMP_Enum; + +/* ======================================================== INTSTAT ======================================================== */ +/* ================================================ ADC INTSTAT DERR [7..7] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_DERR */ + ADC_INTSTAT_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTSTAT_DERR_Enum; + +/* ================================================ ADC INTSTAT DCMP [6..6] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_DCMP */ + ADC_INTSTAT_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTSTAT_DCMP_Enum; + +/* =============================================== ADC INTSTAT WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_WCINC */ + ADC_INTSTAT_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTSTAT_WCINC_Enum; + +/* =============================================== ADC INTSTAT WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTSTAT_WCEXC */ + ADC_INTSTAT_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTSTAT_WCEXC_Enum; + +/* ============================================== ADC INTSTAT FIFOOVR2 [3..3] ============================================== */ +typedef enum { /*!< ADC_INTSTAT_FIFOOVR2 */ + ADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTSTAT_FIFOOVR2_Enum; + +/* ============================================== ADC INTSTAT FIFOOVR1 [2..2] ============================================== */ +typedef enum { /*!< ADC_INTSTAT_FIFOOVR1 */ + ADC_INTSTAT_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTSTAT_FIFOOVR1_Enum; + +/* =============================================== ADC INTSTAT SCNCMP [1..1] =============================================== */ +typedef enum { /*!< ADC_INTSTAT_SCNCMP */ + ADC_INTSTAT_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTSTAT_SCNCMP_Enum; + +/* =============================================== ADC INTSTAT CNVCMP [0..0] =============================================== */ +typedef enum { /*!< ADC_INTSTAT_CNVCMP */ + ADC_INTSTAT_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTSTAT_CNVCMP_Enum; + +/* ======================================================== INTCLR ========================================================= */ +/* ================================================ ADC INTCLR DERR [7..7] ================================================= */ +typedef enum { /*!< ADC_INTCLR_DERR */ + ADC_INTCLR_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTCLR_DERR_Enum; + +/* ================================================ ADC INTCLR DCMP [6..6] ================================================= */ +typedef enum { /*!< ADC_INTCLR_DCMP */ + ADC_INTCLR_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTCLR_DCMP_Enum; + +/* ================================================ ADC INTCLR WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTCLR_WCINC */ + ADC_INTCLR_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTCLR_WCINC_Enum; + +/* ================================================ ADC INTCLR WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTCLR_WCEXC */ + ADC_INTCLR_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTCLR_WCEXC_Enum; + +/* ============================================== ADC INTCLR FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTCLR_FIFOOVR2 */ + ADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTCLR_FIFOOVR2_Enum; + +/* ============================================== ADC INTCLR FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTCLR_FIFOOVR1 */ + ADC_INTCLR_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTCLR_FIFOOVR1_Enum; + +/* =============================================== ADC INTCLR SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTCLR_SCNCMP */ + ADC_INTCLR_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTCLR_SCNCMP_Enum; + +/* =============================================== ADC INTCLR CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTCLR_CNVCMP */ + ADC_INTCLR_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTCLR_CNVCMP_Enum; + +/* ======================================================== INTSET ========================================================= */ +/* ================================================ ADC INTSET DERR [7..7] ================================================= */ +typedef enum { /*!< ADC_INTSET_DERR */ + ADC_INTSET_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ +} ADC_INTSET_DERR_Enum; + +/* ================================================ ADC INTSET DCMP [6..6] ================================================= */ +typedef enum { /*!< ADC_INTSET_DCMP */ + ADC_INTSET_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ +} ADC_INTSET_DCMP_Enum; + +/* ================================================ ADC INTSET WCINC [5..5] ================================================ */ +typedef enum { /*!< ADC_INTSET_WCINC */ + ADC_INTSET_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ +} ADC_INTSET_WCINC_Enum; + +/* ================================================ ADC INTSET WCEXC [4..4] ================================================ */ +typedef enum { /*!< ADC_INTSET_WCEXC */ + ADC_INTSET_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ +} ADC_INTSET_WCEXC_Enum; + +/* ============================================== ADC INTSET FIFOOVR2 [3..3] =============================================== */ +typedef enum { /*!< ADC_INTSET_FIFOOVR2 */ + ADC_INTSET_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ +} ADC_INTSET_FIFOOVR2_Enum; + +/* ============================================== ADC INTSET FIFOOVR1 [2..2] =============================================== */ +typedef enum { /*!< ADC_INTSET_FIFOOVR1 */ + ADC_INTSET_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ +} ADC_INTSET_FIFOOVR1_Enum; + +/* =============================================== ADC INTSET SCNCMP [1..1] ================================================ */ +typedef enum { /*!< ADC_INTSET_SCNCMP */ + ADC_INTSET_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ +} ADC_INTSET_SCNCMP_Enum; + +/* =============================================== ADC INTSET CNVCMP [0..0] ================================================ */ +typedef enum { /*!< ADC_INTSET_CNVCMP */ + ADC_INTSET_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ +} ADC_INTSET_CNVCMP_Enum; + +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* ============================================== ADC DMACFG DMAMSK [17..17] =============================================== */ +typedef enum { /*!< ADC_DMACFG_DMAMSK */ + ADC_DMACFG_DMAMSK_DIS = 0, /*!< DIS : FIFO Contents are copied directly to memory without modification. */ + ADC_DMACFG_DMAMSK_EN = 1, /*!< EN : Only the FIFODATA contents are copied to memory on DMA + transfers. The SLOTNUM and FIFOCNT contents are cleared + to zero. */ +} ADC_DMACFG_DMAMSK_Enum; + +/* ============================================ ADC DMACFG DMAHONSTAT [16..16] ============================================= */ +typedef enum { /*!< ADC_DMACFG_DMAHONSTAT */ + ADC_DMACFG_DMAHONSTAT_DIS = 0, /*!< DIS : ADC conversions will continue regardless of DMA status + register */ + ADC_DMACFG_DMAHONSTAT_EN = 1, /*!< EN : ADC conversions will not progress if DMAERR or DMACPL bits + in DMA status register are set. */ +} ADC_DMACFG_DMAHONSTAT_Enum; + +/* ============================================== ADC DMACFG DMADYNPRI [9..9] ============================================== */ +typedef enum { /*!< ADC_DMACFG_DMADYNPRI */ + ADC_DMACFG_DMADYNPRI_DIS = 0, /*!< DIS : Disable dynamic priority (use DMAPRI setting only) */ + ADC_DMACFG_DMADYNPRI_EN = 1, /*!< EN : Enable dynamic priority */ +} ADC_DMACFG_DMADYNPRI_Enum; + +/* =============================================== ADC DMACFG DMAPRI [8..8] ================================================ */ +typedef enum { /*!< ADC_DMACFG_DMAPRI */ + ADC_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + ADC_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} ADC_DMACFG_DMAPRI_Enum; + +/* =============================================== ADC DMACFG DMADIR [2..2] ================================================ */ +typedef enum { /*!< ADC_DMACFG_DMADIR */ + ADC_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */ + ADC_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */ +} ADC_DMACFG_DMADIR_Enum; + +/* ================================================ ADC DMACFG DMAEN [0..0] ================================================ */ +typedef enum { /*!< ADC_DMACFG_DMAEN */ + ADC_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + ADC_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} ADC_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ APBDMA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BBVALUE ======================================================== */ +/* ====================================================== BBSETCLEAR ======================================================= */ +/* ======================================================== BBINPUT ======================================================== */ +/* ======================================================= DEBUGDATA ======================================================= */ +/* ========================================================= DEBUG ========================================================= */ +/* ============================================== APBDMA DEBUG DEBUGEN [0..3] ============================================== */ +typedef enum { /*!< APBDMA_DEBUG_DEBUGEN */ + APBDMA_DEBUG_DEBUGEN_OFF = 0, /*!< OFF : Debug Disabled */ + APBDMA_DEBUG_DEBUGEN_ARB = 1, /*!< ARB : Debug Arb values */ +} APBDMA_DEBUG_DEBUGEN_Enum; + + + +/* =========================================================================================================================== */ +/* ================ BLEIF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ======================================================== FIFOPOP ======================================================== */ +/* ======================================================= FIFOPUSH ======================================================== */ +/* ======================================================= FIFOCTRL ======================================================== */ +/* ======================================================== FIFOLOC ======================================================== */ +/* ======================================================== CLKCFG ========================================================= */ +/* =============================================== BLEIF CLKCFG FSEL [8..10] =============================================== */ +typedef enum { /*!< BLEIF_CLKCFG_FSEL */ + BLEIF_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should + be used whenever the IOM is not active. */ + BLEIF_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */ + BLEIF_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */ +} BLEIF_CLKCFG_FSEL_Enum; + +/* ========================================================== CMD ========================================================== */ +/* ================================================= BLEIF CMD CMD [0..4] ================================================== */ +typedef enum { /*!< BLEIF_CMD_CMD */ + BLEIF_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified + in the OFFSETCNT field */ + BLEIF_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in + the OFFSETCNT field */ +} BLEIF_CMD_CMD_Enum; + +/* ======================================================== CMDRPT ========================================================= */ +/* ======================================================= OFFSETHI ======================================================== */ +/* ======================================================== CMDSTAT ======================================================== */ +/* ============================================= BLEIF CMDSTAT CMDSTAT [5..7] ============================================== */ +typedef enum { /*!< BLEIF_CMDSTAT_CMDSTAT */ + BLEIF_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */ + BLEIF_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */ + BLEIF_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */ + BLEIF_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */ +} BLEIF_CMDSTAT_CMDSTAT_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* ============================================== BLEIF DMACFG DPWROFF [9..9] ============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DPWROFF */ + BLEIF_DMACFG_DPWROFF_DIS = 0, /*!< DIS : Power off disabled */ + BLEIF_DMACFG_DPWROFF_EN = 1, /*!< EN : Power off enabled */ +} BLEIF_DMACFG_DPWROFF_Enum; + +/* ============================================== BLEIF DMACFG DMAPRI [8..8] =============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DMAPRI */ + BLEIF_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + BLEIF_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} BLEIF_DMACFG_DMAPRI_Enum; + +/* ============================================== BLEIF DMACFG DMADIR [1..1] =============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DMADIR */ + BLEIF_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when + doing IOM read operations, ie reading data from external + devices. */ + BLEIF_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing + IOM write operations, ie writing data to external devices. */ +} BLEIF_DMACFG_DMADIR_Enum; + +/* =============================================== BLEIF DMACFG DMAEN [0..0] =============================================== */ +typedef enum { /*!< BLEIF_DMACFG_DMAEN */ + BLEIF_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + BLEIF_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} BLEIF_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ +/* ========================================================= CQCFG ========================================================= */ +/* =============================================== BLEIF CQCFG CQPRI [1..1] ================================================ */ +typedef enum { /*!< BLEIF_CQCFG_CQPRI */ + BLEIF_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + BLEIF_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} BLEIF_CQCFG_CQPRI_Enum; + +/* ================================================ BLEIF CQCFG CQEN [0..0] ================================================ */ +typedef enum { /*!< BLEIF_CQCFG_CQEN */ + BLEIF_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ + BLEIF_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ +} BLEIF_CQCFG_CQEN_Enum; + +/* ======================================================== CQADDR ========================================================= */ +/* ======================================================== CQSTAT ========================================================= */ +/* ======================================================== CQFLAGS ======================================================== */ +/* ====================================================== CQSETCLEAR ======================================================= */ +/* ======================================================= CQPAUSEEN ======================================================= */ +/* ============================================= BLEIF CQPAUSEEN CQPEN [0..15] ============================================= */ +typedef enum { /*!< BLEIF_CQPAUSEEN_CQPEN */ + BLEIF_CQPAUSEEN_CQPEN_CNTEQ = 32768, /*!< CNTEQ : Pauses command queue processing when HWCNT matches SWCNT */ + BLEIF_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with + SWFLAG4 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with + SWFLAG3 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed + with SWFLAG2 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed + with SWFLAG1 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed + with SWFLAG0 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed + with SWFLAG1 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed + with SWFLAG0 is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7 + is '1'. */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 7 + is '1' */ + BLEIF_CQPAUSEEN_CQPEN_SWFLGEN0 = 1, /*!< SWFLGEN0 : Pause the command queue when software flag bit 7 + is '1' */ +} BLEIF_CQPAUSEEN_CQPEN_Enum; + +/* ======================================================= CQCURIDX ======================================================== */ +/* ======================================================= CQENDIDX ======================================================== */ +/* ======================================================== STATUS ========================================================= */ +/* ============================================== BLEIF STATUS IDLEST [2..2] =============================================== */ +typedef enum { /*!< BLEIF_STATUS_IDLEST */ + BLEIF_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */ +} BLEIF_STATUS_IDLEST_Enum; + +/* ============================================== BLEIF STATUS CMDACT [1..1] =============================================== */ +typedef enum { /*!< BLEIF_STATUS_CMDACT */ + BLEIF_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module + has an active command and is processing this. De-asserted + when the command is completed. */ +} BLEIF_STATUS_CMDACT_Enum; + +/* ================================================ BLEIF STATUS ERR [0..0] ================================================ */ +typedef enum { /*!< BLEIF_STATUS_ERR */ + BLEIF_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */ +} BLEIF_STATUS_ERR_Enum; + +/* ======================================================== MSPICFG ======================================================== */ +/* ============================================= BLEIF MSPICFG SPILSB [23..23] ============================================= */ +typedef enum { /*!< BLEIF_MSPICFG_SPILSB */ + BLEIF_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */ + BLEIF_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */ +} BLEIF_MSPICFG_SPILSB_Enum; + +/* ============================================ BLEIF MSPICFG RDFCPOL [22..22] ============================================= */ +typedef enum { /*!< BLEIF_MSPICFG_RDFCPOL */ + BLEIF_MSPICFG_RDFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow + control and new read spi transactions will not be started + until the signal goes low.(default) */ + BLEIF_MSPICFG_RDFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core low(0) creates flow + control and new read spi transactions will not be started + until the signal goes high. */ +} BLEIF_MSPICFG_RDFCPOL_Enum; + +/* ============================================ BLEIF MSPICFG WTFCPOL [21..21] ============================================= */ +typedef enum { /*!< BLEIF_MSPICFG_WTFCPOL */ + BLEIF_MSPICFG_WTFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow + control and new write spi transactions will not be started + until the signal goes low.(default) */ + BLEIF_MSPICFG_WTFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core high(1) creates low(0) + control and new write spi transactions will not be started + until the signal goes high. */ +} BLEIF_MSPICFG_WTFCPOL_Enum; + +/* ============================================== BLEIF MSPICFG RDFC [17..17] ============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_RDFC */ + BLEIF_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */ + BLEIF_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */ +} BLEIF_MSPICFG_RDFC_Enum; + +/* ============================================== BLEIF MSPICFG WTFC [16..16] ============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_WTFC */ + BLEIF_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */ + BLEIF_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */ +} BLEIF_MSPICFG_WTFC_Enum; + +/* =============================================== BLEIF MSPICFG SPHA [1..1] =============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_SPHA */ + BLEIF_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge, + rising or falling dependant on the value of SPOL */ + BLEIF_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock + edge, rising of falling dependant on the value of SPOL */ +} BLEIF_MSPICFG_SPHA_Enum; + +/* =============================================== BLEIF MSPICFG SPOL [0..0] =============================================== */ +typedef enum { /*!< BLEIF_MSPICFG_SPOL */ + BLEIF_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The initial value of the clock is 0. */ + BLEIF_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The initial value of the clock is 1. */ +} BLEIF_MSPICFG_SPOL_Enum; + +/* ======================================================== BLECFG ========================================================= */ +/* ============================================ BLEIF BLECFG SPIISOCTL [14..15] ============================================ */ +typedef enum { /*!< BLEIF_BLECFG_SPIISOCTL */ + BLEIF_BLECFG_SPIISOCTL_ON = 3, /*!< ON : SPI signals from BLE Core to/from MCU Core are isolated. */ + BLEIF_BLECFG_SPIISOCTL_OFF = 2, /*!< OFF : SPI signals from BLE Core to/from MCU Core are not isolated. */ + BLEIF_BLECFG_SPIISOCTL_AUTO = 0, /*!< AUTO : SPI signals from BLE Core to/from MCU Core are automatically + isolated by the logic */ +} BLEIF_BLECFG_SPIISOCTL_Enum; + +/* ============================================ BLEIF BLECFG PWRISOCTL [12..13] ============================================ */ +typedef enum { /*!< BLEIF_BLECFG_PWRISOCTL */ + BLEIF_BLECFG_PWRISOCTL_ON = 3, /*!< ON : BLEH power signal isolation to on (isolated). */ + BLEIF_BLECFG_PWRISOCTL_OFF = 2, /*!< OFF : BLEH power signal isolation to off (not isolated). */ + BLEIF_BLECFG_PWRISOCTL_AUTO = 0, /*!< AUTO : BLEH Power signal isolation is controlled automatically + through the interface logic */ +} BLEIF_BLECFG_PWRISOCTL_Enum; + +/* ============================================ BLEIF BLECFG BLEHREQCTL [6..7] ============================================= */ +typedef enum { /*!< BLEIF_BLECFG_BLEHREQCTL */ + BLEIF_BLECFG_BLEHREQCTL_ON = 3, /*!< ON : BLEH Power-on reg signal is set to on (1). */ + BLEIF_BLECFG_BLEHREQCTL_OFF = 2, /*!< OFF : BLEH Power-on signal is set to off (0). */ + BLEIF_BLECFG_BLEHREQCTL_AUTO = 0, /*!< AUTO : BLEH Power-on signal is controlled by the PWRSM logic + and automatically controlled */ +} BLEIF_BLECFG_BLEHREQCTL_Enum; + +/* ============================================ BLEIF BLECFG DCDCFLGCTL [4..5] ============================================= */ +typedef enum { /*!< BLEIF_BLECFG_DCDCFLGCTL */ + BLEIF_BLECFG_DCDCFLGCTL_ON = 3, /*!< ON : DCDC Flag signal is set to on (1). */ + BLEIF_BLECFG_DCDCFLGCTL_OFF = 2, /*!< OFF : DCDC Flag signal is set to off (0). */ + BLEIF_BLECFG_DCDCFLGCTL_AUTO = 0, /*!< AUTO : DCDC Flag signal is controlled by the PWRSM logic and + automatically controlled */ +} BLEIF_BLECFG_DCDCFLGCTL_Enum; + +/* ============================================= BLEIF BLECFG WAKEUPCTL [2..3] ============================================= */ +typedef enum { /*!< BLEIF_BLECFG_WAKEUPCTL */ + BLEIF_BLECFG_WAKEUPCTL_ON = 3, /*!< ON : Wake signal is set to on (1). */ + BLEIF_BLECFG_WAKEUPCTL_OFF = 2, /*!< OFF : Wake signal is set to off (0). */ + BLEIF_BLECFG_WAKEUPCTL_AUTO = 0, /*!< AUTO : Wake signal is controlled by the PWRSM logic and automatically + controlled */ +} BLEIF_BLECFG_WAKEUPCTL_Enum; + +/* ============================================== BLEIF BLECFG BLERSTN [1..1] ============================================== */ +typedef enum { /*!< BLEIF_BLECFG_BLERSTN */ + BLEIF_BLECFG_BLERSTN_ACTIVE = 1, /*!< ACTIVE : The reset signal is active (0) */ + BLEIF_BLECFG_BLERSTN_INACTIVE = 0, /*!< INACTIVE : The reset signal is inactive (1) */ +} BLEIF_BLECFG_BLERSTN_Enum; + +/* ============================================== BLEIF BLECFG PWRSMEN [0..0] ============================================== */ +typedef enum { /*!< BLEIF_BLECFG_PWRSMEN */ + BLEIF_BLECFG_PWRSMEN_ON = 1, /*!< ON : Internal power state machine is enabled and will sequence + the BLEH power domain as indicated in the design document. + Overrides for the power signals are not enabled. */ + BLEIF_BLECFG_PWRSMEN_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not + sequence the BLEH power domain. The values of the overrides + will be used to drive the output sequencing signals */ +} BLEIF_BLECFG_PWRSMEN_Enum; + +/* ======================================================== PWRCMD ========================================================= */ +/* ======================================================== BSTATUS ======================================================== */ +/* ============================================== BLEIF BSTATUS PWRST [8..10] ============================================== */ +typedef enum { /*!< BLEIF_BSTATUS_PWRST */ + BLEIF_BSTATUS_PWRST_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not + sequence the BLEH power domain. The values of the overrides + will be used to drive the output sequencing signals */ + BLEIF_BSTATUS_PWRST_INIT = 1, /*!< INIT : Initialization state. BLEH not powered */ + BLEIF_BSTATUS_PWRST_PWRON = 2, /*!< PWRON : Waiting for the powerup of the BLEH */ + BLEIF_BSTATUS_PWRST_ACTIVE = 3, /*!< ACTIVE : The BLE Core is powered and active */ + BLEIF_BSTATUS_PWRST_SLEEP = 6, /*!< SLEEP : The BLE Core has entered sleep mode and the power request + is inactive */ + BLEIF_BSTATUS_PWRST_SHUTDOWN = 4, /*!< SHUTDOWN : The BLE Core is in shutdown mode */ +} BLEIF_BSTATUS_PWRST_Enum; + +/* ============================================= BLEIF BSTATUS B2MSTATE [0..2] ============================================= */ +typedef enum { /*!< BLEIF_BSTATUS_B2MSTATE */ + BLEIF_BSTATUS_B2MSTATE_RESET = 0, /*!< RESET : Reset State */ + BLEIF_BSTATUS_B2MSTATE_Sleep = 1, /*!< Sleep : Sleep state. */ + BLEIF_BSTATUS_B2MSTATE_Standby = 2, /*!< Standby : Standby State */ + BLEIF_BSTATUS_B2MSTATE_Idle = 3, /*!< Idle : Idle state */ + BLEIF_BSTATUS_B2MSTATE_Active = 4, /*!< Active : Active state. */ +} BLEIF_BSTATUS_B2MSTATE_Enum; + +/* ======================================================== BLEDBG ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CACHECTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CACHECFG ======================================================== */ +/* =========================================== CACHECTRL CACHECFG CONFIG [4..7] ============================================ */ +typedef enum { /*!< CACHECTRL_CACHECFG_CONFIG */ + CACHECTRL_CACHECFG_CONFIG_W1_128B_512E = 4, /*!< W1_128B_512E : Direct mapped, 128-bit linesize, 512 entries + (4 SRAMs active) */ + CACHECTRL_CACHECFG_CONFIG_W2_128B_512E = 5, /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512 + entries (8 SRAMs active) */ + CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E = 8, /*!< W1_128B_1024E : Direct mapped, 128-bit linesize, 1024 entries + (8 SRAMs active) */ +} CACHECTRL_CACHECFG_CONFIG_Enum; + +/* ======================================================= FLASHCFG ======================================================== */ +/* ========================================== CACHECTRL FLASHCFG LPMMODE [12..13] ========================================== */ +typedef enum { /*!< CACHECTRL_FLASHCFG_LPMMODE */ + CACHECTRL_FLASHCFG_LPMMODE_NEVER = 0, /*!< NEVER : High power mode (LPM not used). */ + CACHECTRL_FLASHCFG_LPMMODE_STANDBY = 1, /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations, + but asserted while flash IDLE. */ + CACHECTRL_FLASHCFG_LPMMODE_ALWAYS = 2, /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT + must be programmed to accomodate longer read access times. */ +} CACHECTRL_FLASHCFG_LPMMODE_Enum; + +/* ========================================================= CTRL ========================================================== */ +/* =========================================== CACHECTRL CTRL RESET_STAT [1..1] ============================================ */ +typedef enum { /*!< CACHECTRL_CTRL_RESET_STAT */ + CACHECTRL_CTRL_RESET_STAT_CLEAR = 1, /*!< CLEAR : Clear Cache Stats */ +} CACHECTRL_CTRL_RESET_STAT_Enum; + +/* ======================================================= NCR0START ======================================================= */ +/* ======================================================== NCR0END ======================================================== */ +/* ======================================================= NCR1START ======================================================= */ +/* ======================================================== NCR1END ======================================================== */ +/* ========================================================= DMON0 ========================================================= */ +/* ========================================================= DMON1 ========================================================= */ +/* ========================================================= DMON2 ========================================================= */ +/* ========================================================= DMON3 ========================================================= */ +/* ========================================================= IMON0 ========================================================= */ +/* ========================================================= IMON1 ========================================================= */ +/* ========================================================= IMON2 ========================================================= */ +/* ========================================================= IMON3 ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CLKGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CALXT ========================================================= */ +/* ========================================================= CALRC ========================================================= */ +/* ======================================================== ACALCTR ======================================================== */ +/* ========================================================= OCTRL ========================================================= */ +/* =============================================== CLKGEN OCTRL ACAL [8..10] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_ACAL */ + CLKGEN_OCTRL_ACAL_DIS = 0, /*!< DIS : Disable Autocalibration */ + CLKGEN_OCTRL_ACAL_1024SEC = 2, /*!< 1024SEC : Autocalibrate every 1024 seconds. Once autocalibration + is done, an interrupt will be triggered at the end of 1024 + seconds. */ + CLKGEN_OCTRL_ACAL_512SEC = 3, /*!< 512SEC : Autocalibrate every 512 seconds. Once autocalibration + is done, an interrupt will be trigged at the end of 512 + seconds. */ + CLKGEN_OCTRL_ACAL_XTFREQ = 6, /*!< XTFREQ : Frequency measurement using XT. The XT clock is normally + considered much more accurate than the LFRC clock source. */ + CLKGEN_OCTRL_ACAL_EXTFREQ = 7, /*!< EXTFREQ : Frequency measurement using external clock. */ +} CLKGEN_OCTRL_ACAL_Enum; + +/* =============================================== CLKGEN OCTRL OSEL [7..7] ================================================ */ +typedef enum { /*!< CLKGEN_OCTRL_OSEL */ + CLKGEN_OCTRL_OSEL_RTC_XT = 0, /*!< RTC_XT : RTC uses the XT */ + CLKGEN_OCTRL_OSEL_RTC_LFRC = 1, /*!< RTC_LFRC : RTC uses the LFRC */ +} CLKGEN_OCTRL_OSEL_Enum; + +/* ================================================ CLKGEN OCTRL FOS [6..6] ================================================ */ +typedef enum { /*!< CLKGEN_OCTRL_FOS */ + CLKGEN_OCTRL_FOS_DIS = 0, /*!< DIS : Disable the oscillator switch on failure function. */ + CLKGEN_OCTRL_FOS_EN = 1, /*!< EN : Enable the oscillator switch on failure function. */ +} CLKGEN_OCTRL_FOS_Enum; + +/* ============================================== CLKGEN OCTRL STOPRC [1..1] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_STOPRC */ + CLKGEN_OCTRL_STOPRC_EN = 0, /*!< EN : Enable the LFRC Oscillator to drive the RTC */ + CLKGEN_OCTRL_STOPRC_STOP = 1, /*!< STOP : Stop the LFRC Oscillator when driving the RTC */ +} CLKGEN_OCTRL_STOPRC_Enum; + +/* ============================================== CLKGEN OCTRL STOPXT [0..0] =============================================== */ +typedef enum { /*!< CLKGEN_OCTRL_STOPXT */ + CLKGEN_OCTRL_STOPXT_EN = 0, /*!< EN : Enable the XT Oscillator to drive the RTC */ + CLKGEN_OCTRL_STOPXT_STOP = 1, /*!< STOP : Stop the XT Oscillator when driving the RTC */ +} CLKGEN_OCTRL_STOPXT_Enum; + +/* ======================================================== CLKOUT ========================================================= */ +/* =============================================== CLKGEN CLKOUT CKEN [7..7] =============================================== */ +typedef enum { /*!< CLKGEN_CLKOUT_CKEN */ + CLKGEN_CLKOUT_CKEN_DIS = 0, /*!< DIS : Disable CLKOUT */ + CLKGEN_CLKOUT_CKEN_EN = 1, /*!< EN : Enable CLKOUT */ +} CLKGEN_CLKOUT_CKEN_Enum; + +/* ============================================== CLKGEN CLKOUT CKSEL [0..5] =============================================== */ +typedef enum { /*!< CLKGEN_CLKOUT_CKSEL */ + CLKGEN_CLKOUT_CKSEL_LFRC = 0, /*!< LFRC : LFRC */ + CLKGEN_CLKOUT_CKSEL_XT_DIV2 = 1, /*!< XT_DIV2 : XT / 2 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV4 = 2, /*!< XT_DIV4 : XT / 4 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV8 = 3, /*!< XT_DIV8 : XT / 8 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV16 = 4, /*!< XT_DIV16 : XT / 16 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV32 = 5, /*!< XT_DIV32 : XT / 32 */ + CLKGEN_CLKOUT_CKSEL_RTC_1Hz = 16, /*!< RTC_1Hz : 1 Hz as selected in RTC */ + CLKGEN_CLKOUT_CKSEL_XT_DIV2M = 22, /*!< XT_DIV2M : XT / 2^21 */ + CLKGEN_CLKOUT_CKSEL_XT = 23, /*!< XT : XT */ + CLKGEN_CLKOUT_CKSEL_CG_100Hz = 24, /*!< CG_100Hz : 100 Hz as selected in CLKGEN */ + CLKGEN_CLKOUT_CKSEL_HFRC = 25, /*!< HFRC : HFRC */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 = 26, /*!< HFRC_DIV4 : HFRC / 4 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 = 27, /*!< HFRC_DIV8 : HFRC / 8 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 = 28, /*!< HFRC_DIV16 : HFRC / 16 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 = 29, /*!< HFRC_DIV64 : HFRC / 64 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 = 30, /*!< HFRC_DIV128 : HFRC / 128 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 = 31, /*!< HFRC_DIV256 : HFRC / 256 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 = 32, /*!< HFRC_DIV512 : HFRC / 512 */ + CLKGEN_CLKOUT_CKSEL_FLASH_CLK = 34, /*!< FLASH_CLK : Flash Clock */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 = 35, /*!< LFRC_DIV2 : LFRC / 2 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 = 36, /*!< LFRC_DIV32 : LFRC / 32 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 = 37, /*!< LFRC_DIV512 : LFRC / 512 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K = 38, /*!< LFRC_DIV32K : LFRC / 32768 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV256 = 39, /*!< XT_DIV256 : XT / 256 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV8K = 40, /*!< XT_DIV8K : XT / 8192 */ + CLKGEN_CLKOUT_CKSEL_XT_DIV64K = 41, /*!< XT_DIV64K : XT / 2^16 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 = 42, /*!< ULFRC_DIV16 : Uncal LFRC / 16 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 = 43, /*!< ULFRC_DIV128 : Uncal LFRC / 128 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz = 44, /*!< ULFRC_1Hz : Uncal LFRC / 1024 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K = 45, /*!< ULFRC_DIV4K : Uncal LFRC / 4096 */ + CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M = 46, /*!< ULFRC_DIV1M : Uncal LFRC / 2^20 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K = 47, /*!< HFRC_DIV64K : HFRC / 2^16 */ + CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M = 48, /*!< HFRC_DIV16M : HFRC / 2^24 */ + CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M = 49, /*!< LFRC_DIV1M : LFRC / 2^20 */ + CLKGEN_CLKOUT_CKSEL_HFRCNE = 50, /*!< HFRCNE : HFRC (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 = 51, /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_XTNE = 53, /*!< XTNE : XT (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 = 54, /*!< XTNE_DIV16 : XT / 16 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 = 55, /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled) */ + CLKGEN_CLKOUT_CKSEL_LFRCNE = 57, /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values */ +} CLKGEN_CLKOUT_CKSEL_Enum; + +/* ======================================================== CLKKEY ========================================================= */ +/* ============================================= CLKGEN CLKKEY CLKKEY [0..31] ============================================== */ +typedef enum { /*!< CLKGEN_CLKKEY_CLKKEY */ + CLKGEN_CLKKEY_CLKKEY_Key = 71, /*!< Key : Key */ +} CLKGEN_CLKKEY_CLKKEY_Enum; + +/* ========================================================= CCTRL ========================================================= */ +/* ============================================== CLKGEN CCTRL CORESEL [0..0] ============================================== */ +typedef enum { /*!< CLKGEN_CCTRL_CORESEL */ + CLKGEN_CCTRL_CORESEL_HFRC = 0, /*!< HFRC : Core Clock is HFRC */ + CLKGEN_CCTRL_CORESEL_HFRC_DIV2 = 1, /*!< HFRC_DIV2 : Core Clock is HFRC / 2 */ +} CLKGEN_CCTRL_CORESEL_Enum; + +/* ======================================================== STATUS ========================================================= */ +/* ========================================================= HFADJ ========================================================= */ +/* ============================================ CLKGEN HFADJ HFADJGAIN [21..23] ============================================ */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJGAIN */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1 = 0, /*!< Gain_of_1 : HF Adjust with Gain of 1 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1, /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2, /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3, /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4, /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625 */ + CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5, /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125 */ +} CLKGEN_HFADJ_HFADJGAIN_Enum; + +/* ============================================ CLKGEN HFADJ HFWARMUP [20..20] ============================================= */ +typedef enum { /*!< CLKGEN_HFADJ_HFWARMUP */ + CLKGEN_HFADJ_HFWARMUP_1SEC = 0, /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds */ + CLKGEN_HFADJ_HFWARMUP_2SEC = 1, /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds */ +} CLKGEN_HFADJ_HFWARMUP_Enum; + +/* ============================================== CLKGEN HFADJ HFADJCK [1..3] ============================================== */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJCK */ + CLKGEN_HFADJ_HFADJCK_4SEC = 0, /*!< 4SEC : Autoadjust repeat period = 4 seconds */ + CLKGEN_HFADJ_HFADJCK_16SEC = 1, /*!< 16SEC : Autoadjust repeat period = 16 seconds */ + CLKGEN_HFADJ_HFADJCK_32SEC = 2, /*!< 32SEC : Autoadjust repeat period = 32 seconds */ + CLKGEN_HFADJ_HFADJCK_64SEC = 3, /*!< 64SEC : Autoadjust repeat period = 64 seconds */ + CLKGEN_HFADJ_HFADJCK_128SEC = 4, /*!< 128SEC : Autoadjust repeat period = 128 seconds */ + CLKGEN_HFADJ_HFADJCK_256SEC = 5, /*!< 256SEC : Autoadjust repeat period = 256 seconds */ + CLKGEN_HFADJ_HFADJCK_512SEC = 6, /*!< 512SEC : Autoadjust repeat period = 512 seconds */ + CLKGEN_HFADJ_HFADJCK_1024SEC = 7, /*!< 1024SEC : Autoadjust repeat period = 1024 seconds */ +} CLKGEN_HFADJ_HFADJCK_Enum; + +/* ============================================== CLKGEN HFADJ HFADJEN [0..0] ============================================== */ +typedef enum { /*!< CLKGEN_HFADJ_HFADJEN */ + CLKGEN_HFADJ_HFADJEN_DIS = 0, /*!< DIS : Disable the HFRC adjustment */ + CLKGEN_HFADJ_HFADJEN_EN = 1, /*!< EN : Enable the HFRC adjustment */ +} CLKGEN_HFADJ_HFADJEN_Enum; + +/* ====================================================== CLOCKENSTAT ====================================================== */ +/* ======================================== CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31] ========================================= */ +typedef enum { /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_ADC_CLKEN = 1, /*!< ADC_CLKEN : Clock enable for the ADC. */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_ACTIVITY_CLKEN = 2,/*!< APBDMA_ACTIVITY_CLKEN : Clock enable for the APBDMA ACTIVITY */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOH_CLKEN = 4,/*!< APBDMA_AOH_CLKEN : Clock enable for the APBDMA AOH DOMAIN */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOL_CLKEN = 8,/*!< APBDMA_AOL_CLKEN : Clock enable for the APBDMA AOL DOMAIN */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_APB_CLKEN = 16,/*!< APBDMA_APB_CLKEN : Clock enable for the APBDMA_APB */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_BLEL_CLKEN = 32,/*!< APBDMA_BLEL_CLKEN : Clock enable for the APBDMA_BLEL */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPA_CLKEN = 64,/*!< APBDMA_HCPA_CLKEN : Clock enable for the APBDMA_HCPA */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPB_CLKEN = 128,/*!< APBDMA_HCPB_CLKEN : Clock enable for the APBDMA_HCPB */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPC_CLKEN = 256,/*!< APBDMA_HCPC_CLKEN : Clock enable for the APBDMA_HCPC */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI_CLKEN = 512,/*!< APBDMA_MSPI_CLKEN : Clock enable for the APBDMA_MSPI */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_PDM_CLKEN = 1024,/*!< APBDMA_PDM_CLKEN : Clock enable for the APBDMA_PDM */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK_CLKEN = 2048,/*!< BLEIF_CLK_CLKEN : Clock enable for the BLEIF */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK32K_CLKEN = 4096,/*!< BLEIF_CLK32K_CLKEN : Clock enable for the BLEIF 32khZ CLOCK */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER_CLKEN = 8192,/*!< CTIMER_CLKEN : Clock enable for the CTIMER BLOCK */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0A_CLKEN = 16384,/*!< CTIMER0A_CLKEN : Clock enable for the CTIMER0A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0B_CLKEN = 32768,/*!< CTIMER0B_CLKEN : Clock enable for the CTIMER0B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1A_CLKEN = 65536,/*!< CTIMER1A_CLKEN : Clock enable for the CTIMER1A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1B_CLKEN = 131072,/*!< CTIMER1B_CLKEN : Clock enable for the CTIMER1B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2A_CLKEN = 262144,/*!< CTIMER2A_CLKEN : Clock enable for the CTIMER2A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2B_CLKEN = 524288,/*!< CTIMER2B_CLKEN : Clock enable for the CTIMER2B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3A_CLKEN = 1048576,/*!< CTIMER3A_CLKEN : Clock enable for the CTIMER3A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3B_CLKEN = 2097152,/*!< CTIMER3B_CLKEN : Clock enable for the CTIMER3B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4A_CLKEN = 4194304,/*!< CTIMER4A_CLKEN : Clock enable for the CTIMER4A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4B_CLKEN = 8388608,/*!< CTIMER4B_CLKEN : Clock enable for the CTIMER4B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5A_CLKEN = 16777216,/*!< CTIMER5A_CLKEN : Clock enable for the CTIMER5A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5B_CLKEN = 33554432,/*!< CTIMER5B_CLKEN : Clock enable for the CTIMER5B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6A_CLKEN = 67108864,/*!< CTIMER6A_CLKEN : Clock enable for the CTIMER6A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6B_CLKEN = 134217728,/*!< CTIMER6B_CLKEN : Clock enable for the CTIMER6B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7A_CLKEN = 268435456,/*!< CTIMER7A_CLKEN : Clock enable for the CTIMER7A */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7B_CLKEN = 536870912,/*!< CTIMER7B_CLKEN : Clock enable for the CTIMER7B */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_DAP_CLKEN = 1073741824,/*!< DAP_CLKEN : Clock enable for the DAP */ + CLKGEN_CLOCKENSTAT_CLOCKENSTAT_IOMSTRIFC0_CLKEN = -2147483648,/*!< IOMSTRIFC0_CLKEN : Clock enable for the IOMSTRIFC0 */ +} CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum; + +/* ===================================================== CLOCKEN2STAT ====================================================== */ +/* ======================================= CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31] ======================================== */ +typedef enum { /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC1_CLKEN = 1,/*!< IOMSTRIFC1_CLKEN : Clock enable for the IO MASTER 1 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC2_CLKEN = 2,/*!< IOMSTRIFC2_CLKEN : Clock enable for the IO MASTER 2 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC3_CLKEN = 4,/*!< IOMSTRIFC3_CLKEN : Clock enable for the IO MASTER 3 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC4_CLKEN = 8,/*!< IOMSTRIFC4_CLKEN : Clock enable for the IO MASTER 4 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC5_CLKEN = 16,/*!< IOMSTRIFC5_CLKEN : Clock enable for the IO MASTER 5 IFC INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDM_CLKEN = 32,/*!< PDM_CLKEN : Clock enable for the PDM */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDMIFC_CLKEN = 64,/*!< PDMIFC_CLKEN : Clock enable for the PDM INTERFACE */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_CLKEN = 128,/*!< PWRCTRL_CLKEN : Clock enable for the PWRCTRL */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_COUNT_CLKEN = 256,/*!< PWRCTRL_COUNT_CLKEN : Clock enable for the PWRCTRL counter */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_RSTGEN_CLKEN = 512,/*!< RSTGEN_CLKEN : Clock enable for the RSTGEN */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_CLKEN = 1024,/*!< SCARD_CLKEN : Clock enable for the SCARD */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_ALTAPB_CLKEN = 2048,/*!< SCARD_ALTAPB_CLKEN : Clock enable for the SCARD ALTAPB */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_STIMER_CNT_CLKEN = 4096,/*!< STIMER_CNT_CLKEN : Clock enable for the STIMER_CNT_CLKEN */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_TPIU_CLKEN = 8192,/*!< TPIU_CLKEN : Clock enable for the TPIU_CLKEN */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART0HF_CLKEN = 16384,/*!< UART0HF_CLKEN : Clock enable for the UART0 HF */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART1HF_CLKEN = 32768,/*!< UART1HF_CLKEN : Clock enable for the UART1 HF */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_XT_32KHZ_EN = 1073741824,/*!< XT_32KHZ_EN : Clock enable for the XT 32KHZ */ + CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_FORCEHFRC = -2147483648,/*!< FORCEHFRC : HFRC is forced on Status. */ +} CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum; + +/* ===================================================== CLOCKEN3STAT ====================================================== */ +/* ======================================= CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31] ======================================== */ +typedef enum { /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DAP_enabled = 131072,/*!< DAP_enabled : DAP clock is enabled [17] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_VCOMP_enabled = 262144,/*!< VCOMP_enabled : VCOMP powerdown indicator [18] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_XTAL_enabled = 16777216,/*!< XTAL_enabled : XTAL is enabled [24] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_enabled = 33554432,/*!< HFRC_enabled : HFRC is enabled [25] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFADJEN = 67108864,/*!< HFADJEN : HFRC Adjust enabled [26] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_en_out = 134217728,/*!< HFRC_en_out : HFRC Enabled out [27] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_XT = 268435456,/*!< RTC_XT : RTC use XT [28] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_xtal_en = 536870912,/*!< clkout_xtal_en : XTAL clkout enabled [29] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_hfrc_en = 1073741824,/*!< clkout_hfrc_en : HFRC clkout enabled [30] */ + CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_flashclk_en = -2147483648,/*!< flashclk_en : Flash clk is enabled [31] */ +} CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum; + +/* ======================================================= FREQCTRL ======================================================== */ +/* ============================================ CLKGEN FREQCTRL BURSTREQ [0..0] ============================================ */ +typedef enum { /*!< CLKGEN_FREQCTRL_BURSTREQ */ + CLKGEN_FREQCTRL_BURSTREQ_DIS = 0, /*!< DIS : Frequency for ARM core stays at 48MHz */ + CLKGEN_FREQCTRL_BURSTREQ_EN = 1, /*!< EN : Frequency for ARM core is increased to 96MHz */ +} CLKGEN_FREQCTRL_BURSTREQ_Enum; + +/* ===================================================== BLEBUCKTONADJ ===================================================== */ +/* ===================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTEN [27..27] ===================================== */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_DIS = 0, /*!< DIS : Disable Zero Length Detect */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN = 1, /*!< EN : Enable Zero Length Detect */ +} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Enum; + +/* ==================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTTRIM [23..26] ==================================== */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF = 15,/*!< SetF : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 81us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetE = 14,/*!< SetE : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 75.6us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetD = 13,/*!< SetD : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 70.2us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetC = 12,/*!< SetC : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 64.8us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetB = 11,/*!< SetB : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 59.4us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetA = 10,/*!< SetA : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 54.0us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set9 = 9,/*!< Set9 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 48.6us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set8 = 8,/*!< Set8 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 43.2us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set7 = 7,/*!< Set7 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 37.8us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set6 = 6,/*!< Set6 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 32.4us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set5 = 5,/*!< Set5 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 27.0us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set4 = 4,/*!< Set4 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 21.6us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set3 = 3,/*!< Set3 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 16.2us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set2 = 2,/*!< Set2 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 10.8us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set1 = 1,/*!< Set1 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 5.4us (10 percent margin of error) or more */ + CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set0 = 0,/*!< Set0 : Indicator send when the BLE BUCK asserts blebuck_comp1 + for about 2.0us (10 percent margin of error) or more */ +} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Enum; + +/* ======================================= CLKGEN BLEBUCKTONADJ TONADJUSTEN [22..22] ======================================= */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTEN */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS = 0, /*!< DIS : Disable Adjust for BLE BUCK TON trim */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN = 1, /*!< EN : Enable Adjust for BLE BUCK TON trim */ +} CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Enum; + +/* ===================================== CLKGEN BLEBUCKTONADJ TONADJUSTPERIOD [20..21] ===================================== */ +typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_3KHz = 3,/*!< HFRC_3KHz : Adjust done for every 1 3KHz period */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_12KHz = 2,/*!< HFRC_12KHz : Adjust done for every 1 12KHz period */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_47KHz = 1,/*!< HFRC_47KHz : Adjust done for every 1 47KHz period */ + CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz = 0,/*!< HFRC_94KHz : Adjust done for every 1 94KHz period */ +} CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Enum; + +/* ======================================================= INTRPTEN ======================================================== */ +/* ====================================================== INTRPTSTAT ======================================================= */ +/* ======================================================= INTRPTCLR ======================================================= */ +/* ======================================================= INTRPTSET ======================================================= */ + + +/* =========================================================================================================================== */ +/* ================ CTIMER ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TMR0 ========================================================== */ +/* ======================================================== CMPRA0 ========================================================= */ +/* ======================================================== CMPRB0 ========================================================= */ +/* ========================================================= CTRL0 ========================================================= */ +/* ============================================= CTIMER CTRL0 CTLINK0 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_CTLINK0 */ + CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL0_CTLINK0_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer. */ +} CTIMER_CTRL0_CTLINK0_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0POL */ + CTIMER_CTRL0_TMRB0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the + timer output. */ + CTIMER_CTRL0_TMRB0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of + the timer output. */ +} CTIMER_CTRL0_TMRB0POL_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0CLR */ + CTIMER_CTRL0_TMRB0CLR_RUN = 0, /*!< RUN : Allow counter/timer B0 to run */ + CTIMER_CTRL0_TMRB0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B0 at 0x0000. */ +} CTIMER_CTRL0_TMRB0CLR_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0IE1 */ + CTIMER_CTRL0_TMRB0IE1_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL0_TMRB0IE1_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL0_TMRB0IE1_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0IE0 */ + CTIMER_CTRL0_TMRB0IE0_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL0_TMRB0IE0_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL0_TMRB0IE0_Enum; + +/* ============================================= CTIMER CTRL0 TMRB0FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0FN */ + CTIMER_CTRL0_TMRB0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B0, stop. */ + CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B0, restart. */ + CTIMER_CTRL0_TMRB0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert, + count to CMPR1B0, deassert, stop. */ + CTIMER_CTRL0_TMRB0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B0, assert, count + to CMPR1B0, deassert, restart. */ + CTIMER_CTRL0_TMRB0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL0_TMRB0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL0_TMRB0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL0_TMRB0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL0_TMRB0FN_Enum; + +/* ============================================ CTIMER CTRL0 TMRB0CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0CLK */ + CTIMER_CTRL0_TMRB0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL0_TMRB0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL0_TMRB0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL0_TMRB0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL0_TMRB0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL0_TMRB0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL0_TMRB0CLK_CTMRA0 = 20, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB1 = 21, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRA1 = 22, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL0_TMRB0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL0_TMRB0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL0_TMRB0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL0_TMRB0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL0_TMRB0CLK_Enum; + +/* ============================================= CTIMER CTRL0 TMRB0EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRB0EN */ + CTIMER_CTRL0_TMRB0EN_DIS = 0, /*!< DIS : Counter/Timer B0 Disable. */ + CTIMER_CTRL0_TMRB0EN_EN = 1, /*!< EN : Counter/Timer B0 Enable. */ +} CTIMER_CTRL0_TMRB0EN_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0POL */ + CTIMER_CTRL0_TMRA0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the + timer output. */ + CTIMER_CTRL0_TMRA0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of + the timer output. */ +} CTIMER_CTRL0_TMRA0POL_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0CLR */ + CTIMER_CTRL0_TMRA0CLR_RUN = 0, /*!< RUN : Allow counter/timer A0 to run */ + CTIMER_CTRL0_TMRA0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A0 at 0x0000. */ +} CTIMER_CTRL0_TMRA0CLR_Enum; + +/* ============================================ CTIMER CTRL0 TMRA0IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0IE1 */ + CTIMER_CTRL0_TMRA0IE1_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL0_TMRA0IE1_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL0_TMRA0IE1_Enum; + +/* ============================================= CTIMER CTRL0 TMRA0IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0IE0 */ + CTIMER_CTRL0_TMRA0IE0_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL0_TMRA0IE0_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL0_TMRA0IE0_Enum; + +/* ============================================== CTIMER CTRL0 TMRA0FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0FN */ + CTIMER_CTRL0_TMRA0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A0, stop. */ + CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A0, restart. */ + CTIMER_CTRL0_TMRA0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert, + count to CMPR1A0, deassert, stop. */ + CTIMER_CTRL0_TMRA0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A0, assert, count + to CMPR1A0, deassert, restart. */ + CTIMER_CTRL0_TMRA0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL0_TMRA0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL0_TMRA0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL0_TMRA0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL0_TMRA0FN_Enum; + +/* ============================================= CTIMER CTRL0 TMRA0CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0CLK */ + CTIMER_CTRL0_TMRA0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL0_TMRA0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL0_TMRA0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL0_TMRA0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL0_TMRA0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL0_TMRA0CLK_CTMRB0 = 20, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL0_TMRA0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL0_TMRA0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL0_TMRA0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL0_TMRA0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL0_TMRA0CLK_Enum; + +/* ============================================== CTIMER CTRL0 TMRA0EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL0_TMRA0EN */ + CTIMER_CTRL0_TMRA0EN_DIS = 0, /*!< DIS : Counter/Timer A0 Disable. */ + CTIMER_CTRL0_TMRA0EN_EN = 1, /*!< EN : Counter/Timer A0 Enable. */ +} CTIMER_CTRL0_TMRA0EN_Enum; + +/* ======================================================= CMPRAUXA0 ======================================================= */ +/* ======================================================= CMPRAUXB0 ======================================================= */ +/* ========================================================= AUX0 ========================================================== */ +/* ============================================ CTIMER AUX0 TMRB0EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRB0EN23 */ + CTIMER_AUX0_TMRB0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX0_TMRB0EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX0_TMRB0EN23_Enum; + +/* ============================================ CTIMER AUX0 TMRB0POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRB0POL23 */ + CTIMER_AUX0_TMRB0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX0_TMRB0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX0_TMRB0POL23_Enum; + +/* ============================================ CTIMER AUX0 TMRB0TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRB0TINV */ + CTIMER_AUX0_TMRB0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX0_TMRB0TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX0_TMRB0TINV_Enum; + +/* =========================================== CTIMER AUX0 TMRB0NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRB0NOSYNC */ + CTIMER_AUX0_TMRB0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX0_TMRB0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX0_TMRB0NOSYNC_Enum; + +/* ============================================ CTIMER AUX0 TMRB0TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRB0TRIG */ + CTIMER_AUX0_TMRB0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX0_TMRB0TRIG_A0OUT = 1, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX0_TMRB0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B2OUT = 4, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX0_TMRB0TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX0_TMRB0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_B7OUT2 = 10, /*!< B7OUT2 : Trigger source is CTIMERB7 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX0_TMRB0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX0_TMRB0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX0_TMRB0TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX0_TMRB0TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX0_TMRB0TRIG_Enum; + +/* ============================================ CTIMER AUX0 TMRA0EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRA0EN23 */ + CTIMER_AUX0_TMRA0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX0_TMRA0EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX0_TMRA0EN23_Enum; + +/* ============================================ CTIMER AUX0 TMRA0POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRA0POL23 */ + CTIMER_AUX0_TMRA0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX0_TMRA0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX0_TMRA0POL23_Enum; + +/* ============================================ CTIMER AUX0 TMRA0TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRA0TINV */ + CTIMER_AUX0_TMRA0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX0_TMRA0TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX0_TMRA0TINV_Enum; + +/* =========================================== CTIMER AUX0 TMRA0NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX0_TMRA0NOSYNC */ + CTIMER_AUX0_TMRA0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX0_TMRA0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX0_TMRA0NOSYNC_Enum; + +/* ============================================= CTIMER AUX0 TMRA0TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX0_TMRA0TRIG */ + CTIMER_AUX0_TMRA0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX0_TMRA0TRIG_B0OUT = 1, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX0_TMRA0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX0_TMRA0TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX0_TMRA0TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX0_TMRA0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_B6OUT2 = 10, /*!< B6OUT2 : Trigger source is CTIMERB6 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX0_TMRA0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX0_TMRA0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX0_TMRA0TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX0_TMRA0TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX0_TMRA0TRIG_Enum; + +/* ========================================================= TMR1 ========================================================== */ +/* ======================================================== CMPRA1 ========================================================= */ +/* ======================================================== CMPRB1 ========================================================= */ +/* ========================================================= CTRL1 ========================================================= */ +/* ============================================= CTIMER CTRL1 CTLINK1 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_CTLINK1 */ + CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A1/B1 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL1_CTLINK1_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer. */ +} CTIMER_CTRL1_CTLINK1_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1POL */ + CTIMER_CTRL1_TMRB1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the + timer output. */ + CTIMER_CTRL1_TMRB1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of + the timer output. */ +} CTIMER_CTRL1_TMRB1POL_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1CLR */ + CTIMER_CTRL1_TMRB1CLR_RUN = 0, /*!< RUN : Allow counter/timer B1 to run */ + CTIMER_CTRL1_TMRB1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B1 at 0x0000. */ +} CTIMER_CTRL1_TMRB1CLR_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1IE1 */ + CTIMER_CTRL1_TMRB1IE1_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL1_TMRB1IE1_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL1_TMRB1IE1_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1IE0 */ + CTIMER_CTRL1_TMRB1IE0_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL1_TMRB1IE0_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL1_TMRB1IE0_Enum; + +/* ============================================= CTIMER CTRL1 TMRB1FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1FN */ + CTIMER_CTRL1_TMRB1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B1, stop. */ + CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B1, restart. */ + CTIMER_CTRL1_TMRB1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert, + count to CMPR1B1, deassert, stop. */ + CTIMER_CTRL1_TMRB1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B1, assert, count + to CMPR1B1, deassert, restart. */ + CTIMER_CTRL1_TMRB1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL1_TMRB1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL1_TMRB1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL1_TMRB1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL1_TMRB1FN_Enum; + +/* ============================================ CTIMER CTRL1 TMRB1CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1CLK */ + CTIMER_CTRL1_TMRB1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL1_TMRB1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL1_TMRB1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL1_TMRB1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL1_TMRB1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL1_TMRB1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL1_TMRB1CLK_CTMRA1 = 20, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL1_TMRB1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL1_TMRB1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL1_TMRB1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL1_TMRB1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL1_TMRB1CLK_Enum; + +/* ============================================= CTIMER CTRL1 TMRB1EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRB1EN */ + CTIMER_CTRL1_TMRB1EN_DIS = 0, /*!< DIS : Counter/Timer B1 Disable. */ + CTIMER_CTRL1_TMRB1EN_EN = 1, /*!< EN : Counter/Timer B1 Enable. */ +} CTIMER_CTRL1_TMRB1EN_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1POL */ + CTIMER_CTRL1_TMRA1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the + timer output. */ + CTIMER_CTRL1_TMRA1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of + the timer output. */ +} CTIMER_CTRL1_TMRA1POL_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1CLR */ + CTIMER_CTRL1_TMRA1CLR_RUN = 0, /*!< RUN : Allow counter/timer A1 to run */ + CTIMER_CTRL1_TMRA1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A1 at 0x0000. */ +} CTIMER_CTRL1_TMRA1CLR_Enum; + +/* ============================================ CTIMER CTRL1 TMRA1IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1IE1 */ + CTIMER_CTRL1_TMRA1IE1_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL1_TMRA1IE1_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL1_TMRA1IE1_Enum; + +/* ============================================= CTIMER CTRL1 TMRA1IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1IE0 */ + CTIMER_CTRL1_TMRA1IE0_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL1_TMRA1IE0_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL1_TMRA1IE0_Enum; + +/* ============================================== CTIMER CTRL1 TMRA1FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1FN */ + CTIMER_CTRL1_TMRA1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A1, stop. */ + CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A1, restart. */ + CTIMER_CTRL1_TMRA1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert, + count to CMPR1A1, deassert, stop. */ + CTIMER_CTRL1_TMRA1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A1, assert, count + to CMPR1A1, deassert, restart. */ + CTIMER_CTRL1_TMRA1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL1_TMRA1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL1_TMRA1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL1_TMRA1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL1_TMRA1FN_Enum; + +/* ============================================= CTIMER CTRL1 TMRA1CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1CLK */ + CTIMER_CTRL1_TMRA1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL1_TMRA1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL1_TMRA1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL1_TMRA1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL1_TMRA1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL1_TMRA1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL1_TMRA1CLK_CTMRB1 = 20, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL1_TMRA1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL1_TMRA1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL1_TMRA1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL1_TMRA1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL1_TMRA1CLK_Enum; + +/* ============================================== CTIMER CTRL1 TMRA1EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL1_TMRA1EN */ + CTIMER_CTRL1_TMRA1EN_DIS = 0, /*!< DIS : Counter/Timer A1 Disable. */ + CTIMER_CTRL1_TMRA1EN_EN = 1, /*!< EN : Counter/Timer A1 Enable. */ +} CTIMER_CTRL1_TMRA1EN_Enum; + +/* ======================================================= CMPRAUXA1 ======================================================= */ +/* ======================================================= CMPRAUXB1 ======================================================= */ +/* ========================================================= AUX1 ========================================================== */ +/* ============================================ CTIMER AUX1 TMRB1EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRB1EN23 */ + CTIMER_AUX1_TMRB1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX1_TMRB1EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX1_TMRB1EN23_Enum; + +/* ============================================ CTIMER AUX1 TMRB1POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRB1POL23 */ + CTIMER_AUX1_TMRB1POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX1_TMRB1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX1_TMRB1POL23_Enum; + +/* ============================================ CTIMER AUX1 TMRB1TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRB1TINV */ + CTIMER_AUX1_TMRB1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX1_TMRB1TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX1_TMRB1TINV_Enum; + +/* =========================================== CTIMER AUX1 TMRB1NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRB1NOSYNC */ + CTIMER_AUX1_TMRB1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX1_TMRB1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX1_TMRB1NOSYNC_Enum; + +/* ============================================ CTIMER AUX1 TMRB1TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRB1TRIG */ + CTIMER_AUX1_TMRB1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX1_TMRB1TRIG_A1OUT = 1, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX1_TMRB1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX1_TMRB1TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX1_TMRB1TRIG_A0OUT = 6, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B0OUT = 7, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX1_TMRB1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */ + CTIMER_AUX1_TMRB1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX1_TMRB1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX1_TMRB1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX1_TMRB1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX1_TMRB1TRIG_Enum; + +/* ============================================ CTIMER AUX1 TMRA1EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRA1EN23 */ + CTIMER_AUX1_TMRA1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX1_TMRA1EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX1_TMRA1EN23_Enum; + +/* ============================================ CTIMER AUX1 TMRA1POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRA1POL23 */ + CTIMER_AUX1_TMRA1POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */ + CTIMER_AUX1_TMRA1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX1_TMRA1POL23_Enum; + +/* ============================================ CTIMER AUX1 TMRA1TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRA1TINV */ + CTIMER_AUX1_TMRA1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX1_TMRA1TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX1_TMRA1TINV_Enum; + +/* =========================================== CTIMER AUX1 TMRA1NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX1_TMRA1NOSYNC */ + CTIMER_AUX1_TMRA1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX1_TMRA1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX1_TMRA1NOSYNC_Enum; + +/* ============================================= CTIMER AUX1 TMRA1TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX1_TMRA1TRIG */ + CTIMER_AUX1_TMRA1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX1_TMRA1TRIG_B1OUT = 1, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX1_TMRA1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX1_TMRA1TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX1_TMRA1TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX1_TMRA1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */ + CTIMER_AUX1_TMRA1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX1_TMRA1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX1_TMRA1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX1_TMRA1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX1_TMRA1TRIG_Enum; + +/* ========================================================= TMR2 ========================================================== */ +/* ======================================================== CMPRA2 ========================================================= */ +/* ======================================================== CMPRB2 ========================================================= */ +/* ========================================================= CTRL2 ========================================================= */ +/* ============================================= CTIMER CTRL2 CTLINK2 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_CTLINK2 */ + CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A2/B2 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL2_CTLINK2_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer. */ +} CTIMER_CTRL2_CTLINK2_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2POL */ + CTIMER_CTRL2_TMRB2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the + timer output. */ + CTIMER_CTRL2_TMRB2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of + the timer output. */ +} CTIMER_CTRL2_TMRB2POL_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2CLR */ + CTIMER_CTRL2_TMRB2CLR_RUN = 0, /*!< RUN : Allow counter/timer B2 to run */ + CTIMER_CTRL2_TMRB2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B2 at 0x0000. */ +} CTIMER_CTRL2_TMRB2CLR_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2IE1 */ + CTIMER_CTRL2_TMRB2IE1_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL2_TMRB2IE1_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL2_TMRB2IE1_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2IE0 */ + CTIMER_CTRL2_TMRB2IE0_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL2_TMRB2IE0_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL2_TMRB2IE0_Enum; + +/* ============================================= CTIMER CTRL2 TMRB2FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2FN */ + CTIMER_CTRL2_TMRB2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B2, stop. */ + CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B2, restart. */ + CTIMER_CTRL2_TMRB2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert, + count to CMPR1B2, deassert, stop. */ + CTIMER_CTRL2_TMRB2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B2, assert, count + to CMPR1B2, deassert, restart. */ + CTIMER_CTRL2_TMRB2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL2_TMRB2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL2_TMRB2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL2_TMRB2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL2_TMRB2FN_Enum; + +/* ============================================ CTIMER CTRL2 TMRB2CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2CLK */ + CTIMER_CTRL2_TMRB2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL2_TMRB2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL2_TMRB2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL2_TMRB2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL2_TMRB2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL2_TMRB2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL2_TMRB2CLK_CTMRA2 = 20, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL2_TMRB2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL2_TMRB2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL2_TMRB2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL2_TMRB2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL2_TMRB2CLK_Enum; + +/* ============================================= CTIMER CTRL2 TMRB2EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRB2EN */ + CTIMER_CTRL2_TMRB2EN_DIS = 0, /*!< DIS : Counter/Timer B2 Disable. */ + CTIMER_CTRL2_TMRB2EN_EN = 1, /*!< EN : Counter/Timer B2 Enable. */ +} CTIMER_CTRL2_TMRB2EN_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2POL */ + CTIMER_CTRL2_TMRA2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the + timer output. */ + CTIMER_CTRL2_TMRA2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of + the timer output. */ +} CTIMER_CTRL2_TMRA2POL_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2CLR */ + CTIMER_CTRL2_TMRA2CLR_RUN = 0, /*!< RUN : Allow counter/timer A2 to run */ + CTIMER_CTRL2_TMRA2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A2 at 0x0000. */ +} CTIMER_CTRL2_TMRA2CLR_Enum; + +/* ============================================ CTIMER CTRL2 TMRA2IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2IE1 */ + CTIMER_CTRL2_TMRA2IE1_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL2_TMRA2IE1_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL2_TMRA2IE1_Enum; + +/* ============================================= CTIMER CTRL2 TMRA2IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2IE0 */ + CTIMER_CTRL2_TMRA2IE0_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL2_TMRA2IE0_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL2_TMRA2IE0_Enum; + +/* ============================================== CTIMER CTRL2 TMRA2FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2FN */ + CTIMER_CTRL2_TMRA2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A2, stop. */ + CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A2, restart. */ + CTIMER_CTRL2_TMRA2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert, + count to CMPR1A2, deassert, stop. */ + CTIMER_CTRL2_TMRA2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A2, assert, count + to CMPR1A2, deassert, restart. */ + CTIMER_CTRL2_TMRA2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL2_TMRA2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL2_TMRA2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL2_TMRA2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL2_TMRA2FN_Enum; + +/* ============================================= CTIMER CTRL2 TMRA2CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2CLK */ + CTIMER_CTRL2_TMRA2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL2_TMRA2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL2_TMRA2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL2_TMRA2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL2_TMRA2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL2_TMRA2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL2_TMRA2CLK_CTMRB2 = 20, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL2_TMRA2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL2_TMRA2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL2_TMRA2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL2_TMRA2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL2_TMRA2CLK_Enum; + +/* ============================================== CTIMER CTRL2 TMRA2EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL2_TMRA2EN */ + CTIMER_CTRL2_TMRA2EN_DIS = 0, /*!< DIS : Counter/Timer A2 Disable. */ + CTIMER_CTRL2_TMRA2EN_EN = 1, /*!< EN : Counter/Timer A2 Enable. */ +} CTIMER_CTRL2_TMRA2EN_Enum; + +/* ======================================================= CMPRAUXA2 ======================================================= */ +/* ======================================================= CMPRAUXB2 ======================================================= */ +/* ========================================================= AUX2 ========================================================== */ +/* ============================================ CTIMER AUX2 TMRB2EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRB2EN23 */ + CTIMER_AUX2_TMRB2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX2_TMRB2EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX2_TMRB2EN23_Enum; + +/* ============================================ CTIMER AUX2 TMRB2POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRB2POL23 */ + CTIMER_AUX2_TMRB2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX2_TMRB2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX2_TMRB2POL23_Enum; + +/* ============================================ CTIMER AUX2 TMRB2TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRB2TINV */ + CTIMER_AUX2_TMRB2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX2_TMRB2TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX2_TMRB2TINV_Enum; + +/* =========================================== CTIMER AUX2 TMRB2NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRB2NOSYNC */ + CTIMER_AUX2_TMRB2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX2_TMRB2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX2_TMRB2NOSYNC_Enum; + +/* ============================================ CTIMER AUX2 TMRB2TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRB2TRIG */ + CTIMER_AUX2_TMRB2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX2_TMRB2TRIG_A2OUT = 1, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX2_TMRB2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX2_TMRB2TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX2_TMRB2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX2_TMRB2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX2_TMRB2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX2_TMRB2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX2_TMRB2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX2_TMRB2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX2_TMRB2TRIG_Enum; + +/* ============================================ CTIMER AUX2 TMRA2EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRA2EN23 */ + CTIMER_AUX2_TMRA2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX2_TMRA2EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX2_TMRA2EN23_Enum; + +/* ============================================ CTIMER AUX2 TMRA2POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRA2POL23 */ + CTIMER_AUX2_TMRA2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX2_TMRA2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX2_TMRA2POL23_Enum; + +/* ============================================ CTIMER AUX2 TMRA2TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRA2TINV */ + CTIMER_AUX2_TMRA2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX2_TMRA2TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX2_TMRA2TINV_Enum; + +/* =========================================== CTIMER AUX2 TMRA2NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX2_TMRA2NOSYNC */ + CTIMER_AUX2_TMRA2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX2_TMRA2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX2_TMRA2NOSYNC_Enum; + +/* ============================================= CTIMER AUX2 TMRA2TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX2_TMRA2TRIG */ + CTIMER_AUX2_TMRA2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX2_TMRA2TRIG_B2OUT = 1, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX2_TMRA2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX2_TMRA2TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ + CTIMER_AUX2_TMRA2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX2_TMRA2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX2_TMRA2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX2_TMRA2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX2_TMRA2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX2_TMRA2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX2_TMRA2TRIG_Enum; + +/* ========================================================= TMR3 ========================================================== */ +/* ======================================================== CMPRA3 ========================================================= */ +/* ======================================================== CMPRB3 ========================================================= */ +/* ========================================================= CTRL3 ========================================================= */ +/* ============================================= CTIMER CTRL3 CTLINK3 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_CTLINK3 */ + CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A3/B3 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL3_CTLINK3_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer. */ +} CTIMER_CTRL3_CTLINK3_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3POL */ + CTIMER_CTRL3_TMRB3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the + timer output. */ + CTIMER_CTRL3_TMRB3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of + the timer output. */ +} CTIMER_CTRL3_TMRB3POL_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3CLR */ + CTIMER_CTRL3_TMRB3CLR_RUN = 0, /*!< RUN : Allow counter/timer B3 to run */ + CTIMER_CTRL3_TMRB3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B3 at 0x0000. */ +} CTIMER_CTRL3_TMRB3CLR_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3IE1 */ + CTIMER_CTRL3_TMRB3IE1_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL3_TMRB3IE1_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL3_TMRB3IE1_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3IE0 */ + CTIMER_CTRL3_TMRB3IE0_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL3_TMRB3IE0_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL3_TMRB3IE0_Enum; + +/* ============================================= CTIMER CTRL3 TMRB3FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3FN */ + CTIMER_CTRL3_TMRB3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B3, stop. */ + CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B3, restart. */ + CTIMER_CTRL3_TMRB3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert, + count to CMPR1B3, deassert, stop. */ + CTIMER_CTRL3_TMRB3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B3, assert, count + to CMPR1B3, deassert, restart. */ + CTIMER_CTRL3_TMRB3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL3_TMRB3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL3_TMRB3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL3_TMRB3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL3_TMRB3FN_Enum; + +/* ============================================ CTIMER CTRL3 TMRB3CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3CLK */ + CTIMER_CTRL3_TMRB3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL3_TMRB3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL3_TMRB3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL3_TMRB3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL3_TMRB3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL3_TMRB3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL3_TMRB3CLK_CTMRA3 = 20, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL3_TMRB3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL3_TMRB3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL3_TMRB3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL3_TMRB3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL3_TMRB3CLK_Enum; + +/* ============================================= CTIMER CTRL3 TMRB3EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRB3EN */ + CTIMER_CTRL3_TMRB3EN_DIS = 0, /*!< DIS : Counter/Timer B3 Disable. */ + CTIMER_CTRL3_TMRB3EN_EN = 1, /*!< EN : Counter/Timer B3 Enable. */ +} CTIMER_CTRL3_TMRB3EN_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3POL */ + CTIMER_CTRL3_TMRA3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the + timer output. */ + CTIMER_CTRL3_TMRA3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of + the timer output. */ +} CTIMER_CTRL3_TMRA3POL_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3CLR */ + CTIMER_CTRL3_TMRA3CLR_RUN = 0, /*!< RUN : Allow counter/timer A3 to run */ + CTIMER_CTRL3_TMRA3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A3 at 0x0000. */ +} CTIMER_CTRL3_TMRA3CLR_Enum; + +/* ============================================ CTIMER CTRL3 TMRA3IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3IE1 */ + CTIMER_CTRL3_TMRA3IE1_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL3_TMRA3IE1_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL3_TMRA3IE1_Enum; + +/* ============================================= CTIMER CTRL3 TMRA3IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3IE0 */ + CTIMER_CTRL3_TMRA3IE0_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL3_TMRA3IE0_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL3_TMRA3IE0_Enum; + +/* ============================================== CTIMER CTRL3 TMRA3FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3FN */ + CTIMER_CTRL3_TMRA3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A3, stop. */ + CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A3, restart. */ + CTIMER_CTRL3_TMRA3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert, + count to CMPR1A3, deassert, stop. */ + CTIMER_CTRL3_TMRA3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A3, assert, count + to CMPR1A3, deassert, restart. */ + CTIMER_CTRL3_TMRA3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL3_TMRA3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL3_TMRA3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL3_TMRA3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL3_TMRA3FN_Enum; + +/* ============================================= CTIMER CTRL3 TMRA3CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3CLK */ + CTIMER_CTRL3_TMRA3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL3_TMRA3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL3_TMRA3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL3_TMRA3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL3_TMRA3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL3_TMRA3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL3_TMRA3CLK_CTMRB3 = 20, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL3_TMRA3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL3_TMRA3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL3_TMRA3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL3_TMRA3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL3_TMRA3CLK_Enum; + +/* ============================================== CTIMER CTRL3 TMRA3EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL3_TMRA3EN */ + CTIMER_CTRL3_TMRA3EN_DIS = 0, /*!< DIS : Counter/Timer A3 Disable. */ + CTIMER_CTRL3_TMRA3EN_EN = 1, /*!< EN : Counter/Timer A3 Enable. */ +} CTIMER_CTRL3_TMRA3EN_Enum; + +/* ======================================================= CMPRAUXA3 ======================================================= */ +/* ======================================================= CMPRAUXB3 ======================================================= */ +/* ========================================================= AUX3 ========================================================== */ +/* ============================================ CTIMER AUX3 TMRB3EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRB3EN23 */ + CTIMER_AUX3_TMRB3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX3_TMRB3EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX3_TMRB3EN23_Enum; + +/* ============================================ CTIMER AUX3 TMRB3POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRB3POL23 */ + CTIMER_AUX3_TMRB3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX3_TMRB3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX3_TMRB3POL23_Enum; + +/* ============================================ CTIMER AUX3 TMRB3TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRB3TINV */ + CTIMER_AUX3_TMRB3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX3_TMRB3TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX3_TMRB3TINV_Enum; + +/* =========================================== CTIMER AUX3 TMRB3NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRB3NOSYNC */ + CTIMER_AUX3_TMRB3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX3_TMRB3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX3_TMRB3NOSYNC_Enum; + +/* ============================================ CTIMER AUX3 TMRB3TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRB3TRIG */ + CTIMER_AUX3_TMRB3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX3_TMRB3TRIG_A3OUT = 1, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX3_TMRB3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX3_TMRB3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX3_TMRB3TRIG_A6OUT = 6, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B6OUT = 7, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX3_TMRB3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX3_TMRB3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX3_TMRB3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX3_TMRB3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */ + CTIMER_AUX3_TMRB3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */ +} CTIMER_AUX3_TMRB3TRIG_Enum; + +/* ============================================ CTIMER AUX3 TMRA3EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRA3EN23 */ + CTIMER_AUX3_TMRA3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX3_TMRA3EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX3_TMRA3EN23_Enum; + +/* ============================================ CTIMER AUX3 TMRA3POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRA3POL23 */ + CTIMER_AUX3_TMRA3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX3_TMRA3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX3_TMRA3POL23_Enum; + +/* ============================================ CTIMER AUX3 TMRA3TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRA3TINV */ + CTIMER_AUX3_TMRA3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX3_TMRA3TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX3_TMRA3TINV_Enum; + +/* =========================================== CTIMER AUX3 TMRA3NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX3_TMRA3NOSYNC */ + CTIMER_AUX3_TMRA3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX3_TMRA3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX3_TMRA3NOSYNC_Enum; + +/* ============================================= CTIMER AUX3 TMRA3TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX3_TMRA3TRIG */ + CTIMER_AUX3_TMRA3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX3_TMRA3TRIG_B3OUT = 1, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX3_TMRA3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX3_TMRA3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX3_TMRA3TRIG_A7OUT = 6, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B7OUT = 7, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ + CTIMER_AUX3_TMRA3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX3_TMRA3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX3_TMRA3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX3_TMRA3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */ + CTIMER_AUX3_TMRA3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */ +} CTIMER_AUX3_TMRA3TRIG_Enum; + +/* ========================================================= TMR4 ========================================================== */ +/* ======================================================== CMPRA4 ========================================================= */ +/* ======================================================== CMPRB4 ========================================================= */ +/* ========================================================= CTRL4 ========================================================= */ +/* ============================================= CTIMER CTRL4 CTLINK4 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_CTLINK4 */ + CTIMER_CTRL4_CTLINK4_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A4/B4 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL4_CTLINK4_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A4/B4 timers into a single 32-bit timer. */ +} CTIMER_CTRL4_CTLINK4_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4POL */ + CTIMER_CTRL4_TMRB4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB4 pin is the same as the + timer output. */ + CTIMER_CTRL4_TMRB4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB4 pin is the inverse of + the timer output. */ +} CTIMER_CTRL4_TMRB4POL_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4CLR */ + CTIMER_CTRL4_TMRB4CLR_RUN = 0, /*!< RUN : Allow counter/timer B4 to run */ + CTIMER_CTRL4_TMRB4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B4 at 0x0000. */ +} CTIMER_CTRL4_TMRB4CLR_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4IE1 */ + CTIMER_CTRL4_TMRB4IE1_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL4_TMRB4IE1_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL4_TMRB4IE1_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4IE0 */ + CTIMER_CTRL4_TMRB4IE0_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL4_TMRB4IE0_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL4_TMRB4IE0_Enum; + +/* ============================================= CTIMER CTRL4 TMRB4FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4FN */ + CTIMER_CTRL4_TMRB4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B4, stop. */ + CTIMER_CTRL4_TMRB4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B4, restart. */ + CTIMER_CTRL4_TMRB4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B4, assert, + count to CMPR1B4, deassert, stop. */ + CTIMER_CTRL4_TMRB4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B4, assert, count + to CMPR1B4, deassert, restart. */ + CTIMER_CTRL4_TMRB4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL4_TMRB4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL4_TMRB4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL4_TMRB4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL4_TMRB4FN_Enum; + +/* ============================================ CTIMER CTRL4 TMRB4CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4CLK */ + CTIMER_CTRL4_TMRB4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL4_TMRB4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL4_TMRB4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL4_TMRB4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL4_TMRB4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL4_TMRB4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL4_TMRB4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL4_TMRB4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL4_TMRB4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL4_TMRB4CLK_CTMRA4 = 20, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL4_TMRB4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL4_TMRB4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL4_TMRB4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL4_TMRB4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL4_TMRB4CLK_Enum; + +/* ============================================= CTIMER CTRL4 TMRB4EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRB4EN */ + CTIMER_CTRL4_TMRB4EN_DIS = 0, /*!< DIS : Counter/Timer B4 Disable. */ + CTIMER_CTRL4_TMRB4EN_EN = 1, /*!< EN : Counter/Timer B4 Enable. */ +} CTIMER_CTRL4_TMRB4EN_Enum; + +/* ============================================ CTIMER CTRL4 TMRA4POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4POL */ + CTIMER_CTRL4_TMRA4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA4 pin is the same as the + timer output. */ + CTIMER_CTRL4_TMRA4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA4 pin is the inverse of + the timer output. */ +} CTIMER_CTRL4_TMRA4POL_Enum; + +/* ============================================ CTIMER CTRL4 TMRA4CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4CLR */ + CTIMER_CTRL4_TMRA4CLR_RUN = 0, /*!< RUN : Allow counter/timer A4 to run */ + CTIMER_CTRL4_TMRA4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A4 at 0x0000. */ +} CTIMER_CTRL4_TMRA4CLR_Enum; + +/* ============================================ CTIMER CTRL4 TMRA4IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4IE1 */ + CTIMER_CTRL4_TMRA4IE1_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL4_TMRA4IE1_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL4_TMRA4IE1_Enum; + +/* ============================================= CTIMER CTRL4 TMRA4IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4IE0 */ + CTIMER_CTRL4_TMRA4IE0_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL4_TMRA4IE0_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL4_TMRA4IE0_Enum; + +/* ============================================== CTIMER CTRL4 TMRA4FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4FN */ + CTIMER_CTRL4_TMRA4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A4, stop. */ + CTIMER_CTRL4_TMRA4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A4, restart. */ + CTIMER_CTRL4_TMRA4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A4, assert, + count to CMPR1A4, deassert, stop. */ + CTIMER_CTRL4_TMRA4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A4, assert, count + to CMPR1A4, deassert, restart. */ + CTIMER_CTRL4_TMRA4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL4_TMRA4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL4_TMRA4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL4_TMRA4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL4_TMRA4FN_Enum; + +/* ============================================= CTIMER CTRL4 TMRA4CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4CLK */ + CTIMER_CTRL4_TMRA4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL4_TMRA4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL4_TMRA4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL4_TMRA4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL4_TMRA4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL4_TMRA4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL4_TMRA4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL4_TMRA4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4. (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL4_TMRA4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL4_TMRA4CLK_CTMRB4 = 20, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL4_TMRA4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL4_TMRA4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL4_TMRA4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL4_TMRA4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL4_TMRA4CLK_Enum; + +/* ============================================== CTIMER CTRL4 TMRA4EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL4_TMRA4EN */ + CTIMER_CTRL4_TMRA4EN_DIS = 0, /*!< DIS : Counter/Timer A4 Disable. */ + CTIMER_CTRL4_TMRA4EN_EN = 1, /*!< EN : Counter/Timer A4 Enable. */ +} CTIMER_CTRL4_TMRA4EN_Enum; + +/* ======================================================= CMPRAUXA4 ======================================================= */ +/* ======================================================= CMPRAUXB4 ======================================================= */ +/* ========================================================= AUX4 ========================================================== */ +/* ============================================ CTIMER AUX4 TMRB4EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRB4EN23 */ + CTIMER_AUX4_TMRB4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX4_TMRB4EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX4_TMRB4EN23_Enum; + +/* ============================================ CTIMER AUX4 TMRB4POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRB4POL23 */ + CTIMER_AUX4_TMRB4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX4_TMRB4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX4_TMRB4POL23_Enum; + +/* ============================================ CTIMER AUX4 TMRB4TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRB4TINV */ + CTIMER_AUX4_TMRB4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX4_TMRB4TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX4_TMRB4TINV_Enum; + +/* =========================================== CTIMER AUX4 TMRB4NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRB4NOSYNC */ + CTIMER_AUX4_TMRB4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX4_TMRB4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX4_TMRB4NOSYNC_Enum; + +/* ============================================ CTIMER AUX4 TMRB4TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRB4TRIG */ + CTIMER_AUX4_TMRB4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX4_TMRB4TRIG_A4OUT = 1, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX4_TMRB4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX4_TMRB4TRIG_A7OUT = 4, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B7OUT = 5, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ + CTIMER_AUX4_TMRB4TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX4_TMRB4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX4_TMRB4TRIG_Enum; + +/* ============================================ CTIMER AUX4 TMRA4EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRA4EN23 */ + CTIMER_AUX4_TMRA4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX4_TMRA4EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX4_TMRA4EN23_Enum; + +/* ============================================ CTIMER AUX4 TMRA4POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRA4POL23 */ + CTIMER_AUX4_TMRA4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX4_TMRA4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX4_TMRA4POL23_Enum; + +/* ============================================ CTIMER AUX4 TMRA4TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRA4TINV */ + CTIMER_AUX4_TMRA4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX4_TMRA4TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX4_TMRA4TINV_Enum; + +/* =========================================== CTIMER AUX4 TMRA4NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX4_TMRA4NOSYNC */ + CTIMER_AUX4_TMRA4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX4_TMRA4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX4_TMRA4NOSYNC_Enum; + +/* ============================================= CTIMER AUX4 TMRA4TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX4_TMRA4TRIG */ + CTIMER_AUX4_TMRA4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX4_TMRA4TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When + CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER + interrupt */ + CTIMER_AUX4_TMRA4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX4_TMRA4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX4_TMRA4TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX4_TMRA4TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX4_TMRA4TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX4_TMRA4TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX4_TMRA4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ + CTIMER_AUX4_TMRA4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX4_TMRA4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX4_TMRA4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ + CTIMER_AUX4_TMRA4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ +} CTIMER_AUX4_TMRA4TRIG_Enum; + +/* ========================================================= TMR5 ========================================================== */ +/* ======================================================== CMPRA5 ========================================================= */ +/* ======================================================== CMPRB5 ========================================================= */ +/* ========================================================= CTRL5 ========================================================= */ +/* ============================================= CTIMER CTRL5 CTLINK5 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_CTLINK5 */ + CTIMER_CTRL5_CTLINK5_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A5/B5 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL5_CTLINK5_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A5/B5 timers into a single 32-bit timer. */ +} CTIMER_CTRL5_CTLINK5_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5POL */ + CTIMER_CTRL5_TMRB5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB5 pin is the same as the + timer output. */ + CTIMER_CTRL5_TMRB5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB5 pin is the inverse of + the timer output. */ +} CTIMER_CTRL5_TMRB5POL_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5CLR */ + CTIMER_CTRL5_TMRB5CLR_RUN = 0, /*!< RUN : Allow counter/timer B5 to run */ + CTIMER_CTRL5_TMRB5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B5 at 0x0000. */ +} CTIMER_CTRL5_TMRB5CLR_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5IE1 */ + CTIMER_CTRL5_TMRB5IE1_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL5_TMRB5IE1_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL5_TMRB5IE1_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5IE0 */ + CTIMER_CTRL5_TMRB5IE0_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL5_TMRB5IE0_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL5_TMRB5IE0_Enum; + +/* ============================================= CTIMER CTRL5 TMRB5FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5FN */ + CTIMER_CTRL5_TMRB5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B5, stop. */ + CTIMER_CTRL5_TMRB5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B5, restart. */ + CTIMER_CTRL5_TMRB5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B5, assert, + count to CMPR1B5, deassert, stop. */ + CTIMER_CTRL5_TMRB5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B5, assert, count + to CMPR1B5, deassert, restart. */ + CTIMER_CTRL5_TMRB5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL5_TMRB5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL5_TMRB5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL5_TMRB5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL5_TMRB5FN_Enum; + +/* ============================================ CTIMER CTRL5 TMRB5CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5CLK */ + CTIMER_CTRL5_TMRB5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL5_TMRB5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL5_TMRB5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL5_TMRB5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL5_TMRB5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL5_TMRB5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL5_TMRB5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL5_TMRB5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL5_TMRB5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL5_TMRB5CLK_CTMRA5 = 20, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL5_TMRB5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL5_TMRB5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL5_TMRB5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL5_TMRB5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL5_TMRB5CLK_Enum; + +/* ============================================= CTIMER CTRL5 TMRB5EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRB5EN */ + CTIMER_CTRL5_TMRB5EN_DIS = 0, /*!< DIS : Counter/Timer B5 Disable. */ + CTIMER_CTRL5_TMRB5EN_EN = 1, /*!< EN : Counter/Timer B5 Enable. */ +} CTIMER_CTRL5_TMRB5EN_Enum; + +/* ============================================ CTIMER CTRL5 TMRA5POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5POL */ + CTIMER_CTRL5_TMRA5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA5 pin is the same as the + timer output. */ + CTIMER_CTRL5_TMRA5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA5 pin is the inverse of + the timer output. */ +} CTIMER_CTRL5_TMRA5POL_Enum; + +/* ============================================ CTIMER CTRL5 TMRA5CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5CLR */ + CTIMER_CTRL5_TMRA5CLR_RUN = 0, /*!< RUN : Allow counter/timer A5 to run */ + CTIMER_CTRL5_TMRA5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A5 at 0x0000. */ +} CTIMER_CTRL5_TMRA5CLR_Enum; + +/* ============================================ CTIMER CTRL5 TMRA5IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5IE1 */ + CTIMER_CTRL5_TMRA5IE1_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL5_TMRA5IE1_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL5_TMRA5IE1_Enum; + +/* ============================================= CTIMER CTRL5 TMRA5IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5IE0 */ + CTIMER_CTRL5_TMRA5IE0_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL5_TMRA5IE0_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL5_TMRA5IE0_Enum; + +/* ============================================== CTIMER CTRL5 TMRA5FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5FN */ + CTIMER_CTRL5_TMRA5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A5, stop. */ + CTIMER_CTRL5_TMRA5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A5, restart. */ + CTIMER_CTRL5_TMRA5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A5, assert, + count to CMPR1A5, deassert, stop. */ + CTIMER_CTRL5_TMRA5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A5, assert, count + to CMPR1A5, deassert, restart. */ + CTIMER_CTRL5_TMRA5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL5_TMRA5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL5_TMRA5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL5_TMRA5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL5_TMRA5FN_Enum; + +/* ============================================= CTIMER CTRL5 TMRA5CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5CLK */ + CTIMER_CTRL5_TMRA5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL5_TMRA5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL5_TMRA5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL5_TMRA5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL5_TMRA5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL5_TMRA5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL5_TMRA5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL5_TMRA5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL5_TMRA5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL5_TMRA5CLK_CTMRB5 = 20, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL5_TMRA5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL5_TMRA5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL5_TMRA5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL5_TMRA5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL5_TMRA5CLK_Enum; + +/* ============================================== CTIMER CTRL5 TMRA5EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL5_TMRA5EN */ + CTIMER_CTRL5_TMRA5EN_DIS = 0, /*!< DIS : Counter/Timer A5 Disable. */ + CTIMER_CTRL5_TMRA5EN_EN = 1, /*!< EN : Counter/Timer A5 Enable. */ +} CTIMER_CTRL5_TMRA5EN_Enum; + +/* ======================================================= CMPRAUXA5 ======================================================= */ +/* ======================================================= CMPRAUXB5 ======================================================= */ +/* ========================================================= AUX5 ========================================================== */ +/* ============================================ CTIMER AUX5 TMRB5EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRB5EN23 */ + CTIMER_AUX5_TMRB5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX5_TMRB5EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX5_TMRB5EN23_Enum; + +/* ============================================ CTIMER AUX5 TMRB5POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRB5POL23 */ + CTIMER_AUX5_TMRB5POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX5_TMRB5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX5_TMRB5POL23_Enum; + +/* ============================================ CTIMER AUX5 TMRB5TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRB5TINV */ + CTIMER_AUX5_TMRB5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX5_TMRB5TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX5_TMRB5TINV_Enum; + +/* =========================================== CTIMER AUX5 TMRB5NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRB5NOSYNC */ + CTIMER_AUX5_TMRB5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX5_TMRB5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX5_TMRB5NOSYNC_Enum; + +/* ============================================ CTIMER AUX5 TMRB5TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRB5TRIG */ + CTIMER_AUX5_TMRB5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX5_TMRB5TRIG_A5OUT = 1, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX5_TMRB5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX5_TMRB5TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX5_TMRB5TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX5_TMRB5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */ + CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX5_TMRB5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX5_TMRB5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX5_TMRB5TRIG_Enum; + +/* ============================================ CTIMER AUX5 TMRA5EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRA5EN23 */ + CTIMER_AUX5_TMRA5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX5_TMRA5EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX5_TMRA5EN23_Enum; + +/* ============================================ CTIMER AUX5 TMRA5POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRA5POL23 */ + CTIMER_AUX5_TMRA5POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */ + CTIMER_AUX5_TMRA5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX5_TMRA5POL23_Enum; + +/* ============================================ CTIMER AUX5 TMRA5TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRA5TINV */ + CTIMER_AUX5_TMRA5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX5_TMRA5TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX5_TMRA5TINV_Enum; + +/* =========================================== CTIMER AUX5 TMRA5NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX5_TMRA5NOSYNC */ + CTIMER_AUX5_TMRA5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX5_TMRA5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX5_TMRA5NOSYNC_Enum; + +/* ============================================= CTIMER AUX5 TMRA5TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX5_TMRA5TRIG */ + CTIMER_AUX5_TMRA5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX5_TMRA5TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When + CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER + interrupt */ + CTIMER_AUX5_TMRA5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX5_TMRA5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX5_TMRA5TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX5_TMRA5TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX5_TMRA5TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX5_TMRA5TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX5_TMRA5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */ + CTIMER_AUX5_TMRA5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX5_TMRA5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX5_TMRA5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX5_TMRA5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX5_TMRA5TRIG_Enum; + +/* ========================================================= TMR6 ========================================================== */ +/* ======================================================== CMPRA6 ========================================================= */ +/* ======================================================== CMPRB6 ========================================================= */ +/* ========================================================= CTRL6 ========================================================= */ +/* ============================================= CTIMER CTRL6 CTLINK6 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_CTLINK6 */ + CTIMER_CTRL6_CTLINK6_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A6/B6 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL6_CTLINK6_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A6/B6 timers into a single 32-bit timer. */ +} CTIMER_CTRL6_CTLINK6_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6POL */ + CTIMER_CTRL6_TMRB6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB6 pin is the same as the + timer output. */ + CTIMER_CTRL6_TMRB6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB6 pin is the inverse of + the timer output. */ +} CTIMER_CTRL6_TMRB6POL_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6CLR */ + CTIMER_CTRL6_TMRB6CLR_RUN = 0, /*!< RUN : Allow counter/timer B6 to run */ + CTIMER_CTRL6_TMRB6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B6 at 0x0000. */ +} CTIMER_CTRL6_TMRB6CLR_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6IE1 */ + CTIMER_CTRL6_TMRB6IE1_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL6_TMRB6IE1_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL6_TMRB6IE1_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6IE0 */ + CTIMER_CTRL6_TMRB6IE0_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL6_TMRB6IE0_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL6_TMRB6IE0_Enum; + +/* ============================================= CTIMER CTRL6 TMRB6FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6FN */ + CTIMER_CTRL6_TMRB6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B6, stop. */ + CTIMER_CTRL6_TMRB6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B6, restart. */ + CTIMER_CTRL6_TMRB6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B6, assert, + count to CMPR1B6, deassert, stop. */ + CTIMER_CTRL6_TMRB6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B6, assert, count + to CMPR1B6, deassert, restart. */ + CTIMER_CTRL6_TMRB6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL6_TMRB6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL6_TMRB6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL6_TMRB6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL6_TMRB6FN_Enum; + +/* ============================================ CTIMER CTRL6 TMRB6CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6CLK */ + CTIMER_CTRL6_TMRB6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL6_TMRB6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL6_TMRB6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL6_TMRB6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL6_TMRB6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL6_TMRB6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL6_TMRB6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL6_TMRB6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL6_TMRB6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL6_TMRB6CLK_CTMRA6 = 20, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL6_TMRB6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL6_TMRB6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL6_TMRB6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL6_TMRB6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL6_TMRB6CLK_Enum; + +/* ============================================= CTIMER CTRL6 TMRB6EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRB6EN */ + CTIMER_CTRL6_TMRB6EN_DIS = 0, /*!< DIS : Counter/Timer B6 Disable. */ + CTIMER_CTRL6_TMRB6EN_EN = 1, /*!< EN : Counter/Timer B6 Enable. */ +} CTIMER_CTRL6_TMRB6EN_Enum; + +/* ============================================ CTIMER CTRL6 TMRA6POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6POL */ + CTIMER_CTRL6_TMRA6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA6 pin is the same as the + timer output. */ + CTIMER_CTRL6_TMRA6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA6 pin is the inverse of + the timer output. */ +} CTIMER_CTRL6_TMRA6POL_Enum; + +/* ============================================ CTIMER CTRL6 TMRA6CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6CLR */ + CTIMER_CTRL6_TMRA6CLR_RUN = 0, /*!< RUN : Allow counter/timer A6 to run */ + CTIMER_CTRL6_TMRA6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A6 at 0x0000. */ +} CTIMER_CTRL6_TMRA6CLR_Enum; + +/* ============================================ CTIMER CTRL6 TMRA6IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6IE1 */ + CTIMER_CTRL6_TMRA6IE1_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL6_TMRA6IE1_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL6_TMRA6IE1_Enum; + +/* ============================================= CTIMER CTRL6 TMRA6IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6IE0 */ + CTIMER_CTRL6_TMRA6IE0_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL6_TMRA6IE0_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL6_TMRA6IE0_Enum; + +/* ============================================== CTIMER CTRL6 TMRA6FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6FN */ + CTIMER_CTRL6_TMRA6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A6, stop. */ + CTIMER_CTRL6_TMRA6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A6, restart. */ + CTIMER_CTRL6_TMRA6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A6, assert, + count to CMPR1A6, deassert, stop. */ + CTIMER_CTRL6_TMRA6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A6, assert, count + to CMPR1A6, deassert, restart. */ + CTIMER_CTRL6_TMRA6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL6_TMRA6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL6_TMRA6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL6_TMRA6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL6_TMRA6FN_Enum; + +/* ============================================= CTIMER CTRL6 TMRA6CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6CLK */ + CTIMER_CTRL6_TMRA6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL6_TMRA6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL6_TMRA6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL6_TMRA6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL6_TMRA6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL6_TMRA6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL6_TMRA6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL6_TMRA6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL6_TMRA6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL6_TMRA6CLK_CTMRB6 = 20, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL6_TMRA6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL6_TMRA6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL6_TMRA6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL6_TMRA6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL6_TMRA6CLK_Enum; + +/* ============================================== CTIMER CTRL6 TMRA6EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL6_TMRA6EN */ + CTIMER_CTRL6_TMRA6EN_DIS = 0, /*!< DIS : Counter/Timer A6 Disable. */ + CTIMER_CTRL6_TMRA6EN_EN = 1, /*!< EN : Counter/Timer A6 Enable. */ +} CTIMER_CTRL6_TMRA6EN_Enum; + +/* ======================================================= CMPRAUXA6 ======================================================= */ +/* ======================================================= CMPRAUXB6 ======================================================= */ +/* ========================================================= AUX6 ========================================================== */ +/* ============================================ CTIMER AUX6 TMRB6EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRB6EN23 */ + CTIMER_AUX6_TMRB6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX6_TMRB6EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX6_TMRB6EN23_Enum; + +/* ============================================ CTIMER AUX6 TMRB6POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRB6POL23 */ + CTIMER_AUX6_TMRB6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX6_TMRB6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX6_TMRB6POL23_Enum; + +/* ============================================ CTIMER AUX6 TMRB6TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRB6TINV */ + CTIMER_AUX6_TMRB6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX6_TMRB6TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX6_TMRB6TINV_Enum; + +/* =========================================== CTIMER AUX6 TMRB6NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRB6NOSYNC */ + CTIMER_AUX6_TMRB6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX6_TMRB6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX6_TMRB6NOSYNC_Enum; + +/* ============================================ CTIMER AUX6 TMRB6TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRB6TRIG */ + CTIMER_AUX6_TMRB6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX6_TMRB6TRIG_A6OUT = 1, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX6_TMRB6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX6_TMRB6TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX6_TMRB6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX6_TMRB6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ + CTIMER_AUX6_TMRB6TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX6_TMRB6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX6_TMRB6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */ + CTIMER_AUX6_TMRB6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */ +} CTIMER_AUX6_TMRB6TRIG_Enum; + +/* ============================================ CTIMER AUX6 TMRA6EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRA6EN23 */ + CTIMER_AUX6_TMRA6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX6_TMRA6EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX6_TMRA6EN23_Enum; + +/* ============================================ CTIMER AUX6 TMRA6POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRA6POL23 */ + CTIMER_AUX6_TMRA6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX6_TMRA6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX6_TMRA6POL23_Enum; + +/* ============================================ CTIMER AUX6 TMRA6TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRA6TINV */ + CTIMER_AUX6_TMRA6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX6_TMRA6TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX6_TMRA6TINV_Enum; + +/* =========================================== CTIMER AUX6 TMRA6NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX6_TMRA6NOSYNC */ + CTIMER_AUX6_TMRA6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX6_TMRA6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX6_TMRA6NOSYNC_Enum; + +/* ============================================= CTIMER AUX6 TMRA6TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX6_TMRA6TRIG */ + CTIMER_AUX6_TMRA6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX6_TMRA6TRIG_B6OUT = 1, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX6_TMRA6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX6_TMRA6TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX6_TMRA6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX6_TMRA6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX6_TMRA6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX6_TMRA6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX6_TMRA6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERBb OUT2. */ + CTIMER_AUX6_TMRA6TRIG_A5OUT2DUAL = 12, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ + CTIMER_AUX6_TMRA6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX6_TMRA6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */ + CTIMER_AUX6_TMRA6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */ +} CTIMER_AUX6_TMRA6TRIG_Enum; + +/* ========================================================= TMR7 ========================================================== */ +/* ======================================================== CMPRA7 ========================================================= */ +/* ======================================================== CMPRB7 ========================================================= */ +/* ========================================================= CTRL7 ========================================================= */ +/* ============================================= CTIMER CTRL7 CTLINK7 [31..31] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_CTLINK7 */ + CTIMER_CTRL7_CTLINK7_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A7/B7 timers as two independent 16-bit + timers (default). */ + CTIMER_CTRL7_CTLINK7_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A7/B7 timers into a single 32-bit timer. */ +} CTIMER_CTRL7_CTLINK7_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7POL [28..28] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7POL */ + CTIMER_CTRL7_TMRB7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB7 pin is the same as the + timer output. */ + CTIMER_CTRL7_TMRB7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB7 pin is the inverse of + the timer output. */ +} CTIMER_CTRL7_TMRB7POL_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7CLR [27..27] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7CLR */ + CTIMER_CTRL7_TMRB7CLR_RUN = 0, /*!< RUN : Allow counter/timer B7 to run */ + CTIMER_CTRL7_TMRB7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B7 at 0x0000. */ +} CTIMER_CTRL7_TMRB7CLR_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7IE1 [26..26] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7IE1 */ + CTIMER_CTRL7_TMRB7IE1_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL7_TMRB7IE1_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL7_TMRB7IE1_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7IE0 [25..25] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7IE0 */ + CTIMER_CTRL7_TMRB7IE0_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL7_TMRB7IE0_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based + on COMPR0 */ +} CTIMER_CTRL7_TMRB7IE0_Enum; + +/* ============================================= CTIMER CTRL7 TMRB7FN [22..24] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7FN */ + CTIMER_CTRL7_TMRB7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0B7, stop. */ + CTIMER_CTRL7_TMRB7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0B7, restart. */ + CTIMER_CTRL7_TMRB7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B7, assert, + count to CMPR1B7, deassert, stop. */ + CTIMER_CTRL7_TMRB7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B7, assert, count + to CMPR1B7, deassert, restart. */ + CTIMER_CTRL7_TMRB7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL7_TMRB7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL7_TMRB7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL7_TMRB7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL7_TMRB7FN_Enum; + +/* ============================================ CTIMER CTRL7 TMRB7CLK [17..21] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7CLK */ + CTIMER_CTRL7_TMRB7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL7_TMRB7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL7_TMRB7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL7_TMRB7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL7_TMRB7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL7_TMRB7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL7_TMRB7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL7_TMRB7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL7_TMRB7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL7_TMRB7CLK_CTMRA7 = 20, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL7_TMRB7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL7_TMRB7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL7_TMRB7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL7_TMRB7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL7_TMRB7CLK_Enum; + +/* ============================================= CTIMER CTRL7 TMRB7EN [16..16] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRB7EN */ + CTIMER_CTRL7_TMRB7EN_DIS = 0, /*!< DIS : Counter/Timer B7 Disable. */ + CTIMER_CTRL7_TMRB7EN_EN = 1, /*!< EN : Counter/Timer B7 Enable. */ +} CTIMER_CTRL7_TMRB7EN_Enum; + +/* ============================================ CTIMER CTRL7 TMRA7POL [12..12] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7POL */ + CTIMER_CTRL7_TMRA7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA7 pin is the same as the + timer output. */ + CTIMER_CTRL7_TMRA7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA7 pin is the inverse of + the timer output. */ +} CTIMER_CTRL7_TMRA7POL_Enum; + +/* ============================================ CTIMER CTRL7 TMRA7CLR [11..11] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7CLR */ + CTIMER_CTRL7_TMRA7CLR_RUN = 0, /*!< RUN : Allow counter/timer A7 to run */ + CTIMER_CTRL7_TMRA7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A7 at 0x0000. */ +} CTIMER_CTRL7_TMRA7CLR_Enum; + +/* ============================================ CTIMER CTRL7 TMRA7IE1 [10..10] ============================================= */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7IE1 */ + CTIMER_CTRL7_TMRA7IE1_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt + based on COMPR1. */ + CTIMER_CTRL7_TMRA7IE1_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based + on COMPR1. */ +} CTIMER_CTRL7_TMRA7IE1_Enum; + +/* ============================================= CTIMER CTRL7 TMRA7IE0 [9..9] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7IE0 */ + CTIMER_CTRL7_TMRA7IE0_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt + based on COMPR0. */ + CTIMER_CTRL7_TMRA7IE0_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based + on COMPR0. */ +} CTIMER_CTRL7_TMRA7IE0_Enum; + +/* ============================================== CTIMER CTRL7 TMRA7FN [6..8] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7FN */ + CTIMER_CTRL7_TMRA7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count + to CMPR0A7, stop. */ + CTIMER_CTRL7_TMRA7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide + pulses). Count to CMPR0A7, restart. */ + CTIMER_CTRL7_TMRA7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A7, assert, + count to CMPR1A7, deassert, stop. */ + CTIMER_CTRL7_TMRA7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A7, assert, count + to CMPR1A7, deassert, restart. */ + CTIMER_CTRL7_TMRA7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ + CTIMER_CTRL7_TMRA7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ + CTIMER_CTRL7_TMRA7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ + CTIMER_CTRL7_TMRA7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ +} CTIMER_CTRL7_TMRA7FN_Enum; + +/* ============================================= CTIMER CTRL7 TMRA7CLK [1..5] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7CLK */ + CTIMER_CTRL7_TMRA7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ + CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ + CTIMER_CTRL7_TMRA7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ + CTIMER_CTRL7_TMRA7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ + CTIMER_CTRL7_TMRA7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ + CTIMER_CTRL7_TMRA7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ + CTIMER_CTRL7_TMRA7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ + CTIMER_CTRL7_TMRA7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ + CTIMER_CTRL7_TMRA7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only + available when MCU is in active mode) */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ + CTIMER_CTRL7_TMRA7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ + CTIMER_CTRL7_TMRA7CLK_CTMRB7 = 20, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ + CTIMER_CTRL7_TMRA7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ + CTIMER_CTRL7_TMRA7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ + CTIMER_CTRL7_TMRA7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ + CTIMER_CTRL7_TMRA7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ +} CTIMER_CTRL7_TMRA7CLK_Enum; + +/* ============================================== CTIMER CTRL7 TMRA7EN [0..0] ============================================== */ +typedef enum { /*!< CTIMER_CTRL7_TMRA7EN */ + CTIMER_CTRL7_TMRA7EN_DIS = 0, /*!< DIS : Counter/Timer A7 Disable. */ + CTIMER_CTRL7_TMRA7EN_EN = 1, /*!< EN : Counter/Timer A7 Enable. */ +} CTIMER_CTRL7_TMRA7EN_Enum; + +/* ======================================================= CMPRAUXA7 ======================================================= */ +/* ======================================================= CMPRAUXB7 ======================================================= */ +/* ========================================================= AUX7 ========================================================== */ +/* ============================================ CTIMER AUX7 TMRB7EN23 [30..30] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRB7EN23 */ + CTIMER_AUX7_TMRB7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX7_TMRB7EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX7_TMRB7EN23_Enum; + +/* ============================================ CTIMER AUX7 TMRB7POL23 [29..29] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRB7POL23 */ + CTIMER_AUX7_TMRB7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX7_TMRB7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX7_TMRB7POL23_Enum; + +/* ============================================ CTIMER AUX7 TMRB7TINV [28..28] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRB7TINV */ + CTIMER_AUX7_TMRB7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX7_TMRB7TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX7_TMRB7TINV_Enum; + +/* =========================================== CTIMER AUX7 TMRB7NOSYNC [27..27] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRB7NOSYNC */ + CTIMER_AUX7_TMRB7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX7_TMRB7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX7_TMRB7NOSYNC_Enum; + +/* ============================================ CTIMER AUX7 TMRB7TRIG [23..26] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRB7TRIG */ + CTIMER_AUX7_TMRB7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX7_TMRB7TRIG_A7OUT = 1, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX7_TMRB7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX7_TMRB7TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ + CTIMER_AUX7_TMRB7TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ + CTIMER_AUX7_TMRB7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ + CTIMER_AUX7_TMRB7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX7_TMRB7TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ + CTIMER_AUX7_TMRB7TRIG_B1OUT2DUAL = 14, /*!< B1OUT2DUAL : Trigger source is CTIMERB1 OUT2, dual edge. */ + CTIMER_AUX7_TMRB7TRIG_A1OUT2DUAL = 15, /*!< A1OUT2DUAL : Trigger source is CTIMERA1 OUT2, dual edge. */ +} CTIMER_AUX7_TMRB7TRIG_Enum; + +/* ============================================ CTIMER AUX7 TMRA7EN23 [14..14] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRA7EN23 */ + CTIMER_AUX7_TMRA7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ + CTIMER_AUX7_TMRA7EN23_EN = 0, /*!< EN : Enable enhanced functions. */ +} CTIMER_AUX7_TMRA7EN23_Enum; + +/* ============================================ CTIMER AUX7 TMRA7POL23 [13..13] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRA7POL23 */ + CTIMER_AUX7_TMRA7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ + CTIMER_AUX7_TMRA7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ +} CTIMER_AUX7_TMRA7POL23_Enum; + +/* ============================================ CTIMER AUX7 TMRA7TINV [12..12] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRA7TINV */ + CTIMER_AUX7_TMRA7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ + CTIMER_AUX7_TMRA7TINV_EN = 1, /*!< EN : Enable invert on trigger */ +} CTIMER_AUX7_TMRA7TINV_Enum; + +/* =========================================== CTIMER AUX7 TMRA7NOSYNC [11..11] ============================================ */ +typedef enum { /*!< CTIMER_AUX7_TMRA7NOSYNC */ + CTIMER_AUX7_TMRA7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ + CTIMER_AUX7_TMRA7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ +} CTIMER_AUX7_TMRA7NOSYNC_Enum; + +/* ============================================= CTIMER AUX7 TMRA7TRIG [7..10] ============================================= */ +typedef enum { /*!< CTIMER_AUX7_TMRA7TRIG */ + CTIMER_AUX7_TMRA7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ + CTIMER_AUX7_TMRA7TRIG_B7OUT = 1, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ + CTIMER_AUX7_TMRA7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ + CTIMER_AUX7_TMRA7TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ + CTIMER_AUX7_TMRA7TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ + CTIMER_AUX7_TMRA7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ + CTIMER_AUX7_TMRA7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ + CTIMER_AUX7_TMRA7TRIG_A5OUT2DUAL = 13, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ + CTIMER_AUX7_TMRA7TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ + CTIMER_AUX7_TMRA7TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ +} CTIMER_AUX7_TMRA7TRIG_Enum; + +/* ======================================================== GLOBEN ========================================================= */ +/* ============================================== CTIMER GLOBEN ENB7 [15..15] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB7 */ + CTIMER_GLOBEN_ENB7_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB7_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB7_Enum; + +/* ============================================== CTIMER GLOBEN ENA7 [14..14] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA7 */ + CTIMER_GLOBEN_ENA7_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA7_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA7_Enum; + +/* ============================================== CTIMER GLOBEN ENB6 [13..13] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB6 */ + CTIMER_GLOBEN_ENB6_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB6_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB6_Enum; + +/* ============================================== CTIMER GLOBEN ENA6 [12..12] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA6 */ + CTIMER_GLOBEN_ENA6_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA6_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA6_Enum; + +/* ============================================== CTIMER GLOBEN ENB5 [11..11] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB5 */ + CTIMER_GLOBEN_ENB5_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB5_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB5_Enum; + +/* ============================================== CTIMER GLOBEN ENA5 [10..10] ============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA5 */ + CTIMER_GLOBEN_ENA5_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA5_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA5_Enum; + +/* =============================================== CTIMER GLOBEN ENB4 [9..9] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB4 */ + CTIMER_GLOBEN_ENB4_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB4_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB4_Enum; + +/* =============================================== CTIMER GLOBEN ENA4 [8..8] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA4 */ + CTIMER_GLOBEN_ENA4_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA4_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA4_Enum; + +/* =============================================== CTIMER GLOBEN ENB3 [7..7] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB3 */ + CTIMER_GLOBEN_ENB3_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB3_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB3_Enum; + +/* =============================================== CTIMER GLOBEN ENA3 [6..6] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA3 */ + CTIMER_GLOBEN_ENA3_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA3_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA3_Enum; + +/* =============================================== CTIMER GLOBEN ENB2 [5..5] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB2 */ + CTIMER_GLOBEN_ENB2_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB2_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB2_Enum; + +/* =============================================== CTIMER GLOBEN ENA2 [4..4] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA2 */ + CTIMER_GLOBEN_ENA2_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA2_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA2_Enum; + +/* =============================================== CTIMER GLOBEN ENB1 [3..3] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB1 */ + CTIMER_GLOBEN_ENB1_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB1_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB1_Enum; + +/* =============================================== CTIMER GLOBEN ENA1 [2..2] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA1 */ + CTIMER_GLOBEN_ENA1_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA1_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA1_Enum; + +/* =============================================== CTIMER GLOBEN ENB0 [1..1] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENB0 */ + CTIMER_GLOBEN_ENB0_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENB0_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENB0_Enum; + +/* =============================================== CTIMER GLOBEN ENA0 [0..0] =============================================== */ +typedef enum { /*!< CTIMER_GLOBEN_ENA0 */ + CTIMER_GLOBEN_ENA0_LCO = 1, /*!< LCO : Use local enable. */ + CTIMER_GLOBEN_ENA0_DIS = 0, /*!< DIS : Disable CTIMER. */ +} CTIMER_GLOBEN_ENA0_Enum; + +/* ======================================================== OUTCFG0 ======================================================== */ +/* ============================================= CTIMER OUTCFG0 CFG9 [28..30] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG9 */ + CTIMER_OUTCFG0_CFG9_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG9_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG9_B0OUT = 5, /*!< B0OUT : Output is B0OUT. */ + CTIMER_OUTCFG0_CFG9_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */ + CTIMER_OUTCFG0_CFG9_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ + CTIMER_OUTCFG0_CFG9_A2OUT2 = 2, /*!< A2OUT2 : Output is A2OUT2 */ + CTIMER_OUTCFG0_CFG9_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG9_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG9_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG8 [25..27] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG8 */ + CTIMER_OUTCFG0_CFG8_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG8_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG8_B6OUT = 5, /*!< B6OUT : Output is B6OUT. */ + CTIMER_OUTCFG0_CFG8_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */ + CTIMER_OUTCFG0_CFG8_A3OUT2 = 3, /*!< A3OUT2 : Output is A3OUT. */ + CTIMER_OUTCFG0_CFG8_A2OUT = 2, /*!< A2OUT : Output is A2OUT */ + CTIMER_OUTCFG0_CFG8_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG8_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG8_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG7 [22..24] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG7 */ + CTIMER_OUTCFG0_CFG7_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG7_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG7_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG0_CFG7_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */ + CTIMER_OUTCFG0_CFG7_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ + CTIMER_OUTCFG0_CFG7_B1OUT2 = 2, /*!< B1OUT2 : Output is B1OUT2 */ + CTIMER_OUTCFG0_CFG7_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG7_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG7_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG6 [19..21] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG6 */ + CTIMER_OUTCFG0_CFG6_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG6_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG6_B7OUT = 5, /*!< B7OUT : Output is B7OUT. */ + CTIMER_OUTCFG0_CFG6_B5OUT2 = 4, /*!< B5OUT2 : Output is B5OUT2. */ + CTIMER_OUTCFG0_CFG6_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG0_CFG6_B1OUT = 2, /*!< B1OUT : Output is B1OUT */ + CTIMER_OUTCFG0_CFG6_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG6_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG6_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG5 [16..18] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG5 */ + CTIMER_OUTCFG0_CFG5_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG5_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG5_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG0_CFG5_B6OUT = 4, /*!< B6OUT : Output is A5OUT. */ + CTIMER_OUTCFG0_CFG5_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG0_CFG5_A1OUT2 = 2, /*!< A1OUT2 : Output is A1OUT2 */ + CTIMER_OUTCFG0_CFG5_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG5_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG5_Enum; + +/* ============================================= CTIMER OUTCFG0 CFG4 [12..14] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG4 */ + CTIMER_OUTCFG0_CFG4_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG4_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG4_B5OUT = 5, /*!< B5OUT : Output is B5OUT. */ + CTIMER_OUTCFG0_CFG4_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ + CTIMER_OUTCFG0_CFG4_A2OUT2 = 3, /*!< A2OUT2 : Output is A2OUT2. */ + CTIMER_OUTCFG0_CFG4_A1OUT = 2, /*!< A1OUT : Output is A1OUT */ + CTIMER_OUTCFG0_CFG4_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG4_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG4_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG3 [9..11] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG3 */ + CTIMER_OUTCFG0_CFG3_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG3_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG3_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG0_CFG3_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG0_CFG3_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */ + CTIMER_OUTCFG0_CFG3_B0OUT2 = 2, /*!< B0OUT2 : Output is B0OUT2 */ + CTIMER_OUTCFG0_CFG3_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG3_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG3_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG2 [6..8] =============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG2 */ + CTIMER_OUTCFG0_CFG2_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG2_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG2_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG0_CFG2_B6OUT2 = 4, /*!< B6OUT2 : Output is B6OUT2. */ + CTIMER_OUTCFG0_CFG2_B1OUT2 = 3, /*!< B1OUT2 : Output is B1OUT2. */ + CTIMER_OUTCFG0_CFG2_B0OUT = 2, /*!< B0OUT : Output is B0OUT */ + CTIMER_OUTCFG0_CFG2_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG2_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG2_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG1 [3..5] =============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG1 */ + CTIMER_OUTCFG0_CFG1_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG1_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG1_B7OUT2 = 5, /*!< B7OUT2 : Output is B7OUT2. */ + CTIMER_OUTCFG0_CFG1_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ + CTIMER_OUTCFG0_CFG1_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */ + CTIMER_OUTCFG0_CFG1_A0OUT2 = 2, /*!< A0OUT2 : Output is A0OUT2 */ + CTIMER_OUTCFG0_CFG1_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG1_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG1_Enum; + +/* ============================================== CTIMER OUTCFG0 CFG0 [0..2] =============================================== */ +typedef enum { /*!< CTIMER_OUTCFG0_CFG0 */ + CTIMER_OUTCFG0_CFG0_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG0_CFG0_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG0_CFG0_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG0_CFG0_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ + CTIMER_OUTCFG0_CFG0_B2OUT2 = 3, /*!< B2OUT2 : Output is B2OUT2. */ + CTIMER_OUTCFG0_CFG0_A0OUT = 2, /*!< A0OUT : Output is A0OUT */ + CTIMER_OUTCFG0_CFG0_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG0_CFG0_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG0_CFG0_Enum; + +/* ======================================================== OUTCFG1 ======================================================== */ +/* ============================================= CTIMER OUTCFG1 CFG19 [28..30] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG19 */ + CTIMER_OUTCFG1_CFG19_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG19_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG19_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */ + CTIMER_OUTCFG1_CFG19_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */ + CTIMER_OUTCFG1_CFG19_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ + CTIMER_OUTCFG1_CFG19_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */ + CTIMER_OUTCFG1_CFG19_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG19_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG19_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG18 [25..27] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG18 */ + CTIMER_OUTCFG1_CFG18_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG18_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG18_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */ + CTIMER_OUTCFG1_CFG18_A0OUT = 4, /*!< A0OUT : Output is A0OUT. */ + CTIMER_OUTCFG1_CFG18_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */ + CTIMER_OUTCFG1_CFG18_B4OUT = 2, /*!< B4OUT : Output is B4OUT */ + CTIMER_OUTCFG1_CFG18_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG18_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG18_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG17 [22..24] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG17 */ + CTIMER_OUTCFG1_CFG17_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG17_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG17_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */ + CTIMER_OUTCFG1_CFG17_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */ + CTIMER_OUTCFG1_CFG17_B7OUT = 3, /*!< B7OUT : Output is B7OUT. */ + CTIMER_OUTCFG1_CFG17_A4OUT2 = 2, /*!< A4OUT2 : Output is A4OUT2 */ + CTIMER_OUTCFG1_CFG17_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG17_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG17_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG16 [19..21] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG16 */ + CTIMER_OUTCFG1_CFG16_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG16_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG16_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */ + CTIMER_OUTCFG1_CFG16_A0OUT2 = 4, /*!< A0OUT2 : Output is A0OUT2. */ + CTIMER_OUTCFG1_CFG16_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */ + CTIMER_OUTCFG1_CFG16_A4OUT = 2, /*!< A4OUT : Output is A4OUT */ + CTIMER_OUTCFG1_CFG16_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG16_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG16_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG15 [16..18] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG15 */ + CTIMER_OUTCFG1_CFG15_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG15_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG15_A4OUT2 = 5, /*!< A4OUT2 : Output is A4OUT2. */ + CTIMER_OUTCFG1_CFG15_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG1_CFG15_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */ + CTIMER_OUTCFG1_CFG15_B3OUT2 = 2, /*!< B3OUT2 : Output is B3OUT2 */ + CTIMER_OUTCFG1_CFG15_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG15_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG15_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG14 [12..14] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG14 */ + CTIMER_OUTCFG1_CFG14_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG14_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG14_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG1_CFG14_B7OUT2 = 4, /*!< B7OUT2 : Output is B7OUT2. */ + CTIMER_OUTCFG1_CFG14_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ + CTIMER_OUTCFG1_CFG14_B3OUT = 2, /*!< B3OUT : Output is B3OUT */ + CTIMER_OUTCFG1_CFG14_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG14_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG14_Enum; + +/* ============================================= CTIMER OUTCFG1 CFG13 [9..11] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG13 */ + CTIMER_OUTCFG1_CFG13_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG13_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG13_B4OUT2 = 5, /*!< B4OUT2 : Output is B4OUT2. */ + CTIMER_OUTCFG1_CFG13_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG1_CFG13_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */ + CTIMER_OUTCFG1_CFG13_A3OUT2 = 2, /*!< A3OUT2 : Output is A3OUT2 */ + CTIMER_OUTCFG1_CFG13_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG13_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG13_Enum; + +/* ============================================== CTIMER OUTCFG1 CFG12 [6..8] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG12 */ + CTIMER_OUTCFG1_CFG12_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG12_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG12_B6OUT2 = 5, /*!< B6OUT2 : Output is B6OUT2. */ + CTIMER_OUTCFG1_CFG12_B0OUT2 = 4, /*!< B0OUT2 : Output is B0OUT2. */ + CTIMER_OUTCFG1_CFG12_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ + CTIMER_OUTCFG1_CFG12_A3OUT = 2, /*!< A3OUT : Output is A3OUT */ + CTIMER_OUTCFG1_CFG12_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG12_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG12_Enum; + +/* ============================================== CTIMER OUTCFG1 CFG11 [3..5] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG11 */ + CTIMER_OUTCFG1_CFG11_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG11_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG11_B5OUT2 = 5, /*!< B5OUT2 : Output is B5OUT2. */ + CTIMER_OUTCFG1_CFG11_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */ + CTIMER_OUTCFG1_CFG11_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ + CTIMER_OUTCFG1_CFG11_B2OUT2 = 2, /*!< B2OUT2 : Output is B2OUT2 */ + CTIMER_OUTCFG1_CFG11_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG11_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG11_Enum; + +/* ============================================== CTIMER OUTCFG1 CFG10 [0..2] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG1_CFG10 */ + CTIMER_OUTCFG1_CFG10_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG1_CFG10_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG1_CFG10_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG1_CFG10_B4OUT2 = 4, /*!< B4OUT2 : Output is B4OUT2. */ + CTIMER_OUTCFG1_CFG10_B3OUT2 = 3, /*!< B3OUT2 : Output is B3OUT2. */ + CTIMER_OUTCFG1_CFG10_B2OUT = 2, /*!< B2OUT : Output is B2OUT */ + CTIMER_OUTCFG1_CFG10_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG1_CFG10_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG1_CFG10_Enum; + +/* ======================================================== OUTCFG2 ======================================================== */ +/* ============================================= CTIMER OUTCFG2 CFG29 [28..30] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG29 */ + CTIMER_OUTCFG2_CFG29_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG29_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG29_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */ + CTIMER_OUTCFG2_CFG29_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG2_CFG29_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG29_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */ + CTIMER_OUTCFG2_CFG29_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG29_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG29_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG28 [25..27] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG28 */ + CTIMER_OUTCFG2_CFG28_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG28_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG28_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */ + CTIMER_OUTCFG2_CFG28_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ + CTIMER_OUTCFG2_CFG28_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */ + CTIMER_OUTCFG2_CFG28_A7OUT = 2, /*!< A7OUT : Output is A7OUT */ + CTIMER_OUTCFG2_CFG28_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG28_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG28_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG27 [22..24] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG27 */ + CTIMER_OUTCFG2_CFG27_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG27_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG27_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */ + CTIMER_OUTCFG2_CFG27_B6OUT = 4, /*!< B6OUT : Output is B6OUT. */ + CTIMER_OUTCFG2_CFG27_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG27_B6OUT2 = 2, /*!< B6OUT2 : Output is B6OUT2 */ + CTIMER_OUTCFG2_CFG27_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG27_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG27_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG26 [19..21] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG26 */ + CTIMER_OUTCFG2_CFG26_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG26_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG26_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */ + CTIMER_OUTCFG2_CFG26_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ + CTIMER_OUTCFG2_CFG26_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ + CTIMER_OUTCFG2_CFG26_B6OUT = 2, /*!< B6OUT : Output is B6OUT */ + CTIMER_OUTCFG2_CFG26_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG26_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG26_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG25 [16..18] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG25 */ + CTIMER_OUTCFG2_CFG25_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG25_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG25_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */ + CTIMER_OUTCFG2_CFG25_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG2_CFG25_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ + CTIMER_OUTCFG2_CFG25_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */ + CTIMER_OUTCFG2_CFG25_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG25_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG25_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG24 [12..14] ============================================= */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG24 */ + CTIMER_OUTCFG2_CFG24_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG24_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG24_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */ + CTIMER_OUTCFG2_CFG24_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG24_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ + CTIMER_OUTCFG2_CFG24_A6OUT = 2, /*!< A6OUT : Output is A6OUT */ + CTIMER_OUTCFG2_CFG24_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG24_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG24_Enum; + +/* ============================================= CTIMER OUTCFG2 CFG23 [9..11] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG23 */ + CTIMER_OUTCFG2_CFG23_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG23_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG23_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */ + CTIMER_OUTCFG2_CFG23_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ + CTIMER_OUTCFG2_CFG23_A7OUT = 3, /*!< A7OUT : Output is A7OUT. */ + CTIMER_OUTCFG2_CFG23_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */ + CTIMER_OUTCFG2_CFG23_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG23_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG23_Enum; + +/* ============================================== CTIMER OUTCFG2 CFG22 [6..8] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG22 */ + CTIMER_OUTCFG2_CFG22_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG22_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG22_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */ + CTIMER_OUTCFG2_CFG22_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG22_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG2_CFG22_B5OUT = 2, /*!< B5OUT : Output is B5OUT */ + CTIMER_OUTCFG2_CFG22_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG22_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG22_Enum; + +/* ============================================== CTIMER OUTCFG2 CFG21 [3..5] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG21 */ + CTIMER_OUTCFG2_CFG21_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG21_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG21_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */ + CTIMER_OUTCFG2_CFG21_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */ + CTIMER_OUTCFG2_CFG21_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG21_A5OUT2 = 2, /*!< A5OUT2 : Output is A5OUT2 */ + CTIMER_OUTCFG2_CFG21_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG21_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG21_Enum; + +/* ============================================== CTIMER OUTCFG2 CFG20 [0..2] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG2_CFG20 */ + CTIMER_OUTCFG2_CFG20_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG2_CFG20_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG2_CFG20_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */ + CTIMER_OUTCFG2_CFG20_A1OUT2 = 4, /*!< A1OUT2 : Output is A1OUT2. */ + CTIMER_OUTCFG2_CFG20_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ + CTIMER_OUTCFG2_CFG20_A5OUT = 2, /*!< A5OUT : Output is A5OUT */ + CTIMER_OUTCFG2_CFG20_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG2_CFG20_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG2_CFG20_Enum; + +/* ======================================================== OUTCFG3 ======================================================== */ +/* ============================================== CTIMER OUTCFG3 CFG31 [3..5] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG3_CFG31 */ + CTIMER_OUTCFG3_CFG31_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG3_CFG31_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG3_CFG31_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */ + CTIMER_OUTCFG3_CFG31_B7OUT = 4, /*!< B7OUT : Output is B7OUT. */ + CTIMER_OUTCFG3_CFG31_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */ + CTIMER_OUTCFG3_CFG31_B7OUT2 = 2, /*!< B7OUT2 : Output is B7OUT2 */ + CTIMER_OUTCFG3_CFG31_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG3_CFG31_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG3_CFG31_Enum; + +/* ============================================== CTIMER OUTCFG3 CFG30 [0..2] ============================================== */ +typedef enum { /*!< CTIMER_OUTCFG3_CFG30 */ + CTIMER_OUTCFG3_CFG30_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ + CTIMER_OUTCFG3_CFG30_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ + CTIMER_OUTCFG3_CFG30_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */ + CTIMER_OUTCFG3_CFG30_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */ + CTIMER_OUTCFG3_CFG30_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */ + CTIMER_OUTCFG3_CFG30_B7OUT = 2, /*!< B7OUT : Output is B7OUT */ + CTIMER_OUTCFG3_CFG30_ONE = 1, /*!< ONE : Force output to 1. */ + CTIMER_OUTCFG3_CFG30_ZERO = 0, /*!< ZERO : Force output to 0 */ +} CTIMER_OUTCFG3_CFG30_Enum; + +/* ========================================================= INCFG ========================================================= */ +/* ============================================== CTIMER INCFG CFGB7 [15..15] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB7 */ + CTIMER_INCFG_CFGB7_CT31 = 1, /*!< CT31 : Input is CT31 */ + CTIMER_INCFG_CFGB7_CT30 = 0, /*!< CT30 : Input is CT30 */ +} CTIMER_INCFG_CFGB7_Enum; + +/* ============================================== CTIMER INCFG CFGA7 [14..14] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA7 */ + CTIMER_INCFG_CFGA7_CT29 = 1, /*!< CT29 : Input is CT29 */ + CTIMER_INCFG_CFGA7_CT28 = 0, /*!< CT28 : Input is CT28 */ +} CTIMER_INCFG_CFGA7_Enum; + +/* ============================================== CTIMER INCFG CFGB6 [13..13] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB6 */ + CTIMER_INCFG_CFGB6_CT27 = 1, /*!< CT27 : Input is CT27 */ + CTIMER_INCFG_CFGB6_CT26 = 0, /*!< CT26 : Input is CT26 */ +} CTIMER_INCFG_CFGB6_Enum; + +/* ============================================== CTIMER INCFG CFGA6 [12..12] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA6 */ + CTIMER_INCFG_CFGA6_CT25 = 1, /*!< CT25 : Input is CT25 */ + CTIMER_INCFG_CFGA6_CT24 = 0, /*!< CT24 : Input is CT24 */ +} CTIMER_INCFG_CFGA6_Enum; + +/* ============================================== CTIMER INCFG CFGB5 [11..11] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB5 */ + CTIMER_INCFG_CFGB5_CT23 = 1, /*!< CT23 : Input is CT23 */ + CTIMER_INCFG_CFGB5_CT22 = 0, /*!< CT22 : Input is CT22 */ +} CTIMER_INCFG_CFGB5_Enum; + +/* ============================================== CTIMER INCFG CFGA5 [10..10] ============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA5 */ + CTIMER_INCFG_CFGA5_CT21 = 1, /*!< CT21 : Input is CT21 */ + CTIMER_INCFG_CFGA5_CT20 = 0, /*!< CT20 : Input is CT20 */ +} CTIMER_INCFG_CFGA5_Enum; + +/* =============================================== CTIMER INCFG CFGB4 [9..9] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB4 */ + CTIMER_INCFG_CFGB4_CT19 = 1, /*!< CT19 : Input is CT19 */ + CTIMER_INCFG_CFGB4_CT18 = 0, /*!< CT18 : Input is CT18 */ +} CTIMER_INCFG_CFGB4_Enum; + +/* =============================================== CTIMER INCFG CFGA4 [8..8] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA4 */ + CTIMER_INCFG_CFGA4_CT17 = 1, /*!< CT17 : Input is CT17 */ + CTIMER_INCFG_CFGA4_CT16 = 0, /*!< CT16 : Input is CT16 */ +} CTIMER_INCFG_CFGA4_Enum; + +/* =============================================== CTIMER INCFG CFGB3 [7..7] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB3 */ + CTIMER_INCFG_CFGB3_CT15 = 1, /*!< CT15 : Input is CT15 */ + CTIMER_INCFG_CFGB3_CT14 = 0, /*!< CT14 : Input is CT14 */ +} CTIMER_INCFG_CFGB3_Enum; + +/* =============================================== CTIMER INCFG CFGA3 [6..6] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA3 */ + CTIMER_INCFG_CFGA3_CT13 = 1, /*!< CT13 : Input is CT13 */ + CTIMER_INCFG_CFGA3_CT12 = 0, /*!< CT12 : Input is CT12 */ +} CTIMER_INCFG_CFGA3_Enum; + +/* =============================================== CTIMER INCFG CFGB2 [5..5] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB2 */ + CTIMER_INCFG_CFGB2_CT11 = 1, /*!< CT11 : Input is CT11 */ + CTIMER_INCFG_CFGB2_CT10 = 0, /*!< CT10 : Input is CT10 */ +} CTIMER_INCFG_CFGB2_Enum; + +/* =============================================== CTIMER INCFG CFGA2 [4..4] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA2 */ + CTIMER_INCFG_CFGA2_CT9 = 1, /*!< CT9 : Input is CT9 */ + CTIMER_INCFG_CFGA2_CT8 = 0, /*!< CT8 : Input is CT8 */ +} CTIMER_INCFG_CFGA2_Enum; + +/* =============================================== CTIMER INCFG CFGB1 [3..3] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB1 */ + CTIMER_INCFG_CFGB1_CT7 = 1, /*!< CT7 : Input is CT7 */ + CTIMER_INCFG_CFGB1_CT6 = 0, /*!< CT6 : Input is CT6 */ +} CTIMER_INCFG_CFGB1_Enum; + +/* =============================================== CTIMER INCFG CFGA1 [2..2] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA1 */ + CTIMER_INCFG_CFGA1_CT5 = 1, /*!< CT5 : Input is CT5 */ + CTIMER_INCFG_CFGA1_CT4 = 0, /*!< CT4 : Input is CT4 */ +} CTIMER_INCFG_CFGA1_Enum; + +/* =============================================== CTIMER INCFG CFGB0 [1..1] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGB0 */ + CTIMER_INCFG_CFGB0_CT3 = 1, /*!< CT3 : Input is CT3 */ + CTIMER_INCFG_CFGB0_CT2 = 0, /*!< CT2 : Input is CT2 */ +} CTIMER_INCFG_CFGB0_Enum; + +/* =============================================== CTIMER INCFG CFGA0 [0..0] =============================================== */ +typedef enum { /*!< CTIMER_INCFG_CFGA0 */ + CTIMER_INCFG_CFGA0_CT1 = 1, /*!< CT1 : Input is CT1 */ + CTIMER_INCFG_CFGA0_CT0 = 0, /*!< CT0 : Input is CT0 */ +} CTIMER_INCFG_CFGA0_Enum; + +/* ========================================================= STCFG ========================================================= */ +/* ============================================= CTIMER STCFG FREEZE [31..31] ============================================== */ +typedef enum { /*!< CTIMER_STCFG_FREEZE */ + CTIMER_STCFG_FREEZE_THAW = 0, /*!< THAW : Let the COUNTER register run on its input clock. */ + CTIMER_STCFG_FREEZE_FREEZE = 1, /*!< FREEZE : Stop the COUNTER register for loading. */ +} CTIMER_STCFG_FREEZE_Enum; + +/* ============================================== CTIMER STCFG CLEAR [30..30] ============================================== */ +typedef enum { /*!< CTIMER_STCFG_CLEAR */ + CTIMER_STCFG_CLEAR_RUN = 0, /*!< RUN : Let the COUNTER register run on its input clock. */ + CTIMER_STCFG_CLEAR_CLEAR = 1, /*!< CLEAR : Stop the COUNTER register for loading. */ +} CTIMER_STCFG_CLEAR_Enum; + +/* ========================================== CTIMER STCFG COMPARE_H_EN [15..15] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_H_EN */ + CTIMER_STCFG_COMPARE_H_EN_DISABLE = 0, /*!< DISABLE : Compare H disabled. */ + CTIMER_STCFG_COMPARE_H_EN_ENABLE = 1, /*!< ENABLE : Compare H enabled. */ +} CTIMER_STCFG_COMPARE_H_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_G_EN [14..14] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_G_EN */ + CTIMER_STCFG_COMPARE_G_EN_DISABLE = 0, /*!< DISABLE : Compare G disabled. */ + CTIMER_STCFG_COMPARE_G_EN_ENABLE = 1, /*!< ENABLE : Compare G enabled. */ +} CTIMER_STCFG_COMPARE_G_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_F_EN [13..13] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_F_EN */ + CTIMER_STCFG_COMPARE_F_EN_DISABLE = 0, /*!< DISABLE : Compare F disabled. */ + CTIMER_STCFG_COMPARE_F_EN_ENABLE = 1, /*!< ENABLE : Compare F enabled. */ +} CTIMER_STCFG_COMPARE_F_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_E_EN [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_E_EN */ + CTIMER_STCFG_COMPARE_E_EN_DISABLE = 0, /*!< DISABLE : Compare E disabled. */ + CTIMER_STCFG_COMPARE_E_EN_ENABLE = 1, /*!< ENABLE : Compare E enabled. */ +} CTIMER_STCFG_COMPARE_E_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_D_EN [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_D_EN */ + CTIMER_STCFG_COMPARE_D_EN_DISABLE = 0, /*!< DISABLE : Compare D disabled. */ + CTIMER_STCFG_COMPARE_D_EN_ENABLE = 1, /*!< ENABLE : Compare D enabled. */ +} CTIMER_STCFG_COMPARE_D_EN_Enum; + +/* ========================================== CTIMER STCFG COMPARE_C_EN [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_C_EN */ + CTIMER_STCFG_COMPARE_C_EN_DISABLE = 0, /*!< DISABLE : Compare C disabled. */ + CTIMER_STCFG_COMPARE_C_EN_ENABLE = 1, /*!< ENABLE : Compare C enabled. */ +} CTIMER_STCFG_COMPARE_C_EN_Enum; + +/* =========================================== CTIMER STCFG COMPARE_B_EN [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_B_EN */ + CTIMER_STCFG_COMPARE_B_EN_DISABLE = 0, /*!< DISABLE : Compare B disabled. */ + CTIMER_STCFG_COMPARE_B_EN_ENABLE = 1, /*!< ENABLE : Compare B enabled. */ +} CTIMER_STCFG_COMPARE_B_EN_Enum; + +/* =========================================== CTIMER STCFG COMPARE_A_EN [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STCFG_COMPARE_A_EN */ + CTIMER_STCFG_COMPARE_A_EN_DISABLE = 0, /*!< DISABLE : Compare A disabled. */ + CTIMER_STCFG_COMPARE_A_EN_ENABLE = 1, /*!< ENABLE : Compare A enabled. */ +} CTIMER_STCFG_COMPARE_A_EN_Enum; + +/* ============================================== CTIMER STCFG CLKSEL [0..3] =============================================== */ +typedef enum { /*!< CTIMER_STCFG_CLKSEL */ + CTIMER_STCFG_CLKSEL_NOCLK = 0, /*!< NOCLK : No clock enabled. */ + CTIMER_STCFG_CLKSEL_HFRC_DIV16 = 1, /*!< HFRC_DIV16 : 3MHz from the HFRC clock divider. */ + CTIMER_STCFG_CLKSEL_HFRC_DIV256 = 2, /*!< HFRC_DIV256 : 187.5KHz from the HFRC clock divider. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV1 = 3, /*!< XTAL_DIV1 : 32768Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV2 = 4, /*!< XTAL_DIV2 : 16384Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_XTAL_DIV32 = 5, /*!< XTAL_DIV32 : 1024Hz from the crystal oscillator. */ + CTIMER_STCFG_CLKSEL_LFRC_DIV1 = 6, /*!< LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated). */ + CTIMER_STCFG_CLKSEL_CTIMER0A = 7, /*!< CTIMER0A : Use CTIMER 0 section A as a prescaler for the clock + source. */ + CTIMER_STCFG_CLKSEL_CTIMER0B = 8, /*!< CTIMER0B : Use CTIMER 0 section B (or A and B linked together) + as a prescaler for the clock source. */ +} CTIMER_STCFG_CLKSEL_Enum; + +/* ========================================================= STTMR ========================================================= */ +/* ==================================================== CAPTURECONTROL ===================================================== */ +/* ========================================= CTIMER CAPTURECONTROL CAPTURE3 [3..3] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE3 */ + CTIMER_CAPTURECONTROL_CAPTURE3_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE3_Enum; + +/* ========================================= CTIMER CAPTURECONTROL CAPTURE2 [2..2] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE2 */ + CTIMER_CAPTURECONTROL_CAPTURE2_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE2_Enum; + +/* ========================================= CTIMER CAPTURECONTROL CAPTURE1 [1..1] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE1 */ + CTIMER_CAPTURECONTROL_CAPTURE1_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE1_Enum; + +/* ========================================= CTIMER CAPTURECONTROL CAPTURE0 [0..0] ========================================= */ +typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE0 */ + CTIMER_CAPTURECONTROL_CAPTURE0_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ + CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ +} CTIMER_CAPTURECONTROL_CAPTURE0_Enum; + +/* ======================================================== SCMPR0 ========================================================= */ +/* ======================================================== SCMPR1 ========================================================= */ +/* ======================================================== SCMPR2 ========================================================= */ +/* ======================================================== SCMPR3 ========================================================= */ +/* ======================================================== SCMPR4 ========================================================= */ +/* ======================================================== SCMPR5 ========================================================= */ +/* ======================================================== SCMPR6 ========================================================= */ +/* ======================================================== SCMPR7 ========================================================= */ +/* ======================================================== SCAPT0 ========================================================= */ +/* ======================================================== SCAPT1 ========================================================= */ +/* ======================================================== SCAPT2 ========================================================= */ +/* ======================================================== SCAPT3 ========================================================= */ +/* ========================================================= SNVR0 ========================================================= */ +/* ========================================================= SNVR1 ========================================================= */ +/* ========================================================= SNVR2 ========================================================= */ +/* ========================================================= SNVR3 ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================= STMINTEN ======================================================== */ +/* =========================================== CTIMER STMINTEN CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTURED */ + CTIMER_STMINTEN_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTURED_Enum; + +/* =========================================== CTIMER STMINTEN CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREC */ + CTIMER_STMINTEN_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREC_Enum; + +/* =========================================== CTIMER STMINTEN CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREB */ + CTIMER_STMINTEN_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREB_Enum; + +/* ============================================ CTIMER STMINTEN CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_CAPTUREA */ + CTIMER_STMINTEN_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTEN_CAPTUREA_Enum; + +/* ============================================ CTIMER STMINTEN OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_OVERFLOW */ + CTIMER_STMINTEN_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTEN_OVERFLOW_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREH */ + CTIMER_STMINTEN_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREH_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREG */ + CTIMER_STMINTEN_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREG_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREF */ + CTIMER_STMINTEN_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREF_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREE */ + CTIMER_STMINTEN_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREE_Enum; + +/* ============================================ CTIMER STMINTEN COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPARED */ + CTIMER_STMINTEN_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPARED_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREC */ + CTIMER_STMINTEN_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREC_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREB */ + CTIMER_STMINTEN_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREB_Enum; + +/* ============================================ CTIMER STMINTEN COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTEN_COMPAREA */ + CTIMER_STMINTEN_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTEN_COMPAREA_Enum; + +/* ====================================================== STMINTSTAT ======================================================= */ +/* ========================================== CTIMER STMINTSTAT CAPTURED [12..12] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTURED */ + CTIMER_STMINTSTAT_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTSTAT CAPTUREC [11..11] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREC */ + CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTSTAT CAPTUREB [10..10] ========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREB */ + CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTSTAT CAPTUREA [9..9] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREA */ + CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTSTAT_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTSTAT OVERFLOW [8..8] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_OVERFLOW */ + CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTSTAT_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREH [7..7] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREH */ + CTIMER_STMINTSTAT_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREG [6..6] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREG */ + CTIMER_STMINTSTAT_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREF [5..5] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREF */ + CTIMER_STMINTSTAT_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREE [4..4] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREE */ + CTIMER_STMINTSTAT_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPARED [3..3] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPARED */ + CTIMER_STMINTSTAT_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPARED_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREC [2..2] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREC */ + CTIMER_STMINTSTAT_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREB [1..1] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREB */ + CTIMER_STMINTSTAT_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTSTAT COMPAREA [0..0] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREA */ + CTIMER_STMINTSTAT_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSTAT_COMPAREA_Enum; + +/* ======================================================= STMINTCLR ======================================================= */ +/* ========================================== CTIMER STMINTCLR CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTURED */ + CTIMER_STMINTCLR_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTCLR CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREC */ + CTIMER_STMINTCLR_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTCLR CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREB */ + CTIMER_STMINTCLR_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTCLR CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREA */ + CTIMER_STMINTCLR_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTCLR_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTCLR OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_OVERFLOW */ + CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTCLR_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREH */ + CTIMER_STMINTCLR_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREG */ + CTIMER_STMINTCLR_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREF */ + CTIMER_STMINTCLR_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREE */ + CTIMER_STMINTCLR_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTCLR COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPARED */ + CTIMER_STMINTCLR_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPARED_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREC */ + CTIMER_STMINTCLR_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREB */ + CTIMER_STMINTCLR_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTCLR COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTCLR_COMPAREA */ + CTIMER_STMINTCLR_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTCLR_COMPAREA_Enum; + +/* ======================================================= STMINTSET ======================================================= */ +/* ========================================== CTIMER STMINTSET CAPTURED [12..12] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTURED */ + CTIMER_STMINTSET_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTURED_Enum; + +/* ========================================== CTIMER STMINTSET CAPTUREC [11..11] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREC */ + CTIMER_STMINTSET_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREC_Enum; + +/* ========================================== CTIMER STMINTSET CAPTUREB [10..10] =========================================== */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREB */ + CTIMER_STMINTSET_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREB_Enum; + +/* =========================================== CTIMER STMINTSET CAPTUREA [9..9] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_CAPTUREA */ + CTIMER_STMINTSET_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ +} CTIMER_STMINTSET_CAPTUREA_Enum; + +/* =========================================== CTIMER STMINTSET OVERFLOW [8..8] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_OVERFLOW */ + CTIMER_STMINTSET_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ +} CTIMER_STMINTSET_OVERFLOW_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREH [7..7] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREH */ + CTIMER_STMINTSET_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREH_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREG [6..6] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREG */ + CTIMER_STMINTSET_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREG_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREF [5..5] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREF */ + CTIMER_STMINTSET_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREF_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREE [4..4] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREE */ + CTIMER_STMINTSET_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREE_Enum; + +/* =========================================== CTIMER STMINTSET COMPARED [3..3] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPARED */ + CTIMER_STMINTSET_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPARED_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREC [2..2] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREC */ + CTIMER_STMINTSET_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREC_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREB [1..1] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREB */ + CTIMER_STMINTSET_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREB_Enum; + +/* =========================================== CTIMER STMINTSET COMPAREA [0..0] ============================================ */ +typedef enum { /*!< CTIMER_STMINTSET_COMPAREA */ + CTIMER_STMINTSET_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ +} CTIMER_STMINTSET_COMPAREA_Enum; + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PADREGA ======================================================== */ +/* ============================================ GPIO PADREGA PAD3PWRUP [30..30] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3PWRUP */ + GPIO_PADREGA_PAD3PWRUP_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGA_PAD3PWRUP_EN = 1, /*!< EN : Power switch enabled (switched to VDD) */ +} GPIO_PADREGA_PAD3PWRUP_Enum; + +/* =========================================== GPIO PADREGA PAD3FNCSEL [27..29] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3FNCSEL */ + GPIO_PADREGA_PAD3FNCSEL_UA0RTS = 0, /*!< UA0RTS : Configure as the UART0 RTS output */ + GPIO_PADREGA_PAD3FNCSEL_SLnCE = 1, /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal */ + GPIO_PADREGA_PAD3FNCSEL_NCE3 = 2, /*!< NCE3 : IOM/MSPI nCE group 3 */ + GPIO_PADREGA_PAD3FNCSEL_GPIO3 = 3, /*!< GPIO3 : Configure as GPIO3 */ + GPIO_PADREGA_PAD3FNCSEL_MSPI7 = 5, /*!< MSPI7 : MSPI data connection 7 */ + GPIO_PADREGA_PAD3FNCSEL_TRIG1 = 6, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK = 7, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */ +} GPIO_PADREGA_PAD3FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD3STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3STRNG */ + GPIO_PADREGA_PAD3STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD3STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD3STRNG_Enum; + +/* ============================================ GPIO PADREGA PAD3INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD3INPEN */ + GPIO_PADREGA_PAD3INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD3INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD3INPEN_Enum; + +/* ============================================ GPIO PADREGA PAD3PULL [24..24] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD3PULL */ + GPIO_PADREGA_PAD3PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD3PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD3PULL_Enum; + +/* =========================================== GPIO PADREGA PAD2FNCSEL [19..21] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2FNCSEL */ + GPIO_PADREGA_PAD2FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input. */ + GPIO_PADREGA_PAD2FNCSEL_SLMISO = 1, /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal. */ + GPIO_PADREGA_PAD2FNCSEL_UART0RX = 2, /*!< UART0RX : Configure as the UART0 RX input. */ + GPIO_PADREGA_PAD2FNCSEL_GPIO2 = 3, /*!< GPIO2 : Configure as GPIO2. */ + GPIO_PADREGA_PAD2FNCSEL_MSPI6 = 5, /*!< MSPI6 : MSPI data connection 6. */ + GPIO_PADREGA_PAD2FNCSEL_NCE2 = 7, /*!< NCE2 : IOM/MSPI nCE group 2 */ +} GPIO_PADREGA_PAD2FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD2STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2STRNG */ + GPIO_PADREGA_PAD2STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD2STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD2STRNG_Enum; + +/* ============================================ GPIO PADREGA PAD2INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD2INPEN */ + GPIO_PADREGA_PAD2INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD2INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD2INPEN_Enum; + +/* ============================================ GPIO PADREGA PAD2PULL [16..16] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD2PULL */ + GPIO_PADREGA_PAD2PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD2PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD2PULL_Enum; + +/* ============================================ GPIO PADREGA PAD1RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD1RSEL */ + GPIO_PADREGA_PAD1RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGA_PAD1RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGA_PAD1RSEL_Enum; + +/* =========================================== GPIO PADREGA PAD1FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD1FNCSEL */ + GPIO_PADREGA_PAD1FNCSEL_SLSDAWIR3 = 0, /*!< SLSDAWIR3 : Configure as the IOSLAVE I2C SDA or SPI WIR3 signal */ + GPIO_PADREGA_PAD1FNCSEL_SLMOSI = 1, /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal */ + GPIO_PADREGA_PAD1FNCSEL_UART0TX = 2, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGA_PAD1FNCSEL_GPIO1 = 3, /*!< GPIO1 : Configure as GPIO1 */ + GPIO_PADREGA_PAD1FNCSEL_MSPI5 = 5, /*!< MSPI5 : MSPI data connection 5 */ + GPIO_PADREGA_PAD1FNCSEL_NCE1 = 7, /*!< NCE1 : IOM/MSPI nCE group 1 */ +} GPIO_PADREGA_PAD1FNCSEL_Enum; + +/* ============================================ GPIO PADREGA PAD1STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGA_PAD1STRNG */ + GPIO_PADREGA_PAD1STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD1STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD1STRNG_Enum; + +/* ============================================= GPIO PADREGA PAD1INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD1INPEN */ + GPIO_PADREGA_PAD1INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD1INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD1INPEN_Enum; + +/* ============================================= GPIO PADREGA PAD1PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD1PULL */ + GPIO_PADREGA_PAD1PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD1PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD1PULL_Enum; + +/* ============================================= GPIO PADREGA PAD0RSEL [6..7] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD0RSEL */ + GPIO_PADREGA_PAD0RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGA_PAD0RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGA_PAD0RSEL_Enum; + +/* ============================================ GPIO PADREGA PAD0FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0FNCSEL */ + GPIO_PADREGA_PAD0FNCSEL_SLSCL = 0, /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal */ + GPIO_PADREGA_PAD0FNCSEL_SLSCK = 1, /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal */ + GPIO_PADREGA_PAD0FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGA_PAD0FNCSEL_GPIO0 = 3, /*!< GPIO0 : Configure as GPIO0 */ + GPIO_PADREGA_PAD0FNCSEL_MSPI4 = 5, /*!< MSPI4 : MSPI data connection 4 */ + GPIO_PADREGA_PAD0FNCSEL_NCE0 = 7, /*!< NCE0 : IOM/MSPI nCE group 0 */ +} GPIO_PADREGA_PAD0FNCSEL_Enum; + +/* ============================================= GPIO PADREGA PAD0STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0STRNG */ + GPIO_PADREGA_PAD0STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGA_PAD0STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGA_PAD0STRNG_Enum; + +/* ============================================= GPIO PADREGA PAD0INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGA_PAD0INPEN */ + GPIO_PADREGA_PAD0INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGA_PAD0INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGA_PAD0INPEN_Enum; + +/* ============================================= GPIO PADREGA PAD0PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGA_PAD0PULL */ + GPIO_PADREGA_PAD0PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGA_PAD0PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGA_PAD0PULL_Enum; + +/* ======================================================== PADREGB ======================================================== */ +/* =========================================== GPIO PADREGB PAD7FNCSEL [27..29] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7FNCSEL */ + GPIO_PADREGB_PAD7FNCSEL_NCE7 = 0, /*!< NCE7 : IOM/MSPI nCE group 7 */ + GPIO_PADREGB_PAD7FNCSEL_M0MOSI = 1, /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal */ + GPIO_PADREGB_PAD7FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ + GPIO_PADREGB_PAD7FNCSEL_GPIO7 = 3, /*!< GPIO7 : Configure as GPIO7 */ + GPIO_PADREGB_PAD7FNCSEL_TRIG0 = 4, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGB_PAD7FNCSEL_UART0TX = 5, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGB_PAD7FNCSEL_CT19 = 7, /*!< CT19 : CTIMER connection 19 */ +} GPIO_PADREGB_PAD7FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD7STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7STRNG */ + GPIO_PADREGB_PAD7STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD7STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD7STRNG_Enum; + +/* ============================================ GPIO PADREGB PAD7INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD7INPEN */ + GPIO_PADREGB_PAD7INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD7INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD7INPEN_Enum; + +/* ============================================ GPIO PADREGB PAD7PULL [24..24] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD7PULL */ + GPIO_PADREGB_PAD7PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD7PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD7PULL_Enum; + +/* ============================================ GPIO PADREGB PAD6RSEL [22..23] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD6RSEL */ + GPIO_PADREGB_PAD6RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGB_PAD6RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGB_PAD6RSEL_Enum; + +/* =========================================== GPIO PADREGB PAD6FNCSEL [19..21] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6FNCSEL */ + GPIO_PADREGB_PAD6FNCSEL_M0SDAWIR3 = 0, /*!< M0SDAWIR3 : Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGB_PAD6FNCSEL_M0MISO = 1, /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal */ + GPIO_PADREGB_PAD6FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGB_PAD6FNCSEL_GPIO6 = 3, /*!< GPIO6 : Configure as GPIO6 */ + GPIO_PADREGB_PAD6FNCSEL_CT10 = 5, /*!< CT10 : CTIMER connection 10 */ + GPIO_PADREGB_PAD6FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */ +} GPIO_PADREGB_PAD6FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD6STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6STRNG */ + GPIO_PADREGB_PAD6STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD6STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD6STRNG_Enum; + +/* ============================================ GPIO PADREGB PAD6INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD6INPEN */ + GPIO_PADREGB_PAD6INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD6INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD6INPEN_Enum; + +/* ============================================ GPIO PADREGB PAD6PULL [16..16] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD6PULL */ + GPIO_PADREGB_PAD6PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD6PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD6PULL_Enum; + +/* ============================================ GPIO PADREGB PAD5RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD5RSEL */ + GPIO_PADREGB_PAD5RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGB_PAD5RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGB_PAD5RSEL_Enum; + +/* =========================================== GPIO PADREGB PAD5FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD5FNCSEL */ + GPIO_PADREGB_PAD5FNCSEL_M0SCL = 0, /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal */ + GPIO_PADREGB_PAD5FNCSEL_M0SCK = 1, /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal */ + GPIO_PADREGB_PAD5FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS signal output */ + GPIO_PADREGB_PAD5FNCSEL_GPIO5 = 3, /*!< GPIO5 : Configure as GPIO5 */ + GPIO_PADREGB_PAD5FNCSEL_EXTHFA = 5, /*!< EXTHFA : Configure as the External HFA input clock */ + GPIO_PADREGB_PAD5FNCSEL_CT8 = 7, /*!< CT8 : CTIMER connection 8 */ +} GPIO_PADREGB_PAD5FNCSEL_Enum; + +/* ============================================ GPIO PADREGB PAD5STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGB_PAD5STRNG */ + GPIO_PADREGB_PAD5STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD5STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD5STRNG_Enum; + +/* ============================================= GPIO PADREGB PAD5INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD5INPEN */ + GPIO_PADREGB_PAD5INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD5INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD5INPEN_Enum; + +/* ============================================= GPIO PADREGB PAD5PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGB_PAD5PULL */ + GPIO_PADREGB_PAD5PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD5PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD5PULL_Enum; + +/* ============================================ GPIO PADREGB PAD4FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4FNCSEL */ + GPIO_PADREGB_PAD4FNCSEL_UA0CTS = 0, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGB_PAD4FNCSEL_SLINT = 1, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */ + GPIO_PADREGB_PAD4FNCSEL_NCE4 = 2, /*!< NCE4 : IOM/SPI nCE group 4 */ + GPIO_PADREGB_PAD4FNCSEL_GPIO4 = 3, /*!< GPIO4 : Configure as GPIO4 */ + GPIO_PADREGB_PAD4FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ + GPIO_PADREGB_PAD4FNCSEL_CT17 = 6, /*!< CT17 : CTIMER connection 17 */ + GPIO_PADREGB_PAD4FNCSEL_MSPI2 = 7, /*!< MSPI2 : MSPI data connection 2 */ +} GPIO_PADREGB_PAD4FNCSEL_Enum; + +/* ============================================= GPIO PADREGB PAD4STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4STRNG */ + GPIO_PADREGB_PAD4STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGB_PAD4STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGB_PAD4STRNG_Enum; + +/* ============================================= GPIO PADREGB PAD4INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGB_PAD4INPEN */ + GPIO_PADREGB_PAD4INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGB_PAD4INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGB_PAD4INPEN_Enum; + +/* ============================================= GPIO PADREGB PAD4PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGB_PAD4PULL */ + GPIO_PADREGB_PAD4PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGB_PAD4PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGB_PAD4PULL_Enum; + +/* ======================================================== PADREGC ======================================================== */ +/* =========================================== GPIO PADREGC PAD11FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD11FNCSEL */ + GPIO_PADREGC_PAD11FNCSEL_ADCSE2 = 0, /*!< ADCSE2 : Configure as the analog input for ADC single ended + input 2 */ + GPIO_PADREGC_PAD11FNCSEL_NCE11 = 1, /*!< NCE11 : IOM/MSPI nCE group 11 */ + GPIO_PADREGC_PAD11FNCSEL_CT31 = 2, /*!< CT31 : CTIMER connection 31 */ + GPIO_PADREGC_PAD11FNCSEL_GPIO11 = 3, /*!< GPIO11 : Configure as GPIO11 */ + GPIO_PADREGC_PAD11FNCSEL_SLINT = 4, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */ + GPIO_PADREGC_PAD11FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGC_PAD11FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGC_PAD11FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as the PDM Data input signal */ +} GPIO_PADREGC_PAD11FNCSEL_Enum; + +/* =========================================== GPIO PADREGC PAD11STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11STRNG */ + GPIO_PADREGC_PAD11STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD11STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD11STRNG_Enum; + +/* =========================================== GPIO PADREGC PAD11INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11INPEN */ + GPIO_PADREGC_PAD11INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD11INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD11INPEN_Enum; + +/* ============================================ GPIO PADREGC PAD11PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD11PULL */ + GPIO_PADREGC_PAD11PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD11PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD11PULL_Enum; + +/* =========================================== GPIO PADREGC PAD10FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD10FNCSEL */ + GPIO_PADREGC_PAD10FNCSEL_M1MOSI = 1, /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal */ + GPIO_PADREGC_PAD10FNCSEL_NCE10 = 2, /*!< NCE10 : IOM/MSPI nCE group 10 */ + GPIO_PADREGC_PAD10FNCSEL_GPIO10 = 3, /*!< GPIO10 : Configure as GPIO10 */ + GPIO_PADREGC_PAD10FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock out */ + GPIO_PADREGC_PAD10FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */ +} GPIO_PADREGC_PAD10FNCSEL_Enum; + +/* =========================================== GPIO PADREGC PAD10STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10STRNG */ + GPIO_PADREGC_PAD10STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD10STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD10STRNG_Enum; + +/* =========================================== GPIO PADREGC PAD10INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10INPEN */ + GPIO_PADREGC_PAD10INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD10INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD10INPEN_Enum; + +/* ============================================ GPIO PADREGC PAD10PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD10PULL */ + GPIO_PADREGC_PAD10PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD10PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD10PULL_Enum; + +/* ============================================ GPIO PADREGC PAD9RSEL [14..15] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD9RSEL */ + GPIO_PADREGC_PAD9RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGC_PAD9RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGC_PAD9RSEL_Enum; + +/* =========================================== GPIO PADREGC PAD9FNCSEL [11..13] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD9FNCSEL */ + GPIO_PADREGC_PAD9FNCSEL_M1SDAWIR3 = 0, /*!< M1SDAWIR3 : Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGC_PAD9FNCSEL_M1MISO = 1, /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal */ + GPIO_PADREGC_PAD9FNCSEL_NCE9 = 2, /*!< NCE9 : IOM/MSPI nCE group 9 */ + GPIO_PADREGC_PAD9FNCSEL_GPIO9 = 3, /*!< GPIO9 : Configure as GPIO9 */ + GPIO_PADREGC_PAD9FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD data I/O connection */ + GPIO_PADREGC_PAD9FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as UART1 RX input signal */ +} GPIO_PADREGC_PAD9FNCSEL_Enum; + +/* ============================================ GPIO PADREGC PAD9STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGC_PAD9STRNG */ + GPIO_PADREGC_PAD9STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD9STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD9STRNG_Enum; + +/* ============================================= GPIO PADREGC PAD9INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD9INPEN */ + GPIO_PADREGC_PAD9INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD9INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD9INPEN_Enum; + +/* ============================================= GPIO PADREGC PAD9PULL [8..8] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD9PULL */ + GPIO_PADREGC_PAD9PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD9PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD9PULL_Enum; + +/* ============================================= GPIO PADREGC PAD8RSEL [6..7] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD8RSEL */ + GPIO_PADREGC_PAD8RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGC_PAD8RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGC_PAD8RSEL_Enum; + +/* ============================================ GPIO PADREGC PAD8FNCSEL [3..5] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8FNCSEL */ + GPIO_PADREGC_PAD8FNCSEL_M1SCL = 0, /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal */ + GPIO_PADREGC_PAD8FNCSEL_M1SCK = 1, /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal */ + GPIO_PADREGC_PAD8FNCSEL_NCE8 = 2, /*!< NCE8 : IOM/MSPI nCE group 8 */ + GPIO_PADREGC_PAD8FNCSEL_GPIO8 = 3, /*!< GPIO8 : Configure as GPIO8 */ + GPIO_PADREGC_PAD8FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock output */ + GPIO_PADREGC_PAD8FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */ +} GPIO_PADREGC_PAD8FNCSEL_Enum; + +/* ============================================= GPIO PADREGC PAD8STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8STRNG */ + GPIO_PADREGC_PAD8STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGC_PAD8STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGC_PAD8STRNG_Enum; + +/* ============================================= GPIO PADREGC PAD8INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGC_PAD8INPEN */ + GPIO_PADREGC_PAD8INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGC_PAD8INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGC_PAD8INPEN_Enum; + +/* ============================================= GPIO PADREGC PAD8PULL [0..0] ============================================== */ +typedef enum { /*!< GPIO_PADREGC_PAD8PULL */ + GPIO_PADREGC_PAD8PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGC_PAD8PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGC_PAD8PULL_Enum; + +/* ======================================================== PADREGD ======================================================== */ +/* =========================================== GPIO PADREGD PAD15FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD15FNCSEL */ + GPIO_PADREGD_PAD15FNCSEL_ADCD1N = 0, /*!< ADCD1N : Configure as the analog ADC differential pair 1 N input + signal */ + GPIO_PADREGD_PAD15FNCSEL_NCE15 = 1, /*!< NCE15 : IOM/MSPI nCE group 15 */ + GPIO_PADREGD_PAD15FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX signal */ + GPIO_PADREGD_PAD15FNCSEL_GPIO15 = 3, /*!< GPIO15 : Configure as GPIO15 */ + GPIO_PADREGD_PAD15FNCSEL_PDMDATA = 4, /*!< PDMDATA : PDM serial data input */ + GPIO_PADREGD_PAD15FNCSEL_EXTXT = 5, /*!< EXTXT : Configure as the external XTAL oscillator input */ + GPIO_PADREGD_PAD15FNCSEL_SWDIO = 6, /*!< SWDIO : Configure as an alternate port for the SWDIO I/O signal */ + GPIO_PADREGD_PAD15FNCSEL_SWO = 7, /*!< SWO : Configure as an SWO (Serial Wire Trace output) */ +} GPIO_PADREGD_PAD15FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD15STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15STRNG */ + GPIO_PADREGD_PAD15STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD15STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD15STRNG_Enum; + +/* =========================================== GPIO PADREGD PAD15INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15INPEN */ + GPIO_PADREGD_PAD15INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD15INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD15INPEN_Enum; + +/* ============================================ GPIO PADREGD PAD15PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD15PULL */ + GPIO_PADREGD_PAD15PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD15PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD15PULL_Enum; + +/* =========================================== GPIO PADREGD PAD14FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD14FNCSEL */ + GPIO_PADREGD_PAD14FNCSEL_ADCD1P = 0, /*!< ADCD1P : Configure as the analog ADC differential pair 1 P input + signal */ + GPIO_PADREGD_PAD14FNCSEL_NCE14 = 1, /*!< NCE14 : IOM/MSPI nCE group 14 */ + GPIO_PADREGD_PAD14FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGD_PAD14FNCSEL_GPIO14 = 3, /*!< GPIO14 : Configure as GPIO14 */ + GPIO_PADREGD_PAD14FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock output */ + GPIO_PADREGD_PAD14FNCSEL_EXTHFS = 5, /*!< EXTHFS : Configure as the External HFRC oscillator input select */ + GPIO_PADREGD_PAD14FNCSEL_SWDCK = 6, /*!< SWDCK : Configure as the alternate input for the SWDCK input + signal */ + GPIO_PADREGD_PAD14FNCSEL_32kHzXT = 7, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ +} GPIO_PADREGD_PAD14FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD14STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14STRNG */ + GPIO_PADREGD_PAD14STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD14STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD14STRNG_Enum; + +/* =========================================== GPIO PADREGD PAD14INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14INPEN */ + GPIO_PADREGD_PAD14INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD14INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD14INPEN_Enum; + +/* ============================================ GPIO PADREGD PAD14PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD14PULL */ + GPIO_PADREGD_PAD14PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD14PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD14PULL_Enum; + +/* =========================================== GPIO PADREGD PAD13FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGD_PAD13FNCSEL */ + GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8 = 0, /*!< ADCD0PSE8 : Configure as the ADC Differential pair 0 P, or Single + Ended input 8 analog input signal. Determination of the + D0P vs SE8 usage is done when the particular channel is + selected within the ADC module */ + GPIO_PADREGD_PAD13FNCSEL_NCE13 = 1, /*!< NCE13 : IOM/MSPI nCE group 13 */ + GPIO_PADREGD_PAD13FNCSEL_CT2 = 2, /*!< CT2 : CTIMER connection 2 */ + GPIO_PADREGD_PAD13FNCSEL_GPIO13 = 3, /*!< GPIO13 : Configure as GPIO13 */ + GPIO_PADREGD_PAD13FNCSEL_I2SBCLK = 4, /*!< I2SBCLK : I2C interface bit clock */ + GPIO_PADREGD_PAD13FNCSEL_EXTHFB = 5, /*!< EXTHFB : Configure as the external HFRC oscillator input */ + GPIO_PADREGD_PAD13FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS signal output */ + GPIO_PADREGD_PAD13FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input signal */ +} GPIO_PADREGD_PAD13FNCSEL_Enum; + +/* =========================================== GPIO PADREGD PAD13STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD13STRNG */ + GPIO_PADREGD_PAD13STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD13STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD13STRNG_Enum; + +/* ============================================ GPIO PADREGD PAD13INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD13INPEN */ + GPIO_PADREGD_PAD13INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD13INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD13INPEN_Enum; + +/* ============================================= GPIO PADREGD PAD13PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD13PULL */ + GPIO_PADREGD_PAD13PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD13PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD13PULL_Enum; + +/* ============================================ GPIO PADREGD PAD12FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGD_PAD12FNCSEL */ + GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9 = 0, /*!< ADCD0NSE9 : Configure as the ADC Differential pair 0 N, or Single + Ended input 9 analog input signal. Determination of the + D0N vs SE9 usage is done when the particular channel is + selected within the ADC module */ + GPIO_PADREGD_PAD12FNCSEL_NCE12 = 1, /*!< NCE12 : IOM/MSPI nCE group 12 */ + GPIO_PADREGD_PAD12FNCSEL_CT0 = 2, /*!< CT0 : CTIMER connection 0 */ + GPIO_PADREGD_PAD12FNCSEL_GPIO12 = 3, /*!< GPIO12 : Configure as GPIO12 */ + GPIO_PADREGD_PAD12FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */ + GPIO_PADREGD_PAD12FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGD_PAD12FNCSEL_UART1TX = 7, /*!< UART1TX : Configure as the UART1 TX output signal */ +} GPIO_PADREGD_PAD12FNCSEL_Enum; + +/* ============================================ GPIO PADREGD PAD12STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12STRNG */ + GPIO_PADREGD_PAD12STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGD_PAD12STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGD_PAD12STRNG_Enum; + +/* ============================================ GPIO PADREGD PAD12INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12INPEN */ + GPIO_PADREGD_PAD12INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGD_PAD12INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGD_PAD12INPEN_Enum; + +/* ============================================= GPIO PADREGD PAD12PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGD_PAD12PULL */ + GPIO_PADREGD_PAD12PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGD_PAD12PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGD_PAD12PULL_Enum; + +/* ======================================================== PADREGE ======================================================== */ +/* =========================================== GPIO PADREGE PAD19FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD19FNCSEL */ + GPIO_PADREGE_PAD19FNCSEL_CMPRF0 = 0, /*!< CMPRF0 : Configure as the analog comparator reference 0 signal */ + GPIO_PADREGE_PAD19FNCSEL_NCE19 = 1, /*!< NCE19 : IOM/MSPI nCE group 19 */ + GPIO_PADREGE_PAD19FNCSEL_CT6 = 2, /*!< CT6 : CTIMER conenction 6 */ + GPIO_PADREGE_PAD19FNCSEL_GPIO19 = 3, /*!< GPIO19 : Configure as GPIO19 */ + GPIO_PADREGE_PAD19FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock */ + GPIO_PADREGE_PAD19FNCSEL_ANATEST1 = 5, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */ + GPIO_PADREGE_PAD19FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGE_PAD19FNCSEL_I2SBCLK = 7, /*!< I2SBCLK : Configure as the PDM I2S bit clock input signal */ +} GPIO_PADREGE_PAD19FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD19STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19STRNG */ + GPIO_PADREGE_PAD19STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD19STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD19STRNG_Enum; + +/* =========================================== GPIO PADREGE PAD19INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19INPEN */ + GPIO_PADREGE_PAD19INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD19INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD19INPEN_Enum; + +/* ============================================ GPIO PADREGE PAD19PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD19PULL */ + GPIO_PADREGE_PAD19PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD19PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD19PULL_Enum; + +/* =========================================== GPIO PADREGE PAD18FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD18FNCSEL */ + GPIO_PADREGE_PAD18FNCSEL_CMPIN1 = 0, /*!< CMPIN1 : Configure as the analog comparator input 1 signal */ + GPIO_PADREGE_PAD18FNCSEL_NCE18 = 1, /*!< NCE18 : IOM/MSPI nCE group 18 */ + GPIO_PADREGE_PAD18FNCSEL_CT4 = 2, /*!< CT4 : CTIMER connection 4 */ + GPIO_PADREGE_PAD18FNCSEL_GPIO18 = 3, /*!< GPIO18 : Configure as GPIO18 */ + GPIO_PADREGE_PAD18FNCSEL_UA0RTS = 4, /*!< UA0RTS : Configure as UART0 RTS output signal */ + GPIO_PADREGE_PAD18FNCSEL_ANATEST2 = 5, /*!< ANATEST2 : Configure as ANATEST2 I/O signal */ + GPIO_PADREGE_PAD18FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGE_PAD18FNCSEL_SCCIO = 7, /*!< SCCIO : SCARD data input/output connectin */ +} GPIO_PADREGE_PAD18FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD18STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18STRNG */ + GPIO_PADREGE_PAD18STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD18STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD18STRNG_Enum; + +/* =========================================== GPIO PADREGE PAD18INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18INPEN */ + GPIO_PADREGE_PAD18INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD18INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD18INPEN_Enum; + +/* ============================================ GPIO PADREGE PAD18PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD18PULL */ + GPIO_PADREGE_PAD18PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD18PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD18PULL_Enum; + +/* =========================================== GPIO PADREGE PAD17FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGE_PAD17FNCSEL */ + GPIO_PADREGE_PAD17FNCSEL_CMPRF1 = 0, /*!< CMPRF1 : Configure as the analog comparator reference signal + 1 input signal */ + GPIO_PADREGE_PAD17FNCSEL_NCE17 = 1, /*!< NCE17 : IOM/MSPI nCE group 17 */ + GPIO_PADREGE_PAD17FNCSEL_TRIG1 = 2, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGE_PAD17FNCSEL_GPIO17 = 3, /*!< GPIO17 : Configure as GPIO17 */ + GPIO_PADREGE_PAD17FNCSEL_SCCCLK = 4, /*!< SCCCLK : SCARD serial clock output */ + GPIO_PADREGE_PAD17FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGE_PAD17FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ +} GPIO_PADREGE_PAD17FNCSEL_Enum; + +/* =========================================== GPIO PADREGE PAD17STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD17STRNG */ + GPIO_PADREGE_PAD17STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD17STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD17STRNG_Enum; + +/* ============================================ GPIO PADREGE PAD17INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD17INPEN */ + GPIO_PADREGE_PAD17INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD17INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD17INPEN_Enum; + +/* ============================================= GPIO PADREGE PAD17PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD17PULL */ + GPIO_PADREGE_PAD17PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD17PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD17PULL_Enum; + +/* ============================================ GPIO PADREGE PAD16FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGE_PAD16FNCSEL */ + GPIO_PADREGE_PAD16FNCSEL_ADCSE0 = 0, /*!< ADCSE0 : Configure as the analog ADC single ended port 0 input + signal */ + GPIO_PADREGE_PAD16FNCSEL_NCE16 = 1, /*!< NCE16 : IOM/MSPI nCE group 16 */ + GPIO_PADREGE_PAD16FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGE_PAD16FNCSEL_GPIO16 = 3, /*!< GPIO16 : Configure as GPIO16 */ + GPIO_PADREGE_PAD16FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ + GPIO_PADREGE_PAD16FNCSEL_CMPIN0 = 5, /*!< CMPIN0 : Configure as comparator input 0 signal */ + GPIO_PADREGE_PAD16FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGE_PAD16FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ +} GPIO_PADREGE_PAD16FNCSEL_Enum; + +/* ============================================ GPIO PADREGE PAD16STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16STRNG */ + GPIO_PADREGE_PAD16STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGE_PAD16STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGE_PAD16STRNG_Enum; + +/* ============================================ GPIO PADREGE PAD16INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16INPEN */ + GPIO_PADREGE_PAD16INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGE_PAD16INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGE_PAD16INPEN_Enum; + +/* ============================================= GPIO PADREGE PAD16PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGE_PAD16PULL */ + GPIO_PADREGE_PAD16PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGE_PAD16PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGE_PAD16PULL_Enum; + +/* ======================================================== PADREGF ======================================================== */ +/* =========================================== GPIO PADREGF PAD23FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD23FNCSEL */ + GPIO_PADREGF_PAD23FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX signal */ + GPIO_PADREGF_PAD23FNCSEL_NCE23 = 1, /*!< NCE23 : IOM/MSPI nCE group 23 */ + GPIO_PADREGF_PAD23FNCSEL_CT14 = 2, /*!< CT14 : CTIMER connection 14 */ + GPIO_PADREGF_PAD23FNCSEL_GPIO23 = 3, /*!< GPIO23 : Configure as GPIO23 */ + GPIO_PADREGF_PAD23FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */ + GPIO_PADREGF_PAD23FNCSEL_CMPOUT = 5, /*!< CMPOUT : Configure as voltage comparitor output */ + GPIO_PADREGF_PAD23FNCSEL_MSPI3 = 6, /*!< MSPI3 : MSPI data connection 3 */ + GPIO_PADREGF_PAD23FNCSEL_EXTXT = 7, /*!< EXTXT : External XTAL osacillatgor input */ +} GPIO_PADREGF_PAD23FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD23STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23STRNG */ + GPIO_PADREGF_PAD23STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD23STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD23STRNG_Enum; + +/* =========================================== GPIO PADREGF PAD23INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23INPEN */ + GPIO_PADREGF_PAD23INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD23INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD23INPEN_Enum; + +/* ============================================ GPIO PADREGF PAD23PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD23PULL */ + GPIO_PADREGF_PAD23PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD23PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD23PULL_Enum; + +/* =========================================== GPIO PADREGF PAD22FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD22FNCSEL */ + GPIO_PADREGF_PAD22FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX signal */ + GPIO_PADREGF_PAD22FNCSEL_NCE22 = 1, /*!< NCE22 : IOM/MSPI nCE group 22 */ + GPIO_PADREGF_PAD22FNCSEL_CT12 = 2, /*!< CT12 : CTIMER connection 12 */ + GPIO_PADREGF_PAD22FNCSEL_GPIO22 = 3, /*!< GPIO22 : Configure as GPIO22 */ + GPIO_PADREGF_PAD22FNCSEL_PDM_CLK = 4, /*!< PDM_CLK : Configure as the PDM CLK output */ + GPIO_PADREGF_PAD22FNCSEL_EXTLF = 5, /*!< EXTLF : External LFRC input */ + GPIO_PADREGF_PAD22FNCSEL_MSPI0 = 6, /*!< MSPI0 : MSPI data connection 0 */ + GPIO_PADREGF_PAD22FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGF_PAD22FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD22STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22STRNG */ + GPIO_PADREGF_PAD22STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD22STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD22STRNG_Enum; + +/* =========================================== GPIO PADREGF PAD22INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22INPEN */ + GPIO_PADREGF_PAD22INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD22INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD22INPEN_Enum; + +/* ============================================ GPIO PADREGF PAD22PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD22PULL */ + GPIO_PADREGF_PAD22PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD22PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD22PULL_Enum; + +/* =========================================== GPIO PADREGF PAD21FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGF_PAD21FNCSEL */ + GPIO_PADREGF_PAD21FNCSEL_SWDIO = 0, /*!< SWDIO : Configure as the serial wire debug data signal */ + GPIO_PADREGF_PAD21FNCSEL_NCE21 = 1, /*!< NCE21 : IOM/MSPI nCE group 21 */ + GPIO_PADREGF_PAD21FNCSEL_GPIO21 = 3, /*!< GPIO21 : Configure as GPIO21 */ + GPIO_PADREGF_PAD21FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGF_PAD21FNCSEL_UART1RX = 5, /*!< UART1RX : Configure as UART1 RX input signal */ + GPIO_PADREGF_PAD21FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */ + GPIO_PADREGF_PAD21FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ +} GPIO_PADREGF_PAD21FNCSEL_Enum; + +/* =========================================== GPIO PADREGF PAD21STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD21STRNG */ + GPIO_PADREGF_PAD21STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD21STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD21STRNG_Enum; + +/* ============================================ GPIO PADREGF PAD21INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD21INPEN */ + GPIO_PADREGF_PAD21INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD21INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD21INPEN_Enum; + +/* ============================================= GPIO PADREGF PAD21PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD21PULL */ + GPIO_PADREGF_PAD21PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGF_PAD21PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGF_PAD21PULL_Enum; + +/* ============================================ GPIO PADREGF PAD20FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGF_PAD20FNCSEL */ + GPIO_PADREGF_PAD20FNCSEL_SWDCK = 0, /*!< SWDCK : Configure as the serial wire debug clock signal */ + GPIO_PADREGF_PAD20FNCSEL_NCE20 = 1, /*!< NCE20 : IOM/MSPI nCE group 20 */ + GPIO_PADREGF_PAD20FNCSEL_GPIO20 = 3, /*!< GPIO20 : Configure as GPIO20 */ + GPIO_PADREGF_PAD20FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGF_PAD20FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGF_PAD20FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */ + GPIO_PADREGF_PAD20FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ +} GPIO_PADREGF_PAD20FNCSEL_Enum; + +/* ============================================ GPIO PADREGF PAD20STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20STRNG */ + GPIO_PADREGF_PAD20STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGF_PAD20STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGF_PAD20STRNG_Enum; + +/* ============================================ GPIO PADREGF PAD20INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20INPEN */ + GPIO_PADREGF_PAD20INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGF_PAD20INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGF_PAD20INPEN_Enum; + +/* ============================================= GPIO PADREGF PAD20PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGF_PAD20PULL */ + GPIO_PADREGF_PAD20PULL_DIS = 0, /*!< DIS : Pulldown disabled */ + GPIO_PADREGF_PAD20PULL_EN = 1, /*!< EN : Pulldown enabled */ +} GPIO_PADREGF_PAD20PULL_Enum; + +/* ======================================================== PADREGG ======================================================== */ +/* ============================================ GPIO PADREGG PAD27RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27RSEL */ + GPIO_PADREGG_PAD27RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGG_PAD27RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGG_PAD27RSEL_Enum; + +/* =========================================== GPIO PADREGG PAD27FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD27FNCSEL */ + GPIO_PADREGG_PAD27FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as UART0 RX input signal */ + GPIO_PADREGG_PAD27FNCSEL_NCE27 = 1, /*!< NCE27 : IOM/MSPI nCE group 27 */ + GPIO_PADREGG_PAD27FNCSEL_CT5 = 2, /*!< CT5 : CTIMER connection 5 */ + GPIO_PADREGG_PAD27FNCSEL_GPIO27 = 3, /*!< GPIO27 : Configure as GPIO27 */ + GPIO_PADREGG_PAD27FNCSEL_M2SCL = 4, /*!< M2SCL : Configure as I2C clock I/O signal from IOMSTR2 */ + GPIO_PADREGG_PAD27FNCSEL_M2SCK = 5, /*!< M2SCK : Configure as SPI clock output signal from IOMSTR2 */ +} GPIO_PADREGG_PAD27FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD27STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27STRNG */ + GPIO_PADREGG_PAD27STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD27STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD27STRNG_Enum; + +/* =========================================== GPIO PADREGG PAD27INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27INPEN */ + GPIO_PADREGG_PAD27INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD27INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD27INPEN_Enum; + +/* ============================================ GPIO PADREGG PAD27PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD27PULL */ + GPIO_PADREGG_PAD27PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD27PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD27PULL_Enum; + +/* =========================================== GPIO PADREGG PAD26FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD26FNCSEL */ + GPIO_PADREGG_PAD26FNCSEL_EXTHF = 0, /*!< EXTHF : Configure as the external HFRC oscillator input */ + GPIO_PADREGG_PAD26FNCSEL_NCE26 = 1, /*!< NCE26 : IOM/MSPI nCE group 26 */ + GPIO_PADREGG_PAD26FNCSEL_CT3 = 2, /*!< CT3 : CTIMER connection 3 */ + GPIO_PADREGG_PAD26FNCSEL_GPIO26 = 3, /*!< GPIO26 : Configure as GPIO26 */ + GPIO_PADREGG_PAD26FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ + GPIO_PADREGG_PAD26FNCSEL_MSPI1 = 5, /*!< MSPI1 : MSPI data connection 1 */ + GPIO_PADREGG_PAD26FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGG_PAD26FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ +} GPIO_PADREGG_PAD26FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD26STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26STRNG */ + GPIO_PADREGG_PAD26STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD26STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD26STRNG_Enum; + +/* =========================================== GPIO PADREGG PAD26INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26INPEN */ + GPIO_PADREGG_PAD26INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD26INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD26INPEN_Enum; + +/* ============================================ GPIO PADREGG PAD26PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD26PULL */ + GPIO_PADREGG_PAD26PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD26PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD26PULL_Enum; + +/* ============================================ GPIO PADREGG PAD25RSEL [14..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD25RSEL */ + GPIO_PADREGG_PAD25RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGG_PAD25RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGG_PAD25RSEL_Enum; + +/* =========================================== GPIO PADREGG PAD25FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGG_PAD25FNCSEL */ + GPIO_PADREGG_PAD25FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as UART1 RX input signal */ + GPIO_PADREGG_PAD25FNCSEL_NCE25 = 1, /*!< NCE25 : IOM/MSPI nCE group 25 */ + GPIO_PADREGG_PAD25FNCSEL_CT1 = 2, /*!< CT1 : CTIMER connection 1 */ + GPIO_PADREGG_PAD25FNCSEL_GPIO25 = 3, /*!< GPIO25 : Configure as GPIO25 */ + GPIO_PADREGG_PAD25FNCSEL_M2SDAWIR3 = 4, /*!< M2SDAWIR3 : Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGG_PAD25FNCSEL_M2MISO = 5, /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal */ +} GPIO_PADREGG_PAD25FNCSEL_Enum; + +/* =========================================== GPIO PADREGG PAD25STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD25STRNG */ + GPIO_PADREGG_PAD25STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD25STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD25STRNG_Enum; + +/* ============================================ GPIO PADREGG PAD25INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD25INPEN */ + GPIO_PADREGG_PAD25INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD25INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD25INPEN_Enum; + +/* ============================================= GPIO PADREGG PAD25PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD25PULL */ + GPIO_PADREGG_PAD25PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD25PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD25PULL_Enum; + +/* ============================================ GPIO PADREGG PAD24FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGG_PAD24FNCSEL */ + GPIO_PADREGG_PAD24FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as UART1 TX output signal */ + GPIO_PADREGG_PAD24FNCSEL_NCE24 = 1, /*!< NCE24 : IOM/MSPI nCE group 24 */ + GPIO_PADREGG_PAD24FNCSEL_MSPI8 = 2, /*!< MSPI8 : MSPI data connection 8 */ + GPIO_PADREGG_PAD24FNCSEL_GPIO24 = 3, /*!< GPIO24 : Configure as GPIO24 */ + GPIO_PADREGG_PAD24FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as UART0 CTS input signal */ + GPIO_PADREGG_PAD24FNCSEL_CT21 = 5, /*!< CT21 : CTIMER connection 21 */ + GPIO_PADREGG_PAD24FNCSEL_32kHzXT = 6, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ + GPIO_PADREGG_PAD24FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGG_PAD24FNCSEL_Enum; + +/* ============================================ GPIO PADREGG PAD24STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24STRNG */ + GPIO_PADREGG_PAD24STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGG_PAD24STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGG_PAD24STRNG_Enum; + +/* ============================================ GPIO PADREGG PAD24INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24INPEN */ + GPIO_PADREGG_PAD24INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGG_PAD24INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGG_PAD24INPEN_Enum; + +/* ============================================= GPIO PADREGG PAD24PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGG_PAD24PULL */ + GPIO_PADREGG_PAD24PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGG_PAD24PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGG_PAD24PULL_Enum; + +/* ======================================================== PADREGH ======================================================== */ +/* =========================================== GPIO PADREGH PAD31FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD31FNCSEL */ + GPIO_PADREGH_PAD31FNCSEL_ADCSE3 = 0, /*!< ADCSE3 : Configure as the analog input for ADC single ended + input 3 */ + GPIO_PADREGH_PAD31FNCSEL_NCE31 = 1, /*!< NCE31 : IOM/MSPI nCE group 31 */ + GPIO_PADREGH_PAD31FNCSEL_CT13 = 2, /*!< CT13 : CTIMER connection 13 */ + GPIO_PADREGH_PAD31FNCSEL_GPIO31 = 3, /*!< GPIO31 : Configure as GPIO31 */ + GPIO_PADREGH_PAD31FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGH_PAD31FNCSEL_SCCCLK = 5, /*!< SCCCLK : SCARD serial clock output */ + GPIO_PADREGH_PAD31FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ +} GPIO_PADREGH_PAD31FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD31STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31STRNG */ + GPIO_PADREGH_PAD31STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD31STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD31STRNG_Enum; + +/* =========================================== GPIO PADREGH PAD31INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31INPEN */ + GPIO_PADREGH_PAD31INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD31INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD31INPEN_Enum; + +/* ============================================ GPIO PADREGH PAD31PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD31PULL */ + GPIO_PADREGH_PAD31PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD31PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD31PULL_Enum; + +/* =========================================== GPIO PADREGH PAD30FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD30FNCSEL */ + GPIO_PADREGH_PAD30FNCSEL_ANATEST1 = 0, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */ + GPIO_PADREGH_PAD30FNCSEL_NCE30 = 1, /*!< NCE30 : IOM/MSPI nCE group 30 */ + GPIO_PADREGH_PAD30FNCSEL_CT11 = 2, /*!< CT11 : CTIMER connection 11 */ + GPIO_PADREGH_PAD30FNCSEL_GPIO30 = 3, /*!< GPIO30 : Configure as GPIO30 */ + GPIO_PADREGH_PAD30FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ + GPIO_PADREGH_PAD30FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as UART1 RTS output signal */ + GPIO_PADREGH_PAD30FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */ +} GPIO_PADREGH_PAD30FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD30STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30STRNG */ + GPIO_PADREGH_PAD30STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD30STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD30STRNG_Enum; + +/* =========================================== GPIO PADREGH PAD30INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30INPEN */ + GPIO_PADREGH_PAD30INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD30INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD30INPEN_Enum; + +/* ============================================ GPIO PADREGH PAD30PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD30PULL */ + GPIO_PADREGH_PAD30PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD30PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD30PULL_Enum; + +/* =========================================== GPIO PADREGH PAD29FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGH_PAD29FNCSEL */ + GPIO_PADREGH_PAD29FNCSEL_ADCSE1 = 0, /*!< ADCSE1 : Configure as the analog input for ADC single ended + input 1 */ + GPIO_PADREGH_PAD29FNCSEL_NCE29 = 1, /*!< NCE29 : IOM/MSPI nCE group 29 */ + GPIO_PADREGH_PAD29FNCSEL_CT9 = 2, /*!< CT9 : CTIMER connection 9 */ + GPIO_PADREGH_PAD29FNCSEL_GPIO29 = 3, /*!< GPIO29 : Configure as GPIO29 */ + GPIO_PADREGH_PAD29FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGH_PAD29FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGH_PAD29FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGH_PAD29FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as PDM DATA input */ +} GPIO_PADREGH_PAD29FNCSEL_Enum; + +/* =========================================== GPIO PADREGH PAD29STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD29STRNG */ + GPIO_PADREGH_PAD29STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD29STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD29STRNG_Enum; + +/* ============================================ GPIO PADREGH PAD29INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD29INPEN */ + GPIO_PADREGH_PAD29INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD29INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD29INPEN_Enum; + +/* ============================================= GPIO PADREGH PAD29PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD29PULL */ + GPIO_PADREGH_PAD29PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD29PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD29PULL_Enum; + +/* ============================================ GPIO PADREGH PAD28FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGH_PAD28FNCSEL */ + GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK = 0, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */ + GPIO_PADREGH_PAD28FNCSEL_NCE28 = 1, /*!< NCE28 : IOM/MSPI nCE group 28 */ + GPIO_PADREGH_PAD28FNCSEL_CT7 = 2, /*!< CT7 : CTIMER connection 7 */ + GPIO_PADREGH_PAD28FNCSEL_GPIO28 = 3, /*!< GPIO28 : Configure as GPIO28 */ + GPIO_PADREGH_PAD28FNCSEL_M2MOSI = 5, /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal */ + GPIO_PADREGH_PAD28FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */ +} GPIO_PADREGH_PAD28FNCSEL_Enum; + +/* ============================================ GPIO PADREGH PAD28STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28STRNG */ + GPIO_PADREGH_PAD28STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGH_PAD28STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGH_PAD28STRNG_Enum; + +/* ============================================ GPIO PADREGH PAD28INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28INPEN */ + GPIO_PADREGH_PAD28INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGH_PAD28INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGH_PAD28INPEN_Enum; + +/* ============================================= GPIO PADREGH PAD28PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGH_PAD28PULL */ + GPIO_PADREGH_PAD28PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGH_PAD28PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGH_PAD28PULL_Enum; + +/* ======================================================== PADREGI ======================================================== */ +/* =========================================== GPIO PADREGI PAD35FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD35FNCSEL */ + GPIO_PADREGI_PAD35FNCSEL_ADCSE7 = 0, /*!< ADCSE7 : Configure as the analog input for ADC single ended + input 7 */ + GPIO_PADREGI_PAD35FNCSEL_NCE35 = 1, /*!< NCE35 : IOM/MSPI nCE group 35 */ + GPIO_PADREGI_PAD35FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX signal */ + GPIO_PADREGI_PAD35FNCSEL_GPIO35 = 3, /*!< GPIO35 : Configure as GPIO35 */ + GPIO_PADREGI_PAD35FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */ + GPIO_PADREGI_PAD35FNCSEL_CT27 = 5, /*!< CT27 : CTIMER connection 27 */ + GPIO_PADREGI_PAD35FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS output */ +} GPIO_PADREGI_PAD35FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD35STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35STRNG */ + GPIO_PADREGI_PAD35STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD35STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD35STRNG_Enum; + +/* =========================================== GPIO PADREGI PAD35INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35INPEN */ + GPIO_PADREGI_PAD35INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD35INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD35INPEN_Enum; + +/* ============================================ GPIO PADREGI PAD35PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD35PULL */ + GPIO_PADREGI_PAD35PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD35PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD35PULL_Enum; + +/* =========================================== GPIO PADREGI PAD34FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD34FNCSEL */ + GPIO_PADREGI_PAD34FNCSEL_ADCSE6 = 0, /*!< ADCSE6 : Configure as the analog input for ADC single ended + input 6 */ + GPIO_PADREGI_PAD34FNCSEL_NCE34 = 1, /*!< NCE34 : IOM/MSPI nCE group 34 */ + GPIO_PADREGI_PAD34FNCSEL_UA1RTS = 2, /*!< UA1RTS : Configure as the UART1 RTS output */ + GPIO_PADREGI_PAD34FNCSEL_GPIO34 = 3, /*!< GPIO34 : Configure as GPIO34 */ + GPIO_PADREGI_PAD34FNCSEL_CMPRF2 = 4, /*!< CMPRF2 : Configure as the analog comparator reference 2 signal */ + GPIO_PADREGI_PAD34FNCSEL_UA0RTS = 5, /*!< UA0RTS : Configure as the UART0 RTS output */ + GPIO_PADREGI_PAD34FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input */ + GPIO_PADREGI_PAD34FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */ +} GPIO_PADREGI_PAD34FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD34STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34STRNG */ + GPIO_PADREGI_PAD34STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD34STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD34STRNG_Enum; + +/* =========================================== GPIO PADREGI PAD34INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34INPEN */ + GPIO_PADREGI_PAD34INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD34INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD34INPEN_Enum; + +/* ============================================ GPIO PADREGI PAD34PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD34PULL */ + GPIO_PADREGI_PAD34PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD34PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD34PULL_Enum; + +/* =========================================== GPIO PADREGI PAD33FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGI_PAD33FNCSEL */ + GPIO_PADREGI_PAD33FNCSEL_ADCSE5 = 0, /*!< ADCSE5 : Configure as the analog ADC single ended port 5 input + signal */ + GPIO_PADREGI_PAD33FNCSEL_NCE33 = 1, /*!< NCE33 : IOM/MSPI nCE group 33 */ + GPIO_PADREGI_PAD33FNCSEL_32kHzXT = 2, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ + GPIO_PADREGI_PAD33FNCSEL_GPIO33 = 3, /*!< GPIO33 : Configure as GPIO33 */ + GPIO_PADREGI_PAD33FNCSEL_UA0CTS = 5, /*!< UA0CTS : Configure as the UART0 CTS input */ + GPIO_PADREGI_PAD33FNCSEL_CT23 = 6, /*!< CT23 : CTIMER connection 23 */ + GPIO_PADREGI_PAD33FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ +} GPIO_PADREGI_PAD33FNCSEL_Enum; + +/* =========================================== GPIO PADREGI PAD33STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD33STRNG */ + GPIO_PADREGI_PAD33STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD33STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD33STRNG_Enum; + +/* ============================================ GPIO PADREGI PAD33INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD33INPEN */ + GPIO_PADREGI_PAD33INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD33INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD33INPEN_Enum; + +/* ============================================= GPIO PADREGI PAD33PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD33PULL */ + GPIO_PADREGI_PAD33PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD33PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD33PULL_Enum; + +/* ============================================ GPIO PADREGI PAD32FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGI_PAD32FNCSEL */ + GPIO_PADREGI_PAD32FNCSEL_ADCSE4 = 0, /*!< ADCSE4 : Configure as the analog input for ADC single ended + input 4 */ + GPIO_PADREGI_PAD32FNCSEL_NCE32 = 1, /*!< NCE32 : IOM/MSPI nCE group 32 */ + GPIO_PADREGI_PAD32FNCSEL_CT15 = 2, /*!< CT15 : CTIMER connection 15 */ + GPIO_PADREGI_PAD32FNCSEL_GPIO32 = 3, /*!< GPIO32 : Configure as GPIO32 */ + GPIO_PADREGI_PAD32FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */ + GPIO_PADREGI_PAD32FNCSEL_EXTLF = 5, /*!< EXTLF : External input to the LFRC oscillator */ + GPIO_PADREGI_PAD32FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as the UART1 CTS input */ +} GPIO_PADREGI_PAD32FNCSEL_Enum; + +/* ============================================ GPIO PADREGI PAD32STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32STRNG */ + GPIO_PADREGI_PAD32STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGI_PAD32STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGI_PAD32STRNG_Enum; + +/* ============================================ GPIO PADREGI PAD32INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32INPEN */ + GPIO_PADREGI_PAD32INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGI_PAD32INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGI_PAD32INPEN_Enum; + +/* ============================================= GPIO PADREGI PAD32PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGI_PAD32PULL */ + GPIO_PADREGI_PAD32PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGI_PAD32PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGI_PAD32PULL_Enum; + +/* ======================================================== PADREGJ ======================================================== */ +/* ============================================ GPIO PADREGJ PAD39RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39RSEL */ + GPIO_PADREGJ_PAD39RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGJ_PAD39RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGJ_PAD39RSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD39FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD39FNCSEL */ + GPIO_PADREGJ_PAD39FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGJ_PAD39FNCSEL_UART1TX = 1, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGJ_PAD39FNCSEL_CT25 = 2, /*!< CT25 : CTIMER connection 25 */ + GPIO_PADREGJ_PAD39FNCSEL_GPIO39 = 3, /*!< GPIO39 : Configure as GPIO39 */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCL = 4, /*!< M4SCL : Configure as the IOMSTR4 I2C SCL signal */ + GPIO_PADREGJ_PAD39FNCSEL_M4SCK = 5, /*!< M4SCK : Configure as the IOMSTR4 SPI SCK signal */ +} GPIO_PADREGJ_PAD39FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD39STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39STRNG */ + GPIO_PADREGJ_PAD39STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD39STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD39STRNG_Enum; + +/* =========================================== GPIO PADREGJ PAD39INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39INPEN */ + GPIO_PADREGJ_PAD39INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD39INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD39INPEN_Enum; + +/* ============================================ GPIO PADREGJ PAD39PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD39PULL */ + GPIO_PADREGJ_PAD39PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD39PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD39PULL_Enum; + +/* =========================================== GPIO PADREGJ PAD38FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD38FNCSEL */ + GPIO_PADREGJ_PAD38FNCSEL_TRIG3 = 0, /*!< TRIG3 : Configure as the ADC Trigger 3 signal */ + GPIO_PADREGJ_PAD38FNCSEL_NCE38 = 1, /*!< NCE38 : IOM/MSPI nCE group 38 */ + GPIO_PADREGJ_PAD38FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS signal */ + GPIO_PADREGJ_PAD38FNCSEL_GPIO38 = 3, /*!< GPIO38 : Configure as GPIO38 */ + GPIO_PADREGJ_PAD38FNCSEL_M3MOSI = 5, /*!< M3MOSI : Configure as the IOMSTR3 SPI MOSI output signal */ + GPIO_PADREGJ_PAD38FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ +} GPIO_PADREGJ_PAD38FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD38STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38STRNG */ + GPIO_PADREGJ_PAD38STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD38STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD38STRNG_Enum; + +/* =========================================== GPIO PADREGJ PAD38INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38INPEN */ + GPIO_PADREGJ_PAD38INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD38INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD38INPEN_Enum; + +/* ============================================ GPIO PADREGJ PAD38PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD38PULL */ + GPIO_PADREGJ_PAD38PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD38PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD38PULL_Enum; + +/* =========================================== GPIO PADREGJ PAD37PWRDN [15..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD37PWRDN */ + GPIO_PADREGJ_PAD37PWRDN_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGJ_PAD37PWRDN_EN = 1, /*!< EN : Power switch enabled (switch to GND) */ +} GPIO_PADREGJ_PAD37PWRDN_Enum; + +/* =========================================== GPIO PADREGJ PAD37FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGJ_PAD37FNCSEL */ + GPIO_PADREGJ_PAD37FNCSEL_TRIG2 = 0, /*!< TRIG2 : Configure as the ADC Trigger 2 signal */ + GPIO_PADREGJ_PAD37FNCSEL_NCE37 = 1, /*!< NCE37 : IOM/MSPI nCE group 37 */ + GPIO_PADREGJ_PAD37FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS output signal */ + GPIO_PADREGJ_PAD37FNCSEL_GPIO37 = 3, /*!< GPIO37 : Configure as GPIO37 */ + GPIO_PADREGJ_PAD37FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */ + GPIO_PADREGJ_PAD37FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGJ_PAD37FNCSEL_PDMCLK = 6, /*!< PDMCLK : Configure as the PDM CLK output signal */ + GPIO_PADREGJ_PAD37FNCSEL_CT29 = 7, /*!< CT29 : CTIMER connection 29 */ +} GPIO_PADREGJ_PAD37FNCSEL_Enum; + +/* =========================================== GPIO PADREGJ PAD37STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD37STRNG */ + GPIO_PADREGJ_PAD37STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD37STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD37STRNG_Enum; + +/* ============================================ GPIO PADREGJ PAD37INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD37INPEN */ + GPIO_PADREGJ_PAD37INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD37INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD37INPEN_Enum; + +/* ============================================= GPIO PADREGJ PAD37PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD37PULL */ + GPIO_PADREGJ_PAD37PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD37PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD37PULL_Enum; + +/* ============================================ GPIO PADREGJ PAD36PWRUP [6..6] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36PWRUP */ + GPIO_PADREGJ_PAD36PWRUP_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGJ_PAD36PWRUP_EN = 1, /*!< EN : Power switch enabled (switched to VDD) */ +} GPIO_PADREGJ_PAD36PWRUP_Enum; + +/* ============================================ GPIO PADREGJ PAD36FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGJ_PAD36FNCSEL */ + GPIO_PADREGJ_PAD36FNCSEL_TRIG1 = 0, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ + GPIO_PADREGJ_PAD36FNCSEL_NCE36 = 1, /*!< NCE36 : IOM/MSPI nCE group 36 */ + GPIO_PADREGJ_PAD36FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGJ_PAD36FNCSEL_GPIO36 = 3, /*!< GPIO36 : Configure as GPIO36 */ + GPIO_PADREGJ_PAD36FNCSEL_32kHzXT = 4, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGJ_PAD36FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGJ_PAD36FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */ + GPIO_PADREGJ_PAD36FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */ +} GPIO_PADREGJ_PAD36FNCSEL_Enum; + +/* ============================================ GPIO PADREGJ PAD36STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36STRNG */ + GPIO_PADREGJ_PAD36STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGJ_PAD36STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGJ_PAD36STRNG_Enum; + +/* ============================================ GPIO PADREGJ PAD36INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36INPEN */ + GPIO_PADREGJ_PAD36INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGJ_PAD36INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGJ_PAD36INPEN_Enum; + +/* ============================================= GPIO PADREGJ PAD36PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGJ_PAD36PULL */ + GPIO_PADREGJ_PAD36PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGJ_PAD36PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGJ_PAD36PULL_Enum; + +/* ======================================================== PADREGK ======================================================== */ +/* ============================================ GPIO PADREGK PAD43RSEL [30..31] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43RSEL */ + GPIO_PADREGK_PAD43RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD43RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD43RSEL_Enum; + +/* =========================================== GPIO PADREGK PAD43FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD43FNCSEL */ + GPIO_PADREGK_PAD43FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGK_PAD43FNCSEL_NCE43 = 1, /*!< NCE43 : IOM/MSPI nCE group 43 */ + GPIO_PADREGK_PAD43FNCSEL_CT18 = 2, /*!< CT18 : CTIMER connection 18 */ + GPIO_PADREGK_PAD43FNCSEL_GPIO43 = 3, /*!< GPIO43 : Configure as GPIO43 */ + GPIO_PADREGK_PAD43FNCSEL_M3SDAWIR3 = 4, /*!< M3SDAWIR3 : Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGK_PAD43FNCSEL_M3MISO = 5, /*!< M3MISO : Configure as the IOMSTR3 SPI MISO signal */ +} GPIO_PADREGK_PAD43FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD43STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43STRNG */ + GPIO_PADREGK_PAD43STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD43STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD43STRNG_Enum; + +/* =========================================== GPIO PADREGK PAD43INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43INPEN */ + GPIO_PADREGK_PAD43INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD43INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD43INPEN_Enum; + +/* ============================================ GPIO PADREGK PAD43PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD43PULL */ + GPIO_PADREGK_PAD43PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD43PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD43PULL_Enum; + +/* ============================================ GPIO PADREGK PAD42RSEL [22..23] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42RSEL */ + GPIO_PADREGK_PAD42RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD42RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD42RSEL_Enum; + +/* =========================================== GPIO PADREGK PAD42FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD42FNCSEL */ + GPIO_PADREGK_PAD42FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGK_PAD42FNCSEL_NCE42 = 1, /*!< NCE42 : IOM/MSPI nCE group 42 */ + GPIO_PADREGK_PAD42FNCSEL_CT16 = 2, /*!< CT16 : CTIMER connection 16 */ + GPIO_PADREGK_PAD42FNCSEL_GPIO42 = 3, /*!< GPIO42 : Configure as GPIO42 */ + GPIO_PADREGK_PAD42FNCSEL_M3SCL = 4, /*!< M3SCL : Configure as the IOMSTR3 I2C SCL clock I/O signal */ + GPIO_PADREGK_PAD42FNCSEL_M3SCK = 5, /*!< M3SCK : Configure as the IOMSTR3 SPI SCK output */ +} GPIO_PADREGK_PAD42FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD42STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42STRNG */ + GPIO_PADREGK_PAD42STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD42STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD42STRNG_Enum; + +/* =========================================== GPIO PADREGK PAD42INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42INPEN */ + GPIO_PADREGK_PAD42INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD42INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD42INPEN_Enum; + +/* ============================================ GPIO PADREGK PAD42PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD42PULL */ + GPIO_PADREGK_PAD42PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD42PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD42PULL_Enum; + +/* =========================================== GPIO PADREGK PAD41PWRDN [15..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD41PWRDN */ + GPIO_PADREGK_PAD41PWRDN_DIS = 0, /*!< DIS : Power switch disabled */ + GPIO_PADREGK_PAD41PWRDN_EN = 1, /*!< EN : Power switch enabled (Switch pad to VSS) */ +} GPIO_PADREGK_PAD41PWRDN_Enum; + +/* =========================================== GPIO PADREGK PAD41FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGK_PAD41FNCSEL */ + GPIO_PADREGK_PAD41FNCSEL_NCE41 = 0, /*!< NCE41 : IOM/MSPI nCE group 41 */ + GPIO_PADREGK_PAD41FNCSEL_SWO = 2, /*!< SWO : Configure as the serial wire debug SWO signal */ + GPIO_PADREGK_PAD41FNCSEL_GPIO41 = 3, /*!< GPIO41 : Configure as GPIO41 */ + GPIO_PADREGK_PAD41FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */ + GPIO_PADREGK_PAD41FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */ + GPIO_PADREGK_PAD41FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGK_PAD41FNCSEL_UA0RTS = 7, /*!< UA0RTS : Configure as the UART0 RTS output signal */ +} GPIO_PADREGK_PAD41FNCSEL_Enum; + +/* =========================================== GPIO PADREGK PAD41STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD41STRNG */ + GPIO_PADREGK_PAD41STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD41STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD41STRNG_Enum; + +/* ============================================ GPIO PADREGK PAD41INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD41INPEN */ + GPIO_PADREGK_PAD41INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD41INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD41INPEN_Enum; + +/* ============================================= GPIO PADREGK PAD41PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD41PULL */ + GPIO_PADREGK_PAD41PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD41PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD41PULL_Enum; + +/* ============================================= GPIO PADREGK PAD40RSEL [6..7] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40RSEL */ + GPIO_PADREGK_PAD40RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGK_PAD40RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGK_PAD40RSEL_Enum; + +/* ============================================ GPIO PADREGK PAD40FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGK_PAD40FNCSEL */ + GPIO_PADREGK_PAD40FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGK_PAD40FNCSEL_UART1RX = 1, /*!< UART1RX : Configure as the UART1 RX input signal */ + GPIO_PADREGK_PAD40FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ + GPIO_PADREGK_PAD40FNCSEL_GPIO40 = 3, /*!< GPIO40 : Configure as GPIO40 */ + GPIO_PADREGK_PAD40FNCSEL_M4SDAWIR3 = 4, /*!< M4SDAWIR3 : Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGK_PAD40FNCSEL_M4MISO = 5, /*!< M4MISO : Configure as the IOMSTR4 SPI MISO input signal */ +} GPIO_PADREGK_PAD40FNCSEL_Enum; + +/* ============================================ GPIO PADREGK PAD40STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40STRNG */ + GPIO_PADREGK_PAD40STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGK_PAD40STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGK_PAD40STRNG_Enum; + +/* ============================================ GPIO PADREGK PAD40INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40INPEN */ + GPIO_PADREGK_PAD40INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGK_PAD40INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGK_PAD40INPEN_Enum; + +/* ============================================= GPIO PADREGK PAD40PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGK_PAD40PULL */ + GPIO_PADREGK_PAD40PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGK_PAD40PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGK_PAD40PULL_Enum; + +/* ======================================================== PADREGL ======================================================== */ +/* =========================================== GPIO PADREGL PAD47FNCSEL [27..29] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD47FNCSEL */ + GPIO_PADREGL_PAD47FNCSEL_32kHzXT = 0, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGL_PAD47FNCSEL_NCE47 = 1, /*!< NCE47 : IOM/MSPI nCE group 47 */ + GPIO_PADREGL_PAD47FNCSEL_CT26 = 2, /*!< CT26 : CTIMER connection 26 */ + GPIO_PADREGL_PAD47FNCSEL_GPIO47 = 3, /*!< GPIO47 : Configure as GPIO47 */ + GPIO_PADREGL_PAD47FNCSEL_M5MOSI = 5, /*!< M5MOSI : Configure as the IOMSTR5 SPI MOSI output signal */ + GPIO_PADREGL_PAD47FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ +} GPIO_PADREGL_PAD47FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD47STRNG [26..26] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47STRNG */ + GPIO_PADREGL_PAD47STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD47STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD47STRNG_Enum; + +/* =========================================== GPIO PADREGL PAD47INPEN [25..25] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47INPEN */ + GPIO_PADREGL_PAD47INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD47INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD47INPEN_Enum; + +/* ============================================ GPIO PADREGL PAD47PULL [24..24] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD47PULL */ + GPIO_PADREGL_PAD47PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD47PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD47PULL_Enum; + +/* =========================================== GPIO PADREGL PAD46FNCSEL [19..21] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD46FNCSEL */ + GPIO_PADREGL_PAD46FNCSEL_32khz_XT = 0, /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal */ + GPIO_PADREGL_PAD46FNCSEL_NCE46 = 1, /*!< NCE46 : IOM/MSPI nCE group 46 */ + GPIO_PADREGL_PAD46FNCSEL_CT24 = 2, /*!< CT24 : CTIMER connection 24 */ + GPIO_PADREGL_PAD46FNCSEL_GPIO46 = 3, /*!< GPIO46 : Configure as GPIO46 */ + GPIO_PADREGL_PAD46FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ + GPIO_PADREGL_PAD46FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */ + GPIO_PADREGL_PAD46FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */ + GPIO_PADREGL_PAD46FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */ +} GPIO_PADREGL_PAD46FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD46STRNG [18..18] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46STRNG */ + GPIO_PADREGL_PAD46STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD46STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD46STRNG_Enum; + +/* =========================================== GPIO PADREGL PAD46INPEN [17..17] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46INPEN */ + GPIO_PADREGL_PAD46INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD46INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD46INPEN_Enum; + +/* ============================================ GPIO PADREGL PAD46PULL [16..16] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD46PULL */ + GPIO_PADREGL_PAD46PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD46PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD46PULL_Enum; + +/* =========================================== GPIO PADREGL PAD45FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGL_PAD45FNCSEL */ + GPIO_PADREGL_PAD45FNCSEL_UA1CTS = 0, /*!< UA1CTS : Configure as the UART1 CTS input signal */ + GPIO_PADREGL_PAD45FNCSEL_NCE45 = 1, /*!< NCE45 : IOM/MSPI nCE group 45 */ + GPIO_PADREGL_PAD45FNCSEL_CT22 = 2, /*!< CT22 : CTIMER connection 22 */ + GPIO_PADREGL_PAD45FNCSEL_GPIO45 = 3, /*!< GPIO45 : Configure as GPIO45 */ + GPIO_PADREGL_PAD45FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */ + GPIO_PADREGL_PAD45FNCSEL_PDMDATA = 5, /*!< PDMDATA : PDM serial data input */ + GPIO_PADREGL_PAD45FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the SPI channel 5 nCE signal from IOMSTR5 */ + GPIO_PADREGL_PAD45FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */ +} GPIO_PADREGL_PAD45FNCSEL_Enum; + +/* =========================================== GPIO PADREGL PAD45STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD45STRNG */ + GPIO_PADREGL_PAD45STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD45STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD45STRNG_Enum; + +/* ============================================ GPIO PADREGL PAD45INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD45INPEN */ + GPIO_PADREGL_PAD45INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD45INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD45INPEN_Enum; + +/* ============================================= GPIO PADREGL PAD45PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD45PULL */ + GPIO_PADREGL_PAD45PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD45PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD45PULL_Enum; + +/* ============================================ GPIO PADREGL PAD44FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGL_PAD44FNCSEL */ + GPIO_PADREGL_PAD44FNCSEL_UA1RTS = 0, /*!< UA1RTS : Configure as the UART1 RTS output signal */ + GPIO_PADREGL_PAD44FNCSEL_NCE44 = 1, /*!< NCE44 : IOM/MSPI nCE group 44 */ + GPIO_PADREGL_PAD44FNCSEL_CT20 = 2, /*!< CT20 : CTIMER connection 20 */ + GPIO_PADREGL_PAD44FNCSEL_GPIO44 = 3, /*!< GPIO44 : Configure as GPIO44 */ + GPIO_PADREGL_PAD44FNCSEL_M4MOSI = 5, /*!< M4MOSI : Configure as the IOMSTR4 SPI MOSI signal */ + GPIO_PADREGL_PAD44FNCSEL_M5nCE6 = 6, /*!< M5nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR5 */ +} GPIO_PADREGL_PAD44FNCSEL_Enum; + +/* ============================================ GPIO PADREGL PAD44STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44STRNG */ + GPIO_PADREGL_PAD44STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGL_PAD44STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGL_PAD44STRNG_Enum; + +/* ============================================ GPIO PADREGL PAD44INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44INPEN */ + GPIO_PADREGL_PAD44INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGL_PAD44INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGL_PAD44INPEN_Enum; + +/* ============================================= GPIO PADREGL PAD44PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGL_PAD44PULL */ + GPIO_PADREGL_PAD44PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGL_PAD44PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGL_PAD44PULL_Enum; + +/* ======================================================== PADREGM ======================================================== */ +/* ============================================ GPIO PADREGM PAD49RSEL [14..15] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD49RSEL */ + GPIO_PADREGM_PAD49RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGM_PAD49RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGM_PAD49RSEL_Enum; + +/* =========================================== GPIO PADREGM PAD49FNCSEL [11..13] =========================================== */ +typedef enum { /*!< GPIO_PADREGM_PAD49FNCSEL */ + GPIO_PADREGM_PAD49FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */ + GPIO_PADREGM_PAD49FNCSEL_NCE49 = 1, /*!< NCE49 : IOM/MSPPI nCE group 49 */ + GPIO_PADREGM_PAD49FNCSEL_CT30 = 2, /*!< CT30 : CTIMER connection 30 */ + GPIO_PADREGM_PAD49FNCSEL_GPIO49 = 3, /*!< GPIO49 : Configure as GPIO49 */ + GPIO_PADREGM_PAD49FNCSEL_M5SDAWIR3 = 4, /*!< M5SDAWIR3 : Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal */ + GPIO_PADREGM_PAD49FNCSEL_M5MISO = 5, /*!< M5MISO : Configure as the IOMSTR5 SPI MISO input signal */ +} GPIO_PADREGM_PAD49FNCSEL_Enum; + +/* =========================================== GPIO PADREGM PAD49STRNG [10..10] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD49STRNG */ + GPIO_PADREGM_PAD49STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGM_PAD49STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGM_PAD49STRNG_Enum; + +/* ============================================ GPIO PADREGM PAD49INPEN [9..9] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD49INPEN */ + GPIO_PADREGM_PAD49INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGM_PAD49INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGM_PAD49INPEN_Enum; + +/* ============================================= GPIO PADREGM PAD49PULL [8..8] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD49PULL */ + GPIO_PADREGM_PAD49PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGM_PAD49PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGM_PAD49PULL_Enum; + +/* ============================================= GPIO PADREGM PAD48RSEL [6..7] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48RSEL */ + GPIO_PADREGM_PAD48RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ + GPIO_PADREGM_PAD48RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ +} GPIO_PADREGM_PAD48RSEL_Enum; + +/* ============================================ GPIO PADREGM PAD48FNCSEL [3..5] ============================================ */ +typedef enum { /*!< GPIO_PADREGM_PAD48FNCSEL */ + GPIO_PADREGM_PAD48FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */ + GPIO_PADREGM_PAD48FNCSEL_NCE48 = 1, /*!< NCE48 : IOM/MSPI nCE group 48 */ + GPIO_PADREGM_PAD48FNCSEL_CT28 = 2, /*!< CT28 : CTIMER conenction 28 */ + GPIO_PADREGM_PAD48FNCSEL_GPIO48 = 3, /*!< GPIO48 : Configure as GPIO48 */ + GPIO_PADREGM_PAD48FNCSEL_M5SCL = 4, /*!< M5SCL : Configure as the IOMSTR5 I2C SCL clock I/O signal */ + GPIO_PADREGM_PAD48FNCSEL_M5SCK = 5, /*!< M5SCK : Configure as the IOMSTR5 SPI SCK output */ +} GPIO_PADREGM_PAD48FNCSEL_Enum; + +/* ============================================ GPIO PADREGM PAD48STRNG [2..2] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48STRNG */ + GPIO_PADREGM_PAD48STRNG_LOW = 0, /*!< LOW : Low drive strength */ + GPIO_PADREGM_PAD48STRNG_HIGH = 1, /*!< HIGH : High drive strength */ +} GPIO_PADREGM_PAD48STRNG_Enum; + +/* ============================================ GPIO PADREGM PAD48INPEN [1..1] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48INPEN */ + GPIO_PADREGM_PAD48INPEN_DIS = 0, /*!< DIS : Pad input disabled */ + GPIO_PADREGM_PAD48INPEN_EN = 1, /*!< EN : Pad input enabled */ +} GPIO_PADREGM_PAD48INPEN_Enum; + +/* ============================================= GPIO PADREGM PAD48PULL [0..0] ============================================= */ +typedef enum { /*!< GPIO_PADREGM_PAD48PULL */ + GPIO_PADREGM_PAD48PULL_DIS = 0, /*!< DIS : Pullup disabled */ + GPIO_PADREGM_PAD48PULL_EN = 1, /*!< EN : Pullup enabled */ +} GPIO_PADREGM_PAD48PULL_Enum; + +/* ========================================================= CFGA ========================================================== */ +/* ============================================= GPIO CFGA GPIO7INTD [31..31] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO7INTD */ + GPIO_CFGA_GPIO7INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low */ + GPIO_CFGA_GPIO7INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high */ +} GPIO_CFGA_GPIO7INTD_Enum; + +/* ============================================ GPIO CFGA GPIO7OUTCFG [29..30] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO7OUTCFG */ + GPIO_CFGA_GPIO7OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO7OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO7OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO7OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO7OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO7INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO7INCFG */ + GPIO_CFGA_GPIO7INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO7INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO7INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO6INTD [27..27] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO6INTD */ + GPIO_CFGA_GPIO6INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGA_GPIO6INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGA_GPIO6INTD_Enum; + +/* ============================================ GPIO CFGA GPIO6OUTCFG [25..26] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO6OUTCFG */ + GPIO_CFGA_GPIO6OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO6OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO6OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO6OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO6OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO6INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO6INCFG */ + GPIO_CFGA_GPIO6INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO6INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO6INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO5INTD [23..23] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO5INTD */ + GPIO_CFGA_GPIO5INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGA_GPIO5INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGA_GPIO5INTD_Enum; + +/* ============================================ GPIO CFGA GPIO5OUTCFG [21..22] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO5OUTCFG */ + GPIO_CFGA_GPIO5OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO5OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO5OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO5OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO5OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO5INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO5INCFG */ + GPIO_CFGA_GPIO5INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO5INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO5INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO4INTD [19..19] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO4INTD */ + GPIO_CFGA_GPIO4INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGA_GPIO4INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGA_GPIO4INTD_Enum; + +/* ============================================ GPIO CFGA GPIO4OUTCFG [17..18] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO4OUTCFG */ + GPIO_CFGA_GPIO4OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO4OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO4OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO4OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO4OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO4INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO4INCFG */ + GPIO_CFGA_GPIO4INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO4INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO4INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO3INTD [15..15] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO3INTD */ + GPIO_CFGA_GPIO3INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGA_GPIO3INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGA_GPIO3INTD_Enum; + +/* ============================================ GPIO CFGA GPIO3OUTCFG [13..14] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO3OUTCFG */ + GPIO_CFGA_GPIO3OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO3OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO3OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO3OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO3OUTCFG_Enum; + +/* ============================================= GPIO CFGA GPIO3INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO3INCFG */ + GPIO_CFGA_GPIO3INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO3INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO3INCFG_Enum; + +/* ============================================= GPIO CFGA GPIO2INTD [11..11] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO2INTD */ + GPIO_CFGA_GPIO2INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */ + GPIO_CFGA_GPIO2INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */ +} GPIO_CFGA_GPIO2INTD_Enum; + +/* ============================================= GPIO CFGA GPIO2OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGA_GPIO2OUTCFG */ + GPIO_CFGA_GPIO2OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO2OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO2OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO2OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO2OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO2INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO2INCFG */ + GPIO_CFGA_GPIO2INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO2INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO2INCFG_Enum; + +/* ============================================== GPIO CFGA GPIO1INTD [7..7] =============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1INTD */ + GPIO_CFGA_GPIO1INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */ + GPIO_CFGA_GPIO1INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */ +} GPIO_CFGA_GPIO1INTD_Enum; + +/* ============================================= GPIO CFGA GPIO1OUTCFG [5..6] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1OUTCFG */ + GPIO_CFGA_GPIO1OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO1OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO1OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO1OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO1OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO1INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO1INCFG */ + GPIO_CFGA_GPIO1INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO1INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO1INCFG_Enum; + +/* ============================================== GPIO CFGA GPIO0INTD [3..3] =============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0INTD */ + GPIO_CFGA_GPIO0INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */ + GPIO_CFGA_GPIO0INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */ +} GPIO_CFGA_GPIO0INTD_Enum; + +/* ============================================= GPIO CFGA GPIO0OUTCFG [1..2] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0OUTCFG */ + GPIO_CFGA_GPIO0OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGA_GPIO0OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGA_GPIO0OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGA_GPIO0OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGA_GPIO0OUTCFG_Enum; + +/* ============================================== GPIO CFGA GPIO0INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGA_GPIO0INCFG */ + GPIO_CFGA_GPIO0INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGA_GPIO0INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGA_GPIO0INCFG_Enum; + +/* ========================================================= CFGB ========================================================== */ +/* ============================================= GPIO CFGB GPIO15INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO15INTD */ + GPIO_CFGB_GPIO15INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO15INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO15INTD_Enum; + +/* ============================================ GPIO CFGB GPIO15OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO15OUTCFG */ + GPIO_CFGB_GPIO15OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO15OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO15OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO15OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO15OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO15INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO15INCFG */ + GPIO_CFGB_GPIO15INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO15INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO15INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO14INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO14INTD */ + GPIO_CFGB_GPIO14INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO14INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO14INTD_Enum; + +/* ============================================ GPIO CFGB GPIO14OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO14OUTCFG */ + GPIO_CFGB_GPIO14OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO14OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO14OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO14OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO14OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO14INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO14INCFG */ + GPIO_CFGB_GPIO14INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO14INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO14INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO13INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO13INTD */ + GPIO_CFGB_GPIO13INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO13INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO13INTD_Enum; + +/* ============================================ GPIO CFGB GPIO13OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO13OUTCFG */ + GPIO_CFGB_GPIO13OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO13OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO13OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO13OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO13OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO13INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO13INCFG */ + GPIO_CFGB_GPIO13INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO13INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO13INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO12INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO12INTD */ + GPIO_CFGB_GPIO12INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO12INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO12INTD_Enum; + +/* ============================================ GPIO CFGB GPIO12OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO12OUTCFG */ + GPIO_CFGB_GPIO12OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO12OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO12OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO12OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO12OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO12INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO12INCFG */ + GPIO_CFGB_GPIO12INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO12INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO12INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO11INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO11INTD */ + GPIO_CFGB_GPIO11INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGB_GPIO11INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGB_GPIO11INTD_Enum; + +/* ============================================ GPIO CFGB GPIO11OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGB_GPIO11OUTCFG */ + GPIO_CFGB_GPIO11OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO11OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO11OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO11OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO11OUTCFG_Enum; + +/* ============================================ GPIO CFGB GPIO11INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO11INCFG */ + GPIO_CFGB_GPIO11INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO11INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO11INCFG_Enum; + +/* ============================================= GPIO CFGB GPIO10INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO10INTD */ + GPIO_CFGB_GPIO10INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGB_GPIO10INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGB_GPIO10INTD_Enum; + +/* ============================================ GPIO CFGB GPIO10OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGB_GPIO10OUTCFG */ + GPIO_CFGB_GPIO10OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO10OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO10OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO10OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO10OUTCFG_Enum; + +/* ============================================= GPIO CFGB GPIO10INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO10INCFG */ + GPIO_CFGB_GPIO10INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO10INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO10INCFG_Enum; + +/* ============================================== GPIO CFGB GPIO9INTD [7..7] =============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9INTD */ + GPIO_CFGB_GPIO9INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGB_GPIO9INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGB_GPIO9INTD_Enum; + +/* ============================================= GPIO CFGB GPIO9OUTCFG [5..6] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9OUTCFG */ + GPIO_CFGB_GPIO9OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO9OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO9OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO9OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO9OUTCFG_Enum; + +/* ============================================== GPIO CFGB GPIO9INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO9INCFG */ + GPIO_CFGB_GPIO9INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO9INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO9INCFG_Enum; + +/* ============================================== GPIO CFGB GPIO8INTD [3..3] =============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8INTD */ + GPIO_CFGB_GPIO8INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */ + GPIO_CFGB_GPIO8INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */ +} GPIO_CFGB_GPIO8INTD_Enum; + +/* ============================================= GPIO CFGB GPIO8OUTCFG [1..2] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8OUTCFG */ + GPIO_CFGB_GPIO8OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGB_GPIO8OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGB_GPIO8OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGB_GPIO8OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGB_GPIO8OUTCFG_Enum; + +/* ============================================== GPIO CFGB GPIO8INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGB_GPIO8INCFG */ + GPIO_CFGB_GPIO8INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGB_GPIO8INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGB_GPIO8INCFG_Enum; + +/* ========================================================= CFGC ========================================================== */ +/* ============================================= GPIO CFGC GPIO23INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO23INTD */ + GPIO_CFGC_GPIO23INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO23INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO23INTD_Enum; + +/* ============================================ GPIO CFGC GPIO23OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO23OUTCFG */ + GPIO_CFGC_GPIO23OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO23OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO23OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO23OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO23OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO23INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO23INCFG */ + GPIO_CFGC_GPIO23INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO23INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO23INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO22INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO22INTD */ + GPIO_CFGC_GPIO22INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO22INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO22INTD_Enum; + +/* ============================================ GPIO CFGC GPIO22OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO22OUTCFG */ + GPIO_CFGC_GPIO22OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO22OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO22OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO22OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO22OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO22INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO22INCFG */ + GPIO_CFGC_GPIO22INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO22INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO22INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO21INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO21INTD */ + GPIO_CFGC_GPIO21INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO21INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO21INTD_Enum; + +/* ============================================ GPIO CFGC GPIO21OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO21OUTCFG */ + GPIO_CFGC_GPIO21OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO21OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO21OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO21OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO21OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO21INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO21INCFG */ + GPIO_CFGC_GPIO21INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO21INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO21INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO20INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO20INTD */ + GPIO_CFGC_GPIO20INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO20INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO20INTD_Enum; + +/* ============================================ GPIO CFGC GPIO20OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO20OUTCFG */ + GPIO_CFGC_GPIO20OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO20OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO20OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO20OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO20OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO20INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO20INCFG */ + GPIO_CFGC_GPIO20INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO20INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO20INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO19INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO19INTD */ + GPIO_CFGC_GPIO19INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO19INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO19INTD_Enum; + +/* ============================================ GPIO CFGC GPIO19OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGC_GPIO19OUTCFG */ + GPIO_CFGC_GPIO19OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO19OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO19OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO19OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO19OUTCFG_Enum; + +/* ============================================ GPIO CFGC GPIO19INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO19INCFG */ + GPIO_CFGC_GPIO19INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO19INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO19INCFG_Enum; + +/* ============================================= GPIO CFGC GPIO18INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO18INTD */ + GPIO_CFGC_GPIO18INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO18INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO18INTD_Enum; + +/* ============================================ GPIO CFGC GPIO18OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO18OUTCFG */ + GPIO_CFGC_GPIO18OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO18OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO18OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO18OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO18OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO18INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO18INCFG */ + GPIO_CFGC_GPIO18INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO18INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO18INCFG_Enum; + +/* ============================================== GPIO CFGC GPIO17INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO17INTD */ + GPIO_CFGC_GPIO17INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO17INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO17INTD_Enum; + +/* ============================================= GPIO CFGC GPIO17OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO17OUTCFG */ + GPIO_CFGC_GPIO17OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO17OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO17OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO17OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO17OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO17INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO17INCFG */ + GPIO_CFGC_GPIO17INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO17INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO17INCFG_Enum; + +/* ============================================== GPIO CFGC GPIO16INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO16INTD */ + GPIO_CFGC_GPIO16INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGC_GPIO16INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGC_GPIO16INTD_Enum; + +/* ============================================= GPIO CFGC GPIO16OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGC_GPIO16OUTCFG */ + GPIO_CFGC_GPIO16OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGC_GPIO16OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGC_GPIO16OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGC_GPIO16OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGC_GPIO16OUTCFG_Enum; + +/* ============================================= GPIO CFGC GPIO16INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGC_GPIO16INCFG */ + GPIO_CFGC_GPIO16INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGC_GPIO16INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGC_GPIO16INCFG_Enum; + +/* ========================================================= CFGD ========================================================== */ +/* ============================================= GPIO CFGD GPIO31INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO31INTD */ + GPIO_CFGD_GPIO31INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO31INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO31INTD_Enum; + +/* ============================================ GPIO CFGD GPIO31OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO31OUTCFG */ + GPIO_CFGD_GPIO31OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO31OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO31OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO31OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO31OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO31INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO31INCFG */ + GPIO_CFGD_GPIO31INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO31INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO31INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO30INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO30INTD */ + GPIO_CFGD_GPIO30INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO30INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO30INTD_Enum; + +/* ============================================ GPIO CFGD GPIO30OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO30OUTCFG */ + GPIO_CFGD_GPIO30OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO30OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO30OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO30OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO30OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO30INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO30INCFG */ + GPIO_CFGD_GPIO30INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO30INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO30INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO29INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO29INTD */ + GPIO_CFGD_GPIO29INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO29INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO29INTD_Enum; + +/* ============================================ GPIO CFGD GPIO29OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO29OUTCFG */ + GPIO_CFGD_GPIO29OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO29OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO29OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO29OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO29OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO29INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO29INCFG */ + GPIO_CFGD_GPIO29INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO29INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO29INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO28INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO28INTD */ + GPIO_CFGD_GPIO28INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO28INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO28INTD_Enum; + +/* ============================================ GPIO CFGD GPIO28OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO28OUTCFG */ + GPIO_CFGD_GPIO28OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO28OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO28OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO28OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO28OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO28INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO28INCFG */ + GPIO_CFGD_GPIO28INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO28INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO28INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO27INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO27INTD */ + GPIO_CFGD_GPIO27INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO27INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO27INTD_Enum; + +/* ============================================ GPIO CFGD GPIO27OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGD_GPIO27OUTCFG */ + GPIO_CFGD_GPIO27OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO27OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO27OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO27OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO27OUTCFG_Enum; + +/* ============================================ GPIO CFGD GPIO27INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO27INCFG */ + GPIO_CFGD_GPIO27INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO27INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO27INCFG_Enum; + +/* ============================================= GPIO CFGD GPIO26INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO26INTD */ + GPIO_CFGD_GPIO26INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO26INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO26INTD_Enum; + +/* ============================================ GPIO CFGD GPIO26OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO26OUTCFG */ + GPIO_CFGD_GPIO26OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO26OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO26OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO26OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO26OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO26INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO26INCFG */ + GPIO_CFGD_GPIO26INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO26INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO26INCFG_Enum; + +/* ============================================== GPIO CFGD GPIO25INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO25INTD */ + GPIO_CFGD_GPIO25INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO25INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO25INTD_Enum; + +/* ============================================= GPIO CFGD GPIO25OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO25OUTCFG */ + GPIO_CFGD_GPIO25OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO25OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO25OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO25OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO25OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO25INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO25INCFG */ + GPIO_CFGD_GPIO25INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO25INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO25INCFG_Enum; + +/* ============================================== GPIO CFGD GPIO24INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO24INTD */ + GPIO_CFGD_GPIO24INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGD_GPIO24INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGD_GPIO24INTD_Enum; + +/* ============================================= GPIO CFGD GPIO24OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGD_GPIO24OUTCFG */ + GPIO_CFGD_GPIO24OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGD_GPIO24OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGD_GPIO24OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGD_GPIO24OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGD_GPIO24OUTCFG_Enum; + +/* ============================================= GPIO CFGD GPIO24INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGD_GPIO24INCFG */ + GPIO_CFGD_GPIO24INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGD_GPIO24INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGD_GPIO24INCFG_Enum; + +/* ========================================================= CFGE ========================================================== */ +/* ============================================= GPIO CFGE GPIO39INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO39INTD */ + GPIO_CFGE_GPIO39INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGE_GPIO39INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGE_GPIO39INTD_Enum; + +/* ============================================ GPIO CFGE GPIO39OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO39OUTCFG */ + GPIO_CFGE_GPIO39OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO39OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO39OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO39OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO39OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO39INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO39INCFG */ + GPIO_CFGE_GPIO39INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO39INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO39INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO38INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO38INTD */ + GPIO_CFGE_GPIO38INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO38INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO38INTD_Enum; + +/* ============================================ GPIO CFGE GPIO38OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO38OUTCFG */ + GPIO_CFGE_GPIO38OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO38OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO38OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO38OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO38OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO38INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO38INCFG */ + GPIO_CFGE_GPIO38INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO38INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO38INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO37INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO37INTD */ + GPIO_CFGE_GPIO37INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO37INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO37INTD_Enum; + +/* ============================================ GPIO CFGE GPIO37OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO37OUTCFG */ + GPIO_CFGE_GPIO37OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO37OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO37OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO37OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO37OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO37INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO37INCFG */ + GPIO_CFGE_GPIO37INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO37INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO37INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO36INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO36INTD */ + GPIO_CFGE_GPIO36INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO36INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO36INTD_Enum; + +/* ============================================ GPIO CFGE GPIO36OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO36OUTCFG */ + GPIO_CFGE_GPIO36OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO36OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO36OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO36OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO36OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO36INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO36INCFG */ + GPIO_CFGE_GPIO36INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO36INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO36INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO35INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO35INTD */ + GPIO_CFGE_GPIO35INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO35INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO35INTD_Enum; + +/* ============================================ GPIO CFGE GPIO35OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGE_GPIO35OUTCFG */ + GPIO_CFGE_GPIO35OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO35OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO35OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO35OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO35OUTCFG_Enum; + +/* ============================================ GPIO CFGE GPIO35INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO35INCFG */ + GPIO_CFGE_GPIO35INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO35INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO35INCFG_Enum; + +/* ============================================= GPIO CFGE GPIO34INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO34INTD */ + GPIO_CFGE_GPIO34INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO34INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO34INTD_Enum; + +/* ============================================ GPIO CFGE GPIO34OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO34OUTCFG */ + GPIO_CFGE_GPIO34OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO34OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO34OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO34OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO34OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO34INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO34INCFG */ + GPIO_CFGE_GPIO34INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO34INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO34INCFG_Enum; + +/* ============================================== GPIO CFGE GPIO33INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO33INTD */ + GPIO_CFGE_GPIO33INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO33INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO33INTD_Enum; + +/* ============================================= GPIO CFGE GPIO33OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO33OUTCFG */ + GPIO_CFGE_GPIO33OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO33OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO33OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO33OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO33OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO33INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO33INCFG */ + GPIO_CFGE_GPIO33INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO33INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO33INCFG_Enum; + +/* ============================================== GPIO CFGE GPIO32INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO32INTD */ + GPIO_CFGE_GPIO32INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGE_GPIO32INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGE_GPIO32INTD_Enum; + +/* ============================================= GPIO CFGE GPIO32OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGE_GPIO32OUTCFG */ + GPIO_CFGE_GPIO32OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGE_GPIO32OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGE_GPIO32OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGE_GPIO32OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGE_GPIO32OUTCFG_Enum; + +/* ============================================= GPIO CFGE GPIO32INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGE_GPIO32INCFG */ + GPIO_CFGE_GPIO32INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGE_GPIO32INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGE_GPIO32INCFG_Enum; + +/* ========================================================= CFGF ========================================================== */ +/* ============================================= GPIO CFGF GPIO47INTD [31..31] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO47INTD */ + GPIO_CFGF_GPIO47INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO47INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO47INTD_Enum; + +/* ============================================ GPIO CFGF GPIO47OUTCFG [29..30] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO47OUTCFG */ + GPIO_CFGF_GPIO47OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO47OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO47OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO47OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO47OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO47INCFG [28..28] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO47INCFG */ + GPIO_CFGF_GPIO47INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO47INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO47INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO46INTD [27..27] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO46INTD */ + GPIO_CFGF_GPIO46INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO46INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO46INTD_Enum; + +/* ============================================ GPIO CFGF GPIO46OUTCFG [25..26] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO46OUTCFG */ + GPIO_CFGF_GPIO46OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO46OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO46OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO46OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO46OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO46INCFG [24..24] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO46INCFG */ + GPIO_CFGF_GPIO46INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO46INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO46INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO45INTD [23..23] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO45INTD */ + GPIO_CFGF_GPIO45INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO45INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO45INTD_Enum; + +/* ============================================ GPIO CFGF GPIO45OUTCFG [21..22] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO45OUTCFG */ + GPIO_CFGF_GPIO45OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO45OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO45OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO45OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO45OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO45INCFG [20..20] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO45INCFG */ + GPIO_CFGF_GPIO45INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO45INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO45INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO44INTD [19..19] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO44INTD */ + GPIO_CFGF_GPIO44INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO44INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO44INTD_Enum; + +/* ============================================ GPIO CFGF GPIO44OUTCFG [17..18] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO44OUTCFG */ + GPIO_CFGF_GPIO44OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO44OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO44OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO44OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO44OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO44INCFG [16..16] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO44INCFG */ + GPIO_CFGF_GPIO44INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO44INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO44INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO43INTD [15..15] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO43INTD */ + GPIO_CFGF_GPIO43INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO43INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO43INTD_Enum; + +/* ============================================ GPIO CFGF GPIO43OUTCFG [13..14] ============================================ */ +typedef enum { /*!< GPIO_CFGF_GPIO43OUTCFG */ + GPIO_CFGF_GPIO43OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO43OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO43OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO43OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO43OUTCFG_Enum; + +/* ============================================ GPIO CFGF GPIO43INCFG [12..12] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO43INCFG */ + GPIO_CFGF_GPIO43INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO43INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO43INCFG_Enum; + +/* ============================================= GPIO CFGF GPIO42INTD [11..11] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO42INTD */ + GPIO_CFGF_GPIO42INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGF_GPIO42INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGF_GPIO42INTD_Enum; + +/* ============================================ GPIO CFGF GPIO42OUTCFG [9..10] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO42OUTCFG */ + GPIO_CFGF_GPIO42OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO42OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO42OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO42OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO42OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO42INCFG [8..8] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO42INCFG */ + GPIO_CFGF_GPIO42INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO42INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO42INCFG_Enum; + +/* ============================================== GPIO CFGF GPIO41INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO41INTD */ + GPIO_CFGF_GPIO41INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low */ + GPIO_CFGF_GPIO41INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high */ +} GPIO_CFGF_GPIO41INTD_Enum; + +/* ============================================= GPIO CFGF GPIO41OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO41OUTCFG */ + GPIO_CFGF_GPIO41OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO41OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO41OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO41OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO41OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO41INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO41INCFG */ + GPIO_CFGF_GPIO41INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO41INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO41INCFG_Enum; + +/* ============================================== GPIO CFGF GPIO40INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO40INTD */ + GPIO_CFGF_GPIO40INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */ + GPIO_CFGF_GPIO40INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high + to low GPIO transition */ +} GPIO_CFGF_GPIO40INTD_Enum; + +/* ============================================= GPIO CFGF GPIO40OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGF_GPIO40OUTCFG */ + GPIO_CFGF_GPIO40OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGF_GPIO40OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGF_GPIO40OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGF_GPIO40OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGF_GPIO40OUTCFG_Enum; + +/* ============================================= GPIO CFGF GPIO40INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGF_GPIO40INCFG */ + GPIO_CFGF_GPIO40INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGF_GPIO40INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGF_GPIO40INCFG_Enum; + +/* ========================================================= CFGG ========================================================== */ +/* ============================================== GPIO CFGG GPIO49INTD [7..7] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO49INTD */ + GPIO_CFGG_GPIO49INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGG_GPIO49INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGG_GPIO49INTD_Enum; + +/* ============================================= GPIO CFGG GPIO49OUTCFG [5..6] ============================================= */ +typedef enum { /*!< GPIO_CFGG_GPIO49OUTCFG */ + GPIO_CFGG_GPIO49OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGG_GPIO49OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGG_GPIO49OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGG_GPIO49OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGG_GPIO49OUTCFG_Enum; + +/* ============================================= GPIO CFGG GPIO49INCFG [4..4] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO49INCFG */ + GPIO_CFGG_GPIO49INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGG_GPIO49INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGG_GPIO49INCFG_Enum; + +/* ============================================== GPIO CFGG GPIO48INTD [3..3] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO48INTD */ + GPIO_CFGG_GPIO48INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */ + GPIO_CFGG_GPIO48INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */ +} GPIO_CFGG_GPIO48INTD_Enum; + +/* ============================================= GPIO CFGG GPIO48OUTCFG [1..2] ============================================= */ +typedef enum { /*!< GPIO_CFGG_GPIO48OUTCFG */ + GPIO_CFGG_GPIO48OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */ + GPIO_CFGG_GPIO48OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */ + GPIO_CFGG_GPIO48OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */ + GPIO_CFGG_GPIO48OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */ +} GPIO_CFGG_GPIO48OUTCFG_Enum; + +/* ============================================= GPIO CFGG GPIO48INCFG [0..0] ============================================== */ +typedef enum { /*!< GPIO_CFGG_GPIO48INCFG */ + GPIO_CFGG_GPIO48INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ + GPIO_CFGG_GPIO48INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ +} GPIO_CFGG_GPIO48INCFG_Enum; + +/* ======================================================== PADKEY ========================================================= */ +/* ============================================== GPIO PADKEY PADKEY [0..31] =============================================== */ +typedef enum { /*!< GPIO_PADKEY_PADKEY */ + GPIO_PADKEY_PADKEY_Key = 115, /*!< Key : Key */ +} GPIO_PADKEY_PADKEY_Enum; + +/* ========================================================== RDA ========================================================== */ +/* ========================================================== RDB ========================================================== */ +/* ========================================================== WTA ========================================================== */ +/* ========================================================== WTB ========================================================== */ +/* ========================================================= WTSA ========================================================== */ +/* ========================================================= WTSB ========================================================== */ +/* ========================================================= WTCA ========================================================== */ +/* ========================================================= WTCB ========================================================== */ +/* ========================================================== ENA ========================================================== */ +/* ========================================================== ENB ========================================================== */ +/* ========================================================= ENSA ========================================================== */ +/* ========================================================= ENSB ========================================================== */ +/* ========================================================= ENCA ========================================================== */ +/* ========================================================= ENCB ========================================================== */ +/* ======================================================== STMRCAP ======================================================== */ +/* ============================================= GPIO STMRCAP STPOL3 [30..30] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL3 */ + GPIO_STMRCAP_STPOL3_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL3_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL3_Enum; + +/* ============================================= GPIO STMRCAP STPOL2 [22..22] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL2 */ + GPIO_STMRCAP_STPOL2_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL2_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL2_Enum; + +/* ============================================= GPIO STMRCAP STPOL1 [14..14] ============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL1 */ + GPIO_STMRCAP_STPOL1_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL1_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL1_Enum; + +/* ============================================== GPIO STMRCAP STPOL0 [6..6] =============================================== */ +typedef enum { /*!< GPIO_STMRCAP_STPOL0 */ + GPIO_STMRCAP_STPOL0_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ + GPIO_STMRCAP_STPOL0_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ +} GPIO_STMRCAP_STPOL0_Enum; + +/* ======================================================== IOM0IRQ ======================================================== */ +/* ======================================================== IOM1IRQ ======================================================== */ +/* ======================================================== IOM2IRQ ======================================================== */ +/* ======================================================== IOM3IRQ ======================================================== */ +/* ======================================================== IOM4IRQ ======================================================== */ +/* ======================================================== IOM5IRQ ======================================================== */ +/* ======================================================= BLEIFIRQ ======================================================== */ +/* ======================================================== GPIOOBS ======================================================== */ +/* ====================================================== ALTPADCFGA ======================================================= */ +/* =========================================== GPIO ALTPADCFGA PAD3_SR [28..28] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD3_SR */ + GPIO_ALTPADCFGA_PAD3_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD3_SR_Enum; + +/* =========================================== GPIO ALTPADCFGA PAD2_SR [20..20] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD2_SR */ + GPIO_ALTPADCFGA_PAD2_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD2_SR_Enum; + +/* =========================================== GPIO ALTPADCFGA PAD1_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD1_SR */ + GPIO_ALTPADCFGA_PAD1_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD1_SR_Enum; + +/* ============================================ GPIO ALTPADCFGA PAD0_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGA_PAD0_SR */ + GPIO_ALTPADCFGA_PAD0_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGA_PAD0_SR_Enum; + +/* ====================================================== ALTPADCFGB ======================================================= */ +/* =========================================== GPIO ALTPADCFGB PAD7_SR [28..28] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD7_SR */ + GPIO_ALTPADCFGB_PAD7_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD7_SR_Enum; + +/* =========================================== GPIO ALTPADCFGB PAD6_SR [20..20] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD6_SR */ + GPIO_ALTPADCFGB_PAD6_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD6_SR_Enum; + +/* =========================================== GPIO ALTPADCFGB PAD5_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD5_SR */ + GPIO_ALTPADCFGB_PAD5_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD5_SR_Enum; + +/* ============================================ GPIO ALTPADCFGB PAD4_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGB_PAD4_SR */ + GPIO_ALTPADCFGB_PAD4_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGB_PAD4_SR_Enum; + +/* ====================================================== ALTPADCFGC ======================================================= */ +/* =========================================== GPIO ALTPADCFGC PAD11_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD11_SR */ + GPIO_ALTPADCFGC_PAD11_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD11_SR_Enum; + +/* =========================================== GPIO ALTPADCFGC PAD10_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD10_SR */ + GPIO_ALTPADCFGC_PAD10_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD10_SR_Enum; + +/* =========================================== GPIO ALTPADCFGC PAD9_SR [12..12] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD9_SR */ + GPIO_ALTPADCFGC_PAD9_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD9_SR_Enum; + +/* ============================================ GPIO ALTPADCFGC PAD8_SR [4..4] ============================================= */ +typedef enum { /*!< GPIO_ALTPADCFGC_PAD8_SR */ + GPIO_ALTPADCFGC_PAD8_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGC_PAD8_SR_Enum; + +/* ====================================================== ALTPADCFGD ======================================================= */ +/* =========================================== GPIO ALTPADCFGD PAD15_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD15_SR */ + GPIO_ALTPADCFGD_PAD15_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD15_SR_Enum; + +/* =========================================== GPIO ALTPADCFGD PAD14_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD14_SR */ + GPIO_ALTPADCFGD_PAD14_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD14_SR_Enum; + +/* =========================================== GPIO ALTPADCFGD PAD13_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD13_SR */ + GPIO_ALTPADCFGD_PAD13_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD13_SR_Enum; + +/* ============================================ GPIO ALTPADCFGD PAD12_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGD_PAD12_SR */ + GPIO_ALTPADCFGD_PAD12_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGD_PAD12_SR_Enum; + +/* ====================================================== ALTPADCFGE ======================================================= */ +/* =========================================== GPIO ALTPADCFGE PAD19_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD19_SR */ + GPIO_ALTPADCFGE_PAD19_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD19_SR_Enum; + +/* =========================================== GPIO ALTPADCFGE PAD18_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD18_SR */ + GPIO_ALTPADCFGE_PAD18_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD18_SR_Enum; + +/* =========================================== GPIO ALTPADCFGE PAD17_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD17_SR */ + GPIO_ALTPADCFGE_PAD17_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD17_SR_Enum; + +/* ============================================ GPIO ALTPADCFGE PAD16_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGE_PAD16_SR */ + GPIO_ALTPADCFGE_PAD16_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGE_PAD16_SR_Enum; + +/* ====================================================== ALTPADCFGF ======================================================= */ +/* =========================================== GPIO ALTPADCFGF PAD23_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD23_SR */ + GPIO_ALTPADCFGF_PAD23_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD23_SR_Enum; + +/* =========================================== GPIO ALTPADCFGF PAD22_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD22_SR */ + GPIO_ALTPADCFGF_PAD22_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD22_SR_Enum; + +/* =========================================== GPIO ALTPADCFGF PAD21_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD21_SR */ + GPIO_ALTPADCFGF_PAD21_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD21_SR_Enum; + +/* ============================================ GPIO ALTPADCFGF PAD20_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGF_PAD20_SR */ + GPIO_ALTPADCFGF_PAD20_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGF_PAD20_SR_Enum; + +/* ====================================================== ALTPADCFGG ======================================================= */ +/* =========================================== GPIO ALTPADCFGG PAD27_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD27_SR */ + GPIO_ALTPADCFGG_PAD27_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD27_SR_Enum; + +/* =========================================== GPIO ALTPADCFGG PAD26_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD26_SR */ + GPIO_ALTPADCFGG_PAD26_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD26_SR_Enum; + +/* =========================================== GPIO ALTPADCFGG PAD25_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD25_SR */ + GPIO_ALTPADCFGG_PAD25_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD25_SR_Enum; + +/* ============================================ GPIO ALTPADCFGG PAD24_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGG_PAD24_SR */ + GPIO_ALTPADCFGG_PAD24_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGG_PAD24_SR_Enum; + +/* ====================================================== ALTPADCFGH ======================================================= */ +/* =========================================== GPIO ALTPADCFGH PAD31_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD31_SR */ + GPIO_ALTPADCFGH_PAD31_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD31_SR_Enum; + +/* =========================================== GPIO ALTPADCFGH PAD30_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD30_SR */ + GPIO_ALTPADCFGH_PAD30_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD30_SR_Enum; + +/* =========================================== GPIO ALTPADCFGH PAD29_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD29_SR */ + GPIO_ALTPADCFGH_PAD29_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD29_SR_Enum; + +/* ============================================ GPIO ALTPADCFGH PAD28_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGH_PAD28_SR */ + GPIO_ALTPADCFGH_PAD28_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGH_PAD28_SR_Enum; + +/* ====================================================== ALTPADCFGI ======================================================= */ +/* =========================================== GPIO ALTPADCFGI PAD35_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD35_SR */ + GPIO_ALTPADCFGI_PAD35_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD35_SR_Enum; + +/* =========================================== GPIO ALTPADCFGI PAD34_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD34_SR */ + GPIO_ALTPADCFGI_PAD34_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD34_SR_Enum; + +/* =========================================== GPIO ALTPADCFGI PAD33_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD33_SR */ + GPIO_ALTPADCFGI_PAD33_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD33_SR_Enum; + +/* ============================================ GPIO ALTPADCFGI PAD32_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGI_PAD32_SR */ + GPIO_ALTPADCFGI_PAD32_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGI_PAD32_SR_Enum; + +/* ====================================================== ALTPADCFGJ ======================================================= */ +/* =========================================== GPIO ALTPADCFGJ PAD39_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD39_SR */ + GPIO_ALTPADCFGJ_PAD39_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD39_SR_Enum; + +/* =========================================== GPIO ALTPADCFGJ PAD38_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD38_SR */ + GPIO_ALTPADCFGJ_PAD38_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD38_SR_Enum; + +/* =========================================== GPIO ALTPADCFGJ PAD37_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD37_SR */ + GPIO_ALTPADCFGJ_PAD37_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD37_SR_Enum; + +/* ============================================ GPIO ALTPADCFGJ PAD36_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGJ_PAD36_SR */ + GPIO_ALTPADCFGJ_PAD36_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGJ_PAD36_SR_Enum; + +/* ====================================================== ALTPADCFGK ======================================================= */ +/* =========================================== GPIO ALTPADCFGK PAD43_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD43_SR */ + GPIO_ALTPADCFGK_PAD43_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD43_SR_Enum; + +/* =========================================== GPIO ALTPADCFGK PAD42_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD42_SR */ + GPIO_ALTPADCFGK_PAD42_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD42_SR_Enum; + +/* =========================================== GPIO ALTPADCFGK PAD41_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD41_SR */ + GPIO_ALTPADCFGK_PAD41_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD41_SR_Enum; + +/* ============================================ GPIO ALTPADCFGK PAD40_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGK_PAD40_SR */ + GPIO_ALTPADCFGK_PAD40_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGK_PAD40_SR_Enum; + +/* ====================================================== ALTPADCFGL ======================================================= */ +/* =========================================== GPIO ALTPADCFGL PAD47_SR [28..28] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD47_SR */ + GPIO_ALTPADCFGL_PAD47_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD47_SR_Enum; + +/* =========================================== GPIO ALTPADCFGL PAD46_SR [20..20] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD46_SR */ + GPIO_ALTPADCFGL_PAD46_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD46_SR_Enum; + +/* =========================================== GPIO ALTPADCFGL PAD45_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD45_SR */ + GPIO_ALTPADCFGL_PAD45_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD45_SR_Enum; + +/* ============================================ GPIO ALTPADCFGL PAD44_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGL_PAD44_SR */ + GPIO_ALTPADCFGL_PAD44_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGL_PAD44_SR_Enum; + +/* ====================================================== ALTPADCFGM ======================================================= */ +/* =========================================== GPIO ALTPADCFGM PAD49_SR [12..12] =========================================== */ +typedef enum { /*!< GPIO_ALTPADCFGM_PAD49_SR */ + GPIO_ALTPADCFGM_PAD49_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGM_PAD49_SR_Enum; + +/* ============================================ GPIO ALTPADCFGM PAD48_SR [4..4] ============================================ */ +typedef enum { /*!< GPIO_ALTPADCFGM_PAD48_SR */ + GPIO_ALTPADCFGM_PAD48_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ +} GPIO_ALTPADCFGM_PAD48_SR_Enum; + +/* ========================================================= SCDET ========================================================= */ +/* ======================================================== CTENCFG ======================================================== */ +/* ============================================== GPIO CTENCFG EN31 [31..31] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN31 */ + GPIO_CTENCFG_EN31_DIS = 1, /*!< DIS : Disable CT31 for output */ + GPIO_CTENCFG_EN31_EN = 0, /*!< EN : Enable CT31 for output */ +} GPIO_CTENCFG_EN31_Enum; + +/* ============================================== GPIO CTENCFG EN30 [30..30] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN30 */ + GPIO_CTENCFG_EN30_DIS = 1, /*!< DIS : Disable CT30 for output */ + GPIO_CTENCFG_EN30_EN = 0, /*!< EN : Enable CT30 for output */ +} GPIO_CTENCFG_EN30_Enum; + +/* ============================================== GPIO CTENCFG EN29 [29..29] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN29 */ + GPIO_CTENCFG_EN29_DIS = 1, /*!< DIS : Disable CT29 for output */ + GPIO_CTENCFG_EN29_EN = 0, /*!< EN : Enable CT29 for output */ +} GPIO_CTENCFG_EN29_Enum; + +/* ============================================== GPIO CTENCFG EN28 [28..28] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN28 */ + GPIO_CTENCFG_EN28_DIS = 1, /*!< DIS : Disable CT28 for output */ + GPIO_CTENCFG_EN28_EN = 0, /*!< EN : Enable CT28 for output */ +} GPIO_CTENCFG_EN28_Enum; + +/* ============================================== GPIO CTENCFG EN27 [27..27] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN27 */ + GPIO_CTENCFG_EN27_DIS = 1, /*!< DIS : Disable CT27 for output */ + GPIO_CTENCFG_EN27_EN = 0, /*!< EN : Enable CT27 for output */ +} GPIO_CTENCFG_EN27_Enum; + +/* ============================================== GPIO CTENCFG EN26 [26..26] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN26 */ + GPIO_CTENCFG_EN26_DIS = 1, /*!< DIS : Disable CT26 for output */ + GPIO_CTENCFG_EN26_EN = 0, /*!< EN : Enable CT26 for output */ +} GPIO_CTENCFG_EN26_Enum; + +/* ============================================== GPIO CTENCFG EN25 [25..25] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN25 */ + GPIO_CTENCFG_EN25_DIS = 1, /*!< DIS : Disable CT25 for output */ + GPIO_CTENCFG_EN25_EN = 0, /*!< EN : Enable CT25 for output */ +} GPIO_CTENCFG_EN25_Enum; + +/* ============================================== GPIO CTENCFG EN24 [24..24] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN24 */ + GPIO_CTENCFG_EN24_DIS = 1, /*!< DIS : Disable CT24 for output */ + GPIO_CTENCFG_EN24_EN = 0, /*!< EN : Enable CT24 for output */ +} GPIO_CTENCFG_EN24_Enum; + +/* ============================================== GPIO CTENCFG EN23 [23..23] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN23 */ + GPIO_CTENCFG_EN23_DIS = 1, /*!< DIS : Disable CT23 for output */ + GPIO_CTENCFG_EN23_EN = 0, /*!< EN : Enable CT23 for output */ +} GPIO_CTENCFG_EN23_Enum; + +/* ============================================== GPIO CTENCFG EN22 [22..22] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN22 */ + GPIO_CTENCFG_EN22_DIS = 1, /*!< DIS : Disable CT22 for output */ + GPIO_CTENCFG_EN22_EN = 0, /*!< EN : Enable CT22 for output */ +} GPIO_CTENCFG_EN22_Enum; + +/* ============================================== GPIO CTENCFG EN21 [21..21] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN21 */ + GPIO_CTENCFG_EN21_DIS = 1, /*!< DIS : Disable CT21 for output */ + GPIO_CTENCFG_EN21_EN = 0, /*!< EN : Enable CT21 for output */ +} GPIO_CTENCFG_EN21_Enum; + +/* ============================================== GPIO CTENCFG EN20 [20..20] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN20 */ + GPIO_CTENCFG_EN20_DIS = 1, /*!< DIS : Disable CT20 for output */ + GPIO_CTENCFG_EN20_EN = 0, /*!< EN : Enable CT20 for output */ +} GPIO_CTENCFG_EN20_Enum; + +/* ============================================== GPIO CTENCFG EN19 [19..19] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN19 */ + GPIO_CTENCFG_EN19_DIS = 1, /*!< DIS : Disable CT19 for output */ + GPIO_CTENCFG_EN19_EN = 0, /*!< EN : Enable CT19 for output */ +} GPIO_CTENCFG_EN19_Enum; + +/* ============================================== GPIO CTENCFG EN18 [18..18] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN18 */ + GPIO_CTENCFG_EN18_DIS = 1, /*!< DIS : Disable CT18 for output */ + GPIO_CTENCFG_EN18_EN = 0, /*!< EN : Enable CT18 for output */ +} GPIO_CTENCFG_EN18_Enum; + +/* ============================================== GPIO CTENCFG EN17 [17..17] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN17 */ + GPIO_CTENCFG_EN17_DIS = 1, /*!< DIS : Disable CT17 for output */ + GPIO_CTENCFG_EN17_EN = 0, /*!< EN : Enable CT17 for output */ +} GPIO_CTENCFG_EN17_Enum; + +/* ============================================== GPIO CTENCFG EN16 [16..16] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN16 */ + GPIO_CTENCFG_EN16_DIS = 1, /*!< DIS : Disable CT16 for output */ + GPIO_CTENCFG_EN16_EN = 0, /*!< EN : Enable CT16 for output */ +} GPIO_CTENCFG_EN16_Enum; + +/* ============================================== GPIO CTENCFG EN15 [15..15] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN15 */ + GPIO_CTENCFG_EN15_DIS = 1, /*!< DIS : Disable CT15 for output */ + GPIO_CTENCFG_EN15_EN = 0, /*!< EN : Enable CT15 for output */ +} GPIO_CTENCFG_EN15_Enum; + +/* ============================================== GPIO CTENCFG EN14 [14..14] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN14 */ + GPIO_CTENCFG_EN14_DIS = 1, /*!< DIS : Disable CT14 for output */ + GPIO_CTENCFG_EN14_EN = 0, /*!< EN : Enable CT14 for output */ +} GPIO_CTENCFG_EN14_Enum; + +/* ============================================== GPIO CTENCFG EN13 [13..13] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN13 */ + GPIO_CTENCFG_EN13_DIS = 1, /*!< DIS : Disable CT13 for output */ + GPIO_CTENCFG_EN13_EN = 0, /*!< EN : Enable CT13 for output */ +} GPIO_CTENCFG_EN13_Enum; + +/* ============================================== GPIO CTENCFG EN12 [12..12] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN12 */ + GPIO_CTENCFG_EN12_DIS = 1, /*!< DIS : Disable CT12 for output */ + GPIO_CTENCFG_EN12_EN = 0, /*!< EN : Enable CT12 for output */ +} GPIO_CTENCFG_EN12_Enum; + +/* ============================================== GPIO CTENCFG EN11 [11..11] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN11 */ + GPIO_CTENCFG_EN11_DIS = 1, /*!< DIS : Disable CT11 for output */ + GPIO_CTENCFG_EN11_EN = 0, /*!< EN : Enable CT11 for output */ +} GPIO_CTENCFG_EN11_Enum; + +/* ============================================== GPIO CTENCFG EN10 [10..10] =============================================== */ +typedef enum { /*!< GPIO_CTENCFG_EN10 */ + GPIO_CTENCFG_EN10_DIS = 1, /*!< DIS : Disable CT10 for output */ + GPIO_CTENCFG_EN10_EN = 0, /*!< EN : Enable CT10 for output */ +} GPIO_CTENCFG_EN10_Enum; + +/* ================================================ GPIO CTENCFG EN9 [9..9] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN9 */ + GPIO_CTENCFG_EN9_DIS = 0, /*!< DIS : Disable CT9 for output */ +} GPIO_CTENCFG_EN9_Enum; + +/* ================================================ GPIO CTENCFG EN8 [8..8] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN8 */ + GPIO_CTENCFG_EN8_DIS = 1, /*!< DIS : Disable CT8 for output */ + GPIO_CTENCFG_EN8_EN = 0, /*!< EN : Enable CT8 for output */ +} GPIO_CTENCFG_EN8_Enum; + +/* ================================================ GPIO CTENCFG EN7 [7..7] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN7 */ + GPIO_CTENCFG_EN7_DIS = 1, /*!< DIS : Disable CT7 for output */ + GPIO_CTENCFG_EN7_EN = 0, /*!< EN : Enable CT7 for output */ +} GPIO_CTENCFG_EN7_Enum; + +/* ================================================ GPIO CTENCFG EN6 [6..6] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN6 */ + GPIO_CTENCFG_EN6_DIS = 1, /*!< DIS : Disable CT6 for output */ + GPIO_CTENCFG_EN6_EN = 0, /*!< EN : Enable CT6 for output */ +} GPIO_CTENCFG_EN6_Enum; + +/* ================================================ GPIO CTENCFG EN5 [5..5] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN5 */ + GPIO_CTENCFG_EN5_DIS = 1, /*!< DIS : Disable CT5 for output */ + GPIO_CTENCFG_EN5_EN = 0, /*!< EN : Enable CT5 for output */ +} GPIO_CTENCFG_EN5_Enum; + +/* ================================================ GPIO CTENCFG EN4 [4..4] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN4 */ + GPIO_CTENCFG_EN4_DIS = 1, /*!< DIS : Disable CT4 for output */ + GPIO_CTENCFG_EN4_EN = 0, /*!< EN : Enable CT4 for output */ +} GPIO_CTENCFG_EN4_Enum; + +/* ================================================ GPIO CTENCFG EN3 [3..3] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN3 */ + GPIO_CTENCFG_EN3_DIS = 1, /*!< DIS : Disable CT3 for output */ + GPIO_CTENCFG_EN3_EN = 0, /*!< EN : Enable CT3 for output */ +} GPIO_CTENCFG_EN3_Enum; + +/* ================================================ GPIO CTENCFG EN2 [2..2] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN2 */ + GPIO_CTENCFG_EN2_DIS = 1, /*!< DIS : Disable CT2 for output */ + GPIO_CTENCFG_EN2_EN = 0, /*!< EN : Enable CT2 for output */ +} GPIO_CTENCFG_EN2_Enum; + +/* ================================================ GPIO CTENCFG EN1 [1..1] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN1 */ + GPIO_CTENCFG_EN1_DIS = 1, /*!< DIS : Disable CT1 for output */ + GPIO_CTENCFG_EN1_EN = 0, /*!< EN : Enable CT1 for output */ +} GPIO_CTENCFG_EN1_Enum; + +/* ================================================ GPIO CTENCFG EN0 [0..0] ================================================ */ +typedef enum { /*!< GPIO_CTENCFG_EN0 */ + GPIO_CTENCFG_EN0_DIS = 1, /*!< DIS : Disable CT0 for output */ + GPIO_CTENCFG_EN0_EN = 0, /*!< EN : Enable CT0 for output */ +} GPIO_CTENCFG_EN0_Enum; + +/* ======================================================== INT0EN ========================================================= */ +/* ======================================================= INT0STAT ======================================================== */ +/* ======================================================== INT0CLR ======================================================== */ +/* ======================================================== INT0SET ======================================================== */ +/* ======================================================== INT1EN ========================================================= */ +/* ======================================================= INT1STAT ======================================================== */ +/* ======================================================== INT1CLR ======================================================== */ +/* ======================================================== INT1SET ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ IOM0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FIFO ========================================================== */ +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ======================================================== FIFOPOP ======================================================== */ +/* ======================================================= FIFOPUSH ======================================================== */ +/* ======================================================= FIFOCTRL ======================================================== */ +/* ======================================================== FIFOLOC ======================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================== CLKCFG ========================================================= */ +/* ============================================== IOM0 CLKCFG DIVEN [12..12] =============================================== */ +typedef enum { /*!< IOM0_CLKCFG_DIVEN */ + IOM0_CLKCFG_DIVEN_DIS = 0, /*!< DIS : Disable TOTPER division. */ + IOM0_CLKCFG_DIVEN_EN = 1, /*!< EN : Enable TOTPER division. */ +} IOM0_CLKCFG_DIVEN_Enum; + +/* =============================================== IOM0 CLKCFG DIV3 [11..11] =============================================== */ +typedef enum { /*!< IOM0_CLKCFG_DIV3 */ + IOM0_CLKCFG_DIV3_DIS = 0, /*!< DIS : Select divide by 1. */ + IOM0_CLKCFG_DIV3_EN = 1, /*!< EN : Select divide by 3. */ +} IOM0_CLKCFG_DIV3_Enum; + +/* =============================================== IOM0 CLKCFG FSEL [8..10] ================================================ */ +typedef enum { /*!< IOM0_CLKCFG_FSEL */ + IOM0_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should + be used whenever the IOM is not active. */ + IOM0_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */ + IOM0_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */ +} IOM0_CLKCFG_FSEL_Enum; + +/* ====================================================== SUBMODCTRL ======================================================= */ +/* =========================================== IOM0 SUBMODCTRL SMOD1TYPE [5..7] ============================================ */ +typedef enum { /*!< IOM0_SUBMODCTRL_SMOD1TYPE */ + IOM0_SUBMODCTRL_SMOD1TYPE_MSPI = 0, /*!< MSPI : SPI Master submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : MI2C submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */ + IOM0_SUBMODCTRL_SMOD1TYPE_NA = 7, /*!< NA : NOT INSTALLED */ +} IOM0_SUBMODCTRL_SMOD1TYPE_Enum; + +/* =========================================== IOM0 SUBMODCTRL SMOD0TYPE [1..3] ============================================ */ +typedef enum { /*!< IOM0_SUBMODCTRL_SMOD0TYPE */ + IOM0_SUBMODCTRL_SMOD0TYPE_SPI_MASTER = 0, /*!< SPI_MASTER : MSPI submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : I2C Master submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */ + IOM0_SUBMODCTRL_SMOD0TYPE_NA = 7, /*!< NA : NOT INSTALLED */ +} IOM0_SUBMODCTRL_SMOD0TYPE_Enum; + +/* ========================================================== CMD ========================================================== */ +/* ================================================== IOM0 CMD CMD [0..4] ================================================== */ +typedef enum { /*!< IOM0_CMD_CMD */ + IOM0_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified + in the OFFSETCNT field */ + IOM0_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in + the OFFSETCNT field */ + IOM0_CMD_CMD_TMW = 3, /*!< TMW : SPI only. Test mode to do constant write operations. Useful + for debug and power measurements. Will continually send + data in OFFSET field */ + IOM0_CMD_CMD_TMR = 4, /*!< TMR : SPI Only. Test mode to do constant read operations. Useful + for debug and power measurements. Will continually read + data from external input */ +} IOM0_CMD_CMD_Enum; + +/* ========================================================== DCX ========================================================== */ +/* ================================================= IOM0 DCX DCXEN [4..4] ================================================= */ +typedef enum { /*!< IOM0_DCX_DCXEN */ + IOM0_DCX_DCXEN_EN = 1, /*!< EN : Enable DCX. */ + IOM0_DCX_DCXEN_DIS = 0, /*!< DIS : Disable DCX. */ +} IOM0_DCX_DCXEN_Enum; + +/* ======================================================= OFFSETHI ======================================================== */ +/* ======================================================== CMDSTAT ======================================================== */ +/* ============================================== IOM0 CMDSTAT CMDSTAT [5..7] ============================================== */ +typedef enum { /*!< IOM0_CMDSTAT_CMDSTAT */ + IOM0_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */ + IOM0_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */ + IOM0_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */ + IOM0_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */ +} IOM0_CMDSTAT_CMDSTAT_Enum; + +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* ============================================== IOM0 DMACFG DPWROFF [9..9] =============================================== */ +typedef enum { /*!< IOM0_DMACFG_DPWROFF */ + IOM0_DMACFG_DPWROFF_DIS = 0, /*!< DIS : Power off disabled */ + IOM0_DMACFG_DPWROFF_EN = 1, /*!< EN : Power off enabled */ +} IOM0_DMACFG_DPWROFF_Enum; + +/* =============================================== IOM0 DMACFG DMAPRI [8..8] =============================================== */ +typedef enum { /*!< IOM0_DMACFG_DMAPRI */ + IOM0_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + IOM0_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} IOM0_DMACFG_DMAPRI_Enum; + +/* =============================================== IOM0 DMACFG DMADIR [1..1] =============================================== */ +typedef enum { /*!< IOM0_DMACFG_DMADIR */ + IOM0_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when + doing IOM read operations, ie reading data from external + devices. */ + IOM0_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing + IOM write operations, ie writing data to external devices. */ +} IOM0_DMACFG_DMADIR_Enum; + +/* =============================================== IOM0 DMACFG DMAEN [0..0] ================================================ */ +typedef enum { /*!< IOM0_DMACFG_DMAEN */ + IOM0_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + IOM0_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} IOM0_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ +/* ========================================================= CQCFG ========================================================= */ +/* ================================================ IOM0 CQCFG CQPRI [1..1] ================================================ */ +typedef enum { /*!< IOM0_CQCFG_CQPRI */ + IOM0_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + IOM0_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} IOM0_CQCFG_CQPRI_Enum; + +/* ================================================ IOM0 CQCFG CQEN [0..0] ================================================= */ +typedef enum { /*!< IOM0_CQCFG_CQEN */ + IOM0_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ + IOM0_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ +} IOM0_CQCFG_CQEN_Enum; + +/* ======================================================== CQADDR ========================================================= */ +/* ======================================================== CQSTAT ========================================================= */ +/* ======================================================== CQFLAGS ======================================================== */ +/* ====================================================== CQSETCLEAR ======================================================= */ +/* ======================================================= CQPAUSEEN ======================================================= */ +/* ============================================= IOM0 CQPAUSEEN CQPEN [0..15] ============================================== */ +typedef enum { /*!< IOM0_CQPAUSEEN_CQPEN */ + IOM0_CQPAUSEEN_CQPEN_IDXEQ = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches + the last index */ + IOM0_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with + SWFLAG4 is '1' */ + IOM0_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with + SWFLAG3 is '1' */ + IOM0_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed + with SWFLAG2 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed + with SWFLAG1 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed + with SWFLAG0 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed + with SWFLAG1 is '1' */ + IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed + with SWFLAG0 is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7 + is '1'. */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1 + is '1' */ + IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0 = 1, /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0 + is '1' */ +} IOM0_CQPAUSEEN_CQPEN_Enum; + +/* ======================================================= CQCURIDX ======================================================== */ +/* ======================================================= CQENDIDX ======================================================== */ +/* ======================================================== STATUS ========================================================= */ +/* =============================================== IOM0 STATUS IDLEST [2..2] =============================================== */ +typedef enum { /*!< IOM0_STATUS_IDLEST */ + IOM0_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */ +} IOM0_STATUS_IDLEST_Enum; + +/* =============================================== IOM0 STATUS CMDACT [1..1] =============================================== */ +typedef enum { /*!< IOM0_STATUS_CMDACT */ + IOM0_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module + has an active command and is processing this. De-asserted + when the command is completed. */ +} IOM0_STATUS_CMDACT_Enum; + +/* ================================================ IOM0 STATUS ERR [0..0] ================================================= */ +typedef enum { /*!< IOM0_STATUS_ERR */ + IOM0_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */ +} IOM0_STATUS_ERR_Enum; + +/* ======================================================== MSPICFG ======================================================== */ +/* ============================================= IOM0 MSPICFG SPILSB [23..23] ============================================== */ +typedef enum { /*!< IOM0_MSPICFG_SPILSB */ + IOM0_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */ + IOM0_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */ +} IOM0_MSPICFG_SPILSB_Enum; + +/* ============================================= IOM0 MSPICFG RDFCPOL [22..22] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_RDFCPOL */ + IOM0_MSPICFG_RDFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high creates flow control. */ + IOM0_MSPICFG_RDFCPOL_LOW = 1, /*!< LOW : Flow control signal low creates flow control. */ +} IOM0_MSPICFG_RDFCPOL_Enum; + +/* ============================================= IOM0 MSPICFG WTFCPOL [21..21] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_WTFCPOL */ + IOM0_MSPICFG_WTFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high(1) creates flow control and + byte transfers will stop until the flow control signal + goes low. */ + IOM0_MSPICFG_WTFCPOL_LOW = 1, /*!< LOW : Flow control signal low(0) creates flow control and byte + transfers will stop until the flow control signal goes + high(1). */ +} IOM0_MSPICFG_WTFCPOL_Enum; + +/* ============================================= IOM0 MSPICFG WTFCIRQ [20..20] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_WTFCIRQ */ + IOM0_MSPICFG_WTFCIRQ_MISO = 0, /*!< MISO : MISO is used as the write mode flow control signal. */ + IOM0_MSPICFG_WTFCIRQ_IRQ = 1, /*!< IRQ : IRQ is used as the write mode flow control signal. */ +} IOM0_MSPICFG_WTFCIRQ_Enum; + +/* ============================================= IOM0 MSPICFG MOSIINV [18..18] ============================================= */ +typedef enum { /*!< IOM0_MSPICFG_MOSIINV */ + IOM0_MSPICFG_MOSIINV_NORMAL = 0, /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode. */ + IOM0_MSPICFG_MOSIINV_INVERT = 1, /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode. */ +} IOM0_MSPICFG_MOSIINV_Enum; + +/* ============================================== IOM0 MSPICFG RDFC [17..17] =============================================== */ +typedef enum { /*!< IOM0_MSPICFG_RDFC */ + IOM0_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */ + IOM0_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */ +} IOM0_MSPICFG_RDFC_Enum; + +/* ============================================== IOM0 MSPICFG WTFC [16..16] =============================================== */ +typedef enum { /*!< IOM0_MSPICFG_WTFC */ + IOM0_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */ + IOM0_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */ +} IOM0_MSPICFG_WTFC_Enum; + +/* =============================================== IOM0 MSPICFG SPHA [1..1] ================================================ */ +typedef enum { /*!< IOM0_MSPICFG_SPHA */ + IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge. */ + IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock + edge. */ +} IOM0_MSPICFG_SPHA_Enum; + +/* =============================================== IOM0 MSPICFG SPOL [0..0] ================================================ */ +typedef enum { /*!< IOM0_MSPICFG_SPOL */ + IOM0_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The base value of the clock is 0. */ + IOM0_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The base value of the clock is 1. */ +} IOM0_MSPICFG_SPOL_Enum; + +/* ======================================================== MI2CCFG ======================================================== */ +/* =============================================== IOM0 MI2CCFG ARBEN [2..2] =============================================== */ +typedef enum { /*!< IOM0_MI2CCFG_ARBEN */ + IOM0_MI2CCFG_ARBEN_ARBEN = 1, /*!< ARBEN : Enable multi-master bus arbitration support for this + i2c master */ + IOM0_MI2CCFG_ARBEN_ARBDIS = 0, /*!< ARBDIS : Disable multi-master bus arbitration support for this + i2c master */ +} IOM0_MI2CCFG_ARBEN_Enum; + +/* ============================================== IOM0 MI2CCFG I2CLSB [1..1] =============================================== */ +typedef enum { /*!< IOM0_MI2CCFG_I2CLSB */ + IOM0_MI2CCFG_I2CLSB_MSBFIRST = 0, /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read + from the bus */ + IOM0_MI2CCFG_I2CLSB_LSBFIRST = 1, /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read + from the bus */ +} IOM0_MI2CCFG_I2CLSB_Enum; + +/* ============================================== IOM0 MI2CCFG ADDRSZ [0..0] =============================================== */ +typedef enum { /*!< IOM0_MI2CCFG_ADDRSZ */ + IOM0_MI2CCFG_ADDRSZ_ADDRSZ7 = 0, /*!< ADDRSZ7 : Use 7b addressing for I2C master transactions */ + IOM0_MI2CCFG_ADDRSZ_ADDRSZ10 = 1, /*!< ADDRSZ10 : Use 10b addressing for I2C master transactions */ +} IOM0_MI2CCFG_ADDRSZ_Enum; + +/* ======================================================== DEVCFG ========================================================= */ +/* ======================================================== IOMDBG ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ IOSLAVE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FIFOPTR ======================================================== */ +/* ======================================================== FIFOCFG ======================================================== */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ========================================================= FUPD ========================================================== */ +/* ======================================================== FIFOCTR ======================================================== */ +/* ======================================================== FIFOINC ======================================================== */ +/* ========================================================== CFG ========================================================== */ +/* ============================================== IOSLAVE CFG IFCEN [31..31] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_IFCEN */ + IOSLAVE_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IOSLAVE */ + IOSLAVE_CFG_IFCEN_EN = 1, /*!< EN : Enable the IOSLAVE */ +} IOSLAVE_CFG_IFCEN_Enum; + +/* ============================================== IOSLAVE CFG STARTRD [4..4] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_STARTRD */ + IOSLAVE_CFG_STARTRD_LATE = 0, /*!< LATE : Initiate I/O RAM read late in each transferred byte. */ + IOSLAVE_CFG_STARTRD_EARLY = 1, /*!< EARLY : Initiate I/O RAM read early in each transferred byte. */ +} IOSLAVE_CFG_STARTRD_Enum; + +/* ================================================ IOSLAVE CFG LSB [2..2] ================================================= */ +typedef enum { /*!< IOSLAVE_CFG_LSB */ + IOSLAVE_CFG_LSB_MSB_FIRST = 0, /*!< MSB_FIRST : Data is assumed to be sent and received with MSB + first. */ + IOSLAVE_CFG_LSB_LSB_FIRST = 1, /*!< LSB_FIRST : Data is assumed to be sent and received with LSB + first. */ +} IOSLAVE_CFG_LSB_Enum; + +/* ================================================ IOSLAVE CFG SPOL [1..1] ================================================ */ +typedef enum { /*!< IOSLAVE_CFG_SPOL */ + IOSLAVE_CFG_SPOL_SPI_MODES_0_3 = 0, /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3. */ + IOSLAVE_CFG_SPOL_SPI_MODES_1_2 = 1, /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2. */ +} IOSLAVE_CFG_SPOL_Enum; + +/* =============================================== IOSLAVE CFG IFCSEL [0..0] =============================================== */ +typedef enum { /*!< IOSLAVE_CFG_IFCSEL */ + IOSLAVE_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the IO Slave. */ + IOSLAVE_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the IO Slave. */ +} IOSLAVE_CFG_IFCSEL_Enum; + +/* ========================================================= PRENC ========================================================= */ +/* ======================================================= IOINTCTL ======================================================== */ +/* ======================================================== GENADD ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ====================================================== REGACCINTEN ====================================================== */ +/* ===================================================== REGACCINTSTAT ===================================================== */ +/* ===================================================== REGACCINTCLR ====================================================== */ +/* ===================================================== REGACCINTSET ====================================================== */ + + +/* =========================================================================================================================== */ +/* ================ MCUCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CHIPPN ========================================================= */ +/* ============================================ MCUCTRL CHIPPN PARTNUM [0..31] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPPN_PARTNUM */ + MCUCTRL_CHIPPN_PARTNUM_APOLLO3 = 100663296,/*!< APOLLO3 : Apollo3 Blue part number is 0x06xxxxxx. */ + MCUCTRL_CHIPPN_PARTNUM_APOLLO2 = 50331648,/*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx. */ + MCUCTRL_CHIPPN_PARTNUM_APOLLO = 16777216,/*!< APOLLO : Apollo part number is 0x01xxxxxx. */ + MCUCTRL_CHIPPN_PARTNUM_PN_M = -16777216,/*!< PN_M : Mask for the part number field. */ + MCUCTRL_CHIPPN_PARTNUM_PN_S = 24, /*!< PN_S : Bit position for the part number field. */ + MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M = 15728640,/*!< FLASHSIZE_M : Mask for the FLASH_SIZE field.Values:0: 16KB1: + 32KB2: 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 2MB */ + MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S = 20, /*!< FLASHSIZE_S : Bit position for the FLASH_SIZE field. */ + MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M = 983040,/*!< SRAMSIZE_M : Mask for the SRAM_SIZE field.Values:0: 16KB1: 32KB2: + 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 384KB8: 768KB */ + MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S = 16, /*!< SRAMSIZE_S : Bit position for the SRAM_SIZE field. */ + MCUCTRL_CHIPPN_PARTNUM_REV_M = 65280, /*!< REV_M : Mask for the revision field. Bits [15:12] are major + rev, [11:8] are minor rev.Values:0: Major Rev A, Minor + Rev 01: Major Rev B, Minor Rev 1 */ + MCUCTRL_CHIPPN_PARTNUM_REV_S = 8, /*!< REV_S : Bit position for the revision field. */ + MCUCTRL_CHIPPN_PARTNUM_PKG_M = 192, /*!< PKG_M : Mask for the package field.Values:0: SIP1: QFN2: BGA3: + CSP */ + MCUCTRL_CHIPPN_PARTNUM_PKG_S = 6, /*!< PKG_S : Bit position for the package field. */ + MCUCTRL_CHIPPN_PARTNUM_PINS_M = 56, /*!< PINS_M : Mask for the pins field.Values:0: 25 pins1: 49 pins2: + 64 pins3: 81 pins4: 104 pins */ + MCUCTRL_CHIPPN_PARTNUM_PINS_S = 3, /*!< PINS_S : Bit position for the pins field. */ + MCUCTRL_CHIPPN_PARTNUM_TEMP_S = 1, /*!< TEMP_S : Bit position for the temperature field. */ + MCUCTRL_CHIPPN_PARTNUM_QUAL_S = 0, /*!< QUAL_S : Bit position for the qualified field. */ +} MCUCTRL_CHIPPN_PARTNUM_Enum; + +/* ======================================================== CHIPID0 ======================================================== */ +/* ============================================ MCUCTRL CHIPID0 CHIPID0 [0..31] ============================================ */ +typedef enum { /*!< MCUCTRL_CHIPID0_CHIPID0 */ + MCUCTRL_CHIPID0_CHIPID0_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 Blue Plus CHIPID0. */ +} MCUCTRL_CHIPID0_CHIPID0_Enum; + +/* ======================================================== CHIPID1 ======================================================== */ +/* ============================================ MCUCTRL CHIPID1 CHIPID1 [0..31] ============================================ */ +typedef enum { /*!< MCUCTRL_CHIPID1_CHIPID1 */ + MCUCTRL_CHIPID1_CHIPID1_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 Blue Plus CHIPID1. */ +} MCUCTRL_CHIPID1_CHIPID1_Enum; + +/* ======================================================== CHIPREV ======================================================== */ +/* ============================================= MCUCTRL CHIPREV REVMAJ [4..7] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPREV_REVMAJ */ + MCUCTRL_CHIPREV_REVMAJ_B = 2, /*!< B : Apollo3 Blue revision B */ + MCUCTRL_CHIPREV_REVMAJ_A = 1, /*!< A : Apollo3 Blue revision A */ +} MCUCTRL_CHIPREV_REVMAJ_Enum; + +/* ============================================= MCUCTRL CHIPREV REVMIN [0..3] ============================================= */ +typedef enum { /*!< MCUCTRL_CHIPREV_REVMIN */ + MCUCTRL_CHIPREV_REVMIN_REV1 = 2, /*!< REV1 : Apollo3 Blue minor rev 1. */ + MCUCTRL_CHIPREV_REVMIN_REV0 = 1, /*!< REV0 : Apollo3 Blue minor rev 0. Minor revision value, succeeding + minor revisions will increment from this value. */ +} MCUCTRL_CHIPREV_REVMIN_Enum; + +/* ======================================================= VENDORID ======================================================== */ +/* =========================================== MCUCTRL VENDORID VENDORID [0..31] =========================================== */ +typedef enum { /*!< MCUCTRL_VENDORID_VENDORID */ + MCUCTRL_VENDORID_VENDORID_AMBIQ = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ' */ +} MCUCTRL_VENDORID_VENDORID_Enum; + +/* ========================================================== SKU ========================================================== */ +/* ===================================================== FEATUREENABLE ===================================================== */ +/* ======================================== MCUCTRL FEATUREENABLE BURSTAVAIL [6..6] ======================================== */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTAVAIL */ + MCUCTRL_FEATUREENABLE_BURSTAVAIL_AVAIL = 1, /*!< AVAIL : Burst functionality available */ + MCUCTRL_FEATUREENABLE_BURSTAVAIL_NOTAVAIL = 0,/*!< NOTAVAIL : Burst functionality not available */ +} MCUCTRL_FEATUREENABLE_BURSTAVAIL_Enum; + +/* ========================================= MCUCTRL FEATUREENABLE BURSTREQ [4..4] ========================================= */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTREQ */ + MCUCTRL_FEATUREENABLE_BURSTREQ_EN = 1, /*!< EN : Enable the Burst functionality */ + MCUCTRL_FEATUREENABLE_BURSTREQ_DIS = 0, /*!< DIS : Disable the Burst functionality */ +} MCUCTRL_FEATUREENABLE_BURSTREQ_Enum; + +/* ========================================= MCUCTRL FEATUREENABLE BLEAVAIL [2..2] ========================================= */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEAVAIL */ + MCUCTRL_FEATUREENABLE_BLEAVAIL_AVAIL = 1, /*!< AVAIL : BLE functionality available */ + MCUCTRL_FEATUREENABLE_BLEAVAIL_NOTAVAIL = 0, /*!< NOTAVAIL : BLE functionality not available */ +} MCUCTRL_FEATUREENABLE_BLEAVAIL_Enum; + +/* ========================================== MCUCTRL FEATUREENABLE BLEREQ [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEREQ */ + MCUCTRL_FEATUREENABLE_BLEREQ_EN = 1, /*!< EN : Enable the BLE functionality */ + MCUCTRL_FEATUREENABLE_BLEREQ_DIS = 0, /*!< DIS : Disable the BLE functionality */ +} MCUCTRL_FEATUREENABLE_BLEREQ_Enum; + +/* ======================================================= DEBUGGER ======================================================== */ +/* ======================================================== BODCTRL ======================================================== */ +/* ======================================================= ADCPWRDLY ======================================================= */ +/* ======================================================== ADCCAL ========================================================= */ +/* ========================================== MCUCTRL ADCCAL ADCCALIBRATED [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_ADCCAL_ADCCALIBRATED */ + MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE = 0, /*!< FALSE : ADC is not calibrated */ + MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE = 1, /*!< TRUE : ADC is calibrated */ +} MCUCTRL_ADCCAL_ADCCALIBRATED_Enum; + +/* =========================================== MCUCTRL ADCCAL CALONPWRUP [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_ADCCAL_CALONPWRUP */ + MCUCTRL_ADCCAL_CALONPWRUP_DIS = 0, /*!< DIS : Disable automatic calibration on initial power up */ + MCUCTRL_ADCCAL_CALONPWRUP_EN = 1, /*!< EN : Enable automatic calibration on initial power up */ +} MCUCTRL_ADCCAL_CALONPWRUP_Enum; + +/* ====================================================== ADCBATTLOAD ====================================================== */ +/* ========================================== MCUCTRL ADCBATTLOAD BATTLOAD [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD */ + MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS = 0, /*!< DIS : Battery load is disconnected */ + MCUCTRL_ADCBATTLOAD_BATTLOAD_EN = 1, /*!< EN : Battery load is enabled */ +} MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum; + +/* ======================================================== ADCTRIM ======================================================== */ +/* ====================================================== ADCREFCOMP ======================================================= */ +/* ======================================================= XTALCTRL ======================================================== */ +/* ========================================== MCUCTRL XTALCTRL PWDBODXTAL [5..5] =========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_PWDBODXTAL */ + MCUCTRL_XTALCTRL_PWDBODXTAL_PWRUPBOD = 0, /*!< PWRUPBOD : Power up XTAL on BOD. */ + MCUCTRL_XTALCTRL_PWDBODXTAL_PWRDNBOD = 1, /*!< PWRDNBOD : Power down XTAL on BOD. */ +} MCUCTRL_XTALCTRL_PWDBODXTAL_Enum; + +/* ========================================= MCUCTRL XTALCTRL PDNBCMPRXTAL [4..4] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCMPRXTAL */ + MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP = 1, /*!< PWRUPCOMP : Power up XTAL oscillator comparator. */ + MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP = 0, /*!< PWRDNCOMP : Power down XTAL oscillator comparator. */ +} MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Enum; + +/* ========================================= MCUCTRL XTALCTRL PDNBCOREXTAL [3..3] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCOREXTAL */ + MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE = 1, /*!< PWRUPCORE : Power up XTAL oscillator core. */ + MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE = 0, /*!< PWRDNCORE : Power down XTAL oscillator core. */ +} MCUCTRL_XTALCTRL_PDNBCOREXTAL_Enum; + +/* ========================================== MCUCTRL XTALCTRL BYPCMPRXTAL [2..2] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_BYPCMPRXTAL */ + MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP = 0, /*!< USECOMP : Use the XTAL oscillator comparator. */ + MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP = 1, /*!< BYPCOMP : Bypass the XTAL oscillator comparator. */ +} MCUCTRL_XTALCTRL_BYPCMPRXTAL_Enum; + +/* ========================================= MCUCTRL XTALCTRL FDBKDSBLXTAL [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALCTRL_FDBKDSBLXTAL */ + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN = 0, /*!< EN : Enable XTAL oscillator comparator. */ + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS = 1, /*!< DIS : Disable XTAL oscillator comparator. */ +} MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Enum; + +/* ============================================ MCUCTRL XTALCTRL XTALSWE [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_XTALCTRL_XTALSWE */ + MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0, /*!< OVERRIDE_DIS : XTAL Software Override Disable. */ + MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1, /*!< OVERRIDE_EN : XTAL Software Override Enable. */ +} MCUCTRL_XTALCTRL_XTALSWE_Enum; + +/* ====================================================== XTALGENCTRL ====================================================== */ +/* ========================================== MCUCTRL XTALGENCTRL ACWARMUP [0..1] ========================================== */ +typedef enum { /*!< MCUCTRL_XTALGENCTRL_ACWARMUP */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1 = 0, /*!< SEC1 : Warm-up period of 1-2 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2 = 1, /*!< SEC2 : Warm-up period of 2-4 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4 = 2, /*!< SEC4 : Warm-up period of 4-8 seconds */ + MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8 = 3, /*!< SEC8 : Warm-up period of 8-16 seconds */ +} MCUCTRL_XTALGENCTRL_ACWARMUP_Enum; + +/* ======================================================= MISCCTRL ======================================================== */ +/* ====================================================== BOOTLOADER ======================================================= */ +/* ======================================= MCUCTRL BOOTLOADER SECBOOTONRST [30..31] ======================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST */ + MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled */ + MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1, /*!< ENABLED : Secure boot enabled */ + MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ +} MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum; + +/* ========================================== MCUCTRL BOOTLOADER SECBOOT [28..29] ========================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOT */ + MCUCTRL_BOOTLOADER_SECBOOT_DISABLED = 0, /*!< DISABLED : Secure boot disabled */ + MCUCTRL_BOOTLOADER_SECBOOT_ENABLED = 1, /*!< ENABLED : Secure boot enabled */ + MCUCTRL_BOOTLOADER_SECBOOT_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ +} MCUCTRL_BOOTLOADER_SECBOOT_Enum; + +/* ====================================== MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27] ======================================= */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE */ + MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled */ + MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled */ + MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ +} MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum; + +/* ========================================== MCUCTRL BOOTLOADER PROTLOCK [2..2] =========================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_PROTLOCK */ + MCUCTRL_BOOTLOADER_PROTLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */ +} MCUCTRL_BOOTLOADER_PROTLOCK_Enum; + +/* =========================================== MCUCTRL BOOTLOADER SBLOCK [1..1] ============================================ */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_SBLOCK */ + MCUCTRL_BOOTLOADER_SBLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */ +} MCUCTRL_BOOTLOADER_SBLOCK_Enum; + +/* ======================================== MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0] ======================================== */ +typedef enum { /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW */ + MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1, /*!< ADDR0 : Bootloader code at 0x00000000. */ +} MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum; + +/* ====================================================== SHADOWVALID ====================================================== */ +/* ======================================== MCUCTRL SHADOWVALID INFO0_VALID [2..2] ========================================= */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_INFO0_VALID */ + MCUCTRL_SHADOWVALID_INFO0_VALID_VALID = 1, /*!< VALID : Flash INFO0 (customer) space contains valid data. */ +} MCUCTRL_SHADOWVALID_INFO0_VALID_Enum; + +/* ========================================== MCUCTRL SHADOWVALID BLDSLEEP [1..1] ========================================== */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_BLDSLEEP */ + MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1, /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image + loaded */ +} MCUCTRL_SHADOWVALID_BLDSLEEP_Enum; + +/* =========================================== MCUCTRL SHADOWVALID VALID [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_SHADOWVALID_VALID */ + MCUCTRL_SHADOWVALID_VALID_VALID = 1, /*!< VALID : Flash information space contains valid data. */ +} MCUCTRL_SHADOWVALID_VALID_Enum; + +/* ======================================================= SCRATCH0 ======================================================== */ +/* ======================================================= SCRATCH1 ======================================================== */ +/* ==================================================== ICODEFAULTADDR ===================================================== */ +/* ==================================================== DCODEFAULTADDR ===================================================== */ +/* ===================================================== SYSFAULTADDR ====================================================== */ +/* ====================================================== FAULTSTATUS ====================================================== */ +/* ========================================== MCUCTRL FAULTSTATUS SYSFAULT [2..2] ========================================== */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_SYSFAULT */ + MCUCTRL_FAULTSTATUS_SYSFAULT_NOFAULT = 0, /*!< NOFAULT : No bus fault has been detected. */ + MCUCTRL_FAULTSTATUS_SYSFAULT_FAULT = 1, /*!< FAULT : Bus fault detected. */ +} MCUCTRL_FAULTSTATUS_SYSFAULT_Enum; + +/* ========================================= MCUCTRL FAULTSTATUS DCODEFAULT [1..1] ========================================= */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_DCODEFAULT */ + MCUCTRL_FAULTSTATUS_DCODEFAULT_NOFAULT = 0, /*!< NOFAULT : No DCODE fault has been detected. */ + MCUCTRL_FAULTSTATUS_DCODEFAULT_FAULT = 1, /*!< FAULT : DCODE fault detected. */ +} MCUCTRL_FAULTSTATUS_DCODEFAULT_Enum; + +/* ========================================= MCUCTRL FAULTSTATUS ICODEFAULT [0..0] ========================================= */ +typedef enum { /*!< MCUCTRL_FAULTSTATUS_ICODEFAULT */ + MCUCTRL_FAULTSTATUS_ICODEFAULT_NOFAULT = 0, /*!< NOFAULT : No ICODE fault has been detected. */ + MCUCTRL_FAULTSTATUS_ICODEFAULT_FAULT = 1, /*!< FAULT : ICODE fault detected. */ +} MCUCTRL_FAULTSTATUS_ICODEFAULT_Enum; + +/* ==================================================== FAULTCAPTUREEN ===================================================== */ +/* ===================================== MCUCTRL FAULTCAPTUREEN FAULTCAPTUREEN [0..0] ====================================== */ +typedef enum { /*!< MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN */ + MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,/*!< DIS : Disable fault capture. */ + MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1, /*!< EN : Enable fault capture. */ +} MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum; + +/* ========================================================= DBGR1 ========================================================= */ +/* ========================================================= DBGR2 ========================================================= */ +/* ======================================================= PMUENABLE ======================================================= */ +/* ============================================ MCUCTRL PMUENABLE ENABLE [0..0] ============================================ */ +typedef enum { /*!< MCUCTRL_PMUENABLE_ENABLE */ + MCUCTRL_PMUENABLE_ENABLE_DIS = 0, /*!< DIS : Disable MCU power management. */ + MCUCTRL_PMUENABLE_ENABLE_EN = 1, /*!< EN : Enable MCU power management. */ +} MCUCTRL_PMUENABLE_ENABLE_Enum; + +/* ======================================================= TPIUCTRL ======================================================== */ +/* ============================================ MCUCTRL TPIUCTRL CLKSEL [8..10] ============================================ */ +typedef enum { /*!< MCUCTRL_TPIUCTRL_CLKSEL */ + MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR = 0, /*!< LOWPWR : Low power state. */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV2 = 1, /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source TPIU clock */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8 = 2, /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source TPIU clock */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV16 = 3, /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source TPIU clock */ + MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV32 = 4, /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source TPIU clock */ +} MCUCTRL_TPIUCTRL_CLKSEL_Enum; + +/* ============================================ MCUCTRL TPIUCTRL ENABLE [0..0] ============================================= */ +typedef enum { /*!< MCUCTRL_TPIUCTRL_ENABLE */ + MCUCTRL_TPIUCTRL_ENABLE_DIS = 0, /*!< DIS : Disable the TPIU. */ + MCUCTRL_TPIUCTRL_ENABLE_EN = 1, /*!< EN : Enable the TPIU. */ +} MCUCTRL_TPIUCTRL_ENABLE_Enum; + +/* ====================================================== OTAPOINTER ======================================================= */ +/* ====================================================== APBDMACTRL ======================================================= */ +/* ========================================= MCUCTRL APBDMACTRL DECODEABORT [1..1] ========================================= */ +typedef enum { /*!< MCUCTRL_APBDMACTRL_DECODEABORT */ + MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0, /*!< DISABLE : Bus operations to powered down peripherals are quietly + discarded */ + MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1, /*!< ENABLE : Bus operations to powered down peripherals result in + a bus fault. */ +} MCUCTRL_APBDMACTRL_DECODEABORT_Enum; + +/* ========================================= MCUCTRL APBDMACTRL DMA_ENABLE [0..0] ========================================== */ +typedef enum { /*!< MCUCTRL_APBDMACTRL_DMA_ENABLE */ + MCUCTRL_APBDMACTRL_DMA_ENABLE_DISABLE = 0, /*!< DISABLE : DMA operations disabled */ + MCUCTRL_APBDMACTRL_DMA_ENABLE_ENABLE = 1, /*!< ENABLE : DMA operations enabled */ +} MCUCTRL_APBDMACTRL_DMA_ENABLE_Enum; + +/* ======================================================= SRAMMODE ======================================================== */ +/* ====================================================== KEXTCLKSEL ======================================================= */ +/* ========================================= MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31] ========================================= */ +typedef enum { /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL */ + MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key = 83, /*!< Key : Key */ +} MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum; + +/* ======================================================= SIMOBUCK2 ======================================================= */ +/* ======================================================= SIMOBUCK3 ======================================================= */ +/* ======================================================= SIMOBUCK4 ======================================================= */ +/* ======================================================= BLEBUCK2 ======================================================== */ +/* ====================================================== FLASHWPROT0 ====================================================== */ +/* ====================================================== FLASHWPROT1 ====================================================== */ +/* ====================================================== FLASHRPROT0 ====================================================== */ +/* ====================================================== FLASHRPROT1 ====================================================== */ +/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */ +/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */ +/* ================================================== DMASRAMREADPROTECT0 ================================================== */ +/* ================================================== DMASRAMREADPROTECT1 ================================================== */ + + +/* =========================================================================================================================== */ +/* ================ MSPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* ========================================================== CFG ========================================================== */ +/* ================================================ MSPI CFG CPOL [17..17] ================================================= */ +typedef enum { /*!< MSPI_CFG_CPOL */ + MSPI_CFG_CPOL_LOW = 0, /*!< LOW : Clock inactive state is low. */ + MSPI_CFG_CPOL_HIGH = 1, /*!< HIGH : Clock inactive state is high. */ +} MSPI_CFG_CPOL_Enum; + +/* ================================================ MSPI CFG CPHA [16..16] ================================================= */ +typedef enum { /*!< MSPI_CFG_CPHA */ + MSPI_CFG_CPHA_MIDDLE = 0, /*!< MIDDLE : Clock toggles in middle of data bit. */ + MSPI_CFG_CPHA_START = 1, /*!< START : Clock toggles at start of data bit. */ +} MSPI_CFG_CPHA_Enum; + +/* ================================================= MSPI CFG ASIZE [4..5] ================================================= */ +typedef enum { /*!< MSPI_CFG_ASIZE */ + MSPI_CFG_ASIZE_A1 = 0, /*!< A1 : Send one address byte */ + MSPI_CFG_ASIZE_A2 = 1, /*!< A2 : Send two address bytes */ + MSPI_CFG_ASIZE_A3 = 2, /*!< A3 : Send three address bytes */ + MSPI_CFG_ASIZE_A4 = 3, /*!< A4 : Send four address bytes */ +} MSPI_CFG_ASIZE_Enum; + +/* ================================================ MSPI CFG DEVCFG [0..3] ================================================= */ +typedef enum { /*!< MSPI_CFG_DEVCFG */ + MSPI_CFG_DEVCFG_SERIAL0 = 1, /*!< SERIAL0 : Single bit SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_SERIAL1 = 2, /*!< SERIAL1 : Single bit SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_DUAL0 = 5, /*!< DUAL0 : Dual SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_DUAL1 = 6, /*!< DUAL1 : Dual bit SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_QUAD0 = 9, /*!< QUAD0 : Quad SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_QUAD1 = 10, /*!< QUAD1 : Quad SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_OCTAL0 = 13, /*!< OCTAL0 : Octal SPI flash on chip select 0 */ + MSPI_CFG_DEVCFG_OCTAL1 = 14, /*!< OCTAL1 : Octal SPI flash on chip select 1 */ + MSPI_CFG_DEVCFG_QUADPAIRED = 15, /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1. */ + MSPI_CFG_DEVCFG_QUADPAIRED_SERIAL = 3, /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1, + but transmit in serial mode for initialization operations */ +} MSPI_CFG_DEVCFG_Enum; + +/* ========================================================= ADDR ========================================================== */ +/* ========================================================= INSTR ========================================================= */ +/* ======================================================== TXFIFO ========================================================= */ +/* ======================================================== RXFIFO ========================================================= */ +/* ======================================================= TXENTRIES ======================================================= */ +/* ======================================================= RXENTRIES ======================================================= */ +/* ======================================================= THRESHOLD ======================================================= */ +/* ======================================================== MSPICFG ======================================================== */ +/* ============================================== MSPI MSPICFG CLKDIV [8..13] ============================================== */ +typedef enum { /*!< MSPI_MSPICFG_CLKDIV */ + MSPI_MSPICFG_CLKDIV_CLK48 = 1, /*!< CLK48 : 48 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK24 = 2, /*!< CLK24 : 24 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK12 = 4, /*!< CLK12 : 12 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK6 = 8, /*!< CLK6 : 6 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK3 = 16, /*!< CLK3 : 3 MHz MSPI clock */ + MSPI_MSPICFG_CLKDIV_CLK1_5 = 32, /*!< CLK1_5 : 1.5 MHz MSPI clock */ +} MSPI_MSPICFG_CLKDIV_Enum; + +/* ============================================== MSPI MSPICFG IOMSEL [4..6] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_IOMSEL */ + MSPI_MSPICFG_IOMSEL_IOM0 = 0, /*!< IOM0 : IOM0 */ + MSPI_MSPICFG_IOMSEL_IOM1 = 1, /*!< IOM1 : IOM1 */ + MSPI_MSPICFG_IOMSEL_IOM2 = 2, /*!< IOM2 : IOM2 */ + MSPI_MSPICFG_IOMSEL_IOM3 = 3, /*!< IOM3 : IOM3 */ + MSPI_MSPICFG_IOMSEL_IOM4 = 4, /*!< IOM4 : IOM4 */ + MSPI_MSPICFG_IOMSEL_IOM5 = 5, /*!< IOM5 : IOM5 */ + MSPI_MSPICFG_IOMSEL_DISABLED = 7, /*!< DISABLED : No IOM selected. Signals always zero. */ +} MSPI_MSPICFG_IOMSEL_Enum; + +/* =============================================== MSPI MSPICFG TXNEG [3..3] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_TXNEG */ + MSPI_MSPICFG_TXNEG_NORMAL = 0, /*!< NORMAL : TX launched from posedge internal clock */ + MSPI_MSPICFG_TXNEG_NEGEDGE = 1, /*!< NEGEDGE : TX data launched from negedge of internal clock */ +} MSPI_MSPICFG_TXNEG_Enum; + +/* =============================================== MSPI MSPICFG RXNEG [2..2] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_RXNEG */ + MSPI_MSPICFG_RXNEG_NORMAL = 0, /*!< NORMAL : RX data sampled on posedge of internal clock */ + MSPI_MSPICFG_RXNEG_NEGEDGE = 1, /*!< NEGEDGE : RX data sampled on negedge of internal clock */ +} MSPI_MSPICFG_RXNEG_Enum; + +/* =============================================== MSPI MSPICFG RXCAP [1..1] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_RXCAP */ + MSPI_MSPICFG_RXCAP_NORMAL = 0, /*!< NORMAL : RX Capture phase aligns with CPHA setting */ + MSPI_MSPICFG_RXCAP_DELAY = 1, /*!< DELAY : RX Capture phase is delayed from CPHA setting by one + clock edge */ +} MSPI_MSPICFG_RXCAP_Enum; + +/* ============================================== MSPI MSPICFG APBCLK [0..0] =============================================== */ +typedef enum { /*!< MSPI_MSPICFG_APBCLK */ + MSPI_MSPICFG_APBCLK_DIS = 0, /*!< DIS : Disable continuous clock. */ + MSPI_MSPICFG_APBCLK_EN = 1, /*!< EN : Enable continuous clock. */ +} MSPI_MSPICFG_APBCLK_Enum; + +/* ======================================================== PADCFG ========================================================= */ +/* ======================================================= PADOUTEN ======================================================== */ +/* ============================================== MSPI PADOUTEN OUTEN [0..8] =============================================== */ +typedef enum { /*!< MSPI_PADOUTEN_OUTEN */ + MSPI_PADOUTEN_OUTEN_QUAD0 = 271, /*!< QUAD0 : Quad0 (4 data + 1 clock) */ + MSPI_PADOUTEN_OUTEN_QUAD1 = 496, /*!< QUAD1 : Quad1 (4 data + 1 clock) */ + MSPI_PADOUTEN_OUTEN_OCTAL = 511, /*!< OCTAL : Octal (8 data + 1 clock) */ + MSPI_PADOUTEN_OUTEN_SERIAL0 = 259, /*!< SERIAL0 : Serial (2 data + 1 clock) */ +} MSPI_PADOUTEN_OUTEN_Enum; + +/* ========================================================= FLASH ========================================================= */ +/* =============================================== MSPI FLASH XIPACK [2..3] ================================================ */ +typedef enum { /*!< MSPI_FLASH_XIPACK */ + MSPI_FLASH_XIPACK_NOACK = 0, /*!< NOACK : No acknowledgment sent. Data IOs are tri-stated the + first turnaround cycle */ + MSPI_FLASH_XIPACK_ACK = 2, /*!< ACK : Positive acknowledgment sent. Data IOs are driven to 0 + the first turnaround cycle to acknowledge XIP mode */ + MSPI_FLASH_XIPACK_TERMINATE = 3, /*!< TERMINATE : Negative acknowledgment sent. Data IOs are driven + to 1 the first turnaround cycle to terminate XIP mode. + XIPSENDI should be re-enabled for the next transfer */ +} MSPI_FLASH_XIPACK_Enum; + +/* ====================================================== SCRAMBLING ======================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================== DMACFG ========================================================= */ +/* =============================================== MSPI DMACFG DMAPRI [3..4] =============================================== */ +typedef enum { /*!< MSPI_DMACFG_DMAPRI */ + MSPI_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + MSPI_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ + MSPI_DMACFG_DMAPRI_AUTO = 2, /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or + RX FIFO fills) */ +} MSPI_DMACFG_DMAPRI_Enum; + +/* =============================================== MSPI DMACFG DMADIR [2..2] =============================================== */ +typedef enum { /*!< MSPI_DMACFG_DMADIR */ + MSPI_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */ + MSPI_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */ +} MSPI_DMACFG_DMADIR_Enum; + +/* =============================================== MSPI DMACFG DMAEN [0..1] ================================================ */ +typedef enum { /*!< MSPI_DMACFG_DMAEN */ + MSPI_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + MSPI_DMACFG_DMAEN_EN = 3, /*!< EN : Enable HW controlled DMA Function to manage DMA to flash + devices. HW will automatically handle issuance of instruction/address + bytes based on settings in the FLASH register. */ +} MSPI_DMACFG_DMAEN_Enum; + +/* ======================================================== DMASTAT ======================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ====================================================== DMADEVADDR ======================================================= */ +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ======================================================= DMABCOUNT ======================================================= */ +/* ======================================================= DMATHRESH ======================================================= */ +/* ========================================================= CQCFG ========================================================= */ +/* ================================================ MSPI CQCFG CQPRI [1..1] ================================================ */ +typedef enum { /*!< MSPI_CQCFG_CQPRI */ + MSPI_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + MSPI_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} MSPI_CQCFG_CQPRI_Enum; + +/* ================================================ MSPI CQCFG CQEN [0..0] ================================================= */ +typedef enum { /*!< MSPI_CQCFG_CQEN */ + MSPI_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ + MSPI_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ +} MSPI_CQCFG_CQEN_Enum; + +/* ======================================================== CQADDR ========================================================= */ +/* ======================================================== CQSTAT ========================================================= */ +/* ======================================================== CQFLAGS ======================================================== */ +/* ============================================= MSPI CQFLAGS CQFLAGS [0..15] ============================================== */ +typedef enum { /*!< MSPI_CQFLAGS_CQFLAGS */ + MSPI_CQFLAGS_CQFLAGS_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */ + MSPI_CQFLAGS_CQFLAGS_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */ + MSPI_CQFLAGS_CQFLAGS_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */ + MSPI_CQFLAGS_CQFLAGS_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */ + MSPI_CQFLAGS_CQFLAGS_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQFLAGS_CQFLAGS_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause + operations. */ + MSPI_CQFLAGS_CQFLAGS_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause + operations. */ +} MSPI_CQFLAGS_CQFLAGS_Enum; + +/* ====================================================== CQSETCLEAR ======================================================= */ +/* ======================================================== CQPAUSE ======================================================== */ +/* ============================================== MSPI CQPAUSE CQMASK [0..15] ============================================== */ +typedef enum { /*!< MSPI_CQPAUSE_CQMASK */ + MSPI_CQPAUSE_CQMASK_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */ + MSPI_CQPAUSE_CQMASK_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */ + MSPI_CQPAUSE_CQMASK_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */ + MSPI_CQPAUSE_CQMASK_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */ + MSPI_CQPAUSE_CQMASK_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQPAUSE_CQMASK_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This + status is the result of XNOR'ing the IOM0START with the + incoming status from the IOM. When high, MSPI can send + to the buffer. */ + MSPI_CQPAUSE_CQMASK_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause + operations. */ + MSPI_CQPAUSE_CQMASK_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause + operations. */ +} MSPI_CQPAUSE_CQMASK_Enum; + +/* ======================================================= CQCURIDX ======================================================== */ +/* ======================================================= CQENDIDX ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCFG ========================================================== */ +/* =============================================== PDM PCFG LRSWAP [31..31] ================================================ */ +typedef enum { /*!< PDM_PCFG_LRSWAP */ + PDM_PCFG_LRSWAP_EN = 1, /*!< EN : Swap left and right channels (FIFO Read RIGHT_LEFT). */ + PDM_PCFG_LRSWAP_NOSWAP = 0, /*!< NOSWAP : No channel swapping (IFO Read LEFT_RIGHT). */ +} PDM_PCFG_LRSWAP_Enum; + +/* ============================================== PDM PCFG PGARIGHT [26..30] =============================================== */ +typedef enum { /*!< PDM_PCFG_PGARIGHT */ + PDM_PCFG_PGARIGHT_P405DB = 31, /*!< P405DB : 40.5 db gain. */ + PDM_PCFG_PGARIGHT_P390DB = 30, /*!< P390DB : 39.0 db gain. */ + PDM_PCFG_PGARIGHT_P375DB = 29, /*!< P375DB : 37.5 db gain. */ + PDM_PCFG_PGARIGHT_P360DB = 28, /*!< P360DB : 36.0 db gain. */ + PDM_PCFG_PGARIGHT_P345DB = 27, /*!< P345DB : 34.5 db gain. */ + PDM_PCFG_PGARIGHT_P330DB = 26, /*!< P330DB : 33.0 db gain. */ + PDM_PCFG_PGARIGHT_P315DB = 25, /*!< P315DB : 31.5 db gain. */ + PDM_PCFG_PGARIGHT_P300DB = 24, /*!< P300DB : 30.0 db gain. */ + PDM_PCFG_PGARIGHT_P285DB = 23, /*!< P285DB : 28.5 db gain. */ + PDM_PCFG_PGARIGHT_P270DB = 22, /*!< P270DB : 27.0 db gain. */ + PDM_PCFG_PGARIGHT_P255DB = 21, /*!< P255DB : 25.5 db gain. */ + PDM_PCFG_PGARIGHT_P240DB = 20, /*!< P240DB : 24.0 db gain. */ + PDM_PCFG_PGARIGHT_P225DB = 19, /*!< P225DB : 22.5 db gain. */ + PDM_PCFG_PGARIGHT_P210DB = 18, /*!< P210DB : 21.0 db gain. */ + PDM_PCFG_PGARIGHT_P195DB = 17, /*!< P195DB : 19.5 db gain. */ + PDM_PCFG_PGARIGHT_P180DB = 16, /*!< P180DB : 18.0 db gain. */ + PDM_PCFG_PGARIGHT_P165DB = 15, /*!< P165DB : 16.5 db gain. */ + PDM_PCFG_PGARIGHT_P150DB = 14, /*!< P150DB : 15.0 db gain. */ + PDM_PCFG_PGARIGHT_P135DB = 13, /*!< P135DB : 13.5 db gain. */ + PDM_PCFG_PGARIGHT_P120DB = 12, /*!< P120DB : 12.0 db gain. */ + PDM_PCFG_PGARIGHT_P105DB = 11, /*!< P105DB : 10.5 db gain. */ + PDM_PCFG_PGARIGHT_P90DB = 10, /*!< P90DB : 9.0 db gain. */ + PDM_PCFG_PGARIGHT_P75DB = 9, /*!< P75DB : 7.5 db gain. */ + PDM_PCFG_PGARIGHT_P60DB = 8, /*!< P60DB : 6.0 db gain. */ + PDM_PCFG_PGARIGHT_P45DB = 7, /*!< P45DB : 4.5 db gain. */ + PDM_PCFG_PGARIGHT_P30DB = 6, /*!< P30DB : 3.0 db gain. */ + PDM_PCFG_PGARIGHT_P15DB = 5, /*!< P15DB : 1.5 db gain. */ + PDM_PCFG_PGARIGHT_0DB = 4, /*!< 0DB : 0.0 db gain. */ + PDM_PCFG_PGARIGHT_M15DB = 3, /*!< M15DB : -1.5 db gain. */ + PDM_PCFG_PGARIGHT_M300DB = 2, /*!< M300DB : -3.0 db gain. */ + PDM_PCFG_PGARIGHT_M45DB = 1, /*!< M45DB : -4.5 db gain. */ + PDM_PCFG_PGARIGHT_M60DB = 0, /*!< M60DB : -6.0 db gain. */ +} PDM_PCFG_PGARIGHT_Enum; + +/* =============================================== PDM PCFG PGALEFT [21..25] =============================================== */ +typedef enum { /*!< PDM_PCFG_PGALEFT */ + PDM_PCFG_PGALEFT_P405DB = 31, /*!< P405DB : 40.5 db gain. */ + PDM_PCFG_PGALEFT_P390DB = 30, /*!< P390DB : 39.0 db gain. */ + PDM_PCFG_PGALEFT_P375DB = 29, /*!< P375DB : 37.5 db gain. */ + PDM_PCFG_PGALEFT_P360DB = 28, /*!< P360DB : 36.0 db gain. */ + PDM_PCFG_PGALEFT_P345DB = 27, /*!< P345DB : 34.5 db gain. */ + PDM_PCFG_PGALEFT_P330DB = 26, /*!< P330DB : 33.0 db gain. */ + PDM_PCFG_PGALEFT_P315DB = 25, /*!< P315DB : 31.5 db gain. */ + PDM_PCFG_PGALEFT_P300DB = 24, /*!< P300DB : 30.0 db gain. */ + PDM_PCFG_PGALEFT_P285DB = 23, /*!< P285DB : 28.5 db gain. */ + PDM_PCFG_PGALEFT_P270DB = 22, /*!< P270DB : 27.0 db gain. */ + PDM_PCFG_PGALEFT_P255DB = 21, /*!< P255DB : 25.5 db gain. */ + PDM_PCFG_PGALEFT_P240DB = 20, /*!< P240DB : 24.0 db gain. */ + PDM_PCFG_PGALEFT_P225DB = 19, /*!< P225DB : 22.5 db gain. */ + PDM_PCFG_PGALEFT_P210DB = 18, /*!< P210DB : 21.0 db gain. */ + PDM_PCFG_PGALEFT_P195DB = 17, /*!< P195DB : 19.5 db gain. */ + PDM_PCFG_PGALEFT_P180DB = 16, /*!< P180DB : 18.0 db gain. */ + PDM_PCFG_PGALEFT_P165DB = 15, /*!< P165DB : 16.5 db gain. */ + PDM_PCFG_PGALEFT_P150DB = 14, /*!< P150DB : 15.0 db gain. */ + PDM_PCFG_PGALEFT_P135DB = 13, /*!< P135DB : 13.5 db gain. */ + PDM_PCFG_PGALEFT_P120DB = 12, /*!< P120DB : 12.0 db gain. */ + PDM_PCFG_PGALEFT_P105DB = 11, /*!< P105DB : 10.5 db gain. */ + PDM_PCFG_PGALEFT_P90DB = 10, /*!< P90DB : 9.0 db gain. */ + PDM_PCFG_PGALEFT_P75DB = 9, /*!< P75DB : 7.5 db gain. */ + PDM_PCFG_PGALEFT_P60DB = 8, /*!< P60DB : 6.0 db gain. */ + PDM_PCFG_PGALEFT_P45DB = 7, /*!< P45DB : 4.5 db gain. */ + PDM_PCFG_PGALEFT_P30DB = 6, /*!< P30DB : 3.0 db gain. */ + PDM_PCFG_PGALEFT_P15DB = 5, /*!< P15DB : 1.5 db gain. */ + PDM_PCFG_PGALEFT_0DB = 4, /*!< 0DB : 0.0 db gain. */ + PDM_PCFG_PGALEFT_M15DB = 3, /*!< M15DB : -1.5 db gain. */ + PDM_PCFG_PGALEFT_M300DB = 2, /*!< M300DB : -3.0 db gain. */ + PDM_PCFG_PGALEFT_M45DB = 1, /*!< M45DB : -4.5 db gain. */ + PDM_PCFG_PGALEFT_M60DB = 0, /*!< M60DB : -6.0 db gain. */ +} PDM_PCFG_PGALEFT_Enum; + +/* =============================================== PDM PCFG MCLKDIV [17..18] =============================================== */ +typedef enum { /*!< PDM_PCFG_MCLKDIV */ + PDM_PCFG_MCLKDIV_MCKDIV4 = 3, /*!< MCKDIV4 : Divide input clock by 4 */ + PDM_PCFG_MCLKDIV_MCKDIV3 = 2, /*!< MCKDIV3 : Divide input clock by 3 */ + PDM_PCFG_MCLKDIV_MCKDIV2 = 1, /*!< MCKDIV2 : Divide input clock by 2 */ + PDM_PCFG_MCLKDIV_MCKDIV1 = 0, /*!< MCKDIV1 : Divide input clock by 1 */ +} PDM_PCFG_MCLKDIV_Enum; + +/* ================================================ PDM PCFG ADCHPD [9..9] ================================================= */ +typedef enum { /*!< PDM_PCFG_ADCHPD */ + PDM_PCFG_ADCHPD_EN = 0, /*!< EN : Enable high pass filter. */ + PDM_PCFG_ADCHPD_DIS = 1, /*!< DIS : Disable high pass filter. */ +} PDM_PCFG_ADCHPD_Enum; + +/* =============================================== PDM PCFG SOFTMUTE [1..1] ================================================ */ +typedef enum { /*!< PDM_PCFG_SOFTMUTE */ + PDM_PCFG_SOFTMUTE_EN = 1, /*!< EN : Enable Soft Mute. */ + PDM_PCFG_SOFTMUTE_DIS = 0, /*!< DIS : Disable Soft Mute. */ +} PDM_PCFG_SOFTMUTE_Enum; + +/* =============================================== PDM PCFG PDMCOREEN [0..0] =============================================== */ +typedef enum { /*!< PDM_PCFG_PDMCOREEN */ + PDM_PCFG_PDMCOREEN_EN = 1, /*!< EN : Enable Data Streaming. */ + PDM_PCFG_PDMCOREEN_DIS = 0, /*!< DIS : Disable Data Streaming. */ +} PDM_PCFG_PDMCOREEN_Enum; + +/* ========================================================= VCFG ========================================================== */ +/* =============================================== PDM VCFG IOCLKEN [31..31] =============================================== */ +typedef enum { /*!< PDM_VCFG_IOCLKEN */ + PDM_VCFG_IOCLKEN_DIS = 0, /*!< DIS : Disable FIFO read. */ + PDM_VCFG_IOCLKEN_EN = 1, /*!< EN : Enable FIFO read. */ +} PDM_VCFG_IOCLKEN_Enum; + +/* ================================================ PDM VCFG RSTB [30..30] ================================================= */ +typedef enum { /*!< PDM_VCFG_RSTB */ + PDM_VCFG_RSTB_RESET = 0, /*!< RESET : Reset the core. */ + PDM_VCFG_RSTB_NORM = 1, /*!< NORM : Enable the core. */ +} PDM_VCFG_RSTB_Enum; + +/* ============================================== PDM VCFG PDMCLKSEL [27..29] ============================================== */ +typedef enum { /*!< PDM_VCFG_PDMCLKSEL */ + PDM_VCFG_PDMCLKSEL_DISABLE = 0, /*!< DISABLE : Static value. */ + PDM_VCFG_PDMCLKSEL_12MHz = 1, /*!< 12MHz : PDM clock is 12 MHz. */ + PDM_VCFG_PDMCLKSEL_6MHz = 2, /*!< 6MHz : PDM clock is 6 MHz. */ + PDM_VCFG_PDMCLKSEL_3MHz = 3, /*!< 3MHz : PDM clock is 3 MHz. */ + PDM_VCFG_PDMCLKSEL_1_5MHz = 4, /*!< 1_5MHz : PDM clock is 1.5 MHz. */ + PDM_VCFG_PDMCLKSEL_750KHz = 5, /*!< 750KHz : PDM clock is 750 KHz. */ + PDM_VCFG_PDMCLKSEL_375KHz = 6, /*!< 375KHz : PDM clock is 375 KHz. */ + PDM_VCFG_PDMCLKSEL_187KHz = 7, /*!< 187KHz : PDM clock is 187.5 KHz. */ +} PDM_VCFG_PDMCLKSEL_Enum; + +/* ============================================== PDM VCFG PDMCLKEN [26..26] =============================================== */ +typedef enum { /*!< PDM_VCFG_PDMCLKEN */ + PDM_VCFG_PDMCLKEN_DIS = 0, /*!< DIS : Disable serial clock. */ + PDM_VCFG_PDMCLKEN_EN = 1, /*!< EN : Enable serial clock. */ +} PDM_VCFG_PDMCLKEN_Enum; + +/* ================================================ PDM VCFG I2SEN [20..20] ================================================ */ +typedef enum { /*!< PDM_VCFG_I2SEN */ + PDM_VCFG_I2SEN_DIS = 0, /*!< DIS : Disable I2S interface. */ + PDM_VCFG_I2SEN_EN = 1, /*!< EN : Enable I2S interface. */ +} PDM_VCFG_I2SEN_Enum; + +/* =============================================== PDM VCFG BCLKINV [19..19] =============================================== */ +typedef enum { /*!< PDM_VCFG_BCLKINV */ + PDM_VCFG_BCLKINV_INV = 0, /*!< INV : BCLK inverted. */ + PDM_VCFG_BCLKINV_NORM = 1, /*!< NORM : BCLK not inverted. */ +} PDM_VCFG_BCLKINV_Enum; + +/* ============================================== PDM VCFG DMICKDEL [17..17] =============================================== */ +typedef enum { /*!< PDM_VCFG_DMICKDEL */ + PDM_VCFG_DMICKDEL_0CYC = 0, /*!< 0CYC : No delay. */ + PDM_VCFG_DMICKDEL_1CYC = 1, /*!< 1CYC : 1 cycle delay. */ +} PDM_VCFG_DMICKDEL_Enum; + +/* ================================================ PDM VCFG SELAP [16..16] ================================================ */ +typedef enum { /*!< PDM_VCFG_SELAP */ + PDM_VCFG_SELAP_I2S = 1, /*!< I2S : Clock source from I2S BCLK. */ + PDM_VCFG_SELAP_INTERNAL = 0, /*!< INTERNAL : Clock source from internal clock generator. */ +} PDM_VCFG_SELAP_Enum; + +/* ================================================ PDM VCFG PCMPACK [8..8] ================================================ */ +typedef enum { /*!< PDM_VCFG_PCMPACK */ + PDM_VCFG_PCMPACK_DIS = 0, /*!< DIS : Disable PCM packing. */ + PDM_VCFG_PCMPACK_EN = 1, /*!< EN : Enable PCM packing. */ +} PDM_VCFG_PCMPACK_Enum; + +/* ================================================= PDM VCFG CHSET [3..4] ================================================= */ +typedef enum { /*!< PDM_VCFG_CHSET */ + PDM_VCFG_CHSET_DIS = 0, /*!< DIS : Channel disabled. */ + PDM_VCFG_CHSET_LEFT = 1, /*!< LEFT : Mono left channel. */ + PDM_VCFG_CHSET_RIGHT = 2, /*!< RIGHT : Mono right channel. */ + PDM_VCFG_CHSET_STEREO = 3, /*!< STEREO : Stereo channels. */ +} PDM_VCFG_CHSET_Enum; + +/* ======================================================= VOICESTAT ======================================================= */ +/* ======================================================= FIFOREAD ======================================================== */ +/* ======================================================= FIFOFLUSH ======================================================= */ +/* ======================================================== FIFOTHR ======================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ======================================================= DMATRIGEN ======================================================= */ +/* ====================================================== DMATRIGSTAT ====================================================== */ +/* ======================================================== DMACFG ========================================================= */ +/* =============================================== PDM DMACFG DMAPRI [8..8] ================================================ */ +typedef enum { /*!< PDM_DMACFG_DMAPRI */ + PDM_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ + PDM_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ +} PDM_DMACFG_DMAPRI_Enum; + +/* =============================================== PDM DMACFG DMADIR [2..2] ================================================ */ +typedef enum { /*!< PDM_DMACFG_DMADIR */ + PDM_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module + will only DMA to memory. */ + PDM_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. Not available for PDM + module */ +} PDM_DMACFG_DMADIR_Enum; + +/* ================================================ PDM DMACFG DMAEN [0..0] ================================================ */ +typedef enum { /*!< PDM_DMACFG_DMAEN */ + PDM_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ + PDM_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ +} PDM_DMACFG_DMAEN_Enum; + +/* ====================================================== DMATOTCOUNT ====================================================== */ +/* ====================================================== DMATARGADDR ====================================================== */ +/* ======================================================== DMASTAT ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ PWRCTRL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SUPPLYSRC ======================================================= */ +/* ========================================== PWRCTRL SUPPLYSRC BLEBUCKEN [0..0] =========================================== */ +typedef enum { /*!< PWRCTRL_SUPPLYSRC_BLEBUCKEN */ + PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN = 1, /*!< EN : Enable the BLE Buck. */ + PWRCTRL_SUPPLYSRC_BLEBUCKEN_DIS = 0, /*!< DIS : Disable the BLE Buck. */ +} PWRCTRL_SUPPLYSRC_BLEBUCKEN_Enum; + +/* ===================================================== SUPPLYSTATUS ====================================================== */ +/* ========================================= PWRCTRL SUPPLYSTATUS BLEBUCKON [1..1] ========================================= */ +typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_BLEBUCKON */ + PWRCTRL_SUPPLYSTATUS_BLEBUCKON_LDO = 0, /*!< LDO : Indicates the the LDO is supplying the BLE/Burst power + domain */ + PWRCTRL_SUPPLYSTATUS_BLEBUCKON_BUCK = 1, /*!< BUCK : Indicates the the Buck is supplying the BLE/Burst power + domain */ +} PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Enum; + +/* ======================================== PWRCTRL SUPPLYSTATUS SIMOBUCKON [0..0] ========================================= */ +typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_SIMOBUCKON */ + PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_OFF = 0, /*!< OFF : Indicates the the SIMO Buck is OFF. */ + PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_ON = 1, /*!< ON : Indicates the the SIMO Buck is ON. */ +} PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Enum; + +/* ======================================================= DEVPWREN ======================================================== */ +/* =========================================== PWRCTRL DEVPWREN PWRBLEL [13..13] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRBLEL */ + PWRCTRL_DEVPWREN_PWRBLEL_EN = 1, /*!< EN : Power up BLE controller */ + PWRCTRL_DEVPWREN_PWRBLEL_DIS = 0, /*!< DIS : Power down BLE controller */ +} PWRCTRL_DEVPWREN_PWRBLEL_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRPDM [12..12] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRPDM */ + PWRCTRL_DEVPWREN_PWRPDM_EN = 1, /*!< EN : Power up PDM */ + PWRCTRL_DEVPWREN_PWRPDM_DIS = 0, /*!< DIS : Power down PDM */ +} PWRCTRL_DEVPWREN_PWRPDM_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRMSPI [11..11] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRMSPI */ + PWRCTRL_DEVPWREN_PWRMSPI_EN = 1, /*!< EN : Power up MSPI */ + PWRCTRL_DEVPWREN_PWRMSPI_DIS = 0, /*!< DIS : Power down MSPI */ +} PWRCTRL_DEVPWREN_PWRMSPI_Enum; + +/* ========================================== PWRCTRL DEVPWREN PWRSCARD [10..10] =========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRSCARD */ + PWRCTRL_DEVPWREN_PWRSCARD_EN = 1, /*!< EN : Power up SCARD */ + PWRCTRL_DEVPWREN_PWRSCARD_DIS = 0, /*!< DIS : Power down SCARD */ +} PWRCTRL_DEVPWREN_PWRSCARD_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRADC [9..9] ============================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRADC */ + PWRCTRL_DEVPWREN_PWRADC_EN = 1, /*!< EN : Power up ADC */ + PWRCTRL_DEVPWREN_PWRADC_DIS = 0, /*!< DIS : Power Down ADC */ +} PWRCTRL_DEVPWREN_PWRADC_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRUART1 [8..8] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART1 */ + PWRCTRL_DEVPWREN_PWRUART1_EN = 1, /*!< EN : Power up UART 1 */ + PWRCTRL_DEVPWREN_PWRUART1_DIS = 0, /*!< DIS : Power down UART 1 */ +} PWRCTRL_DEVPWREN_PWRUART1_Enum; + +/* =========================================== PWRCTRL DEVPWREN PWRUART0 [7..7] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART0 */ + PWRCTRL_DEVPWREN_PWRUART0_EN = 1, /*!< EN : Power up UART 0 */ + PWRCTRL_DEVPWREN_PWRUART0_DIS = 0, /*!< DIS : Power down UART 0 */ +} PWRCTRL_DEVPWREN_PWRUART0_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM5 [6..6] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM5 */ + PWRCTRL_DEVPWREN_PWRIOM5_EN = 1, /*!< EN : Power up IO Master 5 */ + PWRCTRL_DEVPWREN_PWRIOM5_DIS = 0, /*!< DIS : Power down IO Master 5 */ +} PWRCTRL_DEVPWREN_PWRIOM5_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM4 [5..5] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM4 */ + PWRCTRL_DEVPWREN_PWRIOM4_EN = 1, /*!< EN : Power up IO Master 4 */ + PWRCTRL_DEVPWREN_PWRIOM4_DIS = 0, /*!< DIS : Power down IO Master 4 */ +} PWRCTRL_DEVPWREN_PWRIOM4_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM3 [4..4] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM3 */ + PWRCTRL_DEVPWREN_PWRIOM3_EN = 1, /*!< EN : Power up IO Master 3 */ + PWRCTRL_DEVPWREN_PWRIOM3_DIS = 0, /*!< DIS : Power down IO Master 3 */ +} PWRCTRL_DEVPWREN_PWRIOM3_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM2 [3..3] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM2 */ + PWRCTRL_DEVPWREN_PWRIOM2_EN = 1, /*!< EN : Power up IO Master 2 */ + PWRCTRL_DEVPWREN_PWRIOM2_DIS = 0, /*!< DIS : Power down IO Master 2 */ +} PWRCTRL_DEVPWREN_PWRIOM2_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM1 [2..2] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM1 */ + PWRCTRL_DEVPWREN_PWRIOM1_EN = 1, /*!< EN : Power up IO Master 1 */ + PWRCTRL_DEVPWREN_PWRIOM1_DIS = 0, /*!< DIS : Power down IO Master 1 */ +} PWRCTRL_DEVPWREN_PWRIOM1_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOM0 [1..1] ============================================ */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM0 */ + PWRCTRL_DEVPWREN_PWRIOM0_EN = 1, /*!< EN : Power up IO Master 0 */ + PWRCTRL_DEVPWREN_PWRIOM0_DIS = 0, /*!< DIS : Power down IO Master 0 */ +} PWRCTRL_DEVPWREN_PWRIOM0_Enum; + +/* ============================================ PWRCTRL DEVPWREN PWRIOS [0..0] ============================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOS */ + PWRCTRL_DEVPWREN_PWRIOS_EN = 1, /*!< EN : Power up IO slave */ + PWRCTRL_DEVPWREN_PWRIOS_DIS = 0, /*!< DIS : Power down IO slave */ +} PWRCTRL_DEVPWREN_PWRIOS_Enum; + +/* ===================================================== MEMPWDINSLEEP ===================================================== */ +/* ====================================== PWRCTRL MEMPWDINSLEEP CACHEPWDSLP [31..31] ======================================= */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP */ + PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN = 1, /*!< EN : Power down cache in deep sleep */ + PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_DIS = 0, /*!< DIS : Retain cache in deep sleep */ +} PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Enum; + +/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH1PWDSLP [14..14] ====================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP */ + PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN = 1, /*!< EN : Flash1 is powered down during deepsleep */ + PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_DIS = 0, /*!< DIS : Flash1 is kept powered on during deepsleep */ +} PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Enum; + +/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH0PWDSLP [13..13] ====================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP */ + PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN = 1, /*!< EN : Flash0 is powered down during deepsleep */ + PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_DIS = 0, /*!< DIS : Flash0 is kept powered on during deepsleep */ +} PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Enum; + +/* ======================================= PWRCTRL MEMPWDINSLEEP SRAMPWDSLP [3..12] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_NONE = 0, /*!< NONE : All banks retained */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0 = 1, /*!< GROUP0 : SRAM GROUP0 powered down (64KB-96KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1 = 2, /*!< GROUP1 : SRAM GROUP1 powered down (96KB-128KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2 = 4, /*!< GROUP2 : SRAM GROUP2 powered down (128KB-160KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3 = 8, /*!< GROUP3 : SRAM GROUP3 powered down (160KB-192KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4 = 16, /*!< GROUP4 : SRAM GROUP4 powered down (192KB-224KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5 = 32, /*!< GROUP5 : SRAM GROUP5 powered down (224KB-256KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6 = 64, /*!< GROUP6 : SRAM GROUP6 powered down (256KB-288KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7 = 128,/*!< GROUP7 : SRAM GROUP7 powered down (288KB-320KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8 = 256,/*!< GROUP8 : SRAM GROUP8 powered down (320KB-352KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9 = 512,/*!< GROUP9 : SRAM GROUP9 powered down (352KB-384KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM64K = 3, /*!< SRAM64K : Powerdown lower 64k SRAM (64KB-128KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM128K = 15,/*!< SRAM128K : Powerdown lower 128k SRAM (64KB-192KB) */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER32K = 1022,/*!< ALLBUTLOWER32K : All SRAM banks but lower 32k powered down (96KB-384KB). */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER64K = 1020,/*!< ALLBUTLOWER64K : All banks but lower 64k powered down. */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER128K = 1008,/*!< ALLBUTLOWER128K : All banks but lower 128k powered down. */ + PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL = 1023, /*!< ALL : All banks powered down. */ +} PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Enum; + +/* ======================================== PWRCTRL MEMPWDINSLEEP DTCMPWDSLP [0..2] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_NONE = 0, /*!< NONE : All DTCM retained */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0 = 1,/*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM1 = 2,/*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-32KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0 = 3, /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep + (0KB-32KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down + in deep sleep (8KB-64KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP1 = 4, /*!< GROUP1 : Group1 DTCM powered down in deep sleep (32KB-64KB) */ + PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL = 7, /*!< ALL : All DTCMs powered down in deep sleep (0KB-64KB) */ +} PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Enum; + +/* ======================================================= MEMPWREN ======================================================== */ +/* =========================================== PWRCTRL MEMPWREN CACHEB2 [31..31] =========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB2 */ + PWRCTRL_MEMPWREN_CACHEB2_EN = 1, /*!< EN : Power up Cache Bank 2 */ + PWRCTRL_MEMPWREN_CACHEB2_DIS = 0, /*!< DIS : Power down Cache Bank 2 */ +} PWRCTRL_MEMPWREN_CACHEB2_Enum; + +/* =========================================== PWRCTRL MEMPWREN CACHEB0 [30..30] =========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB0 */ + PWRCTRL_MEMPWREN_CACHEB0_EN = 1, /*!< EN : Power up Cache Bank 0 */ + PWRCTRL_MEMPWREN_CACHEB0_DIS = 0, /*!< DIS : Power down Cache Bank 0 */ +} PWRCTRL_MEMPWREN_CACHEB0_Enum; + +/* =========================================== PWRCTRL MEMPWREN FLASH1 [14..14] ============================================ */ +typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH1 */ + PWRCTRL_MEMPWREN_FLASH1_EN = 1, /*!< EN : Power up Flash1 */ + PWRCTRL_MEMPWREN_FLASH1_DIS = 0, /*!< DIS : Power down Flash1 */ +} PWRCTRL_MEMPWREN_FLASH1_Enum; + +/* =========================================== PWRCTRL MEMPWREN FLASH0 [13..13] ============================================ */ +typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH0 */ + PWRCTRL_MEMPWREN_FLASH0_EN = 1, /*!< EN : Power up Flash0 */ + PWRCTRL_MEMPWREN_FLASH0_DIS = 0, /*!< DIS : Power down Flash0 */ +} PWRCTRL_MEMPWREN_FLASH0_Enum; + +/* ============================================= PWRCTRL MEMPWREN SRAM [3..12] ============================================= */ +typedef enum { /*!< PWRCTRL_MEMPWREN_SRAM */ + PWRCTRL_MEMPWREN_SRAM_NONE = 0, /*!< NONE : Do not power ON any of the SRAM banks */ + PWRCTRL_MEMPWREN_SRAM_GROUP0 = 1, /*!< GROUP0 : Power ON only SRAM group0 (0KB-32KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP1 = 2, /*!< GROUP1 : Power ON only SRAM group1 (32KB-64KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP2 = 4, /*!< GROUP2 : Power ON only SRAM group2 (64KB-96KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP3 = 8, /*!< GROUP3 : Power ON only SRAM group3 (96KB-128KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP4 = 16, /*!< GROUP4 : Power ON only SRAM group4 (128KB-160KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP5 = 32, /*!< GROUP5 : Power ON only SRAM group5 (160KB-192KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP6 = 64, /*!< GROUP6 : Power ON only SRAM group6 (192KB-224KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP7 = 128, /*!< GROUP7 : Power ON only SRAM group7 (224KB-256KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP8 = 256, /*!< GROUP8 : Power ON only SRAM group8 (256KB-288KB) */ + PWRCTRL_MEMPWREN_SRAM_GROUP9 = 512, /*!< GROUP9 : Power ON only SRAM group9 (288KB-320KB) */ + PWRCTRL_MEMPWREN_SRAM_SRAM64K = 3, /*!< SRAM64K : Power ON only lower 64k */ + PWRCTRL_MEMPWREN_SRAM_SRAM128K = 15, /*!< SRAM128K : Power ON only lower 128k */ + PWRCTRL_MEMPWREN_SRAM_SRAM256K = 255, /*!< SRAM256K : Power ON only lower 256k */ + PWRCTRL_MEMPWREN_SRAM_ALL = 1023, /*!< ALL : All SRAM banks (320K) powered ON */ +} PWRCTRL_MEMPWREN_SRAM_Enum; + +/* ============================================= PWRCTRL MEMPWREN DTCM [0..2] ============================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREN_DTCM */ + PWRCTRL_MEMPWREN_DTCM_NONE = 0, /*!< NONE : Do not enable power to any DTCMs */ + PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0 = 1, /*!< GROUP0DTCM0 : Power ON only GROUP0_DTCM0 */ + PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM1 = 2, /*!< GROUP0DTCM1 : Power ON only GROUP0_DTCM1 */ + PWRCTRL_MEMPWREN_DTCM_GROUP0 = 3, /*!< GROUP0 : Power ON only DTCMs in group0 */ + PWRCTRL_MEMPWREN_DTCM_GROUP1 = 4, /*!< GROUP1 : Power ON only DTCMs in group1 */ + PWRCTRL_MEMPWREN_DTCM_ALL = 7, /*!< ALL : Power ON all DTCMs */ +} PWRCTRL_MEMPWREN_DTCM_Enum; + +/* ===================================================== MEMPWRSTATUS ====================================================== */ +/* ===================================================== DEVPWRSTATUS ====================================================== */ +/* ======================================================= SRAMCTRL ======================================================== */ +/* ======================================== PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19] ======================================== */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP */ + PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL = 255, /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs */ + PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS = 0, /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs */ +} PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum; + +/* ======================================= PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2] ======================================= */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE */ + PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1, /*!< EN : Enable Master SRAM Clock Gate */ + PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0, /*!< DIS : Disables Master SRAM Clock Gating */ +} PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum; + +/* ========================================== PWRCTRL SRAMCTRL SRAMCLKGATE [1..1] ========================================== */ +typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE */ + PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN = 1, /*!< EN : Enable Individual SRAM Clock Gating */ + PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS = 0, /*!< DIS : Disables Individual SRAM Clock Gating */ +} PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum; + +/* ======================================================= ADCSTATUS ======================================================= */ +/* ========================================================= MISC ========================================================== */ +/* ============================================ PWRCTRL MISC MEMVRLPBLE [6..6] ============================================= */ +typedef enum { /*!< PWRCTRL_MISC_MEMVRLPBLE */ + PWRCTRL_MISC_MEMVRLPBLE_EN = 1, /*!< EN : Mem VR can go to lp mode even when BLE is powered on. */ + PWRCTRL_MISC_MEMVRLPBLE_DIS = 0, /*!< DIS : Mem VR will stay in active mode when BLE is powered on. */ +} PWRCTRL_MISC_MEMVRLPBLE_Enum; + +/* ===================================================== DEVPWREVENTEN ===================================================== */ +/* ======================================= PWRCTRL DEVPWREVENTEN BURSTEVEN [31..31] ======================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTEVEN */ + PWRCTRL_DEVPWREVENTEN_BURSTEVEN_EN = 1, /*!< EN : Enable BURST status event */ + PWRCTRL_DEVPWREVENTEN_BURSTEVEN_DIS = 0, /*!< DIS : Disable BURST status event */ +} PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Enum; + +/* ==================================== PWRCTRL DEVPWREVENTEN BURSTFEATUREEVEN [30..30] ==================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN */ + PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_EN = 1,/*!< EN : Enable BURSTFEATURE status event */ + PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_DIS = 0,/*!< DIS : Disable BURSTFEATURE status event */ +} PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Enum; + +/* ===================================== PWRCTRL DEVPWREVENTEN BLEFEATUREEVEN [29..29] ===================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN */ + PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_EN = 1, /*!< EN : Enable BLEFEATURE status event */ + PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_DIS = 0, /*!< DIS : Disable BLEFEATURE status event */ +} PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN BLELEVEN [8..8] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLELEVEN */ + PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN = 1, /*!< EN : Enable BLE power-on status event */ + PWRCTRL_DEVPWREVENTEN_BLELEVEN_DIS = 0, /*!< DIS : Disable BLE power-on status event */ +} PWRCTRL_DEVPWREVENTEN_BLELEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN PDMEVEN [7..7] ========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_PDMEVEN */ + PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN = 1, /*!< EN : Enable PDM power-on status event */ + PWRCTRL_DEVPWREVENTEN_PDMEVEN_DIS = 0, /*!< DIS : Disable PDM power-on status event */ +} PWRCTRL_DEVPWREVENTEN_PDMEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN */ + PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN = 1, /*!< EN : Enable MSPI power-on status event */ + PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS = 0, /*!< DIS : Disable MSPI power-on status event */ +} PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN ADCEVEN [5..5] ========================================== */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN */ + PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN = 1, /*!< EN : Enable ADC power-on status event */ + PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS = 0, /*!< DIS : Disable ADC power-on status event */ +} PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN */ + PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN = 1, /*!< EN : Enable HCPC power-on status event */ + PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS = 0, /*!< DIS : Disable HCPC power-on status event */ +} PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN */ + PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN = 1, /*!< EN : Enable HCPB power-on status event */ + PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS = 0, /*!< DIS : Disable HCPB power-on status event */ +} PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN */ + PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN = 1, /*!< EN : Enable HCPA power-on status event */ + PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS = 0, /*!< DIS : Disable HCPA power-on status event */ +} PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN */ + PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN = 1, /*!< EN : Enable MCHU power-on status event */ + PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS = 0, /*!< DIS : Disable MCUH power-on status event */ +} PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum; + +/* ========================================= PWRCTRL DEVPWREVENTEN MCULEVEN [0..0] ========================================= */ +typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN */ + PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN = 1, /*!< EN : Enable MCUL power-on status event */ + PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS = 0, /*!< DIS : Disable MCUL power-on status event */ +} PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum; + +/* ===================================================== MEMPWREVENTEN ===================================================== */ +/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB2EN [31..31] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN */ + PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN = 1, /*!< EN : Enable CACHE BANK 2 status event */ + PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS = 0, /*!< DIS : Disable CACHE BANK 2 status event */ +} PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum; + +/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB0EN [30..30] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN */ + PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN = 1, /*!< EN : Enable CACHE BANK 0 status event */ + PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS = 0, /*!< DIS : Disable CACHE BANK 0 status event */ +} PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum; + +/* ======================================== PWRCTRL MEMPWREVENTEN FLASH1EN [14..14] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH1EN */ + PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN = 1, /*!< EN : Enable FLASH status event */ + PWRCTRL_MEMPWREVENTEN_FLASH1EN_DIS = 0, /*!< DIS : Disables FLASH status event */ +} PWRCTRL_MEMPWREVENTEN_FLASH1EN_Enum; + +/* ======================================== PWRCTRL MEMPWREVENTEN FLASH0EN [13..13] ======================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH0EN */ + PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN = 1, /*!< EN : Enable FLASH status event */ + PWRCTRL_MEMPWREVENTEN_FLASH0EN_DIS = 0, /*!< DIS : Disables FLASH status event */ +} PWRCTRL_MEMPWREVENTEN_FLASH0EN_Enum; + +/* ========================================= PWRCTRL MEMPWREVENTEN SRAMEN [3..12] ========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_SRAMEN */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_NONE = 0, /*!< NONE : Disable SRAM power-on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN = 1, /*!< GROUP0EN : Enable SRAM group0 (0KB-32KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN = 2, /*!< GROUP1EN : Enable SRAM group1 (32KB-64KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN = 4, /*!< GROUP2EN : Enable SRAM group2 (64KB-96KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN = 8, /*!< GROUP3EN : Enable SRAM group3 (96KB-128KB) power on status event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN = 16, /*!< GROUP4EN : Enable SRAM group4 (128KB-160KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN = 32, /*!< GROUP5EN : Enable SRAM group5 (160KB-192KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN = 64, /*!< GROUP6EN : Enable SRAM group6 (192KB-224KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN = 128, /*!< GROUP7EN : Enable SRAM group7 (224KB-256KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN = 256, /*!< GROUP8EN : Enable SRAM group8 (256KB-288KB) power on status + event */ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN = 512, /*!< GROUP9EN : Enable SRAM group9 (288KB-320KB) power on status + event */ +} PWRCTRL_MEMPWREVENTEN_SRAMEN_Enum; + +/* ========================================== PWRCTRL MEMPWREVENTEN DTCMEN [0..2] ========================================== */ +typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE = 0, /*!< NONE : Do not enable DTCM power-on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3, /*!< GROUP0EN : Enable DTCMs in group0 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4, /*!< GROUP1EN : Enable DTCMs in group1 power on status event */ + PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL = 7, /*!< ALL : Enable all DTCM power on status event */ +} PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum; + + + +/* =========================================================================================================================== */ +/* ================ RSTGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ========================================================= SWPOI ========================================================= */ +/* ============================================= RSTGEN SWPOI SWPOIKEY [0..7] ============================================== */ +typedef enum { /*!< RSTGEN_SWPOI_SWPOIKEY */ + RSTGEN_SWPOI_SWPOIKEY_KEYVALUE = 27, /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset. */ +} RSTGEN_SWPOI_SWPOIKEY_Enum; + +/* ========================================================= SWPOR ========================================================= */ +/* ============================================= RSTGEN SWPOR SWPORKEY [0..7] ============================================== */ +typedef enum { /*!< RSTGEN_SWPOR_SWPORKEY */ + RSTGEN_SWPOR_SWPORKEY_KEYVALUE = 212, /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset. */ +} RSTGEN_SWPOR_SWPORKEY_Enum; + +/* ======================================================== TPIURST ======================================================== */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ +/* ========================================================= STAT ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLOW ========================================================= */ +/* ========================================================= CTRUP ========================================================= */ +/* =============================================== RTC CTRUP CTERR [31..31] ================================================ */ +typedef enum { /*!< RTC_CTRUP_CTERR */ + RTC_CTRUP_CTERR_NOERR = 0, /*!< NOERR : No read error occurred */ + RTC_CTRUP_CTERR_RDERR = 1, /*!< RDERR : Read error occurred */ +} RTC_CTRUP_CTERR_Enum; + +/* ================================================ RTC CTRUP CEB [28..28] ================================================= */ +typedef enum { /*!< RTC_CTRUP_CEB */ + RTC_CTRUP_CEB_DIS = 0, /*!< DIS : Disable the Century bit from changing */ + RTC_CTRUP_CEB_EN = 1, /*!< EN : Enable the Century bit to change */ +} RTC_CTRUP_CEB_Enum; + +/* ================================================= RTC CTRUP CB [27..27] ================================================= */ +typedef enum { /*!< RTC_CTRUP_CB */ + RTC_CTRUP_CB_2000 = 0, /*!< 2000 : Century is 2000s */ + RTC_CTRUP_CB_1900_2100 = 1, /*!< 1900_2100 : Century is 1900s/2100s */ +} RTC_CTRUP_CB_Enum; + +/* ======================================================== ALMLOW ========================================================= */ +/* ========================================================= ALMUP ========================================================= */ +/* ======================================================== RTCCTL ========================================================= */ +/* =============================================== RTC RTCCTL HR1224 [5..5] ================================================ */ +typedef enum { /*!< RTC_RTCCTL_HR1224 */ + RTC_RTCCTL_HR1224_24HR = 0, /*!< 24HR : Hours in 24 hour mode */ + RTC_RTCCTL_HR1224_12HR = 1, /*!< 12HR : Hours in 12 hour mode */ +} RTC_RTCCTL_HR1224_Enum; + +/* ================================================ RTC RTCCTL RSTOP [4..4] ================================================ */ +typedef enum { /*!< RTC_RTCCTL_RSTOP */ + RTC_RTCCTL_RSTOP_RUN = 0, /*!< RUN : Allow the RTC input clock to run */ + RTC_RTCCTL_RSTOP_STOP = 1, /*!< STOP : Stop the RTC input clock */ +} RTC_RTCCTL_RSTOP_Enum; + +/* ================================================= RTC RTCCTL RPT [1..3] ================================================= */ +typedef enum { /*!< RTC_RTCCTL_RPT */ + RTC_RTCCTL_RPT_DIS = 0, /*!< DIS : Alarm interrupt disabled */ + RTC_RTCCTL_RPT_YEAR = 1, /*!< YEAR : Interrupt every year */ + RTC_RTCCTL_RPT_MONTH = 2, /*!< MONTH : Interrupt every month */ + RTC_RTCCTL_RPT_WEEK = 3, /*!< WEEK : Interrupt every week */ + RTC_RTCCTL_RPT_DAY = 4, /*!< DAY : Interrupt every day */ + RTC_RTCCTL_RPT_HR = 5, /*!< HR : Interrupt every hour */ + RTC_RTCCTL_RPT_MIN = 6, /*!< MIN : Interrupt every minute */ + RTC_RTCCTL_RPT_SEC = 7, /*!< SEC : Interrupt every second/10th/100th */ +} RTC_RTCCTL_RPT_Enum; + +/* ================================================ RTC RTCCTL WRTC [0..0] ================================================= */ +typedef enum { /*!< RTC_RTCCTL_WRTC */ + RTC_RTCCTL_WRTC_DIS = 0, /*!< DIS : Counter writes are disabled */ + RTC_RTCCTL_WRTC_EN = 1, /*!< EN : Counter writes are enabled */ +} RTC_RTCCTL_WRTC_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ SCARD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SR =========================================================== */ +/* ================================================== SCARD SR FHF [6..6] ================================================== */ +typedef enum { /*!< SCARD_SR_FHF */ + SCARD_SR_FHF_HALFFULL = 1, /*!< HALFFULL : FIFO is half full. */ +} SCARD_SR_FHF_Enum; + +/* ================================================ SCARD SR FT2REND [5..5] ================================================ */ +typedef enum { /*!< SCARD_SR_FT2REND */ + SCARD_SR_FT2REND_CMPL = 1, /*!< CMPL : TX to RX completed. */ + SCARD_SR_FT2REND_NOTCMPL = 0, /*!< NOTCMPL : TX to RX not completed. */ +} SCARD_SR_FT2REND_Enum; + +/* ================================================== SCARD SR PE [4..4] =================================================== */ +typedef enum { /*!< SCARD_SR_PE */ + SCARD_SR_PE_PEERR = 1, /*!< PEERR : Parity error. */ + SCARD_SR_PE_PENONE = 0, /*!< PENONE : No parity error. */ +} SCARD_SR_PE_Enum; + +/* ================================================== SCARD SR OVR [3..3] ================================================== */ +typedef enum { /*!< SCARD_SR_OVR */ + SCARD_SR_OVR_RXOVR = 1, /*!< RXOVR : RX FIFO overflow. */ + SCARD_SR_OVR_RXOVRNONE = 0, /*!< RXOVRNONE : RX FIFO no overflow. */ +} SCARD_SR_OVR_Enum; + +/* ================================================== SCARD SR FER [2..2] ================================================== */ +typedef enum { /*!< SCARD_SR_FER */ + SCARD_SR_FER_FRAMINGERR = 1, /*!< FRAMINGERR : Framing error. */ + SCARD_SR_FER_NOFRAMINGERR = 0, /*!< NOFRAMINGERR : No framing error detected. */ +} SCARD_SR_FER_Enum; + +/* ================================================ SCARD SR TBERBF [1..1] ================================================= */ +typedef enum { /*!< SCARD_SR_TBERBF */ + SCARD_SR_TBERBF_TXFIFOEMPTY = 1, /*!< TXFIFOEMPTY : Transmit: FIFO empty. */ + SCARD_SR_TBERBF_TXFIFONOTEMPTY = 0, /*!< TXFIFONOTEMPTY : Transmit: FIFO not empty. */ +} SCARD_SR_TBERBF_Enum; + +/* ================================================== SCARD SR FNE [0..0] ================================================== */ +typedef enum { /*!< SCARD_SR_FNE */ + SCARD_SR_FNE_NOTEMPTY = 1, /*!< NOTEMPTY : RX FIFO not empty. */ + SCARD_SR_FNE_EMPTY = 0, /*!< EMPTY : RX FIFO empty. */ +} SCARD_SR_FNE_Enum; + +/* ========================================================== IER ========================================================== */ +/* ========================================================== TCR ========================================================== */ +/* ========================================================== UCR ========================================================== */ +/* ========================================================== DR =========================================================== */ +/* ========================================================= BPRL ========================================================== */ +/* ========================================================= BPRH ========================================================== */ +/* ========================================================= UCR1 ========================================================== */ +/* ========================================================== SR1 ========================================================== */ +/* ================================================= SCARD SR1 IDLE [3..3] ================================================= */ +typedef enum { /*!< SCARD_SR1_IDLE */ + SCARD_SR1_IDLE_IDLE = 1, /*!< IDLE : ISO7816 idle. */ + SCARD_SR1_IDLE_ACTIVE = 0, /*!< ACTIVE : ISO7816 active. */ +} SCARD_SR1_IDLE_Enum; + +/* =============================================== SCARD SR1 SYNCEND [2..2] ================================================ */ +typedef enum { /*!< SCARD_SR1_SYNCEND */ + SCARD_SR1_SYNCEND_CMPL = 1, /*!< CMPL : Synchronization complete. */ + SCARD_SR1_SYNCEND_INCMPL = 0, /*!< INCMPL : Incomplete. */ +} SCARD_SR1_SYNCEND_Enum; + +/* ================================================= SCARD SR1 PRL [1..1] ================================================== */ +typedef enum { /*!< SCARD_SR1_PRL */ + SCARD_SR1_PRL_INSREM = 1, /*!< INSREM : Card inserted/removed. */ +} SCARD_SR1_PRL_Enum; + +/* =============================================== SCARD SR1 ECNTOVER [0..0] =============================================== */ +typedef enum { /*!< SCARD_SR1_ECNTOVER */ + SCARD_SR1_ECNTOVER_OVR = 1, /*!< OVR : ETU overflow. */ +} SCARD_SR1_ECNTOVER_Enum; + +/* ========================================================= IER1 ========================================================== */ +/* ========================================================= ECNTL ========================================================= */ +/* ========================================================= ECNTH ========================================================= */ +/* ========================================================== GTR ========================================================== */ +/* ======================================================== RETXCNT ======================================================== */ +/* ====================================================== RETXCNTRMI ======================================================= */ +/* ======================================================== CLKCTRL ======================================================== */ + + +/* =========================================================================================================================== */ +/* ================ SECURITY ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +/* ============================================= SECURITY CTRL FUNCTION [4..7] ============================================= */ +typedef enum { /*!< SECURITY_CTRL_FUNCTION */ + SECURITY_CTRL_FUNCTION_CRC32 = 0, /*!< CRC32 : Perform CRC32 operation */ +} SECURITY_CTRL_FUNCTION_Enum; + +/* ======================================================== SRCADDR ======================================================== */ +/* ========================================================== LEN ========================================================== */ +/* ======================================================== RESULT ========================================================= */ +/* ======================================================= LOCKCTRL ======================================================== */ +/* ============================================ SECURITY LOCKCTRL SELECT [0..7] ============================================ */ +typedef enum { /*!< SECURITY_LOCKCTRL_SELECT */ + SECURITY_LOCKCTRL_SELECT_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Unlock Customer Key (access to top half of info0) */ + SECURITY_LOCKCTRL_SELECT_NONE = 0, /*!< NONE : Lock Control should be set to NONE when not in use. */ +} SECURITY_LOCKCTRL_SELECT_Enum; + +/* ======================================================= LOCKSTAT ======================================================== */ +/* =========================================== SECURITY LOCKSTAT STATUS [0..31] ============================================ */ +typedef enum { /*!< SECURITY_LOCKSTAT_STATUS */ + SECURITY_LOCKSTAT_STATUS_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Customer Key is unlocked (access is granted to + top half of info0) */ + SECURITY_LOCKSTAT_STATUS_NONE = 0, /*!< NONE : No resources are unlocked */ +} SECURITY_LOCKSTAT_STATUS_Enum; + +/* ========================================================= KEY0 ========================================================== */ +/* ========================================================= KEY1 ========================================================== */ +/* ========================================================= KEY2 ========================================================== */ +/* ========================================================= KEY3 ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DR =========================================================== */ +/* =============================================== UART0 DR OEDATA [11..11] ================================================ */ +typedef enum { /*!< UART0_DR_OEDATA */ + UART0_DR_OEDATA_NOERR = 0, /*!< NOERR : No error on UART OEDATA, overrun error indicator. */ + UART0_DR_OEDATA_ERR = 1, /*!< ERR : Error on UART OEDATA, overrun error indicator. */ +} UART0_DR_OEDATA_Enum; + +/* =============================================== UART0 DR BEDATA [10..10] ================================================ */ +typedef enum { /*!< UART0_DR_BEDATA */ + UART0_DR_BEDATA_NOERR = 0, /*!< NOERR : No error on UART BEDATA, break error indicator. */ + UART0_DR_BEDATA_ERR = 1, /*!< ERR : Error on UART BEDATA, break error indicator. */ +} UART0_DR_BEDATA_Enum; + +/* ================================================ UART0 DR PEDATA [9..9] ================================================= */ +typedef enum { /*!< UART0_DR_PEDATA */ + UART0_DR_PEDATA_NOERR = 0, /*!< NOERR : No error on UART PEDATA, parity error indicator. */ + UART0_DR_PEDATA_ERR = 1, /*!< ERR : Error on UART PEDATA, parity error indicator. */ +} UART0_DR_PEDATA_Enum; + +/* ================================================ UART0 DR FEDATA [8..8] ================================================= */ +typedef enum { /*!< UART0_DR_FEDATA */ + UART0_DR_FEDATA_NOERR = 0, /*!< NOERR : No error on UART FEDATA, framing error indicator. */ + UART0_DR_FEDATA_ERR = 1, /*!< ERR : Error on UART FEDATA, framing error indicator. */ +} UART0_DR_FEDATA_Enum; + +/* ========================================================== RSR ========================================================== */ +/* ================================================ UART0 RSR OESTAT [3..3] ================================================ */ +typedef enum { /*!< UART0_RSR_OESTAT */ + UART0_RSR_OESTAT_NOERR = 0, /*!< NOERR : No error on UART OESTAT, overrun error indicator. */ + UART0_RSR_OESTAT_ERR = 1, /*!< ERR : Error on UART OESTAT, overrun error indicator. */ +} UART0_RSR_OESTAT_Enum; + +/* ================================================ UART0 RSR BESTAT [2..2] ================================================ */ +typedef enum { /*!< UART0_RSR_BESTAT */ + UART0_RSR_BESTAT_NOERR = 0, /*!< NOERR : No error on UART BESTAT, break error indicator. */ + UART0_RSR_BESTAT_ERR = 1, /*!< ERR : Error on UART BESTAT, break error indicator. */ +} UART0_RSR_BESTAT_Enum; + +/* ================================================ UART0 RSR PESTAT [1..1] ================================================ */ +typedef enum { /*!< UART0_RSR_PESTAT */ + UART0_RSR_PESTAT_NOERR = 0, /*!< NOERR : No error on UART PESTAT, parity error indicator. */ + UART0_RSR_PESTAT_ERR = 1, /*!< ERR : Error on UART PESTAT, parity error indicator. */ +} UART0_RSR_PESTAT_Enum; + +/* ================================================ UART0 RSR FESTAT [0..0] ================================================ */ +typedef enum { /*!< UART0_RSR_FESTAT */ + UART0_RSR_FESTAT_NOERR = 0, /*!< NOERR : No error on UART FESTAT, framing error indicator. */ + UART0_RSR_FESTAT_ERR = 1, /*!< ERR : Error on UART FESTAT, framing error indicator. */ +} UART0_RSR_FESTAT_Enum; + +/* ========================================================== FR =========================================================== */ +/* ================================================= UART0 FR TXFE [7..7] ================================================== */ +typedef enum { /*!< UART0_FR_TXFE */ + UART0_FR_TXFE_XMTFIFO_EMPTY = 1, /*!< XMTFIFO_EMPTY : Transmit fifo is empty. */ +} UART0_FR_TXFE_Enum; + +/* ================================================= UART0 FR RXFF [6..6] ================================================== */ +typedef enum { /*!< UART0_FR_RXFF */ + UART0_FR_RXFF_RCVFIFO_FULL = 1, /*!< RCVFIFO_FULL : Receive fifo is full. */ +} UART0_FR_RXFF_Enum; + +/* ================================================= UART0 FR TXFF [5..5] ================================================== */ +typedef enum { /*!< UART0_FR_TXFF */ + UART0_FR_TXFF_XMTFIFO_FULL = 1, /*!< XMTFIFO_FULL : Transmit fifo is full. */ +} UART0_FR_TXFF_Enum; + +/* ================================================= UART0 FR RXFE [4..4] ================================================== */ +typedef enum { /*!< UART0_FR_RXFE */ + UART0_FR_RXFE_RCVFIFO_EMPTY = 1, /*!< RCVFIFO_EMPTY : Receive fifo is empty. */ +} UART0_FR_RXFE_Enum; + +/* ================================================= UART0 FR BUSY [3..3] ================================================== */ +typedef enum { /*!< UART0_FR_BUSY */ + UART0_FR_BUSY_BUSY = 1, /*!< BUSY : UART busy indicator. */ +} UART0_FR_BUSY_Enum; + +/* ================================================== UART0 FR DCD [2..2] ================================================== */ +typedef enum { /*!< UART0_FR_DCD */ + UART0_FR_DCD_DETECTED = 1, /*!< DETECTED : Data carrier detect detected. */ +} UART0_FR_DCD_Enum; + +/* ================================================== UART0 FR DSR [1..1] ================================================== */ +typedef enum { /*!< UART0_FR_DSR */ + UART0_FR_DSR_READY = 1, /*!< READY : Data set ready. */ +} UART0_FR_DSR_Enum; + +/* ================================================== UART0 FR CTS [0..0] ================================================== */ +typedef enum { /*!< UART0_FR_CTS */ + UART0_FR_CTS_CLEARTOSEND = 1, /*!< CLEARTOSEND : Clear to send is indicated. */ +} UART0_FR_CTS_Enum; + +/* ========================================================= ILPR ========================================================== */ +/* ========================================================= IBRD ========================================================== */ +/* ========================================================= FBRD ========================================================== */ +/* ========================================================= LCRH ========================================================== */ +/* ========================================================== CR =========================================================== */ +/* ================================================ UART0 CR CLKSEL [4..6] ================================================= */ +typedef enum { /*!< UART0_CR_CLKSEL */ + UART0_CR_CLKSEL_NOCLK = 0, /*!< NOCLK : No UART clock. This is the low power default. */ + UART0_CR_CLKSEL_24MHZ = 1, /*!< 24MHZ : 24 MHz clock. */ + UART0_CR_CLKSEL_12MHZ = 2, /*!< 12MHZ : 12 MHz clock. */ + UART0_CR_CLKSEL_6MHZ = 3, /*!< 6MHZ : 6 MHz clock. */ + UART0_CR_CLKSEL_3MHZ = 4, /*!< 3MHZ : 3 MHz clock. */ +} UART0_CR_CLKSEL_Enum; + +/* ========================================================= IFLS ========================================================== */ +/* ========================================================== IER ========================================================== */ +/* ========================================================== IES ========================================================== */ +/* ========================================================== MIS ========================================================== */ +/* ========================================================== IEC ========================================================== */ + + +/* =========================================================================================================================== */ +/* ================ VCOMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* =============================================== VCOMP CFG LVLSEL [16..19] =============================================== */ +typedef enum { /*!< VCOMP_CFG_LVLSEL */ + VCOMP_CFG_LVLSEL_0P58V = 0, /*!< 0P58V : Set Reference input to 0.58 Volts. */ + VCOMP_CFG_LVLSEL_0P77V = 1, /*!< 0P77V : Set Reference input to 0.77 Volts. */ + VCOMP_CFG_LVLSEL_0P97V = 2, /*!< 0P97V : Set Reference input to 0.97 Volts. */ + VCOMP_CFG_LVLSEL_1P16V = 3, /*!< 1P16V : Set Reference input to 1.16 Volts. */ + VCOMP_CFG_LVLSEL_1P35V = 4, /*!< 1P35V : Set Reference input to 1.35 Volts. */ + VCOMP_CFG_LVLSEL_1P55V = 5, /*!< 1P55V : Set Reference input to 1.55 Volts. */ + VCOMP_CFG_LVLSEL_1P74V = 6, /*!< 1P74V : Set Reference input to 1.74 Volts. */ + VCOMP_CFG_LVLSEL_1P93V = 7, /*!< 1P93V : Set Reference input to 1.93 Volts. */ + VCOMP_CFG_LVLSEL_2P13V = 8, /*!< 2P13V : Set Reference input to 2.13 Volts. */ + VCOMP_CFG_LVLSEL_2P32V = 9, /*!< 2P32V : Set Reference input to 2.32 Volts. */ + VCOMP_CFG_LVLSEL_2P51V = 10, /*!< 2P51V : Set Reference input to 2.51 Volts. */ + VCOMP_CFG_LVLSEL_2P71V = 11, /*!< 2P71V : Set Reference input to 2.71 Volts. */ + VCOMP_CFG_LVLSEL_2P90V = 12, /*!< 2P90V : Set Reference input to 2.90 Volts. */ + VCOMP_CFG_LVLSEL_3P09V = 13, /*!< 3P09V : Set Reference input to 3.09 Volts. */ + VCOMP_CFG_LVLSEL_3P29V = 14, /*!< 3P29V : Set Reference input to 3.29 Volts. */ + VCOMP_CFG_LVLSEL_3P48V = 15, /*!< 3P48V : Set Reference input to 3.48 Volts. */ +} VCOMP_CFG_LVLSEL_Enum; + +/* ================================================= VCOMP CFG NSEL [8..9] ================================================= */ +typedef enum { /*!< VCOMP_CFG_NSEL */ + VCOMP_CFG_NSEL_VREFEXT1 = 0, /*!< VREFEXT1 : Use external reference 1 for reference input. */ + VCOMP_CFG_NSEL_VREFEXT2 = 1, /*!< VREFEXT2 : Use external reference 2 for reference input. */ + VCOMP_CFG_NSEL_VREFEXT3 = 2, /*!< VREFEXT3 : Use external reference 3 for reference input. */ + VCOMP_CFG_NSEL_DAC = 3, /*!< DAC : Use DAC output selected by LVLSEL for reference input. */ +} VCOMP_CFG_NSEL_Enum; + +/* ================================================= VCOMP CFG PSEL [0..1] ================================================= */ +typedef enum { /*!< VCOMP_CFG_PSEL */ + VCOMP_CFG_PSEL_VDDADJ = 0, /*!< VDDADJ : Use VDDADJ for the positive input. */ + VCOMP_CFG_PSEL_VTEMP = 1, /*!< VTEMP : Use the temperature sensor output for the positive input. + Note: If this channel is selected for PSEL, the bandap + circuit required for temperature comparisons will automatically + turn on. The bandgap circuit requires 11us to stabalize. */ + VCOMP_CFG_PSEL_VEXT1 = 2, /*!< VEXT1 : Use external voltage 0 for positive input. */ + VCOMP_CFG_PSEL_VEXT2 = 3, /*!< VEXT2 : Use external voltage 1 for positive input. */ +} VCOMP_CFG_PSEL_Enum; + +/* ========================================================= STAT ========================================================== */ +/* =============================================== VCOMP STAT PWDSTAT [1..1] =============================================== */ +typedef enum { /*!< VCOMP_STAT_PWDSTAT */ + VCOMP_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : The voltage comparator is powered down. */ +} VCOMP_STAT_PWDSTAT_Enum; + +/* =============================================== VCOMP STAT CMPOUT [0..0] ================================================ */ +typedef enum { /*!< VCOMP_STAT_CMPOUT */ + VCOMP_STAT_CMPOUT_VOUT_LOW = 0, /*!< VOUT_LOW : The negative input of the comparator is greater than + the positive input. */ + VCOMP_STAT_CMPOUT_VOUT_HIGH = 1, /*!< VOUT_HIGH : The positive input of the comparator is greater + than the negative input. */ +} VCOMP_STAT_CMPOUT_Enum; + +/* ======================================================== PWDKEY ========================================================= */ +/* ============================================== VCOMP PWDKEY PWDKEY [0..31] ============================================== */ +typedef enum { /*!< VCOMP_PWDKEY_PWDKEY */ + VCOMP_PWDKEY_PWDKEY_Key = 55, /*!< Key : Key */ +} VCOMP_PWDKEY_PWDKEY_Enum; + +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +/* ================================================ WDT CFG CLKSEL [24..26] ================================================ */ +typedef enum { /*!< WDT_CFG_CLKSEL */ + WDT_CFG_CLKSEL_OFF = 0, /*!< OFF : Low Power Mode. This setting disables the watch dog timer. */ + WDT_CFG_CLKSEL_128HZ = 1, /*!< 128HZ : 128 Hz LFRC clock. */ + WDT_CFG_CLKSEL_16HZ = 2, /*!< 16HZ : 16 Hz LFRC clock. */ + WDT_CFG_CLKSEL_1HZ = 3, /*!< 1HZ : 1 Hz LFRC clock. */ + WDT_CFG_CLKSEL_1_16HZ = 4, /*!< 1_16HZ : 1/16th Hz LFRC clock. */ +} WDT_CFG_CLKSEL_Enum; + +/* ========================================================= RSTRT ========================================================= */ +/* ================================================ WDT RSTRT RSTRT [0..7] ================================================= */ +typedef enum { /*!< WDT_RSTRT_RSTRT */ + WDT_RSTRT_RSTRT_KEYVALUE = 178, /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart + the WDT. This is a write only register. */ +} WDT_RSTRT_RSTRT_Enum; + +/* ========================================================= LOCK ========================================================== */ +/* ================================================= WDT LOCK LOCK [0..7] ================================================== */ +typedef enum { /*!< WDT_LOCK_LOCK */ + WDT_LOCK_LOCK_KEYVALUE = 58, /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock + the WDT. */ +} WDT_LOCK_LOCK_Enum; + +/* ========================================================= COUNT ========================================================= */ +/* ========================================================= INTEN ========================================================= */ +/* ======================================================== INTSTAT ======================================================== */ +/* ======================================================== INTCLR ========================================================= */ +/* ======================================================== INTSET ========================================================= */ + +/** @} */ /* End of group EnumValue_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#ifdef OVERFLOW_RESTORE +#define OVERFLOW OVERFLOW_RESTORE +#undef OVERFLOW_RESTORE +#endif // OVERFLOW_RESTORE + +#endif /* APOLLO3_H */ + + +/** @} */ /* End of group apollo3 */ + +/** @} */ /* End of group Ambiq Micro */ diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/system_apollo3.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/system_apollo3.h new file mode 100644 index 0000000000..3ddfb26050 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Include/system_apollo3.h @@ -0,0 +1,70 @@ +//***************************************************************************** +// +//! @file system_Apollo3.h +//! +//! @brief Ambiq Micro Apollo3 MCU specific functions. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef SYSTEM_APOLLO3_H +#define SYSTEM_APOLLO3_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void SystemInit (void); +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif // SYSTEM_APOLLO3_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Source/system_apollo3.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Source/system_apollo3.c new file mode 100644 index 0000000000..896e54e928 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/AmbiqMicro/Source/system_apollo3.c @@ -0,0 +1,114 @@ +//***************************************************************************** +// +//! @file system_apollo3.c +//! +//! @brief Ambiq Micro Apollo3 MCU specific functions. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include "system_apollo3.h" +#include "apollo3.h" + +//***************************************************************************** +// +// Defines +// +//***************************************************************************** + +// +// Clocks +// +#define __HSI (6000000UL) +#define __XTAL (32768UL) // Crystal Oscillator frequency +#define __SYS_OSC_CLK (48000000) // Main oscillator frequency +#define __SYSTEM_CLOCK (1*__SYS_OSC_CLK) + +// +// Initialize SystemCoreClock with the system core clock frequency value +// achieved after system intitialization. +// This means system core clock frequency after call to SystemInit() +// +uint32_t SystemCoreClock = __SYSTEM_CLOCK; // System Clock Frequency (Core Clock) + +//***************************************************************************** +// +//! @brief Set the global clock frequncy. +//! +//! This function sets the global clock frequency. +//! +//! @return None. +// +//***************************************************************************** +void +SystemCoreClockUpdate(void) +{ + // + // Calculate the system frequency based upon the current register settings. + // This function can be used to retrieve the system core clock frequeny + // after user changed register sittings. + // + SystemCoreClock = __SYS_OSC_CLK / (CLKGEN->CCTRL_b.CORESEL + 1); +} + +//***************************************************************************** +// +//! @brief Initialize the system. +//! +//! This function sets up the microcontroller system. +//! +//! @return None. +// +//***************************************************************************** +void +SystemInit(void) +{ + // + // Initialize the system + // Do not use global variables because this function is called before + // reaching pre-main. RW section maybe overwritten afterwards. + // + SystemCoreClock = __SYSTEM_CLOCK; + + CLKGEN->CLKKEY = 0x47; // Enable write to CCTRL + CLKGEN->CCTRL_b.CORESEL = 0; // Div by 1 for 48MHz + CLKGEN->CLKKEY = 0; // Disable write to CCTRL +} + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/version_cmsis_info.txt b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/version_cmsis_info.txt new file mode 100644 index 0000000000..d78a88cc85 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/CMSIS/version_cmsis_info.txt @@ -0,0 +1,24 @@ + +Last updated: August 15, 2019 + +This file contains origination information about the various +CMSIS header and library files located in this folder. + + +ARM/Include/: +AmbiqSuite SDK file: Pack Origination: +cmsis*.h CMSIS/5.6.0/CMSIS/Core/Include/ +core_cm4.h CMSIS/5.6.0/CMSIS/Core/Include/ +mpu_armv7.h CMSIS/5.6.0/CMSIS/Core/Include/ +arm_math.h CMSIS/5.6.0/CMSIS/Include/ + + +ARM/Lib/ARM/: +AmbiqSuite SDK file: Pack Origination: +arm_cortexM4lf_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/ +arm_cortexM4l_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/ +libarm_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/ +libarm_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/ +iar_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/ +iar_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/ + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/am_sdk_version.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/am_sdk_version.h new file mode 100644 index 0000000000..a346225b60 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/am_sdk_version.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// am_sdk_version.h +//! @file +//! +//! @brief Defines SDK version. +//! +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_SDK_VERSION_H +#define AM_SDK_VERSION_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros to define HAL SDK version. +// +//***************************************************************************** +// +// Define the current HAL version. +// +#ifndef AM_HAL_VERSION_MAJ +#define AM_HAL_VERSION_MAJ 2 +#define AM_HAL_VERSION_MIN 4 +#define AM_HAL_VERSION_REV 2 +#endif // AM_HAL_VERSION_MAJ + +#ifdef __cplusplus +} +#endif + +#endif // AM_SDK_VERSION_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/am_mcu_apollo.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/am_mcu_apollo.h new file mode 100644 index 0000000000..fbc03dc014 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/am_mcu_apollo.h @@ -0,0 +1,156 @@ +//***************************************************************************** +// +// am_mcu_apollo.h +//! @file +//! +//! @brief Top Include for Apollo class devices. +//! +//! This file provides all the includes necessary for an apollo device. +//! +//! @addtogroup hal Hardware Abstraction Layer (HAL) +// +//! @defgroup apollo3hal HAL for Apollo3 +//! @ingroup hal +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_MCU_APOLLO_H +#define AM_MCU_APOLLO_H + +//***************************************************************************** +// +// Define AM_CMSIS_REGS to indicate that CMSIS registers are supported. +// +//***************************************************************************** +#define AM_CMSIS_REGS 1 + +//***************************************************************************** +// +// C99 +// +//***************************************************************************** +#include +#include +#include +#include +#if AM_CMSIS_REGS +#include "apollo3.h" +#else // AM_CMSIS_REGS +#ifdef __IAR_SYSTEMS_ICC__ +#include "intrinsics.h" // __CLZ() and other intrinsics +#endif // AM_CMSIS_REGS +#endif + +//***************************************************************************** +// +// Global HAL +// +//***************************************************************************** +// +// Define the following macro to disable API parameter validation. +// Defining this macro will result in smaller, more efficient HAL code, but +// will disable parameter checking/validation throughout the HAL. +// +//#define AM_HAL_DISABLE_API_VALIDATION + +// +// Define the following macro to disable assert messaging. +// Defining this macro will result in smaller, more efficient HAL code, but +// will eliminate debug messaging. +// +//#define AM_HAL_DEBUG_NO_ASSERT + +//***************************************************************************** +// +// Registers +// +//***************************************************************************** +#include "regs/am_reg_base_addresses.h" + +#include "regs/am_reg_macros.h" + +#include "regs/am_reg.h" +#include "regs/am_reg_m4.h" +#include "regs/am_reg_jedec.h" + +//***************************************************************************** +// +// HAL +// +//***************************************************************************** +#include "hal/am_hal_status.h" +#include "hal/am_hal_sysctrl.h" +#include "hal/am_hal_adc.h" +#include "hal/am_hal_ble.h" +#include "hal/am_hal_ble_patch.h" +#include "hal/am_hal_burst.h" +#include "hal/am_hal_cachectrl.h" +#include "hal/am_hal_clkgen.h" +#include "hal/am_hal_cmdq.h" +#include "hal/am_hal_ctimer.h" +#include "hal/am_hal_debug.h" +#include "hal/am_hal_flash.h" +#include "hal/am_hal_global.h" +#include "hal/am_hal_gpio.h" +#include "hal/am_hal_interrupt.h" +#include "hal/am_hal_iom.h" +#include "hal/am_hal_ios.h" +#include "hal/am_hal_itm.h" +#include "hal/am_hal_mcuctrl.h" +#include "hal/am_hal_mspi.h" +#include "hal/am_hal_pdm.h" +#include "hal/am_hal_pin.h" +#include "hal/am_hal_pwrctrl.h" +#include "hal/am_hal_pwrctrl_internal.h" +#include "hal/am_hal_queue.h" +#include "hal/am_hal_reset.h" +#include "hal/am_hal_rtc.h" +#include "hal/am_hal_scard.h" +#include "hal/am_hal_secure_ota.h" +#include "hal/am_hal_stimer.h" +#include "hal/am_hal_security.h" +#include "hal/am_hal_systick.h" +#include "hal/am_hal_tpiu.h" +#include "hal/am_hal_uart.h" +#include "hal/am_hal_wdt.h" + +#endif // AM_MCU_APOLLO_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.c new file mode 100644 index 0000000000..525e6f0ab1 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.c @@ -0,0 +1,1276 @@ +//***************************************************************************** +// +// am_hal_adc.c +//! @file +//! +//! @brief Functions for interfacing with the Analog to Digital Converter. +//! +//! @addtogroup adc3 Analog-to-Digital Converter (ADC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** + +#define AM_HAL_MAGIC_ADC 0xAFAFAF +#define AM_HAL_ADC_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_ADC)) + +// **************************************************************************** +// +// Apollo3 Temperature Trim Value Locations and default coefficients. +// +// **************************************************************************** +#define AM_HAL_ADC_CALIB_TEMP_ADDR (0x50023840) +#define AM_HAL_ADC_CALIB_AMBIENT_ADDR (0x50023844) +#define AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR (0x50023848) + +// **************************************************************************** +// +// Default coefficients (used when trims not provided): +// TEMP_DEFAULT = Temperature in deg K (e.g. 299.5 - 273.15 = 26.35) +// AMBIENT_DEFAULT = Voltage measurement at default temperature. +// OFFSET_DEFAULT = Default ADC offset at 1v. +// +// **************************************************************************** +#define AM_HAL_ADC_CALIB_TEMP_DEFAULT (299.5F) +#define AM_HAL_ADC_CALIB_AMBIENT_DEFAULT (1.02809F) +#define AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT (-0.004281F) + + +// +// ADC Power save register state. +// +typedef struct +{ + bool bValid; + uint32_t regCFG; + uint32_t regSL0CFG; + uint32_t regSL1CFG; + uint32_t regSL2CFG; + uint32_t regSL3CFG; + uint32_t regSL4CFG; + uint32_t regSL5CFG; + uint32_t regSL6CFG; + uint32_t regSL7CFG; + uint32_t regWULIM; + uint32_t regWLLIM; + uint32_t regINTEN; +} am_hal_adc_register_state_t; + +// +// ADC State structure. +// +typedef struct +{ + // + // Handle validation prefix. + // + am_hal_handle_prefix_t prefix; + + // + // Physical module number. + // + uint32_t ui32Module; + + // + // ADC Capabilities. + // + am_hal_adc_capabilities_t capabilities; + + // Power Save-Restore register state + am_hal_adc_register_state_t registerState; + +} am_hal_adc_state_t; + +//***************************************************************************** +// +//! @brief Private SRAM view of temperature trims. +//! +//! This static SRAM union is private to the ADC HAL functions. +// +//***************************************************************************** +static union +{ + //! These trim values are loaded as uint32_t values. + struct + { + //! Temperature of the package test head (in degrees Kelvin) + uint32_t ui32CalibrationTemperature; + + //! Voltage corresponding to temperature measured on test head. + uint32_t ui32CalibrationVoltage; + + //! ADC offset voltage measured on the package test head. + uint32_t ui32CalibrationOffset; + + //! Flag if default (guess) or measured. + bool bMeasured; + } ui32; + //! These trim values are accessed as floats when used in temp calculations. + struct + { + //! Temperature of the package test head in degrees Kelvin + float fCalibrationTemperature; + + //! Voltage corresponding to temperature measured on test head. + float fCalibrationVoltage; + + //! ADC offset voltage measured on the package test head. + float fCalibrationOffset; + + //! Flag if default (guess) or measured. + float fMeasuredFlag; + } flt; +} priv_temp_trims; + +//***************************************************************************** +// +// Global Variables. +// +//***************************************************************************** +am_hal_adc_state_t g_ADCState[AM_REG_ADC_NUM_MODULES]; + +uint32_t g_ADCSlotsConfigured; + +//***************************************************************************** +// +//! @brief ADC initialization function +//! +//! @param ui32Module - module instance. +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a module instance, allocates the interface and then +//! returns a handle to be used by the remaining interface functions. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_initialize(uint32_t ui32Module, void **ppHandle) +{ + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the module number + // + if ( ui32Module >= AM_REG_ADC_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if ( !ppHandle ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if ( g_ADCState[ui32Module].prefix.s.bInit ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the handle. + // + g_ADCState[ui32Module].prefix.s.bInit = true; + g_ADCState[ui32Module].prefix.s.magic = AM_HAL_MAGIC_ADC; + g_ADCState[ui32Module].ui32Module = ui32Module; + + // + // Initialize the number of slots configured. + // + g_ADCSlotsConfigured = 0; + + // + // Return the handle. + // + *ppHandle = (void *)&g_ADCState[ui32Module]; + + // + // Before returning, grab the temperature trims. + // + priv_temp_trims.ui32.ui32CalibrationTemperature = + am_hal_flash_load_ui32((uint32_t*)AM_HAL_ADC_CALIB_TEMP_ADDR); + priv_temp_trims.ui32.ui32CalibrationVoltage = + am_hal_flash_load_ui32((uint32_t*)AM_HAL_ADC_CALIB_AMBIENT_ADDR); + priv_temp_trims.ui32.ui32CalibrationOffset = + am_hal_flash_load_ui32((uint32_t*)AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR); + + if ( (priv_temp_trims.ui32.ui32CalibrationTemperature == 0xffffffff) || + (priv_temp_trims.ui32.ui32CalibrationVoltage == 0xffffffff) || + (priv_temp_trims.ui32.ui32CalibrationOffset == 0xffffffff) ) + { + // + // Since the device has not been calibrated on the tester, we'll load + // default calibration values. These default values should result + // in worst-case temperature measurements of +-6 degress C. + // + priv_temp_trims.flt.fCalibrationTemperature = AM_HAL_ADC_CALIB_TEMP_DEFAULT; + priv_temp_trims.flt.fCalibrationVoltage = AM_HAL_ADC_CALIB_AMBIENT_DEFAULT; + priv_temp_trims.flt.fCalibrationOffset = AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT; + priv_temp_trims.ui32.bMeasured = false; + } + else + { + priv_temp_trims.ui32.bMeasured = true; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief MSPI deinitialization function +//! +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a handle to an instance and de-initializes the +//! interface. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_deinitialize(void *pHandle) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( pADCState->prefix.s.bEnable ) + { + status = am_hal_adc_disable(pHandle); + } + + pADCState->prefix.s.bInit = false; + + // + // Return the status. + // + return status; +} + +//***************************************************************************** +// +//! @brief ADC configuration function +//! +//! @param handle - handle for the module instance. +//! @param pConfig - pointer to the configuration structure. +//! +//! This function configures the ADC for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_configure(void *pHandle, + am_hal_adc_config_t *psConfig) +{ + uint32_t ui32Config; + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Config = 0; + + // + // Set the ADC clock source. + // + ui32Config |= _VAL2FLD(ADC_CFG_CLKSEL, psConfig->eClock); + + // + // Set the ADC trigger polarity. + // + ui32Config |= _VAL2FLD(ADC_CFG_TRIGPOL, psConfig->ePolarity); + + // + // Set the ADC trigger. + // + ui32Config |= _VAL2FLD(ADC_CFG_TRIGSEL, psConfig->eTrigger); + + // + // Set the ADC reference voltage. + // + ui32Config |= _VAL2FLD(ADC_CFG_REFSEL, psConfig->eReference); + + // + // Set the Destructive FIFO read. + // + ui32Config |= _VAL2FLD(ADC_CFG_DFIFORDEN, 1); + + // + // Set the ADC clock mode. + // + ui32Config |= _VAL2FLD(ADC_CFG_CKMODE, psConfig->eClockMode); + + // + // Set the ADC low power mode. + // + ui32Config |= _VAL2FLD(ADC_CFG_LPMODE, psConfig->ePowerMode); + + // + // Set the ADC repetition mode. + // + ui32Config |= _VAL2FLD(ADC_CFG_RPTEN, psConfig->eRepeat); + + // + // Set the configuration in the ADC peripheral. + // + ADCn(ui32Module)->CFG = ui32Config; + + // + // Return status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC slot configuration function +//! +//! @param handle - handle for the module instance. +//! @param pConfig - pointer to the configuration structure. +//! +//! This function configures the ADC slot for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_configure_slot(void *pHandle, + uint32_t ui32SlotNumber, + am_hal_adc_slot_config_t *pSlotConfig) +{ + uint32_t ui32Config; + uint32_t ui32RegOffset; + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check the slot number. + // + if ( ui32SlotNumber >= AM_HAL_ADC_MAX_SLOTS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Config = 0; + + // + // Set the measurements to average + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_ADSEL0, pSlotConfig->eMeasToAvg); + + // + // Set the precision mode. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_PRMODE0, pSlotConfig->ePrecisionMode); + + // + // Set the channel. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_CHSEL0, pSlotConfig->eChannel); + + // + // Enable window comparison if configured. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_WCEN0, pSlotConfig->bWindowCompare); + + // + // Enable the slot if configured. + // + ui32Config |= _VAL2FLD(ADC_SL0CFG_SLEN0, pSlotConfig->bEnabled); + + // + // Locate the correct register for this ADC slot. + // + ui32RegOffset = ((uint32_t)&ADCn(ui32Module)->SL0CFG) + (4 * ui32SlotNumber); + + // + // Write the register with the caller's configuration value. + // + AM_REGVAL(ui32RegOffset) = ui32Config; + + // + // Update the nubmer of slots configured. + // + g_ADCSlotsConfigured++; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC DMA configuration function +//! +//! @param handle - handle for the module instance. +//! @param pConfig - pointer to the configuration structure. +//! +//! This function configures the ADC DMA for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_configure_dma(void *pHandle, + am_hal_adc_dma_config_t *pDMAConfig) +{ + uint32_t ui32Config; + uint32_t ui32Module = ((am_hal_adc_state_t *)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Config = 0; + + // + // Configure the DMA complete power-off. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DPWROFF, 0); // DPWROFF not supported! + + // + // Configure the data to be transferred. + // + if ( g_ADCSlotsConfigured > 1 ) + { + // Need slot number to distinguish between slot results. + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAMSK, ADC_DMACFG_DMAMSK_DIS); + } + else + { + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAMSK, ADC_DMACFG_DMAMSK_EN); + } + + // + // Enable DMA Halt on Status (DMAERR or DMACPL) by default. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAHONSTAT, ADC_DMACFG_DMAHONSTAT_EN); + + // + // Configure the DMA dynamic priority handling. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMADYNPRI, pDMAConfig->bDynamicPriority); + + // + // Configure the DMA static priority. + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAPRI, pDMAConfig->ePriority); + + // + // Enable the DMA (does not start until ADC is enabled and triggered). + // + ui32Config |= _VAL2FLD(ADC_DMACFG_DMAEN, ADC_DMACFG_DMAEN_EN); + + // + // Set the DMA configuration. + // + ADCn(ui32Module)->DMACFG = ui32Config; + + // + // Set the DMA transfer count. + // + ADCn(ui32Module)->DMATOTCOUNT_b.TOTCOUNT = pDMAConfig->ui32SampleCount; + + // + // Set the DMA target address. + // + ADCn(ui32Module)->DMATARGADDR = pDMAConfig->ui32TargetAddress; + + // + // Set the DMA trigger on FIFO 75% full. + // + ADCn(ui32Module)->DMATRIGEN = ADC_DMATRIGEN_DFIFO75_Msk; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC device specific control function. +//! +//! @param handle - handle for the module instance. +//! +//! This function provides for special control functions for the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t am_hal_adc_control(void *pHandle, + am_hal_adc_request_e eRequest, + void *pArgs) +{ + uint32_t ui32Module = ((am_hal_adc_state_t *)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + switch ( eRequest ) + { + case AM_HAL_ADC_REQ_WINDOW_CONFIG: + { + am_hal_adc_window_config_t *pWindowConfig = (am_hal_adc_window_config_t *)pArgs; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the window limits. + // + if ( (pWindowConfig->ui32Upper > ADC_WULIM_ULIM_Msk) || + (pWindowConfig->ui32Lower > ADC_WLLIM_LLIM_Msk) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Set the window comparison upper and lower limits. + // + ADCn(ui32Module)->WULIM = _VAL2FLD(ADC_WULIM_ULIM, pWindowConfig->ui32Upper); + ADCn(ui32Module)->WLLIM = _VAL2FLD(ADC_WLLIM_LLIM, pWindowConfig->ui32Lower); + + // + // Set the window scale per precision mode if indicated. + // + ADCn(ui32Module)->SCWLIM = _VAL2FLD(ADC_SCWLIM_SCWLIMEN, + pWindowConfig->bScaleLimits); + } + break; + + case AM_HAL_ADC_REQ_TEMP_CELSIUS_GET: + // + // pArgs must point to an array of 3 floats. To assure that the + // array is valid, upon calling the 3rd float (pArgs[2]) must be + // set to the value -123.456F. + // + if ( pArgs != NULL ) + { + float *pfArray = (float*)pArgs; + float fTemp, fCalibration_temp, fCalibration_voltage, fCalibration_offset, fVoltage; + + if ( pfArray[2] == -123.456F ) + { + // + // Get the scaled voltage obtained from the ADC sample. + // The ADC sample value is scaled up by the reference voltage + // (e.g. 1.5F), then divided by 65536.0F. + // + fVoltage = pfArray[0]; + + // + // Get calibration temperature from trimmed values & convert to degrees K. + // + fCalibration_temp = priv_temp_trims.flt.fCalibrationTemperature; + fCalibration_voltage = priv_temp_trims.flt.fCalibrationVoltage; + fCalibration_offset = priv_temp_trims.flt.fCalibrationOffset; + + // + // Compute the temperature. + // + fTemp = fCalibration_temp; + fTemp /= (fCalibration_voltage - fCalibration_offset); + fTemp *= (fVoltage - fCalibration_offset); + + // + // Give it back to the caller in Celsius. + // + pfArray[1] = fTemp - 273.15f; + } + else + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_ADC_REQ_TEMP_TRIMS_GET: + // + // pArgs must point to an array of 4 floats. To assure that the + // array is valid, upon calling the 4th float (pArgs[3]) must be + // set to the value -123.456. + // On return, pArgs[3] is set to 1 if the returned values are + // calibrated, or 0 if default calibration values. + // + if ( pArgs != NULL ) + { + float *pfArray = (float*)pArgs; + if ( pfArray[3] == -123.456F ) + { + // + // Return trim temperature as a float. + // + pfArray[0] = priv_temp_trims.flt.fCalibrationTemperature; + + // + // Return trim voltage as a float. + // + pfArray[1] = priv_temp_trims.flt.fCalibrationVoltage; + + // + // Return trim ADC offset voltage as a float. + // + pfArray[2] = priv_temp_trims.flt.fCalibrationOffset; + + // + // Set the calibrated or uncalibrated flag + // + ((uint32_t*)pArgs)[3] = priv_temp_trims.ui32.bMeasured; + } + else + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC enable function +//! +//! @param handle - handle for the module instance. +//! +//! This function enables the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_enable(void *pHandle) +{ + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( pADCState->prefix.s.bEnable ) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable the ADC. + // + ADCn(ui32Module)->CFG_b.ADCEN = 0x1; + + // + // Set flag to indicate module is enabled. + // + pADCState->prefix.s.bEnable = true; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC disable function +//! +//! @param handle - handle for the module instance. +//! +//! This function disables the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_disable(void *pHandle) +{ + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Disable the ADC. + // + ADCn(ui32Module)->CFG_b.ADCEN = 0x0; + + // + // Set flag to indicate module is disabled. + // + pADCState->prefix.s.bEnable = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC status function +//! +//! @param handle - handle for the interface. +//! +//! This function returns the current status of the DMA operation. +//! +//! @return status - DMA status flags. +// +//***************************************************************************** +uint32_t +am_hal_adc_status_get(void *pHandle, am_hal_adc_status_t *pStatus ) +{ + uint32_t ui32Module = ((am_hal_adc_state_t *)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Get the power status. + // + pStatus->bPoweredOn = (ADCn(ui32Module)->STAT & ADC_STAT_PWDSTAT_Msk) == + _VAL2FLD(ADC_STAT_PWDSTAT, ADC_STAT_PWDSTAT_ON); + + // + // Get the low power mode 1 status. + // + pStatus->bLPMode1 = (ADCn(ui32Module)->STAT & ADC_STAT_PWDSTAT_Msk) == + _VAL2FLD(ADC_STAT_PWDSTAT, ADC_STAT_PWDSTAT_POWERED_DOWN); + + // + // Get the DMA status. + // + pStatus->bErr = ((ADCn(ui32Module)->DMASTAT & ADC_DMASTAT_DMAERR_Msk) > 0); + pStatus->bCmp = ((ADCn(ui32Module)->DMASTAT & ADC_DMASTAT_DMACPL_Msk) > 0); + pStatus->bTIP = ((ADCn(ui32Module)->DMASTAT & ADC_DMASTAT_DMATIP_Msk) > 0); + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC enable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - ADC interrupt mask. +//! +//! This function enables the specific indicated interrupts. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable the interrupts. + // + ADCn(ui32Module)->INTEN |= ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC disable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - ADC interrupt mask. +//! +//! This function disable the specific indicated interrupts. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Disable the interrupts. + // + ADCn(ui32Module)->INTEN &= ~ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC interrupt status function +//! +//! @param handle - handle for the interface. +//! +//! This function returns the specific indicated interrupt status. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_status(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // if requested, only return the interrupts that are enabled. + // + if ( bEnabledOnly ) + { + uint32_t ui32RetVal = ADCn(ui32Module)->INTSTAT; + *pui32Status = ADCn(ui32Module)->INTEN & ui32RetVal; + } + else + { + *pui32Status = ADCn(ui32Module)->INTSTAT; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +//! @brief ADC interrupt clear +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - uint32_t for interrupts to clear +//! +//! This function clears the interrupts for the given peripheral. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Clear the interrupts. + // + ADCn(ui32Module)->INTCLR = ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// ADC sample read function +// +// This function reads samples from the ADC FIFO or an SRAM sample buffer +// returned by a DMA operation. +// +//***************************************************************************** +uint32_t am_hal_adc_samples_read(void *pHandle, bool bFullSample, + uint32_t *pui32InSampleBuffer, + uint32_t *pui32InOutNumberSamples, + am_hal_adc_sample_t *pui32OutBuffer) +{ + uint32_t ui32Sample; + uint32_t ui32RequestedSamples = *pui32InOutNumberSamples; + + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check the output sample buffer pointer. + // + if ( NULL == pui32OutBuffer ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + + *pui32InOutNumberSamples = 0; + + // + // Check if we are reading directly from FIFO or DMA SRAM buffer. + // + if ( NULL == pui32InSampleBuffer ) + { + // + // Grab a value from the ADC FIFO + // + do + { + ui32Sample = ADCn(ui32Module)->FIFOPR; + pui32OutBuffer->ui32Slot = AM_HAL_ADC_FIFO_SLOT(ui32Sample); + pui32OutBuffer->ui32Sample = bFullSample ? + AM_HAL_ADC_FIFO_FULL_SAMPLE(ui32Sample) : + AM_HAL_ADC_FIFO_SAMPLE(ui32Sample); + pui32OutBuffer++; + (*pui32InOutNumberSamples)++; + } while ((AM_HAL_ADC_FIFO_COUNT(ui32Sample) > 0) && + (*pui32InOutNumberSamples < ui32RequestedSamples)); + } + else + { + // + // Process the samples from the provided sample buffer + // + do + { + ui32Sample = ADCn(ui32Module)->FIFOPR; + pui32OutBuffer->ui32Slot = AM_HAL_ADC_FIFO_SLOT(*pui32InSampleBuffer); + pui32OutBuffer->ui32Sample = AM_HAL_ADC_FIFO_SAMPLE(*pui32InSampleBuffer); + pui32InSampleBuffer++; + pui32OutBuffer++; + (*pui32InOutNumberSamples)++; + } while (*pui32InOutNumberSamples < ui32RequestedSamples); + } + + // + // Return FIFO valid bits. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Issue Software Trigger to the ADC. +//! +//! @param handle - handle for the module instance. +//! +//! This function triggers the ADC operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_sw_trigger(void *pHandle) +{ + uint32_t ui32Module = ((am_hal_adc_state_t*)pHandle)->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Write to the Software trigger register in the ADC. + // + ADCn(ui32Module)->SWT = 0x37; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief ADC power control function +//! +//! @param handle - handle for the interface. +//! @param ePowerState - the desired power state to move the peripheral to. +//! @param bRetainState - flag (if true) to save/restore peripheral state upon +//! power state change. +//! +//! This function updates the peripheral to a given power state. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_adc_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_adc_state_t *pADCState = (am_hal_adc_state_t *)pHandle; + uint32_t ui32Module = pADCState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_ADC_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update MSPI operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + if ( bRetainState && !pADCState->registerState.bValid ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable the ADC power domain. + // + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_ADC); + + if ( bRetainState ) + { + ADCn(ui32Module)->SL0CFG = pADCState->registerState.regSL0CFG; + ADCn(ui32Module)->SL1CFG = pADCState->registerState.regSL1CFG; + ADCn(ui32Module)->SL2CFG = pADCState->registerState.regSL2CFG; + ADCn(ui32Module)->SL3CFG = pADCState->registerState.regSL3CFG; + ADCn(ui32Module)->SL4CFG = pADCState->registerState.regSL4CFG; + ADCn(ui32Module)->SL5CFG = pADCState->registerState.regSL5CFG; + ADCn(ui32Module)->SL6CFG = pADCState->registerState.regSL6CFG; + ADCn(ui32Module)->SL7CFG = pADCState->registerState.regSL7CFG; + ADCn(ui32Module)->WULIM = pADCState->registerState.regWULIM; + ADCn(ui32Module)->WLLIM = pADCState->registerState.regWLLIM; + ADCn(ui32Module)->INTEN = pADCState->registerState.regINTEN; + ADCn(ui32Module)->CFG = pADCState->registerState.regCFG; + + pADCState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if ( bRetainState ) + { + pADCState->registerState.regSL0CFG = ADCn(ui32Module)->SL0CFG; + pADCState->registerState.regSL1CFG = ADCn(ui32Module)->SL1CFG; + pADCState->registerState.regSL2CFG = ADCn(ui32Module)->SL2CFG; + pADCState->registerState.regSL3CFG = ADCn(ui32Module)->SL3CFG; + pADCState->registerState.regSL4CFG = ADCn(ui32Module)->SL4CFG; + pADCState->registerState.regSL5CFG = ADCn(ui32Module)->SL5CFG; + pADCState->registerState.regSL6CFG = ADCn(ui32Module)->SL6CFG; + pADCState->registerState.regSL7CFG = ADCn(ui32Module)->SL7CFG; + pADCState->registerState.regWULIM = ADCn(ui32Module)->WULIM; + pADCState->registerState.regWLLIM = ADCn(ui32Module)->WLLIM; + pADCState->registerState.regINTEN = ADCn(ui32Module)->INTEN; + pADCState->registerState.regCFG = ADCn(ui32Module)->CFG; + + pADCState->registerState.bValid = true; + } + + // + // Disable the ADC power domain. + // + am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_ADC); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.h new file mode 100644 index 0000000000..59a9d9eefd --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_adc.h @@ -0,0 +1,679 @@ +//***************************************************************************** +// +// am_hal_adc.h +//! @file +//! +//! @brief Functions for interfacing with the Analog to Digital Converter +//! +//! @addtogroup adc3 Analog-to-Digital Converter (ADC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_ADC_H +#define AM_HAL_ADC_H + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable IOM module number. +// +#define ADCn(n) ((ADC_Type*)(ADC_BASE + (n * (ADC_BASE - ADC_BASE)))) +//***************************************************************************** + +// +// Maximum number of slots. +// +#define AM_HAL_ADC_MAX_SLOTS 8 + +// +// ADC clock selection. +// +typedef enum +{ + AM_HAL_ADC_CLKSEL_OFF, + AM_HAL_ADC_CLKSEL_HFRC, + AM_HAL_ADC_CLKSEL_HFRC_DIV2 +} am_hal_adc_clksel_e; + +// +// ADC trigger polarity +// +typedef enum +{ + AM_HAL_ADC_TRIGPOL_RISING, + AM_HAL_ADC_TRIGPOL_FALLING +} am_hal_adc_trigpol_e; + +// +// ADC trigger selection +// +typedef enum +{ + AM_HAL_ADC_TRIGSEL_EXT0, + AM_HAL_ADC_TRIGSEL_EXT1, + AM_HAL_ADC_TRIGSEL_EXT2, + AM_HAL_ADC_TRIGSEL_EXT3, + AM_HAL_ADC_TRIGSEL_VCOMP, + AM_HAL_ADC_TRIGSEL_SOFTWARE = 7 +} am_hal_adc_trigsel_e; + +// +// ADC reference selection. +// +typedef enum +{ + AM_HAL_ADC_REFSEL_INT_2P0, + AM_HAL_ADC_REFSEL_INT_1P5, + AM_HAL_ADC_REFSEL_EXT_2P0, + AM_HAL_ADC_REFSEL_EXT_1P5 +} am_hal_adc_refsel_e; + +// +// ADC clock mode selection. +// +typedef enum +{ + AM_HAL_ADC_CLKMODE_LOW_POWER, // Disable the clock between scans for LPMODE0. + // Set LPCKMODE to 0x1 while configuring the ADC. + AM_HAL_ADC_CLKMODE_LOW_LATENCY // Low Latency Clock Mode. When set, HFRC and the + // adc_clk will remain on while in functioning in LPMODE0. +} am_hal_adc_clkmode_e; + +// +// ADC low-power mode selection. +// +typedef enum +{ + AM_HAL_ADC_LPMODE0, // Low Latency Clock Mode. When set, HFRC and the adc_clk + // will remain on while in functioning in LPMODE0. + AM_HAL_ADC_LPMODE1 // Powers down all circuity and clocks associated with the + // ADC until the next trigger event. Between scans, the reference + // buffer requires up to 50us of delay from a scan trigger event + // before the conversion will commence while operating in this mode. +} am_hal_adc_lpmode_e; + +// +// ADC repetition selection. +// +typedef enum +{ + AM_HAL_ADC_SINGLE_SCAN, + AM_HAL_ADC_REPEATING_SCAN +} am_hal_adc_repeat_e; + +// +// ADC measurement averaging configuration. +// +typedef enum +{ + AM_HAL_ADC_SLOT_AVG_1, + AM_HAL_ADC_SLOT_AVG_2, + AM_HAL_ADC_SLOT_AVG_4, + AM_HAL_ADC_SLOT_AVG_8, + AM_HAL_ADC_SLOT_AVG_16, + AM_HAL_ADC_SLOT_AVG_32, + AM_HAL_ADC_SLOT_AVG_64, + AM_HAL_ADC_SLOT_AVG_128 +} am_hal_adc_meas_avg_e; + +// +// ADC slot precision mode. +// +typedef enum +{ + AM_HAL_ADC_SLOT_14BIT, + AM_HAL_ADC_SLOT_12BIT, + AM_HAL_ADC_SLOT_10BIT, + AM_HAL_ADC_SLOT_8BIT +} am_hal_adc_slot_prec_e; + +// +// ADC slot channel selection. +// +typedef enum +{ + // Single-ended channels + AM_HAL_ADC_SLOT_CHSEL_SE0, + AM_HAL_ADC_SLOT_CHSEL_SE1, + AM_HAL_ADC_SLOT_CHSEL_SE2, + AM_HAL_ADC_SLOT_CHSEL_SE3, + AM_HAL_ADC_SLOT_CHSEL_SE4, + AM_HAL_ADC_SLOT_CHSEL_SE5, + AM_HAL_ADC_SLOT_CHSEL_SE6, + AM_HAL_ADC_SLOT_CHSEL_SE7, + AM_HAL_ADC_SLOT_CHSEL_SE8, + AM_HAL_ADC_SLOT_CHSEL_SE9, + // Differential channels. + AM_HAL_ADC_SLOT_CHSEL_DF0, + AM_HAL_ADC_SLOT_CHSEL_DF1, + // Miscellaneous other signals. + AM_HAL_ADC_SLOT_CHSEL_TEMP, + AM_HAL_ADC_SLOT_CHSEL_BATT, + AM_HAL_ADC_SLOT_CHSEL_VSS +} am_hal_adc_slot_chan_e; + +// +// DMA priority. +// +typedef enum +{ + AM_HAL_ADC_PRIOR_BEST_EFFORT, + AM_HAL_ADC_PRIOR_SERVICE_IMMED +} am_hal_adc_dma_prior_e; + +//! +//! ADC control function request types for am_hal_adc_control(). +//! +//! AM_HAL_ADC_REQ_TEMP_CELSIUS_GET: +//! pArgs must point to an array of 3 floats. To assure that the +//! array is valid, upon calling the 3rd float (pArgs[2]) must be +//! set to the value -123.456F. +//! AM_HAL_ADC_REQ_TEMP_TRIMS_GET: +//! pArgs must point to an array of 4 floats. To assure that the +//! array is valid, upon calling the 4th float (pArgs[3]) must be +//! set to the to the value -123.456F. +//! On return, pArgs[3] is set to 1 if the returned values are +//! calibrated, or 0 if default calibration values. +//! +typedef enum +{ + AM_HAL_ADC_REQ_WINDOW_CONFIG, + AM_HAL_ADC_REQ_TEMP_CELSIUS_GET, + AM_HAL_ADC_REQ_TEMP_TRIMS_GET, +} am_hal_adc_request_e; + +// +// ADC Sample structure. +// +typedef struct +{ + uint32_t ui32Sample; + uint32_t ui32Slot; +} am_hal_adc_sample_t; + + +//***************************************************************************** +// +//! @brief Configuration structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + //! Select the ADC clock source. + am_hal_adc_clksel_e eClock; + + //! Select the ADC trigger polarity. + am_hal_adc_trigpol_e ePolarity; + + //! Select the ADC trigger source. + am_hal_adc_trigsel_e eTrigger; + + //! Select the ADC reference voltage. + am_hal_adc_refsel_e eReference; + + //! Whether to disable clocks between samples. + am_hal_adc_clkmode_e eClockMode; + + //! Select the ADC power mode. + am_hal_adc_lpmode_e ePowerMode; + + //! Select whether the ADC will re-trigger based on a signal from timer 3. + am_hal_adc_repeat_e eRepeat; + +} am_hal_adc_config_t; + +//***************************************************************************** +// +//! @brief Configuration structure for the ADC slot. +// +//***************************************************************************** +typedef struct +{ + //! Select the number of measurements to average + am_hal_adc_meas_avg_e eMeasToAvg; + + //! Select the precision mode + am_hal_adc_slot_prec_e ePrecisionMode; + + //! Select the channel + am_hal_adc_slot_chan_e eChannel; + + //! Select window comparison mode + bool bWindowCompare; + + //! Enable the slot + bool bEnabled; + +} am_hal_adc_slot_config_t; + +//***************************************************************************** +// +//! @brief Configuration structure for the ADC DMA +// +//***************************************************************************** +typedef struct +{ + //! ADC DMA dynamic priority enabled. + bool bDynamicPriority; + + //! ADC DMA static priority. + am_hal_adc_dma_prior_e ePriority; + + //! Enable DMA for ADC + bool bDMAEnable; + + //! Transfer count in samples + uint32_t ui32SampleCount; + + //! Target address + uint32_t ui32TargetAddress; + +} am_hal_adc_dma_config_t; + +//***************************************************************************** +// +//! @brief Window configuration structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + //! Scale window comparison + bool bScaleLimits; + + //! Window limits + uint32_t ui32Upper; + uint32_t ui32Lower; + +} am_hal_adc_window_config_t; + +//***************************************************************************** +// +//! @brief Capabilities structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + uint32_t dummy; + +} am_hal_adc_capabilities_t; + + +//***************************************************************************** +// +//! @brief Status structure for the ADC. +// +//***************************************************************************** +typedef struct +{ + // + // ADC power status. + // + bool bPoweredOn; + bool bLPMode1; + + // + // DMA status. + // + bool bErr; + bool bCmp; + bool bTIP; + +} am_hal_adc_status_t; + +// +// Transfer callback function prototype +// +typedef void (*am_hal_adc_callback_t)(void *pCallbackCtxt, uint32_t status); + +//***************************************************************************** +// +//! @name ADC Interrupts +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to enable an individual ADC interrupt cause. +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_INT_DERR (_VAL2FLD(ADC_INTEN_DERR, 1)) +#define AM_HAL_ADC_INT_DCMP (_VAL2FLD(ADC_INTEN_DCMP, 1)) +#define AM_HAL_ADC_INT_WCINC (_VAL2FLD(ADC_INTEN_WCINC, 1)) +#define AM_HAL_ADC_INT_WCEXC (_VAL2FLD(ADC_INTEN_WCEXC, 1)) +#define AM_HAL_ADC_INT_FIFOOVR2 (_VAL2FLD(ADC_INTEN_FIFOOVR2, 1)) +#define AM_HAL_ADC_INT_FIFOOVR1 (_VAL2FLD(ADC_INTEN_FIFOOVR1, 1)) +#define AM_HAL_ADC_INT_SCNCMP (_VAL2FLD(ADC_INTEN_SCNCMP, 1)) +#define AM_HAL_ADC_INT_CNVCMP (_VAL2FLD(ADC_INTEN_CNVCMP, 1)) +//! @} + +//***************************************************************************** +// +//! @brief ADC Fifo Read macros +//! +//! These are helper macros for interpreting FIFO data. Each ADC FIFO entry +//! contains information about the slot number and the FIFO depth alongside the +//! current sample. These macros perform the correct masking and shifting to +//! read those values. +//! +//! The SAMPLE and FULL_SAMPLE options refer to the fractional part of averaged +//! samples. If you are not using hardware averaging or don't need the +//! fractional part of the ADC sample, you should just use +//! AM_HAL_ADC_FIFO_SAMPLE. +//! +//! If you do need the fractional part, use AM_HAL_ADC_FIFO_FULL_SAMPLE. This +//! macro will keep six bits of precision past the decimal point. Depending on +//! the number of averaged samples, anywhere between 1 and 6 of these bits will +//! be valid. Please consult the datasheet to find out how many bits of data +//! are valid for your chosen averaging settings. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_ADC_FIFO_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value) >> 6) +#define AM_HAL_ADC_FIFO_FULL_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value)) +#define AM_HAL_ADC_FIFO_SLOT(value) (_FLD2VAL(ADC_FIFO_SLOTNUM, value)) +#define AM_HAL_ADC_FIFO_COUNT(value) (_FLD2VAL(ADC_FIFO_COUNT, value)) +//! @} + +#ifdef __cplusplus +extern "C" +{ +#endif + + //***************************************************************************** + // + //! @brief ADC initialization function + //! + //! @param ui32Module - module instance. + //! @param handle - returns the handle for the module instance. + //! + //! This function accepts a module instance, allocates the interface and then + //! returns a handle to be used by the remaining interface functions. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_initialize(uint32_t ui32Module, void **ppHandle); + + //***************************************************************************** + // + //! @brief MSPI deinitialization function + //! + //! @param handle - returns the handle for the module instance. + //! + //! This function accepts a handle to an instance and de-initializes the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_deinitialize(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC configuration function + //! + //! @param handle - handle for the module instance. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the ADC for operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_configure(void *pHandle, + am_hal_adc_config_t *psConfig); + + //***************************************************************************** + // + //! @brief ADC slot configuration function + //! + //! @param handle - handle for the module instance. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the ADC slot for operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_configure_slot(void *pHandle, + uint32_t ui32SlotNumber, + am_hal_adc_slot_config_t *pSlotConfig); + + //***************************************************************************** + // + //! @brief ADC DMA configuration function + //! + //! @param handle - handle for the module instance. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the ADC DMA for operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_configure_dma(void *pHandle, + am_hal_adc_dma_config_t *pDMAConfig); + + //***************************************************************************** + // + //! @brief ADC device specific control function. + //! + //! @param handle - handle for the module instance. + //! @eRequest - One of: + //! AM_HAL_ADC_REQ_WINDOW_CONFIG + //! AM_HAL_ADC_REQ_TEMP_CELSIUS_GET (pArgs is required, see enums). + //! AM_HAL_ADC_REQ_TEMP_TRIMS_GET (pArgs is required, see enums). + //! + //! This function provides for special control functions for the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_control(void *pHandle, + am_hal_adc_request_e eRequest, + void *pArgs); + + //***************************************************************************** + // + //! @brief ADC enable function + //! + //! @param handle - handle for the module instance. + //! + //! This function enables the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_enable(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC disable function + //! + //! @param handle - handle for the module instance. + //! + //! This function disables the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_disable(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC status function + //! + //! @param handle - handle for the interface. + //! + //! This function returns the current status of the DMA operation. + //! + //! @return status - DMA status flags. + // + //***************************************************************************** + extern uint32_t am_hal_adc_status_get(void *pHandle, + am_hal_adc_status_t *pStatus ); + + //***************************************************************************** + // + //! @brief ADC enable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - ADC interrupt mask. + //! + //! This function enables the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_enable(void *pHandle, uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief ADC disable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - ADC interrupt mask. + //! + //! This function disable the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_disable(void *pHandle, uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief ADC interrupt status function + //! + //! @param handle - handle for the interface. + //! + //! This function returns the specific indicated interrupt status. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_status(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly); + + //***************************************************************************** + // + //! @brief ADC interrupt clear + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - uint32_t for interrupts to clear + //! + //! This function clears the interrupts for the given peripheral. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_interrupt_clear(void *pHandle, uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief ADC sample read function + //! + //! @param pHandle - handle for the module instance. + //! @param bFullSample - true to get a full sample including + //! the fractional part. + //! @param pui32InSampleBuffer - Ptr to the input sample buffer. + //! If NULL then samples will be read directly + //! from the FIFO. + //! @param pui32InOutNumberSamples - Ptr to variable containing the number of + //! samples. + //! @param pui32OutSampleBuffer - Ptr to the required output sample buffer. + //! + //! This function reads samples from the ADC FIFO or an SRAM sample buffer + //! returned by a DMA operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_samples_read(void *pHandle, bool bFullSample, + uint32_t *pui32InSampleBuffer, + uint32_t *pui32InOutNumberSamples, + am_hal_adc_sample_t *pui32OutBuffer); + + //***************************************************************************** + // + //! @brief ADC FIFO trigger function + //! + //! @param handle - handle for the module instance. + //! + //! This function triggers the ADC operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_sw_trigger(void *pHandle); + + //***************************************************************************** + // + //! @brief ADC power control function + //! + //! @param handle - handle for the interface. + //! @param ePowerState - the desired power state to move the peripheral to. + //! @param bRetainState - flag (if true) to save/restore peripheral state upon + //! power state change. + //! + //! This function updates the peripheral to a given power state. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_adc_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_ADC_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c new file mode 100644 index 0000000000..6bd5a5375e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.c @@ -0,0 +1,3165 @@ +//***************************************************************************** +// +//! @file am_hal_ble.c +//! +//! @brief HAL functions for the BLE interface. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include "am_mcu_apollo.h" +#include "am_hal_ble_patch.h" +#include "am_hal_ble_patch_b0.h" + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +am_hal_ble_state_t g_sBLEState[AM_REG_BLEIF_NUM_MODULES]; + +//***************************************************************************** +// +// Helper macros for rev B0 parts. +// +//***************************************************************************** +#define BLEIF_INTSTAT_BLECSSTATN_Msk BLEIF_INTSTAT_B2MSHUTDN_Msk +#define BLEIF_INTSTAT_BLECIRQN_Msk BLEIF_INTSTAT_B2MACTIVE_Msk + +#define SKIP_FALLING_EDGES 0 + +//***************************************************************************** +// +// SPI "options" +// +// These values affect the behavior of the BLE HAL in regards to the SPI bus, +// but end users aren't likely to need to modify them. They are collected here +// for testing and debugging purposes. +// +//***************************************************************************** +// The amount of extra delay to add between successive SPI TX packets (in +// microseconds). +#define AM_BLE_TX_PACKET_SPACING_US 1 + +// The BLE core takes a little while to wake up from a fresh boot, which means +// that the patch_apply function might time-out on the first few tries. Set +// this variable to let it try again for a finite number of trials. +#define AM_BLE_NUM_PATCH_TRIALS 5000 + +// Patch complete can also take some time. +#define AM_BLE_NUM_PATCH_CMP_TRIALS 5000 + +// How long the MCU should wait for SPI_STATUS before assuming the BLE core is +// busy (measured in 10 us increments). +#define AM_BLE_STATUS_TIMEOUT 300 + +//***************************************************************************** +// +// Private types. +// +//***************************************************************************** +#define AM_HAL_MAGIC_BLE 0x775230 + +#define AM_HAL_BLE_CHK_HANDLE(h) \ + ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit \ + && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_BLE)) + +//***************************************************************************** +// +// BLE Core maximum patch packet size. +// +// Specified as part of the protocol. +// +//***************************************************************************** +#define MAX_PATCH_PACKET_LEN 0x80 + +//***************************************************************************** +// +// Some of the NationZ register addresses are different between A1/A2 and B0. +// +//***************************************************************************** + +#define AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_A1 0x20006054 +#define AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_A1 0x20006070 +#define AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_A1 0x20006038 +#define AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1 (0x200067b8 + 0x0c) + +#define AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_B0 0x20006858 +#define AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_B0 0x20006874 +#define AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_B0 0x20006838 +#define AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0 (0x20006e0c + 0x0c) + +//***************************************************************************** +// +// Static function prototypes. +// +//***************************************************************************** +static bool am_hal_ble_bus_lock(am_hal_ble_state_t *pBle); +static void am_hal_ble_bus_release(am_hal_ble_state_t *pBle); +static uint32_t am_hal_ble_fifo_drain(void *pHandle); +static void am_hal_ble_fifo_read(void *pHandle, uint32_t *pui32Data, uint32_t ui32NumBytes); +static bool am_hal_ble_check_status(am_hal_ble_state_t *pBle); +static bool am_hal_ble_check_irq(am_hal_ble_state_t *pBle); +static uint32_t am_hal_ble_cmd_write(void *pHandle, am_hal_ble_transfer_t *psTransfer); +static uint32_t am_hal_ble_load_modex_trim_set(void *pHandle); +static uint32_t nonblocking_write(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer); +static uint32_t nonblocking_read(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer); +static uint8_t am_hal_ble_read_trimdata_from_info1(void); + +//***************************************************************************** +// +// Look up Table for NZ CRC16 generation +// +//***************************************************************************** +static const uint16_t ccitt_table[] = +{ + 0x0000, 0x8005, 0x800F, 0x000A, 0x801B, 0x001E, 0x0014, 0x8011, + 0x8033, 0x0036, 0x003C, 0x8039, 0x0028, 0x802D, 0x8027, 0x0022, + 0x8063, 0x0066, 0x006C, 0x8069, 0x0078, 0x807D, 0x8077, 0x0072, + 0x0050, 0x8055, 0x805F, 0x005A, 0x804B, 0x004E, 0x0044, 0x8041, + 0x80C3, 0x00C6, 0x00CC, 0x80C9, 0x00D8, 0x80DD, 0x80D7, 0x00D2, + 0x00F0, 0x80F5, 0x80FF, 0x00FA, 0x80EB, 0x00EE, 0x00E4, 0x80E1, + 0x00A0, 0x80A5, 0x80AF, 0x00AA, 0x80BB, 0x00BE, 0x00B4, 0x80B1, + 0x8093, 0x0096, 0x009C, 0x8099, 0x0088, 0x808D, 0x8087, 0x0082, + 0x8183, 0x0186, 0x018C, 0x8189, 0x0198, 0x819D, 0x8197, 0x0192, + 0x01B0, 0x81B5, 0x81BF, 0x01BA, 0x81AB, 0x01AE, 0x01A4, 0x81A1, + 0x01E0, 0x81E5, 0x81EF, 0x01EA, 0x81FB, 0x01FE, 0x01F4, 0x81F1, + 0x81D3, 0x01D6, 0x01DC, 0x81D9, 0x01C8, 0x81CD, 0x81C7, 0x01C2, + 0x0140, 0x8145, 0x814F, 0x014A, 0x815B, 0x015E, 0x0154, 0x8151, + 0x8173, 0x0176, 0x017C, 0x8179, 0x0168, 0x816D, 0x8167, 0x0162, + 0x8123, 0x0126, 0x012C, 0x8129, 0x0138, 0x813D, 0x8137, 0x0132, + 0x0110, 0x8115, 0x811F, 0x011A, 0x810B, 0x010E, 0x0104, 0x8101, + 0x8303, 0x0306, 0x030C, 0x8309, 0x0318, 0x831D, 0x8317, 0x0312, + 0x0330, 0x8335, 0x833F, 0x033A, 0x832B, 0x032E, 0x0324, 0x8321, + 0x0360, 0x8365, 0x836F, 0x036A, 0x837B, 0x037E, 0x0374, 0x8371, + 0x8353, 0x0356, 0x035C, 0x8359, 0x0348, 0x834D, 0x8347, 0x0342, + 0x03C0, 0x83C5, 0x83CF, 0x03CA, 0x83DB, 0x03DE, 0x03D4, 0x83D1, + 0x83F3, 0x03F6, 0x03FC, 0x83F9, 0x03E8, 0x83ED, 0x83E7, 0x03E2, + 0x83A3, 0x03A6, 0x03AC, 0x83A9, 0x03B8, 0x83BD, 0x83B7, 0x03B2, + 0x0390, 0x8395, 0x839F, 0x039A, 0x838B, 0x038E, 0x0384, 0x8381, + 0x0280, 0x8285, 0x828F, 0x028A, 0x829B, 0x029E, 0x0294, 0x8291, + 0x82B3, 0x02B6, 0x02BC, 0x82B9, 0x02A8, 0x82AD, 0x82A7, 0x02A2, + 0x82E3, 0x02E6, 0x02EC, 0x82E9, 0x02F8, 0x82FD, 0x82F7, 0x02F2, + 0x02D0, 0x82D5, 0x82DF, 0x02DA, 0x82CB, 0x02CE, 0x02C4, 0x82C1, + 0x8243, 0x0246, 0x024C, 0x8249, 0x0258, 0x825D, 0x8257, 0x0252, + 0x0270, 0x8275, 0x827F, 0x027A, 0x826B, 0x026E, 0x0264, 0x8261, + 0x0220, 0x8225, 0x822F, 0x022A, 0x823B, 0x023E, 0x0234, 0x8231, + 0x8213, 0x0216, 0x021C, 0x8219, 0x0208, 0x820D, 0x8207, 0x0202 +}; + +//***************************************************************************** +// +// Helper macros for delays. +// +//***************************************************************************** +#define delay_ms(ms) am_hal_flash_delay(FLASH_CYCLES_US(1000 * (ms))) +#define delay_us(us) am_hal_flash_delay(FLASH_CYCLES_US(us)) + +#define WHILE_TIMEOUT_MS(expr, timeout, error) \ + { \ + uint32_t ui32Timeout = 0; \ + while (expr) \ + { \ + if (ui32Timeout == (timeout * 1000)) \ + { \ + return error; \ + } \ + \ + delay_us(1); \ + ui32Timeout++; \ + } \ + } + +#define WHILE_TIMEOUT_MS_BREAK(expr, timeout, error) \ + { \ + uint32_t ui32Timeout = 0; \ + while (expr) \ + { \ + if (ui32Timeout == (timeout * 1000)) \ + { \ + break; \ + } \ + \ + delay_us(1); \ + ui32Timeout++; \ + } \ + } +//***************************************************************************** +// +// Helper function for checking BLE data. +// +//***************************************************************************** +static bool +buffer_compare(void *b1, void *b2, uint32_t len) +{ + uint8_t *p1 = b1; + uint8_t *p2 = b2; + + for (uint32_t i = 0; i < len; i++) + { + if (p1[i] != p2[i]) + { + return false; + } + } + + return true; +} + +//***************************************************************************** +// +// Helper function for CRC caculation of BLE patch. +// +//***************************************************************************** +static uint16_t +am_hal_ble_crc_nz(uint8_t *pui8Data, uint32_t len) +{ + uint16_t ui16CurValue = 0; + uint32_t i; + + for (i = 0; i < len; i++) + { + ui16CurValue = ccitt_table[(((uint8_t)(ui16CurValue >> 8)) ^ pui8Data[i]) & 0xFF] ^ (ui16CurValue << 8); + } + + return ((ui16CurValue ^ 0) & ((1 << 16) - 1)); +} + +//***************************************************************************** +// +// Default options for the BLE module. +// +//***************************************************************************** +const am_hal_ble_config_t am_hal_ble_default_config = +{ + // Configure the HCI interface clock for 6 MHz + .ui32SpiClkCfg = AM_HAL_BLE_HCI_CLK_DIV8, + + // Set HCI read and write thresholds to 32 bytes each. + .ui32ReadThreshold = 32, + .ui32WriteThreshold = 32, + + // The MCU will supply the clock to the BLE core. + .ui32BleClockConfig = AM_HAL_BLE_CORE_MCU_CLK, + + // Default settings for expected BLE clock drift. + .ui32ClockDrift = 0, + .ui32SleepClockDrift = 50, + + // Default setting - AGC Enabled + .bAgcEnabled = true, + + // Default setting - Sleep Algo enabled + .bSleepEnabled = true, + + // Apply the default patches when am_hal_ble_boot() is called. + .bUseDefaultPatches = true, +}; + +//***************************************************************************** +// +// Function for controlling the WAKE signal. +// +//***************************************************************************** +uint32_t +am_hal_ble_wakeup_set(void *pHandle, uint32_t ui32Mode) +{ + am_hal_ble_state_t *pBle = pHandle; + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + +// am_hal_debug_gpio_set(BLE_DEBUG_TRACE_08); + + if ( ui32Mode ) + { + BLEIFn(pBle->ui32Module)->BLECFG_b.WAKEUPCTL = BLEIF_BLECFG_WAKEUPCTL_ON; + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_08); + } + else + { +#ifndef AM_DISABLE_BLE_SLEEP + BLEIFn(pBle->ui32Module)->BLECFG_b.WAKEUPCTL = BLEIF_BLECFG_WAKEUPCTL_OFF; + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_08); +#endif + } + + return AM_HAL_STATUS_SUCCESS; + +// am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_08); +} + +//***************************************************************************** +// +// Buffer for patch data. +// +//***************************************************************************** +am_hal_ble_buffer(128 + 4) g_psPatchBuffer; + +//***************************************************************************** +// +// Initialize the global variables associated with a BLE module, and return its +// handle. +// +//***************************************************************************** +uint32_t +am_hal_ble_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check the arguments. + // + if (ui32Module >= AM_REG_BLEIF_NUM_MODULES) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_sBLEState[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + memset(&g_sBLEState[ui32Module].sCurrentTransfer, 0, sizeof(am_hal_ble_transfer_t)); + memset(&g_sBLEState[ui32Module].sSavedTransfer, 0, sizeof(am_hal_ble_transfer_t)); + + g_sBLEState[ui32Module].prefix.s.bInit = true; + g_sBLEState[ui32Module].prefix.s.magic = AM_HAL_MAGIC_BLE; + g_sBLEState[ui32Module].ui32Module = ui32Module; + g_sBLEState[ui32Module].ui32TransferIndex = 0; + g_sBLEState[ui32Module].bPatchComplete = 0; + g_sBLEState[ui32Module].bContinuePacket = 0; + g_sBLEState[ui32Module].bSavedPacket = 0; + g_sBLEState[ui32Module].bBusy = 0; + g_sBLEState[ui32Module].bCmdComplete = 0; + g_sBLEState[ui32Module].bDmaComplete = 0; + g_sBLEState[ui32Module].bFlowControlComplete = 0; + g_sBLEState[ui32Module].bUseDefaultPatches = false; + + // + // Pass the handle back to the caller. + // + *ppHandle = &g_sBLEState[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_initialize() + +//***************************************************************************** +// +// Initialize the global variables associated with a BLE module, and return its +// handle. +// +//***************************************************************************** +uint32_t +am_hal_ble_deinitialize(void *pHandle) +{ + am_hal_ble_state_t *pBLE = (am_hal_ble_state_t *)pHandle; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Initialize the handle. + // + memset(&(pBLE->sCurrentTransfer), 0, sizeof(am_hal_ble_transfer_t)); + + pBLE->prefix.s.bInit = false; + pBLE->prefix.s.magic = 0; + pBLE->ui32Module = 0; + pBLE->ui32TransferIndex = 0; + pBLE->bPatchComplete = 0; + pBLE->bContinuePacket = 0; + pBLE->bSavedPacket = 0; + pBLE->bBusy = 0; + pBLE->bCmdComplete = 0; + pBLE->bDmaComplete = 0; + pBLE->bFlowControlComplete = 0; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_deinitialize() + +//***************************************************************************** +// +// Configuration function. +// +//***************************************************************************** +uint32_t +am_hal_ble_config(void *pHandle, const am_hal_ble_config_t *psConfig) +{ + uint32_t ui32Module; + uint32_t ui32BleClkConfig; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Configure the SPI. + // + BLEIFn(ui32Module)->MSPICFG = 0x3; + BLEIFn(ui32Module)->MSPICFG_b.RDFC = 0; + BLEIFn(ui32Module)->MSPICFG_b.WTFC = 0; + BLEIFn(ui32Module)->MSPICFG_b.WTFCPOL = 1; + BLEIFn(ui32Module)->FIFOTHR_b.FIFOWTHR = psConfig->ui32WriteThreshold; + BLEIFn(ui32Module)->FIFOTHR_b.FIFORTHR = psConfig->ui32ReadThreshold; + BLEIFn(ui32Module)->FIFOCTRL |= BLEIF_FIFOCTRL_POPWR_Msk; + + // + // Clock configuration register writes need to be combined to a single + // operation. + // + ui32BleClkConfig = _VAL2FLD(BLEIF_CLKCFG_FSEL, psConfig->ui32SpiClkCfg); + ui32BleClkConfig |= _VAL2FLD(BLEIF_CLKCFG_IOCLKEN, 1); + + if (psConfig->ui32BleClockConfig == AM_HAL_BLE_CORE_MCU_CLK) + { + ui32BleClkConfig |= _VAL2FLD(BLEIF_CLKCFG_CLK32KEN, 1); + } + + BLEIFn(ui32Module)->CLKCFG = ui32BleClkConfig; + + if (APOLLO3_A1) + { + // + // Modify the BLE core's NVDS settings to match our configuration. + // + uint8_t *pui8NVDSData = (uint8_t *) am_ble_nvds_patch.pui32Data; + + // + // Set the clock source. + // + pui8NVDSData[AM_HAL_BLE_NVDS_CLOCKSOURCE_OFFSET + 3] = + (psConfig->ui32BleClockConfig & 0xFF); + + // + // Set the expected BLE clock drift PPM + // + pui8NVDSData[AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET + 3] = + (psConfig->ui32ClockDrift & 0x00FF); + + pui8NVDSData[AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET + 4] = + (psConfig->ui32ClockDrift & 0xFF00) >> 8; + + // + // Set the sleep clock drift PPM. + // + pui8NVDSData[AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET + 3] = + (psConfig->ui32SleepClockDrift & 0x00FF); + + pui8NVDSData[AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET + 4] = + (psConfig->ui32SleepClockDrift & 0xFF00) >> 8; + + // + // Configure Sleep mode. + // + pui8NVDSData[AM_HAL_BLE_NVDS_SLEEPENABLE_OFFSET + 3] = (psConfig->bSleepEnabled == true) ? 1 : 0; + // + // Configure AGC. + // + pui8NVDSData[AM_HAL_BLE_NVDS_AGC_OFFSET + 3] = (psConfig->bAgcEnabled == true) ? 1 : 0; + + // + // Update the CRC. + // + am_ble_nvds_patch.ui32CRC = am_hal_ble_crc_nz(pui8NVDSData, + am_ble_nvds_patch.ui32Length); + } + + // + // Save the addresses to the patches we intend to use. + // + g_sBLEState[ui32Module].bUseDefaultPatches = psConfig->bUseDefaultPatches; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_config() + +//***************************************************************************** +// +// Enable BLE +// +//***************************************************************************** +uint32_t +am_hal_ble_power_control(void *pHandle, uint32_t ui32PowerState) +{ + uint32_t ui32Module; + + // + // BLE buck is shared by Burst as well + // Enable the BLE buck trim values if in use + // + am_hal_pwrctrl_blebuck_trim(); + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + if (ui32PowerState == AM_HAL_BLE_POWER_ACTIVE) + { + // + // Don't run this initialization if the BLE is already enabled. + // + if ( PWRCTRL->DEVPWRSTATUS_b.BLEL == 0) + { + MCUCTRL->FEATUREENABLE |= 1; + WHILE_TIMEOUT_MS ( ((MCUCTRL->FEATUREENABLE & 0x7) != 0x7), 100, + AM_HAL_BLE_FEATURE_DISABLED ); + + // + // Enable the BLE module. + // + if (am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_BLEL) != + AM_HAL_STATUS_SUCCESS) + { + return AM_HAL_BLE_REGULATOR_FAILED; + } + + // + // Release the BLE module RESET, start the "power state machine", and + // enable the clocks. + // + BLEIFn(ui32Module)->CLKCFG = _VAL2FLD(BLEIF_CLKCFG_CLK32KEN, 1); + BLEIFn(ui32Module)->BLEDBG_b.DBGDATA = 1 << 14; + + // + // The reset bit is different between A0 and subsequent revisions. + // + if ( APOLLO3_GE_A1 ) + { + MCUCTRL->MISCCTRL_b.BLE_RESETN = 1; + } + else + { + AM_REGVAL(0x40020198) = 0x1 << 2; + } + + delay_ms(5); + BLEIFn(ui32Module)->BLECFG_b.PWRSMEN = 1; + + // + // Wait for indication that the power is on. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.PWRST != 3, 1000, + AM_HAL_BLE_POWERUP_INCOMPLETE ); + } + } + else if (ui32PowerState == AM_HAL_BLE_POWER_OFF) + { + // + // Reverse of power-up. Disable clocks, set reset, then disable power. + // + BLEIFn(ui32Module)->CLKCFG = 0; + BLEIF->BLEDBG_b.DBGDATA = 0; + + if ( APOLLO3_GE_A1 ) + { + MCUCTRL->MISCCTRL_b.BLE_RESETN = 0; + } + else + { + AM_REGVAL(0x40020198) &= ~(0x1 << 2); + } + + BLEIF->BLECFG_b.PWRSMEN = 0; + + if (am_hal_pwrctrl_periph_disable(AM_HAL_PWRCTRL_PERIPH_BLEL) != + AM_HAL_STATUS_SUCCESS) + { + return AM_HAL_BLE_SHUTDOWN_FAILED; + } + + delay_us(100); + } + else + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_power_control() + +//***************************************************************************** +// +// Perform all of the operations necessary to prepare the BLE controller for +// HCI operation. +// +//***************************************************************************** +uint32_t +am_hal_ble_boot(void *pHandle) +{ + uint32_t ui32Status; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // The handle is good, so we can access it as a structure. + // + am_hal_ble_state_t *pBLE = pHandle; + + if (pBLE->bUseDefaultPatches) + { + // + // The B0 silicon patching method is slightly different from A1. B0 silicon + // does not require the Copy Patch method introduced for A1 silicon. + // + if (APOLLO3_A0 || APOLLO3_A1) + { + ui32Status = am_hal_ble_default_copy_patch_apply(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + } + + // + // Apply the BLE trim value + // + ui32Status = am_hal_ble_default_trim_set_ramcode(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + // + // Apply the NVDS patch. + // + ui32Status = am_hal_ble_default_patch_apply(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + // + // Complete the patching step + // + ui32Status = am_hal_ble_patch_complete(pHandle); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + } + + if (am_hal_ble_check_32k_clock(pBLE) == AM_HAL_STATUS_FAIL) + { + return AM_HAL_BLE_32K_CLOCK_UNSTABLE; + } + else + { + return AM_HAL_STATUS_SUCCESS; + } +} // am_hal_ble_boot() + +//***************************************************************************** +// +// Apply a patch. +// +// Returns 0 for success or a numerical error code for failures. +// +//***************************************************************************** +uint32_t +am_hal_ble_patch_apply(void *pHandle, am_hal_ble_patch_t *psPatch) +{ + uint8_t pui8ExpectedResponse[32]; + uint32_t ui32ErrorStatus; + uint32_t ui32Trial; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + am_hal_ble_transfer_t sTransfer; + am_hal_ble_buffer(16) psPatchBuffer; + + // + // Send a header packet. + // + psPatchBuffer.bytes[0] = 0x01; + psPatchBuffer.bytes[1] = psPatch->ui32Type; + psPatchBuffer.bytes[2] = 0xF1; + psPatchBuffer.bytes[3] = 0x02; + psPatchBuffer.bytes[4] = (psPatch->ui32Length & 0xFF); + psPatchBuffer.bytes[5] = ((psPatch->ui32Length >> 8) & 0xFF); + + // + // This first packet might take a few tries. + // + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_hci_write(pHandle, + AM_HAL_BLE_RAW, + psPatchBuffer.words, + 6); + + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + break; + } + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + // + // Wait for the header response. It should be 5 bytes long. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = psPatch->ui32Type; + pui8ExpectedResponse[2] = 0xF1; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Send all of the data, including the acknowledgements. + // + uint32_t ui32RemainingBytes = psPatch->ui32Length; + uint32_t ui32Index = 0; + + while (ui32RemainingBytes) + { + // + // Figure out how many bytes to send in the next packet. + // + uint32_t ui32TransferSize = (ui32RemainingBytes > MAX_PATCH_PACKET_LEN ? + MAX_PATCH_PACKET_LEN : ui32RemainingBytes); + + // + // Send a data header. + // + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_WRITE; + sTransfer.pui32Data = g_psPatchBuffer.words; + sTransfer.ui16Length = ui32TransferSize + 4; + sTransfer.bContinue = false; + + g_psPatchBuffer.bytes[0] = 0x01; + g_psPatchBuffer.bytes[1] = psPatch->ui32Type; + g_psPatchBuffer.bytes[2] = 0xF2; + g_psPatchBuffer.bytes[3] = ui32TransferSize; + + // copy data into buffer + memcpy(&g_psPatchBuffer.bytes[4], (uint8_t *)&(psPatch->pui32Data[ui32Index / 4]), ui32TransferSize); + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Read the acknowledgement. + // + WHILE_TIMEOUT_MS( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, + AM_HAL_BLE_NO_HCI_RESPONSE); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = psPatch->ui32Type; + pui8ExpectedResponse[2] = 0xF2; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Update the tracking variables + // + ui32RemainingBytes -= ui32TransferSize; + ui32Index += ui32TransferSize; + } + + // + // Send the CRC, and make sure we got it right. + // + psPatchBuffer.bytes[0] = 0x01; + psPatchBuffer.bytes[1] = psPatch->ui32Type; + psPatchBuffer.bytes[2] = 0xF3; + psPatchBuffer.bytes[3] = 0x02; + psPatchBuffer.bytes[4] = (psPatch->ui32CRC & 0xFF); + psPatchBuffer.bytes[5] = ((psPatch->ui32CRC >> 8) & 0xFF); + + if (am_hal_ble_blocking_hci_write(pHandle, AM_HAL_BLE_RAW, psPatchBuffer.words, 6) != + AM_HAL_STATUS_SUCCESS) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Wait for the header response. It should be 5 bytes long. + // + WHILE_TIMEOUT_MS( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = psPatch->ui32Type; + pui8ExpectedResponse[2] = 0xF3; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + return AM_HAL_STATUS_FAIL; + } + else + { + return AM_HAL_STATUS_SUCCESS; + } +} // am_hal_ble_patch_apply() + +uint32_t +am_hal_ble_patch_copy_end_apply(void *pHandle) +{ + uint8_t pui8ExpectedResponse[32]; + uint32_t ui32ErrorStatus; + uint32_t ui32Trial; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + am_hal_ble_transfer_t sTransfer; + am_hal_ble_buffer(16) psPatchBuffer; + + // + // Send a header packet. + // + psPatchBuffer.bytes[0] = 0x01; + psPatchBuffer.bytes[1] = 0xEE; + psPatchBuffer.bytes[2] = 0xF1; + psPatchBuffer.bytes[3] = 0x02; + psPatchBuffer.bytes[4] = 0x00; + psPatchBuffer.bytes[5] = 0x00; + + // + // This first packet might take a few tries. + // + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_hci_write(pHandle, + AM_HAL_BLE_RAW, + psPatchBuffer.words, + 6); + + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + + break; + } + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + + return ui32ErrorStatus; + } + + // + // Wait for the header response. It should be 5 bytes long. + // + WHILE_TIMEOUT_MS( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 1000, AM_HAL_BLE_NO_HCI_RESPONSE); + + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = psPatchBuffer.words; + sTransfer.ui16Length = 5; + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + + return ui32ErrorStatus; + } + + pui8ExpectedResponse[0] = 0x04; + pui8ExpectedResponse[1] = 0xEE; + pui8ExpectedResponse[2] = 0xF1; + pui8ExpectedResponse[3] = 0x01; + pui8ExpectedResponse[4] = 0x00; + + if (!buffer_compare(psPatchBuffer.words, pui8ExpectedResponse, 5)) + { + + return AM_HAL_STATUS_FAIL; + } + return 0; +} // am_hal_ble_patch_copy_end_apply() + +//***************************************************************************** +// +// Apply the default copy patch. +// +// Returns 0 for success or a numerical error code for failures. +// +//***************************************************************************** +uint32_t +am_hal_ble_default_copy_patch_apply(void *pHandle) +{ + uint32_t ui32Status; + uint16_t ui16Crc; + + am_hal_ble_patch_t **psCopyPatch; + + psCopyPatch = am_hal_ble_default_copy_patches; + + ui16Crc = am_hal_ble_crc_nz((uint8_t*)(psCopyPatch[0]->pui32Data), psCopyPatch[0]->ui32Length); + psCopyPatch[0]->ui32CRC = ui16Crc; + ui32Status = am_hal_ble_patch_apply(pHandle, psCopyPatch[0]); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + ui32Status = am_hal_ble_patch_copy_end_apply(pHandle); + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Apply the default patch. +// +// Returns 0 for success or a numerical error code for failures. +// +//***************************************************************************** +uint32_t +am_hal_ble_default_patch_apply(void *pHandle) +{ + uint32_t ui32Status, i = 0; + uint16_t ui16Crc; + uint32_t ui32NumPatches; + am_hal_ble_patch_t **psDefaultPatches; + + if (APOLLO3_A0 || APOLLO3_A1) + { + ui32NumPatches = am_hal_ble_num_default_patches; + psDefaultPatches = am_hal_ble_default_patches; + } + else + { + ui32NumPatches = am_hal_ble_num_default_patches_b0; + psDefaultPatches = am_hal_ble_default_patches_b0; + } + + for ( i = 0; i < ui32NumPatches; i++ ) + { + ui16Crc = am_hal_ble_crc_nz((uint8_t*)(psDefaultPatches[i]->pui32Data), psDefaultPatches[i]->ui32Length); + psDefaultPatches[i]->ui32CRC = ui16Crc; + ui32Status = am_hal_ble_patch_apply(pHandle, psDefaultPatches[i]); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_default_patch_apply() + +//***************************************************************************** +// +// Complete the patching process +// +//***************************************************************************** +uint32_t +am_hal_ble_patch_complete(void *pHandle) +{ + uint32_t ui32ErrorStatus; + am_hal_ble_transfer_t sTransfer; + am_hal_ble_buffer(12) sTxBuffer; + am_hal_ble_buffer(12) sRxBuffer; + uint32_t ui32Trial; + + am_hal_ble_state_t *pBLE = pHandle; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + uint32_t ui32Module = pBLE->ui32Module; + + // + // Write the "patch complete" command. + // + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_WRITE; + sTransfer.pui32Data = sTxBuffer.words; + sTransfer.ui16Length = 6; + + sTxBuffer.bytes[0] = 0x01; + sTxBuffer.bytes[1] = 0xEE; + sTxBuffer.bytes[2] = 0xF1; + sTxBuffer.bytes[3] = 0x02; + sTxBuffer.bytes[4] = 0x00; + sTxBuffer.bytes[5] = 0x00; + + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_CMP_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + break; + } + } + + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 100, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + // + // Read back the response. + // + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = sRxBuffer.words; + sTransfer.ui16Length = 2; + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Check to see which format the response came back in. If it doesn't have + // a 2-byte length header, we need to manually override the length, and + // continue on to adjust the HCI format in the next packet. Otherwise, we + // can just return from here. + // + if ( sRxBuffer.bytes[1] == 0xEE ) + { + sTransfer.ui16Length = 3; + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + } + else + { + sTransfer.ui16Length = (sRxBuffer.bytes[0] + (sRxBuffer.bytes[1] << 8)); + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Make sure to remember that we've sent the "patch complete" packet. + // + pBLE->bPatchComplete = true; + + return AM_HAL_STATUS_SUCCESS; + } + + // + // If we made it here, we need to tell the radio that we need two-byte + // headers prepended to each HCI packet it sends us. + // + memset(&sTransfer, 0, sizeof(am_hal_ble_transfer_t)); + sTransfer.ui8Command = AM_HAL_BLE_WRITE; + sTransfer.pui32Data = sTxBuffer.words; + sTransfer.ui16Length = 5; + + sTxBuffer.bytes[0] = 0x01; + sTxBuffer.bytes[1] = 0x04; + sTxBuffer.bytes[2] = 0xFD; + sTxBuffer.bytes[3] = 0x01; + sTxBuffer.bytes[4] = 0x01; + + for ( ui32Trial = 0; ui32Trial < AM_BLE_NUM_PATCH_CMP_TRIALS; ui32Trial++) + { + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + break; + } + } + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 100, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + sTransfer.ui8Command = AM_HAL_BLE_READ; + sTransfer.pui32Data = sRxBuffer.words; + sTransfer.ui16Length = 9; + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &sTransfer); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS ) + { + return ui32ErrorStatus; + } + + // + // Now that we're done patching, we can let the radio sleep. + // + am_hal_ble_wakeup_set(pBLE, 0); + + // + // Make sure to remember that we've sent the "patch complete" packet. + // + pBLE->bPatchComplete = true; + + // + // Delay to give the BLE core time to take the patch (assuming a patch was sent). + // + delay_ms(500); + + // + // Load the modex trim data to the BLE controller. + // + am_hal_ble_load_modex_trim_set(pBLE); + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_patch_complete() + +//***************************************************************************** +// +// Set one of the trim values for the BLE core. +// +//***************************************************************************** +uint32_t +am_hal_ble_trim_set(void *pHandle, uint32_t ui32BleCoreAddress, uint32_t ui32TrimValue, uint32_t ui32TrimMask) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32TrimValueSwapped, ui32LockValue, ui32ReadVal, ui32WriteVal; + + ui32TrimValueSwapped = (((ui32TrimValue & 0x000000FF) << 24) | + ((ui32TrimValue & 0x0000FF00) << 8) | + ((ui32TrimValue & 0x00FF0000) >> 8) | + ((ui32TrimValue & 0xFF000000) >> 24)); + + if (ui32TrimValue != 0xFFFFFFFF) + { + // + // Unlock the BLE registers and save the "lock register" value. + // + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &ui32LockValue); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + + // + // Check to see if we need a bitfield mask. If not, we can just write + // directly. + // + if (ui32TrimMask == 0xFFFFFFFF) + { + am_hal_ble_plf_reg_write(pBLE, ui32BleCoreAddress, ui32TrimValueSwapped); + } + else + { + // + // If we do need a mask, read the register, mask out the old bits, + // OR in the new, and write the new value back. + // + am_hal_ble_plf_reg_read(pBLE, ui32BleCoreAddress, &ui32ReadVal); + ui32WriteVal = ((ui32ReadVal & (~ui32TrimMask)) | ui32TrimValueSwapped); + + am_hal_ble_plf_reg_write(pBLE, ui32BleCoreAddress, ui32WriteVal); + } + + // + // Unlock the BLE register. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, ui32LockValue); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_trim_set() + +//***************************************************************************** +// +// Set the bandgap voltage, bandgap current, and retention LDO output values +// based on the tested values stored in non-volatile memory. +// +//***************************************************************************** +uint32_t +am_hal_ble_default_trim_set_ramcode(void *pHandle) +{ + uint32_t ui32TrimValue; + uint32_t ui32TrimValueSwapped; + uint32_t *pRamCode; + + if (APOLLO3_B0) + { + pRamCode = (uint32_t *) (am_ble_performance_patch_b0.pui32Data); + } + else + { + pRamCode = (uint32_t *) (am_ble_performance_patch.pui32Data); + } + + // + // Set the bandgap voltage and current. + // + //ui32TrimValue = (AM_REGVAL(0x50023800) | (0x0F000000)) & (0xEFFFFFFF); + ui32TrimValue = AM_REGVAL(0x50023800); + ui32TrimValueSwapped = (((ui32TrimValue & 0x000000FF) << 24) | + ((ui32TrimValue & 0x0000FF00) << 8) | + ((ui32TrimValue & 0x00FF0000) >> 8) | + ((ui32TrimValue & 0xFF000000) >> 24)); + + if (ui32TrimValueSwapped != 0xFFFFFFFF) + { + pRamCode[2] = ui32TrimValueSwapped; + } + + // + // Set the retention LDO voltage. + // + ui32TrimValue = AM_REGVAL(0x50023804); + if (ui32TrimValue != 0xFFFFFFFF) + { + // 0xFFFFFFFF means the part has not been trimed. + ui32TrimValue += 0x40000000; // Increase the retention voltage to > 0.75v + } + ui32TrimValueSwapped = (((ui32TrimValue & 0x000000FF) << 24) | + ((ui32TrimValue & 0x0000FF00) << 8) | + ((ui32TrimValue & 0x00FF0000) >> 8) | + ((ui32TrimValue & 0xFF000000) >> 24)); + + if ( ui32TrimValueSwapped != 0xFFFFFFFF ) + { + pRamCode[3] = ((pRamCode[3] & (~0x1F0)) | ui32TrimValueSwapped); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_default_trim_set_ramcode() + +//***************************************************************************** +// +// Builds a vendor-specific BLE command. +// +//***************************************************************************** +uint32_t +am_hal_ble_vs_command_build(uint32_t *pui32Command, uint32_t ui32OpCode, + uint32_t ui32TotalLength, uint8_t *pui8Parameters) +{ + uint8_t *pui8Dest = (uint8_t *) pui32Command; + + // + // Build the header portion of the command from the given argments. + // + pui8Dest[0] = 0x01; + pui8Dest[1] = ui32OpCode & 0xFF; + pui8Dest[2] = (ui32OpCode >> 8) & 0xFF; + pui8Dest[3] = (ui32TotalLength - 4) & 0xFF; + + // + // Finish filling the array with any parameters that may be required. + // + for (uint32_t i = 4; i < ui32TotalLength; i++) + { + pui8Dest[i] = pui8Parameters[i - 4]; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_vs_command_build() + +//***************************************************************************** +// +// Returns the number of bytes written. +// +//***************************************************************************** +uint32_t +am_hal_ble_blocking_hci_write(void *pHandle, uint8_t ui8Type, + uint32_t *pui32Data, uint32_t ui32NumBytes) +{ + uint32_t ui32ErrorStatus; + + am_hal_ble_transfer_t HciWrite = + { + .pui32Data = pui32Data, + .pui8Offset = {ui8Type, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = ui32NumBytes, + .ui8Command = AM_HAL_BLE_WRITE, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = 0x0, + .pvContext = 0x0, + }; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + // + // Fix up the offset length based on the packet type, and send the bytes. + // + if (ui8Type != AM_HAL_BLE_RAW) + { + HciWrite.ui8OffsetLen = 1; + } + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &HciWrite); + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_blocking_hci_write() + +//***************************************************************************** +// +// Returns the number of bytes received. +// +//***************************************************************************** +uint32_t +am_hal_ble_blocking_hci_read(void *pHandle, uint32_t *pui32Data, uint32_t *pui32BytesReceived) +{ + uint32_t ui32Module, ui32NumBytes, ui32ErrorStatus; + + am_hal_ble_buffer(2) sLengthBytes; + + am_hal_ble_transfer_t HciRead = + { + .pui32Data = sLengthBytes.words, + .pui8Offset = {0x0, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = 2, + .ui8Command = AM_HAL_BLE_READ, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = 0x0, + .pvContext = 0x0, + }; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Make sure the IRQ signal is set. + // + if ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ ) + { + // + // Read the length bytes. + // + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &HciRead); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + // + // Read the rest of the packet. + // + HciRead.pui32Data = pui32Data; + HciRead.ui16Length = (sLengthBytes.bytes[0] + + (sLengthBytes.bytes[1] << 8)); + + // + // Check if the length is not out of the boundary + // + // Fixme: it is assumed here all the sizes of the buffer are 256 + if (HciRead.ui16Length > 256) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + ui32ErrorStatus = am_hal_ble_blocking_transfer(pHandle, &HciRead); + if ( ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + return ui32ErrorStatus; + } + + ui32NumBytes = HciRead.ui16Length; + } + else + { + ui32NumBytes = 0; + } + + if (pui32BytesReceived) + { + *pui32BytesReceived = ui32NumBytes; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_blocking_hci_read() + +//***************************************************************************** +// +// Returns the number of bytes written. +// +//***************************************************************************** +uint32_t +am_hal_ble_nonblocking_hci_write(void *pHandle, uint8_t ui8Type, + uint32_t *pui32Data, uint32_t ui32NumBytes, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext) +{ + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + am_hal_ble_transfer_t HciWrite = + { + .pui32Data = pui32Data, + .pui8Offset = {ui8Type, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = ui32NumBytes, + .ui8Command = AM_HAL_BLE_WRITE, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = pfnCallback, + .pvContext = pvContext, + }; + + // + // Fix up the offset length based on the packet type, and send the bytes. + // + if (ui8Type != AM_HAL_BLE_RAW) + { + HciWrite.ui8OffsetLen = 1; + } + + uint32_t ui32Status = am_hal_ble_nonblocking_transfer(pHandle, &HciWrite); + + return ui32Status; +} // am_hal_ble_nonblocking_hci_write() + +//***************************************************************************** +// +// Returns the number of bytes received. +// +//***************************************************************************** +uint32_t +am_hal_ble_nonblocking_hci_read(void *pHandle, uint32_t *pui32Data, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext) +{ + uint32_t ui32Status; + am_hal_ble_state_t *pBle = pHandle; + + am_hal_ble_buffer(2) sLengthBytes; + + am_hal_ble_transfer_t HciRead = + { + .pui32Data = sLengthBytes.words, + .pui8Offset = {0x0, 0x0, 0x0}, + .ui8OffsetLen = 0, + .ui16Length = 2, + .ui8Command = AM_HAL_BLE_READ, + .ui8RepeatCount = 0, + .bContinue = false, + .pfnTransferCompleteCB = pfnCallback, + .pvContext = pvContext, + }; + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Make sure the IRQ signal is set. + // + if ( am_hal_ble_check_irq(pBle) ) + { + // + // Read the length bytes. + // + ui32Status = am_hal_ble_blocking_transfer(pHandle, &HciRead); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Read the rest of the packet. + // + HciRead.pfnTransferCompleteCB = pfnCallback; + HciRead.pui32Data = pui32Data; + HciRead.ui16Length = (sLengthBytes.bytes[0] + + (sLengthBytes.bytes[1] << 8)); + + return am_hal_ble_nonblocking_transfer(pHandle, &HciRead); + } + + // + // If we get here, return fail. + // + return AM_HAL_STATUS_FAIL; +} // am_hal_ble_nonblocking_hci_read() + +//***************************************************************************** +// +// Return true if BSTATUS is high. +// +//***************************************************************************** +static bool +am_hal_ble_check_status(am_hal_ble_state_t *pBle) +{ + // + // We need to make a special exception for "continue" packets, since the + // BLE radio may deassert the STATUS signal mid-packet. + // + if (pBle->bContinuePacket) + { + pBle->bContinuePacket = false; + return true; + } + + if ( BLEIFn(0)->BSTATUS_b.SPISTATUS == 0) + { + return false; + } + + return true; +} // am_hal_ble_check_status() + +//***************************************************************************** +// +// Return true if IRQ is high. +// +//***************************************************************************** +static bool +am_hal_ble_check_irq(am_hal_ble_state_t *pBle) +{ + if ( BLEIFn(pBle->ui32Module)->BSTATUS_b.BLEIRQ ) + { + return true; + } + + return false; +} // am_hal_ble_check_irq() + +//***************************************************************************** +// +// Return true if we recently received a BSTATUS edge. +// +//***************************************************************************** +static bool +am_hal_ble_check_status_edge(am_hal_ble_state_t *pBle) +{ + // + // We need to make a special exception for "continue" packets, since the + // BLE radio may deassert the STATUS signal mid-packet. + // + if (pBle->bContinuePacket) + { + pBle->bContinuePacket = false; + return true; + } + + if (pBle->bPatchComplete == false) + { + return am_hal_ble_check_status(pBle); + } + + if ( BLEIFn(0)->INTSTAT_b.BLECSSTAT == 0) + { + return false; + } + + return true; +} // am_hal_ble_check_status_edge() + +//***************************************************************************** +// +// Blocking write to the BLE module. +// +//***************************************************************************** +uint32_t +am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) +{ + am_hal_ble_state_t *pBle = pHandle; + uint32_t ui32IntEnable; + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // If the transfer doesn't have any bytes in it, just return success. + // + if (psTransfer->ui16Length == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Make sure we don't get any interrupts that might interfere with this + // operation. We will save the interrupt enable register state so we can + // restore it later. Also, make sure "command complete" is clear, so we can + // detect the end of the transaction. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN_b.BLECIRQ = 0; + BLEIFn(ui32Module)->INTEN_b.BLECSSTAT = 0; + BLEIFn(ui32Module)->INTEN_b.CMDCMP = 0; + BLEIFn(ui32Module)->INTEN_b.THR = 0; + BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; + BLEIFn(ui32Module)->INTCLR_b.BLECSSTAT = 1; + + // + // If we're writing, we need to lock down the bus now. Set the wakeup + // signal, and start monitoring STATUS. If STATUS isn't high within our + // configured timeout, we have to assume that the BLE core is unresponsive + // and report an error back to the caller. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + uint32_t ui32SpiStatus = false; + + if ( pBle->bLastPacketWasTX == true) + { + // + // wait some time to give the controller more time to consume + // the last TX packet + // + if (!pBle->bPatchComplete) + { + delay_ms(3); + } + pBle->bLastPacketWasTX = false; + } + + if (pBle->bPatchComplete) + { + uint32_t statusTimeout = 0; + while (am_hal_ble_check_status(pBle) == true) + { + statusTimeout++; + delay_us(10); + if (statusTimeout > 300) + { + break; + } + } + } + + // + // Make sure the IO clock for the STATUS signal is on. + // + BLEIFn(0)->BLEDBG_b.IOCLKON = 1; + delay_us(5); + + // + // Set WAKE, and wait for a positive edge on the STATUS signal. + // + am_hal_ble_wakeup_set(pBle, 1); + + // + // If we don't see an edge on STATUS in X ms, assume it's not coming + // and return with an AM_HAL_BLE_STATUS_SPI_NOT_READY error. + // + uint32_t ui32Timeout = 0; + uint32_t ui32TimeoutLimit = AM_BLE_STATUS_TIMEOUT; + + while (1) + { + if (am_hal_ble_check_status_edge(pBle) == true) + { + if (am_hal_ble_bus_lock(pBle)) + { + ui32SpiStatus = AM_HAL_STATUS_SUCCESS; + break; + } + } + else if ((ui32Timeout == ui32TimeoutLimit) || + (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ)) + { + ui32SpiStatus = AM_HAL_BLE_STATUS_SPI_NOT_READY; + am_hal_ble_wakeup_set(pBle, 0); + break; + } + + ui32Timeout++; + delay_us(10); + } + + // + // Disable IOCLK + // + BLEIFn(0)->BLEDBG_b.IOCLKON = 0; + + if (ui32SpiStatus != AM_HAL_STATUS_SUCCESS) + { + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + am_hal_ble_wakeup_set(pBle, 0); + return ui32SpiStatus; + } + } + else + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0) + { + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + return AM_HAL_BLE_STATUS_IRQ_LOW; + } + + if (!am_hal_ble_bus_lock(pBle)) + { + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + return AM_HAL_BLE_STATUS_BUS_BUSY; + } + } + + if (psTransfer->bContinue) + { + pBle->bContinuePacket = true; + } + + // + // Set the current transfer, and clear the command complete interrupt so we + // can tell when the next command completes. + // + memcpy(&pBle->sCurrentTransfer, psTransfer, sizeof(am_hal_ble_transfer_t)); + + // + // Critical section to protect the gap between command and data. + // + AM_CRITICAL_BEGIN; + + // + // Write the command word. + // + am_hal_ble_cmd_write(pHandle, psTransfer); + + // + // Now we need to manage the fifos based on the type of transfer. In either + // case, we will keep draining or refilling the FIFO until the full + // transaction is complete. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + bool bCmdCmp = false; + uint32_t numWait = 0; + // Adjust the byte count to be sent/received for repeat count + uint32_t ui32Bytes = pBle->sCurrentTransfer.ui16Length; + + uint32_t ui32FifoRem; + uint32_t *pui32Buffer = pBle->sCurrentTransfer.pui32Data; + + // + // Write the command word. + // + am_hal_ble_cmd_write(pHandle, psTransfer); + + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while (ui32Bytes) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + while ((ui32FifoRem = BLEIFn(ui32Module)->FIFOPTR_b.FIFO0REM) < 4) + { + bCmdCmp = BLEIFn(ui32Module)->INTSTAT_b.CMDCMP; + if (bCmdCmp || (numWait++ >= AM_HAL_IOM_MAX_BLOCKING_WAIT)) + { + // + // FIFO not expected to change any more - get out + // + break; + } + else + { + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + } + if (bCmdCmp || (ui32FifoRem < 4)) + { + // + // Something went wrong - bail out + // + break; + } + + while ((ui32FifoRem >= 4) && ui32Bytes) + { + BLEIFn(ui32Module)->FIFOPUSH = *pui32Buffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + } + WHILE_TIMEOUT_MS_BREAK ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 2, + AM_HAL_BLE_HCI_PACKET_INCOMPLETE ); + am_hal_ble_wakeup_set(pBle, 0); + } + else + { + while (pBle->ui32TransferIndex < pBle->sCurrentTransfer.ui16Length) + { + am_hal_ble_fifo_drain(pHandle); + } + } + + // + // End the critical section. + // + AM_CRITICAL_END; //fixme moved further down to cover am_hal_ble_bus_release(); + + // + // Wait for the transaction to complete, and clear out any interrupts that + // may have come up. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 10, + AM_HAL_BLE_HCI_PACKET_INCOMPLETE ); + BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; + BLEIFn(ui32Module)->INTCLR_b.THR = 1; + + // + // Clear out the current transfer. We're done. + // + memset(&pBle->sCurrentTransfer, 0, sizeof(am_hal_ble_transfer_t)); + pBle->ui32TransferIndex = 0; + + // + // Let the radio go back to sleep. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + am_hal_ble_wakeup_set(pBle, 0); + pBle->bLastPacketWasTX = true; + } + + if ((psTransfer->ui8Command == AM_HAL_BLE_READ) && + (pBle->bPatchComplete == true)) + { + pBle->bLastPacketWasTX = false; + } + + // + // Restore the interrupt state. + // + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + // + // Release the bus. + // + am_hal_ble_bus_release(pBle); + + // + // End the critical section. + // + // AM_CRITICAL_END; //fixme moved further down to cover am_hal_ble_bus_release(); + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_blocking_transfer() + +//***************************************************************************** +// +// Nonblocking write to the BLE module. +// +//***************************************************************************** +uint32_t +am_hal_ble_nonblocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) +{ + am_hal_ble_state_t *pBle = pHandle; + uint32_t ui32Status; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if this is a write or a read. + // + if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) + { + ui32Status = nonblocking_write(pBle, psTransfer); + } + else // AM_HAL_BLE_READ case. + { + ui32Status = nonblocking_read(pBle, psTransfer); + } + + return ui32Status; +} // am_hal_ble_nonblocking_transfer() + +//***************************************************************************** +// +// Function for performing non-blocking writes to the HCI interface. +// +// This function will start a BLE write on the physical bus. The caller should +// have already set WAKEUP and received a STATUS interrupt before they call +// this function. When the write operation is complete, the MCU will receive a +// command complete interrupt. +// +// Before calling this function, the caller is responsible for ensuring that +// STATUS is high, that BLEIRQ is low, and the the bus isn't already in use. If +// any of these problems exists when this function is called, it will simply +// return with an error status. +// +//***************************************************************************** +static uint32_t +nonblocking_write(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer) +{ + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Module = pBle->ui32Module; + + // + // This function goes in a critical section to make sure that the operation + // isn't interrupted or started again. + // + AM_CRITICAL_BEGIN; + + do + { + // + // Check for any of the various reasons that we might not be able to + // perform a write right now. If the bus is busy, if the BLE core requires + // a READ operation, or if the BLE core simply isn't ready yet, stop here + // and throw an error. + // + if ( pBle->bBusy ) + { + ui32Status = AM_HAL_BLE_STATUS_BUS_BUSY; + break; + } + + if ( am_hal_ble_check_irq(pBle) ) + { + ui32Status = AM_HAL_BLE_REQUESTING_READ; + break; + } + + if ( !am_hal_ble_check_status(pBle) ) + { + ui32Status = AM_HAL_BLE_STATUS_SPI_NOT_READY; + break; + } + + if (psTransfer->ui16Length == 0) + { + ui32Status = AM_HAL_STATUS_SUCCESS; + break; + } + + // + // With the obvious error cases out of the way, we can claim the bus and + // start the transaction. + // + if ( pBle->bLastPacketWasTX == true ) + { + delay_us(AM_BLE_TX_PACKET_SPACING_US); + } + + pBle->bBusy = true; + pBle->bLastPacketWasTX = true; + + // + // Save the current transfer. + // + memcpy(&pBle->sCurrentTransfer, psTransfer, sizeof(am_hal_ble_transfer_t)); + + // + // Prepare the DMA. + // + BLEIFn(ui32Module)->DMATARGADDR = (uint32_t)pBle->sCurrentTransfer.pui32Data; + BLEIFn(ui32Module)->DMATOTCOUNT = pBle->sCurrentTransfer.ui16Length; + BLEIFn(ui32Module)->DMATRIGEN = BLEIF_DMATRIGEN_DTHREN_Msk; + BLEIFn(ui32Module)->DMACFG = + (_VAL2FLD(BLEIF_DMACFG_DMADIR, BLEIF_DMACFG_DMADIR_M2P) | + _VAL2FLD(BLEIF_DMACFG_DMAPRI, BLEIF_DMACFG_DMAPRI_HIGH)); + + // + // Write the command word, and enable the DMA. + // + ui32Status = am_hal_ble_cmd_write(pBle, &pBle->sCurrentTransfer); + + BLEIFn(ui32Module)->DMACFG |= _VAL2FLD(BLEIF_DMACFG_DMAEN, BLEIF_DMACFG_DMAEN_EN); + + // + // Make sure WAKE goes low as quickly as possible after starting the write. + // + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + am_hal_ble_wakeup_set(pBle, 0); + } + } + while (0); + + // + // No matter what happened above, the function should end here. We'll end + // the critical section and alert the caller of our status. + // + AM_CRITICAL_END; + return ui32Status; +} // nonblocking_write() + +//***************************************************************************** +// +// This function performs a nonblocking read from the BLE core. +// +//***************************************************************************** +static uint32_t +nonblocking_read(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer) +{ + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Module = pBle->ui32Module; + + // + // This function goes in a critical section to make sure that the operation + // isn't interrupted or started again. + // + AM_CRITICAL_BEGIN; + + do + { + if ( pBle->bBusy ) + { + ui32Status = AM_HAL_BLE_STATUS_BUS_BUSY; + break; + } + + if ( !am_hal_ble_check_irq(pBle) ) + { + ui32Status = AM_HAL_BLE_STATUS_IRQ_LOW; + break; + } + + if (psTransfer->ui16Length == 0) + { + ui32Status = AM_HAL_STATUS_SUCCESS; + break; + } + + // + // With the obvious error cases out of the way, we can claim the bus and + // start the transaction. + // + if ( pBle->bLastPacketWasTX == true ) + { + delay_us(AM_BLE_TX_PACKET_SPACING_US); + } + + pBle->bBusy = true; + pBle->bLastPacketWasTX = false; + + // + // Set the current transfer. + // + memcpy(&pBle->sCurrentTransfer, psTransfer, sizeof(am_hal_ble_transfer_t)); + + BLEIFn(ui32Module)->DMATARGADDR = (uint32_t) pBle->sCurrentTransfer.pui32Data; + BLEIFn(ui32Module)->DMATOTCOUNT = pBle->sCurrentTransfer.ui16Length; + BLEIFn(ui32Module)->DMATRIGEN = (BLEIF_DMATRIGEN_DTHREN_Msk | BLEIF_INTCLR_CMDCMP_Msk); + BLEIFn(ui32Module)->DMACFG = + (_VAL2FLD(BLEIF_DMACFG_DMADIR, BLEIF_DMACFG_DMADIR_P2M) | + _VAL2FLD(BLEIF_DMACFG_DMAPRI, BLEIF_DMACFG_DMAPRI_HIGH)); + + // + // Write the command word, and enable the DMA. + // + ui32Status = am_hal_ble_cmd_write(pBle, &pBle->sCurrentTransfer); + BLEIFn(ui32Module)->DMACFG |= _VAL2FLD(BLEIF_DMACFG_DMAEN, BLEIF_DMACFG_DMAEN_EN); + } + while (0); + + // + // No matter what happened above, the function should end here. We'll end + // the critical section and alert the caller of our status. + // + AM_CRITICAL_END; + return ui32Status; +} // nonblocking_read() + +//***************************************************************************** +// +// Mark the BLE interface busy so it doesn't get used by more than one +// interface. +// +//***************************************************************************** +static bool +am_hal_ble_bus_lock(am_hal_ble_state_t *pBle) +{ + bool bLockObtained; + + // + // In one atomic sweep, check to see if the bus is busy, and reserve it if + // it isn't. + // + AM_CRITICAL_BEGIN; + + if (pBle->bBusy == false) + { + am_hal_debug_gpio_set(BLE_DEBUG_TRACE_11); + pBle->bBusy = true; + bLockObtained = true; + pBle->bCmdComplete = 0; + pBle->bDmaComplete = 0; + pBle->bFlowControlComplete = 0; + } + else + { + bLockObtained = false; + } + + AM_CRITICAL_END; + + // + // Tell the caller if we successfully locked the bus. + // + return bLockObtained; +} // am_hal_ble_bus_lock() + +//***************************************************************************** +// +// Release the bus so someone else can use it. +// +//***************************************************************************** +static void +am_hal_ble_bus_release(am_hal_ble_state_t *pBle) +{ + pBle->bBusy = false; + am_hal_debug_gpio_clear(BLE_DEBUG_TRACE_11); +} + +//***************************************************************************** +// +// Pull data out of the fifo for reads. +// +//***************************************************************************** +static uint32_t +am_hal_ble_fifo_drain(void *pHandle) +{ + uint32_t ui32Module; + uint32_t ui32ReadSize, ui32RxDataLen, ui32BytesLeft; + uint32_t *pDest; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return 0; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Rename some pointers for convenience. + // + am_hal_ble_state_t *pBle = pHandle; + am_hal_ble_transfer_t *pTransfer = &pBle->sCurrentTransfer; + + // + // Check to see how much data there is in the FIFO, and also how many + // bytes are remaining in the transfer. + // + ui32RxDataLen = BLEIFn(ui32Module)->FIFOPTR_b.FIFO1SIZ; + ui32BytesLeft = (pTransfer->ui16Length - pBle->ui32TransferIndex); + + // + // Calculate how much we can drain the fifo. + // + if (ui32RxDataLen < 4) + { + return 0; + } + else if (ui32RxDataLen >= pTransfer->ui16Length) + { + ui32ReadSize = ui32BytesLeft; + } + else + { + ui32ReadSize = ui32RxDataLen & (~0x3); + } + + // + // Calculate the place where we last left off, feed the FIFO starting from + // that location, and update the index to match. + // + pDest = &pTransfer->pui32Data[pBle->ui32TransferIndex / 4]; + + am_hal_ble_fifo_read(pHandle, pDest, ui32ReadSize); + + pBle->ui32TransferIndex += ui32ReadSize; + + // + // Return the number of bytes we wrote. + // + return ui32ReadSize; +} // am_hal_ble_fifo_drain() + +//***************************************************************************** +// +// Write the command word for a BLE transfer. +// +//***************************************************************************** +uint32_t +am_hal_ble_cmd_write(void *pHandle, am_hal_ble_transfer_t *psTransfer) +{ + uint32_t ui32CmdWord, ui32OffsetHigh; + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Figure out the command word and the offset register. Then write them. + // + switch (psTransfer->ui8OffsetLen) + { + case 0: + ui32CmdWord = 0; + ui32OffsetHigh = 0; + break; + + case 1: + ui32CmdWord = _VAL2FLD(BLEIF_CMD_OFFSETLO, psTransfer->pui8Offset[0]); + ui32OffsetHigh = 0; + break; + + case 2: + ui32CmdWord = _VAL2FLD(BLEIF_CMD_OFFSETLO, psTransfer->pui8Offset[1]); + ui32OffsetHigh = psTransfer->pui8Offset[0]; + break; + + case 3: + ui32CmdWord = _VAL2FLD(BLEIF_CMD_OFFSETLO, psTransfer->pui8Offset[2]); + ui32OffsetHigh = ((psTransfer->pui8Offset[1]) | + (psTransfer->pui8Offset[0] << 8)); + break; + + default: + // Offset length was incorrect. + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32CmdWord |= (_VAL2FLD(BLEIF_CMD_OFFSETCNT, psTransfer->ui8OffsetLen) | + _VAL2FLD(BLEIF_CMD_TSIZE, psTransfer->ui16Length) | + _VAL2FLD(BLEIF_CMD_CONT, psTransfer->bContinue) | + psTransfer->ui8Command); + + BLEIFn(ui32Module)->OFFSETHI = ui32OffsetHigh; + BLEIFn(ui32Module)->CMD = ui32CmdWord; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_cmd_write() + +//***************************************************************************** +// +// Read ui32NumBytes from the RX FIFO. +// +//***************************************************************************** +static void +am_hal_ble_fifo_read(void *pHandle, uint32_t *pui32Data, uint32_t ui32NumBytes) +{ + uint32_t ui32Index; + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + for (ui32Index = 0; (ui32Index * 4) < ui32NumBytes; ui32Index++) + { + pui32Data[ui32Index] = BLEIFn(ui32Module)->FIFOPOP; + +#ifndef AM_HAL_BLE_NO_FIFO_PROTECTION + BLEIFn(ui32Module)->FIFOPOP = 0; +#endif + + } +} // am_hal_ble_fifo_read() + +//***************************************************************************** +// +// Call the appropriate callbacks when DMA transfers complete. +// +//***************************************************************************** +uint32_t +am_hal_ble_int_service(void *pHandle, uint32_t ui32Status) +{ + am_hal_ble_state_t *pBle = pHandle; + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // The handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + // + // Track each of the interrupts signaling the end of an HCI transfer. + // + if ( ui32Status & BLEIF_INTSTAT_CMDCMP_Msk ) + { + pBle->bCmdComplete = true; + } + + if ( ui32Status & BLEIF_INTSTAT_DCMP_Msk ) + { + pBle->bDmaComplete = true; + } + + // + // For B0 parts, we can detect when key flow control signals from the BLE + // core are de-asserted. + // + if (APOLLO3_GE_B0) + { + // + // Check for falling IRQ + // + if ( (ui32Status & BLEIF_INTSTAT_BLECIRQN_Msk) && + (pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_READ) ) + { + pBle->bFlowControlComplete = true; + } + + // + // Check for falling status. + // + if ( (ui32Status & BLEIF_INTSTAT_BLECSSTATN_Msk ) && + (pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_WRITE) ) + { + pBle->bFlowControlComplete = true; + } + } + + // + // If we get a command complete, we need to release the wake signal, + // disable the DMA, release the bus, and call any callback that might + // exist. + // + // For revision A parts, "command complete" means that the DMA operation + // and the BLE SPI interface have both finished their operations. For rev B + // parts, we will also wait for the flow control signal (either STATUS or + // IRQ) to be removed. + // + if ( pBle->bCmdComplete && pBle->bDmaComplete && + ((pBle->bFlowControlComplete) || (!APOLLO3_GE_B0) || SKIP_FALLING_EDGES) ) + { + // + // Clean up our state flags. + // + pBle->bCmdComplete = false; + pBle->bDmaComplete = false; + pBle->bFlowControlComplete = false; + + // + // If our FIFOs aren't empty right now, either the DMA didn't finish, + // or this interrupt handler is somehow being called incorrectly. + // + if ( BLEIFn(ui32Module)->FIFOPTR != 0x20002000 ) + { + return AM_HAL_BLE_FIFO_ERROR; + } + + // + // Drop the wake request if we had one, and make sure we remember if + // the last packet was a transmit packet. + // + if ((pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_WRITE) && + (pBle->bPatchComplete == true)) + { + pBle->bLastPacketWasTX = true; + am_hal_ble_wakeup_set(pBle, 0); + } + + // + // If this was a read packet, remember that it wasn't a TX packet. + // + if (pBle->sCurrentTransfer.ui8Command == AM_HAL_BLE_READ) + { + pBle->bLastPacketWasTX = false; + } + + // + // Disable the DMA + // + BLEIFn(ui32Module)->DMACFG = 0; + + am_hal_ble_bus_release(pBle); + + if ( pBle->sCurrentTransfer.pfnTransferCompleteCB ) + { + am_hal_ble_transfer_complete_cb_t pfnCallback; + uint32_t ui32Length; + uint8_t *pui8Data; + void *pvContext; + + pfnCallback = pBle->sCurrentTransfer.pfnTransferCompleteCB; + pui8Data = (uint8_t * ) pBle->sCurrentTransfer.pui32Data; + ui32Length = pBle->sCurrentTransfer.ui16Length; + pvContext = pBle->sCurrentTransfer.pvContext; + + pfnCallback(pui8Data, ui32Length, pvContext); + } + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_service() + +//***************************************************************************** +// +// Interrupt Enable +// +//***************************************************************************** +uint32_t +am_hal_ble_int_enable(void *pHandle, uint32_t ui32InterruptMask) +{ + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + AM_CRITICAL_BEGIN + BLEIFn(ui32Module)->INTEN |= ui32InterruptMask; + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_enable() + +//***************************************************************************** +// +// Interrupt Enable +// +//***************************************************************************** +uint32_t +am_hal_ble_int_disable(void *pHandle, uint32_t ui32InterruptMask) +{ + uint32_t ui32Module; + + // + // Check the handle. + // + if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + AM_CRITICAL_BEGIN + BLEIFn(ui32Module)->INTEN &= ~ui32InterruptMask; + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_disable() + +//***************************************************************************** +// +// Check the status of the interrupts. +// +//***************************************************************************** +uint32_t +am_hal_ble_int_status(void *pHandle, bool bEnabledOnly) +{ + uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; + + if (bEnabledOnly) + { + uint32_t ui32IntEn = BLEIFn(ui32Module)->INTEN; + return ( BLEIFn(ui32Module)->INTSTAT & ui32IntEn ); + } + else + { + return BLEIFn(ui32Module)->INTSTAT; + } +} // am_hal_ble_int_status() + +//***************************************************************************** +// +// Clear the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_ble_int_clear(void *pHandle, uint32_t ui32InterruptMask) +{ + uint32_t ui32Module; + + // + // Check the handle. + // + if ( !AM_HAL_BLE_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Handle is good, so get the module number. + // + ui32Module = ((am_hal_ble_state_t *)pHandle)->ui32Module; + + BLEIFn(ui32Module)->INTCLR = ui32InterruptMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_int_clear() + +//***************************************************************************** +// +// check 32768Hz clock is ready. +// +//***************************************************************************** +uint32_t +am_hal_ble_check_32k_clock(void *pHandle) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t rc32k_clock = 0xFFFFFFFF; + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_B0, &rc32k_clock); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_A1, &rc32k_clock); + } + + // Normal 32KHz clock is about 0x8000 + if ( (rc32k_clock > 0x8200) || (rc32k_clock < 0x7B00) ) + { + return AM_HAL_STATUS_FAIL; + } + else + { + return AM_HAL_STATUS_SUCCESS; + } +} // am_hal_ble_check_32k_clock() + +//***************************************************************************** +// +// Read a register value from the BLE core. +// +//***************************************************************************** +uint32_t +am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint8_t pui8Parameter[4]; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + + // + // Make a buffer big enough to hold the register write command, and a + // second one big enough to hold the response. + // + am_hal_ble_buffer(AM_HAL_BLE_PLF_REGISTER_READ_LENGTH) sWriteCommand; + am_hal_ble_buffer(32) sResponse; + + // + // Prepare our register write value. + // + pui8Parameter[0] = ui32Address; + pui8Parameter[1] = (ui32Address >> 8); + pui8Parameter[2] = (ui32Address >> 16); + pui8Parameter[3] = (ui32Address >> 24); + + sResponse.words[0] = 0; + sResponse.words[1] = 0; + sResponse.words[2] = 0; + + // + // Fill the buffer with the specific command we want to write, and send it. + // + am_hal_ble_vs_command_build(sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_READ_OPCODE, + AM_HAL_BLE_PLF_REGISTER_READ_LENGTH, + pui8Parameter); + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_READ_LENGTH); + + // + // Make sure the IO clock for the STATUS signal is on. + // + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response, and return it to the caller via our variable. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 500, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + *pui32Value = (((sResponse.words[1] & 0xFF000000) >> 24) | + ((sResponse.words[2] & 0x00FFFFFF) << 8)); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ble_plf_reg_read() + +//***************************************************************************** +// +// Write a register value to the BLE core. +// +//***************************************************************************** +uint32_t +am_hal_ble_plf_reg_write(void *pHandle, uint32_t ui32Address, uint32_t ui32Value) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint8_t pui8Parameter[8]; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + + // + // Make a buffer big enough to hold the register write command, and a + // second one big enough to hold the response. + // + am_hal_ble_buffer(AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + + // + // Prepare our register write value. + // + pui8Parameter[0] = ui32Address; + pui8Parameter[1] = (ui32Address >> 8); + pui8Parameter[2] = (ui32Address >> 16); + pui8Parameter[3] = (ui32Address >> 24); + pui8Parameter[4] = ui32Value; + pui8Parameter[5] = (ui32Value >> 8); + pui8Parameter[6] = (ui32Value >> 16); + pui8Parameter[7] = (ui32Value >> 24); + + // + // Fill the buffer with the specific command we want to write, and send it. + // + am_hal_ble_vs_command_build(sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_WRITE_OPCODE, + AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH, + pui8Parameter); + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH); + + // + // Make sure the IO clock for the STATUS signal is on. + // + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0, 50, + AM_HAL_BLE_NO_HCI_RESPONSE ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ble_plf_reg_write() + +//***************************************************************************** +// +// Set the modulation frequency offset from INFO1, +// based on the tested values stored in non-volatile memory. +// +//***************************************************************************** +uint32_t +am_hal_ble_load_modex_trim_set(void *pHandle) +{ + uint8_t ui8TrimValue; + // + // load the modex trim data from info1. + // + ui8TrimValue = am_hal_ble_read_trimdata_from_info1(); + if ( ui8TrimValue ) + { + am_hal_ble_transmitter_modex_set(pHandle, ui8TrimValue); + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } +} // am_hal_ble_load_modex_trim_set() + +//***************************************************************************** +// +// Load the modulation frequency offset from INFO1, +// based on the tested values stored in non-volatile memory. +// +//***************************************************************************** +uint8_t +am_hal_ble_read_trimdata_from_info1(void) +{ + uint32_t ui32TrimValue = 0, temp = 0; + uint8_t TrimData = 0; + + temp = ui32TrimValue = AM_REGVAL(0x50023808); + temp &= 0xffffff00; + + if ( temp == 0x18240600 ) + { + TrimData = ui32TrimValue & 0xFF; + } + else + { + TrimData = 0; + } + + if ( (TrimData > 0x40) || (TrimData < 0x20) ) + { + TrimData = 0; + } + + return TrimData; +} // am_hal_ble_read_trimdata_from_info1() + +//***************************************************************************** +// +// Manually set modulation characteristic +// based on the tested values at customer side. +// manually set frequency offset for 10101010 or 01010101 pattern +// parameter default value is 0x34, increase to get larger frequency offset +// +//***************************************************************************** +uint32_t +am_hal_ble_transmitter_modex_set(void *pHandle, uint8_t ui8ModFrqOffset) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueMCGR, RegValueBACKCR, RegValueSTCR, RegValueDACSPICR, temp = 0; + + ui8ModFrqOffset &= 0x7F; + + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); + + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + am_hal_ble_plf_reg_read(pBLE, 0x52000008, &temp); + temp |= 0x08; + am_hal_ble_plf_reg_read(pBLE, 0x52000000, &RegValueSTCR); + RegValueSTCR |= (1 << 10); + am_hal_ble_plf_reg_write(pBLE, 0x52000000, RegValueSTCR); + + am_hal_ble_plf_reg_read(pBLE, 0x45800070, &RegValueBACKCR); + am_hal_ble_plf_reg_write(pBLE, 0x45800070, (RegValueBACKCR | 0x8)); + RegValueDACSPICR = (ui8ModFrqOffset << 1) | 0x1; + am_hal_ble_plf_reg_write(pBLE, 0x52000014, RegValueDACSPICR); + + am_hal_ble_plf_reg_write(pBLE, 0x52000008, temp); + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_B0, ui8ModFrqOffset); + } + else + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_MODEX_TRIM_ADDR_A1, ui8ModFrqOffset); + } + am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_transmitter_modex_set() + +//***************************************************************************** +// +// Set BLE sleep enable/disable for the BLE core. +// enable = 'true' set sleep enable, enable = 'false' set sleep disable +// +//***************************************************************************** +uint32_t +am_hal_ble_sleep_set(void *pHandle, bool enable) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t sleepenable = 0; + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, &sleepenable); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1, &sleepenable); + } + + sleepenable &= 0xffff0100; + + if ( enable ) + { + sleepenable |= 0x0101; + } + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, sleepenable); + } + else + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1, sleepenable); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_sleep_set() + +//***************************************************************************** +// +// Get current sleep enable status +// return 'true' = sleep enable , 'false' = sleep disable +// +//***************************************************************************** +bool +am_hal_ble_sleep_get(void *pHandle) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t sleepenable = 0; + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, &sleepenable); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_A1, &sleepenable); + } + + if ( (sleepenable & 0xFFFF) > 0 ) + { + return true; + } + + return false; +} // am_hal_ble_sleep_get() + +//***************************************************************************** +// +// set the tx power of BLE +// values. +// ui32TxPower: 0x03->-20dBm 0x04->-10dBm 0x05->-5dBm 0x08->0dBm 0x0F->3dBm +// +//***************************************************************************** +uint32_t +am_hal_ble_tx_power_set(void *pHandle, uint8_t ui32TxPower) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueMCGR, tempreg = 0; + uint32_t ui32PowerValue = 0x00000008; + ui32PowerValue |= (ui32TxPower & 0xF) << 16; + + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); + + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_B0, &tempreg); + } + else + { + am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_A1, &tempreg); + } + + tempreg &= 0xffffff00; + tempreg |= ui32TxPower; + am_hal_ble_plf_reg_write(pBLE, 0x52400018, ui32PowerValue); + + if (APOLLO3_B0) + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_B0, tempreg); + } + else + { + am_hal_ble_plf_reg_write(pBLE, AM_HAL_BLE_IP_RAM_POWER_LEVEL_ADDR_A1, tempreg); + } + + am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ble_tx_power_set() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.h new file mode 100644 index 0000000000..fc6de38abf --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble.h @@ -0,0 +1,1004 @@ +//***************************************************************************** +// +//! @file am_hal_ble.h +//! +//! @brief HAL functions for the BLE interface. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_BLE_H +#define AM_HAL_BLE_H + +#include "am_hal_global.h" +#include "am_hal_status.h" + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable BLEIF module number. +// +#define BLEIFn(n) ((BLEIF_Type*)(BLEIF_BASE + (n * (BLEIF_BASE - BLEIF_BASE)))) +//***************************************************************************** + +//***************************************************************************** +// +// BLE-specific status values. +// +//***************************************************************************** +typedef enum +{ + // + // This error occurs when an HCI read or write function is called while + // another HCI communication function is already in progress. + // + AM_HAL_BLE_STATUS_BUS_BUSY = AM_HAL_STATUS_MODULE_SPECIFIC_START, + + // + // This error happens when the MCU tries to execute an HCI read, but the + // BLE core hasn't asserted the BLEIRQ line. Try waiting for a BLEIRQ + // interrupt, or polling the BLECIRQ bit in the BSTATUS register before + // calling an HCI read function. + // + AM_HAL_BLE_STATUS_IRQ_LOW, + + // + // This error means that the MCU tried to execute an HCI write, but the BLE + // core didn't assert its SPI_STATUS signal within the allotted timeout. + // This might mean that there has been some error inside the BLE core. This + // may require a reboot of the BLE core. + // + AM_HAL_BLE_STATUS_SPI_NOT_READY, + + // + // This error means we were trying to write, but the BLE core has requested + // a READ instead. We will need to perform a read before we can retry this + // write. + // + AM_HAL_BLE_REQUESTING_READ, + + // + // We are expecting an HCI response to a packet we just sent, but the BLE + // core isn't asserting BLEIRQ. Its software may have crashed, and it may + // need to restart. + // + AM_HAL_BLE_NO_HCI_RESPONSE, + + // + // Any of these errors indicate a problem with the BLE hardware that + // requires a complete restart. + // + AM_HAL_BLE_FEATURE_DISABLED, + AM_HAL_BLE_SHUTDOWN_FAILED, + AM_HAL_BLE_REGULATOR_FAILED, + AM_HAL_BLE_POWERUP_INCOMPLETE, + AM_HAL_BLE_HCI_PACKET_INCOMPLETE, + AM_HAL_BLE_FIFO_ERROR, + AM_HAL_BLE_32K_CLOCK_UNSTABLE, +} +am_ble_status_e; + +//***************************************************************************** +// +// BLE power modes. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_BLE_POWER_ACTIVE, + AM_HAL_BLE_POWER_OFF, +} +am_hal_ble_power_state_e; + +//***************************************************************************** +// +// BLE SPI Clock settings. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_BLE_HCI_CLK_DIV2 = BLEIF_CLKCFG_FSEL_HFRC_DIV2, + AM_HAL_BLE_HCI_CLK_DIV4 = BLEIF_CLKCFG_FSEL_HFRC_DIV4, + AM_HAL_BLE_HCI_CLK_DIV8 = BLEIF_CLKCFG_FSEL_HFRC_DIV8, + AM_HAL_BLE_HCI_CLK_DIV16 = BLEIF_CLKCFG_FSEL_HFRC_DIV16, + AM_HAL_BLE_HCI_CLK_DIV32 = BLEIF_CLKCFG_FSEL_HFRC_DIV32, + AM_HAL_BLE_HCI_CLK_DIV64 = BLEIF_CLKCFG_FSEL_HFRC_DIV8, +} +am_hal_ble_hci_clock_e; + +//***************************************************************************** +// +// BLE Core Clock settings. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_BLE_CORE_MCU_CLK = 0x02, + AM_HAL_BLE_CORE_INTERNAL_CLK = 0x00, +} +am_hal_ble_core_clock_e; + +//***************************************************************************** +// +// Interrupts. +// +//***************************************************************************** +// The B2M_STATE went into the shutdown state +#define AM_BLEIF_INT_B2MSHUTDN AM_REG_BLEIF_INTEN_B2MSHUTDN_M +// The B2M_STATE went into the active state +#define AM_BLEIF_INT_B2MACTIVE AM_REG_BLEIF_INTEN_B2MACTIVE_M +// The B2M_STATE went into the sleep state +#define AM_BLEIF_INT_B2MSLEEP AM_REG_BLEIF_INTEN_B2MSLEEP_M +// command queue received and error +#define AM_BLEIF_INT_CQERR AM_REG_BLEIF_INTEN_CQERR_M +// CQ write operation performed a register write with the register address bit +// 0 set to 1. The low address bits in the CQ address fields are unused and +// bit 0 can be used to trigger an interrupt to indicate when this register +// write is performed by the CQ operation. +#define AM_BLEIF_INT_CQUPD AM_REG_BLEIF_INTEN_CQUPD_M +// The command queue is waiting interrupt +#define AM_BLEIF_INT_CQPAUSED AM_REG_BLEIF_INTEN_CQPAUSED_M +// DMA Error +#define AM_BLEIF_INT_DERR AM_REG_BLEIF_INTEN_DERR_M +// DMA Complete +#define AM_BLEIF_INT_DCMP AM_REG_BLEIF_INTEN_DCMP_M +// THis is the BLE Core IRQ signal +#define AM_BLEIF_INT_BLECIRQ AM_REG_BLEIF_INTEN_BLECIRQ_M +// This is the illegal command interrupt. +#define AM_BLEIF_INT_ICMD AM_REG_BLEIF_INTEN_ICMD_M +// This is the illegal FIFO access interrupt. +#define AM_BLEIF_INT_IACC AM_REG_BLEIF_INTEN_IACC_M +// Any change in the B2M_STATE signal from the BLE Core will set this interrupt +#define AM_BLEIF_INT_B2MST AM_REG_BLEIF_INTEN_B2MST_M +// This is the Write FIFO Overflow interrupt. +#define AM_BLEIF_INT_FOVFL AM_REG_BLEIF_INTEN_FOVFL_M +// This is the Read FIFO Underflow interrupt. +#define AM_BLEIF_INT_FUNDFL AM_REG_BLEIF_INTEN_FUNDFL_M +// This is the FIFO Threshold interrupt. +#define AM_BLEIF_INT_THR AM_REG_BLEIF_INTEN_THR_M +// This is the Command Complete interrupt. +#define AM_BLEIF_INT_CMDCMP AM_REG_BLEIF_INTEN_CMDCMP_M + +#define AM_HAL_BLE_INT_B2MSHUTDN BLEIF_INTEN_B2MSHUTDN_Msk // The B2M_STATE went into the shutdown state +#define AM_HAL_BLE_INT_B2MACTIVE BLEIF_INTEN_B2MACTIVE_Msk // The B2M_STATE went into the active state +#define AM_HAL_BLE_INT_B2MSLEEP BLEIF_INTEN_B2MSLEEP_Msk // The B2M_STATE went into the sleep state +#define AM_HAL_BLE_INT_CQERR BLEIF_INTEN_CQERR_Msk // command queue received and error + +// CQ write operation performed a register write with the register address bit +// 0 set to 1. The low address bits in the CQ address fields are unused and +// bit 0 can be used to trigger an interrupt to indicate when this register +// write is performed by the CQ operation. +#define AM_HAL_BLE_INT_CQUPD BLEIF_INTEN_CQUPD_Msk + +#define AM_HAL_BLE_INT_CQPAUSED BLEIF_INTEN_CQPAUSED_Msk // The command queue is waiting interrupt +#define AM_HAL_BLE_INT_DERR BLEIF_INTEN_DERR_Msk // DMA Error +#define AM_HAL_BLE_INT_DCMP BLEIF_INTEN_DCMP_Msk // DMA Complete +#define AM_HAL_BLE_INT_BLECSSTAT BLEIF_INTEN_BLECSSTAT_Msk // This is the BLE Core SPI STATUS signal. +#define AM_HAL_BLE_INT_BLECIRQ BLEIF_INTEN_BLECIRQ_Msk // This is the BLE Core IRQ signal +#define AM_HAL_BLE_INT_ICMD BLEIF_INTEN_ICMD_Msk // This is the illegal command interrupt. +#define AM_HAL_BLE_INT_IACC BLEIF_INTEN_IACC_Msk // This is the illegal FIFO access interrupt. +#define AM_HAL_BLE_INT_B2MST BLEIF_INTEN_B2MST_Msk // Any change in the B2M_STATE signal from the BLE Core will set this interrupt +#define AM_HAL_BLE_INT_FOVFL BLEIF_INTEN_FOVFL_Msk // This is the Write FIFO Overflow interrupt. +#define AM_HAL_BLE_INT_FUNDFL BLEIF_INTEN_FUNDFL_Msk // This is the Read FIFO Underflow interrupt. +#define AM_HAL_BLE_INT_THR BLEIF_INTEN_THR_Msk // This is the FIFO Threshold interrupt. +#define AM_HAL_BLE_INT_CMDCMP BLEIF_INTEN_CMDCMP_Msk // This is the Command Complete interrupt. + +#define AM_HAL_BLE_INT_BLECSSTATN BLEIF_INTSTAT_B2MSHUTDN_Msk +#define AM_HAL_BLE_INT_BLECIRQN BLEIF_INTSTAT_B2MACTIVE_Msk + +//***************************************************************************** +// +// Type definitions. +// +//***************************************************************************** +#define am_hal_ble_buffer(A) \ + union \ + { \ + uint32_t words[(A + 3) >> 2]; \ + uint8_t bytes[A]; \ + } + +// Function pointer for non-blocking ble read callbacks. +typedef void (*am_hal_ble_transfer_complete_cb_t)(uint8_t *pui8Data, uint32_t ui32Length, void *pvContext); + +// +// Patch container +// +typedef struct +{ + uint32_t ui32Type; + uint32_t ui32Length; + uint32_t ui32CRC; + const uint32_t *pui32Data; +} +am_hal_ble_patch_t; + +// +// Configuration structure for the BLE module. +// +typedef struct +{ + // HCI interface options. + uint32_t ui32SpiClkCfg; // Configure the HCI interface clock. + uint32_t ui32ReadThreshold; // Internal HCI READ FIFO size + uint32_t ui32WriteThreshold; // Internal HCI WRITE FIFO size. + + // BLE options. + uint32_t ui32BleClockConfig; // Configure the BLE core clock. + uint32_t ui32ClockDrift; // Set the expected BLE clock drift. + uint32_t ui32SleepClockDrift; // Set the expected sleep clock accuracy. + bool bAgcEnabled; // Enable/Disable AGC + bool bSleepEnabled; // Enable/Disable Sleep Algorithm + + // Patches + bool bUseDefaultPatches; // Apply the default patches? +} +am_hal_ble_config_t; + +// +// Default options for the BLE module. +// +extern const am_hal_ble_config_t am_hal_ble_default_config; + +//***************************************************************************** +// +// Structure for sending SPI commands. +// +//***************************************************************************** +typedef struct +{ + uint32_t *pui32Data; + uint8_t pui8Offset[3]; + uint8_t ui8OffsetLen; + uint16_t ui16Length; + uint8_t ui8Command; + uint8_t ui8RepeatCount; + bool bContinue; + am_hal_ble_transfer_complete_cb_t pfnTransferCompleteCB; + void *pvContext; +} +am_hal_ble_transfer_t; + +//***************************************************************************** +// +// Vendor Specific commands. +// +// Note: Lengths are reported as "4 + ". Each vendor-specific +// header is 4 bytes long. This definition allows the macro version of the +// length to be used in all BLE APIs. +// +//***************************************************************************** +#define AM_HAL_BLE_SET_BD_ADDR_OPCODE 0xFC32 +#define AM_HAL_BLE_SET_BD_ADDR_LENGTH (4 + 6) + +#define AM_HAL_BLE_SET_TX_POWER_OPCODE 0xFC3B +#define AM_HAL_BLE_SET_TX_POWER_LENGTH (4 + 3) + +#define AM_HAL_BLE_READ_VERSIONS_OPCODE 0xFD01 +#define AM_HAL_BLE_READ_VERSIONS_LENGTH (4 + 0) + +#define AM_HAL_BLE_PLF_REGISTER_READ_OPCODE 0xFD02 +#define AM_HAL_BLE_PLF_REGISTER_READ_LENGTH (4 + 4) + +#define AM_HAL_BLE_PLF_REGISTER_WRITE_OPCODE 0xFD03 +#define AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH (4 + 8) + +#define AM_HAL_BLE_GET_RSSI_OPCODE 0x1405 +#define AM_HAL_BLE_GET_RSSI_LENGTH (4 + 0) + +#define AM_HAL_BLE_SET_SLEEP_OPCODE 0xFD09 +#define AM_HAL_BLE_SET_SLEEP_LENGTH (4 + 0) + +#define AM_HAL_BLE_SPI_SENDFRAME_OPCODE 0xFD04 +#define AM_HAL_BLE_SPI_SENDFRAME_LENGTH (4 + 1) + +#define AM_HAL_BLE_SET_BD_ADDR_CMD(...) {0x01, 0x32, 0xFC, 0x06, __VA_ARGS__} +#define AM_HAL_BLE_SET_TX_POWER_CMD(...) {0x01, 0x3B, 0xFC, 0x03, __VA_ARGS__} +#define AM_HAL_BLE_SET_READ_VERSIONS_CMD() {0x01, 0x01, 0xFD, 0x00} +#define AM_HAL_BLE_PLF_REGISTER_READ_CMD(...) {0x01, 0x02, 0xFD, 0x04, __VA_ARGS__} +#define AM_HAL_BLE_PLF_REGISTER_WRITE_CMD(...) {0x01, 0x03, 0xFD, 0x08, __VA_ARGS__} +#define AM_HAL_BLE_GET_RSSI_CMD() {0x01, 0x05, 0x14, 0x00} +#define AM_HAL_BLE_SET_SLEEP_CMD() {0x01, 0x09, 0xFD, 0x00} +#define AM_HAL_BLE_SPI_SENDFRAME_CMD(...) {0x01, 0x04, 0xFD, 0x01, __VA_ARGS__} + +//***************************************************************************** +// +// State variables for the BLE module. +// +//***************************************************************************** +typedef struct +{ + // Handle validation prefix. + am_hal_handle_prefix_t prefix; + + // Which BLE module instance is this? + uint32_t ui32Module; + + // Apply the default patches during the "boot" function? + bool bUseDefaultPatches; + + // What was the last command that we started? + am_hal_ble_transfer_t sCurrentTransfer; + + // If a write is interrupted by a read, we have to save the write + // transaction to execute later. That saved write goes here. + am_hal_ble_transfer_t sSavedTransfer; + + // How far along are we? + uint32_t ui32TransferIndex; + + // Has this radio already been patched? + bool bPatchComplete; + + // Are we in the middle of a continue packet? + bool bContinuePacket; + + // Was our last operation to send a TX packet? If we have two TX packets in + // a row, we need special handling to get the timing right. + bool bLastPacketWasTX; + + // Do we have a saved packet? + bool bSavedPacket; + + // Is the bus already in use? + bool bBusy; + + // Has the last command completed? + bool bCmdComplete; + + // Has the last DMA action completed? + bool bDmaComplete; + + // Has the BLE core's flow control signal been reset? + bool bFlowControlComplete; +} +am_hal_ble_state_t; + +//***************************************************************************** +// +// SPI command macros. +// +//***************************************************************************** +#define AM_HAL_BLE_WRITE 1 +#define AM_HAL_BLE_READ 2 + +//***************************************************************************** +// +// HCI packet types. +// +//***************************************************************************** +#define AM_HAL_BLE_RAW 0x0 +#define AM_HAL_BLE_CMD 0x1 +#define AM_HAL_BLE_ACL 0x2 +#define AM_HAL_BLE_EVT 0x4 + +//***************************************************************************** +// +// External function declarations. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Basics +// +// Initialization, enable/disable, and general configuration. +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Initialize the internal state variables for the BLE module. +//! +//! @param ui32Module - Which BLE module to use. +//! @param ppHandle - Pointer to a handle variable to be initialized. +//! +//! This function initializes the internal state variables associated with a +//! particular BLE module and yields a handle that may be used to perform +//! additional operations with that BLE module. +//! +//! This function must be called before any other BLE module operation. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief De-initialize the internal state variables for the BLE module. +//! +//! @param pHandle - Handle variable to be de-initialized. +//! +//! This function invalidates a previously initialized BLE module handle and +//! deletes the contents of the internal state variables associated with it. +//! This could be used in situations where the caller wants to prevent future +//! function calls to a particular BLE module. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_deinitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Configure a BLE module. +//! +//! @param pHandle - Handle for the BLE module. +//! @param psConfig - Pointer to a BLE configuration structure. +//! +//! This routine performs the necessary configuration steps to prepare the +//! physical BLE interface for operation. This function should be called after +//! \e am_hal_ble_enable() and before any other BLE operation. The \e psConfig +//! parameter may be used to set a specific interface clock frequency or modify +//! the FIFO read and write thresholds, but most users will get the best +//! results from the default settings stored in the global configuration +//! structure \e am_hal_ble_default_config. +//! +//! @note This function will only work if the BLE module has previously been +//! enabled. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_config(void *pHandle, const am_hal_ble_config_t *psConfig); + +//***************************************************************************** +// +//! @brief Enable the BLE module. +//! +//! @param pHandle - Handle for the BLE module. +//! @param ui32PowerState - Determines whether BLE is powered on or off. +//! +//! Performs the power-up or power-down sequence for the BLE module referred to +//! be \e pHandle. This should be called after am_hal_ble_initialize(), but +//! before am_hal_ble_config(). +//! +//! The ui32PowerState variable must be set to either AM_HAL_BLE_POWER_ACTIVE +//! or AM_HAL_BLE_POWER_OFF. +//! +//! After this function is called, the BLE core will be in its startup or +//! "patching" mode. +//! +//! @return BLE status code. +// +//***************************************************************************** +uint32_t am_hal_ble_power_control(void *pHandle, uint32_t ui32PowerState); + +//***************************************************************************** +// +//! @brief Boot the BLE module +//! +//! @param pHandle - Handle for the BLE module. +//! +//! This function performs the complete patching process for the BLE core and +//! returns with the BLE core in HCI mode. If you ask for the default patches +//! your am_hal_ble_config_t structure, then this is the last function you need +//! to call on startup. You don't need to call any of the patching functions. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_boot(void *pHandle); + +//***************************************************************************** +// +// Patching functions. +// +// The following functions allow the caller to apply "patches" to the BLE core +// during its startup phase. These are pre-made configuration files that change +// the operation parameters of the BLE radio. If you have received a patch file +// from the manufacturer, you may use the \e am_hal_ble_patch_apply() function +// during startup to apply these settings to the BLE core. Otherwise, you may +// skip this step by calling the \e am_hal_ble_patch_complete() function. +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Apply a patch to the BLE core. +//! +//! @param pHandle Handle for the BLE module. +//! @param psPatch Pointer to a structure describing the patch. +//! +//! The BLE core is an independent processor that executes code from an +//! on-board ROM. Its behavior can be altered through "patches" which are +//! binary snippets of code that may be loaded at startup to overlay or replace +//! sections of the original ROM (for instance, to modify trim settings). This +//! function allows the caller to apply one of these patches. +//! +//! Patches must be applied after the BLE module is enabled and configured, but +//! before standard HCI operation begins. This is the only time where the BLE +//! core is able to accept patch files. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_patch_apply(void *pHandle, am_hal_ble_patch_t *psPatch); + +extern uint32_t am_hal_ble_default_copy_patch_apply(void *pHandle); + +//***************************************************************************** +// +//! @brief Apply the default manufacturer patch to the BLE core. +//! +//! @param pHandle Handle for the BLE module. +//! @param psPatch Pointer to a structure describing the patch. +//! +//! The BLE core is an independent processor that executes code from an +//! on-board ROM. Its behavior can be altered through "patches" which are +//! binary snippets of code that may be loaded at startup to overlay or replace +//! sections of the original ROM (for instance, to modify trim settings). This +//! function allows the caller to apply one of these patches. +//! +//! Patches must be applied after the BLE module is enabled and configured, but +//! before standard HCI operation begins. This is the only time where the BLE +//! core is able to accept patch files. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_default_patch_apply(void *pHandle); + +//***************************************************************************** +// +//! @brief Complete the patching phase. +//! +//! @param pHandle Handle for the BLE module. +//! +//! After the BLE core is enabled and configured, it enters a "patching mode" +//! where it can accept patches from the main CPU. Once all patches have been +//! applied using the \e am_hal_ble_patch_apply() function. The application +//! must call this function to command the BLE core to switch to standard HCI +//! mode. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_patch_complete(void *pHandle); + +//***************************************************************************** +// +// Manually enable/disable transmitter +// set ui8TxCtrl as 1 to manually enale transmitter, 0 back to default +// +//***************************************************************************** +extern uint32_t am_hal_ble_transmitter_control(void *pHandle, uint8_t ui8TxCtrl); + +//***************************************************************************** +// +// Manually enable/disable transmitter to output carrier signal +// set ui8TxChannel as 0 to 0x27 for each transmit channel, 0xFF back to normal modulate mode +// +//***************************************************************************** +extern uint32_t am_hal_ble_transmitter_control_ex(void *pHandle, uint8_t ui8TxChannel); +//***************************************************************************** +// +// Manually set modulation characteristic +// based on the tested values at customer side. +// manually set frequency offset for 10101010 or 01010101 pattern +// +//***************************************************************************** +extern uint32_t am_hal_ble_transmitter_modex_set(void *pHandle, uint8_t ui8ModFrqOffset); + +//***************************************************************************** +// +//! @brief Performs a blocking read or write to the BLE core. +//! +//! @param pHandle - Handle for the BLE module. +//! @param psTransfer - Structure describing the transaction to execute. +//! +//! Send or receive data from the +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer); + +//***************************************************************************** +// +//! @brief Complete the patching phase. +//! +//! @param pHandle Handle for the BLE module. +//! +//! After the BLE core is enabled and configured, it enters a "patching mode" +//! where it can accept patches from the main CPU. Once all patches have been +//! applied using the \e am_hal_ble_patch_apply() function. The application +//! must call this function to command the BLE core to switch to standard HCI +//! mode. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_nonblocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer); + +// High-level HCI APIs +extern uint32_t am_hal_ble_vs_command_build(uint32_t *pui32Command, + uint32_t ui32OpCode, + uint32_t ui32TotalLength, + uint8_t *pui8Parameters); + +extern uint32_t am_hal_ble_blocking_hci_read(void *pHandle, + uint32_t *pui32Data, + uint32_t *pui32BytesReceived); + +extern uint32_t am_hal_ble_blocking_hci_write(void *pHandle, + uint8_t ui8Type, + uint32_t *pui32Data, + uint32_t ui32NumBytes); + +extern uint32_t am_hal_ble_nonblocking_hci_read(void *pHandle, + uint32_t *pui32Data, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext); + +extern uint32_t am_hal_ble_nonblocking_hci_write(void *pHandle, + uint8_t ui8Type, + uint32_t *pui32Data, + uint32_t ui32NumBytes, + am_hal_ble_transfer_complete_cb_t pfnCallback, + void *pvContext); + +//***************************************************************************** +// +//! @brief Set one of the trim values for the BLE core. +//! +//! @param pHandle is the BLE module handle +//! @param ui32BleCoreAddress is the target address for the trim value. +//! @param ui32TrimValue is the trim value to write to the BLE core. +//! +//! This function takes a BLE core trim value from the MCU memory and writes it +//! to a trim register in the BLE core. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_trim_set(void *pHandle, uint32_t ui32BleCoreAddress, + uint32_t ui32TrimValue, uint32_t ui32TrimMask); + +//***************************************************************************** +// +//! @brief Sets the default trim values for the BLE core. +//! +//! @param pHandle is the BLE module handle +//! +//! This function reads the default trim values for the BLE core from +//! non-volatile memory, and writes them to the BLE core registers. +//! Specifically, this function adjusts the BLE core bandgap voltage, bandgap +//! current, and memory-retention LDO voltage based on chip-specific, +//! manufacturer-determined settings. +//! +//! For best performance and power consumption, this function should be called +//! after the patching process is complete, but before normal HCI operation +//! begins. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_default_trim_set(void *pHandle); + +uint32_t am_hal_ble_default_trim_set_ramcode(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the TX power setting. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32TxPower is the desired power setting. +//! 0x03->-20dBm 0x04->-10dBm 0x05->-5dBm 0x08->0dBm 0x0F->4dBm +//! +//! This function sends a vendor-specific command to change the TX power level +//! setting for the BLE core. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_tx_power_set(void *pHandle, uint8_t ui32TxPower); + +//***************************************************************************** +// +//! @brief Generate continuously moderated signal for SRRC/CE test. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable, true for enabling continous signal, false for disable +//! +//! This function programs an internal register to control transmit mode in +//! BLE controller. +//! +//! @return BLE status code. +// +//***************************************************************************** + +extern uint32_t am_hal_ble_set_constant_transmission(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Generate continuously moderated signal for SRRC/CE test on a +//! specified rf channel. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param channel, 0 to 0x27 for a valid radio channnel while 0xff to set +//! radio transmit mode to normal. +//! +//! This function calls am_hal_ble_set_constant_transmission() and send HCI +//! test command with channel information to BLE controller. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_set_constant_transmission_ex(void *pHandle, uint8_t channel); + +//***************************************************************************** +// +//! @brief This is to workaround a bug for channel 1 in DTM mode. +//! +//! @param pHandle is the Handle for the BLE module. +//! +//! @return BLE status code. +// +// +extern uint32_t am_hal_ble_init_rf_channel(void *pHandle); + +//***************************************************************************** +// +//! @brief This function should be called with enable set to true for +//! BQB testing. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable, true for enabling BQB test mode, false for normal mode +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_BQB_test_init(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Set BLE sleep enable/disable for the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable 'true' set sleep enable, 'false' set sleep disable +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_sleep_set(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Sends a signal to wake up the BLE controller +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32Mode is determines the value of the WAKE signal. +//! +//! The BLE core needs to be awake before we send data to it. This function +//! sends a signal to the BLE core that tells it that we intend to send it +//! data. When the BLE core wakes up, it will generate a BLECSSTAT interrupt, +//! and the SPISTATUS bit in the BSTATUS register will be set. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_wakeup_set(void *pHandle, uint32_t ui32Mode); + +//***************************************************************************** +// +//! @brief Read a register value directly from the BLE Core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32Address is the address of the register. +//! @param *pui32Value is a pointer where the register value will be stored. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! read one of the internal registers within the BLE Core. The value stored in +//! this register will be written to the location specified by \e pui32Value. +//! +//! This function is mostly used during initial radio setup or for internal +//! test commands. Standard applications will not need to call this function +//! directly. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value); + +//***************************************************************************** +// +//! @brief Write a register value directly to the BLE Core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param ui32Address is the address of the register. +//! @param ui32Value is the value to write. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! write one of the internal registers within the BLE Core. +//! +//! This function is mostly used during initial radio setup or for internal +//! test commands. Standard applications will not need to call this function +//! directly. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_plf_reg_write(void *pHandle, uint32_t ui32Address, uint32_t ui32Value); + +//***************************************************************************** +// +//! @brief Change the sleep behavior of the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param enable sets the desired sleep behavior. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! change the default behavior of the BLE core between radio events. Set \e +//! enable to true to allow the BLE core to sleep between radio events, or +//! false to keep the BLE core awake at all times. The default behavior on +//! startup allows the BLE core to sleep. Most applications will not need to +//! modify this setting. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_sleep_set(void *pHandle, bool enable); + +//***************************************************************************** +// +//! @brief Check the sleep behavior of the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! check whether the BLE core is set to go to sleep between BLE transactions. +//! This function will return "true" if BLE sleep is enabled, or "false" if it +//! is disabled. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern bool am_hal_ble_sleep_get(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the TX power setting of the BLE core. +//! +//! @param pHandle is the Handle for the BLE module. +//! @param uint8_t is the desired power setting. +//! +//! This function uses a vendor-specific sequence of blocking HCI commands to +//! change the TX power setting of the radio. +//! +//! @note This function uses multiple blocking HCI commands in sequence. It +//! should not be used in any situation where blocking commands are not +//! desired. Do not use it in applications where interrupt-driven BLE +//! operations have already started. +//! +//! @return BLE status code. +// +//***************************************************************************** +extern uint32_t am_hal_ble_tx_power_set(void *pHandle, uint8_t ui32TxPower); + +//***************************************************************************** +// +// Interrupts. +// +//***************************************************************************** +extern uint32_t am_hal_ble_int_service(void *pHandle, uint32_t ui32Status); +extern uint32_t am_hal_ble_int_enable(void *pHandle, uint32_t ui32InterruptMask); +extern uint32_t am_hal_ble_int_disable(void *pHandle, uint32_t ui32InterruptMask); +extern uint32_t am_hal_ble_int_status(void *pHandle, bool bEnabledOnly); +extern uint32_t am_hal_ble_int_clear(void *pHandle, uint32_t ui32InterruptMask); +extern uint32_t am_hal_ble_check_32k_clock(void *pHandle); +//***************************************************************************** +// +// Debug trace pins. +// +//***************************************************************************** +#ifdef AM_DEBUG_BLE_TIMING + +#define BLE_DEBUG_TRACE_01 11 +#define BLE_DEBUG_TRACE_02 28 +#define BLE_DEBUG_TRACE_03 26 +#define BLE_DEBUG_TRACE_04 4 +#define BLE_DEBUG_TRACE_05 18 +#define BLE_DEBUG_TRACE_06 14 +#define BLE_DEBUG_TRACE_07 6 +#define BLE_DEBUG_TRACE_08 45 +#define BLE_DEBUG_TRACE_09 12 +#define BLE_DEBUG_TRACE_10 13 +#define BLE_DEBUG_TRACE_11 10 +#define BLE_LOCK_TRACE_PIN BLE_DEBUG_TRACE_11 + +#define am_hal_debug_gpio_set(x) am_hal_gpio_state_write(x, AM_HAL_GPIO_OUTPUT_SET) + +#define am_hal_debug_gpio_clear(x) am_hal_gpio_state_write(x, AM_HAL_GPIO_OUTPUT_CLEAR) + +#define am_hal_debug_gpio_toggle(x) am_hal_gpio_state_write(x, AM_HAL_GPIO_OUTPUT_TOGGLE) + +#define am_hal_debug_gpio_pinconfig(x) am_hal_gpio_pinconfig(x, g_AM_HAL_GPIO_OUTPUT) + +#else + +#define am_hal_debug_gpio_set(...) +#define am_hal_debug_gpio_clear(...) +#define am_hal_debug_gpio_toggle(...) +#define am_hal_debug_gpio_pinconfig(...) + +#endif // AM_DEBUG_BLE_TIMING + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BLE_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.c new file mode 100644 index 0000000000..c0ffcc0e4a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.c @@ -0,0 +1,705 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch.c +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// BLE LL local supported feature flags. +// +// Bit position | Link Layer Feature +// 0 | LE Encryption +// 1 | Connection Parameters Request Procedure +// 2 | Extended Reject Indication +// 3 | Slave-initiated Features Exchange +// 4 | LE Ping +// 5 | LE Data Packet Length Extension +// 6 | LL Privacy +// 7 | Extended Scanner Filter Policies +// +// Specified 4.6 Feature Support, Link Layer Specification, Core V4.2. +// +//***************************************************************************** +#ifndef AM_HAL_BLE_LOCAL_FEATURE +#define AM_HAL_BLE_LOCAL_FEATURE 0x21 +#endif + +//***************************************************************************** +// +// Patches included in this file. +// +//***************************************************************************** +am_hal_ble_patch_t am_ble_buffer_patch; +am_hal_ble_patch_t am_ble_performance_patch; +am_hal_ble_patch_t am_ble_performance_copy_patch; +am_hal_ble_patch_t am_ble_nvds_patch; + +//***************************************************************************** +// +// Patch application order. +// +//***************************************************************************** +am_hal_ble_patch_t *am_hal_ble_default_patch_array[] = +{ + // FTCODE patches (type 0xAA) + + // RAMCODE patches (type 0xBB) + &am_ble_performance_patch, + + // Standard patches (type 0xCC) + &am_ble_buffer_patch, + + // nvds param (type 0xDD) + &am_ble_nvds_patch, +}; + +am_hal_ble_patch_t *am_hal_ble_default_copy_patch_array[] = +{ + // FTCODE patches (type 0xAA) + + // RAMCODE patches (type 0xBB) + &am_ble_performance_copy_patch, + +}; + +#define AM_HAL_BLE_NUM_DEFAULT_PATCHES \ + (sizeof(am_hal_ble_default_patch_array) / \ + sizeof(am_hal_ble_default_patch_array[0])) + +am_hal_ble_patch_t **am_hal_ble_default_patches = am_hal_ble_default_patch_array; +am_hal_ble_patch_t **am_hal_ble_default_copy_patches = am_hal_ble_default_copy_patch_array; + +const uint32_t am_hal_ble_num_default_patches = AM_HAL_BLE_NUM_DEFAULT_PATCHES; + +//***************************************************************************** +// +// Patch Name: RAMCODE COPY PATCH v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD trans schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Fix channel map rejected issue +// Optimized AGC Table +// Date: 2019-01-30 +//***************************************************************************** + +const am_hal_ble_buffer(0x0912) am_ble_performance_copy_patch_data = +{ + .bytes = + { + 0x00,0x11,0x6e,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0xc5,0x01, + 0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0x70,0xb5,0x00,0x20,0x0c,0x49,0x49,0x88, + 0x0c,0x4a,0x8b,0x18,0x1a,0x88,0x0c,0x49,0x9b,0x1c,0x00,0x24,0x13,0x25,0x2d,0x02, + 0x0c,0x54,0x40,0x1c,0xa8,0x42,0xfb,0xdb,0x00,0x20,0x00,0x2a,0x04,0xdd,0x1c,0x5c, + 0x0c,0x54,0x40,0x1c,0x90,0x42,0xfa,0xdb,0x04,0x48,0x80,0x47,0x00,0x20,0x70,0xbd, + 0x00,0x48,0x00,0x20,0x02,0x48,0x00,0x20,0x00,0x35,0x00,0x20,0xaf,0x33,0x01,0x00, + 0xa0,0x08,0x1f,0xb5,0x00,0x24,0x00,0x98,0x1d,0x28,0x43,0xd2,0x01,0x00,0x79,0x44, + 0x09,0x79,0x49,0x18,0x8f,0x44,0x0e,0x13,0x40,0x1a,0x25,0x40,0x40,0x40,0x40,0x40, + 0x40,0x40,0x40,0x40,0x40,0x40,0x2a,0x40,0x40,0x40,0x40,0x2d,0x40,0x32,0x40,0x35, + 0x38,0x40,0x40,0x00,0x01,0x98,0xc0,0xb2,0x00,0xf0,0x07,0xfa,0x2c,0xe0,0x02,0x98, + 0xc1,0xb2,0x01,0x98,0xc0,0xb2,0x00,0xf0,0xb8,0xf8,0x25,0xe0,0x06,0x98,0x83,0xb2, + 0x03,0x98,0x82,0xb2,0x02,0x98,0xc1,0xb2,0x01,0x98,0xc0,0xb2,0x00,0xf0,0x71,0xf9, + 0x1a,0xe0,0x01,0x98,0xc0,0xb2,0x00,0xf0,0x0a,0xf9,0x15,0xe0,0x00,0xf0,0x29,0xf8, + 0x12,0xe0,0x01,0x98,0x80,0xb2,0x00,0xf0,0x62,0xf9,0x0d,0xe0,0x00,0xf0,0x3b,0xfb, + 0x0a,0xe0,0x00,0xf0,0x94,0xfb,0x07,0xe0,0x01,0x98,0xc0,0xb2,0x00,0xf0,0xc7,0xfa, + 0x04,0x46,0x01,0xe0,0x00,0x24,0xe4,0x43,0x20,0x46,0x04,0xb0,0x10,0xbd,0x03,0xb4, + 0x01,0x48,0x01,0x90,0x01,0xbd,0x39,0x27,0x00,0x00,0x03,0xb4,0x01,0x48,0x01,0x90, + 0x01,0xbd,0x95,0x28,0x00,0x00,0x03,0xb4,0x01,0x48,0x01,0x90,0x01,0xbd,0x01,0x01, + 0x00,0x00,0xf0,0xb4,0x00,0x20,0x43,0x22,0x12,0x06,0x51,0x68,0xff,0x24,0x01,0x34, + 0x21,0x43,0x51,0x60,0x51,0x68,0x23,0x03,0x19,0x43,0x51,0x60,0xa3,0x23,0xdb,0x05, + 0x19,0x68,0x49,0x08,0x49,0x00,0x19,0x60,0x2a,0x49,0x09,0x69,0xce,0xb2,0x29,0x4d, + 0x2a,0x4f,0x29,0x88,0xb9,0x42,0x01,0xd3,0x04,0x20,0x0d,0xe0,0x28,0x4f,0xb9,0x42, + 0x01,0xd3,0x03,0x20,0x08,0xe0,0x26,0x4f,0xb9,0x42,0x01,0xd3,0x02,0x20,0x03,0xe0, + 0x25,0x4f,0xb9,0x42,0x00,0xd3,0x01,0x20,0x24,0x4f,0x39,0x18,0x20,0x31,0x09,0x7e, + 0xb1,0x42,0x09,0xda,0x00,0x28,0x01,0xdd,0x40,0x1e,0x40,0xb2,0x39,0x18,0x09,0x7a, + 0x40,0x00,0xc0,0x19,0x00,0x8b,0x0b,0xe0,0x04,0x28,0x04,0xda,0x39,0x5c,0xb1,0x42, + 0x01,0xdb,0x40,0x1c,0x40,0xb2,0x39,0x18,0x09,0x7a,0x40,0x00,0xc0,0x19,0x00,0x8b, + 0x17,0x4e,0x31,0x62,0x19,0x68,0x49,0x08,0x49,0x00,0x19,0x60,0x15,0x4e,0x31,0x6b, + 0x0f,0x46,0x27,0x43,0x37,0x63,0x98,0x62,0xa1,0x43,0x31,0x63,0x28,0x80,0x51,0x68, + 0xb0,0x03,0x81,0x43,0x10,0x48,0x00,0x78,0xc0,0x07,0xc0,0x0f,0x03,0x05,0x19,0x43, + 0x51,0x60,0x51,0x68,0x00,0x02,0xa1,0x43,0x01,0x43,0x51,0x60,0xf0,0xbc,0x70,0x47, + 0x00,0x00,0x80,0x00,0x80,0x45,0x4e,0x60,0x00,0x20,0xf6,0x3f,0x00,0x00,0xf6,0x38, + 0x00,0x00,0xf6,0x2d,0x00,0x00,0xf6,0x09,0x00,0x00,0xfc,0x67,0x00,0x20,0x80,0x04, + 0xc0,0x50,0x40,0x00,0x80,0x45,0x3a,0x60,0x00,0x20,0xf0,0xb5,0x82,0xb0,0x43,0x22, + 0x12,0x06,0x53,0x68,0x01,0x24,0x64,0x04,0x23,0x43,0x53,0x60,0xca,0x07,0xd2,0x0f, + 0x96,0x46,0x8a,0x07,0xd3,0x0f,0x4a,0x07,0xd4,0x0f,0x0a,0x07,0xd2,0x0f,0x01,0x92, + 0xca,0x06,0xd2,0x0f,0x00,0x92,0x8a,0x06,0xd2,0x0f,0x94,0x46,0x4a,0x06,0xd5,0x0f, + 0xce,0x09,0x1f,0x4a,0x11,0x68,0x03,0x27,0x7f,0x05,0xb9,0x43,0x12,0x69,0x1d,0x4f, + 0x3a,0x40,0x00,0x28,0x06,0xd0,0x01,0x28,0x09,0xd0,0x01,0x27,0xbf,0x05,0x02,0x28, + 0x03,0xd0,0x39,0x43,0x00,0x28,0x06,0xd0,0x1b,0xe0,0x39,0x43,0xfa,0xe7,0x01,0x27, + 0x7f,0x05,0x39,0x43,0xf6,0xe7,0x30,0x03,0x10,0x43,0x6a,0x01,0x10,0x43,0x62,0x46, + 0xd2,0x02,0x10,0x43,0x00,0x9a,0xd2,0x01,0x10,0x43,0x01,0x9a,0x92,0x01,0x10,0x43, + 0xa2,0x02,0x10,0x43,0x5a,0x02,0x10,0x43,0x72,0x46,0x12,0x02,0x10,0x43,0x08,0x4a, + 0x10,0x61,0x07,0x48,0x01,0x60,0x43,0x20,0x00,0x06,0x41,0x68,0x01,0x22,0x52,0x04, + 0x91,0x43,0x05,0x4a,0x12,0x78,0xd2,0x07,0x92,0x0b,0x11,0x43,0x41,0x60,0x02,0xb0, + 0xf0,0xbd,0x00,0x00,0xc0,0x43,0x03,0xe0,0xff,0xff,0x3a,0x60,0x00,0x20,0xf8,0xb5, + 0x00,0x24,0x43,0x20,0x00,0x06,0x41,0x68,0x01,0x27,0xbf,0x03,0x39,0x43,0x41,0x60, + 0x41,0x68,0xba,0x00,0x11,0x43,0x41,0x60,0x21,0x48,0x05,0x68,0x51,0x1c,0x0d,0x43, + 0x05,0x60,0x1f,0x4e,0xc8,0x20,0xb0,0x47,0x1f,0x49,0x88,0x68,0x38,0x43,0x88,0x60, + 0x0e,0x46,0xf0,0x68,0x00,0x04,0xc7,0x0f,0x1a,0x49,0x01,0x20,0x88,0x47,0x20,0x46, + 0x1a,0x49,0x64,0x1c,0x88,0x42,0x01,0xd8,0x00,0x2f,0xf2,0xd0,0x18,0x48,0x05,0x40, + 0x13,0x48,0x05,0x60,0x01,0x20,0x40,0x03,0xb0,0x60,0xf1,0x68,0x15,0x48,0x01,0x40, + 0x70,0x68,0x14,0x4a,0x10,0x40,0x08,0x43,0x70,0x60,0x30,0x68,0x3f,0x21,0x89,0x02, + 0x88,0x43,0x30,0x60,0x43,0x21,0x09,0x06,0x4a,0x68,0x01,0x20,0x80,0x03,0x82,0x43, + 0x0e,0x48,0x00,0x78,0xc0,0x07,0xc0,0x0f,0x83,0x03,0x1a,0x43,0x4a,0x60,0x4a,0x68, + 0x01,0x23,0x1b,0x04,0x9a,0x43,0x00,0x04,0x02,0x43,0x4a,0x60,0xf8,0xbd,0x00,0x00, + 0x40,0x52,0xa1,0x3b,0x00,0x00,0x00,0x00,0xc0,0x51,0x10,0x27,0x00,0x00,0xfe,0xff, + 0xfe,0xff,0x3f,0x3f,0x00,0x00,0xc0,0xc0,0xff,0xff,0x3a,0x60,0x00,0x20,0x70,0x47, + 0x00,0x00,0xf0,0xb5,0x83,0xb0,0x08,0x25,0x3c,0x49,0x00,0x20,0x08,0x70,0x43,0x20, + 0x00,0x06,0x41,0x68,0xaa,0x02,0x11,0x43,0x41,0x60,0x29,0x27,0x38,0x49,0x7f,0x06, + 0xf9,0x60,0x41,0x68,0x37,0x4b,0x91,0x43,0x1b,0x78,0xdb,0x07,0x9b,0x0c,0x19,0x43, + 0x41,0x60,0x25,0x24,0xa4,0x01,0x41,0x68,0x11,0x43,0x41,0x60,0x41,0x68,0x52,0x10, + 0x11,0x43,0x41,0x60,0xf8,0x68,0x03,0x21,0x49,0x06,0x88,0x43,0x56,0x03,0x06,0x43, + 0x90,0x03,0x06,0x43,0xb8,0x68,0x01,0x20,0xff,0xf7,0x81,0xfe,0x21,0x46,0x10,0x20, + 0xff,0xf7,0x83,0xfe,0x28,0x03,0x06,0x43,0x00,0x24,0x00,0x2d,0x0c,0xd9,0xfe,0x60, + 0x25,0x49,0x64,0x20,0x88,0x47,0xf8,0x68,0x69,0x46,0x00,0x0a,0x80,0x1c,0x08,0x55, + 0x64,0x1c,0xe4,0xb2,0xac,0x42,0xf2,0xd3,0x6a,0x46,0xd0,0x79,0x91,0x79,0x40,0x18, + 0x51,0x79,0x12,0x79,0x89,0x18,0x40,0x18,0x6a,0x46,0xd1,0x78,0x41,0x18,0x90,0x78, + 0x09,0x18,0x50,0x78,0x09,0x18,0x10,0x78,0x08,0x18,0x29,0x46,0xff,0xf7,0x63,0xfe, + 0x12,0x49,0xc0,0xb2,0x08,0x70,0x39,0x68,0x01,0x22,0x92,0x02,0x11,0x43,0x39,0x60, + 0x40,0x00,0x40,0x1c,0x78,0x61,0x00,0x20,0xff,0xf7,0x49,0xfe,0x43,0x21,0x09,0x06, + 0x4a,0x68,0x01,0x20,0x00,0x03,0x82,0x43,0x0a,0x48,0x00,0x78,0xc0,0x07,0xc0,0x0f, + 0x03,0x03,0x1a,0x43,0x4a,0x60,0x4a,0x68,0x01,0x23,0x5b,0x03,0x9a,0x43,0x40,0x03, + 0x02,0x43,0x4a,0x60,0x03,0xb0,0xf0,0xbd,0x00,0x00,0x70,0x60,0x00,0x20,0xcc,0x34, + 0x63,0x02,0x3a,0x60,0x00,0x20,0xa1,0x3b,0x00,0x00,0x70,0xb4,0x43,0x21,0x09,0x06, + 0x48,0x68,0x01,0x24,0xa4,0x04,0x20,0x43,0x48,0x60,0xc4,0x20,0x87,0x22,0xd2,0x05, + 0x10,0x60,0x5c,0x48,0x50,0x61,0x48,0x68,0x5c,0x4a,0xa0,0x43,0x12,0x78,0xd2,0x07, + 0xd2,0x0f,0x93,0x04,0x18,0x43,0x48,0x60,0x8b,0x20,0x58,0x4b,0xc0,0x05,0x43,0x63, + 0x58,0x4b,0x01,0x25,0xdd,0x60,0x06,0x25,0xcd,0x60,0x05,0x25,0xc5,0x63,0x85,0x68, + 0x6d,0x08,0xf0,0x3d,0x85,0x60,0xc5,0x68,0x6d,0x08,0x5d,0x35,0xc5,0x60,0x05,0x69, + 0x6d,0x08,0x05,0x61,0x45,0x69,0x6d,0x08,0x45,0x61,0x85,0x69,0x6d,0x08,0x85,0x61, + 0xc5,0x69,0x6d,0x08,0xc5,0x61,0x05,0x6a,0x6d,0x08,0x05,0x62,0x45,0x6a,0x6d,0x08, + 0x45,0x62,0x85,0x6a,0x6d,0x08,0x85,0x62,0xc5,0x6a,0x6d,0x08,0xc5,0x62,0x01,0x25, + 0x1d,0x61,0x5d,0x62,0x9d,0x63,0x43,0x4b,0x1d,0x60,0x43,0x4d,0x5d,0x61,0x1d,0x6a, + 0x6d,0x08,0x1d,0x62,0xc3,0x6a,0x01,0x25,0x2b,0x43,0xc3,0x62,0x48,0x68,0xa3,0x10, + 0x18,0x43,0x48,0x60,0x48,0x68,0x9b,0x10,0x18,0x43,0x48,0x60,0x3d,0x48,0x3b,0x4b, + 0x43,0x61,0x83,0x68,0x3f,0x25,0xad,0x05,0x2b,0x43,0x83,0x60,0x00,0x23,0xc3,0x60, + 0x39,0x4b,0x83,0x61,0x39,0x4d,0x2b,0x68,0x1e,0x26,0xb3,0x43,0x2b,0x60,0x83,0x6a, + 0xf5,0x03,0xab,0x43,0x1b,0x19,0x83,0x62,0x48,0x68,0xa3,0x10,0x98,0x43,0x13,0x04, + 0x18,0x43,0x48,0x60,0x48,0x68,0x23,0x11,0x98,0x43,0x93,0x03,0x18,0x43,0x48,0x60, + 0x48,0x68,0x63,0x11,0x18,0x43,0x48,0x60,0x29,0x20,0x40,0x06,0x04,0x6a,0x24,0x09, + 0x24,0x01,0x08,0x34,0x04,0x62,0x48,0x68,0x98,0x43,0x53,0x03,0x18,0x43,0x48,0x60, + 0x48,0x68,0x01,0x23,0x1b,0x05,0x18,0x43,0x48,0x60,0x28,0x24,0xa3,0x20,0xc0,0x05, + 0x04,0x60,0x22,0x4d,0x2d,0x88,0x85,0x62,0x48,0x68,0x12,0x05,0x98,0x43,0x10,0x43, + 0x48,0x60,0x1f,0x48,0xe6,0x21,0x01,0x70,0x04,0x72,0x1d,0x4a,0x1e,0x48,0x10,0x83, + 0x1e,0x48,0xe0,0x23,0x03,0x76,0x1a,0x4c,0xd4,0x22,0x62,0x70,0x3c,0x22,0x62,0x72, + 0x1b,0x4a,0x62,0x83,0x41,0x76,0xc8,0x22,0xa2,0x70,0x15,0x4d,0x46,0x24,0xac,0x72, + 0x18,0x4c,0xac,0x83,0x81,0x76,0x29,0x46,0xca,0x70,0x50,0x21,0x2a,0x46,0xd1,0x72, + 0x15,0x49,0xd1,0x83,0xc3,0x76,0x5a,0x21,0x11,0x73,0x13,0x49,0x11,0x84,0x03,0x77, + 0x70,0xbc,0x70,0x47,0x00,0x00,0xff,0x7f,0x00,0x00,0x3a,0x60,0x00,0x20,0x49,0x02, + 0x00,0x00,0x40,0x00,0x80,0x45,0x80,0x00,0x80,0x45,0x1e,0x02,0x00,0x00,0x03,0x00, + 0x3c,0x00,0x00,0x00,0x40,0x52,0x08,0x00,0x0f,0x00,0x00,0x00,0xc0,0x51,0x4e,0x60, + 0x00,0x20,0xfc,0x67,0x00,0x20,0xf6,0x07,0x00,0x00,0x1c,0x68,0x00,0x20,0xf6,0x09, + 0x00,0x00,0xf6,0x2d,0x00,0x00,0xf6,0x38,0x00,0x00,0xf6,0x3f,0x00,0x00,0xf8,0xb5, + 0x2d,0x48,0x00,0x68,0x00,0x28,0x54,0xd1,0x43,0x22,0x12,0x06,0x50,0x68,0x01,0x21, + 0xc9,0x03,0x08,0x43,0x50,0x60,0x28,0x4f,0x3c,0x68,0x01,0x25,0x03,0x20,0x00,0x06, + 0x20,0x43,0x38,0x60,0x00,0x26,0x25,0x49,0x1e,0x20,0x88,0x47,0x24,0x49,0x01,0x20, + 0x88,0x47,0x78,0x68,0xc0,0x07,0xc0,0x0f,0x31,0x46,0x21,0x4a,0x76,0x1c,0x91,0x42, + 0x01,0xd8,0x00,0x28,0xf2,0xd0,0x1c,0x48,0x81,0x68,0x1e,0x48,0x01,0x60,0x00,0x20, + 0x00,0x26,0x00,0x2d,0x11,0xd0,0x1c,0x4b,0x32,0x46,0x00,0x25,0xcb,0x1a,0xaa,0x41, + 0x14,0xda,0x40,0x1c,0x05,0x46,0x18,0x4f,0x4d,0x43,0x33,0x46,0x00,0x22,0x7d,0x1b, + 0x9a,0x41,0x4d,0x1b,0x93,0x41,0xf4,0xdb,0x08,0xe0,0x14,0x4b,0x99,0x42,0x05,0xd2, + 0x40,0x1c,0x02,0x46,0x4a,0x43,0x9a,0x1a,0x8a,0x42,0xf9,0xd8,0x01,0x21,0x09,0x06, + 0x8c,0x43,0x49,0x00,0x0c,0x43,0x08,0x49,0x0c,0x60,0x43,0x22,0x12,0x06,0x51,0x68, + 0x01,0x23,0xdb,0x03,0x99,0x43,0x0a,0x4b,0x1b,0x78,0xdb,0x07,0x1b,0x0c,0x19,0x43, + 0x51,0x60,0xf8,0xbd,0x00,0x00,0x5c,0x60,0x00,0x20,0x00,0x00,0x40,0x44,0xa1,0x3b, + 0x00,0x00,0x10,0x27,0x00,0x00,0x60,0x60,0x00,0x20,0x00,0x20,0xbc,0xbe,0x00,0xd0, + 0x12,0x13,0x3a,0x60,0x00,0x20,0x70,0xb5,0x23,0x48,0x80,0x47,0x43,0x24,0x24,0x06, + 0x01,0x21,0x60,0x68,0x89,0x04,0x08,0x43,0x60,0x60,0x1f,0x48,0x80,0x47,0x1f,0x48, + 0x00,0x78,0xaa,0x28,0x06,0xd1,0xa0,0x68,0x80,0x07,0x03,0xd1,0x1d,0x49,0x88,0x47, + 0x1d,0x49,0x08,0x60,0xa1,0x20,0xc0,0x05,0x02,0x6b,0x02,0x21,0x8a,0x43,0x0a,0x43, + 0x02,0x63,0x01,0x21,0x02,0x6b,0x8a,0x43,0x0a,0x43,0x02,0x63,0x01,0x6b,0x04,0x26, + 0xb1,0x43,0x31,0x43,0x01,0x63,0x14,0x4c,0x60,0x68,0x14,0x4d,0x80,0x00,0x04,0xd5, + 0x01,0x20,0xa8,0x47,0x60,0x68,0x80,0x00,0xfa,0xd4,0x11,0x4c,0x0f,0x20,0x60,0x60, + 0x01,0x20,0xa8,0x47,0x07,0x20,0x60,0x60,0x04,0x20,0xa8,0x47,0x06,0x20,0x60,0x60, + 0x8b,0x21,0x0c,0x48,0xc9,0x05,0x08,0x60,0x0c,0x48,0x01,0x69,0x31,0x43,0x01,0x61, + 0x30,0xbf,0x70,0xbd,0x00,0x00,0x35,0x37,0x00,0x00,0x39,0x9c,0x00,0x00,0x2c,0x60, + 0x00,0x20,0xd1,0x39,0x00,0x00,0x54,0x60,0x00,0x20,0x80,0x00,0x80,0x45,0xa1,0x3b, + 0x00,0x00,0x40,0x00,0x80,0x45,0x26,0x03,0x00,0x00,0x00,0xed,0x00,0xe0,0x70,0xb5, + 0x2f,0x4d,0x0f,0x20,0x68,0x60,0x8b,0x24,0xe4,0x05,0x20,0x68,0x01,0x21,0x49,0x02, + 0x88,0x43,0x20,0x60,0x2b,0x48,0x80,0x47,0x01,0x20,0x80,0xf3,0x10,0x88,0x29,0x48, + 0x40,0x68,0x29,0x49,0x80,0x00,0x06,0xd4,0x20,0x68,0x08,0x22,0x10,0x43,0x20,0x60, + 0x01,0x20,0x88,0x47,0x01,0xe0,0x01,0x20,0x88,0x47,0x24,0x48,0x80,0x47,0x24,0x48, + 0x25,0x49,0x00,0x78,0x88,0x47,0x0d,0x20,0x68,0x60,0x23,0x48,0x80,0x47,0x43,0x20, + 0x00,0x06,0x41,0x68,0x01,0x23,0x5b,0x03,0x19,0x43,0x41,0x60,0x29,0x21,0x1f,0x4a, + 0x49,0x06,0xca,0x60,0x0a,0x6a,0x12,0x09,0x12,0x01,0x08,0x32,0x0a,0x62,0x0a,0x68, + 0xdc,0x10,0x22,0x43,0x0a,0x60,0x1a,0x4a,0x12,0x78,0x52,0x00,0x52,0x1c,0x4a,0x61, + 0x42,0x68,0x18,0x49,0x9a,0x43,0x09,0x78,0xc9,0x07,0xc9,0x0f,0x4b,0x03,0x1a,0x43, + 0x42,0x60,0x43,0x68,0xa2,0x02,0x13,0x43,0x43,0x60,0x28,0x24,0xa3,0x23,0xdb,0x05, + 0x1c,0x60,0x11,0x4c,0x24,0x88,0x9c,0x62,0x43,0x68,0x09,0x05,0x93,0x43,0x0b,0x43, + 0x43,0x60,0x00,0x20,0x80,0xf3,0x10,0x88,0x0d,0x48,0x80,0x47,0x70,0xbd,0x40,0x00, + 0x80,0x45,0x85,0x3b,0x01,0x00,0x80,0x00,0x80,0x45,0x89,0x44,0x01,0x00,0x6d,0x34, + 0x01,0x00,0x40,0x60,0x00,0x20,0xa1,0x3b,0x00,0x00,0x99,0x4d,0x01,0x00,0xcc,0x34, + 0x63,0x04,0x70,0x60,0x00,0x20,0x3a,0x60,0x00,0x20,0x4e,0x60,0x00,0x20,0xad,0x34, + 0x01,0x00 + } +}; + +am_hal_ble_patch_t am_ble_performance_copy_patch = +{ + .ui32Type = 0xBB, + .ui32Length = 0x0912, + .ui32CRC = 0x9516, + .pui32Data = am_ble_performance_copy_patch_data.words, +}; + +//***************************************************************************** +// +// Patch Name: RAMCODE PATCH v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD trans schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Fix channel map rejected issue +// Optimized AGC Table +// Date: 2019-01-30 +//***************************************************************************** + +am_hal_ble_buffer(0x0104) am_ble_performance_patch_data = +{ + .bytes = + { + 0x00,0x11,0x02,0x01,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x01,0xc5,0x01, + 0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x1b,0x00,0xa1,0x06,0x1f,0xb5,0x82,0xb0,0x08,0x98,0x00,0x90, + 0x02,0xa8,0x0f,0xc8,0x01,0x4c,0xa0,0x47,0x06,0xb0,0x10,0xbd,0x01,0x35,0x00,0x20, + 0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x08,0x48,0x80,0x47,0x00,0xbf,0x00,0xbf, + 0x02,0x2d,0x05,0xd1,0x06,0x48,0x80,0x47,0x00,0xbf,0x00,0xbf,0x05,0x48,0x80,0x47, + 0x00,0x21,0x03,0x9a,0x04,0x98,0x90,0x47,0x03,0x48,0x00,0x47,0x99,0x4a,0x01,0x00, + 0x25,0x4b,0x01,0x00,0xaf,0x4a,0x01,0x00,0x8f,0x4c,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x48,0x01,0x68,0x28,0x22,0x11,0x43,0x50,0x22,0x91,0x43,0x01,0x60,0x00,0xbf, + 0x01,0x48,0x00,0x47,0x00,0x00,0xc0,0x52,0x63,0x2a,0x00,0x00,0x00,0x00,0x00,0x00, + 0x04,0x48,0x01,0x68,0x50,0x22,0x11,0x43,0x28,0x22,0x91,0x43,0x01,0x60,0x00,0xbf, + 0x01,0x48,0x00,0x47,0x00,0x00,0xc0,0x52,0x83,0x2a,0x00,0x00,0x00,0xbf,0x00,0xbf, + 0x00,0xbf,0x00,0xbf,0x08,0x98,0x00,0x28,0x01,0xd0,0x01,0x20,0x02,0x90,0x00,0x20, + 0x60,0x85,0x01,0x48,0x00,0x47,0x00,0xbf,0xd5,0xed,0x00,0x00,0x00,0xbf,0x00,0xbf, + 0x60,0x88,0x00,0x28,0x04,0xd1,0x10,0x7d,0x08,0x28,0x01,0xd3,0x04,0x20,0x10,0x75, + 0x02,0x98,0x81,0x79,0x01,0x20,0x01,0x43,0x02,0x98,0x81,0x71,0x00,0x48,0x00,0x47, + 0xa5,0xf7,0x00,0x00 + } +}; + +am_hal_ble_patch_t am_ble_performance_patch = +{ + .ui32Type = 0xBB, + .ui32Length = 0x0104, + .ui32CRC = 0x933d, + .pui32Data = am_ble_performance_patch_data.words, +}; + +//***************************************************************************** +// +// Patch Name: Function PATCH v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD trans schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Fix channel map rejected issue +// Optimized AGC Table +// Date: 2019-01-30 +//***************************************************************************** + +const am_hal_ble_buffer(0x0d38) am_ble_buffer_patch_data = +{ + .bytes = + { + 0x00,0x22,0x38,0x0d,0xff,0xff,0x00,0x00,0x32,0x35,0x09,0x00,0x65,0x39,0x09,0x00, + 0x2b,0x45,0x09,0x00,0xa9,0x48,0x09,0x00,0xf7,0x53,0x09,0x00,0x1a,0x5c,0x09,0x00, + 0x1c,0x64,0x09,0x00,0xfd,0x6a,0x09,0x00,0x1a,0x75,0x09,0x00,0xde,0x7b,0x09,0x00, + 0x4b,0x85,0x09,0x00,0xb3,0x8b,0x09,0x00,0x1f,0x95,0x09,0x00,0x4f,0x9c,0x09,0x00, + 0xf5,0xa2,0x09,0x00,0x1e,0xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x00,0x47, + 0x41,0x48,0x00,0x20,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x05,0xb0,0xf0,0xbd,0x00,0x00, + 0x90,0x67,0x00,0x20,0x10,0x27,0x00,0x00,0x00,0x10,0x00,0x20,0x88,0x13,0x00,0x00, + 0x18,0x10,0x00,0x20,0xff,0x03,0x00,0x00,0xff,0xb5,0xff,0xb0,0x82,0xb0,0x07,0x46, + 0x0c,0x46,0x16,0x46,0x00,0x25,0x30,0x48,0x06,0x60,0x84,0x99,0x04,0xd0,0xee,0x28, + 0x02,0xd0,0x03,0x20,0x60,0x73,0x70,0xbd,0x60,0x7c,0xf1,0x28,0x06,0xd0,0xf2,0x28, + 0x04,0xd0,0xf3,0x28,0x02,0xd0,0x02,0x20,0x60,0x73,0x70,0xbd,0x00,0x20,0x60,0x73, + 0x70,0xbd,0x00,0x00,0x18,0x10,0x00,0x20,0x0a,0x10,0x00,0x20,0x00,0x48,0x00,0x47, + 0x81,0x4d,0x00,0x20,0x70,0x88,0x00,0x28,0x16,0xd1,0x14,0x20,0x01,0x21,0x0b,0x20, + 0xed,0xf7,0xc6,0xfc,0x10,0xbd,0x00,0x00,0x00,0x48,0x00,0x47,0x15,0x4e,0x00,0x20, + 0x00,0x28,0x02,0xd0,0x08,0x78,0x01,0x28,0x1a,0xd0,0x08,0x78,0x02,0x28,0x17,0xd0, + 0x00,0x28,0x0e,0xd0,0x01,0x28,0x0c,0xd0,0xf0,0xf7,0xd9,0xfe,0x00,0x28,0x08,0xd0, + 0x00,0xf0,0x16,0xf8,0x32,0x20,0xef,0xf7,0x51,0xf8,0xf0,0xf7,0x80,0xe1,0x00,0xe0, + 0x00,0xe1,0x00,0xe0,0x02,0x48,0x01,0x68,0x28,0x22,0x91,0x43,0x01,0x60,0x70,0x47, + 0x00,0x00,0xc0,0x52,0x00,0x48,0x00,0x47,0x81,0x48,0x00,0x20,0x01,0x60,0x70,0x47, + 0x00,0x00,0xc0,0x52,0x02,0x48,0x01,0x68,0x50,0x22,0x91,0x43,0x01,0x60,0x70,0x47, + 0x00,0x00,0xc0,0x52,0x00,0x48,0x00,0x47,0xa1,0x48,0x00,0x20,0xc0,0x40,0x80,0x50, + 0x10,0xb5,0x0b,0x46,0x11,0x46,0x02,0x24,0x0c,0x22,0x50,0x43,0x06,0x4a,0x80,0x18, + 0x00,0x28,0x06,0xd0,0x42,0x68,0x00,0x2a,0x03,0xd0,0x18,0x46,0x00,0xf0,0x10,0xfb, + 0x04,0x46,0x20,0x46,0x10,0xbd,0x00,0x00,0x98,0x56,0x01,0x00,0x00,0x49,0x08,0x47, + 0x99,0x4e,0x00,0x20,0xf3,0xf7,0x5c,0xfd,0x7c,0x20,0x00,0x5b,0x0b,0xf8,0x40,0x19, + 0xc1,0xb2,0x00,0x29,0x03,0xd0,0x40,0x34,0xa0,0x8f,0xf9,0xf7,0x73,0xfd,0x70,0xbd, + 0x01,0x21,0xe1,0xe7,0x00,0x49,0x08,0x47,0x81,0x50,0x00,0x20,0x80,0xf3,0x10,0x88, + 0x28,0x46,0xf3,0xf7,0x4d,0xf9,0x00,0x21,0x81,0xf3,0x10,0x88,0x00,0x28,0x0f,0xd0, + 0x81,0x88,0x0a,0x46,0x0a,0x3a,0x46,0x2a,0x0c,0xd2,0x64,0x1c,0xd2,0x0b,0xd2,0x03, + 0x0a,0x43,0xc2,0x84,0x00,0x20,0x80,0xf3,0x10,0x88,0x70,0x47,0x66,0x04,0x00,0x00, + 0x40,0x44,0x80,0x50,0x00,0x49,0x08,0x47,0xed,0x50,0x00,0x20,0x11,0x90,0x80,0x8f, + 0x0e,0x90,0x12,0x98,0x08,0x30,0x0d,0x90,0x12,0x98,0x30,0x30,0x0c,0x90,0x12,0x98, + 0x44,0x30,0x0b,0x90,0x00,0x20,0x0a,0x90,0x01,0x25,0x0c,0x98,0x07,0xf0,0xa4,0xf8, + 0x00,0x28,0x2d,0xd0,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf, + 0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x91,0xe0,0x0c,0x9a,0xff,0x20,0x22,0x23, + 0x11,0x46,0x0a,0x30,0xfd,0xf7,0x9e,0xfb,0x07,0x70,0x61,0x88,0xc1,0x81,0xa1,0x88, + 0x01,0x82,0xe1,0x88,0xc1,0x80,0x21,0x89,0x01,0x81,0xa1,0x7a,0xc0,0x01,0x23,0xe0, + 0x77,0xe0,0x02,0x98,0x08,0x1a,0x40,0x01,0x40,0x09,0x90,0x42,0x1c,0xd9,0x02,0x98, + 0x40,0x1a,0x40,0x01,0x40,0x09,0x40,0x42,0x16,0xe0,0x02,0x98,0x00,0xbf,0x00,0xbf, + 0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0x20, + 0x0a,0xe0,0x02,0x98,0x38,0x1a,0x40,0x01,0x40,0x09,0x90,0x42,0xc1,0x65,0x75,0x60, + 0x60,0x89,0xb8,0x84,0x04,0x9a,0x01,0x20,0x50,0x75,0x60,0x88,0xf8,0x85,0x04,0x9a, + 0x60,0x78,0x10,0x75,0x00,0x48,0x00,0x47,0xe1,0x48,0x00,0x20,0x00,0xbf,0x00,0x00, + 0x60,0x89,0x3a,0x8d,0x40,0x1e,0x80,0xb2,0x82,0x42,0x03,0xd1,0x08,0x20,0x01,0x43, + 0x03,0x98,0x81,0x71,0x07,0xb0,0xf0,0xbd,0x60,0x61,0x00,0x20,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + AM_HAL_BLE_LOCAL_FEATURE,//0x01, + 0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff, + 0xff,0x03,0x00,0x00,0xff,0x00,0x3c,0x1f,0x00,0x00,0x00,0x00,0x01,0x20,0x00,0x00, + 0x89,0x7d,0x00,0x00,0x02,0x20,0x00,0x00,0xfd,0x76,0x00,0x00,0x10,0x18,0x00,0x8c, + 0xc0,0x0b,0x08,0x9b,0x5b,0x1e,0x18,0x42,0x05,0xd1,0x08,0x98,0x00,0x48,0x00,0x47, + 0xc1,0x48,0x00,0x20,0x00,0xbf,0x00,0x00,0x80,0x4b,0xd2,0x18,0x50,0x84,0x01,0x20, + 0x80,0xf3,0x10,0x88,0xb8,0x68,0x00,0x28,0x16,0xd0,0x00,0x20,0x00,0x28,0x19,0xd0, + 0x38,0x6b,0x00,0x28,0x12,0xd0,0x00,0x20,0x00,0x28,0x13,0xd0,0x9f,0xfc,0x00,0x19, + 0x06,0x4b,0x59,0x68,0x09,0x18,0x8a,0x08,0x94,0x00,0x09,0x1b,0x59,0x60,0x41,0x01, + 0x08,0x1a,0x80,0x18,0x10,0xbd,0x00,0x00,0x2c,0x60,0x00,0x20,0xb8,0x67,0x00,0x20, + 0x00,0x49,0x08,0x47,0x79,0x55,0x00,0x20,0x7d,0x21,0x80,0x6a,0x09,0x02,0x88,0x42, + 0x02,0xd3,0x40,0x1a,0x01,0x22,0x00,0xe0,0x08,0x1a,0x00,0x2a,0x29,0x19,0x08,0x1a, + 0x21,0x46,0xee,0xf7,0xb1,0xfe,0x88,0xb2,0x70,0xbd,0x28,0x30,0x60,0x30,0x00,0x7e, + 0x70,0x47,0x10,0xb4,0x02,0x46,0x40,0x32,0xd3,0x8c,0x06,0x24,0x63,0x43,0x14,0x8d, + 0xe3,0x18,0x9b,0xb2,0x93,0x84,0x60,0x30,0x41,0x75,0x18,0x46,0x10,0xbc,0x70,0x47, + 0x28,0x30,0x60,0x30,0x40,0x7d,0x00,0x28,0x00,0x20,0x00,0x20,0x40,0x79,0x00,0x07, + 0x02,0xd5,0x04,0x20,0x60,0x70,0x34,0xe0,0x28,0x69,0x05,0xf0,0x51,0xfb,0x00,0x28, + 0x02,0xd0,0x02,0x20,0x60,0x70,0x2c,0xe0,0x03,0x98,0x03,0xf0,0x4d,0xfe,0x04,0x28, + 0x07,0xd1,0x68,0x46,0x01,0x79,0x02,0x20,0x88,0x43,0x05,0xd0,0x00,0x20,0x00,0x28, + 0x04,0xd0,0x00,0x20,0x60,0x70,0x1c,0xe0,0x01,0x20,0xf8,0xe7,0x58,0x67,0x00,0x20, + 0x40,0x00,0x80,0x50,0xb8,0x67,0x00,0x20,0x00,0x00,0x00,0x04,0xc8,0x67,0x00,0x20, + 0x00,0x49,0x08,0x47,0xcd,0x55,0x00,0x20,0x81,0x6a,0x7d,0x20,0x00,0x02,0x81,0x42, + 0x02,0xd3,0x08,0x1a,0x01,0x22,0x00,0xe0,0x40,0x1a,0x00,0x2a,0x04,0xd0,0x60,0x43, + 0xeb,0xf7,0xa4,0xfc,0x20,0x1a,0x03,0xe0,0x60,0x43,0xeb,0xf7,0xf8,0xb5,0x00,0x24, + 0x1c,0x48,0x00,0x78,0x00,0x28,0x2d,0xd1,0x1b,0x4e,0x70,0x68,0x1b,0x4d,0x00,0x28, + 0x09,0xda,0x1b,0x4f,0x01,0x21,0x0b,0x20,0xb8,0x47,0x01,0x21,0x0b,0x20,0xa8,0x47, + 0x70,0x68,0x00,0x28,0xf6,0xdb,0x00,0x21,0x0b,0x20,0xa8,0x47,0x15,0x4e,0x0a,0x20, + 0xb0,0x47,0x05,0x27,0x3f,0x07,0xf8,0x69,0x05,0x05,0x2d,0x0d,0x00,0x2d,0x04,0xd1, + 0x11,0x48,0xc0,0x68,0x80,0x05,0x80,0x0e,0x0c,0xd0,0x64,0x2c,0x0a,0xd2,0x14,0x20, + 0xb0,0x47,0xf8,0x69,0x00,0x05,0x00,0x0d,0xa8,0x42,0x04,0xd9,0x05,0x46,0x64,0x1c, + 0x64,0x2c,0xf4,0xd3,0xf8,0xbd,0x03,0x49,0x01,0x20,0x08,0x70,0x07,0x49,0x08,0x70, + 0xf8,0xbd,0x00,0x00,0x01,0x10,0x00,0x20,0x80,0x00,0x80,0x45,0x55,0x24,0x00,0x00, + 0x91,0x23,0x00,0x00,0xa1,0x3b,0x00,0x00,0x00,0x00,0xc0,0x52,0x00,0x10,0x00,0x20, + 0x10,0xb5,0x18,0x48,0x01,0x68,0x40,0x29,0x01,0xd2,0x40,0x21,0x01,0x60,0x80,0x7a, + 0xc0,0x07,0x01,0xd0,0x00,0x20,0x10,0xbd,0x13,0x48,0x80,0x47,0x05,0x20,0x00,0x07, + 0xc0,0x69,0x12,0x49,0x00,0x05,0x04,0xd0,0x08,0x78,0x01,0x28,0x14,0xd0,0x02,0x28, + 0x12,0xd0,0x08,0x78,0x00,0x28,0x08,0xd0,0x01,0x28,0x06,0xd0,0x02,0x28,0x04,0xd0, + 0x0b,0x48,0x80,0x47,0x0b,0x49,0x32,0x20,0x88,0x47,0x0b,0x49,0x04,0x20,0x88,0x47, + 0x0a,0x48,0x80,0x47,0x00,0x20,0x10,0xbd,0x09,0x49,0x04,0x20,0x88,0x47,0x01,0x20, + 0x10,0xbd,0x00,0x00,0xb8,0x67,0x00,0x20,0x05,0x93,0x00,0x00,0x18,0x10,0x00,0x20, + 0x25,0x4b,0x01,0x00,0xa1,0x3b,0x00,0x00,0x41,0x44,0x01,0x00,0xaf,0x4a,0x01,0x00, + 0x89,0x44,0x01,0x00,0xf0,0xb5,0x8d,0xb0,0x04,0x46,0x6c,0x49,0x04,0xa8,0x88,0x47, + 0x7c,0x20,0x00,0x5b,0x03,0x90,0x00,0x25,0x00,0x20,0x02,0x90,0x01,0x20,0x80,0xf3, + 0x10,0x88,0x60,0x6c,0x00,0x21,0x81,0xf3,0x10,0x88,0x26,0x46,0x60,0x36,0x00,0x28, + 0x6b,0xd0,0x21,0x46,0x44,0x31,0x0c,0x91,0x28,0x39,0x0b,0x91,0x64,0x31,0x0a,0x91, + 0x81,0x88,0xca,0x00,0x5e,0x49,0x51,0x18,0xc9,0x8c,0xc9,0x0b,0x00,0x29,0x5c,0xd0, + 0x01,0x21,0x81,0xf3,0x10,0x88,0x00,0x68,0x01,0x90,0x5a,0x49,0x0c,0x98,0x88,0x47, + 0x07,0x46,0xe0,0x69,0x00,0x28,0x03,0xd0,0x00,0x20,0x00,0x28,0x02,0xd0,0x08,0xe0, + 0x01,0x20,0xfa,0xe7,0x53,0x49,0x0b,0x98,0x88,0x47,0x00,0x28,0x01,0xd0,0x52,0x49, + 0x88,0x47,0x00,0x20,0x80,0xf3,0x10,0x88,0xb8,0x88,0x4d,0x49,0xc0,0x00,0x40,0x18, + 0xc2,0x8c,0xd2,0x0b,0xd2,0x03,0xc2,0x84,0xb8,0x88,0x07,0x28,0x1e,0xd2,0x30,0x7e, + 0x40,0x1e,0x30,0x76,0x01,0x20,0x80,0xf3,0x10,0x88,0x20,0x6b,0x00,0x28,0x13,0xd0, + 0x00,0x20,0x00,0x28,0x05,0xd0,0x0a,0x98,0xfb,0x21,0x80,0x79,0x08,0x40,0x0a,0x99, + 0x88,0x71,0x41,0x49,0x38,0x46,0x88,0x47,0x00,0x20,0x80,0xf3,0x10,0x88,0x3f,0x4a, + 0x39,0x7b,0x03,0x98,0x90,0x47,0x15,0xe0,0x01,0x20,0xea,0xe7,0x09,0x28,0x0f,0xd9, + 0xc0,0x00,0x40,0x18,0x00,0x8d,0x00,0x0a,0x00,0x90,0x39,0x49,0x38,0x46,0x88,0x47, + 0x00,0x28,0x07,0xd0,0x00,0x98,0x00,0x28,0x04,0xd0,0x6d,0x1c,0xed,0xb2,0x01,0xe0, + 0x6d,0x1c,0xed,0xb2,0x01,0x98,0x00,0x28,0x9a,0xd1,0x03,0x98,0x07,0x28,0x0e,0xd0, + 0x00,0x2d,0x0c,0xd0,0x01,0x20,0x80,0xf3,0x10,0x88,0x30,0x7e,0x40,0x1b,0x30,0x76, + 0x00,0x20,0x80,0xf3,0x10,0x88,0x2b,0x4a,0x29,0x46,0x03,0x98,0x90,0x47,0x01,0x20, + 0x80,0xf3,0x10,0x88,0x28,0x48,0x23,0x4f,0x09,0x90,0xb8,0x47,0x04,0x46,0x00,0x20, + 0x80,0xf3,0x10,0x88,0x20,0x00,0x36,0xd0,0x1f,0x4e,0xe0,0x88,0x03,0x99,0x88,0x42, + 0x12,0xd1,0x07,0x28,0x07,0xd0,0xa1,0x7a,0x00,0x91,0x20,0x4f,0xe3,0x7a,0x22,0x7b, + 0x21,0x89,0xb8,0x47,0x05,0xe0,0x1e,0x4b,0x21,0x79,0x20,0x89,0x2a,0x46,0x98,0x47, + 0x02,0x90,0x20,0x46,0xb0,0x47,0x03,0xe0,0x1a,0x4a,0x21,0x46,0x04,0xa8,0x90,0x47, + 0x01,0x20,0x80,0xf3,0x10,0x88,0x0f,0x49,0x09,0x98,0x88,0x47,0x04,0x46,0x20,0x00, + 0x0c,0xd1,0x04,0x98,0x00,0x28,0x03,0xd0,0x00,0x20,0x00,0x28,0x02,0xd0,0x05,0xe0, + 0x01,0x20,0xfa,0xe7,0x10,0x4a,0x04,0xa9,0x09,0x98,0x90,0x47,0x00,0x20,0x80,0xf3, + 0x10,0x88,0x00,0x2c,0xc9,0xd1,0x02,0x98,0x0d,0xb0,0xf0,0xbd,0xb5,0x38,0x00,0x00, + 0x40,0x44,0x80,0x50,0x45,0x39,0x00,0x00,0xa5,0x93,0x00,0x00,0x09,0xb8,0x00,0x00, + 0x5d,0x56,0x00,0x00,0x05,0xb7,0x00,0x00,0xb8,0x61,0x00,0x20,0x29,0xb7,0x00,0x00, + 0x35,0x22,0x01,0x00,0x67,0x39,0x00,0x00,0x0f,0x39,0x00,0x00,0xf1,0xb5,0x00,0x24, + 0x15,0x4d,0x16,0x4e,0x01,0x20,0x80,0xf3,0x10,0x88,0x00,0x98,0xa8,0x47,0x00,0x21, + 0x81,0xf3,0x10,0x88,0x00,0x28,0x17,0xd0,0x81,0x88,0x0a,0x46,0x0a,0x3a,0x46,0x2a, + 0x14,0xd2,0xc9,0x00,0x89,0x19,0x09,0x8d,0x0f,0x0a,0x01,0x21,0x81,0xf3,0x10,0x88, + 0x0b,0x49,0x88,0x47,0x00,0x28,0x03,0xd0,0x00,0x2f,0x01,0xd0,0x64,0x1c,0xe4,0xb2, + 0x00,0x20,0x80,0xf3,0x10,0x88,0xdd,0xe7,0x20,0x46,0xf8,0xbd,0xc9,0x1f,0x49,0x29, + 0xd8,0xd3,0x04,0x49,0x88,0x47,0xd5,0xe7,0x45,0x39,0x00,0x00,0x40,0x44,0x80,0x50, + 0x5d,0x56,0x00,0x00,0xa5,0x93,0x00,0x00,0xf1,0xb5,0x92,0xb0,0x12,0x98,0x40,0x30, + 0x11,0x90,0x80,0x8f,0x0e,0x90,0x12,0x98,0x08,0x30,0x0d,0x90,0x12,0x98,0x30,0x30, + 0x0c,0x90,0x12,0x98,0x44,0x30,0x0b,0x90,0x00,0x20,0x0a,0x90,0x01,0x25,0x0c,0x98, + 0x04,0x68,0x00,0x2c,0x03,0xd0,0x00,0x20,0x00,0x28,0x02,0xd0,0x93,0xe0,0x01,0x20, + 0xfa,0xe7,0x0e,0x98,0xc1,0x00,0xf9,0x48,0x08,0x18,0x10,0x90,0xc0,0x8c,0xc0,0x0b, + 0x00,0x28,0x6e,0xd0,0x0e,0x98,0xf6,0x49,0x80,0x00,0x0f,0x90,0x08,0x58,0xa0,0x30, + 0x46,0x79,0x01,0x20,0x71,0x07,0x19,0xd5,0x00,0x2c,0x17,0xd0,0xf1,0x4f,0xb0,0x06, + 0x07,0xd5,0x20,0x7b,0xb8,0x47,0x80,0x07,0x01,0xd4,0x00,0x20,0x06,0xe0,0x01,0x20, + 0x04,0xe0,0x20,0x7b,0xb8,0x47,0xc0,0x07,0x03,0xd0,0x01,0x20,0x00,0x28,0x02,0xd0, + 0x04,0xe0,0x00,0x20,0xfa,0xe7,0x24,0x68,0x00,0x2c,0xe8,0xd1,0x00,0x28,0x62,0xd0, + 0xe5,0x4b,0x00,0x22,0x21,0x46,0x0c,0x98,0x98,0x47,0xa6,0x68,0xe3,0x4a,0x09,0xa9, + 0x30,0x46,0x90,0x47,0x00,0x28,0x56,0xd1,0xa0,0x88,0xdc,0x4f,0xc0,0x00,0xc0,0x19, + 0x40,0x8d,0xdf,0x49,0x41,0x18,0x00,0x20,0x08,0xaa,0x12,0x79,0x00,0x2a,0x06,0xdd, + 0x32,0x5c,0x0a,0x54,0x40,0x1c,0x08,0xaa,0x12,0x79,0x90,0x42,0xf8,0xdb,0xd9,0x49, + 0xa0,0x68,0x88,0x47,0xd2,0x49,0x0f,0x98,0x08,0x58,0xa0,0x30,0x40,0x79,0xc0,0x07, + 0x03,0xd0,0x08,0xa9,0x08,0x79,0x00,0x1d,0x09,0x90,0x08,0xa8,0x01,0x79,0x10,0x98, + 0x02,0x8d,0x09,0x02,0xd2,0xb2,0x0a,0x43,0x02,0x85,0x03,0x21,0x10,0x98,0x02,0x8d, + 0x8a,0x43,0x0a,0x43,0x02,0x85,0x11,0x98,0x80,0x8f,0x00,0x21,0xc0,0x00,0xc0,0x19, + 0xc1,0x84,0x0b,0x98,0x00,0x68,0x00,0x28,0x04,0xd0,0x00,0x20,0x00,0x28,0x03,0xd0, + 0x10,0xe0,0x18,0xe0,0x01,0x20,0xf9,0xe7,0x0b,0x98,0xa1,0x88,0x40,0x68,0xca,0x00, + 0xc1,0x49,0x80,0x88,0x51,0x18,0xc0,0x00,0xc0,0x19,0xc2,0x8c,0xd2,0x0b,0xd2,0x03, + 0x0a,0x43,0xc2,0x84,0xbd,0x4a,0x21,0x46,0x0b,0x98,0x90,0x47,0x12,0x98,0x60,0x30, + 0x01,0x7e,0x49,0x1c,0x01,0x76,0x11,0x98,0x80,0x8f,0x07,0x28,0x08,0xd2,0x0e,0x99, + 0x8a,0x00,0xaf,0x49,0x89,0x58,0xa0,0x31,0x49,0x79,0x49,0x07,0x00,0xd5,0x00,0x25, + 0x0d,0x99,0x09,0x68,0x00,0x29,0x1f,0xd0,0x00,0x21,0x2a,0x46,0x8a,0x43,0x77,0xd0, + 0x07,0x28,0x76,0xd2,0xaf,0x49,0xae,0x48,0x88,0x47,0x09,0x90,0x00,0x20,0x08,0x90, + 0x11,0x98,0x80,0x8f,0x81,0x00,0xa2,0x48,0x40,0x58,0xa0,0x30,0x40,0x79,0xc0,0x07, + 0xc0,0x0f,0x07,0x90,0x0d,0x98,0x06,0x68,0x00,0x2e,0x09,0xd0,0x0d,0x99,0x30,0x68, + 0x08,0x60,0x00,0x28,0x02,0xd0,0x03,0xe0,0x01,0x21,0xde,0xe7,0x0d,0x99,0x48,0x60, + 0x00,0x2e,0x7d,0xd0,0x00,0x20,0x06,0x90,0x12,0x98,0x03,0x90,0x06,0xa8,0x04,0x90, + 0x07,0x9f,0x09,0x9b,0x05,0x97,0x08,0x25,0x75,0x5f,0x00,0x20,0x02,0x90,0x01,0x90, + 0x01,0x20,0x00,0x90,0x11,0x98,0x42,0x8e,0x84,0x46,0xd4,0xb2,0x01,0x20,0x29,0x46, + 0x09,0x31,0x89,0xb2,0x05,0x9f,0x00,0x2f,0x01,0xd0,0x09,0x1d,0x89,0xb2,0xc9,0x00, + 0x08,0x31,0x89,0xb2,0x67,0x46,0x3f,0x8e,0x8f,0x42,0x05,0xd2,0x50,0x3f,0x79,0x05, + 0x0c,0x0e,0xa2,0x42,0x00,0xd2,0xd4,0xb2,0xa5,0x42,0x01,0xdd,0x64,0x08,0x64,0x00, + 0x21,0x46,0x6f,0x1a,0x62,0x1c,0x97,0x42,0x05,0xdb,0x09,0x19,0x40,0x1c,0xc0,0xb2, + 0x6f,0x1a,0x97,0x42,0xf9,0xda,0x98,0x42,0x01,0xd9,0x00,0x25,0x34,0xe0,0x04,0x99, + 0x08,0x70,0x81,0x4f,0x81,0x49,0x7e,0x48,0x88,0x47,0x01,0x46,0x00,0x98,0x00,0x28, + 0x12,0xd0,0x00,0x20,0x00,0x90,0xb0,0x7a,0x80,0x07,0x80,0x0f,0x01,0x28,0x09,0xd0, + 0x02,0x20,0x88,0x72,0xf0,0x68,0xc2,0x88,0x02,0x92,0x80,0x88,0x01,0x90,0x09,0xe0, + 0x62,0xe0,0x58,0xe0,0x01,0x20,0xf4,0xe7,0x01,0x20,0x88,0x72,0x02,0x98,0x00,0x19, + 0x80,0xb2,0x02,0x90,0xa5,0x42,0x01,0xdd,0xcc,0x72,0x00,0xe0,0xcd,0x72,0x01,0x98, + 0xc8,0x80,0x02,0x98,0x08,0x81,0x28,0x1b,0x05,0xb2,0x00,0x2d,0x22,0xdc,0x01,0x22, + 0x05,0x9b,0x03,0x98,0xb8,0x47,0x01,0x25,0x00,0x2d,0x20,0xd0,0x68,0x46,0x00,0x7e, + 0x08,0x99,0x09,0x18,0xc9,0xb2,0x08,0x91,0x09,0x99,0x08,0x1a,0x80,0xb2,0x00,0xe0, + 0x35,0xe0,0x09,0x90,0x12,0x98,0xc0,0x69,0x00,0x28,0x1a,0xd0,0x12,0x98,0x00,0x6a, + 0x06,0x60,0x12,0x98,0x06,0x62,0x00,0x20,0x30,0x60,0x08,0x98,0x0a,0x28,0x13,0xd9, + 0x00,0x25,0x24,0xe0,0x00,0x22,0x05,0x9b,0x03,0x98,0xb8,0x47,0xaa,0xe7,0x0d,0x98, + 0x00,0x68,0x00,0x28,0x01,0xd1,0x0d,0x99,0x4e,0x60,0x30,0x60,0x0d,0x98,0x06,0x60, + 0x15,0xe0,0x12,0x98,0xc6,0x61,0xe4,0xe7,0x0d,0x98,0x06,0x68,0x00,0x2e,0x06,0xd0, + 0x0d,0x99,0x30,0x68,0x08,0x60,0x00,0x28,0x01,0xd1,0x0d,0x99,0x48,0x60,0x00,0x2e, + 0x00,0xd0,0x4f,0xe7,0x03,0xe0,0x4a,0x4a,0x0d,0x99,0x0b,0x98,0x90,0x47,0x00,0x2d, + 0x02,0xd0,0x48,0x49,0x0d,0x98,0x88,0x47,0x0b,0x98,0x00,0x68,0x00,0x28,0x03,0xd0, + 0x00,0x20,0x00,0x28,0x02,0xd0,0x4b,0xe0,0x01,0x20,0xfa,0xe7,0x11,0x98,0x80,0x8f, + 0x07,0x28,0x45,0xd2,0x12,0x98,0x80,0x30,0xc0,0x78,0x04,0x28,0x40,0xd1,0x3b,0x49, + 0x37,0x48,0x88,0x47,0x00,0x28,0x3b,0xd0,0x82,0x88,0x00,0x21,0x2b,0x4b,0xd2,0x00, + 0xd2,0x18,0x51,0x85,0x81,0x88,0xc9,0x00,0xc9,0x18,0x8a,0x8d,0x54,0x04,0x64,0x0c, + 0x00,0x22,0x8c,0x85,0x81,0x88,0xc9,0x00,0xc9,0x18,0x0c,0x8d,0xe4,0xb2,0x0c,0x85, + 0x81,0x88,0x01,0x24,0xc9,0x00,0xc9,0x18,0x0d,0x8d,0xad,0x08,0xad,0x00,0x25,0x43, + 0x0d,0x85,0x81,0x88,0xc9,0x00,0xc9,0x18,0xcc,0x8c,0xe4,0x0b,0xe4,0x03,0xcc,0x84, + 0x0b,0x99,0x84,0x88,0x49,0x68,0xe5,0x00,0x1f,0x4c,0x89,0x88,0x2c,0x19,0xc9,0x00, + 0xc9,0x18,0xcb,0x8c,0xdb,0x0b,0xdb,0x03,0x23,0x43,0xcb,0x84,0x0b,0x99,0x09,0x68, + 0x00,0x29,0x0d,0xd0,0x0b,0x99,0x49,0x68,0x08,0x60,0x0b,0x99,0x48,0x60,0x02,0x60, + 0x0b,0x98,0x00,0x68,0x00,0x28,0x06,0xd0,0x00,0x21,0x00,0x29,0x05,0xd0,0x3c,0xe0, + 0x0b,0x99,0x08,0x60,0xf1,0xe7,0x01,0x21,0xf7,0xe7,0x00,0x28,0x0a,0xd0,0x07,0x4a, + 0x81,0x88,0xc9,0x00,0x89,0x18,0xc9,0x8c,0xc9,0x0b,0x00,0x29,0x24,0xd0,0x00,0x68, + 0x00,0x28,0xf5,0xd1,0x00,0x28,0x26,0xd0,0x27,0xe0,0x00,0x00,0x40,0x44,0x80,0x50, + 0x60,0x61,0x00,0x20,0x81,0xaf,0x00,0x00,0x17,0x38,0x00,0x00,0x41,0x03,0x01,0x00, + 0x00,0x40,0x80,0x50,0xa5,0x93,0x00,0x00,0x66,0x04,0x00,0x00,0x67,0x39,0x00,0x00, + 0xe4,0x61,0x00,0x20,0xbb,0x39,0x00,0x00,0x11,0x00,0x01,0x00,0x45,0x39,0x00,0x00, + 0x0f,0x39,0x00,0x00,0xb5,0x38,0x00,0x00,0x81,0x88,0xca,0x00,0x07,0x49,0x51,0x18, + 0x89,0xb2,0x0a,0x91,0xd6,0xe7,0x00,0x20,0x0a,0x90,0x0a,0x99,0x0e,0x98,0x5a,0x22, + 0x50,0x43,0x03,0x4a,0x80,0x18,0x81,0x84,0x13,0xb0,0xf0,0xbd,0x66,0x04,0x00,0x00, + 0x80,0x40,0x80,0x50,0x10,0xb4,0x00,0x23,0x14,0x21,0x02,0x46,0x4a,0x43,0x11,0x49, + 0x7d,0x24,0x09,0x68,0x24,0x02,0xa1,0x42,0x02,0xd9,0x09,0x1b,0x01,0x23,0x00,0xe0, + 0x61,0x1a,0x48,0x43,0x81,0x00,0x41,0x18,0x88,0x0a,0x0c,0x0c,0x00,0x19,0x4c,0x0c, + 0x00,0x19,0x4c,0x0d,0x00,0x19,0x4c,0x0e,0x00,0x19,0xc9,0x0f,0x40,0x18,0xc0,0x08, + 0x00,0x2b,0x01,0xd0,0x10,0x18,0x01,0xe0,0x10,0x1a,0x40,0x1e,0x40,0x1e,0x10,0xbc, + 0x70,0x47,0x00,0x00,0x54,0x60,0x00,0x20,0xf0,0xb4,0x00,0x23,0x18,0x4c,0xe5,0x6b, + 0x18,0x49,0x7d,0x22,0x09,0x68,0x12,0x02,0x91,0x42,0x02,0xd3,0x8a,0x1a,0x01,0x23, + 0x00,0xe0,0x52,0x1a,0x06,0x46,0x56,0x43,0xf2,0x13,0x51,0x43,0x71,0x1a,0x1e,0x26, + 0x4e,0x43,0x4f,0x10,0xf6,0x19,0x8f,0x11,0xf6,0x19,0x49,0x12,0x71,0x18,0xce,0x13, + 0x00,0x2b,0x01,0xd0,0x80,0x1a,0x00,0xe0,0x10,0x18,0x42,0x19,0x91,0x08,0x8d,0x00, + 0x52,0x1b,0x00,0x2b,0x04,0xd0,0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x1b,0x03,0xe0, + 0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x19,0xe2,0x63,0xf0,0xbc,0x70,0x47,0x00,0x00, + 0x80,0x67,0x00,0x20,0x54,0x60,0x00,0x20 + } +}; + +am_hal_ble_patch_t am_ble_buffer_patch = +{ + .ui32Type = 0xCC, + .ui32Length = 0x0d38, + .ui32CRC = 0xf515, + .pui32Data = am_ble_buffer_patch_data.words, +}; + +//***************************************************************************** +// +// Patch Name: NVDS v1.10 for Apollo3 A1 +// +// Bi-directional data fix +// Modulation deviation fix +// Extend patch memory +// Transmit speed patch +// Added AGC table and enabled AGC +// Added local feature support setting +// Fix to connection interval calculation issue with MTK chip sets (OPPO R15 fix) +// Set VCO to 250mv +// Modex auto calibration update +// Fix connection interval calculation issue +// Increase RF LDO ref voltage form 1.0v to 1.1v +// Decrease DAC channel delay cycle +// Increase the VCO swing from 250mv to 300mv +// Fix MD schedule issue (disabled) +// Fix link loss issue +// Reduce duration from TX to TX +// Optimized power consumption (32K clock drift,sleep clock accuracy,,advertising interval (undirect)) +// Date: 2019-01-30 +// +//***************************************************************************** +am_hal_ble_buffer(0x00be) am_ble_buffer_nvds_data = +{ + .bytes = + { + 0x4e,0x56,0x44,0x53, //NVDS_MAGIC_NUMBER + 0x01,0x06,0x06,0xef,0xab,0x23,0x88,0x77,0x56, //bluetooth address + 0x02,0x06,0x0a,0x4e,0x5a,0x38,0x38,0x30,0x31,0x56,0x31,0x41,0x00, //device name + 0x03,0x06,0x01,0x00, //system clock frequency, 00=32MHz 01=24MHz others=16MHz + 0x07,0x06,0x02,0x00,0x00, //32K clock drift, 0x01f4 = 500 ppm + 0x0c,0x06,0x02,50,0x00, //sleep clock accuracy, 0x01f4 = 500 ppm + 0x08,0x06,0x01,0x00, //01 for BQB qualification, 00 for normal usage + 0x09,0x06,0x01,0x02, //clock source selection, 00 = internal RC32KHz, 02= use Apollo3 MCU 32.768KHz + 0x0a,0x06,0x04,0x00,0x00,0x00,0x00, //eb 0x00000000 = auto detect and low frequency clock calibration + 0x0b,0x06,0x01,0x96, //rx_ifs 0x96 = 150us + 0x23,0x06,0x01,0x95, //tx_ifs 0x95 = 149us + 0x0d,0x06,0x02,0xe8,0x03, //duration allowed for XO32M stabilization from external wakeup signal + 0x0e,0x06,0x02,0xe8,0x03, //duration allowed for XO32M stabilization from internal wakeup signal + 0x0f,0x06,0x02,0x2c,0x01, //duration allowed for radio to leave low power mode + 0x10,0x06,0x04,0x00,0xc2,0x01,0x00, //set UART_BAUDRATE + 0x11,0x06,0x01,0x01, //sleep algorithm enabled + 0x12,0x06,0x01,0x01, //external wake-up support + 0x13,0x06,0x02,0xf4,0x01, //duration of sleep and wake-up algorithm + 0x14,0x06,0x02,0x60,0x00, //BLE Company ID + 0x15,0x06,0x01,0x08, //BLE major version + 0x16,0x06,0x01,0x03, //BLE minor version + 0x17,0x06,0x01,0x29, //BLE SW version build + 0x18,0x06,0x02,0xdc,0x05, //advertising interval (undirect) + 0x19,0x06,0x02,0xe2,0x04, //advertising interval (direct) + 0x20,0x06,0x01,0x01, //agc switch + 0x21,0x06,0x01,0x02, //EA programming latency + 0x22,0x06,0x01,0x00, //EA asap latency + 0x24,0x06,0x04,0x42,0x02,0x60,0x09, //radio TRX timing + 0x25,0x06,0x01,0x11, //modem polarity setting + 0x26,0x06,0x01,0x00, //modem sync setting + 0x27,0x06,0x01,0x02, //BLE reset delay + 0x2d,0x06,0x01,0x00, //2 byte mode switch, 01 to enable + 0x28,0x06,0x02,0xf6,0x3f, //initial agc gain setting + 0x29,0x06,0x01,0x0f, //initial Tx output power, 0x0f is +4dBm + 0x35,0x06,0x01,0x08, //maximum Tx ouput power setting + 0x37,0x06,0x01,0x00, //RC32K calibration control, 0xAA to enable + 0x05,0x06,0x02,0x34,0x00, //no use + 0x04,0x06,0x01,0x20, //internal dvdd voltage level control if using 0.9V from MCU side + 0x00,0x00,0x00,0x00 //dummy + } +}; + +am_hal_ble_patch_t am_ble_nvds_patch = +{ + .ui32Type = 0xDD, + .ui32Length = 0x00be, + .ui32CRC = 0x7e77, + .pui32Data = am_ble_buffer_nvds_data.words, +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.h new file mode 100644 index 0000000000..f961626291 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch.h @@ -0,0 +1,106 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch.h +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_BLE_PATCH_H +#define AM_HAL_BLE_PATCH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Patch array pointer. +// +//***************************************************************************** +extern am_hal_ble_patch_t **am_hal_ble_default_patches; +extern am_hal_ble_patch_t **am_hal_ble_default_copy_patches; +extern const uint32_t am_hal_ble_num_default_patches; + +//***************************************************************************** +// +// Pointers for specific patches. +// +//***************************************************************************** +extern am_hal_ble_patch_t am_ble_performance_patch; +extern am_hal_ble_patch_t am_ble_nvds_patch; + +//***************************************************************************** +// +// Default patch structure. +// +//***************************************************************************** +extern am_hal_ble_patch_t g_AMBLEDefaultPatch; + +//***************************************************************************** +// +// Macros for accessing specific NVDS parameters. +// +//***************************************************************************** +#define AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET 30 +#define AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET 35 +#define AM_HAL_BLE_NVDS_CLOCKSOURCE_OFFSET 44 +#define AM_HAL_BLE_NVDS_SLEEPENABLE_OFFSET 85 +#define AM_HAL_BLE_NVDS_AGC_OFFSET 125 + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BLE_PATCH_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c new file mode 100644 index 0000000000..800bf7bb45 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.c @@ -0,0 +1,390 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch_b0.c +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// BLE LL local supported feature flags. +// +// Bit position | Link Layer Feature +// 0 | LE Encryption +// 1 | Connection Parameters Request Procedure +// 2 | Extended Reject Indication +// 3 | Slave-initiated Features Exchange +// 4 | LE Ping +// 5 | LE Data Packet Length Extension +// 6 | LL Privacy +// 7 | Extended Scanner Filter Policies +// +// Specified 4.6 Feature Support, Link Layer Specification, Core V4.2. +// +//***************************************************************************** +#ifndef AM_HAL_BLE_LOCAL_FEATURE +#define AM_HAL_BLE_LOCAL_FEATURE 0x21 +#endif + + + +//***************************************************************************** +// +// Patches included in this file. +// +//***************************************************************************** +am_hal_ble_patch_t am_ble_buffer_patch_b0; +am_hal_ble_patch_t am_ble_performance_patch_b0; +am_hal_ble_patch_t am_ble_nvds_patch_b0; + +//***************************************************************************** +// +// Patch application order. +// +//***************************************************************************** +am_hal_ble_patch_t *am_hal_ble_default_patch_array_b0[] = +{ + // FTCODE patches (type 0xAA) + + // RAMCODE patches (type 0xBB) + &am_ble_performance_patch_b0, + + // Standard patches (type 0xCC) + &am_ble_buffer_patch_b0, + + // nvds param (type 0xDD) + &am_ble_nvds_patch_b0, +}; + +#define AM_HAL_BLE_NUM_DEFAULT_PATCHES_B0 \ + (sizeof(am_hal_ble_default_patch_array_b0) / \ + sizeof(am_hal_ble_default_patch_array_b0[0])) + +am_hal_ble_patch_t **am_hal_ble_default_patches_b0 = am_hal_ble_default_patch_array_b0; +const uint32_t am_hal_ble_num_default_patches_b0 = AM_HAL_BLE_NUM_DEFAULT_PATCHES_B0; + +//***************************************************************************** +// +// Patch Name: RAMCODE PATCH v0.4 for Apollo3 B0 + +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Optimized AGC Table +// Fixed Channelmap indication rejected issue +// Fixed 800M Spur +// Fixed feature issue +// Fixed disconnect issue //long time large data transfer +// Date: 2019-10-25 +//***************************************************************************** + + am_hal_ble_buffer(0x0654)am_ble_performance_patch_data_b0 = +{ + .bytes = + { + 0x00,0x11,0x50,0x06,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x01,0xc5,0x01, + 0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x81,0x06,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x1f,0xb5,0x00,0x24,0x00,0x98,0x22,0x28,0x2d,0xd2,0x01,0x00, + 0x79,0x44,0x09,0x79,0x49,0x18,0x8f,0x44,0x10,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, + 0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x15,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x18, + 0x2a,0x1b,0x1e,0x2a,0x2a,0x28,0x28,0x28,0x28,0x24,0x01,0x98,0xc0,0xb2,0x00,0xf0, + 0x95,0xf8,0x14,0xe0,0x00,0xf0,0x16,0xf8,0x11,0xe0,0x00,0xf0,0xd1,0xf9,0x0e,0xe0, + 0x00,0xf0,0x2c,0xfa,0x0b,0xe0,0x01,0x98,0xc0,0xb2,0x00,0xf0,0x5d,0xf9,0x04,0x46, + 0x05,0xe0,0x00,0xf0,0xa3,0xfa,0x04,0x46,0x01,0xe0,0x00,0x24,0xe4,0x43,0x20,0x46, + 0x04,0xb0,0x10,0xbd,0xf0,0xb4,0x00,0x20,0x43,0x22,0x12,0x06,0x51,0x68,0xff,0x24, + 0x01,0x34,0x21,0x43,0x51,0x60,0x51,0x68,0x23,0x03,0x19,0x43,0x51,0x60,0xa3,0x23, + 0xdb,0x05,0x19,0x68,0x49,0x08,0x49,0x00,0x19,0x60,0x2a,0x49,0x09,0x69,0xce,0xb2, + 0x29,0x4d,0x2a,0x4f,0x29,0x88,0xb9,0x42,0x01,0xd3,0x04,0x20,0x0d,0xe0,0x28,0x4f, + 0xb9,0x42,0x01,0xd3,0x03,0x20,0x08,0xe0,0x26,0x4f,0xb9,0x42,0x01,0xd3,0x02,0x20, + 0x03,0xe0,0x25,0x4f,0xb9,0x42,0x00,0xd3,0x01,0x20,0x24,0x4f,0x39,0x18,0x20,0x31, + 0x09,0x7e,0xb1,0x42,0x09,0xda,0x00,0x28,0x01,0xdd,0x40,0x1e,0x40,0xb2,0x39,0x18, + 0x09,0x7a,0x40,0x00,0xc0,0x19,0x00,0x8b,0x0b,0xe0,0x04,0x28,0x04,0xda,0x39,0x5c, + 0xb1,0x42,0x01,0xdb,0x40,0x1c,0x40,0xb2,0x39,0x18,0x09,0x7a,0x40,0x00,0xc0,0x19, + 0x00,0x8b,0x17,0x4e,0x31,0x62,0x19,0x68,0x49,0x08,0x49,0x00,0x19,0x60,0x15,0x4e, + 0x31,0x6b,0x0f,0x46,0x27,0x43,0x37,0x63,0x98,0x62,0xa1,0x43,0x31,0x63,0x28,0x80, + 0x51,0x68,0xb0,0x03,0x81,0x43,0x10,0x48,0x00,0x78,0xc0,0x07,0xc0,0x0f,0x03,0x05, + 0x19,0x43,0x51,0x60,0x51,0x68,0x00,0x02,0xa1,0x43,0x01,0x43,0x51,0x60,0xf0,0xbc, + 0x70,0x47,0x00,0x00,0x80,0x00,0x80,0x45,0x50,0x68,0x00,0x20,0xf6,0x3f,0x00,0x00, + 0xf6,0x38,0x00,0x00,0xf6,0x2d,0x00,0x00,0xf6,0x09,0x00,0x00,0x50,0x6e,0x00,0x20, + 0x80,0x04,0xc0,0x50,0x40,0x00,0x80,0x45,0x3a,0x68,0x00,0x20,0xf0,0xb4,0x43,0x20, + 0x00,0x06,0x41,0x68,0x01,0x22,0x92,0x04,0x11,0x43,0x41,0x60,0xc4,0x21,0x87,0x22, + 0xd2,0x05,0x11,0x60,0x50,0x49,0x51,0x61,0x42,0x68,0x01,0x21,0x89,0x04,0x8a,0x43, + 0x4e,0x49,0x09,0x78,0xc9,0x07,0xc9,0x0f,0x8b,0x04,0x1a,0x43,0x42,0x60,0x8b,0x23, + 0x4b,0x4a,0xdb,0x05,0x5a,0x63,0x4b,0x4b,0x02,0x22,0xda,0x60,0x05,0x22,0xc2,0x60, + 0x8b,0x23,0xdb,0x05,0xda,0x63,0x47,0x4b,0x01,0x22,0x1a,0x61,0x5a,0x62,0x9a,0x63, + 0x45,0x4b,0x1a,0x60,0x45,0x4c,0x5c,0x61,0x8b,0x23,0xdb,0x05,0xdb,0x6a,0x13,0x43, + 0x8b,0x22,0xd2,0x05,0xd3,0x62,0x42,0x68,0x01,0x25,0x2d,0x04,0x2a,0x43,0x42,0x60, + 0x42,0x68,0xac,0x10,0x22,0x43,0x42,0x60,0x3e,0x4a,0x3d,0x4b,0x53,0x61,0x93,0x68, + 0x3f,0x26,0xb6,0x05,0x33,0x43,0x93,0x60,0x00,0x23,0xd3,0x60,0x3a,0x4b,0x93,0x61, + 0x3a,0x4e,0x33,0x68,0x1e,0x27,0xbb,0x43,0x33,0x60,0x93,0x6a,0xfe,0x03,0xb3,0x43, + 0x26,0x01,0x9b,0x19,0x93,0x62,0x36,0x4b,0xf0,0x22,0x5a,0x60,0x42,0x68,0x0b,0x04, + 0xaa,0x43,0x1a,0x43,0x42,0x60,0x42,0x68,0x8b,0x03,0xa2,0x43,0x1a,0x43,0x42,0x60, + 0x42,0x68,0x64,0x10,0x22,0x43,0x42,0x60,0x29,0x22,0x52,0x06,0x13,0x6a,0x1b,0x09, + 0x1b,0x01,0x08,0x33,0x13,0x62,0x2b,0x4b,0xd3,0x60,0x42,0x68,0x4b,0x03,0xa2,0x43, + 0x1a,0x43,0x42,0x60,0x43,0x68,0xe2,0x01,0x13,0x43,0x43,0x60,0x28,0x24,0xa3,0x23, + 0xdb,0x05,0x1c,0x60,0x24,0x4d,0x2d,0x88,0x9d,0x62,0x43,0x68,0x09,0x05,0x93,0x43, + 0x0b,0x43,0x43,0x60,0x21,0x48,0xe6,0x21,0x01,0x70,0x04,0x72,0x1f,0x4a,0x20,0x48, + 0x10,0x83,0x20,0x48,0xe0,0x23,0x03,0x76,0x1c,0x4c,0xd4,0x22,0x62,0x70,0x3c,0x22, + 0x62,0x72,0x1d,0x4a,0x62,0x83,0x41,0x76,0xc8,0x22,0xa2,0x70,0x17,0x4d,0x46,0x24, + 0xac,0x72,0x1a,0x4c,0xac,0x83,0x81,0x76,0x29,0x46,0xca,0x70,0x50,0x21,0x2a,0x46, + 0xd1,0x72,0x17,0x49,0xd1,0x83,0xc3,0x76,0x5a,0x21,0x11,0x73,0x15,0x49,0x11,0x84, + 0x03,0x77,0xf0,0xbc,0x70,0x47,0x00,0x00,0xff,0x7f,0x00,0x00,0x3a,0x68,0x00,0x20, + 0x49,0x02,0x00,0x00,0x40,0x00,0x80,0x45,0x80,0x00,0x80,0x45,0x1e,0x02,0x00,0x00, + 0x03,0x00,0x3c,0x00,0x00,0x00,0x40,0x52,0x08,0x00,0x0f,0x00,0x00,0x00,0xc0,0x51, + 0x40,0x00,0x40,0x52,0xcc,0x34,0x63,0x02,0x50,0x68,0x00,0x20,0x50,0x6e,0x00,0x20, + 0xf6,0x07,0x00,0x00,0x70,0x6e,0x00,0x20,0xf6,0x09,0x00,0x00,0xf6,0x2d,0x00,0x00, + 0xf6,0x38,0x00,0x00,0xf6,0x3f,0x00,0x00,0xf8,0xb5,0x2d,0x48,0x00,0x68,0x00,0x28, + 0x54,0xd1,0x43,0x22,0x12,0x06,0x50,0x68,0x01,0x21,0xc9,0x03,0x08,0x43,0x50,0x60, + 0x28,0x4f,0x3c,0x68,0x01,0x25,0x03,0x20,0x00,0x06,0x20,0x43,0x38,0x60,0x00,0x26, + 0x25,0x49,0x1e,0x20,0x88,0x47,0x24,0x49,0x01,0x20,0x88,0x47,0x78,0x68,0xc0,0x07, + 0xc0,0x0f,0x31,0x46,0x21,0x4a,0x76,0x1c,0x91,0x42,0x01,0xd8,0x00,0x28,0xf2,0xd0, + 0x1c,0x48,0x81,0x68,0x1e,0x48,0x01,0x60,0x00,0x20,0x00,0x26,0x00,0x2d,0x11,0xd0, + 0x1c,0x4b,0x32,0x46,0x00,0x25,0xcb,0x1a,0xaa,0x41,0x14,0xda,0x40,0x1c,0x05,0x46, + 0x18,0x4f,0x4d,0x43,0x33,0x46,0x00,0x22,0x7d,0x1b,0x9a,0x41,0x4d,0x1b,0x93,0x41, + 0xf4,0xdb,0x08,0xe0,0x14,0x4b,0x99,0x42,0x05,0xd2,0x40,0x1c,0x02,0x46,0x4a,0x43, + 0x9a,0x1a,0x8a,0x42,0xf9,0xd8,0x01,0x21,0x09,0x06,0x8c,0x43,0x49,0x00,0x0c,0x43, + 0x08,0x49,0x0c,0x60,0x43,0x22,0x12,0x06,0x51,0x68,0x01,0x23,0xdb,0x03,0x99,0x43, + 0x0a,0x4b,0x1b,0x78,0xdb,0x07,0x1b,0x0c,0x19,0x43,0x51,0x60,0xf8,0xbd,0x00,0x00, + 0x60,0x68,0x00,0x20,0x00,0x00,0x40,0x44,0xe5,0x3e,0x00,0x00,0x10,0x27,0x00,0x00, + 0x64,0x68,0x00,0x20,0x00,0x20,0xbc,0xbe,0x00,0xd0,0x12,0x13,0x3a,0x68,0x00,0x20, + 0xf8,0xb5,0x24,0x48,0x80,0x47,0x43,0x24,0x24,0x06,0x01,0x21,0x60,0x68,0x89,0x04, + 0x08,0x43,0x60,0x60,0x20,0x48,0x80,0x47,0x20,0x48,0x00,0x78,0xaa,0x28,0x06,0xd1, + 0xa0,0x68,0x80,0x07,0x03,0xd1,0x1e,0x49,0x88,0x47,0x1e,0x49,0x08,0x60,0x06,0x27, + 0xe7,0x60,0x1d,0x4c,0x01,0x20,0xa0,0x47,0xa1,0x20,0xc0,0x05,0x02,0x6b,0x02,0x21, + 0x8a,0x43,0x0a,0x43,0x02,0x63,0x01,0x21,0x02,0x6b,0x8a,0x43,0x0a,0x43,0x02,0x63, + 0x01,0x6b,0x04,0x25,0xa9,0x43,0x29,0x43,0x01,0x63,0x14,0x4e,0x70,0x68,0x80,0x00, + 0x04,0xd5,0x01,0x20,0xa0,0x47,0x70,0x68,0x80,0x00,0xfa,0xd4,0x10,0x4e,0x0f,0x20, + 0x70,0x60,0x01,0x20,0xa0,0x47,0x07,0x20,0x70,0x60,0x04,0x20,0xa0,0x47,0x77,0x60, + 0x8b,0x21,0x0c,0x48,0xc9,0x05,0x08,0x60,0x0b,0x48,0x01,0x69,0x29,0x43,0x01,0x61, + 0x30,0xbf,0xf8,0xbd,0x75,0x3a,0x00,0x00,0x85,0xa3,0x00,0x00,0x2c,0x68,0x00,0x20, + 0x11,0x3d,0x00,0x00,0x58,0x68,0x00,0x20,0xe5,0x3e,0x00,0x00,0x80,0x00,0x80,0x45, + 0x40,0x00,0x80,0x45,0x26,0x03,0x00,0x00,0x00,0xed,0x00,0xe0,0xf8,0xb5,0x05,0x20, + 0x43,0x24,0x24,0x06,0xe0,0x60,0x30,0x4e,0x01,0x20,0xb0,0x47,0x2f,0x4f,0x0f,0x20, + 0x78,0x60,0x8b,0x25,0xed,0x05,0x28,0x68,0x01,0x21,0x49,0x02,0x88,0x43,0x28,0x60, + 0x2b,0x48,0x80,0x47,0x01,0x20,0x80,0xf3,0x10,0x88,0x2a,0x48,0x40,0x68,0x2a,0x49, + 0x80,0x00,0x06,0xd4,0x28,0x68,0x08,0x22,0x10,0x43,0x28,0x60,0x01,0x20,0x88,0x47, + 0x01,0xe0,0x01,0x20,0x88,0x47,0x25,0x48,0x80,0x47,0x25,0x48,0x00,0x78,0xb0,0x47, + 0x0d,0x20,0x78,0x60,0x01,0x20,0xb0,0x47,0x22,0x48,0x80,0x47,0x60,0x68,0x01,0x22, + 0x52,0x03,0x10,0x43,0x60,0x60,0x29,0x20,0x1f,0x49,0x40,0x06,0xc1,0x60,0x01,0x6a, + 0x09,0x09,0x09,0x01,0x08,0x31,0x01,0x62,0x01,0x68,0xd3,0x10,0x19,0x43,0x01,0x60, + 0x1a,0x49,0x09,0x78,0x49,0x00,0x49,0x1c,0x41,0x61,0x61,0x68,0x18,0x48,0x91,0x43, + 0x00,0x78,0xc0,0x07,0xc0,0x0f,0x42,0x03,0x11,0x43,0x61,0x60,0x62,0x68,0x99,0x02, + 0x0a,0x43,0x62,0x60,0x28,0x23,0xa3,0x22,0xd2,0x05,0x13,0x60,0x11,0x4b,0x1b,0x88, + 0x93,0x62,0x62,0x68,0x00,0x05,0x8a,0x43,0x02,0x43,0x62,0x60,0x00,0x20,0x80,0xf3, + 0x10,0x88,0x0d,0x48,0x80,0x47,0xf8,0xbd,0xe5,0x3e,0x00,0x00,0x40,0x00,0x80,0x45, + 0x65,0x50,0x01,0x00,0x80,0x00,0x80,0x45,0xa1,0x59,0x01,0x00,0x29,0x48,0x01,0x00, + 0x41,0x68,0x00,0x20,0xc5,0x64,0x01,0x00,0xcc,0x34,0x63,0x04,0x74,0x68,0x00,0x20, + 0x3a,0x68,0x00,0x20,0x50,0x68,0x00,0x20,0x69,0x48,0x01,0x00,0x10,0xb5,0x15,0x48, + 0x80,0x7a,0xc0,0x07,0x01,0xd0,0x00,0x20,0x10,0xbd,0x13,0x48,0x80,0x47,0x05,0x20, + 0x00,0x07,0xc0,0x69,0x11,0x49,0x00,0x05,0x04,0xd0,0x08,0x78,0x01,0x28,0x14,0xd0, + 0x02,0x28,0x12,0xd0,0x08,0x78,0x00,0x28,0x08,0xd0,0x01,0x28,0x06,0xd0,0x02,0x28, + 0x04,0xd0,0x0b,0x48,0x80,0x47,0x0b,0x49,0x32,0x20,0x88,0x47,0x0a,0x49,0x04,0x20, + 0x88,0x47,0x0a,0x48,0x80,0x47,0x00,0x20,0x10,0xbd,0x09,0x49,0x04,0x20,0x88,0x47, + 0x01,0x20,0x10,0xbd,0x0c,0x6e,0x00,0x20,0x51,0x9a,0x00,0x00,0x18,0x10,0x00,0x20, + 0x69,0x61,0x01,0x00,0xe5,0x3e,0x00,0x00,0x59,0x59,0x01,0x00,0xd3,0x60,0x01,0x00, + 0xa1,0x59,0x01,0x00 + } +}; + +am_hal_ble_patch_t am_ble_performance_patch_b0 = +{ + .ui32Type = 0xBB, + .ui32Length = 0x0654, + .ui32CRC = 0x4c38, + .pui32Data = am_ble_performance_patch_data_b0.words, +}; + + +//***************************************************************************** + + + +//***************************************************************************** +// +// Patch Name: Function PATCH v0.4 for Apollo3 B0 +// +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Optimized AGC Table +// Fixed Channelmap indication rejected issue +// Fixed 800M Spur +// Fixed feature issue +// Fixed disconnect issue //long time large data transfer +// Date: 2019-10-25 +//***************************************************************************** + +const am_hal_ble_buffer(0x0230)am_ble_buffer_patch_data_b0 = +{ + .bytes = + { + 0x00,0x22,0x30,0x02,0x1f,0x00,0x00,0x00,0x84,0x65,0x06,0x00,0x73,0x6d,0x06,0x00, + 0x75,0x75,0x06,0x00,0x17,0x7b,0x06,0x00,0xa9,0x85,0x06,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x20,0xec,0xf7, + 0xf9,0xfc,0x00,0x28,0x0a,0xd0,0x00,0x20,0x00,0x90,0x03,0x46,0x02,0x46,0x01,0x46, + 0x24,0x68,0x21,0x20,0x35,0x34,0xa0,0x47,0x00,0xbf,0x38,0xbd,0xef,0xf7,0xfb,0xfe, + 0x0f,0x49,0x00,0x28,0x02,0xd0,0x08,0x78,0x01,0x28,0x12,0xd0,0x08,0x78,0x02,0x28, + 0x0f,0xd0,0x00,0x28,0x06,0xd0,0x01,0x28,0x04,0xd0,0x00,0xf0,0x0c,0x6e,0x00,0x20, + 0x00,0x00,0x00,0x04,0x1c,0x6e,0x00,0x20,0x00,0x49,0x08,0x47,0x41,0x34,0x00,0x20, + 0x23,0x4e,0xca,0x7c,0x75,0x68,0xc9,0x6a,0x00,0x2a,0x1d,0xd0,0x7d,0x22,0x12,0x02, + 0x91,0x42,0x02,0xd3,0x8a,0x1a,0x01,0x20,0x00,0xe0,0x52,0x1a,0x00,0x28,0x05,0xd0, + 0x20,0x46,0x50,0x43,0xea,0xf7,0x02,0xfa,0x20,0x1a,0x04,0xe0,0xea,0xf7,0xde,0xf9, + 0x00,0x19,0x01,0x02,0xc2,0x00,0x69,0x18,0x12,0x18,0x89,0x18,0x4a,0x0a,0x53,0x02, + 0xc9,0x1a,0x71,0x60,0x1e,0x21,0x48,0x43,0x80,0x18,0x70,0xbd,0x2c,0x68,0x00,0x20, + 0x0c,0x6e,0x00,0x20,0x00,0x49,0x08,0x47,0xb1,0x34,0x00,0x20,0xc1,0x7c,0xc0,0x6a, + 0x00,0x29,0x15,0xd0,0x7d,0x21,0x09,0x02,0x88,0x42,0x02,0xd3,0x02,0xd5,0x04,0x20, + 0x60,0x70,0x34,0xe0,0x28,0x69,0x06,0xf0,0xb5,0xf8,0x00,0x28,0x02,0xd0,0x02,0x20, + 0x60,0x70,0x2c,0xe0,0x03,0x98,0x04,0xf0,0x1f,0xfa,0x04,0x28,0x07,0xd1,0x68,0x46, + 0x01,0x79,0x02,0x20,0x88,0x43,0x05,0xd0,0x00,0x20,0x00,0x28,0x04,0xd0,0x00,0xbf, + 0x00,0x20,0x1c,0xe0,0x01,0x20,0xf8,0xe7,0xf0,0x88,0x00,0x90, + //0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + AM_HAL_BLE_LOCAL_FEATURE,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff, + 0xff,0x03,0x00,0x00,0xff,0x00,0x3c,0x1f,0x00,0x00,0x00,0x00,0x01,0x20,0x00,0x00, + 0x8d,0x84,0x00,0x00,0x02,0x20,0x00,0x00,0xcd,0x7d,0x00,0x00,0x03,0x20,0x00,0x00, + 0xd1,0x7e,0x00,0x00,0x05,0x20,0x00,0x00,0xfd,0x84,0x00,0x00,0xf0,0xb4,0x00,0x23, + 0x18,0x4c,0x25,0x69,0x18,0x49,0x7d,0x22,0x09,0x68,0x12,0x02,0x91,0x42,0x02,0xd3, + 0x8a,0x1a,0x01,0x23,0x00,0xe0,0x52,0x1a,0x06,0x46,0x56,0x43,0xf2,0x13,0x51,0x43, + 0x71,0x1a,0x1e,0x26,0x4e,0x43,0x4f,0x10,0xf6,0x19,0x8f,0x11,0xf6,0x19,0x49,0x12, + 0x71,0x18,0xce,0x13,0x00,0x2b,0x01,0xd0,0x80,0x1a,0x00,0xe0,0x10,0x18,0x42,0x19, + 0x91,0x08,0x8d,0x00,0x52,0x1b,0x00,0x2b,0x04,0xd0,0x43,0x01,0x18,0x1a,0x40,0x18, + 0x80,0x1b,0x03,0xe0,0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x19,0x22,0x61,0xf0,0xbc, + 0x70,0x47,0x00,0x00,0x00,0x6e,0x00,0x20,0x58,0x68,0x00,0x20,0x10,0xb4,0x00,0x23, + 0x14,0x21,0x02,0x46,0x4a,0x43,0x11,0x49,0x7d,0x24,0x09,0x68,0x24,0x02,0xa1,0x42, + 0x02,0xd9,0x09,0x1b,0x01,0x23,0x00,0xe0,0x61,0x1a,0x48,0x43,0x81,0x00,0x41,0x18, + 0x88,0x0a,0x0c,0x0c,0x00,0x19,0x4c,0x0c,0x00,0x19,0x4c,0x0d,0x00,0x19,0x4c,0x0e, + 0x00,0x19,0xc9,0x0f,0x40,0x18,0xc0,0x08,0x00,0x2b,0x01,0xd0,0x10,0x18,0x01,0xe0, + 0x10,0x1a,0x40,0x1e,0x40,0x1e,0x10,0xbc,0x70,0x47,0x00,0x00,0x58,0x68,0x00,0x20 + } +}; + +am_hal_ble_patch_t am_ble_buffer_patch_b0 = +{ + .ui32Type = 0xCC, + .ui32Length = 0x0230, + .ui32CRC = 0x320c, + .pui32Data = am_ble_buffer_patch_data_b0.words, +}; + + +//***************************************************************************** +// +// Patch Name: Function PATCH v0.4 for Apollo3 B0 +// Reduce duration from TX to TX +// Optimized 32K XO frequency calculation +// Optimized AGC Table +// Fixed Channelmap indication rejected issue +// Fixed 800M Spur +// Fixed feature issue +// Date: 2019-05-15 +//***************************************************************************** + + +am_hal_ble_buffer(0x00c2) am_ble_buffer_nvds_data_b0 = +{ + .bytes = + { + 0x4e,0x56,0x44,0x53, //NVDS_MAGIC_NUMBER + 0x01,0x06,0x06,0xef,0xbb,0x23,0x88,0x77,0x66, //bluetooth address + 0x02,0x06,0x0a,0x4e,0x5a,0x38,0x38,0x30,0x31,0x56,0x31,0x41,0x00, //device name + 0x03,0x06,0x01,0x00, //system clock frequency, 00=32MHz 01=24MHz others=16MHz + 0x07,0x06,0x02,0x00,0x00, //32K clock drift, 0x01f4 = 500 ppm + 0x0c,0x06,0x02,50,0x00, //sleep clock accuracy in ppm, 0x01f4 = 500 ppm + 0x08,0x06,0x01,0x00, //01 for BQB qualification, 00 for normal usage + 0x09,0x06,0x01,0x02, //clock source selection, 00 = internal RC32KHz, 02= use Apollo3 MCU 32.768KHz + 0x0a,0x06,0x04,0x00,0x00,0x00,0x00, //0x00000000 = auto detect and low frequency clock calibration + 0x0b,0x06,0x01,0x96, //rx_ifs 0x96 = 150us + 0x23,0x06,0x01,0x95, //tx_ifs 0x95 = 149us + 0x0d,0x06,0x02,0xe8,0x3, //duration allowed for XO32M stabilization from external wakeup + 0x0e,0x06,0x02,0xe8,0x3, //duration allowed for XO32M stabilization from internal wakeup signal + 0x0f,0x06,0x02,0x2c,0x01, //duration allowed for radio to leave low power mode + 0x10,0x06,0x04,0x00,0xc2,0x01,0x00, //set UART_BAUDRATE + 0x11,0x06,0x01,0x01, //sleep algorithm enabled + // 0x11,0x06,0x01,0x00, //sleep algorithm disabled + 0x12,0x06,0x01,0x01, //external wake-up support + 0x13,0x06,0x02,0xf4,0x01, //duration of sleep and wake-up algorithm + 0x14,0x06,0x02,0x60,0x00, //BLE Company ID + 0x15,0x06,0x01,0x08, //BLE major version + 0x16,0x06,0x01,0x03, //BLE minor version + 0x17,0x06,0x01,0x29, //BLE SW version build + 0x18,0x06,0x02,0xdc,0x05, //advertising interval (undirect) + 0x19,0x06,0x02,0xe2,0x04, //advertising interval (direct) + 0x20,0x06,0x01,0x01, //agc switch on + 0x21,0x06,0x01,0x02, //EA programming latency,set '2' with master mode + 0x22,0x06,0x01,0x00, //EA asap latency + 0x24,0x06,0x04,0x5C,0x09,0x6A,0x09, //radio TRX timing + 0x25,0x06,0x01,0x11, //modem polarity setting + 0x26,0x06,0x01,0x00, //modem sync setting + 0x27,0x06,0x01,0x02, //BLE reset delay + 0x2d,0x06,0x01,0x00, //2 byte mode switch, 01 to enable + 0x28,0x06,0x02,0xf6,0x2d, //initial agc gain setting + 0x29,0x06,0x01,0x0f, //initial Tx output power, 0x0f is +4dBm + 0x35,0x06,0x01,0x08, //maximum Tx ouput power setting + 0x37,0x06,0x01,0x00, //RC32K calibration control, 0xAA to enable + 0x05,0x06,0x02,0x34,0x00, //no use + 0x04,0x06,0x01,0x20, //internal dvdd voltage level control if using 0.9V from MCU side + 0x2e,0x06,0x01,0x00, //instant indication,set "0" to disbale instant reject + 0x00,0x00,0x00,0x00 //dummy + } +}; + +am_hal_ble_patch_t am_ble_nvds_patch_b0 = +{ + .ui32Type = 0xDD, + .ui32Length = 0x00c2, + .ui32CRC = 0x112b, + .pui32Data = am_ble_buffer_nvds_data_b0.words, +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h new file mode 100644 index 0000000000..2e444661eb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ble_patch_b0.h @@ -0,0 +1,106 @@ +//***************************************************************************** +// +//! @file am_hal_ble_patch_b0.h +//! +//! @brief This is a binary patch for the BLE core. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_BLE_PATCH_B0_H +#define AM_HAL_BLE_PATCH_B0_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Patch array pointer. +// +//***************************************************************************** +extern am_hal_ble_patch_t **am_hal_ble_default_patches_b0; +extern am_hal_ble_patch_t **am_hal_ble_default_copy_patches_b0; +extern const uint32_t am_hal_ble_num_default_patches_b0; + +//***************************************************************************** +// +// Pointers for specific patches. +// +//***************************************************************************** +extern am_hal_ble_patch_t am_ble_performance_patch_b0; +extern am_hal_ble_patch_t am_ble_nvds_patch_b0; + +//***************************************************************************** +// +// Default patch structure. +// +//***************************************************************************** +extern am_hal_ble_patch_t g_AMBLEDefaultPatchB0; + +//***************************************************************************** +// +// Macros for accessing specific NVDS parameters. +// +//***************************************************************************** +#define AM_HAL_BLE_NVDS_CLOCKDRIFT_OFFSET 30 +#define AM_HAL_BLE_NVDS_SLEEPCLOCKDRIFT_OFFSET 35 +#define AM_HAL_BLE_NVDS_CLOCKSOURCE_OFFSET 44 +#define AM_HAL_BLE_NVDS_SLEEPENABLE_OFFSET 85 +#define AM_HAL_BLE_NVDS_AGC_OFFSET 125 + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BLE_PATCH_B0_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.c new file mode 100644 index 0000000000..66e68fb2e0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.c @@ -0,0 +1,282 @@ +//***************************************************************************** +// +// am_hal_burst.c +//! @file +//! +//! @brief Functions for controlling Burst Mode operation. +//! +//! @addtogroup burstmode3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +// +// Globals. +// +bool g_am_hal_burst_mode_available = false; + +// **************************************************************************** +// +// am_hal_burst_mode_initialize() +// Burst mode initialization function +// +// **************************************************************************** +uint32_t +am_hal_burst_mode_initialize(am_hal_burst_avail_e *peBurstAvail) +{ + uint32_t ui32Status; + // + // Check if the Burst Mode feature is available based on the SKU. + // + if ( 0 == MCUCTRL->SKU_b.ALLOWBURST ) + { + // + // Burst mode is not available. + // + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable the Burst Feature Event (DEVPWREVENTEN). + // + PWRCTRL->DEVPWREVENTEN_b.BURSTEVEN = 1; + + // + // BLE buck is shared by Burst as well + // Enable the BLE buck trim values if in use + // + if (PWRCTRL->SUPPLYSRC_b.BLEBUCKEN) + { + am_hal_pwrctrl_blebuck_trim(); + } + + // + // Enable the Burst Functionality (FEATUREENABLE). + // + MCUCTRL->FEATUREENABLE_b.BURSTREQ = 1; + + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&MCUCTRL->FEATUREENABLE, + MCUCTRL_FEATUREENABLE_BURSTACK_Msk, + MCUCTRL_FEATUREENABLE_BURSTACK_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return ui32Status; + } + + if ( 0 == MCUCTRL->FEATUREENABLE_b.BURSTAVAIL ) + { + // + // Burst mode is not available. + // + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Check the ACK for the Burst Functionality. + // + if ( MCUCTRL->FEATUREENABLE_b.BURSTACK == 0 ) + { + // + // If NACK, return status. + // + g_am_hal_burst_mode_available = false; + *peBurstAvail = AM_HAL_BURST_NOTAVAIL; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Return Availability + // + g_am_hal_burst_mode_available = true; + *peBurstAvail = AM_HAL_BURST_AVAIL; + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_burst_mode_enable() +// Burst mode enable function +// +// **************************************************************************** +uint32_t +am_hal_burst_mode_enable(am_hal_burst_mode_e *peBurstStatus) +{ + uint32_t ui32Status; + + // + // Check if Burst Mode is allowed and return status if it is not. + // + if (!g_am_hal_burst_mode_available) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Request Burst Mode Enable (FREQCTRL) + // + CLKGEN->FREQCTRL_b.BURSTREQ = CLKGEN_FREQCTRL_BURSTREQ_EN; + +// while (0 == AM_BFR(CLKGEN, FREQCTRL, BURSTACK)); + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&CLKGEN->FREQCTRL, + CLKGEN_FREQCTRL_BURSTSTATUS_Msk, + CLKGEN_FREQCTRL_BURSTSTATUS_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return ui32Status; + } + + // + // Check that the Burst Request was ACK'd. + // + if ( 0 == CLKGEN->FREQCTRL_b.BURSTACK ) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return AM_HAL_STATUS_FAIL; + } + + // + // Check the Burst Mode Status (FREQCTRL) + // + if ( CLKGEN->FREQCTRL_b.BURSTSTATUS > 0) + { + *peBurstStatus = AM_HAL_BURST_MODE; + } + else + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + } + + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_burst_mode_disable() +// Burst mode disable function +// +// **************************************************************************** +uint32_t +am_hal_burst_mode_disable(am_hal_burst_mode_e *peBurstStatus) +{ + uint32_t ui32Status; + + // + // Request Burst Mode Enable (FREQCTRL) + // + // + // Safely disable burst mode. + // + AM_CRITICAL_BEGIN + am_hal_flash_store_ui32((uint32_t*)&CLKGEN->FREQCTRL, CLKGEN_FREQCTRL_BURSTREQ_DIS); + AM_CRITICAL_END + + // + // Disable the Burst Feature Event (DEVPWREVENTEN). + // + PWRCTRL->DEVPWREVENTEN_b.BURSTEVEN = 0; + + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&CLKGEN->FREQCTRL, + CLKGEN_FREQCTRL_BURSTSTATUS_Msk, + 0, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + return ui32Status; + } + + // + // Check the Burst Mode Status (FREQCTRL) + // + // + // Check the Burst Mode Status (FREQCTRL) + // + if ( CLKGEN->FREQCTRL_b.BURSTSTATUS > 0 ) + { + *peBurstStatus = AM_HAL_BURST_MODE; + } + else + { + *peBurstStatus = AM_HAL_NORMAL_MODE; + } + + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// am_hal_burst_mode_status() - Return current burst mode state. +// +// Implemented as a macro, this function returns the current burst mode state. +// AM_HAL_BURST_MODE +// AM_HAL_NORMAL_MODE +// +//***************************************************************************** + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.h new file mode 100644 index 0000000000..e95c670af3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_burst.h @@ -0,0 +1,149 @@ +//***************************************************************************** +// +// am_hal_burst.h +//! @file +//! +//! @brief Functions for controlling Burst Mode operation. +//! +//! @addtogroup burstmode3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_BURST_H +#define AM_HAL_BURST_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Burst Mode Status enums +// +//***************************************************************************** +// +// Avail - the result of a feature availability interrogation. +// +typedef enum +{ + AM_HAL_BURST_AVAIL, + AM_HAL_BURST_NOTAVAIL +} am_hal_burst_avail_e; + +// +// Mode - the result of a change request. +// +typedef enum +{ + AM_HAL_BURST_MODE, + AM_HAL_NORMAL_MODE, +} am_hal_burst_mode_e; + +//***************************************************************************** +// +//! @brief Burst mode initialization function +//! +//! @param peBurstAvail - Availibility of feature +//! +//! This function initializes the Apollo3 MCU for Burst Mode operation. It does +//! not set the MCU into Burst Mode. This should be called once at system +//! initialization if Burst Mode is going to be used in the system. +//! +//! @return status of API call. +// +//***************************************************************************** +extern uint32_t am_hal_burst_mode_initialize(am_hal_burst_avail_e *peBurstAvail); + +//***************************************************************************** +// +//! @brief Burst mode enable function +//! +//! @param peBurstStatus - resulting mode after call. +//! +//! This function enables the Apollo3 MCU into Burst Mode operation. +//! +//! @return status of API call. +// +//***************************************************************************** +extern uint32_t am_hal_burst_mode_enable(am_hal_burst_mode_e *peBurstStatus); + +//***************************************************************************** +// +//! @brief Burst mode disable function +//! +//! @param peBurstStatus - resulting mode after call. +//! +//! This function disables the Apollo3 MCU from Burst Mode operation. It returns +//! the MCU to Normal Mode. +//! +//! @return status of API call. +// +//***************************************************************************** +extern uint32_t am_hal_burst_mode_disable(am_hal_burst_mode_e *peBurstStatus); + +//***************************************************************************** +// +//! @brief Return current burst mode state +//! +//! Implemented as a macro, this function returns the current burst mode state. +//! AM_HAL_BURST_MODE +//! AM_HAL_NORMAL_MODE +// +//***************************************************************************** +#define am_hal_burst_mode_status() \ + (CLKGEN->FREQCTRL_b.BURSTSTATUS ? AM_HAL_BURST_MODE : AM_HAL_NORMAL_MODE) + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_BURST_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.c new file mode 100644 index 0000000000..1006de24f1 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.c @@ -0,0 +1,460 @@ +//***************************************************************************** +// +// am_hal_cachectrl.c +//! @file +//! +//! @brief Functions for interfacing with the CACHE controller. +//! +//! @addtogroup cachectrl3 Cache Control (CACHE) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Default settings for the cache. +// +//***************************************************************************** +const am_hal_cachectrl_config_t am_hal_cachectrl_defaults = +{ + .bLRU = 0, + .eDescript = AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E, + .eMode = AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA, +}; + +//***************************************************************************** +// +// Configure the cache with given and recommended settings, but do not enable. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig) +{ + // + // In the case where cache is currently enabled, we need to gracefully + // bow out of that configuration before reconfiguring. The best way to + // accomplish that is to shut down the ID bits, leaving the cache enabled. + // Once the instr and data caches have been disabled, we can safely set + // any new configuration, including disabling the controller. + // + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG &= + ~(CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk | + CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk); + AM_CRITICAL_END + + CACHECTRL->CACHECFG = + _VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 0) | + _VAL2FLD(CACHECTRL_CACHECFG_CACHE_CLKGATE, 1) | + _VAL2FLD(CACHECTRL_CACHECFG_CACHE_LS, 0) | + _VAL2FLD(CACHECTRL_CACHECFG_DATA_CLKGATE, 1) | + _VAL2FLD(CACHECTRL_CACHECFG_ENABLE_MONITOR, 0) | + _VAL2FLD(CACHECTRL_CACHECFG_LRU, psConfig->bLRU) | + _VAL2FLD(CACHECTRL_CACHECFG_CONFIG, psConfig->eDescript) | + ((psConfig->eMode << CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos) & + (CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk | + CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk)); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_cachectrl_config() + +//***************************************************************************** +// +// Enable the cache. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_enable(void) +{ + // + // Enable the cache + // + CACHECTRL->CACHECFG |= _VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 1); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_cachectrl_enable() + +//***************************************************************************** +// +// Disable the cache. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_disable(void) +{ + // + // Shut down as gracefully as possible. + // Disable the I/D cache enable bits first to allow a little time + // for any in-flight transactions to hand off to the line buffer. + // Then clear the enable. + // + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG &= ~(_VAL2FLD(CACHECTRL_CACHECFG_ICACHE_ENABLE, 1) | + _VAL2FLD(CACHECTRL_CACHECFG_DCACHE_ENABLE, 1)); + CACHECTRL->CACHECFG &= ~_VAL2FLD(CACHECTRL_CACHECFG_ENABLE, 1); + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_cachectrl_disable() + +//***************************************************************************** +// +// Control helper functions. +// +//***************************************************************************** +static bool +set_LPMMODE(uint32_t ui32value) +{ + uint32_t ui32Val; + uint32_t *pui32RegAddr; + + if ( ui32value > (CACHECTRL_FLASHCFG_LPMMODE_Msk >> CACHECTRL_FLASHCFG_LPMMODE_Pos) ) + { + return false; + } + + // + // Compute register address (assumes each reg is 1 word offset). + // + pui32RegAddr = (uint32_t*)&CACHECTRL->FLASHCFG; + + AM_CRITICAL_BEGIN + ui32Val = am_hal_flash_load_ui32(pui32RegAddr); + ui32Val &= ~(CACHECTRL_FLASHCFG_LPMMODE_Msk | + CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk); + ui32Val |= _VAL2FLD(CACHECTRL_FLASHCFG_LPMMODE, ui32value) | + _VAL2FLD(CACHECTRL_FLASHCFG_LPM_RD_WAIT, 0x7); + am_hal_flash_store_ui32(pui32RegAddr, ui32Val); + AM_CRITICAL_END + + return true; +} // set_LPMMODE() + +static bool +set_SEDELAY(uint32_t ui32value) +{ + uint32_t ui32Val; + uint32_t *pui32RegAddr; + + if ( ui32value > (CACHECTRL_FLASHCFG_SEDELAY_Msk >> CACHECTRL_FLASHCFG_SEDELAY_Pos) ) + { + return false; + } + + // + // Compute register address (assumes each reg is 1 word offset). + // + pui32RegAddr = (uint32_t*)&CACHECTRL->FLASHCFG; + + AM_CRITICAL_BEGIN + ui32Val = am_hal_flash_load_ui32(pui32RegAddr); + ui32Val &= ~(CACHECTRL_FLASHCFG_SEDELAY_Msk | + CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk); + ui32Val |= _VAL2FLD(CACHECTRL_FLASHCFG_SEDELAY, ui32value) | + _VAL2FLD(CACHECTRL_FLASHCFG_LPM_RD_WAIT, 0x7); + am_hal_flash_store_ui32(pui32RegAddr, ui32Val); + AM_CRITICAL_END + + return true; +} // set_SEDELAY() + +static bool +set_RDWAIT(uint32_t ui32value) +{ + uint32_t ui32Val; + uint32_t *pui32RegAddr; + + if ( ui32value > (CACHECTRL_FLASHCFG_RD_WAIT_Msk >> CACHECTRL_FLASHCFG_RD_WAIT_Pos) ) + { + return false; + } + + // + // Compute register address (assumes each reg is 1 word offset). + // + pui32RegAddr = (uint32_t*)&CACHECTRL->FLASHCFG; + + AM_CRITICAL_BEGIN + ui32Val = am_hal_flash_load_ui32(pui32RegAddr); + ui32Val &= ~(CACHECTRL_FLASHCFG_RD_WAIT_Msk | + CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk); + ui32Val |= _VAL2FLD(CACHECTRL_FLASHCFG_RD_WAIT, ui32value) | + _VAL2FLD(CACHECTRL_FLASHCFG_LPM_RD_WAIT, 0x7); + am_hal_flash_store_ui32(pui32RegAddr, ui32Val); + AM_CRITICAL_END + + return true; +} // set_RDWAIT() + +//***************************************************************************** +// +// Select the cache configuration type. +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_control(am_hal_cachectrl_control_e eControl, void *pArgs) +{ + uint32_t ui32Arg; + uint32_t ui32SetMask = 0; + + switch ( eControl ) + { + case AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE: + ui32SetMask = CACHECTRL_CTRL_INVALIDATE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET: + if ( !_FLD2VAL(CACHECTRL_CACHECFG_ENABLE_MONITOR, CACHECTRL->CACHECFG) ) + { + // + // The monitor must be enabled for the reset to have any affect. + // + return AM_HAL_STATUS_INVALID_OPERATION; + } + else + { + ui32SetMask = CACHECTRL_CTRL_RESET_STAT_Msk; + } + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk | + CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk | + CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE: + ui32SetMask = CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk; + break; + case AM_HAL_CACHECTRL_CONTROL_MONITOR_ENABLE: + ui32SetMask = 0; + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG |= CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk; + AM_CRITICAL_END + break; + case AM_HAL_CACHECTRL_CONTROL_MONITOR_DISABLE: + ui32SetMask = 0; + AM_CRITICAL_BEGIN + CACHECTRL->CACHECFG &= ~CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk; + AM_CRITICAL_END + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_RESET: + // + // Safely set the reset values for LPMMODE, SEDELAY, and RDWAIT. + // + if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_NEVER) || + !set_SEDELAY(0x7) || + !set_RDWAIT(0x3) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED: + // + // Safely set the as recommended values (from the datasheet) + // for LPMMODE, SEDELAY, and RDWAIT. + // + if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY) || + !set_SEDELAY(0x5) || + !set_RDWAIT(0x1) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_AGGRESSIVE: + // + // Safely set aggressive values for LPMMODE, SEDELAY, and RDWAIT. + // (For now select recommended values.) + // + if ( !set_LPMMODE(AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY) || + !set_SEDELAY(0x6) || + !set_RDWAIT(0x1) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_LPMMODE_SET: + // + // Safely set LPMMODE, SEDELAY, or RDWAIT. + // The new value is passed by reference via pArgs. That is, pArgs is + // assumed to be a pointer to a uint32_t of the new value. + // + if ( !pArgs ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + ui32Arg = *(uint32_t*)pArgs; + if ( !set_LPMMODE(ui32Arg) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_SEDELAY_SET: + if ( !pArgs ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + ui32Arg = *(uint32_t*)pArgs; + if ( !set_SEDELAY(ui32Arg) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_RDWAIT_SET: + if ( !pArgs ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + ui32Arg = *(uint32_t*)pArgs; + if ( !set_RDWAIT(ui32Arg) ) + { + return AM_HAL_STATUS_FAIL; + } + break; + case AM_HAL_CACHECTRL_CONTROL_NC_CFG: + { + if ( pArgs == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + am_hal_cachectrl_nc_cfg_t *pNcCfg; + pNcCfg = (am_hal_cachectrl_nc_cfg_t *)pArgs; +#ifndef AM_HAL_DISABLE_API_VALIDATION + // Make sure the addresses are valid + if ((pNcCfg->ui32StartAddr & ~CACHECTRL_NCR0START_ADDR_Msk) || + (pNcCfg->ui32EndAddr & ~CACHECTRL_NCR0START_ADDR_Msk)) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if (pNcCfg->eNCRegion == AM_HAL_CACHECTRL_NCR0) + { + CACHECTRL->NCR0START = pNcCfg->ui32StartAddr; + CACHECTRL->NCR0END = pNcCfg->ui32EndAddr; + CACHECTRL->CACHECFG_b.ENABLE_NC0 = pNcCfg->bEnable; + } + else if (pNcCfg->eNCRegion == AM_HAL_CACHECTRL_NCR1) + { + CACHECTRL->NCR1START = pNcCfg->ui32StartAddr; + CACHECTRL->NCR1END = pNcCfg->ui32EndAddr; + CACHECTRL->CACHECFG_b.ENABLE_NC1 = pNcCfg->bEnable; + } +#ifndef AM_HAL_DISABLE_API_VALIDATION + else + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + return AM_HAL_STATUS_SUCCESS; + } + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // All fields in the CACHECTRL register are write-only or read-only. + // A write to CACHECTRL acts as a mask-set. That is, only the bits + // written as '1' have an effect, any bits written as '0' are unaffected. + // + // Important note - setting of an enable and disable simultanously has + // unpredicable results. + // + if ( ui32SetMask ) + { + CACHECTRL->CTRL = ui32SetMask; + } + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_cachectrl_control() + +//***************************************************************************** +// +// Cache controller status function +// +//***************************************************************************** +uint32_t +am_hal_cachectrl_status_get(am_hal_cachectrl_status_t *psStatus) +{ + uint32_t ui32Status; + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32Status = CACHECTRL->CTRL; + + psStatus->bFlash0SleepMode = + _FLD2VAL(CACHECTRL_CTRL_FLASH0_SLM_STATUS, ui32Status); + psStatus->bFlash1SleepMode = + _FLD2VAL(CACHECTRL_CTRL_FLASH1_SLM_STATUS, ui32Status); + psStatus->bCacheReady = + _FLD2VAL(CACHECTRL_CTRL_CACHE_READY, ui32Status); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_cachectrl_status_get() + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.h new file mode 100644 index 0000000000..fc39115dee --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cachectrl.h @@ -0,0 +1,289 @@ +// **************************************************************************** +// +// am_hal_cachectrl.h +//! @file +//! +//! @brief Functions for accessing and configuring the CACHE controller. +//! +//! @addtogroup cachectrl3 Cache Control (CACHE) +//! @ingroup apollo3hal +//! @{ +// +// **************************************************************************** + +// **************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +// **************************************************************************** +#ifndef AM_HAL_CACHECTRL_H +#define AM_HAL_CACHECTRL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_CACHECTRL 1 + +// +// Cachectrl status. +// +typedef struct +{ + bool bFlash0SleepMode; + bool bFlash1SleepMode; + bool bCacheReady; +} am_hal_cachectrl_status_t; + +// **************************************************************************** +// +//! @name Cache Config +//! @brief Configuration selection for the cache. +//! +//! These macros may be used in conjunction with the +//! am_hal_cachectrl_cache_config() function to select the cache type. +//! +//! @{ +// +// **************************************************************************** +// +// Cache description type, where: +// nWay = number of ways (associativity) +// 128B = 128 bits linesize +// 512E = 512 entries, 1024E = 1024 entries +// +typedef enum +{ + AM_HAL_CACHECTRL_DESCR_1WAY_128B_512E = CACHECTRL_CACHECFG_CONFIG_W1_128B_512E, + AM_HAL_CACHECTRL_DESCR_2WAY_128B_512E = CACHECTRL_CACHECFG_CONFIG_W2_128B_512E, + AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E = CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E +} am_hal_cachectrl_descr_e; + +typedef enum +{ + AM_HAL_CACHECTRL_NCR0 = 0, + AM_HAL_CACHECTRL_NCR1 = 1 +} am_hal_cachectrl_nc_region_e; + +// Config struture for AM_HAL_CACHECTRL_CONTROL_NC_CFG +typedef struct +{ + am_hal_cachectrl_nc_region_e eNCRegion; + bool bEnable; + uint32_t ui32StartAddr; + uint32_t ui32EndAddr; +} am_hal_cachectrl_nc_cfg_t; + +// +// Control operations. +// +typedef enum +{ + AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE = 1, + AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET, + AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE, + AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE, + AM_HAL_CACHECTRL_CONTROL_MONITOR_ENABLE, + AM_HAL_CACHECTRL_CONTROL_MONITOR_DISABLE, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_RESET, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_AGGRESSIVE, + AM_HAL_CACHECTRL_CONTROL_LPMMODE_SET, + AM_HAL_CACHECTRL_CONTROL_SEDELAY_SET, + AM_HAL_CACHECTRL_CONTROL_RDWAIT_SET, + // Configure up to two non-cacheable regions + AM_HAL_CACHECTRL_CONTROL_NC_CFG, +} am_hal_cachectrl_control_e; + +// +// Cache config values used for ui8Mode. +// +typedef enum +{ + // Note - this enum ordering is critical, do not modify. + AM_HAL_CACHECTRL_CONFIG_MODE_DISABLE, + AM_HAL_CACHECTRL_CONFIG_MODE_INSTR, + AM_HAL_CACHECTRL_CONFIG_MODE_DATA, + AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA +} am_hal_cachectrl_config_mode_e; + +// +// FLASHCFG LPMMODE. +// +typedef enum +{ + AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_NEVER = CACHECTRL_FLASHCFG_LPMMODE_NEVER, + AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_STANDBY = CACHECTRL_FLASHCFG_LPMMODE_STANDBY, + AM_HAL_CACHECTRL_FLASHCFG_LPMMODE_ALWAYS = CACHECTRL_FLASHCFG_LPMMODE_ALWAYS +} am_hal_cachectrl_flashcfg_lppmode_e; + +// **************************************************************************** +// +// Cache configuration structure +// This structure used for am_hal_cachectrl_config(). +// +// **************************************************************************** +typedef struct +{ + // + //! Set to one of: + //! AM_HAL_CACHECTRL_DESCR_1WAY_128B_512E + //! Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) + //! AM_HAL_CACHECTRL_DESCR_2WAY_128B_512E + //! Two way set associative, 128-bit linesize, 512 entries (8 SRAMs active) + //! AM_HAL_CACHECTRL_DESCR_1WAY_128B_1024E + //! Direct-mapped set associative, 128-bit linesize, 1024 entries (8 SRAMs active) + am_hal_cachectrl_descr_e eDescript; + + // + //! Set to one of the following: + //! AM_HAL_CACHECTRL_CONFIG_MODE_DISABLE - Disable both instr and data caching + //! AM_HAL_CACHECTRL_CONFIG_MODE_INSTR - Enable instr caching only + //! AM_HAL_CACHECTRL_CONFIG_MODE_DATA - Enable data caching only + //! AM_HAL_CACHECTRL_CONFIG_MODE_INSTR_DATA - Enable both instr and data caching + am_hal_cachectrl_config_mode_e eMode; + + // + //! Set to true to enable the LRU (least recently used) replacement policy. + //! Set to false to enable the LRR (least recently replaced) replacement policy. + //! Note - LRR minimizes writes to the TAG SRAM. + // + bool bLRU; + +} am_hal_cachectrl_config_t; + +extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults; + +// **************************************************************************** +// +// Function prototypes +// +// **************************************************************************** +// **************************************************************************** +// +//! @brief Configure the cache using the supplied settings. +//! +//! @param psConfig - pointer to a config structure containing cache settings. +//! +//! This function takes in a structure of cache settings and uses them to +//! configure the cache. This function will configures all of the settings in +//! the structure as well as recommended settings for various other cache +//! configuration parameters. +//! +//! This function does NOT enable the cache, which is handled in a separate +//! function. In fact, if the cache is enabled prior to calling this function, +//! it will return from the call disabled. +//! +//! For most applications, the default cache settings will be the most +//! efficient choice. To use the default cache settings with this function, use +//! the address of the global am_hal_cachectrl_defaults structure as the +//! psConfig argument. +//! +//! @return Status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig); + +// **************************************************************************** +// +//! @brief Enable the cache. +//! +//! Enable the cache for operation. +//! +//! @return Status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_enable(void); + +// **************************************************************************** +// +//! @brief Disable the cache. +//! +//! Use this function to disable cache. Other configuration settings are not +//! not required. +//! +//! @return Status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_disable(void); + +// **************************************************************************** +// +//! @brief Assert various specific controls on the cache. +//! +//! This function is used to apply various controls on the cache. +//! +//! @param eControl - One of the following: +//! AM_HAL_CACHECTRL_CONTROL_FLASH_CACHE_INVALIDATE +//! AM_HAL_CACHECTRL_CONTROL_STATISTICS_RESET +//! AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_ENABLE, +//! AM_HAL_CACHECTRL_CONTROL_FLASH_ALL_SLEEP_DISABLE, +//! AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_ENABLE +//! AM_HAL_CACHECTRL_CONTROL_FLASH0_SLEEP_DISABLE +//! AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_ENABLE +//! AM_HAL_CACHECTRL_CONTROL_FLASH1_SLEEP_DISABLE +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_control(am_hal_cachectrl_control_e eControl, + void *pArgs); + +// **************************************************************************** +// +//! @brief Cache controller status function +//! +//! This function returns the current status of the cache. +//! +//! @param psStatus - ptr to a status structure to receive the current statuses. +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_cachectrl_status_get(am_hal_cachectrl_status_t *psStatus); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CACHECTRL_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.c new file mode 100644 index 0000000000..6a9d530841 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.c @@ -0,0 +1,410 @@ +// **************************************************************************** +// +// am_hal_clkgen.c +//! @file +//! +//! @brief Functions for interfacing with the CLKGEN. +//! +//! @addtogroup clkgen3 Clock Generator (CLKGEN) +//! @ingroup apollo3hal +//! @{ +// +// **************************************************************************** + +// **************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +// **************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + + +// **************************************************************************** +// +// am_hal_clkgen_control() +// Apply various specific commands/controls on the CLKGEN module. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_control(am_hal_clkgen_control_e eControl, void *pArgs) +{ + uint32_t ui32Regval; + + // + // Take a snapshot of the reset status, if not done already + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + + switch ( eControl ) + { + case AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX: + // + // Unlock the clock control register. + // Set the HFRC divisor to the required operating value. + // Lock the clock configuration registers. + // + CLKGEN->CLKKEY = CLKGEN_CLKKEY_CLKKEY_Key; + CLKGEN->CCTRL = CLKGEN_CCTRL_CORESEL_HFRC; + CLKGEN->CLKKEY = 0; + break; + + case AM_HAL_CLKGEN_CONTROL_SYSCLK_DIV2: + CLKGEN->CLKKEY = CLKGEN_CLKKEY_CLKKEY_Key; + CLKGEN->CCTRL = CLKGEN_CCTRL_CORESEL_HFRC_DIV2; + CLKGEN->CLKKEY = 0; + break; + + case AM_HAL_CLKGEN_CONTROL_LFRC_START: + CLKGEN->OCTRL_b.STOPRC = CLKGEN_OCTRL_STOPRC_EN; + break; + + case AM_HAL_CLKGEN_CONTROL_XTAL_START: + CLKGEN->OCTRL_b.STOPXT = CLKGEN_OCTRL_STOPXT_EN; + break; + + case AM_HAL_CLKGEN_CONTROL_LFRC_STOP: + CLKGEN->OCTRL_b.STOPRC = CLKGEN_OCTRL_STOPRC_STOP; + break; + + case AM_HAL_CLKGEN_CONTROL_XTAL_STOP: + // Software Workaround to guarantee proper function of HFADJ. + if (APOLLO3_B0) + { + MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 1; + } + CLKGEN->OCTRL_b.STOPXT = CLKGEN_OCTRL_STOPXT_STOP; + break; + + case AM_HAL_CLKGEN_CONTROL_RTC_SEL_LFRC: + CLKGEN->OCTRL_b.OSEL = CLKGEN_OCTRL_OSEL_RTC_LFRC; + break; + + case AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL: + CLKGEN->OCTRL_b.OSEL = CLKGEN_OCTRL_OSEL_RTC_XT; + break; + + case AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE: + // Software Workaround to guarantee proper function of HFADJ. + if (APOLLO3_B0) + { + MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 3; + am_hal_flash_delay(FLASH_CYCLES_US(1000)); + } + if ( pArgs == 0 ) + { + ui32Regval = + _VAL2FLD(CLKGEN_HFADJ_HFADJGAIN, CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2) | /* Default value (Apollo3) */ + _VAL2FLD(CLKGEN_HFADJ_HFWARMUP, CLKGEN_HFADJ_HFWARMUP_1SEC) | /* Default value */ + _VAL2FLD(CLKGEN_HFADJ_HFXTADJ, 0x5B8) | /* Default value */ + _VAL2FLD(CLKGEN_HFADJ_HFADJCK, CLKGEN_HFADJ_HFADJCK_4SEC) | /* Default value */ + _VAL2FLD(CLKGEN_HFADJ_HFADJEN, CLKGEN_HFADJ_HFADJEN_EN); + } + else + { + ui32Regval = *(uint32_t*)pArgs; + } + + // + // Make sure the ENABLE bit is set. + // + ui32Regval |= _VAL2FLD(CLKGEN_HFADJ_HFADJEN, CLKGEN_HFADJ_HFADJEN_EN); + CLKGEN->HFADJ = ui32Regval; + break; + + case AM_HAL_CLKGEN_CONTROL_HFADJ_DISABLE: + CLKGEN->HFADJ_b.HFADJEN = 0; + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_control() + +// **************************************************************************** +// +// am_hal_clkgen_status_get() +// This function returns the current value of various CLKGEN statuses. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_status_get(am_hal_clkgen_status_t *psStatus) +{ + uint32_t ui32Status; + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + psStatus->ui32SysclkFreq = + CLKGEN->CCTRL_b.CORESEL ? + AM_HAL_CLKGEN_FREQ_MAX_HZ / 2 : + AM_HAL_CLKGEN_FREQ_MAX_HZ; + + ui32Status = CLKGEN->STATUS; + + psStatus->eRTCOSC = + _FLD2VAL(CLKGEN_STATUS_OMODE, ui32Status) ? + AM_HAL_CLKGEN_STATUS_RTCOSC_LFRC : + AM_HAL_CLKGEN_STATUS_RTCOSC_XTAL; + + psStatus->bXtalFailure = + _FLD2VAL(CLKGEN_STATUS_OSCF, ui32Status); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_status_get() + +// **************************************************************************** +// +// am_hal_clkgen_clkout_enable() +// This function is used to select and enable CLKOUT. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_clkout_enable(bool bEnable, am_hal_clkgen_clkout_e eClkSelect) +{ + if ( !bEnable ) + { + CLKGEN->CLKOUT_b.CKEN = 0; + } + + // + // Do a basic validation of the eClkSelect parameter. + // Not every value in the range is valid, but at least this simple check + // provides a reasonable chance that the parameter is valid. + // + if ( eClkSelect <= (am_hal_clkgen_clkout_e)CLKGEN_CLKOUT_CKSEL_LFRCNE ) + { + // + // Are we actually changing the frequency? + // + if ( CLKGEN->CLKOUT_b.CKSEL != eClkSelect ) + { + // + // Disable before changing the clock + // + CLKGEN->CLKOUT_b.CKEN = 0; + + // + // Set the new clock select + // + CLKGEN->CLKOUT_b.CKSEL = eClkSelect; + } + + // + // Enable/disable as requested. + // + CLKGEN->CLKOUT_b.CKEN = bEnable; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_clkout_enable() + +// **************************************************************************** +// +// am_hal_clkgen_interrupt_enable() +// Enable selected CLKGEN Interrupts. +// +// **************************************************************************** +uint32_t am_hal_clkgen_interrupt_enable(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Set the interrupt enables according to the mask. + // + CLKGEN->INTRPTEN |= ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_enable() + +// **************************************************************************** +// +// am_hal_clkgen_interrupt_disable( +// Disable selected CLKGEN Interrupts. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_interrupt_disable(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Disable the interrupts. + // + CLKGEN->INTRPTEN &= ~ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_disable() + +//***************************************************************************** +// +// am_hal_clkgen_interrupt_clear() +// IOM interrupt clear +// +//***************************************************************************** +uint32_t +am_hal_clkgen_interrupt_clear(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Clear the requested interrupts. + // + CLKGEN->INTRPTCLR = ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_clear() + +// **************************************************************************** +// +// am_hal_clkgen_interrupt_status_get() +// Return CLKGEN interrupts. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + uint32_t ui32IntStatus; + + if ( !pui32IntStatus ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32IntStatus = CLKGEN->INTRPTSTAT; + + if ( bEnabledOnly ) + { + ui32IntStatus &= CLKGEN->INTRPTEN; + } + + *pui32IntStatus = ui32IntStatus; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_status_get) + +// **************************************************************************** +// +// This function sets the CLKGEN interrupts. +// +// **************************************************************************** +uint32_t +am_hal_clkgen_interrupt_set(am_hal_clkgen_interrupt_e ui32IntMask) +{ + if ( (ui32IntMask & + (CLKGEN_INTRPTEN_OF_Msk | + CLKGEN_INTRPTEN_ACC_Msk | + CLKGEN_INTRPTEN_ACF_Msk)) == 0 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Set the interrupt status. + // + CLKGEN->INTRPTSET = ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_clkgen_interrupt_set() + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.h new file mode 100644 index 0000000000..154686d715 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_clkgen.h @@ -0,0 +1,367 @@ +//***************************************************************************** +// +// am_hal_clkgen.h +//! @file +//! +//! @brief Functions for accessing and configuring the CLKGEN. +//! +//! @addtogroup clkgen3 Clock Generator (CLKGEN) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_CLKGEN_H +#define AM_HAL_CLKGEN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// +// Designate this peripheral. +// +#define AM_APOLLO3_CLKGEN 1 + +//***************************************************************************** +// +//! @name System Clock max frequency +//! @brief Defines the maximum clock frequency for this device. +//! +//! These macros provide a definition of the maximum clock frequency. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CLKGEN_FREQ_MAX_HZ 48000000 +#define AM_HAL_CLKGEN_FREQ_MAX_KHZ (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000) +#define AM_HAL_CLKGEN_FREQ_MAX_MHZ (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000000) +#define AM_HAL_CLKGEN_CORESEL_MAXDIV 1 +//! @} + +// +// Control operations. +// +typedef enum +{ + AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, + AM_HAL_CLKGEN_CONTROL_XTAL_START, + AM_HAL_CLKGEN_CONTROL_LFRC_START, + AM_HAL_CLKGEN_CONTROL_XTAL_STOP, + AM_HAL_CLKGEN_CONTROL_LFRC_STOP, + AM_HAL_CLKGEN_CONTROL_SYSCLK_DIV2, + AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL, + AM_HAL_CLKGEN_CONTROL_RTC_SEL_LFRC, + AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE, + AM_HAL_CLKGEN_CONTROL_HFADJ_DISABLE, +} am_hal_clkgen_control_e; + +// +// Current RTC oscillator. +// +typedef enum +{ + AM_HAL_CLKGEN_STATUS_RTCOSC_XTAL, + AM_HAL_CLKGEN_STATUS_RTCOSC_LFRC, +} am_hal_clkgen_status_rtcosc_e; + +// +// CLKOUT +// +typedef enum +{ + AM_HAL_CLKGEN_CLKOUT_LFRC_1024 = 0x0, // LFRC + AM_HAL_CLKGEN_CLKOUT_XTAL_16384, // XTAL / 2 + AM_HAL_CLKGEN_CLKOUT_XTAL_8192, // XTAL / 4 + AM_HAL_CLKGEN_CLKOUT_XTAL_4096, // XTAL / 8 + AM_HAL_CLKGEN_CLKOUT_XTAL_2048, // XTAL / 16 + AM_HAL_CLKGEN_CLKOUT_XTAL_1024, // XTAL / 32 + AM_HAL_CLKGEN_CLKOUT_RTC_1HZ = 0x10, // RTC + AM_HAL_CLKGEN_CLKOUT_XTAL_0_015 = 0x16, // XTAL / 2097152 = 0.015625 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_32768, // XTAL + AM_HAL_CLKGEN_CLKOUT_CG_100, // ClkGen 100Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_512 = 0x23, // LFRC / 2 = 512 Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_32, // LFRC / 32 = 32 Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_2, // LFRC / 512 = 2 Hz + AM_HAL_CLKGEN_CLKOUT_LFRC_0_03, // LFRC / 32768 = 0.03125 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_128, // XTAL / 256 = 128 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_4, // XTAL / 8192 = 4 Hz + AM_HAL_CLKGEN_CLKOUT_XTAL_0_5, // XTAL / 65536 = 0.5 Hz + // The next 5 are Uncalibrated LFRC + AM_HAL_CLKGEN_CLKOUT_ULFRC_64, // ULFRC / 16 = 64 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_8, // ULFRC / 128 = 8 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_1, // ULFRC / 1024 = 1 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_0_25, // ULFRC / 4096 = 0.25 Hz (uncal LFRC) + AM_HAL_CLKGEN_CLKOUT_ULFRC_0_0009, // ULFRC / 1M = 0.000976 Hz (uncal LFRC) + // + AM_HAL_CLKGEN_CLKOUT_LFRC_0_0004 = 0x31, // LFRC / 2M = 0.00048828125 Hz + // Following are Not Autoenabled ("NE") + AM_HAL_CLKGEN_CLKOUT_XTALNE_32768 = 0x35, // XTALNE / 1 = 32768 Hz + AM_HAL_CLKGEN_CLKOUT_XTALNE_2048, // XTALNE / 16 = 2048 Hz + AM_HAL_CLKGEN_CLKOUT_LFRCNE_32, // LFRCNE / 32 = 32 Hz + AM_HAL_CLKGEN_CLKOUT_LFRCNE_1024 = 0x39 // LFRCNE / 1 = 1024 Hz +} am_hal_clkgen_clkout_e; + +// +// ClkGen Interrupts +// +typedef enum +{ + AM_HAL_CLKGEN_INTERRUPT_OF = CLKGEN_INTRPTEN_OF_Msk, + AM_HAL_CLKGEN_INTERRUPT_ACC = CLKGEN_INTRPTEN_ACC_Msk, + AM_HAL_CLKGEN_INTERRUPT_ACF = CLKGEN_INTRPTEN_ACF_Msk +} am_hal_clkgen_interrupt_e; + +// +// Status structure. +// +typedef struct +{ + // + // ui32SysclkFreq + // Returns the current system clock frequency, in hertz. + // + uint32_t ui32SysclkFreq; + + // + // ui32RTCoscillator + // + // Returns the current RTC oscillator as one of: + // AM_HAL_CLKGEN_STATUS_RTCOSC_LFRC + // AM_HAL_CLKGEN_STATUS_RTCOSC_XTAL + // + uint32_t eRTCOSC; + + // + // bXtalFailure + // true = XTAL has failed (is enabled but not oscillating). Also if the + // LFRC is selected as the oscillator in OCTRL.OSEL. + // + bool bXtalFailure; +} am_hal_clkgen_status_t; + + +// **************************************************************************** +// +//! @brief Apply various specific commands/controls on the CLKGEN module. +//! +//! This function is used to apply various controls on CLKGEN. +//! +//! @note IMPORTANT! This function MUST be called very early in execution of +//! an application with the parameter AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX +//! in order to set Apollo3 to its required operating frequency. +//! +//! @param eControl - One of the following: +//! AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX +//! AM_HAL_CLKGEN_CONTROL_XTAL_START +//! AM_HAL_CLKGEN_CONTROL_LFRC_START +//! AM_HAL_CLKGEN_CONTROL_XTAL_STOP +//! AM_HAL_CLKGEN_CONTROL_LFRC_STOP +//! AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL +//! AM_HAL_CLKGEN_CONTROL_RTC_SEL_LFRC +//! AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE +//! AM_HAL_CLKGEN_CONTROL_HFADJ_DISABLE +//! +//! @return status - generic or interface specific status. +//! +//! @note After starting the XTAL, a 2 second warm-up delay is required. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_control(am_hal_clkgen_control_e eControl, + void *pArgs); + +// **************************************************************************** +// +//! @brief Get CLKGEN status. +//! +//! This function returns the current value of various CLKGEN statuses. +//! +//! @param psStatus - ptr to a status structure to receive the current statuses. +//! +//! @return status - generic or interface specific status. +//! +//! @note After selection of the RTC Oscillator, a 2 second delay is required +//! before the new oscillator takes effect. Therefore the CLKGEN.STATUS.OMODE +//! bit will not reflect the new status until after the 2s wait period. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_status_get(am_hal_clkgen_status_t *psStatus); + +// **************************************************************************** +// +//! @brief Enable CLKOUT. +//! +//! This function is used to enable and select a CLKOUT frequency. +//! +//! @param bEnable: true to enable, false to disable. +//! @param eClkSelect - One of the following: +//! AM_HAL_CLKGEN_CLKOUT_LFRC_1024 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_16384 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_8192 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_4096 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_2048 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_1024 +//! AM_HAL_CLKGEN_CLKOUT_RTC_1HZ +//! AM_HAL_CLKGEN_CLKOUT_XTAL_0_015 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_32768 +//! AM_HAL_CLKGEN_CLKOUT_CG_100 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_512 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_32 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_2 +//! AM_HAL_CLKGEN_CLKOUT_LFRC_0_03 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_128 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_4 +//! AM_HAL_CLKGEN_CLKOUT_XTAL_0_5 +//! +//! The next 5 are Uncalibrated LFRC +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_64 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_8 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_1 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_0_25 +//! AM_HAL_CLKGEN_CLKOUT_ULFRC_0_0009 +//! +//! AM_HAL_CLKGEN_CLKOUT_LFRC_0_0004 +//! +//! Following are Not Autoenabled ("NE") +//! AM_HAL_CLKGEN_CLKOUT_XTALNE_32768 +//! AM_HAL_CLKGEN_CLKOUT_XTALNE_2048 +//! AM_HAL_CLKGEN_CLKOUT_LFRCNE_32 +//! AM_HAL_CLKGEN_CLKOUT_LFRCNE_1024 +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_clkout_enable(bool bEnable, + am_hal_clkgen_clkout_e eClkSelect); + +// **************************************************************************** +// +//! @brief Enable selected CLKGEN Interrupts. +//! +//! Use this function to enable the interrupts. +//! +//! @param ui32IntMask - One or more of the following bitmasks. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_enable(am_hal_clkgen_interrupt_e ui32IntMask); + +// **************************************************************************** +// +//! @brief Disable selected CLKGEN Interrupts. +//! +//! Use this function to disable the CLKGEN interrupts. +//! +//! @param ui32IntMask - One or more of the following bitmasks. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_disable(am_hal_clkgen_interrupt_e ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM interrupt clear +//! +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function clears the interrupts for the given peripheral. +//! +//! The following are valid clear bits, any of which can be ORed together. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_clear(am_hal_clkgen_interrupt_e ui32IntMask); + +// **************************************************************************** +// +//! @brief Return CLKGEN interrupts. +//! +//! Use this function to get all CLKGEN interrupts, or only the interrupts +//! that are enabled. +//! +//! @return All or only enabled CLKGEN interrupts. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus); + +// **************************************************************************** +// +//! @brief Sets the interrupt status. +//! +//! This function sets the CLKGEN interrupts. +//! +//! @param ui32IntMask - One or more of the following bitmasks. +//! AM_HAL_CLKGEN_INTERRUPT_OF +//! AM_HAL_CLKGEN_INTERRUPT_ACC +//! AM_HAL_CLKGEN_INTERRUPT_ACF +//! +//! @return None. +// +// **************************************************************************** +extern uint32_t am_hal_clkgen_interrupt_set(am_hal_clkgen_interrupt_e ui32IntMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CLKGEN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.c new file mode 100644 index 0000000000..487e75dd03 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.c @@ -0,0 +1,848 @@ +//***************************************************************************** +// +// am_hal_cmdq.c +//! @file +//! +//! @brief Functions for support command queue operations. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +#define AM_HAL_MAGIC_CMDQ 0xCDCDCD +#define AM_HAL_CMDQ_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_CMDQ)) + +// Make sure certain register assumptions are valid - else throw compile error +// Make sure the max HWIDX value is same for BLEIF, MSPI & IOM +// Make sure the CQCFG structure is same for BLEIF, MSPI & IOM +#if ((IOM0_CQCURIDX_CQCURIDX_Msk != MSPI_CQCURIDX_CQCURIDX_Msk) || \ + (IOM0_CQCURIDX_CQCURIDX_Pos != MSPI_CQCURIDX_CQCURIDX_Pos) || \ + (IOM0_CQCFG_CQEN_Pos != MSPI_CQCFG_CQEN_Pos) || \ + (IOM0_CQCFG_CQEN_Msk != MSPI_CQCFG_CQEN_Msk) || \ + (IOM0_CQCFG_CQPRI_Pos != MSPI_CQCFG_CQPRI_Pos) || \ + (IOM0_CQCFG_CQPRI_Msk != MSPI_CQCFG_CQPRI_Msk) || \ + (IOM0_CQCURIDX_CQCURIDX_Msk != BLEIF_CQCURIDX_CQCURIDX_Msk) || \ + (IOM0_CQCURIDX_CQCURIDX_Pos != BLEIF_CQCURIDX_CQCURIDX_Pos) || \ + (IOM0_CQCFG_CQEN_Pos != BLEIF_CQCFG_CQEN_Pos) || \ + (IOM0_CQCFG_CQEN_Msk != BLEIF_CQCFG_CQEN_Msk) || \ + (IOM0_CQCFG_CQPRI_Pos != BLEIF_CQCFG_CQPRI_Pos) || \ + (IOM0_CQCFG_CQPRI_Msk != BLEIF_CQCFG_CQPRI_Msk) \ + ) +#error "MSPI and IOM HWIDX, CQCFG implementation needs to match for current CMDQ HAL implementation" +#endif + +#define AM_HAL_CMDQ_HW_IDX_MAX (IOM0_CQCURIDX_CQCURIDX_Msk >> IOM0_CQCURIDX_CQCURIDX_Pos) // 8 bit value +#define AM_HAL_CMDQ_ENABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) |= _VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN); } +#define AM_HAL_CMDQ_DISABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) &= ~_VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN); } +#define AM_HAL_CMDQ_INIT_CQCFG(cfgReg, pri, enable) {AM_REGVAL((cfgReg)) = _VAL2FLD(IOM0_CQCFG_CQPRI, (pri)) | _VAL2FLD(IOM0_CQCFG_CQEN, (enable)); } + + +// Need to set the lsb of the CQ entry address for hardware to raise a CQUPD interrupt when processing this entry +#define AM_HAL_CMDQ_ENABLE_CQUPD_INT 0x1 + +typedef struct +{ + volatile uint32_t* regCQCfg; + volatile uint32_t* regCQAddr; + volatile uint32_t* regCurIdx; + volatile uint32_t* regEndIdx; + volatile uint32_t* regCQPause; + uint32_t bitMaskCQPauseIdx; + volatile uint32_t* regCQStat; + + // Different hardware blocks have different bit assignments for status flags + uint32_t bitMaskCQStatTIP; + uint32_t bitMaskCQStatErr; + uint32_t bitMaskCQStatPaused; +} am_hal_cmdq_registers_t; + +typedef struct +{ + am_hal_handle_prefix_t prefix; + uint32_t cmdQBufStart; + uint32_t cmdQBufEnd; + uint32_t cmdQHead; + uint32_t cmdQTail; + uint32_t cmdQNextTail; + uint32_t cmdQSize; + uint32_t curIdx; + uint32_t endIdx; + const am_hal_cmdq_registers_t *pReg; + uint32_t rawSeqStart; +} am_hal_cmdq_t; + +// Global variables +static am_hal_cmdq_t gAmHalCmdq[AM_HAL_CMDQ_IF_MAX]; + +static const am_hal_cmdq_registers_t gAmHalCmdQReg[AM_HAL_CMDQ_IF_MAX] = +{ + // AM_HAL_CMDQ_IF_IOM0 + { + &IOM0->CQCFG, &IOM0->CQADDR, + &IOM0->CQCURIDX, &IOM0->CQENDIDX, + &IOM0->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM0->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM1 + { + &IOM1->CQCFG, &IOM1->CQADDR, + &IOM1->CQCURIDX, &IOM1->CQENDIDX, + &IOM1->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM1->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM2 + { + &IOM2->CQCFG, &IOM2->CQADDR, + &IOM2->CQCURIDX, &IOM2->CQENDIDX, + &IOM2->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM2->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM3 + { + &IOM3->CQCFG, &IOM3->CQADDR, + &IOM3->CQCURIDX, &IOM3->CQENDIDX, + &IOM3->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM3->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM4 + { + &IOM4->CQCFG, &IOM4->CQADDR, + &IOM4->CQCURIDX, &IOM4->CQENDIDX, + &IOM4->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM4->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_IOM5 + { + &IOM5->CQCFG, &IOM5->CQADDR, + &IOM5->CQCURIDX, &IOM5->CQENDIDX, + &IOM5->CQPAUSEEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ, + &IOM5->CQSTAT, IOM0_CQSTAT_CQTIP_Msk, + IOM0_CQSTAT_CQERR_Msk, IOM0_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_MSPI + { + &MSPI->CQCFG, &MSPI->CQADDR, + &MSPI->CQCURIDX, &MSPI->CQENDIDX, + &MSPI->CQPAUSE, MSPI_CQPAUSE_CQMASK_CQIDX, + &MSPI->CQSTAT, MSPI_CQSTAT_CQTIP_Msk, + MSPI_CQSTAT_CQERR_Msk, MSPI_CQSTAT_CQPAUSED_Msk + }, + // AM_HAL_CMDQ_IF_BLEIF + { + &BLEIF->CQCFG, &BLEIF->CQADDR, + &BLEIF->CQCURIDX, &BLEIF->CQENDIDX, + &BLEIF->CQPAUSEEN, BLEIF_CQPAUSEEN_CQPEN_CNTEQ, + &BLEIF->CQSTAT, BLEIF_CQSTAT_CQTIP_Msk, + BLEIF_CQSTAT_CQERR_Msk, BLEIF_CQSTAT_CQPAUSED_Msk + }, +}; + +// Sync up with the current hardware indices and pointers +static void +update_indices(am_hal_cmdq_t *pCmdQ) +{ + int32_t hwCurIdx; + + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + hwCurIdx = AM_REGVAL(pCmdQ->pReg->regCurIdx) & AM_HAL_CMDQ_HW_IDX_MAX; + + // Derive the 32b values from the current hardware index values + // It is guaranteed that pCmdQ->endIdx is <= pCmdQ->curIdx + AM_HAL_CMDQ_HW_IDX_MAX - 1 + pCmdQ->curIdx = (pCmdQ->endIdx & ~AM_HAL_CMDQ_HW_IDX_MAX) | hwCurIdx; + if (AM_HAL_U32_SMALLER(pCmdQ->endIdx, pCmdQ->curIdx)) + { + pCmdQ->curIdx -= (AM_HAL_CMDQ_HW_IDX_MAX + 1); + } + pCmdQ->cmdQHead = AM_REGVAL(pCmdQ->pReg->regCQAddr); + + // + // End the critical section. + // + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Initialize a Command Queue +//! +//! Initializes the command queue data structure for the given interface +//! +//! @param hwIf identifies the underlying hardware interface +//! @param cmdQSize Size of supplied memory in multiple of 8 Bytes +//! @param pCmdQBuf Command Queue Buffer +//! @param ppHandle Return Parameter - handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_init(am_hal_cmdq_if_e hwIf, am_hal_cmdq_cfg_t *pCfg, void **ppHandle) +{ + am_hal_cmdq_t *pCmdQ; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (hwIf >= AM_HAL_CMDQ_IF_MAX) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + if (!pCfg || !pCfg->pCmdQBuf || !ppHandle || (pCfg->cmdQSize < 2)) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (gAmHalCmdq[hwIf].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + pCmdQ = &gAmHalCmdq[hwIf]; + pCmdQ->cmdQSize = pCfg->cmdQSize * sizeof(am_hal_cmdq_entry_t); + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = pCmdQ->cmdQHead = pCmdQ->cmdQBufStart = (uint32_t)pCfg->pCmdQBuf; + pCmdQ->cmdQBufEnd = (uint32_t)pCfg->pCmdQBuf + pCfg->cmdQSize * sizeof(am_hal_cmdq_entry_t); + pCmdQ->prefix.s.bInit = true; + pCmdQ->prefix.s.bEnable = false; + pCmdQ->prefix.s.magic = AM_HAL_MAGIC_CMDQ; + pCmdQ->pReg = &gAmHalCmdQReg[hwIf]; + pCmdQ->curIdx = 0; + pCmdQ->endIdx = 0; + AM_REGVAL(pCmdQ->pReg->regCurIdx) = 0; + AM_REGVAL(pCmdQ->pReg->regEndIdx) = 0; + AM_REGVAL(pCmdQ->pReg->regCQPause) |= pCmdQ->pReg->bitMaskCQPauseIdx; + // Initialize the hardware registers + AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCfg->pCmdQBuf; + AM_HAL_CMDQ_INIT_CQCFG(pCmdQ->pReg->regCQCfg, pCfg->priority, false); + *ppHandle = pCmdQ; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Enable a Command Queue +//! +//! Enables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_enable(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + AM_HAL_CMDQ_ENABLE_CQ(pCmdQ->pReg->regCQCfg); + pCmdQ->prefix.s.bEnable = true; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Disable a Command Queue +//! +//! Disables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_disable(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + pCmdQ->prefix.s.bEnable = false; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Allocate a block of commands for posting to a command queue +//! +//! Allocates a contiguous block of command queue entries from the available +//! space in command queue +//! +//! @param pHandle handle for the command queue +//! @param numCmd Size of the command block (each block being 8 bytes) +//! @param ppBlock - Return parameter - Pointer to contiguous block of commands, +//! which can be posted +//! @param pIdx - Return parameter - monotonically increasing transaction index +//! +//! This function will take care of determining that enough space is available +//! to create the desired block. It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_alloc_block(void *pHandle, uint32_t numCmd, am_hal_cmdq_entry_t **ppBlock, uint32_t *pIdx) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCmdQEntry; + uint32_t blockAddr; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!ppBlock || !pIdx) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pCmdQ->cmdQTail != pCmdQ->cmdQNextTail) + { + // Previously allocated block has not been posted/aborted yet + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + update_indices(pCmdQ); + // We need to not use the hwIdx completely, as otherwise we can not distinguish between + // Empty and full case + if (AM_HAL_U32_SMALLER((pCmdQ->curIdx + AM_HAL_CMDQ_HW_IDX_MAX - 1), (pCmdQ->endIdx))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + // Determine if we can allocate the block, and if so, where + if (pCmdQ->cmdQTail >= pCmdQ->cmdQHead) + { + // Choices: Following last block if there is enough space before wrap + // Otherwise, need to allocate block from the top of the memory + // For a sequence - we'll always come to this case, as the sequence is not started before building + + // Need space for 2 more entries - one for updating curIdx, other for CQ Wrap + if ((pCmdQ->cmdQTail + (numCmd + 2)*sizeof(am_hal_cmdq_entry_t)) <= pCmdQ->cmdQBufEnd) + { + // Enough space in the queue without wrap + blockAddr = pCmdQ->cmdQTail; + } + else + { + // Need to wrap + // Need space for 1 more entry - for updating curIdx + if ((pCmdQ->cmdQBufStart + (numCmd + 1) * sizeof(am_hal_cmdq_entry_t)) < pCmdQ->cmdQHead) + { + // Initialize the tail of CmdQ for Wrap + pCmdQEntry = (am_hal_cmdq_entry_t *)pCmdQ->cmdQTail; + pCmdQEntry->address = (uint32_t)pCmdQ->pReg->regCQAddr; + pCmdQEntry->value = pCmdQ->cmdQBufStart; + blockAddr = pCmdQ->cmdQBufStart; + } + else + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + } + } + else + { + // Need space for 1 more entry - for updating curIdx + if ((pCmdQ->cmdQTail + (numCmd + 1) * sizeof(am_hal_cmdq_entry_t)) < pCmdQ->cmdQHead) + { + blockAddr = pCmdQ->cmdQTail; + } + else + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + } + *ppBlock = (am_hal_cmdq_entry_t *)blockAddr; + *pIdx = ++pCmdQ->endIdx; + pCmdQ->cmdQNextTail = blockAddr + numCmd * sizeof(am_hal_cmdq_entry_t); + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Release a block of commands previously allocated +//! +//! Releases the contiguous block of command queue entries previously allocated +//! without posting +//! +//! @param pHandle handle for the command queue +//! +//! This function will internally handles the curIdx/endIdx manipulation. +//! It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_release_block(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->cmdQTail == pCmdQ->cmdQNextTail) + { + // No block has been allocated + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // Free up the block + pCmdQ->cmdQNextTail = pCmdQ->cmdQTail; + pCmdQ->endIdx--; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Post the last block allocated +//! +//! Post the contiguous block of command queue entries previously allocated +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_block(void *pHandle, bool bInt) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCmdQEntry; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->cmdQTail == pCmdQ->cmdQNextTail) + { + // No block has been allocated + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // CmdQ entries have already been populated. Just need to inform hardware of the new endIdx + // Fill up the index update entry + pCmdQEntry = (am_hal_cmdq_entry_t *)pCmdQ->cmdQNextTail; + pCmdQEntry->address = ((uint32_t)pCmdQ->pReg->regCurIdx) | (bInt ? AM_HAL_CMDQ_ENABLE_CQUPD_INT : 0); + pCmdQEntry->value = pCmdQ->endIdx; + // cmdQNextTail should now point to the first entry after the allocated block + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = (uint32_t)(pCmdQEntry + 1); + AM_REGVAL(pCmdQ->pReg->regEndIdx) = pCmdQ->endIdx & AM_HAL_CMDQ_HW_IDX_MAX; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Get Command Queue status +//! +//! Get the current state of the Command queue +//! +//! @param pHandle handle for the command queue +//! @param pStatus Return Parameter - status information +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_get_status(void *pHandle, am_hal_cmdq_status_t *pStatus) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + uint32_t status; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pStatus) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + update_indices(pCmdQ); + pStatus->lastIdxProcessed = pCmdQ->curIdx; + pStatus->lastIdxAllocated = pCmdQ->endIdx; + pStatus->lastIdxPosted = pCmdQ->endIdx - ((pCmdQ->cmdQNextTail == pCmdQ->cmdQTail) ? 0 : 1); + status = AM_REGVAL(pCmdQ->pReg->regCQStat); + pStatus->bTIP = status & pCmdQ->pReg->bitMaskCQStatTIP; + pStatus->bPaused = status & pCmdQ->pReg->bitMaskCQStatPaused; + pStatus->bErr = status & pCmdQ->pReg->bitMaskCQStatErr; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Terminate a Command Queue +//! +//! Terminates the command queue data structure +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_term(void *pHandle, bool bForce) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + update_indices(pCmdQ); + if (!bForce && (pCmdQ->curIdx != pCmdQ->endIdx)) + { + return AM_HAL_STATUS_IN_USE; + } + pCmdQ->prefix.s.bInit = false; + // Disable Command Queue + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + AM_REGVAL(pCmdQ->pReg->regCQPause) &= ~pCmdQ->pReg->bitMaskCQPauseIdx; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Clear the CQ error and resume with the next transaction. +//! The CQ is left disabled after this call +//! It is the responsibility of the caller to re-enable the CQ +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_error_resume(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCQAddr; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (!pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // First Disable the Command Queue + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + + // Need to identify end of block for the transaction where hardware is stuck + // Move the CQADDR to the last entry in the block which will update the curIdx + // and then move on. + pCQAddr = (am_hal_cmdq_entry_t *)AM_REGVAL(pCmdQ->pReg->regCQAddr); + while ((pCQAddr->address & ~AM_HAL_CMDQ_ENABLE_CQUPD_INT) != (uint32_t)(pCmdQ->pReg->regCurIdx)) + { + // Is this element changing the CQ Address itself? + if (pCQAddr->address == (uint32_t)(pCmdQ->pReg->regCQAddr)) + { + pCQAddr = (am_hal_cmdq_entry_t *)pCQAddr->value; + } + else + { + ++pCQAddr; + } + } + + // The pCQAddr now points to the address of the command which will update the curIdx + // Disable update interrupt, as we would have already handled this error + *(&pCQAddr->address) = (uint32_t)pCmdQ->pReg->regCurIdx; + AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCQAddr; + + pCmdQ->prefix.s.bEnable = false; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Pause the CQ after finishing the current transaction. +//! The CQ is in paused state after this function returns, at the beginning of next transaction +//! +//! @param pHandle handle for the command queue +//! @param pSETCLRAddr Points to the SETCLR register for the module +//! @param ui32CQPauseSETCLR Value to be written to Pause the CQ +//! @param ui32CQUnpauseSETCLR Value to be written to unpause the CQ +//! @param ui32usMaxDelay Max time to wait (in uS) +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_pause(void *pHandle, uint32_t *pSETCLRAddr, uint32_t ui32CQPauseSETCLR, uint32_t ui32CQUnpauseSETCLR, uint32_t ui32usMaxDelay) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + uint32_t cqAddr; + am_hal_cmdq_entry_t *pCQAddr; + am_hal_cmdq_entry_t cqEntry; + uint32_t status = AM_HAL_STATUS_SUCCESS; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (!pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // First Pause the Command Queue + *pSETCLRAddr = ui32CQPauseSETCLR; + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + // Now seek for the end of current transaction + cqAddr = AM_REGVAL(pCmdQ->pReg->regCQAddr); + if (cqAddr == pCmdQ->cmdQNextTail) + { + // Already at the end + // No need to do anything else + } + else + { + // Need to identify end of block for the transaction + pCQAddr = (am_hal_cmdq_entry_t *)cqAddr; + while ((pCQAddr->address & ~AM_HAL_CMDQ_ENABLE_CQUPD_INT) != (uint32_t)(pCmdQ->pReg->regCurIdx)) + { + if ( (uint32_t) ++pCQAddr >= pCmdQ->cmdQBufEnd ) + { + // This should not happen + return AM_HAL_STATUS_FAIL; + } + } + + // The pCQAddr now points to the address of the command which will update the curIdx + // We need to resume the CQ till it finishes this entry + // For that we'll temporarily replace the next entry to cause a Pause + // Backup the current content + cqEntry = *(++pCQAddr); + pCQAddr->address = (uint32_t)pSETCLRAddr; + pCQAddr->value = ui32CQPauseSETCLR; + // Wait for it to execute this new entry, or get paused for some other condition + do + { + // Resume the CQ + *pSETCLRAddr = ui32CQUnpauseSETCLR; + // Ensure CQ sees it + am_hal_flash_delay(3); + // Now wait for it to be paused again + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + // Try Setting the PAUSE condition while in same position + *pSETCLRAddr = ui32CQPauseSETCLR; + // Ensure CQ sees it + am_hal_flash_delay(3); + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + if (cqAddr == AM_REGVAL(pCmdQ->pReg->regCQAddr)) + { + // CQ no longer moving + break; + } + else + { + cqAddr = AM_REGVAL(pCmdQ->pReg->regCQAddr); + } +#if 0 + // Now that it is paused - check if we have reached our entry - or it paused somewhere else + cqAddr = AM_REGVAL(pCmdQ->pReg->regCQAddr); + if (cqAddr != (uint32_t)(pCQAddr + 1)) + { + // It paused due to some other reason + // Try Setting the PAUSE condition while in same position + *pSETCLRAddr = ui32CQPauseSETCLR; + // Ensure CQ sees it + am_hal_flash_delay(3); + status = am_hal_flash_delay_status_change(ui32usMaxDelay, (uint32_t)pCmdQ->pReg->regCQStat, pCmdQ->pReg->bitMaskCQStatPaused, pCmdQ->pReg->bitMaskCQStatPaused); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + if (AM_REGVAL(pCmdQ->pReg->regCQAddr) == cqAddr) + { + // CQ did not move after we set the PAUSE - so it is at a designated pause place + // Safe to return now + break; + } + else + { + // CQ is moving...need to retry + } + } + else + { + // Reached the desired place + break; + } +#endif + } while(1); + // Now let's revert the CQ content and set the CQADDR to correct place for it to resume later + // when the CQ is unpaused + *pCQAddr = cqEntry; + if (AM_REGVAL(pCmdQ->pReg->regCQAddr) == (uint32_t)(pCQAddr + 1)) + { + AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCQAddr; + } + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Reset the Command Queue +//! +//! Reset the Command Queue & associated data structures +//! This will force the CQ reset +//! Caller needs to ensure CQ is in steady state before this is done +//! This also disables the CQ +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_reset(void *pHandle) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + AM_HAL_CMDQ_DISABLE_CQ(pCmdQ->pReg->regCQCfg); + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = pCmdQ->cmdQHead = pCmdQ->cmdQBufStart; + pCmdQ->curIdx = 0; + pCmdQ->endIdx = 0; + AM_REGVAL(pCmdQ->pReg->regCurIdx) = 0; + AM_REGVAL(pCmdQ->pReg->regEndIdx) = 0; + // Initialize the hardware registers + AM_REGVAL(pCmdQ->pReg->regCQAddr) = pCmdQ->cmdQBufStart; + pCmdQ->prefix.s.bEnable = false; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Post the last block allocated with the additional wrap to start +//! +//! Post the contiguous block of command queue entries previously allocated +//! with the additional wrap to start +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_loop_block(void *pHandle, bool bInt) +{ + am_hal_cmdq_t *pCmdQ = (am_hal_cmdq_t *)pHandle; + am_hal_cmdq_entry_t *pCmdQEntry; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_CMDQ_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (pCmdQ->cmdQTail == pCmdQ->cmdQNextTail) + { + // No block has been allocated + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // CmdQ entries have already been populated. Just need to inform hardware of the new endIdx + // Reset the index to 0 + pCmdQEntry = (am_hal_cmdq_entry_t *)pCmdQ->cmdQNextTail; + pCmdQEntry->address = (uint32_t)pCmdQ->pReg->regCurIdx; + pCmdQEntry->value = 0; + pCmdQEntry++; + // Fill up the loopback entry + // At the alloc time, we were guaranteed one extra entry for loopback + pCmdQEntry->address = (uint32_t)pCmdQ->pReg->regCQAddr | (bInt ? AM_HAL_CMDQ_ENABLE_CQUPD_INT : 0); + pCmdQEntry->value = pCmdQ->cmdQBufStart; + // cmdQNextTail should now point to the first entry after the allocated block + pCmdQ->cmdQTail = pCmdQ->cmdQNextTail = (uint32_t)(pCmdQEntry + 1); + // Since we are not updating the curIdx - this will cause CQ to run indefinetely + AM_REGVAL(pCmdQ->pReg->regEndIdx) = pCmdQ->endIdx & AM_HAL_CMDQ_HW_IDX_MAX; + return AM_HAL_STATUS_SUCCESS; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.h new file mode 100644 index 0000000000..6e697cde6d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_cmdq.h @@ -0,0 +1,293 @@ +//***************************************************************************** +// +// am_hal_cmdq.h +//! @file +//! +//! @brief Functions for support command queue operations. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_CMDQ_H +#define AM_HAL_CMDQ_H + +// Identification for underlying hardware interface +typedef enum +{ + AM_HAL_CMDQ_IF_IOM0, + AM_HAL_CMDQ_IF_IOM1, + AM_HAL_CMDQ_IF_IOM2, + AM_HAL_CMDQ_IF_IOM3, + AM_HAL_CMDQ_IF_IOM4, + AM_HAL_CMDQ_IF_IOM5, + AM_HAL_CMDQ_IF_MSPI, + AM_HAL_CMDQ_IF_BLEIF, + AM_HAL_CMDQ_IF_MAX, +} am_hal_cmdq_if_e; + +typedef enum +{ + AM_HAL_CMDQ_PRIO_LOW, + AM_HAL_CMDQ_PRIO_HI, +} am_hal_cmdq_priority_e; + +typedef struct +{ + uint32_t cmdQSize; + uint32_t *pCmdQBuf; + am_hal_cmdq_priority_e priority; +} am_hal_cmdq_cfg_t; + +typedef struct +{ + uint32_t address; + uint32_t value; +} am_hal_cmdq_entry_t; + +typedef struct +{ + uint32_t lastIdxProcessed; + uint32_t lastIdxPosted; + uint32_t lastIdxAllocated; + bool bTIP; + bool bPaused; + bool bErr; +} am_hal_cmdq_status_t; + + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief Initialize a Command Queue +//! +//! Initializes the command queue data structure for the given interface +//! +//! @param hwIf identifies the underlying hardware interface +//! @param cmdQSize Size of supplied memory in multiple of 8 Bytes +//! @param pCmdQBuf Command Queue Buffer +//! @param ppHandle Return Parameter - handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_init(am_hal_cmdq_if_e hwIf, am_hal_cmdq_cfg_t *pCfg, void **ppHandle); + + +//***************************************************************************** +// +//! @brief Enable a Command Queue +//! +//! Enables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_enable(void *pHandle); + +//***************************************************************************** +// +//! @brief Disable a Command Queue +//! +//! Disables the command queue for the given interface +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_disable(void *pHandle); + +//***************************************************************************** +// +//! @brief Allocate a block of commands for posting to a command queue +//! +//! Allocates a contiguous block of command queue entries from the available +//! space in command queue +//! +//! @param pHandle handle for the command queue +//! @param numCmd Size of the command block (each block being 8 bytes) +//! @param ppBlock - Return parameter - Pointer to contiguous block of commands, +//! which can be posted +//! @param pIdx - Return parameter - monotonically increasing transaction index +//! +//! This function will take care of determining that enough space is available +//! to create the desired block. It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_alloc_block(void *pHandle, uint32_t numCmd, am_hal_cmdq_entry_t **ppBlock, uint32_t *pIdx); + +//***************************************************************************** +// +//! @brief Release a block of commands previously allocated +//! +//! Releases the contiguous block of command queue entries previously allocated +//! without posting +//! +//! @param pHandle handle for the command queue +//! +//! This function will internally handles the curIdx/endIdx manipulation. +//! It also takes care of necessary wrap-around +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_release_block(void *pHandle); + +//***************************************************************************** +// +//! @brief Post the last block allocated +//! +//! Post the contiguous block of command queue entries previously allocated +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_block(void *pHandle, bool bInt); + +//***************************************************************************** +// +//! @brief Get Command Queue status +//! +//! Get the current state of the Command queue +//! +//! @param pHandle handle for the command queue +//! @param pStatus Return Parameter - status information +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_get_status(void *pHandle, am_hal_cmdq_status_t *pStatus); + +//***************************************************************************** +// +//! @brief Terminate a Command Queue +//! +//! Terminates the command queue data structure +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_term(void *pHandle, bool bForce); + + +//***************************************************************************** +// +//! @brief Clear the CQ error and resume with the next transaction. +//! +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_error_resume(void *pHandle); + +//***************************************************************************** +// +//! @brief Pause the CQ after finishing the current transaction. +//! The CQ is in paused state after this function returns, at the beginning of next transaction +//! +//! @param pHandle handle for the command queue +//! @param pSETCLRAddr Points to the SETCLR register for the module +//! @param ui32CQPauseSETCLR Value to be written to Pause the CQ +//! @param ui32CQUnpauseSETCLR Value to be written to unpause the CQ +//! @param ui32usMaxDelay Max time to wait (in uS) +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_pause(void *pHandle, uint32_t *pSETCLRAddr, + uint32_t ui32CQPauseSETCLR, + uint32_t ui32CQUnpauseSETCLR, uint32_t ui32usMaxDelay); + +//***************************************************************************** +// +//! @brief Reset the Command Queue +//! +//! Reset the Command Queue & associated data structures +//! This will force the CQ reset +//! Caller needs to ensure CQ is in steady state before this is done +//! This also disables the CQ +//! +//! @param pHandle handle for the command queue +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_reset(void *pHandle); + +//***************************************************************************** +// +//! @brief Post the last block allocated with the additional wrap to start +//! +//! Post the contiguous block of command queue entries previously allocated +//! with the additional wrap to start +//! +//! @param pHandle handle for the command queue +//! @param bInt Whether the UPD interrupt is desired once the block is processed +//! +//! @return Returns 0 on success +// +//***************************************************************************** +uint32_t am_hal_cmdq_post_loop_block(void *pHandle, bool bInt); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CMDQ_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.c new file mode 100644 index 0000000000..4798503bb0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.c @@ -0,0 +1,2294 @@ +//***************************************************************************** +// +// am_hal_ctimer.c +//! @file +//! +//! @brief Functions for interfacing with the Counter/Timer module. +//! +//! @addtogroup ctimer3 Counter/Timer (CTIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Adjacency check +// +// This is related to the timer read workaround. This macro checks to see if +// the two supplied count values are within one "tick" of eachother. It should +// still pass in the event of a timer rollover. +// +//***************************************************************************** +//! Timer read workaround: Do count values differ by one tick or less. +#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) + +//***************************************************************************** +// +//! Array of function pointers for handling CTimer interrupts. +// +//***************************************************************************** +static am_hal_ctimer_handler_t g_am_hal_ctimer_ppfnHandlers[32]; + +// +// Store the timer clock source value depending on segment. +// Getting the source clock everytime from the CTRL register will incur bus +// latency. This table is maintained to minimize the read latency when +// attempting to retrieve the CLKSRC. +// CLKSRC is 5 bits, so uint8_t is adequate for the table. +// +static uint8_t +g_ui8ClkSrc[AM_HAL_CTIMER_TIMERS_NUM][2] = +{ + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF} +}; + +// +// Table of TMR register addresses. +// +static const uint32_t +g_ui32TMRAddrTbl[AM_HAL_CTIMER_TIMERS_NUM] = +{ + AM_REGADDR(CTIMER,TMR0), AM_REGADDR(CTIMER,TMR1), AM_REGADDR(CTIMER,TMR2), + AM_REGADDR(CTIMER,TMR3), AM_REGADDR(CTIMER,TMR4), AM_REGADDR(CTIMER,TMR5), + AM_REGADDR(CTIMER,TMR6), AM_REGADDR(CTIMER,TMR7) +}; + +// +// Given the 5-bit clock source value as an index, this lookup table returns the +// number of LSbs to be masked off for the back2back reads. +// +static const uint8_t +g_ui8TmrClkSrcMask[32] = // 5-bit field = 32 table entries +{ + 0x0F, // 0: CTIMER_CTRL0_TMRA0CLK_TMRPIN (CLK_PIN) + 0x0F, // 1: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 (HFRC_12MHZ) + 0x03, // 2: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 (HFRC_3MHZ) + 0x01, // 3: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 (HFRC_187_5KHZ) + 0x01, // 4: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 (HFRC_47KHZ) + 0x01, // 5: CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K (HFRC_12KHZ) + 0x00, // 6: CTIMER_CTRL0_TMRA0CLK_XT (XT_32_768KHZ) + 0x00, // 7: CTIMER_CTRL0_TMRA0CLK_XT_DIV2 (XT_16_384KHZ) + 0x00, // 8: CTIMER_CTRL0_TMRA0CLK_XT_DIV16 (XT_2_048KHZ) + 0x00, // 9: CTIMER_CTRL0_TMRA0CLK_XT_DIV128 (XT_256HZ) + 0x00, // 10: CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 (LFRC_512HZ) + 0x00, // 11: CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 (LFRC_32HZ) + 0x00, // 12: CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K (LFRC_1HZ) + 0x00, // 13: CTIMER_CTRL0_TMRA0CLK_LFRC (LFRC_1_16HZ) + 0x00, // 14: CTIMER_CTRL0_TMRA0CLK_RTC_100HZ (RTC_100HZ) + 0x00, // 15: CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 (HCLK_DIV4) + 0x00, // 16: CTIMER_CTRL0_TMRA0CLK_XT_DIV4 (XT_DIV4) + 0x00, // 17: CTIMER_CTRL0_TMRA0CLK_XT_DIV8 (XT_DIV8) + 0x00, // 18: CTIMER_CTRL0_TMRA0CLK_XT_DIV32 (XT_DIV32) + 0x00, // 19: Reserved + 0x0F, // 20: CTIMERxx OUT + 0x0F, // 21: " + 0x0F, // 22: " + 0x0F, // 23: " + 0x0F, // 24: " + 0x0F, // 25: " + 0x0F, // 26: " + 0x0F, // 27: " + 0x0F, // 28: " + 0x00, // 29: CTIMER_CTRL0_TMRA0CLK_BUCKBLE + 0x00, // 30: CTIMER_CTRL0_TMRA0CLK_BUCKB + 0x00 // 31: CTIMER_CTRL0_TMRA0CLK_BUCKA +}; + +//***************************************************************************** +// +// Lookup tables used by am_hal_ctimer_output_config(). +// +// CTx_tbl[] relates the padnum and pad funcsel based on a given CTx. +// Valid pads for CTx are: 4-7, 11-13, 18-19, 22-33, 35, 37, 39, 42-49. +// +// outcfg_tbl[] contains attributes of the 4 output signal types for each +// of the 32 CTx signals. Therefore it is indexed by CTnumber 0-31. +// This table provides only the non-common OUTCFG attributes (2-5, other +// settings are shown below). +// OUTCFG 0 = Force output to 0. +// OUTCFG 1 = Force output to 1. +// OUTCFG 6 = A6OUT2. +// OUTCFG 7 = A7OUT2. +// +//***************************************************************************** +#define CTXPADNUM(ctx) ((CTx_tbl[ctx] >> 0) & 0x3f) +#define CTXPADFNC(ctx) ((CTx_tbl[ctx] >> 8) & 0x7) +#define CTX(pad, fn) ((fn << 8) | (pad << 0)) +static const uint16_t CTx_tbl[32] = +{ + CTX(12,2), CTX(25,2), CTX(13,2), CTX(26,2), CTX(18,2), // 0 - 4 + CTX(27,2), CTX(19,2), CTX(28,2), CTX( 5,7), CTX(29,2), // 5 - 9 + CTX( 6,5), CTX(30,2), CTX(22,2), CTX(31,2), CTX(23,2), // 10 - 14 + CTX(32,2), CTX(42,2), CTX( 4,6), CTX(43,2), CTX( 7,7), // 15 - 19 + CTX(44,2), CTX(24,5), CTX(45,2), CTX(33,6), CTX(46,2), // 20 - 24 + CTX(39,2), CTX(47,2), CTX(35,5), CTX(48,2), CTX(37,7), // 25 - 29 + CTX(49,2), CTX(11,2) // 30 - 31 +}; + +#define OUTC(timB,timN,N2) ((N2 << 4) | (timB << 3) | (timN << 0)) +#define OUTCTIMN(ctx,n) (outcfg_tbl[ctx][n] & (0x7 << 0)) +#define OUTCTIMB(ctx,n) (outcfg_tbl[ctx][n] & (0x1 << 3)) +#define OUTCO2(ctx,n) (outcfg_tbl[ctx][n] & (0x1 << 4)) +static const uint8_t outcfg_tbl[32][4] = +{ + {OUTC(0,0,0), OUTC(1,2,1), OUTC(0,5,1), OUTC(0,6,0)}, // CTX0: A0OUT, B2OUT2, A5OUT2, A6OUT + {OUTC(0,0,1), OUTC(0,0,0), OUTC(0,5,0), OUTC(1,7,1)}, // CTX1: A0OUT2, A0OUT, A5OUT, B7OUT2 + {OUTC(1,0,0), OUTC(1,1,1), OUTC(1,6,1), OUTC(0,7,0)}, // CTX2: B0OUT, B1OUT2, B6OUT2, A7OUT + {OUTC(1,0,1), OUTC(1,0,0), OUTC(0,1,0), OUTC(0,6,0)}, // CTX3: B0OUT2, B0OUT, A1OUT, A6OUT + {OUTC(0,1,0), OUTC(0,2,1), OUTC(0,5,1), OUTC(1,5,0)}, // CTX4: A1OUT, A2OUT2, A5OUT2, B5OUT + {OUTC(0,1,1), OUTC(0,1,0), OUTC(1,6,0), OUTC(0,7,0)}, // CTX5: A1OUT2, A1OUT, B6OUT, A7OUT + {OUTC(1,1,0), OUTC(0,1,0), OUTC(1,5,1), OUTC(1,7,0)}, // CTX6: B1OUT, A1OUT, B5OUT2, B7OUT + {OUTC(1,1,1), OUTC(1,1,0), OUTC(1,5,0), OUTC(0,7,0)}, // CTX7: B1OUT2, B1OUT, B5OUT, A7OUT + {OUTC(0,2,0), OUTC(0,3,1), OUTC(0,4,1), OUTC(1,6,0)}, // CTX8: A2OUT, A3OUT2, A4OUT2, B6OUT + {OUTC(0,2,1), OUTC(0,2,0), OUTC(0,4,0), OUTC(1,0,0)}, // CTX9: A2OUT2, A2OUT, A4OUT, B0OUT + {OUTC(1,2,0), OUTC(1,3,1), OUTC(1,4,1), OUTC(0,6,0)}, // CTX10: B2OUT, B3OUT2, B4OUT2, A6OUT + {OUTC(1,2,1), OUTC(1,2,0), OUTC(1,4,0), OUTC(1,5,1)}, // CTX11: B2OUT2, B2OUT, B4OUT, B5OUT2 + {OUTC(0,3,0), OUTC(1,1,0), OUTC(1,0,1), OUTC(1,6,1)}, // CTX12: A3OUT, B1OUT, B0OUT2, B6OUT2 + {OUTC(0,3,1), OUTC(0,3,0), OUTC(0,6,0), OUTC(1,4,1)}, // CTX13: A3OUT2, A3OUT, A6OUT, B4OUT2 + {OUTC(1,3,0), OUTC(1,1,0), OUTC(1,7,1), OUTC(0,7,0)}, // CTX14: B3OUT, B1OUT, B7OUT2, A7OUT + {OUTC(1,3,1), OUTC(1,3,0), OUTC(0,7,0), OUTC(0,4,1)}, // CTX15: B3OUT2, B3OUT, A7OUT, A4OUT2 + {OUTC(0,4,0), OUTC(0,0,0), OUTC(0,0,1), OUTC(1,3,1)}, // CTX16: A4OUT, A0OUT, A0OUT2, B3OUT2 + {OUTC(0,4,1), OUTC(1,7,0), OUTC(0,4,0), OUTC(0,1,1)}, // CTX17: A4OUT2, B7OUT, A4OUT, A1OUT2 + {OUTC(1,4,0), OUTC(1,0,0), OUTC(0,0,0), OUTC(0,3,1)}, // CTX18: B4OUT, B0OUT, A0OUT, A3OUT2 + {OUTC(1,4,1), OUTC(0,2,0), OUTC(1,4,0), OUTC(1,1,1)}, // CTX19: B4OUT2, A2OUT, B4OUT, B1OUT2 + {OUTC(0,5,0), OUTC(0,1,0), OUTC(0,1,1), OUTC(1,2,1)}, // CTX20: A5OUT, A1OUT, A1OUT2, B2OUT2 + {OUTC(0,5,1), OUTC(0,1,0), OUTC(1,5,0), OUTC(0,0,1)}, // CTX21: A5OUT2, A1OUT, B5OUT, A0OUT2 + {OUTC(1,5,0), OUTC(0,6,0), OUTC(0,1,0), OUTC(0,2,1)}, // CTX22: B5OUT, A6OUT, A1OUT, A2OUT2 + {OUTC(1,5,1), OUTC(0,7,0), OUTC(0,5,0), OUTC(1,0,1)}, // CTX23: B5OUT2, A7OUT, A5OUT, B0OUT2 + {OUTC(0,6,0), OUTC(0,2,0), OUTC(0,1,0), OUTC(1,1,1)}, // CTX24: A6OUT, A2OUT, A1OUT, B1OUT2 + {OUTC(1,4,1), OUTC(1,2,0), OUTC(0,6,0), OUTC(0,2,1)}, // CTX25: B4OUT2, B2OUT, A6OUT, A2OUT2 + {OUTC(1,6,0), OUTC(1,2,0), OUTC(0,5,0), OUTC(0,1,1)}, // CTX26: B6OUT, B2OUT, A5OUT, A1OUT2 + {OUTC(1,6,1), OUTC(0,1,0), OUTC(1,6,0), OUTC(1,2,1)}, // CTX27: B6OUT2, A1OUT, B6OUT, B2OUT2 + {OUTC(0,7,0), OUTC(0,3,0), OUTC(0,5,1), OUTC(1,0,1)}, // CTX28: A7OUT, A3OUT, A5OUT2, B0OUT2 + {OUTC(1,5,1), OUTC(0,1,0), OUTC(0,7,0), OUTC(0,3,1)}, // CTX29: B5OUT2, A1OUT, A7OUT, A3OUT2 + {OUTC(1,7,0), OUTC(1,3,0), OUTC(0,4,1), OUTC(0,0,1)}, // CTX30: B7OUT, B3OUT, A4OUT2, A0OUT2 + {OUTC(1,7,1), OUTC(0,6,0), OUTC(1,7,0), OUTC(1,3,1)}, // CTX31: B7OUT2, A6OUT, B7OUT, B3OUT2 +}; + +//***************************************************************************** +// +// Static function for reading the timer value. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + push {r1, r4} // Save r1=ui32Data, r4 + mrs r4, PRIMASK // Save current interrupt state + cpsid i // Disable INTs while reading the reg + ldr r1, [r0, #0] // Read the designated register 3 times + ldr r2, [r0, #0] // " + ldr r3, [r0, #0] // " + msr PRIMASK, r4 // Restore interrupt state + pop {r0, r4} // Get r0=ui32Data, restore r4 + str r1, [r0, #0] // Store 1st read value to array + str r2, [r0, #4] // Store 2nd read value to array + str r3, [r0, #8] // Store 3rd read value to array + bx lr // Return to caller +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm ( + " push {R1, R4}\n" + " mrs R4, PRIMASK\n" + " cpsid i\n" + " nop\n" + " ldr R1, [R0, #0]\n" + " ldr R2, [R0, #0]\n" + " ldr R3, [R0, #0]\n" + " msr PRIMASK, r4\n" + " pop {R0, R4}\n" + " str R1, [R0, #0]\n" + " str R2, [R0, #4]\n" + " str R3, [R0, #8]\n" + : + : [u32TimerAddr] "r" (u32TimerAddr), + [ui32Data] "r" (&ui32Data[0]) + : "r0", "r1", "r2", "r3", "r4" + ); +} +#elif defined(__GNUC_STDC_INLINE__) +__attribute__((naked)) +void +am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm + ( + " push {r1, r4}\n" // Save r1=ui32Data, r4 + " mrs r4, PRIMASK \n" // Save current interrupt state + " cpsid i \n" // Disable INTs while reading the reg + " ldr r1, [r0, #0]\n" // Read the designated register 3 times + " ldr r2, [r0, #0]\n" // " + " ldr r3, [r0, #0]\n" // " + " msr PRIMASK, r4 \n" // Restore interrupt state + " pop {r0, r4}\n" // Get r0=ui32Data, restore r4 + " str r1, [r0, #0]\n" // Store 1st read value to array + " str r2, [r0, #4]\n" // Store 2nd read value to array + " str r3, [r0, #8]\n" // Store 3rd read value to array + " bx lr \n" // Return to caller + ); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless void +am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]) +{ + __asm(" push {r1, r4} "); // Save r1=ui32Data, r4 + __asm(" mrs r4, PRIMASK "); // Save current interrupt state + __asm(" cpsid i "); // Disable INTs while reading the reg + __asm(" ldr r1, [r0, #0]"); // Read the designated register 3 times + __asm(" ldr r2, [r0, #0]"); // " + __asm(" ldr r3, [r0, #0]"); // " + __asm(" msr PRIMASK, r4 "); // Restore interrupt state + __asm(" pop {r0, r4} "); // Get r0=ui32Data, restore r4 + __asm(" str r1, [r0, #0]"); // Store 1st read value to array + __asm(" str r2, [r0, #4]"); // Store 2nd read value to array + __asm(" str r3, [r0, #8]"); // Store 3rd read value to array + __asm(" bx lr "); // Return to caller +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + + + +//***************************************************************************** +// +// ctimer_clr() +// +// For the appropriate ctimer configuration register, set the CLR bit high +// in the appropriate timer segment (A, B, or both). +// +// The CLR bit is required to be set in order to completely initialize +// the timer at config time. The timer clear occurs asynchrnously during the +// low-to-high transition of the CLR bit. +// +// This function only sets the CLR bit. It is assumed that the actual timer +// configuration will occur following the call to this function and will clear +// the CLR bit at that time. +// +//***************************************************************************** +static void +ctimer_clr(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + // + // Find the address of the correct control register and set the CLR bit + // for the timer segment in that control register. + // + volatile uint32_t *pui32ConfigReg = + (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + AM_CRITICAL_BEGIN + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (CTIMER_CTRL0_TMRA0CLR_Msk | + CTIMER_CTRL0_TMRB0CLR_Msk)); + AM_CRITICAL_END + +} // ctimer_clr() + +//***************************************************************************** +// +//! @brief Convenience function for responding to CTimer interrupts. +//! +//! @param ui32Status is the interrupt status as returned by +//! am_hal_ctimer_int_status_get() +//! +//! This function may be called from am_ctimer_isr() to read the status of +//! the CTimer interrupts, determine which source caused the most recent +//! interrupt, and call an interrupt handler function to respond. The interrupt +//! handler to be called must be first registered with the +//! am_hal_ctimer_int_register() function. +//! +//! In the event that multiple sources are active, the corresponding +//! interrupt handlers will be called in numerical order based on interrupt def. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_service(uint32_t ui32Status) +{ + + am_hal_ctimer_handler_t pfnHandler; + + while ( ui32Status ) + { + uint32_t ui32Clz; + // + // Pick one of any remaining active interrupt bits + // +#ifdef __IAR_SYSTEMS_ICC__ + ui32Clz = __CLZ(ui32Status); +#else + ui32Clz = __builtin_clz(ui32Status); +#endif + + // + // Turn off the bit we picked in the working copy + // + ui32Status &= ~(0x80000000 >> ui32Clz); + + // + // Check the bit handler table to see if there is an interrupt handler + // registered for this particular bit. + // + pfnHandler = g_am_hal_ctimer_ppfnHandlers[31 - ui32Clz]; + if ( pfnHandler ) + { + // + // If we found an interrupt handler routine, call it now. + // + pfnHandler(); + } + } + +} // am_hal_ctimer_int_service() + +//***************************************************************************** +// +//! @brief Register an interrupt handler for CTimer. +//! +//! @param ui32Interrupt - interrupt number to assign this interrupt handler to. +//! @param pfnHandler - Function to call when this interrupt is received. +//! +//! This function allows the caller to specify a function that should be called +//! any time a Ctimer interrupt is received. Registering an +//! interrupt handler using this function adds the function pointer to an array +//! in SRAM. This interrupt handler will be called by am_hal_ctimer_int_service() +//! whenever the ui32Status parameter indicates that the corresponding interrupt. +//! +//! To remove an interrupt handler that has already been registered, the +//! pfnHandler parameter may be set to zero. +//! +//! @note This function will not have any effect unless the +//! am_hal_ctimer_int_service() function is being used. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_register(uint32_t ui32Interrupt, + am_hal_ctimer_handler_t pfnHandler) +{ + uint32_t intIdx = 0; + + // + // Check to make sure the interrupt number is valid. (Debug builds only) + // + switch (ui32Interrupt) + { + case CTIMER_INTEN_CTMRA0C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA0C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB0C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB0C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA1C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA1C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB1C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB1C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA2C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA2C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB2C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB2C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA3C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA3C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB3C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB3C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA4C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA4C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB4C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB4C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA5C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA5C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB5C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB5C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA6C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA6C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB6C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB6C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRA7C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRA7C0INT_Pos; + break; + + case CTIMER_INTEN_CTMRB7C0INT_Msk: + intIdx = CTIMER_INTEN_CTMRB7C0INT_Pos; + break; + + // Counter/Timer A0 interrupt based on COMPR1. + case CTIMER_INTEN_CTMRA0C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA0C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB0C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB0C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA1C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA1C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB1C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB1C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA2C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA2C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB2C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB2C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA3C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA3C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB3C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB3C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRA4C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA4C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB4C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB4C1INT_Pos; + break; + case CTIMER_INTEN_CTMRA5C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA5C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB5C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB5C1INT_Pos; + break; + case CTIMER_INTEN_CTMRA6C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA6C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB6C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB6C1INT_Pos; + break; + case CTIMER_INTEN_CTMRA7C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRA7C1INT_Pos; + break; + + case CTIMER_INTEN_CTMRB7C1INT_Msk: + intIdx = CTIMER_INTEN_CTMRB7C1INT_Pos; + break; + + default: + am_hal_debug_assert_msg(false, "CTimer interrupt number out of range."); + } + + g_am_hal_ctimer_ppfnHandlers[intIdx] = pfnHandler; + +} // am_hal_ctimer_int_register() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32ConfigVal is the value to set the global enable register. +//! +//! This function sets the global enable register inside a critical section. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_globen(uint32_t ui32ConfigVal) +{ + uint32_t *pui32ConfigReg; + + // + // Find the correct register to write. + // + pui32ConfigReg = (uint32_t *)(&CTIMERn(0)->GLOBEN); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Write our configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_globen() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param psConfig is a pointer to a structure that holds important settings +//! for the timer. +//! +//! This function should be used to perform the initial set-up of the +//! counter-timer. +//! +//! @note This function is deprecated and will eventually be replaced by +//! am_hal_ctimer_config_single(), which performs the same configuration +//! without requiring a structure and without assuming both timer halves +//! are being configured. +//! Please use am_hal_ctimer_config_single() for new development. +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config(uint32_t ui32TimerNumber, + am_hal_ctimer_config_t *psConfig) +{ + uint32_t ui32ConfigVal; + uint32_t ui32Seg, ui32ClkSrc; + uint32_t *pui32ConfigReg; + + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, AM_HAL_CTIMER_BOTH); + + // + // Start preparing the configuration word for this timer. The configuration + // values for Timer A and Timer B provided in the config structure should + // match the register definitions already, so we will mostly just need to + // OR them together. + // + ui32ConfigVal = ( (psConfig->ui32TimerAConfig) | + (psConfig->ui32TimerBConfig << 16) ); + + // + // OR in the Link bit if the timers need to be linked. + // + ui32ConfigVal |= psConfig->ui32Link ? AM_HAL_CTIMER_LINK : 0; + + // + // Find the correct register to write. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Write our configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + + // + // Save the clock source for this timer. + // + if ( ( psConfig->ui32TimerAConfig != 0 ) || psConfig->ui32Link ) + { + ui32Seg = 0; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, psConfig->ui32TimerAConfig); + } + else if ( psConfig->ui32TimerBConfig != 0) + { + ui32Seg = 1; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, psConfig->ui32TimerBConfig); + } + else + { + return; + } + + // + // Save the clock source for this timer/segment. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = ui32ClkSrc; + +} // am_hal_ctimer_config() + +//***************************************************************************** +// +//! @brief Set up the counter/timer. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. +//! +//! @param ui32ConfigVal specifies the configuration options for the selected +//! timer. +//! +//! This function should be used to perform the initial set-up of the +//! counter-timer. It can be used to configure either a 16-bit timer (A or B) or a +//! 32-bit timer using the BOTH option. +//! +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! The timer's clock source, mode, interrupt, and external pin behavior are +//! all controlled through the \e ui32Configval parameter. The valid options +//! for ui32ConfigVal include any ORed together combination of the following: +//! +//! Clock configuration macros: +//! +//! AM_HAL_CTIMER_HFRC_24MHZ +//! AM_HAL_CTIMER_LFRC_512HZ +//! ... etc. (See am_hal_ctimer.h for the full set of options.) +//! +//! Mode selection macros: +//! +//! AM_HAL_CTIMER_FN_ONCE +//! AM_HAL_CTIMER_FN_REPEAT +//! AM_HAL_CTIMER_FN_PWM_ONCE +//! AM_HAL_CTIMER_FN_PWM_REPEAT +//! AM_HAL_CTIMER_FN_CONTINUOUS +//! +//! Interrupt control: +//! +//! AM_HAL_CTIMER_INT_ENABLE +//! +//! Pin control: +//! +//! AM_HAL_CTIMER_PIN_ENABLE +//! AM_HAL_CTIMER_PIN_INVERT +//! +//! ADC trigger (Timer 3 only): +//! +//! AM_HAL_CTIMER_ADC_TRIG +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config_single(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal) +{ + volatile uint32_t *pui32ConfigReg; + uint32_t ui32Seg, ui32ClkSrc; + + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, ui32TimerSegment); + + // + // Find the correct register to write based on the timer number. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + uint32_t ui32WriteVal; + + // + // Save the value that's already in the register. + // + ui32WriteVal = AM_REGVAL(pui32ConfigReg); + + // + // If we're working with TIMERB, we need to shift our configuration value + // up by 16 bits. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16); + } + + // + // Replace part of the saved register value with the configuration value + // from the caller. + // + ui32WriteVal = (ui32WriteVal & ~(ui32TimerSegment)) | ui32ConfigVal; + + // + // If we're configuring both timers, we need to set the "link" bit. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + ui32WriteVal |= AM_HAL_CTIMER_LINK; + } + + // + // Write our completed configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32WriteVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + + // + // Save the clock source for this timer. + // + switch ( ui32TimerSegment ) + { + case AM_HAL_CTIMER_TIMERA: + case AM_HAL_CTIMER_BOTH: + ui32Seg = 0; + break; + case AM_HAL_CTIMER_TIMERB: + ui32Seg = 1; + break; + default: + return; + } + + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, ui32ConfigVal); + + // + // Save the clock source for this timer/segment. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = (uint8_t)ui32ClkSrc; + +} // am_hal_ctimer_config_single() + +//***************************************************************************** +// +//! @brief Set up the counter/timer trigger. +//! +//! @param ui32TimerNumber is the number of the Timer that should be +//! configured. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. +//! +//! @param ui32ConfigVal specifies the configuration options for the selected +//! timer trigger AUXn register. +//! +//! This function should be used to perform the configuration of the trigger +//! for the counter-timer (A or B). +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! +//! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! +// +//***************************************************************************** +void +am_hal_ctimer_config_trigger(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct register to write based on the timer number. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, AUX0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + uint32_t ui32WriteVal; + + // + // Save the value that's already in the register. + // + ui32WriteVal = AM_REGVAL(pui32ConfigReg); + + // + // If we're working with TIMERB, we need to shift our configuration value + // up by 16 bits. + // + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16); + } + + // + // Replace part of the saved register value with the configuration value + // from the caller. + // + ui32WriteVal = (ui32WriteVal & ~(ui32TimerSegment)) | ui32ConfigVal; + + // + // Write our completed configuration value. + // + AM_REGVAL(pui32ConfigReg) = ui32WriteVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_config_trigger() + +//***************************************************************************** +// +//! @brief Start a timer +//! +//! @param ui32TimerNumber is the number of the timer to enable +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! enabled. Valid values for ui32TimerSegment are: +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! This function will enable a timer to begin incrementing. The \e +//! ui32TimerNumber parameter selects the timer that should be enabled, for +//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows +//! the caller to individually select a segment within a timer to be enabled, +//! such as TIMER0A, TIMER0B, or both. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_start(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + uint32_t ui32Seg, ui32ClkSrc; + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section while config registers are read and modified. + // + AM_CRITICAL_BEGIN + + // + // Read the current value. + // + uint32_t ui32ConfigVal = *pui32ConfigReg; + + // + // Clear out the "clear" bit. + // + ui32ConfigVal &= ~(ui32TimerSegment & (CTIMER_CTRL0_TMRA0CLR_Msk | + CTIMER_CTRL0_TMRB0CLR_Msk)); + + // + // Set the "enable bit" + // + ui32ConfigVal |= (ui32TimerSegment & (CTIMER_CTRL0_TMRA0EN_Msk | + CTIMER_CTRL0_TMRB0EN_Msk)); + + // + // While we already have the CTRL reg, get and save the CLKSRC. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Seg = 1; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRB0CLK, ui32ConfigVal); + } + else + { + ui32Seg = 0; + ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, ui32ConfigVal); + } + + // + // Save the clock source for this timer/segment. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = ui32ClkSrc; + + // + // Write the configuration to start the timer. + // + AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_start() + +//***************************************************************************** +// +//! @brief Stop a timer +//! +//! @param ui32TimerNumber is the number of the timer to disable. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! disabled. +//! +//! This function will stop the selected timer from incrementing. The \e +//! ui32TimerNumber parameter selects the timer that should be disabled, for +//! example, a 0 would target TIMER0. The \e ui32TimerSegment parameter allows +//! the caller to individually select a segment within a timer to be disabled, +//! such as TIMER0A, TIMER0B, or both. +//! +//! This function will stop a counter/timer from counting, but does not return +//! the count value to 'zero'. If you would like to reset the counter back to +//! zero, try the am_hal_ctimer_clear() function instead. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_stop(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Clear the "enable" bit + // + AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment & + (CTIMER_CTRL0_TMRA0EN_Msk | + CTIMER_CTRL0_TMRB0EN_Msk)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_stop() + +//***************************************************************************** +// +//! @brief Stops a timer and resets its value back to zero. +//! +//! @param ui32TimerNumber is the number of the timer to clear. +//! +//! @param ui32TimerSegment specifies which segment of the timer should be +//! cleared. +//! +//! This function will stop a free-running counter-timer, reset its value to +//! zero, and leave the timer disabled. When you would like to restart the +//! counter, you will need to call am_hal_ctimer_start(). +//! +//! The \e ui32TimerSegment parameter allows the caller to individually select +//! a segment within, such as TIMER0A, TIMER0B, or both. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +//! +//! +//! @note Setting the CLR bit is necessary for completing timer initialization +//! including after MCU resets. +//! +// +//***************************************************************************** +void +am_hal_ctimer_clear(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + volatile uint32_t *pui32ConfigReg; + + // + // Find the correct control register. + // + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Set the "clear" bit + // + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (CTIMER_CTRL0_TMRA0CLR_Msk | + CTIMER_CTRL0_TMRB0CLR_Msk)); + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_clear() + +//***************************************************************************** +// +//! @brief Returns the current free-running value of the selected timer. +//! +//! @param ui32TimerNumber is the number of the timer to read. +//! @param ui32TimerSegment specifies which segment of the timer should be +//! read. +//! +//! This function returns the current free-running value of the selected timer. +//! +//! @note When reading from a linked timer, be sure to use AM_HAL_CTIMER both +//! for the segment argument. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return Current timer value. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_read(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + uint32_t ui32RetVal = 0; + uint32_t ui32ClkMsk, ui32Seg, ui32TmrAddr, ui32Ctrl; + uint8_t ui8ClkSrc; + uint32_t ui32Values[3]; + + // + // Determine the timer segment. + // + ui32Seg = ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) ? 1 : 0; + + // + // Get the address of the register for this timer. + // + ui32TmrAddr = g_ui32TMRAddrTbl[ui32TimerNumber]; + + // + // Get the clock source for this timer. + // + ui8ClkSrc = g_ui8ClkSrc[ui32TimerNumber][ui32Seg]; + + if ( ui8ClkSrc == 0xFF ) + { + // + // If user did not configure using am_hal_ctimer_config_single() or + // am_hal_ctimer_config(), read the register to get the clock source. + // Note that this will incur bus latencies. + // + ui32Ctrl = AM_REGVAL(ui32TmrAddr + 0xC); + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui8ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRB0CLK, ui32Ctrl); + } + else + { + ui8ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, ui32Ctrl); + } + + // + // And save the clock source to the lookup table. + // + g_ui8ClkSrc[ui32TimerNumber][ui32Seg] = ui8ClkSrc; + } + + // + // Based on the source clock, mask off bits not needed for the comparison. + // + ui32ClkMsk = g_ui8TmrClkSrcMask[ui8ClkSrc & _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, 0xFFFFFFFF)]; + + if ( ui32ClkMsk != 0 ) + { + if ( am_hal_burst_mode_status() == AM_HAL_BURST_MODE ) + { + // + // In burst mode, extend the mask by 1 bit. + // + ui32ClkMsk <<= 1; + ui32ClkMsk |= 0x1; + } + + // + // Invert the mask so that the unneeded bits can be masked off. + // + ui32ClkMsk = ~ui32ClkMsk; + + // + // Read the register into ui32Values[]. + // + am_hal_triple_read(ui32TmrAddr, ui32Values); + + // + // Now determine which of the three values is the correct value. + // If the first 2 match, then the values are both correct and we're done. + // Otherwise, the third value is taken to be the correct value. + // + if ( (ui32Values[0] & ui32ClkMsk) == (ui32Values[1] & ui32ClkMsk) ) + { + // + // If the first two values match, then neither one was a bad read. + // We'll take this as the current time. + // + ui32RetVal = ui32Values[1]; + } + else + { + ui32RetVal = ui32Values[2]; + } + } + else + { + // + // No need for the workaround. Just read and return the register. + // + ui32RetVal = AM_REGVAL(ui32TmrAddr); + } + + // + // Get the correct return value + // + ui32RetVal &= ui32TimerSegment; + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32RetVal >>= 16; + } + + return ui32RetVal; + +} // am_hal_ctimer_read() + +//***************************************************************************** +// +//! @brief Configure timer pin output. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32TimerOutputConfig Output Configuration options. +//! +//! This function will configure the output pin for the selected timer. +//! +//! ui32TimerNumber +//! The timer number, 0-7. +//! ui32TimerSegment +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! ui32PadNum +//! Pad number to be used for the output signal. +//! eOutputType +//! AM_HAL_CTIMER_OUTPUT_NORMAL +//! AM_HAL_CTIMER_OUTPUT_SECONDARY +//! AM_HAL_CTIMER_OUTPUT_FORCE0 +//! AM_HAL_CTIMER_OUTPUT_FORCE1 +//! eDriveStrength +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA = 0x0, +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA = 0x1, +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA = 0x2, +//! AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA = 0x3 +//! +//! @return None. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_output_config(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32PadNum, + uint32_t eOutputType, + uint32_t eDriveStrength) +{ + uint32_t ux, ui32Ctx, ui32CtxPadNum; + uint32_t ui32CtxOutcfgFnc, ui32CtxOutcfgMsk, ui32CfgShf; + uint32_t ui32OutcfgValue; + + am_hal_gpio_pincfg_t sPinCfg = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + if ( (ui32PadNum > 49) || (ui32TimerNumber > 7) || + (eOutputType > AM_HAL_CTIMER_OUTPUT_FORCE1) || + ( (ui32TimerSegment != AM_HAL_CTIMER_TIMERA) && + (ui32TimerSegment != AM_HAL_CTIMER_TIMERB) && + (ui32TimerSegment != AM_HAL_CTIMER_BOTH) ) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Lookup the CTx number based on the given pad number. + // + for ( ux = 0; ux < 32; ux++ ) + { + ui32CtxPadNum = CTXPADNUM(ux); + if ( ui32CtxPadNum == ui32PadNum ) + { + ui32Ctx = ux; + break; + } + ui32CtxPadNum = 0xFF; + } + + if ( ui32CtxPadNum >= AM_HAL_GPIO_MAX_PADS ) + { + // No valid pad found. + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( ( ui32TimerNumber >= 6 ) && + ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) && + (eOutputType == AM_HAL_CTIMER_OUTPUT_SECONDARY) ) + { + // + // A6OUT2 is function 6 for every CTx. + // A7OUT2 is function 7 for every CTx. + // Set the function to either 6 or 7. + // + ui32CtxOutcfgFnc = ui32TimerNumber; + } + else if ( eOutputType >= AM_HAL_CTIMER_OUTPUT_FORCE0 ) + { + // Set the function to 0 or 1. + ui32CtxOutcfgFnc = eOutputType - AM_HAL_CTIMER_OUTPUT_FORCE0; + } + else + { + // + // Now, scan outcfg_tbl[] to determine how to set the pin. + // + for ( ux = 0; ux < 4; ux++ ) + { + if ( (OUTCTIMN(ui32Ctx, ux) == ui32TimerNumber) ) + { + bool bTimerB = OUTCTIMB(ui32Ctx, ux); + bool bO2 = OUTCO2(ui32Ctx, ux) ? true : false; + bool bOut2 = (eOutputType == AM_HAL_CTIMER_OUTPUT_SECONDARY); + if ( ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) && + (!bTimerB) && + (bO2 == bOut2) ) + { + break; + } + + if ( ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) && + (bTimerB) && + (bO2 == bOut2) ) + { + break; + } + } + } + + if ( ux >= 4 ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + ui32CtxOutcfgFnc = ux + 2; + } + + // + // Looks like everything is valid. Configure the pin. + // Do the actual configuring inside a critical section. + // + ux = ui32Ctx % 10; + ui32CfgShf = ux * 3; + if ( ux > 4 ) + { + ui32CfgShf += 1; + } + ui32CtxOutcfgMsk = 0x7 << ui32CfgShf; + ui32CtxOutcfgFnc <<= ui32CfgShf; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Note: It turns out that the offsets of the 4 OUTCFG registers are not + // evenly spaced. Therefore we purposely use this 'if' chain to program + // them explicitly (as opposed to doing modulo math to compute an addr). + // + if ( ui32Ctx < 10 ) + { + ui32OutcfgValue = CTIMER->OUTCFG0; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG0 = ui32OutcfgValue; + } + else if ( ui32Ctx < 20 ) + { + ui32OutcfgValue = CTIMER->OUTCFG1; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG1 = ui32OutcfgValue; + } + else if ( ui32Ctx < 30 ) + { + ui32OutcfgValue = CTIMER->OUTCFG2; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG2 = ui32OutcfgValue; + } + else + { + ui32OutcfgValue = CTIMER->OUTCFG3; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG3 = ui32OutcfgValue; + } + + GPIO->CTENCFG &= ~(1 << ui32Ctx); + + // + // Done with critical section. + // + AM_CRITICAL_END + + // + // Configure the GPIO for the given pad. + // + sPinCfg.uFuncSel = CTXPADFNC(ui32Ctx); + sPinCfg.eDriveStrength = eDriveStrength; + am_hal_gpio_pinconfig(ui32CtxPadNum, sPinCfg); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ctimer_output_config() + +//***************************************************************************** +// +//! @brief Configure timer inputs. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32TimerInputConfig Input Configuration options. +//! +//! This function will configure the input pin for the selected timer. +//! +//! Valid values for ui32TimerSegment are: +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_input_config(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32TimerInputConfig) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_input_config() + +//***************************************************************************** +// +//! @brief Set a compare register. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @param ui32CompareReg specifies which compare register should be set +//! (either 0 or 1) +//! +//! @param ui32Value is the value that should be written to the compare +//! register. +//! +//! This function allows the caller to set the values in the compare registers +//! for a timer. These registers control the period and duty cycle of the +//! timers and their associated output pins. Please see the datasheet for +//! further information on the operation of the compare registers. The \e +//! ui32TimerSegment parameter allows the caller to individually select a +//! segment within, such as TIMER0A, TIMER0B, or both. +//! +//! @note For simple manipulations of period or duty cycle for timers and PWMs, +//! you may find it easier to use the am_hal_ctimer_period_set() function. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, uint32_t ui32Value) +{ + volatile uint32_t *pui32CmprRegA, *pui32CmprRegB; + uint32_t ui32CmprRegA, ui32CmprRegB, ui32ValB; + + // + // Find the correct compare register to write. + // Assume A or BOTH. We'll change later if B. + // + pui32CmprRegA = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRA0); + pui32CmprRegB = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRB0); + + ui32ValB = ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) ? + ui32Value >> 16 : ui32Value & 0xFFFF; + + // + // Write the compare register with the selected value. + // Begin critical section while CMPR registers are modified. + // + AM_CRITICAL_BEGIN + + ui32CmprRegA = *pui32CmprRegA; + ui32CmprRegB = *pui32CmprRegB; + + if ( ui32CompareReg == 1 ) + { + // + // CMPR reg 1 + // Get the lower 16b (but may not be used if TIMERB). + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRA0_CMPR0A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Value & 0xFFFF) ); + + // + // Get the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRA0_CMPR0A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32ValB) ); + } + else + { + // + // CMPR reg 0 + // Get the lower 16b (but may not be used if TIMERB) + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRA0_CMPR1A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Value & 0xFFFF) ); + + // + // Set the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRA0_CMPR1A0_Msk) | + _VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32ValB) ); + } + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + *pui32CmprRegB = ui32CmprRegB; + } + else + { + // + // It's TIMERA or BOTH. + // + *pui32CmprRegA = ui32CmprRegA; + + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + *pui32CmprRegB = ui32CmprRegB; + } + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_compare_set() + +//***************************************************************************** +// +//! @brief Set a compare register. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @param ui32CompareReg specifies which compare register should be set +//! (either 0 or 1) +//! +//! @param ui32Value is the value that should be written to the compare +//! register. +//! +//! This function allows the caller to set the values in the compare registers +//! for a timer. These registers control the period and duty cycle of the +//! timers and their associated output pins. Please see the datasheet for +//! further information on the operation of the compare registers. The \e +//! ui32TimerSegment parameter allows the caller to individually select a +//! segment within, such as TIMER0A, TIMER0B, or both. +//! +//! @note For simple manipulations of period or duty cycle for timers and PWMs, +//! you may find it easier to use the am_hal_ctimer_period_set() function. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_aux_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, uint32_t ui32Value) +{ + volatile uint32_t *pui32CmprRegA, *pui32CmprRegB; + uint32_t ui32CmprRegA, ui32CmprRegB, ui32ValB; + + // + // Find the correct compare register to write. + // Assume A or BOTH. We'll change later if B. + // + pui32CmprRegA = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXA0); + pui32CmprRegB = (uint32_t *)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXB0); + + ui32ValB = ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) ? + ui32Value >> 16 : ui32Value & 0xFFFF; + + // + // Write the compare register with the selected value. + // Begin critical section while CMPR registers are modified. + // + AM_CRITICAL_BEGIN + + ui32CmprRegA = *pui32CmprRegA; + ui32CmprRegB = *pui32CmprRegB; + + if ( ui32CompareReg == 1 ) + { + // + // CMPR reg 1 + // Get the lower 16b (but may not be used if TIMERB). + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRAUXA0_CMPR2A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Value & 0xFFFF) ); + + // + // Get the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRAUXA0_CMPR2A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32ValB) ); + } + else + { + // + // CMPR reg 0 + // Get the lower 16b (but may not be used if TIMERB) + // + ui32CmprRegA = ( (ui32CmprRegA & CTIMER_CMPRAUXA0_CMPR3A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Value & 0xFFFF) ); + + // + // Set the upper 16b (but may not be used if TIMERA) + // + ui32CmprRegB = ( (ui32CmprRegB & CTIMER_CMPRAUXA0_CMPR3A0_Msk) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32ValB) ); + } + + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + *pui32CmprRegB = ui32CmprRegB; + } + else + { + // + // It's TIMERA or BOTH. + // + *pui32CmprRegA = ui32CmprRegA; + + if ( ui32TimerSegment == AM_HAL_CTIMER_BOTH ) + { + *pui32CmprRegB = ui32CmprRegB; + } + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_aux_compare_set() + +//***************************************************************************** +// +//! @brief Set the period and duty cycle of a timer. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32Period specifies the desired period. This parameter effectively +//! specifies the CTIMER CMPR field(s). The CMPR fields are handled in hardware +//! as (n+1) values, therefore ui32Period is actually specified as 1 less than +//! the desired period. Finally, as mentioned in the data sheet, the CMPR fields +//! cannot be 0 (a value of 1), so neither can ui32Period be 0. +//! +//! @param ui32OnTime set the number of clocks where the output signal is high. +//! +//! This function should be used for simple manipulations of the period and +//! duty cycle of a counter/timer. To set the period and/or duty cycle of a +//! linked timer pair, use AM_HAL_CTIMER_BOTH as the timer segment argument. If +//! you would like to set the period and/or duty cycle for both TIMERA and +//! TIMERB you will need to call this function twice: once for TIMERA, and once +//! for TIMERB. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @note The ui32OnTime parameter will only work if the timer is currently +//! operating in one of the PWM modes. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_period_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32Period, uint32_t ui32OnTime) +{ + volatile uint32_t *pui32ControlReg; + volatile uint32_t *pui32CompareRegA; + volatile uint32_t *pui32CompareRegB; + uint32_t ui32Mode, ui32Comp0, ui32Comp1; + + // + // Find the correct control register to pull the function select field + // from. + // + pui32ControlReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Find the correct compare registers to write. + // + pui32CompareRegA = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRA0); + + pui32CompareRegB = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRB0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Extract the timer mode from the register based on the ui32TimerSegment + // selected by the user. + // + ui32Mode = *pui32ControlReg; + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Mode = ui32Mode >> 16; + } + + // + // Mask to get to the bits we're interested in. + // + ui32Mode = ui32Mode & CTIMER_CTRL0_TMRA0FN_Msk; + + // + // If the mode is a PWM mode, we'll need to calculate the correct CMPR0 and + // CMPR1 values here. + // + if (ui32Mode == AM_HAL_CTIMER_FN_PWM_ONCE || + ui32Mode == AM_HAL_CTIMER_FN_PWM_REPEAT) + { + ui32Comp0 = ui32Period - ui32OnTime; + ui32Comp1 = ui32Period; + } + else + { + ui32Comp0 = ui32Period; + ui32Comp1 = 0; + } + + // + // Based on the timer segment argument, write the calculated Compare 0 and + // Compare 1 values to the correct halves of the correct registers. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) + { + // + // For timer A, write the values to the TIMERA compare register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1)); + } + else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + // + // For timer B, write the values to the TIMERA compare register. + // + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1)); + } + else + { + // + // For the linked case, write the lower halves of the values to the + // TIMERA compare register, and the upper halves to the TIMERB compare + // register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1)); + + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRA0_CMPR0A0, ui32Comp0 >> 16) | + _VAL2FLD(CTIMER_CMPRA0_CMPR1A0, ui32Comp1 >> 16)); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_period_set() + +//***************************************************************************** +// +//! @brief Set the period and duty cycle of a timer. +//! +//! @param ui32TimerNumber is the number of the timer to configure. +//! +//! @param ui32TimerSegment specifies which segment of the timer to use. +//! +//! @param ui32Period specifies the desired period. This parameter effectively +//! specifies the CTIMER CMPR field(s). The CMPR fields are handled in hardware +//! as (n+1) values, therefore ui32Period is actually specified as 1 less than +//! the desired period. Finally, as mentioned in the data sheet, the CMPR fields +//! cannot be 0 (a value of 1), so neither can ui32Period be 0. +//! +//! @param ui32OnTime set the number of clocks where the output signal is high. +//! +//! This function should be used for simple manipulations of the period and +//! duty cycle of a counter/timer. To set the period and/or duty cycle of a +//! linked timer pair, use AM_HAL_CTIMER_BOTH as the timer segment argument. If +//! you would like to set the period and/or duty cycle for both TIMERA and +//! TIMERB you will need to call this function twice: once for TIMERA, and once +//! for TIMERB. +//! +//! Valid values for ui32TimerSegment are: +//! +//! AM_HAL_CTIMER_TIMERA +//! AM_HAL_CTIMER_TIMERB +//! AM_HAL_CTIMER_BOTH +//! +//! @note The ui32OnTime parameter will only work if the timer is currently +//! operating in one of the PWM modes. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_aux_period_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, + uint32_t ui32Period, uint32_t ui32OnTime) +{ + volatile uint32_t *pui32ControlReg; + volatile uint32_t *pui32CompareRegA; + volatile uint32_t *pui32CompareRegB; + uint32_t ui32Mode, ui32Comp0, ui32Comp1; + + // + // Find the correct control register to pull the function select field + // from. + // + pui32ControlReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + // + // Find the correct compare registers to write. + // + pui32CompareRegA = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXA0); + + pui32CompareRegB = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CMPRAUXB0); + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Extract the timer mode from the register based on the ui32TimerSegment + // selected by the user. + // + ui32Mode = *pui32ControlReg; + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + ui32Mode = ui32Mode >> 16; + } + + // + // Mask to get to the bits we're interested in. + // + ui32Mode = ui32Mode & CTIMER_CTRL0_TMRA0FN_Msk; + + // + // If the mode is a PWM mode, we'll need to calculate the correct CMPR0 and + // CMPR1 values here. + // + if (ui32Mode == AM_HAL_CTIMER_FN_PWM_ONCE || + ui32Mode == AM_HAL_CTIMER_FN_PWM_REPEAT) + { + ui32Comp0 = ui32Period - ui32OnTime; + ui32Comp1 = ui32Period; + } + else + { + ui32Comp0 = ui32Period; + ui32Comp1 = 0; + } + + // + // Based on the timer segment argument, write the calculated Compare 0 and + // Compare 1 values to the correct halves of the correct registers. + // + if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERA ) + { + // + // For timer A, write the values to the TIMERA compare register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1)); + } + else if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) + { + // + // For timer B, write the values to the TIMERA compare register. + // + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1)); + } + else + { + // + // For the linked case, write the lower halves of the values to the + // TIMERA compare register, and the upper halves to the TIMERB compare + // register. + // + *pui32CompareRegA = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1)); + + *pui32CompareRegB = (_VAL2FLD(CTIMER_CMPRAUXA0_CMPR2A0, ui32Comp0 >> 16) | + _VAL2FLD(CTIMER_CMPRAUXA0_CMPR3A0, ui32Comp1 >> 16)); + } + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_aux_period_set() + +//***************************************************************************** +// +//! @brief Enable the TIMERA3 ADC trigger +//! +//! This function enables the ADC trigger within TIMERA3. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_adc_trigger_enable(void) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Enable the ADC trigger. + // + CTIMER->CTRL3_b.ADCEN = 1; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_adc_trigger_enable() + +//***************************************************************************** +// +//! @brief Disable the TIMERA3 ADC trigger +//! +//! This function disables the ADC trigger within TIMERA3. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_adc_trigger_disable(void) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the ADC trigger. + // + CTIMERn(0)->CTRL3 &= ~CTIMER_CTRL3_ADCEN_Msk; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_adc_trigger_disable() + +//***************************************************************************** +// +//! @brief Enables the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will enable the selected interrupts in the main CTIMER +//! interrupt enable register. In order to receive an interrupt from a timer, +//! you will need to enable the interrupt for that timer in this main register, +//! as well as in the timer control register (accessible though +//! am_hal_ctimer_config()), and in the NVIC. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_CTIMER_INT_TIMERAxCx, AM_HAL_CTIMER_INT_TIMERAxCx, +//! +//! @note The AM_HAL_CTIMER_INT_TIMER defines were re-definitions of +//! AM_REG_CTIMER_INTEN_CTMRAxCxINT_M register defines. They are +//! dropped in this release to go back to a single source definition. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_enable(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Enable the interrupt at the module level. + // + CTIMERn(0)->INTEN |= ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_enable() + +//***************************************************************************** +// +//! @brief Return the enabled timer interrupts. +//! +//! This function will return all enabled interrupts in the main CTIMER +//! interrupt enable register. +//! +//! @return return enabled interrupts. This will be a logical or of: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return Return the enabled timer interrupts. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + return CTIMERn(0)->INTEN; + +} // am_hal_ctimer_int_enable_get() + +//***************************************************************************** +// +//! @brief Disables the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will disable the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_disable(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->INTEN &= ~ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_disable() + +//***************************************************************************** +// +//! @brief Clears the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will clear the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_clear(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->INTCLR = ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_clear() + +//***************************************************************************** +// +//! @brief Sets the selected timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will set the selected interrupts in the main CTIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_ctimer_int_set(uint32_t ui32Interrupt) +{ + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Set the interrupts. + // + CTIMERn(0)->INTSET = ui32Interrupt; + + // + // Done with critical section. + // + AM_CRITICAL_END + +} // am_hal_ctimer_int_set() + +//***************************************************************************** +// +//! @brief Returns either the enabled or raw timer interrupt status. +//! +//! This function will return the timer interrupt status. +//! +//! @param bEnabledOnly if true returns the status of the enabled interrupts +//! only. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! AM_REG_CTIMER_INTEN_CTMRAxC0INT_M, AM_HAL_CTIMER_INT_TIMERAxC1, +//! +//! @return u32RetVal either the timer interrupt status, or interrupt enabled. +// +//***************************************************************************** +uint32_t +am_hal_ctimer_int_status_get(bool bEnabledOnly) +{ + uint32_t u32RetVal = 0; + + // + // Begin critical section. + // + AM_CRITICAL_BEGIN + + // + // Return the desired status. + // + + if ( bEnabledOnly ) + { + u32RetVal = CTIMERn(0)->INTSTAT; + u32RetVal &= CTIMERn(0)->INTEN; + } + else + { + u32RetVal = CTIMERn(0)->INTSTAT; + } + + // + // Done with critical section. + // + AM_CRITICAL_END + + return u32RetVal; + +} // am_hal_ctimer_int_status_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.h new file mode 100644 index 0000000000..74b53831e6 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ctimer.h @@ -0,0 +1,555 @@ +//***************************************************************************** +// +// am_hal_ctimer.h +//! @file +//! +//! @brief Functions for accessing and configuring the CTIMER. +//! +//! @addtogroup ctimer3 Counter/Timer (CTIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_CTIMER_H +#define AM_HAL_CTIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_CTIMER 1 + +//***************************************************************************** +// +// CTIMERADDRn() +// This is a specialized version of AM_REGADDRn(). It is necessary because +// the CTIMER does not work as a multi-module peripheral. In typical +// multi-module peripherals, the base address is defined as MODULE0_BASE. +// For CTIMER it's CTIMER_BASE (there is no module 0 defined). +// +// Usage: +// CTIMER_ADDRn(CTIMER, n, reg). +// +// periph: Must always be CTIMER. +// n: The timer number specified as a macro, variable, etc. +// reg: The register name always ending in '0'. E.g. TMR0, CTRL0, CMPRB0, +// etc (regardless of the timernum specified by 'n'). +// +//***************************************************************************** +#define CTIMERADDRn(periph, n, reg) ( periph##_BASE + \ + offsetof(periph##_Type, reg) + \ + (n * (offsetof(periph##_Type, TMR1) - offsetof(periph##_Type, TMR0))) ) + +// +// Enumerations for the eOutputType argument of am_hal_ctimer_output_config(). +// +typedef enum +{ + AM_HAL_CTIMER_OUTPUT_NORMAL = 0x0, + AM_HAL_CTIMER_OUTPUT_SECONDARY = 0x1, + AM_HAL_CTIMER_OUTPUT_FORCE0 = 0x2, + AM_HAL_CTIMER_OUTPUT_FORCE1 = 0x3 +} am_hal_ctimer_outputtype_e; + + +//***************************************************************************** +// +//! CMSIS-Style macro for handling a variable CTIMER module number. +// +//***************************************************************************** +#define CTIMERn(n) ((CTIMER_Type*)(CTIMER_BASE + (n * ((uint32_t)&CTIMER->TMR1 - (uint32_t)&CTIMER->TMR0)))) + +//***************************************************************************** +// +//! Number of timers +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMERS_NUM 8 + +//***************************************************************************** +// +//! Timer offset value +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMER_OFFSET ((uint32_t)&CTIMER->TMR1 - (uint32_t)&CTIMER->TMR0) + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_TIMERA0C0 CTIMER_INTEN_CTMRA0C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA0C1 CTIMER_INTEN_CTMRA0C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA1C0 CTIMER_INTEN_CTMRA1C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA1C1 CTIMER_INTEN_CTMRA1C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA2C0 CTIMER_INTEN_CTMRA2C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA2C1 CTIMER_INTEN_CTMRA2C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA3C0 CTIMER_INTEN_CTMRA3C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA3C1 CTIMER_INTEN_CTMRA3C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA4C0 CTIMER_INTEN_CTMRA4C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA4C1 CTIMER_INTEN_CTMRA4C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA5C0 CTIMER_INTEN_CTMRA5C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA5C1 CTIMER_INTEN_CTMRA5C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA6C0 CTIMER_INTEN_CTMRA6C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA6C1 CTIMER_INTEN_CTMRA6C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA7C0 CTIMER_INTEN_CTMRA7C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERA7C1 CTIMER_INTEN_CTMRA7C1INT_Msk + +#define AM_HAL_CTIMER_INT_TIMERB0C0 CTIMER_INTEN_CTMRB0C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB0C1 CTIMER_INTEN_CTMRB0C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB1C0 CTIMER_INTEN_CTMRB1C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB1C1 CTIMER_INTEN_CTMRB1C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB2C0 CTIMER_INTEN_CTMRB2C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB2C1 CTIMER_INTEN_CTMRB2C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB3C0 CTIMER_INTEN_CTMRB3C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB3C1 CTIMER_INTEN_CTMRB3C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB4C0 CTIMER_INTEN_CTMRB4C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB4C1 CTIMER_INTEN_CTMRB4C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB5C0 CTIMER_INTEN_CTMRB5C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB5C1 CTIMER_INTEN_CTMRB5C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB6C0 CTIMER_INTEN_CTMRB6C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB6C1 CTIMER_INTEN_CTMRB6C1INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB7C0 CTIMER_INTEN_CTMRB7C0INT_Msk +#define AM_HAL_CTIMER_INT_TIMERB7C1 CTIMER_INTEN_CTMRB7C1INT_Msk +//! @} + +//***************************************************************************** +// +// DEPRECATED Interrupt Status Bits +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_TIMERA0 AM_HAL_CTIMER_INT_TIMERA0C0 +#define AM_HAL_CTIMER_INT_TIMERB0 AM_HAL_CTIMER_INT_TIMERB0C0 +#define AM_HAL_CTIMER_INT_TIMERA1 AM_HAL_CTIMER_INT_TIMERA1C0 +#define AM_HAL_CTIMER_INT_TIMERB1 AM_HAL_CTIMER_INT_TIMERB1C0 +#define AM_HAL_CTIMER_INT_TIMERA2 AM_HAL_CTIMER_INT_TIMERA2C0 +#define AM_HAL_CTIMER_INT_TIMERB2 AM_HAL_CTIMER_INT_TIMERB2C0 +#define AM_HAL_CTIMER_INT_TIMERA3 AM_HAL_CTIMER_INT_TIMERA3C0 +#define AM_HAL_CTIMER_INT_TIMERB3 AM_HAL_CTIMER_INT_TIMERB3C0 + +//***************************************************************************** +// +//! @name Configuration options +//! @brief Configuration options for \e am_hal_ctimer_config_t +//! +//! These options are to be used with the \e am_hal_ctimer_config_t structure +//! used by \e am_hal_ctimer_config +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_CLK_PIN _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x00) +#define AM_HAL_CTIMER_HFRC_12MHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x01) +#define AM_HAL_CTIMER_HFRC_3MHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x02) +#define AM_HAL_CTIMER_HFRC_187_5KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x03) +#define AM_HAL_CTIMER_HFRC_47KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x04) +#define AM_HAL_CTIMER_HFRC_12KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x05) +#define AM_HAL_CTIMER_XT_32_768KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x06) +#define AM_HAL_CTIMER_XT_16_384KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x07) +#define AM_HAL_CTIMER_XT_2_048KHZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x08) +#define AM_HAL_CTIMER_XT_256HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x09) +#define AM_HAL_CTIMER_LFRC_512HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0A) +#define AM_HAL_CTIMER_LFRC_32HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0B) +#define AM_HAL_CTIMER_LFRC_1HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0C) +#define AM_HAL_CTIMER_LFRC_1_16HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0D) +#define AM_HAL_CTIMER_RTC_100HZ _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0E) +#define AM_HAL_CTIMER_HCLK_DIV4 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x0F) +#define AM_HAL_CTIMER_XT_DIV4 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x10) +#define AM_HAL_CTIMER_XT_DIV8 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x11) +#define AM_HAL_CTIMER_XT_DIV32 _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x12) +#define AM_HAL_CTIMER_RSVD _VAL2FLD(CTIMER_CTRL0_TMRA0CLK, 0x13) +//! @} + +//***************************************************************************** +// +//! Timer function macros. +//! +//! @{ +// +//***************************************************************************** +//! Single Count: Counts one time to the compare value, then the output +//! changes polarity and stays at that level, with an optional interrupt. +#define AM_HAL_CTIMER_FN_ONCE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 0) +//! Repeated Count: Periodic 1-clock-cycle wide pulses with optional interrupts. +#define AM_HAL_CTIMER_FN_REPEAT _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 1) +//! Single Pulse (One Shot): A single pulse of programmed width, with an optional interrupt. +#define AM_HAL_CTIMER_FN_PWM_ONCE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 2) +//! Repeated Pulse: A rectangular (or square) waveform with programmed high and +//! low widths, and optional interrupts on each cycle. +#define AM_HAL_CTIMER_FN_PWM_REPEAT _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 3) +//! Single Pattern: one burst of bits specified by the CMPR0/1/2/3 registers. +#define AM_HAL_CTIMER_FN_PTN_ONCE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 4) +//! Repeated Pattern: repeated burst of bits specified by the CMPR0/1/2/3 registers. +#define AM_HAL_CTIMER_FN_PTN_REPEAT _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 5) +//! Continuous: Free running timer with a single level change on the output and +//! a single optional interrupt. +#define AM_HAL_CTIMER_FN_CONTINUOUS _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 6) +//! Alternate Pulse: like Repeated Pulse but alternating between two different +//! pulse width/spacing settings. +#define AM_HAL_CTIMER_FN_PWM_ALTERNATE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 7) +//! @} + +//***************************************************************************** +// +//! Half-timer options. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_INT_ENABLE CTIMER_CTRL0_TMRA0IE0_Msk +//#define AM_HAL_CTIMER_PIN_ENABLE CTIMER_CTRL0_TMRA0PE_Msk +#define AM_HAL_CTIMER_PIN_INVERT CTIMER_CTRL0_TMRA0POL_Msk +#define AM_HAL_CTIMER_CLEAR CTIMER_CTRL0_TMRA0CLR_Msk +//! @} + +//***************************************************************************** +// +//! Additional timer options. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_LINK CTIMER_CTRL0_CTLINK0_Msk +#define AM_HAL_CTIMER_ADC_TRIG CTIMER_CTRL3_ADCEN_Msk +//! @} + +//***************************************************************************** +// +//! Timer selection macros. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_TIMERA 0x0000FFFF +#define AM_HAL_CTIMER_TIMERB 0xFFFF0000 +#define AM_HAL_CTIMER_BOTH 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! Timer trigger options for Apollo3 Blue (rev B0 and later) including +//! Apollo3 Blue Plus. +//! +//! Valid only for CTIMER4 and CTIMER5 when CTLINK==1 and TMRA4TRIG==1 +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP0 CTIMER_AUX4_TMRB4TRIG_A7OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP1 CTIMER_AUX4_TMRB4TRIG_B7OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP2 CTIMER_AUX4_TMRB4TRIG_A1OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP3 CTIMER_AUX4_TMRB4TRIG_B1OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP0 CTIMER_AUX4_TMRB4TRIG_B3OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP1 CTIMER_AUX4_TMRB4TRIG_A3OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP2 CTIMER_AUX4_TMRB4TRIG_A1OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP3 CTIMER_AUX4_TMRB4TRIG_B1OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP4 CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP5 CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP6 CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP7 CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL + +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP0 CTIMER_AUX5_TMRB5TRIG_A7OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP1 CTIMER_AUX5_TMRB5TRIG_B7OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP2 CTIMER_AUX5_TMRB5TRIG_A1OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP3 CTIMER_AUX5_TMRB5TRIG_B1OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP0 CTIMER_AUX5_TMRB5TRIG_B3OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP1 CTIMER_AUX5_TMRB5TRIG_A3OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP2 CTIMER_AUX5_TMRB5TRIG_A1OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP3 CTIMER_AUX5_TMRB5TRIG_B1OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP4 CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP5 CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP6 CTIMER_AUX5_TMRB5TRIG_B5OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP7 CTIMER_AUX5_TMRB5TRIG_A5OUT2DUAL +//! @} + +//***************************************************************************** +// +//! @name All-In-One Configuration +//! @brief New API for multiple timer configuration. +//! +//! These options are to be used with the \e am_hal_ctimer_config_t structure +//! used by \e am_hal_ctimer_config +//! @{ +// +//***************************************************************************** +//! CTimer AIO Compare Configuration. +typedef struct +{ + // + //! Function Number. + // + uint32_t FN; + // + //! Timer Segment. Timer A, B, BOTH selector. + // + uint32_t AB; + // + //! Compare Register A0. + // + uint32_t A0; + // + //! Compare Register A1. + // + uint32_t A1; + // + //! Compare Register A2. + // + uint32_t A2; + // + //! Compare Register A3. + // + uint32_t A3; + // + //! Compare Register B0. + // + uint32_t B0; + // + //! Compare Register B1. + // + uint32_t B1; + // + //! Compare Register B2. + // + uint32_t B2; + // + //! Compare Register B3. + // + uint32_t B3; + // + //! LMT field values. + // + uint32_t LMT; + // + //! A "T" indicates that a 1 is loaded if the OUT2 output is used, otherwise a 0 is loaded. + // + uint32_t EN23; + // + //! TRIG: a single pattern will be triggered; TERM: a repeated pattern will be terminated. + // + uint32_t TRIG; + // + //! Select clock source: internal, external, a buck pulse, or output of another CTIMER. + // + uint32_t CLK; + // + //! Enable the primary interrupt INT. + // + uint32_t IE0; + // + //! Enable the secondary interrupt INT2. + // + uint32_t IE1; + // + //! Select the polarity of the OUT output. + // + uint32_t POL; + // + //! Select the polarity of the OUT2 output. + // + uint32_t POL23; + // + //! Select polarity of both OUT and OUT2 as a function of the trigger input. + // + uint32_t TINV; + // + //! Disable clock synchronization on read. + // + uint32_t NOSYNC; + // + //! Enable the timer. + // This is ANDed with the global enable in GLOBEN, and allows the counter to begin counting. + // + uint32_t EN; + // + // Clear the timer. This will hold the timer at zero even if EN is asserted. + // It is typically cleared at the end of a configuration and + // is probably not included in the function structure. + // + //uint32_t CLR; + +} +am_hal_ctimer_aio_config_t; + +//! CTimer AIO Output Selection and Interconnect. +typedef struct +{ + //! Pad 0-9 + uint32_t OUTCFG0; + //! Pad 10-19 + uint32_t OUTCFG1; + //! Pad 20-29 + uint32_t OUTCFG2; + //! Pad 30-31 + uint32_t OUTCFG3; +} +am_hal_ctimer_aio_connect_t; +//! @} + +//***************************************************************************** +// +//! Timer configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Set to 1 to operate this timer as a 32-bit timer instead of two 16-bit + //! timers. + // + uint32_t ui32Link; + + // + //! Configuration options for TIMERA + // + uint32_t ui32TimerAConfig; + + // + //! Configuration options for TIMERB + // + uint32_t ui32TimerBConfig; + +} +am_hal_ctimer_config_t; + +//***************************************************************************** +// +//! Function pointer type for CTimer interrupt handlers. +// +//***************************************************************************** +typedef void (*am_hal_ctimer_handler_t)(void); + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_ctimer_globen(uint32_t ui32ConfigVal); + +extern void am_hal_ctimer_config(uint32_t ui32TimerNumber, + am_hal_ctimer_config_t *psConfig); + +extern void am_hal_ctimer_config_single(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal); + +extern void am_hal_ctimer_config_trigger(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32ConfigVal); + +extern void am_hal_ctimer_start(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_stop(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern void am_hal_ctimer_clear(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment); + +extern uint32_t am_hal_ctimer_output_config(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32PadNum, + uint32_t eOutputType, + uint32_t eDriveStrength); + +extern void am_hal_ctimer_input_config(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32TimerOutputConfig); + +extern void am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, + uint32_t ui32Value); + +extern void am_hal_ctimer_aux_compare_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32CompareReg, + uint32_t ui32Value); + +extern void am_hal_ctimer_period_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32Period, + uint32_t ui32OnTime); + +extern void am_hal_ctimer_aux_period_set(uint32_t ui32TimerNumber, + uint32_t ui32TimerSegment, + uint32_t ui32Period, + uint32_t ui32OnTime); + +extern void am_hal_ctimer_adc_trigger_enable(void); +extern void am_hal_ctimer_adc_trigger_disable(void); +extern void am_hal_ctimer_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_ctimer_int_enable_get(void); +extern void am_hal_ctimer_int_disable(uint32_t ui32Interrupt); +extern void am_hal_ctimer_int_set(uint32_t ui32Interrupt); +extern void am_hal_ctimer_int_clear(uint32_t ui32Interrupt); +extern uint32_t am_hal_ctimer_int_status_get(bool bEnabledOnly); +extern void am_hal_ctimer_int_register(uint32_t ui32Interrupt, + am_hal_ctimer_handler_t pfnHandler); +extern void am_hal_ctimer_int_service(uint32_t ui32Status); + +// +// General function to do triple back-to-back reads. +// +extern void am_hal_triple_read(uint32_t u32TimerAddr, uint32_t ui32Data[]); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_CTIMER_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.c new file mode 100644 index 0000000000..e112781bf4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.c @@ -0,0 +1,96 @@ +//***************************************************************************** +// +// am_hal_debug.c +//! @file +//! +//! @brief Useful functions for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +//! +//! @addtogroup haldebug3 HAL Debug/Assert Utilities +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Default implementation of a failed ASSERT statement. +//! +//! @param pcFile is the name of the source file where the error occurred. +//! @param ui32Line is the line number where the error occurred. +//! @param pcMessage is an optional message describing the failure. +//! +//! This function is called by am_hal_debug_assert() macro when the supplied +//! condition is not true. The implementation here simply halts the application +//! for further analysis. Individual applications may define their own +//! implementations of am_hal_debug_error() to provide more detailed feedback +//! about the failed am_hal_debug_assert() statement. +//! +//! @return Never. +// +//***************************************************************************** +#if defined (__IAR_SYSTEMS_ICC__) +__weak void +#else +void __attribute__((weak)) +#endif +am_hal_debug_error(const char *pcFile, uint32_t ui32Line, const char *pcMessage) +{ + // + // Halt for analysis. + // + while(1); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.h new file mode 100644 index 0000000000..dfc4a86b1e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_debug.h @@ -0,0 +1,141 @@ +//***************************************************************************** +// +// am_hal_debug.h +//! @file +//! +//! @brief Useful macros for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +//! +//! @addtogroup haldebug3 HAL Debug/Assert Utilities +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_DEBUG_H +#define AM_HAL_DEBUG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Determine DBG_FILENAME +// +//***************************************************************************** +// +// By spec and convention, the standard __FILE__ compiler macro includes a full +// path (absolute or relative) to the file being compiled. This makes recreating +// binaries virtually impossible unless rebuilt on the same or identically +// configured system. +// +// To be able to build consistent binaries on different systems, we want to make +// sure the full pathname is not included in the binary. Only IAR EWARM provides +// an easy mechanism to provide only the filename without the path. For other +// platforms, we will simply use a generic pathname. +// +#if defined (__IAR_SYSTEMS_ICC__) +// +// With EWARM the --no_path_in_file_macros option reduces __FILE__ to only the +// module name. Therefore this define assumes the option is being used. +// +#define DBG_FILENAME __FILE__ +#elif defined(__KEIL__) +// +// Keil provides __MODULE__ which is simply the module name portion of __FILE__. +// +#define DBG_FILENAME __MODULE__ +#elif defined(__ARMCC_VERSION) +#define DBG_FILENAME __FILE__ +#else +// +// With GCC, we're out of luck. +// +#define DBG_FILENAME "debug_filename.ext" +//#define DBG_FILENAME __FILE__ +#endif + +//***************************************************************************** +// +// Debug assert macros. +// +//***************************************************************************** +#ifndef AM_HAL_DEBUG_NO_ASSERT + +#define am_hal_debug_assert_msg(bCondition, pcMessage) \ + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, pcMessage) + +#define am_hal_debug_assert(bCondition) \ + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, 0) + +#else + +#define am_hal_debug_assert_msg(bCondition, pcMessage) +#define am_hal_debug_assert(bCondition) + +#endif // AM_DEBUG_ASSERT + +//***************************************************************************** +// +// External function prototypes. +// +//***************************************************************************** +extern void am_hal_debug_error(const char *pcFile, uint32_t ui32Line, + const char *pcMessage); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_DEBUG_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.c new file mode 100644 index 0000000000..ed9d94517b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.c @@ -0,0 +1,1883 @@ +//***************************************************************************** +// +// am_hal_flash.c +//! @file +//! +//! @brief Functions for performing Flash operations. +//! +//! IMPORTANT: Interrupts are active during execution of all HAL flash +//! functions. If an interrupt occurs during execution of a flash function +//! that programs or erases flash or INFO space, errors will occur if the +//! interrupt service routine (ISR) is located in on-chip flash. +//! If interrupts are expected during execution of a flash function that +//! programs or erases either flash or INFO space: +//! - Interrupts must be disabled via a critical section handler prior to +//! calling the flash function. +//! - Alternatively, applicable ISRs must be located in non-flash address space +//! (i.e. SRAM, off-chip ROM, etc.). +//! +//! @addtogroup flash3 Flash +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +// +// Look-up table +// +const g_am_hal_flash_t g_am_hal_flash = +{ + ((int (*)(uint32_t, uint32_t)) 0x0800004d), // flash_mass_erase + ((int (*)(uint32_t, uint32_t, uint32_t)) 0x08000051), // flash_page_erase + ((int (*)(uint32_t, uint32_t *, uint32_t *, uint32_t)) 0x08000055), // flash_program_main + ((int (*)(uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t))0x08000059), // flash_program_info_area + ((int (*)(uint32_t, uint32_t)) 0x0800006d), // flash_mass_erase_nb + ((int (*)(uint32_t, uint32_t, uint32_t)) 0x08000071), // flash_page_erase_nb + ((int (*)( uint32_t, uint32_t)) 0x08000095), // flash_page_erase2_nb + ((bool (*)(void)) 0x0800007d), // flash_nb_operation_complete + ((uint32_t (*)(uint32_t *)) 0x08000075), // flash_util_read_word + ((void (*)( uint32_t *, uint32_t)) 0x08000079), // flash_util_write_word + ((void (*)(uint32_t )) 0x0800009D), // bootrom_delay_cycles + ((int (*)( uint32_t, uint32_t)) 0x08000081), // flash_info_erase + ((int (*)( uint32_t, uint32_t)) 0x08000089), // flash_info_plus_main_erase + ((int (*)(uint32_t)) 0x08000091), // flash_info_plus_main_erase_both + ((int (*)( uint32_t )) 0x08000099), // flash_recovery + ((void (*)(void)) 0x0800005d), // flash_program_main_from_sram + ((void (*)(void)) 0x08000061), // flash_program_info_area_from_sram + ((void (*)(void)) 0x08000065), // flash_erase_main_pages_from_sram + ((void (*)(void)) 0x08000069), // flash_mass_erase_from_sram + ((void (*)(void)) 0x08000085), // flash_info_erase_from_sram + ((void (*)(void)) 0x0800008D), // flash_info_plus_main_erase_from_sram + ((void (*)(void)) 0x080000A1), // flash_nb_operation_complete_from_sram + ((void (*)(void)) 0x080000A5), // flash_page_erase2_nb_from_sram + ((void (*)(void)) 0x080000A9) // flash_recovery_from_sram +}; + +const uint32_t ui32SramMaxAddr = (AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR + 1); +//***************************************************************************** +// +//! @brief This function performs a mass erase on a flash instance. +//! +//! @param ui32ProgramKey - The flash program key. +//! @param ui32FlashInst - The flash instance to erase. +//! +//! This function will erase the desired instance of flash. +//! +//! @note For Apollo3, each flash instance contains a maximum of 512KB. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 ui32FlashInst is invalid. +//! 3 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_mass_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst) +{ + return g_am_hal_flash.flash_mass_erase(ui32ProgramKey, ui32FlashInst); +} // am_hal_flash_mass_erase() + +//***************************************************************************** +// +//! @brief This function performs a page erase on a flash instance. +//! +//! @param ui32ProgramKey - The flash program key. +//! @param ui32FlashInst - The flash instance to reference the page number with. +//! @param ui32PageNum - The flash page relative to the specified instance. +//! +//! This function will erase the desired flash page in the desired instance of +//! flash. +//! +//! @note For Apollo3, each flash page is 8KB (or AM_HAL_FLASH_PAGE_SIZE). +//! Each flash instance contains a maximum of 64 pages (or +//! AM_HAL_FLASH_INSTANCE_PAGES). +//! +//! @note When given an absolute flash address, a couple of helpful macros can +//! be utilized when calling this function. +//! For example: +//! am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, +//! AM_HAL_FLASH_ADDR2INST(ui32Addr), +//! AM_HAL_FLASH_ADDR2PAGE(ui32Addr) ); +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 ui32FlashInst is invalid. +//! 3 ui32PageNum is invalid. +//! 4 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_page_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst, + uint32_t ui32PageNum) +{ + return g_am_hal_flash.flash_page_erase(ui32ProgramKey, + ui32FlashInst, + ui32PageNum); +} // am_hal_flash_page_erase() + +//***************************************************************************** +// +//! @brief This programs up to N words of the Main array on one flash instance. +//! +//! @param ui32ProgramKey - The programming key, AM_HAL_FLASH_PROGRAM_KEY. +//! @param pui32Src - Pointer to word aligned array of data to program into +//! the flash instance. +//! @param pui32Dst - Pointer to the word aligned flash location where +//! programming of the flash instance is to begin. +//! @param ui32NumWords - The number of words to be programmed. +//! +//! This function will program multiple words in main flash. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 pui32Dst is invalid. +//! 3 Flash addressing range would be exceeded. That is, (pui32Dst + +//! (ui32NumWords * 4)) is greater than the last valid address. +//! 4 pui32Src is invalid. +//! 5 Unused - will never be returned. +//! 6 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_program_main(uint32_t ui32ProgramKey, uint32_t *pui32Src, + uint32_t *pui32Dst, uint32_t ui32NumWords) +{ + uint32_t ui32MaxSrcAddr = (uint32_t)pui32Src + (ui32NumWords << 2); + + // + // Workaround, the last word of SRAM cannot be the source + // of programming by BootRom, check to see if it is the last + // + if ( ui32MaxSrcAddr == ui32SramMaxAddr ) + { + uint32_t ui32Temp; + int iRetVal; + + // + // program the other words using the boot-rom function + // + if ( ui32NumWords > 1 ) + { + iRetVal = g_am_hal_flash.flash_program_main( + ui32ProgramKey, + pui32Src, + pui32Dst, + ui32NumWords - 1); + + // + // return if anything wrong + // + if ( iRetVal != 0 ) + { + return iRetVal; + } + } + + // + // program the last word of the pSrc from a local + // variable if it is the last word of SRAM + // + ui32Temp = *(uint32_t *)(ui32MaxSrcAddr - 4); + + return g_am_hal_flash.flash_program_main( + ui32ProgramKey, + &ui32Temp, + pui32Dst + ui32NumWords - 1, + 1); + } + + return g_am_hal_flash.flash_program_main(ui32ProgramKey, pui32Src, + pui32Dst, ui32NumWords); +} // am_hal_flash_program_main() + + +//***************************************************************************** +// +//! @brief This clears the specified bits in the addressed flash word +//! +//! @param ui32ProgramKey - The programming key, AM_HAL_FLASH_PROGRAM_KEY. +//! @param pui32Addr - Pointer to word aligned flash word to program into +//! @param ui32BitMask - The bits to be cleared +//! +//! This function will clear one of more bits in a word in main flash. +//! This function is mainly used when the same word is to be written multiple times +//! few bits at a time, between erase cycle +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @note We can reprogram a bit in flash to 0 only once. This function takes +//! care of not re-clearing bits if they are already programmed as 0 +//! +//! @return 0 for success, non-zero for failure. +//! +//! Note: See am_hal_flash_program_main() for further details on return codes. +// +//***************************************************************************** +int +am_hal_flash_clear_bits(uint32_t ui32ProgramKey, uint32_t *pui32Addr, + uint32_t ui32BitMask) +{ + uint32_t ui32Val = ~ui32BitMask; + + // + // CAUTION: We can reprogram a bit in flash to 0 only once...so make sure + // that we do not re-clear bits + // + ui32Val |= ~(*pui32Addr); + + return g_am_hal_flash.flash_program_main(ui32ProgramKey, &ui32Val, + pui32Addr, 1); +} // am_hal_flash_clear_bits() + +//***************************************************************************** +// +//! @brief This function programs multiple words in the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space key. +//! @param ui32InfoInst - The INFO space instance, 0 or 1. +//! @param *pui32Src - Pointer to word aligned array of data to program into +//! the customer INFO space. +//! @param ui32Offset - Word offset into customer INFO space (offset of 0 is +//! the first word, 1 is second word, etc.). +//! @param ui32NumWords - The number of words to be programmed, must not +//! exceed AM_HAL_FLASH_INFO_SIZE/4. +//! +//! This function will program multiple words in the customer INFO space. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32InfoInst is invalid. +//! 3 ui32Offset is invalid. +//! 4 INFO addressing range would be exceeded. That is, (ui32Offset + +//! ui32NumWords) is greater than the last valid address. +//! 5 pui32Src is invalid. +//! 6 pui32Src is invalid. +//! 7 Hardware error. +//! 8 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_program_info(uint32_t ui32InfoKey, uint32_t ui32InfoInst, + uint32_t *pui32Src, uint32_t ui32Offset, + uint32_t ui32NumWords) +{ + uint32_t ui32MaxSrcAddr = (uint32_t)pui32Src + (ui32NumWords << 2); + + // + // workround, the last word of SRAM cannot be the source + // of programming by BootRom, check to see if it is the last + // + if ( ui32MaxSrcAddr == ui32SramMaxAddr ) + { + uint32_t ui32Temp; + int iRetVal; + + // + // program the other words using the boot-rom function + // + if ( ui32NumWords > 1 ) + { + iRetVal = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + ui32InfoInst, + pui32Src, + ui32Offset, + ui32NumWords - 1); + + // + // return if anything wrong + // + if ( iRetVal != 0 ) + { + return iRetVal; + } + } + + // + // program the last word of the pSrc from a local + // variable if it is the last word of SRAM + // + ui32Temp = *(uint32_t *)(ui32MaxSrcAddr - 4); + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + ui32InfoInst, + &ui32Temp, + ui32Offset + ui32NumWords - 1, + 1); + } + + return g_am_hal_flash.flash_program_info_area(ui32InfoKey, ui32InfoInst, pui32Src, + ui32Offset, ui32NumWords); + +} // am_hal_flash_program_info() + +//***************************************************************************** +// +//! @brief This function erases an instance of the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! (AM_HAL_FLASH_INFO_KEY). +//! @param ui32Inst - The flash instance, either 0 or 1. +//! +//! This function will erase the the customer INFO space of the specified +//! instance. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32Inst is invalid. +//! 3 Hardware error. +//! 4 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_erase_info(uint32_t ui32InfoKey, + uint32_t ui32Inst) +{ + return g_am_hal_flash.flash_info_erase(ui32InfoKey, ui32Inst); +} // am_hal_flash_erase_info() + +//***************************************************************************** +// +//! @brief This function erases the main instance + the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space key. +//! @param ui32Inst - The flash instance, either 0 or 1. +//! +//! This function will erase the main flash + the customer INFO space of the +//! specified instance. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32Inst is invalid. +//! 3 Hardware error. +//! 4 Flash controller hardware timeout. +//! 11 Internal error. +//! 12 Internal error. +//! 13 Flash controller hardware timeout. +// +//***************************************************************************** +int +am_hal_flash_erase_main_plus_info(uint32_t ui32InfoKey, + uint32_t ui32Inst) +{ + return g_am_hal_flash.flash_info_plus_main_erase(ui32InfoKey, + ui32Inst); +} // am_hal_flash_erase_main_plus_info() + +//***************************************************************************** +// +//! @brief This function erases the main flash + the customer INFO space. +//! +//! @param ui32InfoKey - The customer INFO space key. +//! +//! This function will erase both instances the main flash + the +//! customer INFO space. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid, instance 0. +//! 2 Internal error, instance 0. +//! 3 Hardware error, instance 0. +//! 4 Flash controller hardware timeout, instance 0. +//! 11 Internal error. +//! 12 Internal error. +//! 13 Flash controller hardware timeout. +//! 21 ui32InfoKey is invalid, instance 1. +//! 22 Internal error, instance 1. +//! 23 Hardware error, instance 1. +//! 24 Flash controller hardware timeout, instance 1. +//! 31 Internal error, instance 1. +//! 32 Internal error, instance 1. +//! 33 Flash controller hardware timeout, instance 1. +// +//***************************************************************************** +int +am_hal_flash_erase_main_plus_info_both_instances(uint32_t ui32InfoKey) +{ + return g_am_hal_flash.flash_info_plus_main_erase_both(ui32InfoKey); +} // am_hal_flash_erase_main_plus_info_both_instances() + +//***************************************************************************** +// +//! @brief This function erases both main flash instances + both customer INFO +//! space instances. +//! +//! @param ui32RecoveryKey - The recovery key. +//! +//! This function erases both main instances and both customer INFOinstances +//! even if the customer INFO space is programmed to not be erasable. This +//! function completely erases the flash main and info instances and wipes the +//! SRAM. Upon completion of the erasure operations, it does a POI (power on +//! initialization) reset. +//! +//! @note The customer key lock is enforced by this function. Therefore, the +//! customer key must be written prior to calling otherwise, the function will +//! fail. Therefore, always check for a return code. If the function returns, +//! a failure has occured. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Does not return if successful. Returns failure code otherwise. +//! Failing return code indicates: +//! 0x00000001 ui32RecoveryKey is invalid. +//! 0x00000002 Customer key lock not set. +//! 0x00001001 Internal error. +//! 0x00001002 Internal error. +//! 0x00001003 Info erase, instance 0 - hardware error. +//! 0x00001004 Info erase, instance 0 - flash controller hardware timeout. +//! 0xi000ppee Error erasing page in instance, pp=page number, ee=error code. +//! i=2|3, instance 0. +//! i=4|5, instance 1. +//! ee=1|2|3 Internal or hardware error. +//! ee=4 Flash controller hardware timeout. +// +//***************************************************************************** +void +am_hal_flash_recovery(uint32_t ui32RecoveryKey) +{ + g_am_hal_flash.flash_recovery(ui32RecoveryKey); +} // am_hal_flash_recovery() + +//***************************************************************************** +// +//! @brief Use the bootrom to implement a spin loop. +//! +//! @param ui32Iterations - Number of iterations to delay. +//! +//! Use this function to implement a CPU busy waiting spin loop without cache +//! or delay uncertainties. +//! +//! Notes for Apollo3: +//! - The ROM-based function executes at 3 cycles per iteration plus the normal +//! function call, entry, and exit overhead and latencies. +//! - Cache settings affect call overhead. However, the cache does not affect +//! the time while inside the BOOTROM function. +//! - The function accounts for burst vs normal mode, along with some of the +//! overhead encountered with executing the function itself (such as the +//! check for burst mode). +//! - Use of the FLASH_CYCLES_US() or FLASH_CYCLES_US_NOCACHE() macros for the +//! ui32Iterations parameter will result in approximate microsecond timing. +//! - The parameter ui32Iterations==0 is allowed but is still incurs a delay. +//! +//! Example: +//! - MCU operating at 48MHz -> 20.83 ns / cycle +//! - Therefore each iteration (once inside the bootrom function) will consume +//! 62.5ns (non-burst-mode). +//! +//! @note Interrupts are not disabled during execution of this function. +//! Therefore, any interrupt taken will affect the delay timing. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_flash_delay(uint32_t ui32Iterations) +{ + // + // The read of the FREQCTRL register in order to check for burst mode + // could take up to 13 cycles, and almost double if in burst mode. + // There are also overhead delays encountered in this function, such + // as computing the cycle count adjustment itself. + // Let's account for these delays as much as possible. + // + register uint32_t ui32CycleCntAdj; + + if ( am_hal_burst_mode_status() == AM_HAL_BURST_MODE ) + { + ui32Iterations <<= 1; + + // + // There's an additional shift to account for. + // + ui32CycleCntAdj = ((13 * 2) + 16) / 3; + } + else + { + ui32CycleCntAdj = ((13 * 1) + 20) / 3; + } + + // + // Allow for the overhead of the burst-mode check and these comparisons + // by eliminating an appropriate number of iterations. + // + if ( ui32Iterations > ui32CycleCntAdj ) + { + ui32Iterations -= ui32CycleCntAdj; + + g_am_hal_flash.bootrom_delay_cycles(ui32Iterations); + } + +} // am_hal_flash_delay() + +//***************************************************************************** +// +//! @brief Delays for a desired amount of cycles while also waiting for a +//! status to change a value. +//! +//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops. +//! @param ui32Address - Address of the register for the status change. +//! @param ui32Mask - Mask for the status change. +//! @param ui32Value - Target value for the status change. +//! +//! This function will delay for approximately the given number of microseconds +//! while checking for a status change, exiting when either the given time has +//! expired or the status change is detected. +//! +//! @returns 0 = timeout. +//! 1 = status change detected. +// +//***************************************************************************** +uint32_t +am_hal_flash_delay_status_change(uint32_t ui32usMaxDelay, uint32_t ui32Address, + uint32_t ui32Mask, uint32_t ui32Value) +{ + while ( 1 ) + { + // + // Check the status + // + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) + { + return AM_HAL_STATUS_SUCCESS; + } + + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + break; + } + } + + return AM_HAL_STATUS_TIMEOUT; + +} // am_hal_flash_delay_status_change() + +//***************************************************************************** +// +//! @brief Delays for a desired amount of cycles while also waiting for a +//! status to equal OR not-equal to a value. +//! +//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops. +//! @param ui32Address - Address of the register for the status change. +//! @param ui32Mask - Mask for the status change. +//! @param ui32Value - Target value for the status change. +//! @param bIsEqual - Check for equal if true; not-equal if false. +//! +//! This function will delay for approximately the given number of microseconds +//! while checking for a status change, exiting when either the given time has +//! expired or the status change is detected. +//! +//! @returns 0 = timeout. +//! 1 = status change detected. +// +//***************************************************************************** +uint32_t +am_hal_flash_delay_status_check(uint32_t ui32usMaxDelay, uint32_t ui32Address, + uint32_t ui32Mask, uint32_t ui32Value, + bool bIsEqual) +{ + while ( 1 ) + { + // + // Check the status + // + if ( bIsEqual ) + { + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) + { + return AM_HAL_STATUS_SUCCESS; + } + } + else + { + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) != ui32Value ) + { + return AM_HAL_STATUS_SUCCESS; + } + } + + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + break; + } + } + + return AM_HAL_STATUS_TIMEOUT; + +} // am_hal_flash_delay_status_check() + +//***************************************************************************** +// +//! @brief Static Helper Function to check customer info valid bits erasure. +//! +//! Use this function to test the state of the 128 valid bits at the beginning +//! of customer info space. If these are all erased then return true. +//! +//! @return true if the customer info bits are currently erased. +// +//***************************************************************************** +static bool +customer_info_signature_erased(void) +{ + uint32_t *pui32Signature = (uint32_t *) AM_HAL_FLASH_INFO_ADDR; + + return ( (pui32Signature[3] == 0xFFFFFFFF) && + (pui32Signature[2] == 0xFFFFFFFF) && + (pui32Signature[1] == 0xFFFFFFFF) && + (pui32Signature[0] == 0xFFFFFFFF) ) ? true : false; + +} // customer_info_signature_erased() + +//***************************************************************************** +// +//! @brief Static Helper Function to set customer info valid bits +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space. If these bits are not set correctly then the +//! customer protection bits in the INFO space will not be honored by the +//! hardware. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +static int +customer_info_signature_set(uint32_t ui32InfoKey) +{ + uint32_t ui32Valid[4]; + int iRC; + + // + // If they are already set then we are done. + // + if ( am_hal_flash_customer_info_signature_check() ) + { + return 0; + } + + // + // If they are not erased at this point we have an error. + // + if ( !customer_info_signature_erased() ) + { + return (2 << 16); + } + + // + // OK they need to be set so do it. + // + ui32Valid[3] = AM_HAL_FLASH_INFO_SIGNATURE3; + ui32Valid[2] = AM_HAL_FLASH_INFO_SIGNATURE2; + ui32Valid[1] = AM_HAL_FLASH_INFO_SIGNATURE1; + ui32Valid[0] = AM_HAL_FLASH_INFO_SIGNATURE0; + + iRC = g_am_hal_flash.flash_program_info_area(ui32InfoKey, + 0, // instance + ui32Valid, // source data + 0, // offset + 4); // number of words + + // + // See am_hal_flash_program_info() for further details on return codes. + // + return iRC | ((iRC) ? (1 << 16) : 0); + +} // customer_info_signature_set() + +//***************************************************************************** +// +//! @brief Check that the customer info bits are valid. +//! +//! Use this function to test the state of the 128 valid bits at the beginning +//! of customer info space. If these are not set correctly then the customer +//! protection bits in the INFO space will not be honored by the hardware. +//! +//! @return true if valid. +// +//***************************************************************************** +bool +am_hal_flash_customer_info_signature_check(void) +{ + uint32_t *pui32Signature = (uint32_t *)AM_HAL_FLASH_INFO_ADDR; + + return ( (pui32Signature[3] == AM_HAL_FLASH_INFO_SIGNATURE3) && + (pui32Signature[2] == AM_HAL_FLASH_INFO_SIGNATURE2) && + (pui32Signature[1] == AM_HAL_FLASH_INFO_SIGNATURE1) && + (pui32Signature[0] == AM_HAL_FLASH_INFO_SIGNATURE0) ); + +} // am_hal_flash_customer_info_signature_check() + +//***************************************************************************** +// +//! @brief INFO signature set. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +bool +am_hal_flash_info_signature_set(uint32_t ui32InfoKey) +{ + // + // Check and set signature. + // + return customer_info_signature_set(ui32InfoKey) ? false : true; + +} // am_hal_flash_info_signature_set() + +//***************************************************************************** +// +//! @brief Disable FLASH INFO space. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then disable FLASH erasure. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_info_erase_disable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear bit in INFO space to disable erasure. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_info_erase_disable() + +//***************************************************************************** +// +//! @brief Check for Disabled FLASH INFO space. +//! +//! Use this function to determine whether FLASH INFO erasure is disabled. +//! +//! @return true if FLASH INFO erase is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_info_erase_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not valid at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SRAM WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M ? false : true; + +} // am_hal_flash_info_erase_disable_check() + +//***************************************************************************** +// +//! @brief Mask off 1 to 4 quadrants of FLASH INFO space for programming. +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then and the mask bits with the INFO +//! space programming disable bits. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! @param ui32Mask - A mask of the 4 quadrants of info space where +//! bit0 = First quadrant (first 2KB). +//! bit1 = Second quadrant (second 2KB). +//! bit2 = Third quadrant (third 2KB). +//! bit3 = Fourth quadrant (fourth 2KB). +//! +//! @note This function disables only, any quadrant already disabled is not +//! reenabled. That is, any ui32Mask bits specified as 0 are essentially nops. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_info_program_disable(uint32_t ui32InfoKey, uint32_t ui32Mask) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Make sure we have a valid mask and get the mask into the correct position. + // + ui32Mask <<= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S; + ui32Mask &= AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M; + + // + // The security bit set to 1 enables programming, 0 disables programming. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & ~ui32Mask; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_info_program_disable() + +//***************************************************************************** +// +//! @brief Return a mask specifying which quadrants of customer INFO space have +//! been disabled for programming. +//! +//! Use this function to determine whether programming of customer INFO space +//! has been disabled. +//! +//! @return A 4-bit mask of the disabled quadrants. +//! 0xFFFFFFFF indicates an error. +//! 0x0 indicates all customer INFO space programming is enabled. +//! 0xF indicates all customer INFO space programming is disabled. +//! bit0 indicates the first customer INFO space is disabled for programming. +//! bit1 indicates the second customer INFO space is disabled for programming. +//! bit2 indicates the third customer INFO space is disabled for programming. +//! bit3 indicates the fourth customer INFO space is disabled for programming. +// +//***************************************************************************** +uint32_t +am_hal_flash_info_program_disable_get(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return 0xFFFFFFFF; + } + + // + // If not valid at this point, then INFO programming can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return 0xFFFFFFFF; + } + + // + // Looking good so far, now return a mask of the disabled bits. + // + return ((AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) ^ + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M) >> + AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S; + +} // am_hal_flash_info_program_disable_get() + +//***************************************************************************** +// +//! @brief Enable FLASH debugger protection (FLASH gets wiped if a debugger is +//! connected). +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then set the FLASH wipe bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_wipe_flash_enable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the FLASH Wipe bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_wipe_flash_enable() + +//***************************************************************************** +// +//! @brief check for FLASH wipe protection enabled. +//! +//! Use this function to determine if FLASH wipe protection is enabled. +//! +//! @return true if FLASH wipe protection is enabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_wipe_flash_enable_check(void) +{ + // + // If they are erased at this point then flash wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not valid at this point then flash wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the Flash WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M ? false : true; + +} // am_hal_flash_wipe_flash_enable_check() + +//***************************************************************************** +// +//! @brief Enable SRAM protection so SRAM gets wiped if a debgger is connected. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Then set the SRAM wipe bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_wipe_sram_enable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the SRAM Wipe bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_wipe_sram_enable() + +//***************************************************************************** +// +//! @brief check for SRAM protection enabled. +//! +//! Use this function to determine if SRAM protection is enabled. +//! +//! @return true if SRAM wipe protection is enabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_wipe_sram_enable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SRAM WIPE bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M ? false : true; + +} // am_hal_flash_wipe_sram_enable_check() + +//***************************************************************************** +// +//! @brief Disable Output from ITM/SWO. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Set the SWO disable bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_swo_disable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the SWO bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_swo_disable() + +//***************************************************************************** +// +//! @brief check for SWO disabled. +//! +//! Use this function to determine if the SWO is disabled. +//! +//! @return true if the ITM/SWO is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_swo_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the SWO bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M ? false : true; + +} // am_hal_flash_swo_disable_check() + +//***************************************************************************** +// +//! @brief Disable Connections from a debugger on the SWD interface. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! +//! Use this function to set the state of the 128 valid bits at the beginning +//! of customer info space, if needed. Set the debugger disable bit to zero. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_debugger_disable(uint32_t ui32InfoKey) +{ + int iRC; + uint32_t ui32SecurityValue; + + // + // Security protection only works if the signature data is correct. + // + iRC = customer_info_signature_set(ui32InfoKey); + if ( iRC ) + { + return iRC; + } + + // + // Clear the DEBUGGER bit. + // + ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + ~AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M; + + // + // Now write the word to the flash INFO space. + // + return g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32SecurityValue, // source data + AM_HAL_FLASH_INFO_SECURITY_O / 4, // word offset + 1 ); // number of words + +} // am_hal_flash_debugger_disable() + +//***************************************************************************** +// +//! @brief check for debugger disabled. +//! +//! Use this function to determine if the debugger is disabled. +//! +//! @return true if the debugger is disabled, otherwise false. +// +//***************************************************************************** +bool +am_hal_flash_debugger_disable_check(void) +{ + // + // If they are erased at this point then SRAM wipe can't be enabled. + // + if ( customer_info_signature_erased() ) + { + return false; + } + + // + // If they are not vale at this point then SRAM wipe can't be enabled. + // + if ( !am_hal_flash_customer_info_signature_check() ) + { + return false; + } + + // + // Looking good so far, now check the debugger disable bit. + // + return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & + AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M ? false : true; + +} // am_hal_flash_debugger_disable_check() + +//***************************************************************************** +// +//! @brief This static helper function generates a 64-bit protection mask. +//! +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function computes a chunk map for the protection range. +//! +//! @return Inverse of the actual chunk mask. That is, chunks to be protected +//! are represented as 0 in the returned mask, while chunks to be left alone +//! are represented as 1. This value can therefore be directly ANDed with the +//! existing bits in INFO space. +//! Note that -1 is returned if input parameters are invalid - this return +//! value would indicate that no chunks are to be protected. +//! +// +//***************************************************************************** +static uint64_t +generate_chunk_mask(uint32_t *pui32StartAddress, uint32_t *pui32StopAddress) +{ + uint32_t ui32ChunkStart, ui32ChunkStop; + uint32_t ui32Width; + uint64_t ui64Mask; + + // + // Validate the address input parameters + // + if ( (pui32StartAddress > pui32StopAddress) || + (pui32StopAddress > (uint32_t*)AM_HAL_FLASH_LARGEST_VALID_ADDR) ) + { + // + // Argument error, return value to leave all chunks unprotected. + // + return 0xFFFFFFFFFFFFFFFF; + } + + // + // Extract chunk related information + // + ui32ChunkStart = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StartAddress); + ui32ChunkStop = AM_HAL_FLASH_INFO_ADDR2CHUNK((uint32_t)pui32StopAddress); + ui32Width = ui32ChunkStop - ui32ChunkStart + 1; + + if ( ui32Width == 64 ) + { + ui64Mask = (uint64_t)0xFFFFFFFFFFFFFFFFLLU; + } + else + { + ui64Mask = ( ((uint64_t)0x0000000000000001) << ui32Width) - 1; + ui64Mask <<= ui32ChunkStart; + } + + // + // OK now return the chunk mask (inverted). + // + return ~ui64Mask; + +} // generate_chunk_mask() + +//***************************************************************************** +// +//! @brief This function sets copy protection for a range of flash chunks. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function will set copy protection bits for a range of flash chunks +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return +//! 0 for success. +//! 0x400000 if the protection bits were already programmed (mask the return +//! value with 0x3FFFFF to ignore this case and treat as success). +//! Otherwise, non-zero for failure. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_copy_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + int iRC; + bool bModified = false; + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t ui32Protection[2]; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return 0x100000; + } + + // + // Go get the current settings for copy protection. + // + ui32Protection[0] = pui32Protection[0]; + ui32Protection[1] = pui32Protection[1]; + + // + // AND mask off the necessary protection bits in the lower word. + // + ui32Work = (uint32_t)ui64Mask; + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[0] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[0] = ui32Work | ~ui32Protection[0]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[0], // source data + (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 0, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x10000; + } + } + + // + // AND mask off the necessary protection bits in the upper word. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[1] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[1] = ui32Work | ~ui32Protection[1]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[1], // source data + (AM_HAL_FLASH_INFO_COPYPROT_O / 4) + 1, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x20000; + } + } + + if ( bModified ) + { + return 0; + } + else + { + return 0x400000; + } + +} // am_hal_flash_copy_protect_set() + +//***************************************************************************** +// +//! @brief This function checks copy protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash. +//! @param pui32StopAddress - Ending address in flash. +//! +//! This function will check copy protection bits for a range of flash chunks +//! it expects all chunks in the range to be protected. +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @return false for at least one chunk in the covered range is not protected, +//! and true if all chunks in the covered range are protected. +//! +// +//***************************************************************************** +bool +am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_COPYPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)ui64Mask; + if ( ~ui32Work & pui32Protection[0] ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ~ui32Work & pui32Protection[1] ) + { + return false; + } + + // + // If we get here, there are no unprotected chunks within specified range. + // + return true; + +} // am_hal_flash_copy_protect_check() + +//***************************************************************************** +// +//! @brief This function sets write protection for a range of flash chunks. +//! +//! @param ui32InfoKey - The customer INFO space programming key +//! @param pui32StartAddress - Starting address in flash to begin protection. +//! @param pui32StopAddress - Ending address in flash to stop protection. +//! +//! This function will set write protection bits for a range of flash chunks +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @note Interrupts are active during execution of this function. Any interrupt +//! taken could cause execution errors. Please see the IMPORTANT note under +//! Detailed Description above for more details. +//! +//! @return +//! 0 for success. +//! 0x400000 if the protection bits were already programmed (mask the return +//! value with 0x3FFFFF to ignore this case and treat as success). +//! Otherwise, non-zero for failure. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. +// +//***************************************************************************** +int32_t +am_hal_flash_write_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + int iRC; + bool bModified = false; + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t ui32Protection[2]; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return 0x100000; + } + + // + // Go get the current settings for copy protection. + // + ui32Protection[0] = pui32Protection[0]; + ui32Protection[1] = pui32Protection[1]; + + // + // AND mask off the necessary protection bits in the lower word. + // + ui32Work = (uint32_t)ui64Mask; + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[0] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[0] = ui32Work | ~ui32Protection[0]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[0], // source data + (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 0, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x10000; + } + } + + // + // AND mask off the necessary protection bits in the upper word. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ( ~ui32Work ) && ( ui32Work != ui32Protection[1] ) ) + { + bModified = true; + // Need to change only the bits changing - bits already set to 0 should not be rewritten to 0 + // Flash has limits on number of times a bit can be set to 0 + ui32Protection[1] = ui32Work | ~ui32Protection[1]; + iRC = g_am_hal_flash.flash_program_info_area( + ui32InfoKey, + 0, // instance + &ui32Protection[1], // source data + (AM_HAL_FLASH_INFO_WRITPROT_O / 4) + 1, // word offset + 1 ); // number of words + + if ( iRC ) + { + return iRC | 0x20000; + } + } + + if ( bModified ) + { + return 0; + } + else + { + return 0x400000; + } + +} // am_hal_flash_write_protect_set() + +//***************************************************************************** +// +//! @brief This function checks write protection for a range of flash chunks. +//! +//! @param pui32StartAddress - Starting address in flash. +//! @param pui32StopAddress - Ending address in flash. +//! +//! This function will check write protection bits for a range of flash chunks +//! it expects all chunks in the range to be protected. +//! +//! @note Each flash chunk contains 16KBytes and corresponds to one bit in +//! the protection register. Set the bit to zero to enable protection. +//! +//! @return false for at least one chunk in the covered range is not protected, +//! and true if all chunks in the covered range are protected. +//! +// +//***************************************************************************** +bool +am_hal_flash_write_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress) +{ + uint64_t ui64Mask; + uint32_t ui32Work; + uint32_t *pui32Protection = (uint32_t *)AM_HAL_FLASH_INFO_WRITPROT_ADDR; + + // + // Extract chunk mask from parameters. + // Also checks parameter validity (returns -1 if bad parameters). + // + ui64Mask = generate_chunk_mask(pui32StartAddress, pui32StopAddress); + if ( ~ui64Mask == 0x0 ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)ui64Mask; + if ( ~ui32Work & pui32Protection[0] ) + { + return false; + } + + // + // Now check the lower word of protection bits. + // + ui32Work = (uint32_t)(ui64Mask >> 32); + if ( ~ui32Work & pui32Protection[1] ) + { + return false; + } + + // + // If we get here, there are no unprotected chunks within specified range. + // + return true; + +}// am_hal_flash_write_protect_check() + +//***************************************************************************** +// +//! @brief Read a uint32 value from a valid memory or peripheral location. +//! +//! @param ui32Address - The location to be read. +//! +//! Use this function to safely read a value from peripheral or memory locations. +//! +//! This function calls a function that resides BOOTROM or SRAM to do the actual +//! read, thus completely avoiding any conflict with flash or INFO space. +//! +//! @return The value read from the given address. +// +//***************************************************************************** +uint32_t +am_hal_flash_load_ui32(uint32_t *pui32Address) +{ + return g_am_hal_flash.flash_util_read_word(pui32Address); +} // am_hal_flash_load_ui32() + +//***************************************************************************** +// +//! @brief Write a given uint32 value to a valid memory or peripheral location. +//! +//! @param pui32Address - The location to be written. +//! +//! Use this function to safely store a value to peripheral or memory locations. +//! +//! This function calls a function that resides in BOOTROM or SRAM to do the +//! actual write, thus completely avoiding any conflict with flash or INFO. +//! +//! @return The value read from the given address. +// +//***************************************************************************** +#if defined(__GNUC_STDC_INLINE__) +uint32_t SRAM_write_ui32[12 / 4] = + { + // + // A very simple, word-aligned function residing in SRAM (stack). This + // function writes a given memory location while executing outside of + // flash. It then does a read back to ensure that the write completed. + // Prototype: uint32_t SRAM_write_ui32(ui32Addr, ui32Value); + // + 0xBF006001, // 6001 str r1,[r0,#0] + // BF00 nop + 0xBF006800, // 6800 ldr r0,[r0,#0] + // BF00 nop + 0xBF004770 // 4770 bx lr + // BF00 nop + }; +#elif (defined (__ARMCC_VERSION) || defined(__IAR_SYSTEMS_ICC__)) +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +void +am_hal_flash_store_ui32(uint32_t *pui32Address, uint32_t ui32Value) +{ +#if (defined (__ARMCC_VERSION) || defined(__IAR_SYSTEMS_ICC__)) + uint32_t SRAM_write_ui32[12 / 4] = + { + // + // A very simple, word-aligned function residing in SRAM (stack). This + // function writes a given memory location while executing outside of + // flash. It then does a read back to ensure that the write completed. + // Prototype: uint32_t SRAM_write_ui32(ui32Addr, ui32Value); + // + 0xBF006001, // 6001 str r1,[r0,#0] + // BF00 nop + 0xBF006800, // 6800 ldr r0,[r0,#0] + // BF00 nop + 0xBF004770 // 4770 bx lr + // BF00 nop + }; +#elif defined(__GNUC_STDC_INLINE__) +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + + // + // Call the simple routine that has been coded in SRAM. + // First set up a function pointer to the array, being sure to set the + // .T bit (Thumb bit, bit0) in the branch address, then use that + // function ptr to call the SRAM function. + // + uint32_t SRAMCode = (uint32_t)SRAM_write_ui32 | 0x1; + uint32_t (*pFunc)(uint32_t*, uint32_t) = (uint32_t (*)(uint32_t*, uint32_t))SRAMCode; + (*pFunc)(pui32Address, ui32Value); + +} // am_hal_flash_store_ui32() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.h new file mode 100644 index 0000000000..ce4f55c116 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_flash.h @@ -0,0 +1,365 @@ +//***************************************************************************** +// +// am_hal_flash.h +//! @file +//! +//! @brief Functions for performing Flash operations. +//! +//! @addtogroup flash3 Flash +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_FLASH_H +#define AM_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +//***************************************************************************** +// +// Flash Program keys. +// +//***************************************************************************** +#define AM_HAL_FLASH_PROGRAM_KEY 0x12344321 +#define AM_HAL_FLASH_INFO_KEY 0xD894E09E + + + +//***************************************************************************** +// +// Some helpful SRAM values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_SRAM_ADDR 0x10000000 +#define AM_HAL_FLASH_SRAM_SIZE (384 * 1024) +#define AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR (AM_HAL_FLASH_SRAM_ADDR + AM_HAL_FLASH_SRAM_SIZE - 1) + +//***************************************************************************** +// +// Some helpful flash values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_ADDR 0x00000000 +#define AM_HAL_FLASH_INSTANCE_SIZE ( 512 * 1024 ) +#define AM_HAL_FLASH_NUM_INSTANCES 2 +#define AM_HAL_FLASH_PAGE_SIZE ( 8 * 1024 ) +#define AM_HAL_FLASH_INFO_SIZE AM_HAL_FLASH_PAGE_SIZE +#define AM_HAL_FLASH_INSTANCE_PAGES ( AM_HAL_FLASH_INSTANCE_SIZE / AM_HAL_FLASH_PAGE_SIZE ) +#define AM_HAL_FLASH_TOTAL_SIZE ( AM_HAL_FLASH_INSTANCE_SIZE * AM_HAL_FLASH_NUM_INSTANCES ) +#define AM_HAL_FLASH_LARGEST_VALID_ADDR ( AM_HAL_FLASH_ADDR + AM_HAL_FLASH_TOTAL_SIZE - 1 ) +#define AM_HAL_FLASH_APPL_ADDR 0xC000 + +// +// Macros to determine whether a given address is a valid internal +// flash or SRAM address. +// +#define ISADDRSRAM(x) ((x >= AM_HAL_FLASH_SRAM_ADDR) && \ + (x <= (AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR & ~0x3))) +#if AM_HAL_FLASH_ADDR == 0x0 +#define ISADDRFLASH(x) (x <= (AM_HAL_FLASH_LARGEST_VALID_ADDR & ~0x3)) +#else +#define ISADDRFLASH(x) ((x >= AM_HAL_FLASH_ADDR) && \ + (x <= (AM_HAL_FLASH_LARGEST_VALID_ADDR & ~0x3))) +#endif + +// +// Macros to describe the flash ROW layout. +// +#define AM_HAL_FLASH_ROW_WIDTH_BYTES (512) + +// +// Convert an absolute flash address to an instance +// +#define AM_HAL_FLASH_ADDR2INST(addr) ( ( addr >> 19 ) & (AM_HAL_FLASH_NUM_INSTANCES - 1) ) + +// +// Convert an absolute flash address to a page number relative to the instance +// +#define AM_HAL_FLASH_ADDR2PAGE(addr) ( ( addr >> 13 ) & 0x3F ) + +// +// Convert an absolute flash address to an absolute page number +// +#define AM_HAL_FLASH_ADDR2ABSPAGE(addr) ( addr >> 13 ) + +//***************************************************************************** +// +//! Given an integer number of microseconds, convert to a value representing +//! the number of am_hal_flash_delay() cycles that will provide that amount +//! of delay. This macro is designed to take into account some of the call +//! overhead and latencies. +//! +//! e.g. To provide a 10us delay: +//! am_hal_flash_delay( FLASH_CYCLES_US(10) ); +//! +//! As of SDK 2.1, burst mode is accounted for in am_hal_flash_delay(). +//! +//! The FLASH_CYCLES_US macro assumes: +//! - Burst or normal mode operation. +//! - If cache is not enabled, use FLASH_CYCLES_US_NOCACHE() instead. +// +//***************************************************************************** +#define CYCLESPERITER (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3) +#define FLASH_CYCLES_US(n) ((n * CYCLESPERITER) + 0) +#define FLASH_CYCLES_US_NOCACHE(n) ( (n == 0) ? 0 : (n * CYCLESPERITER) - 5) + +// +// Backward compatibility +// +#define am_hal_flash_program_otp am_hal_flash_program_info +#define am_hal_flash_program_otp_sram am_hal_flash_program_info_sram + +//***************************************************************************** +// +//! Structure of pointers to helper functions invoking flash operations. +// +//! The functions we are pointing to here are in the Apollo 3 +//! integrated BOOTROM. +// +//***************************************************************************** +typedef struct am_hal_flash_helper_struct +{ + // + // The basics. + // + int (*flash_mass_erase)(uint32_t, uint32_t); + int (*flash_page_erase)(uint32_t, uint32_t, uint32_t); + int (*flash_program_main)(uint32_t, uint32_t *, uint32_t *, uint32_t); + int (*flash_program_info_area)(uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t); + + // + // Non-blocking variants, but be careful these are not interrupt safe so + // mask interrupts while these very long operations proceed. + // + int (*flash_mass_erase_nb)(uint32_t, uint32_t); + int (*flash_page_erase_nb)(uint32_t, uint32_t, uint32_t); + int (*flash_page_erase2_nb)( uint32_t value, uint32_t address); + bool (*flash_nb_operation_complete)(void); + + // + // Useful utilities. + // + uint32_t (*flash_util_read_word)( uint32_t *); + void (*flash_util_write_word)( uint32_t *, uint32_t); + void (*bootrom_delay_cycles)(uint32_t ui32Cycles); + + // + // Essentially these are recovery options. + // + int (*flash_info_erase)( uint32_t, uint32_t); + int (*flash_info_plus_main_erase)( uint32_t, uint32_t); + int (*flash_info_plus_main_erase_both)( uint32_t value); + int (*flash_recovery)( uint32_t value); + + // + // The following functions pointers will generally never be called from + // user programs. They are here primarily to document these entry points + // which are usable from a debugger or debugger script. + // + void (*flash_program_main_from_sram)(void); + void (*flash_program_info_area_from_sram)(void); + void (*flash_erase_main_pages_from_sram)(void); + void (*flash_mass_erase_from_sram)(void); + void (*flash_info_erase_from_sram)(void); + void (*flash_info_plus_main_erase_from_sram)(void); + void (*flash_nb_operation_complete_from_sram)(void); + void (*flash_page_erase2_nb_from_sram)(void); + void (*flash_recovery_from_sram)(void); + +} g_am_hal_flash_t; +extern const g_am_hal_flash_t g_am_hal_flash; + + +//***************************************************************************** +// +// Define some FLASH INFO SPACE values and macros. +// +//***************************************************************************** +#define AM_HAL_FLASH_INFO_ADDR 0x50020000 +#define AM_HAL_FLASH_INFO_SECURITY_O 0x10 +#define AM_HAL_FLASH_INFO_WRITPROT_O 0x40 +#define AM_HAL_FLASH_INFO_COPYPROT_O 0x50 + +#define AM_HAL_FLASH_INFO_SECURITY_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_SECURITY_O) +#define AM_HAL_FLASH_INFO_WRITPROT_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_WRITPROT_O) +#define AM_HAL_FLASH_INFO_COPYPROT_ADDR (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_COPYPROT_O) +#define AM_HAL_FLASH_INFO_CUST_TRIM_ADDR (AM_HAL_FLASH_INFO_ADDR + 0x14) + +// +// Define the customer info signature data (at AM_HAL_FLASH_INFO_ADDR). +// These bits must exist in the customer info space in order for many of the +// security and protection functions to work. +// +#define AM_HAL_FLASH_INFO_SIGNATURE0 0x48EAAD88 +#define AM_HAL_FLASH_INFO_SIGNATURE1 0xC9705737 +#define AM_HAL_FLASH_INFO_SIGNATURE2 0x0A6B8458 +#define AM_HAL_FLASH_INFO_SIGNATURE3 0xE41A9D74 + +// +// Define the customer security bits (at AM_HAL_FLASH_INFO_SECURITY_ADDR) +// +#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S 0 +#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S 1 +#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S 2 +#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S 3 +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S 4 +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S 8 +#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S 9 + +#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S)) +#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S)) +#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M ((uint32_t)(0xF << AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S)) +#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S)) +#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) +#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP_M ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) +#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP ((uint32_t)(0x0 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S)) + +// +// Protection chunk macros +// AM_HAL_FLASH_INFO_CHUNK2ADDR: Convert a chunk number to an address +// AM_HAL_FLASH_INFO_CHUNK2INST: Convert a chunk number to an instance number +// AM_HAL_FLASH_INFO_ADDR2CHUNK: Convert an address to a chunk number +// +#define AM_HAL_FLASH_INFO_CHUNKSIZE (16*1024) + +#define AM_HAL_FLASH_INFO_CHUNK2ADDR(n) (AM_HAL_FLASH_ADDR + (n << 14)) +#define AM_HAL_FLASH_INFO_CHUNK2INST(n) ((n >> 5) & 1 +#define AM_HAL_FLASH_INFO_ADDR2CHUNK(n) ((n) >> 14) + +//***************************************************************************** +// +// Function prototypes for the helper functions +// +//***************************************************************************** +extern int am_hal_flash_mass_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst); +extern int am_hal_flash_page_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst, + uint32_t ui32PageNum); +extern int am_hal_flash_program_main(uint32_t ui32ProgramKey, uint32_t *pSrc, + uint32_t *pDst, uint32_t NumberOfWords); + +// +// Recovery type functions for Customer INFO space. +// +extern int am_hal_flash_program_info(uint32_t ui32InfoKey, uint32_t ui32InfoInst, + uint32_t *pui32Src, uint32_t ui32Offset, + uint32_t ui32NumWords); +extern int am_hal_flash_erase_info(uint32_t ui32InfoKey, + uint32_t ui32Instance); +extern int am_hal_flash_erase_main_plus_info(uint32_t ui32InfoKey, + uint32_t ui32Instance); +extern int am_hal_flash_erase_main_plus_info_both_instances( + uint32_t ui32InfoKey); +extern void am_hal_flash_recovery(uint32_t ui32RecoveryKey); + +// +// This function safely writes to a peripheral or memory address while executing +// from SRAM, thus avoiding any conflict with flash or INFO space. +// +extern void am_hal_flash_store_ui32(uint32_t *pui32Address, uint32_t ui32Data); + +// +// BOOTROM resident reader, writer and delay utility functions. +// +extern uint32_t am_hal_flash_load_ui32(uint32_t *pui32Address); +extern void am_hal_flash_delay(uint32_t ui32Iterations); +extern uint32_t am_hal_flash_delay_status_change(uint32_t ui32Iterations, + uint32_t ui32Address, + uint32_t ui32Mask, + uint32_t ui32Value); +extern uint32_t am_hal_flash_delay_status_check(uint32_t ui32Iterations, + uint32_t ui32Address, + uint32_t ui32Mask, + uint32_t ui32Value, + bool bIsEqual); + +// +// These functions update security/protection bits in the customer INFO blOCK. +// +extern bool am_hal_flash_customer_info_signature_check(void); +extern bool am_hal_flash_info_signature_set(uint32_t ui32InfoKey); +extern int32_t am_hal_flash_info_erase_disable(uint32_t ui32InfoKey); +extern bool am_hal_flash_info_erase_disable_check(void); +extern int32_t am_hal_flash_info_program_disable(uint32_t ui32InfoKey, uint32_t ui32Mask); +extern uint32_t am_hal_flash_info_program_disable_get(void); +extern int32_t am_hal_flash_wipe_flash_enable(uint32_t ui32InfoKey); +extern bool am_hal_flash_wipe_flash_enable_check(void); +extern int32_t am_hal_flash_wipe_sram_enable(uint32_t ui32InfoKey); +extern bool am_hal_flash_wipe_sram_enable_check(void); +extern int32_t am_hal_flash_swo_disable(uint32_t ui32InfoKey); +extern bool am_hal_flash_swo_disable_check(void); +extern int32_t am_hal_flash_debugger_disable(uint32_t ui32InfoKey); +extern bool am_hal_flash_debugger_disable_check(void); + +extern int32_t am_hal_flash_copy_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern bool am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern int32_t am_hal_flash_write_protect_set(uint32_t ui32InfoKey, + uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern bool am_hal_flash_write_protect_check(uint32_t *pui32StartAddress, + uint32_t *pui32StopAddress); +extern int am_hal_flash_clear_bits(uint32_t ui32ProgramKey, + uint32_t *pui32Addr, + uint32_t ui32BitMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_FLASH_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.c new file mode 100644 index 0000000000..37ce3ece23 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.c @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// am_hal_global.c +//! @file +//! +//! @brief Locate global variables here. +//! +//! This module contains global variables that are used throughout the HAL. +//! +//! One use in particular is that it uses a global HAL flags variable that +//! contains flags used in various parts of the HAL. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** +uint32_t volatile g_ui32HALflags = 0x00000000; + +//***************************************************************************** +// +// Version information +// +//***************************************************************************** +const uint8_t g_ui8HALcompiler[] = COMPILER_VERSION; +const am_hal_version_t g_ui32HALversion = +{ + .s.bAMREGS = false, + .s.Major = AM_HAL_VERSION_MAJ, + .s.Minor = AM_HAL_VERSION_MIN, + .s.Revision = AM_HAL_VERSION_REV +}; diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.h new file mode 100644 index 0000000000..a7ba87bf73 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_global.h @@ -0,0 +1,167 @@ +//***************************************************************************** +// +// am_hal_global.h +//! @file +//! +//! @brief Locate all HAL global variables here. +//! +//! This module contains global variables that are used throughout the HAL, +//! but not necessarily those designated as const (which typically end up in +//! flash). Consolidating globals here will make it easier to manage them. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_GLOBAL_H +#define AM_HAL_GLOBAL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Include the SDK global version information. +// +//***************************************************************************** +#include "../../am_sdk_version.h" + +//***************************************************************************** +// +// Device definitions +// +//***************************************************************************** +#define AM_HAL_DEVICE_NAME "Apollo3 Blue" + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** +// Utility for compile time assertions +// Will cause divide by 0 error at build time +#define _AM_ASSERT_CONCAT_(a, b) a##b +#define _AM_ASSERT_CONCAT(a, b) _AM_ASSERT_CONCAT_(a, b) +#define am_ct_assert(e) enum { _AM_ASSERT_CONCAT(assert_line_, __LINE__) = 1/(!!(e)) } + +//***************************************************************************** +// +// Macros to determine compiler version information +// +//***************************************************************************** +// +// Since the stringize operator itself does not first expand macros, two levels +// of indirection are required in order to fully resolve the pre-defined +// compiler (integer) macros. The 1st level expands the macro, and the 2nd +// level actually stringizes it. +// This method will also work even if the argument is not a macro. However, if +// the argument is already a string, the string will end up with inserted quote +// marks. +// +#define STRINGIZE_VAL(n) STRINGIZE_VAL2(n) +#define STRINGIZE_VAL2(n) #n + +#ifdef __GNUC__ +#define COMPILER_VERSION ("GCC " __VERSION__) +#elif defined(__ARMCC_VERSION) +#define COMPILER_VERSION ("ARMCC " STRINGIZE_VAL(__ARMCC_VERSION)) +#elif defined(__KEIL__) +#define COMPILER_VERSION "KEIL_CARM " STRINGIZE_VAL(__CA__) +#elif defined(__IAR_SYSTEMS_ICC__) +#define COMPILER_VERSION __VERSION__ +#else +#define COMPILER_VERSION "Compiler unknown" +#endif + +//***************************************************************************** +// +// Utility Macros +// +//***************************************************************************** +// As long as the two values are not apart by more that 2^31, this should give +// correct result, taking care of wraparound +#define AM_HAL_U32_GREATER(val1, val2) ((int32_t)((int32_t)(val1) - (int32_t)(val2)) > 0) +#define AM_HAL_U32_SMALLER(val1, val2) ((int32_t)((int32_t)(val1) - (int32_t)(val2)) < 0) + +//****************************************************************************** +// +// Global typedefs +// +//****************************************************************************** +typedef union +{ + uint32_t u32; + struct + { + uint32_t resvd : 7; // [6:0] + uint32_t bAMREGS : 1; // [7] + uint32_t Revision : 8; // [15:8] + uint32_t Minor : 8; // [23:16] + uint32_t Major : 8; // [31:24] + } s; +} am_hal_version_t; + +typedef union +{ + uint32_t u32; + struct + { + uint32_t magic : 24; + uint32_t bInit : 1; + uint32_t bEnable : 1; + uint32_t resv : 6; + } s; +} am_hal_handle_prefix_t; + +//***************************************************************************** +// +// Global Variables extern declarations. +// +//***************************************************************************** +extern volatile uint32_t g_ui32HALflags; +extern const uint8_t g_ui8HALcompiler[]; +extern const am_hal_version_t g_ui32HALversion; + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_GLOBAL_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.c new file mode 100644 index 0000000000..50ec4b4237 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.c @@ -0,0 +1,1560 @@ +//***************************************************************************** +// +// am_hal_gpio.c +//! @file +//! +//! @brief Functions for interfacing with the GPIO module +//! +//! @addtogroup gpio3 GPIO +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// Local defines. +//***************************************************************************** +// +// Generally define GPIO PADREG and GPIOCFG bitfields +// +#define PADREG_FLD_76_S 6 +#define PADREG_FLD_FNSEL_S 3 +#define PADREG_FLD_DRVSTR_S 2 +#define PADREG_FLD_INPEN_S 1 +#define PADREG_FLD_PULLUP_S 0 + +#define GPIOCFG_FLD_INTD_S 3 +#define GPIOCFG_FLD_OUTCFG_S 1 +#define GPIOCFG_FLD_INCFG_S 0 + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +//***************************************************************************** +// Define some common GPIO configurations. +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_DISABLE = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_TRISTATE = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_TRISTATE +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN +}; + +// +// Input with various pullups (weak, 1.5K, 6K, 12K, 24K) +// The 1.5K - 24K pullup values are valid for select I2C enabled pads. +// For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49. +// The "weak" value is used for almost every other pad except pin 20. +// +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_WEAK +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_1_5 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_6 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_6K +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_12 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_12K +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_24 = +{ + .uFuncSel = 3, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_DISABLE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_24K +}; + +// +// Variations of output (drive strengths, read, etc) +// +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_4 = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_8 = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_12 = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL +}; + +const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_WITH_READ = +{ + .uFuncSel = 3, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .eGPRdZero = AM_HAL_GPIO_PIN_RDZERO_READPIN +}; + +//***************************************************************************** +// +// g_ui8Inpen[] +// This lookup table determines whether the INPEN bit is required based on +// the pin number and FNSEL. +// +//***************************************************************************** +static const uint8_t +g_ui8Inpen[AM_HAL_GPIO_MAX_PADS] = +{ + //0 1 2 3 4 5 6 7 8 9 + 0x23, 0x23, 0x27, 0x62, 0xA1, 0x03, 0x87, 0x10, 0x03, 0x53, // Pins 0-9 + 0x00, 0xE1, 0x51, 0x81, 0x41, 0x55, 0x05, 0xC4, 0x80, 0x40, // Pins 10-19 + 0x01, 0xB1, 0x40, 0x41, 0x14, 0x31, 0xA0, 0x31, 0x00, 0xF1, // Pins 20-29 + 0x80, 0x11, 0x91, 0x21, 0xC1, 0x11, 0xE5, 0x11, 0x45, 0x30, // Pins 30-39 + 0x37, 0x00, 0x30, 0x31, 0x00, 0x71, 0x00, 0x40, 0x30, 0x31 // Pins 40-49 +}; + +//***************************************************************************** +// +// g_ui8Bit76Capabilities[] +// This lookup table specifies capabilities of each pad for PADREG bits 7:6. +// +//***************************************************************************** +#define CAP_PUP 0x01 // PULLUP +#define CAP_PDN 0x08 // PULLDOWN (pin 20 only) +#define CAP_VDD 0x02 // VDD PWR (power source) +#define CAP_VSS 0x04 // VSS PWR (ground sink) +#define CAP_RSV 0x80 // bits 7:6 are reserved for this pin +static const uint8_t +g_ui8Bit76Capabilities[AM_HAL_GPIO_MAX_PADS] = +{ + //0 1 2 3 4 5 6 7 8 9 + CAP_PUP, CAP_PUP, CAP_RSV, CAP_VDD, CAP_RSV, CAP_PUP, CAP_PUP, CAP_RSV, CAP_PUP, CAP_PUP, // Pins 0-9 + CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, // Pins 10-19 + CAP_PDN, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_PUP, CAP_RSV, CAP_PUP, CAP_RSV, CAP_RSV, // Pins 20-29 + CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_VDD, CAP_VSS, CAP_RSV, CAP_PUP, // Pins 30-39 + CAP_PUP, CAP_VSS, CAP_PUP, CAP_PUP, CAP_RSV, CAP_RSV, CAP_RSV, CAP_RSV, CAP_PUP, CAP_PUP // Pins 40-49 +}; + +//***************************************************************************** +// +// g_ui8nCEpins[] +// This lookup table lists the nCE funcsel value as a function of the pin. +// Almost every pad has a nCE function (except for 4 pads). Every one of those +// nCE functions can select a polarity (active low or high) via the INTD field. +// All non-nCE functions use INCFG and INTD to select interrupt transition types. +// A lookup will return 0-7 if the pin supports nCE, and 8 if it does not. +// +// The truth table summarizes behavior. For the purposes of this table, assume +// "A" is the funcsel that selects nCE (and thus polarity is needed) for the +// given pad. Then "!A" is any other funcsel and selects interrupt transition. +// +// funcsel INCFG INTD Behavior +// !A 0 0 Interrupt on L->H transition. +// !A 0 1 Interrupt on H->L transition. +// !A 1 0 No interrupts. +// !A 1 1 Interrupt either direction. +// A x 0 nCE polarity active low. +// A x 1 nCE polarity active high. +// +//***************************************************************************** +static const uint8_t +g_ui8nCEpins[AM_HAL_GPIO_MAX_PADS] = +{ + // 0 1 2 3 4 5 6 7 8 9 + 0x07, 0x07, 0x07, 0x02, 0x02, 0x08, 0x08, 0x00, 0x02, 0x02, // Pads 0-9 + 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, // Pads 10-19 + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, // Pads 20-29 + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x08, // Pads 30-39 + 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 // Pads 40-49 +}; + +//***************************************************************************** +// +// g_ui8NCEtable[] +// This lookup table lists all available NCEs. It basically reproduces the +// "NCE Encoding Table" from the datasheet. +// The format of this table is: +// High nibble=IOM number; 0-5, MSPI=6 (IOMNUM_MSPI). +// Low nibble=CE number (0-3). +// Every 4 bytes (word) represent the next GPIO number/index. +// +//***************************************************************************** +static const uint8_t +g_ui8NCEtable[AM_HAL_GPIO_MAX_PADS][4] = +{ + // 0 1 2 3 = OUTCFG + {0x32, 0x42, 0x52, 0x13}, // NCE0 + {0x02, 0x12, 0x22, 0x60}, // NCE1 + {0x33, 0x43, 0x53, 0x21}, // NCE2 + {0x30, 0x40, 0x50, 0x20}, // NCE3 + {0x31, 0x41, 0x51, 0x11}, // NCE4 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE5 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE6 + {0x31, 0x41, 0x51, 0x60}, // NCE7 + {0x30, 0x40, 0x50, 0x00}, // NCE8 + {0x33, 0x43, 0x53, 0x23}, // NCE9 + {0x32, 0x42, 0x52, 0x60}, // NCE10 + {0x00, 0x10, 0x20, 0x30}, // NCE11 + {0x30, 0x40, 0x50, 0x61}, // NCE12 + {0x31, 0x41, 0x51, 0x01}, // NCE13 + {0x02, 0x12, 0x22, 0x42}, // NCE14 + {0x03, 0x13, 0x23, 0x60}, // NCE15 + {0x00, 0x10, 0x20, 0x50}, // NCE16 + {0x01, 0x11, 0x21, 0x41}, // NCE17 + {0x02, 0x12, 0x22, 0x32}, // NCE18 + {0x03, 0x13, 0x33, 0x60}, // NCE19 + {0x31, 0x41, 0x51, 0x21}, // NCE20 + {0x32, 0x42, 0x52, 0x22}, // NCE21 + {0x33, 0x43, 0x53, 0x03}, // NCE22 + {0x00, 0x10, 0x20, 0x40}, // NCE23 + {0x01, 0x11, 0x21, 0x51}, // NCE24 + {0x32, 0x42, 0x52, 0x02}, // NCE25 + {0x33, 0x43, 0x53, 0x13}, // NCE26 + {0x30, 0x40, 0x50, 0x10}, // NCE27 + {0x31, 0x41, 0x51, 0x60}, // NCE28 + {0x32, 0x42, 0x52, 0x12}, // NCE29 + {0x33, 0x43, 0x53, 0x03}, // NCE30 + {0x00, 0x10, 0x20, 0x40}, // NCE31 + {0x01, 0x11, 0x21, 0x61}, // NCE32 + {0x02, 0x12, 0x22, 0x52}, // NCE33 + {0x03, 0x13, 0x23, 0x33}, // NCE34 + {0x00, 0x10, 0x20, 0x30}, // NCE35 + {0x31, 0x41, 0x51, 0x61}, // NCE36 + {0x32, 0x42, 0x52, 0x02}, // NCE37 + {0x03, 0x13, 0x33, 0x53}, // NCE38 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE39 + {0xFF, 0xFF, 0xFF, 0xFF}, // NCE40 + {0x01, 0x11, 0x21, 0x61}, // NCE41 + {0x00, 0x10, 0x20, 0x50}, // NCE42 + {0x01, 0x11, 0x21, 0x61}, // NCE43 + {0x02, 0x12, 0x22, 0x52}, // NCE44 + {0x33, 0x43, 0x53, 0x13}, // NCE45 + {0x30, 0x40, 0x50, 0x61}, // NCE46 + {0x01, 0x11, 0x21, 0x31}, // NCE47 + {0x02, 0x12, 0x22, 0x32}, // NCE48 + {0x03, 0x13, 0x23, 0x43} // NCE49 +}; + +// declare ap3_gpio_get_pinconfig_bitmasks +void ap3_gpio_get_pinconfig_bitmasks(am_hal_gpio_pincfg_allow_t sAllowableChanges, uint8_t *padRegMask, uint8_t *GPCfgMask, uint8_t *altPadCfgMask); + +//***************************************************************************** +// +// Array of function pointers for handling GPIO interrupts. +// +//***************************************************************************** +static am_hal_gpio_handler_t gpio_ppfnHandlers[AM_HAL_GPIO_MAX_PADS]; +static void *gpio_pHandlerCtxt[AM_HAL_GPIO_MAX_PADS]; + +//***************************************************************************** +// +// Helper functions +// popcount() - Determine how many bits are set in the given bitmasks. +// pincfg_equ() - compare 2 am_hal_gpio_pincfg_t structures for equality. +// +//***************************************************************************** +static bool +pincfg_equ(void *cfg1, void *cfg2) +{ + uint32_t ui32A, ui32B; + + // + // We're assuming that am_hal_gpio_pincfg_t boils down to a uint32_t, + // which is its intent. + // + ui32A = *((uint32_t*)cfg1); + ui32B = *((uint32_t*)cfg2); + + return ui32A == ui32B ? true : false; + +} // pincfg_equ() + +static uint32_t +popcount(uint64_t ui64bitmask) +{ + uint32_t uCnt = 0; + while ( ui64bitmask ) + { + uCnt += ui64bitmask & 1; + ui64bitmask >>= 1; + } + return uCnt; +} // popcount() + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32Config - Contains multiple descriptor fields. +//! +//! This function configures a pin according to the parameters in ui32Config. +//! All parameters are validated, and the given pin is configured according +//! to the designated parameters. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t +am_hal_gpio_pinconfig(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg) + +{ + uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg; + uint32_t ui32Funcsel, ui32PowerSw; + bool bClearEnable = false; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Pin >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the PADREG accumulator variables. + // + ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0; + + // + // Get the requested function and/or power switch. + // + ui32Funcsel = bfGpioCfg.uFuncSel; + ui32PowerSw = bfGpioCfg.ePowerSw; + + ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S; + + // + // Check for invalid configuration requests. + // + if ( bfGpioCfg.ePullup != AM_HAL_GPIO_PIN_PULLUP_NONE ) + { + // + // This setting is needed for all pullup settings including + // AM_HAL_GPIO_PIN_PULLUP_WEAK and AM_HAL_GPIO_PIN_PULLDOWN. + // + ui32Padreg |= (0x1 << PADREG_FLD_PULLUP_S); + + // + // Check for specific pullup or pulldown settings. + // + if ( (bfGpioCfg.ePullup >= AM_HAL_GPIO_PIN_PULLUP_1_5K) && + (bfGpioCfg.ePullup <= AM_HAL_GPIO_PIN_PULLUP_24K) ) + { + ui32Padreg |= ((bfGpioCfg.ePullup - AM_HAL_GPIO_PIN_PULLUP_1_5K) << + PADREG_FLD_76_S); +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !(g_ui8Bit76Capabilities[ui32Pin] & CAP_PUP) ) + { + return AM_HAL_GPIO_ERR_PULLUP; + } + } + else if ( bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLDOWN ) + { + if ( ui32Pin != 20 ) + { + return AM_HAL_GPIO_ERR_PULLDOWN; + } + } + else if ( bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLUP_WEAK ) + { + // + // All pads except 20 support a weak pullup, for which we only need + // to set PADnPULL and clear 7:6 (already done at this point). + // + if ( ui32Pin == 20 ) + { + return AM_HAL_GPIO_ERR_PULLUP; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + } + } + + // + // Check if requesting a power switch pin + // + if ( ui32PowerSw != AM_HAL_GPIO_PIN_POWERSW_NONE ) + { + if ( (ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VDD) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VDD) ) + { + ui32Padreg |= 0x1 << PADREG_FLD_76_S; + } + else if ( (ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VSS) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VSS) ) + { + ui32Padreg |= 0x2 << PADREG_FLD_76_S; + } + else + { + return AM_HAL_GPIO_ERR_PWRSW; + } + } + + // + // Depending on the selected pin and FNSEL, determine if INPEN needs to be set. + // + ui32Padreg |= (g_ui8Inpen[ui32Pin] & (1 << ui32Funcsel)) ? (1 << PADREG_FLD_INPEN_S) : 0; + + // + // Configure ui32GpCfg based on whether nCE requested. + // + if ( g_ui8nCEpins[ui32Pin] == ui32Funcsel ) + { + uint32_t ui32Outcfg; + uint8_t ui8CEtbl; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // User is configuring a nCE. Verify the requested settings and set the + // polarity and OUTCFG values (INCFG is not used here and should be 0). + // Valid uNCE values are 0-3 (uNCE is a 2-bit field). + // Valid uIOMnum are 0-6 (0-5 for IOMs, 6 for MSPI, 7 is invalid). + // + if ( bfGpioCfg.uIOMnum > IOMNUM_MAX ) + { + return AM_HAL_GPIO_ERR_INVCE; // Invalid CE specified + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Construct the entry we expect to find in the table. We can determine + // the OUTCFG value by looking for that value in the pin row. + // + ui8CEtbl = (bfGpioCfg.uIOMnum << 4) | bfGpioCfg.uNCE; + for ( ui32Outcfg = 0; ui32Outcfg < 4; ui32Outcfg++ ) + { + if ( g_ui8NCEtable[ui32Pin][ui32Outcfg] == ui8CEtbl ) + { + break; + } + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Outcfg >= 4 ) + { + return AM_HAL_GPIO_ERR_INVCEPIN; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32GPCfg |= (ui32Outcfg << GPIOCFG_FLD_OUTCFG_S) | + (bfGpioCfg.eCEpol << GPIOCFG_FLD_INTD_S) | + (0 << GPIOCFG_FLD_INCFG_S); + } + else + { + // + // It's not nCE, it's one of the other funcsels. + // Start by setting the value of the requested GPIO input. + // + ui32Padreg |= (bfGpioCfg.eGPInput << PADREG_FLD_INPEN_S); + + // + // Map the requested interrupt direction settings into the Apollo3 + // GPIOCFG register field, which is a 4-bit field: + // [INTD(1):OUTCFG(2):INCFG(1)]. + // Bit0 of eIntDir maps to GPIOCFG.INTD (b3). + // Bit1 of eIntDir maps to GPIOCFG.INCFG (b0). + // + ui32GPCfg |= (bfGpioCfg.eGPOutcfg << GPIOCFG_FLD_OUTCFG_S) | + (((bfGpioCfg.eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | + (((bfGpioCfg.eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S); + + if ( (bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL) || + pincfg_equ(&bfGpioCfg, (void*)&g_AM_HAL_GPIO_DISABLE) ) + { + // + // For pushpull configurations, we must be sure to clear the ENABLE + // bit. In pushpull, these bits turn on FAST GPIO. For regular + // GPIO, they must be clear. + // + bClearEnable = true; + } + + // + // There is some overlap between eGPRdZero and eIntDir as both settings + // utilize the overloaded INCFG bit. + // Therefore the two fields should be used in a mutually exclusive + // manner. For flexibility however they are not disallowed because + // their functionality is dependent on FUNCSEL and whether interrupts + // are used. + // + // In the vein of mutual exclusion, eGPRdZero is primarily intended for + // use when GPIO interrupts are not in use and can be used when no + // eIntDir setting is provided. + // If eIntDir is provided, eGPRdZero is ignored and can only be + // achieved via the AM_HAL_GPIO_PIN_INTDIR_NONE setting. + // + if ( bfGpioCfg.eIntDir == 0 ) + { + ui32GPCfg &= ~(1 << GPIOCFG_FLD_INCFG_S); + ui32GPCfg |= (bfGpioCfg.eGPRdZero << GPIOCFG_FLD_INCFG_S); + } + } + + switch ( bfGpioCfg.eDriveStrength ) + { + // DRIVESTRENGTH is a 2-bit field. + // bit0 maps to bit2 of a PADREG field. + // bit1 maps to bit0 of an ALTPADCFG field. + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + } + + // + // At this point, the 3 configuration variables, ui32GPCfg, ui32Padreg, + // and ui32AltPadCfg values are set (at bit position 0) and ready to write + // to their respective register bitfields. + // + uint32_t ui32GPCfgAddr, ui32PadregAddr, ui32AltpadAddr; + uint32_t ui32GPCfgClearMask, ui32PadClearMask; + uint32_t ui32GPCfgShft, ui32PadShft; + + ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3); + ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3); + ui32AltpadAddr = AM_REGADDR(GPIO, ALTPADCFGA) + (ui32Pin & ~0x3); + + ui32GPCfgShft = ((ui32Pin & 0x7) << 2); + ui32PadShft = ((ui32Pin & 0x3) << 3); + ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft); + ui32PadClearMask = ~((uint32_t)0xFF << ui32PadShft); + + // + // Get the new values into their rightful bit positions. + // + ui32Padreg <<= ui32PadShft; + ui32AltPadCfg <<= ui32PadShft; + ui32GPCfg <<= ui32GPCfgShft; + + AM_CRITICAL_BEGIN + + if ( bClearEnable ) + { + // + // We're configuring a mode that requires clearing the Enable bit. + // + am_hal_gpio_output_tristate_disable(ui32Pin); + } + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; + AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; + AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32PadClearMask) | ui32AltPadCfg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_pinconfig() + +//***************************************************************************** +// +// brief Configure specified pins for FAST GPIO operation. +// +// ui64PinMask - a mask specifying up to 8 pins to be configured and +// used for FAST GPIO (only bits 0-49 are valid). +// bfGpioCfg - The GPIO configuration (same as am_hal_gpio_pinconfig()). +// All of the pins specified by ui64PinMask will be set to this +// configuration. +// ui32Masks - If provided, an array to receive 2 32-bit values of the +// SET and CLEAR masks that are used for the BBSETCLEAR reg. +// Two 32-bit wds are placed for each pin indicated by the mask. +// The 2 32-bit values will be placed at incremental indexes. +// For example, say pin numbers 5 and 19 are indicated in the +// mask, and an array pointer is provided in ui32Masks. This +// array must be allocated by the caller to be at least 4 words. +// ui32Masks[0] = the set mask used for pin 5. +// ui32Masks[1] = the clear mask used for pin 5. +// ui32Masks[2] = the set mask used for pin 19. +// ui32Masks[3] = the clear mask used for pin 19. +// It is recommended that this array be allocated to 16 uint32_t. +// +//***************************************************************************** +uint32_t +am_hal_gpio_fast_pinconfig(uint64_t ui64PinMask, + am_hal_gpio_pincfg_t bfGpioCfg, + uint32_t ui32Masks[]) +{ + uint32_t ux, ui32pinnum, ui32retval, ui32Mask; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (ui64PinMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1)) || + (popcount(ui64PinMask) > 8) || + (bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_TRISTATE) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Roll through the pin mask and configure any designated pins per the + // bfGpioCfg parameter, and enable for Fast GPIO. + // + ui32Mask = 0; + ui32pinnum = 0; + ux = 0; + while ( ui64PinMask ) + { + if ( ui64PinMask & 0x1 ) + { + // + // It is assumed that the caller will have disabled Fast GPIO and + // initialized the pin value before calling this function. Therefore + // no value initialization is done before the pin configuration, nor + // is the am_hal_gpio_fastgpio_disable() called here. + // + // Configure the pin. + // + ui32retval = am_hal_gpio_pinconfig(ui32pinnum, bfGpioCfg); + if ( ui32retval ) + { + return ui32retval; + } + + ui32Mask |= 1 << (ui32pinnum & 0x7); + + // + // Enable the FAST GPIO for this pin + // + am_hal_gpio_fastgpio_enable(ui32pinnum); + + if ( ui32Masks ) + { + ui32Masks[ux + 0] = _VAL2FLD(APBDMA_BBSETCLEAR_SET, ui32Mask); + ui32Masks[ux + 1] = _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, ui32Mask); + } + ux += 2; // Get next indexes + } + ui32pinnum++; + ui64PinMask >>= 1; + } + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_fast_pinconfig() + +//***************************************************************************** +// +//! @brief Read GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! @param eReadType - State type to read. One of: +//! AM_HAL_GPIO_INPUT_READ +//! AM_HAL_GPIO_OUTPUT_READ +//! AM_HAL_GPIO_ENABLE_READ +//! @param pui32ReadState - Pointer to the value to contain the read state. +//! When reading the value of a bit, will be either 0 or 1. +//! +//! This function reads a pin state as given by ui32Type. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t +am_hal_gpio_state_read(uint32_t ui32Pin, + am_hal_gpio_read_type_e eReadType, + uint32_t *pui32ReadState) +{ + uint32_t ui32ReadValue = 0xFFFFFFFF; + uint32_t ui32BaseAddr, ui32Shift; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( pui32ReadState == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if ( ui32Pin >= AM_HAL_GPIO_MAX_PADS ) + { + *pui32ReadState = ui32ReadValue; + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Compute base address + offset of 0 or 4. + // + ui32BaseAddr = ((ui32Pin & 0x20) >> 3); // 0 or 4 + ui32Shift = ui32Pin & 0x1F; + + switch ( eReadType ) + { + case AM_HAL_GPIO_INPUT_READ: + // + // Assumes eIntDir != AM_HAL_GPIO_PIN_INTDIR_NONE && + // eIntDir != AM_HAL_GPIO_PIN_INTDIR_BOTH + // If either of those configs are set, returns 0. + // + ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, RDA) + ui32BaseAddr); + ui32ReadValue = (ui32ReadValue >> ui32Shift) & 0x01; + break; + case AM_HAL_GPIO_OUTPUT_READ: + ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32BaseAddr); + ui32ReadValue = (ui32ReadValue >> ui32Shift) & 0x01; + break; + case AM_HAL_GPIO_ENABLE_READ: + ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, ENA) + ui32BaseAddr); + ui32ReadValue = (ui32ReadValue >> ui32Shift) & 0x01; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + *pui32ReadState = ui32ReadValue; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_gpio_state_read() + +//***************************************************************************** +// +//! @brief Write GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! +//! @param ui32Type - State type to write. One of: +//! AM_HAL_GPIO_OUTPUT_SET - Write a one to a GPIO. +//! AM_HAL_GPIO_OUTPUT_CLEAR - Write a zero to a GPIO. +//! AM_HAL_GPIO_OUTPUT_TOGGLE - Toggle the GPIO value. +//! The following two apply when output is set for TriState (OUTCFG==3). +//! AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE - Enable a tri-state GPIO. +//! AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE - Disable a tri-state GPIO. +//! +//! This function writes a GPIO value. +//! +//! @return Status. +//! Fails if the pad is not configured for GPIO (PADFNCSEL != 3). +// +//***************************************************************************** +uint32_t +am_hal_gpio_state_write(uint32_t ui32Pin, am_hal_gpio_write_type_e eWriteType) +{ + uint32_t ui32Mask, ui32Off; + uint32_t ui32Return = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Pin >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( eWriteType > AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Mask = (uint32_t)0x1 << (ui32Pin % 32); + ui32Off = (ui32Pin & 0x20) >> 3; // 0 or 4 + + AM_CRITICAL_BEGIN; + switch ( eWriteType ) + { + case AM_HAL_GPIO_OUTPUT_SET: // Write a one to a GPIO. + AM_REGVAL(AM_REGADDR(GPIO, WTSA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_CLEAR: // Write a zero to a GPIO. + AM_REGVAL(AM_REGADDR(GPIO, WTCA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TOGGLE: // Toggle the GPIO value. + AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32Off) ^= ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE: // Enable a tri-state GPIO. + AM_REGVAL(AM_REGADDR(GPIO, ENSA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE: // Disable a tri-state GPIO. + AM_REGVAL(AM_REGADDR(GPIO, ENCA) + ui32Off) = ui32Mask; + break; + case AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE: // Toggle a tri-state GPIO. + AM_REGVAL(AM_REGADDR(GPIO, ENCA) + ui32Off) ^= ui32Mask; + break; + default: + // Type values were validated on entry. + // We can't return from here because we're in a critical section. + ui32Return = AM_HAL_STATUS_INVALID_ARG; + break; + } + + AM_CRITICAL_END; + + return ui32Return; +} // am_hal_gpio_state_write() + +//***************************************************************************** +// +// Enable GPIO interrupts. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_enable(uint64_t ui64InterruptMask) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64InterruptMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable the interrupts. + // + AM_CRITICAL_BEGIN + + GPIO->INT0EN |= (uint32_t)(ui64InterruptMask & 0xFFFFFFFF); + GPIO->INT1EN |= (uint32_t)(ui64InterruptMask >> 32); + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_enable() + +//***************************************************************************** +// +// Disable GPIO interrupts. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_disable(uint64_t ui64InterruptMask) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64InterruptMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Disable the interrupts. + // + AM_CRITICAL_BEGIN + + GPIO->INT0EN &= ~((uint32_t)(ui64InterruptMask & 0xFFFFFFFF)); + GPIO->INT1EN &= ~((uint32_t)(ui64InterruptMask >> 32)); + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_disable() + +//***************************************************************************** +// +// Clear GPIO interrupts. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_clear(uint64_t ui64InterruptMask) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64InterruptMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Clear the interrupts. + // + AM_CRITICAL_BEGIN + + GPIO->INT0CLR = (uint32_t)(ui64InterruptMask & 0xFFFFFFFF); + GPIO->INT1CLR = (uint32_t)(ui64InterruptMask >> 32); + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_clear() + +//***************************************************************************** +// +// Get GPIO interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_status_get(bool bEnabledOnly, uint64_t *pui64IntStatus) +{ + + uint64_t ui64RetVal, ui64Mask; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( pui64IntStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize variable outside critical section + // + ui64Mask = 0xFFFFFFFFFFFFFFFF; + + // + // Combine upper or lower GPIO words into one 64 bit return value. + // + AM_CRITICAL_BEGIN + + ui64RetVal = ((uint64_t)GPIO->INT1STAT) << 32; + ui64RetVal |= ((uint64_t)GPIO->INT0STAT) << 0; + + if ( bEnabledOnly ) + { + ui64Mask = ((uint64_t)GPIO->INT1EN) << 32; + ui64Mask |= ((uint64_t)GPIO->INT0EN) << 0; + } + + ui64RetVal &= ui64Mask; + + *pui64IntStatus = ui64RetVal; + + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_status_get() + +//***************************************************************************** +// +// GPIO interrupt service routine registration. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_register(uint32_t ui32GPIONumber, + am_hal_gpio_handler_t pfnHandler) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( pfnHandler == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Store the handler function pointer. + // + gpio_ppfnHandlers[ui32GPIONumber] = pfnHandler; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_register() + +//***************************************************************************** +// +//! @brief Advanced GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @param pCtxt - context for the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_register_adv(uint32_t ui32GPIONumber, + am_hal_gpio_handler_adv_t pfnHandler, void *pCtxt) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( pfnHandler == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Store the handler function pointer. + // + gpio_ppfnHandlers[ui32GPIONumber] = (am_hal_gpio_handler_t)((uint32_t)pfnHandler & ~0x1); + gpio_pHandlerCtxt[ui32GPIONumber] = pCtxt; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_register_adv() + +//***************************************************************************** +// +// GPIO interrupt service routine. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_service(uint64_t ui64Status) +{ + uint32_t ui32RetStatus = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Status, ui32Clz, ui32FFS, ui32Cnt; + + am_hal_gpio_handler_t pfnHandler; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui64Status & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1) ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( ui64Status == 0 ) + { + return AM_HAL_STATUS_FAIL; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Handle interrupts. + // The 1st iteration handles any active interrupts in the lower 32 bits. + // The 2nd iteration handles any active interrupts in the upper 32 bits. + // (The order of handling upper or lower bits is somewhat arbitrary.) + // + ui32Cnt = 0; + while ( ui32Cnt < 33 ) + { + // + // Get upper or lower status word. + // + ui32Status = (uint32_t)(ui64Status >> ui32Cnt); + + while ( ui32Status ) + { + // + // We need to FFS (Find First Set). We can easily zero-base FFS + // since we know that at least 1 bit is set in ui32Status. + // FFS(x) = 31 - clz(x & -x). // Zero-based version of FFS. + // + ui32FFS = ui32Status & (uint32_t)(-(int32_t)ui32Status); +#ifdef __IAR_SYSTEMS_ICC__ + ui32Clz = __CLZ(ui32FFS); +#else + ui32Clz = __builtin_clz(ui32FFS); +#endif + ui32FFS = 31 - ui32Clz; + + // + // Turn off the bit we picked in the working copy + // + ui32Status &= ~(0x00000001 << ui32FFS); + + // + // Check the bit handler table to see if there is an interrupt handler + // registered for this particular bit. + // + pfnHandler = gpio_ppfnHandlers[ui32Cnt + ui32FFS]; + if ( pfnHandler ) + { + // + // If we found an interrupt handler routine, call it now. + // + if ((uint32_t)pfnHandler & 0x1) + { + pfnHandler(); + } + else + { + am_hal_gpio_handler_adv_t padvHandler = (am_hal_gpio_handler_adv_t)((uint32_t)pfnHandler | 0x1); + padvHandler(gpio_pHandlerCtxt[ui32Cnt + ui32FFS]); + } + } + else + { + // + // No handler was registered for the GPIO that interrupted. + // Return an error. + // + ui32RetStatus = AM_HAL_STATUS_INVALID_OPERATION; + } + } + ui32Cnt += 32; + } + + // + // Return the status. + // + return ui32RetStatus; + +} // am_hal_gpio_interrupt_service() + + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32Config - Contains multiple descriptor fields. +//! +//! This function configures a pin according to the parameters in ui32Config. +//! All parameters are validated, and the given pin is configured according +//! to the designated parameters. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t ap3_hal_gpio_pinconfig_partial(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg, am_hal_gpio_pincfg_allow_t sAllowableChanges) //am_hal_gpio_pincfg_t bfGpioCfgMsk) +{ + uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg; + uint32_t ui32Funcsel, ui32PowerSw; + uint8_t padRegMask = 0, GPCfgMask = 0, altPadCfgMask = 0; + bool bClearEnable = false; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (ui32Pin >= AM_HAL_GPIO_MAX_PADS) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ap3_gpio_get_pinconfig_bitmasks(sAllowableChanges, &padRegMask, &GPCfgMask, &altPadCfgMask); + // + // Initialize the PADREG accumulator variables. + // + ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0; + + // + // Get the requested function and/or power switch. + // + ui32Funcsel = bfGpioCfg.uFuncSel; + ui32PowerSw = bfGpioCfg.ePowerSw; + + ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S; + + // + // Check for invalid configuration requests. + // + if (bfGpioCfg.ePullup != AM_HAL_GPIO_PIN_PULLUP_NONE) + { + // + // This setting is needed for all pullup settings including + // AM_HAL_GPIO_PIN_PULLUP_WEAK and AM_HAL_GPIO_PIN_PULLDOWN. + // + ui32Padreg |= (0x1 << PADREG_FLD_PULLUP_S); + + // + // Check for specific pullup or pulldown settings. + // + if ((bfGpioCfg.ePullup >= AM_HAL_GPIO_PIN_PULLUP_1_5K) && + (bfGpioCfg.ePullup <= AM_HAL_GPIO_PIN_PULLUP_24K)) + { + ui32Padreg |= ((bfGpioCfg.ePullup - AM_HAL_GPIO_PIN_PULLUP_1_5K) << PADREG_FLD_76_S); +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!(g_ui8Bit76Capabilities[ui32Pin] & CAP_PUP)) + { + return AM_HAL_GPIO_ERR_PULLUP; + } + } + else if (bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLDOWN) + { + if (ui32Pin != 20) + { + return AM_HAL_GPIO_ERR_PULLDOWN; + } + } + else if (bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLUP_WEAK) + { + // + // All pads except 20 support a weak pullup, for which we only need + // to set PADnPULL and clear 7:6 (already done at this point). + // + if (ui32Pin == 20) + { + return AM_HAL_GPIO_ERR_PULLUP; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + } + } + + // + // Check if requesting a power switch pin + // + if (ui32PowerSw != AM_HAL_GPIO_PIN_POWERSW_NONE) + { + if ((ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VDD) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VDD)) + { + ui32Padreg |= 0x1 << PADREG_FLD_76_S; + } + else if ((ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VSS) && + (g_ui8Bit76Capabilities[ui32Pin] & CAP_VSS)) + { + ui32Padreg |= 0x2 << PADREG_FLD_76_S; + } + else + { + return AM_HAL_GPIO_ERR_PWRSW; + } + } + + // + // Depending on the selected pin and FNSEL, determine if INPEN needs to be set. + // + ui32Padreg |= (g_ui8Inpen[ui32Pin] & (1 << ui32Funcsel)) ? (1 << PADREG_FLD_INPEN_S) : 0; + + // + // Configure ui32GpCfg based on whether nCE requested. + // + if (g_ui8nCEpins[ui32Pin] == ui32Funcsel) + { + uint32_t ui32Outcfg; + uint8_t ui8CEtbl; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // User is configuring a nCE. Verify the requested settings and set the + // polarity and OUTCFG values (INCFG is not used here and should be 0). + // Valid uNCE values are 0-3 (uNCE is a 2-bit field). + // Valid uIOMnum are 0-6 (0-5 for IOMs, 6 for MSPI, 7 is invalid). + // + if (bfGpioCfg.uIOMnum > IOMNUM_MAX) + { + return AM_HAL_GPIO_ERR_INVCE; // Invalid CE specified + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Construct the entry we expect to find in the table. We can determine + // the OUTCFG value by looking for that value in the pin row. + // + ui8CEtbl = (bfGpioCfg.uIOMnum << 4) | bfGpioCfg.uNCE; + for (ui32Outcfg = 0; ui32Outcfg < 4; ui32Outcfg++) + { + if (g_ui8NCEtable[ui32Pin][ui32Outcfg] == ui8CEtbl) + { + break; + } + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (ui32Outcfg >= 4) + { + return AM_HAL_GPIO_ERR_INVCEPIN; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32GPCfg |= (ui32Outcfg << GPIOCFG_FLD_OUTCFG_S) | + (bfGpioCfg.eCEpol << GPIOCFG_FLD_INTD_S) | + (0 << GPIOCFG_FLD_INCFG_S); + } + else + { + // + // It's not nCE, it's one of the other funcsels. + // Start by setting the value of the requested GPIO input. + // + ui32Padreg |= (bfGpioCfg.eGPInput << PADREG_FLD_INPEN_S); + + // + // Map the requested interrupt direction settings into the Apollo3 + // GPIOCFG register field, which is a 4-bit field: + // [INTD(1):OUTCFG(2):INCFG(1)]. + // Bit0 of eIntDir maps to GPIOCFG.INTD (b3). + // Bit1 of eIntDir maps to GPIOCFG.INCFG (b0). + // + ui32GPCfg |= (bfGpioCfg.eGPOutcfg << GPIOCFG_FLD_OUTCFG_S) | + (((bfGpioCfg.eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | + (((bfGpioCfg.eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S); + + if ((bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL) || + pincfg_equ(&bfGpioCfg, (void *)&g_AM_HAL_GPIO_DISABLE)) + { + // + // For pushpull configurations, we must be sure to clear the ENABLE + // bit. In pushpull, these bits turn on FAST GPIO. For regular + // GPIO, they must be clear. + // + bClearEnable = true; + } + + // + // There is some overlap between eGPRdZero and eIntDir as both settings + // utilize the overloaded INCFG bit. + // Therefore the two fields should be used in a mutually exclusive + // manner. For flexibility however they are not disallowed because + // their functionality is dependent on FUNCSEL and whether interrupts + // are used. + // + // In the vein of mutual exclusion, eGPRdZero is primarily intended for + // use when GPIO interrupts are not in use and can be used when no + // eIntDir setting is provided. + // If eIntDir is provided, eGPRdZero is ignored and can only be + // achieved via the AM_HAL_GPIO_PIN_INTDIR_NONE setting. + // + if (bfGpioCfg.eIntDir == 0) + { + ui32GPCfg &= ~(1 << GPIOCFG_FLD_INCFG_S); + ui32GPCfg |= (bfGpioCfg.eGPRdZero << GPIOCFG_FLD_INCFG_S); + } + } + + switch (bfGpioCfg.eDriveStrength) + { + // DRIVESTRENGTH is a 2-bit field. + // bit0 maps to bit2 of a PADREG field. + // bit1 maps to bit0 of an ALTPADCFG field. + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (0 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA: + ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + case AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA: + ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S); + ui32AltPadCfg |= (1 << 0); + break; + } + + // + // At this point, the 3 configuration variables, ui32GPCfg, ui32Padreg, + // and ui32AltPadCfg values are set (at bit position 0) and ready to write + // to their respective register bitfields. + // + uint32_t ui32GPCfgAddr, ui32PadregAddr, ui32AltpadAddr; + uint32_t ui32GPCfgClearMask, ui32PadClearMask, ui32AltPadClearMask; + uint32_t ui32GPCfgShft, ui32PadShft; + + ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3); + ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3); + ui32AltpadAddr = AM_REGADDR(GPIO, ALTPADCFGA) + (ui32Pin & ~0x3); + + ui32GPCfgShft = ((ui32Pin & 0x7) << 2); + ui32PadShft = ((ui32Pin & 0x3) << 3); + ui32GPCfgClearMask = ~((uint32_t)GPCfgMask << ui32GPCfgShft); + ui32PadClearMask = ~((uint32_t)padRegMask << ui32PadShft); + ui32AltPadClearMask = ~((uint32_t)altPadCfgMask << ui32PadShft); + + // + // Get the new values into their rightful bit positions. + // + ui32Padreg = (ui32Padreg & (uint32_t)padRegMask) << ui32PadShft; + ui32AltPadCfg = (ui32AltPadCfg & (uint32_t)altPadCfgMask) << ui32PadShft; + ui32GPCfg = (ui32GPCfg & (uint32_t)GPCfgMask) << ui32GPCfgShft; + + AM_CRITICAL_BEGIN + + if (bClearEnable) + { + // + // We're configuring a mode that requires clearing the Enable bit. + // + am_hal_gpio_output_tristate_disable(ui32Pin); + } + + GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key; + + AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; + AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; + AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32AltPadClearMask) | ui32AltPadCfg; + + GPIO->PADKEY = 0; + + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; + +} //ap3_hal_gpio_pinconfig_partial + +void ap3_gpio_get_pinconfig_bitmasks(am_hal_gpio_pincfg_allow_t sAllowableChanges, uint8_t *padRegMask, uint8_t *GPCfgMask, uint8_t *altPadCfgMask) +{ + *padRegMask = 0; + *GPCfgMask = 0; + *altPadCfgMask = 0; + + if (sAllowableChanges.uFuncSel) + { + *padRegMask |= 0x38; //bits 3-5 PadReg + } + if (sAllowableChanges.ePowerSw) + { + *padRegMask |= 0xC0; //bits 6 and 7 PadReg + } + if (sAllowableChanges.ePullup) + { + *padRegMask |= 0xC1; //bits 6 and 7 and 0 PadReg + } + if (sAllowableChanges.eDriveStrength) + { + *padRegMask |= 0x04; //bit 2 PadReg + *altPadCfgMask |= 0x10; //bit 4 AltPadReg + } + if (sAllowableChanges.eGPOutcfg) + { + *GPCfgMask |= 0x06; //bits 1 and 2 CFGReg + } + if (sAllowableChanges.eGPInput) + { + *padRegMask |= 0x02; //bit 1 PadReg + } + if (sAllowableChanges.eIntDir) + { + *GPCfgMask |= 0x09; //bit 0 and 3 CFGReg + } + if (sAllowableChanges.eGPRdZero) + { + *GPCfgMask |= 0x01; //bit 0 CFGReg + } +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.h new file mode 100644 index 0000000000..648a40f964 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_gpio.h @@ -0,0 +1,899 @@ +//***************************************************************************** +// +// am_hal_gpio.h +//! @file +//! +//! @brief Functions for accessing and configuring the GPIO module. +//! +//! @addtogroup gpio3 GPIO +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_GPIO_H +#define AM_HAL_GPIO_H 1 + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_GPIO 1 + +// +// Maximum number of GPIOs on this device +// +#define AM_HAL_GPIO_MAX_PADS (50) +#define AM_HAL_GPIO_NUMWORDS ((AM_HAL_GPIO_MAX_PADS + 31) / 32) + +// +//! Macros to assist with defining a GPIO mask given a GPIO number. +//! +//! IMPORTANT: AM_HAL_GPIO_BIT(n) is DEPRECATED and is provided only for +//! backward compatibility. It is replaced with AM_HAL_GPIO_MASKBIT(). +// +#define AM_HAL_GPIO_BIT(n) (((uint64_t) 0x1) << n) /* DEPRECATED, PLEASE USE AM_HAL_GPIO_MASKBIT() */ + +//! +//! The following macros ensure forward compatibility with future SDK releases. +//! They should be used, in lieu of AM_HAL_GPIO_BIT(), when creating bitmasks +//! for GPIO interrupts. +//! AM_HAL_GPIO_MASKCREATE() +//! AM_HAL_GPIO_MASKBIT() +//! + +#define AM_HAL_GPIO_MASKCREATE(sMaskNm) uint64_t p##sMaskNm=0 +//! AM_HAL_GPIO_MASKCREATE() should be used before AM_HAL_GPIO_MASKBIT() to +//! ensure forward compatibility. In future releases it will allocate and +//! initialize a bitmask structure used in the various GPIO interrupt functions. +//! + +// Implented as an inline function below. +//#define AM_HAL_GPIO_MASKBIT(psMaskNm, n) (psMaskNm |= (((uint64_t) 0x1) << n)) +#define AM_HAL_GPIO_MASKBIT(psMaskNm, n) psMaskNm |= (((uint64_t) 0x1) << n) +//! AM_HAL_GPIO_MASKBIT(psMaskNm, n) +//! Support macros for use with AM_HAL_GPIO_MASKBIT(). +//! AM_HAL_GPIO_MASKCREATE() +//! AM_HAL_GPIO_MASKCLR() +//! +//! To set a single bit based on a pin number in an existing bitmask structure. +//! AM_HAL_GPIO_MASKBIT(pGpioIntMask, n) +//! where n is the desired GPIO bit number. +//! Note - this usage is analogous to the deprecated AM_HAL_GPIO_BIT(n). +//! + +#define AM_HAL_GPIO_MASKCLR(psMaskNm) +//! AM_HAL_GPIO_MASKCLR() +//! Clear an existing GpioIntMask bitmask structure. +//! Note that AM_HAL_GPIO_MASKCREATE() clears the bitmask struct on creation. +//! IMPORTANT - The AM_HAL_GPIO_MASKCLR() macro does not operate on any hardware +//! or register. It is used for initializing/clearing the memory allocated for +//! the bitmask structure. +//! +//! // Usage example for any Apollo device: +//! // Create a GPIO interrupt bitmask structure named GpioIntMask, initialize +//! // that structure, and create a ptr to that structure named pGpioIntMask. +//! // Then use that structure to pass a bitmask to the interrupt function. +//! AM_HAL_GPIO_MASKCREATE(GpioIntMask); +//! am_hal_gpio_interrupt_clear(AM_HAL_GPIO_MASKBIT(pGpioIntMask)); +//! + +//***************************************************************************** +//! +//! Structure for defining bitmasks used in the interrupt functions. +//! +//***************************************************************************** +typedef struct // Future use - not currently used for Apollo3. +{ + union + { + volatile uint32_t Msk[AM_HAL_GPIO_NUMWORDS]; + + struct + { + volatile uint32_t b0: 1; + volatile uint32_t b1: 1; + volatile uint32_t b2: 1; + volatile uint32_t b3: 1; + volatile uint32_t b4: 1; + volatile uint32_t b5: 1; + volatile uint32_t b6: 1; + volatile uint32_t b7: 1; + volatile uint32_t b8: 1; + volatile uint32_t b9: 1; + volatile uint32_t b10: 1; + volatile uint32_t b11: 1; + volatile uint32_t b12: 1; + volatile uint32_t b13: 1; + volatile uint32_t b14: 1; + volatile uint32_t b15: 1; + volatile uint32_t b16: 1; + volatile uint32_t b17: 1; + volatile uint32_t b18: 1; + volatile uint32_t b19: 1; + volatile uint32_t b20: 1; + volatile uint32_t b21: 1; + volatile uint32_t b22: 1; + volatile uint32_t b23: 1; + volatile uint32_t b24: 1; + volatile uint32_t b25: 1; + volatile uint32_t b26: 1; + volatile uint32_t b27: 1; + volatile uint32_t b28: 1; + volatile uint32_t b29: 1; + volatile uint32_t b30: 1; + volatile uint32_t b31: 1; + volatile uint32_t b32: 1; + volatile uint32_t b33: 1; + volatile uint32_t b34: 1; + volatile uint32_t b35: 1; + volatile uint32_t b36: 1; + volatile uint32_t b37: 1; + volatile uint32_t b38: 1; + volatile uint32_t b39: 1; + volatile uint32_t b40: 1; + volatile uint32_t b41: 1; + volatile uint32_t b42: 1; + volatile uint32_t b43: 1; + volatile uint32_t b44: 1; + volatile uint32_t b45: 1; + volatile uint32_t b46: 1; + volatile uint32_t b47: 1; + volatile uint32_t b48: 1; + volatile uint32_t b49: 1; + volatile uint32_t brsvd: 14; // Pad out to the next full word + } Msk_b; + } U; +} am_hal_gpio_mask_t; + +//***************************************************************************** +//! +//! Read types for am_hal_gpio_state_read(). +//! +//***************************************************************************** +typedef enum +{ + AM_HAL_GPIO_INPUT_READ, + AM_HAL_GPIO_OUTPUT_READ, + AM_HAL_GPIO_ENABLE_READ +} am_hal_gpio_read_type_e; + +//***************************************************************************** +//! +//! Write types for am_hal_gpio_state_write(). +//! +//***************************************************************************** +typedef enum +{ + AM_HAL_GPIO_OUTPUT_CLEAR, + AM_HAL_GPIO_OUTPUT_SET, + AM_HAL_GPIO_OUTPUT_TOGGLE, + AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE, + AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE, + AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE +} am_hal_gpio_write_type_e; + + +//***************************************************************************** +//! +//! Types for ui32GpioCfg bitfields in am_hal_gpio_pinconfig(). +//! +//***************************************************************************** +//! +//! Power Switch configuration: am_hal_gpio_pincfg_t.ePowerSw enums +//! +typedef enum +{ + AM_HAL_GPIO_PIN_POWERSW_NONE, + AM_HAL_GPIO_PIN_POWERSW_VDD, + AM_HAL_GPIO_PIN_POWERSW_VSS, + AM_HAL_GPIO_PIN_POWERSW_INVALID, +} am_hal_gpio_powersw_e; + +//! +//! Pullup configuration: am_hal_gpio_pincfg_t.ePullup enums +//! +typedef enum +{ + // + //! Define pullup enums. + //! The 1.5K - 24K pullup values are valid for select I2C enabled pads. + //! For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49. + //! The "weak" value is used for almost every other pad except pin 20. + // + AM_HAL_GPIO_PIN_PULLUP_NONE = 0x00, + AM_HAL_GPIO_PIN_PULLUP_WEAK, + AM_HAL_GPIO_PIN_PULLUP_1_5K, + AM_HAL_GPIO_PIN_PULLUP_6K, + AM_HAL_GPIO_PIN_PULLUP_12K, + AM_HAL_GPIO_PIN_PULLUP_24K, + AM_HAL_GPIO_PIN_PULLDOWN +} am_hal_gpio_pullup_e; + +//! +//! Pad Drive Strength configuration: am_hal_gpio_pincfg_t.eDriveStrength enums +//! +typedef enum +{ + // + //! DRIVESTRENGTH is a 2-bit field. + //! bit0 maps to bit2 of a PADREG field. + //! bit1 maps to bit0 of an ALTPADCFG field. + // + AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA = 0x0, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA = 0x1, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA = 0x2, + AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA = 0x3 +} am_hal_gpio_drivestrength_e; + +//! +//! OUTCFG pad configuration: am_hal_gpio_pincfg_t.eGPOutcfg enums +//! Applies only to GPIO configured pins. +//! Ultimately maps to GPIOCFG.OUTCFG, bits [2:1]. +//! +typedef enum +{ + AM_HAL_GPIO_PIN_OUTCFG_DISABLE = 0x0, + AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL = 0x1, + AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN = 0x2, + AM_HAL_GPIO_PIN_OUTCFG_TRISTATE = 0x3 +} am_hal_gpio_outcfg_e; + +//! +//! GPIO input configuration: am_hal_gpio_pincfg_t.eGPInput enums +//! Applies only to GPIO configured pins! +//! Ultimately maps to PADREG.INPEN, bit1. +//! +typedef enum +{ + AM_HAL_GPIO_PIN_INPUT_AUTO = 0x0, + AM_HAL_GPIO_PIN_INPUT_NONE = 0x0, + AM_HAL_GPIO_PIN_INPUT_ENABLE = 0x1 +} am_hal_gpio_input_e; + +//! +//! GPIO interrupt direction configuration: am_hal_gpio_pincfg_t.eIntDir enums +//! Note: Setting INTDIR_NONE has the side-effect of disabling being able to +//! read a pin - the pin will always read back as 0. +//! +typedef enum +{ + // Bit1 of these values maps to GPIOCFG.INCFG (b0). + // Bit0 of these values maps to GPIOCFG.INTD (b3). + AM_HAL_GPIO_PIN_INTDIR_LO2HI = 0x0, + AM_HAL_GPIO_PIN_INTDIR_HI2LO = 0x1, + AM_HAL_GPIO_PIN_INTDIR_NONE = 0x2, + AM_HAL_GPIO_PIN_INTDIR_BOTH = 0x3 +} am_hal_gpio_intdir_e; + +//! +//! am_hal_gpio_pincfg_t.eGPRdZero +//! For GPIO configurations (funcsel=3), the pin value can be read or 0 can be +//! forced as the read value. +//! +typedef enum +{ + AM_HAL_GPIO_PIN_RDZERO_READPIN = 0x0, + AM_HAL_GPIO_PIN_RDZERO_ZERO = 0x1 +} am_hal_gpio_readen_e; + +//! +//! nCE polarity configuration: am_hal_gpio_pincfg_t.eCEpol enums +//! +typedef enum +{ + AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW = 0x0, + AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH = 0x1 +} am_hal_gpio_cepol_e; + + +// +// Apollo3 usage of bits [7:6] of a PADREG field: +// PULLUPs are available on pins: 0,1,5,6,8,9,25,27,39,40,42,43,48,49 +// RESERVED on pins: 2,4,7,10-24,26,28-35,38,44-47 +// VDD PWR on pins: 3, 36 (b7=0, b6=1) +// VSS PWR on pins: 37,41 (b7=1, b6=0) +// + +//! +//! Define the am_hal_gpio_pinconfig() bitfield structure. +//! uFuncSel a value of 0-7 corresponding to the FNCSEL field of PADREG. +//! ePowerSw: Select pins can be set as a power source or sink. +//! ePullup: Select pins can enable a pullup of varying values. +//! eDriveStrength: Select pins can be set for varying drive strengths. +//! eGPOutcfg: GPIO pin only, corresponds to GPIOCFG.OUTCFG field. +//! eGPInput: GPIO pin only, corresponds to PADREG.INPEN. +//! eGPRdZero: GPIO read zero. Corresponds to GPIOCFG.INCFG. +//! eIntDir: Interrupt direction, l2h, h2l, both, none. +//! eGPRdZero: Read the pin value, or always read the pin as zero. +//! uIOMnum: nCE pin IOMnumber (0-5, or 6 for MSPI) +//! nNCE: Selects the SPI channel (CE) number (0-3) +//! eCEpol: CE polarity. +//! +typedef struct +{ + uint32_t uFuncSel : 3; // [2:0] Function select (FUNCSEL) + uint32_t ePowerSw : 2; // [4:3] Pin is a power switch source (VCC) or sink (VSS) + uint32_t ePullup : 3; // [7:5] Pin will enable a pullup resistor + uint32_t eDriveStrength : 2; // [9:8] Pad strength designator + uint32_t eGPOutcfg : 2; // [11:10] OUTCFG (GPIO config only) + uint32_t eGPInput : 1; // [12:12] GPIO Input (GPIO config only) + uint32_t eIntDir : 2; // [14:13] Interrupt direction + uint32_t eGPRdZero : 1; // [15:15] GPIO read as zero + + // + // The following descriptors designate the chip enable features of the + // pin being configured. If not a CE, these descriptors are ignored. + // uIOMnum is 0-5 for the IOMs, or 6 for MSPI, 7 is invalid. + // + uint32_t uIOMnum : 3; // [18:16] IOM number (0-5), 6 for MSPI + uint32_t uNCE : 2; // [20:19] NCE number (0-3). + uint32_t eCEpol : 1; // [21:21] NCE polarity. + + uint32_t uRsvd22 : 10; // [31:22] +} am_hal_gpio_pincfg_t; + +typedef struct +{ + uint16_t uFuncSel : 1; + uint16_t ePowerSw : 1; + uint16_t ePullup : 1; + uint16_t eDriveStrength : 1; + uint16_t eGPOutcfg : 1; + uint16_t eGPInput : 1; + uint16_t eIntDir : 1; + uint16_t eGPRdZero : 1; + uint16_t uIOMnum : 1; + uint16_t uNCE : 1; + uint16_t eCEpol : 1; + + uint16_t _reserved : 5; +} am_hal_gpio_pincfg_allow_t; + +#define IOMNUM_MSPI 6 +#define IOMNUM_MAX IOMNUM_MSPI + +// +// Define shift and width values for the above bitfields. +// - C bitfields do not provide shift, width, or mask values. +// - Shift values are generally compiler specific. However for IAR, Keil, and +// GCC, the bitfields are all exactly as defined in the above structure. +// - These defines should be used sparingly. +// +#define UFUNCSEL_S 0 +#define EPOWERSW_S 3 +#define EPULLUP_S 5 +#define EDRVSTR_S 8 +#define EGPOUTCFG_S 10 +#define EGPINPUT_S 12 +#define EINTDIR_S 13 +#define UIOMNUM_S 16 +#define UNCE_S 19 +#define ECEPOL_S 21 + +#define UFUNCSEL_W 3 +#define EPOWERSW_W 2 +#define EPULLUP_W 3 +#define EDRVSTR_W 2 +#define EGPOUTCFG_W 2 +#define EGPINPUT_W 1 +#define EINTDIR_W 2 +#define UIOMNUM_W 3 +#define UNCE_W 2 +#define ECEPOL_W 1 + +//! +//! Define GPIO error codes that are returned by am_hal_gpio_pinconfig(). +//! +enum am_hal_gpio_pincfgerr +{ + AM_HAL_GPIO_ERR_PULLUP = (AM_HAL_STATUS_MODULE_SPECIFIC_START + 0x100), + AM_HAL_GPIO_ERR_PULLDOWN, + AM_HAL_GPIO_ERR_PWRSW, + AM_HAL_GPIO_ERR_INVCE, + AM_HAL_GPIO_ERR_INVCEPIN, + AM_HAL_GPIO_ERR_PULLUPENUM +}; + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +//***************************************************************************** +// Define some common GPIO pin configurations. +//***************************************************************************** +//! Basics +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_DISABLE; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_TRISTATE; + +//! Input variations +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT; +//! Input with various pullups (weak, 1.5K, 6K, 12K, 24K) +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_1_5; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_6; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_12; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_INPUT_PULLUP_24; + +//! Output variations +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_4; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_8; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_12; +extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_WITH_READ; + +//***************************************************************************** +// +// Function pointer type for GPIO interrupt handlers. +// +//***************************************************************************** +typedef void (*am_hal_gpio_handler_t)(void); +typedef void (*am_hal_gpio_handler_adv_t)(void *); + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32GpioCfg - Contains multiple descriptor fields. +//! +//! This function configures a pin according to the descriptor parameters as +//! passed in sPinCfg. All parameters are validated with regard to each +//! other and according to the requested function. Once the parameters and +//! settings have been confirmed, the pin is configured accordingly. +//! +//! @return Status. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_pinconfig(uint32_t ui32Pin, + am_hal_gpio_pincfg_t sPincfg); + +//***************************************************************************** +// +//! @brief Configure specified pins for FAST GPIO operation. +//! +//! @param ui64PinMask - a mask specifying up to 8 pins to be configured and +//! used for FAST GPIO (only bits 0-49 are valid). +//! @param bfGpioCfg - The GPIO configuration (same as am_hal_gpio_pinconfig()). +//! All of the pins specified by ui64PinMask will be set to this +//! configuration. +//! @param ui32Masks - If NULL, not used. Otherwise if provided, an array to +//! receive two 32-bit values, per pin, of the SET and CLEAR +//! masks that can be used for the BBSETCLEAR register. +//! The two 32-bit values will be placed at incremental indexes. +//! For example, say pin numbers 5 and 19 are indicated in the +//! mask, and an array pointer is provided in ui32Masks. This +//! array must be allocated by the caller to be at least 4 wds. +//! ui32Masks[0] = the set mask used for pin 5. +//! ui32Masks[1] = the clear mask used for pin 5. +//! ui32Masks[2] = the set mask used for pin 19. +//! ui32Masks[3] = the clear mask used for pin 19. +//! +//! @return Status. +//! +//! Fast GPIO helper macros: +//! am_hal_gpio_fastgpio_set(n) - Sets the value for pin number 'n'. +//! am_hal_gpio_fastgpio_clr(n) - Clear the value for pin number 'n'. +//! +//! am_hal_gpio_fastgpio_enable(n) - Enable Fast GPIO on pin 'n'. +//! am_hal_gpio_fastgpio_disable(n) - Disable Fast GPIO on pin 'n'. +//! +//! Note - The enable and disable macros assume the pin has already been +//! configured. Once disabled, the state of the pin will revert to the +//! state of the normal GPIO configuration for that pin. +//! +//! NOTES on pin configuration: +//! - To avoid glitches on the pin, it is strongly recommended that before +// calling am_hal_gpio_fast_pinconfig() that am_hal_gpio_fastgpio_disable() +//! first be called to make sure that Fast GPIO is disabled before config. +//! - If the state of the pin is important, preset the value of the pin to the +//! desired value BEFORE calling am_hal_gpio_fast_pinconfig(). The set and +//! clear macros shown above can be used for this purpose. +//! +//! NOTES on general use of Fast GPIO: +//! Fast GPIO input or output will not work if the pin is configured as +//! tristate. The overloaded OUTPUT ENABLE control is used for enabling both +//! modes, so Apollo3 logic specifically disallows Fast GPIO input or output +//! when the pin is configured for tristate mode. +//! Fast GPIO input can be used for pushpull, opendrain, or disable modes. +//! +//! Fast GPIO pin groupings: +//! The FaST GPIO pins are grouped across a matrix of pins. Each +//! row of pins is controlled by a single data bit. +//! +//! Referring to the below chart: +//! If pin 35 were configured for Fast GPIO output, it would be set +//! when bit3 of BBSETCLEAR.SET was written with a 1. +//! It would be cleared when bit3 of BBSETCLEAR.CLEAR was written with 1. +//! +//! Note that if all the pins in a row were configured for Fast GPIO output, +//! all the pins would respond to set/clear. +//! +//! Input works in a similar fashion. +//! +//! BIT PIN controlled +//! --- --------------------------- +//! 0 0 8 16 24 32 40 48 +//! 1 1 9 17 25 33 41 49 +//! 2 2 10 18 26 34 42 +//! 3 3 11 19 27 35 43 +//! 4 4 12 20 28 36 44 +//! 5 5 13 21 29 37 45 +//! 6 6 14 22 30 38 46 +//! 7 7 15 23 31 39 47 +//! +// +//***************************************************************************** +extern uint32_t am_hal_gpio_fast_pinconfig(uint64_t ui64PinMask, + am_hal_gpio_pincfg_t bfGpioCfg, + uint32_t ui32Masks[]); + +//***************************************************************************** +// +//! @brief Read GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! @param eReadType - State type to read. One of: +//! AM_HAL_GPIO_INPUT_READ +//! AM_HAL_GPIO_OUTPUT_READ +//! AM_HAL_GPIO_ENABLE_READ +//! +//! This function reads a pin state as given by eReadType. +//! +//! @return Status. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_state_read(uint32_t ui32Pin, + am_hal_gpio_read_type_e eReadType, + uint32_t *pu32RetVal); + +//***************************************************************************** +// +//! @brief Write GPIO. +//! +//! @param ui32Pin - pin number to be read. +//! +//! @param eWriteType - State type to write. One of: +//! AM_HAL_GPIO_OUTPUT_SET - Write a one to a GPIO. +//! AM_HAL_GPIO_OUTPUT_CLEAR - Write a zero to a GPIO. +//! AM_HAL_GPIO_OUTPUT_TOGGLE - Toggle the GPIO value. +//! The following two apply when output is set for TriState (OUTCFG==3). +//! AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE - Enable a tri-state GPIO. +//! AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE - Disable a tri-state GPIO. +//! +//! This function writes a GPIO value. +//! +//! @return Status. +//! Fails if the pad is not configured for GPIO (PADFNCSEL != 3). +// +//***************************************************************************** +extern uint32_t am_hal_gpio_state_write(uint32_t ui32Pin, + am_hal_gpio_write_type_e eWriteType); + +//***************************************************************************** +// +//! @brief Enable GPIO interrupts. +//! +//! @param ui64InterruptMask - Mask of GPIO interrupts to enable. +//! Only bits 0-49 are valid in the mask. +//! +//! @return Status. +//! Fails if any bit above bit49 is set in ui64InterruptMask. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_enable(uint64_t ui64InterruptMask); + +//***************************************************************************** +// +//! @brief Disable GPIO interrupts. +//! +//! @param ui64InterruptMask - Mask of GPIO interrupts to disable. +//! Only bits 0-49 are valid in the mask. +//! +//! @return Status. +//! Fails if any bit above bit49 is set in ui64InterruptMask. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_disable(uint64_t ui64InterruptMask); + +//***************************************************************************** +// +//! @brief Clear GPIO interrupts. +//! +//! @param ui64InterruptMask - Mask of GPIO interrupts to be cleared. +//! Only bits 0-49 are valid in the mask. +//! +//! @return Status. +//! Fails if any bit above bit49 is set in ui64InterruptMask. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_clear(uint64_t ui64InterruptMask); + +//***************************************************************************** +// +//! @brief Get GPIO interrupt status. +//! +//! @param bEnabledOnly - Return status only for currently enabled interrupts. +//! +//! @param pui64IntStatus - 64-bit variable to return a bitmask of the status +//! of the interrupts. +//! +//! @return Status. +//! Fails if pui64IntStatus is NULL. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_status_get(bool bEnabledOnly, + uint64_t *pui64IntStatus); + +//***************************************************************************** +// +//! @brief GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_register(uint32_t ui32GPIONumber, + am_hal_gpio_handler_t pfnHandler); + +//***************************************************************************** +// +//! @brief Advanced GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @param pCtxt - context for the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_register_adv(uint32_t ui32GPIONumber, + am_hal_gpio_handler_adv_t pfnHandler, void *pCtxt); + +//***************************************************************************** +// +// GPIO interrupt service routine. +//! @brief GPIO interrupt service routine registration. +//! +//! @param ui64Status - Mask of the interrupt(s) to be serviced. This mask is +//! typically obtained via a call to am_hal_gpio_interrupt_status_get(). +//! +//! The intended use is that the application first registers a handler for a +//! particular GPIO via am_hal_gpio_interrupt_register(), and to supply the +//! main ISR, am_gpio_isr(). +//! +//! On a GPIO interrupt, am_gpio_isr() calls am_hal_gpio_interrupt_status_get() +//! and provides the return value to this function. +//! +//! In the event that multiple GPIO interrupts are active, the corresponding +//! interrupt handlers will be called in numerical order by GPIO number +//! starting with the lowest GPIO number. +//! +//! @return Status. +//! AM_HAL_STATUS_INVALID_OPERATION if no handler had been registered +//! for any of the GPIOs that caused the interrupt. +//! AM_HAL_STATUS_OUT_OF_RANGE if any bit above bit49 is set. +//! AM_HAL_STATUS_FAIL if ui64Status is 0. +//! AM_HAL_STATUS_SUCCESS otherwise. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_service(uint64_t ui64Status); + +//***************************************************************************** +// +//! @brief Configure an Apollo3 pin. +//! +//! @param ui32Pin - pin number to be configured. +//! @param ui32Config - Contains multiple descriptor fields. +//! @param sAllowableChanges - Contains bools corresponding to config fields. +//! +//! This function configures a pin according to the parameters in ui32Config. +//! All parameters are validated, and the given pin is configured according +//! to the designated parameters. +//! +//! @return Status. +// +//***************************************************************************** +uint32_t ap3_hal_gpio_pinconfig_partial(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg, am_hal_gpio_pincfg_allow_t sAllowableChanges); + +//***************************************************************************** +// +//! @brief Macros to read GPIO values in an optimized manner. +//! +//! @param n - The GPIO number to be read. +//! +//! In almost all cases, it is reasonable to use am_hal_gpio_state_read() to +//! read GPIO values with all of the inherent error checking, critical +//! sectioning, and general safety. +//! +//! However, occasionally there is a need to read a GPIO value in an optimized +//! manner. These 3 macros will accomplish that. Each macro will return a +//! value of 1 or 0. +//! +//! Note that the macros are named as lower-case counterparts to the +//! enumerations for the am_hal_gpio_state_read() function. That is: +//! +//! AM_HAL_GPIO_INPUT_READ -> am_hal_gpio_input_read(n) +//! AM_HAL_GPIO_OUTPUT_READ -> am_hal_gpio_output_read(n) +//! AM_HAL_GPIO_ENABLE_READ -> am_hal_gpio_enable_read(n) +//! +//! @return Each macro will return a 1 or 0 per the value of the requested GPIO. +//! +// +//***************************************************************************** +#define am_hal_gpio_input_read(n) ( \ + (AM_REGVAL( (AM_REGADDR(GPIO, RDA) + (((uint32_t)(n) & 0x20) >> 3)) ) >> /* Read appropriate register */ \ + ((uint32_t)(n) & 0x1F) ) & /* Shift by appropriate number of bits */ \ + ((uint32_t)0x1) ) /* Mask out the LSB */ + +#define am_hal_gpio_output_read(n) ( \ + (AM_REGVAL( (AM_REGADDR(GPIO, WTA) + (((uint32_t)(n) & 0x20) >> 3)) ) >> /* Read appropriate register */ \ + ((uint32_t)(n) & 0x1F) ) & /* Shift by appropriate number of bits */ \ + ((uint32_t)0x1) ) /* Mask out the LSB */ + +#define am_hal_gpio_enable_read(n) ( \ + (AM_REGVAL( (AM_REGADDR(GPIO, ENA) + (((uint32_t)(n) & 0x20) >> 3)) ) >> /* Read appropriate register */ \ + ((uint32_t)(n) & 0x1F) ) & /* Shift by appropriate number of bits */ \ + ((uint32_t)0x1) ) /* Mask out the LSB */ + + +//***************************************************************************** +// +//! @brief Macros to write GPIO values in an optimized manner. +//! +//! @param n - The GPIO number to be written. +//! +//! In almost all cases, it is reasonable to use am_hal_gpio_state_write() to +//! write GPIO values with all of the inherent error checking, critical +//! sectioning, and general safety. +//! +//! However, occasionally there is a need to write a GPIO value in an optimized +//! manner. These 3 macros will accomplish that. +//! +//! Note that the macros are named as lower-case counterparts to the +//! enumerations for the am_hal_gpio_state_read() function. That is: +//! +//! AM_HAL_GPIO_OUTPUT_CLEAR -> am_hal_gpio_output_clear(n,v) +//! AM_HAL_GPIO_OUTPUT_SET -> am_hal_gpio_output_set(n,v) +//! AM_HAL_GPIO_OUTPUT_TOGGLE -> am_hal_gpio_output_toggle(n,v) +//! AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE -> am_hal_gpio_output_tristate_disable(n,v) +//! AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE -> am_hal_gpio_output_tristate_enable(n,v) +//! AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE -> am_hal_gpio_output_toggle(n,v) +//! +//! @return None. +//! +//***************************************************************************** +// +// Note - these macros use byte-oriented addressing. +// +#define am_hal_gpio_output_clear(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, WTCA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_set(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, WTSA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_toggle(n) \ + if ( 1 ) \ + { \ + AM_CRITICAL_BEGIN \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, WTA) + (((uint32_t)(n) & 0x20) >> 3))))) ^= \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))); \ + AM_CRITICAL_END \ + } + +#define am_hal_gpio_output_tristate_disable(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, ENCA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_tristate_enable(n) \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, ENSA) + (((uint32_t)(n) & 0x20) >> 3))))) = \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))) + +#define am_hal_gpio_output_tristate_toggle(n) \ + if ( 1 ) \ + { \ + AM_CRITICAL_BEGIN \ + ((*((volatile uint32_t *) \ + ((AM_REGADDR(GPIO, ENA) + (((uint32_t)(n) & 0x20) >> 3))))) ^= \ + ((uint32_t) 0x1 << ((uint32_t)(n) % 32))); \ + AM_CRITICAL_END \ + } + + +//***************************************************************************** +//! +//! @brief Fast GPIO helper macros. +//! +//***************************************************************************** +// +// Define Fast GPIO enable and disable. +// +#define am_hal_gpio_fastgpio_enable(n) am_hal_gpio_output_tristate_enable(n) +#define am_hal_gpio_fastgpio_disable(n) am_hal_gpio_output_tristate_disable(n) + +// +// Macros for accessing Fast GPIO: set, clear, and read. +// The 'n' parameter is the pin number. +// Note - these macros are most efficient if 'n' is a constant value, and +// of course when compiled with -O3. +// +#define am_hal_gpio_fastgpio_read(n) ((APBDMA->BBINPUT >> (n & 0x7)) & 0x1) +#define am_hal_gpio_fastgpio_set(n) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_SET, (1 << (n & 0x7)))) +#define am_hal_gpio_fastgpio_clr(n) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, (1 << (n & 0x7)))) +#define am_hal_gpio_fastgpio_setmsk(m) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_SET, m)) +#define am_hal_gpio_fastgpio_clrmsk(m) (APBDMA->BBSETCLEAR = _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, m)) +#define am_hal_gpio_fastgpio_wrval(val) (APBDMA->BBSETCLEAR = \ + (_VAL2FLD(APBDMA_BBSETCLEAR_SET, val) | \ + _VAL2FLD(APBDMA_BBSETCLEAR_CLEAR, val ^ 0xFF))) + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_GPIO_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.c new file mode 100644 index 0000000000..a4e74c61d9 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.c @@ -0,0 +1,225 @@ +//***************************************************************************** +// +// am_hal_interrupt.c +//! @file +//! +//! @brief Helper functions supporting interrupts and NVIC operation. +//! +//! These functions may be used for NVIC-level interrupt configuration. +//! +//! @addtogroup interrupt3 Interrupt (ARM NVIC support functions) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Globally enable interrupt service routines +//! +//! This function allows interrupt signals from the NVIC to trigger ISR entry +//! in the CPU. This function must be called if interrupts are to be serviced +//! in software. +//! +//! @return 1 if interrupts were previously disabled, 0 otherwise. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm uint32_t +am_hal_interrupt_master_enable(void) +{ + mrs r0, PRIMASK + cpsie i + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless uint32_t +am_hal_interrupt_master_enable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsie i"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +//***************************************************************************** +// +//! @brief Globally disable interrupt service routines +//! +//! This function prevents interrupt signals from the NVIC from triggering ISR +//! entry in the CPU. This will effectively stop incoming interrupt sources +//! from triggering their corresponding ISRs. +//! +//! @note Any external interrupt signal that occurs while the master interrupt +//! disable is active will still reach the "pending" state in the NVIC, but it +//! will not be allowed to reach the "active" state or trigger the +//! corresponding ISR. Instead, these interrupts are essentially "queued" until +//! the next time the master interrupt enable instruction is executed. At that +//! time, the interrupt handlers will be executed in order of decreasing +//! priority. +//! +//! @return 1 if interrupts were previously disabled, 0 otherwise. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm uint32_t +am_hal_interrupt_master_disable(void) +{ + mrs r0, PRIMASK + cpsid i + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +uint32_t __attribute__((naked)) +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless uint32_t +am_hal_interrupt_master_disable(void) +{ + __asm(" mrs r0, PRIMASK"); + __asm(" cpsid i"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +//***************************************************************************** +// +//! @brief Sets the master interrupt state based on the input. +//! +//! @param ui32InterruptState - Desired PRIMASK value. +//! +//! This function directly writes the PRIMASK register in the ARM core. A value +//! of 1 will disable interrupts, while a value of zero will enable them. +//! +//! This function may be used along with am_hal_interrupt_master_disable() to +//! implement a nesting critical section. To do this, call +//! am_hal_interrupt_master_disable() to start the critical section, and save +//! its return value. To complete the critical section, call +//! am_hal_interrupt_master_set() using the saved return value as \e +//! ui32InterruptState. This will safely restore PRIMASK to the value it +//! contained just before the start of the critical section. +//! +//! @return None. +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +__asm void +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + msr PRIMASK, r0 + bx lr +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +void __attribute__((naked)) +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#elif defined(__GNUC_STDC_INLINE__) +void __attribute__((naked)) +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing + // return statement on a non-void function +__stackless void +am_hal_interrupt_master_set(uint32_t ui32InterruptState) +{ + __asm(" msr PRIMASK, r0"); + __asm(" bx lr"); +} +#pragma diag_default = Pe940 // Restore IAR compiler warning +#endif + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.h new file mode 100644 index 0000000000..148e046fda --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_interrupt.h @@ -0,0 +1,84 @@ +//***************************************************************************** +// +// am_hal_interrupt.h +//! @file +//! +//! @brief Helper functions supporting interrupts and NVIC operation. +//! +//! These functions may be used for NVIC-level interrupt configuration. +//! +//! @addtogroup interrupt3 Interrupt (ARM NVIC support functions) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_INTERRUPT_H +#define AM_HAL_INTERRUPT_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Define the last peripheral interrupt as AM_HAL_INTERRUPT_MAX. +// The total number of interrupts in the vector table is therefore +// (AM_HAL_INTERRUPT_MAX + 1 + 16). +// +#define AM_HAL_INTERRUPT_MAX (CLKGEN_IRQn) + +extern uint32_t am_hal_interrupt_master_disable(void); +extern uint32_t am_hal_interrupt_master_enable(void); +extern void am_hal_interrupt_master_set(uint32_t ui32InterruptState); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_INTERRUPT_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.c new file mode 100644 index 0000000000..191296ff52 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.c @@ -0,0 +1,3752 @@ +//***************************************************************************** +// +// am_hal_iom.c +//! @file +//! +//! @brief Functions for interfacing with IO Master serial (SPI/I2C) modules. +//! +//! @addtogroup iom3 IO Master (SPI/I2C) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __IAR_SYSTEMS_ICC__ +#define AM_INSTR_CLZ(n) __CLZ(n) +#else +#define AM_INSTR_CLZ(n) __builtin_clz(n) +#endif + +#define MANUAL_POP 0 + +#define AM_HAL_MAGIC_IOM 0x123456 +#define AM_HAL_IOM_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_IOM)) + +// For IOM - Need to clear the flag for unpausing +#define AM_HAL_IOM_SC_PAUSE_CQ AM_HAL_IOM_SC_PAUSE(AM_HAL_IOM_PAUSE_FLAG_CQ) +#define AM_HAL_IOM_SC_PAUSE_SEQLOOP AM_HAL_IOM_SC_PAUSE(AM_HAL_IOM_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_IOM_SC_UNPAUSE_CQ AM_HAL_IOM_SC_UNPAUSE(AM_HAL_IOM_PAUSE_FLAG_CQ) +#define AM_HAL_IOM_SC_UNPAUSE_SEQLOOP AM_HAL_IOM_SC_UNPAUSE(AM_HAL_IOM_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_IOM_SC_PAUSE_BLOCK AM_HAL_IOM_SC_PAUSE(AM_HAL_IOM_PAUSE_FLAG_BLOCK) +#define AM_HAL_IOM_SC_UNPAUSE_BLOCK AM_HAL_IOM_SC_UNPAUSE(AM_HAL_IOM_PAUSE_FLAG_BLOCK) + +// Max time to wait when attempting to pause the command queue +#define AM_HAL_IOM_MAX_PAUSE_DELAY (100*1000) // 100ms + +//***************************************************************************** +// +// IOM interface clock selections +// +//***************************************************************************** +#define AM_REG_IOM_CLKCFG_FSEL_MIN_PWR 0x00000000 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC 0x00000100 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV2 0x00000200 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV4 0x00000300 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV8 0x00000400 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV16 0x00000500 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV32 0x00000600 +#define AM_REG_IOM_CLKCFG_FSEL_HFRC_DIV64 0x00000700 + +// +// Only keep IOM interrupts we're interested in +// +// Necessary interrupts for respective modes +// For CQ - we rely only on the CQUPD interrupt +#define AM_HAL_IOM_INT_CQMODE (AM_HAL_IOM_INT_CQUPD | AM_HAL_IOM_INT_ERR) +// Need both CMDCMP & DCMP, as for Read we need to wait for DCMP after CMDCMP +#define AM_HAL_IOM_INT_DMAMODE (AM_HAL_IOM_INT_CMDCMP | AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_ERR) + +// Configures the interrupts to provided coniguration - clearing all pending interrupts +#define IOM_SET_INTEN(ui32Module, intCfg) \ + do \ + { \ + IOMn(ui32Module)->INTEN = 0; \ + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; \ + IOMn(ui32Module)->INTEN = (intCfg); \ + } while (0); + + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** + +// +// Command Queue entry structure. +// +typedef struct +{ +#if (AM_HAL_IOM_CQ == 1) + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; +#endif + uint32_t ui32OFFSETHIAddr; + uint32_t ui32OFFSETHIVal; + uint32_t ui32DEVCFGAddr; + uint32_t ui32DEVCFGVal; + uint32_t ui32DMACFGdis1Addr; + uint32_t ui32DMACFGdis1Val; + uint32_t ui32DMATOTCOUNTAddr; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMATARGADDRAddr; + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMACFGAddr; + uint32_t ui32DMACFGVal; + // CMDRPT register has been repurposed for DCX + uint32_t ui32DCXAddr; + uint32_t ui32DCXVal; + uint32_t ui32CMDAddr; + uint32_t ui32CMDVal; +#if (AM_HAL_IOM_CQ == 1) + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +#endif +} am_hal_iom_txn_cmdlist_t; + +// +// Command Queue entry structure for Sequence Repeat +// +typedef struct +{ + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +} am_hal_iom_cq_loop_entry_t; + +#define AM_HAL_IOM_MAX_PENDING_TRANSACTIONS 256 // Must be power of 2 for the implementation below +#define AM_HAL_IOM_CQUPD_INT_FLAG (0x00000001) + +typedef struct +{ + bool bValid; + uint32_t regFIFOTHR; + uint32_t regDMATRIGEN; + uint32_t regCLKCFG; + uint32_t regSUBMODCTRL; + uint32_t regCQCFG; + uint32_t regCQADDR; + uint32_t regCQFLAGS; + uint32_t regCQPAUSEEN; + uint32_t regCQCURIDX; + uint32_t regCQENDIDX; + uint32_t regMSPICFG; + uint32_t regMI2CCFG; + uint32_t regINTEN; +} am_hal_iom_register_state_t; + +typedef enum +{ + AM_HAL_IOM_SEQ_NONE, + AM_HAL_IOM_SEQ_UNDER_CONSTRUCTION, + AM_HAL_IOM_SEQ_RUNNING, +} am_hal_iom_seq_e; + +typedef struct +{ + uint32_t ui32OFFSETHIVal; + uint32_t ui32DEVCFGVal; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMACFGVal; + uint32_t ui32CMDVal; + am_hal_iom_callback_t pfnCallback; + void *pCallbackCtxt; +} am_hal_iom_dma_entry_t; + +typedef struct +{ + am_hal_handle_prefix_t prefix; + // + // Physical module number. + // + uint32_t ui32Module; + + // + // Interface mode (SPI or I2C). + // + am_hal_iom_mode_e eInterfaceMode; + uint32_t *pNBTxnBuf; + uint32_t ui32NBTxnBufLength; + + uint32_t ui32UserIntCfg; + uint32_t ui32TxnInt; + + uint32_t ui32LastIdxProcessed; + uint32_t ui32MaxTransactions; + volatile uint32_t ui32NumPendTransactions; + // + // Stores the CQ callbacks. + // + am_hal_iom_callback_t pfnCallback[AM_HAL_IOM_MAX_PENDING_TRANSACTIONS]; + void *pCallbackCtxt[AM_HAL_IOM_MAX_PENDING_TRANSACTIONS]; +#if (AM_HAL_IOM_CQ == 1) + void *pCmdQHdl; + // To support sequence + am_hal_iom_seq_e eSeq; + bool bAutonomous; + // This is used to track the number of transactions in a sequence + uint32_t ui32NumSeqTransactions; + volatile bool bRestart; + uint32_t block; + // To support high priority transactions - out of band + // High Priority DMA transactions + volatile bool bHP; + uint32_t ui32NumHPEntries; + uint32_t ui32NumHPPendingEntries; + uint32_t ui32MaxHPTransactions; + uint32_t ui32NextHPIdx; + uint32_t ui32LastHPIdxProcessed; + am_hal_iom_dma_entry_t *pHPTransactions; + // Max pending transactions based on NB Buffer size + uint32_t ui32MaxPending; + // Number of back to back transactions with no callbacks + uint32_t ui32NumUnSolicited; +#else + uint32_t ui32NextIdx; + am_hal_iom_txn_cmdlist_t *pTransactions; +#endif + // + // Delay timeout value. + // + uint32_t waitTimeout; + // Configured clock time + uint32_t ui32BitTimeTicks; + + am_hal_iom_register_state_t registerState; + uint8_t dcx[AM_HAL_IOM_MAX_CS_SPI + 1]; + +} am_hal_iom_state_t; + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +am_hal_iom_state_t g_IOMhandles[AM_REG_IOM_NUM_MODULES]; +//***************************************************************************** +// +// Internal Functions. +// +//***************************************************************************** +static uint32_t +get_pause_val(am_hal_iom_state_t *pIOMState, uint32_t pause) +{ + uint32_t retval; + switch (pIOMState->block) + { + case 1: + // Pause the CQ till the whole block is built + retval = pause | AM_HAL_IOM_CQP_PAUSE_DEFAULT | AM_HAL_IOM_PAUSE_FLAG_BLOCK; + pIOMState->block = 2; + break; + case 2: + // No pausing allowed + retval = AM_HAL_IOM_PAUSE_DEFAULT; + break; + default: // case 0 + retval = pause | AM_HAL_IOM_CQP_PAUSE_DEFAULT; + } + return retval; +} + +//***************************************************************************** +// +// Function to build the CMD value. +// Returns the CMD value, but does not set the CMD register. +// +// The OFFSETHI register must still be handled by the caller, e.g. +// AM_REGn(IOM, ui32Module, OFFSETHI) = (uint16_t)(ui32Offset >> 8); +// +//***************************************************************************** +static uint32_t +build_cmd(uint32_t ui32CS, uint32_t ui32Dir, uint32_t ui32Cont, + uint32_t ui32Offset, uint32_t ui32OffsetCnt, + uint32_t ui32nBytes) +{ + // + // Initialize the CMD variable + // + uint32_t ui32Cmd = 0; + + // + // If SPI, we'll need the chip select + // + ui32Cmd |= _VAL2FLD(IOM0_CMD_CMDSEL, ui32CS); + + // + // Build the CMD with number of bytes and direction. + // + ui32Cmd |= _VAL2FLD(IOM0_CMD_TSIZE, ui32nBytes); + + if (ui32Dir == AM_HAL_IOM_RX) + { + ui32Cmd |= _VAL2FLD(IOM0_CMD_CMD, IOM0_CMD_CMD_READ); + } + else + { + ui32Cmd |= _VAL2FLD(IOM0_CMD_CMD, IOM0_CMD_CMD_WRITE); + } + + ui32Cmd |= _VAL2FLD(IOM0_CMD_CONT, ui32Cont); + + // + // Now add the OFFSETLO and OFFSETCNT information. + // + ui32Cmd |= _VAL2FLD(IOM0_CMD_OFFSETLO, (uint8_t)ui32Offset); + ui32Cmd |= _VAL2FLD(IOM0_CMD_OFFSETCNT, ui32OffsetCnt); + + return ui32Cmd; +} // build_cmd() + +//***************************************************************************** +// +// Function to build CMD lists. +// +//***************************************************************************** +static void +build_txn_cmdlist(am_hal_iom_state_t *pIOMState, + am_hal_iom_txn_cmdlist_t *pCQEntry, + am_hal_iom_transfer_t *psTransaction) +{ + uint32_t ui32Cmd; + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t ui32Dir = psTransaction->eDirection; + uint32_t ui32SRAMAddress; + + // + // Command for OFFSETHI + // + pCQEntry->ui32OFFSETHIAddr = (uint32_t)&IOMn(ui32Module)->OFFSETHI; + + pCQEntry->ui32OFFSETHIVal = (uint16_t)(psTransaction->ui32Instr >> 8); + + // + // Command for I2C DEVADDR field in DEVCFG + // + pCQEntry->ui32DEVCFGAddr = (uint32_t)&IOMn(ui32Module)->DEVCFG; + pCQEntry->ui32DEVCFGVal = _VAL2FLD(IOM0_DEVCFG_DEVADDR, psTransaction->uPeerInfo.ui32I2CDevAddr); + + // + // Command to disable DMA before writing TOTCOUNT. + // + pCQEntry->ui32DMACFGdis1Addr = (uint32_t)&IOMn(ui32Module)->DMACFG; + pCQEntry->ui32DMACFGdis1Val = 0x0; + + // + // Command to set DMATOTALCOUNT + // + pCQEntry->ui32DMATOTCOUNTAddr = (uint32_t)&IOMn(ui32Module)->DMATOTCOUNT; + pCQEntry->ui32DMATOTCOUNTVal = psTransaction->ui32NumBytes; + + // + // Command to set DMATARGADDR + // + pCQEntry->ui32DMATARGADDRAddr = (uint32_t)&IOMn(ui32Module)->DMATARGADDR; + ui32SRAMAddress = (ui32Dir == AM_HAL_IOM_TX) ? (uint32_t)psTransaction->pui32TxBuffer : (uint32_t)psTransaction->pui32RxBuffer; + pCQEntry->ui32DMATARGADDRVal = ui32SRAMAddress; + + // + // Command to set DMACFG to start the DMA operation + // + pCQEntry->ui32DMACFGAddr = (uint32_t)&IOMn(ui32Module)->DMACFG; + pCQEntry->ui32DMACFGVal = + _VAL2FLD(IOM0_DMACFG_DMAPRI, psTransaction->ui8Priority) | + _VAL2FLD(IOM0_DMACFG_DMADIR, ui32Dir == AM_HAL_IOM_TX ? 1 : 0); + + if (psTransaction->ui32NumBytes) + { + pCQEntry->ui32DMACFGVal |= IOM0_DMACFG_DMAEN_Msk; + } + + // CMDRPT register has been repurposed for DCX + pCQEntry->ui32DCXAddr = (uint32_t)&IOMn(ui32Module)->DCX; + pCQEntry->ui32DCXVal = (pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? pIOMState->dcx[psTransaction->uPeerInfo.ui32SpiChipSelect] : 0; + // + // Command to start the transfer. + // + ui32Cmd = pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE ? + psTransaction->uPeerInfo.ui32SpiChipSelect : 0; + ui32Cmd = build_cmd(ui32Cmd, // ChipSelect + ui32Dir, // ui32Dir + psTransaction->bContinue, // ui32Cont + psTransaction->ui32Instr, // ui32Offset + psTransaction->ui32InstrLen, // ui32OffsetCnt + psTransaction->ui32NumBytes); // ui32Bytes + + pCQEntry->ui32CMDAddr = (uint32_t)&IOMn(ui32Module)->CMD; + pCQEntry->ui32CMDVal = ui32Cmd; + +#if (AM_HAL_IOM_CQ == 1) + pCQEntry->ui32PAUSENAddr = pCQEntry->ui32PAUSEN2Addr = (uint32_t)&IOMn(ui32Module)->CQPAUSEEN; + pCQEntry->ui32PAUSEEN2Val = AM_HAL_IOM_PAUSE_DEFAULT; + pCQEntry->ui32PAUSEENVal = get_pause_val(pIOMState, psTransaction->ui32PauseCondition); + pCQEntry->ui32SETCLRVal = psTransaction->ui32StatusSetClr; + pCQEntry->ui32SETCLRAddr = (uint32_t)&IOMn(ui32Module)->CQSETCLEAR; +#endif +} // build_txn_cmdlist() + +//***************************************************************************** +// +// enable_submodule() - Utilizes the built-in fields that indicate whether which +// submodule is supported, then enables that submodule. +// +// Input: ui32Type = 0, set for SPI. +// ui32Type = 1, set for I2C. +// +//***************************************************************************** +static void +enable_submodule(uint32_t ui32Module, uint32_t ui32Type) +{ + if ( IOMn(ui32Module)->SUBMODCTRL_b.SMOD0TYPE == ui32Type ) + { + IOMn(ui32Module)->SUBMODCTRL = + _VAL2FLD(IOM0_SUBMODCTRL_SMOD1EN, 0) | + _VAL2FLD(IOM0_SUBMODCTRL_SMOD0EN, 1); + } + else + { + IOMn(ui32Module)->SUBMODCTRL = + _VAL2FLD(IOM0_SUBMODCTRL_SMOD1EN, 1) | + _VAL2FLD(IOM0_SUBMODCTRL_SMOD0EN, 0); + } +} // enable_submodule() + +//***************************************************************************** +// +// Error handling. +// +//***************************************************************************** +uint32_t +internal_iom_get_int_err(uint32_t ui32Module, uint32_t ui32IntStatus) +{ + // + // Map the INTSTAT bits for transaction status + // + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + // + // Let's accumulate the errors + // + ui32IntStatus |= IOMn(ui32Module)->INTSTAT; + + if (ui32IntStatus & AM_HAL_IOM_INT_SWERR) + { + // Error in hardware command issued or illegal access by SW + ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_I2CARBERR) + { + // Loss of I2C multi-master arbitration + ui32Status = AM_HAL_IOM_ERR_I2C_ARB; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_NAK) + { + // I2C NAK + ui32Status = AM_HAL_IOM_ERR_I2C_NAK; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_INTERR) + { + // Other Error + ui32Status = AM_HAL_STATUS_FAIL; + } + + return ui32Status; + +} // internal_iom_get_int_err() + +static void +internal_iom_reset_on_error(am_hal_iom_state_t *pIOMState, uint32_t ui32IntMask) +{ + uint32_t iterationsToWait = 2 * pIOMState->ui32BitTimeTicks; // effectively > 6 clocks + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t curIntCfg = IOMn(ui32Module)->INTEN; + IOMn(ui32Module)->INTEN = 0; + + // Disable interrupts temporarily + if (ui32IntMask & AM_HAL_IOM_INT_DERR) + { + if ((IOMn(ui32Module)->DMACFG & IOM0_DMACFG_DMADIR_Msk) == _VAL2FLD(IOM0_DMACFG_DMADIR, IOM0_DMACFG_DMADIR_M2P)) + { + // Write + uint32_t dummy = 0xDEADBEEF; + uint32_t numBytesRemaining = IOMn(ui32Module)->DMATOTCOUNT; + + while (numBytesRemaining) + { + if (IOMn(ui32Module)->FIFOPTR_b.FIFO0REM >= 4) + { + // Write one 4-byte word to FIFO + IOMn(ui32Module)->FIFOPUSH = dummy; + if (numBytesRemaining > 4) + { + numBytesRemaining -= 4; + } + else + { + break; + } + } + } + // Now wait for command to finish + while ((IOMn(ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk); + } + else + { + // Read + // Let command finish + while (IOMn(ui32Module)->STATUS_b.CMDACT) + { + while (IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ >= 4) + { + // Read one 4-byte word from FIFO + IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + } + } + // Now wait for command to finish + while ((IOMn(ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk); + // Flush any remaining data from FIFO + while (IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ) + { + while (IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ >= 4) + { + // Read one 4-byte word from FIFO + IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + } + } + } + } + if (ui32IntMask & AM_HAL_IOM_INT_NAK) + { + // + // Wait for Idle + // + while ((IOMn(ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk); + + // + // Reset Submodule & FIFO + // + // Disable the submodules + // + IOMn(ui32Module)->SUBMODCTRL_b.SMOD1EN = 0; + // Reset Fifo + IOMn(ui32Module)->FIFOCTRL_b.FIFORSTN = 0; + + // Wait for few IO clock cycles + am_hal_flash_delay(iterationsToWait); + + IOMn(ui32Module)->FIFOCTRL_b.FIFORSTN = 1; + + // Enable submodule + IOMn(ui32Module)->SUBMODCTRL_b.SMOD1EN = 1; + } + + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + + // Restore interrupts + IOMn(ui32Module)->INTEN = curIntCfg; +} + +//***************************************************************************** +// compute_freq() +//***************************************************************************** +// +// Compute the interface frequency based on the given parameters +// +static uint32_t +compute_freq(uint32_t ui32HFRCfreqHz, + uint32_t ui32Fsel, uint32_t ui32Div3, + uint32_t ui32DivEn, uint32_t ui32TotPer) +{ + uint32_t ui32Denomfinal, ui32ClkFreq; + + ui32Denomfinal = ((1 << (ui32Fsel - 1)) * (1 + ui32Div3 * 2) * (1 + ui32DivEn * (ui32TotPer))); + ui32ClkFreq = (ui32HFRCfreqHz) / ui32Denomfinal; // Compute the set frequency value + ui32ClkFreq += (((ui32HFRCfreqHz) % ui32Denomfinal) > (ui32Denomfinal / 2)) ? 1 : 0; + + return ui32ClkFreq; +} // compute_freq() + +//***************************************************************************** +// onebit() +//***************************************************************************** +// +// A power of 2? +// Return true if ui32Value has exactly 1 bit set, otherwise false. +// +static bool +onebit(uint32_t ui32Value) +{ + return ui32Value && !(ui32Value & (ui32Value - 1)); +} // onebit() + +//***************************************************************************** +// +// iom_get_interface_clock_cfg() +// +// Returns the proper settings for the CLKCFG register. +// +// ui32FreqHz - The desired interface frequency in Hz. +// +// Given a desired serial interface clock frequency, this function computes +// the appropriate settings for the various fields in the CLKCFG register +// and returns the 32-bit value that should be written to that register. +// The actual interface frequency may be slightly lower than the specified +// frequency, but the actual frequency is also returned. +// +// Note A couple of criteria that this algorithm follow are: +// 1. For power savings, choose the highest FSEL possible. +// 2. Use DIV3 when possible rather than DIVEN. +// +// Return An unsigned 64-bit value. +// The lower 32-bits represent the value to use to set CLKCFG. +// The upper 32-bits represent the actual frequency (in Hz) that will result +// from setting CLKCFG with the lower 32-bits. +// +// 0 (64 bits) = error. Note that the caller must check the entire 64 bits. +// It is not an error if only the low 32-bits are 0 (this is a valid value). +// But the entire 64 bits returning 0 is an error. +//! +//***************************************************************************** +static +uint64_t iom_get_interface_clock_cfg(uint32_t ui32FreqHz, uint32_t ui32Phase ) +{ + uint32_t ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer, ui32LowPer; + uint32_t ui32Denom, ui32v1, ui32Denomfinal, ui32ClkFreq, ui32ClkCfg; + uint32_t ui32HFRCfreqHz; + int32_t i32Div, i32N; + + if ( ui32FreqHz == 0 ) + { + return 0; + } + + // + // Set the HFRC clock frequency. + // + ui32HFRCfreqHz = AM_HAL_CLKGEN_FREQ_MAX_HZ; + + // + // Compute various parameters used for computing the optimal CLKCFG setting. + // + i32Div = (ui32HFRCfreqHz / ui32FreqHz) + ((ui32HFRCfreqHz % ui32FreqHz) ? 1 : 0); // Round up (ceiling) + + // + // Compute N (count the number of LS zeros of Div) = ctz(Div) = log2(Div & (-Div)) + // + i32N = 31 - AM_INSTR_CLZ((i32Div & (-i32Div))); + + if ( i32N > 6 ) + { + i32N = 6; + } + + ui32Div3 = ( (ui32FreqHz < (ui32HFRCfreqHz / 16384)) || + ( ((ui32FreqHz >= (ui32HFRCfreqHz / 3)) && + (ui32FreqHz <= ((ui32HFRCfreqHz / 2) - 1)) ) ) ) ? 1 : 0; + ui32Denom = ( 1 << i32N ) * ( 1 + (ui32Div3 * 2) ); + ui32TotPer = i32Div / ui32Denom; + ui32TotPer += (i32Div % ui32Denom) ? 1 : 0; + ui32v1 = 31 - AM_INSTR_CLZ(ui32TotPer); // v1 = log2(TotPer) + ui32Fsel = (ui32v1 > 7) ? ui32v1 + i32N - 7 : i32N; + ui32Fsel++; + + if ( ui32Fsel > 7 ) + { + // + // This is an error, can't go that low. + // + return 0; + } + + if ( ui32v1 > 7 ) + { + ui32DivEn = ui32TotPer; // Save TotPer for the round up calculation + ui32TotPer = ui32TotPer>>(ui32v1-7); + ui32TotPer += ((ui32DivEn) % (1 << (ui32v1 - 7))) ? 1 : 0; + } + + ui32DivEn = ( (ui32FreqHz >= (ui32HFRCfreqHz / 4)) || + ((1 << (ui32Fsel - 1)) == i32Div) ) ? 0 : 1; + + if (ui32Phase == 1) + { + ui32LowPer = (ui32TotPer - 2) / 2; // Longer high phase + } + else + { + ui32LowPer = (ui32TotPer - 1) / 2; // Longer low phase + } + + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_FSEL, ui32Fsel) | + _VAL2FLD(IOM0_CLKCFG_DIV3, ui32Div3) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, ui32DivEn) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, ui32LowPer) | + _VAL2FLD(IOM0_CLKCFG_TOTPER, ui32TotPer - 1); + + // + // Now, compute the actual frequency, which will be returned. + // + ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer - 1); + + // + // Determine if the actual frequency is a power of 2 (MHz). + // + if ( (ui32ClkFreq % 250000) == 0 ) + { + // + // If the actual clock frequency is a power of 2 ranging from 250KHz up, + // we can simplify the CLKCFG value using DIV3 (which also results in a + // better duty cycle). + // + ui32Denomfinal = ui32ClkFreq / (uint32_t)250000; + + if ( onebit(ui32Denomfinal) ) + { + // + // These configurations can be simplified by using DIV3. Configs + // using DIV3 have a 50% duty cycle, while those from DIVEN will + // have a 66/33 duty cycle. + // + ui32TotPer = ui32LowPer = ui32DivEn = 0; + ui32Div3 = 1; + + // + // Now, compute the return values. + // + ui32ClkFreq = compute_freq(ui32HFRCfreqHz, ui32Fsel, ui32Div3, ui32DivEn, ui32TotPer); + + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_FSEL, ui32Fsel) | + _VAL2FLD(IOM0_CLKCFG_DIV3, 1) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, 0) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0) | + _VAL2FLD(IOM0_CLKCFG_TOTPER, 0); + } + } + + return ( ((uint64_t)ui32ClkFreq) << 32) | (uint64_t)ui32ClkCfg; + +} //iom_get_interface_clock_cfg() + +#if (AM_HAL_IOM_CQ == 1) +//***************************************************************************** +// +//! @brief Initializes the IOM Command Queue. +//! +//! @param handle - handle for the interface. +//! @param ui32Length - length of the SRAM Command Queue buffer in words. +//! @param pTCB - pointer to the SRAM to use for the Command Queue. +//! +//! This function initializes the global command queue structure. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +uint32_t +am_hal_iom_CQInit(void *pHandle, uint32_t ui32Length, + uint32_t *pTCB) +{ + am_hal_cmdq_cfg_t cqCfg; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + pIOMState->pCmdQHdl = NULL; + pIOMState->ui32MaxTransactions = 0; + pIOMState->ui32NumUnSolicited = 0; + + cqCfg.pCmdQBuf = pTCB; + cqCfg.cmdQSize = ui32Length / 2; + cqCfg.priority = AM_HAL_CMDQ_PRIO_HI; + ui32Status = am_hal_cmdq_init((am_hal_cmdq_if_e)(AM_HAL_CMDQ_IF_IOM0 + ui32Module), + &cqCfg, &pIOMState->pCmdQHdl); + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + pIOMState->ui32MaxTransactions = AM_HAL_IOM_MAX_PENDING_TRANSACTIONS; + } + return ui32Status; +} // am_hal_iom_CQInit() + +//***************************************************************************** +// +//! @brief Resets the IOM Command Queue. +//! +//! @param ui32Module - IOM instance. +//! +//! This function resets the global command queue structure. +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_IOM_CQReset(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + + if (pIOMState->pCmdQHdl) + { + am_hal_cmdq_term(pIOMState->pCmdQHdl, true); + pIOMState->pCmdQHdl = NULL; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_IOM_CQReset() + +//***************************************************************************** +// +//! @brief Adds a transaction the IOM Command Queue. +//! +//! @param handle - handle for the interface. +//! @param pTransaction - transaction to add to the CQ +//! @param pfnCallback - pointer the callback function to be executed when +//! transaction is complete. +//! +//! This function copies data from the IOM FIFO into the array \e pui32Data. +//! This is how input data from SPI or I2C transactions may be retrieved. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_CQAddTransaction(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + am_hal_iom_txn_cmdlist_t *pCQEntry; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + + // + // Check to see if there is enough room in the CQ + // + if ((pIOMState->ui32NumPendTransactions == AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) || + (am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, sizeof(am_hal_iom_txn_cmdlist_t) / 8, &pCQBlock, &index))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQEntry = (am_hal_iom_txn_cmdlist_t *)pCQBlock; + + + build_txn_cmdlist(pIOMState, pCQEntry, psTransaction); + + // + // Will resume here after DMA completes. + // + + // + // Because we set AM_HAL_IOM_CQUPD_INT_FLAG, an interrupt will occur once + // we reach this point in the Command Queue. In the service routine, we'll + // look for the appropriate callback. + // + // If ENDIDX has been reached, the CQ will pause here. Otherwise will + // continue with the next CQ entry. + // + + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pfnCallback; + pIOMState->pCallbackCtxt[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pCallbackCtxt; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_iom_CQAddTransaction() + +//***************************************************************************** +// +//! @brief Enable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function enables Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_CQEnable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + + if (0 == pIOMState->ui32NumPendTransactions) + { + uint32_t *pCqAddr = (uint32_t *)IOMn(pIOMState->ui32Module)->CQADDR; + // When CQ is enabled with nothing there - it always executes the first command + // insert dummy command + *pCqAddr = (uint32_t) &IOMn(pIOMState->ui32Module)->CQADDR; + *(pCqAddr + 1) = (uint32_t)pCqAddr; + } + // + // Enable the Command Queue operation + // + return am_hal_cmdq_enable(pIOMState->pCmdQHdl); + +} // am_hal_iom_CQEnable() + +//***************************************************************************** +// +//! @brief Disable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function disables the Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_CQDisable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + + // + // Disable the Command Queue operation + // + return am_hal_cmdq_disable(pIOMState->pCmdQHdl); +} // am_hal_iom_CQDisable() + +static void iom_dummy_callback(void *pCallbackCtxt, uint32_t status) +{ + // Dummy - Do nothing +} + +static void iom_seq_loopback(void *pCallbackCtxt, uint32_t status) +{ + // Reset the state to allow serving callbacks for next set + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pCallbackCtxt; + pIOMState->ui32NumPendTransactions = pIOMState->ui32NumSeqTransactions + 1; + pIOMState->ui32LastIdxProcessed = 0; + pIOMState->bRestart = true; + // Now resume the CQ - to finish loopback + // Resume the CQ + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_SEQLOOP; +} + +static uint32_t iom_cq_pause(am_hal_iom_state_t *pIOMState) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32usMaxDelay = AM_HAL_IOM_MAX_PAUSE_DELAY; + // Pause the CQ + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_PAUSE_CQ; + // It is possible that CQ is disabled once the last transaction is processed + while ( IOMn(pIOMState->ui32Module)->CQCFG_b.CQEN ) + { + // Need to make sure we're paused at a designated pause point + if ( IOMn(pIOMState->ui32Module)->CQSTAT_b.CQPAUSED && (IOMn(pIOMState->ui32Module)->CQPAUSEEN & AM_HAL_IOM_PAUSE_FLAG_CQ) ) + { + break; + } + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + return AM_HAL_STATUS_TIMEOUT; + } + } + if (status == AM_HAL_STATUS_SUCCESS) + { + // Now that CQ is guaranteed to not progress further - we need to still wait in case the current CQ entry + // resulted in a DMA state....need to make sure we finish the current DMA + status = am_hal_flash_delay_status_check(AM_HAL_IOM_MAX_PAUSE_DELAY, + (uint32_t)&IOMn(pIOMState->ui32Module)->DMASTAT, + IOM0_DMASTAT_DMATIP_Msk, + _VAL2FLD(IOM0_DMASTAT_DMATIP, 0), + true); + + } + return status; +} + +static void +program_dma(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + uint32_t ui32Module = pIOMState->ui32Module; + uint32_t index = (pIOMState->ui32LastHPIdxProcessed + 1) % pIOMState->ui32MaxHPTransactions; + am_hal_iom_dma_entry_t *pDMAEntry = &pIOMState->pHPTransactions[index]; + + // + // OFFSETHI + // + IOMn(ui32Module)->OFFSETHI = pDMAEntry->ui32OFFSETHIVal; + + // + // I2C DEVADDR field in DEVCFG + // + IOMn(ui32Module)->DEVCFG = pDMAEntry->ui32DEVCFGVal; + + // + // disable DMA before writing TOTCOUNT. + // + IOMn(ui32Module)->DMACFG = 0x0; + + // + // set DMATOTALCOUNT + // + IOMn(ui32Module)->DMATOTCOUNT = pDMAEntry->ui32DMATOTCOUNTVal; + + // + // set DMATARGADDR + // + IOMn(ui32Module)->DMATARGADDR = pDMAEntry->ui32DMATARGADDRVal; + + // + // Command to set DMACFG to start the DMA operation + // + IOMn(ui32Module)->DMACFG = pDMAEntry->ui32DMACFGVal; + // + // Command to start the transfer. + // + IOMn(ui32Module)->CMD = pDMAEntry->ui32CMDVal; +} + +static uint32_t +sched_hiprio(am_hal_iom_state_t *pIOMState, uint32_t numTrans) +{ + uint32_t ui32NumPend; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pIOMState->ui32NumHPEntries; + pIOMState->ui32NumHPEntries += numTrans; + + // + // End the critical section. + // + AM_CRITICAL_END + + + if (0 == ui32NumPend) + { + // Force CQ to Pause + ui32Status = iom_cq_pause(pIOMState); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + pIOMState->ui32TxnInt = 0; + // Clear & Enable DMACMP interrupt + IOMn(pIOMState->ui32Module)->INTCLR = AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP; + IOMn(pIOMState->ui32Module)->INTEN |= AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP; + pIOMState->bHP = true; + // + // Program the DMA + // + program_dma(pIOMState); + } + return ui32Status; +} + + +static uint32_t +iom_add_hp_transaction(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + am_hal_iom_dma_entry_t *pDMAEntry; + uint32_t ui32Dir = psTransaction->eDirection; + uint32_t ui32SRAMAddress; + + uint32_t index = pIOMState->ui32NextHPIdx % pIOMState->ui32MaxHPTransactions; + // + // Check to see if there is enough room in the queue + // + if ( pIOMState->ui32NumHPEntries == pIOMState->ui32MaxHPTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + ui32SRAMAddress = (ui32Dir == AM_HAL_IOM_TX) ? (uint32_t)psTransaction->pui32TxBuffer : (uint32_t)psTransaction->pui32RxBuffer; + pDMAEntry = &pIOMState->pHPTransactions[index]; + pDMAEntry->ui32OFFSETHIVal = (uint16_t)(psTransaction->ui32Instr >> 8); + pDMAEntry->ui32DEVCFGVal = _VAL2FLD(IOM0_DEVCFG_DEVADDR, psTransaction->uPeerInfo.ui32I2CDevAddr); + pDMAEntry->ui32DMATARGADDRVal = ui32SRAMAddress; + pDMAEntry->ui32DMATOTCOUNTVal = psTransaction->ui32NumBytes; + pDMAEntry->ui32DMACFGVal = + _VAL2FLD(IOM0_DMACFG_DMAPRI, psTransaction->ui8Priority) | + _VAL2FLD(IOM0_DMACFG_DMADIR, ui32Dir == AM_HAL_IOM_TX ? 1 : 0); + + if (psTransaction->ui32NumBytes) + { + pDMAEntry->ui32DMACFGVal |= IOM0_DMACFG_DMAEN_Msk; + } + // + // Command to start the transfer. + // + pDMAEntry->ui32CMDVal = build_cmd((pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? psTransaction->uPeerInfo.ui32SpiChipSelect : 0, // ChipSelect + ui32Dir, // ui32Dir + psTransaction->bContinue, // ui32Cont + psTransaction->ui32Instr, // ui32Offset + psTransaction->ui32InstrLen, // ui32OffsetCnt + psTransaction->ui32NumBytes); // ui32Bytes + + pDMAEntry->pfnCallback = pfnCallback; + pDMAEntry->pCallbackCtxt = pCallbackCtxt; + + pIOMState->ui32NextHPIdx++; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_iom_DmaAddTransaction() + +#else // AM_HAL_IOM_CQ != 1 +static void +run_txn_cmdlist(void *pCQEntry, uint32_t numEntries) +{ + uint32_t ix; + am_hal_cmdq_entry_t *pCmd = (am_hal_cmdq_entry_t *)pCQEntry; + + for ( ix = 0; ix < numEntries; ix++, pCmd++ ) + { + *((uint32_t *)pCmd->address) = pCmd->value; + } + +} // run_txn_cmdlist() + +//***************************************************************************** +// +//! @brief Adds a transaction the IOM Command Queue. +//! +//! @param handle - handle for the interface. +//! @param pTransaction - transaction to add to the CQ +//! @param pfnCallback - pointer the callback function to be executed when //! transaction is complete. +//! +//! This function copies data from the IOM FIFO into the array \e pui32Data. +//! This is how input data from SPI or I2C transactions may be retrieved. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +uint32_t +am_hal_iom_DmaAddTransaction(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + am_hal_iom_txn_cmdlist_t *pCQEntry; + uint32_t index = pIOMState->ui32NextIdx % pIOMState->ui32MaxTransactions; + + // + // Check to see if there is enough room in the queue + // + if ( pIOMState->ui32NumPendTransactions == pIOMState->ui32MaxTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQEntry = &pIOMState->pTransactions[index]; + + + build_txn_cmdlist(pIOMState, pCQEntry, psTransaction); + + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index] = pfnCallback; + pIOMState->pCallbackCtxt[index] = pCallbackCtxt; + pIOMState->ui32NextIdx++; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_DmaAddTransaction() +#endif // AM_HAL_IOM_CQ == 1 + +//***************************************************************************** +// +// validate_transaction() +// +//***************************************************************************** +uint32_t +validate_transaction(am_hal_iom_state_t *pIOMState, + am_hal_iom_transfer_t *psTransaction, + bool bBlocking) +{ + uint32_t ui32Offset, ui32OffsetCnt, ui32Dir, ui32Bytes; + + // Note - psTransaction is expected to be validated before calling. + //if ( !psTransaction ) + //{ + // return AM_HAL_STATUS_INVALID_ARG; + //} + + ui32Offset = psTransaction->ui32Instr; + ui32OffsetCnt = psTransaction->ui32InstrLen; + ui32Dir = psTransaction->eDirection; + ui32Bytes = psTransaction->ui32NumBytes; + + // + // Validate parameters + // + if ( (ui32OffsetCnt > AM_HAL_IOM_MAX_OFFSETSIZE) || + (ui32Offset & (0xFFFFFFFF << (ui32OffsetCnt*8))) || + (ui32Bytes && (ui32Dir != AM_HAL_IOM_TX) && (psTransaction->pui32RxBuffer == NULL)) || + (ui32Bytes && (ui32Dir != AM_HAL_IOM_RX) && (psTransaction->pui32TxBuffer == NULL)) || + ((pIOMState->eInterfaceMode == AM_HAL_IOM_I2C_MODE) && + (psTransaction->ui32NumBytes > AM_HAL_IOM_MAX_TXNSIZE_I2C)) || + ((pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) && + ((psTransaction->uPeerInfo.ui32SpiChipSelect > AM_HAL_IOM_MAX_CS_SPI) || + (psTransaction->ui32NumBytes > AM_HAL_IOM_MAX_TXNSIZE_SPI))) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (!bBlocking) + { +#if (AM_HAL_IOM_CQ != 1) + if (psTransaction->ui32PauseCondition != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (psTransaction->ui32StatusSetClr != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#else + if (psTransaction->ui32PauseCondition & AM_HAL_IOM_PAUSE_FLAG_RESV) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psTransaction->ui32StatusSetClr & AM_HAL_IOM_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif + } + + return AM_HAL_STATUS_SUCCESS; + +} // validate_transaction() + +//***************************************************************************** +// +// IOM uninitialize function +// +//***************************************************************************** +uint32_t +am_hal_iom_uninitialize(void *pHandle) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (pIOMState->prefix.s.bEnable) + { + am_hal_iom_disable(pHandle); + } + + pIOMState->prefix.s.bInit = false; + + // + // Return the status. + // + return status; + +} // am_hal_iom_uninitialize() + +//***************************************************************************** +// +// IOM initialization function +// +//***************************************************************************** +uint32_t +am_hal_iom_initialize(uint32_t ui32Module, void **ppHandle) +{ + // Compile time check to ensure ENTRY_SIZE macros are defined correctly + // incorrect definition will cause divide by 0 error at build time + am_ct_assert((sizeof(am_hal_iom_txn_cmdlist_t) + 8) == AM_HAL_IOM_CQ_ENTRY_SIZE); + am_ct_assert(sizeof(am_hal_iom_dma_entry_t) == AM_HAL_IOM_HIPRIO_ENTRY_SIZE); + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the module number + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if (ppHandle == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (g_IOMhandles[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + g_IOMhandles[ui32Module].prefix.s.bInit = true; + g_IOMhandles[ui32Module].prefix.s.bEnable = false; + g_IOMhandles[ui32Module].prefix.s.magic = AM_HAL_MAGIC_IOM; + + // + // Initialize the handle. + // + g_IOMhandles[ui32Module].ui32Module = ui32Module; + + // + // Return the handle. + // + *ppHandle = (void *)&g_IOMhandles[ui32Module]; + + // + // Return the status + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_initialize() + +//***************************************************************************** +// +// IOM enable function +// +//***************************************************************************** +uint32_t +am_hal_iom_enable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (pIOMState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // Enable submodule +#if 1 + enable_submodule(pIOMState->ui32Module, ((pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? 0 : 1)); +#endif + +#if MANUAL_POP + IOMn(pIOMState->ui32Module)->FIFOCTRL_b.POPWR = 1; +#endif + + // + // If Enable the Command Queue + // + if ( pIOMState->pNBTxnBuf ) + { + pIOMState->ui32NumPendTransactions = 0; + pIOMState->ui32LastIdxProcessed = 0; +#if (AM_HAL_IOM_CQ == 1) + // Initialize Flags used to force CQ Pause + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_CQ | AM_HAL_IOM_SC_PAUSE_SEQLOOP; + pIOMState->pHPTransactions = NULL; + pIOMState->bHP = false; + pIOMState->block = 0; + pIOMState->ui32NumHPPendingEntries = 0; + pIOMState->ui32NumHPEntries = 0; + pIOMState->eSeq = AM_HAL_IOM_SEQ_NONE; + pIOMState->ui32NumSeqTransactions = 0; + pIOMState->bAutonomous = true; + status = am_hal_iom_CQInit(pIOMState, + pIOMState->ui32NBTxnBufLength, + pIOMState->pNBTxnBuf); +#else + // Determine the maximum number of transactions based on the memory provided + pIOMState->ui32MaxTransactions = pIOMState->ui32NBTxnBufLength * 4 / sizeof(am_hal_iom_txn_cmdlist_t); + if (pIOMState->ui32MaxTransactions > 0) + { + if (pIOMState->ui32MaxTransactions > AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) + { + pIOMState->ui32MaxTransactions = AM_HAL_IOM_MAX_PENDING_TRANSACTIONS; + } + pIOMState->ui32NextIdx = pIOMState->ui32LastIdxProcessed + 1; + pIOMState->pTransactions = (am_hal_iom_txn_cmdlist_t *)pIOMState->pNBTxnBuf; + } +#endif + // Initialize the DMA Trigger Setting + // + // DMATRIG, set DTHREN and/or DCMDCMPEN. + // Note - it is recommended that DTHREN always be set. + // +#if 1 + IOMn(pIOMState->ui32Module)->DMATRIGEN = _VAL2FLD(IOM0_DMATRIGEN_DTHREN, 1); +#endif + } + + if (status == AM_HAL_STATUS_SUCCESS) + { + pIOMState->prefix.s.bEnable = true; + } + + // + // We're done, return the status. + // + return status; + +} // am_hal_iom_enable() + +//***************************************************************************** +// +// IOM disable function +// +//***************************************************************************** +uint32_t +am_hal_iom_disable(void *pHandle) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pIOMState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + + // Check if we have any pending transactions. + if (pIOMState->ui32NumPendTransactions) + { + return AM_HAL_STATUS_IN_USE; + } + + // + // Disable the submodules + // + IOMn(pIOMState->ui32Module)->SUBMODCTRL_b.SMOD0EN = 0; + IOMn(pIOMState->ui32Module)->SUBMODCTRL_b.SMOD1EN = 0; + +#if (AM_HAL_IOM_CQ == 1) + am_hal_IOM_CQReset(pHandle); +#endif + + pIOMState->prefix.s.bEnable = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_disable() + +//***************************************************************************** +// +// IOM get status function +// +//***************************************************************************** +uint32_t +am_hal_iom_status_get(void *pHandle, am_hal_iom_status_t *psStatus) +{ + uint32_t ui32Module, ui32IomStat; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!psStatus) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + + // + // Begin critical section while we gather status information. + // + AM_CRITICAL_BEGIN + + ui32IomStat = IOMn(ui32Module)->STATUS; + psStatus->bStatIdle = _FLD2VAL(IOM0_STATUS_IDLEST, ui32IomStat); + psStatus->bStatErr = _FLD2VAL(IOM0_STATUS_ERR, ui32IomStat); + psStatus->bStatCmdAct = _FLD2VAL(IOM0_STATUS_CMDACT, ui32IomStat); + + + // + // Return all the bitfields of DMASTAT. + // + psStatus->ui32DmaStat = IOMn(ui32Module)->DMASTAT; + + psStatus->ui32MaxTransactions = pIOMState->ui32MaxTransactions; + psStatus->ui32NumPendTransactions = pIOMState->ui32NumPendTransactions; + + // + // End the critical section. + // + AM_CRITICAL_END + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_status_get() + +//***************************************************************************** +// +// IOM enable interrupts function +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (ui32IntMask & AM_HAL_IOM_INT_THR) + { + return AM_HAL_STATUS_INVALID_ARG; // Threshold Interupt should not be used. + } + + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + // + // Set the interrupt enables according to the mask. + // + IOMn(ui32Module)->INTEN |= ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_enable() + +//***************************************************************************** +// +// IOM disable interrupts function +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + // + // Clear the interrupt enables according to the mask. + // + IOMn(ui32Module)->INTEN &= ~ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_disable() + +//***************************************************************************** +// +// IOM get interrupt status +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_status_get(void *pHandle, bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + uint32_t ui32IntStatus; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !pui32IntStatus ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + ui32IntStatus = IOMn(ui32Module)->INTSTAT; + + if ( bEnabledOnly ) + { + ui32IntStatus &= IOMn(ui32Module)->INTEN; + } + + *pui32IntStatus = ui32IntStatus; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_status_get() + +//***************************************************************************** +// +// IOM interrupt clear +// +//***************************************************************************** +uint32_t +am_hal_iom_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ui32Module = ((am_hal_iom_state_t*)pHandle)->ui32Module; + + // + // Clear the requested interrupts. + // + IOMn(ui32Module)->INTCLR = ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_interrupt_clear() + +//***************************************************************************** +// +// IOM interrupt service routine +// +//***************************************************************************** +uint32_t am_hal_iom_interrupt_service(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t index; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + +#if (AM_HAL_IOM_CQ == 1) + if (pIOMState->bHP) + { + // + // Accumulate the INTSTAT for this transaction + // + pIOMState->ui32TxnInt |= ui32IntMask; + + // + // Check for the command completion + // + if (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_CMDCMP | AM_HAL_IOM_INT_DERR)) + { + // + // We need to wait for the DMA complete as well + // Special case for 0 length DMA - by checking the DMAEN register + // + if ((IOMn(ui32Module)->DMACFG_b.DMAEN == 0) || (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_ERR))) + { + // Call the callback + // Need to determine the error, call the callback with proper status + pIOMState->ui32LastHPIdxProcessed++; + pIOMState->ui32NumHPEntries--; + index = pIOMState->ui32LastHPIdxProcessed % pIOMState->ui32MaxHPTransactions; + am_hal_iom_dma_entry_t *pDMAEntry = &pIOMState->pHPTransactions[index]; + if ( pDMAEntry->pfnCallback != NULL ) + { + pDMAEntry->pfnCallback(pDMAEntry->pCallbackCtxt, internal_iom_get_int_err(ui32Module, pIOMState->ui32TxnInt)); + pDMAEntry->pfnCallback = NULL; + } + + if (pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR) + { + // + // Do Error recovery + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Clear DMAERR in DMASTAT + // + IOMn(ui32Module)->DMASTAT = 0; + + // + // Reset Submodule & FIFO + // + internal_iom_reset_on_error(pIOMState, pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR); + } + // + // Post next transaction if queue is not empty + // + if (pIOMState->ui32NumHPEntries) + { + // + // Initialize the DMA state machine (clear the DMACPL flag). + // + IOMn(ui32Module)->DMASTAT = 0; + //AM_REGn(IOM, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + pIOMState->ui32TxnInt = 0; + program_dma(pIOMState); + } + else + { + pIOMState->bHP = false; + // Unpause the CQ + // Restore interrupts + IOMn(ui32Module)->INTEN &= ~(AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP); + // Resume the CQ + IOMn(ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_CQ; + } + } + } + return AM_HAL_STATUS_SUCCESS; + } +#endif + if (pIOMState->ui32NumPendTransactions) + { +#if (AM_HAL_IOM_CQ == 1) + am_hal_cmdq_status_t status; + + // + // Get the current and last indexes. + // + if (pIOMState->pCmdQHdl && ((ui32Status = am_hal_cmdq_get_status(pIOMState->pCmdQHdl, &status)) == AM_HAL_STATUS_SUCCESS)) + { + // For Sequence - this can be updated in the callback + pIOMState->bRestart = false; + // + // Figure out which callbacks need to be handled. + // + while ((pIOMState->ui32LastIdxProcessed != status.lastIdxProcessed) && !(pIOMState->bRestart)) + { + pIOMState->ui32LastIdxProcessed++; + pIOMState->ui32NumPendTransactions--; + index = pIOMState->ui32LastIdxProcessed & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1); + if ( pIOMState->pfnCallback[index] != NULL ) + { + pIOMState->pfnCallback[index](pIOMState->pCallbackCtxt[index], AM_HAL_STATUS_SUCCESS); + if (pIOMState->eSeq != AM_HAL_IOM_SEQ_RUNNING) + { + pIOMState->pfnCallback[index] = NULL; + } + } + } + + // For Sequence - this can be updated in the callback + if (!pIOMState->bRestart) + { + // + // Check the CQError - If set it indicates that the current transaction encountered an error + // + if (ui32IntMask & AM_HAL_IOM_INT_ERR) + { + // Need to determine the error, call the callback with proper status + pIOMState->ui32LastIdxProcessed++; + pIOMState->ui32NumPendTransactions--; + index = pIOMState->ui32LastIdxProcessed & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1); + if ( pIOMState->pfnCallback[index] != NULL ) + { + pIOMState->pfnCallback[index](pIOMState->pCallbackCtxt[index], internal_iom_get_int_err(ui32Module, ui32IntMask)); + if (pIOMState->eSeq != AM_HAL_IOM_SEQ_RUNNING) + { + pIOMState->pfnCallback[index] = NULL; + } + } + + // + // Do Error recovery + // Disable CQ + // + IOMn(ui32Module)->CQCFG_b.CQEN = 0; + + // + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Clear DMAERR in DMASTAT + // + IOMn(ui32Module)->DMASTAT = 0; + + // + // Reset Submodule & FIFO + // + internal_iom_reset_on_error(pIOMState, ui32IntMask & AM_HAL_IOM_INT_ERR); + + // + // Move the command queue at next transaction + // + am_hal_cmdq_error_resume(pIOMState->pCmdQHdl); + if (pIOMState->ui32NumPendTransactions) + { + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + } + + if (pIOMState->ui32NumPendTransactions == 0) + { + // + // Disable the Command Queue + // + am_hal_iom_CQDisable(pHandle); + } + } +#else // !AM_HAL_IOM_CQ + // + // Accumulate the INTSTAT for this transaction + // + pIOMState->ui32TxnInt |= ui32IntMask; + + // + // Check for the command completion + // + if (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_CMDCMP | AM_HAL_IOM_INT_DERR)) + { + // + // We need to wait for the DMA complete as well + // Special case for 0 length DMA - by checking the DMAEN register + // + if ((IOMn(ui32Module)->DMACFG_b.DMAEN == 0) || (pIOMState->ui32TxnInt & (AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_ERR))) + { + // Call the callback + // Need to determine the error, call the callback with proper status + pIOMState->ui32LastIdxProcessed++; + pIOMState->ui32NumPendTransactions--; + index = pIOMState->ui32LastIdxProcessed % pIOMState->ui32MaxTransactions; + if ( pIOMState->pfnCallback[index] != NULL ) + { + pIOMState->pfnCallback[index](pIOMState->pCallbackCtxt[index], internal_iom_get_int_err(ui32Module, pIOMState->ui32TxnInt)); + pIOMState->pfnCallback[index] = NULL; + } + + if (pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR) + { + // + // Do Error recovery + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Clear DMAERR in DMASTAT + // + IOMn(ui32Module)->DMASTAT = 0; + + // + // Reset Submodule & FIFO + // + internal_iom_reset_on_error(pIOMState, pIOMState->ui32TxnInt & AM_HAL_IOM_INT_ERR); + } + // + // Post next transaction if queue is not empty + // + if (pIOMState->ui32NumPendTransactions) + { + index = (pIOMState->ui32LastIdxProcessed + 1) % pIOMState->ui32MaxTransactions; + + // + // Initialize the DMA state machine (clear the DMACPL flag). + // + IOMn(ui32Module)->DMASTAT = 0; + //AM_REGn(IOM, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + pIOMState->ui32TxnInt = 0; + run_txn_cmdlist(&pIOMState->pTransactions[index], sizeof(am_hal_iom_txn_cmdlist_t) / sizeof(am_hal_cmdq_entry_t)); + } + } + } +#endif // !AM_HAL_IOM_CQ + + if (pIOMState->ui32NumPendTransactions == 0) + { +#if 0 // Taken off from here - we'll anyways disable it at the start of next transaction + // + // Disable DMA + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; +#endif + + // + // Clear interrupts + // Restore IOM interrupts. + // + IOM_SET_INTEN(ui32Module, pIOMState->ui32UserIntCfg); + } + } + + // + // Return the status. + // + return ui32Status; + +} // am_hal_iom_interrupt_service() + +//***************************************************************************** +// +// IOM power control function +// +//***************************************************************************** +uint32_t +am_hal_iom_power_ctrl(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update IOM operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + if (bRetainState && !pIOMState->registerState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOM0 + pIOMState->ui32Module)); + + if (bRetainState) + { + // + // Restore IOM registers + IOMn(pIOMState->ui32Module)->FIFOTHR = pIOMState->registerState.regFIFOTHR; + IOMn(pIOMState->ui32Module)->CLKCFG = pIOMState->registerState.regCLKCFG; + IOMn(pIOMState->ui32Module)->SUBMODCTRL = pIOMState->registerState.regSUBMODCTRL; + IOMn(pIOMState->ui32Module)->CQADDR = pIOMState->registerState.regCQADDR; + IOMn(pIOMState->ui32Module)->CQPAUSEEN = pIOMState->registerState.regCQPAUSEEN; + IOMn(pIOMState->ui32Module)->CQCURIDX = pIOMState->registerState.regCQCURIDX; + IOMn(pIOMState->ui32Module)->CQENDIDX = pIOMState->registerState.regCQENDIDX; + IOMn(pIOMState->ui32Module)->MSPICFG = pIOMState->registerState.regMSPICFG; + IOMn(pIOMState->ui32Module)->MI2CCFG = pIOMState->registerState.regMI2CCFG; + IOMn(pIOMState->ui32Module)->INTEN = pIOMState->registerState.regINTEN; + IOMn(pIOMState->ui32Module)->DMATRIGEN = pIOMState->registerState.regDMATRIGEN; + + // CQFGLAGS are Read-Only and hence can not be directly restored. + // We can try to restore the SWFlags here. Hardware flags depend on external conditions + // and hence can not be restored (assuming the external conditions remain the same, it should be set automatically. + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_SET(pIOMState->registerState.regCQFLAGS & 0xFF); + // + // Set CQCFG last - can not set the enable yet + // + IOMn(pIOMState->ui32Module)->CQCFG = pIOMState->registerState.regCQCFG & ~_VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN); + if (pIOMState->registerState.regCQCFG & _VAL2FLD(IOM0_CQCFG_CQEN, IOM0_CQCFG_CQEN_EN)) + { + am_hal_iom_CQEnable(pIOMState); + } + pIOMState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + // Make sure IOM is not active currently + if (pIOMState->prefix.s.bEnable && + (((IOMn(pIOMState->ui32Module)->STATUS & (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk)) != IOM0_STATUS_IDLEST_Msk) || + pIOMState->ui32NumPendTransactions)) + { + return AM_HAL_STATUS_IN_USE; + } + if (bRetainState) + { + // Save IOM Registers + pIOMState->registerState.regFIFOTHR = IOMn(pIOMState->ui32Module)->FIFOTHR; + pIOMState->registerState.regCLKCFG = IOMn(pIOMState->ui32Module)->CLKCFG; + pIOMState->registerState.regSUBMODCTRL = IOMn(pIOMState->ui32Module)->SUBMODCTRL; + pIOMState->registerState.regCQCFG = IOMn(pIOMState->ui32Module)->CQCFG; + pIOMState->registerState.regCQADDR = IOMn(pIOMState->ui32Module)->CQADDR; + pIOMState->registerState.regCQFLAGS = IOMn(pIOMState->ui32Module)->CQFLAGS; + pIOMState->registerState.regCQPAUSEEN = IOMn(pIOMState->ui32Module)->CQPAUSEEN; + pIOMState->registerState.regCQCURIDX = IOMn(pIOMState->ui32Module)->CQCURIDX; + pIOMState->registerState.regCQENDIDX = IOMn(pIOMState->ui32Module)->CQENDIDX; + pIOMState->registerState.regMSPICFG = IOMn(pIOMState->ui32Module)->MSPICFG; + pIOMState->registerState.regMI2CCFG = IOMn(pIOMState->ui32Module)->MI2CCFG; + pIOMState->registerState.regINTEN = IOMn(pIOMState->ui32Module)->INTEN; + pIOMState->registerState.regDMATRIGEN = IOMn(pIOMState->ui32Module)->DMATRIGEN; + pIOMState->registerState.bValid = true; + } + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOM0 + pIOMState->ui32Module)); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_iom_power_ctrl() + +//***************************************************************************** +// +// IOM configuration function. +// +//***************************************************************************** +uint32_t +am_hal_iom_configure(void *pHandle, am_hal_iom_config_t *psConfig) +{ + uint32_t ui32ClkCfg; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ( (pHandle == NULL) || + (psConfig == NULL) || + (pIOMState->ui32Module >= AM_REG_IOM_NUM_MODULES) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // Configure not allowed in Enabled state + if (pIOMState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + // + // Save the interface mode and chip select in the global handle. + // + pIOMState->eInterfaceMode = psConfig->eInterfaceMode; + + // + // Set the IOM read/write FIFO thresholds to default values. + // + IOMn(ui32Module)->FIFOTHR = + _VAL2FLD(IOM0_FIFOTHR_FIFORTHR, 16) | + _VAL2FLD(IOM0_FIFOTHR_FIFOWTHR, 16); + + if ( psConfig->eInterfaceMode == AM_HAL_IOM_SPI_MODE ) + { +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the SPI mode + // + if ( psConfig->eSpiMode > AM_HAL_IOM_SPI_MODE_3 ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psConfig->ui32ClockFreq > AM_HAL_IOM_MAX_FREQ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Determine the CLKCFG value for SPI. + // + ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFreq, (psConfig->eSpiMode & 2) >> 1); + + // + // Set the SPI configuration. + // + IOMn(ui32Module)->MSPICFG = + ( ((psConfig->eSpiMode << IOM0_MSPICFG_SPOL_Pos) & (IOM0_MSPICFG_SPHA_Msk | IOM0_MSPICFG_SPOL_Msk)) | + _VAL2FLD(IOM0_MSPICFG_FULLDUP, 0) | + _VAL2FLD(IOM0_MSPICFG_WTFC, IOM0_MSPICFG_WTFC_DIS) | + _VAL2FLD(IOM0_MSPICFG_RDFC, IOM0_MSPICFG_RDFC_DIS) | + _VAL2FLD(IOM0_MSPICFG_MOSIINV, IOM0_MSPICFG_MOSIINV_NORMAL) | + _VAL2FLD(IOM0_MSPICFG_WTFCIRQ, IOM0_MSPICFG_WTFCIRQ_MISO) | + _VAL2FLD(IOM0_MSPICFG_WTFCPOL, IOM0_MSPICFG_WTFCPOL_HIGH) | + _VAL2FLD(IOM0_MSPICFG_RDFCPOL, IOM0_MSPICFG_RDFCPOL_HIGH) | + _VAL2FLD(IOM0_MSPICFG_SPILSB, IOM0_MSPICFG_SPILSB_MSB) | + _VAL2FLD(IOM0_MSPICFG_DINDLY, 0) | + _VAL2FLD(IOM0_MSPICFG_DOUTDLY, 0) | + _VAL2FLD(IOM0_MSPICFG_MSPIRST, 0) ); + } + else if ( psConfig->eInterfaceMode == AM_HAL_IOM_I2C_MODE ) + { + + switch (psConfig->ui32ClockFreq) + { + case AM_HAL_IOM_100KHZ: + // + // settings below should give ~100 kHz + // + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, 0x77) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0x3B) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, IOM0_CLKCFG_FSEL_HFRC_DIV2) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 3) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 15) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + case AM_HAL_IOM_400KHZ: + // + // settings below should give ~400 kHz + // + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, 0x1D) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0x0E) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, IOM0_CLKCFG_FSEL_HFRC_DIV2) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 3) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 15) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 2) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + case AM_HAL_IOM_1MHZ: + // + // settings below should give ~860 kHz + // + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, 0x06) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, 0x03) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, IOM0_CLKCFG_FSEL_HFRC_DIV4) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 0x21) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + default: + { + //Calculate TOTPER and FSEL based on requested frequency + uint32_t reqFreq = psConfig->ui32ClockFreq; + uint32_t fsel = 2; + uint32_t totper = 0; + for( ; fsel < 128 ; fsel = fsel * 2) + { + //IOM and HFRC are not affected by burst mode + totper = (AM_HAL_IOM_48MHZ / (2 * fsel))/reqFreq - 1; + if(totper < 256) break; + } + + if(fsel == 128) + { + //If fsel is too large, return with error + return AM_HAL_STATUS_INVALID_ARG; + } + + uint32_t fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV2; + + if(fsel == 2) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV2; + else if(fsel == 4) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV4; + else if(fsel == 8) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV8; + else if(fsel == 16) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV16; + else if(fsel == 32) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV32; + else if(fsel == 64) + fsel_bitvalue = IOM0_CLKCFG_FSEL_HFRC_DIV64; + + ui32ClkCfg = _VAL2FLD(IOM0_CLKCFG_TOTPER, totper) | + _VAL2FLD(IOM0_CLKCFG_LOWPER, totper/2) | + _VAL2FLD(IOM0_CLKCFG_DIVEN, IOM0_CLKCFG_DIVEN_EN) | + _VAL2FLD(IOM0_CLKCFG_DIV3, IOM0_CLKCFG_DIV3_DIS) | + _VAL2FLD(IOM0_CLKCFG_FSEL, fsel_bitvalue) | + _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->MI2CCFG = _VAL2FLD(IOM0_MI2CCFG_STRDIS, 0) | + _VAL2FLD(IOM0_MI2CCFG_SMPCNT, 0x21) | + _VAL2FLD(IOM0_MI2CCFG_SDAENDLY, 3) | + _VAL2FLD(IOM0_MI2CCFG_SCLENDLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_MI2CRST, 1) | + _VAL2FLD(IOM0_MI2CCFG_SDADLY, 0) | + _VAL2FLD(IOM0_MI2CCFG_ARBEN, IOM0_MI2CCFG_ARBEN_ARBDIS) | + _VAL2FLD(IOM0_MI2CCFG_I2CLSB, IOM0_MI2CCFG_I2CLSB_MSBFIRST) | + _VAL2FLD(IOM0_MI2CCFG_ADDRSZ, IOM0_MI2CCFG_ADDRSZ_ADDRSZ7); + break; + } + } + + } + else + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Enable and set the clock configuration. + // + ui32ClkCfg |= _VAL2FLD(IOM0_CLKCFG_IOCLKEN, 1); + IOMn(ui32Module)->CLKCFG = ui32ClkCfg; + + pIOMState->ui32BitTimeTicks = AM_HAL_CLKGEN_FREQ_MAX_HZ / psConfig->ui32ClockFreq; + + // + // Set the delay timeout value to the default maximum value. + // + pIOMState->waitTimeout = 1000; + + pIOMState->pNBTxnBuf = psConfig->pNBTxnBuf; + pIOMState->ui32NBTxnBufLength = psConfig->ui32NBTxnBufLength; +#if (AM_HAL_IOM_CQ == 1) + // Worst case minimum CQ entries that can be accomodated in provided buffer + // Need to account for the wrap + pIOMState->ui32MaxPending = ((pIOMState->ui32NBTxnBufLength - 8) * 4 / AM_HAL_IOM_CQ_ENTRY_SIZE); + if (pIOMState->ui32MaxPending > AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) + { + pIOMState->ui32MaxPending = AM_HAL_IOM_MAX_PENDING_TRANSACTIONS; + } +#endif + // Disable the DCX + for (uint8_t i = 0; i <= AM_HAL_IOM_MAX_CS_SPI; i++) + { + pIOMState->dcx[i] = 0; + } + + // + // Return the status. + // + return status; + +} // am_hal_iom_configure() + +//***************************************************************************** +// +// IOM blocking transfer function +// +//***************************************************************************** +uint32_t +am_hal_iom_blocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction) +{ + uint32_t ui32Cmd, ui32Offset, ui32OffsetCnt, ui32Dir, ui32Cont; + uint32_t ui32FifoRem, ui32FifoSiz; + uint32_t ui32Bytes; + uint32_t ui32IntConfig; + uint32_t *pui32Buffer; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + bool bCmdCmp = false; + uint32_t numWait = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !psTransaction ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (psTransaction->eDirection > AM_HAL_IOM_RX) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Bytes = psTransaction->ui32NumBytes; + if ( ui32Bytes == 0 ) + { + // + // Only TX is supported for 0-length transactions. A 0-length + // transfer presumes that only an offset value is being written. + // + psTransaction->eDirection = AM_HAL_IOM_TX; + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, true); + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } +#endif // AM_HAL_DISABLE_API_VALIDATION +#if (AM_HAL_IOM_CQ == 1) + if (pIOMState->eSeq == AM_HAL_IOM_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + + ui32Module = pIOMState->ui32Module; + ui32Offset = psTransaction->ui32Instr; + ui32OffsetCnt = psTransaction->ui32InstrLen; + ui32Dir = psTransaction->eDirection; + ui32Cont = psTransaction->bContinue ? 1 : 0; + pui32Buffer = (ui32Dir == AM_HAL_IOM_TX) ? psTransaction->pui32TxBuffer : psTransaction->pui32RxBuffer; + + // + // Make sure any previous non-blocking transfers have completed. + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&pIOMState->ui32NumPendTransactions, + 0xFFFFFFFF, + 0, + true); + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Make sure any previous blocking transfer has been completed. + // This check is required to make sure previous transaction has cleared if the blocking call + // finished with a timeout + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = IOMn(ui32Module)->INTEN; + // + // Disable IOM interrupts as we'll be polling + // + IOMn(ui32Module)->INTEN = 0; + // + // Disable DMA - in case the last transaction was DMA + // For CQ - we disable DMA only at the start of next transaction + // + IOMn(ui32Module)->DMACFG_b.DMAEN = 0; + + + // + // Clear interrupts + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + + // + // Set the dev addr (either 7 or 10 bit as configured in MI2CCFG). + // + IOMn(ui32Module)->DEVCFG = psTransaction->uPeerInfo.ui32I2CDevAddr; + // CMDRPT register has been repurposed for DCX + // Set the DCX + IOMn(ui32Module)->DCX = (pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE) ? pIOMState->dcx[psTransaction->uPeerInfo.ui32SpiChipSelect] : 0; + // + // Build the CMD value + // + + ui32Cmd = pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE ? + psTransaction->uPeerInfo.ui32SpiChipSelect : 0; + ui32Cmd = build_cmd(ui32Cmd, ui32Dir, ui32Cont, ui32Offset, ui32OffsetCnt, ui32Bytes); + + // + // Set the OFFSETHI register. + // + IOMn(ui32Module)->OFFSETHI = (uint16_t)(ui32Offset >> 8); + + ui32Bytes = psTransaction->ui32NumBytes; + + if ( ui32Dir == AM_HAL_IOM_RX ) + { + // + // Start the transfer + // + IOMn(ui32Module)->CMD = ui32Cmd; + + + // + // Start a loop to catch the Rx data. + // + while ( ui32Bytes ) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + while ((ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ) < 4) + { + if (numWait++ < AM_HAL_IOM_MAX_BLOCKING_WAIT) + { + if (bCmdCmp && (ui32Bytes > ui32FifoSiz)) + { + // + // No more data expected. Get out of the loop + // + break; + } + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + // + // We've waited long enough - get out! + // + break; + } + bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; + } + if (ui32FifoSiz < 4) + { + // + // Something went wrong - get out and report failure + // + break; + } + + while ((ui32FifoSiz >= 4) && ui32Bytes) + { + // + // Safe to read the FIFO, read 4 bytes + // + uint32_t ui32Read; + ui32Read = IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + ui32FifoSiz -= 4; + if (ui32Bytes >= 4) + { + *pui32Buffer++ = ui32Read; + ui32Bytes -= 4; + } + else + { + // Copy byte by byte - so as to not corrupt the rest of the buffer + uint8_t *pui8Buffer = (uint8_t *)pui32Buffer; + do + { + *pui8Buffer++ = ui32Read & 0xFF; + ui32Read >>= 8; + } while (--ui32Bytes); + + } + } + } + } + else if ( ui32Dir == AM_HAL_IOM_TX ) + { + // Write data to FIFO first - before starting the transfer + + ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; + while ((ui32FifoRem >= 4) && ui32Bytes) + { + IOMn(ui32Module)->FIFOPUSH = *pui32Buffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + + // + // Start the transfer + // + IOMn(ui32Module)->CMD = ui32Cmd; + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while (ui32Bytes) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + while ((ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM) < 4) + { + bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; + if (bCmdCmp || (numWait++ >= AM_HAL_IOM_MAX_BLOCKING_WAIT)) + { + // + // FIFO not expected to change any more - get out + // + break; + } + else + { + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + } + if (bCmdCmp || (ui32FifoRem < 4)) + { + // + // Something went wrong - bail out + // + break; + } + + while ((ui32FifoRem >= 4) && ui32Bytes) + { + IOMn(ui32Module)->FIFOPUSH = *pui32Buffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + } + } + + // + // Make sure transfer is completed. + // + ui32Status = am_hal_flash_delay_status_check(AM_HAL_IOM_MAX_BLOCKING_WAIT, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status == AM_HAL_STATUS_SUCCESS ) + { + ui32Status = internal_iom_get_int_err(ui32Module, 0); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (ui32Bytes) + { + // Indicates transaction did not finish for some reason + ui32Status = AM_HAL_STATUS_FAIL; + } + } + } + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + // Do Error recovery + // Reset Submodule & FIFO + internal_iom_reset_on_error(pIOMState, IOMn(ui32Module)->INTSTAT); + } + + // + // Clear interrupts + // Re-enable IOM interrupts. + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + IOMn(ui32Module)->INTEN = ui32IntConfig; + + // + // Return the status. + // + return ui32Status; + +} // am_hal_iom_blocking_transfer() + + +//***************************************************************************** +// +// IOM non-blocking transfer function +// +//***************************************************************************** +uint32_t +am_hal_iom_nonblocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32NumPend; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !psTransaction ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (psTransaction->eDirection > AM_HAL_IOM_RX) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( psTransaction->ui32NumBytes == 0 ) + { + // + // Only TX is supported for 0-length transactions. A 0-length + // transfer presumes that only an offset value is being written. + // + psTransaction->eDirection = AM_HAL_IOM_TX; + } + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, false); + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + +#if (AM_HAL_IOM_CQ == 1) + am_hal_iom_callback_t pfnCallback1 = pfnCallback; + if (!pIOMState->pCmdQHdl) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (pIOMState->eSeq == AM_HAL_IOM_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (pIOMState->block && (psTransaction->ui32PauseCondition != 0)) + { + // Paused operations not allowed in block mode + return AM_HAL_STATUS_INVALID_OPERATION; + } + if ( !pfnCallback1 && !pIOMState->block && (pIOMState->eSeq == AM_HAL_IOM_SEQ_NONE) && + (pIOMState->ui32NumUnSolicited >= (pIOMState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumPendTransactions get updated in ISR + pfnCallback1 = iom_dummy_callback; + } + // + // DMA defaults to using the Command Queue + // + ui32Status = am_hal_iom_CQAddTransaction(pHandle, psTransaction, pfnCallback1, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + uint32_t ui32Critical = 0; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Register for interrupt only if there is a callback + // + ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pfnCallback1); + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + ui32NumPend = pIOMState->ui32NumPendTransactions++; + pIOMState->ui32NumSeqTransactions++; + if (pfnCallback) + { + pIOMState->bAutonomous = false; + pIOMState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pIOMState->ui32NumUnSolicited = 0; + } + else + { + pIOMState->ui32NumUnSolicited++; + } + } + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(pIOMState->ui32Module)->INTEN; + IOM_SET_INTEN(pIOMState->ui32Module, AM_HAL_IOM_INT_CQMODE); + am_hal_iom_CQEnable(pIOMState); + } + + } + else + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + } +#else // !AM_HAL_IOM_CQ + uint32_t ui32Module = pIOMState->ui32Module; + if (pIOMState->ui32MaxTransactions == 0) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + ui32Status = am_hal_iom_DmaAddTransaction(pHandle, psTransaction, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pIOMState->ui32NumPendTransactions++; + + // + // End the critical section. + // + AM_CRITICAL_END + + if (0 == ui32NumPend) + { + uint32_t index = (pIOMState->ui32LastIdxProcessed + 1) % pIOMState->ui32MaxTransactions; + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + + // + // Clear interrupts + // + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_DMAMODE); + + + // + // Initialize the DMA state machine (clear the DMACPL flag). + // + IOMn(ui32Module)->DMASTAT = 0; + pIOMState->ui32TxnInt = 0; + + // + // Run the command list + // + run_txn_cmdlist(&pIOMState->pTransactions[index], sizeof(am_hal_iom_txn_cmdlist_t) / sizeof(am_hal_cmdq_entry_t)); + } + } +#endif // !AM_HAL_IOM_CQ + + // + // Return the status. + // + return ui32Status; + +} // am_hal_iom_nonblocking_transfer() + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex transaction to the SPI interface. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +uint32_t +am_hal_iom_spi_blocking_fullduplex(void *pHandle, + am_hal_iom_transfer_t *psTransaction) +{ + uint32_t ui32Cmd, ui32Offset, ui32OffsetCnt, ui32Dir, ui32Cont; + uint32_t ui32FifoRem, ui32FifoSiz; + uint32_t ui32Bytes; + uint32_t ui32RxBytes; + uint32_t ui32IntConfig; + uint32_t *pui32TxBuffer; + uint32_t *pui32RxBuffer; + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + bool bCmdCmp = false; + uint32_t numWait = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !psTransaction ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if ( psTransaction->eDirection != AM_HAL_IOM_FULLDUPLEX ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOMState->ui32Module; + ui32Offset = psTransaction->ui32Instr; + ui32OffsetCnt = psTransaction->ui32InstrLen; + ui32Bytes = psTransaction->ui32NumBytes; + ui32Dir = psTransaction->eDirection; + ui32Cont = psTransaction->bContinue ? 1 : 0; + pui32RxBuffer = psTransaction->pui32RxBuffer; + pui32TxBuffer = psTransaction->pui32TxBuffer; + + // + // Make sure any previous non-blocking transfers have completed. + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&pIOMState->ui32NumPendTransactions, + 0xFFFFFFFF, + 0, + true); + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Make sure any previous blocking transfer has been completed. + // This check is required to make sure previous transaction has cleared if the blocking call + // finished with a timeout + // + ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = IOMn(ui32Module)->INTEN; + + // + // Disable IOM interrupts as we'll be polling + // + IOMn(ui32Module)->INTEN = 0; + + // + // Clear interrupts + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + + // + // Set the dev addr (either 7 or 10 bit as configured in MI2CCFG). + // + IOMn(ui32Module)->DEVCFG = psTransaction->uPeerInfo.ui32I2CDevAddr; + // CMDRPT register has been repurposed for DCX + // Set the DCX + IOMn(ui32Module)->DCX = pIOMState->dcx[psTransaction->uPeerInfo.ui32SpiChipSelect]; + + // + // Build the CMD value + // + + ui32Cmd = pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE ? + psTransaction->uPeerInfo.ui32SpiChipSelect : 0; + ui32Cmd = build_cmd(ui32Cmd, ui32Dir, ui32Cont, ui32Offset, ui32OffsetCnt, ui32Bytes); + + // + // Set the OFFSETHI register. + // + IOMn(ui32Module)->OFFSETHI = (uint16_t)(ui32Offset >> 8); + + // + // Set FULLDUPLEX mode + // + IOMn(ui32Module)->MSPICFG |= _VAL2FLD(IOM0_MSPICFG_FULLDUP, 1); + + // + // Start the transfer + // + IOMn(ui32Module)->CMD = ui32Cmd; + + ui32Bytes = psTransaction->ui32NumBytes; + ui32RxBytes = ui32Bytes; + + // + // Start a loop to catch the Rx data. + // + // + // Keep looping until we're out of bytes to send or command complete (error). + // + while (ui32Bytes || ui32RxBytes) + { + // + // Limit the wait to reasonable limit - instead of blocking forever + // + numWait = 0; + ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; + ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ; + + while ((ui32FifoRem < 4) && + (ui32FifoSiz < 4)) + { + if (numWait++ < AM_HAL_IOM_MAX_BLOCKING_WAIT) + { + if (bCmdCmp && (ui32RxBytes > ui32FifoSiz)) + { + // + // No more data expected. Get out of the loop + // + break; + } + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + // + // We've waited long enough - get out! + // + break; + } + bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; + ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; + ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ; + } + if (bCmdCmp || ((ui32FifoRem < 4) && (ui32FifoSiz < 4))) + { + // + // Something went wrong - bail out + // + break; + } + + while ((ui32FifoRem >= 4) && ui32Bytes) + { + IOMn(ui32Module)->FIFOPUSH = *pui32TxBuffer++; + ui32FifoRem -= 4; + if (ui32Bytes >= 4) + { + ui32Bytes -= 4; + } + else + { + ui32Bytes = 0; + } + } + while ((ui32FifoSiz >= 4) && ui32RxBytes) + { + // + // Safe to read the FIFO, read 4 bytes + // + *pui32RxBuffer++ = IOMn(ui32Module)->FIFOPOP; +#if MANUAL_POP + IOMn(ui32Module)->FIFOPOP = 0x11111111; +#endif + ui32FifoSiz -= 4; + if (ui32RxBytes >= 4) + { + ui32RxBytes -= 4; + } + else + { + ui32RxBytes = 0; + } + } + } + + // + // Make sure transfer is completed. + // + ui32Status = am_hal_flash_delay_status_check(AM_HAL_IOM_MAX_BLOCKING_WAIT, + (uint32_t)&IOMn(ui32Module)->STATUS, + (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), + IOM0_STATUS_IDLEST_Msk, + true); + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + return ui32Status; + } + + ui32Status = internal_iom_get_int_err(ui32Module, 0); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (ui32Bytes) + { + // Indicates transaction did not finish for some reason + ui32Status = AM_HAL_STATUS_FAIL; + } + } + else + { + // Do Error recovery + // Reset Submodule & FIFO + internal_iom_reset_on_error(pIOMState, IOMn(ui32Module)->INTSTAT); + } + + // + // Clear interrupts + // Re-enable IOM interrupts. + // + IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; + IOMn(ui32Module)->INTEN = ui32IntConfig; + + // + // Return the status. + // + return ui32Status; + +} + +//***************************************************************************** +// +//! @brief IOM control function +//! +//! @param handle - handle for the IOM. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArgs) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if (eReq >= AM_HAL_IOM_REQ_MAX) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + uint32_t ui32Module = pIOMState->ui32Module; + switch (eReq) + { + case AM_HAL_IOM_REQ_FLAG_SETCLR: + if (pArgs) + { +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (*((uint32_t *)pArgs) & AM_HAL_IOM_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + IOMn(ui32Module)->CQSETCLEAR = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_LSB: + if (pArgs) + { + IOMn(ui32Module)->MSPICFG_b.SPILSB = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_FULLDUPLEX: + if (pArgs) + { + IOMn(ui32Module)->MSPICFG_b.FULLDUP = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_RDTHRESH: + if (pArgs) + { + IOMn(ui32Module)->FIFOTHR_b.FIFORTHR = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_IOM_REQ_SPI_WRTHRESH: + if (pArgs) + { + IOMn(ui32Module)->FIFOTHR_b.FIFOWTHR = *((uint32_t *)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_IOM_REQ_PAUSE: + // Force CQ to Paused + status = iom_cq_pause(pIOMState); + break; + + case AM_HAL_IOM_REQ_UNPAUSE: + // Resume the CQ + IOMn(ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_CQ; + break; + + + case AM_HAL_IOM_REQ_SET_SEQMODE: + { + am_hal_iom_seq_e eSeq; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pArgs) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pIOMState->pNBTxnBuf) + { + // No space for CMDQ + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + eSeq = *((bool *)pArgs) ? AM_HAL_IOM_SEQ_UNDER_CONSTRUCTION: AM_HAL_IOM_SEQ_NONE; + if (eSeq == pIOMState->eSeq) + { + // Nothing to do + return AM_HAL_STATUS_SUCCESS; + } + +#if 0 // We should be able to operate on sequence even if there are HP transactions in progress + // Make sure there is no high priority transaction in progress + if (pIOMState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + switch (pIOMState->eSeq) + { + case AM_HAL_IOM_SEQ_RUNNING: + { + // Force CQ to Pause + status = iom_cq_pause(pIOMState); + break; + } + case AM_HAL_IOM_SEQ_NONE: + { + // Make sure there is no non-blocking transaction in progress + if (pIOMState->ui32NumPendTransactions) + { + status = AM_HAL_STATUS_INVALID_OPERATION; + } + break; + } + default: + ; + } + if (status == AM_HAL_STATUS_SUCCESS) + { + // Reset the cmdq + am_hal_cmdq_reset(pIOMState->pCmdQHdl); + pIOMState->ui32LastIdxProcessed = 0; + pIOMState->ui32NumSeqTransactions = 0; + pIOMState->ui32NumPendTransactions = 0; + pIOMState->ui32NumUnSolicited = 0; + pIOMState->eSeq = eSeq; + pIOMState->bAutonomous = true; + } + break; + } + + case AM_HAL_IOM_REQ_SEQ_END: + { + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + am_hal_iom_seq_end_t *pLoop = (am_hal_iom_seq_end_t *)pArgs; + uint32_t pause = 0; + uint32_t scUnpause = 0; + uint32_t ui32Critical = 0; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pArgs) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32PauseCondition & AM_HAL_IOM_PAUSE_FLAG_RESV) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32StatusSetClr & AM_HAL_IOM_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pIOMState->eSeq != AM_HAL_IOM_SEQ_UNDER_CONSTRUCTION) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if (pIOMState->block) + { + // End the block if the sequence is ending + pIOMState->block = 0; + // Unblock the whole batch of commands in this block + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_BLOCK; + } + + if ((pLoop->bLoop) && (!pIOMState->bAutonomous)) + { + // Need to insert special element in CQ to cause a callback + // This is to reset internal state + ui32Status = am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, 1, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = iom_seq_loopback; + pIOMState->pCallbackCtxt[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = (void *)pIOMState; + + // Dummy Entry + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQSETCLEAR; + pCQBlock->value = 0; + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post to the CQ. + // + ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, true); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + else + { + uint32_t ui32NumPend = pIOMState->ui32NumPendTransactions++; + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_CQMODE); + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + // Use SWFLAG6 to cause a pause + pause = AM_HAL_IOM_PAUSE_FLAG_SEQLOOP; + // Revert back the flag after SW callback unpauses it + scUnpause = AM_HAL_IOM_SC_PAUSE_SEQLOOP; + } + } + + // Insert the loopback + ui32Status = am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, sizeof(am_hal_iom_cq_loop_entry_t) / 8, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + am_hal_iom_cq_loop_entry_t *pLoopEntry = (am_hal_iom_cq_loop_entry_t *)pCQBlock; + pLoopEntry->ui32PAUSENAddr = pLoopEntry->ui32PAUSEN2Addr = (uint32_t)&IOMn(ui32Module)->CQPAUSEEN; + pLoopEntry->ui32SETCLRAddr = (uint32_t)&IOMn(ui32Module)->CQSETCLEAR; + pLoopEntry->ui32PAUSEENVal = get_pause_val(pIOMState, pLoop->ui32PauseCondition | pause); + pLoopEntry->ui32PAUSEEN2Val = AM_HAL_IOM_PAUSE_DEFAULT; + pLoopEntry->ui32SETCLRVal = pLoop->ui32StatusSetClr | scUnpause; + + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post to the CQ. + // + if (pLoop->bLoop) + { + ui32Status = am_hal_cmdq_post_loop_block(pIOMState->pCmdQHdl, false); + } + else + { + ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, false); + } + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + else + { + uint32_t ui32NumPend = pIOMState->ui32NumPendTransactions++; + pIOMState->eSeq = (pLoop->bLoop) ? AM_HAL_IOM_SEQ_RUNNING : AM_HAL_IOM_SEQ_NONE; + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_CQMODE); + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + } + return AM_HAL_STATUS_SUCCESS; + //break; + } + case AM_HAL_IOM_REQ_INIT_HIPRIO: + { + am_hal_iom_hiprio_cfg_t *pHPCfg = (am_hal_iom_hiprio_cfg_t *)pArgs; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pHPCfg) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + pIOMState->ui32NumHPEntries = pIOMState->ui32LastHPIdxProcessed = 0; + pIOMState->ui32NextHPIdx = pIOMState->ui32LastHPIdxProcessed + 1; + pIOMState->pHPTransactions = (am_hal_iom_dma_entry_t *)pHPCfg->pBuf; + pIOMState->ui32MaxHPTransactions = pHPCfg->size / sizeof(am_hal_iom_dma_entry_t); + break; + } + + case AM_HAL_IOM_REQ_START_BLOCK: + // Pause the next block from proceeding till whole block is finished + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_PAUSE_BLOCK; + pIOMState->block = 1; + pIOMState->ui32NumHPPendingEntries = 0; + break; + + case AM_HAL_IOM_REQ_END_BLOCK: + // Unblock the whole batch of commands in this block + IOMn(pIOMState->ui32Module)->CQSETCLEAR = AM_HAL_IOM_SC_UNPAUSE_BLOCK; + pIOMState->block = 0; + if (pIOMState->ui32NumHPPendingEntries) + { + // Now it is okay to let go of the block of HiPrio transactions + status = sched_hiprio(pIOMState, pIOMState->ui32NumHPPendingEntries); + if (status == AM_HAL_STATUS_SUCCESS) + { + pIOMState->ui32NumHPPendingEntries = 0; + } + } + break; + + case AM_HAL_IOM_REQ_SET_DCX: + { + am_hal_iom_dcx_cfg_t *pDcxCfg = (am_hal_iom_dcx_cfg_t *)pArgs; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pDcxCfg) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if ((pIOMState->eInterfaceMode != AM_HAL_IOM_SPI_MODE) || + (pDcxCfg->cs == pDcxCfg->dcx) || + (pDcxCfg->cs > AM_HAL_IOM_MAX_CS_SPI) || + ((pDcxCfg->dcx != AM_HAL_IOM_DCX_INVALID) && (pDcxCfg->dcx > AM_HAL_IOM_MAX_CS_SPI))) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if ( !APOLLO3_GE_B0 ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + pIOMState->dcx[pDcxCfg->cs] = (pDcxCfg->dcx == AM_HAL_IOM_DCX_INVALID) ? 0 : (IOM0_DCX_DCXEN_Msk | (0x1 << pDcxCfg->dcx)); + break; + } + + case AM_HAL_IOM_REQ_CQ_RAW: + { +#if (AM_HAL_IOM_CQ == 1) + am_hal_iom_cq_raw_t *pCqRaw = (am_hal_iom_cq_raw_t *)pArgs; + am_hal_cmdq_entry_t *pCQBlock; + am_hal_iom_callback_t pfnCallback1; + + uint32_t ui32Critical = 0; + uint32_t index; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pCqRaw) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pIOMState->pCmdQHdl) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Check to see if there is enough room in the CQ + // + if ((pIOMState->ui32NumPendTransactions == AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) || + (am_hal_cmdq_alloc_block(pIOMState->pCmdQHdl, pCqRaw->numEntries + 3, &pCQBlock, &index))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQPAUSEEN; + pCQBlock->value = get_pause_val(pIOMState, pCqRaw->ui32PauseCondition); + pCQBlock++; + for (uint32_t i = 0; i < pCqRaw->numEntries; i++, pCQBlock++) + { + pCQBlock->address = pCqRaw->pCQEntry[i].address; + pCQBlock->value = pCqRaw->pCQEntry[i].value; + } + // If there is a need - populate the jump back address + if (pCqRaw->pJmpAddr) + { + *(pCqRaw->pJmpAddr) = (uint32_t)pCQBlock; + } + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQPAUSEEN; + pCQBlock->value = AM_HAL_IOM_PAUSE_DEFAULT; + pCQBlock++; + pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQSETCLEAR; + pCQBlock->value = pCqRaw->ui32StatusSetClr; + + pfnCallback1 = pCqRaw->pfnCallback; + if ( !pfnCallback1 && !pIOMState->block && (pIOMState->eSeq == AM_HAL_IOM_SEQ_NONE) && + (pIOMState->ui32NumUnSolicited >= (pIOMState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumPendTransactions get updated in ISR + pfnCallback1 = iom_dummy_callback; + } + // + // Store the callback function pointer. + // + pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pfnCallback1; + pIOMState->pCallbackCtxt[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pCqRaw->pCallbackCtxt; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Register for interrupt only if there is a callback + // + status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pfnCallback1); + + if (status == AM_HAL_STATUS_SUCCESS) + { + uint32_t ui32NumPend = pIOMState->ui32NumPendTransactions++; + pIOMState->ui32NumSeqTransactions++; + if (pCqRaw->pfnCallback) + { + pIOMState->bAutonomous = false; + pIOMState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pIOMState->ui32NumUnSolicited = 0; + } + else + { + pIOMState->ui32NumUnSolicited++; + } + } + if (0 == ui32NumPend) + { + pIOMState->ui32UserIntCfg = IOMn(ui32Module)->INTEN; + IOM_SET_INTEN(ui32Module, AM_HAL_IOM_INT_CQMODE); + // Re-enable the CQ + am_hal_iom_CQEnable(pIOMState); + } + } + else + { + am_hal_cmdq_release_block(pIOMState->pCmdQHdl); + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); +#else // !AM_HAL_IOM_CQ + status = AM_HAL_STATUS_INVALID_ARG; +#endif + break; + } + + + default: + status = AM_HAL_STATUS_INVALID_ARG; + } + + return status; +} + +// +// IOM High Priority transfer function +// +uint32_t am_hal_iom_highprio_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t *)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_IOM_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pIOMState->pNBTxnBuf) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + // + // Validate parameters + // + ui32Status = validate_transaction(pIOMState, psTransaction, false); + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + if (psTransaction->ui32PauseCondition != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psTransaction->ui32StatusSetClr != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (psTransaction->eDirection > AM_HAL_IOM_RX) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (!pIOMState->pHPTransactions) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + +#if (AM_HAL_IOM_CQ == 1) + + ui32Status = iom_add_hp_transaction(pHandle, psTransaction, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (!(pIOMState->block)) + { + ui32Status = sched_hiprio(pIOMState, 1); + } + else + { + pIOMState->ui32NumHPPendingEntries++; + } + } + +#else + ui32Status = AM_HAL_STATUS_INVALID_OPERATION; +#endif // !AM_HAL_IOM_CQ + + // + // Return the status. + // + return ui32Status; +} + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.h new file mode 100644 index 0000000000..c2c68e09c1 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_iom.h @@ -0,0 +1,844 @@ +//***************************************************************************** +// +//! @file am_hal_iom.h +//! +//! @brief Functions for accessing and configuring the IO Master module +//! +//! @addtogroup hal Hardware Abstraction Layer (HAL) +//! @addtogroup iom3 IO Master (SPI/I2C) +//! @ingroup hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_IOM_H +#define AM_HAL_IOM_H + +#include "am_hal_status.h" +#include "am_hal_sysctrl.h" + + +//***************************************************************************** +// +//! CMSIS-Style macro for handling a variable IOM module number. +// +//***************************************************************************** +#define IOMn(n) ((IOM0_Type*)(IOM0_BASE + (n * (IOM1_BASE - IOM0_BASE)))) + +// +// Maximum time to wait for hardware to finish a blocking transaction +// This is an escape to allow for bailing out in case of faulty peripheral +// (e.g. a device pulling the I2C clock low) +// +#define AM_HAL_IOM_MAX_BLOCKING_WAIT 500000 // 0.5 sec + +// +// AM_HAL_IOM_CQ=1 will use the Command Queue in nonblocking transfers. +// 0 uses plain DMA (w/o CQ) in nonblocking transfers. +// This should be enabled only for A1 silicon. +// +#define AM_HAL_IOM_CQ 1 + +// Size guideline for allocation of application supploed buffers +#define AM_HAL_IOM_CQ_ENTRY_SIZE (24 * sizeof(uint32_t)) +#define AM_HAL_IOM_HIPRIO_ENTRY_SIZE (8 * sizeof(uint32_t)) + +#define AM_HAL_IOM_SC_CLEAR(flag) ((flag) << 16) +#define AM_HAL_IOM_SC_SET(flag) ((flag)) + +// For IOM - Need to Clear the flag for unpausing +#define AM_HAL_IOM_SC_UNPAUSE(flag) AM_HAL_IOM_SC_CLEAR(flag) +#define AM_HAL_IOM_SC_PAUSE(flag) AM_HAL_IOM_SC_SET(flag) + +// Use this macro to directly control the flags +#define AM_HAL_IOM_SETCLR(iom, scVal) \ + do { \ + IOMn((iom))->CQSETCLEAR = (scVal); \ + } while (0); + +// Flags 5, 7 & 6 are reserved by HAL +#define AM_HAL_IOM_PAUSE_FLAG_RESV (IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7 | IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6 | IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5) +#define AM_HAL_IOM_SC_RESV_MASK (AM_HAL_IOM_PAUSE_FLAG_RESV | (AM_HAL_IOM_PAUSE_FLAG_RESV << 8) | (AM_HAL_IOM_PAUSE_FLAG_RESV << 16)) + + +// We use SWFLAGEN7 to control SW pausing Command Queue - default unPause +// We use SWFLAGEN6 to pause on the sequece loopback - default Pause +#define AM_HAL_IOM_PAUSE_FLAG_IDX (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_IDXEQ)) +#define AM_HAL_IOM_PAUSE_FLAG_CQ (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7)) +#define AM_HAL_IOM_PAUSE_FLAG_SEQLOOP (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6)) +#define AM_HAL_IOM_PAUSE_FLAG_BLOCK (_VAL2FLD(IOM0_CQPAUSEEN_CQPEN, IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5)) + +// By default - we Pause CQ for no more entries, or force pause from SW +#define AM_HAL_IOM_PAUSE_DEFAULT AM_HAL_IOM_PAUSE_FLAG_IDX +#define AM_HAL_IOM_CQP_PAUSE_DEFAULT (AM_HAL_IOM_PAUSE_FLAG_IDX | AM_HAL_IOM_PAUSE_FLAG_CQ) + +//***************************************************************************** +// +// IOM Specific status codes +// +//***************************************************************************** +typedef enum +{ + // Error in hardware command issued or illegal access by SW + AM_HAL_IOM_ERR_INVALID_OPER = AM_HAL_STATUS_MODULE_SPECIFIC_START, + // Loss of I2C multi-master arbitration + AM_HAL_IOM_ERR_I2C_ARB, + // I2C NAK + AM_HAL_IOM_ERR_I2C_NAK, +} am_hal_iom_err_e; + +//***************************************************************************** +// +// General defines +// +//***************************************************************************** +#define AM_HAL_IOM_FIFO_SIZE_MAX 32 +#define AM_HAL_IOM_MAX_OFFSETSIZE 3 +#define AM_HAL_IOM_MAX_TXNSIZE_SPI 4095 +#define AM_HAL_IOM_MAX_TXNSIZE_I2C 4095 +#define AM_HAL_IOM_MAX_CS_SPI 3 + +//***************************************************************************** +// +//! @brief enumeration types for the IOM. +// +//***************************************************************************** + +// +// IOM mode enumerations +// +typedef enum +{ + AM_HAL_IOM_SPI_MODE, + AM_HAL_IOM_I2C_MODE, + AM_HAL_IOM_NUM_MODES +} am_hal_iom_mode_e; + +// +// Transmit or receive enumerations. +// Make these enums consistent with the IOM CMD register values. +// +typedef enum +{ + AM_HAL_IOM_TX, + AM_HAL_IOM_RX, + AM_HAL_IOM_FULLDUPLEX, +} am_hal_iom_dir_e; + +// +// Enumerate the SPI modes. Note that these are arranged per the ordering of +// SPHA (bit1) and SPOL (bit0) in the IOM.MSPICFG register. +// +typedef enum +{ + AM_HAL_IOM_SPI_MODE_0, // CPOL = 0; CPHA = 0 + AM_HAL_IOM_SPI_MODE_2, // CPOL = 1; CPHA = 0 + AM_HAL_IOM_SPI_MODE_1, // CPOL = 0; CPHA = 1 + AM_HAL_IOM_SPI_MODE_3, // CPOL = 1; CPHA = 1 +} am_hal_iom_spi_mode_e; + + +//***************************************************************************** +// +//! @brief Transfer callback function prototype +// +//***************************************************************************** +typedef void (*am_hal_iom_callback_t)(void *pCallbackCtxt, uint32_t transactionStatus); +// +//***************************************************************************** +// +//! @brief Configuration structure for the IOM. +// +//***************************************************************************** +typedef struct +{ + // + //! Select the interface mode, SPI or I2C + // + am_hal_iom_mode_e eInterfaceMode; + + // + //! Select the interface clock frequency + // + uint32_t ui32ClockFreq; + + // + //! Select the SPI clock mode (polarity/phase). Ignored for I2C operation. + // + am_hal_iom_spi_mode_e eSpiMode; + + // + // Non-Blocking transaction memory configuration + // Set length and pointer to Transfer Control Buffer. + // Length is in 4 byte multiples + // + uint32_t *pNBTxnBuf; + uint32_t ui32NBTxnBufLength; +} +am_hal_iom_config_t; + +//***************************************************************************** +// +//! Configuration structure for an individual SPI device. +// +//***************************************************************************** +typedef struct +{ + // + //! IOM module to use for communicating with this device. + // + uint32_t ui32Module; + + // + //! Chip select signal that should be used for this device. + // + uint32_t ui32ChipSelect; + + // + //! Additional options that will ALWAYS be ORed into the command word. + // + uint32_t ui32Options; +} +am_hal_iom_spi_device_t; + +//***************************************************************************** +// +//! Configuration structure for an individual I2C device. +// +//***************************************************************************** +typedef struct +{ + // + //! IOM module to use for communicating with this device. + // + uint32_t ui32Module; + + // + //! I2C address associated with this device. + // + uint32_t ui32BusAddress; + + // + //! Additional options that will ALWAYS be ORed into the command word. + // + uint32_t ui32Options; +} +am_hal_iom_i2c_device_t; + +//***************************************************************************** +// +//! @brief Status structure for the IOM. +// +//***************************************************************************** +typedef struct +{ + // + // IOM status. + // + bool bStatIdle; + bool bStatCmdAct; + bool bStatErr; + + //! + //! DMA status + //! One of: + //! AM_HAL_IOM_STATUS_DMA_IN_PROGRESS + //! AM_HAL_IOM_STATUS_XFER_COMPLETE + //! AM_HAL_IOM_STATUS_DMAERR + //! + uint32_t ui32DmaStat; + + uint32_t ui32MaxTransactions; + uint32_t ui32NumPendTransactions; +} +am_hal_iom_status_t; + +// +// transfer structure +// +typedef struct +{ + union + { + // + //! Chip enable (chip select) for this transaction on this device. + // + uint32_t ui32SpiChipSelect; + uint32_t ui32I2CDevAddr; + } uPeerInfo; + + // + //! Instruction length (0,1,2, or 3). + // + uint32_t ui32InstrLen; + + // + //! Device Instruction (aka Command). Often used as the offset. + // + uint32_t ui32Instr; + + // + //! Number of bytes to transfer + // + uint32_t ui32NumBytes; + + // + //! Transfer Direction (Transmit/Receive) + // + am_hal_iom_dir_e eDirection; + + // + //! Buffer + // + uint32_t *pui32TxBuffer; + uint32_t *pui32RxBuffer; + + // + // Continue - holds the SPI or I2C bus for multiple transactions. + // + bool bContinue; + + // + // Repeat Count + // + uint8_t ui8RepeatCount; + + // + //! DMA: Priority 0 = Low (best effort); 1 = High (service immediately) + // + uint8_t ui8Priority; + + //! Command Queue Advanced control on gating conditions for transaction to start + // + uint32_t ui32PauseCondition; + //! Command Queue Advanced Post-Transaction status setting + uint32_t ui32StatusSetClr; + +} am_hal_iom_transfer_t; + +typedef struct +{ + bool bLoop; + //! Command Queue Transaction Gating + uint32_t ui32PauseCondition; + //! Command Queue Post-Transaction status setting + uint32_t ui32StatusSetClr; +} am_hal_iom_seq_end_t; + +typedef struct +{ + uint8_t *pBuf; // Buffer provided to store the high priority transaction context + uint32_t size; // Size of buffer in bytes +} am_hal_iom_hiprio_cfg_t; + +#define AM_HAL_IOM_DCX_INVALID 0xFF +typedef struct +{ + uint8_t cs; // CS for which this configuration applies + uint8_t dcx; // alternate CS line used for DCX - AM_HAL_IOM_DCX_INVALID indicates DCX is not used +} am_hal_iom_dcx_cfg_t; + +typedef struct +{ + //! Command Queue Advanced control on gating conditions for transaction to start + uint32_t ui32PauseCondition; + //! Command Queue Advanced Post-Transaction status setting + uint32_t ui32StatusSetClr; + am_hal_cmdq_entry_t *pCQEntry; + uint32_t numEntries; + am_hal_iom_callback_t pfnCallback; + void *pCallbackCtxt; + uint32_t *pJmpAddr; +} am_hal_iom_cq_raw_t; + +typedef enum +{ + // Used to set/clear 8 CQ Pause flags - reserved flags are defined as AM_HAL_IOM_PAUSE_FLAG_RESV + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_FLAG_SETCLR = 0, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_LSB, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_FULLDUPLEX, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_RDTHRESH, + // Pass uint32_t as pArgs + AM_HAL_IOM_REQ_SPI_WRTHRESH, + // Pause the CQ gracefully + // pArgs N/A + AM_HAL_IOM_REQ_PAUSE, + // Unpause the CQ + // pArgs N/A + AM_HAL_IOM_REQ_UNPAUSE, + // Get in and out of Sequence Mode - which allows building a sequence, which either runs once, or repeats + // Pass in bool as pArgs - true/false + AM_HAL_IOM_REQ_SET_SEQMODE, + // pArgs N/A + AM_HAL_IOM_REQ_SEQ_END, + // Initialize configuration for high priority trasactions + // These transactions take precedence over existing CQ transactions + // Pass am_hal_iom_hiprio_cfg_t * as pArgs + AM_HAL_IOM_REQ_INIT_HIPRIO, + // Create a block of transactions which are not paused in between + // pArgs N/A + AM_HAL_IOM_REQ_START_BLOCK, + // pArgs N/A + AM_HAL_IOM_REQ_END_BLOCK, + // Control the DCX line + // Pass am_hal_iom_dcx_cfg_t * as pArgs + AM_HAL_IOM_REQ_SET_DCX, + // Raw CQ transaction + // Pass am_hal_iom_cq_raw_t * as pArgs + AM_HAL_IOM_REQ_CQ_RAW, + AM_HAL_IOM_REQ_MAX +} am_hal_iom_request_e; + +#define am_hal_iom_buffer(A) \ +union \ +{ \ + uint32_t words[(A + 3) >> 2]; \ + uint8_t bytes[A]; \ +} + +//***************************************************************************** +// +//! @name IOM Clock Frequencies +//! @brief Macro definitions for common SPI and I2C clock frequencies. +//! +//! These macros may be used with the ui32ClockFrequency member of the +//! am_hal_iom_config_t structure to set the clock frequency of the serial +//! interfaces. +//! +//! This list of frequencies is not exhaustive by any means. If your desired +//! frequency is not in this list, simply set ui32ClockFrequency to the +//! desired frequency (in Hz) when calling am_hal_iom_config(). +// +//***************************************************************************** +#define AM_HAL_IOM_48MHZ 48000000 +#define AM_HAL_IOM_24MHZ 24000000 +#define AM_HAL_IOM_16MHZ 16000000 +#define AM_HAL_IOM_12MHZ 12000000 +#define AM_HAL_IOM_8MHZ 8000000 +#define AM_HAL_IOM_6MHZ 6000000 +#define AM_HAL_IOM_4MHZ 4000000 +#define AM_HAL_IOM_3MHZ 3000000 +#define AM_HAL_IOM_2MHZ 2000000 +#define AM_HAL_IOM_1_5MHZ 1500000 +#define AM_HAL_IOM_1MHZ 1000000 +#define AM_HAL_IOM_750KHZ 750000 +#define AM_HAL_IOM_500KHZ 500000 +#define AM_HAL_IOM_400KHZ 400000 +#define AM_HAL_IOM_375KHZ 375000 +#define AM_HAL_IOM_250KHZ 250000 +#define AM_HAL_IOM_125KHZ 125000 +#define AM_HAL_IOM_100KHZ 100000 +#define AM_HAL_IOM_50KHZ 50000 +#define AM_HAL_IOM_10KHZ 10000 + +// Max Frequency supported in HAL +#define AM_HAL_IOM_MAX_FREQ AM_HAL_IOM_48MHZ + +//***************************************************************************** +// +// IOM Interrupts +// +//***************************************************************************** +#define AM_HAL_IOM_INT_CQERR IOM0_INTEN_CQERR_Msk // Error during command queue operations +#define AM_HAL_IOM_INT_CQUPD IOM0_INTEN_CQUPD_Msk // Command queue operation performed a register write with the register address bit 0 set to 1. +#define AM_HAL_IOM_INT_CQPAUSED IOM0_INTEN_CQPAUSED_Msk // Command queue operation paused +#define AM_HAL_IOM_INT_DERR IOM0_INTEN_DERR_Msk // DMA error received +#define AM_HAL_IOM_INT_DCMP IOM0_INTEN_DCMP_Msk // DMA transfer complete +#define AM_HAL_IOM_INT_ARB IOM0_INTEN_ARB_Msk // Arbitration loss +#define AM_HAL_IOM_INT_STOP IOM0_INTEN_STOP_Msk // STOP command +#define AM_HAL_IOM_INT_START IOM0_INTEN_START_Msk // START command +#define AM_HAL_IOM_INT_ICMD IOM0_INTEN_ICMD_Msk // ILLEGAL command +#define AM_HAL_IOM_INT_IACC IOM0_INTEN_IACC_Msk // Illegal FIFO access +#define AM_HAL_IOM_INT_NAK IOM0_INTEN_NAK_Msk // I2C NAK +#define AM_HAL_IOM_INT_FOVFL IOM0_INTEN_FOVFL_Msk // Write FIFO overflow +#define AM_HAL_IOM_INT_FUNDFL IOM0_INTEN_FUNDFL_Msk // Read FIFO underflow +#define AM_HAL_IOM_INT_THR IOM0_INTEN_THR_Msk // FIFO threshold interrupt +#define AM_HAL_IOM_INT_CMDCMP IOM0_INTEN_CMDCMP_Msk // Command complete + + +#define AM_HAL_IOM_INT_SWERR (AM_HAL_IOM_INT_ICMD | AM_HAL_IOM_INT_IACC | AM_HAL_IOM_INT_FOVFL | AM_HAL_IOM_INT_FUNDFL) +#define AM_HAL_IOM_INT_I2CARBERR (AM_HAL_IOM_INT_ARB) +#define AM_HAL_IOM_INT_INTERR (AM_HAL_IOM_INT_CQERR | AM_HAL_IOM_INT_DERR) +#define AM_HAL_IOM_INT_ALL 0xFFFFFFFF +// +// Unsuccessful end of a transaction results in one more more of the following +// +#define AM_HAL_IOM_INT_ERR (AM_HAL_IOM_INT_SWERR | AM_HAL_IOM_INT_I2CARBERR | AM_HAL_IOM_INT_INTERR | AM_HAL_IOM_INT_NAK) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief IOM initialization function +//! +//! @param ui32Module - module instance. +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a module instance, allocates the interface and then +//! returns a handle to be used by the remaining interface functions. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief IOM configuration function +//! +//! @param handle - handle for the IOM. +//! @param pConfig - pointer to the IOM specific configuration. +//! +//! This function configures the interface settings for the IO Master. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_configure(void *pHandle, am_hal_iom_config_t *psConfig); + +//***************************************************************************** +// +//! @brief IOM enable function +//! +//! @param handle - handle for the interface. +//! +//! This function enables the IOM for operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_enable(void *pHandle); + +//***************************************************************************** +// +//! @brief IOM disable function +//! +//! @param handle - handle for the interface. +//! +//! This function disables the IOMaster from operation. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_disable(void *pHandle); + +//***************************************************************************** +// +//! @brief IOM control function +//! +//! @param handle - handle for the IOM. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArgs); + +//***************************************************************************** +// +//! @brief IOM status function +//! +//! @param handle - handle for the interface. +//! @param psStatus - pointer to an interface specific structure used to +//! return the status of the interface. +//! +//! This function returns the current status of the interface. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_status_get(void *pHandle, am_hal_iom_status_t *psStatus); + +//***************************************************************************** +// +//! @brief IOM enable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function enables the specific indicated interrupts. +//! +//! The following are valid enable bits, any of which can be ORed together. +//! AM_REG_IOM_INTEN_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTEN_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTEN_DERR_M // DMA error received +//! AM_REG_IOM_INTEN_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTEN_ARB_M // Arbitration loss +//! AM_REG_IOM_INTEN_STOP_M // STOP command +//! AM_REG_IOM_INTEN_START_M // START command +//! AM_REG_IOM_INTEN_ICMD // ILLEGAL command +//! AM_REG_IOM_INTEN_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTEN_NAK_M // I2C NAK +//! AM_REG_IOM_INTEN_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTEN_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTEN_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTEN_CMDCMP_M // Command complete +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_enable(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM disable interrupts function +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function disables the specified interrupts. +//! +//! @return status - generic or interface specific status. +//! +//! The following are valid disable bits, any of which can be ORed together. +//! AM_REG_IOM_INTEN_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTEN_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTEN_DERR_M // DMA error received +//! AM_REG_IOM_INTEN_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTEN_ARB_M // Arbitration loss +//! AM_REG_IOM_INTEN_STOP_M // STOP command +//! AM_REG_IOM_INTEN_START_M // START command +//! AM_REG_IOM_INTEN_ICMD // ILLEGAL command +//! AM_REG_IOM_INTEN_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTEN_NAK_M // I2C NAK +//! AM_REG_IOM_INTEN_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTEN_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTEN_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTEN_CMDCMP_M // Command complete +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_disable(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM get interrupt status +//! +//! @param handle - handle for the interface. +//! @param pui32IntStatus - pointer to a uint32_t to return the interrupt status +//! +//! This function returns the interrupt status for the given peripheral. +//! +//! The following are valid status bits. +//! AM_REG_IOM_INTSTAT_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTSTAT_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTSTAT_DERR_M // DMA error received +//! AM_REG_IOM_INTSTAT_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTSTAT_ARB_M // Arbitration loss +//! AM_REG_IOM_INTSTAT_STOP_M // STOP command +//! AM_REG_IOM_INTSTAT_START_M // START command +//! AM_REG_IOM_INTSTAT_ICMD // ILLEGAL command +//! AM_REG_IOM_INTSTAT_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTSTAT_NAK_M // I2C NAK +//! AM_REG_IOM_INTSTAT_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTSTAT_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTSTAT_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTSTAT_CMDCMP_M // Command complete +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_status_get(void *pHandle, bool bEnabledOnly, + uint32_t *pui32IntStatus); + +//***************************************************************************** +// +//! @brief IOM interrupt clear +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask. +//! +//! This function clears the interrupts for the given peripheral. +//! +//! The following are valid clear bits, any of which can be ORed together. +//! AM_REG_IOM_INTCLR_CQERR_M // Error during command queue operations +//! AM_REG_IOM_INTCLR_CQCMP_M // Command queue operation complete +//! AM_REG_IOM_INTCLR_DERR_M // DMA error received +//! AM_REG_IOM_INTCLR_DCMP_M // DMA transfer complete +//! AM_REG_IOM_INTCLR_ARB_M // Arbitration loss +//! AM_REG_IOM_INTCLR_STOP_M // STOP command +//! AM_REG_IOM_INTCLR_START_M // START command +//! AM_REG_IOM_INTCLR_ICMD // ILLEGAL command +//! AM_REG_IOM_INTCLR_IACC_M // Illegal FIFO access +//! AM_REG_IOM_INTCLR_NAK_M // I2C NAK +//! AM_REG_IOM_INTCLR_FOVFL_M // Write FIFO overflow +//! AM_REG_IOM_INTCLR_FUNDFL_M // Read FIFO underflow +//! AM_REG_IOM_INTCLR_THR_M // FIFO threshold interrupt +//! AM_REG_IOM_INTCLR_CMDCMP_M // Command complete +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_clear(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM interrupt service routine +//! +//! @param handle - handle for the interface. +//! @param ui32IntMask - interface specific interrupt mask indicating +//! interrupts to be serviced +//! +//! This function is designed to be called from within the user defined ISR +//! (am_iom_isr) in order to service the non-blocking, queued, or DMA processing +//! for a given module instance. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_interrupt_service(void *pHandle, uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief IOM power control function +//! +//! @param handle - handle for the interface. +//! @param ePowerState - the desired power state to move the peripheral to. +//! @param retainState - flag (if true) to save/restore perhipheral state upon +//! power state change. +//! +//! This function updates the peripheral to a given power state. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_power_ctrl(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool retainState); + +//***************************************************************************** +// +//! @brief IOM blocking transfer function +//! +//! @param handle - handle for the interface. +//! @param pTransaction - pointer to the transaction control structure. +//! +//! This function performs a transaction on the IOM in PIO mode. It handles +//! half duplex transactions only (TX or RX). +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_blocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction); + +//***************************************************************************** +// +//! @brief IOM non-blocking transfer function +//! +//! @param handle - handle for the interface. +//! @param pTransaction - pointer to the uniform transaction control structure. +//! @param pfnCallback - pointer the callback function to be executed when +//! transaction is complete can be set to NULL). +//! @param pCallbackCtxt- context registered which is passed on to the callback +//! function +//! +//! This function performs a transaction on the interface. It handles both full +//! and half duplex transactions. The callback is executed when the transaction +//! is complete. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_iom_nonblocking_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt); + +//***************************************************************************** +// +//! @brief IOM uninitialize function +//! +//! @param handle - returns the handle for the module instance. +//! +//! This function accepts a handle to the initialized interface and returns +//! the peripheral instance to a known uninitialized state. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +// +// Uninitialize the interface and return the handle to a known state. +// +extern uint32_t am_hal_iom_uninitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Perform a Full Duplex transaction. +//! +//! @param handle - handle for the interface. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +uint32_t +am_hal_iom_spi_blocking_fullduplex(void *pHandle, + am_hal_iom_transfer_t *psTransaction); +// +// IOM High Priority transfer function +// +uint32_t am_hal_iom_highprio_transfer(void *pHandle, + am_hal_iom_transfer_t *psTransaction, + am_hal_iom_callback_t pfnCallback, + void *pCallbackCtxt); + + +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** +#endif // AM_HAL_IOM_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.c new file mode 100644 index 0000000000..35bea247c4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.c @@ -0,0 +1,1151 @@ +//***************************************************************************** +// +// am_hal_ios.c +//! @file +//! +//! @brief Functions for interfacing with the IO Slave module +//! +//! @addtogroup ios3 IO Slave (SPI/I2C) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +#define AM_HAL_IOS_MAX_SW_FIFO_SIZE 1023 +#define AM_HAL_MAGIC_IOS 0x123456 +#define AM_HAL_IOS_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_IOS)) + +//***************************************************************************** +// +// SRAM Buffer structure +// +//***************************************************************************** +am_hal_ios_buffer_t g_sSRAMBuffer; + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** +typedef struct +{ + bool bValid; + uint32_t regFIFOCFG; + uint32_t regFIFOTHR; + uint32_t regCFG; + uint32_t regINTEN; + uint32_t regACCINTEN; +} am_hal_ios_register_state_t; + +typedef struct +{ + am_hal_handle_prefix_t prefix; + // + // Physical module number. + // + uint32_t ui32Module; + + am_hal_ios_register_state_t registerState; + + uint8_t *pui8FIFOBase; + uint8_t *pui8FIFOEnd; + uint8_t *pui8FIFOPtr; + uint8_t ui32HwFifoSize; + uint32_t ui32FifoBaseOffset; +} am_hal_ios_state_t; + +//***************************************************************************** +// +// Forward declarations of static funcitons. +// +//***************************************************************************** +static void am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, + void *pvArray, uint32_t ui32Bytes); +static void fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes); +static uint32_t am_hal_ios_fifo_ptr_set(void *pHandle, uint32_t ui32Offset); +//***************************************************************************** +// +// Function-like macros. +// +//***************************************************************************** +#define am_hal_ios_buffer_empty(psBuffer) \ + ((psBuffer)->ui32Length == 0) + +#define am_hal_ios_buffer_full(psBuffer) \ + ((psBuffer)->ui32Length == (psBuffer)->ui32Capacity) + +#define am_hal_ios_buffer_data_left(psBuffer) \ + ((psBuffer)->ui32Length) + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** +volatile uint8_t * const am_hal_ios_pui8LRAM = (uint8_t *)REG_IOSLAVE_BASEADDR; + +am_hal_ios_state_t g_IOShandles[AM_REG_IOSLAVE_NUM_MODULES]; + +//***************************************************************************** +// +// IOS power control function +// +//***************************************************************************** +uint32_t am_hal_ios_power_ctrl(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOS_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update IOS operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + if (bRetainState && !pIOSState->registerState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOS + pIOSState->ui32Module)); + + if (bRetainState) + { + // + // Restore IOS registers + IOSLAVEn(pIOSState->ui32Module)->FIFOCFG = pIOSState->registerState.regFIFOCFG; + IOSLAVEn(pIOSState->ui32Module)->FIFOTHR = pIOSState->registerState.regFIFOTHR; + IOSLAVEn(pIOSState->ui32Module)->CFG = pIOSState->registerState.regCFG; + IOSLAVEn(pIOSState->ui32Module)->INTEN = pIOSState->registerState.regINTEN; + IOSLAVEn(pIOSState->ui32Module)->REGACCINTEN = pIOSState->registerState.regACCINTEN; + + pIOSState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if (bRetainState) + { + // Save IOS Registers + pIOSState->registerState.regFIFOCFG = IOSLAVEn(pIOSState->ui32Module)->FIFOCFG; + pIOSState->registerState.regFIFOTHR = IOSLAVEn(pIOSState->ui32Module)->FIFOTHR; + pIOSState->registerState.regCFG = IOSLAVEn(pIOSState->ui32Module)->CFG; + pIOSState->registerState.regINTEN = IOSLAVEn(pIOSState->ui32Module)->INTEN; + pIOSState->registerState.regACCINTEN = IOSLAVEn(pIOSState->ui32Module)->REGACCINTEN; + pIOSState->registerState.bValid = true; + } + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_IOS + pIOSState->ui32Module)); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_power_ctrl() + +//***************************************************************************** +// +// IOS uninitialize function +// +//***************************************************************************** +uint32_t am_hal_ios_uninitialize(void *pHandle) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (pIOSState->prefix.s.bEnable) + { + am_hal_ios_disable(pHandle); + } + + pIOSState->prefix.s.bInit = false; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_uninitialize() + + +//***************************************************************************** +// +// IOS initialization function +// +//***************************************************************************** +uint32_t am_hal_ios_initialize(uint32_t ui32Module, void **ppHandle) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Validate the module number + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if (ppHandle == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + if (g_IOShandles[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + g_IOShandles[ui32Module].prefix.s.bInit = true; + g_IOShandles[ui32Module].prefix.s.bEnable = false; + g_IOShandles[ui32Module].prefix.s.magic = AM_HAL_MAGIC_IOS; + + // + // Initialize the handle. + // + g_IOShandles[ui32Module].ui32Module = ui32Module; + + // + // Return the handle. + // + *ppHandle = (void *)&g_IOShandles[ui32Module]; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_initialize() + +//***************************************************************************** +// +// IOS enable function +// +//***************************************************************************** +uint32_t am_hal_ios_enable(void *pHandle) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if (pIOSState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + IOSLAVEn(pIOSState->ui32Module)->CFG |= _VAL2FLD(IOSLAVE_CFG_IFCEN, 1); + + pIOSState->prefix.s.bEnable = true; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_enable() + +//***************************************************************************** +// +// IOS disable function +// +//***************************************************************************** +uint32_t am_hal_ios_disable(void *pHandle) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pIOSState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + + IOSLAVEn(pIOSState->ui32Module)->CFG &= ~(_VAL2FLD(IOSLAVE_CFG_IFCEN, 1)); + + pIOSState->prefix.s.bEnable = false; + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_ios_disable() + +//***************************************************************************** +// +// IOS configuration function. +// +//***************************************************************************** +uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig) +{ + uint32_t ui32LRAMConfig = 0; + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ( (psConfig == NULL) || + (pIOSState->ui32Module >= AM_REG_IOSLAVE_NUM_MODULES) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // Configure not allowed in Enabled state + if (pIOSState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pIOSState->ui32Module; + + am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_IOS); + + // + // Record the FIFO parameters for later use. + // + pIOSState->pui8FIFOBase = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32FIFOBase); + pIOSState->pui8FIFOEnd = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32RAMBase); + pIOSState->ui32HwFifoSize = pIOSState->pui8FIFOEnd - pIOSState->pui8FIFOBase; + pIOSState->ui32FifoBaseOffset = psConfig->ui32FIFOBase; + + // + // Initialize the global SRAM buffer + // Total size, which is SRAM Buffer plus the hardware FIFO needs to be + // limited to 1023 + // + if ( psConfig->ui32SRAMBufferCap > (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1) ) + { + psConfig->ui32SRAMBufferCap = (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1); + } + am_hal_ios_buffer_init(&g_sSRAMBuffer, psConfig->pui8SRAMBuffer, psConfig->ui32SRAMBufferCap); + + // + // Calculate the value for the IO Slave FIFO configuration register. + // + ui32LRAMConfig = _VAL2FLD(IOSLAVE_FIFOCFG_ROBASE, psConfig->ui32ROBase >> 3); + ui32LRAMConfig |= _VAL2FLD(IOSLAVE_FIFOCFG_FIFOBASE, psConfig->ui32FIFOBase >> 3); + ui32LRAMConfig |= _VAL2FLD(IOSLAVE_FIFOCFG_FIFOMAX, psConfig->ui32RAMBase >> 3); + + // + // Just in case, disable the IOS + // + am_hal_ios_disable(pHandle); + + // + // Write the configuration register with the user's selected interface + // characteristics. + // + IOSLAVEn(ui32Module)->CFG = psConfig->ui32InterfaceSelect; + + // + // Write the FIFO configuration register to set the memory map for the LRAM. + // + IOSLAVEn(ui32Module)->FIFOCFG = ui32LRAMConfig; + + // + // Clear the FIFO State + // + IOSLAVEn(pIOSState->ui32Module)->FIFOCTR_b.FIFOCTR = 0x0; + IOSLAVEn(pIOSState->ui32Module)->FIFOPTR_b.FIFOSIZ = 0x0; + am_hal_ios_fifo_ptr_set(pHandle, pIOSState->ui32FifoBaseOffset); + + // + // Enable the IOS. The following configuration options can't be set while + // the IOS is disabled. + // + am_hal_ios_enable(pHandle); + + // + // Initialize the FIFO pointer to the beginning of the FIFO section. + // + am_hal_ios_fifo_ptr_set(pHandle, psConfig->ui32FIFOBase); + + // + // Write the FIFO threshold register. + // + IOSLAVEn(ui32Module)->FIFOTHR = psConfig->ui32FIFOThreshold; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_config() + +//***************************************************************************** +// +// IOS enable interrupts function +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // OR the desired interrupt into the enable register. + // + IOSLAVEn(ui32Module)->INTEN |= ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_enable() + +//***************************************************************************** +// +// IOS disable interrupts function +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Clear the desired bit from the interrupt enable register. + // + IOSLAVEn(ui32Module)->INTEN &= ~(ui32IntMask); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_disable() + +//***************************************************************************** +// +// IOS interrupt clear +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Use the interrupt clear register to deactivate the chosen interrupt. + // + IOSLAVEn(ui32Module)->INTCLR = ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_clear() + +//***************************************************************************** +// +// IOS get interrupt status +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_status_get(void *pHandle, bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + uint32_t ui32IntStatus = 0; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_IOS_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( !pui32IntStatus ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + ui32IntStatus = IOSLAVEn(ui32Module)->INTSTAT; + + if ( bEnabledOnly ) + { + ui32IntStatus &= IOSLAVEn(ui32Module)->INTEN; + } + + *pui32IntStatus = ui32IntStatus; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_int_status_get() + +//***************************************************************************** +// +//! @brief Check the amount of space used in the FIFO +//! +//! @param pui32UsedSpace is bytes used in the Overall FIFO. +//! +//! This function returns the available data in the overall FIFO yet to be +//! read by the host. This takes into account the SRAM buffer and hardware FIFO +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_fifo_space_used(void *pHandle, uint32_t *pui32UsedSpace) +{ + uint32_t ui32Module; + uint32_t ui32Val = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui32UsedSpace ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + ui32Val = g_sSRAMBuffer.ui32Length; + ui32Val += IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ; + + // + // End the critical section + // + AM_CRITICAL_END + + *pui32UsedSpace = ui32Val; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_space_used() + +//***************************************************************************** +// +//! @brief Check the amount of space left in the FIFO +//! +//! @param pui32LeftSpace is bytes left in the Overall FIFO. +//! +//! This function returns the available space in the overall FIFO to accept +//! new data. This takes into account the SRAM buffer and hardware FIFO +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace) +{ + uint32_t ui32Module; + uint32_t ui32Val = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui32LeftSpace ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + // + // We waste one byte in HW FIFO + // + ui32Val = g_sSRAMBuffer.ui32Capacity + ((am_hal_ios_state_t*)pHandle)->ui32HwFifoSize - 1; + ui32Val -= g_sSRAMBuffer.ui32Length; + ui32Val -= IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ; + + // + // End the critical section + // + AM_CRITICAL_END + + *pui32LeftSpace = ui32Val; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_space_left() + +//***************************************************************************** +// +//! @brief Check the amount of space left in the hardware FIFO +//! +//! @param pui32LeftSpace is bytes left in the IOS FIFO. +//! +//! This function reads the IOSLAVE FIFOPTR register and determines the amount +//! of space left in the IOS LRAM FIFO. +//! +//! @return success or error code +// +//***************************************************************************** +static uint32_t fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui32LeftSpace ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // We waste one byte in HW FIFO + // + *pui32LeftSpace = ((uint32_t)((am_hal_ios_state_t*)pHandle)->ui32HwFifoSize - IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ - 1); + + return AM_HAL_STATUS_SUCCESS; +} // fifo_space_left() + +//***************************************************************************** +// +// Helper function for managing IOS FIFO writes. +// +//***************************************************************************** +static void fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + uint8_t *pFifoPtr = pIOSState->pui8FIFOPtr; + uint8_t *pFifoBase = pIOSState->pui8FIFOBase; + uint8_t *pFifoEnd = pIOSState->pui8FIFOEnd; + + while ( ui32NumBytes ) + { + // + // Write the data to the FIFO + // + *pFifoPtr++ = *pui8Data++; + ui32NumBytes--; + + // + // Make sure to wrap the FIFO pointer if necessary. + // + if ( pFifoPtr == pFifoEnd ) + { + pFifoPtr = pFifoBase; + } + } + pIOSState->pui8FIFOPtr = pFifoPtr; +} // fifo_write() + +//***************************************************************************** +// +// IOS interrupt service routine +// +//***************************************************************************** +uint32_t am_hal_ios_interrupt_service(void *pHandle, uint32_t ui32IntMask) +{ + uint32_t thresh; + uint32_t freeSpace, usedSpace, chunk1, chunk2, ui32WriteIndex; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Check for FIFO size interrupts. + // + if ( ui32IntMask & AM_HAL_IOS_INT_FSIZE ) + { + thresh = IOSLAVEn(ui32Module)->FIFOTHR_b.FIFOTHR; + + // + // While the FIFO is at or below threshold Add more data + // If Fifo level is above threshold, we're guaranteed an FSIZ interrupt + // + while ( g_sSRAMBuffer.ui32Length && + ((usedSpace = IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ) <= thresh) ) + { + // + // So, we do have some data in SRAM which needs to be moved to FIFO. + // A chunk of data is a continguous set of bytes in SRAM that can be + // written to FIFO. Determine the chunks of data from SRAM that can + // be written. Up to two chunks possible + // + ui32WriteIndex = g_sSRAMBuffer.ui32WriteIndex; + chunk1 = ((ui32WriteIndex > (uint32_t)g_sSRAMBuffer.ui32ReadIndex) ? \ + (ui32WriteIndex - (uint32_t)g_sSRAMBuffer.ui32ReadIndex) : \ + (g_sSRAMBuffer.ui32Capacity - (uint32_t)g_sSRAMBuffer.ui32ReadIndex)); + chunk2 = g_sSRAMBuffer.ui32Length - chunk1; + // We waste one byte in HW FIFO + freeSpace = ((am_hal_ios_state_t*)pHandle)->ui32HwFifoSize - usedSpace - 1; + // Write data in chunks + // Determine the chunks of data from SRAM that can be written + if ( chunk1 > freeSpace ) + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace); + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += freeSpace; + // No need to check for wrap as we wrote less than chunk1 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= freeSpace; + } + else + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk1); + + // + // Update the read index - wrapping as needed + // + g_sSRAMBuffer.ui32ReadIndex += chunk1; + g_sSRAMBuffer.ui32ReadIndex %= g_sSRAMBuffer.ui32Capacity; + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= chunk1; + freeSpace -= chunk1; + + if ( freeSpace && chunk2 ) + { + if ( chunk2 > freeSpace ) + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), freeSpace); + + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += freeSpace; + + // No need to check for wrap in chunk2 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= freeSpace; + } + else + { + fifo_write(pHandle, (uint8_t *)(g_sSRAMBuffer.pui8Data + g_sSRAMBuffer.ui32ReadIndex), chunk2); + // + // Advance the read index, wrapping if needed. + // + g_sSRAMBuffer.ui32ReadIndex += chunk2; + + // No need to check for wrap in chunk2 + // + // Adjust the length value to reflect the change. + // + g_sSRAMBuffer.ui32Length -= chunk2; + } + } + } + + // + // Need to retake the FIFO space, after Threshold interrupt has been reenabled + // Clear any spurious FSIZE interrupt that might have got raised + // + IOSLAVEn(ui32Module)->INTCLR_b.FSIZE = 1; + } + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_service() + +//***************************************************************************** +// +//! @brief Writes the specified number of bytes to the IOS fifo. +//! +//! @param pui8Data is a pointer to the data to be written to the fifo. +//! @param ui32NumBytes is the number of bytes to send. +//! @param pui32WrittenBytes is number of bytes written (could be less than ui32NumBytes, if not enough space) +//! +//! This function will write data from the caller-provided array to the IOS +//! LRAM FIFO. If there is no space in the LRAM FIFO, the data will be copied +//! to a temporary SRAM buffer instead. +//! +//! The maximum message size for the IO Slave is 1023 bytes. +//! +//! @note In order for SRAM copy operations in the function to work correctly, +//! the \e am_hal_ios_buffer_service() function must be called in the ISR for +//! the ioslave module. +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32WrittenBytes) +{ + uint32_t ui32FIFOSpace = 0; + uint32_t ui32SRAMSpace; + uint32_t ui32SRAMLength; + uint32_t totalBytes = ui32NumBytes; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if ( !pui8Data || !pui32WrittenBytes) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // This operation will only work properly if an SRAM buffer has been + // allocated. Make sure that am_hal_ios_fifo_buffer_init() has been called, + // and the buffer pointer looks valid. + // + am_hal_debug_assert(g_sSRAMBuffer.pui8Data != 0); + + if ( ui32NumBytes == 0 ) + { + *pui32WrittenBytes = 0; + } + else + { + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + ui32SRAMLength = g_sSRAMBuffer.ui32Length; + + // + // End the critical section + // + AM_CRITICAL_END + + // + // If the SRAM buffer is empty, we should just write directly to the FIFO. + // + if ( ui32SRAMLength == 0 ) + { + fifo_space_left(pHandle, &ui32FIFOSpace); + + // + // If the whole message fits, send it now. + // + if ( ui32NumBytes <= ui32FIFOSpace ) + { + fifo_write(pHandle, pui8Data, ui32NumBytes); + ui32NumBytes = 0; + } + else + { + fifo_write(pHandle, pui8Data, ui32FIFOSpace); + ui32NumBytes -= ui32FIFOSpace; + pui8Data += ui32FIFOSpace; + } + } + + // + // If there's still data, write it to the SRAM buffer. + // + if ( ui32NumBytes ) + { + uint32_t idx, writeIdx, capacity, fifoSize; + ui32SRAMSpace = g_sSRAMBuffer.ui32Capacity - ui32SRAMLength; + + writeIdx = g_sSRAMBuffer.ui32WriteIndex; + capacity = g_sSRAMBuffer.ui32Capacity; + + // + // Make sure that the data will fit inside the SRAM buffer. + // + if ( ui32SRAMSpace > ui32NumBytes ) + { + ui32SRAMSpace = ui32NumBytes; + } + + // + // If the data will fit, write it to the SRAM buffer. + // + for ( idx = 0; idx < ui32SRAMSpace; idx++ ) + { + g_sSRAMBuffer.pui8Data[(idx + writeIdx) % capacity] = pui8Data[idx]; + } + + ui32NumBytes -= idx; + + // + // Start a critical section for thread safety before updating length & wrIdx. + // + AM_CRITICAL_BEGIN + + // + // Advance the write index, making sure to wrap if necessary. + // + g_sSRAMBuffer.ui32WriteIndex = (idx + writeIdx) % capacity; + + // + // Update the length value appropriately. + // + g_sSRAMBuffer.ui32Length += idx; + + // + // End the critical section + // + AM_CRITICAL_END + + // It is possible that there is a race condition that the FIFO level has + // gone below the threshold by the time we set the wrIdx above, and hence + // we may never get the threshold interrupt to serve the SRAM data we + // just wrote + + // If that is the case, explicitly generate the FSIZE interrupt from here + fifoSize = IOSLAVEn(ui32Module)->FIFOPTR_b.FIFOSIZ; + + if ( fifoSize <= IOSLAVEn(ui32Module)->FIFOTHR_b.FIFOTHR ) + { + IOSLAVEn(ui32Module)->INTSET_b.FSIZE = 1; + } + } + + *pui32WrittenBytes = totalBytes - ui32NumBytes; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_write() + +//***************************************************************************** +// +//! @brief Sets the IOS FIFO pointer to the specified LRAM offset. +//! +//! @param ui32Offset is LRAM offset to set the FIFO pointer to. +//! +//! @return success or error code +// +//***************************************************************************** +static uint32_t am_hal_ios_fifo_ptr_set(void *pHandle, uint32_t ui32Offset) +{ + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = ((am_hal_ios_state_t*)pHandle)->ui32Module; + + // + // Start a critical section for thread safety. + // + AM_CRITICAL_BEGIN + + // + // Set the FIFO Update bit. + // + IOSLAVEn(ui32Module)->FUPD = 0x1; + + // + // Change the FIFO offset. + // + IOSLAVEn(ui32Module)->FIFOPTR = ui32Offset; + + // + // Clear the FIFO update bit. + // + IOSLAVEn(ui32Module)->FUPD = 0x0; + + // + // Set the global FIFO-pointer tracking variable. + // + ((am_hal_ios_state_t*)pHandle)->pui8FIFOPtr = (uint8_t *) (REG_IOSLAVE_BASEADDR + ui32Offset); + + // + // End the critical section. + // + AM_CRITICAL_END + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_ios_fifo_ptr_set() + +//***************************************************************************** +// +// Initialize an SRAM buffer for use with the IO Slave. +// +//***************************************************************************** +static void am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, void *pvArray, + uint32_t ui32Bytes) +{ + psBuffer->ui32WriteIndex = 0; + psBuffer->ui32ReadIndex = 0; + psBuffer->ui32Length = 0; + psBuffer->ui32Capacity = ui32Bytes; + psBuffer->pui8Data = (uint8_t *)pvArray; +} // am_hal_ios_buffer_init() + +//***************************************************************************** +// +//! @brief IOS control function +//! +//! @param handle - handle for the IOS. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return success or error code +// +//***************************************************************************** +uint32_t am_hal_ios_control(void *pHandle, am_hal_ios_request_e eReq, void *pArgs) +{ + am_hal_ios_state_t *pIOSState = (am_hal_ios_state_t*)pHandle; + uint32_t ui32Val = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!AM_HAL_IOS_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ((eReq < AM_HAL_IOS_REQ_ARG_MAX) && (NULL == pArgs)) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + switch (eReq) + { + case AM_HAL_IOS_REQ_HOST_INTSET: + IOSLAVEn(pIOSState->ui32Module)->IOINTCTL = _VAL2FLD(IOSLAVE_IOINTCTL_IOINTSET, *((uint32_t *)pArgs)); + break; + case AM_HAL_IOS_REQ_HOST_INTCLR: + IOSLAVEn(pIOSState->ui32Module)->IOINTCTL = _VAL2FLD(IOSLAVE_IOINTCTL_IOINTCLR, *((uint32_t *)pArgs)); + break; + case AM_HAL_IOS_REQ_HOST_INTGET: + *((uint32_t*)pArgs) = IOSLAVEn(pIOSState->ui32Module)->IOINTCTL_b.IOINT; + break; + case AM_HAL_IOS_REQ_HOST_INTEN_GET: + *((uint32_t*)pArgs) = IOSLAVEn(pIOSState->ui32Module)->IOINTCTL_b.IOINTEN; + break; + case AM_HAL_IOS_REQ_READ_GADATA: + *((uint32_t*)pArgs) = IOSLAVEn(pIOSState->ui32Module)->GENADD_b.GADATA; + break; + case AM_HAL_IOS_REQ_READ_POLL: + while ( IOSLAVEn(pIOSState->ui32Module)->FUPD & IOSLAVE_FUPD_IOREAD_Msk ); + break; + case AM_HAL_IOS_REQ_FIFO_UPDATE_CTR: + am_hal_ios_fifo_space_used(pHandle, &ui32Val); + IOSLAVEn(pIOSState->ui32Module)->FIFOCTR_b.FIFOCTR = ui32Val; + break; + case AM_HAL_IOS_REQ_FIFO_BUF_CLR: + am_hal_ios_buffer_init(&g_sSRAMBuffer, NULL, 0); + // + // Clear the FIFO State + // + IOSLAVEn(pIOSState->ui32Module)->FIFOCTR_b.FIFOCTR = 0x0; + IOSLAVEn(pIOSState->ui32Module)->FIFOPTR_b.FIFOSIZ = 0x0; + break; + case AM_HAL_IOS_REQ_MAX: + return AM_HAL_STATUS_INVALID_ARG; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// End the doxygen group +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.h new file mode 100644 index 0000000000..b2b7ebd7e7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_ios.h @@ -0,0 +1,378 @@ +//***************************************************************************** +// +// am_hal_ios.h +//! @file +//! +//! @brief Functions for interfacing with the IO Slave module +//! +//! @addtogroup ios3 IO Slave (SPI/I2C) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_IOS_H +#define AM_HAL_IOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable IOS module number. +// +#define IOSLAVEn(n) ((IOSLAVE_Type*)(IOSLAVE_BASE + (n * (IOSLAVE_BASE - IOSLAVE_BASE)))) +//***************************************************************************** + +//***************************************************************************** +// +//! @name Interface Configuration +//! @brief Macro definitions for configuring the physical interface of the IO +//! Slave +//! +//! These macros may be used with the am_hal_ios_config_t structure to set the +//! physical parameters of the SPI/I2C slave module. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_USE_SPI _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_SPI) +#define AM_HAL_IOS_SPIMODE_0 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3) +#define AM_HAL_IOS_SPIMODE_1 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2) +#define AM_HAL_IOS_SPIMODE_2 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_1_2) +#define AM_HAL_IOS_SPIMODE_3 _VAL2FLD(IOSLAVE_CFG_SPOL, IOSLAVE_CFG_SPOL_SPI_MODES_0_3) + +#define AM_HAL_IOS_USE_I2C _VAL2FLD(IOSLAVE_CFG_IFCSEL, IOSLAVE_CFG_IFCSEL_I2C) +#define AM_HAL_IOS_I2C_ADDRESS(n) _VAL2FLD(IOSLAVE_CFG_I2CADDR, n) + +#define AM_HAL_IOS_LSB_FIRST _VAL2FLD(IOSLAVE_CFG_LSB, 1) +//! @} + +//***************************************************************************** +// +//! @name Register Access Interrupts +//! @brief Macro definitions for register access interrupts. +//! +//! These macros may be used with any of the +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_ACCESS_INT_00 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 31) +#define AM_HAL_IOS_ACCESS_INT_01 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 30) +#define AM_HAL_IOS_ACCESS_INT_02 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 29) +#define AM_HAL_IOS_ACCESS_INT_03 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 28) +#define AM_HAL_IOS_ACCESS_INT_04 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 27) +#define AM_HAL_IOS_ACCESS_INT_05 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 26) +#define AM_HAL_IOS_ACCESS_INT_06 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 25) +#define AM_HAL_IOS_ACCESS_INT_07 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 24) +#define AM_HAL_IOS_ACCESS_INT_08 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 23) +#define AM_HAL_IOS_ACCESS_INT_09 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 22) +#define AM_HAL_IOS_ACCESS_INT_0A _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 21) +#define AM_HAL_IOS_ACCESS_INT_0B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 20) +#define AM_HAL_IOS_ACCESS_INT_0C _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 19) +#define AM_HAL_IOS_ACCESS_INT_0D _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 18) +#define AM_HAL_IOS_ACCESS_INT_0E _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 17) +#define AM_HAL_IOS_ACCESS_INT_0F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 16) +#define AM_HAL_IOS_ACCESS_INT_13 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 15) +#define AM_HAL_IOS_ACCESS_INT_17 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 14) +#define AM_HAL_IOS_ACCESS_INT_1B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 13) +#define AM_HAL_IOS_ACCESS_INT_1F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 12) +#define AM_HAL_IOS_ACCESS_INT_23 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 11) +#define AM_HAL_IOS_ACCESS_INT_27 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 10) +#define AM_HAL_IOS_ACCESS_INT_2B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 9) +#define AM_HAL_IOS_ACCESS_INT_2F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 8) +#define AM_HAL_IOS_ACCESS_INT_33 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 7) +#define AM_HAL_IOS_ACCESS_INT_37 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 6) +#define AM_HAL_IOS_ACCESS_INT_3B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 5) +#define AM_HAL_IOS_ACCESS_INT_3F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 4) +#define AM_HAL_IOS_ACCESS_INT_43 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 3) +#define AM_HAL_IOS_ACCESS_INT_47 _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 2) +#define AM_HAL_IOS_ACCESS_INT_4B _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 1) +#define AM_HAL_IOS_ACCESS_INT_4F _VAL2FLD(IOSLAVE_REGACCINTEN_REGACC, (uint32_t)1 << 0) +#define AM_HAL_IOS_ACCESS_INT_ALL 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! @name I/O Slave Interrupts +//! @brief Macro definitions for I/O slave (IOS) interrupts. +//! +//! These macros may be used with any of the +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_INT_FSIZE IOSLAVE_INTEN_FSIZE_Msk +#define AM_HAL_IOS_INT_FOVFL IOSLAVE_INTEN_FOVFL_Msk +#define AM_HAL_IOS_INT_FUNDFL IOSLAVE_INTEN_FUNDFL_Msk +#define AM_HAL_IOS_INT_FRDERR IOSLAVE_INTEN_FRDERR_Msk +#define AM_HAL_IOS_INT_GENAD IOSLAVE_INTEN_GENAD_Msk +#define AM_HAL_IOS_INT_IOINTW IOSLAVE_INTEN_IOINTW_Msk +#define AM_HAL_IOS_INT_XCMPWR IOSLAVE_INTEN_XCMPWR_Msk +#define AM_HAL_IOS_INT_XCMPWF IOSLAVE_INTEN_XCMPWF_Msk +#define AM_HAL_IOS_INT_XCMPRR IOSLAVE_INTEN_XCMPRR_Msk +#define AM_HAL_IOS_INT_XCMPRF IOSLAVE_INTEN_XCMPRF_Msk +#define AM_HAL_IOS_INT_ALL 0xFFFFFFFF +//! @} + +//***************************************************************************** +// +//! @name I/O Slave Interrupts triggers +//! @brief Macro definitions for I/O slave (IOS) interrupts. +//! +//! These macros may be used with am_hal_ios_interrupt_set and am_hal_ios_interrupt_clear +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_IOS_IOINTCTL_INT0 (0x01) +#define AM_HAL_IOS_IOINTCTL_INT1 (0x02) +#define AM_HAL_IOS_IOINTCTL_INT2 (0x04) +#define AM_HAL_IOS_IOINTCTL_INT3 (0x08) +#define AM_HAL_IOS_IOINTCTL_INT4 (0x10) +#define AM_HAL_IOS_IOINTCTL_INT5 (0x20) +//! @} + +//***************************************************************************** +// +// External variable definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief LRAM pointer +//! +//! Pointer to the base of the IO Slave LRAM. +// +//***************************************************************************** +extern volatile uint8_t * const am_hal_ios_pui8LRAM; + +//***************************************************************************** +// +//! @brief Configuration structure for the IO slave module. +//! +//! This structure may be used along with the am_hal_ios_config() function to +//! select key parameters of the IO Slave module. See the descriptions of each +//! parameter within this structure for more information on what they control. +// +//***************************************************************************** +typedef struct +{ + // + //! Interface Selection + //! + //! This word selects the physical behavior of the IO Slave port. For SPI + //! mode, this word should be the logical OR of one or more of the + //! following: + //! + //! AM_HAL_IOS_USE_SPI + //! AM_HAL_IOS_SPIMODE_0 + //! AM_HAL_IOS_SPIMODE_1 + //! AM_HAL_IOS_SPIMODE_2 + //! AM_HAL_IOS_SPIMODE_3 + //! + //! For I2C mode, use the logical OR of one or more of these values instead + //! (where n is the 7 or 10-bit I2C address to use): + //! + //! AM_HAL_IOS_USE_I2C + //! AM_HAL_IOS_I2C_ADDRESS(n) + //! + //! Also, in any mode, you may OR in this value to reverse the order of + //! incoming data bits. + //! + //! AM_HAL_IOS_LSB_FIRST + // + uint32_t ui32InterfaceSelect; + + // + //! Read-Only section + //! + //! The IO Slave LRAM is split into three main sections. The first section + //! is a "Direct Write" section, which may be accessed for reads or write + //! either directly through the Apollo CPU, or over the SPI/I2C bus. The + //! "Direct Write" section always begins at LRAM offset 0x0. At the end of + //! the normal "Direct Write" space, there is a "Read Only" space, which is + //! read/write accessible to the Apollo CPU, but read-only over the I2C/SPI + //! Bus. This word selects the base address of this "Read Only" space. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x78, + //! inclusive. For the configuration to be valid, \e ui32ROBase must also + //! be less than or equal to \e ui32FIFOBase + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "Read Only" space may only be set in 8-byte increments, this + //! value must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32ROBase; + + // + //! FIFO section + //! + //! After the "Direct Access" and "Read Only" sections is a section of LRAM + //! allocated to a FIFO. This section is accessible by the Apollo CPU + //! through the FIFO control registers, and accessible on the SPI/I2C bus + //! through the 0x7F address. This word selects the base address of the + //! FIFO space. The FIFO will extend from the address specified here to the + //! address specified in \e ui32RAMBase. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x78, + //! inclusive. For the configuration to be valid, \e ui32FIFOBase must also + //! be greater than or equal to \e ui32ROBase. + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "FIFO" space may only be set in 8-byte increments, this value + //! must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32FIFOBase; + + // + //! RAM section + //! + //! At the end of the IOS LRAM, the user may allocate a "RAM" space that + //! can only be accessed by the Apollo CPU. This space will not interact + //! with the SPI/I2C bus at all, and may be used as general-purpose memory. + //! Unlike normal SRAM, this section of LRAM will retain its state through + //! Deep Sleep, so it may be used as a data retention space for + //! ultra-low-power applications. + //! + //! This value may be set to any multiple of 8 between 0x0 and 0x100, + //! inclusive. For the configuration to be valid, \e ui32RAMBase must also + //! be greater than or equal to \e ui32FIFOBase. + //! + //! @note The address given here is in units of BYTES. Since the location + //! of the "FIFO" space may only be set in 8-byte increments, this value + //! must be a multiple of 8. + //! + //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions + //! will shift right by 8 internally. + // + uint32_t ui32RAMBase; + + // + //! FIFO threshold + //! + //! The IO Slave module will trigger an interrupt when the number of + //! entries in the FIFO drops below this number of bytes. + // + uint32_t ui32FIFOThreshold; + + // + // Pointer to an SRAM + // + uint8_t *pui8SRAMBuffer; + uint32_t ui32SRAMBufferCap; +} +am_hal_ios_config_t; + +typedef enum +{ + // Request with arg + AM_HAL_IOS_REQ_HOST_INTSET = 0, + AM_HAL_IOS_REQ_HOST_INTCLR, + AM_HAL_IOS_REQ_HOST_INTGET, + AM_HAL_IOS_REQ_HOST_INTEN_GET, + AM_HAL_IOS_REQ_READ_GADATA, + AM_HAL_IOS_REQ_ARG_MAX, + + // Request without arg + AM_HAL_IOS_REQ_READ_POLL = AM_HAL_IOS_REQ_ARG_MAX, + AM_HAL_IOS_REQ_FIFO_UPDATE_CTR, + AM_HAL_IOS_REQ_FIFO_BUF_CLR, + AM_HAL_IOS_REQ_MAX +} am_hal_ios_request_e; + +typedef struct +{ + uint8_t *pui8Data; + volatile uint32_t ui32WriteIndex; + volatile uint32_t ui32ReadIndex; + volatile uint32_t ui32Length; + uint32_t ui32Capacity; +}am_hal_ios_buffer_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern uint32_t am_hal_ios_uninitialize(void *pHandle); +extern uint32_t am_hal_ios_initialize(uint32_t ui32Module, void **ppHandle); +extern uint32_t am_hal_ios_enable(void *pHandle); +extern uint32_t am_hal_ios_disable(void *pHandle); + +// the following interrupts go back to the NVIC +extern uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig); +extern uint32_t am_hal_ios_interrupt_enable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_ios_interrupt_disable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_ios_interrupt_clear(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_ios_interrupt_status_get(void *pHandle, bool bEnabledOnly, uint32_t *pui32IntStatus); +extern uint32_t am_hal_ios_interrupt_service(void *pHandle, uint32_t ui32IntMask); +// Returns the number of bytes actually written +extern uint32_t am_hal_ios_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32WrittenBytes); +extern uint32_t am_hal_ios_fifo_space_used(void *pHandle, uint32_t *pui32UsedSpace); +extern uint32_t am_hal_ios_fifo_space_left(void *pHandle, uint32_t *pui32LeftSpace); + +extern uint32_t am_hal_ios_power_ctrl(void *pHandle, am_hal_sysctrl_power_state_e ePowerState, bool bRetainState); +extern uint32_t am_hal_ios_control(void *pHandle, am_hal_ios_request_e eReq, void *pArgs); + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_IOS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.c new file mode 100644 index 0000000000..24011cda72 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.c @@ -0,0 +1,435 @@ +//***************************************************************************** +// +// am_hal_itm.c +//! @file +//! +//! @brief Functions for operating the instrumentation trace macrocell +//! +//! @addtogroup itm3 Instrumentation Trace Macrocell (ITM) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** + +//***************************************************************************** +// +//! @brief Enables the ITM +//! +//! This function enables the ARM ITM by setting the TRCENA bit in the DEMCR +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_enable(void) +{ + // + // To be able to access ITM registers, set the Trace Enable bit + // in the Debug Exception and Monitor Control Register (DEMCR). + // + CoreDebug->DEMCR |= _VAL2FLD(CoreDebug_DEMCR_TRCENA, 1); + while ( !(CoreDebug->DEMCR & _VAL2FLD(CoreDebug_DEMCR_TRCENA, 1)) ); + + // + // Write the key to the ITM Lock Access register to unlock the ITM_TCR. + // + ITM->LAR = ITM_LAR_KEYVAL; + + // + // Set the enable bits in the ITM trace enable register, and the ITM + // control registers to enable trace data output. + // + ITM->TPR = 0x0000000F; + ITM->TER = 0xFFFFFFFF; + + // + // Write to the ITM control and status register. + // + ITM->TCR = + _VAL2FLD(ITM_TCR_TraceBusID, 0x15) | + _VAL2FLD(ITM_TCR_GTSFREQ, 1) | + _VAL2FLD(ITM_TCR_TSPrescale, 1) | + _VAL2FLD(ITM_TCR_SWOENA, 1) | + _VAL2FLD(ITM_TCR_DWTENA, 0) | + _VAL2FLD(ITM_TCR_SYNCENA, 0) | + _VAL2FLD(ITM_TCR_TSENA, 0) | + _VAL2FLD(ITM_TCR_ITMENA, 1); + + + +} + +//***************************************************************************** +// +//! @brief Disables the ITM +//! +//! This function completely disables the ARM ITM by resetting the TRCENA bit +//! in the DEMCR register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_disable(void) +{ + + if ( MCUCTRL->TPIUCTRL == 0 ) + { + // + // This is a disable without enable, which could be the case with some + // earlier versions of SBL. To avoid a hang, ITM (particularly TPIU + // clock) must first be enabled. + // + am_hal_itm_enable(); + } + + // + // Make sure the ITM/TPIU is not busy. + // + am_hal_itm_not_busy(); + + // + // Make sure the ITM_TCR is unlocked. + // + ITM->LAR = ITM_LAR_KEYVAL; + + // + // Disable the ITM. + // + for (int ix = 0; ix < 100; ix++) + { + ITM->TCR &= ~_VAL2FLD(ITM_TCR_ITMENA, 1); + while ( ITM->TCR & (_VAL2FLD(ITM_TCR_ITMENA, 1) | _VAL2FLD(ITM_TCR_BUSY, 1)) ); + } + + // + // Reset the TRCENA bit in the DEMCR register, which should disable the ITM + // for operation. + // + CoreDebug->DEMCR &= ~_VAL2FLD(CoreDebug_DEMCR_TRCENA, 1); + while ( CoreDebug->DEMCR & _VAL2FLD(CoreDebug_DEMCR_TRCENA, 1) ); + + // + // Disable the TPIU clock source in MCU control. + // + MCUCTRL->TPIUCTRL = + _VAL2FLD(MCUCTRL_TPIUCTRL_CLKSEL, MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR) | + _VAL2FLD(MCUCTRL_TPIUCTRL_ENABLE, MCUCTRL_TPIUCTRL_ENABLE_DIS); + while (MCUCTRL->TPIUCTRL); + +} + +//***************************************************************************** +// +//! @brief Checks if itm is busy and provides a delay to flush the fifo +//! +//! This function disables the ARM ITM by resetting the TRCENA bit in the DEMCR +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_not_busy(void) +{ + // + // Make sure the ITM/TPIU is not busy. + // + while (ITM->TCR & _VAL2FLD(ITM_TCR_BUSY, 1)); + + // + // wait for 50us for the data to flush out + // + am_hal_flash_delay(FLASH_CYCLES_US(50)); +} + +//***************************************************************************** +// +//! @brief Enables tracing on a given set of ITM ports +//! +//! @param ui8portNum - Set ports to be enabled +//! +//! Enables tracing on the ports referred to by \e ui8portNum by writing the +//! associated bit in the Trace Privilege Register in the ITM. The value for +//! ui8portNum should be the logical OR one or more of the following values: +//! +//! \e ITM_PRIVMASK_0_7 - enable ports 0 through 7 +//! \e ITM_PRIVMASK_8_15 - enable ports 8 through 15 +//! \e ITM_PRIVMASK_16_23 - enable ports 16 through 23 +//! \e ITM_PRIVMASK_24_31 - enable ports 24 through 31 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_trace_port_enable(uint8_t ui8portNum) +{ + ITM->TPR |= (0x00000001 << (ui8portNum>>3)); +} + +//***************************************************************************** +// +//! @brief Disable tracing on the given ITM stimulus port. +//! +//! @param ui8portNum +//! +//! Disables tracing on the ports referred to by \e ui8portNum by writing the +//! associated bit in the Trace Privilege Register in the ITM. The value for +//! ui8portNum should be the logical OR one or more of the following values: +//! +//! \e ITM_PRIVMASK_0_7 - disable ports 0 through 7 +//! \e ITM_PRIVMASK_8_15 - disable ports 8 through 15 +//! \e ITM_PRIVMASK_16_23 - disable ports 16 through 23 +//! \e ITM_PRIVMASK_24_31 - disable ports 24 through 31 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_trace_port_disable(uint8_t ui8portNum) +{ + ITM->TPR &= ~(0x00000001 << (ui8portNum >> 3)); +} + +//***************************************************************************** +// +//! @brief Poll the given ITM stimulus register until not busy. +//! +//! @param ui32StimReg - stimulus register +//! +//! @return true if not busy, false if busy (timed out or other error). +// +//***************************************************************************** +bool +am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + // + // Busy waiting until it is available, non-zero means ready. + // + while ( !AM_REGVAL(ui32StimAddr) ); + + return true; +} + +//***************************************************************************** +// +//! @brief Writes a 32-bit value to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui32Value - value to be written. +//! +//! Write a word to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, uint32_t ui32Value) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + + // + // Busy waiting until it is available, non-zero means ready + // + while (!AM_REGVAL(ui32StimAddr)); + + // + // Write the register. + // + AM_REGVAL(ui32StimAddr) = ui32Value; +} + +//***************************************************************************** +// +//! @brief Writes a short to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui16Value - short to be written. +//! +//! Write a short to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, uint16_t ui16Value) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + // + // Busy waiting until it is available non-zero means ready + // + while ( !AM_REGVAL(ui32StimAddr) ); + + // + // Write the register. + // + *((volatile uint16_t *) ui32StimAddr) = ui16Value; +} + +//***************************************************************************** +// +//! @brief Writes a byte to the given ITM stimulus register. +//! +//! @param ui32StimReg - stimulus register +//! @param ui8Value - byte to be written. +//! +//! Write a byte to the desired stimulus register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, uint8_t ui8Value) +{ + uint32_t ui32StimAddr = (uint32_t)&ITM->PORT[0] + (4 * ui32StimReg); + + // + // Busy waiting until it is available (non-zero means ready) + // + while (!AM_REGVAL(ui32StimAddr)); + + // + // Write the register. + // + *((volatile uint8_t *) ui32StimAddr) = ui8Value; +} + +//***************************************************************************** +// +//! @brief Sends a Sync Packet. +//! +//! Sends a sync packet. This can be useful for external software should it +//! become out of sync with the ITM stream. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_sync_send(void) +{ + // + // Write the register. + // + am_hal_itm_stimulus_reg_word_write(AM_HAL_ITM_SYNC_REG, + AM_HAL_ITM_SYNC_VAL); +} + +//***************************************************************************** +// +//! @brief Poll the print stimulus registers until not busy. +//! +//! @return true if not busy, false if busy (timed out or other error). +// +//***************************************************************************** +bool +am_hal_itm_print_not_busy(void) +{ + // + // Poll stimulus register allocated for printing. + // + am_hal_itm_stimulus_not_busy(0); + + + return true; +} + +//***************************************************************************** +// +//! @brief Prints a char string out of the ITM. +//! +//! @param pcString pointer to the character sting +//! +//! This function prints a sting out of the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_itm_print(char *pcString) +{ + uint32_t ui32Length = 0; + + // + // Determine the length of the string. + // + while (*(pcString + ui32Length)) + { + ui32Length++; + } + + // + // If there is no longer a word left, empty out the remaining characters. + // + while (ui32Length) + { + // + // Print string out the ITM. + // + am_hal_itm_stimulus_reg_byte_write(0, (uint8_t)*pcString++); + + // + // Subtract from length. + // + ui32Length--; + } +} +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.h new file mode 100644 index 0000000000..2e48039378 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_itm.h @@ -0,0 +1,110 @@ +//***************************************************************************** +// +// am_hal_itm.h +//! @file +//! +//! @brief Functions for accessing and configuring the ARM ITM. +//! +//! @addtogroup itm3 Instrumentation Trace Macrocell (ITM) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_ITM_H +#define AM_HAL_ITM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Sync Packet Defines +// +//***************************************************************************** +#define AM_HAL_ITM_SYNC_REG 23 +#define AM_HAL_ITM_SYNC_VAL 0xF8F8F8F8 + +//***************************************************************************** +// +// PrintF Setup +// +//***************************************************************************** +#define AM_HAL_ITM_PRINT_NUM_BYTES 1 +#define AM_HAL_ITM_PRINT_NUM_REGS 1 +extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS]; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_itm_enable(void); +extern void am_hal_itm_disable(void); +extern void am_hal_itm_not_busy(void); +extern void am_hal_itm_sync_send(void); +extern void am_hal_itm_trace_port_enable(uint8_t ui8portNum); +extern void am_hal_itm_trace_port_disable(uint8_t ui8portNum); +extern bool am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg); +extern void am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, + uint32_t ui32Value); +extern void am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, + uint16_t ui16Value); +extern void am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, + uint8_t ui8Value); +extern bool am_hal_itm_print_not_busy(void); +extern void am_hal_itm_print(char *pcString); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_ITM_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.c new file mode 100644 index 0000000000..8613c05d13 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.c @@ -0,0 +1,564 @@ +//***************************************************************************** +// +// am_hal_mcuctrl.c +//! @file +//! +//! @brief Functions for interfacing with the MCUCTRL. +//! +//! @addtogroup mcuctrl3 MCU Control (MCUCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Global Variables. +// +//***************************************************************************** +// +// Define the flash sizes from CHIPPN. +// +const uint32_t +g_am_hal_mcuctrl_flash_size[AM_HAL_MCUCTRL_CHIPPN_FLASH_SIZE_N] = +{ + 16 * 1024, /* 0x0 0x00004000 16 KB */ + 32 * 1024, /* 0x1 0x00008000 32 KB */ + 64 * 1024, /* 0x2 0x00010000 64 KB */ + 128 * 1024, /* 0x3 0x00020000 128 KB */ + 256 * 1024, /* 0x4 0x00040000 256 KB */ + 512 * 1024, /* 0x5 0x00080000 512 KB */ + 1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */ + 2 * 1024 * 1024, /* 0x7 0x00200000 2 MB */ + 3 * 1024 * 1024 / 2, /* 0x8 0x00600000 1.5 MB */ + 0, 0, 0, 0, 0, 0, 0 +}; + +const uint32_t +g_am_hal_mcuctrl_sram_size[AM_HAL_MCUCTRL_CHIPPN_SRAM_SIZE_N] = +{ + 16 * 1024, /* 0x0 0x00004000 16 KB */ + 32 * 1024, /* 0x1 0x00008000 32 KB */ + 64 * 1024, /* 0x2 0x00010000 64 KB */ + 128 * 1024, /* 0x3 0x00020000 128 KB */ + 256 * 1024, /* 0x4 0x00040000 256 KB */ + 512 * 1024, /* 0x5 0x00080000 512 KB */ + 1 * 1024 * 1024, /* 0x6 0x00100000 1 MB */ + 384 * 1024, /* 0x7 0x00200000 384 KB */ + 768 * 1024, /* 0x8 0x000C0000 768 KB */ + 0, 0, 0, 0, 0, 0, 0 +}; + +// **************************************************************************** +// +// device_info_get() +// Gets all relevant device information. +// +// **************************************************************************** +static void +device_info_get(am_hal_mcuctrl_device_t *psDevice) +{ + // + // Read the Part Number. + // + psDevice->ui32ChipPN = MCUCTRL->CHIPPN; + + // + // Read the Chip ID0. + // + psDevice->ui32ChipID0 = MCUCTRL->CHIPID0; + + // + // Read the Chip ID1. + // + psDevice->ui32ChipID1 = MCUCTRL->CHIPID1; + + // + // Read the Chip Revision. + // + psDevice->ui32ChipRev = MCUCTRL->CHIPREV; + + // + // Read the Chip VENDOR ID. + // + psDevice->ui32VendorID = MCUCTRL->VENDORID; + + // + // Read the SKU (new for Apollo3). + // + psDevice->ui32SKU = MCUCTRL->SKU; + + // + // Qualified from Part Number. + // + psDevice->ui32Qualified = (psDevice->ui32ChipPN >> MCUCTRL_CHIPPN_PARTNUM_QUAL_S) & 0x1; + + // + // Flash size from Part Number. + // + psDevice->ui32FlashSize = + g_am_hal_mcuctrl_flash_size[ + (psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M) >> + MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S]; + + // + // SRAM size from Part Number. + // + psDevice->ui32SRAMSize = + g_am_hal_mcuctrl_sram_size[ + (psDevice->ui32ChipPN & MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M) >> + MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S]; + + // + // Now, let's look at the JEDEC info. + // The full partnumber is 12 bits total, but is scattered across 2 registers. + // Bits [11:8] are 0xE. + // Bits [7:4] are 0xE for Apollo, 0xD for Apollo2, 0xC for Apollo3. + // Bits [3:0] are defined differently for Apollo and Apollo2/Apollo3. + // For Apollo, the low nibble is 0x0. + // For Apollo2/Apollo3, the low nibble indicates flash and SRAM size. + // + psDevice->ui32JedecPN = JEDEC->PID0_b.PNL8 << 0; + psDevice->ui32JedecPN |= JEDEC->PID1_b.PNH4 << 8; + + // + // JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as + // 0x1B, with parity bit is 0x9B. It is 8 bits located across 2 registers. + // + psDevice->ui32JedecJEPID = JEDEC->PID1_b.JEPIDL << 0; + psDevice->ui32JedecJEPID |= JEDEC->PID2_b.JEPIDH << 4; + + // + // CHIPREV is 8 bits located across 2 registers. + // + psDevice->ui32JedecCHIPREV = JEDEC->PID2_b.CHIPREVH4 << 4; + psDevice->ui32JedecCHIPREV |= JEDEC->PID3_b.CHIPREVL4 << 0; + + // + // Let's get the Coresight ID (32-bits across 4 registers) + // For Apollo and Apollo2, it's expected to be 0xB105100D. + // + psDevice->ui32JedecCID = JEDEC->CID3_b.CID << 24; + psDevice->ui32JedecCID |= JEDEC->CID2_b.CID << 16; + psDevice->ui32JedecCID |= JEDEC->CID1_b.CID << 8; + psDevice->ui32JedecCID |= JEDEC->CID0_b.CID << 0; +} // device_info_get() + +//***************************************************************************** +// +// mcuctrl_fault_status() +// Gets the fault status and capture registers. +// +//***************************************************************************** +static void +mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault) +{ + uint32_t ui32FaultStat; + + // + // Read the Fault Status Register. + // + ui32FaultStat = MCUCTRL->FAULTSTATUS; + psFault->bICODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk); + psFault->bDCODE = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk); + psFault->bSYS = (bool)(ui32FaultStat & MCUCTRL_FAULTSTATUS_SYSFAULT_Msk); + + // + // Read the DCODE fault capture address register. + // + psFault->ui32DCODE = MCUCTRL->DCODEFAULTADDR; + + // + // Read the ICODE fault capture address register. + // + psFault->ui32ICODE |= MCUCTRL->ICODEFAULTADDR; + + // + // Read the ICODE fault capture address register. + // + psFault->ui32SYS |= MCUCTRL->SYSFAULTADDR; +} // mcuctrl_fault_status() + +// **************************************************************************** +// +// am_hal_mcuctrl_control() +// Apply various specific commands/controls on the MCUCTRL module. +// +// **************************************************************************** +uint32_t +am_hal_mcuctrl_control(am_hal_mcuctrl_control_e eControl, void *pArgs) +{ + uint32_t ui32Tbl; + + switch ( eControl ) + { + case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE: + // + // Enable the Fault Capture registers. + // + MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 1; + break; + + case AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE: + // + // Disable the Fault Capture registers. + // + MCUCTRL->FAULTCAPTUREEN_b.FAULTCAPTUREEN = 0; + break; + + case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE: + // + // Configure the bits in XTALCTRL that enable external 32KHz clock. + // + MCUCTRL->XTALCTRL &= + ~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk | + MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk | + MCUCTRL_XTALCTRL_XTALSWE_Msk); + + MCUCTRL->XTALCTRL |= + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE) | + _VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS) | + _VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN); + break; + + case AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE: + // + // Configure the bits in XTALCTRL that disable external 32KHz + // clock, thus re-configuring for the crystal. + // + MCUCTRL->XTALCTRL &= + ~(MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk | + MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk | + MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk | + MCUCTRL_XTALCTRL_XTALSWE_Msk); + + MCUCTRL->XTALCTRL |= + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCMPRXTAL, MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_PDNBCOREXTAL, MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE) | + _VAL2FLD(MCUCTRL_XTALCTRL_BYPCMPRXTAL, MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP) | + _VAL2FLD(MCUCTRL_XTALCTRL_FDBKDSBLXTAL, MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN) | + _VAL2FLD(MCUCTRL_XTALCTRL_XTALSWE, MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS); + break; + + case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH: + { + uint32_t ui32SramPrefetch = *(uint32_t*)pArgs; + uint32_t ui32SetMsk, ui32ClrMsk, ui32SRAMreg; + + // + // Validate the input flags. + // + if ( ui32SramPrefetch & + ~(AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR | + AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE | + AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA | + AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA | + AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + + // + // Given the rule that NOxxx overrides xxx, and keeping in mind + // that the cache settings cannot be set unless the regular + // prefetch is also being set or is already set, the following + // truth table results. + + // Note - this same TT also applies to data settings. + // nc=no change. + // I IC NI NIC: I IC + // 0x0: 0 0 0 0 : nc nc + // 0x1: 0 0 0 1 : nc 0 + // 0x2: 0 0 1 0 : 0 0 + // 0x3: 0 0 1 1 : 0 0 + // 0x4: 0 1 0 0 : INVALID + // 0x5: 0 1 0 1 : nc nc + // 0x6: 0 1 1 0 : INVALID + // 0x7: 0 1 1 1 : 0 0 + // 0x8: 1 0 0 0 : 1 0 + // 0x9: 1 0 0 1 : 1 0 + // 0xA: 1 0 1 0 : 0 0 + // 0xB: 1 0 1 1 : 0 0 + // 0xC: 1 1 0 0 : 1 1 + // 0xD: 1 1 0 1 : 1 0 + // 0xE: 1 1 1 0 : INVALID + // 0xF: 1 1 1 1 : 0 0 + // + + ui32Tbl = 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR) ? (1 << 3) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE) ? (1 << 2) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR) ? (1 << 1) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE) ? (1 << 0) : 0; + + // + // Now augment the table entries with current register settings. + // + ui32SRAMreg = MCUCTRL->SRAMMODE; + + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_Msk ? (1 << 3) : 0; + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk ? (1 << 2) : 0; + + ui32SetMsk = ui32ClrMsk = 0; + switch ( ui32Tbl ) + { + case 0x0: + case 0x5: + break; + case 0x1: + ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + case 0x2: + case 0x3: + case 0x7: + case 0xA: + case 0xB: + case 0xF: + ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + case 0x4: + case 0x6: + case 0xE: + return AM_HAL_STATUS_INVALID_OPERATION; + case 0x8: + case 0x9: + case 0xD: + ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk; + ui32ClrMsk = MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + case 0xC: + ui32SetMsk = MCUCTRL_SRAMMODE_IPREFETCH_Msk | MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } // switch() + + // + // Now, repeat with data settings. + // + ui32Tbl = 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA) ? (1 << 3) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE) ? (1 << 2) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA) ? (1 << 1) : 0; + ui32Tbl |= (ui32SramPrefetch & AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE) ? (1 << 0) : 0; + + // + // Now augment the table entries with current register settings. + // + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_Msk ? (1 << 3) : 0; + ui32Tbl |= ui32SRAMreg & MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk ? (1 << 2) : 0; + + switch ( ui32Tbl ) + { + case 0x0: + case 0x5: + break; + case 0x1: + ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + case 0x2: + case 0x3: + case 0x7: + case 0xA: + case 0xB: + case 0xF: + ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + case 0x4: + case 0x6: + case 0xE: + return AM_HAL_STATUS_INVALID_OPERATION; + case 0x8: + case 0x9: + case 0xD: + ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk; + ui32ClrMsk = MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + case 0xC: + ui32SetMsk = MCUCTRL_SRAMMODE_DPREFETCH_Msk | MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } // switch() + + + // + // Arrange the register update such that clrmsk will have precedence + // over setmsk. + // + AM_CRITICAL_BEGIN + ui32SRAMreg = MCUCTRL->SRAMMODE; + ui32SRAMreg |= ui32SetMsk; + ui32SRAMreg &= ~ui32ClrMsk; + MCUCTRL->SRAMMODE = ui32SRAMreg; + AM_CRITICAL_END + } // case AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_mcuctrl_control() + +// **************************************************************************** +// +// am_hal_mcuctrl_status_get() +//! This function returns current status of the MCUCTRL as obtained from +//! various registers of the MCUCTRL block. +// +// **************************************************************************** +uint32_t +am_hal_mcuctrl_status_get(am_hal_mcuctrl_status_t *psStatus) +{ + uint32_t ui32Status; + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32Status = MCUCTRL->FEATUREENABLE; + psStatus->bBurstAck = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTACK, ui32Status); + psStatus->bBLEAck = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BLEACK, ui32Status); + + psStatus->bDebuggerLockout = + _FLD2VAL(MCUCTRL_DEBUGGER_LOCKOUT, MCUCTRL->DEBUGGER); + + psStatus->bADCcalibrated = + _FLD2VAL(MCUCTRL_ADCCAL_ADCCALIBRATED, MCUCTRL->ADCCAL); + + psStatus->bBattLoadEnabled = + _FLD2VAL(MCUCTRL_ADCBATTLOAD_BATTLOAD, MCUCTRL->ADCBATTLOAD); + + ui32Status = MCUCTRL->BOOTLOADER; + psStatus->bSecBootOnColdRst = + _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOT, ui32Status); + psStatus->bSecBootOnWarmRst = + _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTONRST, ui32Status); + + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_mcuctrl_status_get() + +// **************************************************************************** +// +// am_hal_mcuctrl_info_get() +// Get information of the given MCUCTRL item. +// +// **************************************************************************** +uint32_t +am_hal_mcuctrl_info_get(am_hal_mcuctrl_infoget_e eInfoGet, void *pInfo) +{ + am_hal_mcuctrl_feature_t *psFeature; + uint32_t ui32Feature; + + if ( pInfo == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + switch ( eInfoGet ) + { + case AM_HAL_MCUCTRL_INFO_FEATURES_AVAIL: + psFeature = (am_hal_mcuctrl_feature_t*)pInfo; + ui32Feature = MCUCTRL->FEATUREENABLE; + psFeature->bBurstAvail = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BURSTAVAIL, ui32Feature); + psFeature->bBLEavail = + _FLD2VAL(MCUCTRL_FEATUREENABLE_BLEAVAIL, ui32Feature); + + ui32Feature = MCUCTRL->BOOTLOADER; + psFeature->ui8SecBootFeature = + _FLD2VAL(MCUCTRL_BOOTLOADER_SECBOOTFEATURE, ui32Feature); + + ui32Feature = MCUCTRL->SKU; + psFeature->bBLEFeature = + _FLD2VAL(MCUCTRL_SKU_ALLOWBLE, ui32Feature); + psFeature->bBurstFeature = + _FLD2VAL(MCUCTRL_SKU_ALLOWBURST, ui32Feature); + break; + + case AM_HAL_MCUCTRL_INFO_DEVICEID: + device_info_get((am_hal_mcuctrl_device_t *)pInfo); + break; + + case AM_HAL_MCUCTRL_INFO_FAULT_STATUS: + mcuctrl_fault_status((am_hal_mcuctrl_fault_t*)pInfo); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_mcuctrl_info_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.h new file mode 100644 index 0000000000..0c04d16561 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mcuctrl.h @@ -0,0 +1,368 @@ +//***************************************************************************** +// +// am_hal_mcuctrl.h +//! @file +//! +//! @brief Functions for accessing and configuring the MCUCTRL. +//! +//! @addtogroup mcuctrl3 MCU Control (MCUCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_MCUCTRL_H +#define AM_HAL_MCUCTRL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_MCUCTRL 1 + +//***************************************************************************** +// +// Chip Revision IDentification. +// +//***************************************************************************** +#define APOLLO3_B0 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) == \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_B) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV0))) + +#define APOLLO3_A1 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) == \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_A) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV1))) + +#define APOLLO3_A0 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) == \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_A) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV0))) + +// +// Determine if >= a given revision level. +// +#define APOLLO3_GE_B0 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) >= \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_B) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV0))) + +#define APOLLO3_GE_A1 \ + ((MCUCTRL->CHIPREV & \ + (MCUCTRL_CHIPREV_REVMAJ_Msk | MCUCTRL_CHIPREV_REVMIN_Msk)) >= \ + (_VAL2FLD(MCUCTRL_CHIPREV_REVMAJ, MCUCTRL_CHIPREV_REVMAJ_A) | \ + _VAL2FLD(MCUCTRL_CHIPREV_REVMIN, MCUCTRL_CHIPREV_REVMIN_REV1))) + + +//***************************************************************************** +// +// MCUCTRL specific definitions. +// +//***************************************************************************** +#define AM_HAL_MCUCTRL_CHIPPN_FLASH_SIZE_N ((MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M >> MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S) + 1) +#define AM_HAL_MCUCTRL_CHIPPN_SRAM_SIZE_N ((MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M >> MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S) + 1) + +//***************************************************************************** +// +// MCUCTRL enumerations +// +//***************************************************************************** +//************************************** +//! MCUCTRL control operations +//************************************** +typedef enum +{ + AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE, + AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE, + AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE, + AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE, + AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH +} am_hal_mcuctrl_control_e; + +//************************************** +//! MCUCTRL info get +//************************************** +typedef enum +{ + AM_HAL_MCUCTRL_INFO_FEATURES_AVAIL, + AM_HAL_MCUCTRL_INFO_DEVICEID, + AM_HAL_MCUCTRL_INFO_FAULT_STATUS +} am_hal_mcuctrl_infoget_e; + +//************************************** +//! MCUCTRL SRAM prefetch settings +//! +//! Prefetch settings are made via a call to: +//! am_hal_mcuctrl_control(AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH, +//! &ui32PrefetchSetting); +//! +//! The settings may be logically ORed together to obtain the desired settings. +//! +//! Notes: +//! - NOPREFETCH settings override PREFETCH settings if both are provided. +//! For example, calling with both PREFETCH_INSTR and NOPREFETCH_INSTR +//! will result in instruction prefetch being disabled. +//! - When executing from SRAM, it is recommended that the PREFETCH_INSTR and +//! PREFETCH_INSTRCACHE bits be set. +//! - It is generally okay to have PREFETCH_INSTR & PREFETCH_INSTRCACHE enabled +//! even if no SRAM execution is expected. +//! - It is generally not recommended that data prefetch be enabled unless the +//! work flow has a large number of sequential accesses. +//! - Setting PREFETCH_INSTRCACHE requires PREFETCH_INSTR. This is enforced by +//! the function and an error is returned if both are not being set or if +//! PREFETCH_INSTR is not already set in the register. +//! - Setting PREFETCH_DATACACHE requires PREFETCH_DATA. This is enforced by +//! the function. An error is returned if both are not being set or if +//! PREFETCH_DATA is not already set in the register. +//************************************** +#define SRAM_NOPREFETCH_Pos 16 +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTR (MCUCTRL_SRAMMODE_IPREFETCH_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_INSTRCACHE (MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_DATA (MCUCTRL_SRAMMODE_DPREFETCH_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_PREFETCH_DATACACHE (MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk << 0) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTR (MCUCTRL_SRAMMODE_IPREFETCH_Msk << SRAM_NOPREFETCH_Pos) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_INSTRCACHE (MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk << SRAM_NOPREFETCH_Pos) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATA (MCUCTRL_SRAMMODE_DPREFETCH_Msk << SRAM_NOPREFETCH_Pos) +#define AM_HAL_MCUCTRL_SRAM_NOPREFETCH_DATACACHE (MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk << SRAM_NOPREFETCH_Pos) + +//***************************************************************************** +// +// MCUCTRL data structures +// +//***************************************************************************** +//************************************** +//! MCUCTRL device structure +//************************************** +typedef struct +{ + // + //! Device part number. (BCD format) + // + uint32_t ui32ChipPN; + + // + //! Unique Chip ID 0. + // + uint32_t ui32ChipID0; + + // + //! Unique Chip ID 1. + // + uint32_t ui32ChipID1; + + // + //! Chip Revision. + // + uint32_t ui32ChipRev; + + // + //! Vendor ID. + // + uint32_t ui32VendorID; + + // + //! SKU (Apollo3). + // + uint32_t ui32SKU; + + // + //! Qualified chip. + // + uint32_t ui32Qualified; + + // + //! Flash Size. + // + uint32_t ui32FlashSize; + + // + //! SRAM Size. + // + uint32_t ui32SRAMSize; + + // + // JEDEC chip info + // + uint32_t ui32JedecPN; + uint32_t ui32JedecJEPID; + uint32_t ui32JedecCHIPREV; + uint32_t ui32JedecCID; +} +am_hal_mcuctrl_device_t; + +//************************************** +//! MCUCTRL fault structure +//************************************** +typedef struct +{ + // + //! ICODE bus fault occurred. + // + bool bICODE; + + // + //! ICODE bus fault address. + // + uint32_t ui32ICODE; + + // + //! DCODE bus fault occurred. + // + bool bDCODE; + + // + //! DCODE bus fault address. + // + uint32_t ui32DCODE; + + // + //! SYS bus fault occurred. + // + bool bSYS; + + // + //! SYS bus fault address. + // + uint32_t ui32SYS; +} +am_hal_mcuctrl_fault_t; + +//************************************** +//! MCUCTRL status structure +//************************************** +typedef struct +{ + bool bBurstAck; // FEATUREENABLE + bool bBLEAck; // " + bool bDebuggerLockout; // DEBUGGER + bool bADCcalibrated; // ADCCAL + bool bBattLoadEnabled; // ADCBATTLOAD + uint8_t bSecBootOnWarmRst; // BOOTLOADER + uint8_t bSecBootOnColdRst; // " +} am_hal_mcuctrl_status_t; + +//************************************** +//! MCUCTRL features available structure +//************************************** +typedef struct +{ + bool bBurstAvail; // FEATUREENABLE + bool bBLEavail; // " + bool bBLEFeature; // SKU + bool bBurstFeature; // " + uint8_t ui8SecBootFeature; // BOOTLOADER +} am_hal_mcuctrl_feature_t; + + +// **************************************************************************** +// +//! @brief Apply various specific commands/controls on the MCUCTRL module. +//! +//! This function is used to apply various controls to MCUCTRL. +//! +//! @param eControl - One of the following: +//! AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_ENABLE +//! AM_HAL_MCUCTRL_CONTROL_FAULT_CAPTURE_DISABLE +//! AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_ENABLE +//! AM_HAL_MCUCTRL_CONTROL_EXTCLK32K_DISABLE +//! AM_HAL_MCUCTRL_CONTROL_SRAM_PREFETCH +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_mcuctrl_control(am_hal_mcuctrl_control_e eControl, + void *pArgs); + +// **************************************************************************** +// +//! @brief MCUCTRL status function +//! +//! This function returns current status of the MCUCTRL as obtained from +//! various registers of the MCUCTRL block. +//! +//! @param psStatus - ptr to a status structure to receive the current statuses. +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_mcuctrl_status_get(am_hal_mcuctrl_status_t *psStatus); + +// **************************************************************************** +// +//! @brief Get information of the given MCUCTRL item. +//! +//! This function returns a data structure of information regarding the given +//! MCUCTRL parameter. +//! +//! @param eInfoGet - One of the following: Return structure type: +//! AM_HAL_MCUCTRL_INFO_DEVICEID, psDevice +//! AM_HAL_MCUCTRL_INFO_FAULT_STATUS psFault +//! +//! @param pInfo - A pointer to a structure to receive the return data, +//! the type of which is dependent on the eInfo parameter. +//! +//! @return status - generic or interface specific status. +// +// **************************************************************************** +extern uint32_t am_hal_mcuctrl_info_get(am_hal_mcuctrl_infoget_e eInfoGet, + void *pInfo); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_MCUCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.c new file mode 100644 index 0000000000..d107daa381 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.c @@ -0,0 +1,3438 @@ +//***************************************************************************** +// +// am_hal_mspi.c +//! @file +//! +//! @brief Functions for interfacing with the MSPI. +//! +//! @addtogroup mspi3 Multi-bit SPI (MSPI) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Private Types. +// +//***************************************************************************** + +#define AM_HAL_MAGIC_MSPI 0xBEBEBE +#define AM_HAL_MSPI_CHK_HANDLE(h) ((h) && ((am_hal_handle_prefix_t *)(h))->s.bInit && (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_MSPI)) +#define AM_HAL_MSPI_HW_IDX_MAX (AM_REG_MSPI_CQCURIDX_CQCURIDX_M >> AM_REG_MSPI_CQCURIDX_CQCURIDX_S) // 8 bit value +#define AM_HAL_MSPI_MAX_CQ_ENTRIES (256) + + + +// For MSPI - Need to Set the flag for unpausing +#define AM_HAL_MSPI_SC_PAUSE_CQ AM_HAL_MSPI_SC_PAUSE(AM_HAL_MSPI_PAUSE_FLAG_CQ) +#define AM_HAL_MSPI_SC_PAUSE_SEQLOOP AM_HAL_MSPI_SC_PAUSE(AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_MSPI_SC_UNPAUSE_CQ AM_HAL_MSPI_SC_UNPAUSE(AM_HAL_MSPI_PAUSE_FLAG_CQ) +#define AM_HAL_MSPI_SC_UNPAUSE_SEQLOOP AM_HAL_MSPI_SC_UNPAUSE(AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP) +#define AM_HAL_MSPI_SC_PAUSE_BLOCK AM_HAL_MSPI_SC_PAUSE(AM_HAL_MSPI_PAUSE_FLAG_BLOCK) +#define AM_HAL_MSPI_SC_UNPAUSE_BLOCK AM_HAL_MSPI_SC_UNPAUSE(AM_HAL_MSPI_PAUSE_FLAG_BLOCK) + + +// Max time to wait when attempting to pause the command queue +#define AM_HAL_MSPI_MAX_PAUSE_DELAY (100*1000) // 100ms + +// +// MSPI interface mode and chip enable selection. +// This is an internal extension to am_hal_mspi_device_e +// +typedef enum +{ + AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2 = AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL + 1, + AM_HAL_MSPI_FLASH_DUAL_CE1_1_1_2, + AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2, + AM_HAL_MSPI_FLASH_DUAL_CE1_1_2_2, + AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4, + AM_HAL_MSPI_FLASH_QUAD_CE1_1_1_4, + AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4, + AM_HAL_MSPI_FLASH_QUAD_CE1_1_4_4, + AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE, + AM_HAL_MSPI_FLASH_SERIAL_CE1_3WIRE, +} mspi_device_e; + +// +// Command Queue entry structure for DMA transfer. +// +typedef struct +{ +#if MSPI_USE_CQ + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; +#endif +#if !MSPI_USE_CQ + // Need to disable the DMA before reconfiguring it + uint32_t ui32DMACFG2Addr; + uint32_t ui32DMACFG2Val; +#endif + uint32_t ui32DMATARGADDRAddr; + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMADEVADDRAddr; + uint32_t ui32DMADEVADDRVal; + uint32_t ui32DMATOTCOUNTAddr; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMACFG1Addr; + uint32_t ui32DMACFG1Val; +#if MSPI_USE_CQ + // Need to disable the DMA to prepare for next reconfig + // Need to have this following the DMAEN for CMDQ + uint32_t ui32DMACFG2Addr; + uint32_t ui32DMACFG2Val; + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +#endif +} am_hal_mspi_cq_dma_entry_t; + +// +// structure for Hi Prio DMA transfer. +// +typedef struct +{ + uint32_t ui32DMATARGADDRVal; + uint32_t ui32DMADEVADDRVal; + uint32_t ui32DMATOTCOUNTVal; + uint32_t ui32DMACFG1Val; + am_hal_mspi_callback_t pfnCallback; + void *pCallbackCtxt; +} am_hal_mspi_dma_entry_t; + +// +// Command Queue entry structure for Sequence Repeat +// +typedef struct +{ + uint32_t ui32PAUSENAddr; + uint32_t ui32PAUSEENVal; + uint32_t ui32PAUSEN2Addr; + uint32_t ui32PAUSEEN2Val; + uint32_t ui32SETCLRAddr; + uint32_t ui32SETCLRVal; +} am_hal_mspi_cq_loop_entry_t; + +// +// Command Queue entry structure for PIO transfer. +// +typedef struct +{ + uint32_t ui32ADDRAddr; + uint32_t ui32ADDRVal; + uint32_t ui32INSTRAddr; + uint32_t ui32INSTRVal; + uint32_t ui32CTRLAddr; + uint32_t ui32CTRLVal; +} am_hal_mspi_cq_pio_entry_t; + +typedef struct +{ + bool bValid; + uint32_t regCFG; + uint32_t regMSPICFG; + uint32_t regPADCFG; + uint32_t regPADOUTEN; + uint32_t regFLASH; + uint32_t regSCRAMBLING; + uint32_t regCQCFG; + uint32_t regCQADDR; + uint32_t regCQPAUSE; + uint32_t regCQFLAGS; + uint32_t regCQCURIDX; + uint32_t regCQENDIDX; + uint32_t regINTEN; + // TODO: May be no need to preserve these values, as they are constants anyways? + uint32_t regDMABCOUNT; + uint32_t regDMATHRESH; +} am_hal_mspi_register_state_t; + +// +// Command Queue control structure. +// +typedef struct +{ + void *pCmdQHdl; +} am_hal_mspi_CQ_t; + +typedef enum +{ + AM_HAL_MSPI_SEQ_NONE, + AM_HAL_MSPI_SEQ_UNDER_CONSTRUCTION, + AM_HAL_MSPI_SEQ_RUNNING, +} am_hal_mspi_seq_e; + +// +// MSPI State structure. +// +typedef struct +{ + // + // Handle validation prefix. + // + am_hal_handle_prefix_t prefix; + + // + // Physical module number. + // + uint32_t ui32Module; + + // + // Selected flash device configuration. + // + am_hal_mspi_device_e eDeviceConfig; + + // + // Clock frequency + // + am_hal_mspi_clock_e eClockFreq; + + // + // Endianess of the FIFO interface. + // + bool bBigEndian; + + // + // Delay timeout value. + // + uint32_t waitTimeout; + // DMA Transfer Control Buffer size in words. + uint32_t ui32TCBSize; + + // DMA Transfer Control Buffer + uint32_t *pTCB; + + uint32_t ui32LastIdxProcessed; + uint32_t ui32NumCQEntries; + uint32_t ui32TxnInt; + + // + // Stores the CQ callbacks. + // + am_hal_mspi_callback_t pfnCallback[AM_HAL_MSPI_MAX_CQ_ENTRIES]; + + void *pCallbackCtxt[AM_HAL_MSPI_MAX_CQ_ENTRIES]; +#if MSPI_USE_CQ + // + // Command Queue. + // + am_hal_mspi_CQ_t CQ; + // To support sequence + am_hal_mspi_seq_e eSeq; + bool bAutonomous; + uint32_t ui32NumTransactions; + volatile bool bRestart; + uint32_t block; + // To support high priority transactions - out of band + // High Priority DMA transactions + volatile bool bHP; + uint32_t ui32NumHPEntries; + uint32_t ui32NumHPPendingEntries; + uint32_t ui32MaxHPTransactions; + uint32_t ui32NextHPIdx; + uint32_t ui32LastHPIdxProcessed; + am_hal_mspi_dma_entry_t *pHPTransactions; + // Max pending transactions based on NB Buffer size + uint32_t ui32MaxPending; + // Number of back to back transactions with no callbacks + uint32_t ui32NumUnSolicited; +#else + uint32_t ui32MaxTransactions; + uint32_t ui32NextIdx; + am_hal_mspi_cq_dma_entry_t *pTransactions; +#endif + + // + // MSPI Capabilities. + // + am_hal_mspi_capabilities_t capabilities; + + // Power Save-Restore register state + am_hal_mspi_register_state_t registerState; +} am_hal_mspi_state_t; + +//***************************************************************************** +// +// Global Variables. +// +//***************************************************************************** +am_hal_mspi_state_t g_MSPIState[AM_REG_MSPI_NUM_MODULES]; + + +#if !MSPI_USE_CQ +void (*g_pfnDMACallback[AM_REG_MSPI_NUM_MODULES])(void); +void *g_pCallbackCtxt[AM_REG_MSPI_NUM_MODULES]; +#endif //!MSPI_USE_CQ + +//***************************************************************************** +// +// Internal Functions. +// +//***************************************************************************** +static uint32_t +get_pause_val(am_hal_mspi_state_t *pMSPIState, uint32_t pause) +{ + uint32_t retval; + switch (pMSPIState->block) + { + case 1: + // Pause the CQ till the whole block is built + retval = pause | AM_HAL_MSPI_CQP_PAUSE_DEFAULT | AM_HAL_MSPI_PAUSE_FLAG_BLOCK; + pMSPIState->block = 2; + break; + case 2: + // No pausing allowed + retval = AM_HAL_MSPI_PAUSE_DEFAULT; + break; + default: // case 0 + retval = pause | AM_HAL_MSPI_CQP_PAUSE_DEFAULT; + } + return retval; +} + +uint32_t +build_dma_cmdlist(am_hal_mspi_state_t *pMSPIState, + am_hal_mspi_trans_e eMode, + void *pCQEntry, + void *pTransaction) +{ + uint32_t ui32Module = pMSPIState->ui32Module; + + switch(eMode) + { + case AM_HAL_MSPI_TRANS_PIO: + { + am_hal_mspi_cq_pio_entry_t *pPIOEntry = (am_hal_mspi_cq_pio_entry_t*)pCQEntry; + am_hal_mspi_pio_transfer_t *pPIOTrans = (am_hal_mspi_pio_transfer_t*)pTransaction; + + // + // Perform some sanity checks on the transaction. + // + if (pPIOTrans->ui32NumBytes > 65535) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Command to set the CTRL register. + // + pPIOEntry->ui32ADDRAddr = (uint32_t)&MSPIn(ui32Module)->ADDR; + pPIOEntry->ui32ADDRVal = _VAL2FLD(MSPI_ADDR_ADDR, pPIOTrans->ui32DeviceAddr); + pPIOEntry->ui32INSTRAddr = (uint32_t)&MSPIn(ui32Module)->INSTR; + pPIOEntry->ui32INSTRVal = _VAL2FLD(MSPI_INSTR_INSTR, pPIOTrans->ui16DeviceInstr); + pPIOEntry->ui32CTRLAddr = (uint32_t)&MSPIn(ui32Module)->CTRL; + pPIOEntry->ui32CTRLVal = + _VAL2FLD(MSPI_CTRL_XFERBYTES, pPIOTrans->ui32NumBytes) | // Set the number of bytes to transfer. + _VAL2FLD(MSPI_CTRL_PIOSCRAMBLE, pPIOTrans->bScrambling) | // Set the scrambling if selected. + _VAL2FLD(MSPI_CTRL_TXRX, pPIOTrans->eDirection) | // Set transmit or receive operation. + _VAL2FLD(MSPI_CTRL_SENDI, pPIOTrans->bSendInstr) | // Enable sending the instruction. + _VAL2FLD(MSPI_CTRL_SENDA, pPIOTrans->bSendAddr) | // Enable sending the address. + _VAL2FLD(MSPI_CTRL_ENTURN, pPIOTrans->bTurnaround) | // Set the turn-around if needed. + _VAL2FLD(MSPI_CTRL_BIGENDIAN, pMSPIState->bBigEndian) | // Set the FIFO endian format. + _VAL2FLD(MSPI_CTRL_QUADCMD, pPIOTrans->bQuadCmd) | // Set the Quad Command if indicated. + _VAL2FLD(MSPI_CTRL_START, 1); // Start the transfer. + + } + break; + case AM_HAL_MSPI_TRANS_DMA: + { + am_hal_mspi_cq_dma_entry_t *pDMAEntry = (am_hal_mspi_cq_dma_entry_t *)pCQEntry; + am_hal_mspi_dma_transfer_t *pDMATrans = (am_hal_mspi_dma_transfer_t *)pTransaction; + + // + // Perform some sanity checks on the transaction. + // + if (pDMATrans->ui32TransferCount > 65535) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + if (pMSPIState->block && (pDMATrans->ui32PauseCondition != 0)) + { + // Paused operations not allowed in block mode + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Command to set the DMACFG to disable DMA. + // Need to make sure we disable DMA before we can reprogram + // + pDMAEntry->ui32DMACFG2Addr = (uint32_t)&MSPIn(ui32Module)->DMACFG; + pDMAEntry->ui32DMACFG2Val = _VAL2FLD(MSPI_DMACFG_DMAEN, 0); + + // + // Command to set the DMATARGADDR + // + pDMAEntry->ui32DMATARGADDRAddr = (uint32_t)&MSPIn(ui32Module)->DMATARGADDR; + pDMAEntry->ui32DMATARGADDRVal = pDMATrans->ui32SRAMAddress; + + // + // Command to set the DMADEVADDR + // + pDMAEntry->ui32DMADEVADDRAddr = (uint32_t)&MSPIn(ui32Module)->DMADEVADDR; + pDMAEntry->ui32DMADEVADDRVal = pDMATrans->ui32DeviceAddress; + + // + // Command to set the DMATOTALCOUNT + // + pDMAEntry->ui32DMATOTCOUNTAddr = (uint32_t)&MSPIn(ui32Module)->DMATOTCOUNT; + pDMAEntry->ui32DMATOTCOUNTVal = pDMATrans->ui32TransferCount; + + // + // Command to set the DMACFG to start DMA. + // + pDMAEntry->ui32DMACFG1Addr = (uint32_t)&MSPIn(ui32Module)->DMACFG; + pDMAEntry->ui32DMACFG1Val = + _VAL2FLD(MSPI_DMACFG_DMAPWROFF, 0) | // DMA Auto Power-off not supported! + _VAL2FLD(MSPI_DMACFG_DMAPRI, pDMATrans->ui8Priority) | + _VAL2FLD(MSPI_DMACFG_DMADIR, pDMATrans->eDirection) | + _VAL2FLD(MSPI_DMACFG_DMAEN, 3); +#if MSPI_USE_CQ + pDMAEntry->ui32PAUSENAddr = pDMAEntry->ui32PAUSEN2Addr = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pDMAEntry->ui32PAUSEENVal = get_pause_val(pMSPIState, pDMATrans->ui32PauseCondition); + pDMAEntry->ui32PAUSEEN2Val = AM_HAL_MSPI_PAUSE_DEFAULT; + pDMAEntry->ui32SETCLRVal = pDMATrans->ui32StatusSetClr; + pDMAEntry->ui32SETCLRAddr = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; +#endif + } + break; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Writes data to the MSPI FIFO. +//! +//! @param ui32Module - Selects the MSPI module to use (zero or one). +//! @param pui32Data - Pointer to an array of the data to be written. +//! @param ui32NumBytes - Number of BYTES to copy into the FIFO. +//! +//! This function copies data from the array \e pui32Data into the MSPI FIFO. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +static uint32_t +mspi_fifo_write(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes, uint32_t ui32Timeout) +{ + uint32_t ui32Index; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_MSPI_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Loop over the words in the array until we have the correct number of + // bytes. + // + for ( ui32Index = 0; (4 * ui32Index) < ui32NumBytes; ui32Index++ ) + { + // + // Write the word to the FIFO. + // + MSPIn(ui32Module)->TXFIFO = pui32Data[ui32Index]; + + // + // Wait for the word to go out if there is no room in the FIFO. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->TXENTRIES, + MSPI_TXENTRIES_TXENTRIES_Msk, + _VAL2FLD(MSPI_TXENTRIES_TXENTRIES, AM_HAL_MSPI_MAX_FIFO_SIZE), + false); + } + + // + // Return the status. + // + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Reads data from the MSPI FIFO. +//! +//! @param ui32Module - Selects the IOM module to use (zero or one). +//! @param pui32Data - Pointer to an array where the FIFO data will be copied. +//! @param ui32NumBytes - Number of bytes to copy into array. +//! +//! This function copies data from the MSPI FIFO into the array \e pui32Data. +//! +//! @return HAL status of the operation. +// +//***************************************************************************** +static uint32_t +mspi_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, + uint32_t ui32NumBytes, uint32_t ui32Timeout) +{ + am_hal_mspi_buffer(4) sTempBuffer; + uint32_t i, ui32NumWords, ui32Leftovers; + uint32_t ui32Status; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_MSPI_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Figure out how many whole words we're reading from the fifo, and how + // many bytes will be left over when we're done. + // + ui32NumWords = ui32NumBytes / 4; + ui32Leftovers = ui32NumBytes - (ui32NumWords * 4); + + // + // Copy out as many full words as we can. + // + for ( i = 0; i < ui32NumWords; i++ ) + { + // + // Wait for additinal entries in the MSPI RX FIFO. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->RXENTRIES, + MSPI_RXENTRIES_RXENTRIES_Msk, + _VAL2FLD(MSPI_RXENTRIES_RXENTRIES, 0), + false); + + // + // Check for timeout + // + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Copy data out of the FIFO, one word at a time. + // + pui32Data[i] = MSPIn(ui32Module)->RXFIFO; + } + + // + // If there were leftovers, we'll copy them carefully. Pull the last word + // from the fifo (there should only be one) into a temporary buffer. Also, + // create an 8-bit pointer to help us copy the remaining bytes one at a + // time. + // + // Note: If the data buffer we were given was truly a word pointer like the + // definition requests, we wouldn't need to do this. It's possible to call + // this function with a re-cast or packed pointer instead though. If that + // happens, we want to be careful not to overwrite any data that might be + // sitting just past the end of the destination array. + // + if ( ui32Leftovers ) + { + // + // Wait for additinal entries in the MSPI RX FIFO. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->RXENTRIES, + MSPI_RXENTRIES_RXENTRIES_Msk, + _VAL2FLD(MSPI_RXENTRIES_RXENTRIES, 0), + false); + + // + // Check for timeout + // + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Read the next word from the RX FIFO. + // + sTempBuffer.words[0] = MSPIn(ui32Module)->RXFIFO; + uint8_t *pui8Data; + pui8Data = (uint8_t *) (&pui32Data[i]); + + // + // If we had leftover bytes, copy them out one byte at a time. + // + for ( int j = 0; j < ui32Leftovers; j++ ) + { + pui8Data[j] = sTempBuffer.bytes[j]; + } + } + + return AM_HAL_STATUS_SUCCESS; +} + +#if !MSPI_USE_CQ +static void +run_txn_cmdlist(void *pCQEntry, uint32_t numEntries) +{ + uint32_t ix; + am_hal_cmdq_entry_t *pCmd = (am_hal_cmdq_entry_t *)pCQEntry; + + for ( ix = 0; ix < numEntries; ix++, pCmd++ ) + { + *((uint32_t *)pCmd->address) = pCmd->value; + } +} // run_txn_cmdlist() + +static uint32_t +mspi_dma_add_transaction(void *pHandle, + am_hal_mspi_dma_transfer_t *psTransaction, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + am_hal_mspi_cq_dma_entry_t *pCQEntry; + uint32_t index = pMSPIState->ui32NextIdx % pMSPIState->ui32MaxTransactions; + + // + // Check to see if there is enough room in the queue + // + if ( pMSPIState->ui32NumCQEntries == pMSPIState->ui32MaxTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQEntry = &pMSPIState->pTransactions[index]; + + + if (AM_HAL_STATUS_SUCCESS != build_dma_cmdlist(pMSPIState, AM_HAL_MSPI_TRANS_DMA, pCQEntry, (void *)psTransaction)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index] = pfnCallback; + pMSPIState->pCallbackCtxt[index] = pCallbackCtxt; + pMSPIState->ui32NextIdx++; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_mspi_DmaAddTransaction() + +#else + + +//***************************************************************************** +// +//! @brief Initializes the MSPI Command Queue. +//! +//! @param handle - handle for the interface. +//! @param ui32Length - length of the SRAM Command Queue buffer in words. +//! @param pTCB - pointer to the SRAM to use for the Command Queue. +//! +//! This function initializes the global command queue structure. +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_init(uint32_t ui32Module, uint32_t ui32Length, + uint32_t *pTCB) +{ + am_hal_cmdq_cfg_t cqCfg; + + cqCfg.pCmdQBuf = pTCB; + cqCfg.cmdQSize = ui32Length / 2; + cqCfg.priority = AM_HAL_CMDQ_PRIO_HI; + return am_hal_cmdq_init((am_hal_cmdq_if_e)(AM_HAL_CMDQ_IF_MSPI + ui32Module), + &cqCfg, &g_MSPIState[ui32Module].CQ.pCmdQHdl); +} + +//***************************************************************************** +// +//! @brief Terminates the MSPI Command Queue. +//! +//! @param ui32Module - MSPI instance. +//! +//! This function resets the global command queue structure. +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_term(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module = pMSPIState->ui32Module; + + if (g_MSPIState[ui32Module].CQ.pCmdQHdl) + { + am_hal_cmdq_term(g_MSPIState[ui32Module].CQ.pCmdQHdl, true); + g_MSPIState[ui32Module].CQ.pCmdQHdl = NULL; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! @brief Adds a transaction the MSPI Command Queue. +//! +//! @param handle - handle for the interface. +//! @param pTransaction - transaction to add to the CQ +//! @param pfnCallback - pointer the callback function to be executed when +//! transaction is complete. +//! @param pCallbackCtxt- pointer to the state/context to pass to callback +//! function. +//! +//! This function copies data from the IOM FIFO into the array \e pui32Data. +//! This is how input data from SPI or I2C transactions may be retrieved. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_add_transaction(void *pHandle, + void *pTransaction, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + uint32_t size = 1; + am_hal_mspi_CQ_t *pCQ = &pMSPIState->CQ; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + + // + // Determine the transfer mode and set up accordingly. + // + switch(eMode) + { + case AM_HAL_MSPI_TRANS_PIO: + size = sizeof(am_hal_mspi_cq_pio_entry_t); + break; + case AM_HAL_MSPI_TRANS_DMA: + size = sizeof(am_hal_mspi_cq_dma_entry_t); + break; + } + + // + // Check to see if there is enough room in the CQ + // + if (pMSPIState->ui32NumCQEntries == AM_HAL_MSPI_MAX_CQ_ENTRIES) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + ui32Status = am_hal_cmdq_alloc_block(pCQ->pCmdQHdl, size / 8, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + + ui32Status = build_dma_cmdlist(pMSPIState, eMode, pCQBlock, pTransaction); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + am_hal_cmdq_release_block(pCQ->pCmdQHdl); + return ui32Status; + } + + // + // Because we set AM_HAL_IOM_CQUPD_INT_FLAG, an interrupt will occur once + // we reach this point in the Command Queue. In the service routine, we'll + // look for the appropriate callback. + // + // If ENDIDX has been reached, the CQ will pause here. Otherwise will + // continue with the next CQ entry. + // + + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pfnCallback; + pMSPIState->pCallbackCtxt[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pCallbackCtxt; + + // + // Return the status. + // + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Enable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function enables Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_enable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + + // + // Enable the Command Queue operation + // + return am_hal_cmdq_enable(pMSPIState->CQ.pCmdQHdl); +} +//***************************************************************************** +// +//! @brief Disable the Command Queue operation. +//! +//! @param handle - handle for the interface. +//! +//! This function disables the Command Queue operation. +//! +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_cq_disable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + + // + // Disable the Command Queue operation + // + return am_hal_cmdq_disable(pMSPIState->CQ.pCmdQHdl); +} + +static uint32_t +mspi_cq_pause(am_hal_mspi_state_t *pMSPIState) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32usMaxDelay = AM_HAL_MSPI_MAX_PAUSE_DELAY; + + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_PAUSE_CQ; + // It is possible that CQ is disabled once the last transaction is processed + while ( MSPIn(pMSPIState->ui32Module)->CQCFG_b.CQEN ) + { + // Need to make sure we're paused at a designated pause point + if ( MSPIn(pMSPIState->ui32Module)->CQSTAT_b.CQPAUSED && (MSPIn(pMSPIState->ui32Module)->CQPAUSE & AM_HAL_MSPI_PAUSE_FLAG_CQ)) + { + break; + } + if ( ui32usMaxDelay-- ) + { + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + else + { + return AM_HAL_STATUS_TIMEOUT; + } + } + if (status == AM_HAL_STATUS_SUCCESS) + { + // Now that CQ is guaranteed to not progress further - we need to still wait in case the current CQ entry + // resulted in a DMA state....need to make sure we finish the current DMA + status = am_hal_flash_delay_status_check(AM_HAL_MSPI_MAX_PAUSE_DELAY, + (uint32_t)&MSPIn(pMSPIState->ui32Module)->DMASTAT, + MSPI_DMASTAT_DMATIP_Msk, + _VAL2FLD(MSPI_DMASTAT_DMATIP, 0), + true); + + } + return status; +} + +static void +program_dma(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module = pMSPIState->ui32Module; + uint32_t index = (pMSPIState->ui32LastHPIdxProcessed + 1) % pMSPIState->ui32MaxHPTransactions; + am_hal_mspi_dma_entry_t *pDMAEntry = &pMSPIState->pHPTransactions[index]; + + // Need to make sure we disable DMA before we can reprogram + MSPIn(ui32Module)->DMACFG = _VAL2FLD(MSPI_DMACFG_DMAEN, 0); + // + // set the DMATARGADDR + // + MSPIn(ui32Module)->DMATARGADDR = pDMAEntry->ui32DMATARGADDRVal; + + // + // set the DMADEVADDR + // + MSPIn(ui32Module)->DMADEVADDR = pDMAEntry->ui32DMADEVADDRVal; + + // + // set the DMATOTALCOUNT + // + MSPIn(ui32Module)->DMATOTCOUNT = pDMAEntry->ui32DMATOTCOUNTVal; + + // + // set the DMACFG to start DMA. + // + MSPIn(ui32Module)->DMACFG = pDMAEntry->ui32DMACFG1Val; +} + + +static uint32_t +sched_hiprio(am_hal_mspi_state_t *pMSPIState, uint32_t numTrans) +{ + uint32_t ui32NumPend; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pMSPIState->ui32NumHPEntries; + pMSPIState->ui32NumHPEntries += numTrans; + + // + // End the critical section. + // + AM_CRITICAL_END + + + if (0 == ui32NumPend) + { + // Force CQ to Pause + ui32Status = mspi_cq_pause(pMSPIState); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + pMSPIState->ui32TxnInt = 0; + // Clear DMACMP interrupt + MSPIn(pMSPIState->ui32Module)->INTCLR = AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_CMDCMP; + // Enable DMACMP interrupt + MSPIn(pMSPIState->ui32Module)->INTEN |= AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_CMDCMP; + pMSPIState->bHP = true; + // + // Program the DMA + // + program_dma(pMSPIState); + } + return ui32Status; +} + + +static uint32_t +mspi_add_hp_transaction(void *pHandle, + am_hal_mspi_dma_transfer_t *pDMATrans, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + am_hal_mspi_dma_entry_t *pDMAEntry; + + uint32_t index = pMSPIState->ui32NextHPIdx % pMSPIState->ui32MaxHPTransactions; + + // + // Check to see if there is enough room in the queue + // + if ( pMSPIState->ui32NumHPEntries == pMSPIState->ui32MaxHPTransactions ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pDMAEntry = &pMSPIState->pHPTransactions[index]; + pDMAEntry->ui32DMATARGADDRVal = pDMATrans->ui32SRAMAddress; + pDMAEntry->ui32DMADEVADDRVal = pDMATrans->ui32DeviceAddress; + pDMAEntry->ui32DMATOTCOUNTVal = pDMATrans->ui32TransferCount; + pDMAEntry->ui32DMACFG1Val = + _VAL2FLD(MSPI_DMACFG_DMAPWROFF, 0) | // DMA Auto Power-off not supported! + _VAL2FLD(MSPI_DMACFG_DMAPRI, pDMATrans->ui8Priority) | + _VAL2FLD(MSPI_DMACFG_DMADIR, pDMATrans->eDirection) | + _VAL2FLD(MSPI_DMACFG_DMAEN, 3); + pDMAEntry->pfnCallback = pfnCallback; + pDMAEntry->pCallbackCtxt = pCallbackCtxt; + + pMSPIState->ui32NextHPIdx++; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_mspi_DmaAddTransaction() + +#endif + +//***************************************************************************** +// +//! @brief Determine the virtual device configuration +//! +//! @param handle - handle for the interface. +//! @param eMSPIDevice - external device configuration for MSPI +//! +//! @return virtual device value. +// +// +//***************************************************************************** +// +// MSPI interface mode and chip enable selection. +// This is an internal extension to am_hal_mspi_device_e +// +static uint32_t +mspi_virtual_device(mspi_device_info_t *pMSPIDeviceInfo, uint32_t *pVirtDevice) +{ + // + // Check that the Device Config is in the proper range. + // + if (pMSPIDeviceInfo->eDeviceConfig > AM_HAL_MSPI_FLASH_MAX) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + switch(pMSPIDeviceInfo->eXipMixedMode) + { + case AM_HAL_MSPI_XIPMIXED_NORMAL: + { + // if Serial CE0 or CE1, check for separate I/O. + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + // if serial mode, but not separate I/O , then calculate 3WIRE mode value. + if (!pMSPIDeviceInfo->bSeparateIO) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + // Otherwise return the original eDeviceConfig. + *pVirtDevice = pMSPIDeviceInfo->eDeviceConfig; + return AM_HAL_STATUS_SUCCESS; + } + } + else + { + // Otherwise return the original eDeviceConfig. + *pVirtDevice = pMSPIDeviceInfo->eDeviceConfig; + return AM_HAL_STATUS_SUCCESS; + } + } + break; + + case AM_HAL_MSPI_XIPMIXED_D2: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_AD2: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_D4: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_AD4: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } +} + + //***************************************************************************** +// +//! @brief Configure the device config, seperate I/O, mixed mode, and internal +//! PADs based on the virtual device configuration passed in. +//! +//! @param handle - handle for the interface. +//! @param eMSPIDevice - external device configuration for MSPI +//! +//! @return HAL status of the operation. +// +// +//***************************************************************************** +static uint32_t +mspi_device_configure(void *pHandle, uint32_t ui32MSPIDevice) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module = pMSPIState->ui32Module; + + switch ( ui32MSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 1; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 1; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_DUAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_DUAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_QUAD0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_QUAD1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_OCTAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1FF; + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_OCTAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1FF; + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + return AM_HAL_STATUS_INVALID_ARG; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 1; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1_1_1_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 1; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 3; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1_1_2_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 3; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 5; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1_1_1_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 5; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 7; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1_1_4_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 7; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + // Enable both D0 and D1 - as D1 might be getting used for DCX + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1_3WIRE: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + // Enable both D0 and D1 - as D1 might be getting used for DCX + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + default: + break; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +static void mspi_dummy_callback(void *pCallbackCtxt, uint32_t status) +{ + // Dummy - Do nothing +} + +static void mspi_seq_loopback(void *pCallbackCtxt, uint32_t status) +{ + // Reset the state to allow serving callbacks for next set + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pCallbackCtxt; + pMSPIState->ui32NumCQEntries = pMSPIState->ui32NumTransactions + 1; + pMSPIState->ui32LastIdxProcessed = 0; + pMSPIState->bRestart = true; + // Now resume the CQ - to finish loopback + // Resume the CQ + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_SEQLOOP; +} + +//***************************************************************************** +// +// External Functions. +// +//***************************************************************************** + +// +// MSPI initialization function +// +uint32_t +am_hal_mspi_initialize(uint32_t ui32Module, void **ppHandle) +{ + // Compile time check to ensure ENTRY_SIZE macros are defined correctly + // incorrect definition will cause divide by 0 error at build time + am_ct_assert((sizeof(am_hal_mspi_cq_dma_entry_t) + 8) == AM_HAL_MSPI_CQ_ENTRY_SIZE); + am_ct_assert(sizeof(am_hal_mspi_dma_entry_t) == AM_HAL_MSPI_HIPRIO_ENTRY_SIZE); + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check that the request module is in range. + // + if (ui32Module >= AM_REG_MSPI_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_MSPIState[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Initialize the handle. + // + g_MSPIState[ui32Module].prefix.s.bInit = true; + g_MSPIState[ui32Module].prefix.s.magic = AM_HAL_MAGIC_MSPI; + g_MSPIState[ui32Module].ui32Module = ui32Module; + + // + // Return the handle. + // + *ppHandle = (void *)&g_MSPIState[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI Disable function +// +uint32_t +am_hal_mspi_disable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Status; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_SUCCESS; + } + +#if MSPI_USE_CQ + + if (pMSPIState->pTCB) + { + // + // Disable the Command Queue. + // + ui32Status = mspi_cq_disable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Reset the Command Queue. + // + mspi_cq_term(pHandle); + } + +#endif // MSPI_USE_CQ + + pMSPIState->prefix.s.bEnable = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + + +// +// MSPI Deinitialize function +// +uint32_t +am_hal_mspi_deinitialize(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if (pMSPIState->prefix.s.bEnable) + { + am_hal_mspi_disable(pHandle); + } + + // + // Reset the handle. + // + pMSPIState->prefix.s.bInit = false; + pMSPIState->ui32Module = 0; + pMSPIState->eDeviceConfig = (am_hal_mspi_device_e)0; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI device configuration function +// +uint32_t +am_hal_mspi_device_configure(void *pHandle, + am_hal_mspi_dev_config_t *pConfig) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Config = 0; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Configure not allowed in Enabled state + // + if (pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + + // + // Set the clock polarity and phase based on SPI mode. + // + switch(pConfig->eSpiMode) + { + case AM_HAL_MSPI_SPI_MODE_0: // CPOL = 0; CPHA = 0 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 0) | + _VAL2FLD(MSPI_CFG_CPHA, 0); + break; + case AM_HAL_MSPI_SPI_MODE_2: // CPOL = 1; CPHA = 0 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 1) | + _VAL2FLD(MSPI_CFG_CPHA, 0); + break; + case AM_HAL_MSPI_SPI_MODE_1: // CPOL = 0; CPHA = 1 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 0) | + _VAL2FLD(MSPI_CFG_CPHA, 1); + break; + case AM_HAL_MSPI_SPI_MODE_3: // CPOL = 1; CPHA = 1 + ui32Config |= _VAL2FLD(MSPI_CFG_CPOL, 1) | + _VAL2FLD(MSPI_CFG_CPHA, 1); + break; + } + + // + // Set the number of turn-around cycles. + // + ui32Config |= _VAL2FLD(MSPI_CFG_TURNAROUND, pConfig->ui8TurnAround); + + // + // Set the address configuration. + // + ui32Config |= _VAL2FLD(MSPI_CFG_ASIZE, pConfig->eAddrCfg); + + // + // Set the instruction configuration. + // + ui32Config |= _VAL2FLD(MSPI_CFG_ISIZE, pConfig->eInstrCfg); + + // + // Set the configuration in the MSPI peripheral. + // + MSPIn(ui32Module)->CFG = ui32Config; + + // + // Set the clock divisor to get the desired MSPI clock frequency. + // + MSPIn(ui32Module)->MSPICFG_b.CLKDIV = pConfig->eClockFreq; + + // + // Adjust the clock edge configuration depending upon the clock frequency. + // + if ( pConfig->eClockFreq == AM_HAL_MSPI_CLK_48MHZ ) + { + MSPIn(ui32Module)->MSPICFG_b.TXNEG = 1; + MSPIn(ui32Module)->MSPICFG_b.RXNEG = 0; + MSPIn(ui32Module)->MSPICFG_b.RXCAP = 1; + } + else + { + MSPIn(ui32Module)->MSPICFG_b.TXNEG = 0; + MSPIn(ui32Module)->MSPICFG_b.RXNEG = 0; + MSPIn(ui32Module)->MSPICFG_b.RXCAP = 1; + } + + // + // Set the APBCLK for continuous operation. + // + MSPIn(ui32Module)->MSPICFG_b.APBCLK = 1; + + // + // Reset the register storage for next write. + // + ui32Config = 0; + + // + // Set whether to send an instruction. + // + if ( pConfig->bSendInstr ) + { + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPSENDI, 1); + } + + // + // Set whether to send an address. + // + if ( pConfig->bSendAddr ) + { + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPSENDA, 1); + } + + // + // Set whether to enable the TX to RX turnaround. + // + if ( pConfig->bTurnaround ) + { + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPENTURN, 1); + } + + // + // Set to Little Endian mode by default. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPBIGENDIAN, pMSPIState->bBigEndian); + + // + // Set the XIP ACK value to default to 1's during latency period. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_XIPACK, MSPI_FLASH_XIPACK_TERMINATE); + + // + // Set the read instruction. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_READINSTR, pConfig->ui8ReadInstr); + + // + // Set the write instruction. + // + ui32Config |= _VAL2FLD(MSPI_FLASH_WRITEINSTR, pConfig->ui8WriteInstr); + + // + // Set the configuration in the MSPI peripheral. + // + MSPIn(ui32Module)->FLASH = ui32Config; + + g_MSPIState[ui32Module].pTCB = pConfig->pTCB; + g_MSPIState[ui32Module].ui32TCBSize = pConfig->ui32TCBSize; + + if (pConfig->pTCB) + { + // set the DMABCOUNT + MSPIn(ui32Module)->DMABCOUNT = AM_HAL_MSPI_DEFAULT_BURST_COUNT; + + // set the DMATHRESH + MSPIn(ui32Module)->DMATHRESH = AM_HAL_MSPI_DEFAULT_BURST_COUNT >> 2; + // Worst case minimum CQ entries that can be accomodated in provided buffer + // Need to account for the wrap + g_MSPIState[ui32Module].ui32MaxPending = ((pConfig->ui32TCBSize - 8) * 4 / AM_HAL_MSPI_CQ_ENTRY_SIZE); + if (g_MSPIState[ui32Module].ui32MaxPending > AM_HAL_MSPI_MAX_CQ_ENTRIES) + { + g_MSPIState[ui32Module].ui32MaxPending = AM_HAL_MSPI_MAX_CQ_ENTRIES; + } + } + + // + // Reset the register storage for next write. + // + ui32Config = 0; + + // + // Set the scrambling start and end addresses aligned to 64K region. + // + MSPIn(ui32Module)->SCRAMBLING = + _VAL2FLD(MSPI_SCRAMBLING_SCRSTART, pConfig->scramblingStartAddr >> 16) | + _VAL2FLD(MSPI_SCRAMBLING_SCREND, pConfig->scramblingEndAddr >> 16); + + // + // Set the selected IOM to disable. + // + MSPIn(ui32Module)->MSPICFG_b.IOMSEL = 7; + + { + mspi_device_info_t MSPIDeviceInfo; + uint32_t ui32DeviceConfig; + uint32_t ui32Status; + + // + // Determine the virtual device configuration. + // + MSPIDeviceInfo.eDeviceConfig = pConfig->eDeviceConfig; + MSPIDeviceInfo.eXipMixedMode = pConfig->eXipMixedMode; + MSPIDeviceInfo.bSeparateIO = pConfig->bSeparateIO; + ui32Status = mspi_virtual_device(&MSPIDeviceInfo, &ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Configure the MSPI for a specific device configuration. + // This function sets the following registers/fields: + // CFG.DEVCFG + // CFG.SEPIO + // FLASH.XIPMIXED + // PADCFG + // PADOUTEN + // + mspi_device_configure(pHandle, ui32DeviceConfig); + } + + // + // Set the default endianess for the FIFO. + // + pMSPIState->bBigEndian = false; + + // + // Store the clock frequency for later SW workarounds. + // + pMSPIState->eClockFreq = pConfig->eClockFreq; + + // + // Set the default maximum delay timeout value. + // + pMSPIState->waitTimeout = 10000; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI device configuration function +// +uint32_t +am_hal_mspi_enable(void *pHandle) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + + if (pMSPIState->pTCB) + { + pMSPIState->ui32LastIdxProcessed = 0; + pMSPIState->ui32NumCQEntries = 0; + +#if MSPI_USE_CQ + + // + // Initialize the Command Queue service with memory supplied by the application. + // + mspi_cq_init(pMSPIState->ui32Module, pMSPIState->ui32TCBSize, pMSPIState->pTCB); + // Initialize Flags used to force CQ Pause + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_CQ | AM_HAL_MSPI_SC_PAUSE_SEQLOOP; + pMSPIState->pHPTransactions = NULL; + pMSPIState->bHP = false; + pMSPIState->ui32NumHPPendingEntries = 0; + pMSPIState->block = 0; + pMSPIState->ui32NumHPEntries = 0; + pMSPIState->eSeq = AM_HAL_MSPI_SEQ_NONE; + pMSPIState->ui32NumTransactions = 0; + pMSPIState->bAutonomous = true; + pMSPIState->ui32NumUnSolicited = 0; + +#else + // Use the buffer for software queuing for DMA + // Determine the maximum number of transactions based on the memory provided + pMSPIState->ui32MaxTransactions = pMSPIState->ui32TCBSize * 4 / sizeof(am_hal_mspi_cq_dma_entry_t); + if (pMSPIState->ui32MaxTransactions > 0) + { + if (pMSPIState->ui32MaxTransactions > AM_HAL_MSPI_MAX_CQ_ENTRIES) + { + pMSPIState->ui32MaxTransactions = AM_HAL_MSPI_MAX_CQ_ENTRIES; + } + pMSPIState->ui32NextIdx = pMSPIState->ui32LastIdxProcessed + 1; + pMSPIState->pTransactions = (am_hal_mspi_cq_dma_entry_t *)pMSPIState->pTCB; + } + +#endif // MSPI_USE_CQ + } + + pMSPIState->prefix.s.bEnable = true; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI device specific control function. +// +uint32_t am_hal_mspi_control(void *pHandle, + am_hal_mspi_request_e eRequest, + void *pConfig) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_MSPI_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if (eRequest > AM_HAL_MSPI_REQ_MAX) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ui32Module = pMSPIState->ui32Module; + switch(eRequest) + { + case AM_HAL_MSPI_REQ_APBCLK: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Enable/Disable APBCLK. + // + MSPIn(ui32Module)->MSPICFG_b.APBCLK = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_FLAG_SETCLR: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (*((uint32_t *)pConfig) & AM_HAL_MSPI_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + MSPIn(ui32Module)->CQSETCLEAR = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_LINK_IOM: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (( *((uint32_t *)pConfig) >= AM_REG_IOM_NUM_MODULES ) && ( *((uint32_t *)pConfig) != AM_HAL_MSPI_LINK_IOM_NONE )) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Set the Linked IOM + // + MSPIn(ui32Module)->MSPICFG_b.IOMSEL = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_SCRAMB_DIS: + // + // Disable scrambling. + // + MSPIn(ui32Module)->SCRAMBLING_b.SCRENABLE = 0; + break; + + case AM_HAL_MSPI_REQ_SCRAMB_EN: + // + // Enable scrambling. + // + MSPIn(ui32Module)->SCRAMBLING_b.SCRENABLE = 1; + break; + + case AM_HAL_MSPI_REQ_XIPACK: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Enable/Disable XIPACK. + // + MSPIn(ui32Module)->FLASH_b.XIPACK = *((uint32_t *)pConfig); + break; + + case AM_HAL_MSPI_REQ_XIP_DIS: + // + // Disable XIP. + // + MSPIn(ui32Module)->FLASH_b.XIPEN = 0; + break; + + case AM_HAL_MSPI_REQ_XIP_EN: + // + // Enable XIP. + // + MSPIn(ui32Module)->FLASH_b.XIPEN = 1; + break; + + case AM_HAL_MSPI_REQ_DEVICE_CONFIG: +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_IN_USE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + { + uint32_t ui32DeviceConfig; + uint32_t ui32Status; + + // + // Determine the virtual device configuration. + // + ui32Status = mspi_virtual_device((mspi_device_info_t *)pConfig, &ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Configure the MSPI for a specific device configuration. + // This function sets the following registers/fields: + // CFG.DEVCFG + // CFG.SEPIO + // FLASH.XIPMIXED + // PADCFG + // PADOUTEN + // + ui32Status = mspi_device_configure(pHandle, ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + break; + + case AM_HAL_MSPI_REQ_PAUSE: + ui32Status = mspi_cq_pause(pMSPIState); + break; + + case AM_HAL_MSPI_REQ_UNPAUSE: + // Resume the CQ + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_CQ; + break; + + case AM_HAL_MSPI_REQ_SET_SEQMODE: + { + am_hal_mspi_seq_e eSeq; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pMSPIState->pTCB) + { + // No space for CMDQ + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + eSeq = *((bool *)pConfig) ? AM_HAL_MSPI_SEQ_UNDER_CONSTRUCTION: AM_HAL_MSPI_SEQ_NONE; + if (eSeq == pMSPIState->eSeq) + { + // Nothing to do + return AM_HAL_STATUS_SUCCESS; + } +#if 0 // We should be able to operate on sequence even if there are HP transactions in progress + // Make sure there is no high priority transaction in progress + if (pMSPIState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + switch (pMSPIState->eSeq) + { + case AM_HAL_MSPI_SEQ_RUNNING: + { + ui32Status = mspi_cq_pause(pMSPIState); + break; + } + case AM_HAL_MSPI_SEQ_NONE: + { + // Make sure there is no non-blocking transaction in progress + if (pMSPIState->ui32NumCQEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + break; + } + default: + ; + } + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // Reset the cmdq + am_hal_cmdq_reset(pMSPIState->CQ.pCmdQHdl); + pMSPIState->ui32LastIdxProcessed = 0; + pMSPIState->ui32NumTransactions = 0; + pMSPIState->ui32NumCQEntries = 0; + pMSPIState->eSeq = eSeq; + pMSPIState->bAutonomous = true; + pMSPIState->ui32NumUnSolicited = 0; + } + break; + } + + case AM_HAL_MSPI_REQ_SEQ_END: + { + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t index; + am_hal_mspi_seq_end_t *pLoop = (am_hal_mspi_seq_end_t *)pConfig; + uint32_t pause = 0; + uint32_t scUnpause = 0; + uint32_t ui32Critical = 0; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32PauseCondition & AM_HAL_MSPI_PAUSE_FLAG_RESV) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pLoop->ui32StatusSetClr & AM_HAL_MSPI_SC_RESV_MASK) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pMSPIState->eSeq != AM_HAL_MSPI_SEQ_UNDER_CONSTRUCTION) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + if (pMSPIState->block) + { + // End the block if the sequence is ending + pMSPIState->block = 0; + // Unblock the whole batch of commands in this block + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_BLOCK; + } + if ((pLoop->bLoop) && (!pMSPIState->bAutonomous)) + { + // Need to insert special element in CQ to cause a callback + // This is to reset internal state + ui32Status = am_hal_cmdq_alloc_block(pMSPIState->CQ.pCmdQHdl, 1, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = mspi_seq_loopback; + pMSPIState->pCallbackCtxt[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = (void *)pMSPIState; + + // Dummy Entry + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; + pCQBlock->value = 0; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + // + // Post to the CQ. + // + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, true); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + return ui32Status; + } + else + { + uint32_t ui32NumPend = pMSPIState->ui32NumCQEntries++; + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + // Use SWFLAG6 to cause a pause + pause = AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP; + // Revert back the flag after SW callback unpauses it + scUnpause = AM_HAL_MSPI_SC_PAUSE_SEQLOOP; + } + } + // Insert the loopback + ui32Status = am_hal_cmdq_alloc_block(pMSPIState->CQ.pCmdQHdl, sizeof(am_hal_mspi_cq_loop_entry_t) / 8, &pCQBlock, &index); + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + return ui32Status; + } + else + { + am_hal_mspi_cq_loop_entry_t *pLoopEntry = (am_hal_mspi_cq_loop_entry_t *)pCQBlock; + pLoopEntry->ui32PAUSENAddr = pLoopEntry->ui32PAUSEN2Addr = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pLoopEntry->ui32SETCLRAddr = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; + pLoopEntry->ui32PAUSEENVal = get_pause_val(pMSPIState, pLoop->ui32PauseCondition | pause); + pLoopEntry->ui32PAUSEEN2Val = AM_HAL_MSPI_PAUSE_DEFAULT; + pLoopEntry->ui32SETCLRVal = pLoop->ui32StatusSetClr | scUnpause; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post to the CQ. + // + if (pLoop->bLoop) + { + ui32Status = am_hal_cmdq_post_loop_block(pMSPIState->CQ.pCmdQHdl, false); + } + else + { + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, false); + } + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + } + else + { + uint32_t ui32NumPend = pMSPIState->ui32NumCQEntries++; + pMSPIState->eSeq = (pLoop->bLoop) ? AM_HAL_MSPI_SEQ_RUNNING : AM_HAL_MSPI_SEQ_NONE; + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + } + return ui32Status; + //break; + } + + case AM_HAL_MSPI_REQ_INIT_HIPRIO: + { + am_hal_mspi_hiprio_cfg_t *pHPCfg = (am_hal_mspi_hiprio_cfg_t *)pConfig; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pConfig) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pMSPIState->pHPTransactions) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + pMSPIState->ui32NumHPEntries = pMSPIState->ui32LastHPIdxProcessed = 0; + pMSPIState->ui32NextHPIdx = pMSPIState->ui32LastHPIdxProcessed + 1; + pMSPIState->pHPTransactions = (am_hal_mspi_dma_entry_t *)pHPCfg->pBuf; + pMSPIState->ui32MaxHPTransactions = pHPCfg->size / sizeof(am_hal_mspi_dma_entry_t); + break; + } + + case AM_HAL_MSPI_REQ_START_BLOCK: + // Pause the next block from proceeding till whole block is finished + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_PAUSE_BLOCK; + pMSPIState->block = 1; + pMSPIState->ui32NumHPPendingEntries = 0; + break; + + case AM_HAL_MSPI_REQ_END_BLOCK: + // Unblock the whole batch of commands in this block + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_BLOCK; + pMSPIState->block = 0; + if (pMSPIState->ui32NumHPPendingEntries) + { + // Now it is okay to let go of the block of HiPrio transactions + ui32Status = sched_hiprio(pMSPIState, pMSPIState->ui32NumHPPendingEntries); + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + pMSPIState->ui32NumHPPendingEntries = 0; + } + } + break; + + case AM_HAL_MSPI_REQ_CQ_RAW: + { +#if MSPI_USE_CQ + am_hal_mspi_cq_raw_t *pCqRaw = (am_hal_mspi_cq_raw_t *)pConfig; + am_hal_cmdq_entry_t *pCQBlock; + uint32_t ui32Critical = 0; + uint32_t ui32NumPend; + uint32_t index; + am_hal_mspi_callback_t pfnCallback1; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (!pCqRaw) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (!pMSPIState->CQ.pCmdQHdl) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Check to see if there is enough room in the CQ + // + if ((pMSPIState->ui32NumCQEntries == AM_HAL_MSPI_MAX_CQ_ENTRIES) || + (am_hal_cmdq_alloc_block(pMSPIState->CQ.pCmdQHdl, pCqRaw->numEntries + 3, &pCQBlock, &index))) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pCQBlock->value = get_pause_val(pMSPIState, pCqRaw->ui32PauseCondition); + pCQBlock++; + // Copy the CQ Entry contents + for (uint32_t i = 0; i < pCqRaw->numEntries; i++, pCQBlock++) + { + pCQBlock->address = pCqRaw->pCQEntry[i].address; + pCQBlock->value = pCqRaw->pCQEntry[i].value; + } + // If there is a need - populate the jump back address + if (pCqRaw->pJmpAddr) + { + *(pCqRaw->pJmpAddr) = (uint32_t)pCQBlock; + } + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQPAUSE; + pCQBlock->value = AM_HAL_MSPI_PAUSE_DEFAULT; + pCQBlock++; + pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; + pCQBlock->value = pCqRaw->ui32StatusSetClr; + + pfnCallback1 = pCqRaw->pfnCallback; + if ( !pfnCallback1 && !pMSPIState->block && (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_NONE) && + (pMSPIState->ui32NumUnSolicited >= (pMSPIState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumCQEntries get updated in ISR + pfnCallback1 = mspi_dummy_callback; + } + // + // Store the callback function pointer. + // + pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pfnCallback1; + pMSPIState->pCallbackCtxt[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pCqRaw->pCallbackCtxt; + + // + // Need to protect access of ui32NumPendTransactions as it is accessed + // from ISR as well + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post the transaction to the CQ. + // Register for interrupt only if there is a callback + // + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pfnCallback1); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + } + else + { + ui32NumPend = pMSPIState->ui32NumCQEntries++; + pMSPIState->ui32NumTransactions++; + if (pCqRaw->pfnCallback) + { + pMSPIState->bAutonomous = false; + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + pMSPIState->ui32NumUnSolicited++; + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } +#else // !AM_HAL_MSPI_CQ + ui32Status = AM_HAL_STATUS_INVALID_ARG; +#endif + break; + } + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return ui32Status; +} + +// +// MSPI get capabilities +// +uint32_t am_hal_mspi_capabilities_get(void *pHandle, + am_hal_mspi_capabilities_t **pCapabilities) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // copy the pointer the MSPI instance capabilities into the passed pointer + // + *pCapabilities = &g_MSPIState[ui32Module].capabilities; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI blocking transfer function +// +uint32_t am_hal_mspi_blocking_transfer(void *pHandle, + am_hal_mspi_pio_transfer_t *pTransaction, + uint32_t ui32Timeout) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Control = 0; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t intMask; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + ui32Module = pMSPIState->ui32Module; + + // Make sure there is no non-blocking transaction in progress + if (pMSPIState->ui32NumCQEntries || pMSPIState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#if MSPI_USE_CQ + if (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + + // + // Set the number of bytes to transfer. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_XFERBYTES, pTransaction->ui32NumBytes); + + // + // Set the PIO default to scrambling disabled. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_PIOSCRAMBLE, pTransaction->bScrambling); + + // + // Set transmit or receive operation. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_TXRX, pTransaction->eDirection); + + // + // Set the indication to send an instruction and set the instruction value if + // we have a valid instruction. + // + if ( pTransaction->bSendInstr ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_SENDI, 1); + MSPIn(ui32Module)->INSTR = + _VAL2FLD(MSPI_INSTR_INSTR, pTransaction->ui16DeviceInstr); + } + + // + // Set the inidication to send an address and set the address value if we have + // a valid address. + // + if ( pTransaction->bSendAddr ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_SENDA, 1); + MSPIn(ui32Module)->ADDR = + _VAL2FLD(MSPI_ADDR_ADDR, pTransaction->ui32DeviceAddr); + } + + // + // Set the turn-around if needed. + // + if ( pTransaction->bTurnaround ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_ENTURN, 1); + } + + // + // Set the default FIFO Little Endian format. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_BIGENDIAN, pMSPIState->bBigEndian); + + // + // Set the Quad Command if this is transmit and the device is configured + // for Dual Quad mode. + // + if ( pTransaction->bQuadCmd ) + { + ui32Control |= _VAL2FLD(MSPI_CTRL_QUADCMD, 1); + } + + // + // Start the Transfer. + // + ui32Control |= _VAL2FLD(MSPI_CTRL_START, 1); + + // Disable all interrupts + intMask = MSPIn(ui32Module)->INTEN; + MSPIn(ui32Module)->INTEN = 0; + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + + // + // Initiate the Transfer. + // + MSPIn(ui32Module)->CTRL = ui32Control; + + // + // Read or Feed the FIFOs. + // + if ( AM_HAL_MSPI_RX == pTransaction->eDirection ) + { + ui32Status = mspi_fifo_read(ui32Module, pTransaction->pui32Buffer, + pTransaction->ui32NumBytes, pMSPIState->waitTimeout); + } + else if ( AM_HAL_MSPI_TX == pTransaction->eDirection ) + { + ui32Status = mspi_fifo_write(ui32Module, pTransaction->pui32Buffer, + pTransaction->ui32NumBytes, pMSPIState->waitTimeout ); + } + + // + // Check status. + // + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // Restore interrupts + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + MSPIn(ui32Module)->INTEN = intMask; + return ui32Status; + } + + // + // Wait for the command to complete. + // + ui32Status = am_hal_flash_delay_status_check(ui32Timeout, + (uint32_t)&MSPIn(ui32Module)->CTRL, + MSPI_CTRL_STATUS_Msk, + _VAL2FLD(MSPI_CTRL_STATUS, 1), + true); + + // + // Restore interrupts + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + MSPIn(ui32Module)->INTEN = intMask; + + // + // Return the status. + // + return ui32Status; + +} + +// +// MSPI Non-Blocking transfer function +// +uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, + void *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + uint32_t ui32NumPend; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pMSPIState->pTCB) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + +#if MSPI_USE_CQ +#if 0 // We should be able to queue up the CQ even if high priority transaction is in progress + if (pMSPIState->ui32NumHPEntries) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif + if (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_RUNNING) + { + // Dynamic additions to sequence not allowed + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif +#endif // AM_HAL_DISABLE_API_VALIDATION + +#if MSPI_USE_CQ + am_hal_mspi_callback_t pfnCallback1 = pfnCallback; + if ( !pfnCallback1 && !pMSPIState->block && (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_NONE) && + (pMSPIState->ui32NumUnSolicited >= (pMSPIState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumCQEntries get updated in ISR + pfnCallback1 = mspi_dummy_callback; + } + // + // DMA defaults to using the Command Queue + // + ui32Status = mspi_cq_add_transaction(pHandle, pTransfer, eMode, pfnCallback1, pCallbackCtxt); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + else + { + + uint32_t ui32Critical = 0; + + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); + + // + // Post the transaction to the CQ. + // + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pfnCallback1); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + + am_hal_cmdq_release_block(pMSPIState->CQ.pCmdQHdl); + } + else + { + ui32NumPend = pMSPIState->ui32NumCQEntries++; + pMSPIState->ui32NumTransactions++; + if (pfnCallback) + { + pMSPIState->bAutonomous = false; + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + pMSPIState->ui32NumUnSolicited++; + } + } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); + if (ui32NumPend == 0) + { + // + // Enable the Command Queue + // + ui32Status = mspi_cq_enable(pHandle); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + } + +#else + if (pMSPIState->ui32MaxTransactions == 0) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + if (AM_HAL_MSPI_TRANS_DMA != eMode) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + ui32Status = mspi_dma_add_transaction(pHandle, pTransfer, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + ui32NumPend = pMSPIState->ui32NumCQEntries++; + + // + // End the critical section. + // + AM_CRITICAL_END + + + if (0 == ui32NumPend) + { + uint32_t index = (pMSPIState->ui32LastIdxProcessed + 1) % pMSPIState->ui32MaxTransactions; + + pMSPIState->ui32TxnInt = 0; + // + // Run the command list + // + run_txn_cmdlist(&pMSPIState->pTransactions[index], sizeof(am_hal_mspi_cq_dma_entry_t) / sizeof(am_hal_cmdq_entry_t)); + } + } + +#endif // !MSPI_USE_CQ + + // + // Return the status. + // + return ui32Status; +} + +// +// MSPI status function +// +uint32_t am_hal_mspi_status_get(void *pHandle, + am_hal_mspi_status_t *pStatus ) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Get the Command Complete status. + // + // TODO: Need to implement. + + // + // Get the FIFO status. + // + // TODO: Need to implement. + + // + // Get the DMA status. + // + pStatus->bErr = ((MSPIn(ui32Module)->DMASTAT & MSPI_DMASTAT_DMAERR_Msk) > 0); + pStatus->bCmp = ((MSPIn(ui32Module)->DMASTAT & MSPI_DMASTAT_DMACPL_Msk) > 0); + pStatus->bTIP = ((MSPIn(ui32Module)->DMASTAT & MSPI_DMASTAT_DMATIP_Msk) > 0); + + // + // Get the CQ status. + // + // TODO: Need to implement. + pStatus->ui32NumCQEntries = pMSPIState->ui32NumCQEntries; + + // + // Get the scrambling status. + // + // TODO: Need to implement. + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI enable interrupts function +// +uint32_t am_hal_mspi_interrupt_enable(void *pHandle, + uint32_t ui32IntMask) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Set the interrupt enables according to the mask. + // + MSPIn(ui32Module)->INTEN |= ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI disable interrupts function +// +uint32_t am_hal_mspi_interrupt_disable(void *pHandle, + uint32_t ui32IntMask) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Clear the interrupt enables according to the mask. + // + MSPIn(ui32Module)->INTEN &= ~ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI interrupt status function +// +uint32_t am_hal_mspi_interrupt_status_get(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // if requested, only return the interrupts that are enabled. + // + if ( bEnabledOnly ) + { + uint32_t ui32RetVal = MSPIn(ui32Module)->INTSTAT; + *pui32Status = ui32RetVal & MSPIn(ui32Module)->INTEN; + } + else + { + *pui32Status = MSPIn(ui32Module)->INTSTAT; + } + + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI interrupt clear +// +uint32_t am_hal_mspi_interrupt_clear(void *pHandle, + uint32_t ui32IntMask) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if ( !AM_HAL_MSPI_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // clear the requested interrupts. + // + MSPIn(ui32Module)->INTCLR = ui32IntMask; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI interrupt service routine +// +uint32_t am_hal_mspi_interrupt_service(void *pHandle, uint32_t ui32IntStatus) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Module; + uint32_t ui32Status; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + ui32Module = pMSPIState->ui32Module; + // + // Add a delay to help make the service function work. + // TODO - why do we need this? + // +// am_hal_flash_delay(FLASH_CYCLES_US(10)); + +#if MSPI_USE_CQ + if (pMSPIState->bHP) + { +#if 0 + if (ui32IntStatus & AM_HAL_MSPI_INT_CQUPD) + { + while(1); + } +#endif + // + // Accumulate the INTSTAT for this transaction + // + pMSPIState->ui32TxnInt |= ui32IntStatus; + + // + // We need to wait for the DMA complete as well + // + if (pMSPIState->ui32TxnInt & (AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_ERR)) + { + uint32_t index; + + // + // Wait for the command completion + // + if (!(pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_CMDCMP)) + { + // TODO - We are waiting for CMDCMP indefinetely in the ISR + // May need to re-evaluate + while (!MSPIn(ui32Module)->INTSTAT_b.CMDCMP); + } + pMSPIState->ui32TxnInt |= MSPIn(ui32Module)->INTSTAT; + + // + // Clear the interrupt status + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + + // + // Need to determine the error, call the callback with proper status + // + if (pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_ERR) + { + ui32Status = AM_HAL_STATUS_FAIL; + + // + // Disable DMA + // + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Must reset xfer block + // + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 0; // in reset + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 1; // back out -- clears current transfer + } + else + { + ui32Status = AM_HAL_STATUS_SUCCESS; + } + + pMSPIState->ui32LastHPIdxProcessed++; + pMSPIState->ui32NumHPEntries--; + index = pMSPIState->ui32LastHPIdxProcessed % pMSPIState->ui32MaxHPTransactions; + am_hal_mspi_dma_entry_t *pDMAEntry = &pMSPIState->pHPTransactions[index]; + + // + // Call the callback + // + if ( pDMAEntry->pfnCallback != NULL ) + { + pDMAEntry->pfnCallback(pDMAEntry->pCallbackCtxt, ui32Status); + pDMAEntry->pfnCallback = NULL; + } + + // + // Post next transaction if queue is not empty + // + if (pMSPIState->ui32NumHPEntries) + { + pMSPIState->ui32TxnInt = 0; + program_dma(pMSPIState); + } + else + { + pMSPIState->bHP = false; + // Unpause the CQ + // + // Command to set the DMACFG to disable DMA. + // Need to make sure we disable DMA before we can reprogram + // + MSPIn(ui32Module)->DMACFG = _VAL2FLD(MSPI_DMACFG_DMAEN, 0); + // Restore interrupts + MSPIn(ui32Module)->INTEN &= ~(AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_CMDCMP); + // Resume the CQ + MSPIn(ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_UNPAUSE_CQ; + } + } + return AM_HAL_STATUS_SUCCESS; + } +#endif + // + // Need to check if there is an ongoing transaction + // This is needed because we may get interrupts even for the XIP transactions + // + if (pMSPIState->ui32NumCQEntries) + { +#if MSPI_USE_CQ + am_hal_cmdq_status_t status; + uint32_t index; + am_hal_mspi_CQ_t *pCQ = &g_MSPIState[ui32Module].CQ; + + // + // Get the current and last indexes. + // + if (pCQ->pCmdQHdl) + { + ui32Status = am_hal_cmdq_get_status(pCQ->pCmdQHdl, &status); + + if (AM_HAL_STATUS_SUCCESS == ui32Status) + { + // For Sequence - this can be updated in the callback + pMSPIState->bRestart = false; + // + // Figure out which callbacks need to be handled. + // + while (!pMSPIState->bRestart && (pMSPIState->ui32LastIdxProcessed != status.lastIdxProcessed)) + { + + pMSPIState->ui32LastIdxProcessed++; + pMSPIState->ui32NumCQEntries--; + index = pMSPIState->ui32LastIdxProcessed & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1); + if ( pMSPIState->pfnCallback[index] != NULL ) + { + pMSPIState->pfnCallback[index](pMSPIState->pCallbackCtxt[index], AM_HAL_STATUS_SUCCESS); + if (pMSPIState->eSeq != AM_HAL_MSPI_SEQ_RUNNING) + { + pMSPIState->pfnCallback[index] = NULL; + } + } + } + + // For Sequence - this can be updated in the callback + if (!pMSPIState->bRestart) + { + // + // Process one extra callback if there was an error. + // + if ( (ui32IntStatus & AM_HAL_MSPI_INT_ERR) || (status.bErr) ) + { + pMSPIState->ui32LastIdxProcessed++; + pMSPIState->ui32NumCQEntries--; + index = pMSPIState->ui32LastIdxProcessed & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1); + if ( pMSPIState->pfnCallback[index] != NULL ) + { + pMSPIState->pfnCallback[index](pMSPIState->pCallbackCtxt[index], AM_HAL_STATUS_FAIL); + if (pMSPIState->eSeq != AM_HAL_MSPI_SEQ_RUNNING) + { + pMSPIState->pfnCallback[index] = NULL; + } + } + // Disable CQ + ui32Status = mspi_cq_disable(pMSPIState); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + // Disable DMA + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + + // Must reset xfer block + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 0; // in reset + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 1; // back out -- clears current transfer + + // Clear the CQ error. + MSPIn(ui32Module)->CQSTAT |= _VAL2FLD(MSPI_CQSTAT_CQERR, 0); + am_hal_cmdq_error_resume(pCQ->pCmdQHdl); + if (pMSPIState->ui32NumCQEntries) + { + // Re-enable CQ + ui32Status = mspi_cq_enable(pMSPIState); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + if (pMSPIState->ui32NumCQEntries == 0) + { + // Disable CQ + ui32Status = mspi_cq_disable(pMSPIState); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + } + } + } +#else + // + // Accumulate the INTSTAT for this transaction + // + pMSPIState->ui32TxnInt |= ui32IntStatus; + + // + // We need to wait for the DMA complete as well + // + if (pMSPIState->ui32TxnInt & (AM_HAL_MSPI_INT_DMACMP | AM_HAL_MSPI_INT_ERR)) + { + uint32_t index; + + // + // Wait for the command completion + // + if (!(pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_CMDCMP)) + { + // TODO - We are waiting for CMDCMP indefinetely in the ISR + // May need to re-evaluate + while (!MSPIn(ui32Module)->INTSTAT_b.CMDCMP); + } + pMSPIState->ui32TxnInt |= MSPIn(ui32Module)->INTSTAT; + + // + // Clear the interrupt status + // + MSPIn(ui32Module)->INTCLR = AM_HAL_MSPI_INT_ALL; + + // + // Need to determine the error, call the callback with proper status + // + if (pMSPIState->ui32TxnInt & AM_HAL_MSPI_INT_ERR) + { + ui32Status = AM_HAL_STATUS_FAIL; + + // + // Disable DMA + // + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + + // + // Must reset xfer block + // + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 0; // in reset + MSPIn(ui32Module)->MSPICFG_b.IPRSTN = 1; // back out -- clears current transfer + } + else + { + ui32Status = AM_HAL_STATUS_SUCCESS; + } + + pMSPIState->ui32LastIdxProcessed++; + pMSPIState->ui32NumCQEntries--; + index = pMSPIState->ui32LastIdxProcessed % pMSPIState->ui32MaxTransactions; + + // + // Call the callback + // + if ( pMSPIState->pfnCallback[index] != NULL ) + { + pMSPIState->pfnCallback[index](pMSPIState->pCallbackCtxt[index], ui32Status); + pMSPIState->pfnCallback[index] = NULL; + } + + // + // Post next transaction if queue is not empty + // + if (pMSPIState->ui32NumCQEntries) + { + index = (pMSPIState->ui32LastIdxProcessed + 1) % pMSPIState->ui32MaxTransactions; + + pMSPIState->ui32TxnInt = 0; + run_txn_cmdlist(&pMSPIState->pTransactions[index], sizeof(am_hal_mspi_cq_dma_entry_t) / sizeof(am_hal_cmdq_entry_t)); + } + } + +#endif // !MSPI_USE_CQ + + if (pMSPIState->ui32NumCQEntries == 0) + { + // Disable DMA + MSPIn(ui32Module)->DMACFG_b.DMAEN = 0; + } + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI power control function +// +uint32_t am_hal_mspi_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Decode the requested power state and update MSPI operation accordingly. + // + switch (ePowerState) + { + case AM_HAL_SYSCTRL_WAKE: + + if (bRetainState && !pMSPIState->registerState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_MSPI)); + + if (bRetainState) + { + // + // Restore MSPI registers + // + MSPIn(pMSPIState->ui32Module)->CFG = pMSPIState->registerState.regCFG; + MSPIn(pMSPIState->ui32Module)->MSPICFG = pMSPIState->registerState.regMSPICFG; + MSPIn(pMSPIState->ui32Module)->PADCFG = pMSPIState->registerState.regPADCFG; + MSPIn(pMSPIState->ui32Module)->PADOUTEN = pMSPIState->registerState.regPADOUTEN; + MSPIn(pMSPIState->ui32Module)->FLASH = pMSPIState->registerState.regFLASH; + MSPIn(pMSPIState->ui32Module)->SCRAMBLING = pMSPIState->registerState.regSCRAMBLING; + MSPIn(pMSPIState->ui32Module)->CQADDR = pMSPIState->registerState.regCQADDR; + MSPIn(pMSPIState->ui32Module)->CQPAUSE = pMSPIState->registerState.regCQPAUSE; + MSPIn(pMSPIState->ui32Module)->CQCURIDX = pMSPIState->registerState.regCQCURIDX; + MSPIn(pMSPIState->ui32Module)->CQENDIDX = pMSPIState->registerState.regCQENDIDX; + MSPIn(pMSPIState->ui32Module)->INTEN = pMSPIState->registerState.regINTEN; + + // TODO: May be we can just set these values, as they are constants anyways? + MSPIn(pMSPIState->ui32Module)->DMABCOUNT = pMSPIState->registerState.regDMABCOUNT; + MSPIn(pMSPIState->ui32Module)->DMATHRESH = pMSPIState->registerState.regDMATHRESH; + + // CQFGLAGS are Read-Only and hence can not be directly restored. + // We can try to restore the SWFlags here. Hardware flags depend on external conditions + // and hence can not be restored (assuming the external conditions remain the same, it should be set automatically. + MSPIn(pMSPIState->ui32Module)->CQSETCLEAR = AM_HAL_MSPI_SC_SET(pMSPIState->registerState.regCQFLAGS & 0xFF); + // + // Set the CQCFG last + // + MSPIn(pMSPIState->ui32Module)->CQCFG = pMSPIState->registerState.regCQCFG; + + pMSPIState->registerState.bValid = false; + } + break; + + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + // Make sure MPSI is not active currently + if (pMSPIState->prefix.s.bEnable && + ((MSPIn(pMSPIState->ui32Module)->DMASTAT_b.DMATIP) || + pMSPIState->ui32NumHPPendingEntries)) + { + return AM_HAL_STATUS_IN_USE; + } + if (bRetainState) + { + // + // Save MSPI Registers + // + pMSPIState->registerState.regCFG = MSPIn(pMSPIState->ui32Module)->CFG; + pMSPIState->registerState.regMSPICFG = MSPIn(pMSPIState->ui32Module)->MSPICFG; + pMSPIState->registerState.regPADCFG = MSPIn(pMSPIState->ui32Module)->PADCFG; + pMSPIState->registerState.regPADOUTEN = MSPIn(pMSPIState->ui32Module)->PADOUTEN; + pMSPIState->registerState.regFLASH = MSPIn(pMSPIState->ui32Module)->FLASH; + pMSPIState->registerState.regSCRAMBLING = MSPIn(pMSPIState->ui32Module)->SCRAMBLING; + pMSPIState->registerState.regCQADDR = MSPIn(pMSPIState->ui32Module)->CQADDR; + pMSPIState->registerState.regCQPAUSE = MSPIn(pMSPIState->ui32Module)->CQPAUSE; + pMSPIState->registerState.regCQFLAGS = MSPIn(pMSPIState->ui32Module)->CQFLAGS; + pMSPIState->registerState.regCQCURIDX = MSPIn(pMSPIState->ui32Module)->CQCURIDX; + pMSPIState->registerState.regCQENDIDX = MSPIn(pMSPIState->ui32Module)->CQENDIDX; + pMSPIState->registerState.regINTEN = MSPIn(pMSPIState->ui32Module)->INTEN; + + // TODO: May be no need to store these values, as they are constants anyways? + pMSPIState->registerState.regDMABCOUNT = MSPIn(pMSPIState->ui32Module)->DMABCOUNT; + pMSPIState->registerState.regDMATHRESH = MSPIn(pMSPIState->ui32Module)->DMATHRESH; + + pMSPIState->registerState.regCQCFG = MSPIn(pMSPIState->ui32Module)->CQCFG; + pMSPIState->registerState.bValid = true; + } + + // + // Disable all the interrupts. + // + am_hal_mspi_interrupt_disable(pHandle, MSPI_INTEN_SCRERR_Msk | + MSPI_INTEN_CQERR_Msk | + MSPI_INTEN_CQPAUSED_Msk | + MSPI_INTEN_CQUPD_Msk | + MSPI_INTEN_CQCMP_Msk | + MSPI_INTEN_DERR_Msk | + MSPI_INTEN_DCMP_Msk | + MSPI_INTEN_RXF_Msk | + MSPI_INTEN_RXO_Msk | + MSPI_INTEN_RXU_Msk | + MSPI_INTEN_TXO_Msk | + MSPI_INTEN_TXE_Msk | + MSPI_INTEN_CMDCMP_Msk); + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_MSPI)); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +// +// MSPI High Priority transfer function +// +uint32_t am_hal_mspi_highprio_transfer(void *pHandle, + am_hal_mspi_dma_transfer_t *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt) +{ + am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; + uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check the handle. + // + if (!AM_HAL_MSPI_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + if (!pMSPIState->pTCB) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (!pMSPIState->pHPTransactions) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + if (pTransfer->ui32PauseCondition != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (pTransfer->ui32StatusSetClr != 0) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } +#endif // AM_HAL_DISABLE_API_VALIDATION +#if MSPI_USE_CQ + + ui32Status = mspi_add_hp_transaction(pHandle, pTransfer, pfnCallback, pCallbackCtxt); + + if (ui32Status == AM_HAL_STATUS_SUCCESS) + { + if (!(pMSPIState->block)) + { + ui32Status = sched_hiprio(pMSPIState, 1); + } + else + { + pMSPIState->ui32NumHPPendingEntries++; + } + } + +#else + ui32Status = AM_HAL_STATUS_INVALID_OPERATION; +#endif // !MSPI_USE_CQ + + // + // Return the status. + // + return ui32Status; +} + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.h new file mode 100644 index 0000000000..21b0b7bf96 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_mspi.h @@ -0,0 +1,781 @@ +//***************************************************************************** +// +// am_hal_mspi.h +//! @file +//! +//! @brief Functions for accessing and configuring the MSPI. +//! +//! @addtogroup mspi3 Multi-bit SPI (MSPI) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_MSPI_H +#define AM_HAL_MSPI_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! CMSIS-Style macro for handling a variable MSPI module number. +// +//***************************************************************************** +#define MSPIn(n) ((MSPI_Type*)(MSPI_BASE + (n * (MSPI_BASE - MSPI_BASE)))) + +// +// USE_CQ=1 will use the Command Queue in nonblocking transfers. +// 0 uses plain DMA (w/o CQ) in nonblocking transfers. +// +#define MSPI_USE_CQ 1 + +#define AM_HAL_MSPI_MAX_FIFO_SIZE 16 +#define AM_HAL_MSPI_DEFAULT_BURST_COUNT 32 + +// Size guideline for allocation of application supploed buffers +#define AM_HAL_MSPI_CQ_ENTRY_SIZE (18 * sizeof(uint32_t)) +#define AM_HAL_MSPI_HIPRIO_ENTRY_SIZE (6 * sizeof(uint32_t)) + +#define AM_HAL_MSPI_SC_CLEAR(flag) ((flag) << 16) +#define AM_HAL_MSPI_SC_SET(flag) ((flag)) + +// For MSPI - Need to Set the flag for unpausing +#define AM_HAL_MSPI_SC_UNPAUSE(flag) AM_HAL_MSPI_SC_SET(flag) +#define AM_HAL_MSPI_SC_PAUSE(flag) AM_HAL_MSPI_SC_CLEAR(flag) + +// Use this macro to directly control the flags +#define AM_HAL_MSPI_SETCLR(module, scVal) \ + do { \ + MSPIn(module)->CQSETCLEAR = (scVal); \ + } while (0); + +// Flags 5, 7 & 6 are reserved by HAL +#define AM_HAL_MSPI_PAUSE_FLAG_RESV (MSPI_CQFLAGS_CQFLAGS_SWFLAG7 | MSPI_CQFLAGS_CQFLAGS_SWFLAG6 | MSPI_CQFLAGS_CQFLAGS_SWFLAG5) +#define AM_HAL_MSPI_SC_RESV_MASK (AM_HAL_MSPI_PAUSE_FLAG_RESV | (AM_HAL_MSPI_PAUSE_FLAG_RESV << 8) | (AM_HAL_MSPI_PAUSE_FLAG_RESV << 16)) + +// We use SWFLAGEN7 to control SW pausing Command Queue - default unPause +// We use SWFLAGEN6 to pause on the sequece loopback - default Pause +// We use SWFLAGEN5 to pause CQ while a block is building +#define AM_HAL_MSPI_PAUSE_FLAG_IDX (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_CQIDX)) +#define AM_HAL_MSPI_PAUSE_FLAG_CQ (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_SWFLAG7)) +#define AM_HAL_MSPI_PAUSE_FLAG_SEQLOOP (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_SWFLAG6)) +#define AM_HAL_MSPI_PAUSE_FLAG_BLOCK (_VAL2FLD(MSPI_CQFLAGS_CQFLAGS, MSPI_CQFLAGS_CQFLAGS_SWFLAG5)) + +// By default - we Pause CQ for no more entries, or force pause from SW +#define AM_HAL_MSPI_PAUSE_DEFAULT (AM_HAL_MSPI_PAUSE_FLAG_IDX) +#define AM_HAL_MSPI_CQP_PAUSE_DEFAULT (AM_HAL_MSPI_PAUSE_FLAG_IDX | AM_HAL_MSPI_PAUSE_FLAG_CQ) + + //***************************************************************************** + // + //! @name MSPI Interrupts + //! @brief Macro definitions for MSPI interrupt status bits. + //! + //! These macros correspond to the bits in the MSPI interrupt status register. + //! + //! @{ + // + //***************************************************************************** +#define AM_HAL_MSPI_INT_SCRERR MSPI_INTEN_SCRERR_Msk +#define AM_HAL_MSPI_INT_CQERR MSPI_INTEN_CQERR_Msk +#define AM_HAL_MSPI_INT_CQPAUSED MSPI_INTEN_CQPAUSED_Msk +#define AM_HAL_MSPI_INT_CQUPD MSPI_INTEN_CQUPD_Msk +#define AM_HAL_MSPI_INT_CQCMP MSPI_INTEN_CQCMP_Msk +#define AM_HAL_MSPI_INT_DMAERR MSPI_INTEN_DERR_Msk +#define AM_HAL_MSPI_INT_DMACMP MSPI_INTEN_DCMP_Msk +#define AM_HAL_MSPI_INT_RX_FIFO_FULL MSPI_INTEN_RXF_Msk +#define AM_HAL_MSPI_INT_RX_FIFO_OVFL MSPI_INTEN_RXO_Msk +#define AM_HAL_MSPI_INT_RX_FIFO_UNFL MSPI_INTEN_RXU_Msk +#define AM_HAL_MSPI_INT_TX_FIFO_OVFL MSPI_INTEN_TXO_Msk +#define AM_HAL_MSPI_INT_TX_FIFO_EMPTY MSPI_INTEN_TXE_Msk +#define AM_HAL_MSPI_INT_CMDCMP MSPI_INTEN_CMDCMP_Msk +#define AM_HAL_MSPI_INT_ALL 0xFFFFFFFF + +#define AM_HAL_MSPI_INT_ERR (AM_HAL_MSPI_INT_DMAERR | AM_HAL_MSPI_INT_CQERR | AM_HAL_MSPI_INT_SCRERR) + + +#define AM_HAL_MSPI_LINK_IOM_NONE 0x7 + //***************************************************************************** + // + //! @brief Configuration structure for the MSPI. + // + //***************************************************************************** + + // + // Number of bytes in the address + // + typedef enum + { + AM_HAL_MSPI_ADDR_1_BYTE, + AM_HAL_MSPI_ADDR_2_BYTE, + AM_HAL_MSPI_ADDR_3_BYTE, + AM_HAL_MSPI_ADDR_4_BYTE + } am_hal_mspi_addr_e; + + // + // Number of bytes in the instruction + // + typedef enum + { + AM_HAL_MSPI_INSTR_1_BYTE, + AM_HAL_MSPI_INSTR_2_BYTE + } am_hal_mspi_instr_e; + + // + // Transmit or receive + // + typedef enum + { + AM_HAL_MSPI_RX = 0, + AM_HAL_MSPI_TX = 1 + } am_hal_mspi_dir_e; + + // + // Mode of Transfer. + // + typedef enum + { + AM_HAL_MSPI_TRANS_PIO, + AM_HAL_MSPI_TRANS_DMA + } am_hal_mspi_trans_e; + + // + // MSPI interface mode and chip enable selection + // + typedef enum + { + AM_HAL_MSPI_FLASH_SERIAL_CE0, + AM_HAL_MSPI_FLASH_SERIAL_CE1, + AM_HAL_MSPI_FLASH_DUAL_CE0, + AM_HAL_MSPI_FLASH_DUAL_CE1, + AM_HAL_MSPI_FLASH_QUAD_CE0, + AM_HAL_MSPI_FLASH_QUAD_CE1, + AM_HAL_MSPI_FLASH_OCTAL_CE0, + AM_HAL_MSPI_FLASH_OCTAL_CE1, + AM_HAL_MSPI_FLASH_QUADPAIRED, + AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL, + AM_HAL_MSPI_FLASH_MAX = AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL + } am_hal_mspi_device_e; + + // + // Enumerate the SPI modes. Note that these are arranged per the ordering of + // SPHA (bit1) and SPOL (bit0) in the IOM.MSPICFG register. + // + typedef enum + { + AM_HAL_MSPI_SPI_MODE_0, // CPOL = 0; CPHA = 0 + AM_HAL_MSPI_SPI_MODE_2, // CPOL = 1; CPHA = 0 + AM_HAL_MSPI_SPI_MODE_1, // CPOL = 0; CPHA = 1 + AM_HAL_MSPI_SPI_MODE_3, // CPOL = 1; CPHA = 1 + } am_hal_mspi_spi_mode_e; + + typedef enum + { + AM_HAL_MSPI_CLK_48MHZ = 1, + AM_HAL_MSPI_CLK_24MHZ = 2, + AM_HAL_MSPI_CLK_16MHZ = 3, + AM_HAL_MSPI_CLK_12MHZ = 4, + AM_HAL_MSPI_CLK_8MHZ = 6, + AM_HAL_MSPI_CLK_6MHZ = 8, + AM_HAL_MSPI_CLK_4P8MHZ = 10, + AM_HAL_MSPI_CLK_4MHZ = 12, + AM_HAL_MSPI_CLK_3P2MHZ = 15, + AM_HAL_MSPI_CLK_3MHZ = 16, + AM_HAL_MSPI_CLK_1P5MHZ = 32 + } am_hal_mspi_clock_e; + + // + // Transfer callback function prototype + // + typedef void (*am_hal_mspi_callback_t)(void *pCallbackCtxt, uint32_t status); + + typedef struct + { + bool bLoop; + //! Command Queue Transaction Gating + uint32_t ui32PauseCondition; + //! Command Queue Post-Transaction status setting + uint32_t ui32StatusSetClr; + } am_hal_mspi_seq_end_t; + + typedef struct + { + uint8_t *pBuf; // Buffer provided to store the high priority transaction context + uint32_t size; // Size of buffer in bytes + } am_hal_mspi_hiprio_cfg_t; + + typedef struct + { + //! Command Queue Advanced control on gating conditions for transaction to start + uint32_t ui32PauseCondition; + //! Command Queue Advanced Post-Transaction status setting + uint32_t ui32StatusSetClr; + am_hal_cmdq_entry_t *pCQEntry; + uint32_t numEntries; + am_hal_mspi_callback_t pfnCallback; + void *pCallbackCtxt; + uint32_t *pJmpAddr; + } am_hal_mspi_cq_raw_t; + + typedef enum + { + // Pass uint32_t as pConfig + AM_HAL_MSPI_REQ_APBCLK, + // Used to set/clear 8 CQ Pause flags - reserved flags are defined as AM_HAL_MSPI_PAUSE_FLAG_RESV + AM_HAL_MSPI_REQ_FLAG_SETCLR, + // Pass uint32_t as pConfig indicating the IOM# to link to. AM_HAL_MSPI_LINK_IOM_NONE indicates no IOM linked + AM_HAL_MSPI_REQ_LINK_IOM, + // pConfig N/A + AM_HAL_MSPI_REQ_SCRAMB_DIS, + // pConfig N/A + AM_HAL_MSPI_REQ_SCRAMB_EN, + // Pass uint32_t as pConfig + AM_HAL_MSPI_REQ_XIPACK, + // pConfig N/A + AM_HAL_MSPI_REQ_XIP_DIS, + // pConfig N/A + AM_HAL_MSPI_REQ_XIP_EN, + // Pass mspi_device_info_t as pConfig + AM_HAL_MSPI_REQ_DEVICE_CONFIG, + // Pause the CQ gracefully + AM_HAL_MSPI_REQ_PAUSE, + // Unpause the CQ + AM_HAL_MSPI_REQ_UNPAUSE, + // Get in and out of Sequence Mode - which allows building a sequence, which either runs once, or repeats + // Pass in bool as pConfig - true/false + AM_HAL_MSPI_REQ_SET_SEQMODE, + // Pass am_hal_mspi_seq_end_t * as pConfig + AM_HAL_MSPI_REQ_SEQ_END, + // Initialize configuration for high priority trasactions + // These transactions take precedence over existing CQ transactions + // Pass am_hal_mspi_hiprio_cfg_t * as pConfig + AM_HAL_MSPI_REQ_INIT_HIPRIO, + // Create a block of transactions which are not paused in between + // pConfig N/A + AM_HAL_MSPI_REQ_START_BLOCK, + // pConfig N/A + AM_HAL_MSPI_REQ_END_BLOCK, + // Raw CQ transaction + // Pass am_hal_mspi_cq_raw_t * as pConfig + AM_HAL_MSPI_REQ_CQ_RAW, + AM_HAL_MSPI_REQ_MAX + + } am_hal_mspi_request_e; + + typedef enum + { + AM_HAL_MSPI_XIPMIXED_NORMAL = 0, + AM_HAL_MSPI_XIPMIXED_D2 = 1, //1:1:2 timing for Instr:Addr:Data + AM_HAL_MSPI_XIPMIXED_AD2 = 3, //1:2:2 timing for Instr:Addr:Data + AM_HAL_MSPI_XIPMIXED_D4 = 5, //1:1:4 timing for Instr:Addr:Data + AM_HAL_MSPI_XIPMIXED_AD4 = 7 //1:4:4 timing for Instr:Addr:Data + } am_hal_mspi_xipmixed_mode_e; + + // + // Device configuration structure + // + typedef struct + { + // + // MSPI device configuration for Polling I/O (PIO) Operation. + // + + //! Number of turn around cycles between an Address write and Data read. + uint8_t ui8TurnAround; + + //! Address Configuration + am_hal_mspi_addr_e eAddrCfg; + + //! Instruction Configuration + am_hal_mspi_instr_e eInstrCfg; + + //! Read instruction sent to flash device + uint8_t ui8ReadInstr; + + //! Write instruction sent to flash device + uint8_t ui8WriteInstr; + + //! External Flash Device configuration + am_hal_mspi_device_e eDeviceConfig; + + // + // MSPI clock configuration. + // + + //! SPI Mode. + am_hal_mspi_spi_mode_e eSpiMode; + + //! Clock frequency + am_hal_mspi_clock_e eClockFreq; + + //! XIPMIXED configure + am_hal_mspi_xipmixed_mode_e eXipMixedMode; + + // + // MSPI device configuration for XIP/DMA/Scrambling operations. + // + + //! Send Device Address + bool bSendAddr; + + //! Send Device Instruction + bool bSendInstr; + + //! Separate MOSI/MISO + bool bSeparateIO; + + //! Enable Turnaround between Address write and Data read. + bool bTurnaround; + + // + // MSPI DMA TCB/Command Queue memory allocation. + // + + //! DMA Transfer Control Buffer size in words. + uint32_t ui32TCBSize; + + //! DMA Transfer Control Buffer + uint32_t *pTCB; + + // + // MSPI Scrambling configuration. + // + + //! Scrambling Start Address + uint32_t scramblingStartAddr; + + //! Scrambling End Address + uint32_t scramblingEndAddr; + + } am_hal_mspi_dev_config_t; + + // + // MSPI configuration record for determining virtual device configuration. + // + typedef struct + { + //! External Flash Device configuration + am_hal_mspi_device_e eDeviceConfig; + + //! XIPMIXED configure + am_hal_mspi_xipmixed_mode_e eXipMixedMode; + + //! Separate MOSI/MISO + bool bSeparateIO; + + } mspi_device_info_t; + // + // MSPI Capabilities structure + // + typedef struct + { + am_hal_mspi_device_e eDeviceConfig; + } am_hal_mspi_capabilities_t; + + // + // Device PIO transfer structure + // + typedef struct + { + //! Number of bytes to transfer + uint32_t ui32NumBytes; + + //! Enable scrambling. + bool bScrambling; + + //! Transfer Direction (Transmit/Receive) + am_hal_mspi_dir_e eDirection; + + //! Send Device Address + bool bSendAddr; + + //! Device Address + uint32_t ui32DeviceAddr; + + //! Send Device Instruction + bool bSendInstr; + + //! Device Instruction + uint16_t ui16DeviceInstr; + + //! Enable Turnaround between Address write and Data read. + bool bTurnaround; + + //! Paired-Quad + bool bQuadCmd; + + //! Buffer + uint32_t *pui32Buffer; + + } am_hal_mspi_pio_transfer_t; + + // + // DMA transfer structure + // + typedef struct + { + //! Address Configuration + am_hal_mspi_addr_e eAddrCfg; + + //! Priority 0 = Low (best effort); 1 = High (service immediately) + uint8_t ui8Priority; + + //! Direction RX: 0 = Peripheral to Memory; TX: 1 = Memory to Peripheral + am_hal_mspi_dir_e eDirection; + + //! Transfer Count + uint32_t ui32TransferCount; + + //! External Flash Device Address + uint32_t ui32DeviceAddress; + + //! Internal SRAM Address + uint32_t ui32SRAMAddress; + + //! Command Queue Transaction Gating + uint32_t ui32PauseCondition; + //! Command Queue Post-Transaction status setting + uint32_t ui32StatusSetClr; + + } am_hal_mspi_dma_transfer_t; + + + // + // MSPI status structure. + // + typedef struct + { + // + // DMA status. + // + bool bErr; + bool bCmp; + bool bTIP; + uint32_t ui32NumCQEntries; + } am_hal_mspi_status_t; + + +#define am_hal_mspi_buffer(A) \ + union \ + { \ + uint32_t words[(A + 3) >> 2]; \ + uint8_t bytes[A]; \ + } + + //***************************************************************************** + // + //! @brief MSPI initialization function + //! + //! @param ui32Module - module instance. + //! @param handle - returns the handle for the module instance. + //! + //! This function accepts a module instance, allocates the interface and then + //! returns a handle to be used by the remaining interface functions. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_initialize(uint32_t ui32Module, + void **ppHandle); + + //***************************************************************************** + // + //! @brief MSPI deinitialization function + //! + //! @param handle - the handle for the module instance. + //! + //! This function accepts a handle to an instance and de-initializes the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_deinitialize(void *pHandle); + + //***************************************************************************** + // + //! @brief MSPI device configuration function + //! + //! @param handle - handle for the interface. + //! @param pConfig - pointer to the configuration structure. + //! + //! This function configures the MSPI settings for a particular external flash device. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_device_configure(void *pHandle, + am_hal_mspi_dev_config_t *pConfig); + + //***************************************************************************** + // + //! @brief MSPI enable function + //! + //! @param handle - the handle for the module instance. + //! + //! This function accepts a handle to an instance and enables the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_enable(void *pHandle); + + //***************************************************************************** + // + //! @brief MSPI disable function + //! + //! @param handle - the handle for the module instance. + //! + //! This function accepts a handle to an instance and disables the + //! interface. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_disable(void *pHandle); + + //***************************************************************************** + // + //! @brief MSPI device specific control function. + //! + //! @param handle - handle for the interface. + //! @param request - device specific special request code. + //! @param pConfig - pointer to the request specific configuration. + //! + //! This function configures the MSPI settings for XIP or DMA operation. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_control(void *pHandle, + am_hal_mspi_request_e eRequest, + void *pConfig); + + //***************************************************************************** + // + //! @brief MSPI capability interrogation function + //! + //! @param handle - handle for the interface. + //! @param pCapabilities - pointer to an interface specific structure used to + //! return the capabilities of the interface. + //! + //! This function returns the specific capabilities of the MSPI. In some + //! cases the capabilities may be instance specific (e.g. maximum data rate). + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_capabilities_get(void *pHandle, + am_hal_mspi_capabilities_t **pCapabilities); + + //***************************************************************************** + // + //! @brief MSPI blocking transfer function + //! + //! @param pHandle - handle for the interface. + //! @param pTransaction - pointer to the transaction control structure. + //! @param ui32Timeout - timeout in usecs. + //! + //! This function performs a transaction on the MSPI in PIO mode. It handles + //! half duplex transactions only (TX or RX). + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_blocking_transfer(void *pHandle, + am_hal_mspi_pio_transfer_t *pTransaction, + uint32_t ui32Timeout); + //***************************************************************************** + // + //! @brief MSPI Non-Blocking transfer function + //! + //! @param handle - handle for the interface. + //! @param pTransaction - pointer to the transaction control structure. + //! @param pfnCallback - pointer the callback function to be executed when + //! transaction is complete. + //! + //! This function performs a transaction on the MSPI using either DMA or the + //! Command Queue with DMA. It handles half duplex transactions. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, + void *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt); + + //***************************************************************************** + // + //! @brief MSPI status function + //! + //! @param handle - handle for the interface. + //! + //! This function returns the current status of the DMA operation. + //! + //! @return status - DMA status flags. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_status_get(void *pHandle, + am_hal_mspi_status_t *pStatus ); + + //***************************************************************************** + // + //! @brief MSPI enable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - MSPI interrupt mask. + //! + //! This function enables the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_enable(void *pHandle, + uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief MSPI disable interrupts function + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - MSPI interrupt mask. + //! + //! This function disable the specific indicated interrupts. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_disable(void *pHandle, + uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief MSPI interrupt status function + //! + //! @param handle - handle for the interface. + //! @param pui32Status - returns the interrupt status value. + //! @param bEnabledOnly - TRUE: only report interrupt status for enalbed ints. + //! FALSE: report all interrupt status values. + //! + //! This function returns the specific indicated interrupt status. + //! + //! @return status - interrupt status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_status_get(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly); + + //***************************************************************************** + // + //! @brief MSPI interrupt clear + //! + //! @param handle - handle for the interface. + //! @param ui32IntMask - uint32_t for interrupts to clear + //! + //! This function clears the interrupts for the given peripheral. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_clear(void *pHandle, + uint32_t ui32IntMask); + + //***************************************************************************** + // + //! @brief MSPI interrupt service routine + //! + //! @param handle - handle for the interface. + //! @param ui32IntStatus - interrupt status. + //! + //! This function is designed to be called from within the user defined ISR + //! in order to service the non-blocking, queued, or DMA processing for a given + //! module instance. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_interrupt_service(void *pHandle, + uint32_t ui32IntStatus); + + //***************************************************************************** + // + //! @brief MSPI power control function + //! + //! @param handle - handle for the interface. + //! @param ePowerState - the desired power state to move the peripheral to. + //! @param bRetainState - flag (if true) to save/restore peripheral state upon + //! power state change. + //! + //! This function updates the peripheral to a given power state. + //! + //! @return status - generic or interface specific status. + // + //***************************************************************************** + extern uint32_t am_hal_mspi_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); +// +// MSPI High Priority transfer function +// +extern uint32_t am_hal_mspi_highprio_transfer(void *pHandle, + am_hal_mspi_dma_transfer_t *pTransfer, + am_hal_mspi_trans_e eMode, + am_hal_mspi_callback_t pfnCallback, + void *pCallbackCtxt); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_MSPI_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.c new file mode 100644 index 0000000000..9acb47116a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.c @@ -0,0 +1,651 @@ +//***************************************************************************** +// +//! @file am_hal_pdm.c +//! +//! @brief HAL implementation for the PDM module. +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// PDM magic number for handle verification. +// +//***************************************************************************** +#define AM_HAL_MAGIC_PDM 0xF956E2 + +#define AM_HAL_PDM_HANDLE_VALID(h) \ + ((h) && \ + ((am_hal_handle_prefix_t *)(h))->s.bInit && \ + (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_PDM)) + +//***************************************************************************** +// +// Convenience macro for passing errors. +// +//***************************************************************************** +#define RETURN_ON_ERROR(x) \ + if ((x) != AM_HAL_STATUS_SUCCESS) \ + { \ + return (x); \ + }; + +//***************************************************************************** +// +// Abbreviation for validating handles and returning errors. +// +//***************************************************************************** +#ifndef AM_HAL_DISABLE_API_VALIDATION + +#define AM_HAL_PDM_HANDLE_CHECK(h) \ + if (!AM_HAL_PDM_HANDLE_VALID(h)) \ + { \ + return AM_HAL_STATUS_INVALID_HANDLE; \ + } + +#else + +#define AM_HAL_PDM_HANDLE_CHECK(h) + +#endif // AM_HAL_DISABLE_API_VALIDATION + +//***************************************************************************** +// +// Helper macros for delays. +// +//***************************************************************************** +#define delay_ms(ms) \ + if (1) \ + { \ + am_hal_clkgen_status_t sClkGenStatus; \ + am_hal_clkgen_status_get(&sClkGenStatus); \ + am_hal_flash_delay((ms) * (sClkGenStatus.ui32SysclkFreq / 3000)); \ + } + +#define delay_us(us) \ + if (1) \ + { \ + am_hal_clkgen_status_t sClkGenStatus; \ + am_hal_clkgen_status_get(&sClkGenStatus); \ + am_hal_flash_delay((us) * (sClkGenStatus.ui32SysclkFreq / 3000000)); \ + } + +//***************************************************************************** +// +// Structure for handling PDM register state information for power up/down +// +//***************************************************************************** +typedef struct +{ + bool bValid; +} +am_hal_pdm_register_state_t; + +//***************************************************************************** +// +// Structure for handling PDM HAL state information. +// +//***************************************************************************** +typedef struct +{ + am_hal_handle_prefix_t prefix; + am_hal_pdm_register_state_t sRegState; + uint32_t ui32Module; +} +am_hal_pdm_state_t; + +//***************************************************************************** +// +// State structure for each module. +// +//***************************************************************************** +am_hal_pdm_state_t g_am_hal_pdm_states[AM_REG_PDM_NUM_MODULES]; + +//***************************************************************************** +// +// Static function definitions. +// +//***************************************************************************** +static uint32_t find_dma_threshold(uint32_t ui32TotalCount); + +//***************************************************************************** +// +// Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_pdm_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check that the request module is in range. + // + if ( ui32Module >= AM_REG_PDM_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_am_hal_pdm_states[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + g_am_hal_pdm_states[ui32Module].prefix.s.bInit = true; + g_am_hal_pdm_states[ui32Module].prefix.s.magic = AM_HAL_MAGIC_PDM; + g_am_hal_pdm_states[ui32Module].ui32Module = ui32Module; + g_am_hal_pdm_states[ui32Module].sRegState.bValid = false; + + // + // Return the handle. + // + *ppHandle = (void *)&g_am_hal_pdm_states[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// De-Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_pdm_deinitialize(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *)pHandle; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Reset the handle. + // + pState->prefix.s.bInit = false; + pState->prefix.s.magic = 0; + pState->ui32Module = 0; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Power control function. +// +//***************************************************************************** +uint32_t +am_hal_pdm_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + am_hal_pwrctrl_periph_e ePDMPowerModule = ((am_hal_pwrctrl_periph_e) + (AM_HAL_PWRCTRL_PERIPH_PDM + + ui32Module)); + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Decode the requested power state and update PDM operation accordingly. + // + switch (ePowerState) + { + // + // Turn on the PDM. + // + case AM_HAL_SYSCTRL_WAKE: + // + // Make sure we don't try to restore an invalid state. + // + if (bRetainState && !pState->sRegState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable(ePDMPowerModule); + + if (bRetainState) + { + // + // Restore PDM registers + // + AM_CRITICAL_BEGIN; + + pState->sRegState.bValid = false; + + AM_CRITICAL_END; + } + break; + + // + // Turn off the PDM. + // + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if (bRetainState) + { + AM_CRITICAL_BEGIN; + + pState->sRegState.bValid = true; + + AM_CRITICAL_END; + } + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable(ePDMPowerModule); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Configure the PDM. +// +//***************************************************************************** +uint32_t +am_hal_pdm_configure(void *pHandle, am_hal_pdm_config_t *psConfig) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Apply the config structure settings to the PCFG register. + // + PDMn(ui32Module)->PCFG_b.SOFTMUTE = psConfig->bSoftMute; + PDMn(ui32Module)->PCFG_b.CYCLES = psConfig->ui32GainChangeDelay; + PDMn(ui32Module)->PCFG_b.HPCUTOFF = psConfig->ui32HighPassCutoff; + PDMn(ui32Module)->PCFG_b.ADCHPD = psConfig->bHighPassEnable; + PDMn(ui32Module)->PCFG_b.SINCRATE = psConfig->ui32DecimationRate; + PDMn(ui32Module)->PCFG_b.MCLKDIV = psConfig->eClkDivider; + PDMn(ui32Module)->PCFG_b.PGALEFT = psConfig->eLeftGain; + PDMn(ui32Module)->PCFG_b.PGARIGHT = psConfig->eRightGain; + PDMn(ui32Module)->PCFG_b.LRSWAP = psConfig->bLRSwap; + + // + // Set the PDM Core enable bit to enable PDM to PCM conversions. + // + PDMn(ui32Module)->PCFG_b.PDMCOREEN = PDM_PCFG_PDMCOREEN_EN; + + // + // Program the "voice" registers. + // + PDMn(ui32Module)->VCFG_b.PDMCLKEN = PDM_VCFG_PDMCLKEN_DIS; + PDMn(ui32Module)->VCFG_b.IOCLKEN = PDM_VCFG_IOCLKEN_DIS; + PDMn(ui32Module)->VCFG_b.RSTB = PDM_VCFG_RSTB_RESET; + PDMn(ui32Module)->VCFG_b.CHSET = psConfig->ePCMChannels; + PDMn(ui32Module)->VCFG_b.PCMPACK = psConfig->bDataPacking; + PDMn(ui32Module)->VCFG_b.SELAP = psConfig->ePDMClkSource; + PDMn(ui32Module)->VCFG_b.DMICKDEL = psConfig->bPDMSampleDelay; + PDMn(ui32Module)->VCFG_b.BCLKINV = psConfig->bInvertI2SBCLK; + PDMn(ui32Module)->VCFG_b.I2SEN = psConfig->bI2SEnable; + PDMn(ui32Module)->VCFG_b.PDMCLKSEL = psConfig->ePDMClkSpeed; + + delay_us(100); + + PDMn(ui32Module)->VCFG_b.RSTB = PDM_VCFG_RSTB_NORM; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Enable the PDM. +// +//***************************************************************************** +uint32_t +am_hal_pdm_enable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->VCFG_b.IOCLKEN = PDM_VCFG_IOCLKEN_EN; + PDMn(ui32Module)->VCFG_b.PDMCLKEN = PDM_VCFG_PDMCLKEN_EN; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Disable the PDM. +// +//***************************************************************************** +uint32_t +am_hal_pdm_disable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->VCFG_b.IOCLKEN = PDM_VCFG_IOCLKEN_DIS; + PDMn(ui32Module)->VCFG_b.PDMCLKEN = PDM_VCFG_PDMCLKEN_DIS; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Given the total number of bytes in a DMA transaction, find a reasonable +// threshold setting. +// +//***************************************************************************** +static uint32_t +find_dma_threshold(uint32_t ui32TotalCount) +{ + // + // Start with a threshold value of 24, and search downward for values that + // fit our criteria. + // + uint32_t ui32Threshold; + uint32_t ui32Minimum = AM_HAL_PDM_DMA_THRESHOLD_MIN; + + for ( ui32Threshold = 24; ui32Threshold >= ui32Minimum; ui32Threshold -= 4 ) + { + // + // With our loop parameters, we've already guaranteed that the + // threshold will be no higher than 24, and that it will be divisible + // by 4. The only remaining requirement is that ui32TotalCount must + // also be divisible by the threshold. + // + if ((ui32TotalCount % ui32Threshold) == 0) + { + break; + } + } + + // + // If we found an appropriate value, we'll return it here. Otherwise, we + // will return zero. + // + if (ui32Threshold < ui32Minimum) + { + ui32Threshold = 0; + } + + return ui32Threshold; +} + +//***************************************************************************** +// +// Starts a DMA transaction from the PDM directly to SRAM +// +//***************************************************************************** +uint32_t +am_hal_pdm_dma_start(void *pHandle, am_hal_pdm_transfer_t *pDmaCfg) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Find an appropriate threshold size for this transfer. + // + uint32_t ui32Threshold = find_dma_threshold(pDmaCfg->ui32TotalCount); + + // + // If we didn't find a threshold that will work, throw an error. + // + if (ui32Threshold == 0) + { + return AM_HAL_PDM_STATUS_BAD_TOTALCOUNT; + } + + PDMn(ui32Module)->FIFOTHR = ui32Threshold; + + // + // Configure DMA. + // + PDMn(ui32Module)->DMACFG = 0; + PDMn(ui32Module)->DMACFG_b.DMAPRI = PDM_DMACFG_DMAPRI_LOW; + PDMn(ui32Module)->DMACFG_b.DMADIR = PDM_DMACFG_DMADIR_P2M; + PDMn(ui32Module)->DMATOTCOUNT = pDmaCfg->ui32TotalCount; + PDMn(ui32Module)->DMATARGADDR = pDmaCfg->ui32TargetAddr; + + // + // Make sure the trigger is set for threshold. + // + PDMn(ui32Module)->DMATRIGEN_b.DTHR = 1; + + // + // Enable DMA + // + PDMn(ui32Module)->DMACFG_b.DMAEN = PDM_DMACFG_DMAEN_EN; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Flush the PDM FIFO +// +//***************************************************************************** +uint32_t +am_hal_pdm_fifo_flush(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->FIFOFLUSH = 1; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Enable PDM passthrough to the I2S slave. +// +//***************************************************************************** +uint32_t +am_hal_pdm_i2s_enable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + uint32_t ui32Module = pState->ui32Module; + + PDMn(ui32Module)->VCFG_b.I2SEN = PDM_VCFG_I2SEN_EN; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Disable PDM passthrough to the I2S slave. +// +//***************************************************************************** +uint32_t +am_hal_pdm_i2s_disable(void *pHandle) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + uint32_t ui32Module = pState->ui32Module; + + PDMn(ui32Module)->VCFG_b.I2SEN = PDM_VCFG_I2SEN_DIS; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt enable. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->INTEN |= ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt disable. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->INTEN &= ~ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt clear. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + PDMn(ui32Module)->INTCLR = ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Returns the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_pdm_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEnabledOnly) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check the handle. + // + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // If requested, only return the interrupts that are enabled. + // + if ( bEnabledOnly ) + { + *pui32Status = PDMn(ui32Module)->INTSTAT; + *pui32Status &= PDMn(ui32Module)->INTEN; + } + else + { + *pui32Status = PDMn(ui32Module)->INTSTAT; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.h new file mode 100644 index 0000000000..6968217973 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pdm.h @@ -0,0 +1,318 @@ +//***************************************************************************** +// +//! @file am_hal_pdm.h +//! +//! @brief API for the PDM module +//! +//! @addtogroup +//! @ingroup +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PDM_H +#define AM_HAL_PDM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable IOS module number. +// +//***************************************************************************** +#define AM_REG_PDM_NUM_MODULES 1 +#define PDMn(n) ((PDM_Type*)(PDM_BASE + (n * (PDM_BASE - PDM_BASE)))) + +//***************************************************************************** +// +// DMA threshold minimum. +// +// The PDM DMA works best if its threshold value is set to a multiple of 4 +// between 16 and 24, but it will technically allow threshold settings between +// 4 and 24. This macro sets the minimum threshold value that the HAL layer +// will allow. +// +//***************************************************************************** +#define AM_HAL_PDM_DMA_THRESHOLD_MIN 16 + +//***************************************************************************** +// +// PDM-specific error conditions. +// +//***************************************************************************** +typedef enum +{ + // + // The PDM HAL will throw this error if it can't find a threshold value to + // match the total-count value passed in by a caller requesting a DMA + // transfer. The PDM hardware requires all DMA transactions to be evenly + // divisible in chunks of one FIFO size or smaller. Try changing your + // ui32TotalCount value to a more evenly divisible number. + // + AM_HAL_PDM_STATUS_BAD_TOTALCOUNT = AM_HAL_STATUS_MODULE_SPECIFIC_START, +} +am_hal_pdm_status_e; + +//***************************************************************************** +// +// Gain settings. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_GAIN_P405DB = PDM_PCFG_PGALEFT_P405DB, + AM_HAL_PDM_GAIN_P390DB = PDM_PCFG_PGALEFT_P390DB, + AM_HAL_PDM_GAIN_P375DB = PDM_PCFG_PGALEFT_P375DB, + AM_HAL_PDM_GAIN_P360DB = PDM_PCFG_PGALEFT_P360DB, + AM_HAL_PDM_GAIN_P345DB = PDM_PCFG_PGALEFT_P345DB, + AM_HAL_PDM_GAIN_P330DB = PDM_PCFG_PGALEFT_P330DB, + AM_HAL_PDM_GAIN_P315DB = PDM_PCFG_PGALEFT_P315DB, + AM_HAL_PDM_GAIN_P300DB = PDM_PCFG_PGALEFT_P300DB, + AM_HAL_PDM_GAIN_P285DB = PDM_PCFG_PGALEFT_P285DB, + AM_HAL_PDM_GAIN_P270DB = PDM_PCFG_PGALEFT_P270DB, + AM_HAL_PDM_GAIN_P255DB = PDM_PCFG_PGALEFT_P255DB, + AM_HAL_PDM_GAIN_P240DB = PDM_PCFG_PGALEFT_P240DB, + AM_HAL_PDM_GAIN_P225DB = PDM_PCFG_PGALEFT_P225DB, + AM_HAL_PDM_GAIN_P210DB = PDM_PCFG_PGALEFT_P210DB, + AM_HAL_PDM_GAIN_P195DB = PDM_PCFG_PGALEFT_P195DB, + AM_HAL_PDM_GAIN_P180DB = PDM_PCFG_PGALEFT_P180DB, + AM_HAL_PDM_GAIN_P165DB = PDM_PCFG_PGALEFT_P165DB, + AM_HAL_PDM_GAIN_P150DB = PDM_PCFG_PGALEFT_P150DB, + AM_HAL_PDM_GAIN_P135DB = PDM_PCFG_PGALEFT_P135DB, + AM_HAL_PDM_GAIN_P120DB = PDM_PCFG_PGALEFT_P120DB, + AM_HAL_PDM_GAIN_P105DB = PDM_PCFG_PGALEFT_P105DB, + AM_HAL_PDM_GAIN_P90DB = PDM_PCFG_PGALEFT_P90DB, + AM_HAL_PDM_GAIN_P75DB = PDM_PCFG_PGALEFT_P75DB, + AM_HAL_PDM_GAIN_P60DB = PDM_PCFG_PGALEFT_P60DB, + AM_HAL_PDM_GAIN_P45DB = PDM_PCFG_PGALEFT_P45DB, + AM_HAL_PDM_GAIN_P30DB = PDM_PCFG_PGALEFT_P30DB, + AM_HAL_PDM_GAIN_P15DB = PDM_PCFG_PGALEFT_P15DB, + AM_HAL_PDM_GAIN_0DB = PDM_PCFG_PGALEFT_0DB, + AM_HAL_PDM_GAIN_M15DB = PDM_PCFG_PGALEFT_M15DB, + AM_HAL_PDM_GAIN_M300DB = PDM_PCFG_PGALEFT_M300DB, + AM_HAL_PDM_GAIN_M45DB = PDM_PCFG_PGALEFT_M45DB, + AM_HAL_PDM_GAIN_M60DB = PDM_PCFG_PGALEFT_M60DB, +} +am_hal_pdm_gain_e; + +//***************************************************************************** +// +// Clock Source selection. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_INTERNAL_CLK = PDM_VCFG_SELAP_INTERNAL, + AM_HAL_PDM_I2S_CLK = PDM_VCFG_SELAP_I2S, +} +am_hal_pdm_clksrc_e; + +//***************************************************************************** +// +// PDM internal clock speed selection. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_CLK_DISABLE = PDM_VCFG_PDMCLKSEL_DISABLE, + AM_HAL_PDM_CLK_12MHZ = PDM_VCFG_PDMCLKSEL_12MHz, + AM_HAL_PDM_CLK_6MHZ = PDM_VCFG_PDMCLKSEL_6MHz, + AM_HAL_PDM_CLK_3MHZ = PDM_VCFG_PDMCLKSEL_3MHz, + AM_HAL_PDM_CLK_1_5MHZ = PDM_VCFG_PDMCLKSEL_1_5MHz, + AM_HAL_PDM_CLK_750KHZ = PDM_VCFG_PDMCLKSEL_750KHz, + AM_HAL_PDM_CLK_375KHZ = PDM_VCFG_PDMCLKSEL_375KHz, + AM_HAL_PDM_CLK_187KHZ = PDM_VCFG_PDMCLKSEL_187KHz, +} +am_hal_pdm_clkspd_e; + +//***************************************************************************** +// +// PDM clock divider setting. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_MCLKDIV_4 = PDM_PCFG_MCLKDIV_MCKDIV4, + AM_HAL_PDM_MCLKDIV_3 = PDM_PCFG_MCLKDIV_MCKDIV3, + AM_HAL_PDM_MCLKDIV_2 = PDM_PCFG_MCLKDIV_MCKDIV2, + AM_HAL_PDM_MCLKDIV_1 = PDM_PCFG_MCLKDIV_MCKDIV1, +} +am_hal_pdm_mclkdiv_e; + +//***************************************************************************** +// +// PCM Channel Select. +// +//***************************************************************************** +typedef enum +{ + AM_HAL_PDM_CHANNEL_LEFT = PDM_VCFG_CHSET_LEFT, + AM_HAL_PDM_CHANNEL_RIGHT = PDM_VCFG_CHSET_RIGHT, + AM_HAL_PDM_CHANNEL_STEREO = PDM_VCFG_CHSET_STEREO, +} +am_hal_pdm_chset_e; + +//***************************************************************************** +// +// PDM power state settings. +// +//***************************************************************************** +#define AM_HAL_PDM_POWER_ON AM_HAL_SYSCTRL_WAKE +#define AM_HAL_PDM_POWER_OFF AM_HAL_SYSCTRL_NORMALSLEEP + +//***************************************************************************** +// +// PDM interrupts. +// +//***************************************************************************** +#define AM_HAL_PDM_INT_DERR PDM_INTSTAT_DERR_Msk +#define AM_HAL_PDM_INT_DCMP PDM_INTSTAT_DCMP_Msk +#define AM_HAL_PDM_INT_UNDFL PDM_INTSTAT_UNDFL_Msk +#define AM_HAL_PDM_INT_OVF PDM_INTSTAT_OVF_Msk +#define AM_HAL_PDM_INT_THR PDM_INTSTAT_THR_Msk + +//***************************************************************************** +// +// Configuration structure for the PDM +// +//***************************************************************************** +typedef struct +{ + // Clock + am_hal_pdm_mclkdiv_e eClkDivider; + + // Gain + am_hal_pdm_gain_e eLeftGain; + am_hal_pdm_gain_e eRightGain; + + // Decimation Rate + uint32_t ui32DecimationRate; + + // Filters + bool bHighPassEnable; + uint32_t ui32HighPassCutoff; + + // PDMCLKSEL + am_hal_pdm_clkspd_e ePDMClkSpeed; + + // BCLKINV + bool bInvertI2SBCLK; + + // SELAP + am_hal_pdm_clksrc_e ePDMClkSource; + + // DMICKDEL + bool bPDMSampleDelay; + + // PCMPACK + bool bDataPacking; + + // CHSET + am_hal_pdm_chset_e ePCMChannels; + + uint32_t ui32GainChangeDelay; + + bool bI2SEnable; + + bool bSoftMute; + + bool bLRSwap; +} +am_hal_pdm_config_t; + +//***************************************************************************** +// +// DMA transfer structure +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32TargetAddr; + uint32_t ui32TotalCount; +} +am_hal_pdm_transfer_t; + +// Init/De-init. +extern uint32_t am_hal_pdm_initialize(uint32_t ui32Module, void **ppHandle); +extern uint32_t am_hal_pdm_deinitialize(void *pHandle); + +// Power +extern uint32_t am_hal_pdm_power_control(void *pHandle, am_hal_sysctrl_power_state_e ePowerState, bool bRetainState); + +// Config +extern uint32_t am_hal_pdm_configure(void *pHandle, am_hal_pdm_config_t *psConfig); + +// Enable/Disable +extern uint32_t am_hal_pdm_enable(void *pHandle); +extern uint32_t am_hal_pdm_disable(void *pHandle); + +// Gather PDM data. +extern uint32_t am_hal_pdm_dma_start(void *pHandle, am_hal_pdm_transfer_t *pDmaCfg); + +// Flush the PDM FIFO. +extern uint32_t am_hal_pdm_fifo_flush(void *pHandle); + +// I2S Passthrough +extern uint32_t am_hal_pdm_i2s_enable(void *pHandle); +extern uint32_t am_hal_pdm_i2s_disable(void *pHandle); + +// Interrupts. +extern uint32_t am_hal_pdm_interrupt_enable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_pdm_interrupt_disable(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_pdm_interrupt_clear(void *pHandle, uint32_t ui32IntMask); +extern uint32_t am_hal_pdm_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEnabledOnly); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_PDM_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pin.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pin.h new file mode 100644 index 0000000000..eb158b80bf --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pin.h @@ -0,0 +1,495 @@ +//***************************************************************************** +// +// am_hal_pin.h +//! @file +//! @brief Macros for configuring specific pins. +//! +//! @addtogroup pin3 PIN definitions for Apollo3. +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PIN_H +#define AM_HAL_PIN_H + +//***************************************************************************** +// +// Pin definition macros. +// +//***************************************************************************** +#define AM_HAL_PIN_0_SLSCL (0) +#define AM_HAL_PIN_0_SLSCK (1) +#define AM_HAL_PIN_0_CLKOUT (2) +#define AM_HAL_PIN_0_GPIO (3) +#define AM_HAL_PIN_0_MSPI4 (5) +#define AM_HAL_PIN_0_NCE0 (7) + +#define AM_HAL_PIN_1_SLSDAWIR3 (0) +#define AM_HAL_PIN_1_SLMOSI (1) +#define AM_HAL_PIN_1_UART0TX (2) +#define AM_HAL_PIN_1_GPIO (3) +#define AM_HAL_PIN_1_MSPI5 (5) +#define AM_HAL_PIN_1_NCE1 (7) + +#define AM_HAL_PIN_2_UART1RX (0) +#define AM_HAL_PIN_2_SLMISO (1) +#define AM_HAL_PIN_2_UART0RX (2) +#define AM_HAL_PIN_2_GPIO (3) +#define AM_HAL_PIN_2_MSPI6 (5) +#define AM_HAL_PIN_2_NCE2 (7) + +#define AM_HAL_PIN_3_UART0RTS (0) +#define AM_HAL_PIN_3_SLnCE (1) +#define AM_HAL_PIN_3_NCE3 (2) +#define AM_HAL_PIN_3_GPIO (3) +#define AM_HAL_PIN_3_MSPI7 (5) +#define AM_HAL_PIN_3_TRIG1 (6) +#define AM_HAL_PIN_3_I2S_WCLK (7) +#define AM_HAL_PIN_3_PSOURCE (3) + +#define AM_HAL_PIN_4_UART0CTS (0) +#define AM_HAL_PIN_4_SLINT (1) +#define AM_HAL_PIN_4_NCE4 (2) +#define AM_HAL_PIN_4_GPIO (3) +#define AM_HAL_PIN_4_UART1RX (5) +#define AM_HAL_PIN_4_CTIM17 (6) +#define AM_HAL_PIN_4_MSPI2 (7) + +#define AM_HAL_PIN_5_M0SCL (0) +#define AM_HAL_PIN_5_M0SCK (1) +#define AM_HAL_PIN_5_UART0RTS (2) +#define AM_HAL_PIN_5_GPIO (3) +#define AM_HAL_PIN_5_EXTHFA (5) +#define AM_HAL_PIN_5_CTIM8 (7) + +#define AM_HAL_PIN_6_M0SDAWIR3 (0) +#define AM_HAL_PIN_6_M0MISO (1) +#define AM_HAL_PIN_6_UART0CTS (2) +#define AM_HAL_PIN_6_GPIO (3) +#define AM_HAL_PIN_6_CTIM10 (5) +#define AM_HAL_PIN_6_I2S_DAT (7) + +#define AM_HAL_PIN_7_NCE7 (0) +#define AM_HAL_PIN_7_M0MOSI (1) +#define AM_HAL_PIN_7_CLKOUT (2) +#define AM_HAL_PIN_7_GPIO (3) +#define AM_HAL_PIN_7_TRIG0 (4) +#define AM_HAL_PIN_7_UART0TX (5) +#define AM_HAL_PIN_7_CTIM19 (7) + +#define AM_HAL_PIN_8_M1SCL (0) +#define AM_HAL_PIN_8_M1SCK (1) +#define AM_HAL_PIN_8_NCE8 (2) +#define AM_HAL_PIN_8_GPIO (3) +#define AM_HAL_PIN_8_SCCCLK (4) +#define AM_HAL_PIN_8_UART1TX (6) + +#define AM_HAL_PIN_9_M1SDAWIR3 (0) +#define AM_HAL_PIN_9_M1MISO (1) +#define AM_HAL_PIN_9_NCE9 (2) +#define AM_HAL_PIN_9_GPIO (3) +#define AM_HAL_PIN_9_SCCIO (4) +#define AM_HAL_PIN_9_UART1RX (6) + +#define AM_HAL_PIN_10_UART1TX (0) +#define AM_HAL_PIN_10_M1MOSI (1) +#define AM_HAL_PIN_10_NCE10 (2) +#define AM_HAL_PIN_10_GPIO (3) +#define AM_HAL_PIN_10_PDMCLK (4) +#define AM_HAL_PIN_10_UART1RTS (5) + +#define AM_HAL_PIN_11_ADCSE2 (0) +#define AM_HAL_PIN_11_NCE11 (1) +#define AM_HAL_PIN_11_CTIM31 (2) +#define AM_HAL_PIN_11_GPIO (3) +#define AM_HAL_PIN_11_SLINT (4) +#define AM_HAL_PIN_11_UART1CTS (5) +#define AM_HAL_PIN_11_UART0RX (6) +#define AM_HAL_PIN_11_PDMDATA (7) + +#define AM_HAL_PIN_12_ADCD0NSE9 (0) +#define AM_HAL_PIN_12_NCE12 (1) +#define AM_HAL_PIN_12_CTIM0 (2) +#define AM_HAL_PIN_12_GPIO (3) +#define AM_HAL_PIN_12_SLnCE (4) +#define AM_HAL_PIN_12_PDMCLK (5) +#define AM_HAL_PIN_12_UART0CTS (6) +#define AM_HAL_PIN_12_UART1TX (7) + +#define AM_HAL_PIN_13_ADCD0PSE8 (0) +#define AM_HAL_PIN_13_NCE13 (1) +#define AM_HAL_PIN_13_CTIM2 (2) +#define AM_HAL_PIN_13_GPIO (3) +#define AM_HAL_PIN_13_I2SBCLK (4) +#define AM_HAL_PIN_13_EXTHFB (5) +#define AM_HAL_PIN_13_UART0RTS (6) +#define AM_HAL_PIN_13_UART1RX (7) + +#define AM_HAL_PIN_14_ADCD1P (0) +#define AM_HAL_PIN_14_NCE14 (1) +#define AM_HAL_PIN_14_UART1TX (2) +#define AM_HAL_PIN_14_GPIO (3) +#define AM_HAL_PIN_14_PDMCLK (4) +#define AM_HAL_PIN_14_EXTHFS (5) +#define AM_HAL_PIN_14_SWDCK (6) +#define AM_HAL_PIN_14_32KHZXT (7) + +#define AM_HAL_PIN_15_ADCD1N (0) +#define AM_HAL_PIN_15_NCE15 (1) +#define AM_HAL_PIN_15_UART1RX (2) +#define AM_HAL_PIN_15_GPIO (3) +#define AM_HAL_PIN_15_PDMDATA (4) +#define AM_HAL_PIN_15_EXTXT (5) +#define AM_HAL_PIN_15_SWDIO (6) +#define AM_HAL_PIN_15_SWO (7) + +#define AM_HAL_PIN_16_ADCSE0 (0) +#define AM_HAL_PIN_16_NCE16 (1) +#define AM_HAL_PIN_16_TRIG0 (2) +#define AM_HAL_PIN_16_GPIO (3) +#define AM_HAL_PIN_16_SCCRST (4) +#define AM_HAL_PIN_16_CMPIN0 (5) +#define AM_HAL_PIN_16_UART0TX (6) +#define AM_HAL_PIN_16_UART1RTS (7) + +#define AM_HAL_PIN_17_CMPRF1 (0) +#define AM_HAL_PIN_17_NCE17 (1) +#define AM_HAL_PIN_17_TRIG1 (2) +#define AM_HAL_PIN_17_GPIO (3) +#define AM_HAL_PIN_17_SCCCLK (4) +#define AM_HAL_PIN_17_UART0RX (6) +#define AM_HAL_PIN_17_UART1CTS (7) + +#define AM_HAL_PIN_18_CMPIN1 (0) +#define AM_HAL_PIN_18_NCE18 (1) +#define AM_HAL_PIN_18_CTIM4 (2) +#define AM_HAL_PIN_18_GPIO (3) +#define AM_HAL_PIN_18_UART0RTS (4) +#define AM_HAL_PIN_18_ANATEST2 (5) +#define AM_HAL_PIN_18_UART1TX (6) +#define AM_HAL_PIN_18_SCCIO (7) + +#define AM_HAL_PIN_19_CMPRF0 (0) +#define AM_HAL_PIN_19_NCE19 (1) +#define AM_HAL_PIN_19_CTIM6 (2) +#define AM_HAL_PIN_19_GPIO (3) +#define AM_HAL_PIN_19_SCCCLK (4) +#define AM_HAL_PIN_19_ANATEST1 (5) +#define AM_HAL_PIN_19_UART1RX (6) +#define AM_HAL_PIN_19_I2SBCLK (7) + +#define AM_HAL_PIN_20_SWDCK (0) +#define AM_HAL_PIN_20_NCE20 (1) +#define AM_HAL_PIN_20_GPIO (3) +#define AM_HAL_PIN_20_UART0TX (4) +#define AM_HAL_PIN_20_UART1TX (5) +#define AM_HAL_PIN_20_I2SBCLK (6) +#define AM_HAL_PIN_20_UART1RTS (7) + +#define AM_HAL_PIN_21_SWDIO (0) +#define AM_HAL_PIN_21_NCE21 (1) +#define AM_HAL_PIN_21_GPIO (3) +#define AM_HAL_PIN_21_UART0RX (4) +#define AM_HAL_PIN_21_UART1RX (5) +#define AM_HAL_PIN_21_I2SBCLK (6) +#define AM_HAL_PIN_21_UART1CTS (7) + +#define AM_HAL_PIN_22_UART0TX (0) +#define AM_HAL_PIN_22_NCE22 (1) +#define AM_HAL_PIN_22_CTIM12 (2) +#define AM_HAL_PIN_22_GPIO (3) +#define AM_HAL_PIN_22_PDMCLK (4) +#define AM_HAL_PIN_22_EXTLF (5) +#define AM_HAL_PIN_22_MSPI0 (6) +#define AM_HAL_PIN_22_SWO (7) + +#define AM_HAL_PIN_23_UART0RX (0) +#define AM_HAL_PIN_23_NCE23 (1) +#define AM_HAL_PIN_23_CTIM14 (2) +#define AM_HAL_PIN_23_GPIO (3) +#define AM_HAL_PIN_23_I2SWCLK (4) +#define AM_HAL_PIN_23_CMPOUT (5) +#define AM_HAL_PIN_23_MSPI13 (6) +#define AM_HAL_PIN_23_EXTXT (7) + +#define AM_HAL_PIN_24_UART1TX (0) +#define AM_HAL_PIN_24_NCE24 (1) +#define AM_HAL_PIN_24_MSPI8 (2) +#define AM_HAL_PIN_24_GPIO (3) +#define AM_HAL_PIN_24_UART0CTS (4) +#define AM_HAL_PIN_24_CTIM21 (5) +#define AM_HAL_PIN_24_32KHZXT (6) +#define AM_HAL_PIN_24_SWO (7) + +#define AM_HAL_PIN_25_UART1RX (0) +#define AM_HAL_PIN_25_NCE25 (1) +#define AM_HAL_PIN_25_CTIM1 (2) +#define AM_HAL_PIN_25_GPIO (3) +#define AM_HAL_PIN_25_M2SDAWIR3 (4) +#define AM_HAL_PIN_25_M2MISO (5) + +#define AM_HAL_PIN_26_EXTHF (0) +#define AM_HAL_PIN_26_NCE26 (1) +#define AM_HAL_PIN_26_CTIM3 (2) +#define AM_HAL_PIN_26_GPIO (3) +#define AM_HAL_PIN_26_SCCRST (4) +#define AM_HAL_PIN_26_MSPI1 (5) +#define AM_HAL_PIN_26_UART0TX (6) +#define AM_HAL_PIN_26_UART1CTS (7) + +#define AM_HAL_PIN_27_UART0RX (0) +#define AM_HAL_PIN_27_NCE27 (1) +#define AM_HAL_PIN_27_CTIM5 (2) +#define AM_HAL_PIN_27_GPIO (3) +#define AM_HAL_PIN_27_M2SCL (4) +#define AM_HAL_PIN_27_M2SCK (5) + +#define AM_HAL_PIN_28_I2SWCLK (0) +#define AM_HAL_PIN_28_NCE28 (1) +#define AM_HAL_PIN_28_CTIM7 (2) +#define AM_HAL_PIN_28_GPIO (3) +#define AM_HAL_PIN_28_M2MOSI (5) +#define AM_HAL_PIN_28_UART0TX (6) + +#define AM_HAL_PIN_29_ADCSE1 (0) +#define AM_HAL_PIN_29_NCE29 (1) +#define AM_HAL_PIN_29_CTIM9 (2) +#define AM_HAL_PIN_29_GPIO (3) +#define AM_HAL_PIN_29_UART0CTS (4) +#define AM_HAL_PIN_29_UART1CTS (5) +#define AM_HAL_PIN_29_UART0RX (6) +#define AM_HAL_PIN_29_PDMDATA (7) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_30_ANATEST1 (0) +#define AM_HAL_PIN_30_NCE30 (1) +#define AM_HAL_PIN_30_CTIM11 (2) +#define AM_HAL_PIN_30_GPIO (3) +#define AM_HAL_PIN_30_UART0TX (4) +#define AM_HAL_PIN_30_UART1RTS (5) +#define AM_HAL_PIN_30_I2SDAT (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_31_ADCSE3 (0) +#define AM_HAL_PIN_31_NCE31 (1) +#define AM_HAL_PIN_31_CTIM13 (2) +#define AM_HAL_PIN_31_GPIO (3) +#define AM_HAL_PIN_31_UART0RX (4) +#define AM_HAL_PIN_31_SCCCLK (5) +#define AM_HAL_PIN_31_UART1RTS (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_32_ADCSE4 (0) +#define AM_HAL_PIN_32_NCE32 (1) +#define AM_HAL_PIN_32_CTIM15 (2) +#define AM_HAL_PIN_32_GPIO (3) +#define AM_HAL_PIN_32_SCCIO (4) +#define AM_HAL_PIN_32_EXTLF (5) +#define AM_HAL_PIN_32_UART1CTS (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_33_ADCSE5 (0) +#define AM_HAL_PIN_33_NCE33 (1) +#define AM_HAL_PIN_33_32KHZXT (2) +#define AM_HAL_PIN_33_GPIO (3) +#define AM_HAL_PIN_33_UART0CTS (5) +#define AM_HAL_PIN_33_CTIM23 (6) +#define AM_HAL_PIN_33_SWO (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_34_ADCSE6 (0) +#define AM_HAL_PIN_34_NCE34 (1) +#define AM_HAL_PIN_34_UART1RTS (2) +#define AM_HAL_PIN_34_GPIO (3) +#define AM_HAL_PIN_34_CMPRF2 (4) +#define AM_HAL_PIN_34_UART0RTS (5) +#define AM_HAL_PIN_34_UART0RX (6) +#define AM_HAL_PIN_34_PDMDATA (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_35_ADCSE7 (0) +#define AM_HAL_PIN_35_NCE35 (1) +#define AM_HAL_PIN_35_UART1TX (2) +#define AM_HAL_PIN_35_GPIO (3) +#define AM_HAL_PIN_35_I2SDAT (4) +#define AM_HAL_PIN_35_CTIM27 (5) +#define AM_HAL_PIN_35_UART0RTS (6) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_36_TRIG1 (0) +#define AM_HAL_PIN_36_NCE36 (1) +#define AM_HAL_PIN_36_UART1RX (2) +#define AM_HAL_PIN_36_GPIO (3) +#define AM_HAL_PIN_36_32KHZXT (4) +#define AM_HAL_PIN_36_UART1CTS (5) +#define AM_HAL_PIN_36_UART0CTS (6) +#define AM_HAL_PIN_36_PDMDATA (7) +#define AM_HAL_PIN_36_PSOURCE (3) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_37_TRIG2 (0) +#define AM_HAL_PIN_37_NCE37 (1) +#define AM_HAL_PIN_37_UART0RTS (2) +#define AM_HAL_PIN_37_GPIO (3) +#define AM_HAL_PIN_37_SCCIO (4) +#define AM_HAL_PIN_37_UART1TX (5) +#define AM_HAL_PIN_37_PDMCLK (6) +#define AM_HAL_PIN_37_CTIM29 (7) +#define AM_HAL_PIN_37_PSINK (3) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_38_TRIG3 (0) +#define AM_HAL_PIN_38_NCE38 (1) +#define AM_HAL_PIN_38_UART0CTS (2) +#define AM_HAL_PIN_38_GPIO (3) +#define AM_HAL_PIN_38_M3MOSI (5) +#define AM_HAL_PIN_38_UART1RX (6) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_39_UART0TX (0) +#define AM_HAL_PIN_39_UART1TX (1) +#define AM_HAL_PIN_39_CTIM25 (2) +#define AM_HAL_PIN_39_GPIO (3) +#define AM_HAL_PIN_39_M4SCL (4) +#define AM_HAL_PIN_39_M4SCK (5) + +#define AM_HAL_PIN_40_UART0RX (0) +#define AM_HAL_PIN_40_UART1RX (1) +#define AM_HAL_PIN_40_TRIG0 (2) +#define AM_HAL_PIN_40_GPIO (3) +#define AM_HAL_PIN_40_M4SDAWIR3 (4) +#define AM_HAL_PIN_40_M4MISO (5) + +#define AM_HAL_PIN_41_NCE41 (0) +#define AM_HAL_PIN_41_SWO (2) +#define AM_HAL_PIN_41_GPIO (3) +#define AM_HAL_PIN_41_I2SWCLK (4) +#define AM_HAL_PIN_41_UART1RTS (5) +#define AM_HAL_PIN_41_UART0TX (6) +#define AM_HAL_PIN_41_UART0RTS (7) +#define AM_HAL_PIN_41_PSINK (3) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_42_UART1TX (0) +#define AM_HAL_PIN_42_NCE42 (1) +#define AM_HAL_PIN_42_CTIM16 (2) +#define AM_HAL_PIN_42_GPIO (3) +#define AM_HAL_PIN_42_M3SCL (4) +#define AM_HAL_PIN_42_M3SCK (5) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_43_UART1RX (0) +#define AM_HAL_PIN_43_NCE43 (1) +#define AM_HAL_PIN_43_CTIM18 (2) +#define AM_HAL_PIN_43_GPIO (3) +#define AM_HAL_PIN_43_M3SDAWIR3 (4) +#define AM_HAL_PIN_43_M3MISO (5) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_44_UART1RTS (0) +#define AM_HAL_PIN_44_NCE44 (1) +#define AM_HAL_PIN_44_CTIM20 (2) +#define AM_HAL_PIN_44_GPIO (3) +#define AM_HAL_PIN_44_M4MOSI (5) +#define AM_HAL_PIN_44_UART0TX (6) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_45_UART1CTS (0) +#define AM_HAL_PIN_45_NCE45 (1) +#define AM_HAL_PIN_45_CTIM22 (2) +#define AM_HAL_PIN_45_GPIO (3) +#define AM_HAL_PIN_45_I2SDAT (4) +#define AM_HAL_PIN_45_PDMDATA (5) +#define AM_HAL_PIN_45_UART0RX (6) +#define AM_HAL_PIN_45_SWO (7) +#endif // defined (AM_PACKAGE_BGA) + +#if defined (AM_PACKAGE_BGA) +#define AM_HAL_PIN_46_32KHZXT (0) +#define AM_HAL_PIN_46_NCE46 (1) +#define AM_HAL_PIN_46_CTIM24 (2) +#define AM_HAL_PIN_46_GPIO (3) +#define AM_HAL_PIN_46_SCCRST (4) +#define AM_HAL_PIN_46_PDMCLK (5) +#define AM_HAL_PIN_46_UART1TX (6) +#define AM_HAL_PIN_46_SWO (7) +#endif // defined (AM_PACKAGE_BGA) + +#define AM_HAL_PIN_47_32KHZXT (0) +#define AM_HAL_PIN_47_NCE47 (1) +#define AM_HAL_PIN_47_CTIM26 (2) +#define AM_HAL_PIN_47_GPIO (3) +#define AM_HAL_PIN_47_M5MOSI (5) +#define AM_HAL_PIN_47_UART1RX (6) + +#define AM_HAL_PIN_48_UART0TX (0) +#define AM_HAL_PIN_48_NCE48 (1) +#define AM_HAL_PIN_48_CTIM28 (2) +#define AM_HAL_PIN_48_GPIO (3) +#define AM_HAL_PIN_48_M5SCL (4) +#define AM_HAL_PIN_48_M5SCK (5) + +#define AM_HAL_PIN_49_UART0RX (0) +#define AM_HAL_PIN_49_NCE49 (1) +#define AM_HAL_PIN_49_CTIM30 (2) +#define AM_HAL_PIN_49_GPIO (3) +#define AM_HAL_PIN_49_M5SDAWIR3 (4) +#define AM_HAL_PIN_49_M5MISO (5) + +#endif // AM_HAL_PIN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.c new file mode 100644 index 0000000000..019a9647a4 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.c @@ -0,0 +1,638 @@ +//***************************************************************************** +// +// am_hal_pwrctrl.c +//! @file +//! +//! @brief Functions for enabling and disabling power domains. +//! +//! @addtogroup pwrctrl3 Power Control +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +// +// Maximum number of checks to memory power status before declaring error. +// +#define AM_HAL_PWRCTRL_MAX_WFE 20 + +// +// Define the peripheral control structure. +// +const struct +{ + uint32_t ui32PeriphEnable; + uint32_t ui32PeriphStatus; + uint32_t ui32PeriphEvent; +} +am_hal_pwrctrl_peripheral_control[AM_HAL_PWRCTRL_PERIPH_MAX] = +{ + {0, 0, 0}, // AM_HAL_PWRCTRL_PERIPH_NONE + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOS + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN), + PWRCTRL_DEVPWRSTATUS_HCPB_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM0 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN), + PWRCTRL_DEVPWRSTATUS_HCPB_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM1 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN), + PWRCTRL_DEVPWRSTATUS_HCPB_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPBEVEN, PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM2 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN), + PWRCTRL_DEVPWRSTATUS_HCPC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM3 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN), + PWRCTRL_DEVPWRSTATUS_HCPC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM4 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN), + PWRCTRL_DEVPWRSTATUS_HCPC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPCEVEN, PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_IOM5 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_UART0 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_UART1 + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN), + PWRCTRL_DEVPWRSTATUS_PWRADC_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_ADCEVEN, PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_ADC + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN), + PWRCTRL_DEVPWRSTATUS_HCPA_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_HCPAEVEN, PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_SCARD + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI, PWRCTRL_DEVPWREN_PWRMSPI_EN), + PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_MSPIEVEN, PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_MSPI + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN), + PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_PDMEVEN, PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN)}, // AM_HAL_PWRCTRL_PERIPH_PDM + {_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN), + PWRCTRL_DEVPWRSTATUS_BLEL_Msk, + _VAL2FLD(PWRCTRL_DEVPWREVENTEN_BLELEVEN, PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN)} // AM_HAL_PWRCTRL_PERIPH_BLEL +}; + + +// +// Define the memory control structure. +// +const struct +{ + uint32_t ui32MemoryEnable; + uint32_t ui32MemoryStatus; + uint32_t ui32MemoryEvent; + uint32_t ui32MemoryMask; + uint32_t ui32StatusMask; + uint32_t ui32PwdSlpEnable; +} +am_hal_pwrctrl_memory_control[AM_HAL_PWRCTRL_MEM_MAX] = +{ + {0, 0, 0, 0, 0, 0}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_96K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_128K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_160K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_192K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_224K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_256K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_288K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_320K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_352K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K}, + {AM_HAL_PWRCTRL_MEMEN_SRAM_384K, + AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K}, + {AM_HAL_PWRCTRL_MEMEN_FLASH_512K, + AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K, + AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_512K}, + {AM_HAL_PWRCTRL_MEMEN_FLASH_1M, + AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M, + AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M}, + {AM_HAL_PWRCTRL_MEMEN_CACHE, + 0, + AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE, + AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK, + 0, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE}, + {AM_HAL_PWRCTRL_MEMEN_ALL, + AM_HAL_PWRCTRL_PWRONSTATUS_ALL, + AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL, + AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK, + AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK, + AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL} +}; + +// **************************************************************************** +// +// am_hal_pwrctrl_periph_enable() +// Enable power for a peripheral. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral) +{ + + + // + // Enable power control for the given device. + // + AM_CRITICAL_BEGIN + PWRCTRL->DEVPWREN |= am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; + AM_CRITICAL_END + + + + + for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WFE; wait_usecs += 10) + { + am_hal_flash_delay(FLASH_CYCLES_US(10)); + + if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0) + { + break; + } + } + + // + // Check the device status. + // + if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } + +} + +// **************************************************************************** +// +// am_hal_pwrctrl_periph_disable() +// Disable power for a peripheral. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral) +{ + + // + // Disable power domain for the given device. + // + AM_CRITICAL_BEGIN + PWRCTRL->DEVPWREN &= ~am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; + AM_CRITICAL_END + + + for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WFE; wait_usecs += 10) + { + am_hal_flash_delay(FLASH_CYCLES_US(10)); + + if ( (PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) == 0 ) + { + break; + } + } + + // + // Check the device status. + // + if ( ( PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } +} + +//***************************************************************************** +// +//! @brief Determine whether a peripheral is currently enabled. +//! +//! @param ePeripheral - The peripheral to enable. +//! @param pui32Enabled - Pointer to a ui32 that will return as 1 or 0. +//! +//! This function determines to the caller whether a given peripheral is +//! currently enabled or disabled. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_pwrctrl_periph_enabled(am_hal_pwrctrl_periph_e ePeripheral, + uint32_t *pui32Enabled) +{ + uint32_t ui32Mask = 0; + uint32_t ui32Enabled = 0; + + if ( pui32Enabled == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + switch ( ePeripheral ) + { + case AM_HAL_PWRCTRL_PERIPH_NONE: + case AM_HAL_PWRCTRL_PERIPH_SCARD: + break; + case AM_HAL_PWRCTRL_PERIPH_IOS: + case AM_HAL_PWRCTRL_PERIPH_UART0: + case AM_HAL_PWRCTRL_PERIPH_UART1: + ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPA_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_IOM0: + case AM_HAL_PWRCTRL_PERIPH_IOM1: + case AM_HAL_PWRCTRL_PERIPH_IOM2: + ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPB_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_IOM3: + case AM_HAL_PWRCTRL_PERIPH_IOM4: + case AM_HAL_PWRCTRL_PERIPH_IOM5: + ui32Mask = PWRCTRL_DEVPWRSTATUS_HCPC_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_ADC: + ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRADC_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_MSPI: + ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_PDM: + ui32Mask = PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk; + break; + case AM_HAL_PWRCTRL_PERIPH_BLEL: + ui32Mask = PWRCTRL_DEVPWRSTATUS_BLEL_Msk; + break; + default: + return AM_HAL_STATUS_FAIL; + } + + if ( ui32Mask != 0 ) + { + ui32Enabled = PWRCTRL->DEVPWRSTATUS & ui32Mask ? 1 : 0; + } + + *pui32Enabled = ui32Enabled; + + return AM_HAL_STATUS_SUCCESS; +} + + + +// **************************************************************************** +// +// am_hal_pwrctrl_memory_enable() +// Enable a configuration of memory. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_memory_enable(am_hal_pwrctrl_mem_e eMemConfig) +{ + uint32_t ui32MemEnMask, ui32MemDisMask, ui32MemRegionMask, ui32MemStatusMask; + + ui32MemEnMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryEnable; + ui32MemDisMask = ~am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryEnable; + ui32MemRegionMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryMask; + ui32MemStatusMask = am_hal_pwrctrl_memory_control[eMemConfig].ui32StatusMask; + + // + // Disable unneeded memory. If nothing to be disabled, skip to save time. + // + // Note that a deliberate disable step using a disable mask is taken here + // for 2 reasons: 1) To only affect the specified type of memory, and 2) + // To avoid inadvertently disabling any memory currently being depended on. + // + if ( ui32MemDisMask != 0 ) + { + PWRCTRL->MEMPWREN &= + ~(ui32MemDisMask & ui32MemRegionMask) | + (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0) | + _VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN)); + am_hal_flash_delay(FLASH_CYCLES_US(1)); + } + + + // + // Enable the required memory. + // + if ( ui32MemEnMask != 0 ) + { + PWRCTRL->MEMPWREN |= ui32MemEnMask; + + for (uint32_t wait_usecs = 0; wait_usecs < AM_HAL_PWRCTRL_MAX_WFE; wait_usecs += 10) + { + am_hal_flash_delay(FLASH_CYCLES_US(10)); + + if ( (PWRCTRL->MEMPWRSTATUS & ui32MemStatusMask) == + am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryStatus ) + { + break; + } + } + } + + // + // Return status based on whether the power control memory status has reached the desired state. + // + if ( ( PWRCTRL->MEMPWRSTATUS & ui32MemStatusMask) == + am_hal_pwrctrl_memory_control[eMemConfig].ui32MemoryStatus ) + { + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_FAIL; + } +} + +// **************************************************************************** +// +// am_hal_pwrctrl_memory_deepsleep_powerdown() +// Power down respective memory. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_memory_deepsleep_powerdown(am_hal_pwrctrl_mem_e eMemConfig) +{ + if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX ) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Power down the required memory. + // + PWRCTRL->MEMPWDINSLEEP |= am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_pwrctrl_memory_deepsleep_retain() +// Apply retention voltage to respective memory. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_memory_deepsleep_retain(am_hal_pwrctrl_mem_e eMemConfig) +{ + if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX ) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Retain the required memory. + // + PWRCTRL->MEMPWDINSLEEP &= ~am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +// **************************************************************************** +// +// am_hal_pwrctrl_low_power_init() +// Initialize system for low power configuration. +// +// **************************************************************************** +uint32_t +am_hal_pwrctrl_low_power_init(void) +{ + uint32_t ui32Status; + + // + // Take a snapshot of the reset status, if not done already + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + + // + // Software workaround for Errata ERR019. + // + if ((APOLLO3_A1) && (1 == PWRCTRL->SUPPLYSTATUS_b.SIMOBUCKON)) + { + ui32Status = am_hal_pwrctrl_periph_enable(AM_HAL_PWRCTRL_PERIPH_PDM); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } + + // + // Adjust the SIMOBUCK LP settings. + // + if (APOLLO3_GE_B0) + { + MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPHIGHTONTRIM = 2; + MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPLOWTONTRIM = 3; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPHIGHTOFFTRIM = 5; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPLOWTOFFTRIM = 2; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTOFFTRIM = 6; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPLOWTOFFTRIM = 1; + MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTONTRIM = 3; + MCUCTRL->SIMOBUCK4_b.SIMOBUCKMEMLPLOWTONTRIM = 3; + } + + // + // Adjust the SIMOBUCK Timeout settings. + // + if (APOLLO3_GE_A1) + { + MCUCTRL->SIMOBUCK4_b.SIMOBUCKCOMP2TIMEOUTEN = 0; + } + + // + // Configure cache for low power and performance. + // + am_hal_cachectrl_control(AM_HAL_CACHECTRL_CONTROL_LPMMODE_RECOMMENDED, 0); + + // + // Check if the BLE is already enabled. + // + if ( PWRCTRL->DEVPWRSTATUS_b.BLEL == 0) + { + // + // First request the BLE feature and check that it was available and acknowledged. + // + MCUCTRL->FEATUREENABLE_b.BLEREQ = 1; + ui32Status = am_hal_flash_delay_status_check(10000, + (uint32_t)&MCUCTRL->FEATUREENABLE, + (MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk | + MCUCTRL_FEATUREENABLE_BLEACK_Msk | + MCUCTRL_FEATUREENABLE_BLEREQ_Msk), + (MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk | + MCUCTRL_FEATUREENABLE_BLEACK_Msk | + MCUCTRL_FEATUREENABLE_BLEREQ_Msk), + true); + + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return AM_HAL_STATUS_TIMEOUT; + } + + // + // Next, enable the BLE Buck. + // + PWRCTRL->SUPPLYSRC |= _VAL2FLD(PWRCTRL_SUPPLYSRC_BLEBUCKEN, + PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN); + + // + // Allow the buck to go to low power mode in BLE sleep. + // + PWRCTRL->MISC |= _VAL2FLD(PWRCTRL_MISC_MEMVRLPBLE, + PWRCTRL_MISC_MEMVRLPBLE_EN); + + // + // Check for Apollo3 A0 Silicon. + // + if ( APOLLO3_A0 ) + { + // Disable SIMO Buck clkdiv because if ble is out of reset then the same bit divides the simobuck clk too aggressively. + MCUCTRL->SIMOBUCK4_b.SIMOBUCKCLKDIVSEL = 0x0; + MCUCTRL->BLEBUCK2_b.BLEBUCKTONHITRIM = 0xF; + MCUCTRL->BLEBUCK2_b.BLEBUCKTONLOWTRIM = 0xF; + } + } + + return AM_HAL_STATUS_SUCCESS; +} + +void am_hal_pwrctrl_blebuck_trim(void) +{ + // + // Enable the BLE buck trim values + // + if ( APOLLO3_GE_A1 ) + { + AM_CRITICAL_BEGIN + MCUCTRL->BLEBUCK2_b.BLEBUCKTONHITRIM = 0x19; + MCUCTRL->BLEBUCK2_b.BLEBUCKTONLOWTRIM = 0xC; + CLKGEN->BLEBUCKTONADJ_b.TONADJUSTEN = CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS; + AM_CRITICAL_END + } + +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.h new file mode 100644 index 0000000000..859a3b4d2a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl.h @@ -0,0 +1,261 @@ +//***************************************************************************** +// +// am_hal_pwrctrl.h +//! @file +//! +//! @brief Functions for enabling and disabling power domains. +//! +//! @addtogroup pwrctrl3 Power Control +//! @ingroup apollo3hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PWRCTRL_H +#define AM_HAL_PWRCTRL_H + +// +// Designate this peripheral. +// +#define AM_APOLLO3_PWRCTRL 1 + +typedef enum +{ + AM_HAL_PWRCTRL_PERIPH_NONE, + AM_HAL_PWRCTRL_PERIPH_IOS, + AM_HAL_PWRCTRL_PERIPH_IOM0, + AM_HAL_PWRCTRL_PERIPH_IOM1, + AM_HAL_PWRCTRL_PERIPH_IOM2, + AM_HAL_PWRCTRL_PERIPH_IOM3, + AM_HAL_PWRCTRL_PERIPH_IOM4, + AM_HAL_PWRCTRL_PERIPH_IOM5, + AM_HAL_PWRCTRL_PERIPH_UART0, + AM_HAL_PWRCTRL_PERIPH_UART1, + AM_HAL_PWRCTRL_PERIPH_ADC, + AM_HAL_PWRCTRL_PERIPH_SCARD, + AM_HAL_PWRCTRL_PERIPH_MSPI, + AM_HAL_PWRCTRL_PERIPH_PDM, + AM_HAL_PWRCTRL_PERIPH_BLEL, + AM_HAL_PWRCTRL_PERIPH_MAX +} am_hal_pwrctrl_periph_e; + +typedef enum +{ + AM_HAL_PWRCTRL_MEM_NONE, + AM_HAL_PWRCTRL_MEM_SRAM_8K_DTCM, + AM_HAL_PWRCTRL_MEM_SRAM_32K_DTCM, + AM_HAL_PWRCTRL_MEM_SRAM_64K_DTCM, + AM_HAL_PWRCTRL_MEM_SRAM_96K, + AM_HAL_PWRCTRL_MEM_SRAM_128K, + AM_HAL_PWRCTRL_MEM_SRAM_160K, + AM_HAL_PWRCTRL_MEM_SRAM_192K, + AM_HAL_PWRCTRL_MEM_SRAM_224K, + AM_HAL_PWRCTRL_MEM_SRAM_256K, + AM_HAL_PWRCTRL_MEM_SRAM_288K, + AM_HAL_PWRCTRL_MEM_SRAM_320K, + AM_HAL_PWRCTRL_MEM_SRAM_352K, + AM_HAL_PWRCTRL_MEM_SRAM_384K, + AM_HAL_PWRCTRL_MEM_FLASH_512K, + AM_HAL_PWRCTRL_MEM_FLASH_1M, + AM_HAL_PWRCTRL_MEM_CACHE, + AM_HAL_PWRCTRL_MEM_ALL, + AM_HAL_PWRCTRL_MEM_MAX +} am_hal_pwrctrl_mem_e; + +#define AM_HAL_PWRCTRL_MEM_FLASH_MIN AM_HAL_PWRCTRL_MEM_FLASH_512K +#define AM_HAL_PWRCTRL_MEM_FLASH_MAX AM_HAL_PWRCTRL_MEM_FLASH_1M + +#define AM_HAL_PWRCTRL_MEM_SRAM_MIN AM_HAL_PWRCTRL_MEM_SRAM_8K_DTCM +#define AM_HAL_PWRCTRL_MEM_SRAM_MAX AM_HAL_PWRCTRL_MEM_SRAM_384K + +//***************************************************************************** +// +// Macros to check whether Apollo3 bucks are enabled. +// +//***************************************************************************** +#define am_hal_pwrctrl_simobuck_enabled_check() \ + (AM_BFR(PWRCTRL, SUPPLYSTATUS, SIMOBUCKON)) + +#define am_hal_pwrctrl_blebuck_enabled_check() \ + (AM_BFR(PWRCTRL, SUPPLYSTATUS, BLEBUCKON)) + +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief Enable power to a peripheral. +//! +//! @param ePeripheral - The peripheral to enable. +//! +//! This function enables power to the peripheral and waits for a +//! confirmation from the hardware. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral); + +//***************************************************************************** +// +//! @brief Disable power to a peripheral. +//! +//! @param ePeripheral - The peripheral to disable. +//! +//! This function disables power to the peripheral and waits for a +//! confirmation from the hardware. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral); + +//***************************************************************************** +// +//! @brief Determine whether a peripheral is currently enabled. +//! +//! @param ePeripheral - The peripheral to enable. +//! @param pui32Enabled - Pointer to a ui32 that will return as 1 or 0. +//! +//! This function determines to the caller whether a given peripheral is +//! currently enabled or disabled. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_periph_enabled( + am_hal_pwrctrl_periph_e ePeripheral, uint32_t *pui32Enabled); + +//***************************************************************************** +// +//! @brief Enable a configuration of memory. +//! +//! @param eMemConfig - The memory configuration. +//! +//! This function establishes the desired configuration of flash, SRAM, ICache, +//! and DCache (DTCM) according to the desired Memory Configuration mask. +//! +//! Only the type of memory specified is affected. Therefore separate calls +//! are required to affect power settings for FLASH, SRAM, or CACHE. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_memory_enable(am_hal_pwrctrl_mem_e eMemConfig); + +//***************************************************************************** +// +//! @brief Power down respective memory. +//! +//! @param eMemPwd - The memory power down enum. +//! +//! This function establishes the desired power down of flash, SRAM, ICache, +//! and DCache (DTCM) according to the desired enum. +//! +//! Only the type of memory specified is affected. Therefore separate calls +//! are required to affect power settings for FLASH, SRAM, or CACHE. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_memory_deepsleep_powerdown(am_hal_pwrctrl_mem_e eMemConfig); + +//***************************************************************************** +// +//! @brief Apply retention voltage to respective memory. +//! +//! @param eMemPwd - The memory power down enum. +//! +//! This function establishes the desired power retain of flash, SRAM, ICache, +//! and DCache (DTCM) according to the desired enum. +//! +//! Only the type of memory specified is affected. Therefore separate calls +//! are required to affect power settings for FLASH, SRAM, or CACHE. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_memory_deepsleep_retain(am_hal_pwrctrl_mem_e eMemConfig); + +//***************************************************************************** +// +//! @brief Initialize system for low power configuration. +//! +//! @param none. +//! +//! This function handles low power initialization. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_pwrctrl_low_power_init(void); + +//***************************************************************************** +// +//! @brief Initialize BLE Buck Trims for Lowest Power. +//! +//! @param none. +//! +//! @return none. +// +//***************************************************************************** +extern void am_hal_pwrctrl_blebuck_trim(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_PWRCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl_internal.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl_internal.h new file mode 100644 index 0000000000..46ededf9a5 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_pwrctrl_internal.h @@ -0,0 +1,340 @@ +//***************************************************************************** +// +// am_hal_pwrctrl_internal.h +//! @file +//! +//! @brief Internal definitions for Power Control +//! +//! @addtogroup pwrctrl3 Power Control +//! @ingroup apollo3hal +//! @{ + +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_PWRCTRL_INTERNAL_H +#define AM_HAL_PWRCTRL_INTERNAL_H + + +//***************************************************************************** +// +// Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable() +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_IOS (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN)) +#define AM_HAL_PWRCTRL_IOM0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN)) +#define AM_HAL_PWRCTRL_IOM1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN)) +#define AM_HAL_PWRCTRL_IOM2 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN)) +#define AM_HAL_PWRCTRL_IOM3 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN)) +#define AM_HAL_PWRCTRL_IOM4 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN)) +#define AM_HAL_PWRCTRL_IOM5 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN)) +#define AM_HAL_PWRCTRL_UART0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN)) +#define AM_HAL_PWRCTRL_UART1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN)) +#define AM_HAL_PWRCTRL_ADC (_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN)) +#define AM_HAL_PWRCTRL_SCARD (_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN)) +#define AM_HAL_PWRCTRL_MSPI (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI, PWRCTRL_DEVPWREN_PWRMSPI_EN)) +#define AM_HAL_PWRCTRL_PDM (_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN)) +#define AM_HAL_PWRCTRL_BLEL (_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN)) + +#define AM_HAL_PWRCTRL_DEVPWREN_MASK 0x00003FFF +#define AM_HAL_PWRCTRL_DEVPWRSTATUS_MASK 0x000003FC + +//***************************************************************************** +// +// Memory enable values for all defined memory configurations. +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_96K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP0)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_128K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_96K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP1)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_160K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_128K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP2)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_192K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_160K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP3)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_224K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_192K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP4)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_256K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_224K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP5)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_288K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_256K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP6)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_320K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_288K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP7)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_352K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_320K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP8)) +#define AM_HAL_PWRCTRL_MEMEN_SRAM_384K \ + (AM_HAL_PWRCTRL_MEMEN_SRAM_352K | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP9)) + +#define AM_HAL_PWRCTRL_MEMEN_SRAM_ALL (AM_HAL_PWRCTRL_MEMEN_SRAM_384K) +#define AM_HAL_PWRCTRL_MEMEN_FLASH_512K PWRCTRL_MEMPWREN_FLASH0_Msk +#define AM_HAL_PWRCTRL_MEMEN_FLASH_1M \ + (PWRCTRL_MEMPWREN_FLASH0_Msk | PWRCTRL_MEMPWREN_FLASH1_Msk) +#define AM_HAL_PWRCTRL_MEMEN_CACHE \ + (PWRCTRL_MEMPWREN_CACHEB0_Msk | PWRCTRL_MEMPWREN_CACHEB2_Msk) +#define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS (~AM_HAL_PWRCTRL_MEMEN_CACHE) + +// +// Power up all available memory devices (this is the default power up state) +// +#define AM_HAL_PWRCTRL_MEMEN_ALL \ + (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_FLASH1, PWRCTRL_MEMPWREN_FLASH1_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB0, PWRCTRL_MEMPWREN_CACHEB0_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB2, PWRCTRL_MEMPWREN_CACHEB2_EN)) + +//***************************************************************************** +// +// Memory deepsleep powerdown values for all defined memory configurations. +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8)) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K \ + (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9)) + +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_ALL (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_512K PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M \ + (PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk | PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE (PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk) +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE_DIS (~AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE) + +// +// Power down all available memory devices +// +#define AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL \ + (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN) | \ + _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP, PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN)) + +//***************************************************************************** +// +// Memory status values for all defined memory configurations +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM \ + (PWRCTRL_MEMPWRSTATUS_DTCM00_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM | \ + PWRCTRL_MEMPWRSTATUS_DTCM01_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM | \ + PWRCTRL_MEMPWRSTATUS_DTCM1_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM | \ + PWRCTRL_MEMPWRSTATUS_SRAM0_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K | \ + PWRCTRL_MEMPWRSTATUS_SRAM1_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K | \ + PWRCTRL_MEMPWRSTATUS_SRAM2_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K | \ + PWRCTRL_MEMPWRSTATUS_SRAM3_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K | \ + PWRCTRL_MEMPWRSTATUS_SRAM4_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K | \ + PWRCTRL_MEMPWRSTATUS_SRAM5_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K | \ + PWRCTRL_MEMPWRSTATUS_SRAM6_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K | \ + PWRCTRL_MEMPWRSTATUS_SRAM7_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K | \ + PWRCTRL_MEMPWRSTATUS_SRAM8_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K | \ + PWRCTRL_MEMPWRSTATUS_SRAM9_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K) +#define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K \ + (PWRCTRL_MEMPWRSTATUS_FLASH0_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M \ + (AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K | \ + PWRCTRL_MEMPWRSTATUS_FLASH1_Msk) +#define AM_HAL_PWRCTRL_PWRONSTATUS_ALL \ + (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K | \ + AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M) + +//***************************************************************************** +// +// Memory event values for all defined memory configurations +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K \ + ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ + PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ + PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH0EN, \ + PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN)) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH1EN, \ + PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE \ + ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB0EN, \ + PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN)) | \ + (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB2EN, \ + PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN))) +#define AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL \ + (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K | \ + AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M | \ + AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE) + +//***************************************************************************** +// +// Memory region mask values for all defined memory configurations +// +//***************************************************************************** +#define AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK AM_HAL_PWRCTRL_MEMEN_SRAM_ALL +#define AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK AM_HAL_PWRCTRL_MEMEN_FLASH_1M +#define AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK AM_HAL_PWRCTRL_MEMEN_CACHE +#define AM_HAL_PWRCTRL_MEM_REGION_ALT_CACHE_MASK AM_HAL_PWRCTRL_PWRONSTATUS_CACHE +#define AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK AM_HAL_PWRCTRL_MEMEN_ALL +#define AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK AM_HAL_PWRCTRL_PWRONSTATUS_ALL + + +#endif // AM_HAL_PWRCTRL_INTERNAL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.c new file mode 100644 index 0000000000..d48850b941 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.c @@ -0,0 +1,294 @@ +//***************************************************************************** +// +// am_hal_queue.c +//! @file +//! +//! @brief Functions for implementing a queue system. +//! +//! @addtogroup queue3 (QUEUE) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Initializes a queue. +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvData - Pointer to a memory location to be used for data storage. +//! @param ui32ItemSize - Number of bytes per item in the queue. +//! @param ui32ArraySize - Number of bytes in the data array. +//! +//! This function initializes the members of a queue structure and attaches it +//! to an array of memory that it can use for storage. This function should be +//! called before the queue is used. +//! +//! In this example, we are creating a queue that can hold 1024 32-bit +//! integers. The integers themselves will be stored in the array named +//! pui32WorkingSpace, while information about the queue itself will be stored +//! in sDataQueue. +//! +//! @note The caller should not modify any of the members of am_hal_queue_t +//! structures. The queue API will handle these members in a thread-safe way. +//! +//! @note The queue will remember what size data is in it. Other queue API +//! functions will perform transfers in units of "items" where one "item" is +//! the number of bytes you specify in the \e ui32ItemSize argument upon +//! initialization. +//! +//! Example usage: +//! +//! @code +//! +//! // +//! // Declare a queue structure and an array of bytes we can use to store +//! // data. +//! // +//! am_hal_queue_t sDataQueue; +//! uint32_t pui32WorkingSpace[1024]; +//! +//! // +//! // Attach the queue structure to the working memory. +//! // +//! am_hal_queue_init(&sDataQueue, pui8WorkingSpace, sizeof(uint32_t) +//! sizeof(pui32WorkingSpace)); +//! +//! @endcode +//! +//! The am_hal_queue_from_array macro is a convenient shorthand for this +//! operation. The code below does the same thing as the code above. +//! +//! @code +//! +//! // +//! // Declare a queue structure and an array of bytes we can use to store +//! // data. +//! // +//! am_hal_queue_t sDataQueue; +//! uint32_t pui32WorkingSpace[1024]; +//! +//! // +//! // Attach the queue structure to the working memory. +//! // +//! am_hal_queue_from_array(&sDataQueue, pui8WorkingSpace); +//! +//! @endcode +// +//***************************************************************************** +void +am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize, + uint32_t ui32ArraySize) +{ + psQueue->ui32WriteIndex = 0; + psQueue->ui32ReadIndex = 0; + psQueue->ui32Length = 0; + psQueue->ui32Capacity = ui32ArraySize; + psQueue->ui32ItemSize = ui32ItemSize; + psQueue->pui8Data = (uint8_t *) pvData; +} + +//***************************************************************************** +// +//! @brief Adds an item to the Queue +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvSource - Pointer to the data to be added. +//! @param ui32NumItems - Number of items to be added. +//! +//! This function will copy the data pointed to by pvSource into the queue. The +//! \e ui32NumItems term specifies the number of items to be copied from \e +//! pvSource. The size of an "item" depends on how the queue was initialized. +//! Please see am_hal_queue_init() for more information on this. +//! +//! @return true if the add operation was successful, or false if the queue +//! didn't have enough space. +// +//***************************************************************************** +bool +am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems) +{ + uint8_t *pui8Source; + uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize; + bool bSuccess = false; + + pui8Source = (uint8_t *) pvSource; + + AM_CRITICAL_BEGIN + + // + // Check to make sure that the buffer isn't already full + // + if ( am_hal_queue_space_left(psQueue) >= ui32Bytes ) + { + // + // Loop over the bytes in the source array. + // + for ( uint32_t i = 0; i < ui32Bytes; i++ ) + { + // + // Write the value to the buffer, but only if the source pointer is + // valid. + // + if (pvSource) + { + psQueue->pui8Data[psQueue->ui32WriteIndex] = pui8Source[i]; + } + + // + // Advance the write index, making sure to wrap if necessary. + // + psQueue->ui32WriteIndex = ((psQueue->ui32WriteIndex + 1) % + psQueue->ui32Capacity); + } + + // + // Update the length value appropriately. + // + psQueue->ui32Length += ui32Bytes; + + // + // Report a success. + // + bSuccess = true; + } + else + { + // + // The buffer can't fit the amount of data requested. Return a + // failure. + // + bSuccess = false; + } + + AM_CRITICAL_END + + return bSuccess; +} + +//***************************************************************************** +// +//! @brief Removes an item from the Queue +//! +//! @param psQueue - Pointer to a queue structure. +//! @param pvDest - Pointer to the data to be added. +//! @param ui32NumItems - Number of items to be added. +//! +//! This function will copy the data from the queue into the memory pointed to +//! by pvDest. The \e ui32NumItems term specifies the number of items to be +//! copied from the queue. The size of an "item" depends on how the queue was +//! initialized. Please see am_hal_queue_init() for more information on this. +//! +//! @return true if we were able to pull the requested number of items from the +//! queue, or false if the queue didn't have that many items to pull. +// +//***************************************************************************** +bool +am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems) +{ + uint8_t *pui8Dest; + uint32_t ui32Bytes = ui32NumItems * psQueue->ui32ItemSize; + bool bSuccess = false; + + pui8Dest = (uint8_t *) pvDest; + + AM_CRITICAL_BEGIN + + // + // Check to make sure that the buffer isn't empty + // + if ( am_hal_queue_data_left(psQueue) >= ui32Bytes ) + { + // + // Loop over the bytes in the destination array. + // + for ( uint32_t i = 0; i < ui32Bytes; i++ ) + { + // + // Grab the next value from the buffer, but only if the + // destination pointer is valid. + // + if (pvDest) + { + pui8Dest[i] = psQueue->pui8Data[psQueue->ui32ReadIndex]; + } + + // + // Advance the read index, wrapping if needed. + // + psQueue->ui32ReadIndex = ((psQueue->ui32ReadIndex + 1) % + psQueue->ui32Capacity); + } + + // + // Adjust the length value to reflect the change. + // + psQueue->ui32Length -= ui32Bytes; + + // + // Report a success. + // + bSuccess = true; + } + else + { + // + // If the buffer didn't have enough data, just return false. + // + bSuccess = false; + } + + AM_CRITICAL_END + + return bSuccess; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.h new file mode 100644 index 0000000000..73a8228cad --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_queue.h @@ -0,0 +1,165 @@ +//***************************************************************************** +// +// am_hal_queue.h +//! @file +//! +//! @brief Functions for implementing a queue system. +//! +//! @addtogroup queue3 (QUEUE) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_QUEUE_H +#define AM_HAL_QUEUE_H + +//***************************************************************************** +// +//! @brief A data structure that will operate as a queue. +//! +//! This data structure holds information necessary for operating a thread-safe +//! queue. When declaring a structure of type am_hal_queue_t, you will also need +//! to provide some working memory for the queue to use. For more information on +//! setting up and using the am_hal_queue_t structure, please see the +//! documentation for am_hal_queue_init(). +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32WriteIndex; + uint32_t ui32ReadIndex; + uint32_t ui32Length; + uint32_t ui32Capacity; + uint32_t ui32ItemSize; + uint8_t *pui8Data; +} +am_hal_queue_t; + +//***************************************************************************** +// +// Function-like macros. +// +//***************************************************************************** + +// +// Returns true if the queue is empty. +// +#define am_hal_queue_empty(psQueue) \ + ((psQueue)->ui32Length == 0) + +// +// Returns true if the queue is full. +// +#define am_hal_queue_full(psQueue) \ + ((psQueue)->ui32Length == (psQueue)->ui32Capacity) + +// +// Returns the amount of space left in the queue (in bytes). +// +#define am_hal_queue_space_left(psQueue) \ + ((psQueue)->ui32Capacity - (psQueue)->ui32Length) + +// +// Returns the number of configured items that will fit in the queue. +// +#define am_hal_queue_slots_left(psQueue) \ + (((psQueue)->ui32Capacity - (psQueue)->ui32Length) \ + / (psQueue)->ui32ItemSize) + +// +// Returns the amount of data in the queue (in bytes). +// +#define am_hal_queue_data_left(psQueue) \ + ((psQueue)->ui32Length) + +// +// Returns the number of configured items left in the queue. +// +#define am_hal_queue_items_left(psQueue) \ + ((psQueue)->ui32Length / (psQueue)->ui32ItemSize) + +// +// Can be used as a pointer to the next item to be read from the queue. +// +#define am_hal_queue_peek(psQueue) \ + ((void *) &((psQueue)->pui8Data[(psQueue)->ui32ReadIndex])) + +// +// Can be used as a pointer to the next available slot in the queue memory. +// +#define am_hal_queue_next_slot(psQueue) \ + ((void *) &((psQueue)->pui8Data[(psQueue)->ui32WriteIndex])) + +//***************************************************************************** +// +// Use this to make sure you get the size parameters right. +// +//***************************************************************************** +#define am_hal_queue_from_array(queue, array) \ + am_hal_queue_init((queue), (array), sizeof((array)[0]), sizeof(array)) + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_hal_queue_init(am_hal_queue_t *psQueue, void *pvData, uint32_t ui32ItemSize, uint32_t ui32ArraySize); +extern bool am_hal_queue_item_add(am_hal_queue_t *psQueue, const void *pvSource, uint32_t ui32NumItems); +extern bool am_hal_queue_item_get(am_hal_queue_t *psQueue, void *pvDest, uint32_t ui32NumItems); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_QUEUE_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.c new file mode 100644 index 0000000000..4b45984af2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.c @@ -0,0 +1,314 @@ +//***************************************************************************** +// +// am_hal_reset.c +//! @file +//! +//! @brief Hardware abstraction layer for the Reset Generator module. +//! +//! @addtogroup rstgen3 Reset Generator (RSTGEN) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_mcu_apollo.h" + +uint32_t gAmHalResetStatus = 0; + +//***************************************************************************** +// +// am_hal_reset_enable() +// Enable and configure the Reset controller. +// +//***************************************************************************** +uint32_t +am_hal_reset_configure(am_hal_reset_configure_e eConfigure) +{ + uint32_t ui32Val; + bool bEnable; + + switch ( eConfigure ) + { + case AM_HAL_RESET_BROWNOUT_HIGH_ENABLE: + bEnable = true; + ui32Val = RSTGEN_CFG_BODHREN_Msk; + break; + + case AM_HAL_RESET_WDT_RESET_ENABLE: + bEnable = true; + ui32Val = RSTGEN_CFG_WDREN_Msk; + break; + + case AM_HAL_RESET_BROWNOUT_HIGH_DISABLE: + bEnable = false; + ui32Val = RSTGEN_CFG_BODHREN_Msk; + break; + + case AM_HAL_RESET_WDT_RESET_DISABLE: + bEnable = false; + ui32Val = RSTGEN_CFG_WDREN_Msk; + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + AM_CRITICAL_BEGIN + if ( bEnable ) + { + RSTGEN->CFG |= ui32Val; + } + else + { + RSTGEN->CFG &= ~ui32Val; + } + AM_CRITICAL_END + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_configure() + + +//***************************************************************************** +// +// am_hal_reset_control() +// Perform various reset functions including assertion of software resets. +// +//***************************************************************************** +uint32_t +am_hal_reset_control(am_hal_reset_control_e eControl, void *pArgs) +{ + switch ( eControl ) + { + case AM_HAL_RESET_CONTROL_SWPOR: + // + // Perform a Power On Reset level reset. + // Write the POR key to the software POR register. + // + RSTGEN->SWPOR = + _VAL2FLD(RSTGEN_SWPOR_SWPORKEY, RSTGEN_SWPOR_SWPORKEY_KEYVALUE); + break; + + case AM_HAL_RESET_CONTROL_SWPOI: + // + // Perform a Power On Initialization level reset. + // Write the POI key to the software POI register. + // + RSTGEN->SWPOI = + _VAL2FLD(RSTGEN_SWPOI_SWPOIKEY, RSTGEN_SWPOI_SWPOIKEY_KEYVALUE); + break; + + case AM_HAL_RESET_CONTROL_STATUSCLEAR: + // + // Clear ALL of the reset status register bits. + // + RSTGEN->STAT = 0; + break; + + case AM_HAL_RESET_CONTROL_TPIU_RESET: + // + // Reset the TPIU. + // + RSTGEN->TPIURST = _VAL2FLD(RSTGEN_TPIURST_TPIURST, 1); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_control() + + +//***************************************************************************** +// +// am_hal_reset_status_get() +// Return status of the reset generator. +// Application MUST call this API at least once before going to deepsleep +// Otherwise this API will not provide correct reset status +// +//***************************************************************************** +uint32_t +am_hal_reset_status_get(am_hal_reset_status_t *psStatus) +{ + // Need to read the status only the very first time + + if ( psStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Retrieve the reset generator status bits + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + psStatus->eStatus = (am_hal_reset_status_e)gAmHalResetStatus; + psStatus->bEXTStat = _FLD2VAL(RSTGEN_STAT_EXRSTAT, gAmHalResetStatus); + psStatus->bPORStat = _FLD2VAL(RSTGEN_STAT_PORSTAT, gAmHalResetStatus); + psStatus->bBODStat = _FLD2VAL(RSTGEN_STAT_BORSTAT, gAmHalResetStatus); + psStatus->bSWPORStat = _FLD2VAL(RSTGEN_STAT_SWRSTAT, gAmHalResetStatus); + psStatus->bSWPOIStat = _FLD2VAL(RSTGEN_STAT_POIRSTAT, gAmHalResetStatus); + psStatus->bDBGRStat = _FLD2VAL(RSTGEN_STAT_DBGRSTAT, gAmHalResetStatus); + psStatus->bWDTStat = _FLD2VAL(RSTGEN_STAT_WDRSTAT, gAmHalResetStatus); + psStatus->bBOUnregStat = _FLD2VAL(RSTGEN_STAT_BOUSTAT, gAmHalResetStatus); + psStatus->bBOCOREStat = _FLD2VAL(RSTGEN_STAT_BOCSTAT, gAmHalResetStatus); + psStatus->bBOMEMStat = _FLD2VAL(RSTGEN_STAT_BOFSTAT, gAmHalResetStatus); + psStatus->bBOBLEStat = _FLD2VAL(RSTGEN_STAT_BOBSTAT, gAmHalResetStatus); + + // + // Return status. + // If the Reset Status is 0 - this implies application did not capture the snapshot + // before deepsleep, and hence the result is invalid + // + return (gAmHalResetStatus ? AM_HAL_STATUS_SUCCESS : AM_HAL_STATUS_FAIL); + +} // am_hal_reset_status_get() + +//***************************************************************************** +// +//! @brief Enable selected RSTGEN Interrupts. +//! +//! Use this function to enable the reset generator interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_enable(uint32_t ui32IntMask) +{ + AM_CRITICAL_BEGIN + RSTGEN->INTEN |= ui32IntMask; + AM_CRITICAL_END + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_enable() + +//***************************************************************************** +// +// am_hal_reset_interrupt_disable() +// Disable selected RSTGEN Interrupts. +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_disable(uint32_t ui32IntMask) +{ + AM_CRITICAL_BEGIN + RSTGEN->INTEN &= ~ui32IntMask; + AM_CRITICAL_END + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_disable() + +//***************************************************************************** +// +// am_hal_reset_interrupt_clear() +// Reset generator interrupt clear +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_clear(uint32_t ui32IntMask) +{ + RSTGEN->INTEN = ui32IntMask; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_clear() + +//***************************************************************************** +// +// am_hal_reset_interrupt_status_get() +// Get interrupt status of reset generator. +// +//***************************************************************************** +uint32_t +am_hal_reset_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus) +{ + if ( pui32IntStatus == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Retrieve the reset generator status bits + // + *pui32IntStatus = RSTGEN->INTSTAT; + + // + // Return success status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_reset_interrupt_status_get() + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.h new file mode 100644 index 0000000000..460dc74592 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_reset.h @@ -0,0 +1,308 @@ +//***************************************************************************** +// +// am_hal_reset.h +//! @file +//! +//! @brief Hardware abstraction layer for the Reset Generator module. +//! +//! @addtogroup rstgen3 Reset Generator (RSTGEN) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_RSTGEN_H +#define AM_HAL_RSTGEN_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Designate this peripheral. +// +#define AM_APOLLO3_RESET 1 + +//***************************************************************************** +// +// RESET specific definitions. +// +//***************************************************************************** +//************************************** +//! Reset Generator configuration values +//************************************** +typedef enum +{ + AM_HAL_RESET_BROWNOUT_HIGH_ENABLE, + AM_HAL_RESET_WDT_RESET_ENABLE, + AM_HAL_RESET_BROWNOUT_HIGH_DISABLE, + AM_HAL_RESET_WDT_RESET_DISABLE +} am_hal_reset_configure_e; + +//************************************** +//! Reset Generator control operations +//************************************** +typedef enum +{ + AM_HAL_RESET_CONTROL_SWPOR, + AM_HAL_RESET_CONTROL_SWPOI, + AM_HAL_RESET_CONTROL_STATUSCLEAR, + AM_HAL_RESET_CONTROL_TPIU_RESET +} am_hal_reset_control_e; + +//************************************** +//! Reset Generator status bits +//************************************** +typedef enum +{ + AM_HAL_RESET_STATUS_EXTERNAL = RSTGEN_STAT_EXRSTAT_Msk, + AM_HAL_RESET_STATUS_POR = RSTGEN_STAT_PORSTAT_Msk, + AM_HAL_RESET_STATUS_BOD = RSTGEN_STAT_BORSTAT_Msk, + AM_HAL_RESET_STATUS_SWPOR = RSTGEN_STAT_SWRSTAT_Msk, + AM_HAL_RESET_STATUS_SWPOI = RSTGEN_STAT_POIRSTAT_Msk, + AM_HAL_RESET_STATUS_DEBUGGER = RSTGEN_STAT_DBGRSTAT_Msk, + AM_HAL_RESET_STATUS_WDT = RSTGEN_STAT_WDRSTAT_Msk, + AM_HAL_RESET_STATUS_BOUNREG = RSTGEN_STAT_BOUSTAT_Msk, + AM_HAL_RESET_STATUS_BOCORE = RSTGEN_STAT_BOCSTAT_Msk, + AM_HAL_RESET_STATUS_BOMEM = RSTGEN_STAT_BOFSTAT_Msk, + AM_HAL_RESET_STATUS_BOBLE = RSTGEN_STAT_BOBSTAT_Msk +} am_hal_reset_status_e; + +//************************************** +//! RESET status structure +//************************************** +typedef struct +{ + am_hal_reset_status_e + eStatus; // Return all status bits from RSTGEN.STAT + bool bEXTStat; // External reset + bool bPORStat; // Power-On reset + bool bBODStat; // Brown-Out reset + bool bSWPORStat; // SW Power-On reset or AIRCR reset + bool bSWPOIStat; // SW Power On Initialization reset + bool bDBGRStat; // Debugger reset + bool bWDTStat; // Watch Dog Timer reset + bool bBOUnregStat; // Unregulated Supply Brownout event + bool bBOCOREStat; // Core Regulator Brownout event + bool bBOMEMStat; // Memory Regulator Brownout event + bool bBOBLEStat; // BLE/Burst Regulator Brownout event +} am_hal_reset_status_t; + +// +// Define interrupt bit(s) +// +#define AM_HAL_RESET_INTERRUPT_BODH RSTGEN_INTEN_BODH_Msk + +// Global variable used to capture the reset status +extern uint32_t gAmHalResetStatus; + +//***************************************************************************** +// +//! @brief Enable and configure the Reset controller. +//! +//! This function will configure the specified reset conditions. +//! +//! @param eConfigure - One of configuration enumerations. +//! AM_HAL_RESET_BROWNOUT_HIGH_ENABLE +//! AM_HAL_RESET_WDT_RESET_ENABLE +//! AM_HAL_RESET_BROWNOUT_HIGH_DISABLE +//! AM_HAL_RESET_WDT_RESET_DISABLE +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_configure(am_hal_reset_configure_e eConfigure); + +//***************************************************************************** +// +//! @brief Reset generator functions. +//! +//! This function will perform various reset functions including assertion +//! of software resets. +//! +//! @param eControl - One of the control enumerations. +//! AM_HAL_RESET_CONTROL_SWPOR - power on reset, which results in a reset of +//! all blocks except for registers in clock gen, RTC, stimer, PMU. +//! Equivalent to the reset state obtained by a hardware reset, use of +//! the ARM AIRCR (Application Interrupt and Reset Control Register) +//! core register, debugger reset, watchdog timer expiration, or +//! brown-out event. +//! AM_HAL_RESET_CONTROL_SWPOI - power on initialization, which results in a +//! reset of all blocks except for registers in clock gen, RTC, stimer. +//! The POI reset level is required in order to enable configuration +//! changes such as memory protection. +//! AM_HAL_RESET_CONTROL_STATUSCLEAR - Clear the entire STATUS register. +//! All reset status register bits are cleared. +//! AM_HAL_RESET_CONTROL_TPIU - Reset the TPIU. +//! +//! @return status - generic or interface specific status. +//! When resetting the chip (SWPOR or SWPOI), the function will obviously +//! not return to the caller. +// +//***************************************************************************** +extern uint32_t am_hal_reset_control(am_hal_reset_control_e eControl, + void *pArgs); + +//***************************************************************************** +// +//! @brief Return status of the reset generator. +//! +//! This function will get the status bits from the reset generator. +//! The status value shows the type of reset(s) that have occurred since power +//! on +//! Application MUST call this API at least once before going to deepsleep +//! Otherwise this API will not provide correct reset status +//! +//! @param psStatus - Pointer to a data structure to receive the status +//! information. Most members of the structure are booleans that receive +//! the status of a particular bit. +//! +//! The eStatus member, however, returns a bitmask of one or more of the +//! following values: +//! AM_HAL_RESET_STATUS_EXTERNAL +//! AM_HAL_RESET_STATUS_POR +//! AM_HAL_RESET_STATUS_BOD +//! AM_HAL_RESET_STATUS_SWPOR +//! AM_HAL_RESET_STATUS_SWPOI +//! AM_HAL_RESET_STATUS_DEBUGGER +//! AM_HAL_RESET_STATUS_WDT +//! AM_HAL_RESET_STATUS_BOUNREG +//! AM_HAL_RESET_STATUS_BOCORE +//! AM_HAL_RESET_STATUS_BOMEM +//! AM_HAL_RESET_STATUS_BOBLE +//! +//! @return status. If the API was never called before a valid reset status +//! could be captured, AM_HAL_STATUS_FAIL is returned. +//! Otherwise AM_HAL_STATUS_SUCCESS implies valid reset status returned +// +//***************************************************************************** +extern uint32_t am_hal_reset_status_get(am_hal_reset_status_t *psStatus); + +//***************************************************************************** +// +//! @brief Static reset of the TPIU. +//! +//! Use this function to reset the TPIU. +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_tpiu_reset(void); + +//***************************************************************************** +// +//! @brief Enable selected RSTGEN Interrupts. +//! +//! Use this function to enable the interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_enable(uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Disable selected RSTGEN Interrupts. +//! +//! Use this function to disable the RSTGEN interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_disable(uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Reset generator interrupt clear +//! +//! @param ui32IntMask - Interrupt mask. +//! +//! This function clears the reset generator interrupts. +//! +//! @param ui32IntMask - One or more of the following bits, any of which can +//! be ORed together. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_clear(uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Get interrupt status of reset generator. +//! +//! This function returns the interrupt status for the reset generator. +//! +//! @param pui32IntStatus - ptr to uint32_t to return the interrupt status. +//! +//! The following are valid status bits. +//! AM_HAL_RESET_INTERRUPT_BODH +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +extern uint32_t am_hal_reset_interrupt_status_get(bool bEnabledOnly, + uint32_t *pui32IntStatus); + + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_RSTGEN_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.c new file mode 100644 index 0000000000..4117db5c77 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.c @@ -0,0 +1,651 @@ +//***************************************************************************** +// +// am_hal_rtc.c +//! @file +//! +//! @brief Functions for interfacing with the Real-Time Clock (RTC). +//! +//! @addtogroup rtc3 Real-Time Clock (RTC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Converts a Binary Coded Decimal (BCD) byte to its Decimal form. +// +//***************************************************************************** +static uint8_t +bcd_to_dec(uint8_t ui8BCDByte) +{ + return (((ui8BCDByte & 0xF0) >> 4) * 10) + (ui8BCDByte & 0x0F); +} + +//***************************************************************************** +// +// Converts a Decimal byte to its Binary Coded Decimal (BCD) form. +// +//***************************************************************************** +static uint8_t +dec_to_bcd(uint8_t ui8DecimalByte) +{ + return (((ui8DecimalByte / 10) << 4) | (ui8DecimalByte % 10)); +} + +//***************************************************************************** +// +//! @brief Selects the clock source for the RTC. +//! +//! @param ui32OSC the clock source for the RTC. +//! +//! This function selects the clock source for the RTC. +//! +//! Valid values for ui32OSC are: +//! +//! AM_HAL_RTC_OSC_XT +//! +//! @return None +//! +//! @note After selection of the RTC oscillator, a 2 second delay occurs before +//! the new setting is reflected in status. Therefore the CLKGEN.STATUS.OMODE +//! bit will not reflect the new status until after the 2s wait period. +//! +// +//***************************************************************************** +void +am_hal_rtc_osc_select(uint32_t ui32OSC) +{ + if ( ui32OSC == AM_HAL_RTC_OSC_XT ) + { + // Clear bit to 0 for XTAL + CLKGEN->OCTRL &= ~CLKGEN_OCTRL_OSEL_Msk; + } +} + +//***************************************************************************** +// +//! @brief Enable/Start the RTC oscillator. +//! +//! Starts the RTC oscillator. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_osc_enable(void) +{ + // + // Start the RTC Oscillator. + // + RTC->RTCCTL_b.RSTOP = 0; + +} + +//***************************************************************************** +// +//! @brief Disable/Stop the RTC oscillator. +//! +//! Stops the RTC oscillator. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_osc_disable(void) +{ + // + // Stop the RTC Oscillator. + // + RTC->RTCCTL_b.RSTOP = 1; +} + +//***************************************************************************** +// +//! @brief Configures the RTC for 12 or 24 hour time keeping. +//! +//! @param b12Hour - A 'true' configures the RTC for 12 hour time keeping. +//! +//! Configures the RTC for 12 (true) or 24 (false) hour time keeping. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_time_12hour(bool b12Hour) +{ + // + // Set the 12/24 hour bit. + // + RTC->RTCCTL_b.HR1224 = b12Hour; +} + +//***************************************************************************** +// +//! @brief Enable selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Enables the RTC interrupts. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupts. + // + RTC->INTEN |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled RTC interrupts. +//! +//! Returns the enabled RTC interrupts. +//! +//! @return enabled RTC interrupts. Return is 0 or: +//! +//! AM_HAL_RTC_INT_ALM +// +//***************************************************************************** +uint32_t +am_hal_rtc_int_enable_get(void) +{ + // + // Read the RTC interrupt enable register, and return its contents. + // + return RTC->INTEN; +} + +//***************************************************************************** +// +//! @brief Disable selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Disables the RTC interrupts. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupts. + // + RTC->INTEN &= ~ui32Interrupt; + +} + +//***************************************************************************** +// +//! @brief Sets the selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Sets the RTC interrupts causing them to immediately trigger. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + RTC->INTSET = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clear selected RTC interrupts. +//! +//! @param ui32Interrupt - desired interrupts +//! +//! Clears the RTC interrupts. +//! +//! ui32Interrupt should be the following: +//! +//! AM_HAL_RTC_INT_ALM +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_int_clear(uint32_t ui32Interrupt) +{ + // + // Clear the interrupts. + // + RTC->INTCLR = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Returns the RTC interrupt status. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! Returns the RTC interrupt status. +//! +//! @return Bitwise representation of the current interrupt status. +//! +//! The return value will be 0 or the following: +//! +//! AM_HAL_RTC_INT_ALM +// +//***************************************************************************** +uint32_t +am_hal_rtc_int_status_get(bool bEnabledOnly) +{ + // + // Get the interrupt status. + // + if ( bEnabledOnly ) + { + uint32_t u32RetVal; + u32RetVal = RTC->INTSTAT; + u32RetVal &= RTC->INTEN; + return u32RetVal & (AM_HAL_RTC_INT_ALM); + } + else + { + return RTC->INTSTAT & (AM_HAL_RTC_INT_ALM); + } +} + +//***************************************************************************** +// +//! @brief Set the Real Time Clock counter registers. +//! +//! @param *pTime - A pointer to the time structure. +//! +//! Sets the RTC counter registers to the supplied values. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_time_set(am_hal_rtc_time_t *pTime) +{ + // + // Enable writing to the counters. + // + RTC->RTCCTL_b.WRTC = RTC_RTCCTL_WRTC_EN; + + // + // Write the RTCLOW register. + // + RTC->CTRLOW = + _VAL2FLD(RTC_CTRLOW_CTRHR, dec_to_bcd(pTime->ui32Hour)) | + _VAL2FLD(RTC_CTRLOW_CTRMIN, dec_to_bcd(pTime->ui32Minute)) | + _VAL2FLD(RTC_CTRLOW_CTRSEC, dec_to_bcd(pTime->ui32Second)) | + _VAL2FLD(RTC_CTRLOW_CTR100, dec_to_bcd(pTime->ui32Hundredths)); + + // + // Write the RTCUP register. + // + RTC->CTRUP = + _VAL2FLD(RTC_CTRUP_CEB, (pTime->ui32CenturyEnable)) | + _VAL2FLD(RTC_CTRUP_CB, (pTime->ui32Century)) | + _VAL2FLD(RTC_CTRUP_CTRWKDY, (pTime->ui32Weekday)) | + _VAL2FLD(RTC_CTRUP_CTRYR, dec_to_bcd((pTime->ui32Year))) | + _VAL2FLD(RTC_CTRUP_CTRMO, dec_to_bcd((pTime->ui32Month))) | + _VAL2FLD(RTC_CTRUP_CTRDATE, dec_to_bcd((pTime->ui32DayOfMonth))); + + // + // Disable writing to the counters. + // + RTC->RTCCTL_b.WRTC = RTC_RTCCTL_WRTC_DIS; +} + +//***************************************************************************** +// +//! @brief Get the Real Time Clock current time. +//! +//! @param *pTime - A pointer to the time structure to store the current time. +//! +//! Gets the RTC's current time +//! +//! @return 0 for success and 1 for error. +// +//***************************************************************************** +uint32_t +am_hal_rtc_time_get(am_hal_rtc_time_t *pTime) +{ + uint32_t ui32RTCLow, ui32RTCUp, ui32Value; + + // + // Read the upper and lower RTC registers. + // + ui32RTCLow = RTC->CTRLOW; + ui32RTCUp = RTC->CTRUP; + + // + // Break out the lower word. + // + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTRHR_Msk) >> RTC_CTRLOW_CTRHR_Pos); + pTime->ui32Hour = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTRMIN_Msk) >> RTC_CTRLOW_CTRMIN_Pos); + pTime->ui32Minute = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTRSEC_Msk) >> RTC_CTRLOW_CTRSEC_Pos); + pTime->ui32Second = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCLow & RTC_CTRLOW_CTR100_Msk) >> RTC_CTRLOW_CTR100_Pos); + pTime->ui32Hundredths = bcd_to_dec(ui32Value); + + // + // Break out the upper word. + // + pTime->ui32ReadError = + ((ui32RTCUp & RTC_CTRUP_CTERR_Msk) >> RTC_CTRUP_CTERR_Pos); + + pTime->ui32CenturyEnable = + ((ui32RTCUp & RTC_CTRUP_CEB_Msk) >> RTC_CTRUP_CEB_Pos); + + pTime->ui32Century = + ((ui32RTCUp & RTC_CTRUP_CB_Msk) >> RTC_CTRUP_CB_Pos); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRWKDY_Msk) >> RTC_CTRUP_CTRWKDY_Pos); + pTime->ui32Weekday = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRYR_Msk) >> RTC_CTRUP_CTRYR_Pos); + pTime->ui32Year = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRMO_Msk) >> RTC_CTRUP_CTRMO_Pos); + pTime->ui32Month = bcd_to_dec(ui32Value); + + ui32Value = + ((ui32RTCUp & RTC_CTRUP_CTRDATE_Msk) >> RTC_CTRUP_CTRDATE_Pos); + + pTime->ui32DayOfMonth = bcd_to_dec(ui32Value); + + // + // Was there a read error? + // + if (pTime->ui32ReadError) + { + return 1; + } + else + { + return 0; + } +} + +//***************************************************************************** +// +//! @brief Sets the alarm repeat interval. +//! +//! @param ui32RepeatInterval the desired repeat interval. +//! +//! Sets the alarm repeat interval. +//! +//! Valid values for ui32RepeatInterval: +//! +//! AM_HAL_RTC_ALM_RPT_DIS +//! AM_HAL_RTC_ALM_RPT_YR +//! AM_HAL_RTC_ALM_RPT_MTH +//! AM_HAL_RTC_ALM_RPT_WK +//! AM_HAL_RTC_ALM_RPT_DAY +//! AM_HAL_RTC_ALM_RPT_HR +//! AM_HAL_RTC_ALM_RPT_MIN +//! AM_HAL_RTC_ALM_RPT_SEC +//! AM_HAL_RTC_ALM_RPT_10TH +//! AM_HAL_RTC_ALM_RPT_100TH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval) +{ + uint32_t ui32RptInt, ui32Alm100, ui32Value; + + switch(ui32RepeatInterval) + { + // + // If repeat every 10th set RPT and ALM100 field accordinly + // + case AM_HAL_RTC_ALM_RPT_10TH: + ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC; + ui32Alm100 = AM_HAL_RTC_ALM100_10TH; + break; + // + // If repeat every 100th set RPT and ALM100 field accordinly + // + case AM_HAL_RTC_ALM_RPT_100TH: + ui32RptInt = AM_HAL_RTC_ALM_RPT_SEC; + ui32Alm100 = AM_HAL_RTC_ALM100_100TH; + break; + // + // Otherwise set RPT as value passed. ALM100 values need to be 0xnn + // in this setting where n = 0-9. + // + default: + // + // Get the current value of the ALM100 field. + // + ui32Value = RTC->ALMLOW_b.ALM100; + + // + // If ALM100 was previous EVERY_10TH or EVERY_100TH reset to zero + // otherwise keep previous setting. + // + ui32Alm100 = ui32Value >= 0xF0 ? 0 : ui32Value; + + // + // Set RPT value to value passed. + // + ui32RptInt = ui32RepeatInterval; + break; + } + + + // + // Write the interval to the register. + // + RTC->RTCCTL_b.RPT = ui32RptInt; + + // + // Write the Alarm 100 bits in the ALM100 register. + // + RTC->ALMLOW_b.ALM100 = ui32Alm100; +} + +//***************************************************************************** +// +//! @brief Sets the RTC's Alarm. +//! +//! @param *pTime - A pointer to the time structure. +//! @param ui32RepeatInterval - the desired alarm repeat interval. +//! +//! Set the Real Time Clock Alarm Parameters. +//! +//! Valid values for ui32RepeatInterval: +//! +//! AM_HAL_RTC_ALM_RPT_DIS +//! AM_HAL_RTC_ALM_RPT_YR +//! AM_HAL_RTC_ALM_RPT_MTH +//! AM_HAL_RTC_ALM_RPT_WK +//! AM_HAL_RTC_ALM_RPT_DAY +//! AM_HAL_RTC_ALM_RPT_HR +//! AM_HAL_RTC_ALM_RPT_MIN +//! AM_HAL_RTC_ALM_RPT_SEC +//! AM_HAL_RTC_ALM_RPT_10TH +//! AM_HAL_RTC_ALM_RPT_EVERY_100TH +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime, uint32_t ui32RepeatInterval) +{ + uint8_t ui8Value = 0; + + // + // Write the interval to the register. + // + RTC->RTCCTL |= _VAL2FLD(RTC_RTCCTL_RPT, (ui32RepeatInterval > 0x7 ? 0x7 : ui32RepeatInterval)); + + // + // Check if the interval is 10th or every 100th and track it in ui8Value. + // + if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_10TH) + { + ui8Value = 0xF0; + } + else if (ui32RepeatInterval == AM_HAL_RTC_ALM_RPT_100TH) + { + ui8Value = 0xFF; + } + + // + // Write the ALMUP register. + // + RTC->ALMUP = + _VAL2FLD(RTC_ALMUP_ALMWKDY, (pTime->ui32Weekday)) | + _VAL2FLD(RTC_ALMUP_ALMMO, dec_to_bcd((pTime->ui32Month))) | + _VAL2FLD(RTC_ALMUP_ALMDATE, dec_to_bcd((pTime->ui32DayOfMonth))); + + // + // Write the ALMLOW register. + // + RTC->ALMLOW = + _VAL2FLD(RTC_ALMLOW_ALMHR, dec_to_bcd(pTime->ui32Hour)) | + _VAL2FLD(RTC_ALMLOW_ALMMIN, dec_to_bcd(pTime->ui32Minute)) | + _VAL2FLD(RTC_ALMLOW_ALMSEC, dec_to_bcd(pTime->ui32Second)) | + _VAL2FLD(RTC_ALMLOW_ALM100, dec_to_bcd(pTime->ui32Hundredths) | ui8Value); +} + +//***************************************************************************** +// +//! @brief Get the Real Time Clock Alarm Parameters +//! +//! @param *pTime - A pointer to the time structure to store the current alarm. +//! +//! Gets the RTC's Alarm time +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime) +{ + uint32_t ui32ALMLow, ui32ALMUp, ui32Value; + + // + // Read the upper and lower RTC registers. + // + ui32ALMLow = RTC->ALMLOW; + ui32ALMUp = RTC->ALMUP; + + // + // Break out the lower word. + // + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALMHR_Msk) >> RTC_ALMLOW_ALMHR_Pos); + pTime->ui32Hour = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALMMIN_Msk) >> RTC_ALMLOW_ALMMIN_Pos); + pTime->ui32Minute = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALMSEC_Msk) >> RTC_ALMLOW_ALMSEC_Pos); + pTime->ui32Second = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMLow & RTC_ALMLOW_ALM100_Msk) >> RTC_ALMLOW_ALM100_Pos); + pTime->ui32Hundredths = bcd_to_dec(ui32Value); + + // + // Break out the upper word. + // + pTime->ui32ReadError = 0; + pTime->ui32CenturyEnable = 0; + pTime->ui32Century = 0; + + ui32Value = ((ui32ALMUp & RTC_ALMUP_ALMWKDY_Msk) >> RTC_ALMUP_ALMWKDY_Pos); + pTime->ui32Weekday = bcd_to_dec(ui32Value); + + pTime->ui32Year = 0; + + ui32Value = ((ui32ALMUp & RTC_ALMUP_ALMMO_Msk) >> RTC_ALMUP_ALMMO_Pos); + pTime->ui32Month = bcd_to_dec(ui32Value); + + ui32Value = ((ui32ALMUp & RTC_ALMUP_ALMDATE_Msk) >> RTC_ALMUP_ALMDATE_Pos); + pTime->ui32DayOfMonth = bcd_to_dec(ui32Value); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.h new file mode 100644 index 0000000000..3458112494 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_rtc.h @@ -0,0 +1,185 @@ +//***************************************************************************** +// +// am_hal_rtc.h +//! @file +//! +//! @brief Functions for interfacing and accessing the Real-Time Clock (RTC). +//! +//! @addtogroup rtc3 Real-Time Clock (RTC) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_RTC_H +#define AM_HAL_RTC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @name OSC Start and Stop +//! @brief OSC Start and Stop defines. +//! +//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x(). +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_OSC_XT 0x0 +//! @} + +//***************************************************************************** +// +//! @name RTC Interrupts +//! @brief Macro definitions for RTC interrupt status bits. +//! +//! These macros correspond to the bits in the RTC interrupt status register. +//! They may be used with any of the \e am_hal_rtc_int_x() functions. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_INT_ALM RTC_INTEN_ALM_Msk +//! @} + +//***************************************************************************** +// +//! @name RTC Alarm Repeat Interval. +//! @brief Macro definitions for the RTC alarm repeat interval. +//! +//! These macros correspond to the RPT bits in the RTCCTL register. +//! They may be used with the \e am_hal_rtc_alarm_interval_set() function. +//! +//! Note: AM_HAL_RTC_ALM_RPT_10TH and AM_HAL_RTC_ALM_RPT_100TH do not +//! correspond to the RPT bits but are used in conjunction with setting the +//! ALM100 bits in the ALMLOW register. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_ALM_RPT_DIS 0x0 +#define AM_HAL_RTC_ALM_RPT_YR 0x1 +#define AM_HAL_RTC_ALM_RPT_MTH 0x2 +#define AM_HAL_RTC_ALM_RPT_WK 0x3 +#define AM_HAL_RTC_ALM_RPT_DAY 0x4 +#define AM_HAL_RTC_ALM_RPT_HR 0x5 +#define AM_HAL_RTC_ALM_RPT_MIN 0x6 +#define AM_HAL_RTC_ALM_RPT_SEC 0x7 +#define AM_HAL_RTC_ALM_RPT_10TH 0x8 +#define AM_HAL_RTC_ALM_RPT_100TH 0x9 +//! @} + +//***************************************************************************** +// +//! @name RTC Alarm 100 Interval. +//! @brief Macro definitions for the RTC alarm ms intervals. +//! +//! These macros are used inside the #am_hal_rtc_alarm_interval_set function +//! when 10ms and 100ms repeated alarm intervals are desired. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_RTC_ALM100_DEFAULT 0x00 +#define AM_HAL_RTC_ALM100_10TH 0xF0 +#define AM_HAL_RTC_ALM100_100TH 0xFF +//! @} + +//***************************************************************************** +// +//! @brief The basic time structure used by the HAL for RTC interaction. +//! +//! All values are positive whole numbers. The HAL routines convert back and +//! forth to BCD. +// +//***************************************************************************** +typedef struct am_hal_rtc_time_struct +{ + uint32_t ui32ReadError; + uint32_t ui32CenturyEnable; + uint32_t ui32Weekday; + uint32_t ui32Century; + uint32_t ui32Year; + uint32_t ui32Month; + uint32_t ui32DayOfMonth; + uint32_t ui32Hour; + uint32_t ui32Minute; + uint32_t ui32Second; + uint32_t ui32Hundredths; +}am_hal_rtc_time_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_rtc_osc_select(uint32_t ui32OSC); +extern void am_hal_rtc_osc_enable(void); +extern void am_hal_rtc_osc_disable(void); +extern void am_hal_rtc_time_12hour(bool b12Hour); +extern void am_hal_rtc_time_set(am_hal_rtc_time_t *pTime); +extern uint32_t am_hal_rtc_time_get(am_hal_rtc_time_t *pTime); +extern void am_hal_rtc_alarm_interval_set(uint32_t ui32RepeatInterval); +extern void am_hal_rtc_alarm_set(am_hal_rtc_time_t *pTime, + uint32_t ui32RepeatInterval); +extern void am_hal_rtc_alarm_get(am_hal_rtc_time_t *pTime); +extern void am_hal_rtc_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_rtc_int_enable_get(void); +extern void am_hal_rtc_int_disable(uint32_t ui32Interrupt); +extern void am_hal_rtc_int_clear(uint32_t ui32Interrupt); +extern void am_hal_rtc_int_set(uint32_t ui32Interrupt); +extern uint32_t am_hal_rtc_int_status_get(bool bEnabledOnly); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_RTC_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.c new file mode 100644 index 0000000000..5f1e9e30e5 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.c @@ -0,0 +1,1575 @@ +//***************************************************************************** +// +// am_hal_scard.c +//! @file +//! +//! @brief Functions for interfacing with the SCARD. +//! +//! @addtogroup scard3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// SCARD magic number for handle verification. +// +//***************************************************************************** +#define AM_HAL_MAGIC_SCARD 0xEA9E06 + +#define AM_HAL_SCARD_CHK_HANDLE(h) \ + ((h) && \ + ((am_hal_handle_prefix_t *)(h))->s.bInit && \ + (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_SCARD)) + +//***************************************************************************** +// +// Convenience macro for passing errors. +// +//***************************************************************************** +#define RETURN_ON_ERROR(x) \ + if ((x) != AM_HAL_STATUS_SUCCESS) \ + { \ + return (x); \ + }; + +//***************************************************************************** +// +// Baudrate to byte-time in microseconds with a little extra margin. +// +//***************************************************************************** +#define ONE_BIT_US(baudrate) (AM_HAL_SCARD_CLK_FREQ/(baudrate)) +#define ONE_BIT_DELAY(handle) \ + am_hal_flash_delay(FLASH_CYCLES_US(ONE_BIT_US((handle)->ui32BaudRate))) + +#define SCARD_MAX_SYNC_TIME_MS 10 + +#define delay_ms(ms) am_hal_flash_delay(FLASH_CYCLES_US(1000 * (ms))) +#define delay_us(us) am_hal_flash_delay(FLASH_CYCLES_US(us)) + +#define SCARD_WHILE_TIMEOUT_MS(expr, timeout, error) \ +{ \ + uint32_t ui32Timeout = 0; \ + while ( expr ) \ + { \ + if ( ui32Timeout == (timeout * 1000) ) \ + { \ + return error; \ + } \ + \ + delay_us(1); \ + ui32Timeout++; \ + } \ +} + +#define SCARD_SYNC_OPER(module, operation) do{\ + SCARDn(module)->SR1_b.SYNCEND = 1;\ + operation;\ + SCARD_WHILE_TIMEOUT_MS(!SCARDn(module)->SR1_b.SYNCEND, SCARD_MAX_SYNC_TIME_MS, AM_HAL_SCARD_STATUS_BUS_ERROR) ;\ + } while ( 0 ) + +//***************************************************************************** +// +// Transmission parameters F and D look-up tables +// Per the ETU 7816-3 protocol ETU is computed from 2 parameters, FI and DI. +// ETU: Elementary Time Unit +// FI: Clock rate conversion factor +// DI: Bit rate adjustment factor +// +//***************************************************************************** +static uint16_t g_F_Integer[16][2] = +{ + // FI { F, f(max)} + /*0000*/{ 372, 4}, + /*0001*/{ 372, 5}, + /*0010*/{ 558, 6}, + /*0011*/{ 744, 8}, + /*0100*/{1116, 12}, + /*0101*/{1488, 16}, + /*0110*/{1860, 20}, + /*0111*/{ 0, 0}, + /*1000*/{ 0, 0}, + /*1001*/{ 512, 5}, + /*1010*/{ 768, 7}, //7.5 + /*1011*/{1024, 10}, + /*1100*/{1536, 15}, + /*1101*/{2048, 20}, + /*1110*/{ 0, 0}, + /*1111*/{ 0, 0} +}; +static uint8_t g_D_Integer[16] = +{ + //DI 0000 0001 0010 0011 0100 0101 0110 0111 + /*D*/ 0, 1, 2, 4, 8, 16, 32, 64, + //DI 1000 1001 1010 1011 1100 1101 1110 1111 + /*D*/ 12, 20, 0, 0, 0, 0, 0, 0 +}; + +static uint16_t g_WaitTime = AM_HAL_SCARD_WAIT_MAX_TIME; //Set to max + +//***************************************************************************** +// +// Structure for handling SCARD register state information for power up/down +// +//***************************************************************************** +typedef struct +{ + bool bValid; + uint32_t regIER; + uint32_t regTCR; + uint32_t regUCR; + uint32_t regBPRL; + uint32_t regBPRH; + uint32_t regUCR1; + uint32_t regIER1; + uint32_t regGTR; + uint32_t regRETXCNT; + uint32_t regCLKCTRL; +} +am_hal_scard_register_state_t; + +//***************************************************************************** +// +// Structure for handling SCARD instance state information. +// +//***************************************************************************** +typedef struct +{ + am_hal_handle_prefix_t prefix; + am_hal_scard_register_state_t sRegState; + + uint32_t ui32Module; + + bool bEnableTxQueue; + am_hal_queue_t sTxQueue; + + bool bEnableRxQueue; + am_hal_queue_t sRxQueue; + + uint32_t ui32BaudRate; +} +am_hal_scard_state_t; + +//***************************************************************************** +// +// State structure for each module. +// +//***************************************************************************** +am_hal_scard_state_t g_am_hal_scard_states[AM_REG_SCARD_NUM_MODULES]; + +//***************************************************************************** +// +// Allows the SCARD HAL to use extra space to store TX and RX data. +// +//***************************************************************************** +static uint32_t +buffer_configure(void *pHandle, uint8_t *pui8TxBuffer, uint32_t ui32TxBufferSize, + uint8_t *pui8RxBuffer, uint32_t ui32RxBufferSize) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if we have a TX buffer. + // + if ( pui8TxBuffer && ui32TxBufferSize ) + { + // + // If so, initialzie the transmit queue, and enable the TX FIFO + // interrupt. + // + pState->bEnableTxQueue = true; + am_hal_queue_init(&pState->sTxQueue, pui8TxBuffer, 1, ui32TxBufferSize); + ui32ErrorStatus = am_hal_scard_interrupt_enable(pHandle, 0, AM_HAL_SCARD_INT_TBERBFEN); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If not, make sure the TX FIFO interrupt is disabled. + // + pState->bEnableTxQueue = false; + ui32ErrorStatus = am_hal_scard_interrupt_disable(pHandle, 0, AM_HAL_SCARD_INT_TBERBFEN); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if we have an RX buffer. + // + if ( pui8RxBuffer && ui32RxBufferSize ) + { + // + // If so, initialize the receive queue and the associated interupts. + // + pState->bEnableRxQueue = true; + am_hal_queue_init(&pState->sRxQueue, pui8RxBuffer, 1, ui32RxBufferSize); + ui32ErrorStatus = am_hal_scard_interrupt_enable(pHandle, 0, (AM_HAL_SCARD_INT_FHFEN | + AM_HAL_SCARD_INT_FNEEN)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + pState->bEnableRxQueue = false; + ui32ErrorStatus = am_hal_scard_interrupt_disable(pHandle, 0, (AM_HAL_SCARD_INT_FHFEN | + AM_HAL_SCARD_INT_FNEEN)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + return AM_HAL_STATUS_SUCCESS; +} // buffer_configure() + +//***************************************************************************** +// +// Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_scard_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check that the request module is in range. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Module >= AM_REG_SCARD_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Check for valid arguements. + // + if ( !ppHandle ) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if ( g_am_hal_scard_states[ui32Module].prefix.s.bInit ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + g_am_hal_scard_states[ui32Module].prefix.s.bInit = true; + g_am_hal_scard_states[ui32Module].prefix.s.magic = AM_HAL_MAGIC_SCARD; + g_am_hal_scard_states[ui32Module].ui32Module = ui32Module; + g_am_hal_scard_states[ui32Module].sRegState.bValid = false; + g_am_hal_scard_states[ui32Module].ui32BaudRate = 0; + + // + // Return the handle. + // + *ppHandle = (void *)&g_am_hal_scard_states[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_initialize() + +//***************************************************************************** +// +// De-Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_scard_deinitialize(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *)pHandle; + + // + // Check the handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Reset the handle. + // + pState->prefix.s.bInit = false; + pState->ui32Module = 0; + pState->sRegState.bValid = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_deinitialize() + +//***************************************************************************** +// +// Power control functions. +// +//***************************************************************************** +uint32_t +am_hal_scard_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( ui32Module >= AM_REG_SCARD_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + am_hal_pwrctrl_periph_e eSCCPowerModule = ((am_hal_pwrctrl_periph_e) + (AM_HAL_PWRCTRL_PERIPH_SCARD + + ui32Module)); + + // + // Check to make sure this is a valid handle. + // + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Decode the requested power state and update SCARD operation accordingly. + // + switch (ePowerState) + { + // + // Turn on the SCC. + // + case AM_HAL_SYSCTRL_WAKE: + // + // Make sure we don't try to restore an invalid state. + // + if ( bRetainState && !pState->sRegState.bValid ) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable(eSCCPowerModule); + + if ( bRetainState ) + { + // + // Restore SCC registers + // + AM_CRITICAL_BEGIN + + SCARDn(ui32Module)->IER = pState->sRegState.regIER; + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR = pState->sRegState.regTCR); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR = pState->sRegState.regUCR); + SCARDn(ui32Module)->BPRL = pState->sRegState.regBPRL; + SCARDn(ui32Module)->BPRH = pState->sRegState.regBPRH; + SCARDn(ui32Module)->UCR1 = pState->sRegState.regUCR1; + SCARDn(ui32Module)->IER1 = pState->sRegState.regIER1; + SCARDn(ui32Module)->GTR = pState->sRegState.regGTR; + SCARDn(ui32Module)->RETXCNT = pState->sRegState.regRETXCNT; + SCARDn(ui32Module)->CLKCTRL = pState->sRegState.regCLKCTRL; + pState->sRegState.bValid = false; + + AM_CRITICAL_END + } + break; + + // + // Turn off the SCARD. + // + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if ( bRetainState ) + { + AM_CRITICAL_BEGIN + + pState->sRegState.regIER = SCARDn(ui32Module)->IER; + pState->sRegState.regTCR = SCARDn(ui32Module)->TCR; + pState->sRegState.regUCR = SCARDn(ui32Module)->UCR; + pState->sRegState.regBPRL = SCARDn(ui32Module)->BPRL; + pState->sRegState.regBPRH = SCARDn(ui32Module)->BPRH; + pState->sRegState.regUCR1 = SCARDn(ui32Module)->UCR1; + pState->sRegState.regIER1 = SCARDn(ui32Module)->IER1; + pState->sRegState.regGTR = SCARDn(ui32Module)->GTR; + pState->sRegState.regRETXCNT = SCARDn(ui32Module)->RETXCNT; + pState->sRegState.regCLKCTRL = SCARDn(ui32Module)->CLKCTRL; + pState->sRegState.bValid = true; + + AM_CRITICAL_END + } + + // + // Clear all interrupts before sleeping as having a pending SCARD + // interrupt burns power. + // + am_hal_scard_interrupt_clear(pState, 0, AM_HAL_SCARD_INT_ALL); + am_hal_scard_interrupt_clear(pState, 1, AM_HAL_SCARD_INT_ALL); + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable(eSCCPowerModule); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_power_control() + +//***************************************************************************** +// +// SCARD configuration. +// +//***************************************************************************** +uint32_t +am_hal_scard_configure(void *pHandle, am_hal_scard_config_t *psConfig) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check to make sure this is a valid handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + // + // Start by enabling the clocks, which needs to happen in a critical + // section. + // + AM_CRITICAL_BEGIN + + SCARDn(ui32Module)->CLKCTRL_b.APBCLKEN = 1; + SCARDn(ui32Module)->CLKCTRL_b.CLKEN = 1; + + AM_CRITICAL_END + // + // Set the baud rate. + // + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_BAUDRATE, &psConfig->ui32Fidi); + + //RETURN_ON_ERROR(ui32ErrorStatus); + // + // Copy the configuration options into the appropriate registers. + // + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PROTOCOL, &psConfig->ui32Protocol); + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_CARD_FORMAT, &psConfig->ui32Direction); + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PARITY, &psConfig->ui32Parity); + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_GUARDTIME, &psConfig->ui32GuardTime); + SCARDn(ui32Module)->UCR1_b.CLKIOV = psConfig->ui32ClkLevel; + status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_CLK_STOP, NULL); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.RIU = 1); + if ( AM_HAL_STATUS_SUCCESS != status ) + { + return AM_HAL_STATUS_FAIL; + } + // + // Set up any buffers that might exist. + // + buffer_configure(pHandle, + psConfig->pui8TxBuffer, + psConfig->ui32TxBufferSize, + psConfig->pui8RxBuffer, + psConfig->ui32RxBufferSize); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_configure() + +//***************************************************************************** +// +// Set Baud Rate Register based on the parameters F and D. +// +//***************************************************************************** +static void +config_baudrate(void *pHandle, uint32_t ui32Fidi) +{ + uint16_t bpr; + uint32_t ui32ActualBaud; + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // F is the clock rate conversion integer + // D is the baud rate adjustment integer + // 1 ETU = (F/D)*(1/f) s + // The default values of these parameters are: + // F = 372 ; D = 1; f (max.) = 5 MHz + + // + // BPRL and BPRH are used for counting ETU + // + bpr = ((g_F_Integer[AM_HAL_SCARD_FI(ui32Fidi)][0] != 0) && (g_D_Integer[AM_HAL_SCARD_DI(ui32Fidi)] != 0)) ? \ + g_F_Integer[AM_HAL_SCARD_FI(ui32Fidi)][0] / g_D_Integer[AM_HAL_SCARD_DI(ui32Fidi)] : \ + g_F_Integer[AM_HAL_SCARD_FI(AM_HAL_SCARD_FI_DI_DEFAULT)][0] / g_D_Integer[AM_HAL_SCARD_DI(AM_HAL_SCARD_FI_DI_DEFAULT)]; + + SCARDn(ui32Module)->BPRL = bpr & 0xFF; + SCARDn(ui32Module)->BPRH = (SCARDn(ui32Module)->BPRH & (~SCARD_BPRH_BPRH_Msk)) | ((bpr >> 8) & SCARD_BPRH_BPRH_Msk) ; + ui32ActualBaud = (uint32_t)(AM_HAL_SCARD_CLK_FREQ / bpr); + pState->ui32BaudRate = ui32ActualBaud; +} // config_baudrate() + +//***************************************************************************** +// +// Set card format, direct convention or inverse convention +// +//***************************************************************************** +static uint32_t +config_cardformat(uint32_t ui32Module, uint32_t ui32Format) +{ + switch(ui32Format) + { + // + // Inverse convention + // + case AM_HAL_SCARD_CONV_MSB_0X3F: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.AUTOCONV = 1); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.CONV = 1); + break; + // + // Direct convention + // + case AM_HAL_SCARD_CONV_LSB_0X3B: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.AUTOCONV = 1); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.CONV = 0); + break; + // + // Not set by software, configured by the first received byte + // + case AM_HAL_SCARD_CONV_AUTO: + default: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.AUTOCONV = 0); + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.SS = 1); + break; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Enable/disbale parity and set it to odd/even +// +//***************************************************************************** +static uint32_t +config_parity(uint32_t ui32Module, uint32_t ui32Parity) +{ + // + // T1 protocol + // + if ( SCARDn(ui32Module)->TCR_b.PROT ) + { + // + // Enable parity + // + if ( ui32Parity & 0xF0 ) + { + SCARDn(ui32Module)->UCR1_b.T1PAREN = 1; + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.FIP = ui32Parity & 0xF); + } + // + // Disbale parity + // + else + { + SCARDn(ui32Module)->UCR1_b.T1PAREN = 0; + } + } + // + // T0 protocol, always enable parity + // + else + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.FIP = ui32Parity & 0xF); + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Set protocol, T0 or T1 +// +//***************************************************************************** +static uint32_t +config_protocol(uint32_t ui32Module, uint32_t ui32Protocol) +{ + if ( 1 == ui32Protocol ) + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.PROT = AM_HAL_SCARD_PROTOCOL_T1); + } + else if ( 0 == ui32Protocol ) + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.PROT = AM_HAL_SCARD_PROTOCOL_T0); + } + else + { + return AM_HAL_SCARD_STATUS_PROTOCAL_NOT_SUPPORT; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Set and start ETU counter +// +//***************************************************************************** +static uint32_t +config_etucounter(uint32_t ui32Module, uint16_t ui16Etu) +{ + // + // Set low-8bit first, then set high-8bit, after software writes ECNTH, ETU counter starts counting + // + SCARD_WHILE_TIMEOUT_MS(!SCARDn(ui32Module)->SR1_b.IDLE, 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + SCARDn(ui32Module)->SR1_b.SYNCEND = 1; + SCARDn(ui32Module)->ECNTL = (ui16Etu) & 0xFF; + SCARD_WHILE_TIMEOUT_MS(!SCARDn(ui32Module)->SR1_b.SYNCEND, 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + SCARDn(ui32Module)->ECNTH = ((ui16Etu) >> 8); + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Read as much data from the SCARD FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +uint32_t scard_fifo_read(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32NumBytesRead) +{ + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + uint32_t i = 0; + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint8_t ui8Index = 0; + + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.TR = 0); + + while ( ui32NumBytes ) + { + config_etucounter(ui32Module, g_WaitTime); + while ( (!SCARDn(ui32Module)->SR_b.FNE) && (!SCARDn(ui32Module)->SR1_b.ECNTOVER) && (!SCARDn(ui32Module)->SR_b.PE) && (!SCARDn(ui32Module)->SR_b.FER) ); + // + // Read times out + // + if ( SCARDn(ui32Module)->SR1_b.ECNTOVER ) + { + break; + } + // + // Parity error or Frame error + // + else if ( (SCARDn(ui32Module)->SR_b.PE) || (SCARDn(ui32Module)->SR_b.FER) ) + { + SCARDn(ui32Module)->SR_b.PE = 0; + SCARDn(ui32Module)->SR_b.FER = 0; + ui32ErrorStatus = AM_HAL_STATUS_FAIL; + break; + } + // + // RX FIFO is full, read 8 bytes out + // + else if ( SCARDn(ui32Module)->SR_b.TBERBF ) + { + for ( ui8Index = 0; ui8Index < AM_HAL_SCARD_FIFO_MAX; ui8Index++ ) + { + pui8Data[i++] = SCARDn(ui32Module)->DR_b.DR; + } + ui32NumBytes -= AM_HAL_SCARD_FIFO_MAX; + } + // + // RX FIFO is half full, read 4 bytes out + // + else if ( SCARDn(ui32Module)->SR_b.FHF ) + { + for ( ui8Index = 0; ui8Index < AM_HAL_SCARD_FIFO_MAX / 2; ui8Index++ ) + { + pui8Data[i++] = SCARDn(ui32Module)->DR_b.DR; + } + ui32NumBytes -= AM_HAL_SCARD_FIFO_MAX / 2; + } + // + // RX FIFO is not empty, read as much as we can + // + else if ( SCARDn(ui32Module)->SR_b.FNE ) + { + pui8Data[i++] = SCARDn(ui32Module)->DR_b.DR; + ui32NumBytes--; + } + } + if ( pui32NumBytesRead ) + { + *pui32NumBytesRead = i; + } + return ui32ErrorStatus; +} + +//***************************************************************************** +// +// Read as much data from the SCARD FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +uint32_t scard_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, uint32_t *pui32NumBytesWritten) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint32_t i = 0; + + if ( ui32NumBytes ) + { + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.TR = 1); + + while ( 1 != ui32NumBytes-- ) + { + // + // Write 1 byte into DR + // + SCARDn(ui32Module)->DR_b.DR = pui8Data[i++]; + SCARD_WHILE_TIMEOUT_MS((!SCARDn(ui32Module)->SR_b.TBERBF) && (!SCARDn(ui32Module)->SR_b.PE) && (!SCARDn(ui32Module)->SR_b.FER), 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + // + // Parity error or Frame error + // + if ( (SCARDn(ui32Module)->SR_b.PE) || (SCARDn(ui32Module)->SR_b.FER) ) + { + SCARDn(ui32Module)->SR_b.PE = 0; + SCARDn(ui32Module)->SR_b.FER = 0; + return AM_HAL_STATUS_FAIL; + } + } + + // + // Enable fast TX to RX function before the last byte + // + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.LCT = 1); + SCARDn(ui32Module)->DR_b.DR = pui8Data[i++]; + // + // SCC should switch back to RX after all data sent out + // + SCARD_WHILE_TIMEOUT_MS((!SCARDn(ui32Module)->SR_b.FT2REND) && (!SCARDn(ui32Module)->SR_b.PE) && (!SCARDn(ui32Module)->SR_b.FER), 100, AM_HAL_SCARD_STATUS_BUS_ERROR); + // + // Parity error or Frame error + // + if ( (SCARDn(ui32Module)->SR_b.PE) || (SCARDn(ui32Module)->SR_b.FER) ) + { + SCARDn(ui32Module)->SR_b.PE = 0; + SCARDn(ui32Module)->SR_b.FER = 0; + return AM_HAL_STATUS_FAIL; + } + + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->TCR_b.TR = 0); + } + if ( pui32NumBytesWritten ) + { + *pui32NumBytesWritten = i; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Empty the SCARD RX FIFO, and place the data into the RX queue. +// +//***************************************************************************** +static uint32_t +rx_queue_update(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + uint8_t pui8Data[AM_HAL_SCARD_FIFO_MAX]; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus; + + AM_CRITICAL_BEGIN + + // + // Read as much of the FIFO as we can. + // + ui32ErrorStatus = scard_fifo_read(pHandle, pui8Data, AM_HAL_SCARD_FIFO_MAX, + &ui32BytesTransferred); + // + // If we were successful, go ahead and transfer the data along to the + // buffer. + // + if ( ui32ErrorStatus == AM_HAL_STATUS_SUCCESS ) + { + if ( !am_hal_queue_item_add(&pState->sRxQueue, pui8Data, + ui32BytesTransferred) ) + { + ui32ErrorStatus = AM_HAL_SCARD_STATUS_RX_QUEUE_FULL; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // rx_queue_update() + +//***************************************************************************** +// +// Transfer as much data as possible from the TX queue to the TX FIFO. +// +//***************************************************************************** +static uint32_t +tx_queue_update(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + uint8_t pui8Data; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + AM_CRITICAL_BEGIN + + // + // Attempt to grab an item from the queue, and add it to the fifo. + // + while ( 1 ) + { + if ( am_hal_queue_item_get(&pState->sTxQueue, &pui8Data, 1) ) + { + ui32ErrorStatus = scard_fifo_write(pHandle, &pui8Data, 1, &ui32BytesTransferred); + } + else + { + // + // If we didn't get anything from the queue, we can just return. + // + break; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // tx_queue_update() + +//***************************************************************************** +// +// Attempt to read N bytes from the FIFO, but give up if they aren't there. +// +//***************************************************************************** +static uint32_t +read_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + uint32_t ui32BufferData; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (NULL == pui8Data) || (NULL == pui32NumBytesRead) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Start by setting the number of bytes read to 0. + // + *pui32NumBytesRead = 0; + + if ( ui32NumBytes == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular receive buffer has been enabled. + // + if ( pState->bEnableRxQueue ) + { + // + // If it is, update it, and then try to read the requested number of + // bytes, giving up if fewer were actually found. + // + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + + ui32BufferData = am_hal_queue_data_left(&pState->sRxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferData ? + ui32NumBytes : ui32BufferData); + + am_hal_queue_item_get(&pState->sRxQueue, pui8Data, ui32BytesTransferred); + } + else + { + // + // If the buffer isn't enabled, just read straight from the FIFO. + // + ui32ErrorStatus = scard_fifo_read(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + *pui32NumBytesRead = ui32BytesTransferred; + + return ui32ErrorStatus; +} // read_nonblocking() + +//***************************************************************************** +// +// Attempt to write N bytes to the FIFO, but give up if there's no space. +// +//***************************************************************************** +static uint32_t +write_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + uint32_t ui32ErrorStatus; + uint32_t ui32BufferSpace; + uint32_t ui32BytesTransferred; + + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (NULL == pui8Data) || (NULL == pui32NumBytesWritten) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + *pui32NumBytesWritten = 0; + + if ( ui32NumBytes == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular transmit buffer has been enabled. + // + if ( pState->bEnableTxQueue ) + { + // + // If it has, been enabled, write as much data to it as we can, and let + // the caller know how much that was. + // + ui32BufferSpace = am_hal_queue_space_left(&pState->sTxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferSpace ? + ui32NumBytes : ui32BufferSpace); + + am_hal_queue_item_add(&pState->sTxQueue, pui8Data, ui32BytesTransferred); + + // + // Transfer as much data as possible from the queue to the fifo. + // + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If the buffer isn't enabled, just write straight to the FIFO. + // + scard_fifo_write(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + *pui32NumBytesWritten = ui32BytesTransferred; + + return AM_HAL_STATUS_SUCCESS; +} // write_nonblocking() + +//***************************************************************************** +// +// This function will keep reading bytes until it either gets N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +read_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesRead, ui32RemainingBytes, + ui32TimeSpent, i; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if ( ui32TimeoutMs == 0 ) + { + return read_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesRead); + } + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // Loop until we're done reading. This will either be because we hit a + // timeout, or we got the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while ( ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs) ) + { + // + // Read as much as we can. + // + ui32BytesRead = 0; + ui32Status = read_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesRead); + // + // Update the tracking variables. + // + i += ui32BytesRead; + ui32RemainingBytes -= ui32BytesRead; + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + if ( pui32NumBytesRead ) + { + *pui32NumBytesRead = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if ( ui32RemainingBytes ) + { + delay_us(1); + + if ( ui32TimeoutMs != AM_HAL_SCARD_WAIT_FOREVER ) + { + ui32TimeSpent++; + } + } + } + + if ( pui32NumBytesRead ) + { + *pui32NumBytesRead = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // read_timeout() + +//***************************************************************************** +// +// This function will keep writing bytes until it either sends N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +write_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesWritten, ui32RemainingBytes, + ui32TimeSpent, i; + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if ( ui32TimeoutMs == 0 ) + { + return write_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesWritten); + } + + // + // Loop until we're done write. This will either be because we hit a + // timeout, or we sent the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while ( ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs) ) + { + // + // Write as much as we can. + // + ui32BytesWritten = 0; + ui32Status = write_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesWritten); + // + // Update the tracking variables. + // + i += ui32BytesWritten; + ui32RemainingBytes -= ui32BytesWritten; + + if ( ui32Status != AM_HAL_STATUS_SUCCESS ) + { + if ( pui32NumBytesWritten ) + { + *pui32NumBytesWritten = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if ( ui32RemainingBytes ) + { + delay_us(1); + + if ( ui32TimeoutMs != AM_HAL_SCARD_WAIT_FOREVER ) + { + ui32TimeSpent++; + } + } + } + + if ( pui32NumBytesWritten ) + { + *pui32NumBytesWritten = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // write_timeout() + +//***************************************************************************** +// +// Send or receive bytes. +// +//***************************************************************************** +uint32_t +am_hal_scard_transfer(void *pHandle, const am_hal_scard_transfer_t *pTransfer) +{ + // + // Pick the right function to use based on the transfer structure. + // + if ( pTransfer->ui32Direction == AM_HAL_SCARD_WRITE ) + { + return write_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + else if ( pTransfer->ui32Direction == AM_HAL_SCARD_READ ) + { + return read_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + + return AM_HAL_STATUS_INVALID_OPERATION; +} // am_hal_scard_transfer() + +//***************************************************************************** +// +// Wait for all of the traffic in the TX pipeline to be sent. +// +//***************************************************************************** +uint32_t +am_hal_scard_tx_flush(void *pHandle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // If we have a TX queue, we should wait for it to empty. + // + if ( pState->bEnableTxQueue ) + { + while ( am_hal_queue_data_left(&(pState->sTxQueue)) ) + { + ONE_BIT_DELAY(pState); + } + } + + // + // Wait for the IDLE bit to go high. + // + while ( SCARDn(ui32Module)->SR1_b.IDLE != 1 ) + { + ONE_BIT_DELAY(pState); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_tx_flush() + +//***************************************************************************** +// +// Interrupt service +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_service(void *pHandle, uint32_t ui32Status, uint32_t *pui32ScardTxIdle) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint32_t ui32ErrorStatus; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Check to see if we have filled the Rx FIFO past the configured limit, or + // if we have an 'old' character or two sitting in the FIFO. + // + if ( (ui32Status & (SCARD_SR_TBERBF_Msk | SCARD_SR_FHF_Msk | SCARD_SR_FNE_Msk) ) && + pState->bEnableRxQueue) + { + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if our TX buffer has been recently emptied. If so, we + // should refill it from the TX ring buffer. + // + if ( (ui32Status & SCARD_SR_TBERBF_Msk) && pState->bEnableTxQueue ) + { + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // If this pointer is null, we can just return success now. There is no + // need to figure out if the SCC is idle. + // + if ( pui32ScardTxIdle == 0 ) + { + return AM_HAL_STATUS_SUCCESS; + } + + if ( SCARDn(ui32Module)->SR1_b.IDLE == 1 ) + { + *pui32ScardTxIdle = true; + } + else + { + *pui32ScardTxIdle = false; + } + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Interrupt enable. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_enable(void *pHandle, uint32_t ui32Index, uint32_t ui32IntMask) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (ui32Index > 1) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( 0 == ui32Index ) + { + SCARDn(ui32Module)->IER |= ui32IntMask; + } + else + { + SCARDn(ui32Module)->IER1 |= ui32IntMask; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_enable() + +//***************************************************************************** +// +// Interrupt disable. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_disable(void *pHandle, uint32_t ui32Index, uint32_t ui32IntMask) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (ui32Index > 1) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( 0 == ui32Index ) + { + SCARDn(ui32Module)->IER &= ~ui32IntMask; + } + else + { + SCARDn(ui32Module)->IER1 &= ~ui32IntMask; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_disable() + +//***************************************************************************** +// +// Interrupt clear. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_clear(void *pHandle, uint32_t ui32Index, uint32_t ui32IntMask) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( (!AM_HAL_SCARD_CHK_HANDLE(pHandle)) || (ui32Index > 1) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + if ( 0 == ui32Index ) + { + SCARDn(ui32Module)->SR = ui32IntMask; + } + else + { + SCARDn(ui32Module)->SR1 = ui32IntMask; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_clear() + +//***************************************************************************** +// +// Returns the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_scard_interrupt_status_get(void *pHandle, uint32_t ui32Index, uint32_t *pui32Status) +{ + am_hal_scard_state_t *pState = (am_hal_scard_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // If requested, only return the interrupts that are enabled. + // + *pui32Status = ui32Index ? SCARDn(ui32Module)->SR1 : SCARDn(ui32Module)->SR; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_scard_interrupt_status_get() + + +//***************************************************************************** +// +//! @brief SCARD control function +//! +//! @param handle - handle for the SCARD. +//! @param eReq - device specific special request code. +//! @param pArgs - pointer to the request specific arguments. +//! +//! This function allows advanced settings +//! +//! @return status - generic or interface specific status. +// +//***************************************************************************** +uint32_t +am_hal_scard_control(void *pHandle, am_hal_scard_request_e eReq, void *pArgs) +{ + am_hal_scard_state_t *pSCCState = (am_hal_scard_state_t*)pHandle; + uint32_t status = AM_HAL_STATUS_SUCCESS; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if ( !AM_HAL_SCARD_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Validate the parameters + // + if ( eReq >= AM_HAL_SCARD_REQ_MAX ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + uint32_t ui32Module = pSCCState->ui32Module; + switch (eReq) + { + case AM_HAL_SCARD_REQ_ACTIVATE: + { + uint16_t etu; + etu = ((SCARDn(ui32Module)->BPRH & SCARD_BPRH_BPRH_Msk) << 8); + etu = etu | SCARDn(ui32Module)->BPRL; + etu = (SCARD_RST_LOW_TIME / etu) + 1; + + config_etucounter(ui32Module, etu); + SCARD_WHILE_TIMEOUT_MS(!SCARDn(ui32Module)->SR1_b.ECNTOVER, 1000, AM_HAL_SCARD_STATUS_BUS_ERROR); + SCARDn(ui32Module)->SR1_b.ECNTOVER = 1; + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.RSTIN = 1); + } + break; + case AM_HAL_SCARD_REQ_DEACTIVATE: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.RSTIN = 0); + break; + case AM_HAL_SCARD_REQ_BAUDRATE: + if ( pArgs ) + { + config_baudrate(pHandle, *(uint32_t*)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_CARD_FORMAT: + if ( pArgs ) + { + config_cardformat(ui32Module, *(uint32_t*)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_PARITY: + if ( pArgs ) + { + config_parity(ui32Module, *(uint32_t*)pArgs); + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_PROTOCOL: + if ( pArgs ) + { + if ( AM_HAL_STATUS_SUCCESS != config_protocol(ui32Module, *(uint32_t*)pArgs) ) + { + status = AM_HAL_STATUS_INVALID_ARG; + } + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_GUARDTIME: + if ( pArgs ) + { + SCARDn(ui32Module)->GTR = *(uint32_t*)pArgs; + } + else + { + status = AM_HAL_STATUS_INVALID_ARG; + } + break; + case AM_HAL_SCARD_REQ_CLK_START: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.CST = 0); + break; + case AM_HAL_SCARD_REQ_CLK_STOP: + SCARD_SYNC_OPER(ui32Module, SCARDn(ui32Module)->UCR_b.CST = 1); + break; + default: + status = AM_HAL_STATUS_INVALID_ARG; + } + + return status; +} + + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.h new file mode 100644 index 0000000000..fb9ca1949a --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_scard.h @@ -0,0 +1,660 @@ +//***************************************************************************** +// +// am_hal_scard.h +//! @file +//! +//! @brief Functions for accessing and configuring the SCARD. +//! +//! @addtogroup scard3 +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_SCARD_H +#define AM_HAL_SCARD_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable SCARD module number. +// +//***************************************************************************** +#define SCARDn(n) ((SCARD_Type*)(SCARD_BASE + (n * (SCARD_BASE - SCARD_BASE)))) + +//***************************************************************************** +// +// Initial character TS +// +//***************************************************************************** +#define AM_HAL_SCARD_DIR_MSB 0x3F //(H)LHHL LLL LLH, state L encodes value 1, msb +#define AM_HAL_SCARD_DIR_LSB 0x3B //(H)LHHL HHH LLH, state H encodes value 1, lsb + +//***************************************************************************** +// +// Informations provided by T0 +// +//***************************************************************************** +#define AM_HAL_SCARD_T0_BIT_TA1_MASK (1 << 4) +#define AM_HAL_SCARD_T0_BIT_TB1_MASK (1 << 5) +#define AM_HAL_SCARD_T0_BIT_TC1_MASK (1 << 6) +#define AM_HAL_SCARD_T0_BIT_TD1_MASK (1 << 7) + +#define AM_HAL_SCARD_TA1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TA1_MASK) == AM_HAL_SCARD_T0_BIT_TA1_MASK) +#define AM_HAL_SCARD_TB1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TB1_MASK) == AM_HAL_SCARD_T0_BIT_TB1_MASK) +#define AM_HAL_SCARD_TC1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TC1_MASK) == AM_HAL_SCARD_T0_BIT_TC1_MASK) +#define AM_HAL_SCARD_TD1_PRESENCE(T0) (((T0) & AM_HAL_SCARD_T0_BIT_TD1_MASK) == AM_HAL_SCARD_T0_BIT_TD1_MASK) + +#define AM_HAL_SCARD_HISTORY_LEN(T0) ((T0)&0x0F) + +//***************************************************************************** +// +// Protocol type T +// +//***************************************************************************** +#define AM_HAL_SCARD_PROTOCOL_T0 0 +#define AM_HAL_SCARD_PROTOCOL_T1 1 +#define AM_HAL_SCARD_PROTOCOL_T15 15 + +#define AM_HAL_SCARD_PROTOCOL_DEFAULT AM_HAL_SCARD_PROTOCOL_T0 + +//***************************************************************************** +// +// Structure and content of PPS request and PPS confirm +// +//***************************************************************************** +#define AM_HAL_SCARD_CLA_PPS 0xFF + +#define AM_HAL_SCARD_PPS1_PRESENCE(PPS0) (((PPS0) & (1 << 4)) == (1 << 4)) +#define AM_HAL_SCARD_PPS2_PRESENCE(PPS0) (((PPS0) & (1 << 5)) == (1 << 5)) +#define AM_HAL_SCARD_PPS3_PRESENCE(PPS0) (((PPS0) & (1 << 6)) == (1 << 6)) + +//***************************************************************************** +// +// Informations provided by TA1 +// +//***************************************************************************** +#define AM_HAL_SCARD_FI(TA1) (((TA1) >> 4) & 0x0F) +#define AM_HAL_SCARD_DI(TA1) (((TA1) >> 0) & 0x0F) + +#define AM_HAL_SCARD_FI_DI_DEFAULT 0x11 + +//***************************************************************************** +// +// Informations provided by TDi +// +//***************************************************************************** +#define AM_HAL_SCARD_TDi_BIT_TAiP1_MASK (1 << 4) +#define AM_HAL_SCARD_TDi_BIT_TBiP1_MASK (1 << 5) +#define AM_HAL_SCARD_TDi_BIT_TCiP1_MASK (1 << 6) +#define AM_HAL_SCARD_TDi_BIT_TDiP1_MASK (1 << 7) + +#define AM_HAL_SCARD_TAiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TAiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TAiP1_MASK) +#define AM_HAL_SCARD_TBiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TBiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TBiP1_MASK) +#define AM_HAL_SCARD_TCiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TCiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TCiP1_MASK) +#define AM_HAL_SCARD_TDiP1_PRESENCE(TDi) (((TDi) & AM_HAL_SCARD_TDi_BIT_TDiP1_MASK) == AM_HAL_SCARD_TDi_BIT_TDiP1_MASK) + +#define AM_HAL_SCARD_PROTOCOL_TYPE(TDi) ((TDi) & 0x0F) + +#define AM_HAL_SCARD_MAX_ATR_LENGTH 33 //1+32 +#define AM_HAL_SCARD_MAX_PPS_LENGTH 6 +#define AM_HAL_SCARD_APDU_HEADER_LENGTH 5 +#define AM_HAL_SCARD_SW_LENGTH 2 + +//***************************************************************************** +// +// TypeDefs +// +//***************************************************************************** +typedef struct +{ + uint8_t pps0; + uint8_t pps1; + uint8_t pps2; + uint8_t pps3; +}am_hal_scard_pps_t; + +typedef struct +{ + uint8_t cla; + uint8_t ins; + uint8_t p1; + uint8_t p2; + uint8_t p3; +}am_hal_scard_header_t; + +typedef struct +{ + am_hal_scard_header_t header; + uint8_t data[256]; +}am_hal_scard_tpdu_t; + +typedef union +{ + struct + { + uint8_t s0; + uint8_t s1; + }element; + + uint16_t entirety; +}am_hal_scard_sw_t; + +typedef enum +{ + AM_HAL_SCARD_CONV_AUTO, + AM_HAL_SCARD_CONV_LSB_0X3B, + AM_HAL_SCARD_CONV_MSB_0X3F +}am_hal_scard_cardformat_e; + +typedef enum +{ + AM_HAL_SCARD_EVEN, + AM_HAL_SCARD_ODD +}am_hal_scard_parity_e; + +typedef enum +{ + AM_HAL_SCARD_APDU_CLA, + AM_HAL_SCARD_APDU_INS, + AM_HAL_SCARD_APDU_P1, + AM_HAL_SCARD_APDU_P2, + AM_HAL_SCARD_APDU_LC +}am_hal_scard_apdu_header_e; + +//***************************************************************************** +// +// Definitions +// +//***************************************************************************** +#define SCARD_RST_LOW_TIME 42000 + +#define AM_HAL_SCARD_PARITY_ENABLE 0x10 + +//***************************************************************************** +// +// SCARD configuration options. +// +//***************************************************************************** +typedef struct +{ + // + // Standard SCARD options. + // + uint32_t ui32Fidi; + uint32_t ui32Protocol; + uint32_t ui32Direction; + uint32_t ui32Parity; + uint32_t ui32GuardTime; + uint32_t ui32ClkLevel; + + // + // Timeouts + // + uint32_t ui32TxTimeout; + uint32_t ui32RxTimeout; + + // + // Buffers + // + uint8_t *pui8TxBuffer; + uint32_t ui32TxBufferSize; + uint8_t *pui8RxBuffer; + uint32_t ui32RxBufferSize; +} +am_hal_scard_config_t; + +typedef enum +{ + AM_HAL_SCARD_REQ_ACTIVATE = 0, + AM_HAL_SCARD_REQ_DEACTIVATE, + AM_HAL_SCARD_REQ_BAUDRATE, + AM_HAL_SCARD_REQ_CARD_FORMAT, + AM_HAL_SCARD_REQ_PARITY, + AM_HAL_SCARD_REQ_PROTOCOL, + AM_HAL_SCARD_REQ_GUARDTIME, + AM_HAL_SCARD_REQ_CLK_START, + AM_HAL_SCARD_REQ_CLK_STOP, + AM_HAL_SCARD_REQ_MAX +}am_hal_scard_request_e; + +//***************************************************************************** +// +// @brief SCARD transfer structure. +// +// This structure describes a SCARD transaction that can be performed by \e +// am_hal_scard_transfer() +// +//***************************************************************************** +typedef struct +{ + //! Determines whether data should be read or written. + //! + //! Should be either AM_HAL_SCARD_WRITE or AM_HAL_SCARD_READ + uint32_t ui32Direction; + + //! Pointer to data to be sent, or space to fill with received data. + uint8_t *pui8Data; + + //! Number of bytes to send or receive. + uint32_t ui32NumBytes; + + //! Timeout in milliseconds. + //! + //! Given a timeout value, the \e am_hal_scard_transfer() function will keep + //! trying to transfer data until either the number of bytes is satisfied, + //! or the time runs out. If provided with a value of zero, the transfer + //! function will only send as much data as it can immediately deal with. + //! If provided with a timeout value of \e AM_HAL_SCARD_WAIT_FOREVER, the + //! function will block until either the final "read" byte is received or + //! the final "write" byte is placed in the output buffer. + uint32_t ui32TimeoutMs; + + //! Number of bytes successfully transferred. + uint32_t *pui32BytesTransferred; +} +am_hal_scard_transfer_t; + +//***************************************************************************** +// +// Scard transfer options. +// +//***************************************************************************** +#define AM_HAL_SCARD_WRITE 1 +#define AM_HAL_SCARD_READ 0 +#define AM_HAL_SCARD_WAIT_MAX_TIME 0xFFFF +#define AM_HAL_SCARD_WAIT_FOREVER 0xFFFFFFFF +#define AM_HAL_SCARD_CLK_FREQ 3000000 + +//***************************************************************************** +// +// SCARD interrupts. +// +//***************************************************************************** +#define AM_HAL_SCARD_INT_FHFEN SCARD_IER_FHFEN_Msk +#define AM_HAL_SCARD_INT_FT2RENDEN SCARD_IER_FT2RENDEN_Msk +#define AM_HAL_SCARD_INT_PEEN SCARD_IER_PEEN_Msk +#define AM_HAL_SCARD_INT_OVREN SCARD_IER_OVREN_Msk +#define AM_HAL_SCARD_INT_FEREN SCARD_IER_FEREN_Msk +#define AM_HAL_SCARD_INT_TBERBFEN SCARD_IER_TBERBFEN_Msk +#define AM_HAL_SCARD_INT_FNEEN SCARD_IER_FNEEN_Msk +#define AM_HAL_SCARD_INT_SYNCENDEN SCARD_IER1_SYNCENDEN_Msk +#define AM_HAL_SCARD_INT_PRLEN SCARD_IER1_PRLEN_Msk +#define AM_HAL_SCARD_INT_ECNTOVEREN SCARD_IER1_ECNTOVEREN_Msk +#define AM_HAL_SCARD_INT_ALL 0xFFFFFFFF + +//***************************************************************************** +// +//! @name SCARD Status Register +//! @brief Macro definitions for SCARD Status Register Bits. +// +//***************************************************************************** +#define AM_HAL_SCARD_SR_TX_EMPTY (_VAL2FLD(SCARD_SR_TBERBF, 1)) +#define AM_HAL_SCARD_SR_RX_FULL (_VAL2FLD(SCARD_SR_TBERBF, 1)) +#define AM_HAL_SCARD_SR_RX_HALF_FULL (_VAL2FLD(SCARD_SR_FHF, 1)) +#define AM_HAL_SCARD_SR_RX_NOT_EMPTY (_VAL2FLD(SCARD_SR_FNE, 1)) +#define AM_HAL_SCARD_SR_FT2REND (_VAL2FLD(SCARD_SR_FT2REND, 1)) +#define AM_HAL_SCARD_SR_IDLE (_VAL2FLD(SCARD_SR1_IDLE, 1)) + +//***************************************************************************** +// +// SCC FIFO size for Apollo3. +// +//***************************************************************************** +#define AM_HAL_SCARD_FIFO_MAX 8 + +//***************************************************************************** +// +//! @brief Initialize the SCARD interface. +//! +//! @param ui32Module is the module number for the SCARD to initialize. +//! @param ppHandle is the location to write the SCARD handle. +//! +//! This function sets internal tracking variables associated with a specific +//! SCARD module. It should be the first SCARD API called for each SCARD module in +//! use. The handle can be used to interact with the SCARD +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief Deinitialize the SCARD interface. +//! +//! @param pHandle is a previously initialized SCARD handle. +//! +//! This function effectively disables future calls to interact with the SCARD +//! refered to by \e pHandle. The user may call this function if SCARD operation +//! is no longer desired. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_deinitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the power state of the SCARD module. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ePowerstate is the desired power state of the SCARD. +//! @parame bRetainState is a flag to ask the HAL to save SCARD registers. +//! +//! This function can be used to switch the power to the SCARD on or off. If \e +//! bRetainState is true during a powerdown operation, it will store the SCARD +//! configuration registers to SRAM, so it can restore them on power-up. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); + +//***************************************************************************** +// +//! @brief Used to configure basic SCARD settings. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param psConfig is a structure of SCARD configuration options. +//! +//! This function takes the options from an \e am_hal_scard_config_t structure, +//! and applies them to the SCARD referred to by \e pHandle. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_configure(void *pHandle, + am_hal_scard_config_t *psConfig); + +//***************************************************************************** +// +//! @brief Transfer data through the SCARD interface. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param am_hal_scard_transfer_t is a structure describing the operation. +//! +//! This function executes a transaction as described by the \e +//! am_hal_scard_transfer_t structure. It can either read or write, and it will +//! take advantage of any buffer space provided by the \e +//! am_hal_scard_configure() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_transfer(void *pHandle, + const am_hal_scard_transfer_t *pTransfer); + + +//***************************************************************************** +// +//! @brief Wait for the SCARD TX to become idle +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! +//! This function waits (polling) for all data in the SCARD TX FIFO and SCARD TX +//! buffer (if configured) to be fully sent on the physical SCARD interface. +//! This is not the most power-efficient way to wait for SCARD idle, but it can be +//! useful in simpler applications, or where power-efficiency is less important. +//! +//! Once this function returns, the SCARD can be safely disabled without +//! interfering with any previous transmissions. +//! +//! For a more power-efficient way to shut down the SCARD, check the +//! \e am_hal_scard_interrupt_service() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_tx_flush(void *pHandle); + +//***************************************************************************** +// +//! @brief This function handles the SCARD buffers during SCARD interrupts. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32Status is the interrupt status at the time of ISR entry. +//! @param pui32ScardTxIdle can be used to store the SCARD idle status. +//! +//! The main purpose of this function is to manage the SCARD buffer system. Any +//! buffers configured by \e am_hal_scard_buffer_configure will be managed by +//! this service routine. Data queued for transmit will be added to the SCARD TX +//! FIFO as space allows, and data stored in the SCARD RX FIFO will be copied +//! out and stored in the RX buffer. This function will skip this transfer for +//! any buffer that has not been configured. +//! +//! In addition, this function can be used to alert the caller when the SCARD +//! becomes idle via the optional \e pui32ScardTxIdle argument. This function +//! will set this variable any time it completes its operation and the SCARD TX +//! channel is no longer in use (including both the FIFO and any configured +//! buffer). +//! +//! For RTOS-enabled cases, this function does not necessarily need to be +//! called inside the actual ISR for the SCARD, but it should be called promptly +//! in response to the receipt of a SCARD TX, RX, or RX timeout interrupt. If +//! the service routine is not called quickly enough, the caller risks an RX +//! FIFO overflow (data can be lost here), or a TX FIFO underflow (usually not +//! harmful). +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_service(void *pHandle, + uint32_t ui32Status, + uint32_t *pui32ScardTxIdle); + +//***************************************************************************** +// +//! @brief Enable interrupts. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32IntMask is the bitmask of interrupts to enable. +//! +//! This function enables the SCARD interrupt(s) given by ui32IntMask. If +//! multiple interrupts are desired, they can be OR'ed together. +//! +//! @note This function need not be called for SCARD FIFO interrupts if the SCARD +//! buffer service provided by \e am_hal_scard_buffer_configure() and \e +//! am_hal_scard_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_enable(void *pHandle, uint32_t ui32Index, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Disable interrupts. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32IntMask is the bitmask of interrupts to disable. +//! +//! This function disables the SCARD interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be disabled, they can be OR'ed together. +//! +//! @note This function need not be called for SCARD FIFO interrupts if the SCARD +//! buffer service provided by \e am_hal_scard_buffer_configure() and \e +//! am_hal_scard_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_disable(void *pHandle, uint32_t ui32Index, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Clear interrupt status. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! @param ui32IntMask is the bitmask of interrupts to clear. +//! +//! This function clears the SCARD interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be cleared, they can be OR'ed together. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_clear(void *pHandle, uint32_t ui32Index, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Read interrupt status. +//! +//! @param pHandle is the handle for the SCARD to operate on. +//! +//! @param pui32Status is the returned interrupt status (all bits OR'ed +//! together) +//! +//! @param bEnabled determines whether to read interrupts that were not +//! enabled. +//! +//! This function reads the status the SCARD interrupt(s) if \e bEnabled is +//! true, it will only return the status of the enabled interrupts. Otherwise, +//! it will return the status of all interrupts, enabled or disabled. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_SCARD_INT_FHFEN +//! AM_HAL_SCARD_INT_FT2RENDEN +//! AM_HAL_SCARD_INT_PEEN +//! AM_HAL_SCARD_INT_OVREN +//! AM_HAL_SCARD_INT_FEREN +//! AM_HAL_SCARD_INT_TBERBFEN +//! AM_HAL_SCARD_INT_FNEEN +//! AM_HAL_SCARD_INT_SYNCENDEN +//! AM_HAL_SCARD_INT_PRLEN +//! AM_HAL_SCARD_INT_ECNTOVEREN +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable SCARD errors. + +// +//***************************************************************************** +extern uint32_t am_hal_scard_interrupt_status_get(void *pHandle, uint32_t ui32Index, + uint32_t *pui32Status); + +extern uint32_t am_hal_scard_control(void *pHandle, am_hal_scard_request_e eReq, void *pArgs); + +typedef enum +{ + AM_HAL_SCARD_STATUS_BUS_ERROR = AM_HAL_STATUS_MODULE_SPECIFIC_START, + AM_HAL_SCARD_STATUS_RX_QUEUE_FULL, + AM_HAL_SCARD_STATUS_PROTOCAL_NOT_SUPPORT, +} +am_hal_scard_errors_t; + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SCARD_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.c new file mode 100644 index 0000000000..8a28c3eb37 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.c @@ -0,0 +1,222 @@ +//***************************************************************************** +// +// am_hal_secure_ota.c +//! @file +//! +//! @brief Functions for secure over-the-air. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_mcu_apollo.h" + +// Local defines +#define FLASH_INVALID 0xFFFFFFFF + +// Internal OTA state information +typedef struct +{ + uint32_t flashSize; + uint32_t otaDescAddr; + uint32_t numOta; +} am_hal_secure_ota_state_t; + +static am_hal_secure_ota_state_t gSOtaState; + +// Erase a flash page +static void +erase_flash_page(uint32_t ui32ProgamKey, uint32_t ui32Addr) +{ + uint32_t ui32CurrentPage, ui32CurrentBlock; + + // + // Figure out what page and block we're working on. + // + ui32CurrentPage = AM_HAL_FLASH_ADDR2PAGE(ui32Addr); + ui32CurrentBlock = AM_HAL_FLASH_ADDR2INST(ui32Addr); + + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + am_hal_flash_page_erase(ui32ProgamKey, + ui32CurrentBlock, ui32CurrentPage); + // + // Exit the critical section. + // + AM_CRITICAL_END +} + + +//***************************************************************************** +// +//! @brief Initialize OTA state +//! +//! Initializes the OTA state. This should be called before doing any other operation +//! +//! @param ui32ProgamKey - The Flash programming key +//! @param pOtaDesc should be start of a flash page designated for OTA Descriptor +//! +//! This call will erase the flash page, which will then be incrementally +//! populated as OTA's are added. It will also initialize the OTAPOINTER to point +//! to this descriptor, marking it as invalid at the same time +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_ota_init(uint32_t ui32ProgamKey, uint32_t *pOtaDesc) +{ + am_hal_mcuctrl_device_t sDevice; + uint32_t otaDescAddr = (uint32_t)pOtaDesc; + + // + // Get chip specific info + // + am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &sDevice); + gSOtaState.flashSize = sDevice.ui32FlashSize; + + // Validate the flash page + if ((otaDescAddr >= gSOtaState.flashSize) || + (otaDescAddr & (AM_HAL_FLASH_PAGE_SIZE - 1))) + { + return AM_HAL_STATUS_INVALID_ARG; + } + // TODO - check against protected pages + // Erase the page + erase_flash_page(ui32ProgamKey, otaDescAddr); + // Initialize the OTA Pointer + MCUCTRL->OTAPOINTER = otaDescAddr; + gSOtaState.numOta = 0; + gSOtaState.otaDescAddr = otaDescAddr; + + return AM_HAL_STATUS_SUCCESS; +} + +// Add a new OTA to descriptor +//***************************************************************************** +// +//! @brief Add a new image for OTA +//! +//! Adds a new image to the OTA Descriptor. +//! +//! @param ui32ProgamKey - The Flash programming key +//! @param imageMagic image magic# identifying type of image being added to OTA descr +//! @param pImage should point to the start of new image to be added to descr +//! +//! This will program the next available entry in OTA descriptor. It will also set +//! appropriate state in the OTA pointer register +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_ota_add(uint32_t ui32ProgamKey, uint8_t imageMagic, uint32_t *pImage) +{ + uint32_t imageAddr = (uint32_t)pImage; + // Validate the Image Pointer + if ((imageAddr >= gSOtaState.flashSize) || + (imageAddr & (AM_HAL_FLASH_PAGE_SIZE - 1))) + { + return AM_HAL_STATUS_INVALID_ARG; + } + if (gSOtaState.numOta == AM_HAL_SECURE_OTA_MAX_OTA) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + imageAddr |= AM_HAL_OTA_STATUS_PENDING; + // Program the OTA Descriptor word + am_hal_flash_program_main(ui32ProgamKey, + &imageAddr, + ((uint32_t *)gSOtaState.otaDescAddr + gSOtaState.numOta++), + 1); + + // Set appropriate OTA Pointer bits + MCUCTRL->OTAPOINTER_b.OTAVALID = 1; + if (imageMagic == AM_IMAGE_MAGIC_SBL) + { + MCUCTRL->OTAPOINTER_b.OTASBLUPDATE = 1; + } + + return AM_HAL_STATUS_SUCCESS; +} + +// Get OTA Status +// Can be called anytime (generally after coming back from reset to check the status of OTA +// Will be also used by sbl_main to identify list of OTA's left for it (would show up as PENDING) +//***************************************************************************** +// +//! @brief Get Current OTA Descriptor state +//! +//! @param pOtaDesc should be start of a flash page designated for OTA Descriptor +//! @param maxOta Determines the size of the following buffer +//! @param pStatus - Return Parameter - populated by this function indicating the OTA +//! status of various OTA's +//! +//! This will retrieve the current OTA status of various images added to the OTA descr +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_get_ota_status(uint32_t *pOtaDesc, uint32_t maxOta, am_hal_ota_status_t *pStatus) +{ + uint32_t numOta = 0; + // Fill up the return structure + while (maxOta--) + { + if (pOtaDesc[numOta] == FLASH_INVALID) + { + pStatus[numOta].pImage = (uint32_t *)pOtaDesc[numOta]; + break; + } + else + { + pStatus[numOta].pImage = (uint32_t *)(pOtaDesc[numOta] & ~0x3); + pStatus[numOta].status = (am_hal_ota_status_e)(pOtaDesc[numOta] & 0x3); + } + numOta++; + } + return AM_HAL_STATUS_SUCCESS; +} diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.h new file mode 100644 index 0000000000..400ccbd845 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_secure_ota.h @@ -0,0 +1,228 @@ +//***************************************************************************** +// +// am_hal_secure_ota.h +//! @file +//! +//! @brief Functions for secure over-the-air. +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_SECURE_OTA_H +#define AM_HAL_SECURE_OTA_H +// Ambiq Standard Image Format related definitions +// Magic Numbers +#define AM_IMAGE_MAGIC_SBL 0xA3 +#define AM_IMAGE_MAGIC_AM3P 0x3A +#define AM_IMAGE_MAGIC_PATCH 0xAF +#define AM_IMAGE_MAGIC_MAIN 0xC0 +#define AM_IMAGE_MAGIC_CHILD 0xCC +#define AM_IMAGE_MAGIC_NONSECURE 0xCB +#define AM_IMAGE_MAGIC_INFO0 0xCF + +// First 30 words of the image headers follow similar pattern +typedef struct +{ + union + { + uint32_t ui32; + struct + { + uint32_t blobSize : 20; + uint32_t resvd : 3; + uint32_t encrypted : 1; + uint32_t magicNum : 8; + } s; + } w0; + uint32_t crc; + union + { + uint32_t ui32; + struct + { + uint32_t authAlgo : 4; + uint32_t authKeyIdx : 4; + uint32_t encAlgo : 4; + uint32_t keyIdx : 4; + uint32_t resvd3 : 8; + uint32_t crcBoot : 1; + uint32_t authBoot : 1; + uint32_t resvd2 : 2; + uint32_t crcInstall : 1; + uint32_t authInstall : 1; + uint32_t resvd1 : 2; + } s; + } w2; + uint32_t w3; + uint32_t signature[8]; // w4-11 + uint32_t iv[4]; // w12-w15 + uint32_t kek[4]; // w16-w19 + uint32_t signatureClear[8]; // w20-w27 + union + { + uint32_t ui32; + struct + { + uint32_t offsetWords : 16; + uint32_t sizeWords : 16; + } info0; + struct + { + uint32_t encap : 1; + uint32_t resvd : 1; + uint32_t loadAddrMsb : 30; + } s1; + struct + { + uint32_t writeProtect : 1; + uint32_t copyProtect : 1; + uint32_t loadAddrMsb : 30; + } s; + } addrWord; // w28 + union + { + uint32_t ui32; + uint32_t resv; + uint32_t key; // For info + struct + { + uint32_t version : 15; + uint32_t erasePrev : 1; + uint32_t resv : 16; + } s; + } versionKeyWord; // w29 +} am_image_hdr_common_t; + +// Bitmask used to clear encrypted status in flash +#define AM_IMAGE_BITMASK_ENCRYPTED 0x00800000 +// Number of most significant bits in w28 used for load address +#define AM_IMAGE_LOAD_ADDR_MSB_BITS 30 + +#define AM_IMAGE_GET_LOADADDR(common) (((am_image_hdr_common_t *)(common))->addrWord.s.loadAddrMsb << (32 - AM_IMAGE_LOAD_ADDR_MSB_BITS)) + +#define AM_IMAGE_NUM_TRAILING_WORDS_TO_256 ((256 - sizeof(am_image_hdr_common_t))/4) +#define AM_IMAGE_MAX_CHILD_IMAGE AM_IMAGE_NUM_TRAILING_WORDS_TO_256 + +typedef struct +{ + am_image_hdr_common_t common; + uint32_t childPtr[AM_IMAGE_MAX_CHILD_IMAGE]; +} am_main_image_hdr_t; + +typedef struct +{ + am_image_hdr_common_t common; + uint32_t featureKey; + uint32_t resvd[1]; +} am_thirdparty_image_hdr_t; + +typedef struct +{ + am_image_hdr_common_t common; + uint32_t resvd[AM_IMAGE_NUM_TRAILING_WORDS_TO_256]; +} am_sbl_image_hdr_t; + +// Reserved magic numbers allowed to be used by customer's own bootloader +#define AM_IMAGE_MAGIC_CUST(x) ((((x) & 0xF0) == 0xC0) && ((x) != 0xC0) && ((x) != 0xCC) && ((x) != 0xCB) && ((x) != 0xCF)) + +// OTA Upgrade related definitions + +// Maximum number of OTAs +#define AM_HAL_SECURE_OTA_MAX_OTA 8 + +// OTA Protocol between OTA application and SecureBoot +// OTAPOINTER will be initialized as follows: +// Most significant 30 bits will correspond to most significant 30 bits of OTA Descriptor +// Least Significant bit (bit 0) should be initialized to 1 to indicate a valid OTA Descriptor +// bit 1 should be initialized to 1 to indicate that the list contains an SBL OTA +// OTA Descriptor points to a list of entries, each corresponding to an OTA blob, list terminating in 0xFFFFFFFF +// Each list entry word comprises of following: +// Most significant 30 bits will correspond to most significant 30 bits of OTA blob pointer +// Blob pointer needs to be aligned to Flash Page boundary (8K) +// Least Significant 2 bits should be initialized to 1 to indicate a valid OTA Pending +// After Secboot processes an OTA, it clears the least significant bit (bit 0) +// bit 1 indicates the status of the OTA - 0 for Success, 1 for Failure +#define AM_HAL_SECURE_OTA_OTA_VALID_MASK 0x3 +#define AM_HAL_SECURE_OTA_OTA_GET_BLOB_PTR(ptr) ((uint32_t)(ptr) & ~AM_HAL_SECURE_OTA_OTA_VALID_MASK) +#define AM_HAL_SECURE_OTA_OTA_IS_VALID(ptr) (((uint32_t)(ptr) & AM_HAL_SECURE_OTA_OTA_VALID_MASK) == AM_HAL_SECURE_OTA_OTA_VALID_MASK) +#define AM_HAL_SECURE_OTA_OTA_LIST_END_MARKER 0xFFFFFFFF + +// Bitmasks signifying the bit to be cleared for OTA success/failure +#define AM_HAL_SECURE_OTA_OTA_DONE_FAILURE_CLRMASK 0x1 +#define AM_HAL_SECURE_OTA_OTA_DONE_SUCCESS_CLRMASK 0x3 + + +// OTA Status +typedef enum +{ + AM_HAL_OTA_STATUS_SUCCESS = 0x0, + AM_HAL_OTA_STATUS_ERROR = 0x1, // This should never happen + AM_HAL_OTA_STATUS_FAILURE = 0x2, + AM_HAL_OTA_STATUS_PENDING = 0x3, +} am_hal_ota_status_e; + +// Per Image OTA Status information +typedef struct +{ + uint32_t *pImage; + am_hal_ota_status_e status; +} am_hal_ota_status_t; + +// pOtaDesc should be start of a flash page designated for OTA Descriptor +// This call will erase the flash page, which will then be incrementally populated as OTA's are added +// It will also initialize the OTAPOINTER to point to this descriptor, with LSB indicating it as invalid +uint32_t am_hal_ota_init(uint32_t ui32ProgamKey, uint32_t *pOtaDesc); + +// Add a new OTA to descriptor +// This will program the next available entry in OTA descriptor +// Will also set the valid/sbl flags in OTA pointer register +uint32_t am_hal_ota_add(uint32_t ui32ProgamKey, uint8_t imageMagic, uint32_t *pImage); + +// Get OTA Status +// Can be called anytime (generally after coming back from reset to check the status of OTA +// Will be also used by sbl_main to identify list of OTA's left for it (would show up as PENDING) +uint32_t am_hal_get_ota_status(uint32_t *pOtaDesc, uint32_t maxOta, am_hal_ota_status_t *pStatus); + +#endif // AM_HAL_SECURE_OTA_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.c new file mode 100644 index 0000000000..adc71cbf54 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.c @@ -0,0 +1,573 @@ +//***************************************************************************** +// +// am_hal_security.c +//! @file +//! +//! @brief Functions for on-chip security features +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// Local defines. +//***************************************************************************** +// +// ENABLE_EXTMEM_CRC +// By default, the CRC engine can only operate on data located in internal +// memory (i.e. flash or SRAM). This define enables am_hal_crc() to support +// external memories, but requires a small amount of global SRAM allocated for +// that purpose. If it is not desired to support this feature, set to 0. +// +#define ENABLE_EXTMEM_CRC 1 + +// +// Maximum iterations for hardware CRC to finish +// +#define MAX_CRC_WAIT 100000 + +#define AM_HAL_SECURITY_LOCKSTAT_CUSTOMER 0x1 +#define AM_HAL_SECURITY_LOCKSTAT_RECOVERY 0x40000000 + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +#if ENABLE_EXTMEM_CRC +// +// Set up a small global buffer that can be used am_hal_crc32() when +// computing CRCs on external memory. +// +#define CRC_XFERBUF_SZ (512) // Reserve 512 bytes for the buffer +static uint32_t g_CRC_buffer[CRC_XFERBUF_SZ / 4]; +#endif // ENABLE_EXTMEM_CRC + +// +// Assign ptr variables to avoid an issue with GCC reading from location 0x0. +// +const volatile uint32_t *g_pFlash0 = (uint32_t*)(AM_HAL_SBL_ADDRESS + 0); +const volatile uint32_t *g_pFlash4 = (uint32_t*)(AM_HAL_SBL_ADDRESS + 4); + +//***************************************************************************** +// +//! @brief Hardcoded function - to Run supplied main program +//! +//! @param r0 = vtor - address of the vector table +//! +//! @return Returns None +// +//***************************************************************************** +#if (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION < 6000000) +static __asm void +bl_run_main(uint32_t *vtor) +{ + // + // Store the vector table pointer of the new image into VTOR. + // + movw r3, #0xED08 + movt r3, #0xE000 + str r0, [r3, #0] + + // + // Load the new stack pointer into R1 and the new reset vector into R2. + // + ldr r3, [r0, #0] + ldr r2, [r0, #4] + + // + // Set the stack pointer for the new image. + // + mov sp, r3 + + // + // Jump to the new reset vector. + // + bx r2 +} +#elif (defined (__ARMCC_VERSION)) && (__ARMCC_VERSION >= 6000000) +__attribute__((naked)) +static void +bl_run_main(uint32_t *vtor) +{ + __asm + ( + " movw r3, #0xED08\n\t" // Store the vector table pointer of the new image into VTOR. + " movt r3, #0xE000\n\t" + " str r0, [r3, #0]\n\t" + " ldr r3, [r0, #0]\n\t" // Load the new stack pointer into R1 and the new reset vector into R2. + " ldr r2, [r0, #4]\n\t" + " mov sp, r3\n\t" // Set the stack pointer for the new image. + " bx r2\n\t" // Jump to the new reset vector. + ); +} +#elif defined(__GNUC_STDC_INLINE__) +__attribute__((naked)) +static void +bl_run_main(uint32_t *vtor) +{ + __asm + ( + " movw r3, #0xED08\n\t" // Store the vector table pointer of the new image into VTOR. + " movt r3, #0xE000\n\t" + " str r0, [r3, #0]\n\t" + " ldr r3, [r0, #0]\n\t" // Load the new stack pointer into R1 and the new reset vector into R2. + " ldr r2, [r0, #4]\n\t" + " mov sp, r3\n\t" // Set the stack pointer for the new image. + " bx r2\n\t" // Jump to the new reset vector. + ); +} +#elif defined(__IAR_SYSTEMS_ICC__) +__stackless static inline void +bl_run_main(uint32_t *vtor) +{ + __asm volatile ( + " movw r3, #0xED08\n" // Store the vector table pointer of the new image into VTOR. + " movt r3, #0xE000\n" + " str r0, [r3, #0]\n" + " ldr r3, [r0, #0]\n" // Load the new stack pointer into R1 and the new reset vector into R2. + " ldr r2, [r0, #4]\n" + " mov sp, r3\n" // Set the stack pointer for the new image. + " bx r2\n" // Jump to the new reset vector. + ); +} +#else +#error Compiler is unknown, please contact Ambiq support team +#endif + +// Pre- SBLv2 known versions that do not support callback +static uint32_t sblPreV2[][4] = { + // flash0, flash4, sblVersion, sblVersionAddInfo + {0xA3007860, 0x2E2638FB, 0 , 0}, + {0xA3007E14, 0x5EE4E461, 1 , 0}, + {0xA3008290, 0xB49CECD5, 2 , 0}, +}; + +//***************************************************************************** +// +//! @brief Get Device Security Info +//! +//! @param pSecInfo - Pointer to structure for returned security info +//! +//! This will retrieve the security information for the device +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_info(am_hal_security_info_t *pSecInfo) +{ + uint32_t flash0; + uint32_t flash4; + uint32_t i; + bool bSbl; + if (!pSecInfo) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + pSecInfo->info0Version = AM_REGVAL(0x50020040); + pSecInfo->bInfo0Valid = MCUCTRL->SHADOWVALID_b.INFO0_VALID; + bSbl = MCUCTRL->BOOTLOADER_b.SECBOOTFEATURE; + + if (bSbl) + { + // Check if we're running pre-SBLv2 + flash0 = *g_pFlash0; + flash4 = *g_pFlash4; + // Check if SBL is installed + if ((flash0 >> 24) != AM_IMAGE_MAGIC_SBL) + { + return AM_HAL_STATUS_FAIL; + } + for ( i = 0; i < sizeof(sblPreV2) / sizeof(sblPreV2[0]); i++ ) + { + if ((sblPreV2[i][0] == flash0) && (sblPreV2[i][1] == flash4)) + { + // This is a device prior to SBLv2 + pSecInfo->sblVersion = sblPreV2[i][2]; + pSecInfo->sblVersionAddInfo = sblPreV2[i][3]; + break; + } + } + + if ( i == sizeof(sblPreV2) / sizeof(sblPreV2[0]) ) + { + // SBLv2 or beyond + // Use SBL jump table function + uint32_t status; + uint32_t sblVersion; + uint32_t (*pFuncVersion)(uint32_t *) = (uint32_t (*)(uint32_t *))(AM_HAL_SBL_ADDRESS + 0x1D1); + status = pFuncVersion(&sblVersion); + if (status != AM_HAL_STATUS_SUCCESS) + { + return status; + } + pSecInfo->sblVersion = sblVersion & 0x7FFF; + pSecInfo->sblVersionAddInfo = sblVersion >> 15; + } + } + else + { + return AM_HAL_STATUS_FAIL; + } + return AM_HAL_STATUS_SUCCESS; +} // am_hal_security_get_info() + +//***************************************************************************** +// +//! @brief Set the key for specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pKey - Pointer to 128b key value +//! +//! This will program the lock registers for the specified lock and key +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_set_key(am_hal_security_locktype_t lockType, am_hal_security_128bkey_t *pKey) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (pKey == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + switch (lockType) + { + case AM_HAL_SECURITY_LOCKTYPE_CUSTOMER: + case AM_HAL_SECURITY_LOCKTYPE_RECOVERY: + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + SECURITY->LOCKCTRL = lockType; + SECURITY->KEY0 = pKey->keys.key0; + SECURITY->KEY1 = pKey->keys.key1; + SECURITY->KEY2 = pKey->keys.key2; + SECURITY->KEY3 = pKey->keys.key3; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_security_set_key() + +//***************************************************************************** +// +//! @brief Get the current status of the specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pbUnlockStatus - Pointer to return variable with lock status +//! +//! This will get the lock status for specified lock - true implies unlocked +//! Note that except for customer lock, other locks are self-locking on status read +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_lock_status(am_hal_security_locktype_t lockType, bool *pbUnlockStatus) +{ + uint32_t unlockMask; +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (pbUnlockStatus == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + switch (lockType) + { + case AM_HAL_SECURITY_LOCKTYPE_CUSTOMER: + unlockMask = AM_HAL_SECURITY_LOCKSTAT_CUSTOMER; + break; + case AM_HAL_SECURITY_LOCKTYPE_RECOVERY: + unlockMask = AM_HAL_SECURITY_LOCKSTAT_RECOVERY; + break; + default: + return AM_HAL_STATUS_INVALID_ARG; + } + *pbUnlockStatus = SECURITY->LOCKSTAT & unlockMask; + return AM_HAL_STATUS_SUCCESS; +} // am_hal_security_get_lock_status() + +//***************************************************************************** +// +//! @brief Compute CRC32 for a specified payload +//! +//! @param ui32StartAddr - The start address of the payload. +//! @param ui32SizeBytes - The length of payload in bytes. +//! @param pui32Crc - Pointer to variable to return the computed CRC. +//! +//! This function uses the hardware engine to compute CRC32 on an arbitrary data +//! payload. The payload can reside in any contiguous memory including external +//! memory. +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t +am_hal_crc32(uint32_t ui32StartAddr, uint32_t ui32SizeBytes, uint32_t *pui32Crc) +{ + uint32_t status, ui32CRC32; + bool bInternal; + +#ifndef AM_HAL_DISABLE_API_VALIDATION + if (pui32Crc == NULL) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Make sure size is multiple of 4 bytes + // + if (ui32SizeBytes & 0x3) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + status = AM_HAL_STATUS_OUT_OF_RANGE; // Default status + + // + // Determine whether the startaddr is in internal flash or SRAM. + // + bInternal = ISADDRFLASH(ui32StartAddr) || ISADDRSRAM(ui32StartAddr); + + if ( bInternal ) + { + // + // Program the CRC engine to compute the crc + // + ui32CRC32 = 0xFFFFFFFF; + SECURITY->RESULT = ui32CRC32; + SECURITY->SRCADDR = ui32StartAddr; + SECURITY->LEN = ui32SizeBytes; + SECURITY->CTRL_b.FUNCTION = SECURITY_CTRL_FUNCTION_CRC32; + + // + // Start the CRC + // + SECURITY->CTRL_b.ENABLE = 1; + + // + // Wait for CRC to finish + // + status = am_hal_flash_delay_status_change(MAX_CRC_WAIT, + (uint32_t)&SECURITY->CTRL, SECURITY_CTRL_ENABLE_Msk, 0); + + if (status == AM_HAL_STATUS_SUCCESS) + { + *pui32Crc = SECURITY->RESULT; + } + + return status; + } + +#if ENABLE_EXTMEM_CRC + uint32_t ui32XferSize, ui32cnt; + uint32_t *pui32Buf, *pui32Data; + + // + // If we're here, the source data resides in non-internal memory (that is, + // not flash or SRAM). + // + // Begin the loop for computing the CRC of the external memory. The data + // will first be copied to the SRAM buffer. + // + // Program the parts of the CRC engine that will not need to change + // inside the loop: SRCADDR, FUNCTION, initial seed in RESULT. + // While inside the loop, only the LEN will need to be provided. + // + SECURITY->SRCADDR = (uint32_t)&g_CRC_buffer[0]; + SECURITY->CTRL_b.FUNCTION = SECURITY_CTRL_FUNCTION_CRC32; + + // + // During the loop the RESULT register must not be rewritten, even if the + // value written on each pass is identical. Rewriting it appears to reset + // a state machine such that an incorrect CRC value is computed. + // + ui32CRC32 = 0xFFFFFFFF; + SECURITY->RESULT = ui32CRC32; + + pui32Data = (uint32_t*)ui32StartAddr; + while ( ui32SizeBytes ) + { + // + // First copy a chunk of payload data to SRAM where the CRC engine + // can operate on it. + // + ui32XferSize = (ui32SizeBytes >= CRC_XFERBUF_SZ) ? + CRC_XFERBUF_SZ : ui32SizeBytes; + ui32SizeBytes -= ui32XferSize; + ui32cnt = ui32XferSize / 4; + pui32Buf = &g_CRC_buffer[0]; + while ( ui32cnt-- ) + { + *pui32Buf++ = *pui32Data++; + } + + // + // Program the CRC engine's LEN parameter. + // All other parameters were preprogrammed: SRCADDR, FUNCTION, RESULT. + // + SECURITY->LEN = ui32XferSize; + + // + // Start the CRC + // + SECURITY->CTRL_b.ENABLE = 1; + + // + // Wait for CRC to finish + // + status = am_hal_flash_delay_status_change(MAX_CRC_WAIT, + (uint32_t)&SECURITY->CTRL, SECURITY_CTRL_ENABLE_Msk, 0); + + if ( (status == AM_HAL_STATUS_SUCCESS) && !SECURITY->CTRL_b.CRCERROR ) + { + ui32CRC32 = SECURITY->RESULT; + } + else if ( SECURITY->CTRL_b.CRCERROR ) + { + return AM_HAL_STATUS_HW_ERR; + } + else + { + // + // Error from status_change function. + // Return the CRC value we do have, but return an error. + // + //return status; + break; + } + } + + // + // Return result to caller + // + *pui32Crc = ui32CRC32; +#endif // ENABLE_EXTMEM_CRC + + return status; + +} // am_hal_crc32() + +//***************************************************************************** +// +//! @brief Helper function to Perform exit operations for a secondary bootloader +//! +//! @param pImage - The address of the image to give control to +//! +//! This function does the necessary security operations while exiting from a +//! a secondary bootloader program. If still open, it locks the info0 key region, +//! as well as further updates to the flash protection register. +//! It also checks if it needs to halt to honor a debugger request. +//! If an image address is specified, control is transferred to the same on exit. +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success, if no image address specified +//! If an image address is provided, a successful execution results in transfer to +//! the image - and this function does not return. +// +//***************************************************************************** +uint32_t am_hal_bootloader_exit(uint32_t *pImage) +{ + uint32_t status = AM_HAL_STATUS_SUCCESS; + + // + // Lock the assets + // + if ( MCUCTRL->SHADOWVALID_b.INFO0_VALID && + MCUCTRL->BOOTLOADER_b.PROTLOCK ) + { + am_hal_security_128bkey_t keyVal; + uint32_t *pCustKey = (uint32_t *)0x50021A00; + bool bLockStatus; + + // + // PROTLOCK Open + // This should also mean that Customer key is accessible + // Now lock the key by writing an incorrect value + // + keyVal.keyword[0] = ~pCustKey[0]; + am_hal_security_set_key(AM_HAL_SECURITY_LOCKTYPE_CUSTOMER, &keyVal); + + status = am_hal_security_get_lock_status(AM_HAL_SECURITY_LOCKTYPE_CUSTOMER, &bLockStatus); + + if ((status != AM_HAL_STATUS_SUCCESS) || (bLockStatus)) + { + return AM_HAL_STATUS_FAIL; + } + + // + // Lock the protection register to prevent further region locking + // CAUTION!!! - Can not do AM_BFW on BOOTLOADER register as all writable bits in this register are Write 1 to clear + // + MCUCTRL->BOOTLOADER = _VAL2FLD(MCUCTRL_BOOTLOADER_PROTLOCK, 1); + + // + // Check if we need to halt (debugger request) + // + if (MCUCTRL->SCRATCH0 & 0x1) + { + // Debugger wants to halt + uint32_t dhcsr = AM_REGVAL(0xE000EDF0); + // Clear the flag in Scratch register + MCUCTRL->SCRATCH0 &= ~0x1; + // Halt the core + dhcsr = ((uint32_t)0xA05F << 16) | (dhcsr & 0xFFFF) | 0x3; + AM_REGVAL(0xE000EDF0) = dhcsr; + // Resume from halt + } + } + + // Give control to supplied image + if (pImage) + { + bl_run_main(pImage); + // Does not return + } + + return status; +} // am_hal_bootloader_exit() diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.h new file mode 100644 index 0000000000..207cade085 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_security.h @@ -0,0 +1,185 @@ +//***************************************************************************** +// +// am_hal_security.h +//! @file +//! +//! @brief Functions for security functions +//! +//! @addtogroup +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_HAL_SECURITY_H +#define AM_HAL_SECURITY_H + +// +// Location of SBL install address for this device +// +// Important Note: +// Some caution should be observed when using AM_HAL_SBL_ADDRESS as an address. +// GCC considers use of this address to be a NULL pointer. When compiled with +// high optimization (-O3) and used to read the location with, for example, +// code such as *((volatile uint32_t *)(AM_HAL_SBL_ADDRESS)), GCC will insert +// an instruction it calls "UDF" (undefined), op-code 0xDEFF, which will cause +// a fault on execution to trap the "invalid" null-ptr usage. +// This does not appear to be an issue with IAR and Keil ARM5. +// It is likely an issue with Keil ARM6. +// +#define AM_HAL_SBL_ADDRESS 0x00000000 + + + +typedef struct +{ + bool bInfo0Valid; + uint32_t info0Version; + uint32_t sblVersion; + uint32_t sblVersionAddInfo; +} am_hal_security_info_t; + +// LOCK Definitions +typedef enum +{ + AM_HAL_SECURITY_LOCKTYPE_CUSTOMER = 0x1, + AM_HAL_SECURITY_LOCKTYPE_RECOVERY = 0x9D, +} am_hal_security_locktype_t; + +typedef union +{ + uint32_t keyword[4]; + struct + { + uint32_t key0; + uint32_t key1; + uint32_t key2; + uint32_t key3; + } keys; +} am_hal_security_128bkey_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! @brief Get Device Security Info +//! +//! @param pSecInfo - Pointer to structure for returned security info +//! +//! This will retrieve the security information for the device +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_info(am_hal_security_info_t *pSecInfo); + +//***************************************************************************** +// +//! @brief Set the key for specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pKey - Pointer to 128b key value +//! +//! This will program the lock registers for the specified lock and key +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_set_key(am_hal_security_locktype_t lockType, am_hal_security_128bkey_t *pKey); + +//***************************************************************************** +// +//! @brief Get the current status of the specified lock +//! +//! @param lockType - The lock type to be operated upon +//! @param pbUnlockStatus - Pointer to return variable with lock status +//! +//! This will get the lock status for specified lock +//! Note that except for customer lock, other locks are self-locking on status read +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_security_get_lock_status(am_hal_security_locktype_t lockType, bool *pbUnlockStatus); + +//***************************************************************************** +// +//! @brief Compute CRC32 for a specified payload +//! +//! @param startAddr - The start address of the payload +//! @param sizeBytes - The length of payload in bytes +//! @param pCrc - Pointer to return computed CRC +//! +//! This will use the hardware engine to compute CRC32 on an arbitrary data payload +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success +// +//***************************************************************************** +uint32_t am_hal_crc32(uint32_t startAddr, uint32_t sizeBytes, uint32_t *pCrc); + +//***************************************************************************** +// +//! @brief Helper function to Perform exit operations for a secondary bootloader +//! +//! @param pImage - The address of the image to give control to +//! +//! This function does the necessary security operations while exiting from a +//! a secondary bootloader program. If still open, it locks the info0 key region, +//! as well as further updates to the flash protection register. +//! It also checks if it needs to halt to honor a debugger request. +//! If an image address is specified, control is transferred to the same on exit. +//! +//! @return Returns AM_HAL_STATUS_SUCCESS on success, if no image address specified +//! If an image address is provided, a successful execution results in transfer to +//! the image - and this function does not return. +// +//***************************************************************************** +uint32_t am_hal_bootloader_exit(uint32_t *pImage); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SECURITY_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_status.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_status.h new file mode 100644 index 0000000000..4bb0498c10 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_status.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// am_hal_status.h +//! @file +//! +//! @brief Global status return codes for HAL interface. +//! +//! @addtogroup status3 Global Status Return Codes. +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_STATUS_H +#define AM_HAL_STATUS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + // + // Global Status Returns + // + typedef enum + { + AM_HAL_STATUS_SUCCESS, + AM_HAL_STATUS_FAIL, + AM_HAL_STATUS_INVALID_HANDLE, + AM_HAL_STATUS_IN_USE, + AM_HAL_STATUS_TIMEOUT, + AM_HAL_STATUS_OUT_OF_RANGE, + AM_HAL_STATUS_INVALID_ARG, + AM_HAL_STATUS_INVALID_OPERATION, + AM_HAL_STATUS_MEM_ERR, + AM_HAL_STATUS_HW_ERR, + AM_HAL_STATUS_MODULE_SPECIFIC_START = 0x08000000, + } am_hal_status_e; + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_STATUS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.c new file mode 100644 index 0000000000..cba38f8fa1 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.c @@ -0,0 +1,642 @@ +//***************************************************************************** +// +// am_hal_stimer.c +//! @file +//! +//! @brief Functions for interfacing with the system timer (STIMER). +//! +//! @addtogroup stimer3 System Timer (STIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +//! @brief Set up the stimer. +//! +//! @param ui32STimerConfig is the value to load into the configuration reg. +//! +//! This function should be used to perform the initial set-up of the +//! stimer. +//! +//! @return The 32-bit current config of the STimer Config register +// +//***************************************************************************** +uint32_t +am_hal_stimer_config(uint32_t ui32STimerConfig) +{ + uint32_t ui32CurrVal; + + // + // Read the current config + // + ui32CurrVal = CTIMER->STCFG; + + // + // Write our configuration value. + // + CTIMER->STCFG = ui32STimerConfig; + +#if AM_PART_APOLLO2 + // + // If all of the clock sources are not HFRC, disable LDO when sleeping if timers are enabled. + // + if ( (CTIMER->STCFG_b.CLKSELCTIMER->STCFG_b.CLKSEL == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16) || + (CTIMER->STCFG_b.CLKSELCTIMER->STCFG_b.CLKSEL == AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256) ) + { + PWRCTRL->MISC_b.FORCEMEMVRLPTIMERS = 0; + } + else + { + PWRCTRL->MISC_b.FORCEMEMVRLPTIMERS = 1; + } +#endif + + return ui32CurrVal; +} + +//***************************************************************************** +// +//! @brief Get the current stimer value. +//! +//! This function can be used to read, uninvasively, the value in the stimer. +//! +//! @return The 32-bit value from the STimer counter register. +// +//***************************************************************************** +uint32_t +am_hal_stimer_counter_get(void) +{ + return CTIMER->STTMR; +} + +//***************************************************************************** +// +//! @brief Clear the stimer counter. +//! +//! This function clears the STimer Counter and leaves the stimer running. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_counter_clear(void) +{ + // + // Set the clear bit + // + CTIMER->STCFG |= CTIMER_STCFG_CLEAR_Msk; + + // + // Reset the clear bit + // + CTIMER->STCFG &= ~CTIMER_STCFG_CLEAR_Msk; +} + +//***************************************************************************** +// +//! @brief Set the compare value. +//! +//! @param ui32CmprInstance is the compare register instance number (0-7). +//! @param ui32Delta is the value to add to the STimer counter and load into +//! the comparator register. +//! +//! NOTE: There is no way to set an absolute value into a comparator register. +//! Only deltas added to the STimer counter can be written to the compare +//! registers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta) +{ + uint32_t cfgVal; + uint32_t numTries = 0; + + if ( ui32CmprInstance > 7 ) + { + return; + } + + // We need to disable the compare temporarily while setting the delta value + // That leaves a corner case where we could miss the trigger if setting a very + // small delta. To avoid this, we take critical section, and we should ensure + // that delta value is at least > 1 + + // + // Start a critical section. + // + AM_CRITICAL_BEGIN + + // + // Get current CFG value + // + cfgVal = CTIMER->STCFG; + + // + // Disable the compare if already enabled, when setting the new value + // + CTIMER->STCFG &= ~((AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance)); + + // In rare case the delta might not be effective + // We retry if that is the case. + // Allow for some variability in the value owing to execution latency + while (numTries++ < 4) + { + uint32_t expVal; + uint32_t expMax; + uint32_t cmpVal; + + // Expected value + expVal = CTIMER->STTMR + ui32Delta; + + // Max allowed - taking care of latency + expMax = expVal + 10; + + // + // Set the delta + // + AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; + + // Read back the compare value + cmpVal = AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); + + // Make sure the value is in expected range + if (!AM_HAL_U32_SMALLER(cmpVal, expVal) && !AM_HAL_U32_GREATER(cmpVal, expMax)) + { + break; + } + } + + + // + // Restore Compare Enable bit + // + CTIMER->STCFG |= cfgVal & (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance); + + // + // End the critical section. + // + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Get the current stimer compare register value. +//! +//! @param ui32CmprInstance is the compare register instance number (0-7). +//! +//! This function can be used to read the value in an stimer compare register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t +am_hal_stimer_compare_get(uint32_t ui32CmprInstance) +{ + if ( ui32CmprInstance > 7 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); +} + +//***************************************************************************** +// +//! @brief Start capturing data with the specified capture register. +//! +//! @param ui32CaptureNum is the Capture Register Number to read (0-3). +//! @param ui32GPIONumber is the pin number. +//! @param bPolarity: false (0) = Capture on low to high transition. +//! true (1) = Capture on high to low transition. +//! +//! Use this function to start capturing. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_capture_start(uint32_t ui32CaptureNum, + uint32_t ui32GPIONumber, + bool bPolarity) +{ + uint32_t ui32CapCtrl; + + if ( ui32GPIONumber > (AM_HAL_GPIO_MAX_PADS-1) ) + { + return; + } + + // + // Set the polarity and pin selection in the GPIO block. + // + switch (ui32CaptureNum) + { + case 0: + GPIO->STMRCAP_b.STPOL0 = bPolarity; + GPIO->STMRCAP_b.STSEL0 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE0_Msk; + break; + case 1: + GPIO->STMRCAP_b.STPOL1 = bPolarity; + GPIO->STMRCAP_b.STSEL1 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE1_Msk; + break; + case 2: + GPIO->STMRCAP_b.STPOL2 = bPolarity; + GPIO->STMRCAP_b.STSEL2 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE2_Msk; + break; + case 3: + GPIO->STMRCAP_b.STPOL3 = bPolarity; + GPIO->STMRCAP_b.STSEL3 = ui32GPIONumber; + ui32CapCtrl = CTIMER_CAPTURECONTROL_CAPTURE3_Msk; + break; + default: + return; // error concealment. + } + + // + // Enable it in the CTIMER Block + // + CTIMER->CAPTURECONTROL |= ui32CapCtrl; +} + +//***************************************************************************** +// +//! @brief Start capturing data with the specified capture register. +//! +//! @param ui32CaptureNum is the Capture Register Number to read. +//! +//! Use this function to start capturing. +//! +//! @return None. +// +//***************************************************************************** +void am_hal_stimer_capture_stop(uint32_t ui32CaptureNum) +{ + // + // Disable it in the CTIMER block. + // + CTIMER->CAPTURECONTROL &= + ~(CTIMER_CAPTURECONTROL_CAPTURE0_Msk << + ((CTIMER_CAPTURECONTROL_CAPTURE1_Pos - + CTIMER_CAPTURECONTROL_CAPTURE0_Pos) * ui32CaptureNum)); +} + +//***************************************************************************** +// +//! @brief Get the current stimer nvram register value. +//! +//! @param ui32NvramNum is the NVRAM Register Number to read. +//! @param ui32NvramVal is the value to write to NVRAM. +//! +//! This function can be used to read the value in an stimer NVRAM register. +//! +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_nvram_set(uint32_t ui32NvramNum, uint32_t ui32NvramVal) +{ + if ( ui32NvramNum > 3 ) + { + return; + } + + //AM_REGn(CTIMER, 0, SNVR) + //AM_REG_STIMER_NVRAM(0, ui32NvramNum) = ui32NvramVal; +} + +//***************************************************************************** +// +//! @brief Get the current stimer nvram register value. +//! +//! @param ui32NvramNum is the NVRAM Register Number to read. +//! +//! This function can be used to read the value in an stimer NVRAM register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t am_hal_stimer_nvram_get(uint32_t ui32NvramNum) +{ + if ( ui32NvramNum > 3 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_NVRAM(0, ui32NvramNum)); +} + +//***************************************************************************** +// +//! @brief Get the current stimer capture register value. +//! +//! @param ui32CaptureNum is the Capture Register Number to read. +//! +//! This function can be used to read the value in an stimer capture register. +//! +//! +//! @return None. +// +//***************************************************************************** +uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum) +{ + if ( ui32CaptureNum > 3 ) + { + return 0; + } + + return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum)); +} + +//***************************************************************************** +// +//! @brief Enables the selected system timer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will enable the selected interrupts in the STIMER interrupt +//! enable register. In order to receive an interrupt from an stimer component, +//! you will need to enable the interrupt for that component in this main +//! register, as well as in the stimer configuration register (accessible though +//! am_hal_stimer_config()), and in the NVIC. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_enable(uint32_t ui32Interrupt) +{ + // + // Enable the interrupt at the module level. + // + CTIMERn(0)->STMINTEN |= ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Return the enabled stimer interrupts. +//! +//! This function will return all enabled interrupts in the STIMER +//! interrupt enable register. +//! +//! @return return enabled interrupts. This will be a logical or of: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return Return the enabled timer interrupts. +// +//***************************************************************************** +uint32_t +am_hal_stimer_int_enable_get(void) +{ + // + // Return enabled interrupts. + // + return CTIMERn(0)->STMINTEN; +} + +//***************************************************************************** +// +//! @brief Disables the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will disable the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_disable(uint32_t ui32Interrupt) +{ + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->STMINTEN &= ~ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Sets the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will set the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_set(uint32_t ui32Interrupt) +{ + // + // Set the interrupts. + // + CTIMERn(0)->STMINTSET = ui32Interrupt; +} + +//***************************************************************************** +// +//! @brief Clears the selected stimer interrupt. +//! +//! @param ui32Interrupt is the interrupt to be used. +//! +//! This function will clear the selected interrupts in the STIMER +//! interrupt register. +//! +//! ui32Interrupt should be the logical OR of one or more of the following +//! values: +//! +//! AM_HAL_STIMER_INT_COMPAREA +//! AM_HAL_STIMER_INT_COMPAREB +//! AM_HAL_STIMER_INT_COMPAREC +//! AM_HAL_STIMER_INT_COMPARED +//! AM_HAL_STIMER_INT_COMPAREE +//! AM_HAL_STIMER_INT_COMPAREF +//! AM_HAL_STIMER_INT_COMPAREG +//! AM_HAL_STIMER_INT_COMPAREH +//! +//! AM_HAL_STIMER_INT_OVERFLOW +//! +//! AM_HAL_STIMER_INT_CAPTUREA +//! AM_HAL_STIMER_INT_CAPTUREB +//! AM_HAL_STIMER_INT_CAPTUREC +//! AM_HAL_STIMER_INT_CAPTURED +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_stimer_int_clear(uint32_t ui32Interrupt) +{ + // + // Disable the interrupt at the module level. + // + CTIMERn(0)->STMINTCLR = ui32Interrupt; +} + + +//***************************************************************************** +// +//! @brief Returns either the enabled or raw stimer interrupt status. +//! +//! This function will return the stimer interrupt status. +//! +//! @param bEnabledOnly if true returns the status of the enabled interrupts +//! only. +//! +//! The return value will be the logical OR of one or more of the following +//! values: +//! +//! +//! @return Returns the stimer interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_stimer_int_status_get(bool bEnabledOnly) +{ + // + // Return the desired status. + // + uint32_t ui32RetVal = CTIMERn(0)->STMINTSTAT; + + if ( bEnabledOnly ) + { + ui32RetVal &= CTIMERn(0)->STMINTEN; + } + + return ui32RetVal; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.h new file mode 100644 index 0000000000..24cbefdb1d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_stimer.h @@ -0,0 +1,218 @@ +//***************************************************************************** +// +// am_hal_stimer.h +//! @file +//! +//! @brief Functions for interfacing with the system timer (STIMER). +//! +//! @addtogroup stimer3 System Timer (STIMER) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_STIMER_H +#define AM_HAL_STIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// +//! Compute address of a given COMPARE register. +//! @note - The parameter n should be 0 (as only 1 stimer module exists). +//! For Apollo3, the parameter r should be 0-7 (compare) or 0-3 (capture). +// +#define AM_REG_STIMER_COMPARE(n, r) (CTIMERADDRn(CTIMER, n, SCMPR0) + \ + (r * (offsetof(CTIMER_Type, SCMPR1) - offsetof(CTIMER_Type, SCMPR0)))) + +//! Compute address of a given CAPTURE register. r should be 0-3. +#define AM_REG_STIMER_CAPTURE(n, r) (CTIMERADDRn(CTIMER, n, SCAPT0) + \ + (r * (offsetof(CTIMER_Type, SCAPT1) - offsetof(CTIMER_Type, SCAPT0)))) + +//! Compute address of a given NVRAM register. r should be 0-3. +#define AM_REG_STIMER_NVRAM(n, r) (CTIMERADDRn(CTIMER, n, SNVR0) + \ + (r * (offsetof(CTIMER_Type, SNVR1) - offsetof(CTIMER_Type, SNVR0)))) + + +//***************************************************************************** +// +//! @name Interrupt Status Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_INT_COMPAREA CTIMER_STMINTSTAT_COMPAREA_Msk +#define AM_HAL_STIMER_INT_COMPAREB CTIMER_STMINTSTAT_COMPAREB_Msk +#define AM_HAL_STIMER_INT_COMPAREC CTIMER_STMINTSTAT_COMPAREC_Msk +#define AM_HAL_STIMER_INT_COMPARED CTIMER_STMINTSTAT_COMPARED_Msk +#define AM_HAL_STIMER_INT_COMPAREE CTIMER_STMINTSTAT_COMPAREE_Msk +#define AM_HAL_STIMER_INT_COMPAREF CTIMER_STMINTSTAT_COMPAREF_Msk +#define AM_HAL_STIMER_INT_COMPAREG CTIMER_STMINTSTAT_COMPAREG_Msk +#define AM_HAL_STIMER_INT_COMPAREH CTIMER_STMINTSTAT_COMPAREH_Msk + +#define AM_HAL_STIMER_INT_OVERFLOW CTIMER_STMINTSTAT_OVERFLOW_Msk + +#define AM_HAL_STIMER_INT_CAPTUREA CTIMER_STMINTSTAT_CAPTUREA_Msk +#define AM_HAL_STIMER_INT_CAPTUREB CTIMER_STMINTSTAT_CAPTUREB_Msk +#define AM_HAL_STIMER_INT_CAPTUREC CTIMER_STMINTSTAT_CAPTUREC_Msk +#define AM_HAL_STIMER_INT_CAPTURED CTIMER_STMINTSTAT_CAPTURED_Msk + +//! @} + +//***************************************************************************** +// +//! @name STimer Configuration Bits +//! @brief Interrupt Status Bits for enable/disble use +//! +//! These macros may be used to set and clear interrupt bits +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_CFG_THAW _VAL2FLD(CTIMER_STCFG_FREEZE, CTIMER_STCFG_FREEZE_THAW) +#define AM_HAL_STIMER_CFG_FREEZE _VAL2FLD(CTIMER_STCFG_FREEZE, CTIMER_STCFG_FREEZE_FREEZE) +#define AM_HAL_STIMER_CFG_RUN _VAL2FLD(CTIMER_STCFG_CLEAR, CTIMER_STCFG_CLEAR_RUN) +#define AM_HAL_STIMER_CFG_CLEAR _VAL2FLD(CTIMER_STCFG_CLEAR, CTIMER_STCFG_CLEAR_CLEAR) +#define AM_HAL_STIMER_CFG_COMPARE_A_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_A_EN, CTIMER_STCFG_COMPARE_A_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_B_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_B_EN, CTIMER_STCFG_COMPARE_B_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_C_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_C_EN, CTIMER_STCFG_COMPARE_C_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_D_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_D_EN, CTIMER_STCFG_COMPARE_D_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_E_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_E_EN, CTIMER_STCFG_COMPARE_E_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_F_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_F_EN, CTIMER_STCFG_COMPARE_F_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_G_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_G_EN, CTIMER_STCFG_COMPARE_G_EN_ENABLE) +#define AM_HAL_STIMER_CFG_COMPARE_H_ENABLE _VAL2FLD(CTIMER_STCFG_COMPARE_H_EN, CTIMER_STCFG_COMPARE_H_EN_ENABLE) + +//! @} + +//***************************************************************************** +// +//! @name Clock Configuration options +//! @brief STimer Configuration register options. +//! +//! These options are to be used with the am_hal_stimer_config() function. +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_NO_CLK _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_NOCLK) +#define AM_HAL_STIMER_HFRC_3MHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_HFRC_DIV16) +#define AM_HAL_STIMER_HFRC_187_5KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_HFRC_DIV256) +#define AM_HAL_STIMER_XTAL_32KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_XTAL_DIV1) +#define AM_HAL_STIMER_XTAL_16KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_XTAL_DIV2) +#define AM_HAL_STIMER_XTAL_1KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_XTAL_DIV32) +#define AM_HAL_STIMER_LFRC_1KHZ _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_LFRC_DIV1) +#define AM_HAL_STIMER_HFRC_CTIMER0A _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_CTIMER0A) +#define AM_HAL_STIMER_HFRC_CTIMER0B _VAL2FLD(CTIMER_STCFG_CLKSEL, CTIMER_STCFG_CLKSEL_CTIMER0B) +//! @} + + + +//***************************************************************************** +// +//! @name Capture Control Register options. +//! @brief Configuration options for capture control register. +//! +//! These options are to be used with the am_hal_stimer_capture_control_set +//! function. +//! @{ +// +//***************************************************************************** +#define AM_HAL_STIMER_CAPTURE0_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE0, CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE) +#define AM_HAL_STIMER_CAPTURE1_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE1, CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE) +#define AM_HAL_STIMER_CAPTURE2_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE2, CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE) +#define AM_HAL_STIMER_CAPTURE3_ENABLE _VAL2FLD(CTIMER_CAPTURECONTROL_CAPTURE3, CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE) + +//! @} + +//***************************************************************************** +// +//! Stimer configuration structure +// +//***************************************************************************** +typedef struct +{ + // + //! Configuration options for the STIMER + // + uint32_t ui32STimerConfig; +} +am_hal_stimer_config_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern uint32_t am_hal_stimer_config(uint32_t ui32STimerConfig); +extern uint32_t am_hal_stimer_counter_get(void); +extern void am_hal_stimer_counter_clear(void); +extern void am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, + uint32_t ui32Delta); +extern uint32_t am_hal_stimer_compare_get(uint32_t ui32CmprInstance); +extern void am_hal_stimer_capture_start(uint32_t ui32CaptureNum, + uint32_t ui32GPIONumber, + bool bPolarity); +extern void am_hal_stimer_capture_stop(uint32_t ui32CaptureNum); +extern uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum); +extern void am_hal_stimer_nvram_set(uint32_t ui32NvramNum, uint32_t ui32NvramVal); +extern uint32_t am_hal_stimer_nvram_get(uint32_t ui32NvramNum); +extern void am_hal_stimer_int_enable(uint32_t ui32Interrupt); +extern uint32_t am_hal_stimer_int_enable_get(void); +extern void am_hal_stimer_int_disable(uint32_t ui32Interrupt); +extern void am_hal_stimer_int_set(uint32_t ui32Interrupt); +extern void am_hal_stimer_int_clear(uint32_t ui32Interrupt); +extern uint32_t am_hal_stimer_int_status_get(bool bEnabledOnly); + + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_STIMER_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.c new file mode 100644 index 0000000000..57386de528 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.c @@ -0,0 +1,279 @@ +//***************************************************************************** +// +// am_hal_sysctrl.c +//! @file +//! +//! @brief Functions for interfacing with the M4F system control registers +//! +//! @addtogroup sysctrl3 System Control (SYSCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +// +// g_ui32BusWriteFlush is used by the macro, am_hal_sysctrl_bus_write_flush(). +// It is made global here to avoid compiler 'set but not used' warnings. +// +static volatile uint32_t g_ui32BusWriteFlush; + +//***************************************************************************** +// +//! @brief Place the core into sleep or deepsleep. +//! +//! @param bSleepDeep - False for Normal or True Deep sleep. +//! +//! This function puts the MCU to sleep or deepsleep depending on bSleepDeep. +//! +//! Valid values for bSleepDeep are: +//! +//! AM_HAL_SYSCTRL_SLEEP_NORMAL +//! AM_HAL_SYSCTRL_SLEEP_DEEP +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_sleep(bool bSleepDeep) +{ + // + // Disable interrupts and save the previous interrupt state. + // + AM_CRITICAL_BEGIN + + // + // If the user selected DEEPSLEEP and the TPIU is off, attempt to enter + // DEEP SLEEP. + // + if ( (bSleepDeep == AM_HAL_SYSCTRL_SLEEP_DEEP) && + (MCUCTRL->TPIUCTRL_b.ENABLE == MCUCTRL_TPIUCTRL_ENABLE_DIS) ) + { + + // + // Retrieve the reset generator status bits + // This gets reset on Deep Sleep, so we take a snapshot here + // + if (!gAmHalResetStatus) + { + gAmHalResetStatus = RSTGEN->STAT; + } + // + // Prepare the core for deepsleep (write 1 to the DEEPSLEEP bit). + // + SCB->SCR |= _VAL2FLD(SCB_SCR_SLEEPDEEP, 1); + } + else + { + // + // Prepare the core for normal sleep (write 0 to the DEEPSLEEP bit). + // + SCB->SCR &= ~_VAL2FLD(SCB_SCR_SLEEPDEEP, 1); + } + + // + // Before executing WFI, flush any buffered core and peripheral writes. + // + __DSB(); + am_hal_sysctrl_bus_write_flush(); + + // + // Execute the sleep instruction. + // + __WFI(); + + // + // Upon wake, execute the Instruction Sync Barrier instruction. + // + __ISB(); + + // + // Restore the interrupt state. + // + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Enable the floating point module. +//! +//! Call this function to enable the ARM hardware floating point module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_enable(void) +{ + // + // Enable access to the FPU in both privileged and user modes. + // NOTE: Write 0s to all reserved fields in this register. + // + SCB->CPACR = _VAL2FLD(SCB_CPACR_CP11, 0x3) | + _VAL2FLD(SCB_CPACR_CP10, 0x3); +} + +//***************************************************************************** +// +//! @brief Disable the floating point module. +//! +//! Call this function to disable the ARM hardware floating point module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_disable(void) +{ + // + // Disable access to the FPU in both privileged and user modes. + // NOTE: Write 0s to all reserved fields in this register. + // + SCB->CPACR = 0x00000000 & + ~(_VAL2FLD(SCB_CPACR_CP11, 0x3) | + _VAL2FLD(SCB_CPACR_CP10, 0x3)); +} + +//***************************************************************************** +// +//! @brief Enable stacking of FPU registers on exception entry. +//! +//! @param bLazy - Set to "true" to enable "lazy stacking". +//! +//! This function allows the core to save floating-point information to the +//! stack on exception entry. Setting the bLazy option enables "lazy stacking" +//! for interrupt handlers. Normally, mixing floating-point code and interrupt +//! driven routines causes increased interrupt latency, because the core must +//! save extra information to the stack upon exception entry. With the lazy +//! stacking option enabled, the core will skip the saving of floating-point +//! registers when possible, reducing average interrupt latency. +//! +//! @note At reset of the Cortex M4, the ASPEN and LSPEN bits are set to 1, +//! enabling Lazy mode by default. Therefore this function will generally +//! only have an affect when setting for full-context save (or when switching +//! from full-context to lazy mode). +//! +//! @note See also: +//! infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0298a/DAFGGBJD.html +//! +//! @note Three valid FPU context saving modes are possible. +//! 1. Lazy ASPEN=1 LSPEN=1 am_hal_sysctrl_fpu_stacking_enable(true) +//! and default. +//! 2. Full-context ASPEN=1 LSPEN=0 am_hal_sysctrl_fpu_stacking_enable(false) +//! 3. No FPU state ASPEN=0 LSPEN=0 am_hal_sysctrl_fpu_stacking_disable() +//! 4. Invalid ASPEN=0 LSPEN=1 +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_stacking_enable(bool bLazy) +{ + uint32_t ui32fpccr; + + // + // Set the requested FPU stacking mode in ISRs. + // + AM_CRITICAL_BEGIN +#define SYSCTRL_FPCCR_LAZY (FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk) + ui32fpccr = FPU->FPCCR; + ui32fpccr &= ~SYSCTRL_FPCCR_LAZY; + ui32fpccr |= (bLazy ? SYSCTRL_FPCCR_LAZY : FPU_FPCCR_ASPEN_Msk); + FPU->FPCCR = ui32fpccr; + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Disable FPU register stacking on exception entry. +//! +//! This function disables all stacking of floating point registers for +//! interrupt handlers. This mode should only be used when it is absolutely +//! known that no FPU instructions will be executed in an ISR. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_fpu_stacking_disable(void) +{ + // + // Completely disable FPU context save on entry to ISRs. + // + AM_CRITICAL_BEGIN + FPU->FPCCR &= ~SYSCTRL_FPCCR_LAZY; + AM_CRITICAL_END +} + +//***************************************************************************** +// +//! @brief Issue a system wide reset using the AIRCR bit in the M4 system ctrl. +//! +//! This function issues a system wide reset (Apollo POR level reset). +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_sysctrl_aircr_reset(void) +{ + // + // Set the system reset bit in the AIRCR register + // + __NVIC_SystemReset(); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.h new file mode 100644 index 0000000000..4e4910fc0d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_sysctrl.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// am_hal_sysctrl.h +//! @file +//! +//! @brief Functions for interfacing with the M4F system control registers +//! +//! @addtogroup sysctrl3 System Control (SYSCTRL) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_SYSCTRL_H +#define AM_HAL_SYSCTRL_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Definitions for sleep mode parameter +// +//***************************************************************************** +#define AM_HAL_SYSCTRL_SLEEP_DEEP true +#define AM_HAL_SYSCTRL_SLEEP_NORMAL false + +//***************************************************************************** +// +// Definition of Global Power State enumeration +// +//***************************************************************************** +typedef enum +{ + AM_HAL_SYSCTRL_WAKE, + AM_HAL_SYSCTRL_NORMALSLEEP, + AM_HAL_SYSCTRL_DEEPSLEEP +} am_hal_sysctrl_power_state_e; + +//***************************************************************************** +// +// Write flush - This function will hold the bus until all queued write +// operations have completed, thereby guaranteeing that all writes have +// been flushed. +// +//***************************************************************************** +#define SYNC_READ 0x5FFF0000 +#define am_hal_sysctrl_bus_write_flush() \ + if ( 1 ) \ + { \ + uint32_t *pui32Flush = (uint32_t*)SYNC_READ; \ + g_ui32BusWriteFlush = *pui32Flush; \ + } + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_sysctrl_sleep(bool bSleepDeep); +extern void am_hal_sysctrl_fpu_enable(void); +extern void am_hal_sysctrl_fpu_disable(void); +extern void am_hal_sysctrl_fpu_stacking_enable(bool bLazy); +extern void am_hal_sysctrl_fpu_stacking_disable(void); +extern void am_hal_sysctrl_aircr_reset(void); +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SYSCTRL_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.c new file mode 100644 index 0000000000..d03ddc8f51 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.c @@ -0,0 +1,351 @@ +//***************************************************************************** +// +// am_hal_systick.c +//! @file +//! +//! @brief Functions for interfacing with the SYSTICK +//! +//! @addtogroup systick3 System Timer (SYSTICK) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** +#define SYSTICK_MAX_TICKS ((1 << 24)-1) +#define MAX_U32 (0xffffffff) + +//***************************************************************************** +// +//! @brief Start the SYSTICK. +//! +//! This function starts the systick timer. +//! +//! @note This timer does not run in deep-sleep mode as it runs from the core +//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use +//! one of the ctimers instead. Also to note is this timer will consume higher +//! power than the ctimers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_start(void) +{ + // + // Start the systick timer. + // + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Stop the SYSTICK. +//! +//! This function stops the systick timer. +//! +//! @note This timer does not run in deep-sleep mode as it runs from the core +//! clock, which is gated in deep-sleep. If a timer is needed in deep-sleep use +//! one of the ctimers instead. Also to note is this timer will consume higher +//! power than the ctimers. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_stop(void) +{ + // + // Stop the systick timer. + // + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Enable the interrupt in the SYSTICK. +//! +//! This function enables the interupt in the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_int_enable(void) +{ + // + // Enable the systick timer interrupt. + // + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +//***************************************************************************** +// +//! @brief Disable the interrupt in the SYSTICK. +//! +//! This function disables the interupt in the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_int_disable(void) +{ + // + // Disable the systick timer interrupt. + // + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +//***************************************************************************** +// +//! @brief Reads the interrupt status. +//! +//! This function reads the interrupt status in the systick timer. +//! +//! @return the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_systick_int_status_get(void) +{ + // + // Return the systick timer interrupt status. + // + return SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk; +} + +//***************************************************************************** +// +//! @brief Reset the interrupt in the SYSTICK. +//! +//! This function resets the systick timer by clearing out the configuration +//! register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_reset(void) +{ + // + // Reset the systick timer interrupt. + // + SysTick->CTRL = 0x0; +} + +//***************************************************************************** +// +//! @brief Load the value into the SYSTICK. +//! +//! @param ui32LoadVal the desired load value for the systick. Maximum value is +//! 0x00FF.FFFF. +//! +//! This function loads the desired value into the systick timer. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_systick_load(uint32_t ui32LoadVal) +{ + // + // The proper SysTick initialization sequence is: (p 4-36 of the M4 UG). + // 1. Program reload value + // 2. Clear current value + // 3. Program CSR + // Write the given value to the reload register. + // Write the Current Value Register to clear it to 0. + // + SysTick->LOAD = ui32LoadVal; + SysTick->VAL = 0; +} + +//***************************************************************************** +// +//! @brief Get the current count value in the SYSTICK. +//! +//! This function gets the current count value in the systick timer. +//! +//! @return Current count value. +// +//***************************************************************************** +uint32_t +am_hal_systick_count(void) +{ + // + // Return the current systick timer count value. + // + return SysTick->VAL; +} + +//***************************************************************************** +// +//! @brief Wait the specified number of ticks. +//! +//! This function delays for the given number of SysTick ticks. +//! +//! @note If the SysTick timer is being used elsewhere, it will be corrupted +//! by calling this function. +//! +//! @return 0 if successful. +// +//***************************************************************************** +uint32_t +am_hal_systick_wait_ticks(uint32_t ui32Ticks) +{ + + if ( ui32Ticks == 0 ) + { + ui32Ticks++; // Make sure we get the COUNTFLAG + } + + // + // The proper SysTick initialization sequence is: (p 4-36 of the M4 UG). + // 1. Program reload value + // 2. Clear current value + // 3. Program CSR + // + // Set the reload value to the required number of ticks. + // + SysTick->LOAD = ui32Ticks; + + // + // Clear the current count. + // + SysTick->VAL = 0x0; + + // + // Set to use the processor clock, but don't cause an exception (we'll poll). + // + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; + + // + // Poll till done + // + while ( !(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) ); + + // + // And disable systick before exiting. + // + SysTick->CTRL = 0x0; + + return 0; +} + +//***************************************************************************** +// +//! @brief Delay the specified number of microseconds. +//! +//! This function will use the SysTick timer to delay until the specified +//! number of microseconds have elapsed. It uses the processor clocks and +//! takes into account the current CORESEL setting. +//! +//! @note If the SysTick timer is being used elsewhere, it will be corrupted +//! by calling this function. +//! +//! @return Total number of SysTick ticks delayed. +// +//***************************************************************************** +uint32_t +am_hal_systick_delay_us(uint32_t ui32NumUs) +{ + uint32_t ui32nLoops, ui32Ticks, uRet; + uint32_t ui32ClkFreq, ui32TicksPerMHz; + uint32_t ui32CoreSel = CLKGEN->CCTRL_b.CORESEL; + + ui32nLoops = 0; + if ( (ui32CoreSel <= AM_HAL_CLKGEN_CORESEL_MAXDIV) && (ui32NumUs >= 2) ) + { + // + // Determine clock freq, then whether we need more than 1 iteration. + // + ui32ClkFreq = AM_HAL_CLKGEN_FREQ_MAX_MHZ >> ui32CoreSel; + ui32ClkFreq <<= (am_hal_burst_mode_status() == AM_HAL_BURST_MODE)? 1 : 0; + + ui32TicksPerMHz = SYSTICK_MAX_TICKS / ui32ClkFreq; + if ( ui32NumUs > ui32TicksPerMHz ) + { + // + // Get number of required loops, as well as additional ticks. + // + ui32nLoops = ui32NumUs / ui32TicksPerMHz; + ui32NumUs = ui32NumUs % ui32TicksPerMHz; + } + + // + // Compute the number of ticks required. + // Allow for about 2us of call overhead. + // + ui32Ticks = (ui32NumUs - 2) * ui32ClkFreq; + } + else + { + ui32Ticks = 1; + } + + uRet = (ui32nLoops * SYSTICK_MAX_TICKS) + ui32Ticks; + while ( ui32nLoops ) + { + am_hal_systick_wait_ticks(SYSTICK_MAX_TICKS); + ui32nLoops--; + } + am_hal_systick_wait_ticks(ui32Ticks); + + return uRet; +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.h new file mode 100644 index 0000000000..0896e510e7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_systick.h @@ -0,0 +1,87 @@ +//***************************************************************************** +// +// am_hal_systick.h +//! @file +//! +//! @brief Functions for accessing and configuring the SYSTICK. +//! +//! @addtogroup systick3 System Timer (SYSTICK) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_SYSTICK_H +#define AM_HAL_SYSTICK_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_systick_start(void); +extern void am_hal_systick_stop(void); +extern void am_hal_systick_int_enable(void); +extern void am_hal_systick_int_disable(void); +extern uint32_t am_hal_systick_int_status_get(void); +extern void am_hal_systick_reset(void); +extern void am_hal_systick_load(uint32_t ui32LoadVal); +extern uint32_t am_hal_systick_count(void); +extern uint32_t am_hal_systick_wait_ticks(uint32_t u32Ticks); +extern uint32_t am_hal_systick_delay_us(uint32_t u32NumUs); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_SYSTICK_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.c new file mode 100644 index 0000000000..deb25325d5 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.c @@ -0,0 +1,394 @@ +//***************************************************************************** +// +// am_hal_tpiu.c +//! @file +//! +//! @brief Support functions for the ARM TPIU module +//! +//! Provides support functions for configuring the ARM TPIU module +//! +//! @addtogroup tpiu3 Trace Port Interface Unit (TPIU) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +//! @brief Enable the clock to the TPIU module. +//! +//! This function enables the clock to the TPIU module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_clock_enable(void) +{ + // + // Enable the TPIU clock + // + MCUCTRL->TPIUCTRL |= MCUCTRL_TPIUCTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Disable the clock to the TPIU module. +//! +//! This function disables the clock to the TPIU module. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_clock_disable(void) +{ + // + // Disable the TPIU clock + // + MCUCTRL->TPIUCTRL &= ~MCUCTRL_TPIUCTRL_ENABLE_Msk; +} + +//***************************************************************************** +// +//! @brief Set the output port width of the TPIU +//! +//! @param ui32PortWidth - The desired port width (in bits) +//! +//! This function uses the TPIU_CSPSR register to set the desired output port +//! width of the TPIU. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_port_width_set(uint32_t ui32PortWidth) +{ + TPI->CSPSR = 1 << (ui32PortWidth - 1); +} + +//***************************************************************************** +// +//! @brief Read the supported_output port width of the TPIU +//! +//! This function uses the \e TPIU_SSPSR register to set the supported output +//! port widths of the TPIU. +//! +//! @return Current width of the TPIU output port +// +//***************************************************************************** +uint32_t +am_hal_tpiu_supported_port_width_get(void) +{ + uint32_t i, ui32WidthValue; + + // + // Read the supported width register. + // + ui32WidthValue = TPI->SSPSR; + + // + // The register value is encoded in a one-hot format, so the position of + // the single set bit determines the actual width of the port. + // + for (i = 1; i < 32; i++) + { + // + // Check each bit for a '1'. When we find it, our current loop index + // will be equal to the port width. + // + if (ui32WidthValue == (0x1 << (i - 1))) + { + return i; + } + } + + // + // We should never get here, but if we do, just return the smallest + // possible value for a supported trace port width. + // + return 1; +} + +//***************************************************************************** +// +//! @brief Read the output port width of the TPIU +//! +//! This function uses the \e TPIU_CSPSR register to set the desired output +//! port width of the TPIU. +//! +//! @return Current width of the TPIU output port +// +//***************************************************************************** +uint32_t +am_hal_tpiu_port_width_get(void) +{ + uint32_t ui32Temp; + uint32_t ui32Width; + + ui32Width = 1; + ui32Temp = TPI->CSPSR; + + while ( !(ui32Temp & 1) ) + { + ui32Temp = ui32Temp >> 1; + ui32Width++; + + if (ui32Width > 32) + { + ui32Width = 0; + break; + } + } + + // + // Current width of the TPIU output port. + // + return ui32Width; +} + +//***************************************************************************** +// +//! @brief Configure the TPIU based on the values in the configuration struct. +//! +//! @param psConfig - pointer to an am_hal_tpiu_config_t structure containing +//! the desired configuration information. +//! +//! This function reads the provided configuration structure, and sets the +//! relevant TPIU registers to achieve the desired configuration. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig) +{ + // + // Set the clock freq in the MCUCTRL register. + // + MCUCTRL->TPIUCTRL |= psConfig->ui32TraceClkIn; + + // + // Set the desired protocol. + // + TPI->SPPR = psConfig->ui32PinProtocol; + + // + // Set the parallel port width. This may be redundant if the user has + // selected a serial protocol, but we'll set it anyway. + // + TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); + + // + // Set the clock prescaler. + // + TPI->ACPR = psConfig->ui32ClockPrescaler; +} + +//***************************************************************************** +// +//! @brief Enables the TPIU +//! +//! This function enables the ARM TPIU by setting the TPIU registers and then +//! enabling the TPIU clock source in MCU control register. +//! +//! @param psConfig - structure for configuration. +//! If ui32SetItmBaud, the other structure members are used to set the +//! TPIU configuration. +//! But for simplicity, ui32SetItmBaud can be set to one of the +//! following, in which case all other structure members are ignored. +//! In this case, the given BAUD rate is based on a div-by-8 HFRC clock. +//! AM_HAL_TPIU_BAUD_57600 +//! AM_HAL_TPIU_BAUD_115200 +//! AM_HAL_TPIU_BAUD_230400 +//! AM_HAL_TPIU_BAUD_460800 +//! AM_HAL_TPIU_BAUD_500000 +//! AM_HAL_TPIU_BAUD_1M +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) +{ + am_hal_clkgen_status_t sClkGenStatus; + uint32_t ui32HFRC, ui32SWOscaler, ui32ITMbitrate; + + ui32ITMbitrate = psConfig->ui32SetItmBaud; + + // + // TPIU formatter & flush control register. + // + TPI->FFCR = 0; + + if ( ui32ITMbitrate ) + { + // + // Set the Current Parallel Port Size (note - only 1 bit can be set). + // + TPI->CSPSR = TPI_CSPSR_CWIDTH_1BIT; + + // + // Use some default assumptions to set the ITM frequency. + // + if ( (ui32ITMbitrate < AM_HAL_TPIU_BAUD_57600 ) || + (ui32ITMbitrate > AM_HAL_TPIU_BAUD_2M ) ) + { + ui32ITMbitrate = AM_HAL_TPIU_BAUD_DEFAULT; + } + + // + // Get the current HFRC frequency. + // + am_hal_clkgen_status_get(&sClkGenStatus); + ui32HFRC = sClkGenStatus.ui32SysclkFreq; + + // + // Compute the SWO scaler value. + // + if ( ui32HFRC != 0xFFFFFFFF ) + { + ui32SWOscaler = ((ui32HFRC / 8) / ui32ITMbitrate) - 1; + } + else + { + ui32SWOscaler = ( (AM_HAL_CLKGEN_FREQ_MAX_HZ / 8) / + AM_HAL_TPIU_BAUD_DEFAULT ) - 1; + } + + // + // Set the scaler value. + // + TPI->ACPR = _VAL2FLD(TPI_ACPR_SWOSCALER, ui32SWOscaler); + + // + // Set for UART mode + // + TPI->SPPR = _VAL2FLD( TPI_SPPR_TXMODE, TPI_SPPR_TXMODE_UART); + + // + // Make sure we are not in test mode (important for proper deep sleep + // operation). + // + TPI->ITCTRL = _VAL2FLD(TPI_ITCTRL_Mode, TPI_ITCTRL_Mode_NORMAL); + + // + // Enable the TPIU clock source in MCU control. + // Set TPIU clock for HFRC/8 (6MHz) operation. + // + MCUCTRL->TPIUCTRL = + _VAL2FLD(MCUCTRL_TPIUCTRL_CLKSEL, MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8) | + _VAL2FLD(MCUCTRL_TPIUCTRL_ENABLE, MCUCTRL_TPIUCTRL_ENABLE_EN); + } + else + { + // + // Set the configuration according to the structure values. + // + + // + // Set the Asynchronous Clock Prescaler Register. + // + TPI->ACPR = psConfig->ui32ClockPrescaler; + + // + // Set the Selected Pin Protocol Register. + // e.g. AM_REG_TPIU_SPPR_TXMODE_UART + // + TPI->SPPR = psConfig->ui32PinProtocol; + + // + // Set the Current Parallel Port Size (note - only 1 bit can be set). + // This may be redundant if the user has selected a serial protocol, + // but we'll set it anyway. + // + TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); + + // + // Make sure we are not in test mode (important for proper deep sleep + // operation). + // + TPI->ITCTRL = _VAL2FLD(TPI_ITCTRL_Mode, TPI_ITCTRL_Mode_NORMAL); + + // + // Set the clock freq and enable fields in the MCUCTRL register. + // + MCUCTRL->TPIUCTRL = psConfig->ui32TraceClkIn; + } + + // + // Wait for 50us for the data to flush out. + // + am_hal_flash_delay(FLASH_CYCLES_US(50)); +} + +//***************************************************************************** +// +//! @brief Disables the TPIU +//! +//! This function disables the ARM TPIU by disabling the TPIU clock source +//! in MCU control register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_tpiu_disable(void) +{ + // + // Disable the TPIU clock source in MCU control. + // + MCUCTRL->TPIUCTRL = + _VAL2FLD(MCUCTRL_TPIUCTRL_CLKSEL, MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR) | + _VAL2FLD(MCUCTRL_TPIUCTRL_ENABLE, MCUCTRL_TPIUCTRL_ENABLE_DIS); +} + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.h new file mode 100644 index 0000000000..d3a9f37ce2 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_tpiu.h @@ -0,0 +1,198 @@ +//***************************************************************************** +// +// am_hal_tpiu.h +//! @file +//! +//! @brief Definitions and structures for working with the TPIU. +//! +//! @addtogroup tpiu3 Trace Port Interface Unit (TPIU) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_TPIU_H +#define AM_HAL_TPIU_H + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// TPIU bit rate defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_BAUD_57600 (115200 / 2) +#define AM_HAL_TPIU_BAUD_115200 (115200 * 1) +#define AM_HAL_TPIU_BAUD_230400 (115200 * 2) +#define AM_HAL_TPIU_BAUD_460800 (115200 * 4) +#define AM_HAL_TPIU_BAUD_250000 (1000000 / 4) +#define AM_HAL_TPIU_BAUD_500000 (1000000 / 2) +#define AM_HAL_TPIU_BAUD_1M (1000000 * 1) +#define AM_HAL_TPIU_BAUD_2M (1000000 * 2) +#define AM_HAL_TPIU_BAUD_DEFAULT (AM_HAL_TPIU_BAUD_1M) + +//***************************************************************************** +// +// TPIU register defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_SSPSR 0xE0040000 //! Supported Parallel Port Sizes +#define AM_HAL_TPIU_CSPSR 0xE0040004 //! Current Parallel Port Size +#define AM_HAL_TPIU_ACPR 0xE0040010 //! Asynchronous Clock Prescaler +#define AM_HAL_TPIU_SPPR 0xE00400F0 //! Selected Pin Protocol +#define AM_HAL_TPIU_TYPE 0xE0040FC8 //! TPIU Type + +//***************************************************************************** +// +// TPIU ACPR defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_ACPR_SWOSCALER_M 0x0000FFFF //! SWO baud rate prescalar + +//***************************************************************************** +// +// TPIU_SPPR TXMODE defines. +// +//***************************************************************************** +#define AM_HAL_TPIU_SPPR_PARALLEL 0x00000000 +#define AM_HAL_TPIU_SPPR_MANCHESTER 0x00000001 +#define AM_HAL_TPIU_SPPR_NRZ 0x00000002 + +//***************************************************************************** +// +// TPIU Type defines +// +//***************************************************************************** +#define AM_HAL_TPIU_TYPE_NRZVALID 0x00000800 +#define AM_HAL_TPIU_TYPE_MANCVALID 0x00000400 +#define AM_HAL_TPIU_TYPE_PTINVALID 0x00000200 +#define AM_HAL_TPIU_TYPE_FIFOSZ_M 0x000001C0 + +//***************************************************************************** +// +// TPIU Clock defines +// +//***************************************************************************** +#define AM_HAL_TPIU_TRACECLKIN_6MHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(0) +#define AM_HAL_TPIU_TRACECLKIN_3MHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(1) +#define AM_HAL_TPIU_TRACECLKIN_1_5MHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(2) +#define AM_HAL_TPIU_TRACECLKIN_750KHZ AM_REG_MCUCTRL_TPIUCTRL_CLKSEL(3) + +//***************************************************************************** +// +//! @brief Structure used for configuring the TPIU +// +//***************************************************************************** +typedef struct +{ + // + // If ui32SetItmBaud is non-zero, the ITM frequency is set to the given + // frequency, and is based on a divide-by-8 HFRC TPIU clock. + // If zero, other structure members are used to set the TPIU configuration. + // + uint32_t ui32SetItmBaud; + + // + //! MCU Control TRACECLKIN clock freq. + //! + //! Valid values for ui32TraceClkIn are: + //! + //! AM_HAL_TPIU_TRACECLKIN_6MHZ + //! AM_HAL_TPIU_TRACECLKIN_3MHZ + //! AM_HAL_TPIU_TRACECLKIN_1_5MHZ + //! AM_HAL_TPIU_TRACECLKIN_750KHZ + // + uint32_t ui32TraceClkIn; + + // + //! Protocol to use for the TPIU + //! + //! Valid values for ui32PinProtocol are: + //! + //! AM_HAL_TPIU_SPPR_PARALLEL + //! AM_HAL_TPIU_SPPR_MANCHESTER + //! AM_HAL_TPIU_SPPR_NRZ + // + uint32_t ui32PinProtocol; + + // + //! Desired width of the TPIU parallel port + // + uint32_t ui32ParallelPortSize; + + // + //! Desired Clock prescaler value + // + uint32_t ui32ClockPrescaler; +} +am_hal_tpiu_config_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_tpiu_clock_enable(void); +extern void am_hal_tpiu_clock_disable(void); +extern void am_hal_tpiu_port_width_set(uint32_t ui32PortWidth); +extern uint32_t am_hal_tpiu_supported_port_width_get(void); +extern uint32_t am_hal_tpiu_port_width_get(void); +extern void am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig); +extern void am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig); +extern void am_hal_tpiu_disable(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_TPIU_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.c new file mode 100644 index 0000000000..c141f368b8 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.c @@ -0,0 +1,1516 @@ +//***************************************************************************** +// +// am_hal_uart.c +//! @file +//! +//! @brief Functions for interfacing with the UART. +//! +//! @addtogroup uart3 UART +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// UART magic number for handle verification. +// +//***************************************************************************** +#define AM_HAL_MAGIC_UART 0xEA9E06 + +#define AM_HAL_UART_CHK_HANDLE(h) \ + ((h) && \ + ((am_hal_handle_prefix_t *)(h))->s.bInit && \ + (((am_hal_handle_prefix_t *)(h))->s.magic == AM_HAL_MAGIC_UART)) + +//***************************************************************************** +// +// Convenience macro for passing errors. +// +//***************************************************************************** +#define RETURN_ON_ERROR(x) \ + if ((x) != AM_HAL_STATUS_SUCCESS) \ + { \ + return (x); \ + }; + +//***************************************************************************** +// +// Baudrate to byte-time in microseconds with a little extra margin. +// +//***************************************************************************** +#define ONE_BYTE_US(baudrate) (12000000/(baudrate)) +#define ONE_BYTE_DELAY(handle) \ + am_hal_flash_delay(FLASH_CYCLES_US(ONE_BYTE_US((handle)->ui32BaudRate))) + +//***************************************************************************** +// +// Structure for handling UART register state information for power up/down +// +//***************************************************************************** +typedef struct +{ + bool bValid; + uint32_t regILPR; + uint32_t regIBRD; + uint32_t regFBRD; + uint32_t regLCRH; + uint32_t regCR; + uint32_t regIFLS; + uint32_t regIER; +} +am_hal_uart_register_state_t; + +//***************************************************************************** +// +// Structure for handling UART HAL state information. +// +//***************************************************************************** +typedef struct +{ + am_hal_handle_prefix_t prefix; + am_hal_uart_register_state_t sRegState; + + uint32_t ui32Module; + + bool bEnableTxQueue; + am_hal_queue_t sTxQueue; + + bool bEnableRxQueue; + am_hal_queue_t sRxQueue; + + uint32_t ui32BaudRate; +} +am_hal_uart_state_t; + +//***************************************************************************** +// +// State structure for each module. +// +//***************************************************************************** +am_hal_uart_state_t g_am_hal_uart_states[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// Prototypes for static functions. +// +//***************************************************************************** +static uint32_t config_baudrate(uint32_t ui32Module, uint32_t ui32Baudrate, uint32_t *ui32UartClkFreq); + +static uint32_t buffer_configure(void *pHandle, + uint8_t *pui8TxBuffer, + uint32_t ui32TxBufferSize, + uint8_t *pui8RxBuffer, + uint32_t ui32RxBufferSize); + +static uint32_t tx_queue_update(void *pHandle); +static uint32_t rx_queue_update(void *pHandle); + +static uint32_t uart_fifo_read(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead); + +static uint32_t uart_fifo_write(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten); + +//***************************************************************************** +// +// Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_uart_initialize(uint32_t ui32Module, void **ppHandle) +{ + // + // Check that the request module is in range. + // + if (ui32Module >= AM_REG_UART_NUM_MODULES ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + // + // Check for valid arguements. + // + if (!ppHandle) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Check if the handle is unallocated. + // + if (g_am_hal_uart_states[ui32Module].prefix.s.bInit) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Initialize the handle. + // + g_am_hal_uart_states[ui32Module].prefix.s.bInit = true; + g_am_hal_uart_states[ui32Module].prefix.s.magic = AM_HAL_MAGIC_UART; + g_am_hal_uart_states[ui32Module].ui32Module = ui32Module; + g_am_hal_uart_states[ui32Module].sRegState.bValid = false; + g_am_hal_uart_states[ui32Module].ui32BaudRate = 0; + + // + // Return the handle. + // + *ppHandle = (void *)&g_am_hal_uart_states[ui32Module]; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_initialize() + +//***************************************************************************** +// +// De-Initialization function. +// +//***************************************************************************** +uint32_t +am_hal_uart_deinitialize(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *)pHandle; + + // + // Check the handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Reset the handle. + // + pState->prefix.s.bInit = false; + pState->ui32Module = 0; + pState->sRegState.bValid = false; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_deinitialize() + +//***************************************************************************** +// +// Power control functions. +// +//***************************************************************************** +uint32_t +am_hal_uart_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + am_hal_pwrctrl_periph_e eUARTPowerModule = ((am_hal_pwrctrl_periph_e) + (AM_HAL_PWRCTRL_PERIPH_UART0 + + ui32Module)); + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Decode the requested power state and update UART operation accordingly. + // + switch (ePowerState) + { + // + // Turn on the UART. + // + case AM_HAL_SYSCTRL_WAKE: + // + // Make sure we don't try to restore an invalid state. + // + if (bRetainState && !pState->sRegState.bValid) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } + + // + // Enable power control. + // + am_hal_pwrctrl_periph_enable(eUARTPowerModule); + + if (bRetainState) + { + // + // Restore UART registers + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->ILPR = pState->sRegState.regILPR; + UARTn(ui32Module)->IBRD = pState->sRegState.regIBRD; + UARTn(ui32Module)->FBRD = pState->sRegState.regFBRD; + UARTn(ui32Module)->LCRH = pState->sRegState.regLCRH; + UARTn(ui32Module)->CR = pState->sRegState.regCR; + UARTn(ui32Module)->IFLS = pState->sRegState.regIFLS; + UARTn(ui32Module)->IER = pState->sRegState.regIER; + + pState->sRegState.bValid = false; + + AM_CRITICAL_END + } + break; + + // + // Turn off the UART. + // + case AM_HAL_SYSCTRL_NORMALSLEEP: + case AM_HAL_SYSCTRL_DEEPSLEEP: + if (bRetainState) + { + AM_CRITICAL_BEGIN + + pState->sRegState.regILPR = UARTn(ui32Module)->ILPR; + pState->sRegState.regIBRD = UARTn(ui32Module)->IBRD; + pState->sRegState.regFBRD = UARTn(ui32Module)->FBRD; + pState->sRegState.regLCRH = UARTn(ui32Module)->LCRH; + pState->sRegState.regCR = UARTn(ui32Module)->CR; + pState->sRegState.regIFLS = UARTn(ui32Module)->IFLS; + pState->sRegState.regIER = UARTn(ui32Module)->IER; + pState->sRegState.bValid = true; + + AM_CRITICAL_END + } + + // + // Clear all interrupts before sleeping as having a pending UART + // interrupt burns power. + // + am_hal_uart_interrupt_clear(pState, 0xFFFFFFFF); + + // + // Disable power control. + // + am_hal_pwrctrl_periph_disable(eUARTPowerModule); + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_power_control() + +//***************************************************************************** +// +// UART configuration. +// +//***************************************************************************** +uint32_t +am_hal_uart_configure(void *pHandle, const am_hal_uart_config_t *psConfig) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Reset the CR register to a known value. + // + UARTn(ui32Module)->CR = 0; + + // + // Start by enabling the clocks, which needs to happen in a critical + // section. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.CLKEN = 1; + UARTn(ui32Module)->CR_b.CLKSEL = UART0_CR_CLKSEL_24MHZ; + + AM_CRITICAL_END + + // + // Disable the UART. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 0; + UARTn(ui32Module)->CR_b.RXE = 0; + UARTn(ui32Module)->CR_b.TXE = 0; + + AM_CRITICAL_END + + // + // Set the baud rate. + // + ui32ErrorStatus = config_baudrate(ui32Module, psConfig->ui32BaudRate, + &(pState->ui32BaudRate)); + + RETURN_ON_ERROR(ui32ErrorStatus); + + // + // Copy the configuration options into the appropriate registers. + // + UARTn(ui32Module)->CR_b.RTSEN = 0; + UARTn(ui32Module)->CR_b.CTSEN = 0; + UARTn(ui32Module)->CR |= psConfig->ui32FlowControl; + + UARTn(ui32Module)->IFLS = psConfig->ui32FifoLevels; + + UARTn(ui32Module)->LCRH = (psConfig->ui32DataBits | + psConfig->ui32Parity | + psConfig->ui32StopBits | + AM_HAL_UART_FIFO_ENABLE); + + // + // Enable the UART, RX, and TX. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 1; + UARTn(ui32Module)->CR_b.RXE = 1; + UARTn(ui32Module)->CR_b.TXE = 1; + + AM_CRITICAL_END + + // + // Set up any buffers that might exist. + // + buffer_configure(pHandle, + psConfig->pui8TxBuffer, + psConfig->ui32TxBufferSize, + psConfig->pui8RxBuffer, + psConfig->ui32RxBufferSize); + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_configure() + +uint32_t +am_hal_uart_configure_fifo(void *pHandle, const am_hal_uart_config_t *psConfig, bool bEnableFIFO) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Reset the CR register to a known value. + // + UARTn(ui32Module)->CR = 0; + + // + // Start by enabling the clocks, which needs to happen in a critical + // section. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.CLKEN = 1; + UARTn(ui32Module)->CR_b.CLKSEL = UART0_CR_CLKSEL_24MHZ; + + AM_CRITICAL_END + + // + // Disable the UART. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 0; + UARTn(ui32Module)->CR_b.RXE = 0; + UARTn(ui32Module)->CR_b.TXE = 0; + + AM_CRITICAL_END + + // + // Set the baud rate. + // + ui32ErrorStatus = config_baudrate(ui32Module, psConfig->ui32BaudRate, + &(pState->ui32BaudRate)); + + RETURN_ON_ERROR(ui32ErrorStatus); + + // + // Copy the configuration options into the appropriate registers. + // + UARTn(ui32Module)->CR_b.RTSEN = 0; + UARTn(ui32Module)->CR_b.CTSEN = 0; + UARTn(ui32Module)->CR |= psConfig->ui32FlowControl; + + UARTn(ui32Module)->IFLS = psConfig->ui32FifoLevels; + + UARTn(ui32Module)->LCRH = (psConfig->ui32DataBits | + psConfig->ui32Parity | + psConfig->ui32StopBits | + ((bEnableFIFO) ? AM_HAL_UART_FIFO_ENABLE : AM_HAL_UART_FIFO_DISABLE)); + + // + // Enable the UART, RX, and TX. + // + AM_CRITICAL_BEGIN + + UARTn(ui32Module)->CR_b.UARTEN = 1; + UARTn(ui32Module)->CR_b.RXE = 1; + UARTn(ui32Module)->CR_b.TXE = 1; + + AM_CRITICAL_END + + if(bEnableFIFO){ + // + // Set up any buffers that might exist. + // + buffer_configure(pHandle, + psConfig->pui8TxBuffer, + psConfig->ui32TxBufferSize, + psConfig->pui8RxBuffer, + psConfig->ui32RxBufferSize); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_configure_fifo() + +//***************************************************************************** +// +// Allows the UART HAL to use extra space to store TX and RX data. +// +//***************************************************************************** +static uint32_t +buffer_configure(void *pHandle, uint8_t *pui8TxBuffer, uint32_t ui32TxBufferSize, + uint8_t *pui8RxBuffer, uint32_t ui32RxBufferSize) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32ErrorStatus; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if we have a TX buffer. + // + if (pui8TxBuffer && ui32TxBufferSize) + { + // + // If so, initialzie the transmit queue, and enable the TX FIFO + // interrupt. + // + pState->bEnableTxQueue = true; + am_hal_queue_init(&pState->sTxQueue, pui8TxBuffer, 1, ui32TxBufferSize); + ui32ErrorStatus = am_hal_uart_interrupt_enable(pHandle, AM_HAL_UART_INT_TX); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If not, make sure the TX FIFO interrupt is disabled. + // + pState->bEnableTxQueue = false; + ui32ErrorStatus = am_hal_uart_interrupt_disable(pHandle, AM_HAL_UART_INT_TX); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if we have an RX buffer. + // + if (pui8RxBuffer && ui32RxBufferSize) + { + // + // If so, initialize the receive queue and the associated interupts. + // + pState->bEnableRxQueue = true; + am_hal_queue_init(&pState->sRxQueue, pui8RxBuffer, 1, ui32RxBufferSize); + ui32ErrorStatus = am_hal_uart_interrupt_enable(pHandle, (AM_HAL_UART_INT_RX | + AM_HAL_UART_INT_RX_TMOUT)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + pState->bEnableRxQueue = false; + ui32ErrorStatus = am_hal_uart_interrupt_disable(pHandle, (AM_HAL_UART_INT_RX | + AM_HAL_UART_INT_RX_TMOUT)); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + return AM_HAL_STATUS_SUCCESS; +} // buffer_configure() + +//***************************************************************************** +// +// Set Baud Rate based on the UART clock frequency. +// +//***************************************************************************** +#define BAUDCLK (16) // Number of UART clocks needed per bit. +static uint32_t +config_baudrate(uint32_t ui32Module, uint32_t ui32DesiredBaudrate, uint32_t *pui32ActualBaud) +{ + uint64_t ui64FractionDivisorLong; + uint64_t ui64IntermediateLong; + uint32_t ui32IntegerDivisor; + uint32_t ui32FractionDivisor; + uint32_t ui32BaudClk; + uint32_t ui32UartClkFreq; + + // + // Check that the baudrate is in range. + // + if (APOLLO3_A1) + { + if (ui32DesiredBaudrate > AM_HAL_UART_MAXIMUM_BAUDRATE_A1) + { + return AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE; + } + } + if (APOLLO3_GE_B0) + { + if (ui32DesiredBaudrate > AM_HAL_UART_MAXIMUM_BAUDRATE_B0) + { + return AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE; + } + } + + switch ( UARTn(ui32Module)->CR_b.CLKSEL ) + { + case UART0_CR_CLKSEL_24MHZ: + ui32UartClkFreq = 24000000; + break; + + case UART0_CR_CLKSEL_12MHZ: + ui32UartClkFreq = 12000000; + break; + + case UART0_CR_CLKSEL_6MHZ: + ui32UartClkFreq = 6000000; + break; + + case UART0_CR_CLKSEL_3MHZ: + ui32UartClkFreq = 3000000; + break; + + default: + *pui32ActualBaud = 0; + return AM_HAL_UART_STATUS_CLOCK_NOT_CONFIGURED; + } + + // + // Calculate register values. + // + ui32BaudClk = BAUDCLK * ui32DesiredBaudrate; + ui32IntegerDivisor = (uint32_t)(ui32UartClkFreq / ui32BaudClk); + ui64IntermediateLong = (ui32UartClkFreq * 64) / ui32BaudClk; + ui64FractionDivisorLong = ui64IntermediateLong - (ui32IntegerDivisor * 64); + ui32FractionDivisor = (uint32_t)ui64FractionDivisorLong; + + // + // Check the result. + // + if (ui32IntegerDivisor == 0) + { + *pui32ActualBaud = 0; + return AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE; + } + + // + // Write the UART regs. + // + // TODO: Is this double-write of IBRD really intended? + UARTn(ui32Module)->IBRD = ui32IntegerDivisor; + UARTn(ui32Module)->IBRD = ui32IntegerDivisor; + UARTn(ui32Module)->FBRD = ui32FractionDivisor; + + // + // Return the actual baud rate. + // + *pui32ActualBaud = (ui32UartClkFreq / ((BAUDCLK * ui32IntegerDivisor) + ui32FractionDivisor / 4)); + return AM_HAL_STATUS_SUCCESS; +} // config_baudrate() + +//***************************************************************************** +// +// Read as much data from the UART FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +static uint32_t +uart_fifo_read(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + uint32_t i = 0; + uint32_t ui32ReadData; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Start a loop where we attempt to read everything requested. + // + while (i < ui32NumBytes) + { + // + // If the fifo is empty, return with the number of bytes we read. + // Otherwise, read the data into the provided buffer. + // + if ( UARTn(ui32Module)->FR_b.RXFE ) + { + break; + } + else + { + ui32ReadData = UARTn(ui32Module)->DR; + + // + // If error bits are set, we need to alert the caller. + // + if (ui32ReadData & (_VAL2FLD(UART0_DR_OEDATA, UART0_DR_OEDATA_ERR) | + _VAL2FLD(UART0_DR_BEDATA, UART0_DR_BEDATA_ERR) | + _VAL2FLD(UART0_DR_PEDATA, UART0_DR_PEDATA_ERR) | + _VAL2FLD(UART0_DR_FEDATA, UART0_DR_FEDATA_ERR)) ) + { + ui32ErrorStatus = AM_HAL_UART_STATUS_BUS_ERROR; + break; + } + else + { + pui8Data[i++] = ui32ReadData & 0xFF; + } + } + } + + if (pui32NumBytesRead) + { + *pui32NumBytesRead = i; + } + + return ui32ErrorStatus; +} // uart_fifo_read() + +//***************************************************************************** +// +// Read as much data from the UART FIFO as possible, up to ui32NumBytes +// +//***************************************************************************** +static uint32_t +uart_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + uint32_t i = 0; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Start a loop where we attempt to write everything requested. + // + while (i < ui32NumBytes) + { + // + // If the TX FIFO is full, break out of the loop. We've sent everything + // we can. + // + if ( UARTn(ui32Module)->FR_b.TXFF ) + { + break; + } + else + { + UARTn(ui32Module)->DR = pui8Data[i++]; + } + } + + // + // Let the caller know how much we sent. + // + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // uart_fifo_write() + +//***************************************************************************** +// +// Attempt to read N bytes from the FIFO, but give up if they aren't there. +// +//***************************************************************************** +static uint32_t +read_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + uint32_t ui32BufferData; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Start by setting the number of bytes read to 0. + // + if (pui32NumBytesRead) + { + *pui32NumBytesRead = 0; + } + + if (ui32NumBytes == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular receive buffer has been enabled. + // + if (pState->bEnableRxQueue) + { + // + // If it is, update it, and then try to read the requested number of + // bytes, giving up if fewer were actually found. + // + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + + ui32BufferData = am_hal_queue_data_left(&pState->sRxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferData ? + ui32NumBytes : ui32BufferData); + + am_hal_queue_item_get(&pState->sRxQueue, pui8Data, ui32BytesTransferred); + } + else + { + // + // If the buffer isn't enabled, just read straight from the FIFO. + // + ui32ErrorStatus = uart_fifo_read(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + if (pui32NumBytesRead) + { + *pui32NumBytesRead = ui32BytesTransferred; + } + + return ui32ErrorStatus; +} // read_nonblocking() + +//***************************************************************************** +// +// Attempt to write N bytes to the FIFO, but give up if there's no space. +// +//***************************************************************************** +static uint32_t +write_nonblocking(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + uint32_t ui32ErrorStatus; + uint32_t ui32BufferSpace; + uint32_t ui32BytesTransferred; + + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + + // + // Check to make sure this is a valid handle. + // + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = 0; + } + + if (ui32NumBytes == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if the circular transmit buffer has been enabled. + // + if (pState->bEnableTxQueue) + { + // + // If it has, been enabled, write as much data to it as we can, and let + // the caller know how much that was. + // + ui32BufferSpace = am_hal_queue_space_left(&pState->sTxQueue); + + ui32BytesTransferred = (ui32NumBytes < ui32BufferSpace ? + ui32NumBytes : ui32BufferSpace); + + am_hal_queue_item_add(&pState->sTxQueue, pui8Data, ui32BytesTransferred); + + // + // Transfer as much data as possible from the queue to the fifo. + // + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + else + { + // + // If the buffer isn't enabled, just write straight to the FIFO. + // + uart_fifo_write(pHandle, pui8Data, ui32NumBytes, + &ui32BytesTransferred); + } + + // + // Let the caller know how much we transferred if they provided us with a + // pointer. + // + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = ui32BytesTransferred; + } + + return AM_HAL_STATUS_SUCCESS; +} // write_nonblocking() + +//***************************************************************************** +// +// This function will keep reading bytes until it either gets N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +read_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesRead, ui32RemainingBytes, + ui32TimeSpent, i; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if (ui32TimeoutMs == 0) + { + return read_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesRead); + } + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // Loop until we're done reading. This will either be because we hit a + // timeout, or we got the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while (ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs)) + { + // + // Read as much as we can. + // + ui32BytesRead = 0; + ui32Status = read_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesRead); + // + // Update the tracking variables. + // + i += ui32BytesRead; + ui32RemainingBytes -= ui32BytesRead; + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + if (pui32NumBytesRead) + { + *pui32NumBytesRead = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if (ui32RemainingBytes) + { + am_hal_flash_delay(FLASH_CYCLES_US(1)); + + if (ui32TimeoutMs != AM_HAL_UART_WAIT_FOREVER) + { + ui32TimeSpent++; + } + } + } + + if (pui32NumBytesRead) + { + *pui32NumBytesRead = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // read_timeout() + +//***************************************************************************** +// +// This function will keep writing bytes until it either sends N bytes or runs +// into an error. +// +//***************************************************************************** +static uint32_t +write_timeout(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten, uint32_t ui32TimeoutMs) +{ + uint32_t ui32Status, ui32BytesWritten, ui32RemainingBytes, + ui32TimeSpent, i; + + i = 0; + ui32RemainingBytes = ui32NumBytes; + ui32TimeSpent = 0; + + // + // If we don't have a timeout, just pass this directly to the nonblocking + // call. + // + if (ui32TimeoutMs == 0) + { + return write_nonblocking(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesWritten); + } + + // + // Loop until we're done write. This will either be because we hit a + // timeout, or we sent the right number of bytes. If the caller specified + // "wait forever", then don't check the timeout. + // + while (ui32RemainingBytes && (ui32TimeSpent < ui32TimeoutMs)) + { + // + // Write as much as we can. + // + ui32BytesWritten = 0; + ui32Status = write_nonblocking(pHandle, &pui8Data[i], + ui32RemainingBytes, + &ui32BytesWritten); + // + // Update the tracking variables. + // + i += ui32BytesWritten; + ui32RemainingBytes -= ui32BytesWritten; + + if (ui32Status != AM_HAL_STATUS_SUCCESS) + { + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = i; + } + + return ui32Status; + } + + // + // Update the timeout. + // + if (ui32RemainingBytes) + { + am_hal_flash_delay(FLASH_CYCLES_US(1)); + + if (ui32TimeoutMs != AM_HAL_UART_WAIT_FOREVER) + { + ui32TimeSpent++; + } + } + } + + if (pui32NumBytesWritten) + { + *pui32NumBytesWritten = i; + } + + return AM_HAL_STATUS_SUCCESS; +} // write_timeout() + +//***************************************************************************** +// +// Send or receive bytes. +// +//***************************************************************************** +uint32_t +am_hal_uart_transfer(void *pHandle, const am_hal_uart_transfer_t *pTransfer) +{ + // + // Pick the right function to use based on the transfer structure. + // + if (pTransfer->ui32Direction == AM_HAL_UART_WRITE) + { + return write_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + else if (pTransfer->ui32Direction == AM_HAL_UART_READ) + { + return read_timeout(pHandle, + pTransfer->pui8Data, + pTransfer->ui32NumBytes, + pTransfer->pui32BytesTransferred, + pTransfer->ui32TimeoutMs); + } + + return AM_HAL_STATUS_INVALID_OPERATION; +} // am_hal_uart_transfer() + +//***************************************************************************** +// +// Wait for all of the traffic in the TX pipeline to be sent. +// +//***************************************************************************** +uint32_t +am_hal_uart_tx_flush(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // If we have a TX queue, we should wait for it to empty. + // + if (pState->bEnableTxQueue) + { + while (am_hal_queue_data_left(&(pState->sTxQueue))) + { + ONE_BYTE_DELAY(pState); + } + } + + // + // Wait for the TX busy bit to go low. + // + while ( UARTn(ui32Module)->FR_b.BUSY ) + { + ONE_BYTE_DELAY(pState); + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_tx_flush() + +//***************************************************************************** +// +// Return the most recent set of UART flags. +// +//***************************************************************************** +uint32_t +am_hal_uart_flags_get(void *pHandle, uint32_t *pui32Flags) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + // + // Check to make sure this is a valid handle. + // + if ( !AM_HAL_UART_CHK_HANDLE(pHandle) ) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + if ( pui32Flags ) + { + // + // Set the flags value, then return success. + // + *pui32Flags = UARTn(ui32Module)->FR; + + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + +} // am_hal_uart_flags_get() + +//***************************************************************************** +// +// Empty the UART RX FIFO, and place the data into the RX queue. +// +//***************************************************************************** +static uint32_t +rx_queue_update(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + + uint8_t pui8Data[AM_HAL_UART_FIFO_MAX]; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus; + + AM_CRITICAL_BEGIN + + // + // Read as much of the FIFO as we can. + // + ui32ErrorStatus = uart_fifo_read(pHandle, pui8Data, AM_HAL_UART_FIFO_MAX, + &ui32BytesTransferred); + // + // If we were successful, go ahead and transfer the data along to the + // buffer. + // + if (ui32ErrorStatus == AM_HAL_STATUS_SUCCESS) + { + if (!am_hal_queue_item_add(&pState->sRxQueue, pui8Data, + ui32BytesTransferred)) + { + ui32ErrorStatus = AM_HAL_UART_STATUS_RX_QUEUE_FULL; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // rx_queue_update() + +//***************************************************************************** +// +// Transfer as much data as possible from the TX queue to the TX FIFO. +// +//***************************************************************************** +static uint32_t +tx_queue_update(void *pHandle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + uint8_t pui8Data; + uint32_t ui32BytesTransferred; + uint32_t ui32ErrorStatus = AM_HAL_STATUS_SUCCESS; + + AM_CRITICAL_BEGIN + + // + // Loop as long as the TX fifo isn't full yet. + // + while ( !UARTn(ui32Module)->FR_b.TXFF ) + { + // + // Attempt to grab an item from the queue, and add it to the fifo. + // + if (am_hal_queue_item_get(&pState->sTxQueue, &pui8Data, 1)) + { + ui32ErrorStatus = uart_fifo_write(pHandle, &pui8Data, 1, + &ui32BytesTransferred); + + if (ui32ErrorStatus != AM_HAL_STATUS_SUCCESS) + { + break; + } + } + else + { + // + // If we didn't get anything from the FIFO, we can just return. + // + break; + } + } + + AM_CRITICAL_END + + return ui32ErrorStatus; +} // tx_queue_update() + +//***************************************************************************** +// +// UART FIFO Read. +// +//***************************************************************************** +uint32_t +am_hal_uart_fifo_read(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + return uart_fifo_read(pHandle, pui8Data, ui32NumBytes, pui32NumBytesRead); +} + +//***************************************************************************** +// +// UART FIFO Write. +// +//***************************************************************************** +uint32_t +am_hal_uart_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + return uart_fifo_write(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesWritten); +} + +//***************************************************************************** +// +// Interrupt service +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_service(void *pHandle, uint32_t ui32Status, + uint32_t *pui32UartTxIdle) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + uint32_t ui32ErrorStatus; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // Check to see if we have filled the Rx FIFO past the configured limit, or + // if we have an 'old' character or two sitting in the FIFO. + // + if ((ui32Status & (UART0_IES_RXRIS_Msk | UART0_IES_RTRIS_Msk)) && + pState->bEnableRxQueue) + { + ui32ErrorStatus = rx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // Check to see if our TX buffer has been recently emptied. If so, we + // should refill it from the TX ring buffer. + // + if ((ui32Status & UART0_IES_TXRIS_Msk) && pState->bEnableTxQueue) + { + ui32ErrorStatus = tx_queue_update(pHandle); + RETURN_ON_ERROR(ui32ErrorStatus); + } + + // + // If this pointer is null, we can just return success now. There is no + // need to figure out if the UARt is idle. + // + if (pui32UartTxIdle == 0) + { + return AM_HAL_STATUS_SUCCESS; + } + + // + // Check to see if we should report the UART TX-side idle. This is true if + // the queue is empty and the BUSY bit is low. The check is complicated + // because we don't want to check the queue status unless queues have been + // configured. + // + if (pState->bEnableTxQueue) + { + if ( am_hal_queue_empty(&(pState->sTxQueue) ) && + ( UARTn(ui32Module)->FR_b.BUSY == false ) ) + { + *pui32UartTxIdle = true; + } + } + else if ( UARTn(ui32Module)->FR_b.BUSY == false ) + { + *pui32UartTxIdle = true; + } + else + { + *pui32UartTxIdle = false; + } + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_service() + +//***************************************************************************** +// +// Interrupt enable. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_enable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + UARTn(ui32Module)->IER |= ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_enable() + +//***************************************************************************** +// +// Interrupt disable. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_disable(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + UARTn(ui32Module)->IER &= ~ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_disable() + +//***************************************************************************** +// +// Interrupt clear. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_clear(void *pHandle, uint32_t ui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + UARTn(ui32Module)->IEC = ui32IntMask; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_clear() + +//***************************************************************************** +// +// Returns the interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEnabledOnly) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + // + // If requested, only return the interrupts that are enabled. + // + *pui32Status = bEnabledOnly ? UARTn(ui32Module)->MIS : UARTn(ui32Module)->IES; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_status_get() + +//***************************************************************************** +// +// Return the set of enabled interrupts. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_enable_get(void *pHandle, uint32_t *pui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + *pui32IntMask = UARTn(ui32Module)->IER; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_enable_get() diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.h new file mode 100644 index 0000000000..519a89b277 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_uart.h @@ -0,0 +1,724 @@ +//***************************************************************************** +// +// am_hal_uart.h +//! @file +//! +//! @brief Functions for accessing and configuring the UART. +//! +//! @addtogroup uart3 UART +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_UART_H +#define AM_HAL_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// CMSIS-style macro for handling a variable MSPI module number. +// +#define UARTn(n) ((UART0_Type*)(UART0_BASE + (n * (UART1_BASE - UART0_BASE)))) +//***************************************************************************** + +//***************************************************************************** +// +// UART configuration options. +// +//***************************************************************************** +typedef struct +{ + // + // Standard UART options. + // + uint32_t ui32BaudRate; + uint32_t ui32DataBits; + uint32_t ui32Parity; + uint32_t ui32StopBits; + uint32_t ui32FlowControl; + + // + // Additional options. + // + uint32_t ui32FifoLevels; + + // + // Buffers + // + uint8_t *pui8TxBuffer; + uint32_t ui32TxBufferSize; + uint8_t *pui8RxBuffer; + uint32_t ui32RxBufferSize; +} +am_hal_uart_config_t; + +//***************************************************************************** +// +// @brief UART transfer structure. +// +// This structure describes a UART transaction that can be performed by \e +// am_hal_uart_transfer() +// +//***************************************************************************** +typedef struct +{ + //! Determines whether data should be read or written. + //! + //! Should be either AM_HAL_UART_WRITE or AM_HAL_UART_READ + uint32_t ui32Direction; + + //! Pointer to data to be sent, or space to fill with received data. + uint8_t *pui8Data; + + //! Number of bytes to send or receive. + uint32_t ui32NumBytes; + + //! Timeout in milliseconds. + //! + //! Given a timeout value, the \e am_hal_uart_transfer() function will keep + //! trying to transfer data until either the number of bytes is satisfied, + //! or the time runs out. If provided with a value of zero, the transfer + //! function will only send as much data as it can immediately deal with. + //! If provided with a timeout value of \e AM_HAL_UART_WAIT_FOREVER, the + //! function will block until either the final "read" byte is received or + //! the final "write" byte is placed in the output buffer. + uint32_t ui32TimeoutMs; + + //! Number of bytes successfully transferred. + uint32_t *pui32BytesTransferred; +} +am_hal_uart_transfer_t; + +//***************************************************************************** +// +// Maximum baudrate supported is 921600 for Apollo3-A1 and 1.5Mbaud for +// Apollo3-B0. +// +//***************************************************************************** +#define AM_HAL_UART_MAXIMUM_BAUDRATE_A1 921600 +#define AM_HAL_UART_MAXIMUM_BAUDRATE_B0 1500000 + +//***************************************************************************** +// +// Uart transfer options. +// +//***************************************************************************** +#define AM_HAL_UART_WRITE 0 +#define AM_HAL_UART_READ 1 +#define AM_HAL_UART_WAIT_FOREVER 0xFFFFFFFF + +//***************************************************************************** +// +// UART conficuration option values. +// +//***************************************************************************** + +// Data bits. +#define AM_HAL_UART_DATA_BITS_8 (_VAL2FLD(UART0_LCRH_WLEN, 3)) +#define AM_HAL_UART_DATA_BITS_7 (_VAL2FLD(UART0_LCRH_WLEN, 2)) +#define AM_HAL_UART_DATA_BITS_6 (_VAL2FLD(UART0_LCRH_WLEN, 1)) +#define AM_HAL_UART_DATA_BITS_5 (_VAL2FLD(UART0_LCRH_WLEN, 0)) + +// Parity. +#define AM_HAL_UART_PARITY_NONE 0 +#define AM_HAL_UART_PARITY_ODD UART0_LCRH_PEN_Msk +#define AM_HAL_UART_PARITY_EVEN (UART0_LCRH_PEN_Msk | \ + UART0_LCRH_EPS_Msk) +// Stop Bits +#define AM_HAL_UART_ONE_STOP_BIT (_VAL2FLD(UART0_LCRH_STP2, 0)) +#define AM_HAL_UART_TWO_STOP_BITS (_VAL2FLD(UART0_LCRH_STP2, 1)) + +// Flow control +#define AM_HAL_UART_FLOW_CTRL_NONE 0 +#define AM_HAL_UART_FLOW_CTRL_CTS_ONLY UART0_CR_CTSEN_Msk +#define AM_HAL_UART_FLOW_CTRL_RTS_ONLY UART0_CR_RTSEN_Msk +#define AM_HAL_UART_FLOW_CTRL_RTS_CTS (UART0_CR_CTSEN_Msk | \ + UART0_CR_RTSEN_Msk) +// FIFO enable/disable. +#define AM_HAL_UART_FIFO_ENABLE (_VAL2FLD(UART0_LCRH_FEN, 1)) +#define AM_HAL_UART_FIFO_DISABLE (_VAL2FLD(UART0_LCRH_FEN, 0)) + +// TX FIFO interrupt level settings. +#define AM_HAL_UART_TX_FIFO_1_8 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 0)) +#define AM_HAL_UART_TX_FIFO_1_4 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 1)) +#define AM_HAL_UART_TX_FIFO_1_2 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 2)) +#define AM_HAL_UART_TX_FIFO_3_4 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 3)) +#define AM_HAL_UART_TX_FIFO_7_8 (_VAL2FLD(UART0_IFLS_TXIFLSEL, 4)) + +// RX FIFO interrupt level settings. +#define AM_HAL_UART_RX_FIFO_1_8 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 0)) +#define AM_HAL_UART_RX_FIFO_1_4 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 1)) +#define AM_HAL_UART_RX_FIFO_1_2 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 2)) +#define AM_HAL_UART_RX_FIFO_3_4 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 3)) +#define AM_HAL_UART_RX_FIFO_7_8 (_VAL2FLD(UART0_IFLS_RXIFLSEL, 4)) + +//***************************************************************************** +// +// UART interrupts. +// +//***************************************************************************** +#define AM_HAL_UART_INT_OVER_RUN UART0_IER_OEIM_Msk +#define AM_HAL_UART_INT_BREAK_ERR UART0_IER_BEIM_Msk +#define AM_HAL_UART_INT_PARITY_ERR UART0_IER_PEIM_Msk +#define AM_HAL_UART_INT_FRAME_ERR UART0_IER_FEIM_Msk +#define AM_HAL_UART_INT_RX_TMOUT UART0_IER_RTIM_Msk +#define AM_HAL_UART_INT_TX UART0_IER_TXIM_Msk +#define AM_HAL_UART_INT_RX UART0_IER_RXIM_Msk +#define AM_HAL_UART_INT_DSRM UART0_IER_DSRMIM_Msk +#define AM_HAL_UART_INT_DCDM UART0_IER_DCDMIM_Msk +#define AM_HAL_UART_INT_CTSM UART0_IER_CTSMIM_Msk +#define AM_HAL_UART_INT_TXCMP UART0_IER_TXCMPMIM_Msk + +//***************************************************************************** +// +//! @name UART Flag Register +//! @brief Macro definitions for UART Flag Register Bits. +//! +//! They may be used with the \e am_hal_uart_flags_get() function. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_UART_FR_TX_EMPTY (_VAL2FLD(UART0_FR_TXFE, UART0_FR_TXFE_XMTFIFO_EMPTY)) +#define AM_HAL_UART_FR_RX_FULL (_VAL2FLD(UART0_FR_RXFF, UART0_FR_RXFF_RCVFIFO_FULL)) +#define AM_HAL_UART_FR_TX_FULL (_VAL2FLD(UART0_FR_TXFF, UART0_FR_TXFF_XMTFIFO_FULL)) +#define AM_HAL_UART_FR_RX_EMPTY (_VAL2FLD(UART0_FR_RXFE, UART0_FR_RXFE_RCVFIFO_EMPTY)) +#define AM_HAL_UART_FR_BUSY (_VAL2FLD(UART0_FR_BUSY, UART0_FR_BUSY_BUSY)) +#define AM_HAL_UART_FR_DCD_DETECTED (_VAL2FLD(UART0_FR_DCD, UART0_FR_DCD_DETECTED)) +#define AM_HAL_UART_FR_DSR_READY (_VAL2FLD(UART0_FR_DSR, UART0_FR_DSR_READY)) +#define AM_HAL_UART_FR_CTS UART0_FR_CTS_Msk + +//! @} + +//***************************************************************************** +// +// UART FIFO size for Apollo3. +// +//***************************************************************************** +#define AM_HAL_UART_FIFO_MAX 32 + +//***************************************************************************** +// +// Turn timeouts into indefinite waits. +// +//***************************************************************************** +#define AM_HAL_UART_WAIT_FOREVER 0xFFFFFFFF + +//***************************************************************************** +// +//! @brief Initialize the UART interface. +//! +//! @param ui32Module is the module number for the UART to initialize. +//! @param ppHandle is the location to write the UART handle. +//! +//! This function sets internal tracking variables associated with a specific +//! UART module. It should be the first UART API called for each UART module in +//! use. The handle can be used to interact with the UART +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_initialize(uint32_t ui32Module, void **ppHandle); + +//***************************************************************************** +// +//! @brief Deinitialize the UART interface. +//! +//! @param pHandle is a previously initialized UART handle. +//! +//! This function effectively disables future calls to interact with the UART +//! refered to by \e pHandle. The user may call this function if UART operation +//! is no longer desired. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_deinitialize(void *pHandle); + +//***************************************************************************** +// +//! @brief Change the power state of the UART module. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ePowerstate is the desired power state of the UART. +//! @parame bRetainState is a flag to ask the HAL to save UART registers. +//! +//! This function can be used to switch the power to the UART on or off. If \e +//! bRetainState is true during a powerdown operation, it will store the UART +//! configuration registers to SRAM, so it can restore them on power-up. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_power_control(void *pHandle, + am_hal_sysctrl_power_state_e ePowerState, + bool bRetainState); + +//***************************************************************************** +// +//! @brief Used to configure basic UART settings. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param psConfig is a structure of UART configuration options. +//! +//! This function takes the options from an \e am_hal_uart_config_t structure, +//! and applies them to the UART referred to by \e pHandle. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_configure(void *pHandle, + const am_hal_uart_config_t *psConfig); + +extern uint32_t am_hal_uart_configure_fifo(void *pHandle, + const am_hal_uart_config_t *psConfig, + bool bEnableFIFO); + +//***************************************************************************** +// +//! @brief Transfer data through the UART interface. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param am_hal_uart_transfer_t is a structure describing the operation. +//! +//! This function executes a transaction as described by the \e +//! am_hal_uart_transfer_t structure. It can either read or write, and it will +//! take advantage of any buffer space provided by the \e +//! am_hal_uart_configure() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_transfer(void *pHandle, + const am_hal_uart_transfer_t *pTransfer); + +//***************************************************************************** +// +//! @brief Wait for the UART TX to become idle +//! +//! @param pHandle is the handle for the UART to operate on. +//! +//! This function waits (polling) for all data in the UART TX FIFO and UART TX +//! buffer (if configured) to be fully sent on the physical UART interface. +//! This is not the most power-efficient way to wait for UART idle, but it can be +//! useful in simpler applications, or where power-efficiency is less important. +//! +//! Once this function returns, the UART can be safely disabled without +//! interfering with any previous transmissions. +//! +//! For a more power-efficient way to shut down the UART, check the +//! \e am_hal_uart_interrupt_service() function. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_tx_flush(void *pHandle); + +//***************************************************************************** +// +//! @brief Read the UART flags. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui32Flags is the destination pointer for the UART flags. +//! +//! The UART hardware provides some information about the state of the physical +//! interface at all times. This function provides a way to read that data +//! directly. Below is a list of all possible UART flags. +//! +//! These correspond directly to the bits in the UART_FR register. +//! +//! @code +//! +//! AM_HAL_UART_FR_TX_EMPTY +//! AM_HAL_UART_FR_RX_FULL +//! AM_HAL_UART_FR_TX_FULL +//! AM_HAL_UART_FR_RX_EMPTY +//! AM_HAL_UART_FR_BUSY +//! AM_HAL_UART_FR_DCD_DETECTED +//! AM_HAL_UART_FR_DSR_READY +//! AM_HAL_UART_FR_CTS +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_flags_get(void *pHandle, uint32_t *pui32Flags); + +//***************************************************************************** +// +//! @brief Read the UART FIFO directly. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui8Data is a pointer where the UART data should be written. +//! @param ui32NumBytes is the number of bytes to transfer. +//! @param pui32NumBytesRead is the nubmer of bytes actually transferred. +//! +//! This function reads the UART FIFO directly, and writes the resulting bytes +//! to pui8Data. Since the UART FIFO hardware has no direct size indicator, the +//! caller can only specify the maximum number of bytes they can handle. This +//! function will try to read as many bytes as possible. At the end of the +//! transfer, the number of bytes actually transferred will be written to the +//! pui32NumBytesRead parameter. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART error. +// +//***************************************************************************** +extern uint32_t am_hal_uart_fifo_read(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead); + +//***************************************************************************** +// +//! @brief Write the UART FIFO directly. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui8Data is a pointer where the UART data should be written. +//! @param ui32NumBytes is the number of bytes to transfer. +//! @param pui32NumBytesWritten is the nubmer of bytes actually transferred. +//! +//! This function reads from pui8Data, and writes the requested number of bytes +//! directly to the UART FIFO. Since the UART FIFO hardware has no register to +//! tell us how much free space it has, the caller can only specify the number +//! of bytes they would like to send. This function will try to write as many +//! bytes as possible up to the requested number. At the end of the transfer, +//! the number of bytes actually transferred will be written to the +//! pui32NumBytesWritten parameter. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART error. +// +//***************************************************************************** +extern uint32_t am_hal_uart_fifo_write(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten); + +//***************************************************************************** +// +//! @brief This function handles the UART buffers during UART interrupts. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32Status is the interrupt status at the time of ISR entry. +//! @param pui32UartTxIdle can be used to store the UART idle status. +//! +//! The main purpose of this function is to manage the UART buffer system. Any +//! buffers configured by \e am_hal_uart_buffer_configure will be managed by +//! this service routine. Data queued for transmit will be added to the UART TX +//! FIFO as space allows, and data stored in the UART RX FIFO will be copied +//! out and stored in the RX buffer. This function will skip this transfer for +//! any buffer that has not been configured. +//! +//! In addition, this function can be used to alert the caller when the UART +//! becomes idle via the optional \e pui32UartTxIdle argument. This function +//! will set this variable any time it completes its operation and the UART TX +//! channel is no longer in use (including both the FIFO and any configured +//! buffer). To make sure this happens as early as possible, the user may +//! enable the UART_TXCMP interrupt as shown below. +//! +//! For RTOS-enabled cases, this function does not necessarily need to be +//! called inside the actual ISR for the UART, but it should be called promptly +//! in response to the receipt of a UART TX, RX, or RX timeout interrupt. If +//! the service routine is not called quickly enough, the caller risks an RX +//! FIFO overflow (data can be lost here), or a TX FIFO underflow (usually not +//! harmful). +//! +//! @code +//! +//! void +//! am_uart_isr(void) +//! { +//! // +//! // Service the FIFOs as necessary, and clear the interrupts. +//! // +//! uint32_t ui32Status; +//! uint32_t ui32UartIdle; +//! +//! am_hal_uart_interrupt_status_get(UART, &ui32Status, true); +//! am_hal_uart_interrupt_clear(UART, ui32Status); +//! am_hal_uart_interrupt_service(UART, ui32Status, &ui32UartIdle); +//! +//! ui32TXDoneFlag = ui32UartIdle; +//! } +//! +//! int +//! main(void) +//! { +//! ... +//! +//! // Initialize, power up, and configure the UART. +//! am_hal_uart_initialize(0, &UART); +//! am_hal_uart_power_control(UART, AM_HAL_SYSCTRL_WAKE, false); +//! am_hal_uart_configure(UART, &sUartConfig); +//! +//! ... +//! +//! // Enable the UART0 interrupt vector. +//! am_hal_uart_interrupt_enable(UART, AM_REG_UART_IER_TXCMPMIM_M); +//! am_hal_interrupt_enable(AM_HAL_INTERRUPT_UART0); +//! am_hal_interrupt_master_enable(); +//! } +//! +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_service(void *pHandle, + uint32_t ui32Status, + uint32_t *pui32UartTxIdle); + +//***************************************************************************** +// +//! @brief Enable interrupts. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32IntMask is the bitmask of interrupts to enable. +//! +//! This function enables the UART interrupt(s) given by ui32IntMask. If +//! multiple interrupts are desired, they can be OR'ed together. +//! +//! @note This function need not be called for UART FIFO interrupts if the UART +//! buffer service provided by \e am_hal_uart_buffer_configure() and \e +//! am_hal_uart_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_enable(void *pHandle, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Disable interrupts. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32IntMask is the bitmask of interrupts to disable. +//! +//! This function disables the UART interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be disabled, they can be OR'ed together. +//! +//! @note This function need not be called for UART FIFO interrupts if the UART +//! buffer service provided by \e am_hal_uart_buffer_configure() and \e +//! am_hal_uart_interrupt_service() is already in use. Non-FIFO-related +//! interrupts do require the use of this function. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_disable(void *pHandle, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Clear interrupt status. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param ui32IntMask is the bitmask of interrupts to clear. +//! +//! This function clears the UART interrupt(s) given by ui32IntMask. If +//! multiple interrupts need to be cleared, they can be OR'ed together. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_clear(void *pHandle, + uint32_t ui32IntMask); + +//***************************************************************************** +// +//! @brief Read interrupt status. +//! +//! @param pHandle is the handle for the UART to operate on. +//! +//! @param pui32Status is the returned interrupt status (all bits OR'ed +//! together) +//! +//! @param bEnabled determines whether to read interrupts that were not +//! enabled. +//! +//! This function reads the status the UART interrupt(s) if \e bEnabled is +//! true, it will only return the status of the enabled interrupts. Otherwise, +//! it will return the status of all interrupts, enabled or disabled. +//! +//! The full list of interrupts is given by the following: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_status_get(void *pHandle, + uint32_t *pui32Status, + bool bEnabledOnly); + +typedef enum +{ + AM_HAL_UART_STATUS_BUS_ERROR = AM_HAL_STATUS_MODULE_SPECIFIC_START, + AM_HAL_UART_STATUS_RX_QUEUE_FULL, + AM_HAL_UART_STATUS_CLOCK_NOT_CONFIGURED, + AM_HAL_UART_STATUS_BAUDRATE_NOT_POSSIBLE, +} +am_hal_uart_errors_t; + +//***************************************************************************** +// +//! @brief Check to see which interrupts are enabled. +//! +//! @param pHandle is the handle for the UART to operate on. +//! +//! @param pui32IntMask is the current set of interrupt enable bits (all bits +//! OR'ed together) +//! +//! This function checks the UART Interrupt Enable Register to see which UART +//! interrupts are currently enabled. The result will be an interrupt mask with +//! one bit set for each of the currently enabled UART interrupts. +//! +//! The full set of UART interrupt bits is given by the list below: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_enable_get(void *pHandle, uint32_t *pui32IntMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_UART_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.c new file mode 100644 index 0000000000..d93aad5beb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.c @@ -0,0 +1,417 @@ +//***************************************************************************** +// +// am_hal_wdt.c +//! @file +//! +//! @brief Hardware abstraction layer for the Watchdog Timer module. +//! +//! @addtogroup wdt3 Watchdog Timer (WDT) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Adjacency check +// +// This is related to the timer read workaround. This macro checks to see if +// the two supplied count values are within one "tick" of eachother. It should +// still pass in the event of a timer rollover. The "B" read is assumed to +// follow the "A" read. The macro returns "TRUE" when the adjacent timer reads +// can be used. +// +//***************************************************************************** +#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) + +//***************************************************************************** +// +//! @brief Configure the watchdog timer. +//! +//! @param psConfig - pointer to a configuration structure containing the +//! desired watchdog settings. +//! +//! This function will set the watchdog configuration register based on the +//! user's desired settings listed in the structure referenced by psConfig. If +//! the structure indicates that watchdog interrupts are desired, this function +//! will also set the interrupt enable bit in the configuration register. +//! +//! @note In order to actually receive watchdog interrupt and/or watchdog reset +//! events, the caller will also need to make sure that the watchdog interrupt +//! vector is enabled in the ARM NVIC, and that watchdog resets are enabled in +//! the reset generator module. Otherwise, the watchdog-generated interrupt and +//! reset events will have no effect. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_init(const am_hal_wdt_config_t *psConfig) +{ + uint32_t ui32ConfigVal; + uint16_t ui16IntCount, ui16ResetCount; + bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET; + bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT; + + // + // Read the desired settings from the psConfig structure. + // + ui16IntCount = psConfig->ui16InterruptCount; + ui16ResetCount = psConfig->ui16ResetCount; + + // + // Write the interrupt and reset count values to a temporary variable. + // + // Accept the passed Config value, but clear the Counts that we are about to set. + ui32ConfigVal = psConfig->ui32Config & ~(WDT_CFG_INTVAL_Msk | WDT_CFG_RESVAL_Msk); + ui32ConfigVal |= _VAL2FLD(WDT_CFG_INTVAL, ui16IntCount); + ui32ConfigVal |= _VAL2FLD(WDT_CFG_RESVAL, ui16ResetCount); + + // + // If interrupts should be enabled, set the appropriate bit in the + // temporary variable. Also, enable the interrupt in INTEN register in the + // watchdog module. + // + if ( bInterruptEnabled ) + { + // + // Enable the watchdog interrupt if the configuration calls for them. + // + WDT->INTEN |= WDT_INTEN_WDTINT_Msk; + } + else + { + // + // Disable the watchdog interrupt if the configuration doesn't call for + // watchdog interrupts. + // + WDT->INTEN &= ~WDT_INTEN_WDTINT_Msk; + } + + // + // If resets should be enabled, set the appropriate bit in the temporary + // variable. + // + if ( bResetEnabled ) + { + // + // Also enable watchdog resets in the reset module. + // + RSTGEN->CFG |= RSTGEN_CFG_WDREN_Msk; + } + else + { + // + // Disable watchdog resets in the reset module. + // + RSTGEN->CFG &= ~RSTGEN_CFG_WDREN_Msk; + } + + // + // Check for a user specified clock select. If none specified then + // set 128Hz. + // + if ( !(psConfig->ui32Config & WDT_CFG_CLKSEL_Msk) ) + { + ui32ConfigVal |= _VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_128HZ); + } + + // + // Write the saved value to the watchdog configuration register. + // + WDT->CFG = ui32ConfigVal; +} // am_hal_wdt_init() + +//***************************************************************************** +// +//! @brief Starts the watchdog timer. +//! +//! Enables the watchdog timer tick using the 'enable' bit in the watchdog +//! configuration register. This function does not perform any locking of the +//! watchdog timer, so it can be disabled or reconfigured later. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_start(void) +{ + // + // Make sure the watchdog timer is in the "reset" state, and then set the + // enable bit to start counting. + // + WDT->CFG |= WDT_CFG_WDTEN_Msk; + WDT->RSTRT = WDT_RSTRT_RSTRT_KEYVALUE; +} // am_hal_wdt_start() + +//***************************************************************************** +// +//! @brief Stops the watchdog timer. +//! +//! Disables the watchdog timer tick by clearing the 'enable' bit in the +//! watchdog configuration register. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_halt(void) +{ + // + // Clear the watchdog enable bit. + // + WDT->CFG &= ~WDT_CFG_WDTEN_Msk; +} // am_hal_wdt_halt() + +//***************************************************************************** +// +//! @brief Locks the watchdog configuration and starts the watchdog timer. +//! +//! This function sets the watchdog "lock" register, which prevents software +//! from re-configuring the watchdog. This action will also set the enable bit +//! for the watchdog timer, so it will start counting immediately. +//! +//! @return None. +// +//***************************************************************************** +void +am_hal_wdt_lock_and_start(void) +{ + // + // Write the 'key' value to the watchdog lock register. + // + WDT->LOCK = WDT_LOCK_LOCK_KEYVALUE; +} // am_hal_wdt_lock_and_start() + +//***************************************************************************** +// +//! @brief Read the state of the wdt interrupt status. +//! +//! @param bEnabledOnly - return the status of only the enabled interrupts. +//! +//! This function extracts the interrupt status bits and returns the enabled or +//! raw based on bEnabledOnly. +//! +//! @return WDT interrupt status. +// +//***************************************************************************** +uint32_t +am_hal_wdt_int_status_get(bool bEnabledOnly) +{ + if ( bEnabledOnly ) + { + uint32_t ui32RetVal; + AM_CRITICAL_BEGIN + ui32RetVal = WDT->INTSTAT; + ui32RetVal &= WDT->INTEN; + AM_CRITICAL_END + return ui32RetVal; + } + else + { + return WDT->INTSTAT; + } +} // am_hal_wdt_int_status_get() + +//***************************************************************************** +// +//! @brief Set the state of the wdt interrupt status bit. +//! +//! This function sets the interrupt bit. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_set(void) +{ + WDT->INTSET = WDT_INTSET_WDTINT_Msk; +} // am_hal_wdt_int_set() + +//***************************************************************************** +// +//! @brief Clear the state of the wdt interrupt status bit. +//! +//! This function clear the interrupt bit. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_clear(void) +{ + WDT->INTCLR = WDT_INTCLR_WDTINT_Msk; +} // am_hal_wdt_int_clear() + +//***************************************************************************** +// +//! @brief Enable the wdt interrupt. +//! +//! This function enable the interrupt. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_enable(void) +{ + WDT->INTEN |= WDT_INTEN_WDTINT_Msk; +} // am_hal_wdt_int_enable() + +//***************************************************************************** +// +//! @brief Return the enabled WDT interrupts. +//! +//! This function returns the enabled WDT interrupts. +//! +//! @return enabled WDT interrupts. +// +//***************************************************************************** +uint32_t +am_hal_wdt_int_enable_get(void) +{ + return WDT->INTEN; +} // am_hal_wdt_int_enable_get() + +//***************************************************************************** +// +//! @brief Disable the wdt interrupt. +//! +//! This function disablee the interrupt. +//! +//! @return None +// +//***************************************************************************** +void +am_hal_wdt_int_disable(void) +{ + WDT->INTEN &= ~WDT_INTEN_WDTINT_Msk; +} // am_hal_wdt_int_disable() + +//***************************************************************************** +// +//! @brief Get the wdt counter value. +//! +//! This function reads the current value of watch dog timer counter register. +//! +//! @return None +// +//***************************************************************************** +uint32_t +am_hal_wdt_counter_get(void) +{ + uint32_t ui32Values[3] = {0}; + uint32_t ui32Value; + + // + // Start a critical section. + // + uint32_t ui32InterruptState = am_hal_interrupt_master_disable(); + + // + // First, go read the value from the counter register 3 times + // back to back in assembly language. + // + am_hal_triple_read( AM_REGADDR(WDT, COUNT), ui32Values ); + + // + // Mask out the COUNT field from the 3 read values. + // + ui32Values[0] = _VAL2FLD(WDT_COUNT_COUNT, ui32Values[0]); + ui32Values[1] = _VAL2FLD(WDT_COUNT_COUNT, ui32Values[1]); + ui32Values[2] = _VAL2FLD(WDT_COUNT_COUNT, ui32Values[2]); + + // + // Now, we'll figure out which of the three values is the correct time. + // + if (ui32Values[0] == ui32Values[1]) + { + // + // If the first two values match, then neither one was a bad read. + // We'll take this as the current time. + // + ui32Value = ui32Values[1]; + } + else + { + // + // If the first two values didn't match, then one of them might be bad. + // If one of the first two values is bad, then the third one should + // always be correct. We'll take the third value as the correct count. + // + ui32Value = ui32Values[2]; + + // + // If all of the statements about the architecture are true, the third + // value should be correct, and it should always be within one count of + // either the first or the second value. + // + // Just in case, we'll check against the previous two values to make + // sure that our final answer was reasonable. If it isn't, we will + // flag it as a "bad read", and fail this assert statement. + // + // This shouldn't ever happen, and it hasn't ever happened in any of + // our tests so far. + // + am_hal_debug_assert_msg((adjacent(ui32Values[1], ui32Values[2]) || + adjacent(ui32Values[0], ui32Values[2])), + "Bad CDT read"); + } + + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32InterruptState); + + return ui32Value; +} // am_hal_wdt_counter_get() + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.h new file mode 100644 index 0000000000..ea9019bcaa --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/hal/am_hal_wdt.h @@ -0,0 +1,188 @@ +//***************************************************************************** +// +// am_hal_wdt.h +//! @file +//! +//! @brief Hardware abstraction layer for the Watchdog Timer module. +//! +//! @addtogroup wdt3 Watchdog Timer (WDT) +//! @ingroup apollo3hal +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_HAL_WDT_H +#define AM_HAL_WDT_H + +#include +#include + +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +//***************************************************************************** +// +//! @name WDT Clock Divider Selections. +//! @brief Macro definitions for WDT clock frequencies. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to set the +//! clock frequency of the watch dog timer. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_LFRC_CLK_DEFAULT (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_128HZ)) +#define AM_HAL_WDT_LFRC_CLK_128HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_128HZ)) +#define AM_HAL_WDT_LFRC_CLK_16HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_16HZ)) +#define AM_HAL_WDT_LFRC_CLK_1HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_1HZ)) +#define AM_HAL_WDT_LFRC_CLK_1_16HZ (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_1_16HZ)) +#define AM_HAL_WDT_LFRC_CLK_OFF (_VAL2FLD(WDT_CFG_CLKSEL, WDT_CFG_CLKSEL_OFF)) +//! @} + +//***************************************************************************** +// +//! @name WDT Enable Reset in the WDT Configuration. +//! @brief Macro definitions for WDT Reset Enable. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to enable +//! the watch dog timer to generate resets to the chip. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_ENABLE_RESET (_VAL2FLD(WDT_CFG_RESEN, 1)) +#define AM_HAL_WDT_DISABLE_RESET (_VAL2FLD(WDT_CFG_RESEN, 0)) +//! @} + +//***************************************************************************** +// +//! @name WDT Enable Interrupt Generation from the WDT Configuration. +//! @brief Macro definitions for WDT Interrupt Enable. +//! +//! These macros may be used with the am_hal_wdt_config_t structure to enable +//! the watch dog timer to generate generate WDT interrupts. +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_WDT_ENABLE_INTERRUPT (_VAL2FLD(WDT_CFG_INTEN, 1)) +#define AM_HAL_WDT_DISABLE_INTERRUPT (_VAL2FLD(WDT_CFG_INTEN, 0)) +//! @} + +//***************************************************************************** +// +//! @brief Watchdog timer configuration structure. +//! +//! This structure is made to be used with the am_hal_wdt_init() function. It +//! describes the configuration of the watchdog timer. +// +//***************************************************************************** +typedef struct +{ + //! Configuration Values for watchdog timer + //! event is generated. + uint32_t ui32Config; + + //! Number of watchdog timer ticks allowed before a watchdog interrupt + //! event is generated. + uint16_t ui16InterruptCount; + + //! Number of watchdog timer ticks allowed before the watchdog will issue a + //! system reset. + uint16_t ui16ResetCount; + +} +am_hal_wdt_config_t; + +//***************************************************************************** +// +//! @brief Restarts the watchdog timer ("Pets" the dog) +//! +//! This function restarts the watchdog timer from the beginning, preventing +//! any interrupt or reset even from occuring until the next time the watchdog +//! timer expires. +//! +//! @return None. +// +//***************************************************************************** +#define am_hal_wdt_restart() \ + do \ + { \ + WDT->RSTRT = WDT_RSTRT_RSTRT_KEYVALUE; \ + (void)(WDT->RSTRT); \ + } \ + while (0) + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_hal_wdt_init(const am_hal_wdt_config_t *psConfig); +extern void am_hal_wdt_start(void); +extern void am_hal_wdt_halt(void); +extern void am_hal_wdt_lock_and_start(void); +extern uint32_t am_hal_wdt_counter_get(void); +extern void am_hal_wdt_int_enable(void); +extern uint32_t am_hal_wdt_int_enable_get(void); +extern void am_hal_wdt_int_disable(void); +extern void am_hal_wdt_int_clear(void); +extern void am_hal_wdt_int_set(void); +extern uint32_t am_hal_wdt_int_status_get(bool bEnabledOnly); +#ifdef __cplusplus +} +#endif + +#endif // AM_HAL_WDT_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg.h new file mode 100644 index 0000000000..4c96cc89c7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg.h @@ -0,0 +1,282 @@ +//***************************************************************************** +// +// am_reg.h +//! @file +//! +//! @brief Apollo4 register macros +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_H +#define AM_REG_H + +//***************************************************************************** +// +// ADC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_ADC_NUM_MODULES 1 +#define AM_REG_ADCn(n) \ + (REG_ADC_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// APBDMA +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_APBDMA_NUM_MODULES 1 +#define AM_REG_APBDMAn(n) \ + (REG_APBDMA_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// BLEIF +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_BLEIF_NUM_MODULES 1 +#define AM_REG_BLEIFn(n) \ + (REG_BLEIF_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// CACHECTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CACHECTRL_NUM_MODULES 1 +#define AM_REG_CACHECTRLn(n) \ + (REG_CACHECTRL_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// CLKGEN +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CLKGEN_NUM_MODULES 1 +#define AM_REG_CLKGENn(n) \ + (REG_CLKGEN_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// CTIMER +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_CTIMER_NUM_MODULES 1 +#define AM_REG_CTIMERn(n) \ + (REG_CTIMER_BASEADDR + 0x00000020 * n) + + +//***************************************************************************** +// +// FLASHCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_FLASHCTRL_NUM_MODULES 1 +#define AM_REG_FLASHCTRLn(n) \ + (REG_FLASHCTRL_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// GPIO +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_GPIO_NUM_MODULES 1 +#define AM_REG_GPIOn(n) \ + (REG_GPIO_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// IOM +// Instance finder. (6 instance(s) available) +// +//***************************************************************************** +#define AM_REG_IOM_NUM_MODULES 6 +#define AM_REG_IOMn(n) \ + (REG_IOM_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// IOSLAVE +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_IOSLAVE_NUM_MODULES 1 +#define AM_REG_IOSLAVEn(n) \ + (REG_IOSLAVE_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// MCUCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_MCUCTRL_NUM_MODULES 1 +#define AM_REG_MCUCTRLn(n) \ + (REG_MCUCTRL_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// MSPI +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_MSPI_NUM_MODULES 1 +#define AM_REG_MSPIn(n) \ + (REG_MSPI_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// PDM +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_PDM_NUM_MODULES 1 +#define AM_REG_PDMn(n) \ + (REG_PDM_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// PWRCTRL +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_PWRCTRL_NUM_MODULES 1 +#define AM_REG_PWRCTRLn(n) \ + (REG_PWRCTRL_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// RSTGEN +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_RSTGEN_NUM_MODULES 1 +#define AM_REG_RSTGENn(n) \ + (REG_RSTGEN_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// RTC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_RTC_NUM_MODULES 1 +#define AM_REG_RTCn(n) \ + (REG_RTC_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// SCARD +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_SCARD_NUM_MODULES 1 +#define AM_REG_SCARDn(n) \ + (REG_SCARD_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// SECURITY +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_SECURITY_NUM_MODULES 1 +#define AM_REG_SECURITYn(n) \ + (REG_SECURITY_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// UART +// Instance finder. (2 instance(s) available) +// +//***************************************************************************** +#define AM_REG_UART_NUM_MODULES 2 +#define AM_REG_UARTn(n) \ + (REG_UART_BASEADDR + 0x00001000 * n) + + +//***************************************************************************** +// +// VCOMP +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_VCOMP_NUM_MODULES 1 +#define AM_REG_VCOMPn(n) \ + (REG_VCOMP_BASEADDR + 0x00000000 * n) + + +//***************************************************************************** +// +// WDT +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_WDT_NUM_MODULES 1 +#define AM_REG_WDTn(n) \ + (REG_WDT_BASEADDR + 0x00000000 * n) + + +#endif // AM_REG_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_base_addresses.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_base_addresses.h new file mode 100644 index 0000000000..bd62110ab8 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_base_addresses.h @@ -0,0 +1,99 @@ +//***************************************************************************** +// +// am_reg_base_addresses.h +//! @file +//! +//! @brief Register defines for all module base addresses +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_BASE_ADDRESSES_H +#define AM_REG_BASE_ADDRESSES_H + +#include "stdint.h" + +// +// ARM standard register space (needed for macros) +// +#define REG_ITM_BASEADDR (0x00000000UL) +#define REG_JEDEC_BASEADDR (0x00000000UL) +#define REG_NVIC_BASEADDR (0x00000000UL) +#define REG_SYSCTRL_BASEADDR (0x00000000UL) +#define REG_SYSTICK_BASEADDR (0x00000000UL) +#define REG_TPIU_BASEADDR (0x00000000UL) + +// +// Peripheral register space +// +#define REG_ADC_BASEADDR (0x50010000UL) +#define REG_APBDMA_BASEADDR (0x40011000UL) +#define REG_BLEIF_BASEADDR (0x5000C000UL) +#define REG_CACHECTRL_BASEADDR (0x40018000UL) +#define REG_CLKGEN_BASEADDR (0x40004000UL) +#define REG_CTIMER_BASEADDR (0x40008000UL) +#define REG_GPIO_BASEADDR (0x40010000UL) +//#define REG_IOMSTR_BASEADDR (0x50004000UL) +#define REG_IOM_BASEADDR (0x50004000UL) +#define REG_IOSLAVE_BASEADDR (0x50000000UL) +#define REG_MCUCTRL_BASEADDR (0x40020000UL) +#define REG_MSPI_BASEADDR (0x50014000UL) +#define REG_PDM_BASEADDR (0x50011000UL) +#define REG_PWRCTRL_BASEADDR (0x40021000UL) +#define REG_RSTGEN_BASEADDR (0x40000000UL) +#define REG_RTC_BASEADDR (0x40004200UL) +#define REG_SCARD_BASEADDR (0x40080000UL) +#define REG_SECURITY_BASEADDR (0x40030000UL) +#define REG_UART_BASEADDR (0x4001C000UL) +#define REG_VCOMP_BASEADDR (0x4000C000UL) +#define REG_WDT_BASEADDR (0x40024000UL) + +// +// SRAM address space +// +#define SRAM_BASEADDR (0x10000000UL) + +// +// Flash address space +// +#define FLASH_BASEADDR (0x00000000UL) + +#endif // AM_REG_BASE_ADDRESSES_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h new file mode 100644 index 0000000000..500b47b227 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_iomstr_cmd.h @@ -0,0 +1,77 @@ +//***************************************************************************** +// +// am_reg_iomstr_cmd.h +//! @file +//! +//! @brief Register macros for the IOMSTR module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_IOMSTR_CMD_H +#define AM_REG_IOMSTR_CMD_H + +#if AM_PART_APOLLO2 +//***************************************************************************** +// +// IOMSTR_CMD - Command Register +// +//***************************************************************************** +#define AM_REG_IOMSTR_CMD_CMD_POS_LENGTH 0x00000000 +#define AM_REG_IOMSTR_CMD_CMD_POS_OFFSET 0x00000008 +#define AM_REG_IOMSTR_CMD_CMD_POS_ADDRESS 0x00000010 +#define AM_REG_IOMSTR_CMD_CMD_POS_CHNL 0x00000010 +#define AM_REG_IOMSTR_CMD_CMD_POS_UPLNGTH 0x00000017 +#define AM_REG_IOMSTR_CMD_CMD_POS_10BIT 0x0000001A +#define AM_REG_IOMSTR_CMD_CMD_POS_LSB 0x0000001B +#define AM_REG_IOMSTR_CMD_CMD_POS_CONT 0x0000001C +#define AM_REG_IOMSTR_CMD_CMD_POS_OPER 0x0000001D +#define AM_REG_IOMSTR_CMD_CMD_MSK_LENGTH 0x000000FF +#define AM_REG_IOMSTR_CMD_CMD_MSK_OFFSET 0x0000FF00 +#define AM_REG_IOMSTR_CMD_CMD_MSK_ADDRESS 0x00FF0000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_CHNL 0x00070000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_UPLNGTH 0x07800000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_10BIT 0x04000000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_LSB 0x08000000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_CONT 0x10000000 +#define AM_REG_IOMSTR_CMD_CMD_MSK_OPER 0xE0000000 +#endif // AM_PART_APOLLO2 + +#endif // AM_REG_IOMSTR_CMD_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_jedec.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_jedec.h new file mode 100644 index 0000000000..d7f651885d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_jedec.h @@ -0,0 +1,370 @@ +//***************************************************************************** +// +// am_reg_jedec.h +//! @file +//! +//! @brief Register macros for the ARM JEDEC module +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_REG_JEDEC_H +#define AM_REG_JEDEC_H + +//***************************************************************************** +// +// JEDEC +// Instance finder. (1 instance(s) available) +// +//***************************************************************************** +#define AM_REG_JEDEC_NUM_MODULES 1 +#define AM_REG_JEDECn(n) \ + (REG_JEDEC_BASEADDR + 0x00000000 * n) + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language = extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** + \brief Structure type to access the Apollo CM4 JEDEC registers. + */ +typedef struct +{ + uint32_t RESERVED0[52U]; /* 0xF00 - 0xFCF */ + + union + { + __IM uint32_t PID4; /*!< 0xF0000FD0 (R/ ) PID4 Register */ + + struct + { + __IM uint32_t JEPCONT : 4; /* [3..0] Contains the JEP Continuation bits. */ + } PID4_b; + }; + + union + { + __IM uint32_t PID5; /*!< 0xF0000FD4 (R/ ) PID5 Register */ + + struct + { + __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ + } PID5_b; + }; + + union + { + __IM uint32_t PID6; /*!< 0xF0000FD8 (R/ ) PID6 Register */ + + struct + { + __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ + } PID6_b; + }; + + union + { + __IM uint32_t PID7; /*!< 0xF0000FDC (R/ ) PID7 Register */ + + struct + { + __IM uint32_t VALUE : 32; /* [31..0] Contains the value of 0x00000000. */ + } PID7_b; + }; + + union + { + __IM uint32_t PID0; /*!< 0xF0000FE0 (R/ ) PID0 Register */ + + struct + { + __IM uint32_t PNL8 : 8; /* [7..0] Contains the low 8 bits of the Ambiq Micro device part number. */ + } PID0_b; + }; + + union + { + __IM uint32_t PID1; /*!< 0xF0000FE4 (R/ ) PID1 Register */ + + struct + { + __IM uint32_t PNH4 : 4; /* [3..0] Contains the high 4 bits of the Ambiq Micro device part number. */ + __IM uint32_t JEPIDL : 4; /* [7..4] Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID is therefore 0x9B. */ + } PID1_b; + }; + + union + { + __IM uint32_t PID2; /*!< 0xF0000FE8 (R/ ) PID2 Register */ + + struct + { + __IM uint32_t JEPIDH : 4; /* [3..0] Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this field is hard-coded to 1. The full JEPID is therefore 0x9B. */ + __IM uint32_t CHIPREVH4 : 4; /* [7..4] Contains the high 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */ + } PID2_b; + }; + + union + { + __IM uint32_t PID3; /*!< 0xF0000FEC (R/ ) PID3 Register */ + + struct + { + __IM uint32_t ZERO : 4; /* [3..0] This field is hard-coded to 0x0. */ + __IM uint32_t CHIPREVL4 : 4; /* [7..0] Contains the low 4 bits of the Ambiq Micro CHIPREV (see also MCUCTRL.CHIPREV). Note that this field will change with each revision of the chip. */ + } PID3_b; + }; + + union + { + __IM uint32_t CID0; /*!< 0xF0000FE0 (R/ ) CID0 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID0. */ + } CID0_b; + }; + + union + { + __IM uint32_t CID1; /*!< 0xF0000FE4 (R/ ) CID1 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID1. */ + } CID1_b; + }; + + union + { + __IM uint32_t CID2; /*!< 0xF0000FE8 (R/ ) CID2 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID2. */ + } CID2_b; + }; + + union + { + __IM uint32_t CID3; /*!< 0xF0000FEC (R/ ) CID3 Register */ + + struct + { + __IM uint32_t CID : 8; /* [7..0] Coresight ROM Table, CID3. */ + } CID3_b; + }; +} JEDEC_Type; + + +//***************************************************************************** +// +// JEDEC_PID4 - JEP Continuation Register +// +//***************************************************************************** +// Contains the JEP Continuation bits. +#define JEDEC_PID4_JEPCONT_Pos 0U +#define JEDEC_PID4_JEPCONT_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_PID5 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define JEDEC_PID5_VALUE_Pos 0U +#define JEDEC_PID5_VALUE_Msk (0xFFFFFFFFUL) + +//***************************************************************************** +// +// JEDEC_PID6 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define JEDEC_PID6_VALUE_Pos 0U +#define JEDEC_PID6_VALUE_Msk (0xFFFFFFFFUL) + +//***************************************************************************** +// +// JEDEC_PID7 - JEP reserved Register +// +//***************************************************************************** +// Contains the value of 0x00000000. +#define JEDEC_PID7_VALUE_Pos 0U +#define JEDEC_PID7_VALUE_Msk (0xFFFFFFFFUL) + +//***************************************************************************** +// +// JEDEC_PID0 - Ambiq Partnum low byte +// +//***************************************************************************** +// Contains the low 8 bits of the Ambiq Micro device part number. +#define JEDEC_PID0_PNL8_Pos 0U +#define JEDEC_PID0_PNL8_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble. +// +//***************************************************************************** +// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID +// is therefore 0x9B. +#define JEDEC_PID1_JEPIDL_Pos 4U +#define JEDEC_PID1_JEPIDL_Msk (0x000000F0UL) + +// Contains the high 4 bits of the Ambiq Micro device part number. +#define JEDEC_PID1_PNH4_Pos 0U +#define JEDEC_PID1_PNH4_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble +// +//***************************************************************************** +// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also +// MCUCTRL.CHIPREV). Note that this field will change with each revision of the +// chip. +#define JEDEC_PID2_CHIPREVH4_Pos 4U +#define JEDEC_PID2_CHIPREVH4_Msk (0x000000F0UL) + +// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this +// field is hard-coded to 1. The full JEPID is therefore 0x9B. +#define JEDEC_PID2_JEPIDH_Pos 0U +#define JEDEC_PID2_JEPIDH_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_PID3 - Ambiq chip revision high-nibble. +// +//***************************************************************************** +// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also +// MCUCTRL.CHIPREV). Note that this field will change with each revision of the +// chip. +#define JEDEC_PID3_CHIPREVL4_Pos 4U +#define JEDEC_PID3_CHIPREVL4_Msk (0x000000F0UL) + +// This field is hard-coded to 0x0. +#define JEDEC_PID3_ZERO_Pos 0U +#define JEDEC_PID3_ZERO_Msk (0x0000000FUL) + +//***************************************************************************** +// +// JEDEC_CID0 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID0. +#define JEDEC_CID0_CID_Pos 0U +#define JEDEC_CID0_CID_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_CID1 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID1. +#define JEDEC_CID1_CID_Pos 0U +#define JEDEC_CID1_CID_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_CID2 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID2. +#define JEDEC_CID2_CID_Pos 0U +#define JEDEC_CID2_CID_Msk (0x000000FFUL) + +//***************************************************************************** +// +// JEDEC_CID3 - Coresight ROM Table. +// +//***************************************************************************** +// Coresight ROM Table, CID3. +#define JEDEC_CID3_CID_Pos 0U +#define JEDEC_CID3_CID_Msk (0x000000FFUL) + + + + +#define JEDEC_BASE (0xF0000F00UL) /*!< JEDEC Base Address */ + +#define JEDEC ((JEDEC_Type *) JEDEC_BASE ) /*!< JEDEC configuration struct */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + + +#endif // AM_REG_JEDEC_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_m4.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_m4.h new file mode 100644 index 0000000000..307fd79822 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_m4.h @@ -0,0 +1,93 @@ +//***************************************************************************** +// +// am_reg_m4.h +//! @file +//! +//! @brief A collection of a few CMSIS-style macros that are not automatically +//! generated in their respective core files. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_REG_CM4_H +#define AM_REG_CM4_H + +//***************************************************************************** +// +// am_reg_itm.h +// CMSIS-style defines. +// +//***************************************************************************** +#define ITM_LAR_KEYVAL 0xC5ACCE55 + +//***************************************************************************** +// +// am_reg_sysctrl.h +// CMSIS-style defines. +// +//***************************************************************************** +#define SCB_CPACR_CP11_Pos 22 +#define SCB_CPACR_CP11_Msk 0x00C00000 +#define SCB_CPACR_CP10_Pos 20 +#define SCB_CPACR_CP10_Msk 0x00300000 + +//***************************************************************************** +// +// am_reg_tpiu.h +// CMSIS-style defines. +// +//***************************************************************************** +#define TPI_CSPSR_CWIDTH_1BIT 1 +#define TPI_SPPR_TXMODE_UART 2 +#define TPI_ITCTRL_Mode_NORMAL 0 + +#ifndef TPI_ACPR_SWOSCALER_Pos +// +// In the CMSIS 5.6.0 version of core_cm4.h, the SWOSCALER field was no longer +// defined, while the PRESCALER field was left intact even though previous CMSIS +// versions PRESCALER as deprecated. On the off chance that future versions +// make a correction and remove PRESCALER, define SWOSCALER here (per 5.3.0). +// +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#endif + +#endif // AM_REG_CM4_H diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros.h new file mode 100644 index 0000000000..89b6942081 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros.h @@ -0,0 +1,111 @@ +//***************************************************************************** +// +// am_reg_macros.h +//! @file +//! +//! @brief Helper macros for using hardware registers. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_REG_MACROS_H +#define AM_REG_MACROS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// For direct 32-bit access to a register or memory location, use AM_REGVAL: +// AM_REGVAL(0x1234567) |= 0xDEADBEEF; +// +//***************************************************************************** +#define AM_REGVAL(x) (*((volatile uint32_t *)(x))) +#define AM_REGVAL_FLOAT(x) (*((volatile float *)(x))) + +//***************************************************************************** +// +// AM_REGADDR() +// One thing CMSIS does not do well natively is to provide for static register +// address computation. The address-of operator (e.g. &periph->reg) is helpful, +// but does run into problems, such as when attempting to cast the resulting +// pointer to a uint32_t. The standard C macro, offsetof() can help. +// +// Use AM_REGADDR() for single-module peripherals. +// Use AM_REGADDRn() for multi-module peripherals (e.g. IOM, UART). +// +//***************************************************************************** +#define AM_REGADDR(periph, reg) ( periph##_BASE + offsetof(periph##_Type, reg) ) + +#define AM_REGADDRn(periph, n, reg) ( periph##0_BASE + \ + offsetof(periph##0_Type, reg) + \ + (n * (periph##1_BASE - periph##0_BASE)) ) + +//***************************************************************************** +// +// Critical section assembly macros +// +// These macros implement critical section protection using inline assembly +// for various compilers. They are intended to be used in other register +// macros or directly in sections of code. +// +// Important usage note: These macros create a local scope and therefore MUST +// be used in pairs. +// +//***************************************************************************** +#define AM_CRITICAL_BEGIN \ + if ( 1 ) \ + { \ + volatile uint32_t ui32Primask_04172010; \ + ui32Primask_04172010 = am_hal_interrupt_master_disable(); + +#define AM_CRITICAL_END \ + am_hal_interrupt_master_set(ui32Primask_04172010); \ + } + +#ifdef __cplusplus +} +#endif + +#endif // AM_REG_MACROS_H + diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros_asm.h b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros_asm.h new file mode 100644 index 0000000000..b711935e75 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/sdk/mcu/apollo3/regs/am_reg_macros_asm.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// am_reg_macros_asm.h +//! @file +//! +//! @brief Inline assembly macros. Initially for critical section handling in +//! protecting hardware registers. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_REG_MACROS_ASM_H +#define AM_REG_MACROS_ASM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // AM_REG_MACROS_ASM_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices.h b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices.h new file mode 100644 index 0000000000..f8416f4d6e --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +//! @file am_devices.h +//! +//! @brief Includes for all devices. +//! +//! @addtogroup devices External Device Control Library +//! @ingroup devices +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_DEVICES_H +#define AM_DEVICES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// All DEVICES includes +// +//***************************************************************************** +#include "am_devices_button.h" +#include "am_devices_da14581.h" +#include "am_devices_em9304.h" +#include "am_devices_led.h" +#include "am_devices_spiflash.h" + +#ifdef __cplusplus +} +#endif + +#endif // AM_DEVICES_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.c b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.c new file mode 100644 index 0000000000..728beee541 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.c @@ -0,0 +1,226 @@ +//***************************************************************************** +// +//! @file am_devices_button.c +//! +//! @brief Functions for controlling an array of LEDs +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" +#include "am_devices_button.h" + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButton is a pointer to a button structure. +//! +//! This function configures a GPIO to read a button in a low-power way. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_init(am_devices_button_t *psButton) +{ + // + // Disable the pin to save power. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig(psButton->ui32GPIONumber, g_AM_HAL_GPIO_DISABLE); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config(psButton->ui32GPIONumber, AM_HAL_PIN_DISABLE); +#endif // AM_APOLLO3_GPIO + + + // + // Initialize the state variables. + // + psButton->ui32Count = 0; + psButton->bPressed = false; + psButton->bChanged = false; +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButtons is an array of button structures. +//! @param ui32NumButtons is the total number of buttons in the array. +//! +//! This function configures the GPIOs for an array of buttons. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_array_init(am_devices_button_t *psButtons, + uint32_t ui32NumButtons) +{ + uint32_t i; + + // + // Loop through the list of buttons, configuring each one individually. + // + for ( i = 0; i < ui32NumButtons; i++ ) + { + am_devices_button_init(psButtons + i); + } +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButtons is an array of button structures. +//! @param ui32NumButtons is the total number of buttons in the array. +//! +//! This function configures the GPIOs for an array of buttons. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_tick(am_devices_button_t *psButton) +{ + uint32_t ui32PinState; + bool bRawButtonPressed; + + // + // Enable the button pin. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig(psButton->ui32GPIONumber, g_AM_HAL_GPIO_INPUT); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config(psButton->ui32GPIONumber, AM_HAL_PIN_INPUT); +#endif // AM_APOLLO3_GPIO + + // + // Read the pin state. If the pin is in its normal (unpressed) state, set + // its "state" counter to zero. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_state_read(psButton->ui32GPIONumber, AM_HAL_GPIO_INPUT_READ, &ui32PinState); +#else // AM_APOLLO3_GPIO + ui32PinState = am_hal_gpio_input_bit_read(psButton->ui32GPIONumber); +#endif // AM_APOLLO3_GPIO + + // + // Check to see if the button is "pressed" according to our GPIO reading. + // + bRawButtonPressed = (ui32PinState != psButton->ui32Polarity); + + // + // Is this button state different from the last saved state? + // + if ( bRawButtonPressed != psButton->bPressed ) + { + // + // If so, increase the debounce count. + // + psButton->ui32Count++; + } + else + { + // + // Otherwise, set the count back to zero. + // + psButton->ui32Count = 0; + } + + // + // If we hit the button debounce delay, record a button press to the + // structure, and reset the count. + // + if ( psButton->ui32Count >= AM_DEVICES_BUTTON_DEBOUNCE_DELAY ) + { + psButton->bPressed = bRawButtonPressed; + psButton->bChanged = true; + psButton->ui32Count = 0; + } + else + { + // + // If we didn't just record a press/release event, update the structure + // to say that the current state isn't new. + // + psButton->bChanged = false; + } + + // + // Disable the button pin to save power. + // +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig(psButton->ui32GPIONumber, g_AM_HAL_GPIO_DISABLE); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config(psButton->ui32GPIONumber, AM_HAL_PIN_DISABLE); +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of buttons. +//! +//! @param psButtons is an array of button structures. +//! @param ui32NumButtons is the total number of buttons in the array. +//! +//! This function configures the GPIOs for an array of buttons. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_button_array_tick(am_devices_button_t *psButtons, + uint32_t ui32NumButtons) +{ + uint32_t i; + + // + // Run the "tick" function for each button in the list. + // + for ( i = 0; i < ui32NumButtons; i++ ) + { + am_devices_button_tick(psButtons + i); + } +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.h b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.h new file mode 100644 index 0000000000..a51dc1b674 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_button.h @@ -0,0 +1,129 @@ +//***************************************************************************** +// +//! @file am_devices_button.h +//! +//! @brief Functions for controlling an array of buttons. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_DEVICES_BUTTON_H +#define AM_DEVICES_BUTTON_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Number of "ticks" to delay before registering a button press or release. +// +//***************************************************************************** +#define AM_DEVICES_BUTTON_DEBOUNCE_DELAY 0x4 + +//***************************************************************************** +// +// Button polarity macros +// +//***************************************************************************** +#define AM_DEVICES_BUTTON_NORMAL_HIGH 0x1 +#define AM_DEVICES_BUTTON_NORMAL_LOW 0x0 + +//***************************************************************************** +// +// Structure for keeping track of buttons. +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32GPIONumber; + uint32_t ui32Polarity; + uint32_t ui32Count; + bool bPressed; + bool bChanged; +} +am_devices_button_t; + +//***************************************************************************** +// +// Macro for declaring a button structure. +// +//***************************************************************************** +#define AM_DEVICES_BUTTON(ui32GPIONumber, ui32Polarity) \ + {ui32GPIONumber, ui32Polarity, 0, 0, 0} + +//***************************************************************************** +// +// Macros for checking button state. +// +//***************************************************************************** +#define am_devices_button_is_up(button) \ + ((button).bPressed == false) + +#define am_devices_button_is_down(button) \ + ((button).bPressed == true) + +#define am_devices_button_pressed(button) \ + (((button).bPressed == true) && ((button).bChanged == true)) + +#define am_devices_button_released(button) \ + (((button).bPressed == false) && ((button).bChanged == true)) + + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_devices_button_init(am_devices_button_t *psButton); + +extern void am_devices_button_array_init(am_devices_button_t *psButtons, + uint32_t ui32NumButtons); +extern void am_devices_button_tick(am_devices_button_t *psButton); + +extern void am_devices_button_array_tick(am_devices_button_t *psButtons, + uint32_t ui32NumButtons); +#ifdef __cplusplus +} +#endif + +#endif // AM_DEVICES_BUTTON_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.c b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.c new file mode 100644 index 0000000000..98226f36fb --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.c @@ -0,0 +1,556 @@ +//***************************************************************************** +// +//! @file am_devices_led.c +//! +//! @brief Functions for controlling an array of LEDs +//! +//! @addtogroup devices External Device Control Library +//! @addtogroup LED SPI Device Control for programmable LEDs. +//! @ingroup devices +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_mcu_apollo.h" +#include "am_devices_led.h" + +// +// Define a somewhat arbitrary maximum number of LEDs. No board is actually +// expected to have this many LEDs, the value is used for parameter validation. +// +#define MAX_LEDS 31 + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of LEDs +//! +//! @param psLED is a pointer to an LED structure. +//! +//! This function configures a GPIO to drive an LED in a low-power way. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_init(am_devices_led_t *psLED) +{ + if ( (psLED == NULL) || + (psLED->ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLED->ui32Polarity ) + { + // + // Configure the pin as a push-pull GPIO output. + // + am_hal_gpio_pinconfig(psLED->ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. Note that for Apollo3 GPIOs in push-pull mode, the output + // enable, normally a tri-state control, instead functions as an enable + // for Fast GPIO. Its state does not matter on previous chips, so for + // normal GPIO usage on Apollo3, it must be disabled. + // + am_hal_gpio_state_write(psLED->ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(psLED->ui32GPIONumber, + psLED->ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_SET : AM_HAL_GPIO_OUTPUT_CLEAR); + } + else + { + // + // Configure the pin as a tri-state GPIO. + // + am_hal_gpio_pinconfig(psLED->ui32GPIONumber, g_AM_HAL_GPIO_TRISTATE); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. + // + am_hal_gpio_state_write(psLED->ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(psLED->ui32GPIONumber, + psLED->ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_SET : AM_HAL_GPIO_OUTPUT_CLEAR); + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLED->ui32Polarity ) + { + // + // Configure the pin as a push-pull GPIO output. + // + am_hal_gpio_pin_config(psLED->ui32GPIONumber, AM_HAL_GPIO_OUTPUT); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. + // + am_hal_gpio_out_enable_bit_clear(psLED->ui32GPIONumber); + am_hal_gpio_out_bit_replace(psLED->ui32GPIONumber, + psLED->ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M); + } + else + { + // + // Configure the pin as a tri-state GPIO. + // + am_hal_gpio_pin_config(psLED->ui32GPIONumber, AM_HAL_GPIO_3STATE); + + // + // Disable the output driver, and set the output value to the LEDs "ON" + // state. + // + am_hal_gpio_out_enable_bit_clear(psLED->ui32GPIONumber); + am_hal_gpio_out_bit_replace(psLED->ui32GPIONumber, + psLED->ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M ); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Disables an array of LEDs +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32NumLEDs is the total number of LEDs in the array. +//! +//! This function disables the GPIOs for an array of LEDs. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_array_disable(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs) +{ + if ( (psLEDs == NULL) || + (ui32NumLEDs > MAX_LEDS) ) + { + return; + } + + // + // Loop through the list of LEDs, configuring each one individually. + // + for ( uint32_t i = 0; i < ui32NumLEDs; i++ ) + { + if ( psLEDs[i].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS ) + { + continue; + } + +#if AM_APOLLO3_GPIO + am_hal_gpio_pinconfig((psLEDs + i)->ui32GPIONumber, g_AM_HAL_GPIO_DISABLE); +#else // AM_APOLLO3_GPIO + am_hal_gpio_pin_config((psLEDs + i)->ui32GPIONumber, AM_HAL_GPIO_DISABLE); +#endif // AM_APOLLO3_GPIO + } +} + +//***************************************************************************** +// +//! @brief Configures the necessary pins for an array of LEDs +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32NumLEDs is the total number of LEDs in the array. +//! +//! This function configures the GPIOs for an array of LEDs. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_array_init(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs) +{ + uint32_t i; + + if ( (psLEDs == NULL) || + (ui32NumLEDs > MAX_LEDS) ) + { + return; + } + + // + // Loop through the list of LEDs, configuring each one individually. + // + for ( i = 0; i < ui32NumLEDs; i++ ) + { + am_devices_led_init(psLEDs + i); + } +} + +//***************************************************************************** +// +//! @brief Turns on the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED number for the light to turn on. +//! +//! This function turns on a single LED. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_on(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + psLEDs[ui32LEDNum].ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_SET : AM_HAL_GPIO_OUTPUT_CLEAR); + } + else + { + // + // Turn on the output driver for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE); + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_out_bit_replace(psLEDs[ui32LEDNum].ui32GPIONumber, + psLEDs[ui32LEDNum].ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M ); + } + else + { + // + // Turn on the output driver for the LED. + // + am_hal_gpio_out_enable_bit_set(psLEDs[ui32LEDNum].ui32GPIONumber); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Turns off the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED number for the light to turn off. +//! +//! This function turns off a single LED. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_off(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + psLEDs[ui32LEDNum].ui32Polarity & AM_DEVICES_LED_POL_POLARITY_M ? + AM_HAL_GPIO_OUTPUT_CLEAR : AM_HAL_GPIO_OUTPUT_SET); + } + else + { + // + // Turn off the output driver for the LED. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Set the output to the correct state for the LED. + // + am_hal_gpio_out_bit_replace(psLEDs[ui32LEDNum].ui32GPIONumber, + !(psLEDs[ui32LEDNum].ui32Polarity & + AM_DEVICES_LED_POL_POLARITY_M) ); + } + else + { + // + // Turn off the output driver for the LED. + // + am_hal_gpio_out_enable_bit_clear(psLEDs[ui32LEDNum].ui32GPIONumber); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Toggles the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED number for the light to toggle. +//! +//! This function toggles a single LED. +//! +//! @return None. +// +//***************************************************************************** +void +am_devices_led_toggle(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return; + } + +#if AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TOGGLE); + } + else + { + uint32_t ui32Ret, ui32Value; + + // + // Check to see if the LED pin is enabled. + // + ui32Ret = am_hal_gpio_state_read(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_ENABLE_READ, &ui32Value); + + if ( ui32Ret == AM_HAL_STATUS_SUCCESS ) + { + if ( ui32Value ) + { + // + // If it was enabled, turn if off. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + } + else + { + // + // If it was not enabled, turn it on. + // + am_hal_gpio_state_write(psLEDs[ui32LEDNum].ui32GPIONumber, + AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE); + } + } + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + am_hal_gpio_out_bit_toggle(psLEDs[ui32LEDNum].ui32GPIONumber); + } + else + { + // + // Check to see if the LED pin is enabled. + // + if ( am_hal_gpio_out_enable_bit_get(psLEDs[ui32LEDNum].ui32GPIONumber) ) + { + // + // If it was enabled, turn if off. + // + am_hal_gpio_out_enable_bit_clear(psLEDs[ui32LEDNum].ui32GPIONumber); + } + else + { + // + // If it was not enabled, turn if on. + // + am_hal_gpio_out_enable_bit_set(psLEDs[ui32LEDNum].ui32GPIONumber); + } + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Gets the state of the requested LED. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32LEDNum is the LED to check. +//! +//! This function checks the state of a single LED. +//! +//! @return true if the LED is on. +// +//***************************************************************************** +bool +am_devices_led_get(am_devices_led_t *psLEDs, uint32_t ui32LEDNum) +{ + if ( (psLEDs == NULL) || + (ui32LEDNum >= MAX_LEDS) || + (psLEDs[ui32LEDNum].ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS) ) + { + return false; // No error return, so return as off + } + +#if AM_APOLLO3_GPIO + uint32_t ui32Ret, ui32Value; + am_hal_gpio_read_type_e eReadType; + + eReadType = AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ? + AM_HAL_GPIO_OUTPUT_READ : AM_HAL_GPIO_ENABLE_READ; + + ui32Ret = am_hal_gpio_state_read(psLEDs[ui32LEDNum].ui32GPIONumber, + eReadType, &ui32Value); + + if ( ui32Ret == AM_HAL_STATUS_SUCCESS ) + { + return (bool)ui32Value; + } + else + { + return false; + } +#else // AM_APOLLO3_GPIO + // + // Handle Direct Drive Versus 3-State (with pull-up or no buffer). + // + if ( AM_DEVICES_LED_POL_DIRECT_DRIVE_M & psLEDs[ui32LEDNum].ui32Polarity ) + { + // + // Mask to the GPIO bit position for this GPIO number. + // + uint64_t ui64Mask = ((uint64_t)0x01l) << psLEDs[ui32LEDNum].ui32GPIONumber; + + // + // Extract the state of this bit and return it. + // + return !!(am_hal_gpio_out_read() & ui64Mask); + } + else + { + return am_hal_gpio_out_enable_bit_get(psLEDs[ui32LEDNum].ui32GPIONumber); + } +#endif // AM_APOLLO3_GPIO +} + +//***************************************************************************** +// +//! @brief Display a binary value using LEDs. +//! +//! @param psLEDs is an array of LED structures. +//! @param ui32NumLEDs is the number of LEDs in the array. +//! @param ui32Value is the value to display on the LEDs. +//! +//! This function displays a value in binary across an array of LEDs. +//! +//! @return true if the LED is on. +// +//***************************************************************************** +void +am_devices_led_array_out(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs, + uint32_t ui32Value) +{ + uint32_t i; + + for ( i = 0; i < ui32NumLEDs; i++ ) + { + if ( ui32Value & (1 << i) ) + { + am_devices_led_on(psLEDs, i); + } + else + { + am_devices_led_off(psLEDs, i); + } + } +} +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.h b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.h new file mode 100644 index 0000000000..1a518f06f7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/devices/am_devices_led.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +//! @file am_devices_led.h +//! +//! @brief Functions for controlling an array of LEDs +//! +//! @addtogroup devices External Device Control Library +//! @addtogroup LED SPI Device Control for programmable LEDs. +//! @ingroup devices +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_DEVICES_LED_H +#define AM_DEVICES_LED_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// LED polarity macros +// +//***************************************************************************** +#define AM_DEVICES_LED_POL_POLARITY_M 0x1 +#define AM_DEVICES_LED_ON_HIGH 0x1 +#define AM_DEVICES_LED_ON_LOW 0x0 + +//***************************************************************************** +// +// LED direct drive indicator macro +// Or this in with the polarity value to use the GPIO DATA register instead of +// the GPIO DATA ENABLE register to directly drive an LED buffer. +// +//***************************************************************************** +#define AM_DEVICES_LED_POL_DIRECT_DRIVE_M 0x2 + +//***************************************************************************** +// +// Structure for keeping track of LEDs +// +//***************************************************************************** +typedef struct +{ + uint32_t ui32GPIONumber; + uint32_t ui32Polarity; +} +am_devices_led_t; + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_devices_led_init(am_devices_led_t *psLED); +extern void am_devices_led_array_init(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs); +extern void am_devices_led_array_disable(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs); +extern void am_devices_led_on(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern void am_devices_led_off(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern void am_devices_led_toggle(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern bool am_devices_led_get(am_devices_led_t *psLEDs, uint32_t ui32LEDNum); +extern void am_devices_led_array_out(am_devices_led_t *psLEDs, uint32_t ui32NumLEDs, + uint32_t ui32Value); +#ifdef __cplusplus +} +#endif + +#endif // AM_DEVICES_LED_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util.h new file mode 100644 index 0000000000..35e8941aea --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util.h @@ -0,0 +1,77 @@ +//***************************************************************************** +// +//! @file am_util.h +//! +//! @brief Top Include for all of the utilities +//! +//! This file provides all the includes necessary to use the utilities. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_H +#define AM_UTIL_H + +//***************************************************************************** +// +// C99 +// +//***************************************************************************** +#include +#include + +//***************************************************************************** +// +// Utilities +// +//***************************************************************************** +#include "am_util_debug.h" +#include "am_util_delay.h" +#include "am_util_id.h" +#include "am_util_regdump.h" +#include "am_util_stdio.h" +#include "am_util_string.h" +#include "am_util_time.h" + +#if defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P) +#include "am_util_ble.h" +#endif + +#endif // AM_UTIL_H diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.c new file mode 100644 index 0000000000..691fda6088 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.c @@ -0,0 +1,632 @@ +//***************************************************************************** +// +//! @file am_util_apollo3_ble.c +//! +//! @brief Useful BLE functions not covered by the HAL. +//! +//! This file contains functions for interacting with the Apollo3 BLE hardware +//! that are not already covered by the HAL. Most of these commands either +//! adjust RF settings or facilitate RF testing operations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include "am_util_delay.h" +#include "am_mcu_apollo.h" + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** + +//***************************************************************************** +// +// In DTM mode, set TX to constant trans mode for SRRC/FCC/CE +//set enable as 'true' to constant trans mode, 'false' back to normal +//***************************************************************************** +uint32_t +am_util_ble_set_constant_transmission(void *pHandle, bool enable) +{ + am_hal_ble_state_t *pBLE = pHandle; + + am_hal_ble_sleep_set(pBLE, false); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + if ( enable ) + { + am_hal_ble_plf_reg_write(pBLE, 0x508000E0, 0x00008000); + } + else + { + am_hal_ble_plf_reg_write(pBLE, 0x508000E0, 0x00000000); + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Manually enable/disable transmitter +// set ui8TxCtrl as 1 to manually enable transmitter, 0 back to default +// +//***************************************************************************** +uint32_t +am_util_ble_transmitter_control(void *pHandle, uint8_t ui8TxCtrl) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueTRX; + + am_hal_ble_sleep_set(pBLE, false); + if (ui8TxCtrl) + { + RegValueTRX = 0x2000A; + } + else + { + RegValueTRX = 0x8; + } + + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + am_hal_ble_plf_reg_write(pBLE, 0x52400000, RegValueTRX); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to fix the channel 1 bug in DTM mode +// +//***************************************************************************** + +uint32_t +am_util_ble_init_rf_channel(void *pHandle) +{ + if (!APOLLO3_GE_B0) + { + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + am_hal_ble_sleep_set(pBLE, false); + + //issue the HCI command with to init for the channel 1 + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1d; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x01; + sWriteCommand.bytes[4] = 0x00; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 5); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + am_util_delay_ms(10); + + // issue the HCI command with to stop test for the channel 1 + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1f; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x00; + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 4); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + } + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// BLE init for BQB test +//set enable as 'true' to init as BQB test mode, 'false' back to default +//***************************************************************************** +uint32_t +am_util_ble_BQB_test_init(void *pHandle, bool enable) +{ + am_hal_ble_state_t *pBLE = pHandle; + + am_hal_ble_sleep_set(pBLE, false); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + + if ( enable ) + { + am_hal_ble_plf_reg_write(pBLE, 0x51800028, 0x0000209c); + } + else + { + am_hal_ble_plf_reg_write(pBLE, 0x51800028, 0x00003ff6); + } + + am_hal_ble_plf_reg_write(pBLE, 0x45800070, 0x100); + am_hal_ble_plf_reg_write(pBLE, 0x45800070, 0); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Set the 32M crystal frequency +// based on the tested values at customer side. +// set trim value smaller in case of negative frequency offset +// ui32TrimValue: default is 0x400 +//***************************************************************************** +uint32_t +am_util_ble_crystal_trim_set(void *pHandle, uint32_t ui32TrimValue) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t RegValueMCGR; + + ui32TrimValue &= 0x7FF; + + am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); + // + // Unlock the BLE registers. + // + am_hal_ble_plf_reg_write(pBLE, 0x43000004, 0xFFFFFFFF); + am_hal_ble_plf_reg_write(pBLE, 0x43800004, ui32TrimValue); + am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Manually enable/disable transmitter to output carrier signal +// set ui8TxChannel as 0 to 0x27 for each transmit channel, 0xFF back to normal modulate mode +// +//***************************************************************************** +uint32_t +am_util_ble_hci_reset(void *pHandle) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + am_hal_ble_sleep_set(pBLE, false); + uint32_t ui32Module = pBLE->ui32Module; + + // issue the HCI command with to reset hci + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x03; + sWriteCommand.bytes[2] = 0x0c; + sWriteCommand.bytes[3] = 0x00; + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 4); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 1000; i++) + { + if ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0 ) + { + break; + } + else if (i == (1000 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to do directly output modulation signal. change channel ranges from 0 to 0x27, pattern from 0 to 7. +// +//***************************************************************************** +uint32_t +am_util_ble_trasmitter_test_ex(void *pHandle, uint8_t channel, uint8_t pattern) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + am_hal_ble_sleep_set(pBLE, false); + uint32_t ui32Module = pBLE->ui32Module; + + // issue the HCI command with to TX carrier wave + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1E; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x03; + sWriteCommand.bytes[4] = channel; + sWriteCommand.bytes[5] = 0x25; + sWriteCommand.bytes[6] = pattern; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 7); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 100; i++) + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0) + { + break; + } + else if (i == (100 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to do directly receiver test. change channel ranges from 0 to 0x27, return received packets in 100ms. +// +//***************************************************************************** + +uint32_t +am_util_ble_receiver_test_ex(void *pHandle, uint8_t channel, uint32_t *recvpackets) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + uint32_t ui32Module = pBLE->ui32Module; + am_hal_ble_sleep_set(pBLE, false); + + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1d; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x01; + sWriteCommand.bytes[4] = channel; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 5); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + am_util_delay_ms(100); + +// issue the HCI command with to stop test for the channel 1 + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1f; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x00; + // reserved packet_payload + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 4); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + while ( BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ == 0 ); + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + *recvpackets = (sResponse.bytes[8] << 8) + sResponse.bytes[7]; + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +//to directly output carrier wave. change channel ranges from 0 to 0x27. +// +//***************************************************************************** +uint32_t +am_util_ble_set_carrier_wave_ex(void *pHandle, uint8_t channel) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + // channel 0xFF to disable the constant transmission + if ( channel == 0xFF ) + { + am_util_ble_transmitter_control(pBLE, false); + return AM_HAL_STATUS_SUCCESS; + } + + am_hal_ble_sleep_set(pBLE, false); + uint32_t ui32Module = pBLE->ui32Module; + + // issue the HCI command with to TX carrier wave + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1E; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x03; + sWriteCommand.bytes[4] = channel; + sWriteCommand.bytes[5] = 0x25; + sWriteCommand.bytes[6] = 0x00; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 7); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 100; i++) + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0) + { + break; + } + else if (i == (100 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + am_util_ble_transmitter_control(pBLE, true); + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Manually enable/disable transmitter to output carrier wave signal +// set ui8TxChannel as 0 to 0x27 for each transmit channel, 0xFF back to normal modulate mode +// +//***************************************************************************** +uint32_t +am_util_ble_transmitter_control_ex(void *pHandle, uint8_t ui8TxChannel) +{ + return am_util_ble_set_carrier_wave_ex(pHandle, ui8TxChannel); +} + +//***************************************************************************** +// +//to directly output constant modulation signal. change channel from 0 to 0x27. +// +//***************************************************************************** +uint32_t +am_util_ble_set_constant_transmission_ex(void *pHandle, uint8_t channel) +{ + am_hal_ble_buffer(16) sWriteCommand; + am_hal_ble_buffer(16) sResponse; + am_hal_ble_state_t *pBLE = pHandle; + uint32_t ui32IntEnable; + + // channel 0xFF to disable the constant transmission + if ( channel == 0xFF ) + { + am_util_ble_set_constant_transmission(pBLE, false); + return AM_HAL_STATUS_SUCCESS; + } + + uint32_t ui32Module = pBLE->ui32Module; + am_util_ble_set_constant_transmission(pBLE, true); + + // issue the HCI command with to TX constant transmission + sWriteCommand.bytes[0] = 0x01; + sWriteCommand.bytes[1] = 0x1E; + sWriteCommand.bytes[2] = 0x20; + sWriteCommand.bytes[3] = 0x03; + sWriteCommand.bytes[4] = channel; + sWriteCommand.bytes[5] = 0x25; + sWriteCommand.bytes[6] = 0x00; + + // + // Temporarily disable BLE interrupts. + // + ui32IntEnable = BLEIFn(ui32Module)->INTEN; + BLEIFn(ui32Module)->INTEN = 0; + + am_hal_ble_blocking_hci_write(pBLE, + AM_HAL_BLE_RAW, + sWriteCommand.words, + 7); + BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; + + // + // Wait for the response. + // + for (uint32_t i = 0; i < 100; i++) + { + if (BLEIFn(ui32Module)->BSTATUS_b.BLEIRQ != 0) + { + break; + } + else if (i == (100 - 1)) + { + return AM_HAL_BLE_NO_HCI_RESPONSE; + } + else + { + am_util_delay_ms(1); + } + } + + am_hal_ble_blocking_hci_read(pBLE, sResponse.words, 0); + + // + // Re-enable BLE interrupts. + // + BLEIFn(ui32Module)->INTCLR = ui32IntEnable; + BLEIFn(ui32Module)->INTEN = ui32IntEnable; + + return AM_HAL_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// read current modex value from BLEIP +//***************************************************************************** +uint32_t +am_util_ble_read_modex_value(void *pHandle) +{ + am_hal_ble_state_t *pBLE = pHandle; + uint32_t temp = 0; + if (APOLLO3_GE_B0) + { + // for B0 Chip,the modex value address is changed to 0x20006874 + am_hal_ble_plf_reg_read(pBLE, 0x20006874, &temp); + } + else + { + am_hal_ble_plf_reg_read(pBLE, 0x20006070, &temp); + } + return temp; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.h new file mode 100644 index 0000000000..41b7bf3bf6 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_ble.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +//! @file am_util_apollo3_ble.h +//! +//! @brief Useful BLE functions not covered by the HAL. +//! +//! This file contains functions for interacting with the Apollo3 BLE hardware +//! that are not already covered by the HAL. Most of these commands either +//! adjust RF settings or facilitate RF testing operations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#ifndef AM_UTIL_BLE_H +#define AM_UTIL_BLE_H + +//***************************************************************************** +// +// External function declarations. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +extern uint32_t am_util_ble_set_constant_transmission(void *pHandle, bool enable); +extern uint32_t am_util_ble_transmitter_control(void *pHandle, uint8_t ui8TxCtrl); +extern uint32_t am_util_ble_init_rf_channel(void *pHandle); +extern uint32_t am_util_ble_BQB_test_init(void *pHandle, bool enable); +extern uint32_t am_util_ble_crystal_trim_set(void *pHandle, uint32_t ui32TrimValue); +extern uint32_t am_util_ble_hci_reset(void *pHandle); +extern uint32_t am_util_ble_trasmitter_test_ex(void *pHandle, uint8_t channel, uint8_t pattern); +extern uint32_t am_util_ble_receiver_test_ex(void *pHandle, uint8_t channel, uint32_t *recvpackets); +extern uint32_t am_util_ble_set_carrier_wave_ex(void *pHandle, uint8_t channel); +extern uint32_t am_util_ble_transmitter_control_ex(void *pHandle, uint8_t ui8TxChannel); +extern uint32_t am_util_ble_set_constant_transmission_ex(void *pHandle, uint8_t channel); +extern uint32_t am_util_ble_read_modex_value(void *pHandle); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_BLE_H diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.c new file mode 100644 index 0000000000..2975ff3af1 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.c @@ -0,0 +1,52 @@ +//***************************************************************************** +// +//! @file am_util_debug.c +//! +//! @brief Useful functions for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include "am_util_debug.h" diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.h new file mode 100644 index 0000000000..8ca2a3cea3 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_debug.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +//! @file am_util_debug.h +//! +//! @brief Useful functions for debugging. +//! +//! These functions and macros were created to assist with debugging. They are +//! intended to be as unintrusive as possible and designed to be removed from +//! the compilation of a project when they are no longer needed. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_DEBUG_H +#define AM_UTIL_DEBUG_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Debug printf macros. +// +//***************************************************************************** +#ifdef AM_DEBUG_PRINTF + +#define am_util_debug_printf_init(x) \ + am_util_stdio_printf_init(x); + +#define am_util_debug_printf(...) \ + am_util_stdio_printf(__VA_ARGS__); + +#else + +#define am_util_debug_printf_init(...) +#define am_util_debug_printf(...) + +#endif // AM_DEBUG_PRINTF + +//***************************************************************************** +// +// Debug trace macros. +// +//***************************************************************************** +#ifdef AM_DEBUG_TRACE + +#define am_util_debug_trace_init(PinNumber) \ + do \ + { \ + am_hal_gpio_out_bit_clear(PinNumber); \ + am_hal_gpio_pin_config(PinNumber, AM_HAL_GPIO_OUTPUT); \ + } \ + while(0) + + +#define am_util_debug_trace_start(PinNumber) \ + am_hal_gpio_out_bit_set(PinNumber) + +#define am_util_debug_trace_end(PinNumber) \ + am_hal_gpio_out_bit_clear(PinNumber) + +#else + +#define am_util_debug_trace_init(PinNumber) +#define am_util_debug_trace_start(PinNumber) +#define am_util_debug_trace_end(PinNumber) + +#endif // AM_DEBUG_TRACE + + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_DEBUG_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.c new file mode 100644 index 0000000000..7eba513d6d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.c @@ -0,0 +1,138 @@ +//***************************************************************************** +// +//! @file am_util_delay.c +//! +//! @brief A few useful delay functions. +//! +//! Functions for fixed delays. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_mcu_apollo.h" +#include "am_util_delay.h" + +//***************************************************************************** +// +//! @brief Delays for a desired amount of loops. +//! +//! @param ui32CycleLoops - Desired number of cycle loops to delay for. +//! +//! This function will delay for a number of cycle loops. +//! +//! @note - the number of cycles each loops takes to execute is approximately 3. +//! Therefore the actual number of cycles executed will be ~3x ui32CycleLoops. +//! +//! For example, a ui32CycleLoops value of 100 will delay for 300 cycles. +//! +//! @returns None +// +//***************************************************************************** +void +am_util_delay_cycles(uint32_t ui32Iterations) +{ + // + // Call the BOOTROM cycle delay function + // + am_hal_flash_delay(ui32Iterations); +} + +//***************************************************************************** +// +//! @brief Delays for a desired amount of milliseconds. +//! +//! @param ui32MilliSeconds - number of milliseconds to delay for. +//! +//! This function will delay for a number of milliseconds. +//! +//! @returns None +// +//***************************************************************************** +void +am_util_delay_ms(uint32_t ui32MilliSeconds) +{ + uint32_t ui32Loops, ui32HFRC; +#if AM_APOLLO3_CLKGEN + am_hal_clkgen_status_t sClkgenStatus; + am_hal_clkgen_status_get(&sClkgenStatus); + ui32HFRC = sClkgenStatus.ui32SysclkFreq; +#else // AM_APOLLO3_CLKGEN + ui32HFRC = am_hal_clkgen_sysclk_get(); +#endif // AM_APOLLO3_CLKGEN + ui32Loops = ui32MilliSeconds * (ui32HFRC / 3000); + + // + // Call the BOOTROM cycle delay function + // + am_hal_flash_delay(ui32Loops); +} + +//***************************************************************************** +// +//! @brief Delays for a desired amount of microseconds. +//! +//! @param ui32MicroSeconds - number of microseconds to delay for. +//! +//! This function will delay for a number of microseconds. +//! +//! @returns None +// +//***************************************************************************** +void +am_util_delay_us(uint32_t ui32MicroSeconds) +{ + uint32_t ui32Loops, ui32HFRC; + +#if AM_APOLLO3_CLKGEN + am_hal_clkgen_status_t sClkgenStatus; + am_hal_clkgen_status_get(&sClkgenStatus); + ui32HFRC = sClkgenStatus.ui32SysclkFreq; +#else // AM_APOLLO3_CLKGEN + ui32HFRC = am_hal_clkgen_sysclk_get(); +#endif // AM_APOLLO3_CLKGEN + ui32Loops = ui32MicroSeconds * (ui32HFRC / 3000000); + + // + // Call the BOOTROM cycle delay function + // + am_hal_flash_delay(ui32Loops); +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.h new file mode 100644 index 0000000000..034d378197 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_delay.h @@ -0,0 +1,69 @@ +//***************************************************************************** +// +//! @file am_util_delay.h +//! +//! @brief A few useful delay functions +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_DELAY_H +#define AM_UTIL_DELAY_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_util_delay_cycles(uint32_t ui32Iterations); +extern void am_util_delay_ms(uint32_t ui32MilliSeconds); +extern void am_util_delay_us(uint32_t ui32MicroSeconds); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_DELAY_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.c new file mode 100644 index 0000000000..8ee0435fa0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.c @@ -0,0 +1,220 @@ +//***************************************************************************** +// +//! @file am_util_id.c +//! +//! @brief Identification of the Ambiq Micro device. +//! +//! This module contains functions for run time identification of Ambiq Micro +//! devices. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_util_id.h" + + +//***************************************************************************** +// +// Globals. +// +//***************************************************************************** +// +// Strings for use with pui8VendorName. +// +static const uint8_t g_DeviceNameApollo[] = "Apollo"; +static const uint8_t g_DeviceNameApollo2[] = "Apollo2"; +static const uint8_t g_DeviceNameApollo3[] = "Apollo3 Blue"; +static const uint8_t g_DeviceNameApollo3p[] = "Apollo3 Blue Plus"; +static const uint8_t g_ui8VendorNameAmbq[] = "AMBQ"; +static const uint8_t g_ui8VendorNameUnknown[] = "????"; +static const uint8_t g_ui8DeviceNameUnknown[] = "Unknown device"; + +//***************************************************************************** +// Return the major version of the chip rev. +// Returns: 'A', 'B', 'C', ... +//***************************************************************************** +static uint32_t +revmaj_get(uint32_t ui32ChipRev) +{ + uint32_t ui32ret; + +#ifdef _FLD2VAL + ui32ret = _FLD2VAL(MCUCTRL_CHIPREV_REVMAJ, ui32ChipRev); +#else + ui32ret = (ui32ChipRev & 0xF0) >> 4; +#endif + + // + // Major revision is 1=A, 2=B, 3=C, ... + // Convert to the expected return value. + // + return ui32ret + 'A' - 1; + +} // revmaj_get() + +//***************************************************************************** +// Update the ID structure with the appropriate ChipRev letter. +// ui32minrevbase should be 0 for Apollo or Apollo2, 1 for Apollo3. +//***************************************************************************** +static void +chiprev_set(am_util_id_t *psIDDevice, uint32_t ui32minrevbase) +{ + uint32_t ui32maj, ui32min; + + ui32maj = ((psIDDevice->sMcuCtrlDevice.ui32ChipRev & 0xF0) >> 4); + psIDDevice->ui8ChipRevMaj = (uint8_t)('A' - 1 + ui32maj); + + // + // For Apollo and Apollo2: rev0=0, rev1=1, ... (0-based) + // For Apollo3: rev0=1, rev1=2, ... (1-based) + // + ui32min = ((psIDDevice->sMcuCtrlDevice.ui32ChipRev & 0x0F) >> 0); + psIDDevice->ui8ChipRevMin = (uint8_t)('0' + ui32min - ui32minrevbase); + +} // chiprev_set() + +//***************************************************************************** +// +//! @brief Device identification. +//! +//! @param psIDDevice - ptr to a device ID structure (am_util_id_t*) to be +//! filled in by the function. +//! +//! This function provides additional information about the currently running +//! Ambiq Micro MCU device. +//! +//! @returns The ui32Device value, which is a value corresponding to the +//! device type. +// +//***************************************************************************** +uint32_t +am_util_id_device(am_util_id_t *psIDDevice) +{ + uint32_t ui32PN, ui32ChipRev; + + // + // Go get all the device (hardware) info from the HAL + // +#if AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &psIDDevice->sMcuCtrlDevice); +#else // AM_APOLLO3_MCUCTRL + am_hal_mcuctrl_device_info_get(&psIDDevice->sMcuCtrlDevice); +#endif // AM_APOLLO3_MCUCTRL + + // + // Device identification + // + ui32PN = psIDDevice->sMcuCtrlDevice.ui32ChipPN & + AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_PN_M; + ui32ChipRev = psIDDevice->sMcuCtrlDevice.ui32ChipRev; + + if ( (psIDDevice->sMcuCtrlDevice.ui32JedecCID == 0xB105100D) && + (psIDDevice->sMcuCtrlDevice.ui32JedecJEPID == 0x0000009B) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0xF00) != 0xE00) ) + { + // + // It's Ambiq Micro, set up the VENDORID. + // + psIDDevice->pui8VendorName = g_ui8VendorNameAmbq; + } + else + { + // + // For now, set it as unknown vendor, but we may change it later. + // + psIDDevice->pui8VendorName = g_ui8VendorNameUnknown; + } + + if ( psIDDevice->sMcuCtrlDevice.ui32VendorID == + (('A' << 24) | ('M' << 16) | ('B' << 8) | ('Q' << 0)) ) + { + // + // VENDORID is AMBQ, so set the string pointer. + // + psIDDevice->pui8VendorName = g_ui8VendorNameAmbq; + } + + if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO ) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0E0) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO; + psIDDevice->pui8DeviceName = g_DeviceNameApollo; + chiprev_set(psIDDevice, 0); + + // + // Force the vendor name for Apollo, which did not support VENDORID. + // + psIDDevice->pui8VendorName = g_ui8VendorNameAmbq; + } + else if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2 ) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0D0) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO2; + psIDDevice->pui8DeviceName = g_DeviceNameApollo2; + chiprev_set(psIDDevice, 0); + } + else if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3 ) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0C0) && + ( revmaj_get(ui32ChipRev) <= 'B' ) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO3; + psIDDevice->pui8DeviceName = g_DeviceNameApollo3; + chiprev_set(psIDDevice, 1); + } + else if ( ( ui32PN == AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3P) && + ((psIDDevice->sMcuCtrlDevice.ui32JedecPN & 0x0F0) == 0x0C0) && + ( revmaj_get(ui32ChipRev) == 'C' ) ) + { + psIDDevice->ui32Device = AM_UTIL_ID_APOLLO3P; + psIDDevice->pui8DeviceName = g_DeviceNameApollo3p; + chiprev_set(psIDDevice, 1); + } + else + { + psIDDevice->ui32Device = AM_UTIL_ID_UNKNOWN; + psIDDevice->pui8DeviceName = g_ui8DeviceNameUnknown; + psIDDevice->ui8ChipRevMaj = (uint8_t)'?'; + psIDDevice->ui8ChipRevMin = (uint8_t)' '; + } + + return psIDDevice->ui32Device; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.h new file mode 100644 index 0000000000..bddf98f39d --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_id.h @@ -0,0 +1,133 @@ +//***************************************************************************** +// +//! @file am_util_id.h +//! +//! @brief Identification of the Ambiq Micro device. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_ID_H +#define AM_UTIL_ID_H + +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! ID structure +// +//***************************************************************************** +typedef struct +{ + // + //! Contains the HAL hardware information about the device. + // + am_hal_mcuctrl_device_t sMcuCtrlDevice; + + // + //! Device type (derived value, not a hardware value) + // + uint32_t ui32Device; + + // + //! Vendor name from the MCUCTRL VENDORID register and stringized here. + // + const uint8_t *pui8VendorName; + + // + //! Device name (derived value, not a hardware value) + // + const uint8_t *pui8DeviceName; + + // + // Major chip revision (e.g. char 'A' or 'B') + // + uint8_t ui8ChipRevMaj; + + // + // Minor chip revision (e.g. char '0', '1', ' ') + // + uint8_t ui8ChipRevMin; +} +am_util_id_t; + +//***************************************************************************** +// +// Macros for MCUCTRL CHIP_INFO field. +// Note - these macros are derived from the Apollo2 auto-generated register +// definitions. +// +//***************************************************************************** +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3P 0x07000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO3 0x06000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLOBL 0x05000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO2 0x03000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_APOLLO 0x01000000 +#define AM_UTIL_MCUCTRL_CHIP_INFO_PARTNUM_PN_M 0xFF000000 + +//***************************************************************************** +// +// Macros for silicon identification +// +//***************************************************************************** +#define AM_UTIL_ID_UNKNOWN 0 +#define AM_UTIL_ID_APOLLO 0x0001 +#define AM_UTIL_ID_APOLLO2 0x0002 +#define AM_UTIL_ID_APOLLO3 0x0003 // Apollo3 Blue +#define AM_UTIL_ID_APOLLO3P 0x0103 // Apollo3 Blue Plus + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern uint32_t am_util_id_device(am_util_id_t *psIDDevice); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_ID_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_regdump.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_regdump.h new file mode 100644 index 0000000000..9b50aebd01 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_regdump.h @@ -0,0 +1,185 @@ +//***************************************************************************** +// +//! @file am_util_regdump.h +//! +//! @brief Dump specified registers for debug purposes. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_REGDUMP_H +#define AM_UTIL_REGDUMP_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "am_mcu_apollo.h" + +// +// Apollo peripherals +// +#define AM_UTIL_REGDUMP_ADC (1 << 0) +#define AM_UTIL_REGDUMP_CLKGEN (1 << 1) +#define AM_UTIL_REGDUMP_CTIMER (1 << 2) +#define AM_UTIL_REGDUMP_GPIO (1 << 3) +#define AM_UTIL_REGDUMP_IOM (1 << 4) +#define AM_UTIL_REGDUMP_IOS (1 << 5) +#define AM_UTIL_REGDUMP_MCUCTRL (1 << 6) +#define AM_UTIL_REGDUMP_RSTGEN (1 << 7) +#define AM_UTIL_REGDUMP_RTC (1 << 8) +#define AM_UTIL_REGDUMP_UART (1 << 9) +#define AM_UTIL_REGDUMP_VCOMP (1 << 10) +#define AM_UTIL_REGDUMP_WDT (1 << 11) + +// +// Apollo2 new peripherals +// +#define AM_UTIL_REGDUMP_CACHE (1 << 12) +#define AM_UTIL_REGDUMP_PDM (1 << 13) +#define AM_UTIL_REGDUMP_PWRCTRL (1 << 14) + +// +// Apollo3 new peripherals +// +#define AM_UTIL_REGDUMP_BLE (1 << 15) +#define AM_UTIL_REGDUMP_MSPI (1 << 16) + + +#define AM_UTIL_REGDUMP_INFO0 (1 << 24) + +// +// ARM Core blocks +// +#define AM_UTIL_REGDUMP_ITM (1 << 25) +#define AM_UTIL_REGDUMP_NVIC (1 << 26) +#define AM_UTIL_REGDUMP_SYSCTRL (1 << 27) +#define AM_UTIL_REGDUMP_SYSTICK (1 << 28) +#define AM_UTIL_REGDUMP_TPIU (1 << 29) + + + +//***************************************************************************** +// +// Module mask definitions +// +//***************************************************************************** +#define AM_UTIL_REGDUMP_APOLLO \ + ( AM_UTIL_REGDUMP_ADC | \ + AM_UTIL_REGDUMP_CLKGEN | \ + AM_UTIL_REGDUMP_CTIMER | \ + AM_UTIL_REGDUMP_GPIO | \ + AM_UTIL_REGDUMP_IOM | \ + AM_UTIL_REGDUMP_IOS | \ + AM_UTIL_REGDUMP_MCUCTRL | \ + AM_UTIL_REGDUMP_RSTGEN | \ + AM_UTIL_REGDUMP_RTC | \ + AM_UTIL_REGDUMP_UART | \ + AM_UTIL_REGDUMP_VCOMP | \ + AM_UTIL_REGDUMP_WDT ) + +#define AM_UTIL_REGDUMP_APOLLO2 \ + ( AM_UTIL_REGDUMP_CACHE | \ + AM_UTIL_REGDUMP_PDM | \ + AM_UTIL_REGDUMP_PWRCTRL ) + +#define AM_UTIL_REGDUMP_CORE \ + ( AM_UTIL_REGDUMP_ITM | \ + AM_UTIL_REGDUMP_NVIC | \ + AM_UTIL_REGDUMP_SYSCTRL | \ + AM_UTIL_REGDUMP_SYSTICK | \ + AM_UTIL_REGDUMP_TPIU ) + +// +// Get a register dump of ALL modules in a block. +// +#ifdef AM_PART_APOLLO +#define AM_UTIL_REGDUMP_ALL \ + ( AM_UTIL_REGDUMP_APOLLO | \ + AM_UTIL_REGDUMP_CORE ) +#endif // PART_APOLLO + +#if defined(AM_PART_APOLLO2) || defined(AM_PART_APOLLO3) || defined(AM_PART_APOLLO3P) +#define AM_UTIL_REGDUMP_ALL \ + ( AM_UTIL_REGDUMP_APOLLO | \ + AM_UTIL_REGDUMP_APOLLO2 | \ + AM_UTIL_REGDUMP_CORE ) +#endif // PART_APOLLO + +// +// Get a register dump of ALL modules in a block. +// +#define AM_UTIL_REGDUMP_MOD_ALL 0xFFFFFFFF + +// +// This macro determines a mask given the first and last modules desired. e.g. +// REGDUMP_MOD_MASK(2,4) // Dump regs for modules 2, 3, and 4 +// +#define REGDUMP_MOD_MASK(modfirst, modlast) \ + (((1 << (modlast - modfirst + 1)) - 1) << modfirst) + +// +// These macros determine a single module. e.g. +// REGDUMP_MOD2 | REGDUMP_MOD4 // Dump regs for modules 2 and 4 (skip 3) +// +#define REGDUMP_MOD(n) (1 << n) +#define REGDUMP_MOD0 (REGDUMP_MOD(0)) +#define REGDUMP_MOD1 (REGDUMP_MOD(1)) +#define REGDUMP_MOD2 (REGDUMP_MOD(2)) +#define REGDUMP_MOD3 (REGDUMP_MOD(3)) +#define REGDUMP_MOD4 (REGDUMP_MOD(4)) +#define REGDUMP_MOD5 (REGDUMP_MOD(5)) +#define REGDUMP_MOD6 (REGDUMP_MOD(6)) +#define REGDUMP_MOD7 (REGDUMP_MOD(7)) + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_util_regdump_print(uint32_t ui32PeriphMask, uint32_t ui32ModuleMask); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_REGDUMP_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.c new file mode 100644 index 0000000000..2352e72ff7 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.c @@ -0,0 +1,1258 @@ +//***************************************************************************** +// +//! @file am_util_stdio.c +//! +//! @brief A few printf-style functions for use with Ambiq products +//! +//! Functions for performing printf-style operations without dynamic memory +//! allocation. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include "am_util_stdio.h" + +//***************************************************************************** +// +// Global Variables +// +//***************************************************************************** + +// function pointer for printf +am_util_stdio_print_char_t g_pfnCharPrint; + +// buffer for printf +static char g_prfbuf[AM_PRINTF_BUFSIZE]; + +// Flag to do conversion of '\n' to '\n\r' in sprintf() +static bool g_bTxtXlate = false; + +//***************************************************************************** +// +//! @brief Sets the interface for printf calls. +//! +//! @param pfnCharPrint - Function pointer to be used to print to interface +//! +//! This function initializes the global print function which is used for +//! printf. This allows users to define their own printf interface and pass it +//! in as a am_util_stdio_print_char_t type. +//! +//! @return None. +// +//***************************************************************************** +void +am_util_stdio_printf_init(am_util_stdio_print_char_t pfnCharPrint) +{ + g_pfnCharPrint = pfnCharPrint; +} + +//***************************************************************************** +// +//! @brief Converts strings to 32-bit unsigned integers. +//! +//! @param *str - Pointer to the string to convert +//! @param **endptr - strtoul will set this to the char after the converted num +//! @param base - Base of the number as written in the input string. +//! +//! This function was implemented in a way similar to the strtoul function +//! found in the C standard library. It will attempt to extract a numerical +//! value from the input string, and return it to the caller. Invalid input +//! strings will return a value of zero. +//! +//! @return uint32_t representing the numerical value from the string. +// +//***************************************************************************** +uint32_t +am_util_stdio_strtoul(const char *str, char **endptr, int base) +{ + char *pos; + uint32_t ui32BaseVal; + uint32_t ui32RetVal; + + // + // Prepare a pointer to start advancing through the string. + // + pos = (char *)str; + + // + // Determine what base we are using. Default to '16', but change to other + // values as specified by the user. If the user didn't specify anything, + // try to guess the base value from looking at the first few characters of + // the input + // + ui32BaseVal = 16; + + // + // Switch to octal for a leading zero + // + if (*pos == '0') + { + ui32BaseVal = 8; + pos++; + + // + // Switch back to hex for a leading '0x' + // + if (*pos == 'x') + { + ui32BaseVal = 16; + pos++; + } + } + + // + // No matter what, if the user specified a base value, use that as the real + // base value. + // + if (base) + { + ui32BaseVal = base; + } + + // + // Start accumulating the converted integer value + // + ui32RetVal = 0; + + // + // Loop through the digits, one character at a time. End the loop if the + // number is out of range + // + while ((*pos >= 'a' && *pos <= 'f' && ui32BaseVal == 16) || + (*pos >= 'A' && *pos <= 'F' && ui32BaseVal == 16) || + (*pos >= '0' && *pos <= '9')) + { + // + // Make sure to stop if we hit a NULL byte. + // + if (*pos == 0) + { + break; + } + + // + // Multiply by the base value to move up one 'digit' + // + ui32RetVal *= ui32BaseVal; + + // + // Add the value of the next character. + // + if (*pos >= '0' && *pos <= '9') + { + ui32RetVal += *pos - '0'; + } + else if (*pos >= 'A' && *pos <= 'F') + { + ui32RetVal += (*pos - 'A') + 10; + } + else + { + ui32RetVal += (*pos - 'a') + 10; + } + + // + // Grab the next character. + // + pos++; + } + + // + // If we get here, hopefully it means that we have parsed a number + // correctly. The 'pos' pointer should already be pointing at the character + // right after the last valid number, so set the enptr appropriately, and + // return the calculated numerical value of the string. + // + if (endptr) + { + *endptr = pos; + } + + return ui32RetVal; +} + +//***************************************************************************** +// +// Divide an unsigned 32-bit value by 10. +// +// Note: Adapted from Ch10 of Hackers Delight (hackersdelight.org). +// +//***************************************************************************** +static uint64_t +divu64_10(uint64_t ui64Val) +{ + uint64_t q64, r64; + uint32_t q32, r32, ui32Val; + + // + // If a 32-bit value, use the more optimal 32-bit routine. + // + if ( ui64Val >> 32 ) + { + q64 = (ui64Val>>1) + (ui64Val>>2); + q64 += (q64 >> 4); + q64 += (q64 >> 8); + q64 += (q64 >> 16); + q64 += (q64 >> 32); + q64 >>= 3; + r64 = ui64Val - q64*10; + return q64 + ((r64 + 6) >> 4); + } + else + { + ui32Val = (uint32_t)(ui64Val & 0xffffffff); + q32 = (ui32Val>>1) + (ui32Val>>2); + q32 += (q32 >> 4); + q32 += (q32 >> 8); + q32 += (q32 >> 16); + q32 >>= 3; + r32 = ui32Val - q32*10; + return (uint64_t)(q32 + ((r32 + 6) >> 4)); + } +} + +//***************************************************************************** +// +// Return the number of decimal digits in an uint64_t. +// +// example: 10000 return 5, 123 returns 3. +// +//***************************************************************************** +static int +ndigits_in_u64(uint64_t ui64Val) +{ + int iNDigits = ui64Val ? 0 : 1; + + while ( ui64Val ) + { + // + // ui32Val /= 10; + // + ui64Val = divu64_10(ui64Val); + ++iNDigits; + } + + return iNDigits; +} + +//***************************************************************************** +// +// Return the number of decimal digits in a 64-bit integer. +// +// Note: Does not include the '-' sign. +// +// example: -3 returns 1, 3 returns 1, 15 returns 2, -15 returns 2, ... +// +//***************************************************************************** +static int +ndigits_in_i64(int64_t i64Val) +{ + if ( i64Val < 0 ) + { + // + // Get absolute value + // + i64Val = -i64Val; + } + + return ndigits_in_u64((uint64_t) i64Val); +} + +//***************************************************************************** +// +// Return the number of hex digits in an uint64_t. +// +//***************************************************************************** +static int +ndigits_in_hex(uint64_t ui64Val) +{ + int iDigits = ui64Val ? 0 : 1; + + while ( ui64Val ) + { + ui64Val >>= 4; + ++iDigits; + } + + return iDigits; +} + +//***************************************************************************** +// +// Converts a string representing a decimal value to an int32_t. +// +// Returns the int32_t integer value. +// +// Note: If a count of the number of chars is desired, then provide +// pui32CharCnt. +// +//***************************************************************************** +static uint32_t +decstr_to_int(const char *pcStr, uint32_t *pui32CharCnt) +{ + bool bNeg = false; + uint32_t ui32Val = 0, uCnt = 0; + + if ( *pcStr == '-') + { + bNeg = true; + pcStr++; + uCnt++; + } + + while ( *pcStr >= '0' && *pcStr <= '9' ) + { + ++uCnt; + + // + // Multiply accumulated value by 10. + // + ui32Val *= 10; + + // + // Add in the new low digit. + // + ui32Val += (*pcStr - '0'); + pcStr++; + } + + if ( pui32CharCnt ) + { + *pui32CharCnt = uCnt; + } + + return bNeg ? -ui32Val : ui32Val; +} + +//***************************************************************************** +// +// Converts ui64Val to a string. +// Note: pcBuf[] must be sized for a minimum of 21 characters. +// +// Returns the number of decimal digits in the string. +// +// NOTE: If pcBuf is NULL, will compute a return ui64Val only (no chars +// written). +// +//***************************************************************************** +static int +uint64_to_str(uint64_t ui64Val, char *pcBuf) +{ + char tbuf[25]; + int ix = 0, iNumDig = 0; + unsigned uMod; + uint64_t u64Tmp; + + do + { + // + // Divide by 10 + // + u64Tmp = divu64_10(ui64Val); + + // + // Get modulus + // + uMod = ui64Val - (u64Tmp * 10); + + tbuf[ix++] = uMod + '0'; + ui64Val = u64Tmp; + } while ( ui64Val ); + + // + // Save the total number of digits + // + iNumDig = ix; + + // + // Now, reverse the buffer when saving to the caller's buffer. + // + if ( pcBuf ) + { + while ( ix-- ) + { + *pcBuf++ = tbuf[ix]; + } + + // + // Terminate the caller's buffer + // + *pcBuf = 0x00; + } + + return iNumDig; +} + +//***************************************************************************** +// +// Converts ui64Val to a hex string. Alpha chars are lower case. +// Input: +// ui64Val = Value to be converted. +// pcBuf[] must be sized for a minimum of 17 characters. +// +// Returns the number of hex digits required for ui64Val (does not +// include the terminating NULL char in the string). +// +// NOTE: If pcBuf is NULL, will compute a return value only (no chars +// written). +// +//***************************************************************************** +static int +uint64_to_hexstr(uint64_t ui64Val, char *pcBuf, bool bLower) +{ + int iNumDig, ix = 0; + char cCh, tbuf[20]; + + if ( ui64Val == 0 ) + { + tbuf[ix++] = '0'; // Print a '0' + } + + while ( ui64Val ) + { + cCh = ui64Val & 0xf; + + // + // Alpha character + // + if ( cCh > 9 ) + { + cCh += bLower ? 0x27 : 0x7; + } + + tbuf[ix++] = cCh + '0'; + ui64Val >>= 4; + } + + // + // Save the total number of digits + // + iNumDig = ix; + + // + // Now, reverse the buffer when saving to the callers buffer. + // + if (pcBuf) + { + while (ix--) + { + *pcBuf++ = tbuf[ix]; + } + + // + // Terminate the caller's buffer + // + *pcBuf = 0; + } + + return iNumDig; +} + +//***************************************************************************** +// +// Return length of the given string. +// +//***************************************************************************** +static uint32_t +simple_strlen(char *pcBuf) +{ + uint32_t ui32RetVal = 0; + if ( !pcBuf ) + { + return ui32RetVal; + } + + while ( *pcBuf++ ) + { + ui32RetVal++; + } + return ui32RetVal; +} + +//***************************************************************************** +// +// Pad a string buffer with pad characters. +// +//***************************************************************************** +static int32_t +padbuffer(char *pcBuf, uint8_t cPadChar, int32_t i32NumChars) +{ + int32_t i32Cnt = 0; + + if ( i32NumChars <= 0 ) + { + return i32Cnt; + } + + while ( i32NumChars-- ) + { + if ( pcBuf ) + { + *pcBuf++ = cPadChar; + } + i32Cnt++; + } + + return i32Cnt; +} + +//***************************************************************************** +// +//! @brief Text mode translates linefeed (\n) characters to carriage return/ +//! linefeed (CR/LF) combinations in printf() and sprintf() functions. +//! +//! @param bSetTextTranslationMode - true: Do LF to CR/LF translation. +//! false: Don't do the text mode translation. +//! +//! This function causes the printf() and sprintf() functions to translate +//! newline characters (\\n) into CR/LF (\\r\\n) combinations. +//! +//! @return Previous mode. +// +//***************************************************************************** +bool +am_util_stdio_textmode_set(bool bSetTextTranslationMode) +{ + bool bRet = g_bTxtXlate; + + // + // true=cvt LF chars to CR/LF + // + g_bTxtXlate = bSetTextTranslationMode; + + // + // return previous mode. + // + return bRet; +} + +//***************************************************************************** +// +// Float to ASCII text. A basic implementation for providing support for +// single-precision %f. +// +// param +// fValue = Float value to be converted. +// pcBuf = Buffer to place string AND input of buffer size. +// iPrecision = Desired number of decimal places. +// IMPORTANT: On entry, the first 32-bit word of pcBuf must +// contain the size (in bytes) of the buffer! +// The recommended size is at least 16 bytes. +// +// This function performs a basic translation of a floating point single +// precision value to a string. +// +// return Number of chars printed to the buffer. +// +//***************************************************************************** +#define AM_FTOA_ERR_VAL_TOO_SMALL -1 +#define AM_FTOA_ERR_VAL_TOO_LARGE -2 +#define AM_FTOA_ERR_BUFSIZE -3 + +typedef union +{ + int32_t I32; + float F; +} i32fl_t; + +static int ftoa(float fValue, char *pcBuf, int iPrecision) +{ + i32fl_t unFloatValue; + int iExp2, iBufSize; + int32_t i32Significand, i32IntPart, i32FracPart; + char *pcBufInitial, *pcBuftmp; + + iBufSize = *(uint32_t*)pcBuf; + if (iBufSize < 4) + { + return AM_FTOA_ERR_BUFSIZE; + } + + if (fValue == 0.0f) + { + // "0.0" + *(uint32_t*)pcBuf = 0x00 << 24 | ('0' << 16) | ('.' << 8) | ('0' << 0); + return 3; + } + + pcBufInitial = pcBuf; + + unFloatValue.F = fValue; + + iExp2 = ((unFloatValue.I32 >> 23) & 0x000000FF) - 127; + i32Significand = (unFloatValue.I32 & 0x00FFFFFF) | 0x00800000; + i32FracPart = 0; + i32IntPart = 0; + + if (iExp2 >= 31) + { + return AM_FTOA_ERR_VAL_TOO_LARGE; + } + else if (iExp2 < -23) + { + return AM_FTOA_ERR_VAL_TOO_SMALL; + } + else if (iExp2 >= 23) + { + i32IntPart = i32Significand << (iExp2 - 23); + } + else if (iExp2 >= 0) + { + i32IntPart = i32Significand >> (23 - iExp2); + i32FracPart = (i32Significand << (iExp2 + 1)) & 0x00FFFFFF; + } + else // if (iExp2 < 0) + { + i32FracPart = (i32Significand & 0x00FFFFFF) >> -(iExp2 + 1); + } + + if (unFloatValue.I32 < 0) + { + *pcBuf++ = '-'; + } + + if (i32IntPart == 0) + { + *pcBuf++ = '0'; + } + else + { + if (i32IntPart > 0) + { + uint64_to_str(i32IntPart, pcBuf); + } + else + { + *pcBuf++ = '-'; + uint64_to_str(-i32IntPart, pcBuf); + } + while (*pcBuf) // Get to end of new string + { + pcBuf++; + } + } + + // + // Now, begin the fractional part + // + *pcBuf++ = '.'; + + if (i32FracPart == 0) + { + *pcBuf++ = '0'; + } + else + { + int jx, iMax; + + iMax = iBufSize - (pcBuf - pcBufInitial) - 1; + iMax = (iMax > iPrecision) ? iPrecision : iMax; + + for (jx = 0; jx < iMax; jx++) + { + i32FracPart *= 10; + *pcBuf++ = (i32FracPart >> 24) + '0'; + i32FracPart &= 0x00FFFFFF; + } + + // + // Per the printf spec, the number of digits printed to the right of the + // decimal point (i.e. iPrecision) should be rounded. + // Some examples: + // Value iPrecision Formatted value + // 1.36399 Unspecified (6) 1.363990 + // 1.36399 3 1.364 + // 1.36399 4 1.3640 + // 1.36399 5 1.36399 + // 1.363994 Unspecified (6) 1.363994 + // 1.363994 3 1.364 + // 1.363994 4 1.3640 + // 1.363994 5 1.36399 + // 1.363995 Unspecified (6) 1.363995 + // 1.363995 3 1.364 + // 1.363995 4 1.3640 + // 1.363995 5 1.36400 + // 1.996 Unspecified (6) 1.996000 + // 1.996 2 2.00 + // 1.996 3 1.996 + // 1.996 4 1.9960 + // + // To determine whether to round up, we'll look at what the next + // decimal value would have been. + // + if ( ((i32FracPart * 10) >> 24) >= 5 ) + { + // + // Yes, we need to round up. + // Go back through the string and make adjustments as necessary. + // + pcBuftmp = pcBuf - 1; + while ( pcBuftmp >= pcBufInitial ) + { + if ( *pcBuftmp == '.' ) + { + } + else if ( *pcBuftmp == '9' ) + { + *pcBuftmp = '0'; + } + else + { + *pcBuftmp += 1; + break; + } + pcBuftmp--; + } + } + } + + // + // Terminate the string and we're done + // + *pcBuf = 0x00; + + return (pcBuf - pcBufInitial); +} // ftoa() + +//****************************************************************************** +// +//! @brief Format data into string. (va_list implementation) +//! +//! @param *pcBuf - Pointer to the buffer to store the string +//! @param *pcFmt - Pointer to formatter string +//! +//! A lite version of vsprintf(). +//! Currently handles the following specifiers: +//! %c +//! %s +//! %[0][width]d (also %i) +//! %[0][width]u +//! %[0][width]x +//! %[.precision]f +//! +//! Note than any unrecognized or unhandled format specifier character is +//! simply printed. For example, "%%" will print a '%' character. +//! +//! @return uint32_t representing the number of characters printed. +// +//****************************************************************************** +uint32_t +am_util_stdio_vsprintf(char *pcBuf, const char *pcFmt, va_list pArgs) +{ + char *pcStr; + uint64_t ui64Val; + int64_t i64Val; + uint32_t ui32NumChars, ui32CharCnt = 0; + int iWidth, iVal, iPrecision; + uint8_t ui8CharSpecifier, ui8PadChar; + bool bLower, bLongLong, bNeg; + uint32_t ui32strlen = 0; + + while ( *pcFmt != 0x0 ) + { + iPrecision = 6; // printf() default precision for %f is 6 + + if ( *pcFmt != '%' ) + { + // + // Accumulate the string portion of the format specification. + // + if ( pcBuf ) + { + // If '\n', convert to '\r\n' + if ( *pcFmt == '\n' && g_bTxtXlate ) + { + *pcBuf++ = '\r'; + ++ui32CharCnt; + } + *pcBuf++ = *pcFmt; + } + + ++pcFmt; + ++ui32CharCnt; + continue; + } + + // + // Handle the specifier. + // + ++pcFmt; + bLower = bLongLong = false; + + // + // Default to space as ui8PadChar + // + ui8PadChar = ' '; + + if ( *pcFmt == '0' ) + { + ui8PadChar = '0'; + ++pcFmt; + } + + // + // Width specifier + // + iWidth = decstr_to_int(pcFmt, &ui32NumChars); + pcFmt += ui32NumChars; + + // + // For now, only support a negative width specifier for %s + // + if ( ( *pcFmt != 's' ) && ( iWidth < 0 ) ) + { + iWidth = -iWidth; + } + + // + // Check for precision specifier + // + if (*pcFmt == '.') + { + ++pcFmt; + iPrecision = decstr_to_int(pcFmt, &ui32NumChars); + pcFmt += ui32NumChars; + } + + // + // Check for the long or long long length field sub-specifiers, 'l' or + // 'll', which must be a modifier for either 'd', 'i', 'u', 'x', or 'X' + // (or even 'o', which is not currently supported). Other sub-specifiers + // like 'hh','h', etc. are not currently handled. + // Note - 'l' is used in Coremark, a primary reason it's supported here. + // + if ( *pcFmt == 'l' ) + { + pcFmt++; + if ( *pcFmt == 'l' ) // "ll" (long long) + { + pcFmt++; + bLongLong = true; + } + } + + switch ( *pcFmt ) + { + case 'c': + ui8CharSpecifier = va_arg(pArgs, uint32_t); + + if ( pcBuf ) + { + *pcBuf++ = ui8CharSpecifier; + } + + ++ui32CharCnt; + break; + + case 's': + pcStr = va_arg(pArgs, char *); + + // + // For %s, we support the width specifier. If iWidth is negative + // the string is left-aligned (padding on the right). Otherwise + // the string is padded at the beginning with spaces. + // + ui32strlen = simple_strlen(pcStr); + if ( iWidth > 0 ) + { + // Pad the beginning of the string (right-aligned). + if ( ui32strlen < iWidth ) + { + // String needs some padding. + iWidth -= ui32strlen; + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + } + + while (*pcStr != 0x0) + { + if ( pcBuf ) + { + *pcBuf++ = *pcStr; + } + + ++pcStr; + ++ui32CharCnt; + } + + if ( iWidth ) + { + iWidth = -iWidth; + + // Pad the end of the string (left-aligned). + if ( ui32strlen < iWidth ) + { + // String needs some padding. + iWidth -= ui32strlen; + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + } + break; + + case 'x': + bLower = true; + case 'X': + ui64Val = bLongLong ? va_arg(pArgs, uint64_t) : + va_arg(pArgs, uint32_t); + + if ( iWidth ) + { + // + // Compute # of leading chars + // + iWidth -= ndigits_in_hex(ui64Val); + + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + + iVal = uint64_to_hexstr(ui64Val, pcBuf, bLower); + + if ( pcBuf ) + { + pcBuf += iVal; + } + + ui32CharCnt += iVal; + break; + + case 'u': + ui64Val = bLongLong ? va_arg(pArgs, uint64_t) : + va_arg(pArgs, uint32_t); + + if ( iWidth ) + { + // + // We need to pad the beginning of the value. + // Compute # of leading chars + // + iWidth -= ndigits_in_u64(ui64Val); + + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + } + + iVal = uint64_to_str(ui64Val, pcBuf); + + if ( pcBuf ) + { + pcBuf += iVal; + } + + ui32CharCnt += iVal; + break; + + case 'd': + case 'i': + // + // Output for a negative number, for example, -5: + // %d:-5 + // %5d: -5 + // %05d:-0005 + // + i64Val = bLongLong ? va_arg(pArgs, int64_t) : + va_arg(pArgs, int32_t); + + // + // Get absolute value + // + if ( i64Val < 0 ) + { + ui64Val = -i64Val; // Get absolute value + bNeg = true; + } + else + { + ui64Val = i64Val; + bNeg = false; + } + + if ( iWidth ) + { + // + // We need to pad the beginning of the value. + // Compute # of leading chars + // + iWidth -= ndigits_in_i64(ui64Val); + + if ( bNeg ) + { + --iWidth; + + // + // Allow for the negative sign + // + if ( ui8PadChar == '0' ) + { + // + // Print the neg sign BEFORE the leading zeros + // + if ( pcBuf ) + { + *pcBuf++ = '-'; + } + + ++ui32CharCnt; + } + } + + iWidth = padbuffer(pcBuf, ui8PadChar, iWidth); + pcBuf += pcBuf ? iWidth : 0; + ui32CharCnt += iWidth; + iWidth = 0; + + if ( bNeg && (ui8PadChar == ' ') ) + { + // + // Print the neg sign AFTER the leading blanks + // + if ( pcBuf ) + { + *pcBuf++ = '-'; + } + + ++ui32CharCnt; + } + } + else + { + if ( bNeg ) + { + if ( pcBuf ) + { + *pcBuf++ = '-'; + } + ++ui32CharCnt; + } + } + + iVal = uint64_to_str(ui64Val, pcBuf); + + if ( pcBuf ) + { + pcBuf += iVal; + } + + ui32CharCnt += iVal; + break; + + + case 'f': + case 'F': + if ( pcBuf ) + { + float fValue = va_arg(pArgs, double); + + // + // pcBuf is an input (size of buffer) and also an output of ftoa() + // + *(uint32_t*)pcBuf = 20; + + iVal = ftoa(fValue, pcBuf, iPrecision); + if ( iVal < 0 ) + { + uint32_t u32PrntErrVal; + if ( iVal == AM_FTOA_ERR_VAL_TOO_SMALL ) + { + u32PrntErrVal = (0x00 << 24) | ('0' << 16) | + ('.' << 8) | ('0' << 0); // "0.0" + } + else if ( iVal == AM_FTOA_ERR_VAL_TOO_LARGE ) + { + u32PrntErrVal = (0x00 << 24) | ('#' << 16) | + ('.' << 8) | ('#' << 0); // "#.#" + } + else + { + u32PrntErrVal = (0x00 << 24) | ('?' << 16) | + ('.' << 8) | ('?' << 0); // "?.?" + } + *(uint32_t*)pcBuf = u32PrntErrVal; + iVal = 3; + } + ui32CharCnt += iVal; + pcBuf += iVal; + } + break; + + // + // Invalid specifier character + // For non-handled specifiers, we'll just print the character. + // e.g. this will allow the normal printing of a '%' using + // "%%". + // + default: + if ( pcBuf ) + { + *pcBuf++ = *pcFmt; + } + + ++ui32CharCnt; + break; + + } // switch() + + // + // Bump the format specification to the next character + // + ++pcFmt; + + } // while () + + // + // Terminate the string + // + if ( pcBuf ) + { + *pcBuf = 0x0; + } + + return (ui32CharCnt); +} + +//****************************************************************************** +// +//! @brief Format data into string. +//! +//! @param *pcBuf - Pointer to the buffer to store the string +//! @param *pcFmt - Pointer to formater string +//! +//! A lite version of vsprintf(). +//! Currently handles the following specifiers: +//! %c +//! %s +//! %[0][width]d (also %i) +//! %[0][width]u +//! %[0][width]x +//! +//! Note than any unrecognized or unhandled format specifier character is +//! simply printed. For example, "%%" will print a '%' character. +//! +//! @return uint32_t representing the number of characters printed. +// +//****************************************************************************** +uint32_t +am_util_stdio_sprintf(char *pcBuf, const char *pcFmt, ...) +{ + uint32_t ui32CharCnt; + + va_list pArgs; + va_start(pArgs, pcFmt); + ui32CharCnt = am_util_stdio_vsprintf(pcBuf, pcFmt, pArgs); + va_end(pArgs); + + return ui32CharCnt; +} + +//***************************************************************************** +// +//! @brief A lite version of printf() +//! +//! @param *pcFmt - Pointer to formatter string +//! +//! See am_util_stdio_sprintf() for more details. +//! +//! @return uint32_t representing the number of characters printed. +// +// ***************************************************************************** +uint32_t +am_util_stdio_printf(const char *pcFmt, ...) +{ + uint32_t ui32NumChars; + + if (!g_pfnCharPrint) + { + return 0; + } + + // + // Convert to the desired string. + // + va_list pArgs; + va_start(pArgs, pcFmt); + ui32NumChars = am_util_stdio_vsprintf(g_prfbuf, pcFmt, pArgs); + va_end(pArgs); + + // + // This is where we print the buffer to the configured interface. + // + g_pfnCharPrint(g_prfbuf); + + // + // return the number of characters printed. + // + return ui32NumChars; +} + +//***************************************************************************** +// +//! @brief Clear the terminal screen +//! +//! This function clears a standard terminal screen. +//! +//! @return None. +// +//***************************************************************************** +void +am_util_stdio_terminal_clear(void) +{ + // + // Escape codes to clear a terminal screen and put the cursor in the top + // left corner. + // We'll first print a number of spaces, which helps get the ITM in sync + // with AM Flash, especially after a reset event or a system clock + // frequency change. + // + am_util_stdio_printf("\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"); +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.h new file mode 100644 index 0000000000..da046dce9c --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_stdio.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +//! @file am_util_stdio.h +//! +//! @brief A few printf-style functions for use with Ambiq products +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_STDIO_H +#define AM_UTIL_STDIO_H + +/* get va_list from compiler. */ +#include + +#ifdef __cplusplus +extern "C" +{ +#endif +//***************************************************************************** +// +// Macro definitions +// +//***************************************************************************** + +// buffer size for printf +#ifndef AM_PRINTF_BUFSIZE +#define AM_PRINTF_BUFSIZE 256 +#endif + +typedef void (*am_util_stdio_print_char_t)(char *pcStr); + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern void am_util_stdio_printf_init(am_util_stdio_print_char_t pfnCharPrint); +extern uint32_t am_util_stdio_strtoul(const char *str, char **endptr, int base); +extern bool am_util_stdio_textmode_set(bool bSetTextTranslationMode); +extern uint32_t am_util_stdio_vsprintf(char *pcBuf, const char *pcFmt, va_list pArgs); +extern uint32_t am_util_stdio_sprintf(char *pui8Buf, const char *pui8Fmt, ...); +extern uint32_t am_util_stdio_printf(const char *pui8Fmt, ...); +extern void am_util_stdio_terminal_clear(void); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_STDIO_H + diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.c new file mode 100644 index 0000000000..d173f0caf0 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.c @@ -0,0 +1,614 @@ +//***************************************************************************** +// +//! @file am_util_string.c +//! +//! @brief A subset of the functions provided in the C standard string library. +//! +//! The functions here are reimplementation of some of the standard "string" +//! functions. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include "am_util_string.h" + + +//***************************************************************************** +// +//! @brief Table for quick lookup of character attributes. +// +//***************************************************************************** +#if MINIMIZE_CATTR_TABLE +#define CATTR_TBL_SIZE 128 +#else +#define CATTR_TBL_SIZE 256 +#endif + +const uint8_t am_cattr[CATTR_TBL_SIZE] = +{ + AM_CATTR_NONE, /* 0x00 */ + AM_CATTR_NONE, /* 0x01 */ + AM_CATTR_NONE, /* 0x02 */ + AM_CATTR_NONE, /* 0x03 */ + AM_CATTR_NONE, /* 0x04 */ + AM_CATTR_NONE, /* 0x05 */ + AM_CATTR_NONE, /* 0x06 */ + AM_CATTR_NONE, /* 0x07 */ + AM_CATTR_NONE, /* 0x08 */ + AM_CATTR_WHSPACE, /* 0x09 */ + AM_CATTR_WHSPACE, /* 0x0A */ + AM_CATTR_WHSPACE, /* 0x0B */ + AM_CATTR_WHSPACE, /* 0x0C */ + AM_CATTR_WHSPACE, /* 0x0D */ + AM_CATTR_NONE, /* 0x0E */ + AM_CATTR_NONE, /* 0x0F */ + AM_CATTR_NONE, /* 0x00 */ + AM_CATTR_NONE, /* 0x11 */ + AM_CATTR_NONE, /* 0x12 */ + AM_CATTR_NONE, /* 0x13 */ + AM_CATTR_NONE, /* 0x14 */ + AM_CATTR_NONE, /* 0x15 */ + AM_CATTR_NONE, /* 0x16 */ + AM_CATTR_NONE, /* 0x17 */ + AM_CATTR_NONE, /* 0x18 */ + AM_CATTR_NONE, /* 0x19 */ + AM_CATTR_NONE, /* 0x1A */ + AM_CATTR_NONE, /* 0x1B */ + AM_CATTR_NONE, /* 0x1C */ + AM_CATTR_NONE, /* 0x1D */ + AM_CATTR_NONE, /* 0x1E */ + AM_CATTR_NONE, /* 0x1F */ + AM_CATTR_WHSPACE, /* 0x20, space */ + AM_CATTR_FILENM83, /* 0x21, ! */ + AM_CATTR_NONE, /* 0x22, " */ + AM_CATTR_FILENM83, /* 0x23, # */ + AM_CATTR_FILENM83, /* 0x24, $ */ + AM_CATTR_FILENM83, /* 0x25, % */ + AM_CATTR_FILENM83, /* 0x26, & */ + AM_CATTR_FILENM83, /* 0x27, ' */ + AM_CATTR_FILENM83, /* 0x28, ( */ + AM_CATTR_FILENM83, /* 0x29, ) */ + AM_CATTR_NONE, /* 0x2A, * */ + AM_CATTR_NONE, /* 0x2B, + */ + AM_CATTR_NONE, /* 0x2C, , */ + AM_CATTR_FILENM83, /* 0x2D, - */ + AM_CATTR_FILENM83, /* 0x2E, . */ + AM_CATTR_NONE, /* 0x2F, / */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x30, 0 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x31, 1 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x32, 2 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x33, 3 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x34, 4 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x35, 5 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x36, 6 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x37, 7 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x38, 8 */ + AM_CATTR_DIGIT | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x39, 9 */ + AM_CATTR_NONE, /* 0x3A, : */ + AM_CATTR_NONE, /* 0x3B, ; */ + AM_CATTR_NONE, /* 0x3C, < */ + AM_CATTR_NONE, /* 0x3D, = */ + AM_CATTR_NONE, /* 0x3E, > */ + AM_CATTR_NONE, /* 0x3F, ? */ + AM_CATTR_FILENM83, /* 0x40, @ */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x41, A */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x42, B */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x43, C */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x44, D */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x45, E */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x46, F */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x47, G */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x48, H */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x49, I */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4A, J */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4B, K */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4C, L */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4D, M */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4E, N */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x4F, O */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x50, P */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x51, Q */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x52, R */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x53, S */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x54, T */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x55, U */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x56, V */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x57, W */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x58, X */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x59, Y */ + AM_CATTR_ALPHA | AM_CATTR_UPPER | AM_CATTR_FILENM83, /* 0x5A, Z */ + AM_CATTR_NONE, /* 0x5B, [ */ + AM_CATTR_NONE, /* 0x5C, \ */ + AM_CATTR_NONE, /* 0x5D, ] */ + AM_CATTR_FILENM83, /* 0x5E, ^ */ + AM_CATTR_FILENM83, /* 0x5F, _ */ + AM_CATTR_FILENM83, /* 0x60, ` */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x61, a */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x62, b */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x63, c */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x64, d */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x65, e */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_XDIGIT | AM_CATTR_FILENM83, /* 0x66, f */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x67, g */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x68, h */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x69, i */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6A, j */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6B, k */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6C, l */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6D, m */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6E, n */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x6F, o */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x70, p */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x71, q */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x72, r */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x73, s */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x74, t */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x75, u */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x76, v */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x77, w */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x78, x */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x79, y */ + AM_CATTR_ALPHA | AM_CATTR_LOWER | AM_CATTR_FILENM83, /* 0x7A, z */ + AM_CATTR_FILENM83, /* 0x7B, { */ + AM_CATTR_NONE, /* 0x7C, | */ + AM_CATTR_FILENM83, /* 0x7D, } */ + AM_CATTR_FILENM83, /* 0x7E, ~ */ + AM_CATTR_NONE /* 0x7F, delete */ + + // + // All bit7 chars are AM_CATTR_NONE. + // +}; + +//***************************************************************************** +// +//! @brief Character "is" functions +//! +//! This family of functions tests a given integer value in order to determine +//! whether the integer satisfies the test condition. +//! These functions are generally based on the C99 standard functions. +//! +//! By default all of the "is" functions are implemented as macros. To implement +//! as functions rather than macros, use a global compiler command line (-D) +//! option to define AM_UTIL_STRING_CTYPE_DISABLE_MACROS. +//! +//! Standard functions currently implemented include: +//! isalnum(), isalpha(), islower(), isupper(), isdigit(), isxdigit(), +//! isspace(). +//! +//! Standard functions not currently implemented include: +//! iscntrl(), isgraph(), isprint(), ispunct(), isblank() (new for C99). +//! +//! Non-standard functions currently implemented include: +//! isfilenm83(). +//! +//! @return Each function returns a nonzero value if the integer satisfies +//! the test condition and 0 if it does not. +// +//***************************************************************************** + +#ifdef AM_UTIL_STRING_CTYPE_DISABLE_MACROS +int +am_util_string_isalnum(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) ? 1 : 0; +#endif +} + +int +am_util_string_isalpha(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_ALPHA) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_ALPHA) ? 1 : 0; +#endif +} + +int +am_util_string_isdigit(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_DIGIT) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_DIGIT) ? 1 : 0; +#endif +} + +int am_util_string_islower(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_LOWER) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_LOWER) ? 1 : 0; +#endif +} + +int +am_util_string_isspace(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_WHSPACE) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_WHSPACE) ? 1 : 0; +#endif +} + +int +am_util_string_isupper(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_UPPER) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_UPPER) ? 1 : 0; +#endif +} + +int +am_util_string_isxdigit(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_XDIGIT) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_XDIGIT) ? 1 : 0; +#endif +} + +int am_util_string_tolower(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (am_cattr[c & 0x7f] & AM_CATTR_UPPER) ? c | 0x20 : c; +#else + return (am_cattr[c & 0xff] & AM_CATTR_UPPER) ? c | 0x20 : c; +#endif +} + +int am_util_string_toupper(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (am_cattr[c & 0x7f] & AM_CATTR_LOWER) ? c & ~0x20 : c; +#else + return (am_cattr[c & 0xff] & AM_CATTR_LOWER) ? c & ~0x20 : c; +#endif +} + + +// +// Non-standard "is" Functions +// +int +am_util_string_isfilenm83(int c) +{ +#if MINIMIZE_CATTR_TABLE + return (c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_FILENM83) ? 1 : 0; +#else + return (am_cattr[c & 0xff] & AM_CATTR_FILENM83) ? 1 : 0; +#endif +} +#endif // AM_UTIL_STRING_CTYPE_DISABLE_MACROS + + +//***************************************************************************** +// +//! @brief Compare two strings. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! +//! This function steps through a pair of strings, character by character, to +//! determine if the strings contain the same characters. If the strings match, +//! this function will return a zero. If str1 is alphabetically earlier than +//! str2, the return value will be negative. Otherwise, the return value will +//! be positive. +//! +//! @return 0 for a perfect match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_strcmp(const char *str1, const char *str2) +{ + return am_util_string_strncmp(str1, str2, 0xffffffff); +} + +//***************************************************************************** +// +//! @brief Compare two strings with a specified count. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! @param num is the maximum number of characters to compare. +//! +//! This function steps through a pair of strings, character by character, to +//! determine if the strings contain the same characters. If the strings match, +//! this function will return a zero. If str1 is alphabetically earlier than +//! str2, the return value will be negative. Otherwise, the return value will +//! be positive. +//! +//! @return 0 for a perfect match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_strncmp(const char *str1, const char *str2, uint32_t num) +{ + while ( num-- ) + { + // Check for inequality OR end of string + if ( *str1 != *str2 || *str1 == '\0' ) + { + return *str1 - *str2; + } + + str1++; + str2++; + } + + // + // Since we made it here, the strings must be equal to n characters. + // + return 0; +} + +//***************************************************************************** +// +//! @brief Compare two strings with a specified count and without regard to +//! letter case in the strings. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! @param num is the maximum number of characters to compare. +//! +//! This function steps through a pair of strings, character by character, to +//! determine if the strings contain the same characters. If the strings match, +//! this function will return a zero. If str1 is alphabetically earlier than +//! str2, the return value will be negative. Otherwise, the return value will +//! be positive. +//! +//! @return 0 for a perfect match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_strnicmp(const char *str1, const char *str2, int num) +{ + uint8_t cChar1, cChar2; + + while ( *str1 && *str2 && num ) + { + cChar1 = *str1; + cChar2 = *str2; + + cChar1 |= ( am_cattr[cChar1] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + cChar2 |= ( am_cattr[cChar2] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + + if ( cChar1 != cChar2 ) + { + return cChar1 - cChar2; + } + + str1++; + str2++; + num--; + } + + // + // Since we made it here, the strings must be equal to n characters. + // + return 0; +} + +//***************************************************************************** +// +//! @brief Compare two strings with case-insensitivity. +//! +//! @param str1 is the first string to compare. +//! @param str2 is the second string to compare +//! +//! This function compares each character in the 2 strings, converting all +//! alpha characters to lower-case to make the comparison. +//! +//! To illustrate a possible unexpected outcome due to comparing the strings +//! as lower case, consider the example strings "AMBIQ_MICRO" and "AMBIQMICRO". +//! For these strings, stricmp() will return a negative value (indicating the +//! first as before the second), whereas strcmp() will return a positive value. +//! +//! @return 0 for a case-insensitive match, negative value if str1str2. +// +//***************************************************************************** +int32_t +am_util_string_stricmp(const char *str1, const char *str2) +{ + uint8_t cChar1, cChar2; + + while ( *str1 && *str2 ) + { + cChar1 = *str1++; + cChar2 = *str2++; + + cChar1 |= ( am_cattr[cChar1] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + cChar2 |= ( am_cattr[cChar2] & AM_CATTR_UPPER ) ? 0x20 : 0x00; + + if ( cChar1 != cChar2 ) + { + return cChar1 - cChar2; + } + } + + return *str1 - *str2; +} + +//***************************************************************************** +// +//! @brief Return the length of a string. +//! +//! @param pcStr pointer to the string. +//! +//! This function returns the length of the string at pcStr. +//! +//! @return length of the string pcStr. +// +//***************************************************************************** +uint32_t +am_util_string_strlen(const char *pcStr) +{ + const char *pcS; + + // + // Loop through the string. + // + for (pcS = pcStr; *pcS; ++pcS); + + // + // Return the length. + // + return(pcS - pcStr); +} + +//***************************************************************************** +// +//! @brief Copies a string. +//! +//! @param pcDst pointer to the destination string. +//! @param pcSrc pointer to the source string to be copied to pcDst. +//! +//! This function copies pcSrc to the location specified by pcDst. +//! +//! @return pcDst (the location of the destination string). +// +//***************************************************************************** +char * +am_util_string_strcpy(char *pcDst, const char *pcSrc) +{ + char *pcRet = pcDst; + + // + // Blindly copy the string until we hit a terminating NULL char. + // + do + { + *pcDst++ = *pcSrc; + } while ( *pcSrc++ ); + + return pcRet; +} + +//***************************************************************************** +// +//! @brief Copies a specified number of characters of a string. +//! +//! @param pcDst pointer to the destination string. +//! @param pcSrc pointer to the source string to be copied to pcDst. +//! +//! This function copies uNum characters of pcSrc to the location specified +//! by pcDst. +//! If uNum is less than the length of pcSrc, a NULL terminating character +//! is not appended to the copied string. Thus the resultant string will be +//! exactly uNum chars in length and not terminated. +//! If uNum is greater than the length of pcSrc, then pcDst is padded with +//! NULL characters up to the uNum length. +//! Behavior is undefined if the addresses ranges overlap. +//! +//! @return pcDst (the location of the destination string). +// +//***************************************************************************** +char * +am_util_string_strncpy(char *pcDst, const char *pcSrc, uint32_t uNum) +{ + char *pcRet = pcDst; + + while (uNum > 0) + { + if ( *pcSrc ) + { + *pcDst++ = *pcSrc++; + } + else + { + *pcDst++ = 0x00; + } + uNum--; + } + + return pcRet; +} + +//***************************************************************************** +// +//! @brief Concatenate a string. +//! +//! @param pcDst pointer to the destination string. +//! @param pcSrc pointer to the source string to be copied to pcDst. +//! +//! This function concatenates the string at pcSrc to the existing string +//! at pcDst. +//! +//! Both strings, pcDst and pcSrc, must be NULL-terminated. +//! No overflow checking is performed. +//! pcDst and pcSrc shall not overlap. +//! +//! @return pcDst (the location of the destination string). +// +//***************************************************************************** +char * +am_util_string_strcat(char *pcDst, const char *pcSrc) +{ + char *pcRet = pcDst; + + // + // Find the end of the existing string. + // + while ( *pcDst++ ); + pcDst--; + + // + // Now, copy the new string. + // + am_util_string_strcpy(pcDst, pcSrc); + + return pcRet; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.h new file mode 100644 index 0000000000..b39ceb4202 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_string.h @@ -0,0 +1,162 @@ +//***************************************************************************** +// +//! @file am_util_string.h +//! +//! @brief A subset of the functions provided in the C standard string library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_STRING_H +#define AM_UTIL_STRING_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Character attributes lookup table defines. +// +//***************************************************************************** +#define AM_CATTR_NONE 0x00 +#define AM_CATTR_ALPHA 0x01 +#define AM_CATTR_LOWER 0x02 +#define AM_CATTR_UPPER 0x04 +#define AM_CATTR_DIGIT 0x08 +#define AM_CATTR_XDIGIT 0x10 +#define AM_CATTR_WHSPACE 0x20 +#define AM_CATTR_FILENM83 0x80 + +// +// Set MINIMIZE_CATTR_TABLE to 1 to configure for minimal CATTR table size, +// (256 instead of 512 bytes) but at a cost of slightly larger code size. +// However, setting this option also provides an additional level of checking +// of the argument; if the argument is not a uint8_t, the functions are +// guaranteed to return 0. +// +#define MINIMIZE_CATTR_TABLE 0 + + +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +extern const uint8_t am_cattr[]; + + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern int32_t am_util_string_strcmp(const char *str1, const char *str2); +extern int32_t am_util_string_stricmp(const char *str1, const char *str2); +extern int32_t am_util_string_strncmp(const char *str1, const char *str2, + uint32_t num); +extern int32_t am_util_string_strnicmp(const char *str1, const char *str2, + int num); +extern uint32_t am_util_string_strlen(const char *pcStr); +extern char *am_util_string_strcpy(char *pcDst, const char *pcSrc); +extern char *am_util_string_strncpy(char *pcDst, const char *pcSrc, uint32_t uNum); +extern char *am_util_string_strcat(char *pcDst, const char *pcSrc); + + +//***************************************************************************** +// +// Character "is" macros and functions +// +//***************************************************************************** +// +// By default all of the "is" functions are implemented as macros. To implement +// as functions rather than macros, use a global compiler command line (-D) +// option to define AM_UTIL_STRING_CTYPE_DISABLE_MACROS. +// +#ifdef AM_UTIL_STRING_CTYPE_DISABLE_MACROS +extern int am_util_string_isalnum(int c); +extern int am_util_string_isalpha(int c); +extern int am_util_string_isdigit(int c); +extern int am_util_string_islower(int c); +extern int am_util_string_isspace(int c); +extern int am_util_string_isupper(int c); +extern int am_util_string_isxdigit(int c); +extern int am_util_string_tolower(int c); +extern int am_util_string_toupper(int c); + +// Non-standard "is" Functions +extern int am_util_string_isfilenm83(int c); +#else +#if MINIMIZE_CATTR_TABLE +#define am_util_string_isalnum(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) ? 1 : 0) +#define am_util_string_isalpha(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_ALPHA) ? 1 : 0) +#define am_util_string_isdigit(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_DIGIT) ? 1 : 0) +#define am_util_string_islower(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_LOWER) ? 1 : 0) +#define am_util_string_isspace(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_WHSPACE) ? 1 : 0) +#define am_util_string_isupper(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_UPPER) ? 1 : 0) +#define am_util_string_isxdigit(c) ((c & 0xffffff80) ? 0 : (am_cattr[c] & AM_CATTR_XDIGIT) ? 1 : 0) +#define am_util_string_tolower(c) ((am_cattr[c & 0x7f] & AM_CATTR_UPPER) ? c | 0x20 : c) +#define am_util_string_toupper(c) ((am_cattr[c & 0x7f] & AM_CATTR_LOWER) ? c & ~0x20 : c) +#else +#define am_util_string_isalnum(c) (am_cattr[c & 0xff] & (AM_CATTR_ALPHA | AM_CATTR_DIGIT)) +#define am_util_string_isalpha(c) (am_cattr[c & 0xff] & AM_CATTR_ALPHA) +#define am_util_string_isdigit(c) (am_cattr[c & 0xff] & AM_CATTR_DIGIT) +#define am_util_string_islower(c) (am_cattr[c & 0xff] & AM_CATTR_LOWER) +#define am_util_string_isspace(c) (am_cattr[c & 0xff] & AM_CATTR_WHSPACE) +#define am_util_string_isupper(c) (am_cattr[c & 0xff] & AM_CATTR_UPPER) +#define am_util_string_isxdigit(c) (am_cattr[c & 0xff] & AM_CATTR_XDIGIT) +#define am_util_string_tolower(c) ((am_cattr[c & 0xff] & AM_CATTR_UPPER) ? c | 0x20 : c) +#define am_util_string_toupper(c) ((am_cattr[c & 0xff] & AM_CATTR_LOWER) ? c & ~0x20 : c) +#endif // MINIMIZE_CATTR_TABLE + +// +// Non-standard "is" Functions +// +#define am_util_string_isfilenm83(c) (am_cattr[c & 0xff] & AM_CATTR_FILENM83) +#endif // AM_UTIL_STRING_CTYPE_DISABLE_MACROS + + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_STRING_H diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.c b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.c new file mode 100644 index 0000000000..c815212495 --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.c @@ -0,0 +1,146 @@ +//***************************************************************************** +// +//! @file am_util_time.h +//! +//! @brief Functions useful for RTC, calendar, time, etc. computations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#include +#include +#include "am_util_time.h" + +//***************************************************************************** +// +// Macro definitions. +// +//***************************************************************************** +#define AM_UTIL_TIME_IS_LEAP_YEAR(year) \ + (year % 4 == 0 && ((year % 100 != 0) || (year % 400 != 0))) + +//***************************************************************************** +// +// Local variables. +// +//***************************************************************************** + +// +// Numer of days in each month in a standard year. +// +const static uint32_t g_iDaysPerMonth[] = + {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +// +// Weekday drift numbers for each month. +// +const static int g_iMonthOffsets[] = + {4, 0, 0, 3, 5, 1, 3, 6, 2, 4, 0, 2}; + +//***************************************************************************** +// +//! @brief Compute the day of the week given the month, day, and year. +//! +//! @param iYear - The year of the desired date (e.g. 2016). +//! @param iMonth - The month of the desired date (1-12). +//! @param iDay - The day of the month of the desired date (1-31). +//! +//! This function is general in nature, but is designed to be used with the RTC. +//! +//! @returns An index value indicating the day of the week. +//! 0-6 indicate Sun, Mon, Tue, Wed, Thu, Fri, Sat, respectively. +//! 7 indicates that the given date is invalid (e.g. 2/29/2015). +// +//***************************************************************************** +int +am_util_time_computeDayofWeek(int iYear, int iMonth, int iDay) +{ + bool bInvalidDay; + int iYearOffset; + int iMonthOffset; + int iWeekday; + + int iLeapYearOffset = 0; + + // + // Validate inputs. Return 7 if any are out-of-bounds. + // + if ( (iMonth < 1) || (iMonth > 12) || (iYear < 0) || (iDay < 1) ) + { + return 7; + } + + // + // Make sure this day actually exists in this month. Make sure to include + // an exception for leap years. + // + if (iDay > g_iDaysPerMonth[iMonth - 1]) + { + if (iMonth == 2 && AM_UTIL_TIME_IS_LEAP_YEAR(iYear) && iDay == 29) + { + bInvalidDay = false; + } + else + { + bInvalidDay = true; + } + } + else + { + bInvalidDay = false; + } + + if (bInvalidDay) + { + return 7; + } + + iYearOffset = 2 + iYear + iYear / 4 - iYear / 100 + iYear / 400; + iMonthOffset = g_iMonthOffsets[iMonth - 1]; + + if (AM_UTIL_TIME_IS_LEAP_YEAR(iYear) && (iMonth < 3)) + { + iLeapYearOffset = -1; + } + + iWeekday = iDay + iYearOffset + iMonthOffset + iLeapYearOffset; + + return iWeekday % 7; +} diff --git a/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.h b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.h new file mode 100644 index 0000000000..23f362590b --- /dev/null +++ b/targets/TARGET_Ambiq_Micro/sdk/utils/am_util_time.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +//! @file am_util_time.h +//! +//! @brief Functions useful for RTC, calendar, time, etc. computations. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2020, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// +//***************************************************************************** +// SPDX-License-Identifier: BSD-3-Clause +#ifndef AM_UTIL_TIME_H +#define AM_UTIL_TIME_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// External function definitions +// +//***************************************************************************** +extern int am_util_time_computeDayofWeek(int iYear, int iMonth, int iDay); + +#ifdef __cplusplus +} +#endif + +#endif // AM_UTIL_TIME_H + diff --git a/targets/targets.json b/targets/targets.json index 67b809954a..86a1350fc8 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6802,6 +6802,71 @@ "release_versions": ["5"], "detect_code": ["3703"] }, + "FAMILY_Apollo3": { + "inherits": ["Target"], + "core": "Cortex-M4F", + "features": ["BLE"], + "default_toolchain": "GCC_ARM", + "supported_toolchains": [ + "GCC_ARM", + "ARMC6" + ], + "public": false, + "extra_labels": [ + "Ambiq_Micro", + "Apollo3", + "CORDIO" + ], + "device_has": [ + "MPU", + "USTICKER", + "SERIAL", + "INTERRUPTIN", + "LPTICKER", + "STDIO_MESSAGES", + "FLASH", + "SPI", + "I2C" + ], + "components": [ + "FLASHIAP" + ], + "macros": ["CORDIO_ZERO_COPY_HCI", + "USE_AMBIQ_DRIVER" + ] + }, + "AMA3B1KK": { + "public": false, + "inherits": ["FAMILY_Apollo3"], + "macros_add": ["AM_PACKAGE_BGA"] + }, + "SFE_ARTEMIS": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_ATP": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_DK": { + "inherits": ["AMA3B1KK"], + "components_add": ["lis2dh12", "hm01b0"] + }, + "SFE_ARTEMIS_MODULE": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_NANO": { + "inherits": ["AMA3B1KK"] + }, + "SFE_ARTEMIS_THING_PLUS": { + "inherits": ["AMA3B1KK"] + }, + "SFE_EDGE": { + "inherits": ["AMA3B1KK"], + "components_add": ["lis2dh12", "hm01b0"] + }, + "SFE_EDGE2": { + "inherits": ["AMA3B1KK"], + "components_add": ["lis2dh12", "hm01b0"] + }, "__build_tools_metadata__": { "version": "1", "public": false