Modifies are as below.
- Add flow control
- Change the range of baud rate that can be set in the baud function.
8138 bps more -> 128 bps more
- Fixed a bug that designation of parity had been reversed in format().
Fixed the incorrect clocksource for the baud generator. Should be MainClock instead of SystemCoreClock. This also allows the correct use of the PLL for MainClock and SystemCoreClock without breaking the serial baudrate.
LPC812 was running at 12MHz on IRC. Added and fixed PLL activation to change the clockspeed into the expected 30MHz. Clock source is still the IRC. Selecting the 12 MHz XTAL clocksource should also work with the PLL.
Added MainClock to fix wrong setting of SystemCoreClock and allow the serial_api to use the correct clock.
Quick fix of block read and write. The i2c_start is still wrong: it
should setup the address before initiating a Start condition. Status
read is also wrong in i2c_do_read.
I was getting Hard Faults in even the simplest of samples before I made
these fixes.
* WaitUs() did nothing on optimized builds. I added the volatile
qualifier to the cyc variable to make sure that the delay loop
doesn't get optimized out.
* I removed the #ifdef which skipped the fpuInit() call when building
with GCC.
If user set P0_0 as DigitalOut and set it to low, LPC1114 will be in
reset condion. To avoid this situation, p4, xp4 and dp23 was removed
from PinNames.h.
Find some bugs in USBHost common codes. Bugs as below.
- USBHostMouse.cpp
- Memory destroy will occur when the size of interrupt transfer is larger than 4 bytes.
- USBHostMSD.cpp
- Type declaration of vender dependent.
U16 -> uint16_t
- USBHostSerial.cpp
- connected() will not be "true".
- Communication with USBSerial will not start.
Please note that this commit goes with another recent commit to the nRF51822 repository which updated values under projectconfig.h. Please remember to update nRF51822 as well.
This has a bearing on issue #832.
Bugs are as below.
- Add terminal setting of IRQ4 and IRQ6 that leaked.
- When set the interrupt function by rise()/fall(), the interrupt disable state will be released by disable_irq().
- Interrupt will be continued to occur when execute disable_irq() after rise(NULL)/fall(NULL) set.
- Fix the setting timing of PMC register.
guidelines.
* Uncommented assertions in operators and added check for operator[] index < 0.
* Moved one operator from private to public, this was a typo thing.
- some minor error correction
- add pin definition for 3 tests (MBED_A5,6,7)
- add new target disco_f401vc to travis_build
travis_build and all test are OK except missing STM32F4 target
MTS_MDOT_F405RG
This is a fix for issue #285. This fix is similar to that proposed by
@oresths in the original issue.
There is code in rt_init_stack() which compares the task_id against the
value of 1 before writing MAGIC_WORD to the bottom of the stack. This
is supposed to stop the write from occurring for the main thread but
svcThreadCreate() doesn't initialize the P_TCB's task_id field until
after rt_init_stack() is executed. If any dynamic memory allocation
has occurred before the main thread is started (from the standard C
startup code) then this write could overwrite data in that allocation.
This change:
* moves the task_id initialization in svcThreadCreate() to happen
before the call to rt_init_context() is made.
* cleans up some comments in svcThreadCreate() which appear to
reference older versions of the code which would automatically
allocate stack memory if size == 0.
* still keeps the call to rt_dispatch() occurring after the call to
rt_init_context() so that the task is not dispatched to the
scheduler until the task fields have been populated.
I stepped through the rt_init_stack() code on my mbedLPC1768 after this
change was made to make sure that the write of MAGIC_WORD is now
skipped.
-----------------------------------------------------------------------
(gdb) break HAL_CM.c:95
Breakpoint 1 at 0x482c: file ../../external/mbed/libraries/rtos/rtx/TARGET_CORTEX_M/HAL_CM.c, line 95.
(gdb) c
Continuing.
Note: automatically using hardware breakpoints for read-only addresses.
Breakpoint 1, rt_init_stack (p_TCB=0x10000774 <os_idle_TCB>, task_body=0x4899 <os_idle_demon>)
at ../../external/mbed/libraries/rtos/rtx/TARGET_CORTEX_M/HAL_CM.c:95
95 if (p_TCB->task_id != 0x01)
(gdb) p *p_TCB
$1 = {
cb_type = 0 '\000',
state = 1 '\001',
prio = 0 '\000',
task_id = 255 '\377',
p_lnk = 0x0 <_reclaim_reent>,
p_rlnk = 0x0 <_reclaim_reent>,
p_dlnk = 0x0 <_reclaim_reent>,
p_blnk = 0x0 <_reclaim_reent>,
delta_time = 0,
interval_time = 0,
events = 0,
waits = 0,
msg = 0x0 <_reclaim_reent>,
stack_frame = 0 '\000',
reserved = 0 '\000',
priv_stack = 128,
tsk_stack = 268437480,
stack = 0x100007a8 <idle_task_stack>,
ptask = 0x4899 <os_idle_demon>
}
(gdb) c
Continuing.
Breakpoint 1, rt_init_stack (p_TCB=0x10000120 <os_thread_def_main+16>, task_body=0x620d <__wrap_main()>)
at ../../external/mbed/libraries/rtos/rtx/TARGET_CORTEX_M/HAL_CM.c:95
95 if (p_TCB->task_id != 0x01)
(gdb) p *p_TCB
$2 = {
cb_type = 0 '\000',
state = 1 '\001',
prio = 4 '\004',
task_id = 1 '\001',
p_lnk = 0x0 <_reclaim_reent>,
p_rlnk = 0x0 <_reclaim_reent>,
p_dlnk = 0x0 <_reclaim_reent>,
p_blnk = 0x0 <_reclaim_reent>,
delta_time = 0,
interval_time = 0,
events = 0,
waits = 0,
msg = 0x0 <_reclaim_reent>,
stack_frame = 0 '\000',
reserved = 0 '\000',
priv_stack = 26968,
tsk_stack = 268467136,
stack = 0x100012a8,
ptask = 0x620d <__wrap_main()>
}
(gdb) n
97 }
When the p_TCB for ptask==__wrap_main() is encountered, the task_id
now has a value of 1 and the write of MAGIC_WORD on line 96 is
skipped.
This issue was originally reported on the mbed site:
http://developer.mbed.org/questions/5570/mbed-rtos-memory-utilization/
The cause of the 64k limitation is that even though the user can set a
stack size larger than 64k in the osThreadDef_t::stacksize 32-bit
field, this size is truncated to 16-bit when it is copied to
the priv_stack field in the OS_TCB structure.
This commit corrects that problem by making the OS_TCB::priv_stack
field 32-bit. Due to word alignment, this introduces another 2 bytes
of padding in the structure which I have made explicit with the
addition of the reserved2 field.
The tsk_stack field which follows priv_stack is referenced directly by
assembly language code responsible for context switching. This context
switching code used a fixed byte offset, TCB_TSTACK, to access this
tsk_stack field. I had to update the TCB_TSTACK definition in various
locations from 36 to 40 to account for the extra alignment padding and
increased size of the priv_stack field.
TESTING
* GCC_ARM - mbedLPC1768 and mbedLPC11U24
* Online mbed Compiler - mbedLPC1768 and mbedLPC11U24
NOTES: I had to change assembly language code that was specific to IAR
but I don't have that toolchain so those changes aren't tested.
They do however follow the same pattern as the tested GCC
modifications.
Reverting the DEFAULT_STACK_SIZE changes in cmsis.oh.h and adding
changes to RTOS_x tests, to create threads with the neccessary reduced
stack sizes for these targets.
The mcu STM32L053C8 seems to have a problem in the RCC - LSE hardware
block. The Disco_L053 don't have a 32kHz crystal connected to LSE port
pins in contrast to NUCLEO_L053.
During initialization the HAL tests if it can start the LSE oscillator.
The Flag LSERDY in RCC_CSR is set to 1 by RCC clock control when the
oscillator runs stable. Without a crystal the flag shouldn't be set and
the HAL trys to start the internal LSI oscillator.
But the flag is always set to 1 also without a crystal. That's why the
RTC doesn't start.
Stack should be 8 byte aligned on ARM.
Fix the automatic correction of the alignment in rt_init_stack,
and make sure that all stacks are aligned by the compiler.
Decreasing OS_SCHEDULERSTKSIZE to 112 bytes solves the problem of the
failed test RTOS_3 (Semaphore resource lock).
The test itself was successfull but the final printf failed.
With the reduced stacksize now every test is OK.
There exists an inconsistency between official STM schematic of Nucleo
boards and the existing hardware. Each board should have an 8MHz
external clock source. That is not the case. At some boards the solder
jumper is existing and with that the external clock source. At some
other boards the solder jumper is not available. The Nucleo_F302 should
run with 72MHz but that is only possible with an external clock source.
Because of a missing solder jumper it runs only with the internal clock
source, and that's why only with 64MHz.
In case of off-line compiler, there is no problem about the frequency setting processing.
But in case of online compiler, the frequency setting processing will be error.
So, modify frequency setting processing of SPI to pass in online compiler.
Issue originally reported on mbed site here:
https://developer.mbed.org/questions/5695/FRDM-KL05z-hardfault-when-compiled-with-/
The RAM base address was incorrectly set to the beginning of RAM
instead of at a 0xC0 byte offset to reserve room for the interrupt
vectors. Without this fix, the global variables and the interrupt
vectors were occupying the same space in RAM once the user enabled the
timer interrupt.
The user who originally reported the issue on the mbed site has tested
this fix and verified that it corrected the hard fault issue that they
were encountering.
Martin Kojtal
Marcomissyou
Masao Hamanaka
ohagendorf
Wim
nitin.bhaskar.27.09@gmail.com
Przemek Wirkus
Jun-Ru Chang
bcostm
milangit
Willem23
Anders Lindvall
ZKvAH
Adam Green
ytsuboi
Paul Staron
Rohit Grover
kazu-zamasu
Per Kristian Gjermshus
albert361
Toyomasa Watarai