This change moves all PDL drivers into common source and include
directories to alleviate issue with Windows version of GNU Make 4.x
maximum command line length limit.
Fixed interrupt vector settings on M0 core. Wrong vector settings prevented
LP_TICKER from working, resulting in deep sleep tests failing on M0
or PSA variant.
Needed for PSoC to deep-sleep for more than 2 seconds
Max sleep with 16 bit lp_ticker (before this change) : 2sec
Max sleep with 32 bit lp_ticker (after this change) : 36hours
This data, placed at physically not existing addresses (0x9xxxxxxx) was used
only by PSoC Programmer and KitProg2 and is no longer needed, but was causing
issues with standard hex file processing tools like srecord (srec_cat).
If the board-specific initialization code configures the serial port to
use an 8-bit divider, the serial_init_clock function would configure the
16-bit divider with the same index instead of the intended 8-bit
divider.
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
Page size in all PSOC6 boards is 512 bytes. This is very problematic in
all storage applications. This change reduces the page size (in flash_api's
flash_program_page API) to 32 by reading the original page, modifying it
with programmed data and programming it back. The number 32 for page size
conforms to the number of times (16) this action can be done.
Fix port_write API to correctly shift the passed value.
This allows the reference application provided in PortOut docs
to work corectly with arbitrary LED_MASK.
https://os.mbed.com/docs/mbed-os/v5.11/apis/portout.html
The fix applies to both PSOC6 and PSOC6_FUTURE HAL implementations.
Use ModusToolbox Device Configurator 1.1.0.284 to generate the
BSP low-level initialization code. Compatible version of Device
Configurator to be released with ModusToolbox 1.1.
Notable changes:
* rename cycfg_connectivity -> cycfg_routing
* switch LF_CLK clock source from ILO to WCO on
CY8CPROTO-062-4343W and CYW943012P6EVB-01
Enabled tickless mode for Sequana PSA M0 core code to allow it to enter
deep sleep mode. This fixes issue #9094 where tests were failing due to
M0 core not entering deep sleep mode, blocking the whole chip.
Fixed incorrect resource management on M0 core, which crashed tickless
mode.
1. Removed random i/o glitches occurring during device reconfiguration
2. Fixed hazardous reads occurring at the end of transfer resulting
in incorrect values being received
3. Added spi_free() function
4. Replaced default M0 image with a one ignoring i/o reservation. This is
a workaround for missing proper destructors in Mbed drivers and BlockDevice
tests failing on repeated initialization
Fixes issue #9620.
Leszek Rusinowicz
Martin Kojtal
Vivek Pallantla
Cruz Monrreal
Ryan Morse
Yossi Levy
Oren Cohen
Oren Cohen
Oleg Kapshii
Evgeni
Kyle Kearney
Neil Tuttle
Neil Tuttle
Sergii Vozniak
David Saada
Netanel Gonen
Michael Schwarcz
itayzafrir
Volodymyr Medvid
deepikabhavnani
Alexander Zilberkant