Simplify tickers to stop emulating 1us ticks by using native timer resolutions.
Implement ticker get info functions.
Separate rtc and lp ticker init status by implementing separate functions.
Compile: stm32f7xx_hal_pcd.c
../targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c: In function 'PCD_WriteEmptyTxFifo':
../targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c:1310:11: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (len > ep->maxpacket)
^
../targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c:1325:13: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (len > ep->maxpacket)
^
Simplify tickers to stop emulating 1us ticks by using native timer resolutions.
Implement ticker get info functions.
Separate rtc and lp ticker init status by implementing separate functions.
Simplify tickers to stop emulating 1us ticks by using native timer resolutions.
Implement ticker get info functions.
Separate rtc and lp ticker init status by implementing separate functions.
Add mbed_critical include file to disable compiler warning messages.
MTB_ADV_WISE_1530 and MTB_USI_WM_BN_BM_22 includes same usi chip,
so common USI_WM_BN_BM_22 target has been created.
MTB_ADV_WISE_1530 and MTB_USI_WM_BN_BM_22 are inheting the common usi target
Since revision 5499db1 (mbed-os-5.6.0) a hardfault occurs after a power-cycle.
It doesn't occur after a reset when the application has been downloaded using
drag-and-drop or via debugger. This is probably the reason why this problem
isn't detected when testing new mbed releases.
The hardfault occured in hal_sleep(). Adding a __NOP after __WFI solves the
problem although I don't fully understand why.
- Revision ca661f9 is the last revision where the problem doesn't occur.
- The problem doesn't occur when compiling with GCC instead of ARM compiler
- This issue describes a similar, but not identical problem and led me to test adding a __NOP: https://github.com/ARMmbed/mbed-os/issues/5065
1. Fix the check to look for if MCG has a PLL
2. Do setup before and after deep sleep mode execution
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Tests have shown that there is hich-up on MSI clock during the setup phase.
If this stabilization phase happens when application has restarted again
this can have side effects, like grambled UART characters typically.
So we're adding a delay before hading-over back to application.
With this modification, on NCULEO_L476RG, the wake-up time is increased
from 2ms to 2,5ms.
If possible this should be improved in the future to save 500 microseconds
of wak-up time. See TODO
There are cases where HW registers are found in unpexcepted state when
exiting Deep Sleep only few micro-seconds after it was entered.
By using an internal clock that does not depend on anythin and clocking
the system without using PLL, this allows SetSysClock default configuration
to run fine whatever possible configuration we find the HW in when
exiting Deep Sleep.
Also we shall restore interrupts only after all cloks are back to
expected running state.
This patchs adds TRNG support using the upstreamed, open-source, TZ-TRNG
driver.
It also implements the HAL for TRNG and add it in features.
The mbed-os.py script deletes files that are unused by mbed-os.
Change-Id: Idf8eefd809f00d40e0ad3cf7657f2a8c2eca3505
Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
- ensure us_ticker_irq_handler() is called only when GP2 timer expires
- set us_ticker_set_interrupt() time interval to be 9.846 us
- set us_ticker_fire_interrupt() time interval to be 0.03846 us
- ensure us_ticker_irq_handler() is called only when GP2 timer expires
- set us_ticker_set_interrupt() time interval to be 9.846 us
- set us_ticker_fire_interrupt() time interval to be 0.03846 us
- convert tab to space
* Add source address word alignment check
* malloc and memcpy are called only if data is unaligned
* malloc size is now copySize (program page size), rather than whole buffer to be written
1. Disable unnecessary TX/RX threshold interrupts to avoid potential trap in DMA transfer
2. Start TX/RX DMA transfer simultaneously to fit H/W spec and avoid potential RX FIFO overflow issue
In Mbed OS, page size is program unit, which is different than FMC definition.
After fixing page size, we can pass NVSTORE test (mbed-os-features-nvstore-tests-nvstore-functionality).
This patch fix flash write issue when program size is more than page size (= 1024 bytes). See detail - https://github.com/ARMmbed/mbed-os/issues/6165
Source data always use aligned data in heap memory.
Mbed-os 5.4.7 was the last unofficial working support for this target.
Since Mbed-os 5.6.0, the support is now official and VK_RZ_A1H is now "codebase aligned" with GR_PEACH (RZ_A1H) & GR_LYCHEE (RZ_A1LU) !
- sector size is 0x800 bytes
- writeable unit size is 0x8 bytes
- flash start address is 0x0
- total ADuCM3029 on chip flash size is 0x40000 bytes
- total ADuCM4050 on chip flash size is 0x7F000 bytes
fix mbed-ci build error L6216E
* (.ARM.exidx) and *(.init_array) must be placed explicitly, otherwise it is shared between two regions, and the linker is unable to decide where to place it.
This patch changes the linker files and defines to use the ZBT SSRAM
instead of the FPGA Block RAM for code and data.
The section 4.1.1, Code and RAM memory map, of the CM3DS Eval RTL and
testbench user guide explains the available memories.
This switch improves code memory from 256 kB to 4 MB and data memory
from 128 kB to 4 MB.
However, the ZBT SSRAM1 for code memory begins at 0x00400000 while the
processor can only boot at address 0x00000000 which means that it
expects the vector table to be at that address. That is why we have to
create 2 load regions in the linker scripts: one with only the vector
table at address 0x0 and one with code + data at address 0x00400000.
Because of these two load regions, linker will produce different
behaviours:
* GCC_ARM and IAR will only create 1 binary with both load regions
padding with 0 in between. The binary will then be very large (at least
4 MB) and the flash process will take longer.
* ARM and ARMC6 will create 2 binaries for the two load regions. The
load addresses of the two binaries can be written in the images.txt file
on the MPS2 board. You can also use the --bincombined option of fromelf
utility to produce only 1 large binary.
This patch also adds the memory_zones.h file to try to put in common all
the memory addresses that were previously hard coded in the linker
scripts / startup files.
With that patch in, the simplest option is to directly use the .elf file
with the MPS2, which is only possible with mbb_v225.ebf and more recent
firmwares. It will now be the default for CM3DS.
This commit works with greentea thanks to the now merged pull request
ARMmbed/htrun#181 in order to copy .elf file to the MPS2 board.
Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
Ameba has two memory blocks: SDRAM(2M) and SRAM(512KB). SRAM has better access performance than SDRAM. So some timing critical codes must be moved to SRAM.
fix for mbed-os issue #5778
rebase for #6289
1. Start function: Issue repeat start when bus is busy
2. Byte write function: Do not call SDK function as this does
not work for some of the Kinetis device
3. Byte read function: Do not call SDK function as this would
issue a START and STOP signal which is not required for
I2C byte functions
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
I2C3 clock define was missing. I2C3 is connected to the Arduino
connector which is used by the ci-test shield
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
fix section error, ARM compiler uses IRAM1.bss to calculate the heap size
fix conflict of _memset between Ameba's library and ARM compiler's library, use standard memset() instead of _memset() in case of ARM compiler
Originally, we use 2 H/W timers for us_ticker/lp_ticker, one for counting and the other for alarm.
With H/W timer running in continuous mode, we could use just one H/W timer for counting/alarm simultaneously.
Few targets need more than just pending IRQ set. They include some flags to be
set that are checked in IRQ handler. This is the case for targets in this
commit.
This commit adds the UART driver and updates the UART HAL implementation
to use this driver.
It also removes legacy definitions.
Change-Id: Ie8e7a7bb64c763a2d97bc66d949fab3596736bbc
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
This commit adds the SPI driver which is now called by the SPI HAL
implementation.
It also removes legacy definitions.
Change-Id: Iadb20dda9dfa571db3de66c3a1ce45d80d8b81b6
Signed-off-by: Tamas Kaman <tamas.kaman@arm.com>
Keyur Hariya
Paul Thompson
jeromecoutant
Kari Haapalehto
Andreas Rebert
Cruz Monrreal
Mahesh Mahadevan
Netanel Gonen
Martin Kojtal
Joris Aerts
bcostm
ccli8
Laurent MEUNIER
Hugues de Valon
Jimmy Brisson
Wilfried Chauveau
Edmund Hsu
Cruz Monrreal
Ashok Rao
Netanel Gonen
Steven Cooreman
toyowata
Ganesh Ramachandran
Martin Kojtal
cyliangtw
zzw
mbedNoobNinja
Amanda Butler
amq
Evan Hosseini
Juha Ylinen
TomoYamanaka
Marcus Chang
paul-szczepanek-arm
Rob Meades
Bartek Szatkowski
Anna Bridge
gorazd
daid
adustm
Maciej Bocianski
Avinash Mehta
Tamas Kaman