mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #5902 from ganesh-ramachandran/master
Added Support for Toshiba TMPM46Bpull/6518/head
Jimmy Brisson
GitHub
commit
0615111785
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@ -0,0 +1,236 @@
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/**
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*******************************************************************************
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* @file tmpm46b_adc.h
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* @brief This file provides all the functions prototypes for ADC driver.
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* @version V2.0.2.1
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* @date 2015/02/11
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*
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* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
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*
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* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
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*******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __TMPM46B_ADC_H
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#define __TMPM46B_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "TMPM46B.h"
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#include "tx04_common.h"
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/** @addtogroup TX04_Periph_Driver
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* @{
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*/
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/** @addtogroup ADC
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* @{
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*/
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/** @defgroup ADC_Exported_Types
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* @{
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*/
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#define IS_ADC_UNIT(param) (((param) == TSB_AD))
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#define ADC_CONVERSION_CLK_10 ((uint32_t)0x00000000)
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#define ADC_CONVERSION_CLK_20 ((uint32_t)0x00000010)
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#define ADC_CONVERSION_CLK_30 ((uint32_t)0x00000020)
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#define ADC_CONVERSION_CLK_40 ((uint32_t)0x00000030)
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#define ADC_CONVERSION_CLK_80 ((uint32_t)0x00000040)
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#define ADC_CONVERSION_CLK_160 ((uint32_t)0x00000050)
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#define ADC_CONVERSION_CLK_320 ((uint32_t)0x00000060)
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#define IS_ADC_HOLD_TIME(param) (((param) == ADC_CONVERSION_CLK_10) || \
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((param) == ADC_CONVERSION_CLK_20) || \
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((param) == ADC_CONVERSION_CLK_30) || \
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((param) == ADC_CONVERSION_CLK_40) || \
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((param) == ADC_CONVERSION_CLK_80) || \
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((param) == ADC_CONVERSION_CLK_160)|| \
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((param) == ADC_CONVERSION_CLK_320))
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#define ADC_FC_DIVIDE_LEVEL_1 ((uint32_t)0x00000000)
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#define ADC_FC_DIVIDE_LEVEL_2 ((uint32_t)0x00000001)
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#define ADC_FC_DIVIDE_LEVEL_4 ((uint32_t)0x00000002)
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#define ADC_FC_DIVIDE_LEVEL_8 ((uint32_t)0x00000003)
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#define ADC_FC_DIVIDE_LEVEL_16 ((uint32_t)0x00000004)
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#define IS_ADC_PRESCALER(param) ((param) <= ADC_FC_DIVIDE_LEVEL_16)
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/* Interrupt generation timing in fixed channel mode */
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#define ADC_INT_SINGLE ((uint32_t)0x00000000)
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#define ADC_INT_CONVERSION_2 ((uint32_t)0x00000010)
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#define ADC_INT_CONVERSION_3 ((uint32_t)0x00000020)
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#define ADC_INT_CONVERSION_4 ((uint32_t)0x00000030)
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#define ADC_INT_CONVERSION_5 ((uint32_t)0x00000040)
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#define ADC_INT_CONVERSION_6 ((uint32_t)0x00000050)
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#define ADC_INT_CONVERSION_7 ((uint32_t)0x00000060)
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#define ADC_INT_CONVERSION_8 ((uint32_t)0x00000070)
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#define IS_ADC_INT_MODE(param) (((param) == ADC_INT_SINGLE) || \
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((param) == ADC_INT_CONVERSION_2) || \
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((param) == ADC_INT_CONVERSION_3) || \
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((param) == ADC_INT_CONVERSION_4) || \
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((param) == ADC_INT_CONVERSION_5) || \
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((param) == ADC_INT_CONVERSION_6) || \
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((param) == ADC_INT_CONVERSION_7) || \
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((param) == ADC_INT_CONVERSION_8))
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typedef enum {
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ADC_AN_00 = 0U, /*!< define for Analog Input channel */
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ADC_AN_01 = 1U,
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ADC_AN_02 = 2U,
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ADC_AN_03 = 3U,
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ADC_AN_04 = 4U,
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ADC_AN_05 = 5U,
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ADC_AN_06 = 6U,
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ADC_AN_07 = 7U,
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} ADC_AINx;
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#define IS_ADC_INPUT_CHANNEL(param) ((param) <= ADC_AN_07)
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#define IS_ADC_SCAN_CHANNEL(start, range) (((start) <= ADC_AN_07) && \
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((range) >= 1U) && \
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(((start) + (range)) <= 8U))
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typedef enum {
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ADC_REG_00 = 0U,
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ADC_REG_01 = 1U,
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ADC_REG_02 = 2U,
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ADC_REG_03 = 3U,
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ADC_REG_04 = 4U,
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ADC_REG_05 = 5U,
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ADC_REG_06 = 6U,
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ADC_REG_07 = 7U,
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ADC_REG_SP = 8U
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} ADC_REGx;
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#define IS_ADC_REG(param) ((param) <= ADC_REG_SP)
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#define ADC_APPLY_VREF_IN_CONVERSION ((uint32_t)0x00000000)
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#define ADC_APPLY_VREF_AT_ANY_TIME ((uint32_t)0x00000001)
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#define IS_ADC_VREF_CTRL(param) (((param) == ADC_APPLY_VREF_IN_CONVERSION) || \
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((param) == ADC_APPLY_VREF_AT_ANY_TIME))
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typedef enum {
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ADC_CMPCR_0 = 0U,
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ADC_CMPCR_1 = 1U
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} ADC_CMPCRx;
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#define IS_ADC_CMPCRx(param) ((param) <= ADC_CMPCR_1)
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#define ADC_EXTERADTRG ((uint32_t)0x00000000)
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#define ADC_INTERTRIGGER ((uint32_t)0x00000001)
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#define IS_ADC_EXTERADTRG(param) (((param) == ADC_EXTERADTRG)|| \
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((param) == ADC_INTERTRIGGER))
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#define IS_ADC_EXTERADTRG_TOP(param) (((param) == ADC_EXTERADTRG)|| \
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((param) == ADC_INTERTRIGGER))
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typedef enum {
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ADC_LARGER_THAN_CMP_REG = 0U,
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ADC_SMALLER_THAN_CMP_REG = 1U
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} ADC_CmpCondition;
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#define IS_ADC_CMPCONDITION(param) ((param) <= ADC_SMALLER_THAN_CMP_REG)
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typedef enum {
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ADC_SEQUENCE_CMP_MODE = 0U,
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ADC_CUMULATION_CMP_MODE = 1U
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} ADC_CmpCntMode;
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#define IS_ADC_CMPMODE(param) ((param) <= ADC_CUMULATION_CMP_MODE)
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typedef enum {
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ADC_TRG_00 = 0U,
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ADC_TRG_01 = 1U,
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ADC_TRG_02 = 2U,
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ADC_TRG_03 = 3U,
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ADC_TRG_04 = 4U,
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ADC_TRG_05 = 5U,
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ADC_TRG_06 = 6U,
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ADC_TRG_07 = 7U,
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ADC_TRG_08 = 8U,
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ADC_TRG_09 = 9U
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} ADC_TRGx;
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#define IS_ADC_TRG(param) ((param) <= ADC_TRG_09)
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/**
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* @brief ADC Monitor Configuration Structure definition
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*/
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typedef struct {
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ADC_AINx CmpChannel; /*!< Select which ADC channel will be used */
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uint32_t CmpCnt; /*!< How many times will valid comparisons be counted, range from 1 to 16 */
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ADC_CmpCondition Condition; /*!< Condition to compare ADC channel with Compare Register */
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ADC_CmpCntMode CntMode; /*!< Mode to compare ADC channel with Compare Register */
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uint32_t CmpValue; /*!< Comparison value to be set in Compare Register, max value is 4095 */
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} ADC_MonitorTypeDef;
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#define IS_ADC_CMPCNT(param) (((param) >= 1U) && ((param) <= 16U))
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#define IS_ADC_CMPVALUE_12BIT(param) ((param) <= 4095U)
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/**
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* @brief Union to store ADC state
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*/
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typedef union {
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uint32_t All;
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struct {
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uint32_t NormalBusy:1; /*!< bit0, Normal A/D conversion busy flag (ADBF) */
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uint32_t NormalComplete:1; /*!< bit1, Normal AD conversion complete flag (EOCF) */
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uint32_t TopBusy:1; /*!< bit2, Top-priority A/D conversion busy flag (HPADBF) */
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uint32_t TopComplete:1; /*!< bit3, Top-priority AD conversion complete flag (HPEOCF) */
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uint32_t Reserved:28; /*!< bit4 to bit 31, reserved */
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} Bit;
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} ADC_State;
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/**
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* @brief Union to store ADC result
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*/
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typedef union {
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uint32_t All;
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struct {
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uint32_t ADResult:12; /*!< bit0 to bit11, store AD result */
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uint32_t Stored:1; /*!< bit12, AD result has been stored */
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uint32_t OverRun:1; /*!< bit13, new AD result is stored before the old one is read */
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uint32_t Reserved:18; /*!< bit14 to bit31, reserved */
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} Bit;
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} ADC_Result;
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/** @} */
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/* End of group ADC_Exported_Types */
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/** @defgroup ADC_Exported_FunctionPrototypes
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* @{
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*/
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void ADC_SWReset(TSB_AD_TypeDef * ADx);
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void ADC_SetClk(TSB_AD_TypeDef * ADx, uint32_t Sample_HoldTime, uint32_t Prescaler_Output);
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void ADC_Start(TSB_AD_TypeDef * ADx);
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void ADC_SetScanMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetRepeatMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetINTMode(TSB_AD_TypeDef * ADx, uint32_t INTMode);
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void ADC_SetInputChannel(TSB_AD_TypeDef * ADx, ADC_AINx InputChannel);
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void ADC_SetScanChannel(TSB_AD_TypeDef * ADx, ADC_AINx StartChannel, uint32_t Range);
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void ADC_SetVrefCut(TSB_AD_TypeDef * ADx, uint32_t VrefCtrl);
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void ADC_SetIdleMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetVref(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetInputChannelTop(TSB_AD_TypeDef * ADx, ADC_AINx TopInputChannel);
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void ADC_StartTopConvert(TSB_AD_TypeDef * ADx);
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void ADC_SetMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, FunctionalState NewState);
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void ADC_ConfigMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, ADC_MonitorTypeDef * Monitor);
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void ADC_SetHWTrg(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState);
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void ADC_SetHWTrgTop(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState);
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ADC_State ADC_GetConvertState(TSB_AD_TypeDef * ADx);
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ADC_Result ADC_GetConvertResult(TSB_AD_TypeDef * ADx, ADC_REGx ADREGx);
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void ADC_EnableTrigger(void);
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void ADC_DisableTrigger(void);
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void ADC_SetTriggerStartup(ADC_TRGx TriggerStartup);
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void ADC_SetTriggerStartupTop(ADC_TRGx TopTriggerStartup);
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/** @} */
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/* End of group ADC_Exported_FunctionPrototypes */
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/** @} */
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/* End of group ADC */
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/** @} */
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/* End of group TX04_Periph_Driver */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __TMPM46B_ADC_H */
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@ -0,0 +1,342 @@
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/**
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*******************************************************************************
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* @file tmpm46b_cg.h
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* @brief This file provides all the functions prototypes for CG driver.
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* @version V2.0.2.1
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* @date 2015/02/26
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*
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* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
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*
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* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
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*******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __TMPM46B_CG_H
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#define __TMPM46B_CG_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* Includes ------------------------------------------------------------------*/
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#include "TMPM46B.h"
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#include "tx04_common.h"
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/** @addtogroup TX04_Periph_Driver
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* @{
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*/
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/** @addtogroup CG
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* @{
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*/
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/** @addtogroup CG_Exported_types
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* @{
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*/
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typedef enum {
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CG_DIVIDE_1 = 0U,
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CG_DIVIDE_2 = 1U,
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CG_DIVIDE_4 = 2U,
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CG_DIVIDE_8 = 3U,
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CG_DIVIDE_16 = 4U,
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CG_DIVIDE_32 = 5U,
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CG_DIVIDE_64 = 6U,
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CG_DIVIDE_128 = 7U,
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CG_DIVIDE_256 = 8U,
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CG_DIVIDE_512 = 9U,
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CG_DIVIDE_UNKNOWN = 10U,
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CG_DIVIDE_MAX = 11U
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} CG_DivideLevel;
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#define IS_CG_GEAR_DIVIDE_LEVEL(param) (((param) == CG_DIVIDE_1) || \
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((param) == CG_DIVIDE_2) || \
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((param) == CG_DIVIDE_4) || \
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((param) == CG_DIVIDE_8) || \
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((param) == CG_DIVIDE_16))
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#define IS_CG_FC_DIVIDE_LEVEL(param) (((param) == CG_DIVIDE_1) || \
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((param) == CG_DIVIDE_2) || \
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((param) == CG_DIVIDE_4) || \
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((param) == CG_DIVIDE_8) || \
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((param) == CG_DIVIDE_16)|| \
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((param) == CG_DIVIDE_32))
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#define IS_CG_DIVIDE_FC_LEVEL(param) (((param) == CG_DIVIDE_1) || \
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((param) == CG_DIVIDE_2) || \
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((param) == CG_DIVIDE_4) || \
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((param) == CG_DIVIDE_8) || \
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((param) == CG_DIVIDE_16) || \
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((param) == CG_DIVIDE_32) || \
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((param) == CG_DIVIDE_64)|| \
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((param) == CG_DIVIDE_128) || \
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((param) == CG_DIVIDE_256) || \
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((param) == CG_DIVIDE_512))
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typedef enum {
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CG_FOSC_OSC_EXT = 0U,
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CG_FOSC_OSC_INT = 1U,
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CG_FOSC_CLKIN_EXT = 2U
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} CG_FoscSrc;
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#define IS_CG_FOSC_SRC(param) (((param) == CG_FOSC_OSC_EXT) || \
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((param) == CG_FOSC_OSC_INT) || \
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((param) == CG_FOSC_CLKIN_EXT))
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#define IS_CG_FOSC_STATE(param) (((param) == CG_FOSC_OSC_EXT) || \
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((param) == CG_FOSC_OSC_INT) )
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typedef enum {
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CG_SCOUT_SRC_FS = 0U,
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CG_SCOUT_SRC_FSYS_DIVIDE_8 = 1U,
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CG_SCOUT_SRC_FSYS_DIVIDE_4 = 2U,
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CG_SCOUT_SRC_FOSC = 3U
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} CG_SCOUTSrc;
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#define IS_CG_SCOUT_SRC(param) (((param) == CG_SCOUT_SRC_FS) || \
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((param) == CG_SCOUT_SRC_FSYS_DIVIDE_8) || \
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((param) == CG_SCOUT_SRC_FSYS_DIVIDE_4) || \
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((param) == CG_SCOUT_SRC_FOSC))
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typedef enum {
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CG_WARM_UP_SRC_OSC_INT_HIGH = 0U,
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CG_WARM_UP_SRC_OSC_EXT_HIGH = 1U,
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CG_WARM_UP_SRC_OSC_EXT_LOW = 2U
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} CG_WarmUpSrc;
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#define IS_CG_WARM_UP_SRC(param) (((param) == CG_WARM_UP_SRC_OSC_INT_HIGH) || \
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((param) == CG_WARM_UP_SRC_OSC_EXT_HIGH) || \
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((param) == CG_WARM_UP_SRC_OSC_EXT_LOW))
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typedef enum {
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CG_FC_SRC_FOSC = 0U,
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CG_FC_SRC_FPLL = 1U
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} CG_FcSrc;
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#define IS_CG_FC_SRC(param) (((param) == CG_FC_SRC_FOSC) || \
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((param) == CG_FC_SRC_FPLL))
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#define CG_8M_MUL_4_FPLL (0x00006A0FUL<<1U) /* 4 fold, input 8MHz, output 32MHz */
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#define CG_8M_MUL_5_FPLL (0x00006A13UL<<1U) /* 5 fold, input 8MHz, output 40MHz */
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#define CG_8M_MUL_6_FPLL (0x00006917UL<<1U) /* 6 fold, input 8MHz, output 48MHz */
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#define CG_8M_MUL_8_FPLL (0x0000691FUL<<1U) /* 8 fold, input 8MHz, output 64MHz */
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#define CG_8M_MUL_10_FPLL (0x00006A26UL<<1U) /* 10 fold, input 8MHz, output 80MHz */
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#define CG_8M_MUL_12_FPLL (0x0000692EUL<<1U) /* 12 fold, input 8MHz, output 96MHz */
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#define CG_10M_MUL_4_FPLL (0x00006A0FUL<<1U) /* 4 fold, input 10MHz, output 40MHz */
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#define CG_10M_MUL_5_FPLL (0x00006A13UL<<1U) /* 5 fold, input 10MHz, output 50MHz */
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#define CG_10M_MUL_6_FPLL (0x00006917UL<<1U) /* 6 fold, input 10MHz, output 60MHz */
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#define CG_10M_MUL_8_FPLL (0x0000691FUL<<1U) /* 8 fold, input 10MHz, output 80MHz */
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#define CG_10M_MUL_10_FPLL (0x00006A26UL<<1U) /* 10 fold, input 10MHz, output 100MHz */
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#define CG_10M_MUL_12_FPLL (0x0000692EUL<<1U) /* 12 fold, input 10MHz, output 120MHz */
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#define CG_12M_MUL_4_FPLL (0x00006A0FUL<<1U) /* 4 fold, input 12MHz, output 48MHz */
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#define CG_12M_MUL_5_FPLL (0x00006A13UL<<1U) /* 5 fold, input 12MHz, output 60MHz */
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#define CG_12M_MUL_6_FPLL (0x00006917UL<<1U) /* 6 fold, input 12MHz, output 72MHz */
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#define CG_12M_MUL_8_FPLL (0x0000691FUL<<1U) /* 8 fold, input 12MHz, output 96MHz */
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#define CG_12M_MUL_10_FPLL (0x00006A26UL<<1U) /* 10 fold, input 12MHz, output 120MHz */
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#define CG_16M_MUL_4_FPLL (0x00006A0FUL<<1U) /* 4 fold, input 16MHz, output 64MHz */
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#define CG_16M_MUL_5_FPLL (0x00006A13UL<<1U) /* 5 fold, input 16MHz, output 80MHz */
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#define IS_CG_FPLL_VALUE(param) (((param) == CG_8M_MUL_4_FPLL) || \
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((param) == CG_8M_MUL_5_FPLL) || \
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||||
((param) == CG_8M_MUL_6_FPLL) || \
|
||||
((param) == CG_8M_MUL_8_FPLL) || \
|
||||
((param) == CG_8M_MUL_10_FPLL) || \
|
||||
((param) == CG_8M_MUL_12_FPLL) || \
|
||||
((param) == CG_10M_MUL_4_FPLL) || \
|
||||
((param) == CG_10M_MUL_5_FPLL) || \
|
||||
((param) == CG_10M_MUL_6_FPLL) || \
|
||||
((param) == CG_10M_MUL_8_FPLL) || \
|
||||
((param) == CG_10M_MUL_10_FPLL) || \
|
||||
((param) == CG_10M_MUL_12_FPLL) || \
|
||||
((param) == CG_12M_MUL_4_FPLL) || \
|
||||
((param) == CG_12M_MUL_5_FPLL) || \
|
||||
((param) == CG_12M_MUL_6_FPLL) || \
|
||||
((param) == CG_12M_MUL_8_FPLL) || \
|
||||
((param) == CG_12M_MUL_10_FPLL) || \
|
||||
((param) == CG_16M_MUL_4_FPLL) || \
|
||||
((param) == CG_16M_MUL_5_FPLL))
|
||||
|
||||
typedef enum {
|
||||
CG_STBY_MODE_UNKNOWN = 0U,
|
||||
CG_STBY_MODE_STOP1 = 1U,
|
||||
CG_STBY_MODE_IDLE = 3U,
|
||||
CG_STBY_MODE_STOP2 = 5U,
|
||||
CG_STBY_MODE_MAX = 8U
|
||||
} CG_STBYMode;
|
||||
#define IS_CG_STBY_MODE(param) (((param) == CG_STBY_MODE_STOP1) || \
|
||||
((param) == CG_STBY_MODE_IDLE)|| \
|
||||
((param) == CG_STBY_MODE_STOP2))
|
||||
|
||||
typedef enum {
|
||||
CG_PHIT0_SRC_FGEAR = 0U,
|
||||
CG_PHIT0_SRC_FC = 1U,
|
||||
CG_PHIT0_SRC_MAX = 2U
|
||||
} CG_PhiT0Src;
|
||||
#define IS_CG_PHIT0_SRC(param) (((param) == CG_PHIT0_SRC_FGEAR) || \
|
||||
((param) == CG_PHIT0_SRC_FC))
|
||||
|
||||
typedef enum {
|
||||
CG_INT_SRC_1 = 0U,
|
||||
CG_INT_SRC_2 = 1U,
|
||||
CG_INT_SRC_7 = 2U,
|
||||
CG_INT_SRC_8 = 3U,
|
||||
CG_INT_SRC_D = 4U,
|
||||
CG_INT_SRC_E = 5U,
|
||||
CG_INT_SRC_F = 6U,
|
||||
CG_INT_SRC_RTC = 7U
|
||||
} CG_INTSrc;
|
||||
|
||||
#define IS_CG_INT_SRC(param) (((param) == CG_INT_SRC_1) || \
|
||||
((param) == CG_INT_SRC_2) || \
|
||||
((param) == CG_INT_SRC_7) || \
|
||||
((param) == CG_INT_SRC_8) || \
|
||||
((param) == CG_INT_SRC_D) || \
|
||||
((param) == CG_INT_SRC_E) || \
|
||||
((param) == CG_INT_SRC_F) || \
|
||||
((param) == CG_INT_SRC_RTC))
|
||||
|
||||
typedef enum {
|
||||
CG_INT_ACTIVE_STATE_L = 0x00U,
|
||||
CG_INT_ACTIVE_STATE_H = 0x10U,
|
||||
CG_INT_ACTIVE_STATE_FALLING = 0x20U,
|
||||
CG_INT_ACTIVE_STATE_RISING = 0x30U,
|
||||
CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x40U,
|
||||
CG_INT_ACTIVE_STATE_INVALID = 0x50U
|
||||
} CG_INTActiveState;
|
||||
#define IS_CG_INT_ACTIVE_STATE(param) (((param) == CG_INT_ACTIVE_STATE_L) || \
|
||||
((param) == CG_INT_ACTIVE_STATE_H) || \
|
||||
((param) == CG_INT_ACTIVE_STATE_FALLING) || \
|
||||
((param) == CG_INT_ACTIVE_STATE_RISING) || \
|
||||
((param) == CG_INT_ACTIVE_STATE_BOTH_EDGES))
|
||||
|
||||
#define IS_CG_INT_RTC_ACTIVE_STATE(param) ((param) == CG_INT_ACTIVE_STATE_FALLING)
|
||||
|
||||
#define CG_FC_PERIPH_PORTA (0x00000001U << 0U)
|
||||
#define CG_FC_PERIPH_PORTB (0x00000001U << 1U)
|
||||
#define CG_FC_PERIPH_PORTC (0x00000001U << 2U)
|
||||
#define CG_FC_PERIPH_PORTD (0x00000001U << 3U)
|
||||
#define CG_FC_PERIPH_PORTE (0x00000001U << 4U)
|
||||
#define CG_FC_PERIPH_PORTF (0x00000001U << 5U)
|
||||
#define CG_FC_PERIPH_PORTG (0x00000001U << 6U)
|
||||
#define CG_FC_PERIPH_PORTH (0x00000001U << 7U)
|
||||
#define CG_FC_PERIPH_PORTJ (0x00000001U << 8U)
|
||||
#define CG_FC_PERIPH_PORTK (0x00000001U << 9U)
|
||||
#define CG_FC_PERIPH_PORTL (0x00000001U << 10U)
|
||||
#define CG_FC_PERIPH_TMRB0 (0x00000001U << 13U)
|
||||
#define CG_FC_PERIPH_TMRB1 (0x00000001U << 14U)
|
||||
#define CG_FC_PERIPH_TMRB2 (0x00000001U << 15U)
|
||||
#define CG_FC_PERIPH_TMRB3 (0x00000001U << 16U)
|
||||
#define CG_FC_PERIPH_TMRB4 (0x00000001U << 17U)
|
||||
#define CG_FC_PERIPH_TMRB5 (0x00000001U << 18U)
|
||||
#define CG_FC_PERIPH_TMRB6 (0x00000001U << 19U)
|
||||
#define CG_FC_PERIPH_TMRB7 (0x00000001U << 20U)
|
||||
#define CG_FC_PERIPH_MPT0 (0x00000001U << 27U)
|
||||
#define CG_FC_PERIPH_MPT1 (0x00000001U << 28U)
|
||||
#define CG_FC_PERIPH_MPT2 (0x00000001U << 29U)
|
||||
#define CG_FC_PERIPH_MPT3 (0x00000001U << 30U)
|
||||
#define CG_FC_PERIPH_TRACE (0x00000001U << 31U)
|
||||
#define CG_FC_PERIPHA_ALL (0xF81FE7FFU)
|
||||
#define IS_CG_FC_PERIPHA(param) ((param) > 0U)
|
||||
|
||||
#define CG_FC_PERIPH_SIO_UART0 (0x00000001U << 0U)
|
||||
#define CG_FC_PERIPH_SIO_UART1 (0x00000001U << 1U)
|
||||
#define CG_FC_PERIPH_SIO_UART2 (0x00000001U << 2U)
|
||||
#define CG_FC_PERIPH_SIO_UART3 (0x00000001U << 3U)
|
||||
#define CG_FC_PERIPH_UART0 (0x00000001U << 10U)
|
||||
#define CG_FC_PERIPH_UART1 (0x00000001U << 11U)
|
||||
#define CG_FC_PERIPH_I2C0 (0x00000001U << 12U)
|
||||
#define CG_FC_PERIPH_I2C1 (0x00000001U << 13U)
|
||||
#define CG_FC_PERIPH_I2C2 (0x00000001U << 14U)
|
||||
#define CG_FC_PERIPH_SSP0 (0x00000001U << 17U)
|
||||
#define CG_FC_PERIPH_SSP1 (0x00000001U << 18U)
|
||||
#define CG_FC_PERIPH_SSP2 (0x00000001U << 19U)
|
||||
#define CG_FC_PERIPH_EBIF (0x00000001U << 20U)
|
||||
#define CG_FC_PERIPH_DMACA (0x00000001U << 21U)
|
||||
#define CG_FC_PERIPH_DMACB (0x00000001U << 22U)
|
||||
#define CG_FC_PERIPH_DMACC (0x00000001U << 23U)
|
||||
#define CG_FC_PERIPH_DMAIF (0x00000001U << 24U)
|
||||
#define CG_FC_PERIPH_ADC (0x00000001U << 25U)
|
||||
#define CG_FC_PERIPH_WDT (0x00000001U << 26U)
|
||||
#define CG_FC_PERIPH_MLA (0x00000001U << 28U)
|
||||
#define CG_FC_PERIPH_ESG (0x00000001U << 29U)
|
||||
#define CG_FC_PERIPH_SHA (0x00000001U << 30U)
|
||||
#define CG_FC_PERIPH_AES (0x00000001U << 31U)
|
||||
#define CG_FC_PERIPHB_ALL (0xF7FE7C0FU)
|
||||
#define IS_CG_FC_PERIPHB(param) (((param) > 0U) && ((param) <= CG_FC_PERIPHB_ALL))
|
||||
|
||||
typedef union {
|
||||
uint32_t All;
|
||||
struct {
|
||||
uint32_t WDT:1;
|
||||
uint32_t Reserved0:1;
|
||||
uint32_t DetectLowVoltage:1;
|
||||
uint32_t Reserved1:29;
|
||||
} Bit;
|
||||
} CG_NMIFactor;
|
||||
|
||||
typedef union {
|
||||
uint32_t All;
|
||||
struct {
|
||||
uint32_t PinReset:1;
|
||||
uint32_t OSCFLF:1;
|
||||
uint32_t WDTReset:1;
|
||||
uint32_t STOP2Reset:1;
|
||||
uint32_t DebugReset:1;
|
||||
uint32_t Reserved0:1;
|
||||
uint32_t LVDReset:1;
|
||||
uint32_t Reserved1:25;
|
||||
} Bit;
|
||||
} CG_ResetFlag;
|
||||
|
||||
/** @} */
|
||||
/* End of group CG_Exported_types */
|
||||
|
||||
/** @defgroup CG_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc);
|
||||
CG_DivideLevel CG_GetFgearLevel(void);
|
||||
void CG_SetPhiT0Src(CG_PhiT0Src PhiT0Src);
|
||||
CG_PhiT0Src CG_GetPhiT0Src(void);
|
||||
Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc);
|
||||
CG_DivideLevel CG_GetPhiT0Level(void);
|
||||
void CG_SetSCOUTSrc(CG_SCOUTSrc Source);
|
||||
CG_SCOUTSrc CG_GetSCOUTSrc(void);
|
||||
void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time);
|
||||
void CG_StartWarmUp(void);
|
||||
WorkState CG_GetWarmUpState(void);
|
||||
Result CG_SetFPLLValue(uint32_t NewValue);
|
||||
uint32_t CG_GetFPLLValue(void);
|
||||
Result CG_SetPLL(FunctionalState NewState);
|
||||
FunctionalState CG_GetPLLState(void);
|
||||
Result CG_SetFosc(CG_FoscSrc Source, FunctionalState NewState);
|
||||
void CG_SetFoscSrc(CG_FoscSrc Source);
|
||||
CG_FoscSrc CG_GetFoscSrc(void);
|
||||
FunctionalState CG_GetFoscState(CG_FoscSrc Source);
|
||||
void CG_SetSTBYMode(CG_STBYMode Mode);
|
||||
CG_STBYMode CG_GetSTBYMode(void);
|
||||
void CG_SetPortKeepInStop2Mode(FunctionalState NewState);
|
||||
FunctionalState CG_GetPortKeepInStop2Mode(void);
|
||||
Result CG_SetFcSrc(CG_FcSrc Source);
|
||||
CG_FcSrc CG_GetFcSrc(void);
|
||||
void CG_SetProtectCtrl(FunctionalState NewState);
|
||||
void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource,
|
||||
CG_INTActiveState ActiveState, FunctionalState NewState);
|
||||
CG_INTActiveState CG_GetSTBYReleaseINTState(CG_INTSrc INTSource);
|
||||
void CG_ClearINTReq(CG_INTSrc INTSource);
|
||||
CG_NMIFactor CG_GetNMIFlag(void);
|
||||
FunctionalState CG_GetIOSCFlashFlag(void);
|
||||
CG_ResetFlag CG_GetResetFlag(void);
|
||||
void CG_SetADCClkSupply(FunctionalState NewState);
|
||||
void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState);
|
||||
void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState);
|
||||
void CG_SetFs(FunctionalState NewState);
|
||||
|
||||
/** @} */
|
||||
/* End of group CG_Exported_FunctionPrototype */
|
||||
|
||||
/** @} */
|
||||
/* End of group CG */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __TMPM46B_CG_H */
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_esg.h
|
||||
* @brief This file provides all the functions prototypes for ESG driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/04
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_ESG_H
|
||||
#define __TMPM46B_ESG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ESG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ESG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of ESG_Exported_Constants */
|
||||
|
||||
/** @defgroup ESG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
ESG_CALCULATION_COMPLETE = 0U,
|
||||
ESG_CALCULATION_PROCESS = 1U
|
||||
} ESG_CalculationStatus;
|
||||
|
||||
typedef enum {
|
||||
ESG_LATCH_TIMING_1 = 0U,
|
||||
ESG_LATCH_TIMING_2 = 1U,
|
||||
ESG_LATCH_TIMING_3 = 2U,
|
||||
ESG_LATCH_TIMING_4 = 3U,
|
||||
ESG_LATCH_TIMING_5 = 4U,
|
||||
ESG_LATCH_TIMING_6 = 5U,
|
||||
ESG_LATCH_TIMING_7 = 6U,
|
||||
ESG_LATCH_TIMING_8 = 7U,
|
||||
ESG_LATCH_TIMING_9 = 8U,
|
||||
ESG_LATCH_TIMING_10 = 9U,
|
||||
ESG_LATCH_TIMING_11 = 10U,
|
||||
ESG_LATCH_TIMING_12 = 11U,
|
||||
ESG_LATCH_TIMING_13 = 12U,
|
||||
ESG_LATCH_TIMING_14 = 13U,
|
||||
ESG_LATCH_TIMING_15 = 14U,
|
||||
ESG_LATCH_TIMING_16 = 15U
|
||||
} ESG_LatchTiming;
|
||||
#define IS_ESG_LATCH_TIMING(param) ((param) <= ESG_LATCH_TIMING_16)
|
||||
|
||||
/** @} */
|
||||
/* End of ESG_Exported_types */
|
||||
|
||||
/** @addtogroup ESG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ESG Init Structure definition
|
||||
*/
|
||||
/** @} */
|
||||
/* End of group ESG_Exported_Types */
|
||||
|
||||
/** @defgroup ESG_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
Result ESG_Startup(void);
|
||||
Result ESG_SetLatchTiming(ESG_LatchTiming Value);
|
||||
uint32_t ESG_GetLatchTiming(void);
|
||||
Result ESG_SetFintiming(uint16_t Fintming);
|
||||
uint16_t ESG_GetFintiming(void);
|
||||
Result ESG_ClrInt(void);
|
||||
FunctionalState ESG_GetIntStatus(void);
|
||||
void ESG_IPReset(void);
|
||||
ESG_CalculationStatus ESG_GetCalculationStatus(void);
|
||||
void ESG_GetResult(uint32_t Seed[16U]);
|
||||
|
||||
/** @} */
|
||||
/* End of ESG_Exported_FunctionPrototypes */
|
||||
|
||||
/** @} */
|
||||
/* End of group ESG */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __TMPM46B_ESG_H */
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_fc.h
|
||||
* @brief This file provides all the functions prototypes for FC driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/27
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_FC_H
|
||||
#define __TMPM46B_FC_H
|
||||
|
||||
|
||||
/* #define SINGLE_BOOT_MODE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
FC_SUCCESS = 0U,
|
||||
FC_ERROR_PROTECTED = 1U,
|
||||
FC_ERROR_OVER_TIME = 2U
|
||||
} FC_Result;
|
||||
|
||||
/** @} */
|
||||
/* End of group FC_Exported_Types */
|
||||
|
||||
/** @defgroup FC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_PAGE_SIZE ((uint32_t)0x00001000) /* Page Size 4096 Bytes/1024 words */
|
||||
#define PROGRAM_UNIT 4U /* Page program could be written 16 bytes/4 words once */
|
||||
|
||||
#define FC_PAGE_0 ((uint8_t)0x00)
|
||||
#define FC_PAGE_1 ((uint8_t)0x01)
|
||||
#define FC_PAGE_2 ((uint8_t)0x02)
|
||||
#define FC_PAGE_3 ((uint8_t)0x03)
|
||||
#define FC_PAGE_4 ((uint8_t)0x04)
|
||||
#define FC_PAGE_5 ((uint8_t)0x05)
|
||||
#define FC_PAGE_6 ((uint8_t)0x06)
|
||||
#define FC_PAGE_7 ((uint8_t)0x07)
|
||||
|
||||
#define FC_PAGE_MAX FC_PAGE_7
|
||||
#define IS_FC_PAGE_NUM(param) ((param) <= FC_PAGE_MAX)
|
||||
|
||||
#define FC_BLOCK_0 ((uint8_t)0x00)
|
||||
#define FC_BLOCK_1 ((uint8_t)0x01)
|
||||
#define FC_BLOCK_2 ((uint8_t)0x02)
|
||||
#define FC_BLOCK_3 ((uint8_t)0x03)
|
||||
#define FC_BLOCK_4 ((uint8_t)0x04)
|
||||
#define FC_BLOCK_5 ((uint8_t)0x05)
|
||||
#define FC_BLOCK_6 ((uint8_t)0x06)
|
||||
#define FC_BLOCK_7 ((uint8_t)0x07)
|
||||
#define FC_BLOCK_8 ((uint8_t)0x08)
|
||||
#define FC_BLOCK_9 ((uint8_t)0x09)
|
||||
#define FC_BLOCK_10 ((uint8_t)0x0A)
|
||||
#define FC_BLOCK_11 ((uint8_t)0x0B)
|
||||
#define FC_BLOCK_12 ((uint8_t)0x0C)
|
||||
#define FC_BLOCK_13 ((uint8_t)0x0D)
|
||||
#define FC_BLOCK_14 ((uint8_t)0x0E)
|
||||
#define FC_BLOCK_15 ((uint8_t)0x0F)
|
||||
#define FC_BLOCK_16 ((uint8_t)0x10)
|
||||
#define FC_BLOCK_17 ((uint8_t)0x11)
|
||||
#define FC_BLOCK_18 ((uint8_t)0x12)
|
||||
#define FC_BLOCK_19 ((uint8_t)0x13)
|
||||
#define FC_BLOCK_20 ((uint8_t)0x14)
|
||||
#define FC_BLOCK_21 ((uint8_t)0x15)
|
||||
#define FC_BLOCK_22 ((uint8_t)0x16)
|
||||
#define FC_BLOCK_23 ((uint8_t)0x17)
|
||||
#define FC_BLOCK_24 ((uint8_t)0x18)
|
||||
#define FC_BLOCK_25 ((uint8_t)0x19)
|
||||
#define FC_BLOCK_26 ((uint8_t)0x1A)
|
||||
#define FC_BLOCK_27 ((uint8_t)0x1B)
|
||||
#define FC_BLOCK_28 ((uint8_t)0x1C)
|
||||
#define FC_BLOCK_29 ((uint8_t)0x1D)
|
||||
#define FC_BLOCK_30 ((uint8_t)0x1E)
|
||||
#define FC_BLOCK_31 ((uint8_t)0x1F)
|
||||
|
||||
#define FLASH_CHIP_SIZE ((uint32_t)0x00100000) /* Flash chip size is 1024KByte */
|
||||
#define FC_BLOCK_MAX FC_BLOCK_31
|
||||
|
||||
#define IS_FC_BLOCK_NUM(param) (((param) <= FC_BLOCK_MAX) && ((param) >= FC_BLOCK_1))
|
||||
|
||||
#define FC_AREA_ALL ((uint8_t)0x00)
|
||||
#define FC_AREA_0 ((uint8_t)0x01)
|
||||
#define FC_AREA_1 ((uint8_t)0x02)
|
||||
|
||||
#define IS_FC_AREA(param) ((param) <= FC_AREA_1)
|
||||
|
||||
#define FC_SWAP_SIZE_4K ((uint32_t)0x00000000)
|
||||
#define FC_SWAP_SIZE_8K ((uint32_t)0x00000001)
|
||||
#define FC_SWAP_SIZE_16K ((uint32_t)0x00000002)
|
||||
#define FC_SWAP_SIZE_32K ((uint32_t)0x00000003)
|
||||
#define FC_SWAP_SIZE_512K ((uint32_t)0x00000004)
|
||||
|
||||
#define FC_SWAP_INITIAL ((uint32_t)0x00000000)
|
||||
#define FC_SWAPPING ((uint32_t)0x00000001)
|
||||
#define FC_SWAP_PROHIBIT ((uint32_t)0x00000002)
|
||||
#define FC_SWAP_RELEASE ((uint32_t)0x00000003)
|
||||
|
||||
#define FC_Clk_Div_1 ((uint8_t) 0x00)
|
||||
#define FC_Clk_Div_2 ((uint8_t) 0x01)
|
||||
#define FC_Clk_Div_3 ((uint8_t) 0x02)
|
||||
#define FC_Clk_Div_4 ((uint8_t) 0x03)
|
||||
#define FC_Clk_Div_5 ((uint8_t) 0x04)
|
||||
#define FC_Clk_Div_6 ((uint8_t) 0x05)
|
||||
#define FC_Clk_Div_7 ((uint8_t) 0x06)
|
||||
#define FC_Clk_Div_8 ((uint8_t) 0x07)
|
||||
#define FC_Clk_Div_9 ((uint8_t) 0x08)
|
||||
#define FC_Clk_Div_10 ((uint8_t) 0x09)
|
||||
#define FC_Clk_Div_11 ((uint8_t) 0x0A)
|
||||
#define FC_Clk_Div_12 ((uint8_t) 0x0B)
|
||||
#define FC_Clk_Div_13 ((uint8_t) 0x0C)
|
||||
#define FC_Clk_Div_14 ((uint8_t) 0x0D)
|
||||
#define FC_Clk_Div_15 ((uint8_t) 0x0E)
|
||||
#define FC_Clk_Div_16 ((uint8_t) 0x0F)
|
||||
#define FC_Clk_Div_17 ((uint8_t) 0x10)
|
||||
#define FC_Clk_Div_18 ((uint8_t) 0x11)
|
||||
#define FC_Clk_Div_19 ((uint8_t) 0x12)
|
||||
#define FC_Clk_Div_20 ((uint8_t) 0x13)
|
||||
#define FC_Clk_Div_21 ((uint8_t) 0x14)
|
||||
#define FC_Clk_Div_22 ((uint8_t) 0x15)
|
||||
#define FC_Clk_Div_23 ((uint8_t) 0x16)
|
||||
#define FC_Clk_Div_24 ((uint8_t) 0x17)
|
||||
#define FC_Clk_Div_25 ((uint8_t) 0x18)
|
||||
#define FC_Clk_Div_26 ((uint8_t) 0x19)
|
||||
#define FC_Clk_Div_27 ((uint8_t) 0x1A)
|
||||
#define FC_Clk_Div_28 ((uint8_t) 0x1B)
|
||||
#define FC_Clk_Div_29 ((uint8_t) 0x1C)
|
||||
#define FC_Clk_Div_30 ((uint8_t) 0x1D)
|
||||
#define FC_Clk_Div_31 ((uint8_t) 0x1E)
|
||||
#define FC_Clk_Div_32 ((uint8_t) 0x1F)
|
||||
#define IS_FC_WCLK_DIV(param) ((param) <= FC_Clk_Div_32)
|
||||
|
||||
#define FC_PROG_CNT_250 ((uint8_t) 0x00)
|
||||
#define FC_PROG_CNT_300 ((uint8_t) 0x01)
|
||||
#define FC_PROG_CNT_350 ((uint8_t) 0x02)
|
||||
#define IS_FC_PROG_CNT(param) ((param) <= (FC_PROG_CNT_350))
|
||||
|
||||
#define FC_ERAS_CNT_85 ((uint8_t) 0x00)
|
||||
#define FC_ERAS_CNT_90 ((uint8_t) 0x01)
|
||||
#define FC_ERAS_CNT_95 ((uint8_t) 0x02)
|
||||
#define FC_ERAS_CNT_100 ((uint8_t) 0x03)
|
||||
#define FC_ERAS_CNT_105 ((uint8_t) 0x04)
|
||||
#define FC_ERAS_CNT_110 ((uint8_t) 0x05)
|
||||
#define FC_ERAS_CNT_115 ((uint8_t) 0x06)
|
||||
#define FC_ERAS_CNT_120 ((uint8_t) 0x07)
|
||||
#define FC_ERAS_CNT_125 ((uint8_t) 0x08)
|
||||
#define FC_ERAS_CNT_130 ((uint8_t) 0x09)
|
||||
#define FC_ERAS_CNT_135 ((uint8_t) 0x0A)
|
||||
#define FC_ERAS_CNT_140 ((uint8_t) 0x0B)
|
||||
#define IS_FC_ERASE_CNT(param) ((param) <= FC_ERAS_CNT_140)
|
||||
|
||||
#define FC_SWPSR_BIT_0 ((uint8_t) 0x00)
|
||||
#define FC_SWPSR_BIT_1 ((uint8_t) 0x01)
|
||||
#define FC_SWPSR_BIT_2 ((uint8_t) 0x02)
|
||||
#define FC_SWPSR_BIT_3 ((uint8_t) 0x03)
|
||||
#define FC_SWPSR_BIT_4 ((uint8_t) 0x04)
|
||||
#define FC_SWPSR_BIT_5 ((uint8_t) 0x05)
|
||||
#define FC_SWPSR_BIT_6 ((uint8_t) 0x06)
|
||||
#define FC_SWPSR_BIT_7 ((uint8_t) 0x07)
|
||||
#define FC_SWPSR_BIT_8 ((uint8_t) 0x08)
|
||||
#define FC_SWPSR_BIT_9 ((uint8_t) 0x09)
|
||||
#define FC_SWPSR_BIT_10 ((uint8_t) 0x0A)
|
||||
#define IS_FC_SWPSR_BIT_NUM(param) ((param) <= FC_SWPSR_BIT_10)
|
||||
|
||||
#define FC_BIT_VALUE_0 ((uint32_t)0x00000000)
|
||||
#define FC_BIT_VALUE_1 ((uint32_t)0x00000001)
|
||||
|
||||
#ifdef SINGLE_BOOT_MODE
|
||||
#define FLASH_START_ADDR ((uint32_t)0x5E000000) /* SINGLE_BOOT_MODE */
|
||||
#else
|
||||
#define FLASH_START_ADDR ((uint32_t)0x00000000) /* User Boot Mode As Default */
|
||||
#endif
|
||||
|
||||
#define FLASH_END_ADDR (FLASH_START_ADDR + FLASH_CHIP_SIZE - 1U)
|
||||
|
||||
#ifdef SINGLE_BOOT_MODE
|
||||
#define IS_FC_ADDR(param) (((param) >= FLASH_START_ADDR) && \
|
||||
((param) <= FLASH_END_ADDR))
|
||||
#else
|
||||
#define IS_FC_ADDR(param) ((param) <= FLASH_END_ADDR)
|
||||
#endif
|
||||
|
||||
#define IS_FC_PAGE_ADDR(param) ((((param) > FLASH_START_ADDR) || ((param) == FLASH_START_ADDR)) && \
|
||||
((param) <= (FLASH_END_ADDR - PROGRAM_UNIT)))
|
||||
|
||||
|
||||
/** @} */
|
||||
/* End of group FC_Exported_Constants */
|
||||
|
||||
|
||||
/** @defgroup FC_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FC_SetSecurityBit(FunctionalState NewState);
|
||||
FunctionalState FC_GetSecurityBit(void);
|
||||
WorkState FC_GetBusyState(void);
|
||||
FunctionalState FC_GetBlockProtectState(uint8_t BlockNum);
|
||||
FunctionalState FC_GetPageProtectState(uint8_t PageNum);
|
||||
FunctionalState FC_GetAbortState(void);
|
||||
uint32_t FC_GetSwapSize(void);
|
||||
uint32_t FC_GetSwapState(void);
|
||||
void FC_SelectArea(uint8_t AreaNum, FunctionalState NewState);
|
||||
void FC_SetAbortion(void);
|
||||
void FC_ClearAbortion(void);
|
||||
void FC_SetClkDiv(uint8_t ClkDiv);
|
||||
void FC_SetProgramCount(uint8_t ProgramCount);
|
||||
void FC_SetEraseCounter(uint8_t EraseCounter);
|
||||
FC_Result FC_ProgramBlockProtectState(uint8_t BlockNum);
|
||||
FC_Result FC_ProgramPageProtectState(uint8_t PageNum);
|
||||
FC_Result FC_EraseProtectState(void);
|
||||
FC_Result FC_WritePage(uint32_t PageAddr, uint32_t * Data);
|
||||
FC_Result FC_EraseBlock(uint32_t BlockAddr);
|
||||
FC_Result FC_EraseArea(uint32_t AreaAddr);
|
||||
FC_Result FC_ErasePage(uint32_t PageAddr);
|
||||
FC_Result FC_EraseChip(void);
|
||||
FC_Result FC_SetSwpsrBit(uint8_t BitNum);
|
||||
uint32_t FC_GetSwpsrBitValue(uint8_t BitNum);
|
||||
|
||||
/** @} */
|
||||
/* End of group FC_Exported_FunctionPrototypes */
|
||||
|
||||
/** @} */
|
||||
/* End of group FC */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __TMPM46B_FC_H */
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_fuart.h
|
||||
* @brief This file provides all the functions prototypes for Full UART driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/26
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_FUART_H
|
||||
#define __TMPM46B_FUART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FUART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FUART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FUART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
uint32_t BaudRate; /*!< This member configures the Full UART communication
|
||||
baud rate. */
|
||||
uint32_t DataBits; /*!< Specifies FUART transfer mode, which could be
|
||||
5-bit mode, 6-bit mode, 7-bit mode or 8-bit mode. */
|
||||
uint32_t StopBits; /*!< Specifies the length of stop bit transmission
|
||||
in Full UART. */
|
||||
uint32_t Parity; /*!< Specifies the parity mode which could be 0 parity,
|
||||
1 parity, odd parity, even parity or no parity. */
|
||||
uint32_t Mode; /*!< Enables or disables Receive, Transmit or
|
||||
both. */
|
||||
uint32_t FlowCtrl; /*!< Specifies the hardware flow control mode, which can be
|
||||
CTS flow control, RTS flow control or none flow control. */
|
||||
} FUART_InitTypeDef;
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART_Exported_Types */
|
||||
|
||||
/** @defgroup FUART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FUART0 TSB_UART0
|
||||
#define FUART1 TSB_UART1
|
||||
#define TSB_FUART_TypeDef TSB_UART_TypeDef
|
||||
|
||||
#define IS_FUART_PERIPH(param) (((param) == FUART0) || \
|
||||
((param) == FUART1))
|
||||
|
||||
#define IS_FUART_BAUDRATE(param) (((param) != 0U) && \
|
||||
((param) <= 2950000U))
|
||||
|
||||
#define FUART_DATA_BITS_5 ((uint32_t)0x00000000)
|
||||
#define FUART_DATA_BITS_6 ((uint32_t)0x00000020)
|
||||
#define FUART_DATA_BITS_7 ((uint32_t)0x00000040)
|
||||
#define FUART_DATA_BITS_8 ((uint32_t)0x00000060)
|
||||
|
||||
#define IS_FUART_DATA_BITS(param) (((param) == FUART_DATA_BITS_5) || \
|
||||
((param) == FUART_DATA_BITS_6) || \
|
||||
((param) == FUART_DATA_BITS_7) || \
|
||||
((param) == FUART_DATA_BITS_8))
|
||||
|
||||
#define FUART_STOP_BITS_1 ((uint32_t)0x00000000)
|
||||
#define FUART_STOP_BITS_2 ((uint32_t)0x00000008)
|
||||
#define IS_FUART_STOPBITS(param) (((param) == FUART_STOP_BITS_1) || \
|
||||
((param) == FUART_STOP_BITS_2))
|
||||
|
||||
#define FUART_NO_PARITY ((uint32_t)0x00000000)
|
||||
#define FUART_0_PARITY ((uint32_t)0x00000086)
|
||||
#define FUART_1_PARITY ((uint32_t)0x00000082)
|
||||
#define FUART_EVEN_PARITY ((uint32_t)0x00000006)
|
||||
#define FUART_ODD_PARITY ((uint32_t)0x00000002)
|
||||
#define IS_FUART_PARITY(param) (((param) == FUART_NO_PARITY) || \
|
||||
((param) == FUART_0_PARITY) || \
|
||||
((param) == FUART_1_PARITY) || \
|
||||
((param) == FUART_EVEN_PARITY) || \
|
||||
((param) == FUART_ODD_PARITY))
|
||||
|
||||
#define FUART_ENABLE_RX ((uint32_t)0x00000200)
|
||||
#define FUART_ENABLE_TX ((uint32_t)0x00000100)
|
||||
#define IS_FUART_MODE(param) (((param) == FUART_ENABLE_RX) || \
|
||||
((param) == FUART_ENABLE_TX) || \
|
||||
((param) == (FUART_ENABLE_TX | FUART_ENABLE_RX)))
|
||||
|
||||
#define FUART_NONE_FLOW_CTRL ((uint32_t)0x00000000)
|
||||
#define FUART_CTS_FLOW_CTRL ((uint32_t)0x00008000)
|
||||
#define FUART_RTS_FLOW_CTRL ((uint32_t)0x00004000)
|
||||
#define IS_FUART_FLOW_CTRL(param) (((param) == FUART_NONE_FLOW_CTRL) || \
|
||||
((param) == FUART_CTS_FLOW_CTRL) || \
|
||||
((param) == FUART_RTS_FLOW_CTRL) || \
|
||||
((param) == (FUART_CTS_FLOW_CTRL | FUART_RTS_FLOW_CTRL)))
|
||||
|
||||
#define FUART_IRDA_3_16_BIT_PERIOD_MODE ((uint32_t)0x00000000)
|
||||
#define FUART_IRDA_3_TIMES_IRLPBAUD16_MODE ((uint32_t)0x00000004)
|
||||
#define IS_IRDA_ENCODE_MODE(param) (((param) == FUART_IRDA_3_16_BIT_PERIOD_MODE) || \
|
||||
((param) == FUART_IRDA_3_TIMES_IRLPBAUD16_MODE))
|
||||
|
||||
#define FUART_RX_FIFO_LEVEL_4 ((uint32_t)0x00000000)
|
||||
#define FUART_RX_FIFO_LEVEL_8 ((uint32_t)0x00000008)
|
||||
#define FUART_RX_FIFO_LEVEL_16 ((uint32_t)0x00000010)
|
||||
#define FUART_RX_FIFO_LEVEL_24 ((uint32_t)0x00000018)
|
||||
#define FUART_RX_FIFO_LEVEL_28 ((uint32_t)0x00000020)
|
||||
#define IS_FUART_RX_FIFO_LEVEL(param) (((param) == FUART_RX_FIFO_LEVEL_4) || \
|
||||
((param) == FUART_RX_FIFO_LEVEL_8) || \
|
||||
((param) == FUART_RX_FIFO_LEVEL_16) || \
|
||||
((param) == FUART_RX_FIFO_LEVEL_24) || \
|
||||
((param) == FUART_RX_FIFO_LEVEL_28))
|
||||
|
||||
#define FUART_TX_FIFO_LEVEL_4 ((uint32_t)0x00000000)
|
||||
#define FUART_TX_FIFO_LEVEL_8 ((uint32_t)0x00000001)
|
||||
#define FUART_TX_FIFO_LEVEL_16 ((uint32_t)0x00000002)
|
||||
#define FUART_TX_FIFO_LEVEL_24 ((uint32_t)0x00000003)
|
||||
#define FUART_TX_FIFO_LEVEL_28 ((uint32_t)0x00000004)
|
||||
#define IS_FUART_TX_FIFO_LEVEL(param) (((param) == FUART_TX_FIFO_LEVEL_4) || \
|
||||
((param) == FUART_TX_FIFO_LEVEL_8) || \
|
||||
((param) == FUART_TX_FIFO_LEVEL_16) || \
|
||||
((param) == FUART_TX_FIFO_LEVEL_24) || \
|
||||
((param) == FUART_TX_FIFO_LEVEL_28))
|
||||
|
||||
|
||||
#define FUART_NONE_INT_MASK ((uint32_t)0x00000000)
|
||||
#define FUART_RIN_MODEM_INT_MASK ((uint32_t)0x00000001)
|
||||
#define FUART_CTS_MODEM_INT_MASK ((uint32_t)0x00000002)
|
||||
#define FUART_DCD_MODEM_INT_MASK ((uint32_t)0x00000004)
|
||||
#define FUART_DSR_MODEM_INT_MASK ((uint32_t)0x00000008)
|
||||
#define FUART_RX_FIFO_INT_MASK ((uint32_t)0x00000010)
|
||||
#define FUART_TX_FIFO_INT_MASK ((uint32_t)0x00000020)
|
||||
#define FUART_RX_TIMEOUT_INT_MASK ((uint32_t)0x00000040)
|
||||
#define FUART_FRAMING_ERR_INT_MASK ((uint32_t)0x00000080)
|
||||
#define FUART_PARITY_ERR_INT_MASK ((uint32_t)0x00000100)
|
||||
#define FUART_BREAK_ERR_INT_MASK ((uint32_t)0x00000200)
|
||||
#define FUART_OVERRUN_ERR_INT_MASK ((uint32_t)0x00000400)
|
||||
#define FUART_ALL_INT_MASK ((uint32_t)0x000007FF)
|
||||
|
||||
#define IS_INT_MASK_SRC(param) ((param) <= FUART_ALL_INT_MASK)
|
||||
|
||||
#define IS_FUART_DATA(param) ((param) <= (uint32_t)0x000000FF)
|
||||
|
||||
#define IS_FUART_IRDA_DIVISOR(param) (((param) != (uint32_t)0x00000000) && \
|
||||
((param) <= (uint32_t)0x000000FF))
|
||||
/** @} */
|
||||
/* End of group FUART_Exported_Constants */
|
||||
|
||||
/** @addtogroup FUART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
FUART_STORAGE_EMPTY = 0U,
|
||||
FUART_STORAGE_NORMAL = 1U,
|
||||
FUART_STORAGE_INVALID = 2U,
|
||||
FUART_STORAGE_FULL = 3U
|
||||
} FUART_StorageStatus;
|
||||
|
||||
typedef enum {
|
||||
FUART_RX = 0U,
|
||||
FUART_TX = 1U
|
||||
} FUART_Direction;
|
||||
|
||||
#define IS_FUART_DIRECTION(param) (((param) == FUART_RX) || \
|
||||
((param) == FUART_TX))
|
||||
|
||||
typedef enum {
|
||||
FUART_NO_ERR = 0U,
|
||||
FUART_OVERRUN = 1U,
|
||||
FUART_PARITY_ERR = 2U,
|
||||
FUART_FRAMING_ERR = 3U,
|
||||
FUART_BREAK_ERR = 4U,
|
||||
FUART_ERRS = 5U
|
||||
} FUART_Err;
|
||||
|
||||
typedef union {
|
||||
uint32_t All;
|
||||
struct {
|
||||
uint32_t RIN:1; /* bit 0 */
|
||||
uint32_t CTS:1; /* bit 1 */
|
||||
uint32_t DCD:1; /* bit 2 */
|
||||
uint32_t DSR:1; /* bit 3 */
|
||||
uint32_t RxFIFO:1; /* bit 4 */
|
||||
uint32_t TxFIFO:1; /* bit 5 */
|
||||
uint32_t RxTimeout:1; /* bit 6 */
|
||||
uint32_t FramingErr:1; /* bit 7 */
|
||||
uint32_t ParityErr:1; /* bit 8 */
|
||||
uint32_t BreakErr:1; /* bit 9 */
|
||||
uint32_t OverrunErr:1; /* bit 10 */
|
||||
uint32_t Reserved:21; /* bit 11~31 */
|
||||
} Bit;
|
||||
} FUART_INTStatus;
|
||||
|
||||
typedef union {
|
||||
uint32_t All;
|
||||
struct {
|
||||
uint32_t CTS:1; /* bit 0 */
|
||||
uint32_t DSR:1; /* bit 1 */
|
||||
uint32_t DCD:1; /* bit 2 */
|
||||
uint32_t Reserved1:5; /* bit 3~7 */
|
||||
uint32_t RI:1; /* bit 8 */
|
||||
uint32_t Reserved2:1; /* bit 9 */
|
||||
uint32_t DTR:1; /* bit 10 */
|
||||
uint32_t RTS:1; /* bit 11 */
|
||||
uint32_t Reserved3:20; /* bit 12~31 */
|
||||
} Bit;
|
||||
} FUART_AllModemStatus;
|
||||
|
||||
typedef enum {
|
||||
FUART_MODEM_STATUS_1 = 0U,
|
||||
FUART_MODEM_STATUS_0 = 1U
|
||||
} FUART_ModemStatus;
|
||||
|
||||
#define IS_MODEM_STATUS(param) (((param) == FUART_MODEM_STATUS_1) || \
|
||||
((param) == FUART_MODEM_STATUS_0))
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART_Exported_Types */
|
||||
|
||||
/** @defgroup FUART_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FUART_Enable(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_Disable(TSB_FUART_TypeDef * FUARTx);
|
||||
uint32_t FUART_GetRxData(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_SetTxData(TSB_FUART_TypeDef * FUARTx, uint32_t Data);
|
||||
FUART_Err FUART_GetErrStatus(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_ClearErrStatus(TSB_FUART_TypeDef * FUARTx);
|
||||
WorkState FUART_GetBusyState(TSB_FUART_TypeDef * FUARTx);
|
||||
FUART_StorageStatus FUART_GetStorageStatus(TSB_FUART_TypeDef * FUARTx,
|
||||
FUART_Direction Direction);
|
||||
void FUART_SetIrDADivisor(TSB_FUART_TypeDef * FUARTx, uint32_t Divisor);
|
||||
void FUART_Init(TSB_FUART_TypeDef * FUARTx, FUART_InitTypeDef * InitStruct);
|
||||
void FUART_EnableFIFO(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_DisableFIFO(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_SetSendBreak(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState);
|
||||
void FUART_SetIrDAEncodeMode(TSB_FUART_TypeDef * FUARTx, uint32_t Mode);
|
||||
Result FUART_EnableIrDA(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_DisableIrDA(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_SetINTFIFOLevel(TSB_FUART_TypeDef * FUARTx, uint32_t RxLevel, uint32_t TxLevel);
|
||||
void FUART_SetINTMask(TSB_FUART_TypeDef * FUARTx, uint32_t IntMaskSrc);
|
||||
FUART_INTStatus FUART_GetINTMask(TSB_FUART_TypeDef * FUARTx);
|
||||
FUART_INTStatus FUART_GetRawINTStatus(TSB_FUART_TypeDef * FUARTx);
|
||||
FUART_INTStatus FUART_GetMaskedINTStatus(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_ClearINT(TSB_FUART_TypeDef * FUARTx, FUART_INTStatus INTStatus);
|
||||
void FUART_SetDMAOnErr(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState);
|
||||
void FUART_SetFIFODMA(TSB_FUART_TypeDef * FUARTx, FUART_Direction Direction,
|
||||
FunctionalState NewState);
|
||||
FUART_AllModemStatus FUART_GetModemStatus(TSB_FUART_TypeDef * FUARTx);
|
||||
void FUART_SetRTSStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status);
|
||||
void FUART_SetDTRStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status);
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART_Exported_FunctionPrototypes */
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __TMPM46B_FUART_H */
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_gpio.h
|
||||
* @brief This file provides all the functions prototypes for GPIO driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/09
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_GPIO_H
|
||||
#define __TMPM46B_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup GPIO_Parameter_Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief :The maximum number of the Function Register
|
||||
* Note for porting:
|
||||
* If function register 6 is the maximum number in
|
||||
* all the GPIO port,then define FRMAX (6U)
|
||||
*/
|
||||
#define FRMAX (6U) /* the max number of Port I/O function register is 6 */
|
||||
|
||||
/** @brief: define for function register
|
||||
* Note for porting:
|
||||
* If the maximum number of the function Register is 6,
|
||||
* then you need to define 6 GPIO_FUNC_REG_x ,
|
||||
* the value should be increased from 0 to 5
|
||||
*/
|
||||
#define GPIO_FUNC_REG_1 ((uint8_t)0x00)
|
||||
#define GPIO_FUNC_REG_2 ((uint8_t)0x01)
|
||||
#define GPIO_FUNC_REG_3 ((uint8_t)0x02)
|
||||
#define GPIO_FUNC_REG_4 ((uint8_t)0x03)
|
||||
#define GPIO_FUNC_REG_5 ((uint8_t)0x04)
|
||||
#define GPIO_FUNC_REG_6 ((uint8_t)0x05)
|
||||
|
||||
/** @brief :The GPIO_Port enum
|
||||
* Note for porting:
|
||||
* the port value order from low to high with '1' step
|
||||
* and begin with "0".
|
||||
*/
|
||||
typedef enum {
|
||||
GPIO_PA = 0U,
|
||||
GPIO_PB = 1U,
|
||||
GPIO_PC = 2U,
|
||||
GPIO_PD = 3U,
|
||||
GPIO_PE = 4U,
|
||||
GPIO_PF = 5U,
|
||||
GPIO_PG = 6U,
|
||||
GPIO_PH = 7U,
|
||||
GPIO_PJ = 8U,
|
||||
GPIO_PK = 9U,
|
||||
GPIO_PL = 10U
|
||||
} GPIO_Port;
|
||||
|
||||
#define IS_GPIO_PORT(param) ((param) <= GPIO_PL) /* parameter checking for port number */
|
||||
|
||||
#define RESER (8U-(FRMAX))
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t DATA;
|
||||
__IO uint32_t CR;
|
||||
__IO uint32_t FR[FRMAX];
|
||||
uint32_t RESERVED0[RESER];
|
||||
__IO uint32_t OD;
|
||||
__IO uint32_t PUP;
|
||||
__IO uint32_t PDN;
|
||||
uint32_t RESERVED1;
|
||||
__IO uint32_t IE;
|
||||
} TSB_Port_TypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint8_t PinDATA;
|
||||
uint8_t PinCR;
|
||||
uint8_t PinFR[FRMAX];
|
||||
uint8_t PinOD;
|
||||
uint8_t PinPUP;
|
||||
uint8_t PinPDN;
|
||||
uint8_t PinIE;
|
||||
} GPIO_RegTypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint8_t IOMode; /* Set the port input or output mode */
|
||||
uint8_t PullUp; /* Enable or disable Pull-up function */
|
||||
uint8_t OpenDrain; /* Enable or disable open drain function */
|
||||
uint8_t PullDown; /* Enable or disable Pull-down function */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
#define GPIO_INPUT_MODE ((uint8_t)0x00)
|
||||
#define GPIO_OUTPUT_MODE ((uint8_t)0x01)
|
||||
#define GPIO_IO_MODE_NONE ((uint8_t)0x02)
|
||||
#define IS_GPIO_IO_MODE_STATE(param) (((param) == GPIO_INPUT_MODE) || \
|
||||
((param) == GPIO_OUTPUT_MODE) || \
|
||||
((param) == GPIO_IO_MODE_NONE))
|
||||
|
||||
#define GPIO_PULLUP_DISABLE ((uint8_t)0x00)
|
||||
#define GPIO_PULLUP_ENABLE ((uint8_t)0x01)
|
||||
#define GPIO_PULLUP_NONE ((uint8_t)0x02)
|
||||
#define IS_GPIO_PULLUP_STATE(param) (((param) == GPIO_PULLUP_ENABLE) || \
|
||||
((param) == GPIO_PULLUP_DISABLE) || \
|
||||
((param) == GPIO_PULLUP_NONE))
|
||||
|
||||
#define GPIO_PULLDOWN_DISABLE ((uint8_t)0x00)
|
||||
#define GPIO_PULLDOWN_ENABLE ((uint8_t)0x01)
|
||||
#define GPIO_PULLDOWN_NONE ((uint8_t)0x02)
|
||||
#define IS_GPIO_PULLDOWN_STATE(param) (((param) == GPIO_PULLDOWN_ENABLE) || \
|
||||
((param) == GPIO_PULLDOWN_DISABLE) || \
|
||||
((param) == GPIO_PULLDOWN_NONE))
|
||||
|
||||
#define GPIO_OPEN_DRAIN_DISABLE ((uint8_t)0x00)
|
||||
#define GPIO_OPEN_DRAIN_ENABLE ((uint8_t)0x01)
|
||||
#define GPIO_OPEN_DRAIN_NONE ((uint8_t)0x02)
|
||||
#define IS_GPIO_OPEN_DRAIN_STATE(param) (((param) == GPIO_OPEN_DRAIN_ENABLE) || \
|
||||
((param) == GPIO_OPEN_DRAIN_DISABLE) || \
|
||||
((param) == GPIO_OPEN_DRAIN_NONE))
|
||||
|
||||
#define GPIO_BIT_VALUE_1 ((uint8_t)0x01)
|
||||
#define GPIO_BIT_VALUE_0 ((uint8_t)0x00)
|
||||
|
||||
#define IS_GPIO_BIT_VALUE(BitValue) (((BitValue) == GPIO_BIT_VALUE_1)|| \
|
||||
((BitValue) == GPIO_BIT_VALUE_0))
|
||||
|
||||
#define GPIO_BIT_0 ((uint8_t)0x01)
|
||||
#define GPIO_BIT_1 ((uint8_t)0x02)
|
||||
#define GPIO_BIT_2 ((uint8_t)0x04)
|
||||
#define GPIO_BIT_3 ((uint8_t)0x08)
|
||||
#define GPIO_BIT_4 ((uint8_t)0x10)
|
||||
#define GPIO_BIT_5 ((uint8_t)0x20)
|
||||
#define GPIO_BIT_6 ((uint8_t)0x40)
|
||||
#define GPIO_BIT_7 ((uint8_t)0x80)
|
||||
#define GPIO_BIT_ALL ((uint8_t)0xFF)
|
||||
|
||||
#define IS_GPIO_WRITE(GPIO_x) (GPIO_SFRs[(GPIO_x)].PinCR)
|
||||
|
||||
#define IS_GPIO_BIT_DATA(GPIO_x,Bit_x) ((((GPIO_SFRs[(GPIO_x)].PinDATA) & (Bit_x))&&\
|
||||
(!((uint8_t)(~(GPIO_SFRs[(GPIO_x)].PinDATA))&(Bit_x)))))
|
||||
|
||||
#define IS_GPIO_BIT_OUT(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinCR &(Bit_x))&&\
|
||||
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinCR)&(Bit_x)))))
|
||||
|
||||
#define IS_GPIO_BIT_IN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinIE &(Bit_x))&&\
|
||||
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinIE)&(Bit_x)))))
|
||||
|
||||
#define IS_GPIO_BIT_PUP(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPUP &(Bit_x))&&\
|
||||
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPUP)&(Bit_x)))))
|
||||
|
||||
#define IS_GPIO_BIT_PDN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPDN &(Bit_x))&&\
|
||||
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPDN)&(Bit_x)))))
|
||||
|
||||
#define IS_GPIO_BIT_OD(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinOD &(Bit_x))&&\
|
||||
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinOD)&(Bit_x)))))
|
||||
|
||||
#define IS_GPIO_BIT_FR(GPIO_x,FuncReg_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)]&(Bit_x))&&\
|
||||
(!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)])&(Bit_x)))))
|
||||
|
||||
#define IS_GPIO_FUNCTION_REG(param) ((param) < (FRMAX))
|
||||
|
||||
#define IS_GPIO_BIT(param) (((param) == GPIO_BIT_0)|| \
|
||||
((param) == GPIO_BIT_1)|| \
|
||||
((param) == GPIO_BIT_2)|| \
|
||||
((param) == GPIO_BIT_3)|| \
|
||||
((param) == GPIO_BIT_4)|| \
|
||||
((param) == GPIO_BIT_5)|| \
|
||||
((param) == GPIO_BIT_6)|| \
|
||||
((param) == GPIO_BIT_7))
|
||||
/** @} */
|
||||
/* End of group GPIO_Bit_Define */
|
||||
|
||||
/** @defgroup GPIO_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint8_t GPIO_ReadData(GPIO_Port GPIO_x);
|
||||
uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x);
|
||||
void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data);
|
||||
void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue);
|
||||
void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct);
|
||||
void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x);
|
||||
void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x);
|
||||
void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
|
||||
void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
|
||||
void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
|
||||
void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
|
||||
void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
|
||||
void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
|
||||
void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
|
||||
|
||||
/** @} */
|
||||
/* End of group GPIO_Exported_FunctionPrototypes */
|
||||
/** @} */
|
||||
/* End of group GPIO */
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __TMPM46B_GPIO_H */
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_i2c.h
|
||||
* @brief This file provides all the functions prototypes for I2C driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/13
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_I2C_H
|
||||
#define __TMPM46B_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /*__cplusplus*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t I2CSelfAddr; /*!< Specify self-address of the I2C channel in I2C mode */
|
||||
uint32_t I2CDataLen; /*!< Specify data length of the I2C channel in I2C mode */
|
||||
FunctionalState I2CACKState; /*!< Enable or disable the generation of ACK clock */
|
||||
uint32_t I2CClkDiv; /*!< Select the division of the prescaler clock for generating the serial clock */
|
||||
uint32_t PrescalerClkDiv; /*!< Select the division of fsys for generating the fprsck */
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint32_t All;
|
||||
struct {
|
||||
uint32_t LastRxBit:1;
|
||||
uint32_t GeneralCall:1;
|
||||
uint32_t SlaveAddrMatch:1;
|
||||
uint32_t ArbitrationLost:1;
|
||||
uint32_t INTReq:1;
|
||||
uint32_t BusState:1;
|
||||
uint32_t TRx:1;
|
||||
uint32_t MasterSlave:1;
|
||||
} Bit;
|
||||
} I2C_State;
|
||||
|
||||
#define I2C_CHANNEL_NUMBER 3U
|
||||
#define IS_I2C_PERIPH(param) (((param) == TSB_I2C0) || \
|
||||
((param) == TSB_I2C1) || \
|
||||
((param) == TSB_I2C2))
|
||||
|
||||
#define I2C_DATA_LEN_8 ((uint32_t)0x00000000)
|
||||
#define I2C_DATA_LEN_1 ((uint32_t)0x00000001)
|
||||
#define I2C_DATA_LEN_2 ((uint32_t)0x00000002)
|
||||
#define I2C_DATA_LEN_3 ((uint32_t)0x00000003)
|
||||
#define I2C_DATA_LEN_4 ((uint32_t)0x00000004)
|
||||
#define I2C_DATA_LEN_5 ((uint32_t)0x00000005)
|
||||
#define I2C_DATA_LEN_6 ((uint32_t)0x00000006)
|
||||
#define I2C_DATA_LEN_7 ((uint32_t)0x00000007)
|
||||
|
||||
#define I2C_SCK_CLK_DIV_20 ((uint32_t)0x00000000)
|
||||
#define I2C_SCK_CLK_DIV_24 ((uint32_t)0x00000001)
|
||||
#define I2C_SCK_CLK_DIV_32 ((uint32_t)0x00000002)
|
||||
#define I2C_SCK_CLK_DIV_48 ((uint32_t)0x00000003)
|
||||
#define I2C_SCK_CLK_DIV_80 ((uint32_t)0x00000004)
|
||||
#define I2C_SCK_CLK_DIV_144 ((uint32_t)0x00000005)
|
||||
#define I2C_SCK_CLK_DIV_272 ((uint32_t)0x00000006)
|
||||
#define I2C_SCK_CLK_DIV_528 ((uint32_t)0x00000007)
|
||||
#define IS_I2C_SCK_CLK_DIV(param) (((param) == I2C_SCK_CLK_DIV_20) || \
|
||||
((param) == I2C_SCK_CLK_DIV_24) || \
|
||||
((param) == I2C_SCK_CLK_DIV_32) || \
|
||||
((param) == I2C_SCK_CLK_DIV_48) || \
|
||||
((param) == I2C_SCK_CLK_DIV_80) || \
|
||||
((param) == I2C_SCK_CLK_DIV_144) || \
|
||||
((param) == I2C_SCK_CLK_DIV_272) || \
|
||||
((param) == I2C_SCK_CLK_DIV_528))
|
||||
|
||||
#define I2C_PRESCALER_DIV_1 ((uint32_t)0x00000001)
|
||||
#define I2C_PRESCALER_DIV_2 ((uint32_t)0x00000002)
|
||||
#define I2C_PRESCALER_DIV_3 ((uint32_t)0x00000003)
|
||||
#define I2C_PRESCALER_DIV_4 ((uint32_t)0x00000004)
|
||||
#define I2C_PRESCALER_DIV_5 ((uint32_t)0x00000005)
|
||||
#define I2C_PRESCALER_DIV_6 ((uint32_t)0x00000006)
|
||||
#define I2C_PRESCALER_DIV_7 ((uint32_t)0x00000007)
|
||||
#define I2C_PRESCALER_DIV_8 ((uint32_t)0x00000008)
|
||||
#define I2C_PRESCALER_DIV_9 ((uint32_t)0x00000009)
|
||||
#define I2C_PRESCALER_DIV_10 ((uint32_t)0x0000000A)
|
||||
#define I2C_PRESCALER_DIV_11 ((uint32_t)0x0000000B)
|
||||
#define I2C_PRESCALER_DIV_12 ((uint32_t)0x0000000C)
|
||||
#define I2C_PRESCALER_DIV_13 ((uint32_t)0x0000000D)
|
||||
#define I2C_PRESCALER_DIV_14 ((uint32_t)0x0000000E)
|
||||
#define I2C_PRESCALER_DIV_15 ((uint32_t)0x0000000F)
|
||||
#define I2C_PRESCALER_DIV_16 ((uint32_t)0x00000010)
|
||||
#define I2C_PRESCALER_DIV_17 ((uint32_t)0x00000011)
|
||||
#define I2C_PRESCALER_DIV_18 ((uint32_t)0x00000012)
|
||||
#define I2C_PRESCALER_DIV_19 ((uint32_t)0x00000013)
|
||||
#define I2C_PRESCALER_DIV_20 ((uint32_t)0x00000014)
|
||||
#define I2C_PRESCALER_DIV_21 ((uint32_t)0x00000015)
|
||||
#define I2C_PRESCALER_DIV_22 ((uint32_t)0x00000016)
|
||||
#define I2C_PRESCALER_DIV_23 ((uint32_t)0x00000017)
|
||||
#define I2C_PRESCALER_DIV_24 ((uint32_t)0x00000018)
|
||||
#define I2C_PRESCALER_DIV_25 ((uint32_t)0x00000019)
|
||||
#define I2C_PRESCALER_DIV_26 ((uint32_t)0x0000001A)
|
||||
#define I2C_PRESCALER_DIV_27 ((uint32_t)0x0000001B)
|
||||
#define I2C_PRESCALER_DIV_28 ((uint32_t)0x0000001C)
|
||||
#define I2C_PRESCALER_DIV_29 ((uint32_t)0x0000001D)
|
||||
#define I2C_PRESCALER_DIV_30 ((uint32_t)0x0000001E)
|
||||
#define I2C_PRESCALER_DIV_31 ((uint32_t)0x0000001F)
|
||||
#define I2C_PRESCALER_DIV_32 ((uint32_t)0x00000020)
|
||||
|
||||
/** @} */
|
||||
/* End of group I2C_Exported_Types */
|
||||
|
||||
/** @defgroup I2C_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_PRESCALER_CLK_VALID(param1, param2) (((param1) >= I2C_PRESCALER_DIV_1) && \
|
||||
((param1) <= I2C_PRESCALER_DIV_32) && \
|
||||
(((param2) / (param1)) > 666666U) && \
|
||||
(((param2) / (param1)) < 20000000U))
|
||||
|
||||
#define IS_I2C_DATA(param) ((param) <= (uint32_t)0x000000FF)
|
||||
|
||||
#define IS_I2C_BIT_NUM(param) ((param) <= (uint32_t)0x00000007)
|
||||
|
||||
#define IS_I2C_ADDR(param) (((param) < (uint32_t)0x000000FF) && \
|
||||
(!((param) & (uint32_t)0x00000001)))
|
||||
|
||||
/** @} */
|
||||
/* End of group I2C_Exported_Macros */
|
||||
|
||||
/** @defgroup I2C_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
|
||||
void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct);
|
||||
void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum);
|
||||
void I2C_SWReset(TSB_I2C_TypeDef * I2Cx);
|
||||
void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx);
|
||||
void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx);
|
||||
void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx);
|
||||
I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx);
|
||||
void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data);
|
||||
uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx);
|
||||
void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
|
||||
FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx);
|
||||
void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock);
|
||||
void I2C_SetINTReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
|
||||
FunctionalState I2C_GetINTStatus(TSB_I2C_TypeDef * I2Cx);
|
||||
void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx);
|
||||
/** @} */
|
||||
/* End of group I2C_Exported_FunctionPrototypes */
|
||||
|
||||
/** @} */
|
||||
/* End of group I2C */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __TMPM46B_I2C_H */
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_rtc.h
|
||||
* @brief This file provides all the functions prototypes for RTC driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/11
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_RTC_H
|
||||
#define __TMPM46B_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RTC Structure definition
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
uint8_t HourMode; /*!< Select RTC 12-Hour mode or 24-Hour mode */
|
||||
uint8_t Hour; /*!< Set RTC hour value */
|
||||
uint8_t AmPm; /*!< Select AM/PM mode in 12H mode */
|
||||
uint8_t Min; /*!< Set RTC minute value */
|
||||
uint8_t Sec; /*!< Set RTC second value */
|
||||
} RTC_TimeTypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint8_t LeapYear; /*!< Select RTC Leap-Year status */
|
||||
uint8_t Year; /*!< Set RTC year value */
|
||||
uint8_t Month; /*!< Set RTC month value */
|
||||
uint8_t Date; /*!< Set RTC date value */
|
||||
uint8_t Day; /*!< Set RTC day value */
|
||||
} RTC_DateTypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint8_t Date; /*!< Set alarm date value */
|
||||
uint8_t Day; /*!< Set alarm day value */
|
||||
uint8_t Hour; /*!< Set alarm hour value */
|
||||
uint8_t AmPm; /*!< Select AM/PM mode in 12H mode */
|
||||
uint8_t Min; /*!< Set alarm minute value */
|
||||
} RTC_AlarmTypeDef;
|
||||
|
||||
/** @} */
|
||||
/* End of group RTC_Exported_Types */
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_24_HOUR_MODE ((uint8_t)0x01)
|
||||
#define RTC_12_HOUR_MODE ((uint8_t)0x00)
|
||||
#define IS_RTC_HOUR_MODE(param) (((param) == RTC_24_HOUR_MODE) || \
|
||||
((param) == RTC_12_HOUR_MODE))
|
||||
|
||||
#define RTC_AM_MODE ((uint8_t)0x00)
|
||||
#define RTC_PM_MODE ((uint8_t)0x01)
|
||||
#define RTC_AMPM_INVALID ((uint8_t)0x02)
|
||||
#define IS_RTC_AMPM_MODE(param) (((param) == RTC_AM_MODE) || \
|
||||
((param) == RTC_PM_MODE))
|
||||
|
||||
#define RTC_LEAP_YEAR_0 ((uint8_t)0x00)
|
||||
#define RTC_LEAP_YEAR_1 ((uint8_t)0x01)
|
||||
#define RTC_LEAP_YEAR_2 ((uint8_t)0x02)
|
||||
#define RTC_LEAP_YEAR_3 ((uint8_t)0x03)
|
||||
#define IS_RTC_LEAP_YEAR(param) (((param) == RTC_LEAP_YEAR_0) || \
|
||||
((param) == RTC_LEAP_YEAR_1) || \
|
||||
((param) == RTC_LEAP_YEAR_2) || \
|
||||
((param) == RTC_LEAP_YEAR_3))
|
||||
|
||||
#define RTC_SUN ((uint8_t)0x00)
|
||||
#define RTC_MON ((uint8_t)0x01)
|
||||
#define RTC_TUE ((uint8_t)0x02)
|
||||
#define RTC_WED ((uint8_t)0x03)
|
||||
#define RTC_THU ((uint8_t)0x04)
|
||||
#define RTC_FRI ((uint8_t)0x05)
|
||||
#define RTC_SAT ((uint8_t)0x06)
|
||||
#define IS_RTC_DAY(param) (((param) == RTC_SUN) || \
|
||||
((param) == RTC_MON) || \
|
||||
((param) == RTC_TUE) || \
|
||||
((param) == RTC_WED) || \
|
||||
((param) == RTC_THU) || \
|
||||
((param) == RTC_FRI) || \
|
||||
((param) == RTC_SAT))
|
||||
|
||||
#define RTC_LOW_LEVEL ((uint8_t)0x00)
|
||||
#define RTC_PULSE_1_HZ ((uint8_t)0x01)
|
||||
#define RTC_PULSE_16_HZ ((uint8_t)0x02)
|
||||
#define RTC_PULSE_2_HZ ((uint8_t)0x03)
|
||||
#define RTC_PULSE_4_HZ ((uint8_t)0x04)
|
||||
#define RTC_PULSE_8_HZ ((uint8_t)0x05)
|
||||
#define IS_RTC_ALARM_OUTPUT(param) (((param) == RTC_LOW_LEVEL) || \
|
||||
((param) == RTC_PULSE_1_HZ) || \
|
||||
((param) == RTC_PULSE_16_HZ)|| \
|
||||
((param) == RTC_PULSE_2_HZ) || \
|
||||
((param) == RTC_PULSE_4_HZ) || \
|
||||
((param) == RTC_PULSE_8_HZ))
|
||||
|
||||
#define IS_RTC_YEAR(param) ((param) <= 99U)
|
||||
|
||||
#define IS_RTC_MONTH(param) (((param) >= 1U)&&((param) <= 12U))
|
||||
|
||||
#define IS_RTC_DATE(param) (((param) >= 1U)&&((param) <= 31U))
|
||||
|
||||
#define IS_RTC_HOUR_24(param) ((param) <= 23U)
|
||||
|
||||
#define IS_RTC_HOUR_12(param) ((param) <= 11U)
|
||||
|
||||
#define IS_RTC_MINUTE(param) ((param) <= 59U)
|
||||
|
||||
#define IS_RTC_SECOND(param) ((param) <= 59U)
|
||||
|
||||
#define RTC_ADJ_TIME_1_SEC ((uint8_t)0x00)
|
||||
#define RTC_ADJ_TIME_10_SEC ((uint8_t)0x02)
|
||||
#define RTC_ADJ_TIME_20_SEC ((uint8_t)0x04)
|
||||
#define RTC_ADJ_TIME_30_SEC ((uint8_t)0x06)
|
||||
#define RTC_ADJ_TIME_1_MIN ((uint8_t)0x08)
|
||||
#define IS_RTC_ADJ_TIME(param) (((param) == RTC_ADJ_TIME_1_SEC) || \
|
||||
((param) == RTC_ADJ_TIME_10_SEC) || \
|
||||
((param) == RTC_ADJ_TIME_20_SEC) || \
|
||||
((param) == RTC_ADJ_TIME_30_SEC) || \
|
||||
((param) == RTC_ADJ_TIME_1_MIN))
|
||||
/** @} */
|
||||
/* End of group RTC_Exported_Constants */
|
||||
|
||||
/** @defgroup RTC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
RTC_NO_REQ = 0U,
|
||||
RTC_REQ = 1U
|
||||
} RTC_ReqState;
|
||||
|
||||
typedef enum {
|
||||
RTC_CLOCK_MODE = 0U,
|
||||
RTC_ALARM_MODE = 1U
|
||||
} RTC_FuncMode;
|
||||
#define IS_RTC_FUNC_MODE(param) (((param) == RTC_CLOCK_MODE) || \
|
||||
((param) == RTC_ALARM_MODE))
|
||||
|
||||
typedef enum {
|
||||
RTC_CORRECTION_PLUS = 0U,
|
||||
RTC_CORRECTION_MINUS = 1U
|
||||
} RTC_CorrectionMode;
|
||||
#define IS_RTC_CORRECTION_MODE(param) (((param) == RTC_CORRECTION_PLUS) || \
|
||||
((param) == RTC_CORRECTION_MINUS))
|
||||
|
||||
#define IS_RTC_PLUS_VALUE(param) ((param) <= 255U)
|
||||
#define IS_RTC_MINUS_VALUE(param) (((param) >= 1U)&&((param) <= 256U))
|
||||
/** @} */
|
||||
/* End of group RTC_Exported_Types */
|
||||
|
||||
/** @defgroup RTC_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
void RTC_SetSec(uint8_t Sec);
|
||||
uint8_t RTC_GetSec(void);
|
||||
void RTC_SetMin(RTC_FuncMode NewMode, uint8_t Min);
|
||||
uint8_t RTC_GetMin(RTC_FuncMode NewMode);
|
||||
uint8_t RTC_GetAMPM(RTC_FuncMode NewMode);
|
||||
void RTC_SetHour24(RTC_FuncMode NewMode, uint8_t Hour);
|
||||
void RTC_SetHour12(RTC_FuncMode NewMode, uint8_t Hour, uint8_t AmPm);
|
||||
uint8_t RTC_GetHour(RTC_FuncMode NewMode);
|
||||
void RTC_SetDay(RTC_FuncMode NewMode, uint8_t Day);
|
||||
uint8_t RTC_GetDay(RTC_FuncMode NewMode);
|
||||
void RTC_SetDate(RTC_FuncMode NewMode, uint8_t Date);
|
||||
uint8_t RTC_GetDate(RTC_FuncMode NewMode);
|
||||
void RTC_SetMonth(uint8_t Month);
|
||||
uint8_t RTC_GetMonth(void);
|
||||
void RTC_SetYear(uint8_t Year);
|
||||
uint8_t RTC_GetYear(void);
|
||||
void RTC_SetHourMode(uint8_t HourMode);
|
||||
uint8_t RTC_GetHourMode(void);
|
||||
void RTC_SetLeapYear(uint8_t LeapYear);
|
||||
uint8_t RTC_GetLeapYear(void);
|
||||
void RTC_SetTimeAdjustReq(void);
|
||||
RTC_ReqState RTC_GetTimeAdjustReq(void);
|
||||
void RTC_EnableClock(void);
|
||||
void RTC_DisableClock(void);
|
||||
void RTC_EnableAlarm(void);
|
||||
void RTC_DisableAlarm(void);
|
||||
void RTC_SetRTCINT(FunctionalState NewState);
|
||||
void RTC_SetAlarmOutput(uint8_t Output);
|
||||
void RTC_ResetAlarm(void);
|
||||
void RTC_ResetClockSec(void);
|
||||
RTC_ReqState RTC_GetResetClockSecReq(void);
|
||||
void RTC_SetDateValue(RTC_DateTypeDef * DateStruct);
|
||||
void RTC_GetDateValue(RTC_DateTypeDef * DateStruct);
|
||||
void RTC_SetTimeValue(RTC_TimeTypeDef * TimeStruct);
|
||||
void RTC_GetTimeValue(RTC_TimeTypeDef * TimeStruct);
|
||||
void RTC_SetClockValue(RTC_DateTypeDef * DateStruct, RTC_TimeTypeDef * TimeStruct);
|
||||
void RTC_GetClockValue(RTC_DateTypeDef * DateStruct, RTC_TimeTypeDef * TimeStruct);
|
||||
void RTC_SetAlarmValue(RTC_AlarmTypeDef * AlarmStruct);
|
||||
void RTC_GetAlarmValue(RTC_AlarmTypeDef * AlarmStruct);
|
||||
void RTC_SetProtectCtrl(FunctionalState NewState);
|
||||
void RTC_EnableCorrection(void);
|
||||
void RTC_DisableCorrection(void);
|
||||
void RTC_SetCorrectionTime(uint8_t Time);
|
||||
void RTC_SetCorrectionValue(RTC_CorrectionMode Mode, uint16_t Cnt);
|
||||
|
||||
/** @} */
|
||||
/* End of group RTC_Exported_FunctionPrototype */
|
||||
|
||||
/** @} */
|
||||
/* End of group RTC */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __TMPM46B_RTC_H */
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_ssp.h
|
||||
* @brief This file provides all the functions prototypes for SSP driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/05
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_SSP_H
|
||||
#define __TMPM46B_SSP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SSP_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SSP_PERIPH(param) (((param) == TSB_SSP0) || \
|
||||
((param) == TSB_SSP1) || \
|
||||
((param) == TSB_SSP2) )
|
||||
|
||||
typedef enum {
|
||||
SSP_FORMAT_SPI = 0U,
|
||||
SSP_FORMAT_SSI = 1U,
|
||||
SSP_FORMAT_MICROWIRE = 2U
|
||||
} SSP_FrameFormat;
|
||||
#define IS_SSP_FRAME_FORMAT(param) (((param) == SSP_FORMAT_SPI) || \
|
||||
((param) == SSP_FORMAT_SSI) || \
|
||||
((param) == SSP_FORMAT_MICROWIRE))
|
||||
|
||||
typedef enum {
|
||||
SSP_POLARITY_LOW = 0U,
|
||||
SSP_POLARITY_HIGH = 1U
|
||||
} SSP_ClkPolarity;
|
||||
#define IS_SSP_CLK_POLARITY(param) (((param) == SSP_POLARITY_LOW) || \
|
||||
((param) == SSP_POLARITY_HIGH))
|
||||
|
||||
typedef enum {
|
||||
SSP_PHASE_FIRST_EDGE = 0U,
|
||||
SSP_PHASE_SECOND_EDGE = 1U
|
||||
} SSP_ClkPhase;
|
||||
#define IS_SSP_CLK_PHASE(param) (((param) == SSP_PHASE_FIRST_EDGE) || \
|
||||
((param) == SSP_PHASE_SECOND_EDGE))
|
||||
|
||||
typedef enum {
|
||||
SSP_MASTER = 0U,
|
||||
SSP_SLAVE = 1U
|
||||
} SSP_MS_Mode;
|
||||
#define IS_SSP_MS_MODE(param) (((param) == SSP_MASTER) || \
|
||||
((param) == SSP_SLAVE))
|
||||
|
||||
typedef enum {
|
||||
SSP_FIFO_EMPTY = 0U,
|
||||
SSP_FIFO_NORMAL = 1U,
|
||||
SSP_FIFO_INVALID = 2U,
|
||||
SSP_FIFO_FULL = 3U
|
||||
} SSP_FIFOState;
|
||||
|
||||
#define IS_SSP_PRE_SCALE(param) (((param)>=2U)&&((param)<=254U)&&(((param)%2U)==0U))
|
||||
#define IS_SSP_DATA_BIT_SIZE(param) (((param)>=4U)&&((param)<=16U))
|
||||
|
||||
typedef enum {
|
||||
SSP_RX = 0U,
|
||||
SSP_TX = 1U
|
||||
} SSP_Direction;
|
||||
#define IS_SSP_DIRECTION(param) (((param) == SSP_RX) || \
|
||||
((param) == SSP_TX))
|
||||
|
||||
typedef struct {
|
||||
SSP_FrameFormat FrameFormat;
|
||||
uint8_t PreScale;
|
||||
uint8_t ClkRate;
|
||||
SSP_ClkPolarity ClkPolarity;
|
||||
SSP_ClkPhase ClkPhase;
|
||||
uint8_t DataSize;
|
||||
SSP_MS_Mode Mode;
|
||||
} SSP_InitTypeDef;
|
||||
|
||||
/* Parameter to configure SSP interrupt enable/disable Register */
|
||||
#define SSP_INTCFG_NONE ((uint32_t)0x00000000)
|
||||
#define SSP_INTCFG_RX_OVERRUN ((uint32_t)0x00000001)
|
||||
#define SSP_INTCFG_RX_TIMEOUT ((uint32_t)0x00000002)
|
||||
#define SSP_INTCFG_RX ((uint32_t)0x00000004)
|
||||
#define SSP_INTCFG_TX ((uint32_t)0x00000008)
|
||||
#define SSP_INTCFG_ALL ((uint32_t)0x0000000F)
|
||||
|
||||
#define IS_SSP_INT_SRC(param) ((param) <= SSP_INTCFG_ALL )
|
||||
|
||||
#define IS_SSP_CLEAR_INT_SRC(param) (((param) == SSP_INTCFG_RX_OVERRUN) || \
|
||||
((param) == SSP_INTCFG_RX_TIMEOUT) || \
|
||||
((param) == SSP_INTCFG_ALL) )
|
||||
|
||||
typedef union {
|
||||
uint32_t All;
|
||||
struct {
|
||||
uint32_t OverRun:1; /* Bit 0 , for TSB-M4 in IAR EWARM */
|
||||
uint32_t TimeOut:1;
|
||||
uint32_t Rx:1;
|
||||
uint32_t Tx:1;
|
||||
uint32_t Reserved:28; /* Bit 4 to 31 */
|
||||
} Bit;
|
||||
} SSP_INTState;
|
||||
|
||||
/** @} */
|
||||
/* End of group SSP_Exported_types */
|
||||
|
||||
/** @defgroup SSP_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
void SSP_Enable(TSB_SSP_TypeDef * SSPx);
|
||||
void SSP_Disable(TSB_SSP_TypeDef * SSPx);
|
||||
void SSP_Init(TSB_SSP_TypeDef * SSPx, SSP_InitTypeDef * InitStruct);
|
||||
void SSP_SetClkPreScale(TSB_SSP_TypeDef * SSPx, uint8_t PreScale, uint8_t ClkRate);
|
||||
void SSP_SetFrameFormat(TSB_SSP_TypeDef * SSPx, SSP_FrameFormat FrameFormat);
|
||||
void SSP_SetClkPolarity(TSB_SSP_TypeDef * SSPx, SSP_ClkPolarity ClkPolarity);
|
||||
void SSP_SetClkPhase(TSB_SSP_TypeDef * SSPx, SSP_ClkPhase ClkPhase);
|
||||
void SSP_SetDataSize(TSB_SSP_TypeDef * SSPx, uint8_t DataSize);
|
||||
void SSP_SetSlaveOutputCtrl(TSB_SSP_TypeDef * SSPx, FunctionalState NewState);
|
||||
void SSP_SetMSMode(TSB_SSP_TypeDef * SSPx, SSP_MS_Mode Mode);
|
||||
void SSP_SetLoopBackMode(TSB_SSP_TypeDef * SSPx, FunctionalState NewState);
|
||||
void SSP_SetTxData(TSB_SSP_TypeDef * SSPx, uint16_t Data);
|
||||
uint16_t SSP_GetRxData(TSB_SSP_TypeDef * SSPx);
|
||||
WorkState SSP_GetWorkState(TSB_SSP_TypeDef * SSPx);
|
||||
SSP_FIFOState SSP_GetFIFOState(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction);
|
||||
void SSP_SetINTConfig(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc);
|
||||
SSP_INTState SSP_GetINTConfig(TSB_SSP_TypeDef * SSPx);
|
||||
SSP_INTState SSP_GetPreEnableINTState(TSB_SSP_TypeDef * SSPx);
|
||||
SSP_INTState SSP_GetPostEnableINTState(TSB_SSP_TypeDef * SSPx);
|
||||
void SSP_ClearINTFlag(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc);
|
||||
void SSP_SetDMACtrl(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction, FunctionalState NewState);
|
||||
/** @} */
|
||||
/* End of group SSP_Exported_FunctionPrototypes */
|
||||
|
||||
/** @} */
|
||||
/* End of group SSP */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /*__TMPM46B_SSP_H */
|
||||
|
|
@ -0,0 +1,283 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_tmrb.h
|
||||
* @brief This file provides all the functions prototypes for TMRB driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/27
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_TMRB_H
|
||||
#define __TMPM46B_TMRB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TMRB
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TMRB_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TMRB Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
uint32_t Mode; /*!< Select TMRB mode between internal interval
|
||||
timer mode and external event counter */
|
||||
uint32_t ClkDiv; /*!< Select the division for TMRB source clock */
|
||||
uint32_t TrailingTiming; /*!< Specify the trailingTiming value to be written
|
||||
into TBnRG1 */
|
||||
uint32_t UpCntCtrl; /*!< Select up-counter work mode between
|
||||
freerun and auto-reload */
|
||||
uint32_t LeadingTiming; /*!< Specify the LeadingTiming value to be written
|
||||
into TBnRG0 */
|
||||
} TMRB_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TMRB Flip-flop Structure definition
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
uint32_t FlipflopCtrl; /*!< Select TMRB flip-flop output level */
|
||||
uint32_t FlipflopReverseTrg; /*!< Specify TMRB flip-flop reverse trigger */
|
||||
} TMRB_FFOutputTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TMRB Interrupt factor Union definition
|
||||
*/
|
||||
typedef union {
|
||||
uint32_t All;
|
||||
struct {
|
||||
uint32_t MatchLeadingTiming:1;
|
||||
uint32_t MatchTrailingTiming:1;
|
||||
uint32_t OverFlow:1;
|
||||
uint32_t Reserverd:29;
|
||||
} Bit;
|
||||
} TMRB_INTFactor;
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB_Exported_Types */
|
||||
|
||||
/** @defgroup TMRB_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define TSB_TB_MPT0 ((TSB_TB_TypeDef *)TSB_MT0)
|
||||
#define TSB_TB_MPT1 ((TSB_TB_TypeDef *)TSB_MT1)
|
||||
#define TSB_TB_MPT2 ((TSB_TB_TypeDef *)TSB_MT2)
|
||||
#define TSB_TB_MPT3 ((TSB_TB_TypeDef *)TSB_MT3)
|
||||
#define IS_TMRB_ALL_PERIPH(param) (((param) == TSB_TB0) || \
|
||||
((param) == TSB_TB1) || \
|
||||
((param) == TSB_TB2) || \
|
||||
((param) == TSB_TB3) || \
|
||||
((param) == TSB_TB4) || \
|
||||
((param) == TSB_TB5) || \
|
||||
((param) == TSB_TB6) || \
|
||||
((param) == TSB_TB7) || \
|
||||
((param) == TSB_TB_MPT0) || \
|
||||
((param) == TSB_TB_MPT1) || \
|
||||
((param) == TSB_TB_MPT2) || \
|
||||
((param) == TSB_TB_MPT3))
|
||||
|
||||
#define IS_TMRB_TMRB_PERIPH(param) (((param) == TSB_TB0) || \
|
||||
((param) == TSB_TB1) || \
|
||||
((param) == TSB_TB2) || \
|
||||
((param) == TSB_TB3) || \
|
||||
((param) == TSB_TB4) || \
|
||||
((param) == TSB_TB5) || \
|
||||
((param) == TSB_TB6) || \
|
||||
((param) == TSB_TB7))
|
||||
|
||||
#define IS_TMRB_MPT_PERIPH(param) (((param) == TSB_TB_MPT0) || \
|
||||
((param) == TSB_TB_MPT1) || \
|
||||
((param) == TSB_TB_MPT2) || \
|
||||
((param) == TSB_TB_MPT3))
|
||||
|
||||
#define IS_TMRB_SYNC_PERIPH(param) (((param) == TSB_TB1) || \
|
||||
((param) == TSB_TB2) || \
|
||||
((param) == TSB_TB3) || \
|
||||
((param) == TSB_TB5) || \
|
||||
((param) == TSB_TB6) || \
|
||||
((param) == TSB_TB7))
|
||||
|
||||
#define TMRB_INTERVAL_TIMER ((uint32_t)0x00000001)
|
||||
#define TMRB_EVENT_CNT ((uint32_t)0x00000000)
|
||||
#define IS_TMRB_MODE(param) (((param) == TMRB_INTERVAL_TIMER) || \
|
||||
((param) == TMRB_EVENT_CNT))
|
||||
|
||||
#define TMRB_CLK_DIV_2 ((uint32_t)0x00000001)
|
||||
#define TMRB_CLK_DIV_8 ((uint32_t)0x00000002)
|
||||
#define TMRB_CLK_DIV_32 ((uint32_t)0x00000003)
|
||||
#define TMRB_CLK_DIV_64 ((uint32_t)0x00000004)
|
||||
#define TMRB_CLK_DIV_128 ((uint32_t)0x00000005)
|
||||
#define TMRB_CLK_DIV_256 ((uint32_t)0x00000006)
|
||||
#define TMRB_CLK_DIV_512 ((uint32_t)0x00000007)
|
||||
#define IS_TMRB_CLK_DIV(param) (((param) == TMRB_CLK_DIV_2) || \
|
||||
((param) == TMRB_CLK_DIV_8) || \
|
||||
((param) == TMRB_CLK_DIV_32) || \
|
||||
((param) == TMRB_CLK_DIV_64) || \
|
||||
((param) == TMRB_CLK_DIV_128) || \
|
||||
((param) == TMRB_CLK_DIV_256) || \
|
||||
((param) == TMRB_CLK_DIV_512))
|
||||
|
||||
#define IS_MPT_CLK_DIV(param) (((param) == TMRB_CLK_DIV_2) || \
|
||||
((param) == TMRB_CLK_DIV_8) || \
|
||||
((param) == TMRB_CLK_DIV_32))
|
||||
|
||||
#define TMRB_FREE_RUN ((uint32_t)0x00000000)
|
||||
#define TMRB_AUTO_CLEAR ((uint32_t)0x00000008)
|
||||
#define IS_TMRB_UC_CTRL(param) (((param) == TMRB_FREE_RUN) || \
|
||||
((param) == TMRB_AUTO_CLEAR))
|
||||
|
||||
#define MPT_FREE_RUN ((uint32_t)0x00000000)
|
||||
#define MPT_AUTO_CLEAR ((uint32_t)0x00000004)
|
||||
#define IS_MPT_UC_CTRL(param) (((param) == MPT_FREE_RUN) || \
|
||||
((param) == MPT_AUTO_CLEAR))
|
||||
|
||||
#define TMRB_FLIPFLOP_INVERT ((uint32_t)0x00000000)
|
||||
#define TMRB_FLIPFLOP_SET ((uint32_t)0x00000001)
|
||||
#define TMRB_FLIPFLOP_CLEAR ((uint32_t)0x00000002)
|
||||
#define IS_TMRB_FLIPFLOP_CTRL(param) (((param) == TMRB_FLIPFLOP_INVERT) || \
|
||||
((param) == TMRB_FLIPFLOP_SET) || \
|
||||
((param) == TMRB_FLIPFLOP_CLEAR))
|
||||
|
||||
#define TMRB_DISABLE_FLIPFLOP ((uint32_t)0x00000000)
|
||||
#define TMRB_FLIPFLOP_TAKE_CAPTURE_0 ((uint32_t)0x00000010)
|
||||
#define TMRB_FLIPFLOP_TAKE_CAPTURE_1 ((uint32_t)0x00000020)
|
||||
#define TMRB_FLIPFLOP_MATCH_TRAILING ((uint32_t)0x00000008)
|
||||
#define TMRB_FLIPFLOP_MATCH_LEADING ((uint32_t)0x00000004)
|
||||
#define IS_TMRB_FLIPFLOP_TRG(param) (((param) == TMRB_DISABLE_FLIPFLOP) || \
|
||||
((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_0) || \
|
||||
((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_1) || \
|
||||
((param) == TMRB_FLIPFLOP_MATCH_TRAILING) || \
|
||||
((param) == TMRB_FLIPFLOP_MATCH_LEADING) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_LEADING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADING)) || \
|
||||
((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)))
|
||||
|
||||
#define TMRB_DISABLE_CAPTURE ((uint32_t)0x00000000)
|
||||
#define TMRB_CAPTURE_TBIN0_TBIN1_RISING ((uint32_t)0x00000100)
|
||||
#define TMRB_CAPTURE_TBIN0_RISING_FALLING ((uint32_t)0x00000200)
|
||||
#define TMRB_CAPTURE_TBFF0_EDGE ((uint32_t)0x00000300)
|
||||
#define TMRB_CLEAR_TBIN1_RISING ((uint32_t)0x00000400)
|
||||
#define TMRB_CAPTURE_TBIN0_RISING_CLEAR_TBIN1_RISING ((uint32_t)0x00000500)
|
||||
#define IS_TMRB_CAPTURE_TIMING_ALL(param) (((param) == TMRB_DISABLE_CAPTURE) || \
|
||||
((param) == TMRB_CAPTURE_TBIN0_TBIN1_RISING) || \
|
||||
((param) == TMRB_CAPTURE_TBIN0_RISING_FALLING) || \
|
||||
((param) == TMRB_CAPTURE_TBFF0_EDGE) || \
|
||||
((param) == TMRB_CLEAR_TBIN1_RISING) || \
|
||||
((param) == TMRB_CAPTURE_TBIN0_RISING_CLEAR_TBIN1_RISING))
|
||||
|
||||
#define IS_TMRB_CAPTURE_TIMING_NONE_TBIN1(param) (((param) == TMRB_DISABLE_CAPTURE) || \
|
||||
((param) == TMRB_CAPTURE_TBIN0_RISING_FALLING) || \
|
||||
((param) == TMRB_CAPTURE_TBFF0_EDGE))
|
||||
|
||||
#define MPT_DISABLE_CAPTURE ((uint32_t)0x00000000)
|
||||
#define MPT_CAPTURE_IN_RISING ((uint32_t)0x00000008)
|
||||
#define MPT_CAPTURE_IN_RISING_FALLING ((uint32_t)0x00000010)
|
||||
#define IS_MPT_CAPTURE_TIMING(param) (((param) == MPT_DISABLE_CAPTURE) || \
|
||||
((param) == MPT_CAPTURE_IN_RISING) || \
|
||||
((param) == MPT_CAPTURE_IN_RISING_FALLING))
|
||||
|
||||
#define TMRB_RUN ((uint32_t)0x00000005)
|
||||
#define TMRB_STOP ((uint32_t)0x00000000)
|
||||
#define IS_TMRB_CMD(param) (((param) == TMRB_RUN) || ((param) == TMRB_STOP))
|
||||
|
||||
#define TMRB_CAPTURE_0 ((uint8_t)0x00)
|
||||
#define TMRB_CAPTURE_1 ((uint8_t)0x01)
|
||||
#define IS_TMRB_CAPTURE_REG(param) (((param) == TMRB_CAPTURE_0) || ((param) == TMRB_CAPTURE_1))
|
||||
|
||||
#define TMRB_NO_INT_MASK ((uint32_t)0x00000000)
|
||||
#define TMRB_MASK_MATCH_LEADING_INT ((uint32_t)0x00000001)
|
||||
#define TMRB_MASK_MATCH_TRAILING_INT ((uint32_t)0x00000002)
|
||||
#define TMRB_MASK_OVERFLOW_INT ((uint32_t)0x00000004)
|
||||
#define IS_TMRB_INT_MASK(param) (((param) == TMRB_NO_INT_MASK) || \
|
||||
((param) == TMRB_MASK_MATCH_LEADING_INT) || \
|
||||
((param) == TMRB_MASK_MATCH_TRAILING_INT) || \
|
||||
((param) == TMRB_MASK_OVERFLOW_INT) || \
|
||||
((param) == (TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT)) || \
|
||||
((param) == (TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_OVERFLOW_INT)) || \
|
||||
((param) == (TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT)) || \
|
||||
((param) == (TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT)))
|
||||
|
||||
#define TMRB_TRG_EDGE_RISING ((uint8_t)0x00)
|
||||
#define TMRB_TRG_EDGE_FALLING ((uint8_t)0x02)
|
||||
#define IS_TMRB_TRG_EDGE(param) (((param) == TMRB_TRG_EDGE_RISING) || \
|
||||
((param) == TMRB_TRG_EDGE_FALLING))
|
||||
|
||||
#define TMRB_WRITE_REG_SEPARATE ((uint8_t)0x00)
|
||||
#define TMRB_WRITE_REG_SIMULTANEOUS ((uint8_t)0x40)
|
||||
#define IS_TMRB_WRITE_REG_MODE(param) (((param) == TMRB_WRITE_REG_SEPARATE) || \
|
||||
((param) == TMRB_WRITE_REG_SIMULTANEOUS))
|
||||
|
||||
#define TMRB_RUNNING_IN_CORE_HALT ((uint8_t)0x00)
|
||||
#define TMRB_STOP_IN_CORE_HALT ((uint8_t)0x40)
|
||||
#define IS_TMRB_CLK_IN_CORE_HALT(param) (((param) == TMRB_RUNNING_IN_CORE_HALT) || \
|
||||
((param) == TMRB_STOP_IN_CORE_HALT))
|
||||
|
||||
#define TMRB_NO_INT ((uint32_t)0x00000000)
|
||||
#define IS_TMRB_VALUE(param) ((param) <= 0x0000FFFFU)
|
||||
#define IS_VALID_LEADING(param1, param2) ((param1) <= (param2))
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB_Exported_Constants */
|
||||
/** @defgroup TMRB_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
void TMRB_Enable(TSB_TB_TypeDef * TBx);
|
||||
void TMRB_Disable(TSB_TB_TypeDef * TBx);
|
||||
void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd);
|
||||
void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct);
|
||||
void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming);
|
||||
void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct);
|
||||
TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx);
|
||||
void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask);
|
||||
void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming);
|
||||
void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming);
|
||||
uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx);
|
||||
uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg);
|
||||
void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx);
|
||||
void TMRB_SetIdleMode(TSB_TB_TypeDef * TBx, FunctionalState NewState);
|
||||
void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState);
|
||||
void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t WriteRegMode);
|
||||
void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode);
|
||||
void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState);
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB_Exported_FunctionPrototypes */
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __TMPM46B_TMRB_H */
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_uart.h
|
||||
* @brief This file provides all the functions prototypes for UART driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/26
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TMPM46B_UART_H
|
||||
#define __TMPM46B_UART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "TMPM46B.h"
|
||||
#include "tx04_common.h"
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief UART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
uint32_t BaudRate; /*!< This member configures the UART communication
|
||||
baud rate. */
|
||||
uint32_t DataBits; /*!< Specifies UART transfer mode, which could be
|
||||
7-bit mode, 8-bit mode or 9-bit mode. */
|
||||
uint32_t StopBits; /*!< Specifies the length of stop bit transmission
|
||||
in UART mode. */
|
||||
uint32_t Parity; /*!< Specifies the parity mode which could be odd
|
||||
parity, even parity or no parity. */
|
||||
uint32_t Mode; /*!< Enables or disables Receive, Transmit or
|
||||
both. */
|
||||
uint32_t FlowCtrl; /*!< Specifies whether the hardware flow control
|
||||
mode is enabled or disabled. */
|
||||
} UART_InitTypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint32_t InputClkEdge; /*!< Select the input clock edge.on the SCLK output mode
|
||||
this bit only can set to be 0(SIO_SCLKS_TXDF_RXDR) */
|
||||
uint32_t TIDLE; /*!< The status of TXDx pin after output of the
|
||||
last bit */
|
||||
uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error
|
||||
is occurred in SCLK input mode */
|
||||
uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK
|
||||
input mode */
|
||||
uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which
|
||||
could be None,1*SCLK,2*SCLK,4*SCLK,8*SCLK,16*SCLK,32*SCLK,64*SCLK.
|
||||
this bit is valid only for SCLK output mode and double
|
||||
buffer is enabled. */
|
||||
uint32_t TransferMode; /*!< Setting transfer mode which could be transfer prohibited,
|
||||
half duplex(Receive),half duplex(Transmit) or full duplex. */
|
||||
uint32_t TransferDir; /*!< Setting transfer direction which could be
|
||||
LSB_FRIST or MSB_FRIST. */
|
||||
uint32_t Mode; /*!< Enables or disables Receive, Transmit or both. */
|
||||
uint32_t DoubleBuffer; /*!< Double Buffer mode is enabled or disabled. */
|
||||
uint32_t BaudRateClock; /*!< Select the input clock for baud rate generator */
|
||||
uint32_t Divider; /*!< Division ratio "N" */
|
||||
} SIO_InitTypeDef;
|
||||
|
||||
/** @} */
|
||||
/* End of group UART_Exported_Types */
|
||||
|
||||
/** @defgroup UART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define UART0 TSB_SC0
|
||||
#define UART1 TSB_SC1
|
||||
#define UART2 TSB_SC2
|
||||
#define UART3 TSB_SC3
|
||||
#define IS_UART_PERIPH(param) (((param) == UART0) || \
|
||||
((param) == UART1) || \
|
||||
((param) == UART2) || \
|
||||
((param) == UART3))
|
||||
|
||||
#define SIO0 TSB_SC0
|
||||
#define SIO1 TSB_SC1
|
||||
#define SIO2 TSB_SC2
|
||||
#define SIO3 TSB_SC3
|
||||
#define IS_SIO_PERIPH(param) (((param) == SIO0)|| \
|
||||
((param) == SIO1) || \
|
||||
((param) == SIO2) || \
|
||||
((param) == SIO3))
|
||||
|
||||
#define UART_DATA_BITS_7 ((uint32_t)0x00000004)
|
||||
#define UART_DATA_BITS_8 ((uint32_t)0x00000008)
|
||||
#define UART_DATA_BITS_9 ((uint32_t)0x0000000C)
|
||||
#define IS_UART_DATA_BITS(param) (((param) == UART_DATA_BITS_7) || \
|
||||
((param) == UART_DATA_BITS_8) || \
|
||||
((param) == UART_DATA_BITS_9))
|
||||
|
||||
#define UART_STOP_BITS_1 ((uint32_t)0x00000000)
|
||||
#define UART_STOP_BITS_2 ((uint32_t)0x00000010)
|
||||
#define IS_UART_STOPBITS(param) (((param) == UART_STOP_BITS_1) || \
|
||||
((param) == UART_STOP_BITS_2))
|
||||
|
||||
#define UART_NO_PARITY ((uint32_t)0x00000000)
|
||||
#define UART_EVEN_PARITY ((uint32_t)0x00000060)
|
||||
#define UART_ODD_PARITY ((uint32_t)0x00000020)
|
||||
#define IS_UART_PARITY(param) (((param) == UART_NO_PARITY) || \
|
||||
((param) == UART_EVEN_PARITY) || \
|
||||
((param) == UART_ODD_PARITY))
|
||||
|
||||
#define SIO_CLK_SCLKOUTPUT ((uint32_t)0x00000000)
|
||||
#define SIO_CLK_SCLKINPUT ((uint32_t)0x00000001)
|
||||
#define IS_SIO_CLK_SEL(param) (((param) == SIO_CLK_SCLKOUTPUT) || \
|
||||
((param) == SIO_CLK_SCLKINPUT))
|
||||
|
||||
#define SIO_SCLKS_TXDF_RXDR ((uint32_t)0x00000000)
|
||||
#define SIO_SCLKS_TXDR_RXDF ((uint32_t)0x00000002)
|
||||
#define IS_SIO_SCLKS_TRXD(param) (((param) == SIO_SCLKS_TXDF_RXDR) || \
|
||||
((param) == SIO_SCLKS_TXDR_RXDF))
|
||||
|
||||
#define SIO_TIDLE_LOW ((uint32_t)0x00000000)
|
||||
#define SIO_TIDLE_HIGH ((uint32_t)0x00000100)
|
||||
#define SIO_TIDLE_LAST ((uint32_t)0x00000200)
|
||||
#define IS_SIO_TIDLE_LEVEL(param) (((param) == SIO_TIDLE_LOW) || \
|
||||
((param) == SIO_TIDLE_HIGH) || \
|
||||
((param) == SIO_TIDLE_LAST))
|
||||
|
||||
#define SIO_TXDEMP_LOW ((uint32_t)0x00000000)
|
||||
#define SIO_TXDEMP_HIGH ((uint32_t)0x00000400)
|
||||
#define IS_SIO_TXDEMP_LEVEL(param) (((param) == SIO_TXDEMP_LOW) || \
|
||||
((param) == SIO_TXDEMP_HIGH))
|
||||
|
||||
#define SIO_EHOLD_FC_2 ((uint32_t)0x00000000)
|
||||
#define SIO_EHOLD_FC_4 ((uint32_t)0x00001000)
|
||||
#define SIO_EHOLD_FC_8 ((uint32_t)0x00002000)
|
||||
#define SIO_EHOLD_FC_16 ((uint32_t)0x00003000)
|
||||
#define SIO_EHOLD_FC_32 ((uint32_t)0x00004000)
|
||||
#define SIO_EHOLD_FC_64 ((uint32_t)0x00005000)
|
||||
#define SIO_EHOLD_FC_128 ((uint32_t)0x00006000)
|
||||
#define IS_SIO_EHOLD_TIME(param) (((param) == SIO_EHOLD_FC_2) || \
|
||||
((param) == SIO_EHOLD_FC_4) || \
|
||||
((param) == SIO_EHOLD_FC_8) || \
|
||||
((param) == SIO_EHOLD_FC_16) || \
|
||||
((param) == SIO_EHOLD_FC_32) || \
|
||||
((param) == SIO_EHOLD_FC_64) || \
|
||||
((param) == SIO_EHOLD_FC_128))
|
||||
|
||||
#define SIO_SINT_TIME_NONE ((uint32_t)0x00000000)
|
||||
#define SIO_SINT_TIME_SCLK_1 ((uint32_t)0x00000002)
|
||||
#define SIO_SINT_TIME_SCLK_2 ((uint32_t)0x00000004)
|
||||
#define SIO_SINT_TIME_SCLK_4 ((uint32_t)0x00000006)
|
||||
#define SIO_SINT_TIME_SCLK_8 ((uint32_t)0x00000008)
|
||||
#define SIO_SINT_TIME_SCLK_16 ((uint32_t)0x0000000A)
|
||||
#define SIO_SINT_TIME_SCLK_32 ((uint32_t)0x0000000C)
|
||||
#define SIO_SINT_TIME_SCLK_64 ((uint32_t)0x0000000E)
|
||||
#define IS_SIO_SINT_TIME(param) (((param) == SIO_SINT_TIME_NONE) || \
|
||||
((param) == SIO_SINT_TIME_SCLK_1) || \
|
||||
((param) == SIO_SINT_TIME_SCLK_2) || \
|
||||
((param) == SIO_SINT_TIME_SCLK_4) || \
|
||||
((param) == SIO_SINT_TIME_SCLK_8) || \
|
||||
((param) == SIO_SINT_TIME_SCLK_16) || \
|
||||
((param) == SIO_SINT_TIME_SCLK_32) || \
|
||||
((param) == SIO_SINT_TIME_SCLK_64))
|
||||
|
||||
#define SIO_TRANSFER_PROHIBIT ((uint32_t)0x00000000)
|
||||
#define SIO_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020)
|
||||
#define SIO_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040)
|
||||
#define SIO_TRANSFER_FULLDPX ((uint32_t)0x00000060)
|
||||
#define IS_SIO_TRANSFER_MODE(param) (((param) == SIO_TRANSFER_PROHIBIT) || \
|
||||
((param) == SIO_TRANSFER_HALFDPX_RX) || \
|
||||
((param) == SIO_TRANSFER_HALFDPX_TX) || \
|
||||
((param) == SIO_TRANSFER_FULLDPX))
|
||||
|
||||
#define SIO_ENABLE_RX ((uint32_t)0x00000020)
|
||||
#define SIO_ENABLE_TX ((uint32_t)0x00000010)
|
||||
#define IS_SIO_MODE(param) (((param) == SIO_ENABLE_RX) || \
|
||||
((param) == SIO_ENABLE_TX) || \
|
||||
((param) == (SIO_ENABLE_TX | SIO_ENABLE_RX)))
|
||||
|
||||
#define SIO_LSB_FRIST ((uint32_t)0x00000000)
|
||||
#define SIO_MSB_FRIST ((uint32_t)0x00000008)
|
||||
#define IS_SIO_TRANS_DIR(param) (((param) == SIO_LSB_FRIST) || \
|
||||
((param) == SIO_MSB_FRIST))
|
||||
|
||||
#define SIO_WBUF_DISABLE ((uint32_t)0x00000000)
|
||||
#define SIO_WBUF_ENABLE ((uint32_t)0x00000004)
|
||||
#define IS_SIO_WBUF_SET(param) (((param) == SIO_WBUF_DISABLE) || \
|
||||
((param) == SIO_WBUF_ENABLE))
|
||||
|
||||
#define SIO_BR_CLOCK_TS0 ((uint32_t)0x00000000)
|
||||
#define SIO_BR_CLOCK_TS2 ((uint32_t)0x00000010)
|
||||
#define SIO_BR_CLOCK_TS8 ((uint32_t)0x00000020)
|
||||
#define SIO_BR_CLOCK_TS32 ((uint32_t)0x00000030)
|
||||
#define IS_SIO_BR_CLOCK(param) (((param) == SIO_BR_CLOCK_TS0) || \
|
||||
((param) == SIO_BR_CLOCK_TS2) || \
|
||||
((param) == SIO_BR_CLOCK_TS8) || \
|
||||
((param) == SIO_BR_CLOCK_TS32))
|
||||
|
||||
#define SIO_BR_DIVIDER_16 ((uint32_t)0x00000000)
|
||||
#define SIO_BR_DIVIDER_1 ((uint32_t)0x00000001)
|
||||
#define SIO_BR_DIVIDER_2 ((uint32_t)0x00000002)
|
||||
#define SIO_BR_DIVIDER_3 ((uint32_t)0x00000003)
|
||||
#define SIO_BR_DIVIDER_4 ((uint32_t)0x00000004)
|
||||
#define SIO_BR_DIVIDER_5 ((uint32_t)0x00000005)
|
||||
#define SIO_BR_DIVIDER_6 ((uint32_t)0x00000006)
|
||||
#define SIO_BR_DIVIDER_7 ((uint32_t)0x00000007)
|
||||
#define SIO_BR_DIVIDER_8 ((uint32_t)0x00000008)
|
||||
#define SIO_BR_DIVIDER_9 ((uint32_t)0x00000009)
|
||||
#define SIO_BR_DIVIDER_10 ((uint32_t)0x0000000A)
|
||||
#define SIO_BR_DIVIDER_11 ((uint32_t)0x0000000B)
|
||||
#define SIO_BR_DIVIDER_12 ((uint32_t)0x0000000C)
|
||||
#define SIO_BR_DIVIDER_13 ((uint32_t)0x0000000D)
|
||||
#define SIO_BR_DIVIDER_14 ((uint32_t)0x0000000E)
|
||||
#define SIO_BR_DIVIDER_15 ((uint32_t)0x0000000F)
|
||||
#define IS_SIO_BR_DIVIDER(param) ((param) <= SIO_BR_DIVIDER_15)
|
||||
|
||||
#define IS_SIO_DATA(param) ((param) <= 0xFFU)
|
||||
|
||||
#define SIO_CLOCK_T0_HALF ((uint32_t)0x00000000)
|
||||
#define SIO_CLOCK_T0 ((uint32_t)0x00000002)
|
||||
#define IS_SIO_CLOCK(param) (((param) == SIO_CLOCK_T0_HALF) || \
|
||||
((param) == SIO_CLOCK_T0))
|
||||
|
||||
#define UART_ENABLE_RX ((uint32_t)0x00000020)
|
||||
#define UART_ENABLE_TX ((uint32_t)0x00000010)
|
||||
#define IS_UART_MODE(param) (((param) == UART_ENABLE_RX) || \
|
||||
((param) == UART_ENABLE_TX) || \
|
||||
((param) == (UART_ENABLE_TX | UART_ENABLE_RX)))
|
||||
|
||||
#define UART_NONE_FLOW_CTRL ((uint32_t)0x00000000)
|
||||
#define IS_UART_FLOW_CONTROL(param) ((param) == UART_NONE_FLOW_CTRL)
|
||||
|
||||
#ifdef USE_STK
|
||||
#define IS_UART_BAUDRATE(param) (((param) >= 3663U) && \
|
||||
((param) <= 921600U))
|
||||
#else
|
||||
#define IS_UART_BAUDRATE(param) (((param) >= 2929U) && \
|
||||
((param) <= 921600U))
|
||||
#endif
|
||||
|
||||
#define IS_UART_DATA(param) ((param) <= 0x01FFU)
|
||||
|
||||
#define IS_UART_CLOCK(param) ((param) <= ((uint32_t)0x00000001))
|
||||
#define IS_UART_TIME(param) ((param) <= ((uint32_t)0x00000006))
|
||||
#define UART_RX ((uint32_t)0x00000020)
|
||||
#define UART_TX ((uint32_t)0x00000040)
|
||||
#define IS_UART_TRX(param) (((param) == UART_RX) || \
|
||||
((param) == UART_TX))
|
||||
|
||||
#define UART_TRANSFER_PROHIBIT ((uint32_t)0x00000000)
|
||||
#define UART_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020)
|
||||
#define UART_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040)
|
||||
#define UART_TRANSFER_FULLDPX ((uint32_t)0x00000060)
|
||||
#define IS_UART_TRANSFER_MODE(param) (((param) == UART_TRANSFER_PROHIBIT) || \
|
||||
((param) == UART_TRANSFER_HALFDPX_RX) || \
|
||||
((param) == UART_TRANSFER_HALFDPX_TX) || \
|
||||
((param) == UART_TRANSFER_FULLDPX))
|
||||
|
||||
#define UART_RXFIFO_MAX ((uint32_t)0x00000000)
|
||||
#define UART_RXFIFO_RXFLEVEL ((uint32_t)0x00000010)
|
||||
#define IS_UATR_RXFIFO_BYTESUSED(param) (((param) == UART_RXFIFO_MAX) || \
|
||||
((param) == UART_RXFIFO_RXFLEVEL))
|
||||
|
||||
#define UART_RXFIFO4B_FLEVLE_4_2B ((uint32_t)0x00000000)
|
||||
#define UART_RXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001)
|
||||
#define UART_RXFIFO4B_FLEVLE_2_2B ((uint32_t)0x00000002)
|
||||
#define UART_RXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003)
|
||||
#define IS_UART_RXFIFO4B_FLEVLE(param) (((param) == UART_RXFIFO4B_FLEVLE_4_2B) || \
|
||||
((param) == UART_RXFIFO4B_FLEVLE_1_1B) || \
|
||||
((param) == UART_RXFIFO4B_FLEVLE_2_2B) || \
|
||||
((param) == UART_RXFIFO4B_FLEVLE_3_1B))
|
||||
|
||||
#define UART_RFIS_REACH_FLEVEL ((uint32_t)0x00000000)
|
||||
#define UART_RFIS_REACH_EXCEED_FLEVEL ((uint32_t)0x00000040)
|
||||
#define IS_UATR_RFIS_CONDITION(param) (((param) == UART_RFIS_REACH_FLEVEL) || \
|
||||
((param) == UART_RFIS_REACH_EXCEED_FLEVEL))
|
||||
|
||||
#define UART_TXFIFO4B_FLEVLE_0_0B ((uint32_t)0x00000000)
|
||||
#define UART_TXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001)
|
||||
#define UART_TXFIFO4B_FLEVLE_2_0B ((uint32_t)0x00000002)
|
||||
#define UART_TXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003)
|
||||
#define IS_UART_TXFIFO4B_FLEVLE(param) (((param) == UART_TXFIFO4B_FLEVLE_0_0B) || \
|
||||
((param) == UART_TXFIFO4B_FLEVLE_1_1B) || \
|
||||
((param) == UART_TXFIFO4B_FLEVLE_2_0B) || \
|
||||
((param) == UART_TXFIFO4B_FLEVLE_3_1B))
|
||||
|
||||
#define UART_TRXFIFO_EMPTY ((uint32_t)0x00000000)
|
||||
#define UART_TRXFIFO_1B ((uint32_t)0x00000001)
|
||||
#define UART_TRXFIFO_2B ((uint32_t)0x00000002)
|
||||
#define UART_TRXFIFO_3B ((uint32_t)0x00000003)
|
||||
#define UART_TRXFIFO_4B ((uint32_t)0x00000004)
|
||||
|
||||
#define UART_TFIS_REACH_FLEVEL ((uint32_t)0x00000000)
|
||||
#define UART_TFIS_REACH_NOREACH_FLEVEL ((uint32_t)0x00000040)
|
||||
#define IS_UATR_TFIS_CONDITION(param) (((param) == UART_TFIS_REACH_FLEVEL) || \
|
||||
((param) == UART_TFIS_REACH_NOREACH_FLEVEL))
|
||||
|
||||
#define UART_RXFIFO_OVERRUN ((uint32_t)0x00000001)
|
||||
|
||||
#define UART_TXFIFO_UNDERRUN ((uint32_t)0x00000001)
|
||||
|
||||
/** @} */
|
||||
/* End of group UART_Exported_Constants */
|
||||
|
||||
/** @addtogroup UART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
UART_NO_ERR = 0U,
|
||||
UART_OVERRUN = 1U,
|
||||
UART_PARITY_ERR = 2U,
|
||||
UART_FRAMING_ERR = 3U,
|
||||
UART_ERRS = 4U
|
||||
} UART_Err;
|
||||
|
||||
typedef enum {
|
||||
UART_RXTXCNT_NONE = 0U,
|
||||
UART_RXTXCNT_AUTODISABLE = 1U
|
||||
} UART_TRxDisable;
|
||||
#define IS_UATR_TRX_AUTODISABLE(param) (((param) == UART_RXTXCNT_NONE) || \
|
||||
((param) == UART_RXTXCNT_AUTODISABLE))
|
||||
|
||||
/** @} */
|
||||
/* End of group UART_Exported_Types */
|
||||
|
||||
/** @defgroup UART_Exported_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
void UART_Enable(TSB_SC_TypeDef * UARTx);
|
||||
void UART_Disable(TSB_SC_TypeDef * UARTx);
|
||||
WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint8_t Direction);
|
||||
void UART_SWReset(TSB_SC_TypeDef * UARTx);
|
||||
void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct);
|
||||
uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx);
|
||||
void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data);
|
||||
void UART_DefaultConfig(TSB_SC_TypeDef * UARTx);
|
||||
UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx);
|
||||
void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
|
||||
void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
|
||||
void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock);
|
||||
void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
|
||||
void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode);
|
||||
void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable);
|
||||
void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
|
||||
void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
|
||||
void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed);
|
||||
void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel);
|
||||
void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition);
|
||||
void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx);
|
||||
void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel);
|
||||
void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition);
|
||||
void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx);
|
||||
void UART_TxBufferClear(TSB_SC_TypeDef * UARTx);
|
||||
uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
|
||||
uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx);
|
||||
uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
|
||||
uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx);
|
||||
void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock);
|
||||
void SIO_Enable(TSB_SC_TypeDef * SIOx);
|
||||
void SIO_Disable(TSB_SC_TypeDef * SIOx);
|
||||
uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx);
|
||||
void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data);
|
||||
void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct);
|
||||
/** @} */
|
||||
/* End of group UART_Exported_FunctionPrototypes */
|
||||
|
||||
/** @} */
|
||||
/* End of group UART */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __TMPM46B_UART_H */
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tx04_common.h
|
||||
* @brief All common macro and definition for TX04 peripheral drivers
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/04
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TX04_COMMON_H
|
||||
#define __TX04_COMMON_H
|
||||
|
||||
typedef enum {
|
||||
SUCCESS = 0U,
|
||||
ERROR = 1U,
|
||||
FAIL = -1
|
||||
} Result;
|
||||
|
||||
typedef enum {
|
||||
BUSY = 0U,
|
||||
DONE = 1U
|
||||
} WorkState;
|
||||
|
||||
typedef enum {
|
||||
DISABLE = 0U,
|
||||
ENABLE = 1U
|
||||
} FunctionalState;
|
||||
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
#define IS_POINTER_NOT_NULL(param) ((void*)(param) != (void*)0)
|
||||
|
||||
/*
|
||||
* To report the name of the source file and source line number where the
|
||||
* assert_param error has occurred, "DEBUG" must be defined. And detailed
|
||||
* definition of assert_failed() is needed to be implemented, which can be
|
||||
* done, for example, in the main.c file.
|
||||
*/
|
||||
#ifdef DEBUG
|
||||
void assert_failed(char *file, int32_t line);
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
|
||||
#else
|
||||
#define assert_param(expr)
|
||||
#endif /* DEBUG */
|
||||
|
||||
#endif /* __TX04_COMMON_H */
|
||||
|
|
@ -0,0 +1,621 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_adc.c
|
||||
* @brief This file provides API functions for ADC driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/11
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tmpm46b_adc.h"
|
||||
|
||||
#if defined(__TMPM46B_ADC_H)
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC
|
||||
* @brief ADC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define MOD6_ADRST_10 ((uint32_t)0x00000002)
|
||||
#define MOD6_ADRST_01 ((uint32_t)0x00000001)
|
||||
|
||||
#define MOD3_ITM_CLEAR ((uint32_t)0x00000003)
|
||||
|
||||
#define MOD2_ADCH_CLEAR ((uint32_t)0x000000F0)
|
||||
#define MOD2_HPADCH_CLEAR ((uint32_t)0x0000000F)
|
||||
|
||||
#define MOD1_ADHWE_CLEAR ((uint32_t)0x000000EE)
|
||||
#define MOD1_ADHWE_SET ((uint32_t)0x00000001)
|
||||
#define MOD1_ADHWS_CLEAR ((uint32_t)0x000000ED)
|
||||
#define MOD1_HPADHWE_CLEAR ((uint32_t)0x000000EB)
|
||||
#define MOD1_HPADHWE_SET ((uint32_t)0x00000004)
|
||||
#define MOD1_HPADHWS_CLEAR ((uint32_t)0x000000E7)
|
||||
|
||||
#define ADILV_TRGSEL_CLEAR ((uint32_t)0x0000F0FF)
|
||||
#define ADILV_HPTRGSEL_CLEAR ((uint32_t)0x00000FFF)
|
||||
|
||||
|
||||
/** @} */
|
||||
/* End of group ADC_Private_Defines */
|
||||
|
||||
/** @defgroup ADC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group ADC_Private_FunctionPrototypes */
|
||||
|
||||
/** @defgroup ADC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group ADC_Private_Functions */
|
||||
|
||||
/** @defgroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Software reset ADC.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SWReset(TSB_AD_TypeDef * ADx)
|
||||
{
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
|
||||
ADC_SetVref(ADx, ENABLE);
|
||||
ADx->MOD6 = MOD6_ADRST_10;
|
||||
ADx->MOD6 = MOD6_ADRST_01;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set AD sample hold time and prescaler clock.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param Sample_HoldTime: Select the AD sample hold time.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_CONVERSION_CLK_10, ADC_CONVERSION_CLK_20,
|
||||
* ADC_CONVERSION_CLK_30, ADC_CONVERSION_CLK_40,
|
||||
* ADC_CONVERSION_CLK_80, ADC_CONVERSION_CLK_160,
|
||||
* ADC_CONVERSION_CLK_320
|
||||
* @param Prescaler_Output: Select the AD prescaler clock.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_FC_DIVIDE_LEVEL_1, ADC_FC_DIVIDE_LEVEL_2,
|
||||
* ADC_FC_DIVIDE_LEVEL_4, ADC_FC_DIVIDE_LEVEL_8,
|
||||
* ADC_FC_DIVIDE_LEVEL_16.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetClk(TSB_AD_TypeDef * ADx, uint32_t Sample_HoldTime, uint32_t Prescaler_Output)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_HOLD_TIME(Sample_HoldTime));
|
||||
assert_param(IS_ADC_PRESCALER(Prescaler_Output));
|
||||
|
||||
/* Set ADCLK */
|
||||
ADx->CLK = Sample_HoldTime + Prescaler_Output;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start AD conversion.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_Start(TSB_AD_TypeDef * ADx)
|
||||
{
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
|
||||
/* Set ADMOD0<ADS> = 1 to start AD conversion */
|
||||
TSB_AD_MOD0_ADS = 1U;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable ADC scan mode.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param NewState: Specify ADC scan mode state.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetScanMode(TSB_AD_TypeDef * ADx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set ADMOD3<SCAN> */
|
||||
TSB_AD_MOD3_SCAN = NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable ADC repeat mode.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param NewState: Specify ADC repeat mode state.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetRepeatMode(TSB_AD_TypeDef * ADx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set ADMOD3<REPEAT> */
|
||||
TSB_AD_MOD3_REPEAT = NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set ADC interrupt mode in fixed channel repeat conversion mode.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param INTMode: Specify AD conversion interrupt mode.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_INT_SINGLE, ADC_INT_CONVERSION_2,
|
||||
* ADC_INT_CONVERSION_3, ADC_INT_CONVERSION_4,
|
||||
* ADC_INT_CONVERSION_5, ADC_INT_CONVERSION_6,
|
||||
* ADC_INT_CONVERSION_7, ADC_INT_CONVERSION_8.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetINTMode(TSB_AD_TypeDef * ADx, uint32_t INTMode)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_INT_MODE(INTMode));
|
||||
|
||||
/* Set ADMOD3<ITM[2:0]> */
|
||||
tmp = ADx->MOD3;
|
||||
tmp &= MOD3_ITM_CLEAR;
|
||||
tmp |= INTMode;
|
||||
ADx->MOD3 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set ADC input channel.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param InputChannel: Analog input channel.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_AN_00, ADC_AN_01, ADC_AN_02, ADC_AN_03,
|
||||
* ADC_AN_04, ADC_AN_05, ADC_AN_06, ADC_AN_07.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetInputChannel(TSB_AD_TypeDef * ADx, ADC_AINx InputChannel)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_INPUT_CHANNEL(InputChannel));
|
||||
|
||||
/* Set ADMOD2<ADCH[3:0]> */
|
||||
tmp = ADx->MOD2;
|
||||
tmp &= MOD2_ADCH_CLEAR;
|
||||
tmp |= InputChannel;
|
||||
ADx->MOD2 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set ADC scan channel.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param StartChannel: Specify the start channel to be scanned.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_AN_00, ADC_AN_01, ADC_AN_02, ADC_AN_03,
|
||||
* ADC_AN_04, ADC_AN_05, ADC_AN_06, ADC_AN_07.
|
||||
* @param Range: Specify the range of assignable channel scan value.
|
||||
* This parameter can be one of the following values:
|
||||
* 1, 2, 3, 4, 5, 6, 7, 8 (note: StartChannel + Range <= 8 )
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetScanChannel(TSB_AD_TypeDef * ADx, ADC_AINx StartChannel, uint32_t Range)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_SCAN_CHANNEL(StartChannel, Range));
|
||||
|
||||
/* Set ADMOD4<SCANAREA> */
|
||||
ADx->MOD4 = (uint32_t) (StartChannel | ((Range - 1U) << 4U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Control AVREFH-AVREFL current.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param VrefCtrl: Specify how to apply AVREFH-AVREFL current.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_APPLY_VREF_IN_CONVERSION or ADC_APPLY_VREF_AT_ANY_TIME.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetVrefCut(TSB_AD_TypeDef * ADx, uint32_t VrefCtrl)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_VREF_CTRL(VrefCtrl));
|
||||
|
||||
/* Set ADMOD1<RCUT> */
|
||||
TSB_AD_MOD1_RCUT = VrefCtrl;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set ADC operation in IDLE mode.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param NewState: Specify ADC operation state in IDLE mode.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetIdleMode(TSB_AD_TypeDef * ADx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set ADMOD1<I2AD> */
|
||||
TSB_AD_MOD1_I2AD = NewState;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set ADC VREF application.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param NewState: Specify ADC Vref application state.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetVref(TSB_AD_TypeDef * ADx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set ADMOD1<VREFON> */
|
||||
TSB_AD_MOD1_DACON = NewState;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select ADC top-priority conversion analog input channel.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following values:
|
||||
* TSB_AD
|
||||
* @param TopInputChannel: Analog input channel for top-priority conversion.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_AN_00, ADC_AN_01, ADC_AN_02, ADC_AN_03,
|
||||
* ADC_AN_04, ADC_AN_05, ADC_AN_06, ADC_AN_07.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetInputChannelTop(TSB_AD_TypeDef * ADx, ADC_AINx TopInputChannel)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_INPUT_CHANNEL(TopInputChannel));
|
||||
|
||||
/* Set ADMOD2<HPADCH[3:0]> */
|
||||
tmp = ADx->MOD2;
|
||||
tmp &= MOD2_HPADCH_CLEAR;
|
||||
tmp |= ((uint32_t) TopInputChannel << 4U);
|
||||
ADx->MOD2 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start top-priority AD conversion.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_StartTopConvert(TSB_AD_TypeDef * ADx)
|
||||
{
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
|
||||
/* Set ADMOD0<HPADS> = 1 to start top-priority AD conversion */
|
||||
TSB_AD_MOD0_HPADS = 1U;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the specified ADC monitor module.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param ADCMPx: Select which compare control register will be used.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_CMPCR_0 or ADC_CMPCR_1.
|
||||
* @param NewState: Specify ADC monitor function state.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_CMPCRx(ADCMPx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (ADCMPx == ADC_CMPCR_0) {
|
||||
/* Set ADCMPCR0<CMP0EN> */
|
||||
TSB_AD_CMPCR0_CMP0EN = NewState;
|
||||
} else {
|
||||
/* Set ADCMPCR1<CMP1EN> */
|
||||
TSB_AD_CMPCR1_CMP1EN = NewState;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the specified ADC monitor module.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param ADCMPx: Select which compare control register will be used.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_CMPCR_0 or ADC_CMPCR_1.
|
||||
* @param Monitor: The structure containing ADC monitor configuration.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_ConfigMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, ADC_MonitorTypeDef * Monitor)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_CMPCRx(ADCMPx));
|
||||
assert_param(IS_POINTER_NOT_NULL(Monitor));
|
||||
assert_param(IS_ADC_INPUT_CHANNEL(Monitor->CmpChannel));
|
||||
assert_param(IS_ADC_CMPCNT(Monitor->CmpCnt));
|
||||
assert_param(IS_ADC_CMPCONDITION(Monitor->Condition));
|
||||
assert_param(IS_ADC_CMPMODE(Monitor->CntMode));
|
||||
assert_param(IS_ADC_CMPVALUE_12BIT(Monitor->CmpValue));
|
||||
|
||||
tmp |= (uint32_t) (Monitor->CmpChannel);
|
||||
tmp |= (uint32_t) (Monitor->Condition) << 4U;
|
||||
tmp |= (uint32_t) (Monitor->CntMode) << 5U;
|
||||
tmp |= (uint32_t) (Monitor->CmpCnt - 1U) << 8U;
|
||||
|
||||
if (ADCMPx == ADC_CMPCR_0) {
|
||||
ADx->CMPCR0 = tmp;
|
||||
ADx->CMP0 = Monitor->CmpValue;
|
||||
} else {
|
||||
ADx->CMPCR1 = tmp;
|
||||
ADx->CMP1 = Monitor->CmpValue;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set hardware trigger for normal AD conversion.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param HWSrc: Hardware source for activating normal AD conversion.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_EXTERADTRG,ADC_INTERTRIGGER
|
||||
* @param NewState: Specify state of hardware source for activating normal AD conversion.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetHWTrg(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_EXTERADTRG(HWSrc));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set ADMOD1<ADHWS> */
|
||||
tmp = ADx->MOD1;
|
||||
tmp &= MOD1_ADHWS_CLEAR;
|
||||
tmp |= (HWSrc << 1U);
|
||||
|
||||
/* Set ADMOD1<ADHWE> */
|
||||
if (NewState == ENABLE) {
|
||||
tmp |= MOD1_ADHWE_SET;
|
||||
} else {
|
||||
tmp &= MOD1_ADHWE_CLEAR;
|
||||
}
|
||||
|
||||
ADx->MOD1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set hardware trigger for top-priority AD conversion.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param HWSrc: Hardware source for activating top-priority AD conversion.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_EXTERADTRG,ADC_INTERTRIGGER
|
||||
* @param NewState: Specify state of hardware source for activating top-priority AD conversion.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetHWTrgTop(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_EXTERADTRG_TOP(HWSrc));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set ADMOD1<HPADHWS> */
|
||||
tmp = ADx->MOD1;
|
||||
tmp &= MOD1_HPADHWS_CLEAR;
|
||||
tmp |= (HWSrc << 3U);
|
||||
|
||||
/* Set ADMOD1<HPADHWE> */
|
||||
if (NewState == ENABLE) {
|
||||
tmp |= MOD1_HPADHWE_SET;
|
||||
} else {
|
||||
tmp &= MOD1_HPADHWE_CLEAR;
|
||||
}
|
||||
|
||||
ADx->MOD1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read AD conversion completion/busy flag (normal and top-priority).
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @retval A union with the state of AD conversion.
|
||||
*/
|
||||
ADC_State ADC_GetConvertState(TSB_AD_TypeDef * ADx)
|
||||
{
|
||||
ADC_State retval = { 0U };
|
||||
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
|
||||
retval.All = ADx->MOD5;
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read AD conversion result.
|
||||
* @param ADx: Select ADC unit.
|
||||
* This parameter can be the following value:
|
||||
* TSB_AD
|
||||
* @param ADREGx: ADC result register.
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_REG_00, ADC_REG_01, ADC_REG_02, ADC_REG_03,
|
||||
* ADC_REG_04, ADC_REG_05, ADC_REG_06, ADC_REG_07,
|
||||
* ADC_REG_SP.
|
||||
* @retval A union with AD result and 2 bits of extra information.
|
||||
*/
|
||||
ADC_Result ADC_GetConvertResult(TSB_AD_TypeDef * ADx, ADC_REGx ADREGx)
|
||||
{
|
||||
ADC_Result retval = { 0U };
|
||||
uint32_t tmpAddr = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_UNIT(ADx));
|
||||
assert_param(IS_ADC_REG(ADREGx));
|
||||
|
||||
if (ADREGx == ADC_REG_SP) {
|
||||
retval.All = ADx->REGSP;
|
||||
} else {
|
||||
tmpAddr = (uint32_t) (&ADx->REG00);
|
||||
tmpAddr += (0x4U * (uint32_t) ADREGx);
|
||||
retval.All = *((uint32_t *) (tmpAddr));
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the trigger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_EnableTrigger(void)
|
||||
{
|
||||
/* Set TRGSEL<TRGSELEN> to enable trigger */
|
||||
TSB_ADILV_TRGSEL_TRGSELEN = 1U;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the trigger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_DisableTrigger(void)
|
||||
{
|
||||
/* Set TRGSEL<TRGSELEN> to disable trigger */
|
||||
TSB_ADILV_TRGSEL_TRGSELEN = 0U;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects a trigger for startup of normal AD conversion
|
||||
* @param TriggerStartup: trigger for startup of normal AD conversion
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_TRG_00, ADC_TRG_01, ADC_TRG_02, ADC_TRG_03,
|
||||
* ADC_TRG_04, ADC_TRG_05, ADC_TRG_06, ADC_TRG_07,
|
||||
* ADC_TRG_08, ADC_TRG_09.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetTriggerStartup(ADC_TRGx TriggerStartup)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_TRG(TriggerStartup));
|
||||
|
||||
/* Set TRGSEL<TRGSEL[3:0]> */
|
||||
tmp = TSB_ADILV->TRGSEL;
|
||||
tmp &= ADILV_TRGSEL_CLEAR;
|
||||
tmp |= ((uint32_t) TriggerStartup << 8U);
|
||||
TSB_ADILV->TRGSEL = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects a trigger for startup of top-priority AD conversion
|
||||
* @param TopTriggerStartup: trigger for startup of top-priority AD conversion
|
||||
* This parameter can be one of the following values:
|
||||
* ADC_TRG_00, ADC_TRG_01, ADC_TRG_02, ADC_TRG_03,
|
||||
* ADC_TRG_04, ADC_TRG_05, ADC_TRG_06, ADC_TRG_07,
|
||||
* ADC_TRG_08, ADC_TRG_09.
|
||||
* @retval None.
|
||||
*/
|
||||
void ADC_SetTriggerStartupTop(ADC_TRGx TopTriggerStartup)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_TRG(TopTriggerStartup));
|
||||
|
||||
/* Set TRGSEL<HPTRGSEL[3:0]> */
|
||||
tmp = TSB_ADILV->TRGSEL;
|
||||
tmp &= ADILV_HPTRGSEL_CLEAR;
|
||||
tmp |= ((uint32_t) TopTriggerStartup << 12U);
|
||||
TSB_ADILV->TRGSEL = tmp;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
/* End of group ADC_Exported_Functions */
|
||||
|
||||
/** @} */
|
||||
/* End of group ADC */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#endif /* defined(__TMPM46B_ADC_H) */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,308 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46B_esg.c
|
||||
* @brief This file provides API functions for ESG driver.
|
||||
* @version V2.0.2.2
|
||||
* @date 2018/03/15
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------ */
|
||||
#include "tmpm46b_esg.h"
|
||||
|
||||
#if defined(__TMPM46B_ESG_H)
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ESG
|
||||
* @brief ESG driver modules
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup ESG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define ESG_START_SET (0x00000001U)
|
||||
#define ESG_FINTIMING_CLEAR (0xFFFF0000U)
|
||||
#define ESG_FINTIMING_SET (0x0000FFFFU)
|
||||
#define ESG_LATCHTIMING_SET (0x000F0000U)
|
||||
#define ESG_LATCHTIMING_CLEAR (0xFFF0FFFFU)
|
||||
#define ESG_BUSY_SET (0x00000001U)
|
||||
#define ESG_INT_SET (0x00000001U)
|
||||
#define SRST_IPRST_3_SET (0x00000008U)
|
||||
#define SRST_IPRST_3_CLEAR (0xFFFFFFF7U)
|
||||
#define SRST_PROTECT_DISABLE (0x0000006BU)
|
||||
#define SRST_PROTECT_ENABLE (0x00000000U)
|
||||
#define NUM_BLK (16U)
|
||||
|
||||
static const volatile uint32_t *const ESG_Blk[NUM_BLK] = {
|
||||
&TSB_ESG->BLK00, &TSB_ESG->BLK01, &TSB_ESG->BLK02, &TSB_ESG->BLK03,
|
||||
&TSB_ESG->BLK04, &TSB_ESG->BLK05, &TSB_ESG->BLK06, &TSB_ESG->BLK07,
|
||||
&TSB_ESG->BLK08, &TSB_ESG->BLK09, &TSB_ESG->BLK10, &TSB_ESG->BLK11,
|
||||
&TSB_ESG->BLK12, &TSB_ESG->BLK13, &TSB_ESG->BLK14, &TSB_ESG->BLK15
|
||||
};
|
||||
|
||||
/** @} */
|
||||
/* End of group ESG_Private_Defines */
|
||||
|
||||
/** @defgroup ESG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group ESG_Private_FunctionPrototypes */
|
||||
|
||||
/** @defgroup ESG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group ESG_Private_Functions */
|
||||
|
||||
/** @defgroup ESG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start-up ESG operation.
|
||||
* @param None
|
||||
* @retval The value returned can be one of the following values:
|
||||
* SUCCESS or ERROR
|
||||
* @register The used registers:
|
||||
* ESGCR<START>
|
||||
*/
|
||||
Result ESG_Startup(void)
|
||||
{
|
||||
Result retval = ERROR;
|
||||
|
||||
if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
|
||||
/* Write '1' to ESGCR<START> to enable */
|
||||
TSB_ESG->CR = ESG_START_SET;
|
||||
retval = SUCCESS;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set entropy seed latch timing.
|
||||
* @param Value: The latch timing for ESG
|
||||
* This parameter can be one of the following values:
|
||||
* ESG_LATCH_TIMING_1, ESG_LATCH_TIMING_2, ESG_LATCH_TIMING_3,
|
||||
* ESG_LATCH_TIMING_4, ESG_LATCH_TIMING_5, ESG_LATCH_TIMING_6,
|
||||
* ESG_LATCH_TIMING_7, ESG_LATCH_TIMING_8, ESG_LATCH_TIMING_9,
|
||||
* ESG_LATCH_TIMING_10, ESG_LATCH_TIMING_11, ESG_LATCH_TIMING_12,
|
||||
* ESG_LATCH_TIMING_13, ESG_LATCH_TIMING_14, ESG_LATCH_TIMING_15,
|
||||
* ESG_LATCH_TIMING_16.
|
||||
* @retval The value returned can be one of the following values:
|
||||
* SUCCESS or ERROR
|
||||
* @register The used registers:
|
||||
* ESGOUTCR<LATCHTIMING[19:16]>
|
||||
*/
|
||||
Result ESG_SetLatchTiming(ESG_LatchTiming Value)
|
||||
{
|
||||
/* Read OUTCR, keep bit 15 to 0, clear bit 19 to 16 */
|
||||
uint32_t tmp = TSB_ESG->OUTCR & ESG_LATCHTIMING_CLEAR;
|
||||
Result retval = ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ESG_LATCH_TIMING(Value));
|
||||
|
||||
if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
|
||||
tmp |= (uint32_t) Value << 16;
|
||||
TSB_ESG->OUTCR = tmp;
|
||||
retval = SUCCESS;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get entropy seed latch timing.
|
||||
* @param None
|
||||
* @retval tmp: the value of entropy seed latch timing
|
||||
* @register The used registers:
|
||||
* ESGOUTCR<LATCHTIMING[19:16]>
|
||||
*/
|
||||
uint32_t ESG_GetLatchTiming(void)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = (TSB_ESG->OUTCR & ESG_LATCHTIMING_SET) >> 16;
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Entropy seed output timing.
|
||||
* @param Fintming: the value of entropy seed output timing
|
||||
* @retval The value returned can be one of the following values:
|
||||
* SUCCESS or ERROR
|
||||
* @register The used registers:
|
||||
* ESGOUTCR<FINTIMING[15:0]>
|
||||
*/
|
||||
Result ESG_SetFintiming(uint16_t Fintming)
|
||||
{
|
||||
/* Read OUTCR, keep bit 19 to 16, clear bit 15 to 0 */
|
||||
uint32_t tmp = TSB_ESG->OUTCR & ESG_FINTIMING_CLEAR;
|
||||
Result retval = ERROR;
|
||||
|
||||
/* Get latchtiming value */
|
||||
uint16_t latchtiming = (uint16_t) ESG_GetLatchTiming();
|
||||
|
||||
if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
|
||||
if (Fintming >= 512U * (latchtiming + 1U) + 3U) {
|
||||
tmp |= (uint32_t) Fintming;
|
||||
TSB_ESG->OUTCR = tmp;
|
||||
retval = SUCCESS;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get entropy seed Fintiming.
|
||||
* @param None
|
||||
* @retval tmp: the value of entropy seed Fintiming
|
||||
* @register The used registers:
|
||||
* ESGOUTCR<FINTIMING[15:0]>
|
||||
*/
|
||||
uint16_t ESG_GetFintiming(void)
|
||||
{
|
||||
uint16_t tmp;
|
||||
|
||||
tmp = (uint16_t) TSB_ESG->OUTCR & ESG_FINTIMING_SET;
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the ESG interrupt.
|
||||
* @param None
|
||||
* @retval The value returned can be one of the following values:
|
||||
* SUCCESS or ERROR
|
||||
* @register The used registers:
|
||||
* ESGINT<INT>
|
||||
*/
|
||||
Result ESG_ClrInt(void)
|
||||
{
|
||||
Result retval = ERROR;
|
||||
|
||||
if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
|
||||
/* Write '1' to ESGINT<INT> to clear the interrupt */
|
||||
TSB_ESG->INT = ESG_INT_SET;
|
||||
retval = SUCCESS;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the ESG interrupt status.
|
||||
* @param None
|
||||
* @retval The value returned can be one of the following values:
|
||||
* ENABLE: interrupt occurs
|
||||
* DISABLE: no interrupt
|
||||
* @register The used registers:
|
||||
* ESGINT<INT>
|
||||
*/
|
||||
FunctionalState ESG_GetIntStatus(void)
|
||||
{
|
||||
FunctionalState retval = DISABLE;
|
||||
|
||||
if (TSB_ESG->INT == ESG_INT_SET) {
|
||||
retval = ENABLE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset ESG by peripheral function.
|
||||
* @param None
|
||||
* @retval None
|
||||
* @register The used register:
|
||||
* SRSTIPRST<IPRST3>
|
||||
* SRSTPROTECT
|
||||
*/
|
||||
void ESG_IPReset(void)
|
||||
{
|
||||
uint32_t iprst3 = 0U;
|
||||
|
||||
/* Disable write protection state of SRSTIPRST */
|
||||
TSB_SRST->PROTECT = SRST_PROTECT_DISABLE;
|
||||
|
||||
TSB_SRST->IPRST |= SRST_IPRST_3_SET;
|
||||
|
||||
/* Release reset state */
|
||||
TSB_SRST->IPRST &= SRST_IPRST_3_CLEAR;
|
||||
|
||||
/* Enable write protection state of SRSTIPRST */
|
||||
TSB_SRST->PROTECT = SRST_PROTECT_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the calculation status.
|
||||
* @param None
|
||||
* @retval The calculation status.
|
||||
* The value returned can be one of the following values:
|
||||
* ESG_CALCULATION_COMPLETE, ESG_CALCULATION_PROCESS.
|
||||
* @note Do not write any value to ESG registers when calculation is in process.
|
||||
* @register The used register:
|
||||
* ESGST<BUSY>
|
||||
*/
|
||||
ESG_CalculationStatus ESG_GetCalculationStatus(void)
|
||||
{
|
||||
ESG_CalculationStatus retval = ESG_CALCULATION_COMPLETE;
|
||||
|
||||
if (TSB_ESG->ST == ESG_BUSY_SET) {
|
||||
retval = ESG_CALCULATION_PROCESS;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the calculation result.
|
||||
* @param Seed[16U]: A point that points to the value of calculation result.
|
||||
* @retval None
|
||||
* @register The used registers:
|
||||
* ESGBLK00 to ESGBLK15
|
||||
*/
|
||||
void ESG_GetResult(uint32_t Seed[NUM_BLK])
|
||||
{
|
||||
uint32_t i = 0U;
|
||||
|
||||
for (i = 0U; i < NUM_BLK; i++) {
|
||||
Seed[i] = *ESG_Blk[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** @} */
|
||||
/* End of group ESG_Exported_Functions */
|
||||
|
||||
/** @} */
|
||||
/* End of group ESG */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
#endif /* defined(__TMPM46B_ESG_H) */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,881 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46B_fuart.c
|
||||
* @brief This file provides API functions for Full UART driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/26
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tmpm46b_fuart.h"
|
||||
|
||||
#if defined(__TMPM46B_FUART_H)
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FUART
|
||||
* @brief FUART driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FUART_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define CR_UARTEN_SET ((uint32_t)0x00000001)
|
||||
#define CR_UARTEN_CLEAR ((uint32_t)0xFFFFFF7E)
|
||||
|
||||
#define RSR_ERROR_MASK ((uint32_t)0x0000000F)
|
||||
#define RSR_FERR_FLAG ((uint32_t)0x00000001)
|
||||
#define RSR_PERR_FLAG ((uint32_t)0x00000002)
|
||||
#define RSR_BERR_FLAG ((uint32_t)0x00000004)
|
||||
#define RSR_OERR_FLAG ((uint32_t)0x00000008)
|
||||
|
||||
#define ECR_ERROR_CLEAR ((uint32_t)0x00000000)
|
||||
|
||||
#define FR_BUSY_FLAG ((uint32_t)0x00000008)
|
||||
|
||||
#define LCR_H_FIFO_EN_FLAG ((uint32_t)0x00000010)
|
||||
#define LCR_H_FIFO_EN_SET ((uint32_t)0x00000010)
|
||||
#define LCR_H_FIFO_EN_CLEAR ((uint32_t)0xFFFFFFEF)
|
||||
#define FR_TX_STORAGE_MASK ((uint32_t)0x000000A0)
|
||||
#define FR_RX_STORAGE_MASK ((uint32_t)0x00000050)
|
||||
|
||||
#define FR_TX_STORAGE_NORMAL ((uint32_t)0x00000000)
|
||||
#define FR_TX_STORAGE_FULL ((uint32_t)0x00000020)
|
||||
#define FR_TX_STORAGE_EMPTY ((uint32_t)0x00000080)
|
||||
#define FR_TX_STORAGE_INVALID ((uint32_t)0x000000A0)
|
||||
|
||||
#define FR_RX_STORAGE_NORMAL ((uint32_t)0x00000000)
|
||||
#define FR_RX_STORAGE_EMPTY ((uint32_t)0x00000010)
|
||||
#define FR_RX_STORAGE_FULL ((uint32_t)0x00000040)
|
||||
#define FR_RX_STORAGE_INVALID ((uint32_t)0x00000050)
|
||||
|
||||
#define LCR_H_WLEN_MASK ((uint32_t)0xFFFFFF9F)
|
||||
#define LCR_H_STP2_MASK ((uint32_t)0xFFFFFFF7)
|
||||
#define LCR_H_PARITY_MASK ((uint32_t)0xFFFFFF79)
|
||||
#define CR_FLOW_CTRL_MASK ((uint32_t)0x00000F07)
|
||||
#define CR_MODE_MASK ((uint32_t)0x0000CC07)
|
||||
|
||||
#define LCR_H_BRK_SET ((uint32_t)0x00000001)
|
||||
#define LCR_H_BRK_CLEAR ((uint32_t)0xFFFFFFFE)
|
||||
|
||||
#define CR_SIRLP_MASK ((uint32_t)0xFFFFFFFB)
|
||||
|
||||
#define CR_UARTEN_MASK ((uint32_t)0x00000001)
|
||||
#define CR_SIREN_SET ((uint32_t)0x00000002)
|
||||
#define CR_SIREN_CLEAR ((uint32_t)0xFFFFFFFD)
|
||||
|
||||
#define FUART_INT_BITS ((uint32_t)0x000007FF)
|
||||
|
||||
#define DMACR_DMAONERR_CLEAR ((uint32_t)0x00000003)
|
||||
#define DMACR_DMAONERR_SET ((uint32_t)0x00000004)
|
||||
|
||||
#define DMACR_TXDMAE_CLEAR ((uint32_t)0x00000005)
|
||||
#define DMACR_TXDMAE_SET ((uint32_t)0x00000002)
|
||||
#define DMACR_RXDMAE_CLEAR ((uint32_t)0x00000006)
|
||||
#define DMACR_RXDMAE_SET ((uint32_t)0x00000001)
|
||||
|
||||
#define FR_MODEM_STATUS_MASK ((uint32_t)0x00000107)
|
||||
#define CR_MODEM_STATUS_MASK ((uint32_t)0x00000C00)
|
||||
|
||||
#define CR_RTS_OUTPUT_0 ((uint32_t)0x00000800)
|
||||
#define CR_RTS_OUTPUT_1 ((uint32_t)0xFFFFF77F)
|
||||
|
||||
#define CR_DTR_OUTPUT_0 ((uint32_t)0x00000400)
|
||||
#define CR_DTR_OUTPUT_1 ((uint32_t)0xFFFFFB7F)
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART_Private_Defines */
|
||||
|
||||
/** @defgroup FUART_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART_Private_FunctionPrototypes */
|
||||
|
||||
/** @defgroup FUART_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART_Private_Functions */
|
||||
|
||||
/** @defgroup FUART_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_Enable(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
tmp = FUARTx->CR | CR_UARTEN_SET;
|
||||
FUARTx->CR = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_Disable(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
FUARTx->CR &= CR_UARTEN_CLEAR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get received data from the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval The data received from FUARTx
|
||||
*/
|
||||
uint32_t FUART_GetRxData(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
uint32_t retval = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
/* Return received data */
|
||||
retval = FUARTx->DR & 0xFFU;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set data to be sent and start transmitting via the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param Data: The data to be sent.
|
||||
* The Data range is 0x00 to 0xFF.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetTxData(TSB_FUART_TypeDef * FUARTx, uint32_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUART_DATA(Data));
|
||||
|
||||
FUARTx->DR = Data & 0xFFU;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get receive error status.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval The error flag.
|
||||
* The value returned can be one of the followings:
|
||||
* FUART_NO_ERR, FUART_OVERRUN, FUART_PARITY_ERR,
|
||||
* FUART_FRAMING_ERR, FUART_BREAK_ERR, FUART_ERRS.
|
||||
*/
|
||||
FUART_Err FUART_GetErrStatus(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
FUART_Err retval = FUART_NO_ERR;
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
tmp = (FUARTx->RSR & RSR_ERROR_MASK);
|
||||
switch (tmp) {
|
||||
case RSR_FERR_FLAG: /* Check overrun flag */
|
||||
retval = FUART_FRAMING_ERR;
|
||||
break;
|
||||
case RSR_PERR_FLAG: /* Check parity flag */
|
||||
retval = FUART_PARITY_ERR;
|
||||
break;
|
||||
case RSR_BERR_FLAG: /* Check break flag */
|
||||
retval = FUART_BREAK_ERR;
|
||||
break;
|
||||
case RSR_OERR_FLAG: /* Check overrun flag */
|
||||
retval = FUART_OVERRUN;
|
||||
break;
|
||||
default:
|
||||
if (tmp != 0U) {
|
||||
/* more than one error */
|
||||
retval = FUART_ERRS;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear receive error status.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_ClearErrStatus(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
/* Clear the receive error status */
|
||||
FUARTx->ECR &= ECR_ERROR_CLEAR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the state that whether the specified Full UART channel
|
||||
* is transmitting data or stopped.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval The work state of specified Full UART channel
|
||||
* This parameter can be one of the following values:
|
||||
* BUSY: The Full UART is transmitting data
|
||||
* DONE: The Full UART has stopped transmitting data
|
||||
*/
|
||||
WorkState FUART_GetBusyState(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
WorkState retval = DONE;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
tmp = FUARTx->FR & FR_BUSY_FLAG;
|
||||
|
||||
/* Check busy flag */
|
||||
if (tmp == FR_BUSY_FLAG) {
|
||||
retval = BUSY;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
return retval;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the FIFO or hold register status.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param Direction: The direction of Full UART.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART_RX, FUART_TX
|
||||
* @retval The storage status.
|
||||
* When FIFO is enabled, FUART_StorageStatus indicates the FIFO status.
|
||||
* When FIFO is disabled, FUART_StorageStatus indicates the hold register status.
|
||||
*/
|
||||
FUART_StorageStatus FUART_GetStorageStatus(TSB_FUART_TypeDef * FUARTx, FUART_Direction Direction)
|
||||
{
|
||||
uint32_t fen = 0U;
|
||||
uint32_t src = 0U;
|
||||
FUART_StorageStatus retval = FUART_STORAGE_EMPTY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUART_DIRECTION(Direction));
|
||||
|
||||
fen = FUARTx->LCR_H & LCR_H_FIFO_EN_FLAG;
|
||||
src = FUARTx->FR;
|
||||
if (fen == LCR_H_FIFO_EN_FLAG) { /* FIFO mode */
|
||||
if (Direction == FUART_TX) { /* Get Transmit FIFO status */
|
||||
src = FUARTx->FR & FR_TX_STORAGE_MASK;
|
||||
switch (src) {
|
||||
case FR_TX_STORAGE_NORMAL:
|
||||
retval = FUART_STORAGE_NORMAL;
|
||||
break;
|
||||
case FR_TX_STORAGE_FULL:
|
||||
retval = FUART_STORAGE_FULL;
|
||||
break;
|
||||
case FR_TX_STORAGE_EMPTY:
|
||||
retval = FUART_STORAGE_EMPTY;
|
||||
break;
|
||||
case FR_TX_STORAGE_INVALID:
|
||||
retval = FUART_STORAGE_INVALID;
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
} else { /* Get Receive FIFO status */
|
||||
src = FUARTx->FR & FR_RX_STORAGE_MASK;
|
||||
switch (src) {
|
||||
case FR_RX_STORAGE_NORMAL:
|
||||
retval = FUART_STORAGE_NORMAL;
|
||||
break;
|
||||
case FR_RX_STORAGE_EMPTY:
|
||||
retval = FUART_STORAGE_EMPTY;
|
||||
break;
|
||||
case FR_RX_STORAGE_FULL:
|
||||
retval = FUART_STORAGE_FULL;
|
||||
break;
|
||||
case FR_RX_STORAGE_INVALID:
|
||||
retval = FUART_STORAGE_INVALID;
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else { /* character mode */
|
||||
if (Direction == FUART_TX) { /* Get Transmit hold register status */
|
||||
src = FUARTx->FR & FR_TX_STORAGE_MASK;
|
||||
switch (src) {
|
||||
case FR_TX_STORAGE_NORMAL:
|
||||
case FR_TX_STORAGE_INVALID:
|
||||
retval = FUART_STORAGE_INVALID;
|
||||
break;
|
||||
case FR_TX_STORAGE_FULL:
|
||||
retval = FUART_STORAGE_FULL;
|
||||
break;
|
||||
case FR_TX_STORAGE_EMPTY:
|
||||
retval = FUART_STORAGE_EMPTY;
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
} else { /* Get Receive hold register status */
|
||||
src = FUARTx->FR & FR_RX_STORAGE_MASK;
|
||||
switch (src) {
|
||||
case FR_RX_STORAGE_NORMAL:
|
||||
case FR_RX_STORAGE_INVALID:
|
||||
retval = FUART_STORAGE_INVALID;
|
||||
break;
|
||||
case FR_RX_STORAGE_EMPTY:
|
||||
retval = FUART_STORAGE_EMPTY;
|
||||
break;
|
||||
case FR_RX_STORAGE_FULL:
|
||||
retval = FUART_STORAGE_FULL;
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set IrDA lower-power divisor.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param Divisor: The IrDA Low-power divisor (from 0x01 to 0xFF)
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetIrDADivisor(TSB_FUART_TypeDef * FUARTx, uint32_t Divisor)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUART_IRDA_DIVISOR(Divisor));
|
||||
|
||||
FUARTx->ILPR = Divisor & 0xFFU;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize and configure the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param InitStruct: The structure containing basic Full UART configuration
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_Init(TSB_FUART_TypeDef * FUARTx, FUART_InitTypeDef * InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
uint32_t fuartclk = 0U;
|
||||
uint32_t ibd = 0U; /* Integer part of baud rate divisor */
|
||||
uint32_t fbd = 0U; /* Fractional part of baud rate divisor */
|
||||
uint32_t br = InitStruct->BaudRate; /* BaudRate */
|
||||
/* Check the parameters */
|
||||
assert_param(IS_POINTER_NOT_NULL(InitStruct));
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUART_BAUDRATE(InitStruct->BaudRate));
|
||||
assert_param(IS_FUART_DATA_BITS(InitStruct->DataBits));
|
||||
assert_param(IS_FUART_STOPBITS(InitStruct->StopBits));
|
||||
assert_param(IS_FUART_PARITY(InitStruct->Parity));
|
||||
assert_param(IS_FUART_MODE(InitStruct->Mode));
|
||||
assert_param(IS_FUART_FLOW_CTRL(InitStruct->FlowCtrl));
|
||||
|
||||
/* Get UARTCLK */
|
||||
SystemCoreClockUpdate();
|
||||
fuartclk = SystemCoreClock; /* UARTCLK = fsys */
|
||||
|
||||
ibd = fuartclk / (16U * br);
|
||||
fbd = (8U * fuartclk + br - 128U * ibd * br) / (2U * br);
|
||||
|
||||
if (fbd == 0U) {
|
||||
fbd = 1U; /* Fractional part of baud rate divisor can not be 0x00 */
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
FUARTx->IBRD = ibd; /* Set integer part of baud rate divisor */
|
||||
FUARTx->FBRD = fbd; /* Set fractional part of baud rate divisor */
|
||||
|
||||
tmp = FUARTx->LCR_H;
|
||||
|
||||
tmp &= LCR_H_WLEN_MASK;
|
||||
tmp |= InitStruct->DataBits;
|
||||
|
||||
tmp &= LCR_H_STP2_MASK;
|
||||
tmp |= InitStruct->StopBits;
|
||||
|
||||
tmp &= LCR_H_PARITY_MASK;
|
||||
tmp |= InitStruct->Parity;
|
||||
|
||||
FUARTx->LCR_H = tmp; /* Set DataBits, StopBits, Parity */
|
||||
|
||||
tmp = FUARTx->CR;
|
||||
tmp &= CR_FLOW_CTRL_MASK;
|
||||
tmp |= InitStruct->FlowCtrl;
|
||||
|
||||
tmp &= CR_MODE_MASK;
|
||||
tmp |= InitStruct->Mode;
|
||||
|
||||
FUARTx->CR = tmp; /* Set Flow Control, Mode */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the transmit and receive FIFO.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_EnableFIFO(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
FUARTx->LCR_H |= LCR_H_FIFO_EN_SET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the transmit and receive FIFO and the mode will be changed to character mode.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_DisableFIFO(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
FUARTx->LCR_H &= LCR_H_FIFO_EN_CLEAR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate the break condition for Full UART.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param NewState: New state of the FUART Send break.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetSendBreak(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* Set UARTxLCR_H<BRK> to enable the send break to generate transmit break condition */
|
||||
FUARTx->LCR_H |= LCR_H_BRK_SET;
|
||||
} else {
|
||||
/* Clear UARTxLCR_H<BRK> to disable the send break */
|
||||
FUARTx->LCR_H &= LCR_H_BRK_CLEAR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select IrDA encoding mode for transmitting 0 bits.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param Mode: IrDA encoding mode select for transmitting 0 bits.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART_IRDA_3_16_BIT_PERIOD_MODE
|
||||
* FUART_IRDA_3_TIMES_IRLPBAUD16_MODE
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetIrDAEncodeMode(TSB_FUART_TypeDef * FUARTx, uint32_t Mode)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_IRDA_ENCODE_MODE(Mode));
|
||||
|
||||
/* read UARTCR register then clear bit<SIRLP> as FUART_IRDA_3_16_BIT_PERIOD_MODE */
|
||||
tmp = FUARTx->CR & CR_SIRLP_MASK;
|
||||
|
||||
if (Mode == FUART_IRDA_3_TIMES_IRLPBAUD16_MODE) {
|
||||
/* Set mode as FUART_IRDA_3_TIMES_IRLPBAUD16_MODE */
|
||||
tmp |= FUART_IRDA_3_TIMES_IRLPBAUD16_MODE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
FUARTx->CR = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the IrDA circuit
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval The result of enabling IrDA circuit
|
||||
* This parameter can be one of the following values:
|
||||
* SUCCESS: Enable IrDA circuit successfully.
|
||||
* ERROR: The UART channel is disabled, can not enable IrDA circuit.
|
||||
*/
|
||||
Result FUART_EnableIrDA(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
Result retval = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
/* Get UARTCR<UARTEN> to check if Full UART channel is enabled */
|
||||
tmp = FUARTx->CR & CR_UARTEN_MASK;
|
||||
|
||||
if (tmp == CR_UARTEN_SET) { /* Full UART is enabled */
|
||||
tmp = FUARTx->CR | CR_SIREN_SET;
|
||||
FUARTx->CR = tmp;
|
||||
} else { /* Full UART is disabled */
|
||||
retval = ERROR; /* Can not enable IrDA circuit */
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the IrDA circuit
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_DisableIrDA(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
/* Get UARTCR<UARTEN> to check if Full UART channel is enabled */
|
||||
tmp = FUARTx->CR & CR_UARTEN_MASK;
|
||||
|
||||
if (tmp == CR_UARTEN_SET) { /* Full UART is enabled */
|
||||
tmp = FUARTx->CR & CR_SIREN_CLEAR;
|
||||
FUARTx->CR = tmp;
|
||||
} else { /* Full UART is disabled */
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Receive and Transmit interrupt FIFO level.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param RxLevel: Receive interrupt FIFO level.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART_RX_FIFO_LEVEL_4: The data in Receive FIFO become >= 4 words
|
||||
* FUART_RX_FIFO_LEVEL_8: The data in Receive FIFO become >= 8 words
|
||||
* FUART_RX_FIFO_LEVEL_16: The data in Receive FIFO become >= 16 words
|
||||
* FUART_RX_FIFO_LEVEL_24: The data in Receive FIFO become >= 24 words
|
||||
* FUART_RX_FIFO_LEVEL_28: The data in Receive FIFO become >= 28 words
|
||||
* @param TxLevel: Transmit interrupt FIFO level.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART_TX_FIFO_LEVEL_4: The data in Transmit FIFO become <= 4 words
|
||||
* FUART_TX_FIFO_LEVEL_8: The data in Transmit FIFO become <= 8 words
|
||||
* FUART_TX_FIFO_LEVEL_16: The data in Transmit FIFO become <= 16 words
|
||||
* FUART_TX_FIFO_LEVEL_24: The data in Transmit FIFO become <= 24 words
|
||||
* FUART_TX_FIFO_LEVEL_28: The data in Transmit FIFO become <= 28 words
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetINTFIFOLevel(TSB_FUART_TypeDef * FUARTx, uint32_t RxLevel, uint32_t TxLevel)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUART_RX_FIFO_LEVEL(RxLevel));
|
||||
assert_param(IS_FUART_TX_FIFO_LEVEL(TxLevel));
|
||||
|
||||
tmp = RxLevel | TxLevel;
|
||||
|
||||
FUARTx->IFLS = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Mask(Enable) interrupt source of the specified channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param IntMaskSrc: The interrupt source to be masked(enabled).
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetINTMask(TSB_FUART_TypeDef * FUARTx, uint32_t IntMaskSrc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_INT_MASK_SRC(IntMaskSrc));
|
||||
|
||||
FUARTx->IMSC = IntMaskSrc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the mask(enable) setting for each interrupt source.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval A data with union that it indicates the mask setting.
|
||||
*/
|
||||
FUART_INTStatus FUART_GetINTMask(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
FUART_INTStatus retval = { 0U };
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
retval.All = FUARTx->IMSC & FUART_INT_BITS;
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the raw interrupt status of the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval A data with union that indicates the raw interrupt status.
|
||||
*/
|
||||
FUART_INTStatus FUART_GetRawINTStatus(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
FUART_INTStatus retval = { 0U };
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
retval.All = FUARTx->RIS & FUART_INT_BITS;
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the masked interrupt status of the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval A data with union that indicates the masked interrupt status.
|
||||
*/
|
||||
FUART_INTStatus FUART_GetMaskedINTStatus(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
FUART_INTStatus retval = { 0U };
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
retval.All = FUARTx->MIS & FUART_INT_BITS;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the interrupts of the specified Full UART channel.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param INTStatus: A data with union that indicates the interrupts to be cleared.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_ClearINT(TSB_FUART_TypeDef * FUARTx, FUART_INTStatus INTStatus)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_INT_MASK_SRC(INTStatus.All));
|
||||
|
||||
FUARTx->ICR = INTStatus.All;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the DMA receive request output
|
||||
* on assertion of a UART error interrupt.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param NewState: New state of the DMA receive request output
|
||||
* on assertion of a UART error interrupt.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetDMAOnErr(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* read UARTDMACR then clear bit2 as disable it */
|
||||
tmp = FUARTx->DMACR & DMACR_DMAONERR_CLEAR;
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* if enable, Set bit2: UARTDMACR<DMAONERR> */
|
||||
tmp |= DMACR_DMAONERR_SET;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
FUARTx->DMACR = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable the Transmit FIFO DMA or Receive FIFO DMA.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param Direction: The direction of Full UART.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART_RX, FUART_TX
|
||||
* @param NewState: New state of Transmit or Receive FIFO DMA.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetFIFODMA(TSB_FUART_TypeDef * FUARTx, FUART_Direction Direction,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_FUART_DIRECTION(Direction));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (Direction == FUART_TX) { /* Configure Transmit FIFO DMA */
|
||||
tmp = FUARTx->DMACR & DMACR_TXDMAE_CLEAR;
|
||||
if (NewState == ENABLE) {
|
||||
/* if enable, Set bit1: UARTDMACR<TXDMAE> */
|
||||
tmp |= DMACR_TXDMAE_SET;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
} else { /* Configure Receive FIFO DMA */
|
||||
tmp = FUARTx->DMACR & DMACR_RXDMAE_CLEAR;
|
||||
if (NewState == ENABLE) {
|
||||
/* if enable, Set bit0: UARTDMACR<RXDMAE> */
|
||||
tmp |= DMACR_RXDMAE_SET;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
|
||||
FUARTx->DMACR = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get all the Modem Status, include: CTS, DSR, DCD, RIN, DTR, and RTS.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @retval A data with union that indicates all the modem status.
|
||||
*/
|
||||
FUART_AllModemStatus FUART_GetModemStatus(TSB_FUART_TypeDef * FUARTx)
|
||||
{
|
||||
uint32_t tmpfr = 0U;
|
||||
uint32_t tmpcr = 0U;
|
||||
FUART_AllModemStatus retval = { 0U };
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
|
||||
tmpfr = FUARTx->FR & FR_MODEM_STATUS_MASK; /* Get RI, DCD, DSR, CTS status */
|
||||
tmpcr = FUARTx->CR & CR_MODEM_STATUS_MASK; /* Get RTS,DTS status */
|
||||
|
||||
tmpfr |= tmpcr;
|
||||
retval.All = tmpfr;
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Full UART RTS(Request To Send) modem status output.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param Status: RTS modem status output.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART_MODEM_STATUS_0: The modem status output is 0
|
||||
* FUART_MODEM_STATUS_1: The modem status output is 1
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetRTSStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_MODEM_STATUS(Status));
|
||||
|
||||
if (Status == FUART_MODEM_STATUS_1) {
|
||||
/* Set UARTxCR<RTS> to make RTS modem status output be 1 */
|
||||
FUARTx->CR &= CR_RTS_OUTPUT_1;
|
||||
} else {
|
||||
/* Set UARTxCR<RTS> to make RTS modem status output be 0 */
|
||||
tmp = FUARTx->CR | CR_RTS_OUTPUT_0;
|
||||
FUARTx->CR = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Full UART DTR(Data Transmit Ready) modem status output.
|
||||
* @param FUARTx: Select the Full UART channel.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART0, FUART1.
|
||||
* @param Status: DTR modem status output.
|
||||
* This parameter can be one of the following values:
|
||||
* FUART_MODEM_STATUS_0: The modem status output is 0
|
||||
* FUART_MODEM_STATUS_1: The modem status output is 1
|
||||
* @retval None
|
||||
*/
|
||||
void FUART_SetDTRStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUART_PERIPH(FUARTx));
|
||||
assert_param(IS_MODEM_STATUS(Status));
|
||||
|
||||
if (Status == FUART_MODEM_STATUS_1) {
|
||||
/* Set UARTxCR<DTR> to make DTR modem status output be 1 */
|
||||
FUARTx->CR &= CR_DTR_OUTPUT_1;
|
||||
} else {
|
||||
/* Set UARTxCR<DTR> to make DTR modem status output be 0 */
|
||||
tmp = FUARTx->CR | CR_DTR_OUTPUT_0;
|
||||
FUARTx->CR = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART_Exported_Functions */
|
||||
|
||||
/** @} */
|
||||
/* End of group FUART */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#endif /* defined(__TMPM46B_FUART_H) */
|
||||
|
|
@ -0,0 +1,659 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_gpio.c
|
||||
* @brief This file provides API functions for GPIO driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/09
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tmpm46b_gpio.h"
|
||||
|
||||
#if defined(__TMPM46B_GPIO_H)
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_NUM (11U) /* total number of gpio */
|
||||
|
||||
/**
|
||||
* @brief the base address of GPIO port.
|
||||
*/
|
||||
const uint32_t GPIO_Base[GPIO_NUM] = {
|
||||
TSB_PA_BASE, TSB_PB_BASE, TSB_PC_BASE, TSB_PD_BASE, TSB_PE_BASE,
|
||||
TSB_PF_BASE, TSB_PG_BASE, TSB_PH_BASE, TSB_PJ_BASE, TSB_PK_BASE,
|
||||
TSB_PL_BASE
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief:Information of gpio port.
|
||||
* Note: for bit0 to bit7 of each member below, its value '0' or '1' has the means:
|
||||
* '0': that bit is not available
|
||||
* '1': that bit is available
|
||||
* For example, if DATA = 0x7F, it mean the bit0 to bit6 of DATA register are available.
|
||||
*/
|
||||
const GPIO_RegTypeDef GPIO_SFRs[GPIO_NUM] = {
|
||||
/* DATA CR FR1 FR2 FR3 FR4 FR5 FR6 OD PUP PDN IE */
|
||||
/* PA */ {0xFFU, 0xFFU, {0xFFU, 0xFFU, 0xE0U, 0x80U, 0x80U, 0x00U}, 0xFFU, 0xFBU, 0x04U, 0xFFU},
|
||||
/* PB */ {0xFFU, 0xFFU, {0x7FU, 0x40U, 0x3FU, 0x4CU, 0xFCU, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xBFU},
|
||||
/* PC */ {0x3FU, 0x3FU, {0x3CU, 0x20U, 0x00U, 0x00U, 0x00U, 0x00U}, 0x3FU, 0x3FU, 0x00U, 0x3FU},
|
||||
/* PD */ {0x1FU, 0x1FU, {0x1FU, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, 0x1FU, 0x1FU, 0x00U, 0x1FU},
|
||||
/* PE */ {0xFFU, 0xFFU, {0x7EU, 0x00U, 0xFFU, 0x18U, 0x9FU, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
|
||||
/* PF */ {0xFFU, 0xFFU, {0xFFU, 0x00U, 0xFFU, 0xC6U, 0x78U, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
|
||||
/* PG */ {0xFFU, 0xFFU, {0xFFU, 0x00U, 0x0FU, 0x0CU, 0xFFU, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
|
||||
/* PH */ {0x0FU, 0x0FU, {0x0FU, 0x03U, 0x0FU, 0x0FU, 0x00U, 0x00U}, 0x0FU, 0x0FU, 0x00U, 0x0FU},
|
||||
/* PJ */ {0xFFU, 0xFFU, {0x80U, 0x80U, 0x80U, 0x00U, 0x00U, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
|
||||
/* PK */ {0x1FU, 0x1FU, {0x00U, 0x1EU, 0x0CU, 0x02U, 0x00U, 0x00U}, 0x1FU, 0x1FU, 0x00U, 0x1FU},
|
||||
/* PL */ {0x0FU, 0x0FU, {0x00U, 0x00U, 0x0FU, 0x0DU, 0x0EU, 0x08U}, 0x0FU, 0x0FU, 0x00U, 0x0FU}
|
||||
};
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read GPIO Data register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL
|
||||
* @retval Data:The value of DATA register.
|
||||
*/
|
||||
uint8_t GPIO_ReadData(GPIO_Port GPIO_x)
|
||||
{
|
||||
uint8_t Data = 0U;
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
Data = (uint8_t) PORT->DATA;
|
||||
|
||||
return Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read Bit of GPIO Data register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7.
|
||||
* @retval BitValue:The value of specified Bit.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
|
||||
*/
|
||||
uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x)
|
||||
{
|
||||
uint8_t Data = 0U;
|
||||
uint8_t tmp = 0U;
|
||||
uint8_t BitValue = 0U;
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_GPIO_BIT(Bit_x));
|
||||
assert_param(IS_GPIO_BIT_DATA(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
Data = (uint8_t) PORT->DATA;
|
||||
tmp = (uint8_t) (Data & Bit_x);
|
||||
if (tmp) {
|
||||
BitValue = GPIO_BIT_VALUE_1;
|
||||
} else {
|
||||
BitValue = GPIO_BIT_VALUE_0;
|
||||
}
|
||||
|
||||
return (BitValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write specified value to GPIO DATA register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Data: specified value will be written to GPIO DATA register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data)
|
||||
{
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_GPIO_WRITE(GPIO_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
PORT->DATA = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write to specified Bit of GPIO DATA register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin,which can set as output.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @param BitValue:The value of specified Bit.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue)
|
||||
{
|
||||
uint8_t tmp = 0U;
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_GPIO_BIT_VALUE(BitValue));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinCR;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
tmp = GPIO_ReadData(GPIO_x);
|
||||
if (BitValue) {
|
||||
tmp |= Bit_x;
|
||||
} else {
|
||||
Bit_x = (~Bit_x);
|
||||
tmp &= Bit_x;
|
||||
}
|
||||
PORT->DATA = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the specified GPIO pin.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @param GPIO_InitStruct: The structure containing basic GPIO configuration.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct)
|
||||
{
|
||||
uint8_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_POINTER_NOT_NULL(GPIO_InitStruct));
|
||||
assert_param(IS_GPIO_IO_MODE_STATE(GPIO_InitStruct->IOMode));
|
||||
assert_param(IS_GPIO_PULLUP_STATE(GPIO_InitStruct->PullUp));
|
||||
assert_param(IS_GPIO_PULLDOWN_STATE(GPIO_InitStruct->PullDown));
|
||||
assert_param(IS_GPIO_OPEN_DRAIN_STATE(GPIO_InitStruct->OpenDrain));
|
||||
|
||||
tmp = GPIO_InitStruct->IOMode;
|
||||
switch (tmp) {
|
||||
case GPIO_INPUT_MODE:
|
||||
GPIO_SetInput(GPIO_x, Bit_x);
|
||||
break;
|
||||
case GPIO_OUTPUT_MODE:
|
||||
GPIO_SetOutput(GPIO_x, Bit_x);
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
tmp = GPIO_InitStruct->PullUp;
|
||||
switch (tmp) {
|
||||
case GPIO_PULLUP_ENABLE:
|
||||
GPIO_SetPullUp(GPIO_x, Bit_x, ENABLE);
|
||||
break;
|
||||
case GPIO_PULLUP_DISABLE:
|
||||
GPIO_SetPullUp(GPIO_x, Bit_x, DISABLE);
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
tmp = GPIO_InitStruct->PullDown;
|
||||
switch (tmp) {
|
||||
case GPIO_PULLDOWN_ENABLE:
|
||||
GPIO_SetPullDown(GPIO_x, Bit_x, ENABLE);
|
||||
break;
|
||||
case GPIO_PULLDOWN_DISABLE:
|
||||
GPIO_SetPullDown(GPIO_x, Bit_x, DISABLE);
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
tmp = GPIO_InitStruct->OpenDrain;
|
||||
switch (tmp) {
|
||||
case GPIO_OPEN_DRAIN_ENABLE:
|
||||
GPIO_SetOpenDrain(GPIO_x, Bit_x, ENABLE);
|
||||
break;
|
||||
case GPIO_OPEN_DRAIN_DISABLE:
|
||||
GPIO_SetOpenDrain(GPIO_x, Bit_x, DISABLE);
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set specified GPIO Pin as output port.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x)
|
||||
{
|
||||
uint8_t tmp = 0U;
|
||||
uint32_t i;
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinCR;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
tmp = (~Bit_x);
|
||||
for (i = 0U; i < FRMAX; i++) {
|
||||
if (GPIO_SFRs[GPIO_x].PinFR[i]) {
|
||||
PORT->FR[i] &= tmp;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
if (GPIO_SFRs[GPIO_x].PinIE) {
|
||||
PORT->IE &= tmp;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
PORT->CR |= Bit_x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set specified GPIO Pin as input port.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x)
|
||||
{
|
||||
uint8_t tmp = 0U;
|
||||
uint32_t i;
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinIE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
tmp = (~Bit_x);
|
||||
for (i = 0U; i < FRMAX; i++) {
|
||||
if (GPIO_SFRs[GPIO_x].PinFR[i]) {
|
||||
PORT->FR[i] &= tmp;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
if (GPIO_SFRs[GPIO_x].PinCR) {
|
||||
PORT->CR &= tmp;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
PORT->IE |= Bit_x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or clear the bit setting in output control register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @param NewState: The output state of the pin.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE , DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
|
||||
{
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinCR;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
if (NewState == ENABLE) {
|
||||
PORT->CR |= Bit_x;
|
||||
} else {
|
||||
PORT->CR &= (~(uint32_t) Bit_x);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or clear the bit setting in input control register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @param NewState: The input state of the pin.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE , DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
|
||||
{
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinIE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
PORT->IE |= Bit_x;
|
||||
} else {
|
||||
PORT->IE &= (~(uint32_t) Bit_x);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable pull-up function of specified GPIO Pin.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @param NewState: New state of the Pull-Up function.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE , DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
|
||||
{
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinPUP;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_PUP(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
if (NewState == ENABLE) {
|
||||
PORT->PUP |= Bit_x;
|
||||
} else {
|
||||
PORT->PUP &= (~(uint32_t) Bit_x);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable pull-down function of specified GPIO Pin.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_2, GPIO_BIT_ALL, or combination of the effective bits.
|
||||
* @param NewState: New state of the Pull-Down function.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE , DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
|
||||
{
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinPDN;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_PDN(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
if (NewState == ENABLE) {
|
||||
PORT->PDN |= Bit_x;
|
||||
} else {
|
||||
PORT->PDN &= (~(uint32_t) Bit_x);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set specified GPIO Pin as open drain port or CMOS port.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @param NewState: New state of the Open Drain function.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE , DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
|
||||
{
|
||||
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinOD;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_OD(GPIO_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
if (NewState == ENABLE) {
|
||||
PORT->OD |= Bit_x;
|
||||
} else {
|
||||
PORT->OD &= (~(uint32_t) Bit_x);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable specified GPIO Function register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK
|
||||
* GPIO_PL.
|
||||
* @param FuncReg_x: Select Function register of GPIO.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_FUNC_REG_1, GPIO_FUNC_REG_2, GPIO_FUNC_REG_3,
|
||||
* GPIO_FUNC_REG_4, GPIO_FUNC_REG_5, GPIO_FUNC_REG_6.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
|
||||
{
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
PORT->FR[FuncReg_x] |= Bit_x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable specified GPIO Function register.
|
||||
* @param GPIO_x: Select GPIO port.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
|
||||
* GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
|
||||
* GPIO_PL.
|
||||
* @param FuncReg_x: Select Function register of GPIO.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_FUNC_REG_1, GPIO_FUNC_REG_2, GPIO_FUNC_REG_3,
|
||||
* GPIO_FUNC_REG_4, GPIO_FUNC_REG_5, GPIO_FUNC_REG_6.
|
||||
* @param Bit_x: Select GPIO pin.
|
||||
* This parameter can be one of the following values:
|
||||
* GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
|
||||
* GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
|
||||
* or combination of the effective bits.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
|
||||
{
|
||||
TSB_Port_TypeDef *PORT = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PORT(GPIO_x));
|
||||
assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
|
||||
|
||||
if (Bit_x == GPIO_BIT_ALL) {
|
||||
Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
|
||||
|
||||
PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
|
||||
PORT->FR[FuncReg_x] &= (~(uint32_t) Bit_x);
|
||||
}
|
||||
|
||||
/** @} */
|
||||
/* End of group GPIO_Exported_Functions */
|
||||
/** @} */
|
||||
/* End of group GPIO */
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
#endif /* defined(__TMPM46B_GPIO_H) */
|
||||
|
|
@ -0,0 +1,450 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_i2c.c
|
||||
* @brief This file provides API functions for I2C driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/13
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tmpm46b_i2c.h"
|
||||
|
||||
#if defined(__TMPM46B_I2C_H)
|
||||
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C
|
||||
* @brief I2C driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2CCR1_BC_MASK ((uint32_t)0x0000001F)
|
||||
#define I2CCR1_ACK_SET ((uint32_t)0x00000010)
|
||||
#define I2CCR1_ACK_CLEAR ((uint32_t)0x000000EF)
|
||||
#define I2CCR1_SCK_MASK ((uint32_t)0x000000F8)
|
||||
#define I2CCR1_NOACK_MASK ((uint32_t)0x00000008)
|
||||
#define I2CCR1_NOACK_ENABLE ((uint32_t)0x00000000)
|
||||
|
||||
#define I2CCR2_PIN_SET ((uint32_t)0x00000010)
|
||||
#define I2CCR2_I2CM_I2C ((uint32_t)0x00000008)
|
||||
#define I2CCR2_SWRST_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define I2CCR2_SWRST_CMD1 ((uint32_t)0x00000002)
|
||||
#define I2CCR2_SWRST_CMD2 ((uint32_t)0x00000001)
|
||||
#define I2CCR2_START_CONDITION ((uint32_t)0x000000F0)
|
||||
#define I2CCR2_STOP_CONDITION ((uint32_t)0x000000D0)
|
||||
|
||||
|
||||
#define I2CAR_SA_MASK ((uint32_t)0x000000FE)
|
||||
#define I2CAR_ALS_SET ((uint32_t)0x00000001)
|
||||
#define I2CAR_ALS_CLEAR ((uint32_t)0xFFFFFFFE)
|
||||
#define I2C_DATA_MASK ((uint32_t)0x000000FF)
|
||||
|
||||
#define I2CIE_IE_SET ((uint32_t)0x00000001)
|
||||
#define I2CIE_IE_CLEAR ((uint32_t)0xFFFFFFFE)
|
||||
|
||||
#define I2CIR_ISIC_MASK ((uint32_t)0x00000001)
|
||||
#define I2CIR_ISIC_SET ((uint32_t)0x00000001)
|
||||
|
||||
/** @} */
|
||||
/* End of group I2C_Private_Defines */
|
||||
|
||||
/** @defgroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the generation of ACK clock.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @param NewState: New state of ACK clock.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
tmp = I2Cx->CR1;
|
||||
if (NewState == ENABLE) {
|
||||
/* Set I2CxCR1<ACK> to enable generation of ACK clock */
|
||||
tmp |= I2CCR1_ACK_SET;
|
||||
} else {
|
||||
/* Clear I2CxCR1<ACK> to disable generation of ACK clock */
|
||||
tmp &= I2CCR1_ACK_CLEAR;
|
||||
}
|
||||
I2Cx->CR1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the specified I2C channel in I2C mode.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @param InitI2CStruct: The structure containing I2C in I2C mode configuration.
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
assert_param(IS_POINTER_NOT_NULL(InitI2CStruct));
|
||||
assert_param(IS_I2C_ADDR(InitI2CStruct->I2CSelfAddr));
|
||||
assert_param(IS_I2C_BIT_NUM(InitI2CStruct->I2CDataLen));
|
||||
assert_param(IS_I2C_SCK_CLK_DIV(InitI2CStruct->I2CClkDiv));
|
||||
assert_param(IS_FUNCTIONAL_STATE(InitI2CStruct->I2CACKState));
|
||||
|
||||
/* Get the system clock frequency */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Check the prescaler clock in the range between 50ns and 150ns */
|
||||
assert_param(IS_PRESCALER_CLK_VALID(InitI2CStruct->PrescalerClkDiv, SystemCoreClock));
|
||||
|
||||
/* Set prescaler clock */
|
||||
I2Cx->PRS = InitI2CStruct->PrescalerClkDiv % I2C_PRESCALER_DIV_32;
|
||||
|
||||
/* Set selfaddress for I2Cx */
|
||||
I2Cx->AR = InitI2CStruct->I2CSelfAddr & I2CAR_SA_MASK;
|
||||
|
||||
/* Set I2C bit length of transfer data */
|
||||
tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
|
||||
tmp |= (InitI2CStruct->I2CDataLen << 5U);
|
||||
/* Set I2C clock division */
|
||||
tmp &= I2CCR1_SCK_MASK;
|
||||
tmp |= InitI2CStruct->I2CClkDiv;
|
||||
if (InitI2CStruct->I2CACKState) {
|
||||
/* Set I2CxCR1<ACK> to enable generation of ACK clock */
|
||||
tmp |= I2CCR1_ACK_SET;
|
||||
} else {
|
||||
/* Clear I2CxCR1<ACK> to disable generation of ACK clock */
|
||||
tmp &= I2CCR1_ACK_CLEAR;
|
||||
}
|
||||
I2Cx->CR1 = tmp;
|
||||
|
||||
/* Initialize I2C to I2C Slave-Rx mode */
|
||||
I2Cx->CR2 = I2CCR2_PIN_SET | I2CCR2_I2CM_I2C;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify the number of bits per transfer.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @param I2CBitNum: Specify the number of bits.
|
||||
* This parameter can be one of the following values:
|
||||
* I2C_DATA_LEN_8, I2C_DATA_LEN_1,I2C_DATA_LEN_2,I2C_DATA_LEN_3,
|
||||
* I2C_DATA_LEN_4, I2C_DATA_LEN_5,I2C_DATA_LEN_6 and I2C_DATA_LEN_7.
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
assert_param(IS_I2C_BIT_NUM(I2CBitNum));
|
||||
|
||||
/* Write number of bits per transfer into I2CxCR1<BC> */
|
||||
tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
|
||||
tmp |= ((uint32_t) I2CBitNum << 5U);
|
||||
|
||||
I2Cx->CR1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the state of the specified I2C channel.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_SWReset(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
tmp = I2Cx->CR2 & I2CCR2_SWRST_MASK;
|
||||
I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD1;
|
||||
I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear I2C interrupt request in I2C mode.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
/* Set I2CxCR2<PIN> to clear request, and Set I2CxCR2<I2CM> to enable I2C operation */
|
||||
tmp = I2Cx->SR;
|
||||
tmp &= (uint32_t) 0x000000E0;
|
||||
tmp |= (I2CCR2_PIN_SET | I2CCR2_I2CM_I2C);
|
||||
I2Cx->CR2 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set I2c bus to Master mode and Generate start condition in I2C mode.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
/* Set I2CxCR2<MST>, <TRX>, <BB> and <PIN> to generate start condition */
|
||||
I2Cx->CR2 = I2CCR2_START_CONDITION | I2CCR2_I2CM_I2C;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set I2c bus to Master mode and Generate stop condition in I2C mode.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
/* Set I2CxCR2<MST>, <TRX>, <PIN> and clear <BB> to generate stop condition */
|
||||
I2Cx->CR2 = I2CCR2_STOP_CONDITION | I2CCR2_I2CM_I2C;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the I2C channel state in I2C mode
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval The state of the I2C channel in I2C bus.
|
||||
*/
|
||||
I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
I2C_State state;
|
||||
state.All = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
state.All = I2Cx->SR;
|
||||
state.All &= I2C_DATA_MASK;
|
||||
return state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set data to be sent and MCU starts transmission.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @param Data: The data to be sent, max 0xFF.
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
assert_param(IS_I2C_DATA(Data));
|
||||
|
||||
/* Write data into I2CxDBR */
|
||||
I2Cx->DBR = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get data having been received.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval The data having been received
|
||||
*/
|
||||
uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
uint32_t retval = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
/* Save the received data */
|
||||
retval = I2Cx->DBR;
|
||||
retval &= I2C_DATA_MASK;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable I2C free data mode of the I2C channel.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @param NewState: New state of free data mode.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* Set I2CxI2CAR<ALS> to use free data mode transfer in I2C mode */
|
||||
I2Cx->AR |= I2CAR_ALS_SET;
|
||||
} else {
|
||||
/* Clear I2CxI2CAR<ALS> to not use free data mode transfer in I2C mode */
|
||||
I2Cx->AR &= I2CAR_ALS_CLEAR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get slave address match detection state.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval DISABLE or ENABLE.
|
||||
*/
|
||||
FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
FunctionalState retval = DISABLE;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
tmp = I2Cx->CR1 & I2CCR1_NOACK_MASK;
|
||||
if (tmp == I2CCR1_NOACK_ENABLE) {
|
||||
/* the slave address match or general call detection are enabled. */
|
||||
retval = ENABLE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set prescaler clock of the specified I2C channel.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @param PrescalerClock: the prescaler clock value.
|
||||
* This parameter can be one of the following values:
|
||||
* I2C_PRESCALER_DIV_1 to I2C_PRESCALER_DIV_32
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
/* Get the system clock frequency */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Check the prescaler clock in the range between 50ns and 150ns */
|
||||
assert_param(IS_PRESCALER_CLK_VALID(PrescalerClock, SystemCoreClock));
|
||||
|
||||
/* Write prescaler clock into I2CxPRS<PRSCK> */
|
||||
I2Cx->PRS = PrescalerClock % I2C_PRESCALER_DIV_32;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable interrupt request of the I2C channel.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @param NewState: Specify I2C interrupt setting.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_SetINTReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* Set I2CxIE<IE> to enable interrupt request */
|
||||
I2Cx->IE |= I2CIE_IE_SET;
|
||||
} else {
|
||||
/* Clear I2CxIE<IE> to disable interrupt request */
|
||||
I2Cx->IE &= I2CIE_IE_CLEAR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt generation state.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval DISABLE or ENABLE.
|
||||
*/
|
||||
FunctionalState I2C_GetINTStatus(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
FunctionalState retval = DISABLE;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
tmp = I2Cx->IR & I2CIR_ISIC_MASK;
|
||||
if (tmp == I2CIR_ISIC_SET) {
|
||||
/* the I2C interrupt has been generated */
|
||||
retval = ENABLE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the I2C interrupt output.
|
||||
* @param I2Cx: Select the I2C channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_I2C0,TSB_I2C1,TSB_I2C2
|
||||
* @retval None
|
||||
*/
|
||||
void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_PERIPH(I2Cx));
|
||||
|
||||
/* Set I2CxIR<ISIC> to clear the I2C interrupt output(INTI2Cx) */
|
||||
I2Cx->IR = I2CIR_ISIC_SET;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
/* End of group I2C_Exported_Functions */
|
||||
|
||||
/** @} */
|
||||
/* End of group I2C */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#endif /* defined(__TMPM46B_I2C_H) */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,661 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_ssp.c
|
||||
* @brief This file provides API functions for SSP driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/05
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
******************************************************************************/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tmpm46b_ssp.h"
|
||||
|
||||
#if defined(__TMPM46B_SSP_H)
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SSP
|
||||
* @brief SSP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SSP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SSP_ENABLE_SET ((uint32_t)0x00000002)
|
||||
#define SSP_CR1_MASK ((uint32_t)0x0000000F)
|
||||
#define SSP_ENABLE_CLEAR ((uint32_t)0x0000000D)
|
||||
|
||||
#define SSP_SCR_MASK ((uint32_t)0x000000FF)
|
||||
#define SSP_FORMAT_MASK ((uint32_t)0x0000FFCF)
|
||||
#define SSP_SPO_MASK ((uint32_t)0x0000FFBF)
|
||||
#define SSP_SPH_MASK ((uint32_t)0x0000FF7F)
|
||||
#define SSP_DSS_MASK ((uint32_t)0x0000FFF0)
|
||||
#define SSP_SOD_SET ((uint32_t)0x00000008)
|
||||
#define SSP_SOD_CLEAR ((uint32_t)0x00000007)
|
||||
|
||||
#define SSP_MS_SETSLAVE ((uint32_t)0x00000004)
|
||||
#define SSP_MS_MASK ((uint32_t)0x0000000B)
|
||||
|
||||
#define SSP_LBM_SET ((uint32_t)0x00000001)
|
||||
#define SSP_LBM_CLEAR ((uint32_t)0x0000000E)
|
||||
|
||||
#define SSP_BSY_MASK ((uint32_t)0x00000010)
|
||||
|
||||
#define SSP_TXFIFO_SR_MASK ((uint32_t)0x00000003)
|
||||
#define SSP_RXFIFO_SR_MASK ((uint32_t)0x0000000C)
|
||||
|
||||
#define SSP_IMSC_MASK ((uint32_t)0x0000000F)
|
||||
#define SSP_RIS_MASK ((uint32_t)0x0000000F)
|
||||
#define SSP_MIS_MASK ((uint32_t)0x0000000F)
|
||||
|
||||
#define SSP_DMA_MASK ((uint32_t)0x00000003)
|
||||
|
||||
#define SSP_TXFIFO_FULL 0U
|
||||
#define SSP_TXFIFO_INVALID 1U
|
||||
#define SSP_TXFIFO_NORMAL 2U
|
||||
#define SSP_TXFIFO_EMPTY 3U
|
||||
|
||||
#define SSP_RXFIFO_FULL 3U
|
||||
#define SSP_RXFIFO_INVALID 2U
|
||||
#define SSP_RXFIFO_NORMAL 1U
|
||||
#define SSP_RXFIFO_EMPTY 0U
|
||||
|
||||
/** @} */
|
||||
/* End of group SSP_Private_Defines */
|
||||
|
||||
/** @defgroup SSP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group SSP_Private_FunctionPrototypes */
|
||||
|
||||
/** @defgroup SSP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group SSP_Private_Functions */
|
||||
|
||||
/** @defgroup SSP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified SSP channel
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_Enable(TSB_SSP_TypeDef * SSPx)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
/* Set SSPxCR1<SSE> to enable SSP module */
|
||||
tmp = SSPx->CR1 & SSP_CR1_MASK;
|
||||
tmp |= SSP_ENABLE_SET;
|
||||
SSPx->CR1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the specified SSP channel
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_Disable(TSB_SSP_TypeDef * SSPx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
/* Clear SSPxCR1<SSE> to disable SSP module */
|
||||
SSPx->CR1 &= SSP_ENABLE_CLEAR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the specified SSP channel through the data in structure SSP_InitTypeDef
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param InitStruct: Parameters to configure SSP module,
|
||||
* It includes data to set Frame Format, Clock prescale divider, Clock Rate,Clock Phase and Polarity, DataSize and Mode.
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_Init(TSB_SSP_TypeDef * SSPx, SSP_InitTypeDef * InitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_POINTER_NOT_NULL(InitStruct));
|
||||
|
||||
SSP_SetFrameFormat(SSPx, InitStruct->FrameFormat);
|
||||
SSP_SetClkPreScale(SSPx, InitStruct->PreScale, InitStruct->ClkRate);
|
||||
SSP_SetClkPolarity(SSPx, InitStruct->ClkPolarity);
|
||||
SSP_SetClkPhase(SSPx, InitStruct->ClkPhase);
|
||||
SSP_SetDataSize(SSPx, InitStruct->DataSize);
|
||||
SSP_SetMSMode(SSPx, InitStruct->Mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bit rate for transmit and receive for the specified SSP channel.
|
||||
* BitRate = fSYS / (PreScale x (1 + ClkRate))
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param PreScale: Clock prescale divider(even number from 2 to 254)
|
||||
* @param ClkRate: Serial clock rate (From 0 to 255)
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetClkPreScale(TSB_SSP_TypeDef * SSPx, uint8_t PreScale, uint8_t ClkRate)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_PRE_SCALE(PreScale));
|
||||
|
||||
/* Set serial clock rate */
|
||||
tmp = SSPx->CR0 & SSP_SCR_MASK;
|
||||
tmp |= (((uint32_t) ClkRate) << 8U);
|
||||
SSPx->CR0 = tmp;
|
||||
|
||||
/* Set clock prescale divider */
|
||||
SSPx->CPSR = (uint32_t) PreScale;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify the Frame Format of specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param FrameFormat: Frame Format of SSP
|
||||
* This parameter can be one of the following values:
|
||||
* SSP_FORMAT_SPI,
|
||||
* SSP_FORMAT_SSI,
|
||||
* SSP_FORMAT_MICROWIRE
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetFrameFormat(TSB_SSP_TypeDef * SSPx, SSP_FrameFormat FrameFormat)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_FRAME_FORMAT(FrameFormat));
|
||||
|
||||
/* Set Frame Format */
|
||||
tmp = SSPx->CR0 & SSP_FORMAT_MASK;
|
||||
tmp |= (((uint32_t) FrameFormat) << 4U);
|
||||
SSPx->CR0 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief When specified SSP channel is configured as SPI mode, specify the clock polarity in its idle state.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param ClkPolarity: SPI clock polarity
|
||||
* This parameter can be one of the following values:
|
||||
* SSP_POLARITY_LOW,
|
||||
* SSP_POLARITY_HIGH
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetClkPolarity(TSB_SSP_TypeDef * SSPx, SSP_ClkPolarity ClkPolarity)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_CLK_POLARITY(ClkPolarity));
|
||||
|
||||
/* Set clock polarity */
|
||||
tmp = SSPx->CR0 & SSP_SPO_MASK;
|
||||
tmp |= (((uint32_t) ClkPolarity) << 6U);
|
||||
SSPx->CR0 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief When specified SSP channel is configured as SPI mode, specify its clock phase.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param ClkPolarity: SPI clock phase
|
||||
* This parameter can be one of the following values:
|
||||
* SSP_PHASE_FIRST_EDGE : To captures serial data on the first clock transition of a frame.
|
||||
* SSP_PHASE_SECOND_EDGE : To captures serial data on the second clock transition of a frame
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetClkPhase(TSB_SSP_TypeDef * SSPx, SSP_ClkPhase ClkPhase)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_CLK_PHASE(ClkPhase));
|
||||
|
||||
/* Set clock phase */
|
||||
tmp = SSPx->CR0 & SSP_SPH_MASK;
|
||||
tmp |= (((uint32_t) ClkPhase) << 7U);
|
||||
SSPx->CR0 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Rx/Tx data size for the specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param DataSize: Data size select. From 4 to 16
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetDataSize(TSB_SSP_TypeDef * SSPx, uint8_t DataSize)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_DATA_BIT_SIZE(DataSize));
|
||||
|
||||
/* Set Rx/Tx Data Size */
|
||||
tmp = SSPx->CR0 & SSP_DSS_MASK;
|
||||
tmp |= ((uint32_t) DataSize - 1U);
|
||||
SSPx->CR0 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable slave mode, SPDO pin output for the specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param NewState: New state of slave mode output setting.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetSlaveOutputCtrl(TSB_SSP_TypeDef * SSPx, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Read SFR(Special Function Register)then clear other bits, also clear SSPxCR1<SOD>), bit3 as enable it */
|
||||
tmp = SSPx->CR1 & SSP_SOD_CLEAR;
|
||||
|
||||
/* Set SSPxCR1<SOD>, bit3 */
|
||||
if (NewState == DISABLE) {
|
||||
tmp |= SSP_SOD_SET;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
SSPx->CR1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select Master or Slave mode for the specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param Mode: SSP device mode
|
||||
* This parameter can be SSP_MASTER or SSP_SLAVE.
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetMSMode(TSB_SSP_TypeDef * SSPx, SSP_MS_Mode Mode)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_MS_MODE(Mode));
|
||||
|
||||
/* Read SFR(Special Function Register)then clear other bits, also clear(SSPxCR1<MS>), bit2 as select master mode */
|
||||
tmp = SSPx->CR1 & SSP_MS_MASK;
|
||||
|
||||
/* Set SSPxCR1<MS>, bit2 */
|
||||
if (Mode == SSP_SLAVE) {
|
||||
tmp |= SSP_MS_SETSLAVE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
SSPx->CR1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set loop back mode for the specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param NewState: New state of loop back mode.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE,
|
||||
* DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetLoopBackMode(TSB_SSP_TypeDef * SSPx, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Read SFR(Special Function Register)then clear other bits, also clear (SSPxCR1<LBM>), bit0 as disable it */
|
||||
tmp = SSPx->CR1 & SSP_LBM_CLEAR;
|
||||
|
||||
/* Set SSPxCR1<LBM>, bit0 */
|
||||
if (NewState == ENABLE) {
|
||||
tmp |= SSP_LBM_SET;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
SSPx->CR1 = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the data to be sent into Tx FIFO of the specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param Data: the 4~16bit data to be send
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetTxData(TSB_SSP_TypeDef * SSPx, uint16_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
SSPx->DR = (uint32_t) Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the data received from Rx FIFO of the specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @retval The 4~16bit data received from FIFO.
|
||||
*/
|
||||
uint16_t SSP_GetRxData(TSB_SSP_TypeDef * SSPx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
return ((uint16_t) (SSPx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Busy or Idle state of the specified SSP channel
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @retval The state of SSP, which can be BUSY or DONE
|
||||
*/
|
||||
WorkState SSP_GetWorkState(TSB_SSP_TypeDef * SSPx)
|
||||
{
|
||||
WorkState tmp = DONE;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
/* Check the bit 'BSY'(bit4) of register SSPSR, */
|
||||
/* 1 == busy, 0 == idle or done */
|
||||
if ((SSPx->SR & SSP_BSY_MASK) == SSP_BSY_MASK) {
|
||||
tmp = BUSY;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Rx/Tx FIFO state of the specified SSP channel
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param Direction: the communication direction which will be check.
|
||||
* This parameter can be one of the following values:
|
||||
* SSP_TX
|
||||
SSP_RX
|
||||
* @retval The state of Rx/Tx FIFO,
|
||||
* This parameter can be one of the following values:
|
||||
* SSP_FIFO_EMPTY : FIFO is empty
|
||||
* SSP_FIFO_NORMAL : FIFO is not full and not empty
|
||||
* SSP_FIFO_INVALID : FIFO is invalid state
|
||||
* SSP_FIFO_FULL : FIFO is full
|
||||
*/
|
||||
SSP_FIFOState SSP_GetFIFOState(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction)
|
||||
{
|
||||
uint32_t src = 0U;
|
||||
SSP_FIFOState tgt = SSP_FIFO_EMPTY;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_DIRECTION(Direction));
|
||||
|
||||
src = SSPx->SR;
|
||||
if (Direction == SSP_TX) {
|
||||
src &= SSP_TXFIFO_SR_MASK;
|
||||
switch (src) {
|
||||
case SSP_TXFIFO_FULL:
|
||||
tgt = SSP_FIFO_FULL;
|
||||
break;
|
||||
case SSP_TXFIFO_INVALID:
|
||||
tgt = SSP_FIFO_INVALID;
|
||||
break;
|
||||
case SSP_TXFIFO_NORMAL:
|
||||
tgt = SSP_FIFO_NORMAL;
|
||||
break;
|
||||
case SSP_TXFIFO_EMPTY:
|
||||
tgt = SSP_FIFO_EMPTY;
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
src &= SSP_RXFIFO_SR_MASK;
|
||||
src >>= 2U;
|
||||
switch (src) {
|
||||
case SSP_RXFIFO_FULL:
|
||||
tgt = SSP_FIFO_FULL;
|
||||
break;
|
||||
case SSP_RXFIFO_INVALID:
|
||||
tgt = SSP_FIFO_INVALID;
|
||||
break;
|
||||
case SSP_RXFIFO_NORMAL:
|
||||
tgt = SSP_FIFO_NORMAL;
|
||||
break;
|
||||
case SSP_RXFIFO_EMPTY:
|
||||
tgt = SSP_FIFO_EMPTY;
|
||||
break;
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return tgt;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable interrupt source of the specified SSP channel
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param INTSrc: The interrupt source for SSP to be enable or disable.
|
||||
* To disable all interrupt source,use the parameter:
|
||||
* SSP_INTCFG_NONE
|
||||
* To enable the interrupt one by one, use the "OR" operation with below parameter:
|
||||
* SSP_INTCFG_RX_OVERRUN Receive overrun interrupt
|
||||
* SSP_INTCFG_RX_TIMEOUT Receive timeout interrupt
|
||||
* SSP_INTCFG_RX Receive FIFO interrupt(at least half full)
|
||||
* SSP_INTCFG_TX Transmit FIFO interrupt(at least half empty)
|
||||
* To enable all the 4 interrupt above together, use the parameter:
|
||||
* SSP_INTCFG_ALL
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetINTConfig(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_INT_SRC(IntSrc));
|
||||
|
||||
SSPx->IMSC = IntSrc & SSP_IMSC_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Enable/Disable mask setting for each Interrupt source in the specified SSP channel
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @retval A data with union SSP_INTState type.
|
||||
*/
|
||||
SSP_INTState SSP_GetINTConfig(TSB_SSP_TypeDef * SSPx)
|
||||
{
|
||||
SSP_INTState state = { 0U };
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
state.All = SSPx->IMSC & SSP_IMSC_MASK;
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SSP pre-enable interrupt status of the specified SSP channel.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @retval A data with union SSP_INTState type.
|
||||
*/
|
||||
SSP_INTState SSP_GetPreEnableINTState(TSB_SSP_TypeDef * SSPx)
|
||||
{
|
||||
SSP_INTState state = { 0U };
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
state.All = SSPx->RIS & SSP_RIS_MASK;
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SSP post-enable interrupt status of the specified SSP channel.( after masked)
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @retval A data with union SSP_INTState type.
|
||||
*/
|
||||
SSP_INTState SSP_GetPostEnableINTState(TSB_SSP_TypeDef * SSPx)
|
||||
{
|
||||
SSP_INTState state = { 0U };
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
|
||||
state.All = SSPx->MIS & SSP_MIS_MASK;
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt flag of specified SSP channel by writing '1' to correspond bit.
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param INTSrc: The interrupt source to be cleared.
|
||||
* This parameter can be one of the following values:
|
||||
* SSP_INTCFG_RX_OVERRUN Receive overrun interrupt
|
||||
* SSP_INTCFG_RX_TIMEOUT Receive timeout interrupt
|
||||
* SSP_INTCFG_ALL All interrupt flags above
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_ClearINTFlag(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_CLEAR_INT_SRC(IntSrc));
|
||||
|
||||
if (IntSrc == SSP_INTCFG_RX_OVERRUN) {
|
||||
tmp = 1U;
|
||||
} else if (IntSrc == SSP_INTCFG_RX_TIMEOUT) {
|
||||
tmp = 2U;
|
||||
} else {
|
||||
tmp = 3U;
|
||||
}
|
||||
|
||||
SSPx->ICR = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the Rx/Tx DMA FIFO of the specified SSP channel
|
||||
* @param SSPx: Select the SSP channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_SSP0, TSB_SSP1, TSB_SSP2
|
||||
* @param Direction: The Direction of SSP,
|
||||
* This parameter can be one of the following values:
|
||||
* SSP_RX,
|
||||
* SSP_TX
|
||||
* @param NewState: New state of DMA FIFO Rx/Tx.
|
||||
* This parameter can be one of the following values:
|
||||
* ENABLE,
|
||||
* DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void SSP_SetDMACtrl(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
uint32_t tmpDMASet = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SSP_PERIPH(SSPx));
|
||||
assert_param(IS_SSP_DIRECTION(Direction));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (Direction == SSP_RX) {
|
||||
/* Bit0 is for Rx */
|
||||
tmp = 1U;
|
||||
} else {
|
||||
/* Bit1 is for Tx */
|
||||
tmp = 2U;
|
||||
}
|
||||
|
||||
/* Read, then clear all bits except bit0 and bit1 */
|
||||
tmpDMASet = SSPx->DMACR & SSP_DMA_MASK;
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
tmpDMASet |= tmp;
|
||||
} else {
|
||||
/* Disable, clear bit */
|
||||
tmpDMASet &= ((uint32_t) ~tmp & SSP_DMA_MASK);
|
||||
}
|
||||
|
||||
SSPx->DMACR = tmpDMASet;
|
||||
}
|
||||
|
||||
/** @} */
|
||||
/* End of group SSP_Exported_Functions */
|
||||
|
||||
/** @} */
|
||||
/* End of group SSP */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#endif /* defined(__TMPM46B_SSP_H) */
|
||||
|
|
@ -0,0 +1,547 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file tmpm46b_tmrb.c
|
||||
* @brief This file provides API functions for TMRB driver.
|
||||
* @version V2.0.2.1
|
||||
* @date 2015/02/27
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tmpm46b_tmrb.h"
|
||||
|
||||
#if defined(__TMPM46B_TMRB_H)
|
||||
/** @addtogroup TX04_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TMRB
|
||||
* @brief TMRB driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TMRB_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EN_TBEN_SET ((uint32_t)0x00000080)
|
||||
#define EN_TBEN_CLEAR ((uint32_t)0xFFFFFF7F)
|
||||
|
||||
#define MPT_TIMER_MODE ((uint32_t)0xFFFFFFFE)
|
||||
|
||||
#define CR_I2TB_SET ((uint32_t)0x00000008)
|
||||
#define CR_I2TB_CLEAR ((uint32_t)0xFFFFFFF7)
|
||||
#define CR_TBSYNC_SET ((uint32_t)0x00000020)
|
||||
#define CR_TBSYNC_CLEAR ((uint32_t)0xFFFFFFDF)
|
||||
#define CR_TBWBF_SET ((uint32_t)0x00000080)
|
||||
#define CR_TBWBF_CLEAR ((uint32_t)0xFFFFFF7F)
|
||||
#define CR_CSSEL_SET ((uint32_t)0x00000001)
|
||||
#define CR_CSSEL_CLEAR ((uint32_t)0xFFFFFFFE)
|
||||
#define CR_TRGSEL_CLEAR ((uint32_t)0xFFFFFFBD)
|
||||
|
||||
#define MOD_CLK_CLE_CLEAR_MPT ((uint32_t)0xFFFFFFF8)
|
||||
#define MOD_CLK_CLE_CLEAR_TMRB ((uint32_t)0xFFFFFFF0)
|
||||
#define MOD_TBCPM_CLEAR_MPT ((uint32_t)0xFFFFFFE7)
|
||||
#define MOD_TBCPM_CLEAR_TMRB ((uint32_t)0xFFFFF8FF)
|
||||
#define MOD_TBCP_CLEAR_MPT ((uint32_t)0xFFFFFFDF)
|
||||
#define MOD_TBCP_CLEAR_TMRB ((uint32_t)0xFFFFFFBF)
|
||||
#define MOD_TBRSWR_CLEAR ((uint32_t)0xFFFFFFBF)
|
||||
|
||||
#define TB_ST_MASK ((uint32_t)0x00000007)
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB_Private_Defines */
|
||||
|
||||
/** @defgroup TMRB_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB_Private_FunctionPrototypes */
|
||||
|
||||
/** @defgroup TMRB_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB_Private_Functions */
|
||||
|
||||
/** @defgroup TMRB_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified TMRB channel.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_Enable(TSB_TB_TypeDef * TBx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
/* Clear MPTxEN<MTMODE> to Timer mode */
|
||||
if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
|
||||
TBx->EN &= MPT_TIMER_MODE;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
/* Set TBxEN<TBEN> to enable TBx */
|
||||
TBx->EN |= EN_TBEN_SET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the specified TMRB channel.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_Disable(TSB_TB_TypeDef * TBx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
/* Clear TBxEN<TBEN> to disable TBx */
|
||||
TBx->EN &= EN_TBEN_CLEAR;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Start or stop counter of the specified TMRB channel.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param Cmd: The command for the counter.
|
||||
* This parameter can be TMRB_RUN or TMRB_STOP.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_CMD(Cmd));
|
||||
|
||||
/* Write command into RUN register */
|
||||
TBx->RUN = Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the specified TMRB channel.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param InitStruct: The structure containing basic TMRB configuration.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_POINTER_NOT_NULL(InitStruct));
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_MODE(InitStruct->Mode));
|
||||
assert_param(IS_TMRB_VALUE(InitStruct->TrailingTiming));
|
||||
assert_param(IS_TMRB_VALUE(InitStruct->LeadingTiming));
|
||||
assert_param(IS_VALID_LEADING(InitStruct->LeadingTiming, InitStruct->TrailingTiming));
|
||||
tmp = TBx->MOD;
|
||||
|
||||
if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
|
||||
assert_param(IS_MPT_CLK_DIV(InitStruct->ClkDiv));
|
||||
assert_param(IS_MPT_UC_CTRL(InitStruct->UpCntCtrl));
|
||||
tmp &= MOD_CLK_CLE_CLEAR_MPT;
|
||||
} else {
|
||||
assert_param(IS_TMRB_CLK_DIV(InitStruct->ClkDiv));
|
||||
assert_param(IS_TMRB_UC_CTRL(InitStruct->UpCntCtrl));
|
||||
tmp &= MOD_CLK_CLE_CLEAR_TMRB;
|
||||
}
|
||||
|
||||
if (InitStruct->Mode != 0U) {
|
||||
/* Use internal clock, set the prescaler */
|
||||
tmp |= InitStruct->ClkDiv;
|
||||
} else {
|
||||
/* Use external clock */
|
||||
/* Do nothing */
|
||||
}
|
||||
/* Set up-counter running mode */
|
||||
tmp |= InitStruct->UpCntCtrl;
|
||||
TBx->MOD = tmp;
|
||||
|
||||
/* Write leading-timing into RG0 */
|
||||
TBx->RG0 = InitStruct->LeadingTiming;
|
||||
|
||||
/* Write trailing-timing into RG1 */
|
||||
TBx->RG1 = InitStruct->TrailingTiming;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the capture timing and up-counter clearing timing.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param CaptureTiming: Specify TMRB capture timing.
|
||||
* This parameter can be one of the following values:
|
||||
* TBx = TSB_TB_MPT0 or TSB_TB_MPT1 or TSB_TB_MPT2 or TSB_TB_MPT3:
|
||||
* MPT_DISABLE_CAPTURE, MPT_CAPTURE_IN_RISING, MPT_CAPTURE_IN_RISING_FALLING.
|
||||
* TBx = TSB_TB0 to TSB_TB3:
|
||||
* TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_TBIN0_RISING_FALLING,
|
||||
* TMRB_CAPTURE_TBFF0_EDGE.
|
||||
* TBx = TSB_TB4 to TSB_TB7:
|
||||
* TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_TBIN0_TBIN1_RISING,
|
||||
* TMRB_CAPTURE_TBIN0_RISING_FALLING, TMRB_CAPTURE_TBFF0_EDGE,
|
||||
* TMRB_CLEAR_TBIN1_RISING, TMRB_CAPTURE_TBIN0_RISING_CLEAR_TBIN1_RISING.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
|
||||
/* Configure capture timing */
|
||||
if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
|
||||
assert_param(IS_MPT_CAPTURE_TIMING(CaptureTiming));
|
||||
tmp = TBx->MOD & MOD_TBCPM_CLEAR_MPT;
|
||||
} else {
|
||||
if ((TBx == TSB_TB0) || (TBx == TSB_TB1) || (TBx == TSB_TB2) || (TBx == TSB_TB3)) {
|
||||
assert_param(IS_TMRB_CAPTURE_TIMING_NONE_TBIN1(CaptureTiming));
|
||||
} else {
|
||||
assert_param(IS_TMRB_CAPTURE_TIMING_ALL(CaptureTiming));
|
||||
}
|
||||
tmp = TBx->MOD & MOD_TBCPM_CLEAR_TMRB;
|
||||
}
|
||||
tmp |= CaptureTiming;
|
||||
TBx->MOD = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the flip-flop function.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param FFStruct: The structure containing TMRB flip-flop configuration
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_POINTER_NOT_NULL(FFStruct));
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_FLIPFLOP_CTRL(FFStruct->FlipflopCtrl));
|
||||
assert_param(IS_TMRB_FLIPFLOP_TRG(FFStruct->FlipflopReverseTrg));
|
||||
|
||||
/* Configure the flip-flop function of TBx */
|
||||
TBx->FFCR = (FFStruct->FlipflopCtrl | FFStruct->FlipflopReverseTrg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate what causes the interrupt.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @retval The interrupt factor of TBx.
|
||||
*/
|
||||
TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx)
|
||||
{
|
||||
TMRB_INTFactor retval;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
|
||||
retval.All = 0U;
|
||||
retval.All = TBx->ST & TB_ST_MASK;
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Mask some TMRB interrupt.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param INTMask: Select the mask of TMRB interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* TMRB_NO_INT_MASK, TMRB_MASK_MATCH_LEADING_INT, TMRB_MASK_MATCH_TRAILING_INT,
|
||||
* TMRB_MASK_OVERFLOW_INT, TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT,
|
||||
* TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_OVERFLOW_INT,
|
||||
* TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT,
|
||||
* TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_INT_MASK(INTMask));
|
||||
|
||||
/* Mask the specified interrupt */
|
||||
TBx->IM = INTMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change leadingtiming value of TBx.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param LeadingTiming: New leadingtiming value, max 0xFFFF.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_VALUE(LeadingTiming));
|
||||
assert_param(IS_VALID_LEADING(LeadingTiming, TBx->RG1));
|
||||
|
||||
/* Write leadingtiming into RG0 */
|
||||
TBx->RG0 = LeadingTiming;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change trailingtiming value of TBx.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param TrailingTiming: New trailingtiming value, max 0xFFFF.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_VALUE(TrailingTiming));
|
||||
assert_param(IS_VALID_LEADING(TBx->RG0, TrailingTiming));
|
||||
|
||||
/* Write trailingtiming into RG1 */
|
||||
TBx->RG1 = TrailingTiming;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get up-counter value of TBx.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @retval Up-counter value of TBx
|
||||
*/
|
||||
uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
|
||||
/* Return up-counter value */
|
||||
return (uint16_t) TBx->UC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TMRB capture value of TBx.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param CapReg: Select the capture register to read.
|
||||
* This parameter can be: TMRB_CAPTURE_0 or TMRB_CAPTURE_1.
|
||||
* @retval Capture value of TBx
|
||||
*/
|
||||
uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_CAPTURE_REG(CapReg));
|
||||
|
||||
return CapReg ? (uint16_t) TBx->CP1 : (uint16_t) TBx->CP0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Capture counter by software and take them into capture register 0.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
|
||||
/* Set software capture */
|
||||
|
||||
if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
|
||||
TBx->MOD &= MOD_TBCP_CLEAR_MPT;
|
||||
} else {
|
||||
TBx->MOD &= MOD_TBCP_CLEAR_TMRB;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable TMRB when system is in idle mode.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param NewState: New state of TMRB in system idle mode.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetIdleMode(TSB_TB_TypeDef * TBx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* Set TBxCR<I2TB> to enable TBx in system idle mode */
|
||||
TBx->CR |= CR_I2TB_SET;
|
||||
} else {
|
||||
/* Clear TBxCR<I2TB> to disable TBx in system idle mode */
|
||||
TBx->CR &= CR_I2TB_CLEAR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the synchronous mode of specified TMRB channel.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB5, TSB_TB6, TSB_TB7.
|
||||
* @param NewState: New state of TBx synchronous mode.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_SYNC_PERIPH(TBx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* Set TBxCR<TBSYNC> to make TBx running in synchronous mode */
|
||||
TBx->CR |= CR_TBSYNC_SET;
|
||||
} else {
|
||||
/* Clear TBxCR<TBSYNC> to make TBx running in individual mode */
|
||||
TBx->CR &= CR_TBSYNC_CLEAR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable double buffer of TBx and set the timing to write to timer register.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param NewState: New state of TBx double buffer.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @param WriteRegMode: Timing to write to timer register.
|
||||
* This parameter can be TMRB_WRITE_REG_SEPARATE or TMRB_WRITE_REG_SIMULTANEOUS.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t WriteRegMode)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_TMRB_WRITE_REG_MODE(WriteRegMode));
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* Set TBxCR<TBWBF> to enable TBx double buffer */
|
||||
TBx->CR |= CR_TBWBF_SET;
|
||||
if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
|
||||
/* Write timer register timing */
|
||||
tmp = TBx->MOD & MOD_TBRSWR_CLEAR;
|
||||
tmp |= (uint32_t) WriteRegMode;
|
||||
TBx->MOD = tmp;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
} else {
|
||||
/* Clear TBxCR<TBWBF> to disable TBx double buffer */
|
||||
TBx->CR &= CR_TBWBF_CLEAR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable external trigger to start count and set the active edge.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param NewState: New state of external trigger.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @param TrgMode: Active edge of the external trigger signal.
|
||||
* This parameter can be TMRB_TRG_EDGE_RISING or TMRB_TRG_EDGE_FALLING.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_TMRB_TRG_EDGE(TrgMode));
|
||||
|
||||
if (NewState == ENABLE) {
|
||||
/* Set TBxCR<CSSEL> to choose external trigger */
|
||||
TBx->CR |= CR_CSSEL_SET;
|
||||
} else {
|
||||
/* Clear TBxCR<CSSEL> to choose software start */
|
||||
TBx->CR &= CR_CSSEL_CLEAR;
|
||||
}
|
||||
|
||||
/* external trigger selection */
|
||||
tmp = TBx->CR & CR_TRGSEL_CLEAR;
|
||||
tmp |= (uint32_t) TrgMode;
|
||||
TBx->CR = tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable clock operation during debug HALT.
|
||||
* @param TBx: Select the TMRB channel.
|
||||
* This parameter can be one of the following values:
|
||||
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
|
||||
* TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
|
||||
* @param ClkState: Timer state in HALT mode.
|
||||
* This parameter can be TMRB_RUNNING_IN_CORE_HALT or TMRB_STOP_IN_CORE_HALT.
|
||||
* @retval None
|
||||
*/
|
||||
void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TMRB_ALL_PERIPH(TBx));
|
||||
assert_param(IS_TMRB_CLK_IN_CORE_HALT(ClkState));
|
||||
|
||||
if (ClkState == TMRB_STOP_IN_CORE_HALT) {
|
||||
/* Set TBEN<TBHALT> */
|
||||
TBx->EN |= (uint32_t) TMRB_STOP_IN_CORE_HALT;
|
||||
} else {
|
||||
/* Clear TBEN<TBHALT> */
|
||||
TBx->EN &= ~(uint32_t) TMRB_STOP_IN_CORE_HALT;
|
||||
}
|
||||
}
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB_Exported_Functions */
|
||||
|
||||
/** @} */
|
||||
/* End of group TMRB */
|
||||
|
||||
/** @} */
|
||||
/* End of group TX04_Periph_Driver */
|
||||
|
||||
#endif /* defined(__TMPM46B_TMRB_H) */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,119 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
SERIAL_0 = 0,
|
||||
SERIAL_1,
|
||||
SERIAL_2,
|
||||
SERIAL_3,
|
||||
SERIAL_4,
|
||||
SERIAL_5,
|
||||
INVALID_SERIAL = (int)NC
|
||||
} UARTName;
|
||||
|
||||
typedef enum {
|
||||
ADC_A0,
|
||||
ADC_A1,
|
||||
ADC_A2,
|
||||
ADC_A3,
|
||||
ADC_A4,
|
||||
ADC_A5,
|
||||
ADC_A6,
|
||||
ADC_A7,
|
||||
INVALID_ADC = (int)NC
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = 0,
|
||||
SPI_1,
|
||||
SPI_2,
|
||||
INVALID_SPI = (int)NC
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = 0,
|
||||
I2C_1,
|
||||
I2C_2,
|
||||
INVALID_I2C = (int)NC
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
PWM_0 = 0,
|
||||
PWM_1,
|
||||
PWM_2,
|
||||
PWM_3,
|
||||
PWM_4,
|
||||
PWM_5,
|
||||
INVALID_PWM = (int)NC
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
GPIO_IRQ_0 = 1,
|
||||
GPIO_IRQ_1 = 2,
|
||||
GPIO_IRQ_2 = 7,
|
||||
GPIO_IRQ_3 = 8,
|
||||
GPIO_IRQ_4 = 13,
|
||||
GPIO_IRQ_5 = 14,
|
||||
GPIO_IRQ_6 = 15,
|
||||
INVALID_GPIO_IRQ = (int)NC
|
||||
} GPIO_IRQName;
|
||||
|
||||
#define STDIO_UART_TX PE5
|
||||
#define STDIO_UART_RX PE6
|
||||
#define STDIO_UART SERIAL_1
|
||||
|
||||
#define MBED_SPI0 PK3, PK2, PK4, PK1
|
||||
#define MBED_SPI1 PF4, PF5, PF3, PF6
|
||||
#define MBED_SPI2 PD2, PD1, PD3, PD0
|
||||
|
||||
#define MBED_UART0 PE2, PE1
|
||||
#define MBED_UART1 PE5, PE6
|
||||
#define MBED_UART2 PL2, PL1
|
||||
#define MBED_UART3 PB0, PB1
|
||||
#define MBED_UART4 PF1, PF2
|
||||
#define MBED_UART5 PA6, PA5
|
||||
#define MBED_UARTUSB USBTX, USBRX
|
||||
|
||||
#define MBED_I2C0 PK2, PK3
|
||||
#define MBED_I2C1 PF7, PF6
|
||||
#define MBED_I2C2 PH0, PH1
|
||||
|
||||
#define MBED_ANALOGIN0 A0
|
||||
#define MBED_ANALOGIN1 A1
|
||||
#define MBED_ANALOGIN2 A2
|
||||
#define MBED_ANALOGIN3 A3
|
||||
#define MBED_ANALOGIN4 A4
|
||||
#define MBED_ANALOGIN5 A5
|
||||
|
||||
#define MBED_PWMOUT0 PE4
|
||||
#define MBED_PWMOUT1 PB6
|
||||
#define MBED_PWMOUT2 PH1
|
||||
#define MBED_PWMOUT3 PH0
|
||||
#define MBED_PWMOUT4 PA7
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF)
|
||||
#define PIN_POS(X) ((uint32_t)(X) & 0x7)
|
||||
|
||||
// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
|
||||
#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0))
|
||||
#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16)
|
||||
#define PIN_DIR(X) ((X) & 0xffff)
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT,
|
||||
PIN_INOUT
|
||||
} PinDirection;
|
||||
|
||||
typedef enum {
|
||||
// TMPM46B Pin Names
|
||||
PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
|
||||
PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
|
||||
PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5,
|
||||
PD0 = 3 << 3, PD1, PD2, PD3, PD4,
|
||||
PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
|
||||
PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
|
||||
PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7,
|
||||
PH0 = 7 << 3, PH1, PH2, PH3,
|
||||
PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7,
|
||||
PK0 = 9 << 3, PK1, PK2, PK3, PK4,
|
||||
PL0 = 10 << 3, PL1, PL2, PL3,
|
||||
|
||||
// Other mbed Pin Names
|
||||
LED1 = PF4,
|
||||
LED2 = PF5,
|
||||
LED3 = PF6,
|
||||
LED4 = PF7,
|
||||
|
||||
// External data bus Pin Names
|
||||
D0 = PL1,
|
||||
D1 = PL2,
|
||||
D2 = PC0,
|
||||
D3 = PE3,
|
||||
D4 = PC1,
|
||||
D5 = PE4,
|
||||
D6 = PH1,
|
||||
D7 = PC2,
|
||||
D8 = PC3,
|
||||
D9 = PH0,
|
||||
D10 = PD0,
|
||||
D11 = PD2,
|
||||
D12 = PD1,
|
||||
D13 = PD3,
|
||||
D14 = PK2,
|
||||
D15 = PK3,
|
||||
|
||||
// Analogue out pins
|
||||
A0 = PJ2,
|
||||
A1 = PJ3,
|
||||
A2 = PJ4,
|
||||
A3 = PJ5,
|
||||
A4 = PJ6,
|
||||
A5 = PJ7,
|
||||
|
||||
// DAP_UART
|
||||
USBTX = PE5,
|
||||
USBRX = PE6,
|
||||
MBEDIF_TXD = USBTX,
|
||||
MBEDIF_RXD = USBRX,
|
||||
|
||||
MBED_CONF_APP_UART0_TX = PE2,
|
||||
MBED_CONF_APP_UART0_RX = PE1,
|
||||
|
||||
// Switches
|
||||
SW1 = PF0,
|
||||
SW2 = PF1,
|
||||
SW3 = PF2,
|
||||
SW4 = PF3,
|
||||
|
||||
// I2C pins
|
||||
SDA = PK2,
|
||||
SCL = PK3,
|
||||
I2C_SDA = SDA,
|
||||
I2C_SCL = SCL,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF,
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullUp = 0,
|
||||
PullDown,
|
||||
PullNone,
|
||||
OpenDrain,
|
||||
PullDefault = PullDown
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PORTNAMES_H
|
||||
#define MBED_PORTNAMES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PortA = 0,
|
||||
PortB,
|
||||
PortC,
|
||||
PortD,
|
||||
PortE,
|
||||
PortF,
|
||||
PortG,
|
||||
PortH,
|
||||
PortJ,
|
||||
PortK,
|
||||
PortL
|
||||
} PortName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "analogin_api.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "pinmap.h"
|
||||
#include "mbed_wait_api.h"
|
||||
|
||||
static uint8_t adc_reset_init = 0; // Is ADC Reset happened yet?
|
||||
#define ADC_12BIT_RANGE 0xFFF
|
||||
|
||||
static const PinMap PinMap_ADC[] = {
|
||||
{PJ0, ADC_A0, PIN_DATA(2, 0)},
|
||||
{PJ1, ADC_A1, PIN_DATA(2, 0)},
|
||||
{PJ2, ADC_A2, PIN_DATA(2, 0)},
|
||||
{PJ3, ADC_A3, PIN_DATA(2, 0)},
|
||||
{PJ4, ADC_A4, PIN_DATA(2, 0)},
|
||||
{PJ5, ADC_A5, PIN_DATA(2, 0)},
|
||||
{PJ6, ADC_A6, PIN_DATA(2, 0)},
|
||||
{PJ7, ADC_A7, PIN_DATA(2, 0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
void analogin_init(analogin_t *obj, PinName pin)
|
||||
{
|
||||
// Check that pin belong to ADC module
|
||||
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
|
||||
MBED_ASSERT(obj->adc != (ADCName)NC);
|
||||
|
||||
// Enable clock supply
|
||||
CG_SetADCClkSupply(ENABLE);
|
||||
// Set pin function as ADC
|
||||
pinmap_pinout(pin, PinMap_ADC);
|
||||
if (!adc_reset_init) {
|
||||
// Software reset ADC
|
||||
ADC_SWReset(TSB_AD);
|
||||
adc_reset_init = 1;
|
||||
}
|
||||
// Set sample hold time and pre-scale clock
|
||||
ADC_SetClk(TSB_AD, ADC_CONVERSION_CLK_80, ADC_FC_DIVIDE_LEVEL_8);
|
||||
// Set input channel
|
||||
ADC_SetInputChannel(TSB_AD, (ADC_AINx)obj->adc);
|
||||
// Turn VREF on
|
||||
ADC_SetVref(TSB_AD, ENABLE);
|
||||
// Use fixed-channel single conversion mode
|
||||
ADC_SetRepeatMode(TSB_AD, DISABLE);
|
||||
ADC_SetScanMode(TSB_AD, DISABLE);
|
||||
}
|
||||
|
||||
uint16_t analogin_read_u16(analogin_t *obj)
|
||||
{
|
||||
ADC_Result ret = {0x00};
|
||||
|
||||
// Assert that ADC channel is valid
|
||||
MBED_ASSERT(obj->adc != (ADCName)NC);
|
||||
wait_us(300); // Wait for register to update with convert value
|
||||
|
||||
// Set input channel
|
||||
ADC_SetInputChannel(TSB_AD, (ADC_AINx)obj->adc);
|
||||
// Enable Vref
|
||||
ADC_SetVref(TSB_AD, ENABLE);
|
||||
// Wait at least 3us to ensure the voltage is stable
|
||||
wait_us(10U);
|
||||
// Start ADC conversion
|
||||
ADC_Start(TSB_AD);
|
||||
// Wait until AD conversion complete
|
||||
while(ADC_GetConvertState(TSB_AD).Bit.NormalComplete != 1) {
|
||||
// Do nothing
|
||||
}
|
||||
wait_us(30);
|
||||
// Convert result
|
||||
ret = ADC_GetConvertResult(TSB_AD, (ADC_REGx)obj->adc);
|
||||
// Disable Vref to go into standby mode
|
||||
ADC_SetVref(TSB_AD, DISABLE);
|
||||
return (uint16_t)ret.Bit.ADResult;
|
||||
}
|
||||
|
||||
float analogin_read(analogin_t *obj)
|
||||
{
|
||||
uint16_t value = analogin_read_u16(obj);
|
||||
return (float)(value * (1.0f / (float)ADC_12BIT_RANGE));
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_ID_LENGTH 32
|
||||
|
||||
#include "objects.h"
|
||||
#include <stddef.h>
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,418 @@
|
|||
;/**
|
||||
; *******************************************************************************
|
||||
; * @file startup_TMPM46B.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for the
|
||||
; * TOSHIBA 'TMPM46B' Device Series
|
||||
; * @version V2.0.2.4
|
||||
; * @date 2015/03/31
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
; *
|
||||
; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
; *******************************************************************************
|
||||
; */
|
||||
|
||||
__initial_sp EQU 0x20080000
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD INT0_IRQHandler ; 0: Interrupt pin 0
|
||||
DCD INT1_IRQHandler ; 1: Interrupt pin 1
|
||||
DCD INT2_IRQHandler ; 2: Interrupt pin 2
|
||||
DCD INT3_IRQHandler ; 3: Interrupt pin 3
|
||||
DCD INT4_IRQHandler ; 4: Interrupt pin 4
|
||||
DCD INT5_IRQHandler ; 5: Interrupt pin 5
|
||||
DCD INT6_IRQHandler ; 6: Interrupt pin 6
|
||||
DCD INT7_IRQHandler ; 7: Interrupt pin 7
|
||||
DCD INT8_IRQHandler ; 8: Interrupt pin 8
|
||||
DCD INT9_IRQHandler ; 9: Interrupt pin 9
|
||||
DCD INTA_IRQHandler ; 10: Interrupt pin A
|
||||
DCD INTB_IRQHandler ; 11: Interrupt pin B
|
||||
DCD INTC_IRQHandler ; 12: Interrupt pin C
|
||||
DCD INTD_IRQHandler ; 13: Interrupt pin D
|
||||
DCD INTE_IRQHandler ; 14: Interrupt pin E
|
||||
DCD INTF_IRQHandler ; 15: Interrupt pin F
|
||||
DCD INTRX0_IRQHandler ; 16: Serial0 reception interrupt
|
||||
DCD INTTX0_IRQHandler ; 17: Serial0 transmission interrupt
|
||||
DCD INTRX1_IRQHandler ; 18: Serial1 reception interrupt
|
||||
DCD INTTX1_IRQHandler ; 19: Serial1 transmission interrupt
|
||||
DCD INTRX2_IRQHandler ; 20: Serial2 reception interrupt
|
||||
DCD INTTX2_IRQHandler ; 21: Serial2 transmission interrupt
|
||||
DCD INTRX3_IRQHandler ; 22: Serial3 reception interrupt
|
||||
DCD INTTX3_IRQHandler ; 23: Serial3 transmission interrupt
|
||||
DCD INTUART0_IRQHandler ; 24: Full UART0 transmission and reception interrupt
|
||||
DCD INTUART1_IRQHandler ; 25: Full UART1 transmission and reception interrupt
|
||||
DCD INTI2C0_IRQHandler ; 26: I2C0 transmission and reception interrupt
|
||||
DCD INTI2C1_IRQHandler ; 27: I2C1 transmission and reception interrupt
|
||||
DCD INTI2C2_IRQHandler ; 28: I2C2 transmission and reception interrupt
|
||||
DCD INTSSP0_IRQHandler ; 29: SSP(SPI) Serial interface 0 interrupt
|
||||
DCD INTSSP1_IRQHandler ; 30: SSP(SPI) Serial interface 1 interrupt
|
||||
DCD INTSSP2_IRQHandler ; 31: SSP(SPI) Serial interface 2 interrupt
|
||||
DCD INTADHP_IRQHandler ; 32: High Priority AD conversion interrupt
|
||||
DCD INTADM0_IRQHandler ; 33: AD conversion monitor interrupt 0
|
||||
DCD INTADM1_IRQHandler ; 34: AD conversion monitor interrupt 1
|
||||
DCD INTAD_IRQHandler ; 35: AD conversion interrupt
|
||||
DCD INTAES_IRQHandler ; 36: AES completion interrupt
|
||||
DCD INTSHA_IRQHandler ; 37: SHA completion interrupt
|
||||
DCD INTMLA_IRQHandler ; 38: MLA completion interrupt
|
||||
DCD INTESG_IRQHandler ; 39: ESG completion interrupt
|
||||
DCD INTSNFCSEQ_IRQHandler ; 40: SNFC command sequence end interrupt
|
||||
DCD INTSNFCPRTAE_IRQHandler ; 41: SNFC page lead RAM transfer end interrupt
|
||||
DCD INTSNFCPRTCE_IRQHandler ; 42: SNFC decode data RAM transmission end interrupt
|
||||
DCD INTSNFCFAIL_IRQHandler ; 43: SNFC decode fail interrupt
|
||||
DCD 0 ; 44: Reserved1
|
||||
DCD 0 ; 45: Reserved2
|
||||
DCD 0 ; 46: Reserved3
|
||||
DCD INTMTEMG0_IRQHandler ; 47: MPT0 EMG interrupt
|
||||
DCD INTMTPTB00_IRQHandler ; 48: MPT0 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTPTB01_IRQHandler ; 49: MPT0 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP00_IRQHandler ; 50: MPT0 input capture0 interrupt
|
||||
DCD INTMTCAP01_IRQHandler ; 51: MPT0 input capture1 interrupt
|
||||
DCD INTMTEMG1_IRQHandler ; 52: MPT1 EMG interrupt
|
||||
DCD INTMTPTB10_IRQHandler ; 53: MPT1 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTPTB11_IRQHandler ; 54: MPT1 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP10_IRQHandler ; 55: MPT1 input capture0 interrupt
|
||||
DCD INTMTCAP11_IRQHandler ; 56: MPT1 input capture1 interrupt
|
||||
DCD INTMTEMG2_IRQHandler ; 57: MPT2 EMG interrupt
|
||||
DCD INTMTPTB20_IRQHandler ; 58: MPT2 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTTTB21_IRQHandler ; 59: MPT2 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP20_IRQHandler ; 60: MPT2 input capture0 interrupt
|
||||
DCD INTMTCAP21_IRQHandler ; 61: MPT2 input capture1 interrupt
|
||||
DCD INTMTEMG3_IRQHandler ; 62: MPT3 EMG interrupt
|
||||
DCD INTMTPTB30_IRQHandler ; 63: MPT3 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTTTB31_IRQHandler ; 64: MPT3 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP30_IRQHandler ; 65: MPT3 input capture0 interrupt
|
||||
DCD INTMTCAP31_IRQHandler ; 66: MPT3 input capture1 interrupt
|
||||
DCD INTTB0_IRQHandler ; 67: TMRB0 compare match detection interrupt
|
||||
DCD INTCAP00_IRQHandler ; 68: TMRB0 input capture 0 interrupt
|
||||
DCD INTCAP01_IRQHandler ; 69: TMRB0 input capture 1 interrupt
|
||||
DCD INTTB1_IRQHandler ; 70: TMRB1 compare match detection interrupt
|
||||
DCD INTCAP10_IRQHandler ; 71: TMRB1 input capture 0 interrupt
|
||||
DCD INTCAP11_IRQHandler ; 72: TMRB1 input capture 1 interrupt
|
||||
DCD INTTB2_IRQHandler ; 73: TMRB2 compare match detection interrupt
|
||||
DCD INTCAP20_IRQHandler ; 74: TMRB2 input capture 0 interrupt
|
||||
DCD INTCAP21_IRQHandler ; 75: TMRB2 input capture 1 interrupt
|
||||
DCD INTTB3_IRQHandler ; 76: TMRB3 compare match detection interrupt
|
||||
DCD INTCAP30_IRQHandler ; 77: TMRB3 input capture 0 interrupt
|
||||
DCD INTCAP31_IRQHandler ; 78: TMRB3 input capture 1 interrupt
|
||||
DCD INTTB4_IRQHandler ; 79: TMRB4 compare match detection interrupt
|
||||
DCD INTCAP40_IRQHandler ; 80: TMRB4 input capture 0 interrupt
|
||||
DCD INTCAP41_IRQHandler ; 81: TMRB4 input capture 1 interrupt
|
||||
DCD INTTB5_IRQHandler ; 82: TMRB5 compare match detection interrupt
|
||||
DCD INTCAP50_IRQHandler ; 83: TMRB5 input capture 0 interrupt
|
||||
DCD INTCAP51_IRQHandler ; 84: TMRB5 input capture 1 interrupt
|
||||
DCD INTTB6_IRQHandler ; 85: TMRB6 compare match detection interrupt
|
||||
DCD INTCAP60_IRQHandler ; 86: TMRB6 input capture 0 interrupt
|
||||
DCD INTCAP61_IRQHandler ; 87: TMRB6 input capture 1 interrupt
|
||||
DCD INTTB7_IRQHandler ; 88: TMRB7 compare match detection interrupt
|
||||
DCD INTCAP70_IRQHandler ; 89: TMRB7 input capture 0 interrupt
|
||||
DCD INTCAP71_IRQHandler ; 90: TMRB7 input capture 1 interrupt
|
||||
DCD INTRTC_IRQHandler ; 91: Real time clock interrupt
|
||||
DCD INTDMAA_IRQHandler ; 92: DMAC unitA transmission completion interrupt(ch4-31)
|
||||
DCD INTDMAB_IRQHandler ; 93: DMAC unitB transmission completion interrupt(ch24-31)
|
||||
DCD INTDMAC_IRQHandler ; 94: DMAC unitC transmission completion interrupt(ch12-31)
|
||||
DCD INTDMACTC8_IRQHandler ; 95: DMAC unitC transmission completion interrupt(ch8)
|
||||
DCD INTDMACTC9_IRQHandler ; 96: DMAC unitC transmission completion interrupt(ch9)
|
||||
DCD INTDMACTC10_IRQHandler ; 97: DMAC unitC transmission completion interrupt(ch10)
|
||||
DCD INTDMACTC11_IRQHandler ; 98: DMAC unitC transmission completion interrupt(ch11)
|
||||
DCD INTDMAAERR_IRQHandler ; 99: DMAC transmission error interrupt(unitA)
|
||||
DCD INTDMABERR_IRQHandler ; 100: DMAC transmission error interrupt(unitB)
|
||||
DCD INTDMACERR_IRQHandler ; 101: DMAC transmission error interrupt(unitC)
|
||||
DCD INTFLRDY_IRQHandler ; 102: Flash Ready interrupt
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT INT0_IRQHandler [WEAK]
|
||||
EXPORT INT1_IRQHandler [WEAK]
|
||||
EXPORT INT2_IRQHandler [WEAK]
|
||||
EXPORT INT3_IRQHandler [WEAK]
|
||||
EXPORT INT4_IRQHandler [WEAK]
|
||||
EXPORT INT5_IRQHandler [WEAK]
|
||||
EXPORT INT6_IRQHandler [WEAK]
|
||||
EXPORT INT7_IRQHandler [WEAK]
|
||||
EXPORT INT8_IRQHandler [WEAK]
|
||||
EXPORT INT9_IRQHandler [WEAK]
|
||||
EXPORT INTA_IRQHandler [WEAK]
|
||||
EXPORT INTB_IRQHandler [WEAK]
|
||||
EXPORT INTC_IRQHandler [WEAK]
|
||||
EXPORT INTD_IRQHandler [WEAK]
|
||||
EXPORT INTE_IRQHandler [WEAK]
|
||||
EXPORT INTF_IRQHandler [WEAK]
|
||||
EXPORT INTRX0_IRQHandler [WEAK]
|
||||
EXPORT INTTX0_IRQHandler [WEAK]
|
||||
EXPORT INTRX1_IRQHandler [WEAK]
|
||||
EXPORT INTTX1_IRQHandler [WEAK]
|
||||
EXPORT INTRX2_IRQHandler [WEAK]
|
||||
EXPORT INTTX2_IRQHandler [WEAK]
|
||||
EXPORT INTRX3_IRQHandler [WEAK]
|
||||
EXPORT INTTX3_IRQHandler [WEAK]
|
||||
EXPORT INTUART0_IRQHandler [WEAK]
|
||||
EXPORT INTUART1_IRQHandler [WEAK]
|
||||
EXPORT INTI2C0_IRQHandler [WEAK]
|
||||
EXPORT INTI2C1_IRQHandler [WEAK]
|
||||
EXPORT INTI2C2_IRQHandler [WEAK]
|
||||
EXPORT INTSSP0_IRQHandler [WEAK]
|
||||
EXPORT INTSSP1_IRQHandler [WEAK]
|
||||
EXPORT INTSSP2_IRQHandler [WEAK]
|
||||
EXPORT INTADHP_IRQHandler [WEAK]
|
||||
EXPORT INTADM0_IRQHandler [WEAK]
|
||||
EXPORT INTADM1_IRQHandler [WEAK]
|
||||
EXPORT INTAD_IRQHandler [WEAK]
|
||||
EXPORT INTAES_IRQHandler [WEAK]
|
||||
EXPORT INTSHA_IRQHandler [WEAK]
|
||||
EXPORT INTMLA_IRQHandler [WEAK]
|
||||
EXPORT INTESG_IRQHandler [WEAK]
|
||||
EXPORT INTSNFCSEQ_IRQHandler [WEAK]
|
||||
EXPORT INTSNFCPRTAE_IRQHandler [WEAK]
|
||||
EXPORT INTSNFCPRTCE_IRQHandler [WEAK]
|
||||
EXPORT INTSNFCFAIL_IRQHandler [WEAK]
|
||||
EXPORT INTMTEMG0_IRQHandler [WEAK]
|
||||
EXPORT INTMTPTB00_IRQHandler [WEAK]
|
||||
EXPORT INTMTPTB01_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP00_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP01_IRQHandler [WEAK]
|
||||
EXPORT INTMTEMG1_IRQHandler [WEAK]
|
||||
EXPORT INTMTPTB10_IRQHandler [WEAK]
|
||||
EXPORT INTMTPTB11_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP10_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP11_IRQHandler [WEAK]
|
||||
EXPORT INTMTEMG2_IRQHandler [WEAK]
|
||||
EXPORT INTMTPTB20_IRQHandler [WEAK]
|
||||
EXPORT INTMTTTB21_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP20_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP21_IRQHandler [WEAK]
|
||||
EXPORT INTMTEMG3_IRQHandler [WEAK]
|
||||
EXPORT INTMTPTB30_IRQHandler [WEAK]
|
||||
EXPORT INTMTTTB31_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP30_IRQHandler [WEAK]
|
||||
EXPORT INTMTCAP31_IRQHandler [WEAK]
|
||||
EXPORT INTTB0_IRQHandler [WEAK]
|
||||
EXPORT INTCAP00_IRQHandler [WEAK]
|
||||
EXPORT INTCAP01_IRQHandler [WEAK]
|
||||
EXPORT INTTB1_IRQHandler [WEAK]
|
||||
EXPORT INTCAP10_IRQHandler [WEAK]
|
||||
EXPORT INTCAP11_IRQHandler [WEAK]
|
||||
EXPORT INTTB2_IRQHandler [WEAK]
|
||||
EXPORT INTCAP20_IRQHandler [WEAK]
|
||||
EXPORT INTCAP21_IRQHandler [WEAK]
|
||||
EXPORT INTTB3_IRQHandler [WEAK]
|
||||
EXPORT INTCAP30_IRQHandler [WEAK]
|
||||
EXPORT INTCAP31_IRQHandler [WEAK]
|
||||
EXPORT INTTB4_IRQHandler [WEAK]
|
||||
EXPORT INTCAP40_IRQHandler [WEAK]
|
||||
EXPORT INTCAP41_IRQHandler [WEAK]
|
||||
EXPORT INTTB5_IRQHandler [WEAK]
|
||||
EXPORT INTCAP50_IRQHandler [WEAK]
|
||||
EXPORT INTCAP51_IRQHandler [WEAK]
|
||||
EXPORT INTTB6_IRQHandler [WEAK]
|
||||
EXPORT INTCAP60_IRQHandler [WEAK]
|
||||
EXPORT INTCAP61_IRQHandler [WEAK]
|
||||
EXPORT INTTB7_IRQHandler [WEAK]
|
||||
EXPORT INTCAP70_IRQHandler [WEAK]
|
||||
EXPORT INTCAP71_IRQHandler [WEAK]
|
||||
EXPORT INTRTC_IRQHandler [WEAK]
|
||||
EXPORT INTDMAA_IRQHandler [WEAK]
|
||||
EXPORT INTDMAB_IRQHandler [WEAK]
|
||||
EXPORT INTDMAC_IRQHandler [WEAK]
|
||||
EXPORT INTDMACTC8_IRQHandler [WEAK]
|
||||
EXPORT INTDMACTC9_IRQHandler [WEAK]
|
||||
EXPORT INTDMACTC10_IRQHandler [WEAK]
|
||||
EXPORT INTDMACTC11_IRQHandler [WEAK]
|
||||
EXPORT INTDMAAERR_IRQHandler [WEAK]
|
||||
EXPORT INTDMABERR_IRQHandler [WEAK]
|
||||
EXPORT INTDMACERR_IRQHandler [WEAK]
|
||||
EXPORT INTFLRDY_IRQHandler [WEAK]
|
||||
|
||||
INT0_IRQHandler
|
||||
INT1_IRQHandler
|
||||
INT2_IRQHandler
|
||||
INT3_IRQHandler
|
||||
INT4_IRQHandler
|
||||
INT5_IRQHandler
|
||||
INT6_IRQHandler
|
||||
INT7_IRQHandler
|
||||
INT8_IRQHandler
|
||||
INT9_IRQHandler
|
||||
INTA_IRQHandler
|
||||
INTB_IRQHandler
|
||||
INTC_IRQHandler
|
||||
INTD_IRQHandler
|
||||
INTE_IRQHandler
|
||||
INTF_IRQHandler
|
||||
INTRX0_IRQHandler
|
||||
INTTX0_IRQHandler
|
||||
INTRX1_IRQHandler
|
||||
INTTX1_IRQHandler
|
||||
INTRX2_IRQHandler
|
||||
INTTX2_IRQHandler
|
||||
INTRX3_IRQHandler
|
||||
INTTX3_IRQHandler
|
||||
INTUART0_IRQHandler
|
||||
INTUART1_IRQHandler
|
||||
INTI2C0_IRQHandler
|
||||
INTI2C1_IRQHandler
|
||||
INTI2C2_IRQHandler
|
||||
INTSSP0_IRQHandler
|
||||
INTSSP1_IRQHandler
|
||||
INTSSP2_IRQHandler
|
||||
INTADHP_IRQHandler
|
||||
INTADM0_IRQHandler
|
||||
INTADM1_IRQHandler
|
||||
INTAD_IRQHandler
|
||||
INTAES_IRQHandler
|
||||
INTSHA_IRQHandler
|
||||
INTMLA_IRQHandler
|
||||
INTESG_IRQHandler
|
||||
INTSNFCSEQ_IRQHandler
|
||||
INTSNFCPRTAE_IRQHandler
|
||||
INTSNFCPRTCE_IRQHandler
|
||||
INTSNFCFAIL_IRQHandler
|
||||
INTMTEMG0_IRQHandler
|
||||
INTMTPTB00_IRQHandler
|
||||
INTMTPTB01_IRQHandler
|
||||
INTMTCAP00_IRQHandler
|
||||
INTMTCAP01_IRQHandler
|
||||
INTMTEMG1_IRQHandler
|
||||
INTMTPTB10_IRQHandler
|
||||
INTMTPTB11_IRQHandler
|
||||
INTMTCAP10_IRQHandler
|
||||
INTMTCAP11_IRQHandler
|
||||
INTMTEMG2_IRQHandler
|
||||
INTMTPTB20_IRQHandler
|
||||
INTMTTTB21_IRQHandler
|
||||
INTMTCAP20_IRQHandler
|
||||
INTMTCAP21_IRQHandler
|
||||
INTMTEMG3_IRQHandler
|
||||
INTMTPTB30_IRQHandler
|
||||
INTMTTTB31_IRQHandler
|
||||
INTMTCAP30_IRQHandler
|
||||
INTMTCAP31_IRQHandler
|
||||
INTTB0_IRQHandler
|
||||
INTCAP00_IRQHandler
|
||||
INTCAP01_IRQHandler
|
||||
INTTB1_IRQHandler
|
||||
INTCAP10_IRQHandler
|
||||
INTCAP11_IRQHandler
|
||||
INTTB2_IRQHandler
|
||||
INTCAP20_IRQHandler
|
||||
INTCAP21_IRQHandler
|
||||
INTTB3_IRQHandler
|
||||
INTCAP30_IRQHandler
|
||||
INTCAP31_IRQHandler
|
||||
INTTB4_IRQHandler
|
||||
INTCAP40_IRQHandler
|
||||
INTCAP41_IRQHandler
|
||||
INTTB5_IRQHandler
|
||||
INTCAP50_IRQHandler
|
||||
INTCAP51_IRQHandler
|
||||
INTTB6_IRQHandler
|
||||
INTCAP60_IRQHandler
|
||||
INTCAP61_IRQHandler
|
||||
INTTB7_IRQHandler
|
||||
INTCAP70_IRQHandler
|
||||
INTCAP71_IRQHandler
|
||||
INTRTC_IRQHandler
|
||||
INTDMAA_IRQHandler
|
||||
INTDMAB_IRQHandler
|
||||
INTDMAC_IRQHandler
|
||||
INTDMACTC8_IRQHandler
|
||||
INTDMACTC9_IRQHandler
|
||||
INTDMACTC10_IRQHandler
|
||||
INTDMACTC11_IRQHandler
|
||||
INTDMAAERR_IRQHandler
|
||||
INTDMABERR_IRQHandler
|
||||
INTDMACERR_IRQHandler
|
||||
INTFLRDY_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
#! armcc -E -I. --cpu Cortex-M4
|
||||
;; TMPM46BF10 scatter file
|
||||
|
||||
;; Vector table starts at 0
|
||||
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
|
||||
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
|
||||
;; Initial PC == &__main (with LSB set to indicate Thumb)
|
||||
;; These two values are provided by the library
|
||||
;; Other vectors must be provided by the user
|
||||
;; Code starts after the last possible vector
|
||||
;; Data starts at 0x20000000
|
||||
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
|
||||
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
|
||||
|
||||
;; Compatible with ISSM model
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x00000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x100000
|
||||
#endif
|
||||
|
||||
; TMPM46B: 1024 KB FLASH (0x100000) + 512 KB SRAM (0x80000)
|
||||
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
|
||||
{
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE
|
||||
{
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
RW_IRAM1 0x200001E0 (0x80000 - 0x1E0)
|
||||
{
|
||||
tmpm46b_fc.o(+RO)
|
||||
.ANY (+RW, +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,453 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file startup_TMPM46b.s
|
||||
* @brief CMSIS Cortex-M4F Core Device Startup File for the
|
||||
* TOSHIBA 'TMPM46B' Device Series
|
||||
* @version V5.00
|
||||
* @date 2016/03/02
|
||||
*------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
|
||||
/*
|
||||
// <h> Stack Configuration
|
||||
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*/
|
||||
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
/*
|
||||
// <h> Heap Configuration
|
||||
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*/
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long INT0_IRQHandler // 0: Interrupt pin 0
|
||||
.long INT1_IRQHandler // 1: Interrupt pin 1
|
||||
.long INT2_IRQHandler // 2: Interrupt pin 2
|
||||
.long INT3_IRQHandler // 3: Interrupt pin 3
|
||||
.long INT4_IRQHandler // 4: Interrupt pin 4
|
||||
.long INT5_IRQHandler // 5: Interrupt pin 5
|
||||
.long INT6_IRQHandler // 6: Interrupt pin 6
|
||||
.long INT7_IRQHandler // 7: Interrupt pin 7
|
||||
.long INT8_IRQHandler // 8: Interrupt pin 8
|
||||
.long INT9_IRQHandler // 9: Interrupt pin 9
|
||||
.long INTA_IRQHandler // 10: Interrupt pin A
|
||||
.long INTB_IRQHandler // 11: Interrupt pin B
|
||||
.long INTC_IRQHandler // 12: Interrupt pin C
|
||||
.long INTD_IRQHandler // 13: Interrupt pin D
|
||||
.long INTE_IRQHandler // 14: Interrupt pin E
|
||||
.long INTF_IRQHandler // 15: Interrupt pin F
|
||||
.long INTRX0_IRQHandler // 16: Serial0 reception interrupt
|
||||
.long INTTX0_IRQHandler // 17: Serial0 transmission interrupt
|
||||
.long INTRX1_IRQHandler // 18: Serial1 reception interrupt
|
||||
.long INTTX1_IRQHandler // 19: Serial1 transmission interrupt
|
||||
.long INTRX2_IRQHandler // 20: Serial2 reception interrupt
|
||||
.long INTTX2_IRQHandler // 21: Serial2 transmission interrupt
|
||||
.long INTRX3_IRQHandler // 22: Serial3 reception interrupt
|
||||
.long INTTX3_IRQHandler // 23: Serial3 transmission interrupt
|
||||
.long INTUART0_IRQHandler // 24: Full UART0 transmission and reception interrupt
|
||||
.long INTUART1_IRQHandler // 25: Full UART1 transmission and reception interrupt
|
||||
.long INTI2C0_IRQHandler // 26: I2C0 transmission and reception interrupt
|
||||
.long INTI2C1_IRQHandler // 27: I2C1 transmission and reception interrupt
|
||||
.long INTI2C2_IRQHandler // 28: I2C2 transmission and reception interrupt
|
||||
.long INTSSP0_IRQHandler // 29: SSP(SPI) Serial interface 0 interrupt
|
||||
.long INTSSP1_IRQHandler // 30: SSP(SPI) Serial interface 1 interrupt
|
||||
.long INTSSP2_IRQHandler // 31: SSP(SPI) Serial interface 2 interrupt
|
||||
.long INTADHP_IRQHandler // 32: High Priority AD conversion interrupt
|
||||
.long INTADM0_IRQHandler // 33: AD conversion monitor interrupt 0
|
||||
.long INTADM1_IRQHandler // 34: AD conversion monitor interrupt 1
|
||||
.long INTAD_IRQHandler // 35: AD conversion interrupt
|
||||
.long INTAES_IRQHandler // 36: AES completion interrupt
|
||||
.long INTSHA_IRQHandler // 37: SHA completion interrupt
|
||||
.long INTMLA_IRQHandler // 38: MLA completion interrupt
|
||||
.long INTESG_IRQHandler // 39: ESG completion interrupt
|
||||
.long INTSNFCSEQ_IRQHandler // 40: SNFC command sequence end interrupt
|
||||
.long INTSNFCPRTAE_IRQHandler // 41: SNFC page lead RAM transfer end interrupt
|
||||
.long INTSNFCPRTCE_IRQHandler // 42: SNFC decode data RAM transmission end interrupt
|
||||
.long INTSNFCFAIL_IRQHandler // 43: SNFC decode fail interrupt
|
||||
.long 0 // 44: Reserved1
|
||||
.long 0 // 45: Reserved2
|
||||
.long 0 // 46: Reserved3
|
||||
.long INTMTEMG0_IRQHandler // 47: MPT0 EMG interrupt
|
||||
.long INTMTPTB00_IRQHandler // 48: MPT0 compare match0/overflow,IGBT cycle interrupt
|
||||
.long INTMTPTB01_IRQHandler // 49: MPT0 compare match1/overflow,IGBT cycle interrupt
|
||||
.long INTMTCAP00_IRQHandler // 50: MPT0 input capture0 interrupt
|
||||
.long INTMTCAP01_IRQHandler // 51: MPT0 input capture1 interrupt
|
||||
.long INTMTEMG1_IRQHandler // 52: MPT1 EMG interrupt
|
||||
.long INTMTPTB10_IRQHandler // 53: MPT1 compare match0/overflow,IGBT cycle interrupt
|
||||
.long INTMTPTB11_IRQHandler // 54: MPT1 compare match1/overflow,IGBT cycle interrupt
|
||||
.long INTMTCAP10_IRQHandler // 55: MPT1 input capture0 interrupt
|
||||
.long INTMTCAP11_IRQHandler // 56: MPT1 input capture1 interrupt
|
||||
.long INTMTEMG2_IRQHandler // 57: MPT2 EMG interrupt
|
||||
.long INTMTPTB20_IRQHandler // 58: MPT2 compare match0/overflow,IGBT cycle interrupt
|
||||
.long INTMTTTB21_IRQHandler // 59: MPT2 compare match1/overflow,IGBT cycle interrupt
|
||||
.long INTMTCAP20_IRQHandler // 60: MPT2 input capture0 interrupt
|
||||
.long INTMTCAP21_IRQHandler // 61: MPT2 input capture1 interrupt
|
||||
.long INTMTEMG3_IRQHandler // 62: MPT3 EMG interrupt
|
||||
.long INTMTPTB30_IRQHandler // 63: MPT3 compare match0/overflow,IGBT cycle interrupt
|
||||
.long INTMTTTB31_IRQHandler // 64: MPT3 compare match1/overflow,IGBT cycle interrupt
|
||||
.long INTMTCAP30_IRQHandler // 65: MPT3 input capture0 interrupt
|
||||
.long INTMTCAP31_IRQHandler // 66: MPT3 input capture1 interrupt
|
||||
.long INTTB0_IRQHandler // 67: TMRB0 compare match detection interrupt
|
||||
.long INTCAP00_IRQHandler // 68: TMRB0 input capture 0 interrupt
|
||||
.long INTCAP01_IRQHandler // 69: TMRB0 input capture 1 interrupt
|
||||
.long INTTB1_IRQHandler // 70: TMRB1 compare match detection interrupt
|
||||
.long INTCAP10_IRQHandler // 71: TMRB1 input capture 0 interrupt
|
||||
.long INTCAP11_IRQHandler // 72: TMRB1 input capture 1 interrupt
|
||||
.long INTTB2_IRQHandler // 73: TMRB2 compare match detection interrupt
|
||||
.long INTCAP20_IRQHandler // 74: TMRB2 input capture 0 interrupt
|
||||
.long INTCAP21_IRQHandler // 75: TMRB2 input capture 1 interrupt
|
||||
.long INTTB3_IRQHandler // 76: TMRB3 compare match detection interrupt
|
||||
.long INTCAP30_IRQHandler // 77: TMRB3 input capture 0 interrupt
|
||||
.long INTCAP31_IRQHandler // 78: TMRB3 input capture 1 interrupt
|
||||
.long INTTB4_IRQHandler // 79: TMRB4 compare match detection interrupt
|
||||
.long INTCAP40_IRQHandler // 80: TMRB4 input capture 0 interrupt
|
||||
.long INTCAP41_IRQHandler // 81: TMRB4 input capture 1 interrupt
|
||||
.long INTTB5_IRQHandler // 82: TMRB5 compare match detection interrupt
|
||||
.long INTCAP50_IRQHandler // 83: TMRB5 input capture 0 interrupt
|
||||
.long INTCAP51_IRQHandler // 84: TMRB5 input capture 1 interrupt
|
||||
.long INTTB6_IRQHandler // 85: TMRB6 compare match detection interrupt
|
||||
.long INTCAP60_IRQHandler // 86: TMRB6 input capture 0 interrupt
|
||||
.long INTCAP61_IRQHandler // 87: TMRB6 input capture 1 interrupt
|
||||
.long INTTB7_IRQHandler // 88: TMRB7 compare match detection interrupt
|
||||
.long INTCAP70_IRQHandler // 89: TMRB7 input capture 0 interrupt
|
||||
.long INTCAP71_IRQHandler // 90: TMRB7 input capture 1 interrupt
|
||||
.long INTRTC_IRQHandler // 91: Real time clock interrupt
|
||||
.long INTDMAA_IRQHandler // 92: DMAC unitA transmission completion interrupt(ch4-31)
|
||||
.long INTDMAB_IRQHandler // 93: DMAC unitB transmission completion interrupt(ch24-31)
|
||||
.long INTDMAC_IRQHandler // 94: DMAC unitC transmission completion interrupt(ch12-31)
|
||||
.long INTDMACTC8_IRQHandler // 95: DMAC unitC transmission completion interrupt(ch8)
|
||||
.long INTDMACTC9_IRQHandler // 96: DMAC unitC transmission completion interrupt(ch9)
|
||||
.long INTDMACTC10_IRQHandler // 97: DMAC unitC transmission completion interrupt(ch10)
|
||||
.long INTDMACTC11_IRQHandler // 98: DMAC unitC transmission completion interrupt(ch11)
|
||||
.long INTDMAAERR_IRQHandler // 99: DMAC transmission error interrupt(unitA)
|
||||
.long INTDMABERR_IRQHandler // 100: DMAC transmission error interrupt(unitB)
|
||||
.long INTDMACERR_IRQHandler // 101: DMAC transmission error interrupt(unitC)
|
||||
.long INTFLRDY_IRQHandler // 102: Flash Ready interrupt
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler INT0_IRQHandler
|
||||
def_irq_handler INT1_IRQHandler
|
||||
def_irq_handler INT2_IRQHandler
|
||||
def_irq_handler INT3_IRQHandler
|
||||
def_irq_handler INT4_IRQHandler
|
||||
def_irq_handler INT5_IRQHandler
|
||||
def_irq_handler INT6_IRQHandler
|
||||
def_irq_handler INT7_IRQHandler
|
||||
def_irq_handler INT8_IRQHandler
|
||||
def_irq_handler INT9_IRQHandler
|
||||
def_irq_handler INTA_IRQHandler
|
||||
def_irq_handler INTB_IRQHandler
|
||||
def_irq_handler INTC_IRQHandler
|
||||
def_irq_handler INTD_IRQHandler
|
||||
def_irq_handler INTE_IRQHandler
|
||||
def_irq_handler INTF_IRQHandler
|
||||
def_irq_handler INTRX0_IRQHandler
|
||||
def_irq_handler INTTX0_IRQHandler
|
||||
def_irq_handler INTRX1_IRQHandler
|
||||
def_irq_handler INTTX1_IRQHandler
|
||||
def_irq_handler INTRX2_IRQHandler
|
||||
def_irq_handler INTTX2_IRQHandler
|
||||
def_irq_handler INTRX3_IRQHandler
|
||||
def_irq_handler INTTX3_IRQHandler
|
||||
def_irq_handler INTUART0_IRQHandler
|
||||
def_irq_handler INTUART1_IRQHandler
|
||||
def_irq_handler INTI2C0_IRQHandler
|
||||
def_irq_handler INTI2C1_IRQHandler
|
||||
def_irq_handler INTI2C2_IRQHandler
|
||||
def_irq_handler INTSSP0_IRQHandler
|
||||
def_irq_handler INTSSP1_IRQHandler
|
||||
def_irq_handler INTSSP2_IRQHandler
|
||||
def_irq_handler INTADHP_IRQHandler
|
||||
def_irq_handler INTADM0_IRQHandler
|
||||
def_irq_handler INTADM1_IRQHandler
|
||||
def_irq_handler INTAD_IRQHandler
|
||||
def_irq_handler INTAES_IRQHandler
|
||||
def_irq_handler INTSHA_IRQHandler
|
||||
def_irq_handler INTMLA_IRQHandler
|
||||
def_irq_handler INTESG_IRQHandler
|
||||
def_irq_handler INTSNFCSEQ_IRQHandler
|
||||
def_irq_handler INTSNFCPRTAE_IRQHandler
|
||||
def_irq_handler INTSNFCPRTCE_IRQHandler
|
||||
def_irq_handler INTSNFCFAIL_IRQHandler
|
||||
def_irq_handler INTMTEMG0_IRQHandler
|
||||
def_irq_handler INTMTPTB00_IRQHandler
|
||||
def_irq_handler INTMTPTB01_IRQHandler
|
||||
def_irq_handler INTMTCAP00_IRQHandler
|
||||
def_irq_handler INTMTCAP01_IRQHandler
|
||||
def_irq_handler INTMTEMG1_IRQHandler
|
||||
def_irq_handler INTMTPTB10_IRQHandler
|
||||
def_irq_handler INTMTPTB11_IRQHandler
|
||||
def_irq_handler INTMTCAP10_IRQHandler
|
||||
def_irq_handler INTMTCAP11_IRQHandler
|
||||
def_irq_handler INTMTEMG2_IRQHandler
|
||||
def_irq_handler INTMTPTB20_IRQHandler
|
||||
def_irq_handler INTMTTTB21_IRQHandler
|
||||
def_irq_handler INTMTCAP20_IRQHandler
|
||||
def_irq_handler INTMTCAP21_IRQHandler
|
||||
def_irq_handler INTMTEMG3_IRQHandler
|
||||
def_irq_handler INTMTPTB30_IRQHandler
|
||||
def_irq_handler INTMTTTB31_IRQHandler
|
||||
def_irq_handler INTMTCAP30_IRQHandler
|
||||
def_irq_handler INTMTCAP31_IRQHandler
|
||||
def_irq_handler INTTB0_IRQHandler
|
||||
def_irq_handler INTCAP00_IRQHandler
|
||||
def_irq_handler INTCAP01_IRQHandler
|
||||
def_irq_handler INTTB1_IRQHandler
|
||||
def_irq_handler INTCAP10_IRQHandler
|
||||
def_irq_handler INTCAP11_IRQHandler
|
||||
def_irq_handler INTTB2_IRQHandler
|
||||
def_irq_handler INTCAP20_IRQHandler
|
||||
def_irq_handler INTCAP21_IRQHandler
|
||||
def_irq_handler INTTB3_IRQHandler
|
||||
def_irq_handler INTCAP30_IRQHandler
|
||||
def_irq_handler INTCAP31_IRQHandler
|
||||
def_irq_handler INTTB4_IRQHandler
|
||||
def_irq_handler INTCAP40_IRQHandler
|
||||
def_irq_handler INTCAP41_IRQHandler
|
||||
def_irq_handler INTTB5_IRQHandler
|
||||
def_irq_handler INTCAP50_IRQHandler
|
||||
def_irq_handler INTCAP51_IRQHandler
|
||||
def_irq_handler INTTB6_IRQHandler
|
||||
def_irq_handler INTCAP60_IRQHandler
|
||||
def_irq_handler INTCAP61_IRQHandler
|
||||
def_irq_handler INTTB7_IRQHandler
|
||||
def_irq_handler INTCAP70_IRQHandler
|
||||
def_irq_handler INTCAP71_IRQHandler
|
||||
def_irq_handler INTRTC_IRQHandler
|
||||
def_irq_handler INTDMAA_IRQHandler
|
||||
def_irq_handler INTDMAB_IRQHandler
|
||||
def_irq_handler INTDMAC_IRQHandler
|
||||
def_irq_handler INTDMACTC8_IRQHandler
|
||||
def_irq_handler INTDMACTC9_IRQHandler
|
||||
def_irq_handler INTDMACTC10_IRQHandler
|
||||
def_irq_handler INTDMACTC11_IRQHandler
|
||||
def_irq_handler INTDMAAERR_IRQHandler
|
||||
def_irq_handler INTDMABERR_IRQHandler
|
||||
def_irq_handler INTDMACERR_IRQHandler
|
||||
def_irq_handler INTFLRDY_IRQHandler
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,207 @@
|
|||
/* Linker script for Toshiba TMPM46B */
|
||||
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x00000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x100000
|
||||
#endif
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
|
||||
RAM (rwx) : ORIGIN = 0x200001E0, LENGTH = (512K - 0x1E0)
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapBase
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.vectors))
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
__end__ = .;
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
*(.ram_func*)
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__HeapBase = .;
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
KEEP(*(.heap*))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
KEEP(*(.stack*))
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,714 @@
|
|||
;/**
|
||||
; *******************************************************************************
|
||||
; * @file startup_TMPM46B.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for the
|
||||
; * TOSHIBA 'TMPM46B' Device Series
|
||||
; * @version V2.0.2.4
|
||||
; * @date 2015/03/31
|
||||
; *
|
||||
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
; *
|
||||
; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
; *******************************************************************************
|
||||
; */
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD INT0_IRQHandler ; 0: Interrupt pin 0
|
||||
DCD INT1_IRQHandler ; 1: Interrupt pin 1
|
||||
DCD INT2_IRQHandler ; 2: Interrupt pin 2
|
||||
DCD INT3_IRQHandler ; 3: Interrupt pin 3
|
||||
DCD INT4_IRQHandler ; 4: Interrupt pin 4
|
||||
DCD INT5_IRQHandler ; 5: Interrupt pin 5
|
||||
DCD INT6_IRQHandler ; 6: Interrupt pin 6
|
||||
DCD INT7_IRQHandler ; 7: Interrupt pin 7
|
||||
DCD INT8_IRQHandler ; 8: Interrupt pin 8
|
||||
DCD INT9_IRQHandler ; 9: Interrupt pin 9
|
||||
DCD INTA_IRQHandler ; 10: Interrupt pin A
|
||||
DCD INTB_IRQHandler ; 11: Interrupt pin B
|
||||
DCD INTC_IRQHandler ; 12: Interrupt pin C
|
||||
DCD INTD_IRQHandler ; 13: Interrupt pin D
|
||||
DCD INTE_IRQHandler ; 14: Interrupt pin E
|
||||
DCD INTF_IRQHandler ; 15: Interrupt pin F
|
||||
DCD INTRX0_IRQHandler ; 16: Serial0 reception interrupt
|
||||
DCD INTTX0_IRQHandler ; 17: Serial0 transmission interrupt
|
||||
DCD INTRX1_IRQHandler ; 18: Serial1 reception interrupt
|
||||
DCD INTTX1_IRQHandler ; 19: Serial1 transmission interrupt
|
||||
DCD INTRX2_IRQHandler ; 20: Serial2 reception interrupt
|
||||
DCD INTTX2_IRQHandler ; 21: Serial2 transmission interrupt
|
||||
DCD INTRX3_IRQHandler ; 22: Serial3 reception interrupt
|
||||
DCD INTTX3_IRQHandler ; 23: Serial3 transmission interrupt
|
||||
DCD INTUART0_IRQHandler ; 24: Full UART0 transmission and reception interrupt
|
||||
DCD INTUART1_IRQHandler ; 25: Full UART1 transmission and reception interrupt
|
||||
DCD INTI2C0_IRQHandler ; 26: I2C0 transmission and reception interrupt
|
||||
DCD INTI2C1_IRQHandler ; 27: I2C1 transmission and reception interrupt
|
||||
DCD INTI2C2_IRQHandler ; 28: I2C2 transmission and reception interrupt
|
||||
DCD INTSSP0_IRQHandler ; 29: SSP(SPI) Serial interface 0 interrupt
|
||||
DCD INTSSP1_IRQHandler ; 30: SSP(SPI) Serial interface 1 interrupt
|
||||
DCD INTSSP2_IRQHandler ; 31: SSP(SPI) Serial interface 2 interrupt
|
||||
DCD INTADHP_IRQHandler ; 32: High Priority AD conversion interrupt
|
||||
DCD INTADM0_IRQHandler ; 33: AD conversion monitor interrupt 0
|
||||
DCD INTADM1_IRQHandler ; 34: AD conversion monitor interrupt 1
|
||||
DCD INTAD_IRQHandler ; 35: AD conversion interrupt
|
||||
DCD INTAES_IRQHandler ; 36: AES completion interrupt
|
||||
DCD INTSHA_IRQHandler ; 37: SHA completion interrupt
|
||||
DCD INTMLA_IRQHandler ; 38: MLA completion interrupt
|
||||
DCD INTESG_IRQHandler ; 39: ESG completion interrupt
|
||||
DCD INTSNFCSEQ_IRQHandler ; 40: SNFC command sequence end interrupt
|
||||
DCD INTSNFCPRTAE_IRQHandler ; 41: SNFC page lead RAM transfer end interrupt
|
||||
DCD INTSNFCPRTCE_IRQHandler ; 42: SNFC decode data RAM transmission end interrupt
|
||||
DCD INTSNFCFAIL_IRQHandler ; 43: SNFC decode fail interrupt
|
||||
DCD 0 ; 44: Reserved
|
||||
DCD 0 ; 45: Reserved
|
||||
DCD 0 ; 46: Reserved
|
||||
DCD INTMTEMG0_IRQHandler ; 47: MPT0 EMG interrupt
|
||||
DCD INTMTPTB00_IRQHandler ; 48: MPT0 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTPTB01_IRQHandler ; 49: MPT0 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP00_IRQHandler ; 50: MPT0 input capture0 interrupt
|
||||
DCD INTMTCAP01_IRQHandler ; 51: MPT0 input capture1 interrupt
|
||||
DCD INTMTEMG1_IRQHandler ; 52: MPT1 EMG interrupt
|
||||
DCD INTMTPTB10_IRQHandler ; 53: MPT1 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTPTB11_IRQHandler ; 54: MPT1 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP10_IRQHandler ; 55: MPT1 input capture0 interrupt
|
||||
DCD INTMTCAP11_IRQHandler ; 56: MPT1 input capture1 interrupt
|
||||
DCD INTMTEMG2_IRQHandler ; 57: MPT2 EMG interrupt
|
||||
DCD INTMTPTB20_IRQHandler ; 58: MPT2 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTTTB21_IRQHandler ; 59: MPT2 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP20_IRQHandler ; 60: MPT2 input capture0 interrupt
|
||||
DCD INTMTCAP21_IRQHandler ; 61: MPT2 input capture1 interrupt
|
||||
DCD INTMTEMG3_IRQHandler ; 62: MPT3 EMG interrupt
|
||||
DCD INTMTPTB30_IRQHandler ; 63: MPT3 compare match0/overflow,IGBT cycle interrupt
|
||||
DCD INTMTTTB31_IRQHandler ; 64: MPT3 compare match1/overflow,IGBT cycle interrupt
|
||||
DCD INTMTCAP30_IRQHandler ; 65: MPT3 input capture0 interrupt
|
||||
DCD INTMTCAP31_IRQHandler ; 66: MPT3 input capture1 interrupt
|
||||
DCD INTTB0_IRQHandler ; 67: TMRB0 compare match detection interrupt
|
||||
DCD INTCAP00_IRQHandler ; 68: TMRB0 input capture 0 interrupt
|
||||
DCD INTCAP01_IRQHandler ; 69: TMRB0 input capture 1 interrupt
|
||||
DCD INTTB1_IRQHandler ; 70: TMRB1 compare match detection interrupt
|
||||
DCD INTCAP10_IRQHandler ; 71: TMRB1 input capture 0 interrupt
|
||||
DCD INTCAP11_IRQHandler ; 72: TMRB1 input capture 1 interrupt
|
||||
DCD INTTB2_IRQHandler ; 73: TMRB2 compare match detection interrupt
|
||||
DCD INTCAP20_IRQHandler ; 74: TMRB2 input capture 0 interrupt
|
||||
DCD INTCAP21_IRQHandler ; 75: TMRB2 input capture 1 interrupt
|
||||
DCD INTTB3_IRQHandler ; 76: TMRB3 compare match detection interrupt
|
||||
DCD INTCAP30_IRQHandler ; 77: TMRB3 input capture 0 interrupt
|
||||
DCD INTCAP31_IRQHandler ; 78: TMRB3 input capture 1 interrupt
|
||||
DCD INTTB4_IRQHandler ; 79: TMRB4 compare match detection interrupt
|
||||
DCD INTCAP40_IRQHandler ; 80: TMRB4 input capture 0 interrupt
|
||||
DCD INTCAP41_IRQHandler ; 81: TMRB4 input capture 1 interrupt
|
||||
DCD INTTB5_IRQHandler ; 82: TMRB5 compare match detection interrupt
|
||||
DCD INTCAP50_IRQHandler ; 83: TMRB5 input capture 0 interrupt
|
||||
DCD INTCAP51_IRQHandler ; 84: TMRB5 input capture 1 interrupt
|
||||
DCD INTTB6_IRQHandler ; 85: TMRB6 compare match detection interrupt
|
||||
DCD INTCAP60_IRQHandler ; 86: TMRB6 input capture 0 interrupt
|
||||
DCD INTCAP61_IRQHandler ; 87: TMRB6 input capture 1 interrupt
|
||||
DCD INTTB7_IRQHandler ; 88: TMRB7 compare match detection interrupt
|
||||
DCD INTCAP70_IRQHandler ; 89: TMRB7 input capture 0 interrupt
|
||||
DCD INTCAP71_IRQHandler ; 90: TMRB7 input capture 1 interrupt
|
||||
DCD INTRTC_IRQHandler ; 91: Real time clock interrupt
|
||||
DCD INTDMAA_IRQHandler ; 92: DMAC unitA transmission completion interrupt(ch4-31)
|
||||
DCD INTDMAB_IRQHandler ; 93: DMAC unitB transmission completion interrupt(ch24-31)
|
||||
DCD INTDMAC_IRQHandler ; 94: DMAC unitC transmission completion interrupt(ch12-31)
|
||||
DCD INTDMACTC8_IRQHandler ; 95: DMAC unitC transmission completion interrupt(ch8)
|
||||
DCD INTDMACTC9_IRQHandler ; 96: DMAC unitC transmission completion interrupt(ch9)
|
||||
DCD INTDMACTC10_IRQHandler ; 97: DMAC unitC transmission completion interrupt(ch10)
|
||||
DCD INTDMACTC11_IRQHandler ; 98: DMAC unitC transmission completion interrupt(ch11)
|
||||
DCD INTDMAAERR_IRQHandler ; 99: DMAC transmission error interrupt(unitA)
|
||||
DCD INTDMABERR_IRQHandler ; 100: DMAC transmission error interrupt(unitB)
|
||||
DCD INTDMACERR_IRQHandler ; 101: DMAC transmission error interrupt(unitC)
|
||||
DCD INTFLRDY_IRQHandler ; 102: Flash Ready interrupt
|
||||
THUMB
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK INT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT0_IRQHandler
|
||||
B INT0_IRQHandler
|
||||
|
||||
PUBWEAK INT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT1_IRQHandler
|
||||
B INT1_IRQHandler
|
||||
|
||||
PUBWEAK INT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT2_IRQHandler
|
||||
B INT2_IRQHandler
|
||||
|
||||
PUBWEAK INT3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT3_IRQHandler
|
||||
B INT3_IRQHandler
|
||||
|
||||
PUBWEAK INT4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT4_IRQHandler
|
||||
B INT4_IRQHandler
|
||||
|
||||
PUBWEAK INT5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT5_IRQHandler
|
||||
B INT5_IRQHandler
|
||||
|
||||
PUBWEAK INT6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT6_IRQHandler
|
||||
B INT6_IRQHandler
|
||||
|
||||
PUBWEAK INT7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT7_IRQHandler
|
||||
B INT7_IRQHandler
|
||||
|
||||
PUBWEAK INT8_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT8_IRQHandler
|
||||
B INT8_IRQHandler
|
||||
|
||||
PUBWEAK INT9_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INT9_IRQHandler
|
||||
B INT9_IRQHandler
|
||||
|
||||
PUBWEAK INTA_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTA_IRQHandler
|
||||
B INTA_IRQHandler
|
||||
|
||||
PUBWEAK INTB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTB_IRQHandler
|
||||
B INTB_IRQHandler
|
||||
|
||||
PUBWEAK INTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTC_IRQHandler
|
||||
B INTC_IRQHandler
|
||||
|
||||
PUBWEAK INTD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTD_IRQHandler
|
||||
B INTD_IRQHandler
|
||||
|
||||
PUBWEAK INTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTE_IRQHandler
|
||||
B INTE_IRQHandler
|
||||
|
||||
PUBWEAK INTF_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTF_IRQHandler
|
||||
B INTF_IRQHandler
|
||||
|
||||
PUBWEAK INTRX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTRX0_IRQHandler
|
||||
B INTRX0_IRQHandler
|
||||
|
||||
PUBWEAK INTTX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTX0_IRQHandler
|
||||
B INTTX0_IRQHandler
|
||||
|
||||
PUBWEAK INTRX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTRX1_IRQHandler
|
||||
B INTRX1_IRQHandler
|
||||
|
||||
PUBWEAK INTTX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTX1_IRQHandler
|
||||
B INTTX1_IRQHandler
|
||||
|
||||
PUBWEAK INTRX2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTRX2_IRQHandler
|
||||
B INTRX2_IRQHandler
|
||||
|
||||
PUBWEAK INTTX2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTX2_IRQHandler
|
||||
B INTTX2_IRQHandler
|
||||
|
||||
PUBWEAK INTRX3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTRX3_IRQHandler
|
||||
B INTRX3_IRQHandler
|
||||
|
||||
PUBWEAK INTTX3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTX3_IRQHandler
|
||||
B INTTX3_IRQHandler
|
||||
|
||||
PUBWEAK INTUART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTUART0_IRQHandler
|
||||
B INTUART0_IRQHandler
|
||||
|
||||
PUBWEAK INTUART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTUART1_IRQHandler
|
||||
B INTUART1_IRQHandler
|
||||
|
||||
PUBWEAK INTI2C0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTI2C0_IRQHandler
|
||||
B INTI2C0_IRQHandler
|
||||
|
||||
PUBWEAK INTI2C1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTI2C1_IRQHandler
|
||||
B INTI2C1_IRQHandler
|
||||
|
||||
PUBWEAK INTI2C2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTI2C2_IRQHandler
|
||||
B INTI2C2_IRQHandler
|
||||
|
||||
PUBWEAK INTSSP0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSSP0_IRQHandler
|
||||
B INTSSP0_IRQHandler
|
||||
|
||||
PUBWEAK INTSSP1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSSP1_IRQHandler
|
||||
B INTSSP1_IRQHandler
|
||||
|
||||
PUBWEAK INTSSP2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSSP2_IRQHandler
|
||||
B INTSSP2_IRQHandler
|
||||
|
||||
PUBWEAK INTADHP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTADHP_IRQHandler
|
||||
B INTADHP_IRQHandler
|
||||
|
||||
PUBWEAK INTADM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTADM0_IRQHandler
|
||||
B INTADM0_IRQHandler
|
||||
|
||||
PUBWEAK INTADM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTADM1_IRQHandler
|
||||
B INTADM1_IRQHandler
|
||||
|
||||
PUBWEAK INTAD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTAD_IRQHandler
|
||||
B INTAD_IRQHandler
|
||||
|
||||
PUBWEAK INTAES_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTAES_IRQHandler
|
||||
B INTAES_IRQHandler
|
||||
|
||||
PUBWEAK INTSHA_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSHA_IRQHandler
|
||||
B INTSHA_IRQHandler
|
||||
|
||||
PUBWEAK INTMLA_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMLA_IRQHandler
|
||||
B INTMLA_IRQHandler
|
||||
|
||||
PUBWEAK INTESG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTESG_IRQHandler
|
||||
B INTESG_IRQHandler
|
||||
|
||||
PUBWEAK INTSNFCSEQ_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSNFCSEQ_IRQHandler
|
||||
B INTSNFCSEQ_IRQHandler
|
||||
|
||||
PUBWEAK INTSNFCPRTAE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSNFCPRTAE_IRQHandler
|
||||
B INTSNFCPRTAE_IRQHandler
|
||||
|
||||
PUBWEAK INTSNFCPRTCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSNFCPRTCE_IRQHandler
|
||||
B INTSNFCPRTCE_IRQHandler
|
||||
|
||||
PUBWEAK INTSNFCFAIL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTSNFCFAIL_IRQHandler
|
||||
B INTSNFCFAIL_IRQHandler
|
||||
|
||||
PUBWEAK INTMTEMG0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTEMG0_IRQHandler
|
||||
B INTMTEMG0_IRQHandler
|
||||
|
||||
PUBWEAK INTMTPTB00_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTPTB00_IRQHandler
|
||||
B INTMTPTB00_IRQHandler
|
||||
|
||||
PUBWEAK INTMTPTB01_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTPTB01_IRQHandler
|
||||
B INTMTPTB01_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP00_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP00_IRQHandler
|
||||
B INTMTCAP00_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP01_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP01_IRQHandler
|
||||
B INTMTCAP01_IRQHandler
|
||||
|
||||
PUBWEAK INTMTEMG1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTEMG1_IRQHandler
|
||||
B INTMTEMG1_IRQHandler
|
||||
|
||||
PUBWEAK INTMTPTB10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTPTB10_IRQHandler
|
||||
B INTMTPTB10_IRQHandler
|
||||
|
||||
PUBWEAK INTMTPTB11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTPTB11_IRQHandler
|
||||
B INTMTPTB11_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP10_IRQHandler
|
||||
B INTMTCAP10_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP11_IRQHandler
|
||||
B INTMTCAP11_IRQHandler
|
||||
|
||||
PUBWEAK INTMTEMG2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTEMG2_IRQHandler
|
||||
B INTMTEMG2_IRQHandler
|
||||
|
||||
PUBWEAK INTMTPTB20_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTPTB20_IRQHandler
|
||||
B INTMTPTB20_IRQHandler
|
||||
|
||||
PUBWEAK INTMTTTB21_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTTTB21_IRQHandler
|
||||
B INTMTTTB21_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP20_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP20_IRQHandler
|
||||
B INTMTCAP20_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP21_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP21_IRQHandler
|
||||
B INTMTCAP21_IRQHandler
|
||||
|
||||
PUBWEAK INTMTEMG3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTEMG3_IRQHandler
|
||||
B INTMTEMG3_IRQHandler
|
||||
|
||||
PUBWEAK INTMTPTB30_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTPTB30_IRQHandler
|
||||
B INTMTPTB30_IRQHandler
|
||||
|
||||
PUBWEAK INTMTTTB31_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTTTB31_IRQHandler
|
||||
B INTMTTTB31_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP30_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP30_IRQHandler
|
||||
B INTMTCAP30_IRQHandler
|
||||
|
||||
PUBWEAK INTMTCAP31_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTMTCAP31_IRQHandler
|
||||
B INTMTCAP31_IRQHandler
|
||||
|
||||
PUBWEAK INTTB0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB0_IRQHandler
|
||||
B INTTB0_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP00_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP00_IRQHandler
|
||||
B INTCAP00_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP01_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP01_IRQHandler
|
||||
B INTCAP01_IRQHandler
|
||||
|
||||
PUBWEAK INTTB1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB1_IRQHandler
|
||||
B INTTB1_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP10_IRQHandler
|
||||
B INTCAP10_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP11_IRQHandler
|
||||
B INTCAP11_IRQHandler
|
||||
|
||||
PUBWEAK INTTB2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB2_IRQHandler
|
||||
B INTTB2_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP20_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP20_IRQHandler
|
||||
B INTCAP20_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP21_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP21_IRQHandler
|
||||
B INTCAP21_IRQHandler
|
||||
|
||||
PUBWEAK INTTB3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB3_IRQHandler
|
||||
B INTTB3_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP30_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP30_IRQHandler
|
||||
B INTCAP30_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP31_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP31_IRQHandler
|
||||
B INTCAP31_IRQHandler
|
||||
|
||||
PUBWEAK INTTB4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB4_IRQHandler
|
||||
B INTTB4_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP40_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP40_IRQHandler
|
||||
B INTCAP40_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP41_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP41_IRQHandler
|
||||
B INTCAP41_IRQHandler
|
||||
|
||||
PUBWEAK INTTB5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB5_IRQHandler
|
||||
B INTTB5_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP50_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP50_IRQHandler
|
||||
B INTCAP50_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP51_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP51_IRQHandler
|
||||
B INTCAP51_IRQHandler
|
||||
|
||||
PUBWEAK INTTB6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB6_IRQHandler
|
||||
B INTTB6_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP60_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP60_IRQHandler
|
||||
B INTCAP60_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP61_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP61_IRQHandler
|
||||
B INTCAP61_IRQHandler
|
||||
|
||||
PUBWEAK INTTB7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTTB7_IRQHandler
|
||||
B INTTB7_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP70_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP70_IRQHandler
|
||||
B INTCAP70_IRQHandler
|
||||
|
||||
PUBWEAK INTCAP71_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTCAP71_IRQHandler
|
||||
B INTCAP71_IRQHandler
|
||||
|
||||
PUBWEAK INTRTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTRTC_IRQHandler
|
||||
B INTRTC_IRQHandler
|
||||
|
||||
PUBWEAK INTDMAA_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMAA_IRQHandler
|
||||
B INTDMAA_IRQHandler
|
||||
|
||||
PUBWEAK INTDMAB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMAB_IRQHandler
|
||||
B INTDMAB_IRQHandler
|
||||
|
||||
PUBWEAK INTDMAC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMAC_IRQHandler
|
||||
B INTDMAC_IRQHandler
|
||||
|
||||
PUBWEAK INTDMACTC8_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMACTC8_IRQHandler
|
||||
B INTDMACTC8_IRQHandler
|
||||
|
||||
PUBWEAK INTDMACTC9_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMACTC9_IRQHandler
|
||||
B INTDMACTC9_IRQHandler
|
||||
|
||||
PUBWEAK INTDMACTC10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMACTC10_IRQHandler
|
||||
B INTDMACTC10_IRQHandler
|
||||
|
||||
PUBWEAK INTDMACTC11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMACTC11_IRQHandler
|
||||
B INTDMACTC11_IRQHandler
|
||||
|
||||
PUBWEAK INTDMAAERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMAAERR_IRQHandler
|
||||
B INTDMAAERR_IRQHandler
|
||||
|
||||
PUBWEAK INTDMABERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMABERR_IRQHandler
|
||||
B INTDMABERR_IRQHandler
|
||||
|
||||
PUBWEAK INTDMACERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTDMACERR_IRQHandler
|
||||
B INTDMACERR_IRQHandler
|
||||
|
||||
PUBWEAK INTFLRDY_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
INTFLRDY_IRQHandler
|
||||
B INTFLRDY_IRQHandler
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
|
||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x200001E0;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2006FFFF;
|
||||
define symbol __ICFEDIT_region_BRAM_start__ = 0x20070000;
|
||||
define symbol __ICFEDIT_region_BRAM_end__ = 0x200807FF;
|
||||
/*-Sizes-*/
|
||||
/*Heap 1/4 of ram and stack 1/8*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x10000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x20000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define block FLASH_CODE_ROM {section FLASH_ROM_init object flash_api.o, section .text_init object tmpm46b_fc.o};
|
||||
define block FLASH_CODE_RAM {section FLASH_ROM object flash_api.o, section .text object tmpm46b_fc.o};
|
||||
|
||||
initialize by copy { readwrite };
|
||||
initialize manually { section FLASH_ROM object flash_api.o, section .text object tmpm46b_fc.o};
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place at address mem: 0x400 { block FLASH_CODE_ROM };
|
||||
place at address mem: 0x20070000 { block FLASH_CODE_RAM };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in ROM_region { readonly };
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* mbed Microcontroller Library - CMSIS for TMPM46B
|
||||
* Copyright (C) 2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in TMPM46B specifics
|
||||
*/
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "TMPM46B.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic for TMPM46B
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma section=".intvec"
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
|
||||
#elif defined(__CC_ARM)
|
||||
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t vectors[];
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors)
|
||||
#else
|
||||
#error "Flash vector address not set for this toolchain"
|
||||
#endif
|
||||
|
||||
|
||||
#define NVIC_NUM_VECTORS (119)
|
||||
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,387 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file system_TMPM46B.c
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
|
||||
* TOSHIBA 'TMPM46B' Device Series
|
||||
* @version V2.0.2.4
|
||||
* @date 2018/3/15
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "TMPM46B.h"
|
||||
|
||||
/*-------- <<< Start of configuration section >>> ----------------------------*/
|
||||
|
||||
/* Watchdog Timer (WD) Configuration */
|
||||
#define WD_SETUP (1U)
|
||||
#define WDMOD_Val (0x00000000UL)
|
||||
#define WDCR_Val (0x000000B1UL)
|
||||
|
||||
/* Clock Generator (CG) Configuration */
|
||||
#define CLOCK_SETUP (1U)
|
||||
#define SYSCR_Val (0x00010000UL)
|
||||
#define OSCCR_Val (0x00020501UL) /* OSCCR<OSCSEL> = 1, OSCCR<XEN2> = 0, OSCCR<XEN1> = 1, <HOSCON> = 1 */
|
||||
|
||||
#define STBYCR_Val (0x00000003UL)
|
||||
|
||||
#define CG_8M_MUL_4_FPLL (0x00006A0FUL<<1U)
|
||||
#define CG_8M_MUL_5_FPLL (0x00006A13UL<<1U)
|
||||
#define CG_8M_MUL_6_FPLL (0x00006917UL<<1U)
|
||||
#define CG_8M_MUL_10_FPLL (0x00006A26UL<<1U)
|
||||
#define CG_8M_MUL_12_FPLL (0x0000692EUL<<1U)
|
||||
|
||||
#define CG_10M_MUL_4_FPLL (0x00006A0FUL<<1U)
|
||||
#define CG_10M_MUL_5_FPLL (0x00006A13UL<<1U)
|
||||
#define CG_10M_MUL_6_FPLL (0x00006917UL<<1U)
|
||||
#define CG_10M_MUL_8_FPLL (0x00006A1EUL<<1U)
|
||||
#define CG_10M_MUL_10_FPLL (0x00006A26UL<<1U)
|
||||
#define CG_10M_MUL_12_FPLL (0x0000692EUL<<1U)
|
||||
|
||||
#define CG_12M_MUL_4_FPLL (0x00006A0FUL<<1U)
|
||||
#define CG_12M_MUL_5_FPLL (0x00006A13UL<<1U)
|
||||
#define CG_12M_MUL_8_FPLL (0x00006A1EUL<<1U)
|
||||
#define CG_12M_MUL_10_FPLL (0x00006A26UL<<1U)
|
||||
|
||||
#define CG_16M_MUL_4_FPLL (0x00006A0FUL<<1U)
|
||||
|
||||
#define CG_PLLSEL_PLLON_SET ((uint32_t)0x00010000)
|
||||
#define CG_PLLSEL_PLLON_CLEAR ((uint32_t)0xFFFEFFFF)
|
||||
#define CG_PLLSEL_PLLSEL_SET ((uint32_t)0x00020000)
|
||||
#define CG_PLLSEL_PLLST_MASK ((uint32_t)0x00040000)
|
||||
|
||||
#define CG_OSCCR_XEN1_SET ((uint32_t)0x00000001)
|
||||
#define CG_OSCCR_XEN2_CLEAR ((uint32_t)0xFFFFFFFD)
|
||||
#define CG_OSCCR_HOSCON_SET ((uint32_t)0x00000400)
|
||||
#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
|
||||
#define CG_WUP_START_SET ((uint32_t)0x00004000)
|
||||
#define CG_WUEF_VALUE_MASK ((uint32_t)0x00008000)
|
||||
#define CG_OSCCR_WUPSEL2_SET ((uint32_t)0x00020000)
|
||||
#define CG_OSCCR_WUPSEL1_CLEAR ((uint32_t)0xFFFEFFFF)
|
||||
#define CG_OSCCR_OSCF_MASK ((uint32_t)0x00000200)
|
||||
|
||||
#define WD_MOD_WDTE_SET ((uint32_t)0x00000080)
|
||||
|
||||
//#define PLLSEL_Ready CG_16M_MUL_5_FPLL /* -M46BSTK */
|
||||
#define PLLSEL_Ready CG_12M_MUL_5_FPLL /* +M46BSTK */
|
||||
|
||||
#define PLLSEL_Val (PLLSEL_Ready|0x00030000UL)
|
||||
#define PLLSEL_MASK (0x0000FFFEUL)
|
||||
|
||||
/*-------- <<< End of configuration section >>> ------------------------------*/
|
||||
|
||||
/*-------- DEFINES -----------------------------------------------------------*/
|
||||
/* Define clocks */
|
||||
#define OSC_8M ( 8000000UL)
|
||||
#define OSC_10M (10000000UL)
|
||||
#define OSC_12M (12000000UL)
|
||||
#define OSC_16M (16000000UL)
|
||||
//#define EXTALH OSC_16M /* External high-speed oscillator freq */ /* -M46BSTK */
|
||||
#define EXTALH OSC_12M /* External high-speed oscillator freq */ /* +M46BSTK */
|
||||
#define XTALH OSC_10M /* Internal high-speed oscillator freq */
|
||||
|
||||
/* Configure Warm-up time */
|
||||
#define HZ_1M (1000000UL)
|
||||
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
|
||||
#define WU_TIME_PLL (100UL) /* warm-up time for PLL is 100us */
|
||||
#define OSCCR_WUPT_MASK (0x000FFFFFUL)
|
||||
#define OSCCR_WUPT_EXT ((uint32_t)(((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M / 16UL) << 20U)) /* OSCCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
|
||||
#define OSCCR_WUPT_PLL ((WU_TIME_PLL * EXTALH / HZ_1M /16UL) << 20U)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
||||
/* Determine core clock frequency according to settings */
|
||||
/* System clock is high-speed clock*/
|
||||
#if (OSCCR_Val & (1U<<8U))
|
||||
#define CORE_TALH (EXTALH)
|
||||
#else
|
||||
#define CORE_TALH (XTALH)
|
||||
#endif
|
||||
|
||||
#if ((PLLSEL_Val & (1U<<16U)) && (PLLSEL_Val & (1U<<17U))) /* If PLL selected and enabled */
|
||||
#if (CORE_TALH == OSC_8M) /* If input is 8MHz */
|
||||
#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_4_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 32MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_5_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 40MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_6_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 6U ) /* output clock is 48MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_8_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 8U ) /* output clock is 64MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_10_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 10U ) /* output clock is 80MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_12_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 12U ) /* output clock is 96MHz */
|
||||
#else /* fc -> reserved */
|
||||
#define __CORE_CLK (0U)
|
||||
#endif /* End input is 8MHz */
|
||||
#elif (CORE_TALH == OSC_10M) /* If input is 10MHz */
|
||||
#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_4_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 40MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_5_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 50MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_6_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 6U ) /* output clock is 60MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_8_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 8U ) /* output clock is 80MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_10_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 10U ) /* output clock is 100MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_12_FPLL))
|
||||
#define __CORE_CLK (CORE_TALH * 12U ) /* output clock is 120MHz */
|
||||
#else /* fc -> reserved */
|
||||
#define __CORE_CLK (0U)
|
||||
#endif /* End input is 10MHz */
|
||||
#elif (CORE_TALH == OSC_12M) /* If input is 12MHz */
|
||||
#if ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_4_FPLL)
|
||||
#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 48MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_5_FPLL)
|
||||
#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 60MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_6_FPLL)
|
||||
#define __CORE_CLK (CORE_TALH * 6U ) /* output clock is 72MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_8_FPLL)
|
||||
#define __CORE_CLK (CORE_TALH * 8U ) /* output clock is 96MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_10_FPLL)
|
||||
#define __CORE_CLK (CORE_TALH * 10U ) /* output clock is 120MHz */
|
||||
#else /* fc -> reserved */
|
||||
#define __CORE_CLK (0U)
|
||||
#endif /* End input is 12MHz */
|
||||
#elif (CORE_TALH == OSC_16M) /* If input is 16MHz */
|
||||
#if ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_4_FPLL)
|
||||
#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 64MHz */
|
||||
#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_5_FPLL)
|
||||
#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 80MHz */
|
||||
#else /* fc -> reserved */
|
||||
#define __CORE_CLK (0U)
|
||||
#endif /* End input is 16MHz */
|
||||
#else /* input clock not known */
|
||||
#define __CORE_CLK (0U)
|
||||
#error "Core Oscillator Frequency invalid!"
|
||||
#endif /* End switch input clock */
|
||||
#else
|
||||
#define __CORE_CLK (CORE_TALH)
|
||||
#endif
|
||||
|
||||
#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
|
||||
#define __CORE_SYS (__CORE_CLK)
|
||||
#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/2 */
|
||||
#define __CORE_SYS (__CORE_CLK / 2U)
|
||||
#elif ((SYSCR_Val & 7U) == 5U) /* Gear -> fc/4 */
|
||||
#define __CORE_SYS (__CORE_CLK / 4U)
|
||||
#elif ((SYSCR_Val & 7U) == 6U) /* Gear -> fc/8 */
|
||||
#define __CORE_SYS (__CORE_CLK / 8U)
|
||||
#elif ((SYSCR_Val & 7U) == 7U) /* Gear -> fc/16 */
|
||||
#define __CORE_SYS (__CORE_CLK / 16U)
|
||||
#else /* Gear -> reserved */
|
||||
#define __CORE_SYS (0U)
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define __CORE_SYS (XTALH)
|
||||
|
||||
#endif /* clock Setup */
|
||||
|
||||
/* Clock Variable definitions */
|
||||
uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Update SystemCoreClock according register values.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{ /* Get Core Clock Frequency */
|
||||
uint32_t CoreClock = 0U;
|
||||
uint32_t CoreClockInput = 0U;
|
||||
uint32_t regval = 0U;
|
||||
uint32_t oscsel = 0U;
|
||||
uint32_t pllsel = 0U;
|
||||
uint32_t pllon = 0U;
|
||||
/* Determine clock frequency according to clock register values */
|
||||
/* System clock is high-speed clock */
|
||||
regval = TSB_CG->OSCCR;
|
||||
oscsel = regval & CG_OSCCR_OSCSEL_SET;
|
||||
if (oscsel) { /* If system clock is External high-speed oscillator freq */
|
||||
CoreClock = EXTALH;
|
||||
} else { /* If system clock is Internal high-speed oscillator freq */
|
||||
CoreClock = XTALH;
|
||||
}
|
||||
regval = TSB_CG->PLLSEL;
|
||||
pllsel = regval & CG_PLLSEL_PLLSEL_SET;
|
||||
pllon = regval & CG_PLLSEL_PLLON_SET;
|
||||
if (pllsel && pllon) { /* If PLL enabled */
|
||||
if (CoreClock == OSC_8M) { /* If input is 8MHz */
|
||||
if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_4_FPLL) {
|
||||
CoreClockInput = CoreClock * 4U; /* output clock is 32MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_5_FPLL) {
|
||||
CoreClockInput = CoreClock * 5U; /* output clock is 40MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_6_FPLL) {
|
||||
CoreClockInput = CoreClock * 6U; /* output clock is 48MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_10_FPLL) {
|
||||
CoreClockInput = CoreClock * 10U; /* output clock is 80MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_12_FPLL) {
|
||||
CoreClockInput = CoreClock * 12U; /* output clock is 96MHz */
|
||||
} else {
|
||||
CoreClockInput = 0U; /* fc -> reserved */
|
||||
}
|
||||
} else if (CoreClock == OSC_10M) { /* If input is 10MHz */
|
||||
if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_4_FPLL) {
|
||||
CoreClockInput = CoreClock * 4U; /* output clock is 40MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_5_FPLL) {
|
||||
CoreClockInput = CoreClock * 5U; /* output clock is 50MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_6_FPLL) {
|
||||
CoreClockInput = CoreClock * 6U; /* output clock is 60MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_8_FPLL) {
|
||||
CoreClockInput = CoreClock * 8U; /* output clock is 80MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_10_FPLL) {
|
||||
CoreClockInput = CoreClock * 10U; /* output clock is 100MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_12_FPLL) {
|
||||
CoreClockInput = CoreClock * 12U; /* output clock is 120MHz */
|
||||
}else {
|
||||
CoreClockInput = 0U; /* fc -> reserved */
|
||||
}
|
||||
} else if (CoreClock == OSC_12M) { /* If input is 12MHz */
|
||||
if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_4_FPLL) {
|
||||
CoreClockInput = CoreClock * 4U; /* output clock is 48MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_5_FPLL) {
|
||||
CoreClockInput = CoreClock * 5U; /* output clock is 60MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) {
|
||||
CoreClockInput = CoreClock * 8U; /* output clock is 96MHz */
|
||||
} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_10_FPLL) {
|
||||
CoreClockInput = CoreClock * 10U; /* output clock is 120MHz */
|
||||
} else {
|
||||
CoreClockInput = 0U; /* fc -> reserved */
|
||||
}
|
||||
} else if (CoreClock == OSC_16M) { /* If input is 16MHz */
|
||||
if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_16M_MUL_4_FPLL) {
|
||||
CoreClockInput = CoreClock * 4U; /* output clock is 64MHz */
|
||||
} else {
|
||||
CoreClockInput = 0U; /* fc -> reserved */
|
||||
}
|
||||
} else {
|
||||
CoreClockInput = 0U;
|
||||
}
|
||||
} else {
|
||||
CoreClockInput = CoreClock;
|
||||
}
|
||||
switch (TSB_CG->SYSCR & 7U) {
|
||||
case 0U:
|
||||
SystemCoreClock = CoreClockInput; /* Gear -> fc */
|
||||
break;
|
||||
case 1U:
|
||||
case 2U:
|
||||
case 3U: /* Gear -> reserved */
|
||||
SystemCoreClock = 0U;
|
||||
break;
|
||||
case 4U: /* Gear -> fc/2 */
|
||||
SystemCoreClock = CoreClockInput / 2U;
|
||||
break;
|
||||
case 5U: /* Gear -> fc/4 */
|
||||
SystemCoreClock = CoreClockInput / 4U;
|
||||
break;
|
||||
case 6U: /* Gear -> fc/8 */
|
||||
SystemCoreClock = CoreClockInput / 8U;
|
||||
break;
|
||||
case 7U: /* Gear -> fc/16 */
|
||||
if (CoreClockInput >= OSC_16M){
|
||||
SystemCoreClock = CoreClockInput / 16U;
|
||||
} else{
|
||||
SystemCoreClock = 0U;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
uint32_t regval = 0U;
|
||||
volatile uint32_t pllst = 0U;
|
||||
volatile uint32_t wuef = 0U;
|
||||
volatile uint32_t oscf = 0U;
|
||||
uint32_t wdte = 0U;
|
||||
|
||||
#if defined ( __CC_ARM )/*Enable FPU for Keil*/
|
||||
#if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
|
||||
/* enable FPU if available and used */
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (WD_SETUP) /* Watchdog Setup */
|
||||
while (TSB_WD->FLG != 0U) {
|
||||
} /* When writing to WDMOD or WDCR, confirm "0" of WDFLG<FLG>. */
|
||||
TSB_WD->MOD = WDMOD_Val;
|
||||
regval = TSB_WD->MOD;
|
||||
wdte = regval & WD_MOD_WDTE_SET;
|
||||
if (!wdte) { /* If watchdog is to be disabled */
|
||||
TSB_WD->CR = WDCR_Val;
|
||||
} else {
|
||||
/*Do nothing*/
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
||||
TSB_CG->SYSCR = SYSCR_Val;
|
||||
TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
|
||||
TSB_CG->OSCCR |= OSCCR_WUPT_EXT;
|
||||
TSB_CG->OSCCR |= CG_OSCCR_HOSCON_SET;
|
||||
TSB_CG->OSCCR |= CG_OSCCR_XEN1_SET;
|
||||
TSB_CG->OSCCR |= CG_OSCCR_WUPSEL2_SET;
|
||||
TSB_CG->OSCCR &= CG_OSCCR_WUPSEL1_CLEAR;
|
||||
TSB_CG->OSCCR |= CG_WUP_START_SET;
|
||||
wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
|
||||
while (wuef) {
|
||||
wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
|
||||
} /* Warm-up */
|
||||
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
|
||||
oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
|
||||
while (oscf != CG_OSCCR_OSCF_MASK) {
|
||||
oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
|
||||
} /* Confirm CGOSCCR<OSCF>="1" */
|
||||
/* TSB_CG->OSCCR &= CG_OSCCR_XEN2_CLEAR ; */ /* IHOSC should be not stopped for using WDT. */
|
||||
|
||||
TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
|
||||
TSB_CG->OSCCR |= OSCCR_WUPT_PLL;
|
||||
TSB_CG->PLLSEL &= CG_PLLSEL_PLLON_CLEAR;
|
||||
TSB_CG->PLLSEL = PLLSEL_Ready;
|
||||
TSB_CG->OSCCR |= CG_WUP_START_SET;
|
||||
wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
|
||||
while (wuef) {
|
||||
wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
|
||||
} /* Warm-up */
|
||||
|
||||
TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
|
||||
TSB_CG->OSCCR |= OSCCR_WUPT_PLL;
|
||||
TSB_CG->PLLSEL |= CG_PLLSEL_PLLON_SET; /* PLL enabled */
|
||||
TSB_CG->STBYCR = STBYCR_Val;
|
||||
TSB_CG->OSCCR |= CG_WUP_START_SET;
|
||||
wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
|
||||
while (wuef) {
|
||||
wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
|
||||
} /* Warm-up */
|
||||
TSB_CG->PLLSEL |= CG_PLLSEL_PLLSEL_SET;
|
||||
pllst = TSB_CG->PLLSEL & CG_PLLSEL_PLLST_MASK;
|
||||
while (pllst != CG_PLLSEL_PLLST_MASK) {
|
||||
pllst = TSB_CG->PLLSEL & CG_PLLSEL_PLLST_MASK;
|
||||
} /*Confirm CGPLLSEL<PLLST> = "1" */
|
||||
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/**
|
||||
*****************************************************************************
|
||||
* @file system_TMPM46B.h
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the
|
||||
* TOSHIBA 'TMPM46B' Device Series
|
||||
* @version V2.0.2.1
|
||||
* @date 2014/12/03
|
||||
*
|
||||
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_TMPM46B_H
|
||||
#define __SYSTEM_TMPM46B_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "flash_api.h"
|
||||
#include "mbed_critical.h"
|
||||
#include "tmpm46b_fc.h"
|
||||
|
||||
#define PROGRAM_WIRTE_MAX 16U /* Page program could be written 16 bytes/4 words once */
|
||||
#define SECTOR_SIZE 0x8000 /* (512 * 8) sectors */
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM"))
|
||||
#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM"))
|
||||
#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM"))
|
||||
#pragma section = "FLASH_CODE_RAM"
|
||||
#pragma section = "FLASH_CODE_ROM"
|
||||
#endif
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
static void Copy_Routine(uint32_t * dest, uint32_t * source, uint32_t size)
|
||||
{
|
||||
uint32_t *dest_addr, *source_addr, tmpsize;
|
||||
uint32_t i, tmps, tmpd, mask;
|
||||
|
||||
dest_addr = dest;
|
||||
source_addr = source;
|
||||
|
||||
tmpsize = size >> 2U;
|
||||
for (i = 0U; i < tmpsize; i++) { /* 32bits copy */
|
||||
*dest_addr = *source_addr;
|
||||
dest_addr++;
|
||||
source_addr++;
|
||||
}
|
||||
if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */
|
||||
mask = 0xFFFFFF00U;
|
||||
i = size & 0x00000003U;
|
||||
tmps = *source_addr;
|
||||
tmpd = *dest_addr;
|
||||
while (i - 1U) {
|
||||
mask = mask << 8U;
|
||||
i--;
|
||||
}
|
||||
tmps = tmps & (~mask);
|
||||
tmpd = tmpd & (mask);
|
||||
*dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
int32_t flash_init(flash_t *obj)
|
||||
{
|
||||
TSB_FC->WCLKCR = 0x00000004U;
|
||||
TSB_FC->PROGCR = 0x00000001U;
|
||||
TSB_FC->ERASECR = 0x00000007U;
|
||||
TSB_FC->AREASEL = 0x00000000U;
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t flash_free(flash_t *obj)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
#pragma location = "FLASH_ROM"
|
||||
#endif
|
||||
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
|
||||
{
|
||||
int status = FAIL;
|
||||
/* We need to prevent flash accesses during erase operation */
|
||||
core_util_critical_section_enter();
|
||||
|
||||
if (FC_SUCCESS == FC_EraseBlock(address)) {
|
||||
status = SUCCESS;
|
||||
} else {
|
||||
/* Do nothing */
|
||||
}
|
||||
core_util_critical_section_exit();
|
||||
return status;
|
||||
}
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
#pragma location = "FLASH_ROM"
|
||||
#endif
|
||||
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
|
||||
{
|
||||
int status = SUCCESS;
|
||||
|
||||
/* We need to prevent flash accesses during program operation */
|
||||
core_util_critical_section_enter();
|
||||
while (size > PROGRAM_WIRTE_MAX) {
|
||||
if (FC_SUCCESS == FC_WritePage((uint32_t)address, (uint32_t *)data)) { /* write one page every time */
|
||||
/* Do nothing */
|
||||
} else {
|
||||
status = FAIL;
|
||||
break;
|
||||
}
|
||||
size = size - PROGRAM_WIRTE_MAX;
|
||||
address = address + PROGRAM_WIRTE_MAX;
|
||||
data = data + PROGRAM_WIRTE_MAX;
|
||||
}
|
||||
if (FC_SUCCESS == FC_WritePage((uint32_t)address, (uint32_t *)data)) { /* write the last data, no more than one page */
|
||||
/* Do nothing */
|
||||
} else {
|
||||
status = FAIL;
|
||||
}
|
||||
|
||||
core_util_critical_section_exit();
|
||||
return status;
|
||||
}
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
#pragma location = "FLASH_ROM"
|
||||
#endif
|
||||
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
|
||||
{
|
||||
if (address >= FLASH_CHIP_SIZE)
|
||||
return MBED_FLASH_INVALID_SIZE;
|
||||
|
||||
return SECTOR_SIZE;
|
||||
}
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
#pragma location = "FLASH_ROM"
|
||||
#endif
|
||||
uint32_t flash_get_page_size(const flash_t *obj)
|
||||
{
|
||||
return FLASH_PAGE_SIZE;
|
||||
}
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
#pragma location = "FLASH_ROM"
|
||||
#endif
|
||||
uint32_t flash_get_start_address(const flash_t *obj)
|
||||
{
|
||||
return FLASH_START_ADDR;
|
||||
}
|
||||
|
||||
#if defined ( __ICCARM__ ) /* IAR Compiler */
|
||||
#pragma location = "FLASH_ROM"
|
||||
#endif
|
||||
uint32_t flash_get_size(const flash_t *obj)
|
||||
{
|
||||
return FLASH_CHIP_SIZE;
|
||||
}
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_api.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "pinmap.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
#define GPIO_DATA PIN_DATA(0, 3)
|
||||
extern const PinMap PinMap_GPIO_IRQ[];
|
||||
|
||||
uint32_t gpio_set(PinName pin)
|
||||
{
|
||||
// Check that pin is valid
|
||||
MBED_ASSERT(pin != (PinName)NC);
|
||||
|
||||
// Set pin function as GPIO pin
|
||||
pin_function(pin, GPIO_DATA);
|
||||
|
||||
// Return pin mask
|
||||
return (1 << (pin & 0x07));
|
||||
}
|
||||
|
||||
void gpio_init(gpio_t *obj, PinName pin)
|
||||
{
|
||||
// Store above pin mask, pin name into GPIO object
|
||||
obj->pin = pin;
|
||||
obj->mask = gpio_set(pin);
|
||||
obj->port = (GPIO_Port) (pin >> 3);
|
||||
CG_SetFcPeriphA((1 << obj->port), ENABLE);
|
||||
}
|
||||
|
||||
void gpio_mode(gpio_t *obj, PinMode mode)
|
||||
{
|
||||
// Set pin mode
|
||||
pin_mode(obj->pin, mode);
|
||||
}
|
||||
|
||||
// Set gpio object pin direction
|
||||
void gpio_dir(gpio_t *obj, PinDirection direction)
|
||||
{
|
||||
// Set direction
|
||||
switch (direction) {
|
||||
case PIN_INPUT:
|
||||
// Set pin input
|
||||
GPIO_SetInput(obj->port, obj->mask);
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
// Set pin output
|
||||
GPIO_SetOutput(obj->port, obj->mask);
|
||||
break;
|
||||
case PIN_INOUT:
|
||||
// Set pin both input and output
|
||||
GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
|
||||
GPIO_SetInputEnableReg(obj->port, obj->mask, ENABLE);
|
||||
break;
|
||||
default:
|
||||
error("Invalid direction\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_write(gpio_t *obj, int value)
|
||||
{
|
||||
// Write gpio object pin data
|
||||
if ((value == 0) || (value == 1)) {
|
||||
GPIO_WriteDataBit(obj->port, obj->mask, value);
|
||||
} else {
|
||||
error("Invalid value\n");
|
||||
}
|
||||
}
|
||||
|
||||
int gpio_read(gpio_t *obj)
|
||||
{
|
||||
// Read gpio object pin data
|
||||
return GPIO_ReadDataBit(obj->port, obj->mask);
|
||||
}
|
||||
|
|
@ -0,0 +1,233 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_irq_api.h"
|
||||
#include "mbed_error.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "pinmap.h"
|
||||
#include "mbed_critical.h"
|
||||
|
||||
#define CHANNEL_NUM 7
|
||||
|
||||
const PinMap PinMap_GPIO_IRQ[] = {
|
||||
{PC4, GPIO_IRQ_0, PIN_DATA(0, 0)},
|
||||
{PL0, GPIO_IRQ_1, PIN_DATA(0, 0)},
|
||||
{PD4, GPIO_IRQ_2, PIN_DATA(0, 0)},
|
||||
{PK1, GPIO_IRQ_3, PIN_DATA(0, 0)},
|
||||
{PK0, GPIO_IRQ_4, PIN_DATA(0, 0)},
|
||||
{PC0, GPIO_IRQ_5, PIN_DATA(0, 0)},
|
||||
{PC1, GPIO_IRQ_6, PIN_DATA(0, 0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static uint32_t channel_ids[CHANNEL_NUM] = {0};
|
||||
static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
|
||||
|
||||
static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index)
|
||||
{
|
||||
uint32_t val;
|
||||
GPIO_Port port;
|
||||
uint32_t mask;
|
||||
|
||||
port = (GPIO_Port)(pin >> 3);
|
||||
mask = 0x01 << (pin & 0x07);
|
||||
|
||||
// Clear interrupt request
|
||||
CG_ClearINTReq((CG_INTSrc)(CG_INT_SRC_1 + index));
|
||||
// Get pin value
|
||||
val = GPIO_ReadDataBit(port, mask);
|
||||
switch (val) {
|
||||
// Falling edge detection
|
||||
case 0:
|
||||
hal_irq_handler[index](channel_ids[index], IRQ_FALL);
|
||||
break;
|
||||
// Rising edge detection
|
||||
case 1:
|
||||
hal_irq_handler[index](channel_ids[index], IRQ_RISE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void INT1_IRQHandler(void)
|
||||
{
|
||||
INT_IRQHandler(PC4, GPIO_IRQ_0, 0);
|
||||
}
|
||||
|
||||
void INT2_IRQHandler(void)
|
||||
{
|
||||
INT_IRQHandler(PL0, GPIO_IRQ_1, 1);
|
||||
}
|
||||
|
||||
void INT7_IRQHandler(void)
|
||||
{
|
||||
INT_IRQHandler(PD4, GPIO_IRQ_2, 2);
|
||||
}
|
||||
|
||||
void INT8_IRQHandler(void)
|
||||
{
|
||||
INT_IRQHandler(PK1, GPIO_IRQ_3, 3);
|
||||
}
|
||||
|
||||
void INTD_IRQHandler(void)
|
||||
{
|
||||
INT_IRQHandler(PK0, GPIO_IRQ_4, 4);
|
||||
}
|
||||
|
||||
void INTE_IRQHandler(void)
|
||||
{
|
||||
INT_IRQHandler(PC0, GPIO_IRQ_5, 5);
|
||||
}
|
||||
|
||||
void INTF_IRQHandler(void)
|
||||
{
|
||||
INT_IRQHandler(PC1, GPIO_IRQ_6, 6);
|
||||
}
|
||||
|
||||
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
|
||||
{
|
||||
// Get gpio interrupt ID
|
||||
obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
|
||||
core_util_critical_section_enter();
|
||||
// Get pin mask
|
||||
obj->mask = (uint32_t)(1 << (pin & 0x07));
|
||||
// Get GPIO port
|
||||
obj->port = (GPIO_Port)(pin >> 3);
|
||||
// Set pin level as LOW
|
||||
GPIO_WriteDataBit(obj->port, obj->mask, 0);
|
||||
// Enable gpio interrupt function
|
||||
pinmap_pinout(pin, PinMap_GPIO_IRQ);
|
||||
|
||||
// Get GPIO irq source
|
||||
switch (obj->irq_id) {
|
||||
case GPIO_IRQ_0:
|
||||
obj->irq_src = CG_INT_SRC_1;
|
||||
break;
|
||||
case GPIO_IRQ_1:
|
||||
obj->irq_src = CG_INT_SRC_2;
|
||||
break;
|
||||
case GPIO_IRQ_2:
|
||||
obj->irq_src = CG_INT_SRC_7;
|
||||
break;
|
||||
case GPIO_IRQ_3:
|
||||
obj->irq_src = CG_INT_SRC_8;
|
||||
break;
|
||||
case GPIO_IRQ_4:
|
||||
obj->irq_src = CG_INT_SRC_D;
|
||||
break;
|
||||
case GPIO_IRQ_5:
|
||||
obj->irq_src = CG_INT_SRC_E;
|
||||
break;
|
||||
case GPIO_IRQ_6:
|
||||
obj->irq_src = CG_INT_SRC_F;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
// Save irq handler
|
||||
hal_irq_handler[obj->irq_src] = handler;
|
||||
// Save irq id
|
||||
channel_ids[obj->irq_src] = id;
|
||||
// Initialize interrupt event as both edges detection
|
||||
obj->event = CG_INT_ACTIVE_STATE_INVALID;
|
||||
// Clear gpio pending interrupt
|
||||
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
|
||||
// Set interrupt event and enable INTx clear
|
||||
CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
|
||||
core_util_critical_section_exit();;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void gpio_irq_free(gpio_irq_t *obj)
|
||||
{
|
||||
// Clear gpio_irq
|
||||
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
|
||||
// Reset interrupt handler
|
||||
hal_irq_handler[obj->irq_src] = NULL;
|
||||
// Reset interrupt id
|
||||
channel_ids[obj->irq_src] = 0;
|
||||
}
|
||||
|
||||
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
|
||||
{
|
||||
//Disable GPIO interrupt on obj
|
||||
gpio_irq_disable(obj);
|
||||
if (enable) {
|
||||
// Get gpio interrupt event
|
||||
if (event == IRQ_RISE) {
|
||||
if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
|
||||
(obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
|
||||
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
|
||||
} else {
|
||||
obj->event = CG_INT_ACTIVE_STATE_RISING;
|
||||
}
|
||||
} else if (event == IRQ_FALL) {
|
||||
if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
|
||||
(obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
|
||||
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
|
||||
} else {
|
||||
obj->event = CG_INT_ACTIVE_STATE_FALLING;
|
||||
}
|
||||
} else {
|
||||
error("Not supported event\n");
|
||||
}
|
||||
} else {
|
||||
// Get gpio interrupt event
|
||||
if (event == IRQ_RISE) {
|
||||
if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
|
||||
(obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
|
||||
obj->event = CG_INT_ACTIVE_STATE_INVALID;
|
||||
} else {
|
||||
obj->event = CG_INT_ACTIVE_STATE_FALLING;
|
||||
}
|
||||
} else if (event == IRQ_FALL) {
|
||||
if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
|
||||
(obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
|
||||
obj->event = CG_INT_ACTIVE_STATE_INVALID;
|
||||
} else {
|
||||
obj->event = CG_INT_ACTIVE_STATE_RISING;
|
||||
}
|
||||
} else {
|
||||
error("Not supported event\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (obj->event != CG_INT_ACTIVE_STATE_INVALID ) {
|
||||
// Set interrupt event and enable INTx clear
|
||||
CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
|
||||
GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE);
|
||||
} else {
|
||||
GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
|
||||
}
|
||||
|
||||
// Clear interrupt request
|
||||
CG_ClearINTReq(obj->irq_src);
|
||||
// Enable GPIO interrupt on obj
|
||||
gpio_irq_enable(obj);
|
||||
}
|
||||
|
||||
void gpio_irq_enable(gpio_irq_t *obj)
|
||||
{
|
||||
// Clear and Enable gpio_irq object
|
||||
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
|
||||
NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
|
||||
}
|
||||
|
||||
void gpio_irq_disable(gpio_irq_t *obj)
|
||||
{
|
||||
// Disable gpio_irq object
|
||||
NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_GPIO_OBJECT_H
|
||||
#define MBED_GPIO_OBJECT_H
|
||||
|
||||
#include "mbed_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
uint32_t mask;
|
||||
GPIO_Port port;
|
||||
} gpio_t;
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj)
|
||||
{
|
||||
return (obj->pin != (PinName)NC);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,348 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "i2c_api.h"
|
||||
#include "mbed_error.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "pinmap.h"
|
||||
#include "tmpm46b_i2c.h"
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
static const PinMap PinMap_I2C_SDA[] = {
|
||||
{PK2, I2C_0, PIN_DATA(3, 2)},
|
||||
{PF7, I2C_1, PIN_DATA(4, 2)},
|
||||
{PH0, I2C_2, PIN_DATA(4, 2)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_I2C_SCL[] = {
|
||||
{PK3, I2C_0, PIN_DATA(3, 2)},
|
||||
{PF6, I2C_1, PIN_DATA(4, 2)},
|
||||
{PH1, I2C_2, PIN_DATA(4, 2)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
#define SBI_I2C_SEND 0x00
|
||||
#define SBI_I2C_RECEIVE 0x01
|
||||
#define MAX_NUM_I2C 3
|
||||
#define DELAY_MS_MULTIPLIER 5500
|
||||
|
||||
struct i2c_xfer {
|
||||
int32_t count;
|
||||
int32_t len;
|
||||
void *done;
|
||||
char *buf;
|
||||
};
|
||||
|
||||
// Clock setting structure definition
|
||||
typedef struct {
|
||||
uint32_t sck;
|
||||
uint32_t prsck;
|
||||
} I2C_clock_setting_t;
|
||||
|
||||
static void DelayMS(uint32_t delay)
|
||||
{
|
||||
volatile uint32_t VarI;
|
||||
for (VarI = 0; VarI < delay * DELAY_MS_MULTIPLIER; VarI++);
|
||||
}
|
||||
|
||||
static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {
|
||||
20, 24, 32, 48, 80, 144, 272, 528
|
||||
}; // SCK Divider value table
|
||||
|
||||
static I2C_clock_setting_t clk;
|
||||
static I2C_InitTypeDef myi2c;
|
||||
static int32_t start_flag = 1;
|
||||
static struct i2c_xfer xfer[MAX_NUM_I2C];
|
||||
static TSB_I2C_TypeDef *i2c_lut[MAX_NUM_I2C] = {TSB_I2C0, TSB_I2C1, TSB_I2C2};
|
||||
static char *gI2C_TxData = NULL;
|
||||
static char *gI2C_LTxData = NULL;
|
||||
static uint8_t send_byte = 0;
|
||||
static uint8_t byte_func = 0;
|
||||
|
||||
// Initialize the I2C peripheral. It sets the default parameters for I2C
|
||||
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
|
||||
{
|
||||
MBED_ASSERT(obj != NULL);
|
||||
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
|
||||
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
|
||||
I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
|
||||
MBED_ASSERT((int)i2c_name != NC);
|
||||
|
||||
switch(i2c_name) {
|
||||
case I2C_0:
|
||||
CG_SetFcPeriphB(CG_FC_PERIPH_I2C0, ENABLE);
|
||||
CG_SetFcPeriphA(CG_FC_PERIPH_PORTK, ENABLE);
|
||||
obj->i2c = TSB_I2C0;
|
||||
obj->index = 0;
|
||||
obj->IRQn = INTI2C0_IRQn;
|
||||
break;
|
||||
case I2C_1:
|
||||
CG_SetFcPeriphB(CG_FC_PERIPH_I2C1, ENABLE);
|
||||
CG_SetFcPeriphA(CG_FC_PERIPH_PORTF, ENABLE);
|
||||
obj->i2c = TSB_I2C1;
|
||||
obj->index = 1;
|
||||
obj->IRQn = INTI2C1_IRQn;
|
||||
break;
|
||||
case I2C_2:
|
||||
CG_SetFcPeriphB(CG_FC_PERIPH_I2C2, ENABLE);
|
||||
CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE);
|
||||
obj->i2c = TSB_I2C2;
|
||||
obj->index = 2;
|
||||
obj->IRQn = INTI2C2_IRQn;
|
||||
break;
|
||||
default:
|
||||
error("I2C is not available");
|
||||
break;
|
||||
}
|
||||
|
||||
pinmap_pinout(sda, PinMap_I2C_SDA);
|
||||
pin_mode(sda, OpenDrain);
|
||||
pin_mode(sda, PullUp);
|
||||
|
||||
pinmap_pinout(scl, PinMap_I2C_SCL);
|
||||
pin_mode(scl, OpenDrain);
|
||||
pin_mode(scl, PullUp);
|
||||
|
||||
i2c_reset(obj);
|
||||
i2c_frequency(obj, 100000);
|
||||
}
|
||||
|
||||
// Configure the I2C frequency
|
||||
void i2c_frequency(i2c_t *obj, int hz)
|
||||
{
|
||||
uint32_t sck = 0;
|
||||
uint32_t tmp_sck = 0;
|
||||
uint32_t prsck = 1;
|
||||
uint32_t tmp_prsck = 1;
|
||||
uint32_t fscl = 0;
|
||||
uint32_t tmp_fscl = 0;
|
||||
uint64_t fx;
|
||||
|
||||
if (hz <= 400000) { // Maximum 400khz clock frequency supported by M46B
|
||||
for (prsck = 1; prsck <= 32; prsck++) {
|
||||
fx = ((uint64_t)SystemCoreClock / prsck);
|
||||
if ((fx < 20000000U) && (fx > 6666666U)) {
|
||||
for (sck = 0; sck <= 7; sck++) {
|
||||
fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
|
||||
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
|
||||
tmp_fscl = fscl;
|
||||
tmp_sck = sck;
|
||||
tmp_prsck = (prsck < 32)? prsck: 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
clk.sck = (uint32_t)tmp_sck;
|
||||
clk.prsck = (tmp_prsck < 32)? (uint32_t)tmp_prsck - 1 : 1;
|
||||
} else {
|
||||
clk.sck = I2C_SCK_CLK_DIV_24;
|
||||
clk.prsck = I2C_PRESCALER_DIV_4;
|
||||
}
|
||||
myi2c.I2CSelfAddr = 0xE0; // Self Address
|
||||
myi2c.I2CDataLen = I2C_DATA_LEN_8;
|
||||
myi2c.I2CACKState = ENABLE;
|
||||
myi2c.I2CClkDiv = clk.sck;
|
||||
myi2c.PrescalerClkDiv = clk.prsck;
|
||||
|
||||
I2C_SWReset(obj->i2c);
|
||||
I2C_Init(obj->i2c, &myi2c);
|
||||
NVIC_EnableIRQ(obj->IRQn);
|
||||
I2C_SetINTReq(obj->i2c, ENABLE);
|
||||
}
|
||||
|
||||
int i2c_start(i2c_t *obj)
|
||||
{
|
||||
start_flag = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_stop(i2c_t *obj)
|
||||
{
|
||||
I2C_GenerateStop(obj->i2c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i2c_reset(i2c_t *obj)
|
||||
{
|
||||
I2C_SWReset(obj->i2c);
|
||||
}
|
||||
|
||||
static void wait_i2c_bus_free(i2c_t *obj)
|
||||
{
|
||||
I2C_State status;
|
||||
|
||||
do {
|
||||
status = I2C_GetState(obj->i2c);
|
||||
} while (status.Bit.BusState);
|
||||
}
|
||||
|
||||
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
||||
{
|
||||
TSB_I2C_TypeDef *sbi = obj->i2c;
|
||||
uint32_t i2c_num = 0;
|
||||
obj->address = address;
|
||||
|
||||
i2c_num = obj->index;
|
||||
|
||||
// receive data
|
||||
xfer[i2c_num].count = 0;
|
||||
xfer[i2c_num].len = length;
|
||||
xfer[i2c_num].buf = data;
|
||||
|
||||
I2C_SetSendData(sbi, address | SBI_I2C_RECEIVE);
|
||||
I2C_GenerateStart(sbi);
|
||||
|
||||
wait_i2c_bus_free(obj);
|
||||
return (xfer[i2c_num].count - 1);
|
||||
}
|
||||
|
||||
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
||||
{
|
||||
int8_t i = 0;
|
||||
TSB_I2C_TypeDef *sbi = obj->i2c;
|
||||
uint32_t i2c_num = 0;
|
||||
obj->address = address;
|
||||
|
||||
i2c_num = obj->index;
|
||||
gI2C_TxData = (char *)calloc(length, sizeof(int8_t));
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
gI2C_TxData[i] = data[i];
|
||||
}
|
||||
// receive data
|
||||
xfer[i2c_num].count = 0;
|
||||
xfer[i2c_num].len = length;
|
||||
xfer[i2c_num].buf = gI2C_TxData;
|
||||
|
||||
I2C_SetSendData(sbi, address | SBI_I2C_SEND);
|
||||
I2C_GenerateStart(sbi); // Start condition
|
||||
|
||||
wait_i2c_bus_free(obj);
|
||||
free(gI2C_TxData);
|
||||
DelayMS(8);
|
||||
if (((xfer[i2c_num].count - 1) == 0) && (byte_func == 1)) {
|
||||
send_byte = 1;
|
||||
i2c_byte_write(obj, 0x00);
|
||||
xfer[i2c_num].count = 1;
|
||||
byte_func = 0;
|
||||
}
|
||||
return (xfer[i2c_num].count - 1);
|
||||
}
|
||||
|
||||
int i2c_byte_read(i2c_t *obj, int last)
|
||||
{
|
||||
char i2c_ret = 0;
|
||||
i2c_read(obj, obj->address, &i2c_ret, 1, last);
|
||||
return i2c_ret;
|
||||
}
|
||||
|
||||
int i2c_byte_write(i2c_t *obj, int data)
|
||||
{
|
||||
uint32_t wb = 1;
|
||||
static size_t counter = 1;
|
||||
|
||||
byte_func = 1;
|
||||
if (start_flag == 0 && send_byte == 0) {
|
||||
gI2C_LTxData = (char *)realloc(gI2C_LTxData, counter++);
|
||||
gI2C_LTxData[counter - 2] = data;
|
||||
}
|
||||
|
||||
if (send_byte == 1) {
|
||||
wb = i2c_write(obj, obj->address, gI2C_LTxData, (counter - 1), 0);
|
||||
start_flag = 1;
|
||||
send_byte = 0;
|
||||
byte_func = 0;
|
||||
counter = 1;
|
||||
return wb;
|
||||
} else {
|
||||
if (start_flag == 1) {
|
||||
obj->address = data;
|
||||
start_flag = 0;
|
||||
} else {
|
||||
// Store the number of written bytes
|
||||
wb = i2c_write(obj, obj->address, (char*)&data, 1, 0);
|
||||
}
|
||||
if (wb == 1)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void i2c_irq_handler(int i2c_num)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
TSB_I2C_TypeDef *sbi = i2c_lut[i2c_num];
|
||||
I2C_State sbi_sr;
|
||||
|
||||
sbi_sr = I2C_GetState(sbi);
|
||||
|
||||
// we don't support slave mode
|
||||
if (!sbi_sr.Bit.MasterSlave)
|
||||
return;
|
||||
|
||||
if (sbi_sr.Bit.TRx) { // Tx mode
|
||||
if (sbi_sr.Bit.LastRxBit) { // LRB=1: the receiver requires no further data.
|
||||
I2C_GenerateStop(sbi);
|
||||
} else { // LRB=0: the receiver requires further data.
|
||||
if (xfer[i2c_num].count < xfer[i2c_num].len) {
|
||||
I2C_SetSendData(sbi, xfer[i2c_num].buf[xfer[i2c_num].count]); // Send next data
|
||||
} else if (xfer[i2c_num].count == xfer[i2c_num].len) { // I2C data send finished.
|
||||
I2C_GenerateStop(sbi);
|
||||
} else {
|
||||
// Do nothing
|
||||
}
|
||||
xfer[i2c_num].count++;
|
||||
}
|
||||
} else { // Rx Mode
|
||||
if (xfer[i2c_num].count > xfer[i2c_num].len) {
|
||||
I2C_GenerateStop(sbi);
|
||||
I2C_SetACK(sbi, ENABLE);
|
||||
} else {
|
||||
if (xfer[i2c_num].count == xfer[i2c_num].len) { // Rx last data
|
||||
I2C_SetBitNum(sbi, I2C_DATA_LEN_1);
|
||||
} else if (xfer[i2c_num].count == (xfer[i2c_num].len - 1)) { // Rx the data second to last
|
||||
// Not generate ACK for next data Rx end.
|
||||
I2C_SetACK(sbi, DISABLE);
|
||||
} else {
|
||||
// Do nothing
|
||||
}
|
||||
tmp = I2C_GetReceiveData(sbi);
|
||||
if (xfer[i2c_num].count > 0) {
|
||||
xfer[i2c_num].buf[xfer[i2c_num].count - 1U] = tmp;
|
||||
} else {
|
||||
// first read is dummy read
|
||||
}
|
||||
xfer[i2c_num].count++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void INTI2C0_IRQHandler(void)
|
||||
{
|
||||
i2c_irq_handler(0);
|
||||
}
|
||||
|
||||
void INTI2C1_IRQHandler(void)
|
||||
{
|
||||
i2c_irq_handler(1);
|
||||
}
|
||||
|
||||
void INTI2C2_IRQHandler(void)
|
||||
{
|
||||
i2c_irq_handler(2);
|
||||
}
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_OBJECTS_H
|
||||
#define MBED_OBJECTS_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "tmpm46b_gpio.h"
|
||||
#include "tmpm46b_uart.h"
|
||||
#include "tmpm46b_fuart.h"
|
||||
#include "tmpm46b_cg.h"
|
||||
#include "tmpm46b_i2c.h"
|
||||
#include "tmpm46b_adc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct gpio_irq_s {
|
||||
uint32_t mask;
|
||||
GPIO_Port port;
|
||||
uint32_t irq_id;
|
||||
CG_INTActiveState event;
|
||||
CG_INTSrc irq_src;
|
||||
};
|
||||
|
||||
struct port_s {
|
||||
PortName port;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
struct pwmout_s {
|
||||
PinName pin;
|
||||
TSB_TB_TypeDef * channel;
|
||||
uint16_t trailing_timing;
|
||||
uint16_t leading_timing;
|
||||
uint16_t divisor;
|
||||
float period;
|
||||
};
|
||||
|
||||
struct serial_s {
|
||||
PinName pin;
|
||||
uint32_t index;
|
||||
TSB_SC_TypeDef * UARTx;
|
||||
TSB_FUART_TypeDef *FUART;
|
||||
UART_InitTypeDef uart_config;
|
||||
FUART_InitTypeDef fuart_config;
|
||||
TSB_UART_TypeDef *FUART_Reg;
|
||||
};
|
||||
|
||||
struct analogin_s {
|
||||
PinName pin;
|
||||
ADCName adc;
|
||||
TSB_AD_TypeDef* obj;
|
||||
ADC_AINx channel;
|
||||
};
|
||||
|
||||
struct i2c_s {
|
||||
uint32_t index;
|
||||
int address;
|
||||
IRQn_Type IRQn;
|
||||
TSB_I2C_TypeDef *i2c;
|
||||
I2C_InitTypeDef myi2c;
|
||||
};
|
||||
|
||||
struct spi_s {
|
||||
TSB_SSP_TypeDef *spi;
|
||||
SPIName module;
|
||||
uint8_t bits;
|
||||
};
|
||||
|
||||
struct trng_s {
|
||||
bool trng_init;
|
||||
};
|
||||
|
||||
struct flash_s {
|
||||
uint8_t dummy;
|
||||
};
|
||||
#include "gpio_object.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "pinmap.h"
|
||||
#include "tmpm46b_gpio.h"
|
||||
|
||||
#define PIN_FUNC_MAX 6
|
||||
|
||||
void pin_function(PinName pin, int function)
|
||||
{
|
||||
uint32_t port = 0;
|
||||
uint8_t bit = 0;
|
||||
uint8_t i = 0;
|
||||
uint8_t func = 0;
|
||||
uint8_t dir = 0;
|
||||
|
||||
// Assert that pin is valid
|
||||
MBED_ASSERT(pin != NC);
|
||||
|
||||
// Calculate pin function and pin direction
|
||||
func = PIN_FUNC(function);
|
||||
dir = PIN_DIR(function);
|
||||
// Calculate port and pin position
|
||||
port = PIN_PORT(pin);
|
||||
bit = PIN_POS(pin);
|
||||
// Set function if function is in range
|
||||
if (func <= PIN_FUNC_MAX) {
|
||||
// Disable other functions
|
||||
for (i = 0; i < PIN_FUNC_MAX; i++) {
|
||||
if (i != (func - 1)) {
|
||||
GPIO_DisableFuncReg((GPIO_Port)port, i, (1 << bit));
|
||||
}
|
||||
}
|
||||
// Set pin function
|
||||
if (func) {
|
||||
GPIO_EnableFuncReg((GPIO_Port)port, (uint8_t)(func - 1), (1 << bit));
|
||||
}
|
||||
}
|
||||
|
||||
// Set direction if direction is in range
|
||||
switch (dir) {
|
||||
case PIN_INPUT:
|
||||
GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
|
||||
GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
|
||||
GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
|
||||
break;
|
||||
case PIN_INOUT:
|
||||
GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
|
||||
GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void pin_mode(PinName pin, PinMode mode)
|
||||
{
|
||||
uint32_t port = 0;
|
||||
uint8_t bit = 0;
|
||||
|
||||
// Assert that pin is valid
|
||||
MBED_ASSERT(pin != NC);
|
||||
|
||||
// Check if function is in range
|
||||
if (mode > OpenDrain) {
|
||||
return;
|
||||
}
|
||||
// Calculate port and pin position
|
||||
port = PIN_PORT(pin);
|
||||
bit = PIN_POS(pin);
|
||||
// Set pin mode
|
||||
switch (mode) {
|
||||
case PullNone:
|
||||
GPIO_SetPullUp((GPIO_Port)port, (1 << bit), DISABLE);
|
||||
GPIO_SetPullDown((GPIO_Port)port, (1 << bit), DISABLE);
|
||||
GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), DISABLE);
|
||||
break;
|
||||
case PullUp:
|
||||
GPIO_SetPullUp((GPIO_Port)port, (1 << bit), ENABLE);
|
||||
break;
|
||||
case PullDown:
|
||||
GPIO_SetPullDown((GPIO_Port)port, (1 << bit), ENABLE);
|
||||
break;
|
||||
case OpenDrain:
|
||||
GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), ENABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "port_api.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
#define PORT_PIN_NUM 8
|
||||
|
||||
PinName port_pin(PortName port, int pin_n)
|
||||
{
|
||||
PinName pin = NC;
|
||||
pin = (PinName)((port << 3) | pin_n);
|
||||
return pin;
|
||||
}
|
||||
|
||||
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
|
||||
// Assert that port is valid
|
||||
MBED_ASSERT(port <= PortL);
|
||||
|
||||
// Store port and port mask for future use
|
||||
obj->port = port;
|
||||
obj->mask = mask;
|
||||
|
||||
CG_SetFcPeriphA((1 << obj->port), ENABLE);
|
||||
|
||||
// Set port function and port direction
|
||||
for (i = 0; i < PORT_PIN_NUM; i++) {
|
||||
// If the pin is used
|
||||
if (obj->mask & (1 << i)) {
|
||||
pin_function(port_pin(obj->port, i), dir);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void port_mode(port_t *obj, PinMode mode)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
|
||||
// Assert that port is valid
|
||||
MBED_ASSERT(obj->port <= PortL);
|
||||
|
||||
// Set mode for masked pins
|
||||
for (i = 0; i < PORT_PIN_NUM; i++) {
|
||||
// If the pin is used
|
||||
if (obj->mask & (1 << i)) {
|
||||
pin_mode(port_pin(obj->port, i), mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void port_dir(port_t *obj, PinDirection dir)
|
||||
{
|
||||
// Assert that port is valid
|
||||
MBED_ASSERT(obj->port <= PortL);
|
||||
|
||||
// Set direction for masked pins
|
||||
switch (dir) {
|
||||
case PIN_INPUT:
|
||||
GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
|
||||
GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
|
||||
GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
|
||||
break;
|
||||
case PIN_INOUT:
|
||||
GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
|
||||
GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void port_write(port_t *obj, int value)
|
||||
{
|
||||
uint8_t port_data = 0;
|
||||
uint8_t data = 0;
|
||||
|
||||
// Assert that port is valid
|
||||
MBED_ASSERT(obj->port <= PortL);
|
||||
|
||||
// Get current data of port
|
||||
port_data = GPIO_ReadData((GPIO_Port)obj->port);
|
||||
// Calculate data to write to masked pins
|
||||
data = (port_data & ~obj->mask) | (value & obj->mask);
|
||||
// Write data to masked pins of the port
|
||||
GPIO_WriteData((GPIO_Port)obj->port, data);
|
||||
}
|
||||
|
||||
int port_read(port_t *obj)
|
||||
{
|
||||
uint8_t port_data = 0;
|
||||
uint8_t data = 0;
|
||||
|
||||
// Assert that port is valid
|
||||
MBED_ASSERT(obj->port <= PortL);
|
||||
|
||||
// Get current data of port
|
||||
port_data = GPIO_ReadData((GPIO_Port)obj->port);
|
||||
// Calculate data of masked pins
|
||||
data = port_data & obj->mask;
|
||||
return data;
|
||||
}
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "pwmout_api.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "pinmap.h"
|
||||
#include "tmpm46b_tmrb.h"
|
||||
|
||||
#define MAX_COUNTER_16B 0xFFFF
|
||||
|
||||
static TMRB_InitTypeDef m_tmrb;
|
||||
static TMRB_FFOutputTypeDef FFStruct;
|
||||
|
||||
static const PinMap PinMap_PWM[] = {
|
||||
{PE4, PWM_0, PIN_DATA(5, 1)},
|
||||
{PB6, PWM_1, PIN_DATA(4, 1)},
|
||||
{PH1, PWM_2, PIN_DATA(2, 1)},
|
||||
{PH0, PWM_3, PIN_DATA(2, 1)},
|
||||
{PK1, PWM_4, PIN_DATA(4, 1)},
|
||||
{PA7, PWM_5, PIN_DATA(5, 1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const uint32_t prescale_tbl[] = {
|
||||
2, 8, 32, 64, 128, 256, 512
|
||||
};
|
||||
|
||||
#define CLOCK_FREQUENCY (48000000) // Input source clock
|
||||
|
||||
void pwmout_init(pwmout_t *obj, PinName pin)
|
||||
{
|
||||
// Determine the pwm channel
|
||||
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
|
||||
//Assert input is valid
|
||||
MBED_ASSERT(pwm != (PWMName)NC);
|
||||
switch (pwm) {
|
||||
case PWM_0:
|
||||
obj->channel = TSB_TB2;
|
||||
break;
|
||||
case PWM_1:
|
||||
obj->channel = TSB_TB3;
|
||||
break;
|
||||
case PWM_2:
|
||||
obj->channel = TSB_TB4;
|
||||
break;
|
||||
case PWM_3:
|
||||
obj->channel = TSB_TB5;
|
||||
break;
|
||||
case PWM_4:
|
||||
obj->channel = TSB_TB6;
|
||||
break;
|
||||
case PWM_5:
|
||||
obj->channel = TSB_TB7;
|
||||
break;
|
||||
default:
|
||||
obj->channel = NULL;
|
||||
break;
|
||||
}
|
||||
CG_SetFcPeriphA((0x01U << (15U + pwm)), ENABLE);
|
||||
TMRB_SetIdleMode(TSB_TB0, DISABLE);
|
||||
// Set pin function as PWM
|
||||
pinmap_pinout(pin, PinMap_PWM);
|
||||
// Default to 20ms, 0% duty cycle
|
||||
pwmout_period_ms(obj, 20);
|
||||
}
|
||||
|
||||
void pwmout_free(pwmout_t *obj)
|
||||
{
|
||||
// Stops and clear count operation
|
||||
TMRB_SetRunState(obj->channel, TMRB_STOP);
|
||||
pwmout_write(obj,0);
|
||||
obj->channel = NULL;
|
||||
obj->trailing_timing = 0;
|
||||
obj->leading_timing = 0;
|
||||
obj->divisor = 0;
|
||||
TMRB_SetIdleMode(TSB_TB0, ENABLE);
|
||||
}
|
||||
|
||||
void pwmout_write(pwmout_t *obj, float value)
|
||||
{
|
||||
// Stop timer for setting clock again
|
||||
TMRB_SetRunState(obj->channel, TMRB_STOP);
|
||||
// values outside this range will be saturated to 0.0f or 1.0f
|
||||
// Disable flip-flop reverse trigger when leading_timing and trailing_timing are duplicated
|
||||
if (value <= 0.0f) {
|
||||
value = 0;
|
||||
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
|
||||
FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
|
||||
} else if (value >= 1.0f) {
|
||||
value = 1;
|
||||
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET;
|
||||
FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
|
||||
} else {
|
||||
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
|
||||
FFStruct.FlipflopReverseTrg = (TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING);
|
||||
}
|
||||
TMRB_SetFlipFlop(obj->channel, &FFStruct);
|
||||
|
||||
if (obj->period > 0.7) {
|
||||
value = 1; //TMPM46B duty cycle should be < 700ms, above 700ms fixed 50% duty cycle
|
||||
}
|
||||
// Store the new leading_timing value
|
||||
obj->leading_timing = obj->trailing_timing - (uint16_t)(obj->trailing_timing * value);
|
||||
|
||||
// Setting TBxRG0 register
|
||||
TMRB_ChangeLeadingTiming(obj->channel, obj->leading_timing);
|
||||
TMRB_SetRunState(obj->channel, TMRB_RUN);
|
||||
}
|
||||
|
||||
float pwmout_read(pwmout_t *obj)
|
||||
{
|
||||
float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
|
||||
return duty_cycle;
|
||||
}
|
||||
|
||||
void pwmout_period(pwmout_t *obj, float seconds)
|
||||
{
|
||||
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
|
||||
}
|
||||
|
||||
void pwmout_period_ms(pwmout_t *obj, int ms)
|
||||
{
|
||||
pwmout_period_us(obj, (ms * 1000));
|
||||
}
|
||||
|
||||
// Set the PWM period, keeping the duty cycle the same.
|
||||
void pwmout_period_us(pwmout_t *obj, int us)
|
||||
{
|
||||
float seconds = 0;
|
||||
uint32_t cycles = 0;
|
||||
int ClkDiv = 0;
|
||||
int i = 0;
|
||||
float duty_cycle = 0;
|
||||
uint32_t clk_freq = 0;
|
||||
|
||||
seconds = (float)((us) / 1000000.0f);
|
||||
obj->period = seconds;
|
||||
|
||||
if (obj->period > 0.7) {
|
||||
clk_freq = (CLOCK_FREQUENCY / 2);
|
||||
} else {
|
||||
clk_freq = CLOCK_FREQUENCY;
|
||||
}
|
||||
// Select highest timer resolution
|
||||
for (i = 0; i < 7; ++i) {
|
||||
cycles = (int)((clk_freq / prescale_tbl[i]) * seconds);
|
||||
if (cycles <= MAX_COUNTER_16B) {
|
||||
ClkDiv = i + 1; // range 1:6
|
||||
break;
|
||||
} else {
|
||||
cycles = MAX_COUNTER_16B;
|
||||
ClkDiv = 7;
|
||||
}
|
||||
}
|
||||
// Stops and clear count operation
|
||||
TMRB_SetRunState(obj->channel, TMRB_STOP);
|
||||
// Restore the duty-cycle
|
||||
duty_cycle = (float)((obj->trailing_timing - obj->leading_timing) / obj->trailing_timing);
|
||||
obj->trailing_timing = cycles;
|
||||
obj->leading_timing = ((cycles)- (uint16_t)(cycles * duty_cycle));
|
||||
|
||||
// Change the source clock division and period
|
||||
m_tmrb.Mode = TMRB_INTERVAL_TIMER;
|
||||
m_tmrb.ClkDiv = ClkDiv;
|
||||
m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR;
|
||||
m_tmrb.TrailingTiming = obj->trailing_timing;
|
||||
m_tmrb.LeadingTiming = obj->leading_timing;
|
||||
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET;
|
||||
FFStruct.FlipflopReverseTrg = (TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING);
|
||||
// Enable channel
|
||||
TMRB_Enable(obj->channel);
|
||||
// Disable double buffering
|
||||
TMRB_SetDoubleBuf(obj->channel, DISABLE, TMRB_WRITE_REG_SEPARATE);
|
||||
// Init timer function
|
||||
TMRB_Init(obj->channel, &m_tmrb);
|
||||
// Enable double buffering
|
||||
TMRB_SetDoubleBuf(obj->channel, ENABLE, TMRB_WRITE_REG_SEPARATE);
|
||||
TMRB_SetFlipFlop(obj->channel, &FFStruct);
|
||||
// Start timer function
|
||||
TMRB_SetRunState(obj->channel, TMRB_RUN);
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
|
||||
{
|
||||
pwmout_pulsewidth_us(obj, (seconds * 1000000.0f));
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
|
||||
{
|
||||
pwmout_pulsewidth_us(obj, (ms * 1000));
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
|
||||
{
|
||||
float seconds = 0;
|
||||
float value = 0;
|
||||
|
||||
seconds = (float)(us / 1000000.0f);
|
||||
value = (((seconds / obj->period) * 100.0f) / 100.0f);
|
||||
pwmout_write(obj, value);
|
||||
}
|
||||
|
|
@ -0,0 +1,573 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <string.h>
|
||||
#include "serial_api.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "pinmap.h"
|
||||
#include "tmpm46b_uart.h"
|
||||
#include "tmpm46b_fuart.h"
|
||||
|
||||
#define UART_NUM 6
|
||||
#define FUART_INT_BITS 0x07FF
|
||||
|
||||
static const PinMap PinMap_UART_TX[] = {
|
||||
{PE2, SERIAL_0, PIN_DATA(1, 1)},
|
||||
{PE5, SERIAL_1, PIN_DATA(1, 1)},
|
||||
{PL2, SERIAL_2, PIN_DATA(5, 1)},
|
||||
{PB0, SERIAL_3, PIN_DATA(3, 1)},
|
||||
{PF1, SERIAL_4, PIN_DATA(3, 1)},
|
||||
{PA6, SERIAL_5, PIN_DATA(2, 1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_UART_RX[] = {
|
||||
{PE1, SERIAL_0, PIN_DATA(1, 0)},
|
||||
{PE6, SERIAL_1, PIN_DATA(1, 0)},
|
||||
{PL1, SERIAL_2, PIN_DATA(5, 0)},
|
||||
{PB1, SERIAL_3, PIN_DATA(3, 0)},
|
||||
{PF2, SERIAL_4, PIN_DATA(3, 0)},
|
||||
{PA5, SERIAL_5, PIN_DATA(2, 0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_UART_CTS[] = {
|
||||
{PE3, SERIAL_0, PIN_DATA(4, 0)},
|
||||
{PE4, SERIAL_1, PIN_DATA(4, 0)},
|
||||
{PL3, SERIAL_2, PIN_DATA(6, 0)},
|
||||
{PA7, SERIAL_3, PIN_DATA(4, 0)},
|
||||
{PF0, SERIAL_4, PIN_DATA(3, 0)},
|
||||
{PA7, SERIAL_5, PIN_DATA(2, 0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_UART_RTS[] = {
|
||||
{PF3, SERIAL_4, PIN_DATA(3, 1)},
|
||||
{PA4, SERIAL_5, PIN_DATA(2, 1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
|
||||
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||
static uart_irq_handler irq_handler;
|
||||
void serial_init_UART_configure(int uartname, serial_t *obj, PinName tx, PinName rx);
|
||||
|
||||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx)
|
||||
{
|
||||
int is_stdio_uart = 0;
|
||||
|
||||
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
|
||||
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
|
||||
UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
|
||||
MBED_ASSERT((int)uart_name != NC);
|
||||
|
||||
obj->index = uart_name;
|
||||
// Initialize UART instance
|
||||
switch (uart_name) {
|
||||
case SERIAL_0:
|
||||
obj->UARTx = UART0;
|
||||
serial_init_UART_configure(SERIAL_0, obj, tx, rx);
|
||||
break;
|
||||
case SERIAL_1:
|
||||
obj->UARTx = UART1;
|
||||
serial_init_UART_configure(SERIAL_1, obj, tx, rx);
|
||||
break;
|
||||
case SERIAL_2:
|
||||
obj->UARTx = UART2;
|
||||
serial_init_UART_configure(SERIAL_2, obj, tx, rx);
|
||||
break;
|
||||
case SERIAL_3:
|
||||
obj->UARTx = UART3;
|
||||
serial_init_UART_configure(SERIAL_3, obj, tx, rx);
|
||||
break;
|
||||
case SERIAL_4:
|
||||
obj->FUART = FUART0;
|
||||
serial_init_UART_configure(SERIAL_4, obj, tx, rx);
|
||||
break;
|
||||
case SERIAL_5:
|
||||
obj->FUART = FUART1;
|
||||
serial_init_UART_configure(SERIAL_5, obj, tx, rx);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
|
||||
|
||||
if (is_stdio_uart) {
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
}
|
||||
|
||||
void serial_init_UART_configure(int uartname, serial_t *obj, PinName tx, PinName rx)
|
||||
{
|
||||
if (uartname <= SERIAL_3) {
|
||||
obj->uart_config.BaudRate = 9600U;
|
||||
obj->uart_config.DataBits = UART_DATA_BITS_8;
|
||||
obj->uart_config.StopBits = UART_STOP_BITS_1;
|
||||
obj->uart_config.Parity = UART_NO_PARITY;
|
||||
obj->uart_config.FlowCtrl = UART_NONE_FLOW_CTRL;
|
||||
|
||||
if (tx != NC && rx != NC) {
|
||||
obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
|
||||
} else if (tx != NC) {
|
||||
obj->uart_config.Mode = UART_ENABLE_TX;
|
||||
} else if (rx != NC) {
|
||||
obj->uart_config.Mode = UART_ENABLE_RX;
|
||||
}
|
||||
|
||||
// Pinout the chosen uart
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
pinmap_pinout(rx, PinMap_UART_RX);
|
||||
|
||||
UART_Enable(obj->UARTx);
|
||||
UART_SetIdleMode(obj->UARTx, ENABLE);
|
||||
UART_Init(obj->UARTx, &obj->uart_config);
|
||||
} else {
|
||||
obj->fuart_config.BaudRate = 9600U;
|
||||
obj->fuart_config.DataBits = FUART_DATA_BITS_8;
|
||||
obj->fuart_config.StopBits = FUART_STOP_BITS_1;
|
||||
obj->fuart_config.Parity = FUART_NO_PARITY;
|
||||
obj->fuart_config.FlowCtrl = FUART_NONE_FLOW_CTRL;
|
||||
|
||||
if (tx != NC && rx != NC) {
|
||||
obj->fuart_config.Mode = FUART_ENABLE_TX | FUART_ENABLE_RX;
|
||||
} else if (tx != NC) {
|
||||
obj->fuart_config.Mode = FUART_ENABLE_TX;
|
||||
} else if (rx != NC) {
|
||||
obj->fuart_config.Mode = FUART_ENABLE_RX;
|
||||
}
|
||||
|
||||
// pin-out the chosen UART
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
pinmap_pinout(rx, PinMap_UART_RX);
|
||||
|
||||
FUART_Init(obj->FUART, &obj->fuart_config);
|
||||
FUART_Enable(obj->FUART);
|
||||
}
|
||||
}
|
||||
|
||||
void serial_free(serial_t *obj)
|
||||
{
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
// Disable UART
|
||||
UART_Disable(obj->UARTx);
|
||||
UART_SWReset(obj->UARTx);
|
||||
// set information of object to invalid
|
||||
obj->uart_config.BaudRate = 0;
|
||||
obj->uart_config.DataBits = 0;
|
||||
obj->uart_config.StopBits = 0;
|
||||
obj->uart_config.Parity = 0;
|
||||
obj->uart_config.Mode = 0;
|
||||
obj->uart_config.FlowCtrl = 0;
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
// Disable UART
|
||||
FUART_Disable(obj->FUART);
|
||||
// set information of object to invalid
|
||||
obj->fuart_config.BaudRate = 0;
|
||||
obj->fuart_config.DataBits = 0;
|
||||
obj->fuart_config.StopBits = 0;
|
||||
obj->fuart_config.Parity = 0;
|
||||
obj->fuart_config.Mode = 0;
|
||||
obj->fuart_config.FlowCtrl = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// serial_baud
|
||||
void serial_baud(serial_t *obj, int baudrate)
|
||||
{
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
obj->uart_config.BaudRate = baudrate;
|
||||
UART_Init(obj->UARTx,&obj->uart_config);
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
FUART_Disable(obj->FUART);
|
||||
obj->fuart_config.BaudRate = baudrate;
|
||||
FUART_Init(obj->FUART,&obj->fuart_config);
|
||||
FUART_Enable(obj->FUART);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
|
||||
{
|
||||
// 0: 1 stop bits, 1: 2 stop bits
|
||||
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
|
||||
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
|
||||
(parity == ParityForced1) || (parity == ParityForced0));
|
||||
// 0: 7 data bits ... 2: 9 data bits
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
|
||||
obj->uart_config.DataBits = data_bits;
|
||||
obj->uart_config.StopBits = stop_bits;
|
||||
obj->uart_config.Parity = parity;
|
||||
UART_Init(obj->UARTx,&obj->uart_config);
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
FUART_Disable(obj->FUART);
|
||||
MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits
|
||||
obj->fuart_config.DataBits = data_bits;
|
||||
obj->fuart_config.StopBits = stop_bits;
|
||||
obj->fuart_config.Parity = parity;
|
||||
FUART_Init(obj->FUART,&obj->fuart_config);
|
||||
FUART_Enable(obj->FUART);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void INTTX0_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
|
||||
}
|
||||
|
||||
void INTRX0_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
|
||||
}
|
||||
|
||||
void INTTX1_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
|
||||
}
|
||||
|
||||
void INTRX1_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
|
||||
}
|
||||
|
||||
void INTTX2_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_2], TxIrq);
|
||||
}
|
||||
|
||||
void INTRX2_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_2], RxIrq);
|
||||
}
|
||||
|
||||
void INTTX3_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_3], TxIrq);
|
||||
}
|
||||
|
||||
void INTRX3_IRQHandler(void)
|
||||
{
|
||||
irq_handler(serial_irq_ids[SERIAL_3], RxIrq);
|
||||
}
|
||||
|
||||
void INTUART0_IRQHandler(void)
|
||||
{
|
||||
FUART_INTStatus fuart_int;
|
||||
fuart_int = FUART_GetMaskedINTStatus(FUART0);
|
||||
if (fuart_int.Bit.TxFIFO == 1) {
|
||||
irq_handler(serial_irq_ids[SERIAL_4], TxIrq);
|
||||
}
|
||||
if (fuart_int.Bit.RxFIFO == 1) {
|
||||
irq_handler(serial_irq_ids[SERIAL_4], RxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
void INTUART1_IRQHandler(void)
|
||||
{
|
||||
FUART_INTStatus fuart_int;
|
||||
fuart_int = FUART_GetMaskedINTStatus(FUART1);
|
||||
if (fuart_int.Bit.TxFIFO == 1) {
|
||||
irq_handler(serial_irq_ids[SERIAL_5], TxIrq);
|
||||
}
|
||||
if (fuart_int.Bit.RxFIFO == 1) {
|
||||
irq_handler(serial_irq_ids[SERIAL_5], RxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
|
||||
{
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj->index] = id;
|
||||
}
|
||||
|
||||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
|
||||
{
|
||||
IRQn_Type irq_n = (IRQn_Type)0;
|
||||
uint32_t int_mask = 0;
|
||||
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
if (irq == RxIrq) {
|
||||
irq_n = INTRX0_IRQn;
|
||||
} else {
|
||||
irq_n = INTTX0_IRQn;
|
||||
}
|
||||
break;
|
||||
case SERIAL_1:
|
||||
if (irq == RxIrq) {
|
||||
irq_n = INTRX1_IRQn;
|
||||
} else {
|
||||
irq_n = INTTX1_IRQn;
|
||||
}
|
||||
break;
|
||||
case SERIAL_2:
|
||||
if (irq == RxIrq) {
|
||||
irq_n = INTRX2_IRQn;
|
||||
} else {
|
||||
irq_n = INTTX2_IRQn;
|
||||
}
|
||||
break;
|
||||
case SERIAL_3:
|
||||
if (irq == RxIrq) {
|
||||
irq_n = INTRX3_IRQn;
|
||||
} else {
|
||||
irq_n = INTTX3_IRQn;
|
||||
}
|
||||
break;
|
||||
case SERIAL_4:
|
||||
irq_n = INTUART0_IRQn;
|
||||
break;
|
||||
case SERIAL_5:
|
||||
irq_n = INTUART1_IRQn;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((obj->index == SERIAL_4) || (obj->index == SERIAL_5)) {
|
||||
// Get interrupt mask
|
||||
int_mask = obj->FUART->IMSC & FUART_INT_BITS;
|
||||
|
||||
// Set interrupt mask
|
||||
if (irq == RxIrq) {
|
||||
int_mask |= FUART_RX_FIFO_INT_MASK;
|
||||
} else {
|
||||
int_mask |= FUART_TX_FIFO_INT_MASK;
|
||||
}
|
||||
FUART_SetINTMask(obj->FUART, int_mask);
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
} else {
|
||||
NVIC_DisableIRQ(irq_n);
|
||||
}
|
||||
}
|
||||
|
||||
int serial_getc(serial_t *obj)
|
||||
{
|
||||
int data = 0;
|
||||
|
||||
// Wait until Rx buffer is full
|
||||
while (!serial_readable(obj)) {
|
||||
// Do nothing
|
||||
}
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
data = (int) UART_GetRxData(obj->UARTx);
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
data = (int) FUART_GetRxData(obj->FUART);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
void serial_putc(serial_t *obj, int c)
|
||||
{
|
||||
// Wait until Tx buffer is empty
|
||||
while (!serial_writable(obj)) {
|
||||
// Do nothing
|
||||
}
|
||||
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
UART_SetTxData(obj->UARTx,(uint32_t)c);
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
FUART_SetTxData(obj->FUART,(uint32_t)c);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int serial_readable(serial_t *obj)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
if(UART_GetBufState(obj->UARTx, UART_RX) == DONE) {
|
||||
ret = 1;
|
||||
}
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
if (FUART_GetStorageStatus(obj->FUART, FUART_RX) == FUART_STORAGE_FULL) {
|
||||
ret = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int serial_writable(serial_t *obj)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
if(UART_GetBufState(obj->UARTx, UART_TX) == DONE) {
|
||||
ret = 1;
|
||||
}
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
if (FUART_GetStorageStatus(obj->FUART, FUART_TX) == FUART_STORAGE_EMPTY) {
|
||||
ret = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void serial_clear(serial_t *obj)
|
||||
{
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
UART_GetRxData(obj->UARTx);
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
FUART_GetRxData(obj->FUART);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void serial_pinout_tx(PinName tx)
|
||||
{
|
||||
// pin out the chosen UART
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
}
|
||||
|
||||
// Set flow control, Just support CTS
|
||||
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
|
||||
{
|
||||
UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
|
||||
UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
|
||||
UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts);
|
||||
|
||||
switch (obj->index) {
|
||||
case SERIAL_0:
|
||||
case SERIAL_1:
|
||||
case SERIAL_2:
|
||||
case SERIAL_3:
|
||||
if (FlowControlCTS == type) {
|
||||
MBED_ASSERT(uart_cts != (UARTName) NC);
|
||||
|
||||
// Enable the pin for CTS function
|
||||
pinmap_pinout(txflow, PinMap_UART_CTS);
|
||||
|
||||
// Support CTS hardware control flow only
|
||||
obj->UARTx->MOD0 |= 1 << 6;
|
||||
} else {
|
||||
// Disable hardware flow control
|
||||
obj->UARTx->MOD0 &= !(1 << 6);
|
||||
}
|
||||
break;
|
||||
case SERIAL_4:
|
||||
case SERIAL_5:
|
||||
FUART_Disable(obj->FUART);
|
||||
if (type == FlowControlCTS) {
|
||||
MBED_ASSERT(uart_cts != (UARTName) NC);
|
||||
|
||||
// Enable CTS hardware flow control
|
||||
obj->FUART->CR |= FUART_CTS_FLOW_CTRL;
|
||||
|
||||
// Enable the pin for CTS and RTS function
|
||||
pinmap_pinout(txflow, PinMap_UART_CTS);
|
||||
} else if (type == FlowControlRTS) {
|
||||
MBED_ASSERT(uart_rts != (UARTName) NC);
|
||||
|
||||
// Enable RTS hardware flow control
|
||||
obj->FUART->CR |= FUART_RTS_FLOW_CTRL;
|
||||
|
||||
// Enable the pin for RTS function
|
||||
pinmap_pinout(rxflow, PinMap_UART_RTS);
|
||||
} else if (type == FlowControlRTSCTS) {
|
||||
MBED_ASSERT(uart_name != (UARTName) NC);
|
||||
|
||||
// Enable CTS and RTS hardware flow control
|
||||
obj->FUART->CR |= FUART_CTS_FLOW_CTRL | FUART_RTS_FLOW_CTRL;
|
||||
|
||||
// Enable the pin for CTS and RTS function
|
||||
pinmap_pinout(txflow, PinMap_UART_CTS);
|
||||
pinmap_pinout(rxflow, PinMap_UART_RTS);
|
||||
} else {
|
||||
// Disable CTS and RTS hardware flow control
|
||||
obj->FUART->CR &= (uint32_t) 0xFFFF0FFF;
|
||||
}
|
||||
FUART_Enable(obj->FUART);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Pause transmission
|
||||
void serial_break_set(serial_t *obj)
|
||||
{
|
||||
if (obj->index == SERIAL_4 || obj->index == SERIAL_5) {
|
||||
FUART_SetSendBreak(obj->FUART, ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
// Switch to normal transmission
|
||||
void serial_break_clear(serial_t *obj)
|
||||
{
|
||||
if (obj->index == SERIAL_4 || obj->index == SERIAL_5) {
|
||||
FUART_SetSendBreak(obj->FUART, DISABLE);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "sleep_api.h"
|
||||
|
||||
// Number of warm-up cycle = warm-up time to set / input frequency cycle (s)
|
||||
// Number of 3*10^-6 (s) / (1/12 (MHz)) = 60000 = 0xea60
|
||||
#define CG_WUODR_INT ((uint16_t)0xea60)
|
||||
|
||||
static void external_losc_enable(void);
|
||||
|
||||
void hal_sleep(void)
|
||||
{
|
||||
// Set low power consumption mode IDLE
|
||||
CG_SetSTBYMode(CG_STBY_MODE_IDLE);
|
||||
// Enter idle mode
|
||||
__WFI();
|
||||
}
|
||||
|
||||
void hal_deepsleep(void)
|
||||
{
|
||||
// Set low power consumption mode STOP1
|
||||
CG_SetSTBYMode(CG_STBY_MODE_STOP1);
|
||||
// Setup warm up time
|
||||
CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_EXT_HIGH, CG_WUODR_INT);
|
||||
// Enter stop1 mode
|
||||
__WFI();
|
||||
// Switch over from IHOSC to EHOSC
|
||||
external_losc_enable();
|
||||
}
|
||||
|
||||
static void external_losc_enable(void)
|
||||
{
|
||||
// Enable high-speed oscillator
|
||||
CG_SetFosc(CG_FOSC_OSC_EXT, ENABLE);
|
||||
// Select internal(fIHOSC) as warm-up clock
|
||||
CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WUODR_INT);
|
||||
// Start warm-up
|
||||
CG_StartWarmUp();
|
||||
// Wait until EHOSC become stable
|
||||
while (CG_GetWarmUpState() != DONE) {
|
||||
// Do nothing
|
||||
}
|
||||
|
||||
// Set fosc source
|
||||
CG_SetFoscSrc(CG_FOSC_OSC_EXT);
|
||||
// Wait for <OSCSEL> to become "1"
|
||||
while (CG_GetFoscSrc() != CG_FOSC_OSC_EXT) {
|
||||
// Do nothing
|
||||
}
|
||||
|
||||
// Stop IHOSC
|
||||
CG_SetFosc(CG_FOSC_OSC_INT, DISABLE);
|
||||
}
|
||||
|
|
@ -0,0 +1,283 @@
|
|||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "spi_api.h"
|
||||
#include "mbed_error.h"
|
||||
#include "pinmap.h"
|
||||
#include "tmpm46b_ssp.h"
|
||||
|
||||
static const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PK4, SPI_0, PIN_DATA(2, 1)},
|
||||
{PF3, SPI_1, PIN_DATA(5, 1)},
|
||||
{PD3, SPI_2, PIN_DATA(1, 1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PK3, SPI_0, PIN_DATA(2, 1)},
|
||||
{PF4, SPI_1, PIN_DATA(5, 1)},
|
||||
{PD2, SPI_2, PIN_DATA(1, 1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MISO[] = {
|
||||
{PK2, SPI_0, PIN_DATA(2, 0)},
|
||||
{PF5, SPI_1, PIN_DATA(5, 0)},
|
||||
{PD1, SPI_2, PIN_DATA(1, 0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PK1, SPI_0, PIN_DATA(2, 1)},
|
||||
{PF6, SPI_1, PIN_DATA(5, 1)},
|
||||
{PD0, SPI_2, PIN_DATA(1, 1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
#define TMPM46B_SPI_2_FMAX 20000000
|
||||
#define TMPM46B_SPI_FMAX 10000000
|
||||
|
||||
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
|
||||
{
|
||||
SSP_InitTypeDef config;
|
||||
|
||||
// Check pin parameters
|
||||
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
|
||||
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
|
||||
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
|
||||
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
|
||||
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
|
||||
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
|
||||
|
||||
obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk);
|
||||
obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl);
|
||||
MBED_ASSERT((int)obj->module!= NC);
|
||||
|
||||
// Identify SPI module to use
|
||||
switch ((int)obj->module) {
|
||||
case SPI_0:
|
||||
obj->spi = TSB_SSP0;
|
||||
break;
|
||||
case SPI_1:
|
||||
obj->spi = TSB_SSP1;
|
||||
break;
|
||||
case SPI_2:
|
||||
obj->spi = TSB_SSP2;
|
||||
break;
|
||||
default:
|
||||
obj->spi= NULL;
|
||||
obj->module = (SPIName)NC;
|
||||
error("Cannot found SPI module corresponding with input pins.");
|
||||
break;
|
||||
}
|
||||
|
||||
// pin out the spi pins
|
||||
pinmap_pinout(mosi, PinMap_SPI_MOSI);
|
||||
pinmap_pinout(miso, PinMap_SPI_MISO);
|
||||
pinmap_pinout(sclk, PinMap_SPI_SCLK);
|
||||
|
||||
if (ssel != NC) {
|
||||
pinmap_pinout(ssel, PinMap_SPI_SSEL);
|
||||
}
|
||||
|
||||
// Declare Config
|
||||
config.FrameFormat = SSP_FORMAT_SPI;
|
||||
|
||||
// bit_rate = Fsys / (clk_prescale * (clk_rate + 1))
|
||||
config.PreScale = 48;
|
||||
config.ClkRate = 0;
|
||||
|
||||
config.ClkPolarity = SSP_POLARITY_LOW;
|
||||
config.ClkPhase = SSP_PHASE_FIRST_EDGE;
|
||||
config.DataSize = 0x08;
|
||||
|
||||
obj->bits = config.DataSize;
|
||||
config.Mode = SSP_MASTER;
|
||||
SSP_Init(obj->spi, &config);
|
||||
|
||||
// Disable all interrupt
|
||||
|
||||
SSP_SetINTConfig(obj->spi, SSP_INTCFG_NONE);
|
||||
SSP_Enable(obj->spi);
|
||||
}
|
||||
|
||||
void spi_free(spi_t *obj)
|
||||
{
|
||||
SSP_Disable(obj->spi);
|
||||
obj->spi = NULL;
|
||||
obj->module = (SPIName)NC;
|
||||
}
|
||||
|
||||
void spi_format(spi_t *obj, int bits, int mode, int slave)
|
||||
{
|
||||
TSB_SSP_TypeDef* spi;
|
||||
MBED_ASSERT(slave == SSP_MASTER); // Master mode only
|
||||
|
||||
spi = obj->spi;
|
||||
|
||||
SSP_Disable(spi);
|
||||
|
||||
obj->bits = bits;
|
||||
|
||||
SSP_SetDataSize(spi, bits);
|
||||
SSP_SetClkPolarity(spi, (SSP_ClkPolarity)(mode & 0x1));
|
||||
SSP_SetClkPhase(spi, (SSP_ClkPhase)((mode >> 1) & 0x1));
|
||||
|
||||
SSP_Enable(spi);
|
||||
}
|
||||
|
||||
void spi_frequency(spi_t *obj, int hz)
|
||||
{
|
||||
TSB_SSP_TypeDef* spi;
|
||||
|
||||
// Search Freq data
|
||||
int fr_gear = 1;
|
||||
int cur_hz = 1;
|
||||
int32_t best_diff = TMPM46B_SPI_FMAX;
|
||||
int best_cpsdvsr = 254;
|
||||
int best_scr = 255;
|
||||
int cur_cpsdvsr = 48;
|
||||
int cur_scr = 0;
|
||||
int32_t diff;
|
||||
|
||||
/* Assert Min frequency
|
||||
Hz = Fsys / (CPSDVSR * (SCR + 1))
|
||||
Domain value of CPSDVSR is an even number between 2 to 254
|
||||
Domain value of SCR is a number between 0 to 255
|
||||
Hz Min if CPSDVSR and SCR max (CPSDVSR = 254, SCR = 255)
|
||||
*/
|
||||
MBED_ASSERT((SystemCoreClock / 65024) <= (uint32_t)hz);
|
||||
|
||||
if (obj->module == SPI_2) {
|
||||
MBED_ASSERT(hz <= TMPM46B_SPI_2_FMAX);
|
||||
} else {
|
||||
MBED_ASSERT(hz <= TMPM46B_SPI_FMAX); // Default value of SPI_0, SPI_1, SPI_2
|
||||
}
|
||||
|
||||
spi = obj->spi;
|
||||
fr_gear = SystemCoreClock / hz;
|
||||
if (fr_gear < 48) {
|
||||
cur_cpsdvsr = fr_gear;
|
||||
}
|
||||
while (best_diff != 0 && cur_cpsdvsr <= 254) {
|
||||
cur_scr = fr_gear / cur_cpsdvsr - 1;
|
||||
|
||||
if (cur_scr < 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
for (; cur_scr < 256; ++cur_scr) {
|
||||
cur_hz = SystemCoreClock / (cur_cpsdvsr * (1 + cur_scr));
|
||||
|
||||
diff = cur_hz - hz;
|
||||
|
||||
if (diff < 0) {
|
||||
diff = -diff;
|
||||
}
|
||||
|
||||
if (diff < best_diff) {
|
||||
best_cpsdvsr = cur_cpsdvsr;
|
||||
best_scr = cur_scr;
|
||||
best_diff = diff;
|
||||
} else if (diff >= best_diff) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
cur_cpsdvsr += 2;
|
||||
}
|
||||
|
||||
SSP_Disable(spi);
|
||||
// Set bit rate of SPI
|
||||
SSP_SetClkPreScale(spi, (uint8_t)best_cpsdvsr, (uint8_t)best_scr);
|
||||
SSP_Enable(spi);
|
||||
}
|
||||
|
||||
static void spi_clear_FIFOs(TSB_SSP_TypeDef *spi)
|
||||
{
|
||||
SSP_FIFOState tx_buf_state, rx_buf_state;
|
||||
|
||||
do {
|
||||
while (SSP_GetWorkState(spi) == BUSY);
|
||||
|
||||
// Get data from receive FIFO
|
||||
SSP_GetRxData(spi);
|
||||
|
||||
// Check receive FIFO
|
||||
rx_buf_state = SSP_GetFIFOState(spi, SSP_RX);
|
||||
|
||||
// Check transmit FIFO
|
||||
tx_buf_state = SSP_GetFIFOState(spi, SSP_TX);
|
||||
} while (rx_buf_state != SSP_FIFO_EMPTY || tx_buf_state != SSP_FIFO_EMPTY);
|
||||
}
|
||||
|
||||
int spi_master_write(spi_t *obj, int value)
|
||||
{
|
||||
TSB_SSP_TypeDef* spi;
|
||||
|
||||
spi = obj->spi;
|
||||
// Clear all data in transmit FIFO and receive FIFO
|
||||
spi_clear_FIFOs(spi);
|
||||
// Transmit data
|
||||
SSP_SetTxData(spi, value);
|
||||
// Wait for transmitting
|
||||
while (SSP_GetWorkState(spi) == BUSY);
|
||||
// Read received data
|
||||
value = SSP_GetRxData(spi);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
|
||||
char *rx_buffer, int rx_length, char write_fill)
|
||||
{
|
||||
int total = (tx_length > rx_length) ? tx_length : rx_length;
|
||||
|
||||
for (int i = 0; i < total; i++) {
|
||||
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
|
||||
char in = spi_master_write(obj, out);
|
||||
if (i < rx_length) {
|
||||
rx_buffer[i] = in;
|
||||
}
|
||||
}
|
||||
|
||||
return total;
|
||||
}
|
||||
|
||||
int spi_busy(spi_t *obj)
|
||||
{
|
||||
WorkState state;
|
||||
state = SSP_GetWorkState(obj->spi);
|
||||
return (state == BUSY);
|
||||
}
|
||||
|
||||
uint8_t spi_get_module(spi_t *obj)
|
||||
{
|
||||
return (uint8_t)(obj->module);
|
||||
}
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_error.h"
|
||||
#include "tmpm46b_esg.h"
|
||||
#include "trng_api.h"
|
||||
|
||||
static Result ESG_Config(void)
|
||||
{
|
||||
Result ret = ERROR;
|
||||
uint16_t Fintming = 560U;
|
||||
|
||||
// Confirm the ESG core stops
|
||||
if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
|
||||
// Confirm no interrupt generation
|
||||
if (ESG_GetIntStatus() == DISABLE) {
|
||||
// Set the latch timing & output timing
|
||||
if ((ESG_SetLatchTiming(ESG_LATCH_TIMING_1) == SUCCESS) &&
|
||||
(ESG_SetFintiming(Fintming) == SUCCESS)) {
|
||||
ret = SUCCESS;
|
||||
}
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void trng_init(trng_t *obj)
|
||||
{
|
||||
// Enable clock supply
|
||||
CG_SetFcPeriphB(CG_FC_PERIPH_ESG, ENABLE);
|
||||
// Initialise ESG core & Start up the ESG core
|
||||
if ((ESG_Config() == SUCCESS) && (ESG_Startup() == SUCCESS)) {
|
||||
obj->trng_init = true;
|
||||
} else {
|
||||
error("TRNG is not Initialised");
|
||||
obj->trng_init = false;
|
||||
}
|
||||
}
|
||||
|
||||
void trng_free(trng_t *obj)
|
||||
{
|
||||
ESG_IPReset();
|
||||
// Disable clock supply
|
||||
CG_SetFcPeriphB(CG_FC_PERIPH_ESG, DISABLE);
|
||||
obj->trng_init = false;
|
||||
}
|
||||
|
||||
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
|
||||
{
|
||||
volatile uint8_t random[64] = {0};
|
||||
uint8_t i;
|
||||
Result ret = ERROR;
|
||||
|
||||
*output_length = 0;
|
||||
|
||||
if (!obj->trng_init) {
|
||||
error("TRNG is not Initialised");
|
||||
return FAIL; // fail i.e. -1
|
||||
}
|
||||
|
||||
while (ESG_GetIntStatus() == DISABLE) {
|
||||
// Wait for ESG core for generating an interrupt
|
||||
}
|
||||
// Interrupt clearing
|
||||
ret = ESG_ClrInt();
|
||||
if (ret == ERROR) {
|
||||
return FAIL; // fail i.e. -1
|
||||
}
|
||||
// Get the calculation result
|
||||
ESG_GetResult((uint32_t*)random); //512-bit entropy
|
||||
|
||||
for (i = 0; (i < 64) && (i < length); i++) {
|
||||
*output++ = random[i];
|
||||
// clear the buffer
|
||||
random[i] = 0;
|
||||
}
|
||||
*output_length = i;
|
||||
//clear and restart the ESG core
|
||||
ESG_IPReset();
|
||||
ret |= ESG_Startup();
|
||||
if (ret == ERROR) {
|
||||
return FAIL; // fail i.e. -1
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/* mbed Microcontroller Library
|
||||
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "us_ticker_api.h"
|
||||
#include "tmpm46b_tmrb.h"
|
||||
|
||||
#define TMR16A_100US 0xFFFF
|
||||
#define TMRB_CLK_DIV 0x3
|
||||
|
||||
static uint8_t us_ticker_inited = 0; // Is ticker initialized yet?
|
||||
static volatile uint32_t us_ticker = 0; // timer counter
|
||||
|
||||
const ticker_info_t* us_ticker_get_info()
|
||||
{
|
||||
static const ticker_info_t info = {
|
||||
1875000, // 1875000,
|
||||
16 // 16 bit counter
|
||||
};
|
||||
return &info;
|
||||
}
|
||||
|
||||
// initialize us_ticker
|
||||
void us_ticker_init(void)
|
||||
{
|
||||
TMRB_InitTypeDef m_tmrb0;
|
||||
TMRB_FFOutputTypeDef FFStruct;
|
||||
|
||||
if (us_ticker_inited) {
|
||||
return;
|
||||
}
|
||||
us_ticker_inited = 1;
|
||||
|
||||
// Enable channel 0
|
||||
TMRB_Enable(TSB_TB0);
|
||||
// Stops and clear count operation
|
||||
TMRB_SetRunState(TSB_TB0, TMRB_STOP);
|
||||
// Disable to TBxFF0 reverse trigger
|
||||
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
|
||||
FFStruct.FlipflopReverseTrg =TMRB_DISABLE_FLIPFLOP;
|
||||
TMRB_SetFlipFlop(TSB_TB0, &FFStruct);
|
||||
|
||||
// TSB_TB0 using free-run
|
||||
m_tmrb0.Mode = TMRB_INTERVAL_TIMER;
|
||||
m_tmrb0.ClkDiv = TMRB_CLK_DIV;
|
||||
m_tmrb0.UpCntCtrl = TMRB_AUTO_CLEAR;
|
||||
m_tmrb0.TrailingTiming = TMR16A_100US;
|
||||
m_tmrb0.LeadingTiming = TMR16A_100US;
|
||||
TMRB_Init(TSB_TB0, &m_tmrb0);
|
||||
|
||||
// Enable TMRB when system is in idle mode
|
||||
TMRB_SetIdleMode(TSB_TB0, ENABLE);
|
||||
// Starts TSB_TB0
|
||||
TMRB_SetRunState(TSB_TB0, TMRB_RUN);
|
||||
}
|
||||
|
||||
uint32_t us_ticker_read(void)
|
||||
{
|
||||
uint32_t ret_val = 0;
|
||||
|
||||
if (!us_ticker_inited) {
|
||||
us_ticker_init();
|
||||
}
|
||||
|
||||
ret_val = (uint32_t)TMRB_GetUpCntValue(TSB_TB0);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
void us_ticker_set_interrupt(timestamp_t timestamp)
|
||||
{
|
||||
TMRB_InitTypeDef m_tmrb1;
|
||||
TMRB_FFOutputTypeDef FFStruct;
|
||||
|
||||
const uint32_t now_ticks = us_ticker_read();
|
||||
uint32_t delta_ticks =
|
||||
timestamp >= now_ticks ? timestamp - now_ticks : (uint32_t)((uint64_t) timestamp + 0xFFFF - now_ticks);
|
||||
|
||||
if (delta_ticks == 0) {
|
||||
/* The requested delay is less than the minimum resolution of this counter. */
|
||||
delta_ticks = 1;
|
||||
}
|
||||
|
||||
// Ticker interrupt handle
|
||||
TMRB_Enable(TSB_TB1);
|
||||
TMRB_SetRunState(TSB_TB1, TMRB_STOP);
|
||||
NVIC_SetVector(INTTB1_IRQn, (uint32_t)us_ticker_irq_handler);
|
||||
NVIC_EnableIRQ(INTTB1_IRQn);
|
||||
|
||||
// Split delta for preventing the Multiply overflowing
|
||||
FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
|
||||
FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
|
||||
TMRB_SetFlipFlop(TSB_TB1, &FFStruct);
|
||||
|
||||
// TSB_TB0 using free-run
|
||||
m_tmrb1.Mode = TMRB_INTERVAL_TIMER;
|
||||
m_tmrb1.ClkDiv = TMRB_CLK_DIV;
|
||||
m_tmrb1.UpCntCtrl = TMRB_AUTO_CLEAR;
|
||||
m_tmrb1.TrailingTiming = delta_ticks;
|
||||
m_tmrb1.LeadingTiming = delta_ticks;
|
||||
TMRB_Init(TSB_TB1, &m_tmrb1);
|
||||
TMRB_SetINTMask(TSB_TB1,TMRB_MASK_OVERFLOW_INT | TMRB_MASK_MATCH_LEADING_INT);
|
||||
// Enable TMRB when system is in idle mode
|
||||
TMRB_SetIdleMode(TSB_TB1, ENABLE);
|
||||
TMRB_SetRunState(TSB_TB1, TMRB_RUN);
|
||||
}
|
||||
|
||||
void us_ticker_fire_interrupt(void)
|
||||
{
|
||||
NVIC_SetPendingIRQ(INTTB1_IRQn);
|
||||
}
|
||||
|
||||
void us_ticker_disable_interrupt(void)
|
||||
{
|
||||
// Also disable interrupts by NVIC
|
||||
NVIC_DisableIRQ(INTTB1_IRQn);
|
||||
}
|
||||
|
||||
void us_ticker_clear_interrupt(void)
|
||||
{
|
||||
// No flag to clear
|
||||
}
|
||||
|
|
@ -25,4 +25,12 @@
|
|||
|
||||
#endif
|
||||
|
||||
#if defined(TARGET_TMPM46B)
|
||||
|
||||
#ifndef INITIAL_SP
|
||||
#define INITIAL_SP (0x20080000UL)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif // MBED_MBED_RTX_H
|
||||
|
|
|
|||
|
|
@ -3957,5 +3957,18 @@
|
|||
"device_has_add": ["LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
|
||||
"release_versions": ["2"],
|
||||
"device_name": "STM32F411RE"
|
||||
},
|
||||
"TMPM46B": {
|
||||
"inherits": ["Target"],
|
||||
"core": "Cortex-M4",
|
||||
"is_disk_virtual": true,
|
||||
"extra_labels": ["TOSHIBA"],
|
||||
"macros": ["__TMPM46B__"],
|
||||
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
|
||||
"device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "I2C", "STDIO_MESSAGES", "TRNG", "FLASH", "SLEEP"],
|
||||
"device_name": "TMPM46BF10FG",
|
||||
"detect_code": ["7013"],
|
||||
"release_versions": ["5"],
|
||||
"bootloader_supported": true
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue