mirror of https://github.com/ARMmbed/mbed-os.git
ff_lpc546xx: Add support for 220MHz core speed.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>pull/6147/head
Mahesh Mahadevan
parent
a9cd4705d8
commit
069c80b7a5
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@ -1,9 +1,12 @@
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/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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@ -16,6 +19,7 @@
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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@ -45,11 +49,11 @@
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!ClocksProfile
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product: Clocks v1.0
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processor: LPC54618J512
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package_id: LPC54618J512ET180
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processor: LPC54628J512
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package_id: LPC54628J512ET180
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mcu_data: ksdk2_0
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processor_version: 0.0.0
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board: LPCXpresso54618
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board: LPCXpresso54628
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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#include "fsl_power.h"
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@ -244,5 +248,65 @@ void BOARD_BootClockPLL180M(void)
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CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
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SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL220M *********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL220M
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called_from_default_init: true
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outputs:
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- {id: FRO12M_clock.outFreq, value: 12 MHz}
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- {id: FROHF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 220 MHz}
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- {id: SYSPLL_clock.outFreq, value: 220 MHz}
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- {id: System_clock.outFreq, value: 220 MHz}
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settings:
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- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
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- {id: SYSCON.M_MULT.scale, value: '110', locked: true}
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- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
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- {id: SYSCON.PDEC.scale, value: '2', locked: true}
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- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL220M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL220M configuration
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******************************************************************************/
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void BOARD_BootClockPLL220M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */
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/*!< Set up SYS PLL */
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const pll_setup_t pllSetup = {
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.pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U),
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.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)),
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.pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)),
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.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
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.pllRate = 220000000U,
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.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
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};
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CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
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CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
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SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK;
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}
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@ -1,9 +1,12 @@
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/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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|
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@ -16,6 +19,7 @@
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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@ -122,7 +126,7 @@ void BOARD_BootClockFROHF96M(void);
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/*******************************************************************************
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* Definitions for BOARD_BootClockPLL180M configuration
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******************************************************************************/
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#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
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#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
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/*******************************************************************************
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* API for BOARD_BootClockPLL180M configuration
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@ -140,5 +144,30 @@ void BOARD_BootClockPLL180M(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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#endif /* _CLOCK_CONFIG_H_ */
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL220M *********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockPLL220M configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKPLL220M_CORE_CLOCK 220000000U /*!< Core clock frequency:220000000Hz */
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/*******************************************************************************
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* API for BOARD_BootClockPLL220M configuration
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes configuration of clocks.
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*
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*/
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void BOARD_BootClockPLL220M(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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#endif /* _CLOCK_CONFIG_H_ */
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@ -40,7 +40,12 @@
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// called before main
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void mbed_sdk_init()
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{
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BOARD_BootClockFROHF48M();
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if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
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/* LPC54628 runs at a higher core speed */
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BOARD_BootClockPLL220M();
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} else {
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BOARD_BootClockFROHF48M();
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}
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}
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// Change the NMI pin to an input. This allows NMI pin to
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@ -56,7 +56,12 @@ uint32_t FLASHIAP_ReadUid(uint32_t *addr)
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// called before main
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void mbed_sdk_init()
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{
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BOARD_BootClockFROHF48M();
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if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
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/* LPC54628 runs at a higher core speed */
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BOARD_BootClockPLL220M();
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} else {
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BOARD_BootClockFROHF48M();
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}
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}
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// Change the NMI pin to an input. This allows NMI pin to
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